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lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_camera_test/zed_camera_test.srcs/sources_1/bd/system/ip/system_ov7670_vga_0_0/system_ov7670_vga_0_0_stub.vhdl | 3 | 1414 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Thu May 25 20:55:11 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub
-- C:/ZyboIP/examples/zed_camera_test/zed_camera_test.srcs/sources_1/bd/system/ip/system_ov7670_vga_0_0/system_ov7670_vga_0_0_stub.vhdl
-- Design : system_ov7670_vga_0_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity system_ov7670_vga_0_0 is
Port (
clk_x2 : in STD_LOGIC;
active : in STD_LOGIC;
data : in STD_LOGIC_VECTOR ( 7 downto 0 );
rgb : out STD_LOGIC_VECTOR ( 15 downto 0 )
);
end system_ov7670_vga_0_0;
architecture stub of system_ov7670_vga_0_0 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clk_x2,active,data[7:0],rgb[15:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "ov7670_vga,Vivado 2016.4";
begin
end;
| mit |
ashikpoojari/Hardware-Security | DES CryptoCore/src/s6.vhd | 2 | 3965 | library ieee;
use ieee.std_logic_1164.all;
entity s6 is port
(clk: in std_logic;
b : in std_logic_vector(1 to 6);
so : out std_logic_vector(1 to 4)
);
end s6;
architecture behaviour of s6 is
begin
process(b,clk)
begin
case b is
when "000000"=> so<=To_StdLogicVector(Bit_Vector'(x"c"));
when "000010"=> so<=To_StdLogicVector(Bit_Vector'(x"1"));
when "000100"=> so<=To_StdLogicVector(Bit_Vector'(x"a"));
when "000110"=> so<=To_StdLogicVector(Bit_Vector'(x"f"));
when "001000"=> so<=To_StdLogicVector(Bit_Vector'(x"9"));
when "001010"=> so<=To_StdLogicVector(Bit_Vector'(x"2"));
when "001100"=> so<=To_StdLogicVector(Bit_Vector'(x"6"));
when "001110"=> so<=To_StdLogicVector(Bit_Vector'(x"8"));
when "010000"=> so<=To_StdLogicVector(Bit_Vector'(x"0"));
when "010010"=> so<=To_StdLogicVector(Bit_Vector'(x"d"));
when "010100"=> so<=To_StdLogicVector(Bit_Vector'(x"3"));
when "010110"=> so<=To_StdLogicVector(Bit_Vector'(x"4"));
when "011000"=> so<=To_StdLogicVector(Bit_Vector'(x"e"));
when "011010"=> so<=To_StdLogicVector(Bit_Vector'(x"7"));
when "011100"=> so<=To_StdLogicVector(Bit_Vector'(x"5"));
when "011110"=> so<=To_StdLogicVector(Bit_Vector'(x"b"));
when "000001"=> so<=To_StdLogicVector(Bit_Vector'(x"a"));
when "000011"=> so<=To_StdLogicVector(Bit_Vector'(x"f"));
when "000101"=> so<=To_StdLogicVector(Bit_Vector'(x"4"));
when "000111"=> so<=To_StdLogicVector(Bit_Vector'(x"2"));
when "001001"=> so<=To_StdLogicVector(Bit_Vector'(x"7"));
when "001011"=> so<=To_StdLogicVector(Bit_Vector'(x"c"));
when "001101"=> so<=To_StdLogicVector(Bit_Vector'(x"9"));
when "001111"=> so<=To_StdLogicVector(Bit_Vector'(x"5"));
when "010001"=> so<=To_StdLogicVector(Bit_Vector'(x"6"));
when "010011"=> so<=To_StdLogicVector(Bit_Vector'(x"1"));
when "010101"=> so<=To_StdLogicVector(Bit_Vector'(x"d"));
when "010111"=> so<=To_StdLogicVector(Bit_Vector'(x"e"));
when "011001"=> so<=To_StdLogicVector(Bit_Vector'(x"0"));
when "011011"=> so<=To_StdLogicVector(Bit_Vector'(x"b"));
when "011101"=> so<=To_StdLogicVector(Bit_Vector'(x"3"));
when "011111"=> so<=To_StdLogicVector(Bit_Vector'(x"8"));
when "100000"=> so<=To_StdLogicVector(Bit_Vector'(x"9"));
when "100010"=> so<=To_StdLogicVector(Bit_Vector'(x"e"));
when "100100"=> so<=To_StdLogicVector(Bit_Vector'(x"f"));
when "100110"=> so<=To_StdLogicVector(Bit_Vector'(x"5"));
when "101000"=> so<=To_StdLogicVector(Bit_Vector'(x"2"));
when "101010"=> so<=To_StdLogicVector(Bit_Vector'(x"8"));
when "101100"=> so<=To_StdLogicVector(Bit_Vector'(x"c"));
when "101110"=> so<=To_StdLogicVector(Bit_Vector'(x"3"));
when "110000"=> so<=To_StdLogicVector(Bit_Vector'(x"7"));
when "110010"=> so<=To_StdLogicVector(Bit_Vector'(x"0"));
when "110100"=> so<=To_StdLogicVector(Bit_Vector'(x"4"));
when "110110"=> so<=To_StdLogicVector(Bit_Vector'(x"a"));
when "111000"=> so<=To_StdLogicVector(Bit_Vector'(x"1"));
when "111010"=> so<=To_StdLogicVector(Bit_Vector'(x"d"));
when "111100"=> so<=To_StdLogicVector(Bit_Vector'(x"b"));
when "111110"=> so<=To_StdLogicVector(Bit_Vector'(x"6"));
when "100001"=> so<=To_StdLogicVector(Bit_Vector'(x"4"));
when "100011"=> so<=To_StdLogicVector(Bit_Vector'(x"3"));
when "100101"=> so<=To_StdLogicVector(Bit_Vector'(x"2"));
when "100111"=> so<=To_StdLogicVector(Bit_Vector'(x"c"));
when "101001"=> so<=To_StdLogicVector(Bit_Vector'(x"9"));
when "101011"=> so<=To_StdLogicVector(Bit_Vector'(x"5"));
when "101101"=> so<=To_StdLogicVector(Bit_Vector'(x"f"));
when "101111"=> so<=To_StdLogicVector(Bit_Vector'(x"a"));
when "110001"=> so<=To_StdLogicVector(Bit_Vector'(x"b"));
when "110011"=> so<=To_StdLogicVector(Bit_Vector'(x"e"));
when "110101"=> so<=To_StdLogicVector(Bit_Vector'(x"1"));
when "110111"=> so<=To_StdLogicVector(Bit_Vector'(x"7"));
when "111001"=> so<=To_StdLogicVector(Bit_Vector'(x"6"));
when "111011"=> so<=To_StdLogicVector(Bit_Vector'(x"0"));
when "111101"=> so<=To_StdLogicVector(Bit_Vector'(x"8"));
when others=> so<=To_StdLogicVector(Bit_Vector'(x"d"));
end case;
end process;
end; | mit |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_camera_hessian/zed_camera_hessian.srcs/sources_1/bd/system/ip/system_zed_hdmi_0_0/sim/system_zed_hdmi_0_0.vhd | 6 | 4282 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:zed_hdmi:1.0
-- IP Revision: 11
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_zed_hdmi_0_0 IS
PORT (
clk : IN STD_LOGIC;
clk_x2 : IN STD_LOGIC;
clk_100 : IN STD_LOGIC;
active : IN STD_LOGIC;
hsync : IN STD_LOGIC;
vsync : IN STD_LOGIC;
rgb888 : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
hdmi_clk : OUT STD_LOGIC;
hdmi_hsync : OUT STD_LOGIC;
hdmi_vsync : OUT STD_LOGIC;
hdmi_d : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
hdmi_de : OUT STD_LOGIC;
hdmi_scl : OUT STD_LOGIC;
hdmi_sda : INOUT STD_LOGIC
);
END system_zed_hdmi_0_0;
ARCHITECTURE system_zed_hdmi_0_0_arch OF system_zed_hdmi_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_zed_hdmi_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT zed_hdmi IS
PORT (
clk : IN STD_LOGIC;
clk_x2 : IN STD_LOGIC;
clk_100 : IN STD_LOGIC;
active : IN STD_LOGIC;
hsync : IN STD_LOGIC;
vsync : IN STD_LOGIC;
rgb888 : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
hdmi_clk : OUT STD_LOGIC;
hdmi_hsync : OUT STD_LOGIC;
hdmi_vsync : OUT STD_LOGIC;
hdmi_d : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
hdmi_de : OUT STD_LOGIC;
hdmi_scl : OUT STD_LOGIC;
hdmi_sda : INOUT STD_LOGIC
);
END COMPONENT zed_hdmi;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clk CLK";
ATTRIBUTE X_INTERFACE_INFO OF hdmi_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 hdmi_clk CLK";
BEGIN
U0 : zed_hdmi
PORT MAP (
clk => clk,
clk_x2 => clk_x2,
clk_100 => clk_100,
active => active,
hsync => hsync,
vsync => vsync,
rgb888 => rgb888,
hdmi_clk => hdmi_clk,
hdmi_hsync => hdmi_hsync,
hdmi_vsync => hdmi_vsync,
hdmi_d => hdmi_d,
hdmi_de => hdmi_de,
hdmi_scl => hdmi_scl,
hdmi_sda => hdmi_sda
);
END system_zed_hdmi_0_0_arch;
| mit |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | general_ip/ieee754_fp_multiplier/ieee754_fp_multiplier.srcs/sources_1/new/ieee754_fp_multiplier.vhd | 3 | 2829 | ----------------------------------------------------------------------------------
-- Company: Drexel University
-- Engineer: Rob Taglang
--
-- Module Name: ieee754_fp_multiplier - Structural
-- Description: Multiplies two IEEE-754 floating point numbers
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity ieee754_fp_multiplier is
port(
x : in std_logic_vector(31 downto 0);
y : in std_logic_vector(31 downto 0);
z : out std_logic_vector(31 downto 0)
);
end ieee754_fp_multiplier;
architecture Structural of ieee754_fp_multiplier is
signal x_sign, y_sign, z_sign : std_logic;
signal x_exponent, y_exponent, z_exponent : std_logic_vector(7 downto 0);
signal x_mantissa, y_mantissa : std_logic_vector(23 downto 0);
signal z_mantissa : std_logic_vector(22 downto 0);
begin
x_sign <= x(31);
y_sign <= y(31);
z(31) <= z_sign;
-- output sign is negative if only one input is negative
z_sign <= x_sign xor y_sign;
x_mantissa(23) <= '1';
x_mantissa(22 downto 0) <= x(22 downto 0);
y_mantissa(23) <= '1';
y_mantissa(22 downto 0) <= y(22 downto 0);
z(22 downto 0) <= z_mantissa;
x_exponent <= x(30 downto 23);
y_exponent <= y(30 downto 23);
z(30 downto 23) <= z_exponent;
process(x_exponent, y_exponent, x_mantissa, y_mantissa)
variable add, msb : integer;
variable multiply, shift_multiply : unsigned(47 downto 0);
variable mantissa : unsigned(22 downto 0);
begin
if (x_exponent = x"00" and x_mantissa = "100000000000000000000000") or (y_exponent = x"00" and y_mantissa = "100000000000000000000000") then
z_exponent <= x"00";
z_mantissa <= "00000000000000000000000";
else
-- add the exponents
add := to_integer(unsigned(x_exponent) + unsigned(y_exponent)) - 127;
-- multiply the mantissas
multiply := unsigned(x_mantissa) * unsigned(y_mantissa);
msb := 0;
for i in 0 to 47 loop
if multiply(i) = '1' then
msb := i;
end if;
end loop;
shift_multiply := multiply srl msb - 23;
mantissa := shift_multiply(22 downto 0);
if mantissa = "11111111111111111111111" then
z_mantissa <= std_logic_vector(mantissa + 1);
z_exponent <= std_logic_vector(to_unsigned(add + (msb - 46) + 1, 8));
else
z_mantissa <= std_logic_vector(shift_multiply(22 downto 0));
z_exponent <= std_logic_vector(to_unsigned(add + (msb - 46), 8));
end if;
end if;
end process;
end Structural;
| mit |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | general_ip/affine_transform/affine_transform.srcs/sources_1/bd/affine_block/ipshared/0995/ieee754_fp_multiplier.vhd | 3 | 2829 | ----------------------------------------------------------------------------------
-- Company: Drexel University
-- Engineer: Rob Taglang
--
-- Module Name: ieee754_fp_multiplier - Structural
-- Description: Multiplies two IEEE-754 floating point numbers
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity ieee754_fp_multiplier is
port(
x : in std_logic_vector(31 downto 0);
y : in std_logic_vector(31 downto 0);
z : out std_logic_vector(31 downto 0)
);
end ieee754_fp_multiplier;
architecture Structural of ieee754_fp_multiplier is
signal x_sign, y_sign, z_sign : std_logic;
signal x_exponent, y_exponent, z_exponent : std_logic_vector(7 downto 0);
signal x_mantissa, y_mantissa : std_logic_vector(23 downto 0);
signal z_mantissa : std_logic_vector(22 downto 0);
begin
x_sign <= x(31);
y_sign <= y(31);
z(31) <= z_sign;
-- output sign is negative if only one input is negative
z_sign <= x_sign xor y_sign;
x_mantissa(23) <= '1';
x_mantissa(22 downto 0) <= x(22 downto 0);
y_mantissa(23) <= '1';
y_mantissa(22 downto 0) <= y(22 downto 0);
z(22 downto 0) <= z_mantissa;
x_exponent <= x(30 downto 23);
y_exponent <= y(30 downto 23);
z(30 downto 23) <= z_exponent;
process(x_exponent, y_exponent, x_mantissa, y_mantissa)
variable add, msb : integer;
variable multiply, shift_multiply : unsigned(47 downto 0);
variable mantissa : unsigned(22 downto 0);
begin
if (x_exponent = x"00" and x_mantissa = "100000000000000000000000") or (y_exponent = x"00" and y_mantissa = "100000000000000000000000") then
z_exponent <= x"00";
z_mantissa <= "00000000000000000000000";
else
-- add the exponents
add := to_integer(unsigned(x_exponent) + unsigned(y_exponent)) - 127;
-- multiply the mantissas
multiply := unsigned(x_mantissa) * unsigned(y_mantissa);
msb := 0;
for i in 0 to 47 loop
if multiply(i) = '1' then
msb := i;
end if;
end loop;
shift_multiply := multiply srl msb - 23;
mantissa := shift_multiply(22 downto 0);
if mantissa = "11111111111111111111111" then
z_mantissa <= std_logic_vector(mantissa + 1);
z_exponent <= std_logic_vector(to_unsigned(add + (msb - 46) + 1, 8));
else
z_mantissa <= std_logic_vector(shift_multiply(22 downto 0));
z_exponent <= std_logic_vector(to_unsigned(add + (msb - 46), 8));
end if;
end if;
end process;
end Structural;
| mit |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/affine_transform_demo/affine_transform_demo.srcs/sources_1/bd/system/ip/system_affine_transform_0_1/system_affine_transform_0_1_sim_netlist.vhdl | 1 | 1513296 | null | mit |
ashikpoojari/Hardware-Security | Interfaces/UART_Version_2/UART_TX_CTRL.vhd | 2 | 2829 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer: Vinayaka Jyothi
--
-- Create Date: 21:49:51 11/23/2016
-- Design Name:
-- Module Name: UART_TX_CTRL - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_unsigned.all;
entity UART_TX_CTRL is
Port ( SEND : in STD_LOGIC;
DATA : in STD_LOGIC_VECTOR (7 downto 0);
CLK : in STD_LOGIC;
READY : out STD_LOGIC;
UART_TX : out STD_LOGIC);
end UART_TX_CTRL;
architecture Behavioral of UART_TX_CTRL is
type TX_STATE_TYPE is (RDY, LOAD_BIT, SEND_BIT);
constant BIT_TMR_MAX : std_logic_vector(13 downto 0) := "10100010110000"; --10416 = (round(100MHz / 9600)) - 1
constant BIT_INDEX_MAX : natural := 10;
signal bitTmr : std_logic_vector(13 downto 0) := (others => '0');
signal bitDone : std_logic;
signal bitIndex : natural;
signal txBit : std_logic := '1';
signal txData : std_logic_vector(9 downto 0);
signal txState : TX_STATE_TYPE := RDY;
begin
next_txState_process : process (CLK)
begin
if (rising_edge(CLK)) then
case txState is
when RDY => if (SEND = '1') then
txState <= LOAD_BIT;
end if;
when LOAD_BIT => txState <= SEND_BIT;
when SEND_BIT => if (bitDone = '1') then
if (bitIndex = BIT_INDEX_MAX) then
txState <= RDY;
else
txState <= LOAD_BIT;
end if;
end if;
when others => txState <= RDY;
end case;
end if;
end process;
bit_timing_process : process (CLK)
begin
if (rising_edge(CLK)) then
if (txState = RDY) then
bitTmr <= (others => '0');
else
if (bitDone = '1') then
bitTmr <= (others => '0');
else
bitTmr <= bitTmr + 1;
end if;
end if;
end if;
end process;
bitDone <= '1' when (bitTmr = BIT_TMR_MAX) else '0';
bit_counting_process : process (CLK)
begin
if (rising_edge(CLK)) then
if (txState = RDY) then
bitIndex <= 0;
elsif (txState = LOAD_BIT) then
bitIndex <= bitIndex + 1;
end if;
end if;
end process;
tx_data_latch_process : process (CLK)
begin
if (rising_edge(CLK)) then
if (SEND = '1') then
txData <= '1' & DATA & '0';
end if;
end if;
end process;
tx_bit_process : process (CLK)
begin
if (rising_edge(CLK)) then
if (txState = RDY) then
txBit <= '1';
elsif (txState = LOAD_BIT) then
txBit <= txData(bitIndex);
end if;
end if;
end process;
UART_TX <= txBit;
READY <= '1' when (txState = RDY) else
'0';
end Behavioral;
| mit |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/ov7670_fusion/ov7670_fusion.srcs/sources_1/bd/system/ipshared/37f6/zybo_hdmi.vhd | 6 | 2777 | ----------------------------------------------------------------------------------
-- Company: DBRSS
-- Engineer: Daniel Barcklow
-- Module: TOP level DVI-D
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-- Adapted by: Rob Taglang
----------------------------------------------------------------------------------
library IEEE;
library UNISIM;
use IEEE.STD_LOGIC_1164.ALL;
use UNISIM.VCOMPONENTS.ALL;
entity zybo_hdmi is
port(
clk_125 : in std_logic;
clk_25 : in std_logic;
hsync : in std_logic;
vsync : in std_logic;
active : in std_logic;
rgb : in std_logic_vector(23 downto 0);
tmds : out std_logic_vector(3 downto 0);
tmdsb : out std_logic_vector(3 downto 0);
hdmi_cec : in std_logic;
hdmi_hpd : in std_logic;
hdmi_out_en : out std_logic
);
end zybo_hdmi;
architecture Structural of zybo_hdmi is
signal clk_dvi : std_logic := '0';
signal clk_dvin : std_logic := '0';
signal clk_vga : std_logic := '0';
signal red : std_logic_vector(7 downto 0) := (others => '0');
signal green : std_logic_vector(7 downto 0) := (others => '0');
signal blue : std_logic_vector(7 downto 0) := (others => '0');
signal red_s : std_logic;
signal green_s : std_logic;
signal blue_s : std_logic;
signal clock_s : std_logic;
begin
-- Enable HDMI enable out signal, as stated in reference
hdmi_out_en <= '1';
-- Map rgb in to the separate channels
red <= rgb(23 downto 16);
green <= rgb(15 downto 8);
blue <= rgb(7 downto 0);
-- DVI-D module
DVID : entity work.dvid(Behavioral)
port map(
clk => clk_dvi,
clk_n => clk_dvin,
clk_pixel => clk_vga,
red_p => red,
green_p => green,
blue_p => blue,
video_on => active,
hsync => hsync,
vsync => vsync,
-- outputs to TMDS drivers
red_serial => red_s,
green_serial => green_s,
blue_serial => blue_s,
clock_serial => clock_s
);
OBUFDS_blue : OBUFDS PORT MAP ( O => TMDS(0), OB => TMDSB(0), I => blue_s );
OBUFDS_red : OBUFDS PORT MAP ( O => TMDS(1), OB => TMDSB(1), I => green_s );
OBUFDS_green : OBUFDS PORT MAP ( O => TMDS(2), OB => TMDSB(2), I => red_s );
OBUFDS_clock : OBUFDS PORT MAP ( O => TMDS(3), OB => TMDSB(3), I => clock_s );
clk_dvi <= clk_125; -- DVI clk (pos)
clk_dvin <= not clk_125; -- DVI clk (neg)
clk_vga <= clk_25; -- VGA clk
end Structural; | mit |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/ov7670_passthrough/ov7670_passthrough.srcs/sources_1/bd/system/ipshared/37f6/zybo_hdmi.vhd | 6 | 2777 | ----------------------------------------------------------------------------------
-- Company: DBRSS
-- Engineer: Daniel Barcklow
-- Module: TOP level DVI-D
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-- Adapted by: Rob Taglang
----------------------------------------------------------------------------------
library IEEE;
library UNISIM;
use IEEE.STD_LOGIC_1164.ALL;
use UNISIM.VCOMPONENTS.ALL;
entity zybo_hdmi is
port(
clk_125 : in std_logic;
clk_25 : in std_logic;
hsync : in std_logic;
vsync : in std_logic;
active : in std_logic;
rgb : in std_logic_vector(23 downto 0);
tmds : out std_logic_vector(3 downto 0);
tmdsb : out std_logic_vector(3 downto 0);
hdmi_cec : in std_logic;
hdmi_hpd : in std_logic;
hdmi_out_en : out std_logic
);
end zybo_hdmi;
architecture Structural of zybo_hdmi is
signal clk_dvi : std_logic := '0';
signal clk_dvin : std_logic := '0';
signal clk_vga : std_logic := '0';
signal red : std_logic_vector(7 downto 0) := (others => '0');
signal green : std_logic_vector(7 downto 0) := (others => '0');
signal blue : std_logic_vector(7 downto 0) := (others => '0');
signal red_s : std_logic;
signal green_s : std_logic;
signal blue_s : std_logic;
signal clock_s : std_logic;
begin
-- Enable HDMI enable out signal, as stated in reference
hdmi_out_en <= '1';
-- Map rgb in to the separate channels
red <= rgb(23 downto 16);
green <= rgb(15 downto 8);
blue <= rgb(7 downto 0);
-- DVI-D module
DVID : entity work.dvid(Behavioral)
port map(
clk => clk_dvi,
clk_n => clk_dvin,
clk_pixel => clk_vga,
red_p => red,
green_p => green,
blue_p => blue,
video_on => active,
hsync => hsync,
vsync => vsync,
-- outputs to TMDS drivers
red_serial => red_s,
green_serial => green_s,
blue_serial => blue_s,
clock_serial => clock_s
);
OBUFDS_blue : OBUFDS PORT MAP ( O => TMDS(0), OB => TMDSB(0), I => blue_s );
OBUFDS_red : OBUFDS PORT MAP ( O => TMDS(1), OB => TMDSB(1), I => green_s );
OBUFDS_green : OBUFDS PORT MAP ( O => TMDS(2), OB => TMDSB(2), I => red_s );
OBUFDS_clock : OBUFDS PORT MAP ( O => TMDS(3), OB => TMDSB(3), I => clock_s );
clk_dvi <= clk_125; -- DVI clk (pos)
clk_dvin <= not clk_125; -- DVI clk (neg)
clk_vga <= clk_25; -- VGA clk
end Structural; | mit |
SoCdesign/audiomixer | ZedBoard_Linux_Design/hw/xps_proj/pcores/superip_v1_00_a/hdl/vhdl/IIR_Biquad_II_v2.vhd | 4 | 22166 | --////////////////////// IIR_Biquad_II /////////////////////////////////--
-- ***********************************************************************
-- FileName: IIR_Biquad_II.vhd
-- FPGA: Xilinx Spartan 6
-- IDE: Xilinx ISE 13.1
--
-- HDL IS PROVIDED "AS IS." DIGI-KEY EXPRESSLY DISCLAIMS ANY
-- WARRANTY OF ANY KIND, WHETHER EXPRESS OR IMPLIED, INCLUDING BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
-- PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL DIGI-KEY
-- BE LIABLE FOR ANY INCIDENTAL, SPECIAL, INDIRECT OR CONSEQUENTIAL
-- DAMAGES, LOST PROFITS OR LOST DATA, HARM TO YOUR EQUIPMENT, COST OF
-- PROCUREMENT OF SUBSTITUTE GOODS, TECHNOLOGY OR SERVICES, ANY CLAIMS
-- BY THIRD PARTIES (INCLUDING BUT NOT LIMITED TO ANY DEFENSE THEREOF),
-- ANY CLAIMS FOR INDEMNITY OR CONTRIBUTION, OR OTHER SIMILAR COSTS.
-- DIGI-KEY ALSO DISCLAIMS ANY LIABILITY FOR PATENT OR COPYRIGHT
-- INFRINGEMENT.
--
-- Version History
-- Version 1.0 7/31/2012 Tony Storey
-- Initial Public Releaselibrary ieee;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity IIR_Biquad_II_v2 is
Port (
Coef_b0 : std_logic_vector(31 downto 0);
Coef_b1 : std_logic_vector(31 downto 0);
Coef_b2 : std_logic_vector(31 downto 0);
Coef_a1 : std_logic_vector(31 downto 0);
Coef_a2 : std_logic_vector(31 downto 0);
clk : in STD_LOGIC;
clk_100M : in STD_LOGIC;
rst : in STD_LOGIC;
sample_trig : in STD_LOGIC;
X_in : in STD_LOGIC_VECTOR (15 downto 0);
filter_done : out STD_LOGIC;
Y_out : out STD_LOGIC_VECTOR (15 downto 0)
);
end IIR_Biquad_II_v2;
architecture arch of IIR_Biquad_II_v2 is
-- band stop butterworth 2nd order fo = 59.79, fl = 55Hz, fu = 65Hz, Fs = 48000Hz, PBR = .08 dB, SBR = .03 dB
--------------------------------------------------------------------------
--
-- b0 + b1*Z^-1 + b2*Z^-2
-- H[z] = -------------------------
-- 1 + a1*Z^-1 + a2*Z^-2
--
--------------------------------------------------------------------------
-- define biquad coefficients --WORKED WITH HIGH SOUND
-- constant Coef_b0 : std_logic_vector(31 downto 0) := B"00_11_1111_1111_1101_1101_1011_0000_1001"; -- b0 ~ +0.999869117
-- constant Coef_b1 : std_logic_vector(31 downto 0) := B"10_00_0000_0000_0101_0100_1100_1000_1010"; -- b1 ~ -1.999676575
-- constant Coef_b2 : std_logic_vector(31 downto 0) := B"00_11_1111_1111_1101_1101_1011_0000_1001"; -- b2 ~ +0.999869117
--
-- constant Coef_a1 : std_logic_vector(31 downto 0) := B"10_00_0000_0000_0101_0100_1100_1000_1010"; -- a1 ~ -1.999676575
-- constant Coef_a2 : std_logic_vector(31 downto 0) := B"00_11_1111_1111_1011_1011_0110_0001_0011"; -- a2 ~ +0.999738235
-- Pre Generated Example IIR filters
-------------------------------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------------------------------------
-- -- band pass 2nd order butterworth f0 = 2000Hz, fl = 1500Hz, fu = 2500 Fs = 48000Hz, PBR = .08 dB, SBR = .03 dB
-- --------------------------------------------------------------------------
----
---- b0 + b1*Z^-1 + b2*Z^-2
---- H[z] = -------------------------
---- 1 + a1*Z^-1 + a2*Z^-2
----
-- --------------------------------------------------------------------------
--
---- define biquad coefficients --DID NOT WORK NO SOUND
-- constant Coef_b0 : std_logic_vector(31 downto 0) := B"00_00_0011_1110_1111_1100_1111_0000_1111"; -- b0 ~ +0.061511769
-- constant Coef_b1 : std_logic_vector(31 downto 0) := B"00_00_0000_0000_0000_0000_0000_0000_0000"; -- b1 ~ 0.0
-- constant Coef_b2 : std_logic_vector(31 downto 0) := B"11_11_1100_0001_0000_0011_0000_1111_0001"; -- b0 ~ -0.061511769
--
-- constant Coef_a1 : std_logic_vector(31 downto 0) := B"10_00_1011_1011_0111_1011_1110_0101_0111"; -- a1 ~ -1.816910185
-- constant Coef_a2 : std_logic_vector(31 downto 0) := B"00_11_1000_0010_0000_0110_0001_1110_0010"; -- a2 ~ +0.876976463
-- -- band pass 2nd order elliptical fl= 7200Hz, fu = 7400Hz, Fs = 48000Hz, PBR = .08 dB, SBR = .03 dB
-- --------------------------------------------------------------------------
----
---- b0 + b1*Z^-1 + b2*Z^-2
---- H[z] = -------------------------
---- 1 + a1*Z^-1 + a2*Z^-2
----
-- --------------------------------------------------------------------------
--
---- define biquad coefficients --WORKED WITH VERY HIGH SOUND
-- constant Coef_b0 : std_logic_vector(31 downto 0) := B"00_11_1111_1101_0010_0010_0011_1010_0101"; -- b0 ~ +0.9944543
-- constant Coef_b1 : std_logic_vector(31 downto 0) := B"10_11_0110_1000_0111_0101_1111_1101_1011"; -- b1 ~ -1.1479874
-- constant Coef_b2 : std_logic_vector(31 downto 0) := B"00_11_1111_1101_0010_0010_0011_1010_0101"; -- b2 ~ +0.9944543
--
-- constant Coef_a1 : std_logic_vector(31 downto 0) := B"10_11_0110_1000_0111_0101_1111_1101_1011"; -- a1 ~ -1.1479874
-- constant Coef_a2 : std_logic_vector(31 downto 0) := B"00_11_1111_0100_1010_0100_0111_0100_1011"; -- a2 ~ +0.9889086
-- stop band 2nd order butterworth f0 = 3000Hz, fl = 2000Hz, fu = 4000Hz, Fs = 48000Hz, PBR = .08 dB, SBR = .03 dB
-- --------------------------------------------------------------------------
----
---- b0 + b1*Z^-1 + b2*Z^-2
---- H[z] = -------------------------
---- 1 + a1*Z^-1 + a2*Z^-2
----
-- --------------------------------------------------------------------------
--
---- define biquad coefficients -- WORKED WITH VERY HIGH SOUND
-- constant Coef_b0 : std_logic_vector(31 downto 0) := B"00_11_1000_1000_1101_1111_0001_1100_0110"; -- b0 ~ +0.8836636
-- constant Coef_b1 : std_logic_vector(31 downto 0) := B"10_01_0110_1001_1001_0110_1000_0001_1011"; -- b1 ~ -1.6468868
-- constant Coef_b2 : std_logic_vector(31 downto 0) := B"00_11_1000_1000_1101_1111_0001_1100_0110"; -- b2 ~ +0.8836636
--
-- constant Coef_a1 : std_logic_vector(31 downto 0) := B"10_01_0110_1001_1001_0110_1000_0001_1011"; -- a1 ~ -1.6468868
-- constant Coef_a2 : std_logic_vector(31 downto 0) := B"00_11_0001_0001_1011_1110_0011_1000_1011"; -- a2 ~ +0.7673272
-- -- band pass 2nd order elliptical fl= 2000Hz, fu = 2500Hz, Fs = 48000Hz, PBR = .08 dB, SBR = .03 dB
-- --------------------------------------------------------------------------
----
---- b0 + b1*Z^-1 + b2*Z^-2
---- H[z] = -------------------------
---- 1 + a1*Z^-1 + a2*Z^-2
----
-- --------------------------------------------------------------------------
--
---- define biquad coefficients DID NOT WORK NO SOUND
-- constant Coef_b0 : std_logic_vector(31 downto 0) := B"00_00_0100_1001_0001_0011_0101_0100_0111"; -- b0 ~ +0.0713628
-- constant Coef_b1 : std_logic_vector(31 downto 0) := B"00_00_0000_0000_0000_0000_0000_0000_0000"; -- b1 ~ +0.0
-- constant Coef_b2 : std_logic_vector(31 downto 0) := B"11_11_1011_0110_1110_1100_1010_1011_1000"; -- b2 ~ -0.0713628
--
-- constant Coef_a1 : std_logic_vector(31 downto 0) := B"10_00_1110_0011_0001_0001_1010_1011_1111"; -- a1 ~ -1.7782529
-- constant Coef_a2 : std_logic_vector(31 downto 0) := B"00_11_0110_1101_1101_1001_0101_0111_0001"; -- a2 ~ +0.8572744
-- -- Used Bilinear Z Transform
-- -- low pass 2nd order butterworth fc = 12000Hz, Fs = 48000Hz, PBR = .08 dB, SBR = .03 dB
-- --------------------------------------------------------------------------
----
---- b0 + b1*Z^-1 + b2*Z^-2
---- H[z] = -------------------------
---- 1 + a1*Z^-1 + a2*Z^-2
----
-- --------------------------------------------------------------------------
--
---- define biquad coefficients --WORKED WITH VERY HIGH SOUND
-- constant Coef_b0 : std_logic_vector(31 downto 0) := B"00_01_0010_1011_1110_1100_0011_0011_0011"; -- b0 ~ +0.292893219
-- constant Coef_b1 : std_logic_vector(31 downto 0) := B"00_10_0101_0111_1101_1000_0110_0110_0110"; -- b1 ~ +0.585786438
-- constant Coef_b2 : std_logic_vector(31 downto 0) := B"00_01_0010_1011_1110_1100_0011_0011_0011"; -- b2 ~ +0.292893219
--
-- constant Coef_a1 : std_logic_vector(31 downto 0) := B"00_00_0000_0000_0000_0000_0000_0000_0000"; -- a1 ~ 0.0
-- constant Coef_a2 : std_logic_vector(31 downto 0) := B"00_00_0000_0000_0000_0101_0111_1101_1000"; -- a2 ~ +0.171572875
--
-- -- stop band 2nd order butterworth f0 = 3000Hz, fl = 2000Hz, fu = 4000Hz, Fs = 48000Hz, PBR = .08 dB, SBR = .03 dB
-- --------------------------------------------------------------------------
----
---- b0 + b1*Z^-1 + b2*Z^-2
---- H[z] = -------------------------
---- 1 + a1*Z^-1 + a2*Z^-2
----
-- --------------------------------------------------------------------------
--
---- define biquad coefficients WORKED WITH VERY HIGH SOUND
-- constant Coef_b0 : std_logic_vector(31 downto 0) := B"00_11_1000_1000_1101_1111_0001_1100_0110"; -- b0 ~ +0.8836636
-- constant Coef_b1 : std_logic_vector(31 downto 0) := B"10_01_0110_1001_1001_0110_1000_0001_1011"; -- b1 ~ -1.6468868
-- constant Coef_b2 : std_logic_vector(31 downto 0) := B"00_11_1000_1000_1101_1111_0001_1100_0110"; -- b2 ~ +0.8836636
--
-- constant Coef_a1 : std_logic_vector(31 downto 0) := B"10_01_0110_1001_1001_0110_1000_0001_1011"; -- a1 ~ -1.6468868
-- constant Coef_a2 : std_logic_vector(31 downto 0) := B"00_11_0001_0001_1011_1110_0011_1000_1011"; -- a2 ~ +0.7673272
-- constant Coef_b0 : std_logic_vector(31 downto 0) := B"00_00_0000_0001_0000_1100_0011_1001_1100"; -- b0 ~ +0.0010232
-- constant Coef_b1 : std_logic_vector(31 downto 0) := B"00_00_0000_0010_0001_1000_0111_0011_1001"; -- b1 ~ +0.0020464
-- constant Coef_b2 : std_logic_vector(31 downto 0) := B"00_00_0000_0001_0000_1100_0011_1001_1100"; -- b2 ~ +0.0010232
--
-- constant Coef_a1 : std_logic_vector(31 downto 0) := B"10_00_0101_1110_1011_0111_1110_0110_1000"; -- a1 ~ -1.9075016
-- constant Coef_a2 : std_logic_vector(31 downto 0) := B"00_11_1010_0101_0111_1001_0000_0111_0101"; -- a2 ~ +0.9115945
-- define each pre gain sample flip flop
signal ZFF_X0, ZFF_X1, ZFF_X2, ZFF_Y1, ZFF_Y2 : std_logic_vector(31 downto 0) := (others => '0');
-- define each post gain 64 bit sample
signal pgZFF_X0_quad, pgZFF_X1_quad, pgZFF_X2_quad, pgZFF_Y1_quad, pgZFF_Y2_quad : std_logic_vector( 63 downto 0) := (others => '0');
-- define each post gain 32 but truncated sample
signal pgZFF_X0, pgZFF_X1, pgZFF_X2, pgZFF_Y1, pgZFF_Y2 : std_logic_vector(31 downto 0) := (others => '0');
-- define output double reg
signal Y_out_double : std_logic_vector(31 downto 0) := (others => '0');
-- state machine signals
type state_type is (idle, run);
signal state_reg, state_next : state_type;
-- counter signals
signal q_reg, q_next : unsigned(2 downto 0);
signal q_reset, q_add : std_logic;
-- data path flags
signal mul_coefs, trunc_prods, sum_stg_a, trunc_out : std_logic;
begin
-- process to shift samples
process(clk_100M, rst, Y_out_double, sample_trig)
begin
if(rst = '1') then
ZFF_X0 <= (others => '0');
ZFF_X1 <= (others => '0');
ZFF_X2 <= (others => '0');
ZFF_Y1 <= (others => '0');
ZFF_Y2 <= (others => '0');
elsif(rising_edge(clk_100M)) then
if clk = '1' then
if(sample_trig = '1' AND state_reg = idle) then
ZFF_X0 <= X_in(15) & X_in(15) & X_in(15) & X_in(15) & X_in & B"0000_0000_0000"; -- X_in(17) & X_in(17) & X_in & B"0000_0000_0000";
ZFF_X1 <= ZFF_X0;
ZFF_X2 <= ZFF_X1;
ZFF_Y1 <= Y_out_double;
ZFF_Y2 <= ZFF_Y1;
end if;
end if;
end if;
end process;
-- STATE UPDATE AND TIMING
process(clk_100M, rst)
begin
if(rst = '1') then
state_reg <= idle;
q_reg <= (others => '0'); -- reset counter
elsif (rising_edge(clk_100M)) then
if clk = '1' then
state_reg <= state_next; -- update the state
q_reg <= q_next;
end if;
end if;
end process;
-- COUNTER FOR TIMING
q_next <= (others => '0') when q_reset = '1' else -- resets the counter
q_reg + 1 when q_add = '1' else -- increment count if commanded
q_reg;
-- process for control of data path flags
process( q_reg, state_reg, sample_trig)
begin
-- defaults
q_reset <= '0';
q_add <= '0';
mul_coefs <= '0';
trunc_prods <= '0';
sum_stg_a <= '0';
trunc_out <= '0';
filter_done <= '0';
case state_reg is
when idle =>
if(sample_trig = '1') then
state_next <= run;
else
state_next <= idle;
end if;
when run =>
if( q_reg < B"001") then
q_add <= '1';
state_next <= run;
elsif( q_reg < "011") then
mul_coefs <= '1';
q_add <= '1';
state_next <= run;
elsif( q_reg < "100") then
trunc_prods <= '1';
q_add <= '1';
state_next <= run;
elsif( q_reg < "101") then
sum_stg_a <= '1';
q_add <= '1';
state_next <= run;
elsif( q_reg < "110") then
trunc_out <= '1';
q_add <= '1';
state_next <= run;
else
q_reset <= '1';
filter_done <= '1';
state_next <= idle;
end if;
end case;
end process;
-- add gain factors to numerator of biquad (feed forward path)
pgZFF_X0_quad <= std_logic_vector( signed(Coef_b0) * signed(ZFF_X0)) when mul_coefs = '1';
pgZFF_X1_quad <= std_logic_vector( signed(Coef_b1) * signed(ZFF_X1)) when mul_coefs = '1';
pgZFF_X2_quad <= std_logic_vector( signed(Coef_b2) * signed(ZFF_X2)) when mul_coefs = '1';
-- add gain factors to denominator of biquad (feed back path)
pgZFF_Y1_quad <= std_logic_vector( signed(Coef_a1) * signed(ZFF_Y1)) when mul_coefs = '1';
pgZFF_Y2_quad <= std_logic_vector( signed(Coef_a2) * signed(ZFF_Y2)) when mul_coefs = '1';
-- truncate the output to summation block
process(clk_100M, trunc_prods, pgZFF_X0_quad, pgZFF_X1_quad, pgZFF_X2_quad, pgZFF_Y1_quad, pgZFF_Y2_quad)
begin
if rising_edge(clk_100M) then
if clk = '1' then
if (trunc_prods = '1') then
pgZFF_X0 <= pgZFF_X0_quad(61 downto 30);
pgZFF_X2 <= pgZFF_X2_quad(61 downto 30);
pgZFF_X1 <= pgZFF_X1_quad(61 downto 30);
pgZFF_Y1 <= pgZFF_Y1_quad(61 downto 30);
pgZFF_Y2 <= pgZFF_Y2_quad(61 downto 30);
end if;
end if;
end if;
end process;
-- sum all post gain feedback and feedfoward paths
-- Y[z] = X[z]*bo + X[z]*b1*Z^-1 + X[z]*b2*Z^-2 - Y[z]*a1*z^-1 + Y[z]*a2*z^-2
process(clk_100M, sum_stg_a)
begin
if(rising_edge(clk_100M)) then
if clk = '1' then
if(sum_stg_a = '1') then
Y_out_double <= std_logic_vector(signed(pgZFF_X0) + signed(pgZFF_X1) + signed(pgZFF_X2) - signed(pgZFF_Y1) - signed(pgZFF_Y2));
end if;
end if;
end if;
end process;
-- output truncation block
process(clk_100M, trunc_out)
begin
if rising_edge(clk_100M) then
if clk = '1' then
if (trunc_out = '1') then
Y_out <= Y_out_double( 30 downto 15);
end if;
end if;
end if;
end process;
end arch;
-- Pre Generated Example IIR filters
-------------------------------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------------------------------------
-- -- band pass 2nd order butterworth f0 = 2000Hz, fl = 1500Hz, fu = 2500 Fs = 48000Hz, PBR = .08 dB, SBR = .03 dB
-- --------------------------------------------------------------------------
----
---- b0 + b1*Z^-1 + b2*Z^-2
---- H[z] = -------------------------
---- 1 + a1*Z^-1 + a2*Z^-2
----
-- --------------------------------------------------------------------------
--
---- define biquad coefficients
-- constant Coef_b0 : std_logic_vector(31 downto 0) := B"00_00_0011_1110_1111_1100_1111_0000_1111"; -- b0 ~ +0.061511769
-- constant Coef_b1 : std_logic_vector(31 downto 0) := B"00_00_0000_0000_0000_0000_0000_0000_0000"; -- b1 ~ 0.0
-- constant Coef_b2 : std_logic_vector(31 downto 0) := B"11_11_1100_0001_0000_0011_0000_1111_0001"; -- b0 ~ -0.061511769
-- constant Coef_a1 : std_logic_vector(31 downto 0) := B"10_00_1011_1011_0111_1011_1110_0101_0111"; -- a1 ~ -1.816910185
-- constant Coef_a2 : std_logic_vector(31 downto 0) := B"00_11_1000_0010_0000_0110_0001_1110_0010"; -- a2 ~ +0.876976463
-- -- band pass 2nd order elliptical fl= 7200Hz, fu = 7400Hz, Fs = 48000Hz, PBR = .08 dB, SBR = .03 dB
-- --------------------------------------------------------------------------
----
---- b0 + b1*Z^-1 + b2*Z^-2
---- H[z] = -------------------------
---- 1 + a1*Z^-1 + a2*Z^-2
----
-- --------------------------------------------------------------------------
--
---- define biquad coefficients
-- constant Coef_b0 : std_logic_vector(31 downto 0) := B"00_11_1111_1101_0010_0010_0011_1010_0101"; -- b0 ~ +0.9944543
-- constant Coef_b1 : std_logic_vector(31 downto 0) := B"10_11_0110_1000_0111_0101_1111_1101_1011"; -- b1 ~ -1.1479874
-- constant Coef_b2 : std_logic_vector(31 downto 0) := B"00_11_1111_1101_0010_0010_0011_1010_0101"; -- b2 ~ +0.9944543
-- constant Coef_a1 : std_logic_vector(31 downto 0) := B"10_11_0110_1000_0111_0101_1111_1101_1011"; -- a1 ~ -1.1479874
-- constant Coef_a2 : std_logic_vector(31 downto 0) := B"00_11_1111_0100_1010_0100_0111_0100_1011"; -- a2 ~ +0.9889086
-- stop band 2nd order butterworth f0 = 3000Hz, fl = 2000Hz, fu = 4000Hz, Fs = 48000Hz, PBR = .08 dB, SBR = .03 dB
-- --------------------------------------------------------------------------
----
---- b0 + b1*Z^-1 + b2*Z^-2
---- H[z] = -------------------------
---- 1 + a1*Z^-1 + a2*Z^-2
----
-- --------------------------------------------------------------------------
--
---- define biquad coefficients
-- constant Coef_b0 : std_logic_vector(31 downto 0) := B"00_11_1000_1000_1101_1111_0001_1100_0110"; -- b0 ~ +0.8836636
-- constant Coef_b1 : std_logic_vector(31 downto 0) := B"10_01_0110_1001_1001_0110_1000_0001_1011"; -- b1 ~ -1.6468868
-- constant Coef_b2 : std_logic_vector(31 downto 0) := B"00_11_1000_1000_1101_1111_0001_1100_0110"; -- b2 ~ +0.8836636
-- constant Coef_a1 : std_logic_vector(31 downto 0) := B"10_01_0110_1001_1001_0110_1000_0001_1011"; -- a1 ~ -1.6468868
-- constant Coef_a2 : std_logic_vector(31 downto 0) := B"00_11_0001_0001_1011_1110_0011_1000_1011"; -- a2 ~ +0.7673272
-- -- band pass 2nd order elliptical fl= 2000Hz, fu = 2500Hz, Fs = 48000Hz, PBR = .08 dB, SBR = .03 dB
-- --------------------------------------------------------------------------
----
---- b0 + b1*Z^-1 + b2*Z^-2
---- H[z] = -------------------------
---- 1 + a1*Z^-1 + a2*Z^-2
----
-- --------------------------------------------------------------------------
--
---- define biquad coefficients
-- constant Coef_b0 : std_logic_vector(31 downto 0) := B"00_00_0100_1001_0001_0011_0101_0100_0111"; -- b0 ~ +0.0713628
-- constant Coef_b1 : std_logic_vector(31 downto 0) := B"00_00_0000_0000_0000_0000_0000_0000_0000"; -- b1 ~ +0.0
-- constant Coef_b2 : std_logic_vector(31 downto 0) := B"11_11_1011_0110_1110_1100_1010_1011_1000"; -- b2 ~ -0.0713628
-- constant Coef_a1 : std_logic_vector(31 downto 0) := B"10_00_1110_0011_0001_0001_1010_1011_1111"; -- a1 ~ -1.7782529
-- constant Coef_a2 : std_logic_vector(31 downto 0) := B"00_11_0110_1101_1101_1001_0101_0111_0001"; -- a2 ~ +0.8572744
-- -- Used Bilinear Z Transform
-- -- low pass 2nd order butterworth fc = 12000Hz, Fs = 48000Hz, PBR = .08 dB, SBR = .03 dB
-- --------------------------------------------------------------------------
----
---- b0 + b1*Z^-1 + b2*Z^-2
---- H[z] = -------------------------
---- 1 + a1*Z^-1 + a2*Z^-2
----
-- --------------------------------------------------------------------------
--
---- define biquad coefficients
-- constant Coef_b0 : std_logic_vector(31 downto 0) := B"00_01_0010_1011_1110_1100_0011_0011_0011"; -- b0 ~ +0.292893219
-- constant Coef_b1 : std_logic_vector(31 downto 0) := B"00_10_0101_0111_1101_1000_0110_0110_0110"; -- b1 ~ +0.585786438
-- constant Coef_b2 : std_logic_vector(31 downto 0) := B"00_01_0010_1011_1110_1100_0011_0011_0011"; -- b2 ~ +0.292893219
-- constant Coef_a1 : std_logic_vector(31 downto 0) := B"00_00_0000_0000_0000_0000_0000_0000_0000"; -- a1 ~ 0.0
-- constant Coef_a2 : std_logic_vector(31 downto 0) := B"00_00_0000_0000_0000_0101_0111_1101_1000"; -- a2 ~ +0.171572875
--
-- -- stop band 2nd order butterworth f0 = 3000Hz, fl = 2000Hz, fu = 4000Hz, Fs = 48000Hz, PBR = .08 dB, SBR = .03 dB
-- --------------------------------------------------------------------------
----
---- b0 + b1*Z^-1 + b2*Z^-2
---- H[z] = -------------------------
---- 1 + a1*Z^-1 + a2*Z^-2
----
-- --------------------------------------------------------------------------
--
---- define biquad coefficients
-- constant Coef_b0 : std_logic_vector(31 downto 0) := B"00_11_1000_1000_1101_1111_0001_1100_0110"; -- b0 ~ +0.8836636
-- constant Coef_b1 : std_logic_vector(31 downto 0) := B"10_01_0110_1001_1001_0110_1000_0001_1011"; -- b1 ~ -1.6468868
-- constant Coef_b2 : std_logic_vector(31 downto 0) := B"00_11_1000_1000_1101_1111_0001_1100_0110"; -- b2 ~ +0.8836636
-- constant Coef_a1 : std_logic_vector(31 downto 0) := B"10_01_0110_1001_1001_0110_1000_0001_1011"; -- a1 ~ -1.6468868
-- constant Coef_a2 : std_logic_vector(31 downto 0) := B"00_11_0001_0001_1011_1110_0011_1000_1011"; -- a2 ~ +0.7673272 | mit |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | video_ip/vga_axi_buffer/vga_axi_buffer_1.0/hdl/vga_axi_buffer_v1_0.vhd | 1 | 4461 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity vga_axi_buffer_v1_0 is
generic (
-- Users to add parameters here
-- User parameters ends
-- Do not modify the parameters beyond this line
-- Parameters of Axi Slave Bus Interface SAXI
C_SAXI_DATA_WIDTH : integer := 32;
C_SAXI_ADDR_WIDTH : integer := 5
);
port (
-- Users to add ports here
clk : in std_logic;
wen : in std_logic;
x_addr_w : in std_logic_vector(9 downto 0);
y_addr_w : in std_logic_vector(9 downto 0);
x_addr_r : in std_logic_vector(9 downto 0);
y_addr_r : in std_logic_vector(9 downto 0);
data_w : in std_logic_vector(23 downto 0);
data_r : out std_logic_vector(23 downto 0);
-- User ports ends
-- Do not modify the ports beyond this line
-- Ports of Axi Slave Bus Interface SAXI
saxi_aclk : in std_logic;
saxi_aresetn : in std_logic;
saxi_awaddr : in std_logic_vector(C_SAXI_ADDR_WIDTH-1 downto 0);
saxi_awprot : in std_logic_vector(2 downto 0);
saxi_awvalid : in std_logic;
saxi_awready : out std_logic;
saxi_wdata : in std_logic_vector(C_SAXI_DATA_WIDTH-1 downto 0);
saxi_wstrb : in std_logic_vector((C_SAXI_DATA_WIDTH/8)-1 downto 0);
saxi_wvalid : in std_logic;
saxi_wready : out std_logic;
saxi_bresp : out std_logic_vector(1 downto 0);
saxi_bvalid : out std_logic;
saxi_bready : in std_logic;
saxi_araddr : in std_logic_vector(C_SAXI_ADDR_WIDTH-1 downto 0);
saxi_arprot : in std_logic_vector(2 downto 0);
saxi_arvalid : in std_logic;
saxi_arready : out std_logic;
saxi_rdata : out std_logic_vector(C_SAXI_DATA_WIDTH-1 downto 0);
saxi_rresp : out std_logic_vector(1 downto 0);
saxi_rvalid : out std_logic;
saxi_rready : in std_logic
);
end vga_axi_buffer_v1_0;
architecture arch_imp of vga_axi_buffer_v1_0 is
-- component declaration
component vga_axi_buffer_v1_0_SAXI is
generic (
C_S_AXI_DATA_WIDTH : integer := 32;
C_S_AXI_ADDR_WIDTH : integer := 5
);
port (
clk : in std_logic;
wen : in std_logic;
x_addr_w : in std_logic_vector(9 downto 0);
y_addr_w : in std_logic_vector(9 downto 0);
x_addr_r : in std_logic_vector(9 downto 0);
y_addr_r : in std_logic_vector(9 downto 0);
data_w : in std_logic_vector(23 downto 0);
data_r : out std_logic_vector(23 downto 0);
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWPROT : in std_logic_vector(2 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARPROT : in std_logic_vector(2 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic
);
end component vga_axi_buffer_v1_0_SAXI;
begin
-- Instantiation of Axi Bus Interface SAXI
vga_axi_buffer_v1_0_SAXI_inst : vga_axi_buffer_v1_0_SAXI
generic map (
C_S_AXI_DATA_WIDTH => C_SAXI_DATA_WIDTH,
C_S_AXI_ADDR_WIDTH => C_SAXI_ADDR_WIDTH
)
port map (
clk => clk,
wen => wen,
x_addr_w => x_addr_w,
y_addr_w => y_addr_w,
x_addr_r => x_addr_r,
y_addr_r => y_addr_r,
data_w => data_w,
data_r => data_r,
S_AXI_ACLK => saxi_aclk,
S_AXI_ARESETN => saxi_aresetn,
S_AXI_AWADDR => saxi_awaddr,
S_AXI_AWPROT => saxi_awprot,
S_AXI_AWVALID => saxi_awvalid,
S_AXI_AWREADY => saxi_awready,
S_AXI_WDATA => saxi_wdata,
S_AXI_WSTRB => saxi_wstrb,
S_AXI_WVALID => saxi_wvalid,
S_AXI_WREADY => saxi_wready,
S_AXI_BRESP => saxi_bresp,
S_AXI_BVALID => saxi_bvalid,
S_AXI_BREADY => saxi_bready,
S_AXI_ARADDR => saxi_araddr,
S_AXI_ARPROT => saxi_arprot,
S_AXI_ARVALID => saxi_arvalid,
S_AXI_ARREADY => saxi_arready,
S_AXI_RDATA => saxi_rdata,
S_AXI_RRESP => saxi_rresp,
S_AXI_RVALID => saxi_rvalid,
S_AXI_RREADY => saxi_rready
);
-- Add user logic here
-- User logic ends
end arch_imp;
| mit |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | general_ip/affine_transform/affine_transform.srcs/sources_1/bd/affine_block/ip/affine_block_ieee754_fp_multiplier_0_0/synth/affine_block_ieee754_fp_multiplier_0_0.vhd | 2 | 4008 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:ieee754_fp_multiplier:1.0
-- IP Revision: 5
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY affine_block_ieee754_fp_multiplier_0_0 IS
PORT (
x : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
y : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
z : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END affine_block_ieee754_fp_multiplier_0_0;
ARCHITECTURE affine_block_ieee754_fp_multiplier_0_0_arch OF affine_block_ieee754_fp_multiplier_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF affine_block_ieee754_fp_multiplier_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT ieee754_fp_multiplier IS
PORT (
x : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
y : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
z : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT ieee754_fp_multiplier;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF affine_block_ieee754_fp_multiplier_0_0_arch: ARCHITECTURE IS "ieee754_fp_multiplier,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF affine_block_ieee754_fp_multiplier_0_0_arch : ARCHITECTURE IS "affine_block_ieee754_fp_multiplier_0_0,ieee754_fp_multiplier,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF affine_block_ieee754_fp_multiplier_0_0_arch: ARCHITECTURE IS "affine_block_ieee754_fp_multiplier_0_0,ieee754_fp_multiplier,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=user,x_ipName=ieee754_fp_multiplier,x_ipVersion=1.0,x_ipCoreRevision=5,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED}";
BEGIN
U0 : ieee754_fp_multiplier
PORT MAP (
x => x,
y => y,
z => z
);
END affine_block_ieee754_fp_multiplier_0_0_arch;
| mit |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_vga_test/zed_vga_test.srcs/sources_1/bd/system/ip/system_rgb888_to_rgb565_0_0/system_rgb888_to_rgb565_0_0_stub.vhdl | 1 | 1374 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Mon May 08 17:42:47 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub -rename_top system_rgb888_to_rgb565_0_0 -prefix
-- system_rgb888_to_rgb565_0_0_ system_rgb888_to_rgb565_0_0_stub.vhdl
-- Design : system_rgb888_to_rgb565_0_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity system_rgb888_to_rgb565_0_0 is
Port (
rgb_888 : in STD_LOGIC_VECTOR ( 23 downto 0 );
rgb_565 : out STD_LOGIC_VECTOR ( 15 downto 0 )
);
end system_rgb888_to_rgb565_0_0;
architecture stub of system_rgb888_to_rgb565_0_0 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "rgb_888[23:0],rgb_565[15:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "rgb888_to_rgb565,Vivado 2016.4";
begin
end;
| mit |
ashikpoojari/Hardware-Security | PUF Lab/Ring_Ocillator_VHDL_Code/RO_GENIE.vhd | 4 | 2221 | ----------------------------------------------------------------------------------
-- Company: VNIE ENTITIES
-- Engineer: Vinayaka Jyothi
--
-- Create Date: 18:42:34 04/19/2017
-- Design Name: Variable_Chain_Ring_Oscillator_Generator
-- Module Name: RO_GENIE - Structural
-- Project Name: FPGA Trojan Detection
-- Target Devices: Any FPGA Device
-- Tool versions: ISE, Vivado
-- Description: This file allows to describe a N-stage ring oscillator.
-- User can change the value of RO_ChainLength in Line 30.
-- RO needs odd number of elements. RO_ChainLength should be odd.
-- ENABLE=1 to activate RO--> you get oscillations else RO is deactivated
--
-- Dependencies: None
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
--library UNISIM;
--use UNISIM.VComponents.all;
entity RO_GENIE is
generic (RO_ChainLength: integer := 5
);
port( ENABLE : in std_logic;
RO_OSC_OUT: out std_logic
);
end RO_GENIE;
architecture structure of RO_GENIE is
signal RO_PATH_INV : std_logic_vector(RO_ChainLength-1 downto 0);
-- The following attributes stop delay/inverter logic chain from being optimised
-- Keeps the nodes being absorbed/collapsed and allows creating a combinational loop
ATTRIBUTE KEEP: BOOLEAN;
ATTRIBUTE SYN_KEEP: BOOLEAN;
ATTRIBUTE KEEP of RO_PATH_INV: signal is TRUE;
ATTRIBUTE SYN_KEEP of RO_PATH_INV: signal is TRUE;
begin
--This line raises an error if the user specifies a RO with even number of inverting elements. Will not generate any hardware
assert RO_ChainLength mod 2 = 1 report "The number of inverting elements should be an odd number.. Change RO_ChainLength!" severity failure;
gen_ring_osc:
for i in 2 to RO_ChainLength generate
RO_PATH_INV(i-1) <= not RO_PATH_INV(i-2);
end generate;
-- NAND GATES ACTS AS INVERTER WHEN '1'; So when ENABLE=1, you get oscillations else RO chain is broken and no oscillations are produced
RO_PATH_INV(0) <= RO_PATH_INV(RO_ChainLength-1) nand enable;
RO_OSC_OUT <= RO_PATH_INV(RO_ChainLength-2);
end structure; | mit |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_camera_hessian/zed_camera_hessian.srcs/sources_1/bd/system/ip/system_debounce_0_0/system_debounce_0_0_sim_netlist.vhdl | 1 | 18057 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Sun May 28 18:34:35 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim -rename_top system_debounce_0_0 -prefix
-- system_debounce_0_0_ system_debounce_0_0_sim_netlist.vhdl
-- Design : system_debounce_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_debounce_0_0_debounce is
port (
signal_out : out STD_LOGIC;
clk : in STD_LOGIC;
signal_in : in STD_LOGIC
);
end system_debounce_0_0_debounce;
architecture STRUCTURE of system_debounce_0_0_debounce is
signal \c[0]_i_3_n_0\ : STD_LOGIC;
signal \c[0]_i_4_n_0\ : STD_LOGIC;
signal \c[0]_i_5_n_0\ : STD_LOGIC;
signal \c[0]_i_6_n_0\ : STD_LOGIC;
signal \c[12]_i_2_n_0\ : STD_LOGIC;
signal \c[12]_i_3_n_0\ : STD_LOGIC;
signal \c[12]_i_4_n_0\ : STD_LOGIC;
signal \c[12]_i_5_n_0\ : STD_LOGIC;
signal \c[16]_i_2_n_0\ : STD_LOGIC;
signal \c[16]_i_3_n_0\ : STD_LOGIC;
signal \c[16]_i_4_n_0\ : STD_LOGIC;
signal \c[16]_i_5_n_0\ : STD_LOGIC;
signal \c[20]_i_2_n_0\ : STD_LOGIC;
signal \c[20]_i_3_n_0\ : STD_LOGIC;
signal \c[20]_i_4_n_0\ : STD_LOGIC;
signal \c[20]_i_5_n_0\ : STD_LOGIC;
signal \c[4]_i_2_n_0\ : STD_LOGIC;
signal \c[4]_i_3_n_0\ : STD_LOGIC;
signal \c[4]_i_4_n_0\ : STD_LOGIC;
signal \c[4]_i_5_n_0\ : STD_LOGIC;
signal \c[8]_i_2_n_0\ : STD_LOGIC;
signal \c[8]_i_3_n_0\ : STD_LOGIC;
signal \c[8]_i_4_n_0\ : STD_LOGIC;
signal \c[8]_i_5_n_0\ : STD_LOGIC;
signal c_reg : STD_LOGIC_VECTOR ( 23 downto 0 );
signal \c_reg[0]_i_2_n_0\ : STD_LOGIC;
signal \c_reg[0]_i_2_n_1\ : STD_LOGIC;
signal \c_reg[0]_i_2_n_2\ : STD_LOGIC;
signal \c_reg[0]_i_2_n_3\ : STD_LOGIC;
signal \c_reg[0]_i_2_n_4\ : STD_LOGIC;
signal \c_reg[0]_i_2_n_5\ : STD_LOGIC;
signal \c_reg[0]_i_2_n_6\ : STD_LOGIC;
signal \c_reg[0]_i_2_n_7\ : STD_LOGIC;
signal \c_reg[12]_i_1_n_0\ : STD_LOGIC;
signal \c_reg[12]_i_1_n_1\ : STD_LOGIC;
signal \c_reg[12]_i_1_n_2\ : STD_LOGIC;
signal \c_reg[12]_i_1_n_3\ : STD_LOGIC;
signal \c_reg[12]_i_1_n_4\ : STD_LOGIC;
signal \c_reg[12]_i_1_n_5\ : STD_LOGIC;
signal \c_reg[12]_i_1_n_6\ : STD_LOGIC;
signal \c_reg[12]_i_1_n_7\ : STD_LOGIC;
signal \c_reg[16]_i_1_n_0\ : STD_LOGIC;
signal \c_reg[16]_i_1_n_1\ : STD_LOGIC;
signal \c_reg[16]_i_1_n_2\ : STD_LOGIC;
signal \c_reg[16]_i_1_n_3\ : STD_LOGIC;
signal \c_reg[16]_i_1_n_4\ : STD_LOGIC;
signal \c_reg[16]_i_1_n_5\ : STD_LOGIC;
signal \c_reg[16]_i_1_n_6\ : STD_LOGIC;
signal \c_reg[16]_i_1_n_7\ : STD_LOGIC;
signal \c_reg[20]_i_1_n_1\ : STD_LOGIC;
signal \c_reg[20]_i_1_n_2\ : STD_LOGIC;
signal \c_reg[20]_i_1_n_3\ : STD_LOGIC;
signal \c_reg[20]_i_1_n_4\ : STD_LOGIC;
signal \c_reg[20]_i_1_n_5\ : STD_LOGIC;
signal \c_reg[20]_i_1_n_6\ : STD_LOGIC;
signal \c_reg[20]_i_1_n_7\ : STD_LOGIC;
signal \c_reg[4]_i_1_n_0\ : STD_LOGIC;
signal \c_reg[4]_i_1_n_1\ : STD_LOGIC;
signal \c_reg[4]_i_1_n_2\ : STD_LOGIC;
signal \c_reg[4]_i_1_n_3\ : STD_LOGIC;
signal \c_reg[4]_i_1_n_4\ : STD_LOGIC;
signal \c_reg[4]_i_1_n_5\ : STD_LOGIC;
signal \c_reg[4]_i_1_n_6\ : STD_LOGIC;
signal \c_reg[4]_i_1_n_7\ : STD_LOGIC;
signal \c_reg[8]_i_1_n_0\ : STD_LOGIC;
signal \c_reg[8]_i_1_n_1\ : STD_LOGIC;
signal \c_reg[8]_i_1_n_2\ : STD_LOGIC;
signal \c_reg[8]_i_1_n_3\ : STD_LOGIC;
signal \c_reg[8]_i_1_n_4\ : STD_LOGIC;
signal \c_reg[8]_i_1_n_5\ : STD_LOGIC;
signal \c_reg[8]_i_1_n_6\ : STD_LOGIC;
signal \c_reg[8]_i_1_n_7\ : STD_LOGIC;
signal clear : STD_LOGIC;
signal signal_out_i_1_n_0 : STD_LOGIC;
signal signal_out_i_2_n_0 : STD_LOGIC;
signal signal_out_i_3_n_0 : STD_LOGIC;
signal signal_out_i_4_n_0 : STD_LOGIC;
signal signal_out_i_5_n_0 : STD_LOGIC;
signal \NLW_c_reg[20]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
begin
\c[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => signal_in,
O => clear
);
\c[0]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => c_reg(3),
O => \c[0]_i_3_n_0\
);
\c[0]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => c_reg(2),
O => \c[0]_i_4_n_0\
);
\c[0]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => c_reg(1),
O => \c[0]_i_5_n_0\
);
\c[0]_i_6\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => c_reg(0),
O => \c[0]_i_6_n_0\
);
\c[12]_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => c_reg(15),
O => \c[12]_i_2_n_0\
);
\c[12]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => c_reg(14),
O => \c[12]_i_3_n_0\
);
\c[12]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => c_reg(13),
O => \c[12]_i_4_n_0\
);
\c[12]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => c_reg(12),
O => \c[12]_i_5_n_0\
);
\c[16]_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => c_reg(19),
O => \c[16]_i_2_n_0\
);
\c[16]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => c_reg(18),
O => \c[16]_i_3_n_0\
);
\c[16]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => c_reg(17),
O => \c[16]_i_4_n_0\
);
\c[16]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => c_reg(16),
O => \c[16]_i_5_n_0\
);
\c[20]_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => c_reg(23),
O => \c[20]_i_2_n_0\
);
\c[20]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => c_reg(22),
O => \c[20]_i_3_n_0\
);
\c[20]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => c_reg(21),
O => \c[20]_i_4_n_0\
);
\c[20]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => c_reg(20),
O => \c[20]_i_5_n_0\
);
\c[4]_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => c_reg(7),
O => \c[4]_i_2_n_0\
);
\c[4]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => c_reg(6),
O => \c[4]_i_3_n_0\
);
\c[4]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => c_reg(5),
O => \c[4]_i_4_n_0\
);
\c[4]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => c_reg(4),
O => \c[4]_i_5_n_0\
);
\c[8]_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => c_reg(11),
O => \c[8]_i_2_n_0\
);
\c[8]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => c_reg(10),
O => \c[8]_i_3_n_0\
);
\c[8]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => c_reg(9),
O => \c[8]_i_4_n_0\
);
\c[8]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => c_reg(8),
O => \c[8]_i_5_n_0\
);
\c_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \c_reg[0]_i_2_n_7\,
Q => c_reg(0),
R => clear
);
\c_reg[0]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \c_reg[0]_i_2_n_0\,
CO(2) => \c_reg[0]_i_2_n_1\,
CO(1) => \c_reg[0]_i_2_n_2\,
CO(0) => \c_reg[0]_i_2_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0001",
O(3) => \c_reg[0]_i_2_n_4\,
O(2) => \c_reg[0]_i_2_n_5\,
O(1) => \c_reg[0]_i_2_n_6\,
O(0) => \c_reg[0]_i_2_n_7\,
S(3) => \c[0]_i_3_n_0\,
S(2) => \c[0]_i_4_n_0\,
S(1) => \c[0]_i_5_n_0\,
S(0) => \c[0]_i_6_n_0\
);
\c_reg[10]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \c_reg[8]_i_1_n_5\,
Q => c_reg(10),
R => clear
);
\c_reg[11]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \c_reg[8]_i_1_n_4\,
Q => c_reg(11),
R => clear
);
\c_reg[12]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \c_reg[12]_i_1_n_7\,
Q => c_reg(12),
R => clear
);
\c_reg[12]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \c_reg[8]_i_1_n_0\,
CO(3) => \c_reg[12]_i_1_n_0\,
CO(2) => \c_reg[12]_i_1_n_1\,
CO(1) => \c_reg[12]_i_1_n_2\,
CO(0) => \c_reg[12]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \c_reg[12]_i_1_n_4\,
O(2) => \c_reg[12]_i_1_n_5\,
O(1) => \c_reg[12]_i_1_n_6\,
O(0) => \c_reg[12]_i_1_n_7\,
S(3) => \c[12]_i_2_n_0\,
S(2) => \c[12]_i_3_n_0\,
S(1) => \c[12]_i_4_n_0\,
S(0) => \c[12]_i_5_n_0\
);
\c_reg[13]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \c_reg[12]_i_1_n_6\,
Q => c_reg(13),
R => clear
);
\c_reg[14]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \c_reg[12]_i_1_n_5\,
Q => c_reg(14),
R => clear
);
\c_reg[15]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \c_reg[12]_i_1_n_4\,
Q => c_reg(15),
R => clear
);
\c_reg[16]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \c_reg[16]_i_1_n_7\,
Q => c_reg(16),
R => clear
);
\c_reg[16]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \c_reg[12]_i_1_n_0\,
CO(3) => \c_reg[16]_i_1_n_0\,
CO(2) => \c_reg[16]_i_1_n_1\,
CO(1) => \c_reg[16]_i_1_n_2\,
CO(0) => \c_reg[16]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \c_reg[16]_i_1_n_4\,
O(2) => \c_reg[16]_i_1_n_5\,
O(1) => \c_reg[16]_i_1_n_6\,
O(0) => \c_reg[16]_i_1_n_7\,
S(3) => \c[16]_i_2_n_0\,
S(2) => \c[16]_i_3_n_0\,
S(1) => \c[16]_i_4_n_0\,
S(0) => \c[16]_i_5_n_0\
);
\c_reg[17]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \c_reg[16]_i_1_n_6\,
Q => c_reg(17),
R => clear
);
\c_reg[18]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \c_reg[16]_i_1_n_5\,
Q => c_reg(18),
R => clear
);
\c_reg[19]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \c_reg[16]_i_1_n_4\,
Q => c_reg(19),
R => clear
);
\c_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \c_reg[0]_i_2_n_6\,
Q => c_reg(1),
R => clear
);
\c_reg[20]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \c_reg[20]_i_1_n_7\,
Q => c_reg(20),
R => clear
);
\c_reg[20]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \c_reg[16]_i_1_n_0\,
CO(3) => \NLW_c_reg[20]_i_1_CO_UNCONNECTED\(3),
CO(2) => \c_reg[20]_i_1_n_1\,
CO(1) => \c_reg[20]_i_1_n_2\,
CO(0) => \c_reg[20]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \c_reg[20]_i_1_n_4\,
O(2) => \c_reg[20]_i_1_n_5\,
O(1) => \c_reg[20]_i_1_n_6\,
O(0) => \c_reg[20]_i_1_n_7\,
S(3) => \c[20]_i_2_n_0\,
S(2) => \c[20]_i_3_n_0\,
S(1) => \c[20]_i_4_n_0\,
S(0) => \c[20]_i_5_n_0\
);
\c_reg[21]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \c_reg[20]_i_1_n_6\,
Q => c_reg(21),
R => clear
);
\c_reg[22]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \c_reg[20]_i_1_n_5\,
Q => c_reg(22),
R => clear
);
\c_reg[23]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \c_reg[20]_i_1_n_4\,
Q => c_reg(23),
R => clear
);
\c_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \c_reg[0]_i_2_n_5\,
Q => c_reg(2),
R => clear
);
\c_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \c_reg[0]_i_2_n_4\,
Q => c_reg(3),
R => clear
);
\c_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \c_reg[4]_i_1_n_7\,
Q => c_reg(4),
R => clear
);
\c_reg[4]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \c_reg[0]_i_2_n_0\,
CO(3) => \c_reg[4]_i_1_n_0\,
CO(2) => \c_reg[4]_i_1_n_1\,
CO(1) => \c_reg[4]_i_1_n_2\,
CO(0) => \c_reg[4]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \c_reg[4]_i_1_n_4\,
O(2) => \c_reg[4]_i_1_n_5\,
O(1) => \c_reg[4]_i_1_n_6\,
O(0) => \c_reg[4]_i_1_n_7\,
S(3) => \c[4]_i_2_n_0\,
S(2) => \c[4]_i_3_n_0\,
S(1) => \c[4]_i_4_n_0\,
S(0) => \c[4]_i_5_n_0\
);
\c_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \c_reg[4]_i_1_n_6\,
Q => c_reg(5),
R => clear
);
\c_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \c_reg[4]_i_1_n_5\,
Q => c_reg(6),
R => clear
);
\c_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \c_reg[4]_i_1_n_4\,
Q => c_reg(7),
R => clear
);
\c_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \c_reg[8]_i_1_n_7\,
Q => c_reg(8),
R => clear
);
\c_reg[8]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \c_reg[4]_i_1_n_0\,
CO(3) => \c_reg[8]_i_1_n_0\,
CO(2) => \c_reg[8]_i_1_n_1\,
CO(1) => \c_reg[8]_i_1_n_2\,
CO(0) => \c_reg[8]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \c_reg[8]_i_1_n_4\,
O(2) => \c_reg[8]_i_1_n_5\,
O(1) => \c_reg[8]_i_1_n_6\,
O(0) => \c_reg[8]_i_1_n_7\,
S(3) => \c[8]_i_2_n_0\,
S(2) => \c[8]_i_3_n_0\,
S(1) => \c[8]_i_4_n_0\,
S(0) => \c[8]_i_5_n_0\
);
\c_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \c_reg[8]_i_1_n_6\,
Q => c_reg(9),
R => clear
);
signal_out_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"80000000"
)
port map (
I0 => signal_out_i_2_n_0,
I1 => signal_out_i_3_n_0,
I2 => signal_out_i_4_n_0,
I3 => c_reg(0),
I4 => signal_out_i_5_n_0,
O => signal_out_i_1_n_0
);
signal_out_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"8000000000000000"
)
port map (
I0 => c_reg(3),
I1 => c_reg(4),
I2 => c_reg(1),
I3 => c_reg(2),
I4 => c_reg(6),
I5 => c_reg(5),
O => signal_out_i_2_n_0
);
signal_out_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"8000000000000000"
)
port map (
I0 => c_reg(21),
I1 => c_reg(22),
I2 => c_reg(19),
I3 => c_reg(20),
I4 => signal_in,
I5 => c_reg(23),
O => signal_out_i_3_n_0
);
signal_out_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"8000000000000000"
)
port map (
I0 => c_reg(15),
I1 => c_reg(16),
I2 => c_reg(13),
I3 => c_reg(14),
I4 => c_reg(18),
I5 => c_reg(17),
O => signal_out_i_4_n_0
);
signal_out_i_5: unisim.vcomponents.LUT6
generic map(
INIT => X"8000000000000000"
)
port map (
I0 => c_reg(9),
I1 => c_reg(10),
I2 => c_reg(7),
I3 => c_reg(8),
I4 => c_reg(12),
I5 => c_reg(11),
O => signal_out_i_5_n_0
);
signal_out_reg: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => signal_out_i_1_n_0,
Q => signal_out,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_debounce_0_0 is
port (
clk : in STD_LOGIC;
signal_in : in STD_LOGIC;
signal_out : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_debounce_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_debounce_0_0 : entity is "system_debounce_0_0,debounce,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_debounce_0_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_debounce_0_0 : entity is "debounce,Vivado 2016.4";
end system_debounce_0_0;
architecture STRUCTURE of system_debounce_0_0 is
begin
U0: entity work.system_debounce_0_0_debounce
port map (
clk => clk,
signal_in => signal_in,
signal_out => signal_out
);
end STRUCTURE;
| mit |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_dual_fusion/zed_dual_fusion.srcs/sources_1/bd/system/ip/system_rgb888_to_g8_1_0/system_rgb888_to_g8_1_0_stub.vhdl | 1 | 1356 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Tue May 30 22:30:37 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub -rename_top system_rgb888_to_g8_1_0 -prefix
-- system_rgb888_to_g8_1_0_ system_rgb888_to_g8_1_0_stub.vhdl
-- Design : system_rgb888_to_g8_1_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity system_rgb888_to_g8_1_0 is
Port (
clk : in STD_LOGIC;
rgb888 : in STD_LOGIC_VECTOR ( 23 downto 0 );
g8 : out STD_LOGIC_VECTOR ( 7 downto 0 )
);
end system_rgb888_to_g8_1_0;
architecture stub of system_rgb888_to_g8_1_0 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clk,rgb888[23:0],g8[7:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "rgb888_to_g8,Vivado 2016.4";
begin
end;
| mit |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_transform_test/zed_transform_test.srcs/sources_1/bd/system/ip/system_vga_hessian_0_0/synth/system_vga_hessian_0_0.vhd | 1 | 4403 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:vga_hessian:1.0
-- IP Revision: 41
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_vga_hessian_0_0 IS
PORT (
clk_x16 : IN STD_LOGIC;
active : IN STD_LOGIC;
rst : IN STD_LOGIC;
x_addr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
y_addr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
g_in : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
hessian_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END system_vga_hessian_0_0;
ARCHITECTURE system_vga_hessian_0_0_arch OF system_vga_hessian_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_vga_hessian_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT vga_hessian IS
GENERIC (
ROW_WIDTH : INTEGER
);
PORT (
clk_x16 : IN STD_LOGIC;
active : IN STD_LOGIC;
rst : IN STD_LOGIC;
x_addr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
y_addr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
g_in : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
hessian_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT vga_hessian;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF system_vga_hessian_0_0_arch: ARCHITECTURE IS "vga_hessian,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF system_vga_hessian_0_0_arch : ARCHITECTURE IS "system_vga_hessian_0_0,vga_hessian,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF system_vga_hessian_0_0_arch: ARCHITECTURE IS "system_vga_hessian_0_0,vga_hessian,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=user,x_ipName=vga_hessian,x_ipVersion=1.0,x_ipCoreRevision=41,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,ROW_WIDTH=10}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF rst: SIGNAL IS "xilinx.com:signal:reset:1.0 rst RST";
BEGIN
U0 : vga_hessian
GENERIC MAP (
ROW_WIDTH => 10
)
PORT MAP (
clk_x16 => clk_x16,
active => active,
rst => rst,
x_addr => x_addr,
y_addr => y_addr,
g_in => g_in,
hessian_out => hessian_out
);
END system_vga_hessian_0_0_arch;
| mit |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | general_ip/affine_transform/affine_transform.srcs/sources_1/bd/affine_block/ip/affine_block_ieee754_fp_multiplier_0_0/sim/affine_block_ieee754_fp_multiplier_0_0.vhd | 2 | 3266 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:ieee754_fp_multiplier:1.0
-- IP Revision: 5
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY affine_block_ieee754_fp_multiplier_0_0 IS
PORT (
x : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
y : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
z : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END affine_block_ieee754_fp_multiplier_0_0;
ARCHITECTURE affine_block_ieee754_fp_multiplier_0_0_arch OF affine_block_ieee754_fp_multiplier_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF affine_block_ieee754_fp_multiplier_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT ieee754_fp_multiplier IS
PORT (
x : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
y : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
z : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT ieee754_fp_multiplier;
BEGIN
U0 : ieee754_fp_multiplier
PORT MAP (
x => x,
y => y,
z => z
);
END affine_block_ieee754_fp_multiplier_0_0_arch;
| mit |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_transform_test/zed_transform_test.srcs/sources_1/bd/system/ip/system_vga_transform_0_1/sim/system_vga_transform_0_1.vhd | 1 | 4361 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:vga_transform:1.0
-- IP Revision: 4
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_vga_transform_0_1 IS
PORT (
clk : IN STD_LOGIC;
enable : IN STD_LOGIC;
x_addr_in : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
y_addr_in : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
rot_m00 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
rot_m01 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
rot_m10 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
rot_m11 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
t_x : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
t_y : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
x_addr_out : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
y_addr_out : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END system_vga_transform_0_1;
ARCHITECTURE system_vga_transform_0_1_arch OF system_vga_transform_0_1 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_vga_transform_0_1_arch: ARCHITECTURE IS "yes";
COMPONENT vga_transform IS
PORT (
clk : IN STD_LOGIC;
enable : IN STD_LOGIC;
x_addr_in : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
y_addr_in : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
rot_m00 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
rot_m01 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
rot_m10 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
rot_m11 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
t_x : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
t_y : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
x_addr_out : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
y_addr_out : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END COMPONENT vga_transform;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clk CLK";
BEGIN
U0 : vga_transform
PORT MAP (
clk => clk,
enable => enable,
x_addr_in => x_addr_in,
y_addr_in => y_addr_in,
rot_m00 => rot_m00,
rot_m01 => rot_m01,
rot_m10 => rot_m10,
rot_m11 => rot_m11,
t_x => t_x,
t_y => t_y,
x_addr_out => x_addr_out,
y_addr_out => y_addr_out
);
END system_vga_transform_0_1_arch;
| mit |
freecores/tcp_socket | source/atlys.vhd | 1 | 21715 | --------------------------------------------------------------------------------
---
--- CHIPS - 2.0 Simple Web App Demo
---
--- :Author: Jonathan P Dawson
--- :Date: 17/10/2013
--- :email: [email protected]
--- :license: MIT
--- :Copyright: Copyright (C) Jonathan P Dawson 2013
---
--- A Serial Input Component
---
--------------------------------------------------------------------------------
---
--- +--------------+
--- | CLOCK TREE |
--- +--------------+
--- | >-- CLK1 (50MHz) ---> CLK
--- CLK_IN >--> |
--- | >-- CLK2 (100MHz)
--- | | +-------+
--- | +-- CLK3 (125MHz) ->+ ODDR2 +-->[GTXCLK]
--- | | | |
--- | +-- CLK3_N (125MHZ) ->+ |
--- | | +-------+
--- RST >-----> >-- CLK4 (200MHz)
--- | |
--- | |
--- | | CLK >--+--------+
--- | | | |
--- | | +--v-+ +--v-+
--- | | | | | |
--- | LOCKED >------> >---> >-------> INTERNAL_RESET
--- | | | | | |
--- +--------------+ +----+ +----+
---
--- +-------------+ +--------------+
--- | SERVER | | USER DESIGN |
--- +-------------+ +--------------+
--- | | | |
--- | >-----> <-------< SWITCHES
--- | | | |
--- | <-----< >-------> LEDS
--- | | | |
--- | | | <-------< BUTTONS
--- | | | |
--- | | +----^----v----+
--- | | | |
--- | | +----^----v----+
--- | | | UART |
--- | | +--------------+
--- | | | >-------> RS232-TX
--- | | | |
--- +---v-----^---+ | <-------< RS232-RX
--- | | +--------------+
--- +---v-----^---+
--- | ETHERNET |
--- | MAC |
--- +-------------+
--- | +------> [PHY_RESET]
--- | |
---[RXCLK] ----->+ +------> [TXCLK]
--- | |
--- 125MHZ ----->+ +------> open
--- | |
--- [RXD] ----->+ +------> [TXD]
--- | |
--- [RXDV] ----->+ +------> [TXEN]
--- | |
--- [RXER] ----->+ +------> [TXER]
--- | |
--- | |
--- +-------------+
---
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity ATLYS is
port(
CLK_IN : in std_logic;
RST : in std_logic;
--PHY INTERFACE
TX : out std_logic;
RX : in std_logic;
PHY_RESET : out std_logic;
RXDV : in std_logic;
RXER : in std_logic;
RXCLK : in std_logic;
RXD : in std_logic_vector(7 downto 0);
TXCLK : in std_logic;
GTXCLK : out std_logic;
TXD : out std_logic_vector(7 downto 0);
TXEN : out std_logic;
TXER : out std_logic;
--LEDS
GPIO_LEDS : out std_logic_vector(7 downto 0);
GPIO_SWITCHES : in std_logic_vector(7 downto 0);
GPIO_BUTTONS : in std_logic_vector(3 downto 0);
--RS232 INTERFACE
RS232_RX : in std_logic;
RS232_TX : out std_logic
);
end entity ATLYS;
architecture RTL of ATLYS is
component gigabit_ethernet is
port(
CLK : in std_logic;
RST : in std_logic;
--Ethernet Clock
CLK_125_MHZ : in std_logic;
--GMII IF
GTXCLK : out std_logic;
TXCLK : in std_logic;
TXER : out std_logic;
TXEN : out std_logic;
TXD : out std_logic_vector(7 downto 0);
PHY_RESET : out std_logic;
RXCLK : in std_logic;
RXER : in std_logic;
RXDV : in std_logic;
RXD : in std_logic_vector(7 downto 0);
--RX STREAM
TX : in std_logic_vector(15 downto 0);
TX_STB : in std_logic;
TX_ACK : out std_logic;
--RX STREAM
RX : out std_logic_vector(15 downto 0);
RX_STB : out std_logic;
RX_ACK : in std_logic
);
end component gigabit_ethernet;
component SERVER is
port(
CLK : in std_logic;
RST : in std_logic;
--ETH RX STREAM
INPUT_ETH_RX : in std_logic_vector(15 downto 0);
INPUT_ETH_RX_STB : in std_logic;
INPUT_ETH_RX_ACK : out std_logic;
--ETH TX STREAM
output_eth_tx : out std_logic_vector(15 downto 0);
OUTPUT_ETH_TX_STB : out std_logic;
OUTPUT_ETH_TX_ACK : in std_logic;
--SOCKET RX STREAM
INPUT_SOCKET : in std_logic_vector(15 downto 0);
INPUT_SOCKET_STB : in std_logic;
INPUT_SOCKET_ACK : out std_logic;
--SOCKET TX STREAM
OUTPUT_SOCKET : out std_logic_vector(15 downto 0);
OUTPUT_SOCKET_STB : out std_logic;
OUTPUT_SOCKET_ACK : in std_logic
);
end component;
component USER_DESIGN is
port(
CLK : in std_logic;
RST : in std_logic;
OUTPUT_LEDS : out std_logic_vector(15 downto 0);
OUTPUT_LEDS_STB : out std_logic;
OUTPUT_LEDS_ACK : in std_logic;
INPUT_SWITCHES : in std_logic_vector(15 downto 0);
INPUT_SWITCHES_STB : in std_logic;
INPUT_SWITCHES_ACK : out std_logic;
INPUT_BUTTONS : in std_logic_vector(15 downto 0);
INPUT_BUTTONS_STB : in std_logic;
INPUT_BUTTONS_ACK : out std_logic;
--SOCKET RX STREAM
INPUT_SOCKET : in std_logic_vector(15 downto 0);
INPUT_SOCKET_STB : in std_logic;
INPUT_SOCKET_ACK : out std_logic;
--SOCKET TX STREAM
OUTPUT_SOCKET : out std_logic_vector(15 downto 0);
OUTPUT_SOCKET_STB : out std_logic;
OUTPUT_SOCKET_ACK : in std_logic;
--RS232 RX STREAM
INPUT_RS232_RX : in std_logic_vector(15 downto 0);
INPUT_RS232_RX_STB : in std_logic;
INPUT_RS232_RX_ACK : out std_logic;
--RS232 TX STREAM
OUTPUT_RS232_TX : out std_logic_vector(15 downto 0);
OUTPUT_RS232_TX_STB : out std_logic;
OUTPUT_RS232_TX_ACK : in std_logic
);
end component;
component SERIAL_INPUT is
generic(
CLOCK_FREQUENCY : integer;
BAUD_RATE : integer
);
port(
CLK : in std_logic;
RST : in std_logic;
RX : in std_logic;
OUT1 : out std_logic_vector(7 downto 0);
OUT1_STB : out std_logic;
OUT1_ACK : in std_logic
);
end component SERIAL_INPUT;
component serial_output is
generic(
CLOCK_FREQUENCY : integer;
BAUD_RATE : integer
);
port(
CLK : in std_logic;
RST : in std_logic;
TX : out std_logic;
IN1 : in std_logic_vector(7 downto 0);
IN1_STB : in std_logic;
IN1_ACK : out std_logic
);
end component serial_output;
--chips signals
signal CLK : std_logic;
signal RST_INV : std_logic;
--clock tree signals
signal clkin1 : std_logic;
-- Output clock buffering
signal clkfb : std_logic;
signal clk0 : std_logic;
signal clk2x : std_logic;
signal clkfx : std_logic;
signal clkfx180 : std_logic;
signal clkdv : std_logic;
signal clkfbout : std_logic;
signal locked_internal : std_logic;
signal status_internal : std_logic_vector(7 downto 0);
signal CLK_OUT1 : std_logic;
signal CLK_OUT2 : std_logic;
signal CLK_OUT3 : std_logic;
signal CLK_OUT3_N : std_logic;
signal CLK_OUT4 : std_logic;
signal NOT_LOCKED : std_logic;
signal INTERNAL_RST : std_logic;
signal RXD1 : std_logic;
signal TX_LOCKED : std_logic;
signal INTERNAL_RXCLK : std_logic;
signal INTERNAL_RXCLK_BUF: std_logic;
signal RXCLK_BUF : std_logic;
signal INTERNAL_TXD : std_logic_vector(7 downto 0);
signal INTERNAL_TXEN : std_logic;
signal INTERNAL_TXER : std_logic;
signal OUTPUT_LEDS : std_logic_vector(15 downto 0);
signal OUTPUT_LEDS_STB : std_logic;
signal OUTPUT_LEDS_ACK : std_logic;
signal INPUT_SWITCHES : std_logic_vector(15 downto 0);
signal INPUT_SWITCHES_STB : std_logic;
signal INPUT_SWITCHES_ACK : std_logic;
signal GPIO_SWITCHES_D : std_logic_vector(7 downto 0);
signal INPUT_BUTTONS : std_logic_vector(15 downto 0);
signal INPUT_BUTTONS_STB : std_logic;
signal INPUT_BUTTONS_ACK : std_logic;
signal GPIO_BUTTONS_D : std_logic_vector(3 downto 0);
--ETH RX STREAM
signal ETH_RX : std_logic_vector(15 downto 0);
signal ETH_RX_STB : std_logic;
signal ETH_RX_ACK : std_logic;
--ETH TX STREAM
signal ETH_TX : std_logic_vector(15 downto 0);
signal ETH_TX_STB : std_logic;
signal ETH_TX_ACK : std_logic;
--RS232 RX STREAM
signal INPUT_RS232_RX : std_logic_vector(15 downto 0);
signal INPUT_RS232_RX_STB : std_logic;
signal INPUT_RS232_RX_ACK : std_logic;
--RS232 TX STREAM
signal OUTPUT_RS232_TX : std_logic_vector(15 downto 0);
signal OUTPUT_RS232_TX_STB : std_logic;
signal OUTPUT_RS232_TX_ACK : std_logic;
--SOCKET RX STREAM
signal INPUT_SOCKET : std_logic_vector(15 downto 0);
signal INPUT_SOCKET_STB : std_logic;
signal INPUT_SOCKET_ACK : std_logic;
--SOCKET TX STREAM
signal OUTPUT_SOCKET : std_logic_vector(15 downto 0);
signal OUTPUT_SOCKET_STB : std_logic;
signal OUTPUT_SOCKET_ACK : std_logic;
begin
gigabit_ethernet_inst_1 : gigabit_ethernet port map(
CLK => CLK,
RST => INTERNAL_RST,
--Ethernet Clock
CLK_125_MHZ => CLK_OUT3,
--GMII IF
GTXCLK => open,
TXCLK => TXCLK,
TXER => INTERNAL_TXER,
TXEN => INTERNAL_TXEN,
TXD => INTERNAL_TXD,
PHY_RESET => PHY_RESET,
RXCLK => INTERNAL_RXCLK,
RXER => RXER,
RXDV => RXDV,
RXD => RXD,
--RX STREAM
TX => ETH_TX,
TX_STB => ETH_TX_STB,
TX_ACK => ETH_TX_ACK,
--RX STREAM
RX => ETH_RX,
RX_STB => ETH_RX_STB,
RX_ACK => ETH_RX_ACK
);
SERVER_INST_1 : SERVER port map(
CLK => CLK,
RST => INTERNAL_RST,
--ETH RX STREAM
INPUT_ETH_RX => ETH_RX,
INPUT_ETH_RX_STB => ETH_RX_STB,
INPUT_ETH_RX_ACK => ETH_RX_ACK,
--ETH TX STREAM
OUTPUT_ETH_TX => ETH_TX,
OUTPUT_ETH_TX_STB => ETH_TX_STB,
OUTPUT_ETH_TX_ACK => ETH_TX_ACK,
--SOCKET STREAM
INPUT_SOCKET => INPUT_SOCKET,
INPUT_SOCKET_STB => INPUT_SOCKET_STB,
INPUT_SOCKET_ACK => INPUT_SOCKET_ACK,
--SOCKET STREAM
OUTPUT_SOCKET => OUTPUT_SOCKET,
OUTPUT_SOCKET_STB => OUTPUT_SOCKET_STB,
OUTPUT_SOCKET_ACK => OUTPUT_SOCKET_ACK
);
USER_DESIGN_INST_1 : USER_DESIGN port map(
CLK => CLK,
RST => INTERNAL_RST,
OUTPUT_LEDS => OUTPUT_LEDS,
OUTPUT_LEDS_STB => OUTPUT_LEDS_STB,
OUTPUT_LEDS_ACK => OUTPUT_LEDS_ACK,
INPUT_SWITCHES => INPUT_SWITCHES,
INPUT_SWITCHES_STB => INPUT_SWITCHES_STB,
INPUT_SWITCHES_ACK => INPUT_SWITCHES_ACK,
INPUT_BUTTONS => INPUT_BUTTONS,
INPUT_BUTTONS_STB => INPUT_BUTTONS_STB,
INPUT_BUTTONS_ACK => INPUT_BUTTONS_ACK,
--RS232 RX STREAM
INPUT_RS232_RX => INPUT_RS232_RX,
INPUT_RS232_RX_STB => INPUT_RS232_RX_STB,
INPUT_RS232_RX_ACK => INPUT_RS232_RX_ACK,
--RS232 TX STREAM
OUTPUT_RS232_TX => OUTPUT_RS232_TX,
OUTPUT_RS232_TX_STB => OUTPUT_RS232_TX_STB,
OUTPUT_RS232_TX_ACK => OUTPUT_RS232_TX_ACK,
--SOCKET STREAM
INPUT_SOCKET => OUTPUT_SOCKET,
INPUT_SOCKET_STB => OUTPUT_SOCKET_STB,
INPUT_SOCKET_ACK => OUTPUT_SOCKET_ACK,
--SOCKET STREAM
OUTPUT_SOCKET => INPUT_SOCKET,
OUTPUT_SOCKET_STB => INPUT_SOCKET_STB,
OUTPUT_SOCKET_ACK => INPUT_SOCKET_ACK
);
SERIAL_OUTPUT_INST_1 : serial_output generic map(
CLOCK_FREQUENCY => 50000000,
BAUD_RATE => 115200
)port map(
CLK => CLK,
RST => INTERNAL_RST,
TX => RS232_TX,
IN1 => OUTPUT_RS232_TX(7 downto 0),
IN1_STB => OUTPUT_RS232_TX_STB,
IN1_ACK => OUTPUT_RS232_TX_ACK
);
SERIAL_INPUT_INST_1 : SERIAL_INPUT generic map(
CLOCK_FREQUENCY => 50000000,
BAUD_RATE => 115200
) port map (
CLK => CLK,
RST => INTERNAL_RST,
RX => RS232_RX,
OUT1 => INPUT_RS232_RX(7 downto 0),
OUT1_STB => INPUT_RS232_RX_STB,
OUT1_ACK => INPUT_RS232_RX_ACK
);
INPUT_RS232_RX(15 downto 8) <= (others => '0');
process
begin
wait until rising_edge(CLK);
NOT_LOCKED <= not LOCKED_INTERNAL;
INTERNAL_RST <= NOT_LOCKED;
if OUTPUT_LEDS_STB = '1' then
GPIO_LEDS <= OUTPUT_LEDS(7 downto 0);
end if;
OUTPUT_LEDS_ACK <= '1';
INPUT_SWITCHES_STB <= '1';
GPIO_SWITCHES_D <= GPIO_SWITCHES;
INPUT_SWITCHES(7 downto 0) <= GPIO_SWITCHES_D;
INPUT_SWITCHES(15 downto 8) <= (others => '0');
INPUT_BUTTONS_STB <= '1';
GPIO_BUTTONS_D <= GPIO_BUTTONS;
INPUT_BUTTONS(3 downto 0) <= GPIO_BUTTONS_D;
INPUT_BUTTONS(15 downto 4) <= (others => '0');
end process;
-------------------------
-- Output Output
-- Clock Freq (MHz)
-------------------------
-- CLK_OUT1 50.000
-- CLK_OUT2 100.000
-- CLK_OUT3 125.000
-- CLK_OUT4 200.000
----------------------------------
-- Input Clock Input Freq (MHz)
----------------------------------
-- primary 200.000
-- Input buffering
--------------------------------------
clkin1_buf : IBUFG
port map
(O => clkin1,
I => CLK_IN);
-- Clocking primitive
--------------------------------------
-- Instantiation of the DCM primitive
-- * Unused inputs are tied off
-- * Unused outputs are labeled unused
dcm_sp_inst: DCM_SP
generic map
(CLKDV_DIVIDE => 2.000,
CLKFX_DIVIDE => 4,
CLKFX_MULTIPLY => 5,
CLKIN_DIVIDE_BY_2 => FALSE,
CLKIN_PERIOD => 10.0,
CLKOUT_PHASE_SHIFT => "NONE",
CLK_FEEDBACK => "1X",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
PHASE_SHIFT => 0,
STARTUP_WAIT => FALSE)
port map
-- Input clock
(CLKIN => clkin1,
CLKFB => clkfb,
-- Output clocks
CLK0 => clk0,
CLK90 => open,
CLK180 => open,
CLK270 => open,
CLK2X => clk2x,
CLK2X180 => open,
CLKFX => clkfx,
CLKFX180 => clkfx180,
CLKDV => clkdv,
-- Ports for dynamic phase shift
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => open,
-- Other control and status signals
LOCKED => TX_LOCKED,
STATUS => status_internal,
RST => RST_INV,
-- Unused pin, tie low
DSSEN => '0');
RST_INV <= not RST;
-- Output buffering
-------------------------------------
clkfb <= CLK_OUT2;
BUFG_INST1 : BUFG
port map
(O => CLK_OUT1,
I => clkdv);
BUFG_INST2 : BUFG
port map
(O => CLK_OUT2,
I => clk0);
BUFG_INST3 : BUFG
port map
(O => CLK_OUT3,
I => clkfx);
BUFG_INST4 : BUFG
port map
(O => CLK_OUT3_N,
I => clkfx180);
BUFG_INST5 : BUFG
port map
(O => CLK_OUT4,
I => clk2x);
ODDR2_INST1 : ODDR2
generic map(
DDR_ALIGNMENT => "NONE", -- Sets output alignment to "NONE", "C0", "C1"
INIT => '0', -- Sets initial state of the Q output to '0' or '1'
SRTYPE => "SYNC"
) port map (
Q => GTXCLK, -- 1-bit output data
C0 => CLK_OUT3, -- 1-bit clock input
C1 => CLK_OUT3_N, -- 1-bit clock input
CE => '1', -- 1-bit clock enable input
D0 => '1', -- 1-bit data input (associated with C0)
D1 => '0', -- 1-bit data input (associated with C1)
R => '0', -- 1-bit reset input
S => '0' -- 1-bit set input
);
-- Input buffering
--------------------------------------
BUFG_INST6 : IBUFG
port map
(O => RXCLK_BUF,
I => RXCLK);
-- DCM
--------------------------------------
dcm_sp_inst2: DCM_SP
generic map
(CLKDV_DIVIDE => 2.000,
CLKFX_DIVIDE => 4,
CLKFX_MULTIPLY => 5,
CLKIN_DIVIDE_BY_2 => FALSE,
CLKIN_PERIOD => 8.0,
CLKOUT_PHASE_SHIFT => "FIXED",
CLK_FEEDBACK => "1X",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
PHASE_SHIFT => 14,
STARTUP_WAIT => FALSE)
port map
-- Input clock
(CLKIN => RXCLK_BUF,
CLKFB => INTERNAL_RXCLK,
-- Output clocks
CLK0 => INTERNAL_RXCLK_BUF,
CLK90 => open,
CLK180 => open,
CLK270 => open,
CLK2X => open,
CLK2X180 => open,
CLKFX => open,
CLKFX180 => open,
CLKDV => open,
-- Ports for dynamic phase shift
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => open,
-- Other control and status signals
LOCKED => open,
STATUS => open,
RST => RST_INV,
-- Unused pin, tie low
DSSEN => '0');
-- Output buffering
--------------------------------------
BUFG_INST7 : BUFG
port map
(O => INTERNAL_RXCLK,
I => INTERNAL_RXCLK_BUF);
LOCKED_INTERNAL <= TX_LOCKED;
-- Use ODDRs for clock/data forwarding
--------------------------------------
ODDR2_INST2_GENERATE : for I in 0 to 7 generate
ODDR2_INST2 : ODDR2
generic map(
DDR_ALIGNMENT => "NONE", -- Sets output alignment to "NONE", "C0", "C1"
INIT => '0', -- Sets initial state of the Q output to '0' or '1'
SRTYPE => "SYNC"
) port map (
Q => TXD(I), -- 1-bit output data
C0 => CLK_OUT3, -- 1-bit clock input
C1 => CLK_OUT3_N, -- 1-bit clock input
CE => '1', -- 1-bit clock enable input
D0 => INTERNAL_TXD(I), -- 1-bit data input (associated with C0)
D1 => INTERNAL_TXD(I), -- 1-bit data input (associated with C1)
R => '0', -- 1-bit reset input
S => '0' -- 1-bit set input
);
end generate;
ODDR2_INST3 : ODDR2
generic map(
DDR_ALIGNMENT => "NONE", -- Sets output alignment to "NONE", "C0", "C1"
INIT => '0', -- Sets initial state of the Q output to '0' or '1'
SRTYPE => "SYNC"
) port map (
Q => TXEN, -- 1-bit output data
C0 => CLK_OUT3, -- 1-bit clock input
C1 => CLK_OUT3_N, -- 1-bit clock input
CE => '1', -- 1-bit clock enable input
D0 => INTERNAL_TXEN, -- 1-bit data input (associated with C0)
D1 => INTERNAL_TXEN, -- 1-bit data input (associated with C1)
R => '0', -- 1-bit reset input
S => '0' -- 1-bit set input
);
ODDR2_INST4 : ODDR2
generic map(
DDR_ALIGNMENT => "NONE", -- Sets output alignment to "NONE", "C0", "C1"
INIT => '0', -- Sets initial state of the Q output to '0' or '1'
SRTYPE => "SYNC"
) port map (
Q => TXER, -- 1-bit output data
C0 => CLK_OUT3, -- 1-bit clock input
C1 => CLK_OUT3_N, -- 1-bit clock input
CE => '1', -- 1-bit clock enable input
D0 => INTERNAL_TXER, -- 1-bit data input (associated with C0)
D1 => INTERNAL_TXER, -- 1-bit data input (associated with C1)
R => '0', -- 1-bit reset input
S => '0' -- 1-bit set input
);
-- Chips CLK frequency selection
-------------------------------------
CLK <= CLK_OUT1; --50 MHz
--CLK <= CLK_OUT2; --100 MHz
--CLK <= CLK_OUT3; --125 MHz
--CLK <= CLK_OUT4; --200 MHz
end architecture RTL;
| mit |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | general_ip/svd_2x2/svd_2x2.srcs/sources_1/ip/sqrt/demo_tb/tb_sqrt.vhd | 1 | 15398 | --------------------------------------------------------------------------------
-- (c) Copyright 2011 - 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
-- Description:
-- This is an example testbench for the CORDIC IP core.
-- The testbench has been generated by Vivado to accompany the IP core
-- instance you have generated.
--
-- This testbench is for demonstration purposes only. See note below for
-- instructions on how to use it with your core.
--
-- See the CORDIC product guide for further information
-- about this core.
--
--------------------------------------------------------------------------------
-- Using this testbench
--
-- This testbench instantiates your generated CORDIC core
-- instance named "sqrt".
--
-- Use Vivado's Run Simulation flow to run this testbench. See the Vivado
-- documentation for details.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
entity tb_sqrt is
end tb_sqrt;
architecture tb of tb_sqrt is
-----------------------------------------------------------------------
-- Timing constants
-----------------------------------------------------------------------
constant CLOCK_PERIOD : time := 100 ns;
constant T_HOLD : time := 10 ns;
constant T_STROBE : time := CLOCK_PERIOD - (1 ns);
constant TEST_CYCLES : integer := 3000;
constant PHASE_CYCLES : integer := 1000;
-----------------------------------------------------------------------
-- DUT input signals
-----------------------------------------------------------------------
-- General inputs
signal aclk : std_logic := '0'; -- the master clock
-- Slave channel CARTESIAN inputs
signal s_axis_cartesian_tvalid : std_logic := '0'; -- TVALID for channel S_AXIS_CARTESIAN
signal s_axis_cartesian_tdata : std_logic_vector(15 downto 0) := (others => 'X'); -- TDATA for channel S_AXIS_CARTESIAN
-- Slave channel PHASE inputs
signal s_axis_phase_tvalid : std_logic := '0'; -- TVALID for channel S_AXIS_PHASE
signal s_axis_phase_tdata : std_logic_vector(15 downto 0) := (others => 'X'); -- TDATA for channel S_AXIS_PHASE
-----------------------------------------------------------------------
-- DUT output signals
-----------------------------------------------------------------------
-- Master channel DOUT outputs
signal m_axis_dout_tvalid : std_logic := '0'; -- TVALID for channel M_AXIS_DOUT
signal m_axis_dout_tdata : std_logic_vector(15 downto 0) := (others => '0'); -- TDATA for channel M_AXIS_DOUT
-----------------------------------------------------------------------
-- Aliases for AXI channel TDATA fields
-- These are a convenience for viewing data in a simulator waveform viewer.
-- If using ModelSim or Questa, add "-voptargs=+acc=n" to the vsim command
-- to prevent the simulator optimizing away these signals.
-----------------------------------------------------------------------
signal s_axis_cartesian_tdata_real : std_logic_vector(15 downto 0) := (others => '0');
signal s_axis_cartesian_tdata_imag : std_logic_vector(15 downto 0) := (others => '0');
signal s_axis_phase_tdata_real : std_logic_vector(15 downto 0) := (others => '0');
signal m_axis_dout_tdata_real : std_logic_vector(15 downto 0) := (others => '0');
signal m_axis_dout_tdata_imag : std_logic_vector(15 downto 0) := (others => '0');
signal m_axis_dout_tdata_phase : std_logic_vector(15 downto 0) := (others => '0');
-----------------------------------------------------------------------
-- Testbench signals
-----------------------------------------------------------------------
signal cycles : integer := 0; -- Clock cycle counter
-----------------------------------------------------------------------
-- Constants, types and functions to create input data
-- The CORDIC is fed two sinusoids exp(+/-jwt) of different frequencies and amplitudes:
-- channel CARTESIAN: exp(+jwt), frequency = clock / 30,
-- channel PHASE: exp(-jwt), frequency = clock / 32,
-----------------------------------------------------------------------
constant IP_CARTESIAN_DEPTH : integer := 30;
constant IP_CARTESIAN_WIDTH : integer := 16;
constant IP_CARTESIAN_SHIFT : integer := 3; -- bit shift for amplitude
constant IP_PHASE_DEPTH : integer := 32;
constant IP_PHASE_WIDTH : integer := 16;
constant IP_PHASE_SHIFT : integer := 0; -- no bit shift, max amplitude
type T_IP_INT_ENTRY is record
re : integer;
im : integer;
end record;
type T_IP_CARTESIAN_ENTRY is record
re : std_logic_vector(IP_CARTESIAN_WIDTH-1 downto 0);
im : std_logic_vector(IP_CARTESIAN_WIDTH-1 downto 0);
end record;
type T_IP_PHASE_ENTRY is record
re : std_logic_vector(IP_PHASE_WIDTH-1 downto 0);
end record;
type T_IP_CARTESIAN_TABLE is array (0 to IP_CARTESIAN_DEPTH-1) of T_IP_CARTESIAN_ENTRY;
type T_IP_PHASE_TABLE is array (0 to IP_PHASE_DEPTH-1) of T_IP_PHASE_ENTRY;
-- Common function to calculate sine and cosine values
function create_ip_entry(index, depth, width : integer) return T_IP_INT_ENTRY is
variable result : T_IP_INT_ENTRY;
variable theta : real;
variable limited_width : integer := width - 2;
begin
if limited_width > 30 then
limited_width := 30; --avoid integer overflow
end if;
theta := real(index) / real(depth) * 2.0 * MATH_PI;
result.re := integer(round(cos(theta) * real(2**limited_width)));
result.im := integer(round(sin(theta) * real(2**limited_width)));
return result;
end function create_ip_entry;
-- Use separate functions to calculate channel S_AXIS_CARTESIAN and S_AXIS_PHASE sinusoids as they return different types
function create_ip_cartesian_table return T_IP_CARTESIAN_TABLE is
variable result : T_IP_CARTESIAN_TABLE;
variable entry_int : T_IP_INT_ENTRY;
begin
for i in 0 to IP_CARTESIAN_DEPTH-1 loop
entry_int := create_ip_entry(i, IP_CARTESIAN_DEPTH, IP_CARTESIAN_WIDTH - IP_CARTESIAN_SHIFT);
result(i).re := std_logic_vector(to_signed(entry_int.re, IP_CARTESIAN_WIDTH));
result(i).im := std_logic_vector(to_signed(entry_int.im, IP_CARTESIAN_WIDTH));
end loop;
return result;
end function create_ip_cartesian_table;
function create_ip_phase_table return T_IP_PHASE_TABLE is
variable result : T_IP_PHASE_TABLE;
variable entry_int : T_IP_INT_ENTRY;
begin
for i in 0 to IP_PHASE_DEPTH-1 loop
entry_int := create_ip_entry(IP_PHASE_DEPTH-1-i, IP_PHASE_DEPTH, IP_PHASE_WIDTH - IP_PHASE_SHIFT); -- note rotation direction
result(i).re := std_logic_vector(to_signed(entry_int.re, IP_PHASE_WIDTH));
end loop;
return result;
end function create_ip_phase_table;
-- Call the functions to create the data
constant IP_CARTESIAN_DATA : T_IP_CARTESIAN_TABLE := create_ip_cartesian_table;
constant IP_PHASE_DATA : T_IP_PHASE_TABLE := create_ip_phase_table;
begin
-----------------------------------------------------------------------
-- Instantiate the DUT
-----------------------------------------------------------------------
dut : entity work.sqrt
port map (
aclk => aclk,
s_axis_cartesian_tvalid => s_axis_cartesian_tvalid,
s_axis_cartesian_tdata => s_axis_cartesian_tdata,
m_axis_dout_tvalid => m_axis_dout_tvalid,
m_axis_dout_tdata => m_axis_dout_tdata
);
-----------------------------------------------------------------------
-- Generate clock
-----------------------------------------------------------------------
clock_gen : process
begin
aclk <= '0';
wait for CLOCK_PERIOD;
loop
cycles <= cycles + 1;
aclk <= '0';
wait for CLOCK_PERIOD/2;
aclk <= '1';
wait for CLOCK_PERIOD/2;
if cycles >= TEST_CYCLES then
report "Not a real failure. Simulation finished successfully. Test completed successfully" severity failure;
wait;
end if;
end loop;
end process clock_gen;
-----------------------------------------------------------------------
-- Generate inputs
-----------------------------------------------------------------------
stimuli : process
variable ip_cartesian_index : integer := 0;
variable ip_phase_index : integer := 0;
variable cartesian_tvalid_nxt : std_logic := '0';
variable phase_tvalid_nxt : std_logic := '0';
variable phase2_cycles : integer := 1;
variable phase2_count : integer := 0;
constant PHASE2_LIMIT : integer := 30;
begin
-- Test is stopped in clock_gen process, use endless loop here
loop
-- Drive inputs T_HOLD time after rising edge of clock
wait until rising_edge(aclk);
wait for T_HOLD;
-- Drive AXI TVALID signals to demonstrate different types of operation
case cycles is -- do different types of operation at different phases of the test
when 0 to PHASE_CYCLES * 1 - 1 =>
-- Phase 1: inputs always valid, no missing input data
cartesian_tvalid_nxt := '1';
phase_tvalid_nxt := '1';
when PHASE_CYCLES * 1 to PHASE_CYCLES * 2 - 1 =>
-- Phase 2: deprive channel S_AXIS_CARTESIAN of valid transactions at an increasing rate
phase_tvalid_nxt := '1';
if phase2_count < phase2_cycles then
cartesian_tvalid_nxt := '0';
else
cartesian_tvalid_nxt := '1';
end if;
phase2_count := phase2_count + 1;
if phase2_count >= PHASE2_LIMIT then
phase2_count := 0;
phase2_cycles := phase2_cycles + 1;
end if;
when PHASE_CYCLES * 2 to PHASE_CYCLES * 3 - 1 =>
-- Phase 3: deprive channel S_AXIS_CARTESIAN of 1 out of 2 transactions, and channel S_AXIS_PHASE of 1 out of 3 transactions
if cycles mod 2 = 0 then
cartesian_tvalid_nxt := '0';
else
cartesian_tvalid_nxt := '1';
end if;
if cycles mod 3 = 0 then
phase_tvalid_nxt := '0';
else
phase_tvalid_nxt := '1';
end if;
when others =>
-- Test will stop imminently - do nothing
null;
end case;
-- Drive handshake signals with local variable values
s_axis_cartesian_tvalid <= cartesian_tvalid_nxt;
s_axis_phase_tvalid <= phase_tvalid_nxt;
-- Drive AXI slave channel CARTESIAN payload
-- Drive 'X's on payload signals when not valid
if cartesian_tvalid_nxt /= '1' then
s_axis_cartesian_tdata <= (others => 'X');
else
-- TDATA: Real and imaginary components are each 16 bits wide and byte-aligned at their LSBs
s_axis_cartesian_tdata(15 downto 0) <= IP_CARTESIAN_DATA(ip_cartesian_index).re;
end if;
-- Drive AXI slave channel PHASE payload
-- Drive 'X's on payload signals when not valid
if phase_tvalid_nxt /= '1' then
s_axis_phase_tdata <= (others => 'X');
else
-- TDATA: Real component is 16 bits wide and byte-aligned at its LSBs
s_axis_phase_tdata(15 downto 0) <= IP_PHASE_DATA(ip_phase_index).re;
end if;
-- Increment input data indices
if cartesian_tvalid_nxt = '1' then
ip_cartesian_index := ip_cartesian_index + 1;
if ip_cartesian_index = IP_CARTESIAN_DEPTH then
ip_cartesian_index := 0;
end if;
end if;
if phase_tvalid_nxt = '1' then
ip_phase_index := ip_phase_index + 1;
if ip_phase_index = IP_PHASE_DEPTH then
ip_phase_index := 0;
end if;
end if;
end loop;
end process stimuli;
-----------------------------------------------------------------------
-- Check outputs
-----------------------------------------------------------------------
check_outputs : process
variable check_ok : boolean := true;
begin
-- Check outputs T_STROBE time after rising edge of clock
wait until rising_edge(aclk);
wait for T_STROBE;
-- Do not check the output payload values, as this requires the behavioral model
-- which would make this demonstration testbench unwieldy.
-- Instead, check the protocol of the DOUT channel:
-- check that the payload is valid (not X) when TVALID is high
if m_axis_dout_tvalid = '1' then
if is_x(m_axis_dout_tdata) then
report "ERROR: m_axis_dout_tdata is invalid when m_axis_dout_tvalid is high" severity error;
check_ok := false;
end if;
end if;
assert check_ok
report "ERROR: terminating test with failures." severity failure;
end process check_outputs;
-----------------------------------------------------------------------
-- Assign TDATA fields to aliases, for easy simulator waveform viewing
-----------------------------------------------------------------------
s_axis_cartesian_tdata_real <= s_axis_cartesian_tdata(15 downto 0);
m_axis_dout_tdata_real <= m_axis_dout_tdata(15 downto 0);
end tb;
| mit |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_dual_fusion/zed_dual_fusion.srcs/sources_1/bd/system/ip/system_rgb565_to_rgb888_0_0/sim/system_rgb565_to_rgb888_0_0.vhd | 5 | 3321 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:rgb565_to_rgb888:1.0
-- IP Revision: 3
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_rgb565_to_rgb888_0_0 IS
PORT (
clk : IN STD_LOGIC;
rgb_565 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
rgb_888 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
);
END system_rgb565_to_rgb888_0_0;
ARCHITECTURE system_rgb565_to_rgb888_0_0_arch OF system_rgb565_to_rgb888_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_rgb565_to_rgb888_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT rgb565_to_rgb888 IS
PORT (
clk : IN STD_LOGIC;
rgb_565 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
rgb_888 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
);
END COMPONENT rgb565_to_rgb888;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clk CLK";
BEGIN
U0 : rgb565_to_rgb888
PORT MAP (
clk => clk,
rgb_565 => rgb_565,
rgb_888 => rgb_888
);
END system_rgb565_to_rgb888_0_0_arch;
| mit |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_transform_test/zed_transform_test.srcs/sources_1/bd/system/ip/system_util_ds_buf_0_0/sim/system_util_ds_buf_0_0.vhd | 1 | 5806 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:util_ds_buf:2.1
-- IP Revision: 6
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY util_ds_buf_v2_01_a;
USE util_ds_buf_v2_01_a.util_ds_buf;
ENTITY system_util_ds_buf_0_0 IS
PORT (
BUFG_I : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
BUFG_O : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END system_util_ds_buf_0_0;
ARCHITECTURE system_util_ds_buf_0_0_arch OF system_util_ds_buf_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_util_ds_buf_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT util_ds_buf IS
GENERIC (
C_BUF_TYPE : STRING;
C_SIZE : INTEGER
);
PORT (
IBUF_DS_P : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
IBUF_DS_N : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
IBUF_OUT : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
IBUF_DS_ODIV2 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
OBUF_IN : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
OBUF_DS_P : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
OBUF_DS_N : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
IOBUF_DS_P : INOUT STD_LOGIC_VECTOR(0 DOWNTO 0);
IOBUF_DS_N : INOUT STD_LOGIC_VECTOR(0 DOWNTO 0);
IOBUF_IO_T : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
IOBUF_IO_I : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
IOBUF_IO_O : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
BUFG_I : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
BUFG_O : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
BUFGCE_I : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
BUFGCE_CE : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
BUFGCE_O : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
BUFH_I : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
BUFH_O : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
BUFHCE_I : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
BUFHCE_CE : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
BUFHCE_O : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
BUFG_GT_I : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
BUFG_GT_CE : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
BUFG_GT_CEMASK : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
BUFG_GT_CLR : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
BUFG_GT_CLRMASK : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
BUFG_GT_DIV : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
BUFG_GT_O : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT util_ds_buf;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF BUFG_I: SIGNAL IS "xilinx.com:signal:clock:1.0 BUFG_I CLK";
ATTRIBUTE X_INTERFACE_INFO OF BUFG_O: SIGNAL IS "xilinx.com:signal:clock:1.0 BUFG_O CLK";
BEGIN
U0 : util_ds_buf
GENERIC MAP (
C_BUF_TYPE => "BUFG",
C_SIZE => 1
)
PORT MAP (
IBUF_DS_P => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
IBUF_DS_N => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
OBUF_IN => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
IOBUF_IO_T => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
IOBUF_IO_I => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
BUFG_I => BUFG_I,
BUFG_O => BUFG_O,
BUFGCE_I => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
BUFGCE_CE => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
BUFH_I => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
BUFHCE_I => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
BUFHCE_CE => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
BUFG_GT_I => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
BUFG_GT_CE => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
BUFG_GT_CEMASK => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
BUFG_GT_CLR => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
BUFG_GT_CLRMASK => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
BUFG_GT_DIV => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3))
);
END system_util_ds_buf_0_0_arch;
| mit |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_transform_test/zed_transform_test.srcs/sources_1/bd/system/ip/system_util_ds_buf_0_0/system_util_ds_buf_0_0_sim_netlist.vhdl | 1 | 6355 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Mon Jun 05 11:21:36 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim -rename_top system_util_ds_buf_0_0 -prefix
-- system_util_ds_buf_0_0_ system_util_ds_buf_0_0_sim_netlist.vhdl
-- Design : system_util_ds_buf_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_util_ds_buf_0_0_util_ds_buf is
port (
IBUF_DS_P : in STD_LOGIC_VECTOR ( 0 to 0 );
IBUF_DS_N : in STD_LOGIC_VECTOR ( 0 to 0 );
IBUF_OUT : out STD_LOGIC_VECTOR ( 0 to 0 );
IBUF_DS_ODIV2 : out STD_LOGIC_VECTOR ( 0 to 0 );
OBUF_IN : in STD_LOGIC_VECTOR ( 0 to 0 );
OBUF_DS_P : out STD_LOGIC_VECTOR ( 0 to 0 );
OBUF_DS_N : out STD_LOGIC_VECTOR ( 0 to 0 );
IOBUF_DS_P : inout STD_LOGIC_VECTOR ( 0 to 0 );
IOBUF_DS_N : inout STD_LOGIC_VECTOR ( 0 to 0 );
IOBUF_IO_T : in STD_LOGIC_VECTOR ( 0 to 0 );
IOBUF_IO_I : in STD_LOGIC_VECTOR ( 0 to 0 );
IOBUF_IO_O : out STD_LOGIC_VECTOR ( 0 to 0 );
BUFG_I : in STD_LOGIC_VECTOR ( 0 to 0 );
BUFG_O : out STD_LOGIC_VECTOR ( 0 to 0 );
BUFGCE_I : in STD_LOGIC_VECTOR ( 0 to 0 );
BUFGCE_CE : in STD_LOGIC_VECTOR ( 0 to 0 );
BUFGCE_O : out STD_LOGIC_VECTOR ( 0 to 0 );
BUFH_I : in STD_LOGIC_VECTOR ( 0 to 0 );
BUFH_O : out STD_LOGIC_VECTOR ( 0 to 0 );
BUFHCE_I : in STD_LOGIC_VECTOR ( 0 to 0 );
BUFHCE_CE : in STD_LOGIC_VECTOR ( 0 to 0 );
BUFHCE_O : out STD_LOGIC_VECTOR ( 0 to 0 );
BUFG_GT_I : in STD_LOGIC_VECTOR ( 0 to 0 );
BUFG_GT_CE : in STD_LOGIC_VECTOR ( 0 to 0 );
BUFG_GT_CEMASK : in STD_LOGIC_VECTOR ( 0 to 0 );
BUFG_GT_CLR : in STD_LOGIC_VECTOR ( 0 to 0 );
BUFG_GT_CLRMASK : in STD_LOGIC_VECTOR ( 0 to 0 );
BUFG_GT_DIV : in STD_LOGIC_VECTOR ( 2 downto 0 );
BUFG_GT_O : out STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute C_BUF_TYPE : string;
attribute C_BUF_TYPE of system_util_ds_buf_0_0_util_ds_buf : entity is "BUFG";
attribute C_SIZE : integer;
attribute C_SIZE of system_util_ds_buf_0_0_util_ds_buf : entity is 1;
end system_util_ds_buf_0_0_util_ds_buf;
architecture STRUCTURE of system_util_ds_buf_0_0_util_ds_buf is
signal \<const0>\ : STD_LOGIC;
attribute box_type : string;
attribute box_type of \USE_BUFG.GEN_BUFG[0].BUFG_U\ : label is "PRIMITIVE";
begin
BUFGCE_O(0) <= \<const0>\;
BUFG_GT_O(0) <= \<const0>\;
BUFHCE_O(0) <= \<const0>\;
BUFH_O(0) <= \<const0>\;
IBUF_DS_ODIV2(0) <= \<const0>\;
IBUF_OUT(0) <= \<const0>\;
IOBUF_IO_O(0) <= \<const0>\;
OBUF_DS_N(0) <= \<const0>\;
OBUF_DS_P(0) <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
\USE_BUFG.GEN_BUFG[0].BUFG_U\: unisim.vcomponents.BUFG
port map (
I => BUFG_I(0),
O => BUFG_O(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_util_ds_buf_0_0 is
port (
BUFG_I : in STD_LOGIC_VECTOR ( 0 to 0 );
BUFG_O : out STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_util_ds_buf_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_util_ds_buf_0_0 : entity is "system_util_ds_buf_0_0,util_ds_buf,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_util_ds_buf_0_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_util_ds_buf_0_0 : entity is "util_ds_buf,Vivado 2016.4";
end system_util_ds_buf_0_0;
architecture STRUCTURE of system_util_ds_buf_0_0 is
signal NLW_U0_BUFGCE_O_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_BUFG_GT_O_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_BUFHCE_O_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_BUFH_O_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_IBUF_DS_ODIV2_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_IBUF_OUT_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_IOBUF_DS_N_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_IOBUF_DS_P_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_IOBUF_IO_O_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_OBUF_DS_N_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_OBUF_DS_P_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
attribute C_BUF_TYPE : string;
attribute C_BUF_TYPE of U0 : label is "BUFG";
attribute C_SIZE : integer;
attribute C_SIZE of U0 : label is 1;
begin
U0: entity work.system_util_ds_buf_0_0_util_ds_buf
port map (
BUFGCE_CE(0) => '0',
BUFGCE_I(0) => '0',
BUFGCE_O(0) => NLW_U0_BUFGCE_O_UNCONNECTED(0),
BUFG_GT_CE(0) => '0',
BUFG_GT_CEMASK(0) => '0',
BUFG_GT_CLR(0) => '0',
BUFG_GT_CLRMASK(0) => '0',
BUFG_GT_DIV(2 downto 0) => B"000",
BUFG_GT_I(0) => '0',
BUFG_GT_O(0) => NLW_U0_BUFG_GT_O_UNCONNECTED(0),
BUFG_I(0) => BUFG_I(0),
BUFG_O(0) => BUFG_O(0),
BUFHCE_CE(0) => '0',
BUFHCE_I(0) => '0',
BUFHCE_O(0) => NLW_U0_BUFHCE_O_UNCONNECTED(0),
BUFH_I(0) => '0',
BUFH_O(0) => NLW_U0_BUFH_O_UNCONNECTED(0),
IBUF_DS_N(0) => '0',
IBUF_DS_ODIV2(0) => NLW_U0_IBUF_DS_ODIV2_UNCONNECTED(0),
IBUF_DS_P(0) => '0',
IBUF_OUT(0) => NLW_U0_IBUF_OUT_UNCONNECTED(0),
IOBUF_DS_N(0) => NLW_U0_IOBUF_DS_N_UNCONNECTED(0),
IOBUF_DS_P(0) => NLW_U0_IOBUF_DS_P_UNCONNECTED(0),
IOBUF_IO_I(0) => '0',
IOBUF_IO_O(0) => NLW_U0_IOBUF_IO_O_UNCONNECTED(0),
IOBUF_IO_T(0) => '0',
OBUF_DS_N(0) => NLW_U0_OBUF_DS_N_UNCONNECTED(0),
OBUF_DS_P(0) => NLW_U0_OBUF_DS_P_UNCONNECTED(0),
OBUF_IN(0) => '0'
);
end STRUCTURE;
| mit |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_dual_fusion/zed_dual_fusion.srcs/sources_1/bd/system/ipshared/88c4/vga_overlay.vhd | 4 | 1070 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
entity vga_overlay is
port (
clk : in std_logic;
rgb_0 : in std_logic_vector(23 downto 0);
rgb_1 : in std_logic_vector(23 downto 0);
rgb : out std_logic_vector(23 downto 0)
);
end vga_overlay;
architecture Behavioral of vga_overlay is
signal r_0, g_0, b_0, r_1, g_1, b_1 : unsigned(7 downto 0);
begin
process(clk)
begin
if rising_edge(clk) then
r_0 <= unsigned(rgb_0(23 downto 16)) srl 1;
g_0 <= unsigned(rgb_0(15 downto 8)) srl 1;
b_0 <= unsigned(rgb_0(7 downto 0)) srl 1;
r_1 <= unsigned(rgb_1(23 downto 16)) srl 1;
g_1 <= unsigned(rgb_1(15 downto 8)) srl 1;
b_1 <= unsigned(rgb_1(7 downto 0)) srl 1;
rgb(23 downto 16) <= std_logic_vector(r_0 + r_1);
rgb(15 downto 8) <= std_logic_vector(g_0 + g_1);
rgb(7 downto 0) <= std_logic_vector(b_0 + b_1);
end if;
end process;
end Behavioral;
| mit |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_camera_hessian/zed_camera_hessian.srcs/sources_1/bd/system/ipshared/349b/vga_pll.vhd | 7 | 1175 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity vga_pll is
port (
clk_100 : in std_logic;
clk_50 : out std_logic;
clk_25 : out std_logic;
clk_12_5 : out std_logic;
clk_6_25 : out std_logic
);
end vga_pll;
architecture Behavioral of vga_pll is
signal clk_50_s : std_logic := '0';
signal clk_25_s : std_logic := '0';
signal clk_12_5_s : std_logic := '0';
signal clk_6_25_s : std_logic := '0';
begin
clk_50 <= clk_50_s;
clk_25 <= clk_25_s;
clk_12_5 <= clk_12_5_s;
clk_6_25 <= clk_6_25_s;
process(clk_100)
begin
if rising_edge(clk_100) then
clk_50_s <= not clk_50_s;
end if;
end process;
process(clk_50_s)
begin
if rising_edge(clk_50_s) then
clk_25_s <= not clk_25_s;
end if;
end process;
process(clk_25_s)
begin
if rising_edge(clk_25_s) then
clk_12_5_s <= not clk_12_5_s;
end if;
end process;
process(clk_6_25_s)
begin
if rising_edge(clk_6_25_s) then
clk_6_25_s <= not clk_6_25_s;
end if;
end process;
end Behavioral;
| mit |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/dma_example/dma_example.srcs/sources_1/bd/system/ip/system_axi_dma_0_0/sim/system_axi_dma_0_0.vhd | 1 | 30349 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_dma:7.1
-- IP Revision: 12
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_dma_v7_1_12;
USE axi_dma_v7_1_12.axi_dma;
ENTITY system_axi_dma_0_0 IS
PORT (
s_axi_lite_aclk : IN STD_LOGIC;
m_axi_sg_aclk : IN STD_LOGIC;
m_axi_mm2s_aclk : IN STD_LOGIC;
m_axi_s2mm_aclk : IN STD_LOGIC;
axi_resetn : IN STD_LOGIC;
s_axi_lite_awvalid : IN STD_LOGIC;
s_axi_lite_awready : OUT STD_LOGIC;
s_axi_lite_awaddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
s_axi_lite_wvalid : IN STD_LOGIC;
s_axi_lite_wready : OUT STD_LOGIC;
s_axi_lite_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_lite_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_lite_bvalid : OUT STD_LOGIC;
s_axi_lite_bready : IN STD_LOGIC;
s_axi_lite_arvalid : IN STD_LOGIC;
s_axi_lite_arready : OUT STD_LOGIC;
s_axi_lite_araddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
s_axi_lite_rvalid : OUT STD_LOGIC;
s_axi_lite_rready : IN STD_LOGIC;
s_axi_lite_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_lite_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_sg_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_sg_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_sg_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_sg_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_sg_awvalid : OUT STD_LOGIC;
m_axi_sg_awready : IN STD_LOGIC;
m_axi_sg_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_sg_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_sg_wlast : OUT STD_LOGIC;
m_axi_sg_wvalid : OUT STD_LOGIC;
m_axi_sg_wready : IN STD_LOGIC;
m_axi_sg_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_bvalid : IN STD_LOGIC;
m_axi_sg_bready : OUT STD_LOGIC;
m_axi_sg_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_sg_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_sg_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_sg_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_sg_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_sg_arvalid : OUT STD_LOGIC;
m_axi_sg_arready : IN STD_LOGIC;
m_axi_sg_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_sg_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_rlast : IN STD_LOGIC;
m_axi_sg_rvalid : IN STD_LOGIC;
m_axi_sg_rready : OUT STD_LOGIC;
m_axi_mm2s_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_mm2s_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_mm2s_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_mm2s_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mm2s_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_mm2s_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_mm2s_arvalid : OUT STD_LOGIC;
m_axi_mm2s_arready : IN STD_LOGIC;
m_axi_mm2s_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_mm2s_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mm2s_rlast : IN STD_LOGIC;
m_axi_mm2s_rvalid : IN STD_LOGIC;
m_axi_mm2s_rready : OUT STD_LOGIC;
mm2s_prmry_reset_out_n : OUT STD_LOGIC;
m_axis_mm2s_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_mm2s_tkeep : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_mm2s_tvalid : OUT STD_LOGIC;
m_axis_mm2s_tready : IN STD_LOGIC;
m_axis_mm2s_tlast : OUT STD_LOGIC;
m_axi_s2mm_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_s2mm_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_s2mm_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_s2mm_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_s2mm_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_s2mm_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_s2mm_awvalid : OUT STD_LOGIC;
m_axi_s2mm_awready : IN STD_LOGIC;
m_axi_s2mm_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_s2mm_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_s2mm_wlast : OUT STD_LOGIC;
m_axi_s2mm_wvalid : OUT STD_LOGIC;
m_axi_s2mm_wready : IN STD_LOGIC;
m_axi_s2mm_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_s2mm_bvalid : IN STD_LOGIC;
m_axi_s2mm_bready : OUT STD_LOGIC;
s2mm_prmry_reset_out_n : OUT STD_LOGIC;
s_axis_s2mm_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_s2mm_tkeep : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_s2mm_tvalid : IN STD_LOGIC;
s_axis_s2mm_tready : OUT STD_LOGIC;
s_axis_s2mm_tlast : IN STD_LOGIC;
mm2s_introut : OUT STD_LOGIC;
s2mm_introut : OUT STD_LOGIC;
axi_dma_tstvec : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END system_axi_dma_0_0;
ARCHITECTURE system_axi_dma_0_0_arch OF system_axi_dma_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_axi_dma_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_dma IS
GENERIC (
C_S_AXI_LITE_ADDR_WIDTH : INTEGER;
C_S_AXI_LITE_DATA_WIDTH : INTEGER;
C_DLYTMR_RESOLUTION : INTEGER;
C_PRMRY_IS_ACLK_ASYNC : INTEGER;
C_ENABLE_MULTI_CHANNEL : INTEGER;
C_NUM_MM2S_CHANNELS : INTEGER;
C_NUM_S2MM_CHANNELS : INTEGER;
C_INCLUDE_SG : INTEGER;
C_SG_INCLUDE_STSCNTRL_STRM : INTEGER;
C_SG_USE_STSAPP_LENGTH : INTEGER;
C_SG_LENGTH_WIDTH : INTEGER;
C_M_AXI_SG_ADDR_WIDTH : INTEGER;
C_M_AXI_SG_DATA_WIDTH : INTEGER;
C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH : INTEGER;
C_S_AXIS_S2MM_STS_TDATA_WIDTH : INTEGER;
C_MICRO_DMA : INTEGER;
C_INCLUDE_MM2S : INTEGER;
C_INCLUDE_MM2S_SF : INTEGER;
C_MM2S_BURST_SIZE : INTEGER;
C_M_AXI_MM2S_ADDR_WIDTH : INTEGER;
C_M_AXI_MM2S_DATA_WIDTH : INTEGER;
C_M_AXIS_MM2S_TDATA_WIDTH : INTEGER;
C_INCLUDE_MM2S_DRE : INTEGER;
C_INCLUDE_S2MM : INTEGER;
C_INCLUDE_S2MM_SF : INTEGER;
C_S2MM_BURST_SIZE : INTEGER;
C_M_AXI_S2MM_ADDR_WIDTH : INTEGER;
C_M_AXI_S2MM_DATA_WIDTH : INTEGER;
C_S_AXIS_S2MM_TDATA_WIDTH : INTEGER;
C_INCLUDE_S2MM_DRE : INTEGER;
C_FAMILY : STRING
);
PORT (
s_axi_lite_aclk : IN STD_LOGIC;
m_axi_sg_aclk : IN STD_LOGIC;
m_axi_mm2s_aclk : IN STD_LOGIC;
m_axi_s2mm_aclk : IN STD_LOGIC;
axi_resetn : IN STD_LOGIC;
s_axi_lite_awvalid : IN STD_LOGIC;
s_axi_lite_awready : OUT STD_LOGIC;
s_axi_lite_awaddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
s_axi_lite_wvalid : IN STD_LOGIC;
s_axi_lite_wready : OUT STD_LOGIC;
s_axi_lite_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_lite_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_lite_bvalid : OUT STD_LOGIC;
s_axi_lite_bready : IN STD_LOGIC;
s_axi_lite_arvalid : IN STD_LOGIC;
s_axi_lite_arready : OUT STD_LOGIC;
s_axi_lite_araddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
s_axi_lite_rvalid : OUT STD_LOGIC;
s_axi_lite_rready : IN STD_LOGIC;
s_axi_lite_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_lite_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_sg_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_sg_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_sg_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_sg_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_sg_awuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_sg_awvalid : OUT STD_LOGIC;
m_axi_sg_awready : IN STD_LOGIC;
m_axi_sg_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_sg_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_sg_wlast : OUT STD_LOGIC;
m_axi_sg_wvalid : OUT STD_LOGIC;
m_axi_sg_wready : IN STD_LOGIC;
m_axi_sg_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_bvalid : IN STD_LOGIC;
m_axi_sg_bready : OUT STD_LOGIC;
m_axi_sg_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_sg_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_sg_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_sg_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_sg_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_sg_aruser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_sg_arvalid : OUT STD_LOGIC;
m_axi_sg_arready : IN STD_LOGIC;
m_axi_sg_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_sg_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_rlast : IN STD_LOGIC;
m_axi_sg_rvalid : IN STD_LOGIC;
m_axi_sg_rready : OUT STD_LOGIC;
m_axi_mm2s_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_mm2s_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_mm2s_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_mm2s_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mm2s_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_mm2s_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_mm2s_aruser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_mm2s_arvalid : OUT STD_LOGIC;
m_axi_mm2s_arready : IN STD_LOGIC;
m_axi_mm2s_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_mm2s_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mm2s_rlast : IN STD_LOGIC;
m_axi_mm2s_rvalid : IN STD_LOGIC;
m_axi_mm2s_rready : OUT STD_LOGIC;
mm2s_prmry_reset_out_n : OUT STD_LOGIC;
m_axis_mm2s_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_mm2s_tkeep : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_mm2s_tvalid : OUT STD_LOGIC;
m_axis_mm2s_tready : IN STD_LOGIC;
m_axis_mm2s_tlast : OUT STD_LOGIC;
m_axis_mm2s_tuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_mm2s_tid : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
m_axis_mm2s_tdest : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
mm2s_cntrl_reset_out_n : OUT STD_LOGIC;
m_axis_mm2s_cntrl_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_mm2s_cntrl_tkeep : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_mm2s_cntrl_tvalid : OUT STD_LOGIC;
m_axis_mm2s_cntrl_tready : IN STD_LOGIC;
m_axis_mm2s_cntrl_tlast : OUT STD_LOGIC;
m_axi_s2mm_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_s2mm_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_s2mm_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_s2mm_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_s2mm_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_s2mm_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_s2mm_awuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_s2mm_awvalid : OUT STD_LOGIC;
m_axi_s2mm_awready : IN STD_LOGIC;
m_axi_s2mm_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_s2mm_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_s2mm_wlast : OUT STD_LOGIC;
m_axi_s2mm_wvalid : OUT STD_LOGIC;
m_axi_s2mm_wready : IN STD_LOGIC;
m_axi_s2mm_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_s2mm_bvalid : IN STD_LOGIC;
m_axi_s2mm_bready : OUT STD_LOGIC;
s2mm_prmry_reset_out_n : OUT STD_LOGIC;
s_axis_s2mm_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_s2mm_tkeep : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_s2mm_tvalid : IN STD_LOGIC;
s_axis_s2mm_tready : OUT STD_LOGIC;
s_axis_s2mm_tlast : IN STD_LOGIC;
s_axis_s2mm_tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_s2mm_tid : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s_axis_s2mm_tdest : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s2mm_sts_reset_out_n : OUT STD_LOGIC;
s_axis_s2mm_sts_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_s2mm_sts_tkeep : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_s2mm_sts_tvalid : IN STD_LOGIC;
s_axis_s2mm_sts_tready : OUT STD_LOGIC;
s_axis_s2mm_sts_tlast : IN STD_LOGIC;
mm2s_introut : OUT STD_LOGIC;
s2mm_introut : OUT STD_LOGIC;
axi_dma_tstvec : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT axi_dma;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_LITE_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 M_AXI_SG_CLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 M_AXI_MM2S_CLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 M_AXI_S2MM_CLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF axi_resetn: SIGNAL IS "xilinx.com:signal:reset:1.0 AXI_RESETN RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RRESP";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_awlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG AWLEN";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_awsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG AWSIZE";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_awburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG AWBURST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_awprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG AWPROT";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_awcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG AWCACHE";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG WDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_wlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG WLAST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG WVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG WREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG BRESP";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG BVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG BREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_arlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG ARLEN";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_arsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG ARSIZE";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_arburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG ARBURST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_arprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG ARPROT";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_arcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG ARCACHE";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG RDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG RRESP";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_rlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG RLAST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG RVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG RREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARLEN";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARSIZE";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARBURST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARPROT";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARCACHE";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RRESP";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RLAST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RREADY";
ATTRIBUTE X_INTERFACE_INFO OF mm2s_prmry_reset_out_n: SIGNAL IS "xilinx.com:signal:reset:1.0 MM2S_PRMRY_RESET_OUT_N RST";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tkeep: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TKEEP";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tlast: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TLAST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWLEN";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWSIZE";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWBURST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWPROT";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWCACHE";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WLAST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM BRESP";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM BVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s2mm_prmry_reset_out_n: SIGNAL IS "xilinx.com:signal:reset:1.0 S2MM_PRMRY_RESET_OUT_N RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tkeep: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TKEEP";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tlast: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TLAST";
ATTRIBUTE X_INTERFACE_INFO OF mm2s_introut: SIGNAL IS "xilinx.com:signal:interrupt:1.0 MM2S_INTROUT INTERRUPT";
ATTRIBUTE X_INTERFACE_INFO OF s2mm_introut: SIGNAL IS "xilinx.com:signal:interrupt:1.0 S2MM_INTROUT INTERRUPT";
BEGIN
U0 : axi_dma
GENERIC MAP (
C_S_AXI_LITE_ADDR_WIDTH => 10,
C_S_AXI_LITE_DATA_WIDTH => 32,
C_DLYTMR_RESOLUTION => 125,
C_PRMRY_IS_ACLK_ASYNC => 0,
C_ENABLE_MULTI_CHANNEL => 0,
C_NUM_MM2S_CHANNELS => 1,
C_NUM_S2MM_CHANNELS => 1,
C_INCLUDE_SG => 1,
C_SG_INCLUDE_STSCNTRL_STRM => 0,
C_SG_USE_STSAPP_LENGTH => 0,
C_SG_LENGTH_WIDTH => 14,
C_M_AXI_SG_ADDR_WIDTH => 32,
C_M_AXI_SG_DATA_WIDTH => 32,
C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH => 32,
C_S_AXIS_S2MM_STS_TDATA_WIDTH => 32,
C_MICRO_DMA => 0,
C_INCLUDE_MM2S => 1,
C_INCLUDE_MM2S_SF => 1,
C_MM2S_BURST_SIZE => 16,
C_M_AXI_MM2S_ADDR_WIDTH => 32,
C_M_AXI_MM2S_DATA_WIDTH => 32,
C_M_AXIS_MM2S_TDATA_WIDTH => 32,
C_INCLUDE_MM2S_DRE => 0,
C_INCLUDE_S2MM => 1,
C_INCLUDE_S2MM_SF => 1,
C_S2MM_BURST_SIZE => 16,
C_M_AXI_S2MM_ADDR_WIDTH => 32,
C_M_AXI_S2MM_DATA_WIDTH => 32,
C_S_AXIS_S2MM_TDATA_WIDTH => 32,
C_INCLUDE_S2MM_DRE => 0,
C_FAMILY => "zynq"
)
PORT MAP (
s_axi_lite_aclk => s_axi_lite_aclk,
m_axi_sg_aclk => m_axi_sg_aclk,
m_axi_mm2s_aclk => m_axi_mm2s_aclk,
m_axi_s2mm_aclk => m_axi_s2mm_aclk,
axi_resetn => axi_resetn,
s_axi_lite_awvalid => s_axi_lite_awvalid,
s_axi_lite_awready => s_axi_lite_awready,
s_axi_lite_awaddr => s_axi_lite_awaddr,
s_axi_lite_wvalid => s_axi_lite_wvalid,
s_axi_lite_wready => s_axi_lite_wready,
s_axi_lite_wdata => s_axi_lite_wdata,
s_axi_lite_bresp => s_axi_lite_bresp,
s_axi_lite_bvalid => s_axi_lite_bvalid,
s_axi_lite_bready => s_axi_lite_bready,
s_axi_lite_arvalid => s_axi_lite_arvalid,
s_axi_lite_arready => s_axi_lite_arready,
s_axi_lite_araddr => s_axi_lite_araddr,
s_axi_lite_rvalid => s_axi_lite_rvalid,
s_axi_lite_rready => s_axi_lite_rready,
s_axi_lite_rdata => s_axi_lite_rdata,
s_axi_lite_rresp => s_axi_lite_rresp,
m_axi_sg_awaddr => m_axi_sg_awaddr,
m_axi_sg_awlen => m_axi_sg_awlen,
m_axi_sg_awsize => m_axi_sg_awsize,
m_axi_sg_awburst => m_axi_sg_awburst,
m_axi_sg_awprot => m_axi_sg_awprot,
m_axi_sg_awcache => m_axi_sg_awcache,
m_axi_sg_awvalid => m_axi_sg_awvalid,
m_axi_sg_awready => m_axi_sg_awready,
m_axi_sg_wdata => m_axi_sg_wdata,
m_axi_sg_wstrb => m_axi_sg_wstrb,
m_axi_sg_wlast => m_axi_sg_wlast,
m_axi_sg_wvalid => m_axi_sg_wvalid,
m_axi_sg_wready => m_axi_sg_wready,
m_axi_sg_bresp => m_axi_sg_bresp,
m_axi_sg_bvalid => m_axi_sg_bvalid,
m_axi_sg_bready => m_axi_sg_bready,
m_axi_sg_araddr => m_axi_sg_araddr,
m_axi_sg_arlen => m_axi_sg_arlen,
m_axi_sg_arsize => m_axi_sg_arsize,
m_axi_sg_arburst => m_axi_sg_arburst,
m_axi_sg_arprot => m_axi_sg_arprot,
m_axi_sg_arcache => m_axi_sg_arcache,
m_axi_sg_arvalid => m_axi_sg_arvalid,
m_axi_sg_arready => m_axi_sg_arready,
m_axi_sg_rdata => m_axi_sg_rdata,
m_axi_sg_rresp => m_axi_sg_rresp,
m_axi_sg_rlast => m_axi_sg_rlast,
m_axi_sg_rvalid => m_axi_sg_rvalid,
m_axi_sg_rready => m_axi_sg_rready,
m_axi_mm2s_araddr => m_axi_mm2s_araddr,
m_axi_mm2s_arlen => m_axi_mm2s_arlen,
m_axi_mm2s_arsize => m_axi_mm2s_arsize,
m_axi_mm2s_arburst => m_axi_mm2s_arburst,
m_axi_mm2s_arprot => m_axi_mm2s_arprot,
m_axi_mm2s_arcache => m_axi_mm2s_arcache,
m_axi_mm2s_arvalid => m_axi_mm2s_arvalid,
m_axi_mm2s_arready => m_axi_mm2s_arready,
m_axi_mm2s_rdata => m_axi_mm2s_rdata,
m_axi_mm2s_rresp => m_axi_mm2s_rresp,
m_axi_mm2s_rlast => m_axi_mm2s_rlast,
m_axi_mm2s_rvalid => m_axi_mm2s_rvalid,
m_axi_mm2s_rready => m_axi_mm2s_rready,
mm2s_prmry_reset_out_n => mm2s_prmry_reset_out_n,
m_axis_mm2s_tdata => m_axis_mm2s_tdata,
m_axis_mm2s_tkeep => m_axis_mm2s_tkeep,
m_axis_mm2s_tvalid => m_axis_mm2s_tvalid,
m_axis_mm2s_tready => m_axis_mm2s_tready,
m_axis_mm2s_tlast => m_axis_mm2s_tlast,
m_axis_mm2s_cntrl_tready => '0',
m_axi_s2mm_awaddr => m_axi_s2mm_awaddr,
m_axi_s2mm_awlen => m_axi_s2mm_awlen,
m_axi_s2mm_awsize => m_axi_s2mm_awsize,
m_axi_s2mm_awburst => m_axi_s2mm_awburst,
m_axi_s2mm_awprot => m_axi_s2mm_awprot,
m_axi_s2mm_awcache => m_axi_s2mm_awcache,
m_axi_s2mm_awvalid => m_axi_s2mm_awvalid,
m_axi_s2mm_awready => m_axi_s2mm_awready,
m_axi_s2mm_wdata => m_axi_s2mm_wdata,
m_axi_s2mm_wstrb => m_axi_s2mm_wstrb,
m_axi_s2mm_wlast => m_axi_s2mm_wlast,
m_axi_s2mm_wvalid => m_axi_s2mm_wvalid,
m_axi_s2mm_wready => m_axi_s2mm_wready,
m_axi_s2mm_bresp => m_axi_s2mm_bresp,
m_axi_s2mm_bvalid => m_axi_s2mm_bvalid,
m_axi_s2mm_bready => m_axi_s2mm_bready,
s2mm_prmry_reset_out_n => s2mm_prmry_reset_out_n,
s_axis_s2mm_tdata => s_axis_s2mm_tdata,
s_axis_s2mm_tkeep => s_axis_s2mm_tkeep,
s_axis_s2mm_tvalid => s_axis_s2mm_tvalid,
s_axis_s2mm_tready => s_axis_s2mm_tready,
s_axis_s2mm_tlast => s_axis_s2mm_tlast,
s_axis_s2mm_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axis_s2mm_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 5)),
s_axis_s2mm_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 5)),
s_axis_s2mm_sts_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_s2mm_sts_tkeep => X"F",
s_axis_s2mm_sts_tvalid => '0',
s_axis_s2mm_sts_tlast => '0',
mm2s_introut => mm2s_introut,
s2mm_introut => s2mm_introut,
axi_dma_tstvec => axi_dma_tstvec
);
END system_axi_dma_0_0_arch;
| mit |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/ov7670_hessian_split/ov7670_hessian_split.srcs/sources_1/bd/system/ip/system_ov7670_controller_1_0_1/system_ov7670_controller_1_0_stub.vhdl | 1 | 1566 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Sun Apr 09 07:03:52 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub
-- C:/ZyboIP/examples/ov7670_hessian_split/ov7670_hessian_split.srcs/sources_1/bd/system/ip/system_ov7670_controller_1_0_1/system_ov7670_controller_1_0_stub.vhdl
-- Design : system_ov7670_controller_1_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity system_ov7670_controller_1_0 is
Port (
clk : in STD_LOGIC;
resend : in STD_LOGIC;
config_finished : out STD_LOGIC;
sioc : out STD_LOGIC;
siod : inout STD_LOGIC;
reset : out STD_LOGIC;
pwdn : out STD_LOGIC;
xclk : out STD_LOGIC
);
end system_ov7670_controller_1_0;
architecture stub of system_ov7670_controller_1_0 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clk,resend,config_finished,sioc,siod,reset,pwdn,xclk";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "ov7670_controller,Vivado 2016.4";
begin
end;
| mit |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_camera_hessian/zed_camera_hessian.srcs/sources_1/bd/system/ip/system_vga_pll_0_0/sim/system_vga_pll_0_0.vhd | 3 | 3725 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:vga_pll:1.0
-- IP Revision: 3
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_vga_pll_0_0 IS
PORT (
clk_100 : IN STD_LOGIC;
clk_50 : OUT STD_LOGIC;
clk_25 : OUT STD_LOGIC;
clk_12_5 : OUT STD_LOGIC;
clk_6_25 : OUT STD_LOGIC
);
END system_vga_pll_0_0;
ARCHITECTURE system_vga_pll_0_0_arch OF system_vga_pll_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_vga_pll_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT vga_pll IS
PORT (
clk_100 : IN STD_LOGIC;
clk_50 : OUT STD_LOGIC;
clk_25 : OUT STD_LOGIC;
clk_12_5 : OUT STD_LOGIC;
clk_6_25 : OUT STD_LOGIC
);
END COMPONENT vga_pll;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clk_100: SIGNAL IS "xilinx.com:signal:clock:1.0 clk_100 CLK";
ATTRIBUTE X_INTERFACE_INFO OF clk_50: SIGNAL IS "xilinx.com:signal:clock:1.0 clk_50 CLK";
ATTRIBUTE X_INTERFACE_INFO OF clk_25: SIGNAL IS "xilinx.com:signal:clock:1.0 clk_25 CLK";
ATTRIBUTE X_INTERFACE_INFO OF clk_12_5: SIGNAL IS "xilinx.com:signal:clock:1.0 clk_12_5 CLK";
ATTRIBUTE X_INTERFACE_INFO OF clk_6_25: SIGNAL IS "xilinx.com:signal:clock:1.0 clk_6_25 CLK";
BEGIN
U0 : vga_pll
PORT MAP (
clk_100 => clk_100,
clk_50 => clk_50,
clk_25 => clk_25,
clk_12_5 => clk_12_5,
clk_6_25 => clk_6_25
);
END system_vga_pll_0_0_arch;
| mit |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_dual_fusion/zed_dual_fusion.srcs/sources_1/bd/system/ip/system_inverter_0_0/system_inverter_0_0_sim_netlist.vhdl | 2 | 1838 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Mon May 29 20:53:01 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- c:/ZyboIP/examples/zed_camera_hessian/zed_camera_hessian.srcs/sources_1/bd/system/ip/system_inverter_0_0/system_inverter_0_0_sim_netlist.vhdl
-- Design : system_inverter_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_inverter_0_0 is
port (
x : in STD_LOGIC;
x_not : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_inverter_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_inverter_0_0 : entity is "system_inverter_0_0,inverter,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_inverter_0_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_inverter_0_0 : entity is "inverter,Vivado 2016.4";
end system_inverter_0_0;
architecture STRUCTURE of system_inverter_0_0 is
begin
x_not_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => x,
O => x_not
);
end STRUCTURE;
| mit |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/dma_example/dma_example.srcs/sources_1/bd/system/ip/system_auto_pc_1/system_auto_pc_1_sim_netlist.vhdl | 1 | 770799 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Wed May 31 20:12:37 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- c:/ZyboIP/examples/dma_example/dma_example.srcs/sources_1/bd/system/ip/system_auto_pc_1/system_auto_pc_1_sim_netlist.vhdl
-- Design : system_auto_pc_1
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_pc_1_axi_protocol_converter_v2_1_11_b_downsizer is
port (
E : out STD_LOGIC_VECTOR ( 0 to 0 );
wr_cmd_b_ready : out STD_LOGIC;
\S_AXI_BRESP_ACC_reg[0]_0\ : out STD_LOGIC;
s_axi_bvalid : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
aclk : in STD_LOGIC;
dout : in STD_LOGIC_VECTOR ( 4 downto 0 );
m_axi_bvalid : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
empty : in STD_LOGIC;
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_pc_1_axi_protocol_converter_v2_1_11_b_downsizer : entity is "axi_protocol_converter_v2_1_11_b_downsizer";
end system_auto_pc_1_axi_protocol_converter_v2_1_11_b_downsizer;
architecture STRUCTURE of system_auto_pc_1_axi_protocol_converter_v2_1_11_b_downsizer is
signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal S_AXI_BRESP_ACC : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^s_axi_bresp_acc_reg[0]_0\ : STD_LOGIC;
signal first_mi_word : STD_LOGIC;
signal last_word : STD_LOGIC;
signal next_repeat_cnt : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \repeat_cnt[1]_i_1_n_0\ : STD_LOGIC;
signal \repeat_cnt[2]_i_2_n_0\ : STD_LOGIC;
signal \repeat_cnt[3]_i_2_n_0\ : STD_LOGIC;
signal \repeat_cnt_reg__0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^s_axi_bresp\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of fifo_gen_inst_i_3 : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \repeat_cnt[0]_i_1\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \repeat_cnt[1]_i_1\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \repeat_cnt[2]_i_2\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \repeat_cnt[3]_i_2\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of s_axi_bvalid_INST_0 : label is "soft_lutpair26";
begin
E(0) <= \^e\(0);
\S_AXI_BRESP_ACC_reg[0]_0\ <= \^s_axi_bresp_acc_reg[0]_0\;
s_axi_bresp(1 downto 0) <= \^s_axi_bresp\(1 downto 0);
\S_AXI_BRESP_ACC_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => \^s_axi_bresp\(0),
Q => S_AXI_BRESP_ACC(0),
R => SR(0)
);
\S_AXI_BRESP_ACC_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => \^s_axi_bresp\(1),
Q => S_AXI_BRESP_ACC(1),
R => SR(0)
);
fifo_gen_inst_i_3: unisim.vcomponents.LUT4
generic map(
INIT => X"0040"
)
port map (
I0 => \^s_axi_bresp_acc_reg[0]_0\,
I1 => m_axi_bvalid,
I2 => s_axi_bready,
I3 => empty,
O => wr_cmd_b_ready
);
first_mi_word_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"00000001FFFFFFFF"
)
port map (
I0 => \repeat_cnt_reg__0\(1),
I1 => first_mi_word,
I2 => \repeat_cnt_reg__0\(3),
I3 => \repeat_cnt_reg__0\(0),
I4 => \repeat_cnt_reg__0\(2),
I5 => dout(4),
O => last_word
);
first_mi_word_reg: unisim.vcomponents.FDSE
port map (
C => aclk,
CE => \^e\(0),
D => last_word,
Q => first_mi_word,
S => SR(0)
);
m_axi_bready_INST_0: unisim.vcomponents.LUT3
generic map(
INIT => X"A8"
)
port map (
I0 => m_axi_bvalid,
I1 => \^s_axi_bresp_acc_reg[0]_0\,
I2 => s_axi_bready,
O => \^e\(0)
);
\repeat_cnt[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \repeat_cnt_reg__0\(0),
I1 => first_mi_word,
I2 => dout(0),
O => next_repeat_cnt(0)
);
\repeat_cnt[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"CCA533A5"
)
port map (
I0 => \repeat_cnt_reg__0\(1),
I1 => dout(1),
I2 => \repeat_cnt_reg__0\(0),
I3 => first_mi_word,
I4 => dout(0),
O => \repeat_cnt[1]_i_1_n_0\
);
\repeat_cnt[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"EEEEFA051111FA05"
)
port map (
I0 => \repeat_cnt[2]_i_2_n_0\,
I1 => dout(1),
I2 => \repeat_cnt_reg__0\(1),
I3 => \repeat_cnt_reg__0\(2),
I4 => first_mi_word,
I5 => dout(2),
O => next_repeat_cnt(2)
);
\repeat_cnt[2]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => dout(0),
I1 => first_mi_word,
I2 => \repeat_cnt_reg__0\(0),
O => \repeat_cnt[2]_i_2_n_0\
);
\repeat_cnt[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFAFCF305050CF30"
)
port map (
I0 => dout(2),
I1 => \repeat_cnt_reg__0\(2),
I2 => \repeat_cnt[3]_i_2_n_0\,
I3 => \repeat_cnt_reg__0\(3),
I4 => first_mi_word,
I5 => dout(3),
O => next_repeat_cnt(3)
);
\repeat_cnt[3]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"00053305"
)
port map (
I0 => \repeat_cnt_reg__0\(1),
I1 => dout(1),
I2 => \repeat_cnt_reg__0\(0),
I3 => first_mi_word,
I4 => dout(0),
O => \repeat_cnt[3]_i_2_n_0\
);
\repeat_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => next_repeat_cnt(0),
Q => \repeat_cnt_reg__0\(0),
R => SR(0)
);
\repeat_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => \repeat_cnt[1]_i_1_n_0\,
Q => \repeat_cnt_reg__0\(1),
R => SR(0)
);
\repeat_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => next_repeat_cnt(2),
Q => \repeat_cnt_reg__0\(2),
R => SR(0)
);
\repeat_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => next_repeat_cnt(3),
Q => \repeat_cnt_reg__0\(3),
R => SR(0)
);
\s_axi_bresp[0]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF00B0FFDF0000"
)
port map (
I0 => S_AXI_BRESP_ACC(1),
I1 => m_axi_bresp(1),
I2 => dout(4),
I3 => first_mi_word,
I4 => m_axi_bresp(0),
I5 => S_AXI_BRESP_ACC(0),
O => \^s_axi_bresp\(0)
);
\s_axi_bresp[1]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"CCEC"
)
port map (
I0 => S_AXI_BRESP_ACC(1),
I1 => m_axi_bresp(1),
I2 => dout(4),
I3 => first_mi_word,
O => \^s_axi_bresp\(1)
);
s_axi_bvalid_INST_0: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => m_axi_bvalid,
I1 => \^s_axi_bresp_acc_reg[0]_0\,
O => s_axi_bvalid
);
s_axi_bvalid_INST_0_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAAAAAAAAA8"
)
port map (
I0 => dout(4),
I1 => \repeat_cnt_reg__0\(2),
I2 => \repeat_cnt_reg__0\(0),
I3 => \repeat_cnt_reg__0\(3),
I4 => first_mi_word,
I5 => \repeat_cnt_reg__0\(1),
O => \^s_axi_bresp_acc_reg[0]_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_pc_1_axi_protocol_converter_v2_1_11_w_axi3_conv is
port (
\length_counter_1_reg[1]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
first_mi_word : out STD_LOGIC;
wr_cmd_ready : out STD_LOGIC;
m_axi_wlast : out STD_LOGIC;
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
aclk : in STD_LOGIC;
\goreg_dm.dout_i_reg[0]\ : in STD_LOGIC;
empty_fwft_i_reg : in STD_LOGIC;
dout : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
empty : in STD_LOGIC;
m_axi_wready : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_pc_1_axi_protocol_converter_v2_1_11_w_axi3_conv : entity is "axi_protocol_converter_v2_1_11_w_axi3_conv";
end system_auto_pc_1_axi_protocol_converter_v2_1_11_w_axi3_conv;
architecture STRUCTURE of system_auto_pc_1_axi_protocol_converter_v2_1_11_w_axi3_conv is
signal \fifo_gen_inst_i_3__0_n_0\ : STD_LOGIC;
signal \^first_mi_word\ : STD_LOGIC;
signal \first_mi_word_i_1__0_n_0\ : STD_LOGIC;
signal \length_counter_1[1]_i_1_n_0\ : STD_LOGIC;
signal \length_counter_1[2]_i_1_n_0\ : STD_LOGIC;
signal \length_counter_1[3]_i_1_n_0\ : STD_LOGIC;
signal \length_counter_1[3]_i_2_n_0\ : STD_LOGIC;
signal \length_counter_1[4]_i_1_n_0\ : STD_LOGIC;
signal \length_counter_1[4]_i_2_n_0\ : STD_LOGIC;
signal \length_counter_1[5]_i_1_n_0\ : STD_LOGIC;
signal \length_counter_1[6]_i_1_n_0\ : STD_LOGIC;
signal \length_counter_1[7]_i_1_n_0\ : STD_LOGIC;
signal \length_counter_1[7]_i_2_n_0\ : STD_LOGIC;
signal length_counter_1_reg : STD_LOGIC_VECTOR ( 7 downto 1 );
signal \^length_counter_1_reg[1]_0\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^m_axi_wlast\ : STD_LOGIC;
signal m_axi_wlast_INST_0_i_1_n_0 : STD_LOGIC;
signal m_axi_wlast_INST_0_i_2_n_0 : STD_LOGIC;
signal m_axi_wlast_INST_0_i_3_n_0 : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \fifo_gen_inst_i_3__0\ : label is "soft_lutpair64";
attribute SOFT_HLUTNM of \length_counter_1[2]_i_1\ : label is "soft_lutpair63";
attribute SOFT_HLUTNM of \length_counter_1[3]_i_1\ : label is "soft_lutpair62";
attribute SOFT_HLUTNM of \length_counter_1[3]_i_2\ : label is "soft_lutpair63";
attribute SOFT_HLUTNM of \length_counter_1[4]_i_2\ : label is "soft_lutpair62";
attribute SOFT_HLUTNM of m_axi_wlast_INST_0_i_1 : label is "soft_lutpair64";
begin
first_mi_word <= \^first_mi_word\;
\length_counter_1_reg[1]_0\(0) <= \^length_counter_1_reg[1]_0\(0);
m_axi_wlast <= \^m_axi_wlast\;
\fifo_gen_inst_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => empty_fwft_i_reg,
I1 => m_axi_wlast_INST_0_i_3_n_0,
I2 => \fifo_gen_inst_i_3__0_n_0\,
I3 => m_axi_wlast_INST_0_i_2_n_0,
I4 => m_axi_wlast_INST_0_i_1_n_0,
O => wr_cmd_ready
);
\fifo_gen_inst_i_3__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"35"
)
port map (
I0 => length_counter_1_reg(2),
I1 => dout(2),
I2 => \^first_mi_word\,
O => \fifo_gen_inst_i_3__0_n_0\
);
\first_mi_word_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FBFF0800"
)
port map (
I0 => \^m_axi_wlast\,
I1 => m_axi_wready,
I2 => empty,
I3 => s_axi_wvalid,
I4 => \^first_mi_word\,
O => \first_mi_word_i_1__0_n_0\
);
first_mi_word_reg: unisim.vcomponents.FDSE
port map (
C => aclk,
CE => '1',
D => \first_mi_word_i_1__0_n_0\,
Q => \^first_mi_word\,
S => SR(0)
);
\length_counter_1[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"E2AA2EAAE2662E66"
)
port map (
I0 => length_counter_1_reg(1),
I1 => empty_fwft_i_reg,
I2 => dout(1),
I3 => \^first_mi_word\,
I4 => dout(0),
I5 => \^length_counter_1_reg[1]_0\(0),
O => \length_counter_1[1]_i_1_n_0\
);
\length_counter_1[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"4E66E4CC"
)
port map (
I0 => empty_fwft_i_reg,
I1 => length_counter_1_reg(2),
I2 => dout(2),
I3 => \^first_mi_word\,
I4 => m_axi_wlast_INST_0_i_2_n_0,
O => \length_counter_1[2]_i_1_n_0\
);
\length_counter_1[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"E22EA6A6"
)
port map (
I0 => length_counter_1_reg(3),
I1 => empty_fwft_i_reg,
I2 => \length_counter_1[3]_i_2_n_0\,
I3 => dout(3),
I4 => \^first_mi_word\,
O => \length_counter_1[3]_i_1_n_0\
);
\length_counter_1[3]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"F7D5"
)
port map (
I0 => m_axi_wlast_INST_0_i_2_n_0,
I1 => \^first_mi_word\,
I2 => dout(2),
I3 => length_counter_1_reg(2),
O => \length_counter_1[3]_i_2_n_0\
);
\length_counter_1[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"59555555AAAAAAAA"
)
port map (
I0 => \length_counter_1[4]_i_2_n_0\,
I1 => s_axi_wvalid,
I2 => empty,
I3 => m_axi_wready,
I4 => \^first_mi_word\,
I5 => length_counter_1_reg(4),
O => \length_counter_1[4]_i_1_n_0\
);
\length_counter_1[4]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"0000202A"
)
port map (
I0 => empty_fwft_i_reg,
I1 => dout(3),
I2 => \^first_mi_word\,
I3 => length_counter_1_reg(3),
I4 => \length_counter_1[3]_i_2_n_0\,
O => \length_counter_1[4]_i_2_n_0\
);
\length_counter_1[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"E6E6A6E6E6E6E6E6"
)
port map (
I0 => \length_counter_1[7]_i_2_n_0\,
I1 => length_counter_1_reg(5),
I2 => \^first_mi_word\,
I3 => m_axi_wready,
I4 => empty,
I5 => s_axi_wvalid,
O => \length_counter_1[5]_i_1_n_0\
);
\length_counter_1[6]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FC70CF70"
)
port map (
I0 => empty_fwft_i_reg,
I1 => \^first_mi_word\,
I2 => length_counter_1_reg(6),
I3 => \length_counter_1[7]_i_2_n_0\,
I4 => length_counter_1_reg(5),
O => \length_counter_1[6]_i_1_n_0\
);
\length_counter_1[7]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"BBB9888AFFFD888A"
)
port map (
I0 => \length_counter_1[7]_i_2_n_0\,
I1 => \^first_mi_word\,
I2 => length_counter_1_reg(6),
I3 => length_counter_1_reg(5),
I4 => length_counter_1_reg(7),
I5 => empty_fwft_i_reg,
O => \length_counter_1[7]_i_1_n_0\
);
\length_counter_1[7]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000500000105010"
)
port map (
I0 => \length_counter_1[3]_i_2_n_0\,
I1 => length_counter_1_reg(3),
I2 => empty_fwft_i_reg,
I3 => \^first_mi_word\,
I4 => dout(3),
I5 => length_counter_1_reg(4),
O => \length_counter_1[7]_i_2_n_0\
);
\length_counter_1_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \goreg_dm.dout_i_reg[0]\,
Q => \^length_counter_1_reg[1]_0\(0),
R => SR(0)
);
\length_counter_1_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \length_counter_1[1]_i_1_n_0\,
Q => length_counter_1_reg(1),
R => SR(0)
);
\length_counter_1_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \length_counter_1[2]_i_1_n_0\,
Q => length_counter_1_reg(2),
R => SR(0)
);
\length_counter_1_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \length_counter_1[3]_i_1_n_0\,
Q => length_counter_1_reg(3),
R => SR(0)
);
\length_counter_1_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \length_counter_1[4]_i_1_n_0\,
Q => length_counter_1_reg(4),
R => SR(0)
);
\length_counter_1_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \length_counter_1[5]_i_1_n_0\,
Q => length_counter_1_reg(5),
R => SR(0)
);
\length_counter_1_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \length_counter_1[6]_i_1_n_0\,
Q => length_counter_1_reg(6),
R => SR(0)
);
\length_counter_1_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \length_counter_1[7]_i_1_n_0\,
Q => length_counter_1_reg(7),
R => SR(0)
);
m_axi_wlast_INST_0: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000800888"
)
port map (
I0 => m_axi_wlast_INST_0_i_1_n_0,
I1 => m_axi_wlast_INST_0_i_2_n_0,
I2 => \^first_mi_word\,
I3 => dout(2),
I4 => length_counter_1_reg(2),
I5 => m_axi_wlast_INST_0_i_3_n_0,
O => \^m_axi_wlast\
);
m_axi_wlast_INST_0_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => dout(3),
I1 => \^first_mi_word\,
I2 => length_counter_1_reg(3),
O => m_axi_wlast_INST_0_i_1_n_0
);
m_axi_wlast_INST_0_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"00053305"
)
port map (
I0 => \^length_counter_1_reg[1]_0\(0),
I1 => dout(0),
I2 => length_counter_1_reg(1),
I3 => \^first_mi_word\,
I4 => dout(1),
O => m_axi_wlast_INST_0_i_2_n_0
);
m_axi_wlast_INST_0_i_3: unisim.vcomponents.LUT5
generic map(
INIT => X"55555554"
)
port map (
I0 => \^first_mi_word\,
I1 => length_counter_1_reg(5),
I2 => length_counter_1_reg(4),
I3 => length_counter_1_reg(7),
I4 => length_counter_1_reg(6),
O => m_axi_wlast_INST_0_i_3_n_0
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_pc_1_dmem is
port (
dout_i : out STD_LOGIC_VECTOR ( 5 downto 0 );
clk : in STD_LOGIC;
EN : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 5 downto 0 );
\gc0.count_d1_reg[4]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
I54 : in STD_LOGIC_VECTOR ( 4 downto 0 );
\gpregsm1.curr_fwft_state_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_pc_1_dmem : entity is "dmem";
end system_auto_pc_1_dmem;
architecture STRUCTURE of system_auto_pc_1_dmem is
signal p_0_out : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_RAM_reg_0_31_0_5_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute METHODOLOGY_DRC_VIOS : string;
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_31_0_5 : label is "";
begin
RAM_reg_0_31_0_5: unisim.vcomponents.RAM32M
port map (
ADDRA(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0),
ADDRB(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0),
ADDRC(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0),
ADDRD(4 downto 0) => I54(4 downto 0),
DIA(1 downto 0) => din(1 downto 0),
DIB(1 downto 0) => din(3 downto 2),
DIC(1 downto 0) => din(5 downto 4),
DID(1 downto 0) => B"00",
DOA(1 downto 0) => p_0_out(1 downto 0),
DOB(1 downto 0) => p_0_out(3 downto 2),
DOC(1 downto 0) => p_0_out(5 downto 4),
DOD(1 downto 0) => NLW_RAM_reg_0_31_0_5_DOD_UNCONNECTED(1 downto 0),
WCLK => clk,
WE => EN
);
\gpr1.dout_i_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => p_0_out(0),
Q => dout_i(0),
R => '0'
);
\gpr1.dout_i_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => p_0_out(1),
Q => dout_i(1),
R => '0'
);
\gpr1.dout_i_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => p_0_out(2),
Q => dout_i(2),
R => '0'
);
\gpr1.dout_i_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => p_0_out(3),
Q => dout_i(3),
R => '0'
);
\gpr1.dout_i_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => p_0_out(4),
Q => dout_i(4),
R => '0'
);
\gpr1.dout_i_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => p_0_out(5),
Q => dout_i(5),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_auto_pc_1_dmem__parameterized0\ is
port (
dout_i : out STD_LOGIC_VECTOR ( 4 downto 0 );
clk : in STD_LOGIC;
EN : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 4 downto 0 );
\gc0.count_d1_reg[4]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
I55 : in STD_LOGIC_VECTOR ( 4 downto 0 );
\gpregsm1.curr_fwft_state_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_auto_pc_1_dmem__parameterized0\ : entity is "dmem";
end \system_auto_pc_1_dmem__parameterized0\;
architecture STRUCTURE of \system_auto_pc_1_dmem__parameterized0\ is
signal p_0_out : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_RAM_reg_0_31_0_4_DOC_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 );
signal NLW_RAM_reg_0_31_0_4_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute METHODOLOGY_DRC_VIOS : string;
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_31_0_4 : label is "";
begin
RAM_reg_0_31_0_4: unisim.vcomponents.RAM32M
port map (
ADDRA(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0),
ADDRB(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0),
ADDRC(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0),
ADDRD(4 downto 0) => I55(4 downto 0),
DIA(1 downto 0) => din(1 downto 0),
DIB(1 downto 0) => din(3 downto 2),
DIC(1) => '0',
DIC(0) => din(4),
DID(1 downto 0) => B"00",
DOA(1 downto 0) => p_0_out(1 downto 0),
DOB(1 downto 0) => p_0_out(3 downto 2),
DOC(1) => NLW_RAM_reg_0_31_0_4_DOC_UNCONNECTED(1),
DOC(0) => p_0_out(4),
DOD(1 downto 0) => NLW_RAM_reg_0_31_0_4_DOD_UNCONNECTED(1 downto 0),
WCLK => clk,
WE => EN
);
\gpr1.dout_i_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => p_0_out(0),
Q => dout_i(0),
R => '0'
);
\gpr1.dout_i_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => p_0_out(1),
Q => dout_i(1),
R => '0'
);
\gpr1.dout_i_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => p_0_out(2),
Q => dout_i(2),
R => '0'
);
\gpr1.dout_i_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => p_0_out(3),
Q => dout_i(3),
R => '0'
);
\gpr1.dout_i_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => p_0_out(4),
Q => dout_i(4),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_auto_pc_1_dmem__parameterized1\ is
port (
p_0_out : out STD_LOGIC;
dout_i : out STD_LOGIC;
\goreg_dm.dout_i_reg[0]\ : out STD_LOGIC;
clk : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 0 to 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 4 downto 0 );
\gc0.count_d1_reg[4]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
\gpregsm1.curr_fwft_state_reg[1]\ : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\gpregsm1.curr_fwft_state_reg[1]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
rd_en : in STD_LOGIC;
dout : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_auto_pc_1_dmem__parameterized1\ : entity is "dmem";
end \system_auto_pc_1_dmem__parameterized1\;
architecture STRUCTURE of \system_auto_pc_1_dmem__parameterized1\ is
signal \^dout_i\ : STD_LOGIC;
signal NLW_RAM_reg_0_31_0_0_SPO_UNCONNECTED : STD_LOGIC;
begin
dout_i <= \^dout_i\;
RAM_reg_0_31_0_0: unisim.vcomponents.RAM32X1D
port map (
A0 => Q(0),
A1 => Q(1),
A2 => Q(2),
A3 => Q(3),
A4 => Q(4),
D => din(0),
DPO => p_0_out,
DPRA0 => \gc0.count_d1_reg[4]\(0),
DPRA1 => \gc0.count_d1_reg[4]\(1),
DPRA2 => \gc0.count_d1_reg[4]\(2),
DPRA3 => \gc0.count_d1_reg[4]\(3),
DPRA4 => \gc0.count_d1_reg[4]\(4),
SPO => NLW_RAM_reg_0_31_0_0_SPO_UNCONNECTED,
WCLK => clk,
WE => E(0)
);
\goreg_dm.dout_i[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFEFFFEF20200020"
)
port map (
I0 => \^dout_i\,
I1 => \out\(0),
I2 => \gpregsm1.curr_fwft_state_reg[1]_0\(1),
I3 => \gpregsm1.curr_fwft_state_reg[1]_0\(0),
I4 => rd_en,
I5 => dout(0),
O => \goreg_dm.dout_i_reg[0]\
);
\gpr1.dout_i_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => \gpregsm1.curr_fwft_state_reg[1]\,
Q => \^dout_i\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_pc_1_rd_bin_cntr is
port (
Q : out STD_LOGIC_VECTOR ( 2 downto 0 );
ram_empty_fb_i_reg : out STD_LOGIC;
ram_empty_fb_i_reg_0 : out STD_LOGIC;
\gpr1.dout_i_reg[1]\ : out STD_LOGIC_VECTOR ( 4 downto 0 );
wr_en : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC;
\out\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[4]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
\gpregsm1.curr_fwft_state_reg[0]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[2]\ : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
clk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_pc_1_rd_bin_cntr : entity is "rd_bin_cntr";
end system_auto_pc_1_rd_bin_cntr;
architecture STRUCTURE of system_auto_pc_1_rd_bin_cntr is
signal \^q\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \^gpr1.dout_i_reg[1]\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal plusOp : STD_LOGIC_VECTOR ( 4 downto 0 );
signal ram_empty_fb_i_i_2_n_0 : STD_LOGIC;
signal ram_empty_fb_i_i_6_n_0 : STD_LOGIC;
signal \^ram_empty_fb_i_reg_0\ : STD_LOGIC;
signal rd_pntr_plus1 : STD_LOGIC_VECTOR ( 4 downto 3 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gc0.count[1]_i_1\ : label is "soft_lutpair34";
attribute SOFT_HLUTNM of \gc0.count[2]_i_1\ : label is "soft_lutpair34";
attribute SOFT_HLUTNM of \gc0.count[3]_i_1\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \gc0.count[4]_i_1\ : label is "soft_lutpair33";
begin
Q(2 downto 0) <= \^q\(2 downto 0);
\gpr1.dout_i_reg[1]\(4 downto 0) <= \^gpr1.dout_i_reg[1]\(4 downto 0);
ram_empty_fb_i_reg_0 <= \^ram_empty_fb_i_reg_0\;
\gc0.count[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^q\(0),
O => plusOp(0)
);
\gc0.count[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
O => plusOp(1)
);
\gc0.count[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \^q\(1),
I1 => \^q\(0),
I2 => \^q\(2),
O => plusOp(2)
);
\gc0.count[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^q\(2),
I1 => \^q\(0),
I2 => \^q\(1),
I3 => rd_pntr_plus1(3),
O => plusOp(3)
);
\gc0.count[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => rd_pntr_plus1(3),
I1 => \^q\(1),
I2 => \^q\(0),
I3 => \^q\(2),
I4 => rd_pntr_plus1(4),
O => plusOp(4)
);
\gc0.count_d1_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => \^q\(0),
Q => \^gpr1.dout_i_reg[1]\(0)
);
\gc0.count_d1_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => \^q\(1),
Q => \^gpr1.dout_i_reg[1]\(1)
);
\gc0.count_d1_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => \^q\(2),
Q => \^gpr1.dout_i_reg[1]\(2)
);
\gc0.count_d1_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => rd_pntr_plus1(3),
Q => \^gpr1.dout_i_reg[1]\(3)
);
\gc0.count_d1_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => rd_pntr_plus1(4),
Q => \^gpr1.dout_i_reg[1]\(4)
);
\gc0.count_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => E(0),
D => plusOp(0),
PRE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
Q => \^q\(0)
);
\gc0.count_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => plusOp(1),
Q => \^q\(1)
);
\gc0.count_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => plusOp(2),
Q => \^q\(2)
);
\gc0.count_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => plusOp(3),
Q => rd_pntr_plus1(3)
);
\gc0.count_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => plusOp(4),
Q => rd_pntr_plus1(4)
);
ram_empty_fb_i_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"FFA2F3A2"
)
port map (
I0 => ram_empty_fb_i_i_2_n_0,
I1 => wr_en,
I2 => ram_full_fb_i_reg,
I3 => \out\,
I4 => \^ram_empty_fb_i_reg_0\,
O => ram_empty_fb_i_reg
);
ram_empty_fb_i_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000000000"
)
port map (
I0 => rd_pntr_plus1(3),
I1 => \gcc0.gc0.count_d1_reg[4]\(3),
I2 => rd_pntr_plus1(4),
I3 => \gcc0.gc0.count_d1_reg[4]\(4),
I4 => \gpregsm1.curr_fwft_state_reg[0]\,
I5 => \gcc0.gc0.count_d1_reg[2]\,
O => ram_empty_fb_i_i_2_n_0
);
ram_empty_fb_i_i_3: unisim.vcomponents.LUT5
generic map(
INIT => X"BEFFFFBE"
)
port map (
I0 => ram_empty_fb_i_i_6_n_0,
I1 => \^gpr1.dout_i_reg[1]\(2),
I2 => \gcc0.gc0.count_d1_reg[4]\(2),
I3 => \^gpr1.dout_i_reg[1]\(1),
I4 => \gcc0.gc0.count_d1_reg[4]\(1),
O => \^ram_empty_fb_i_reg_0\
);
ram_empty_fb_i_i_6: unisim.vcomponents.LUT6
generic map(
INIT => X"6FF6FFFFFFFF6FF6"
)
port map (
I0 => \^gpr1.dout_i_reg[1]\(4),
I1 => \gcc0.gc0.count_d1_reg[4]\(4),
I2 => \^gpr1.dout_i_reg[1]\(3),
I3 => \gcc0.gc0.count_d1_reg[4]\(3),
I4 => \gcc0.gc0.count_d1_reg[4]\(0),
I5 => \^gpr1.dout_i_reg[1]\(0),
O => ram_empty_fb_i_i_6_n_0
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_pc_1_rd_bin_cntr_18 is
port (
Q : out STD_LOGIC_VECTOR ( 2 downto 0 );
ram_empty_fb_i_reg : out STD_LOGIC;
ram_empty_fb_i_reg_0 : out STD_LOGIC;
\gpr1.dout_i_reg[1]\ : out STD_LOGIC_VECTOR ( 4 downto 0 );
wr_en : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC;
\out\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[4]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
\gpregsm1.curr_fwft_state_reg[0]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[2]\ : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
clk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_pc_1_rd_bin_cntr_18 : entity is "rd_bin_cntr";
end system_auto_pc_1_rd_bin_cntr_18;
architecture STRUCTURE of system_auto_pc_1_rd_bin_cntr_18 is
signal \^q\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \^gpr1.dout_i_reg[1]\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal plusOp : STD_LOGIC_VECTOR ( 4 downto 0 );
signal ram_empty_fb_i_i_2_n_0 : STD_LOGIC;
signal ram_empty_fb_i_i_6_n_0 : STD_LOGIC;
signal \^ram_empty_fb_i_reg_0\ : STD_LOGIC;
signal rd_pntr_plus1 : STD_LOGIC_VECTOR ( 4 downto 3 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gc0.count[1]_i_1\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \gc0.count[2]_i_1\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \gc0.count[3]_i_1\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \gc0.count[4]_i_1\ : label is "soft_lutpair28";
begin
Q(2 downto 0) <= \^q\(2 downto 0);
\gpr1.dout_i_reg[1]\(4 downto 0) <= \^gpr1.dout_i_reg[1]\(4 downto 0);
ram_empty_fb_i_reg_0 <= \^ram_empty_fb_i_reg_0\;
\gc0.count[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^q\(0),
O => plusOp(0)
);
\gc0.count[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
O => plusOp(1)
);
\gc0.count[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \^q\(1),
I1 => \^q\(0),
I2 => \^q\(2),
O => plusOp(2)
);
\gc0.count[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^q\(2),
I1 => \^q\(0),
I2 => \^q\(1),
I3 => rd_pntr_plus1(3),
O => plusOp(3)
);
\gc0.count[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => rd_pntr_plus1(3),
I1 => \^q\(1),
I2 => \^q\(0),
I3 => \^q\(2),
I4 => rd_pntr_plus1(4),
O => plusOp(4)
);
\gc0.count_d1_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => \^q\(0),
Q => \^gpr1.dout_i_reg[1]\(0)
);
\gc0.count_d1_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => \^q\(1),
Q => \^gpr1.dout_i_reg[1]\(1)
);
\gc0.count_d1_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => \^q\(2),
Q => \^gpr1.dout_i_reg[1]\(2)
);
\gc0.count_d1_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => rd_pntr_plus1(3),
Q => \^gpr1.dout_i_reg[1]\(3)
);
\gc0.count_d1_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => rd_pntr_plus1(4),
Q => \^gpr1.dout_i_reg[1]\(4)
);
\gc0.count_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => E(0),
D => plusOp(0),
PRE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
Q => \^q\(0)
);
\gc0.count_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => plusOp(1),
Q => \^q\(1)
);
\gc0.count_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => plusOp(2),
Q => \^q\(2)
);
\gc0.count_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => plusOp(3),
Q => rd_pntr_plus1(3)
);
\gc0.count_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => plusOp(4),
Q => rd_pntr_plus1(4)
);
ram_empty_fb_i_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"FFA2F3A2"
)
port map (
I0 => ram_empty_fb_i_i_2_n_0,
I1 => wr_en,
I2 => ram_full_fb_i_reg,
I3 => \out\,
I4 => \^ram_empty_fb_i_reg_0\,
O => ram_empty_fb_i_reg
);
ram_empty_fb_i_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000000000"
)
port map (
I0 => rd_pntr_plus1(3),
I1 => \gcc0.gc0.count_d1_reg[4]\(3),
I2 => rd_pntr_plus1(4),
I3 => \gcc0.gc0.count_d1_reg[4]\(4),
I4 => \gpregsm1.curr_fwft_state_reg[0]\,
I5 => \gcc0.gc0.count_d1_reg[2]\,
O => ram_empty_fb_i_i_2_n_0
);
ram_empty_fb_i_i_3: unisim.vcomponents.LUT5
generic map(
INIT => X"BEFFFFBE"
)
port map (
I0 => ram_empty_fb_i_i_6_n_0,
I1 => \^gpr1.dout_i_reg[1]\(2),
I2 => \gcc0.gc0.count_d1_reg[4]\(2),
I3 => \^gpr1.dout_i_reg[1]\(1),
I4 => \gcc0.gc0.count_d1_reg[4]\(1),
O => \^ram_empty_fb_i_reg_0\
);
ram_empty_fb_i_i_6: unisim.vcomponents.LUT6
generic map(
INIT => X"6FF6FFFFFFFF6FF6"
)
port map (
I0 => \^gpr1.dout_i_reg[1]\(4),
I1 => \gcc0.gc0.count_d1_reg[4]\(4),
I2 => \^gpr1.dout_i_reg[1]\(3),
I3 => \gcc0.gc0.count_d1_reg[4]\(3),
I4 => \gcc0.gc0.count_d1_reg[4]\(0),
I5 => \^gpr1.dout_i_reg[1]\(0),
O => ram_empty_fb_i_i_6_n_0
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_pc_1_rd_bin_cntr_32 is
port (
Q : out STD_LOGIC_VECTOR ( 2 downto 0 );
ram_empty_fb_i_reg : out STD_LOGIC;
ram_empty_fb_i_reg_0 : out STD_LOGIC;
\gpr1.dout_i_reg[0]\ : out STD_LOGIC_VECTOR ( 4 downto 0 );
wr_en : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC;
\out\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[4]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
\gpregsm1.curr_fwft_state_reg[0]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[2]\ : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
clk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_pc_1_rd_bin_cntr_32 : entity is "rd_bin_cntr";
end system_auto_pc_1_rd_bin_cntr_32;
architecture STRUCTURE of system_auto_pc_1_rd_bin_cntr_32 is
signal \^q\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \^gpr1.dout_i_reg[0]\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal plusOp : STD_LOGIC_VECTOR ( 4 downto 0 );
signal ram_empty_fb_i_i_2_n_0 : STD_LOGIC;
signal ram_empty_fb_i_i_6_n_0 : STD_LOGIC;
signal \^ram_empty_fb_i_reg_0\ : STD_LOGIC;
signal rd_pntr_plus1 : STD_LOGIC_VECTOR ( 4 downto 3 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gc0.count[1]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \gc0.count[2]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \gc0.count[3]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \gc0.count[4]_i_1\ : label is "soft_lutpair0";
begin
Q(2 downto 0) <= \^q\(2 downto 0);
\gpr1.dout_i_reg[0]\(4 downto 0) <= \^gpr1.dout_i_reg[0]\(4 downto 0);
ram_empty_fb_i_reg_0 <= \^ram_empty_fb_i_reg_0\;
\gc0.count[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^q\(0),
O => plusOp(0)
);
\gc0.count[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
O => plusOp(1)
);
\gc0.count[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \^q\(1),
I1 => \^q\(0),
I2 => \^q\(2),
O => plusOp(2)
);
\gc0.count[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^q\(2),
I1 => \^q\(0),
I2 => \^q\(1),
I3 => rd_pntr_plus1(3),
O => plusOp(3)
);
\gc0.count[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => rd_pntr_plus1(3),
I1 => \^q\(1),
I2 => \^q\(0),
I3 => \^q\(2),
I4 => rd_pntr_plus1(4),
O => plusOp(4)
);
\gc0.count_d1_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => \^q\(0),
Q => \^gpr1.dout_i_reg[0]\(0)
);
\gc0.count_d1_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => \^q\(1),
Q => \^gpr1.dout_i_reg[0]\(1)
);
\gc0.count_d1_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => \^q\(2),
Q => \^gpr1.dout_i_reg[0]\(2)
);
\gc0.count_d1_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => rd_pntr_plus1(3),
Q => \^gpr1.dout_i_reg[0]\(3)
);
\gc0.count_d1_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => rd_pntr_plus1(4),
Q => \^gpr1.dout_i_reg[0]\(4)
);
\gc0.count_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => E(0),
D => plusOp(0),
PRE => AR(0),
Q => \^q\(0)
);
\gc0.count_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => plusOp(1),
Q => \^q\(1)
);
\gc0.count_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => plusOp(2),
Q => \^q\(2)
);
\gc0.count_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => plusOp(3),
Q => rd_pntr_plus1(3)
);
\gc0.count_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => plusOp(4),
Q => rd_pntr_plus1(4)
);
ram_empty_fb_i_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"FFA2F3A2"
)
port map (
I0 => ram_empty_fb_i_i_2_n_0,
I1 => wr_en,
I2 => ram_full_fb_i_reg,
I3 => \out\,
I4 => \^ram_empty_fb_i_reg_0\,
O => ram_empty_fb_i_reg
);
ram_empty_fb_i_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000000000"
)
port map (
I0 => rd_pntr_plus1(3),
I1 => \gcc0.gc0.count_d1_reg[4]\(3),
I2 => rd_pntr_plus1(4),
I3 => \gcc0.gc0.count_d1_reg[4]\(4),
I4 => \gpregsm1.curr_fwft_state_reg[0]\,
I5 => \gcc0.gc0.count_d1_reg[2]\,
O => ram_empty_fb_i_i_2_n_0
);
ram_empty_fb_i_i_3: unisim.vcomponents.LUT5
generic map(
INIT => X"BEFFFFBE"
)
port map (
I0 => ram_empty_fb_i_i_6_n_0,
I1 => \^gpr1.dout_i_reg[0]\(2),
I2 => \gcc0.gc0.count_d1_reg[4]\(2),
I3 => \^gpr1.dout_i_reg[0]\(1),
I4 => \gcc0.gc0.count_d1_reg[4]\(1),
O => \^ram_empty_fb_i_reg_0\
);
ram_empty_fb_i_i_6: unisim.vcomponents.LUT6
generic map(
INIT => X"6FF6FFFFFFFF6FF6"
)
port map (
I0 => \^gpr1.dout_i_reg[0]\(4),
I1 => \gcc0.gc0.count_d1_reg[4]\(4),
I2 => \^gpr1.dout_i_reg[0]\(3),
I3 => \gcc0.gc0.count_d1_reg[4]\(3),
I4 => \gcc0.gc0.count_d1_reg[4]\(0),
I5 => \^gpr1.dout_i_reg[0]\(0),
O => ram_empty_fb_i_i_6_n_0
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_pc_1_rd_fwft is
port (
empty : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
ram_empty_fb_i_reg : out STD_LOGIC;
\goreg_dm.dout_i_reg[4]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
ram_full_fb_i_reg : out STD_LOGIC;
clk : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
rd_en : in STD_LOGIC;
ram_empty_fb_i_reg_0 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_pc_1_rd_fwft : entity is "rd_fwft";
end system_auto_pc_1_rd_fwft;
architecture STRUCTURE of system_auto_pc_1_rd_fwft is
signal aempty_fwft_fb_i : STD_LOGIC;
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of aempty_fwft_fb_i : signal is std.standard.true;
signal aempty_fwft_i : STD_LOGIC;
attribute DONT_TOUCH of aempty_fwft_i : signal is std.standard.true;
signal aempty_fwft_i0 : STD_LOGIC;
signal curr_fwft_state : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute DONT_TOUCH of curr_fwft_state : signal is std.standard.true;
signal empty_fwft_fb_i : STD_LOGIC;
attribute DONT_TOUCH of empty_fwft_fb_i : signal is std.standard.true;
signal empty_fwft_fb_o_i : STD_LOGIC;
attribute DONT_TOUCH of empty_fwft_fb_o_i : signal is std.standard.true;
signal empty_fwft_fb_o_i0 : STD_LOGIC;
signal empty_fwft_i : STD_LOGIC;
attribute DONT_TOUCH of empty_fwft_i : signal is std.standard.true;
signal empty_fwft_i0 : STD_LOGIC;
signal next_fwft_state : STD_LOGIC_VECTOR ( 1 downto 0 );
signal user_valid : STD_LOGIC;
attribute DONT_TOUCH of user_valid : signal is std.standard.true;
attribute DONT_TOUCH of aempty_fwft_fb_i_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of aempty_fwft_fb_i_reg : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of aempty_fwft_fb_i_reg : label is "no";
attribute DONT_TOUCH of aempty_fwft_i_reg : label is std.standard.true;
attribute KEEP of aempty_fwft_i_reg : label is "yes";
attribute equivalent_register_removal of aempty_fwft_i_reg : label is "no";
attribute DONT_TOUCH of empty_fwft_fb_i_reg : label is std.standard.true;
attribute KEEP of empty_fwft_fb_i_reg : label is "yes";
attribute equivalent_register_removal of empty_fwft_fb_i_reg : label is "no";
attribute DONT_TOUCH of empty_fwft_fb_o_i_reg : label is std.standard.true;
attribute KEEP of empty_fwft_fb_o_i_reg : label is "yes";
attribute equivalent_register_removal of empty_fwft_fb_o_i_reg : label is "no";
attribute DONT_TOUCH of empty_fwft_i_reg : label is std.standard.true;
attribute KEEP of empty_fwft_i_reg : label is "yes";
attribute equivalent_register_removal of empty_fwft_i_reg : label is "no";
attribute DONT_TOUCH of \gpregsm1.curr_fwft_state_reg[0]\ : label is std.standard.true;
attribute KEEP of \gpregsm1.curr_fwft_state_reg[0]\ : label is "yes";
attribute equivalent_register_removal of \gpregsm1.curr_fwft_state_reg[0]\ : label is "no";
attribute DONT_TOUCH of \gpregsm1.curr_fwft_state_reg[1]\ : label is std.standard.true;
attribute KEEP of \gpregsm1.curr_fwft_state_reg[1]\ : label is "yes";
attribute equivalent_register_removal of \gpregsm1.curr_fwft_state_reg[1]\ : label is "no";
attribute DONT_TOUCH of \gpregsm1.user_valid_reg\ : label is std.standard.true;
attribute KEEP of \gpregsm1.user_valid_reg\ : label is "yes";
attribute equivalent_register_removal of \gpregsm1.user_valid_reg\ : label is "no";
begin
empty <= empty_fwft_i;
aempty_fwft_fb_i_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"FAEF8000"
)
port map (
I0 => ram_empty_fb_i_reg_0,
I1 => rd_en,
I2 => curr_fwft_state(0),
I3 => curr_fwft_state(1),
I4 => aempty_fwft_fb_i,
O => aempty_fwft_i0
);
aempty_fwft_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => aempty_fwft_i0,
PRE => \out\(1),
Q => aempty_fwft_fb_i
);
aempty_fwft_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => aempty_fwft_i0,
PRE => \out\(1),
Q => aempty_fwft_i
);
empty_fwft_fb_i_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"B2A2"
)
port map (
I0 => empty_fwft_fb_i,
I1 => curr_fwft_state(1),
I2 => curr_fwft_state(0),
I3 => rd_en,
O => empty_fwft_i0
);
empty_fwft_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => empty_fwft_i0,
PRE => \out\(1),
Q => empty_fwft_fb_i
);
empty_fwft_fb_o_i_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"B2A2"
)
port map (
I0 => empty_fwft_fb_o_i,
I1 => curr_fwft_state(1),
I2 => curr_fwft_state(0),
I3 => rd_en,
O => empty_fwft_fb_o_i0
);
empty_fwft_fb_o_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => empty_fwft_fb_o_i0,
PRE => \out\(1),
Q => empty_fwft_fb_o_i
);
empty_fwft_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => empty_fwft_i0,
PRE => \out\(1),
Q => empty_fwft_i
);
\gc0.count_d1[4]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"00DF"
)
port map (
I0 => curr_fwft_state(1),
I1 => rd_en,
I2 => curr_fwft_state(0),
I3 => ram_empty_fb_i_reg_0,
O => E(0)
);
\goreg_dm.dout_i[4]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"4404"
)
port map (
I0 => \out\(0),
I1 => curr_fwft_state(1),
I2 => curr_fwft_state(0),
I3 => rd_en,
O => \goreg_dm.dout_i_reg[4]\(0)
);
\gpregsm1.curr_fwft_state[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AE"
)
port map (
I0 => curr_fwft_state(1),
I1 => curr_fwft_state(0),
I2 => rd_en,
O => next_fwft_state(0)
);
\gpregsm1.curr_fwft_state[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"20FF"
)
port map (
I0 => curr_fwft_state(1),
I1 => rd_en,
I2 => curr_fwft_state(0),
I3 => ram_empty_fb_i_reg_0,
O => next_fwft_state(1)
);
\gpregsm1.curr_fwft_state_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
CLR => \out\(1),
D => next_fwft_state(0),
Q => curr_fwft_state(0)
);
\gpregsm1.curr_fwft_state_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
CLR => \out\(1),
D => next_fwft_state(1),
Q => curr_fwft_state(1)
);
\gpregsm1.user_valid_reg\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
CLR => \out\(1),
D => next_fwft_state(0),
Q => user_valid
);
ram_empty_fb_i_i_4: unisim.vcomponents.LUT3
generic map(
INIT => X"DF"
)
port map (
I0 => curr_fwft_state(0),
I1 => rd_en,
I2 => curr_fwft_state(1),
O => ram_empty_fb_i_reg
);
ram_full_fb_i_i_3: unisim.vcomponents.LUT4
generic map(
INIT => X"FF08"
)
port map (
I0 => curr_fwft_state(0),
I1 => curr_fwft_state(1),
I2 => rd_en,
I3 => ram_empty_fb_i_reg_0,
O => ram_full_fb_i_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_pc_1_rd_fwft_16 is
port (
empty : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
ram_empty_fb_i_reg : out STD_LOGIC;
\goreg_dm.dout_i_reg[5]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
ram_full_fb_i_reg : out STD_LOGIC;
clk : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
rd_en : in STD_LOGIC;
ram_empty_fb_i_reg_0 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_pc_1_rd_fwft_16 : entity is "rd_fwft";
end system_auto_pc_1_rd_fwft_16;
architecture STRUCTURE of system_auto_pc_1_rd_fwft_16 is
signal aempty_fwft_fb_i : STD_LOGIC;
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of aempty_fwft_fb_i : signal is std.standard.true;
signal aempty_fwft_i : STD_LOGIC;
attribute DONT_TOUCH of aempty_fwft_i : signal is std.standard.true;
signal aempty_fwft_i0 : STD_LOGIC;
signal curr_fwft_state : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute DONT_TOUCH of curr_fwft_state : signal is std.standard.true;
signal empty_fwft_fb_i : STD_LOGIC;
attribute DONT_TOUCH of empty_fwft_fb_i : signal is std.standard.true;
signal empty_fwft_fb_o_i : STD_LOGIC;
attribute DONT_TOUCH of empty_fwft_fb_o_i : signal is std.standard.true;
signal empty_fwft_fb_o_i0 : STD_LOGIC;
signal empty_fwft_i : STD_LOGIC;
attribute DONT_TOUCH of empty_fwft_i : signal is std.standard.true;
signal empty_fwft_i0 : STD_LOGIC;
signal next_fwft_state : STD_LOGIC_VECTOR ( 1 downto 0 );
signal user_valid : STD_LOGIC;
attribute DONT_TOUCH of user_valid : signal is std.standard.true;
attribute DONT_TOUCH of aempty_fwft_fb_i_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of aempty_fwft_fb_i_reg : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of aempty_fwft_fb_i_reg : label is "no";
attribute DONT_TOUCH of aempty_fwft_i_reg : label is std.standard.true;
attribute KEEP of aempty_fwft_i_reg : label is "yes";
attribute equivalent_register_removal of aempty_fwft_i_reg : label is "no";
attribute DONT_TOUCH of empty_fwft_fb_i_reg : label is std.standard.true;
attribute KEEP of empty_fwft_fb_i_reg : label is "yes";
attribute equivalent_register_removal of empty_fwft_fb_i_reg : label is "no";
attribute DONT_TOUCH of empty_fwft_fb_o_i_reg : label is std.standard.true;
attribute KEEP of empty_fwft_fb_o_i_reg : label is "yes";
attribute equivalent_register_removal of empty_fwft_fb_o_i_reg : label is "no";
attribute DONT_TOUCH of empty_fwft_i_reg : label is std.standard.true;
attribute KEEP of empty_fwft_i_reg : label is "yes";
attribute equivalent_register_removal of empty_fwft_i_reg : label is "no";
attribute DONT_TOUCH of \gpregsm1.curr_fwft_state_reg[0]\ : label is std.standard.true;
attribute KEEP of \gpregsm1.curr_fwft_state_reg[0]\ : label is "yes";
attribute equivalent_register_removal of \gpregsm1.curr_fwft_state_reg[0]\ : label is "no";
attribute DONT_TOUCH of \gpregsm1.curr_fwft_state_reg[1]\ : label is std.standard.true;
attribute KEEP of \gpregsm1.curr_fwft_state_reg[1]\ : label is "yes";
attribute equivalent_register_removal of \gpregsm1.curr_fwft_state_reg[1]\ : label is "no";
attribute DONT_TOUCH of \gpregsm1.user_valid_reg\ : label is std.standard.true;
attribute KEEP of \gpregsm1.user_valid_reg\ : label is "yes";
attribute equivalent_register_removal of \gpregsm1.user_valid_reg\ : label is "no";
begin
empty <= empty_fwft_i;
aempty_fwft_fb_i_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"FAEF8000"
)
port map (
I0 => ram_empty_fb_i_reg_0,
I1 => rd_en,
I2 => curr_fwft_state(0),
I3 => curr_fwft_state(1),
I4 => aempty_fwft_fb_i,
O => aempty_fwft_i0
);
aempty_fwft_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => aempty_fwft_i0,
PRE => \out\(1),
Q => aempty_fwft_fb_i
);
aempty_fwft_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => aempty_fwft_i0,
PRE => \out\(1),
Q => aempty_fwft_i
);
empty_fwft_fb_i_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"B2A2"
)
port map (
I0 => empty_fwft_fb_i,
I1 => curr_fwft_state(1),
I2 => curr_fwft_state(0),
I3 => rd_en,
O => empty_fwft_i0
);
empty_fwft_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => empty_fwft_i0,
PRE => \out\(1),
Q => empty_fwft_fb_i
);
empty_fwft_fb_o_i_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"B2A2"
)
port map (
I0 => empty_fwft_fb_o_i,
I1 => curr_fwft_state(1),
I2 => curr_fwft_state(0),
I3 => rd_en,
O => empty_fwft_fb_o_i0
);
empty_fwft_fb_o_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => empty_fwft_fb_o_i0,
PRE => \out\(1),
Q => empty_fwft_fb_o_i
);
empty_fwft_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => empty_fwft_i0,
PRE => \out\(1),
Q => empty_fwft_i
);
\gc0.count_d1[4]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"00DF"
)
port map (
I0 => curr_fwft_state(1),
I1 => rd_en,
I2 => curr_fwft_state(0),
I3 => ram_empty_fb_i_reg_0,
O => E(0)
);
\goreg_dm.dout_i[5]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"4404"
)
port map (
I0 => \out\(0),
I1 => curr_fwft_state(1),
I2 => curr_fwft_state(0),
I3 => rd_en,
O => \goreg_dm.dout_i_reg[5]\(0)
);
\gpregsm1.curr_fwft_state[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AE"
)
port map (
I0 => curr_fwft_state(1),
I1 => curr_fwft_state(0),
I2 => rd_en,
O => next_fwft_state(0)
);
\gpregsm1.curr_fwft_state[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"20FF"
)
port map (
I0 => curr_fwft_state(1),
I1 => rd_en,
I2 => curr_fwft_state(0),
I3 => ram_empty_fb_i_reg_0,
O => next_fwft_state(1)
);
\gpregsm1.curr_fwft_state_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
CLR => \out\(1),
D => next_fwft_state(0),
Q => curr_fwft_state(0)
);
\gpregsm1.curr_fwft_state_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
CLR => \out\(1),
D => next_fwft_state(1),
Q => curr_fwft_state(1)
);
\gpregsm1.user_valid_reg\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
CLR => \out\(1),
D => next_fwft_state(0),
Q => user_valid
);
ram_empty_fb_i_i_4: unisim.vcomponents.LUT3
generic map(
INIT => X"DF"
)
port map (
I0 => curr_fwft_state(0),
I1 => rd_en,
I2 => curr_fwft_state(1),
O => ram_empty_fb_i_reg
);
ram_full_fb_i_i_3: unisim.vcomponents.LUT4
generic map(
INIT => X"FF08"
)
port map (
I0 => curr_fwft_state(0),
I1 => curr_fwft_state(1),
I2 => rd_en,
I3 => ram_empty_fb_i_reg_0,
O => ram_full_fb_i_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_pc_1_rd_fwft_30 is
port (
\out\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
empty : out STD_LOGIC;
\gpr1.dout_i_reg[0]\ : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
ram_empty_fb_i_reg : out STD_LOGIC;
ram_full_fb_i_reg : out STD_LOGIC;
clk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 );
p_0_out : in STD_LOGIC;
rd_en : in STD_LOGIC;
ram_empty_fb_i_reg_0 : in STD_LOGIC;
dout_i : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_pc_1_rd_fwft_30 : entity is "rd_fwft";
end system_auto_pc_1_rd_fwft_30;
architecture STRUCTURE of system_auto_pc_1_rd_fwft_30 is
signal aempty_fwft_fb_i : STD_LOGIC;
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of aempty_fwft_fb_i : signal is std.standard.true;
signal aempty_fwft_i : STD_LOGIC;
attribute DONT_TOUCH of aempty_fwft_i : signal is std.standard.true;
signal aempty_fwft_i0 : STD_LOGIC;
signal curr_fwft_state : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute DONT_TOUCH of curr_fwft_state : signal is std.standard.true;
signal empty_fwft_fb_i : STD_LOGIC;
attribute DONT_TOUCH of empty_fwft_fb_i : signal is std.standard.true;
signal empty_fwft_fb_o_i : STD_LOGIC;
attribute DONT_TOUCH of empty_fwft_fb_o_i : signal is std.standard.true;
signal empty_fwft_fb_o_i0 : STD_LOGIC;
signal empty_fwft_i : STD_LOGIC;
attribute DONT_TOUCH of empty_fwft_i : signal is std.standard.true;
signal empty_fwft_i0 : STD_LOGIC;
signal next_fwft_state : STD_LOGIC_VECTOR ( 1 downto 0 );
signal user_valid : STD_LOGIC;
attribute DONT_TOUCH of user_valid : signal is std.standard.true;
attribute DONT_TOUCH of aempty_fwft_fb_i_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of aempty_fwft_fb_i_reg : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of aempty_fwft_fb_i_reg : label is "no";
attribute DONT_TOUCH of aempty_fwft_i_reg : label is std.standard.true;
attribute KEEP of aempty_fwft_i_reg : label is "yes";
attribute equivalent_register_removal of aempty_fwft_i_reg : label is "no";
attribute DONT_TOUCH of empty_fwft_fb_i_reg : label is std.standard.true;
attribute KEEP of empty_fwft_fb_i_reg : label is "yes";
attribute equivalent_register_removal of empty_fwft_fb_i_reg : label is "no";
attribute DONT_TOUCH of empty_fwft_fb_o_i_reg : label is std.standard.true;
attribute KEEP of empty_fwft_fb_o_i_reg : label is "yes";
attribute equivalent_register_removal of empty_fwft_fb_o_i_reg : label is "no";
attribute DONT_TOUCH of empty_fwft_i_reg : label is std.standard.true;
attribute KEEP of empty_fwft_i_reg : label is "yes";
attribute equivalent_register_removal of empty_fwft_i_reg : label is "no";
attribute DONT_TOUCH of \gpregsm1.curr_fwft_state_reg[0]\ : label is std.standard.true;
attribute KEEP of \gpregsm1.curr_fwft_state_reg[0]\ : label is "yes";
attribute equivalent_register_removal of \gpregsm1.curr_fwft_state_reg[0]\ : label is "no";
attribute DONT_TOUCH of \gpregsm1.curr_fwft_state_reg[1]\ : label is std.standard.true;
attribute KEEP of \gpregsm1.curr_fwft_state_reg[1]\ : label is "yes";
attribute equivalent_register_removal of \gpregsm1.curr_fwft_state_reg[1]\ : label is "no";
attribute DONT_TOUCH of \gpregsm1.user_valid_reg\ : label is std.standard.true;
attribute KEEP of \gpregsm1.user_valid_reg\ : label is "yes";
attribute equivalent_register_removal of \gpregsm1.user_valid_reg\ : label is "no";
begin
empty <= empty_fwft_i;
\out\(1 downto 0) <= curr_fwft_state(1 downto 0);
aempty_fwft_fb_i_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"FAEF8000"
)
port map (
I0 => ram_empty_fb_i_reg_0,
I1 => rd_en,
I2 => curr_fwft_state(0),
I3 => curr_fwft_state(1),
I4 => aempty_fwft_fb_i,
O => aempty_fwft_i0
);
aempty_fwft_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => aempty_fwft_i0,
PRE => AR(0),
Q => aempty_fwft_fb_i
);
aempty_fwft_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => aempty_fwft_i0,
PRE => AR(0),
Q => aempty_fwft_i
);
empty_fwft_fb_i_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"B2A2"
)
port map (
I0 => empty_fwft_fb_i,
I1 => curr_fwft_state(1),
I2 => curr_fwft_state(0),
I3 => rd_en,
O => empty_fwft_i0
);
empty_fwft_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => empty_fwft_i0,
PRE => AR(0),
Q => empty_fwft_fb_i
);
empty_fwft_fb_o_i_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"B2A2"
)
port map (
I0 => empty_fwft_fb_o_i,
I1 => curr_fwft_state(1),
I2 => curr_fwft_state(0),
I3 => rd_en,
O => empty_fwft_fb_o_i0
);
empty_fwft_fb_o_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => empty_fwft_fb_o_i0,
PRE => AR(0),
Q => empty_fwft_fb_o_i
);
empty_fwft_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => empty_fwft_i0,
PRE => AR(0),
Q => empty_fwft_i
);
\gc0.count_d1[4]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"00DF"
)
port map (
I0 => curr_fwft_state(1),
I1 => rd_en,
I2 => curr_fwft_state(0),
I3 => ram_empty_fb_i_reg_0,
O => E(0)
);
\gpr1.dout_i[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFAEAA0000A2AA"
)
port map (
I0 => p_0_out,
I1 => curr_fwft_state(1),
I2 => rd_en,
I3 => curr_fwft_state(0),
I4 => ram_empty_fb_i_reg_0,
I5 => dout_i,
O => \gpr1.dout_i_reg[0]\
);
\gpregsm1.curr_fwft_state[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AE"
)
port map (
I0 => curr_fwft_state(1),
I1 => curr_fwft_state(0),
I2 => rd_en,
O => next_fwft_state(0)
);
\gpregsm1.curr_fwft_state[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"20FF"
)
port map (
I0 => curr_fwft_state(1),
I1 => rd_en,
I2 => curr_fwft_state(0),
I3 => ram_empty_fb_i_reg_0,
O => next_fwft_state(1)
);
\gpregsm1.curr_fwft_state_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
CLR => AR(0),
D => next_fwft_state(0),
Q => curr_fwft_state(0)
);
\gpregsm1.curr_fwft_state_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
CLR => AR(0),
D => next_fwft_state(1),
Q => curr_fwft_state(1)
);
\gpregsm1.user_valid_reg\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
CLR => AR(0),
D => next_fwft_state(0),
Q => user_valid
);
ram_empty_fb_i_i_4: unisim.vcomponents.LUT3
generic map(
INIT => X"DF"
)
port map (
I0 => curr_fwft_state(0),
I1 => rd_en,
I2 => curr_fwft_state(1),
O => ram_empty_fb_i_reg
);
ram_full_fb_i_i_3: unisim.vcomponents.LUT4
generic map(
INIT => X"FF08"
)
port map (
I0 => curr_fwft_state(0),
I1 => curr_fwft_state(1),
I2 => rd_en,
I3 => ram_empty_fb_i_reg_0,
O => ram_full_fb_i_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_pc_1_rd_status_flags_ss is
port (
\out\ : out STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC;
clk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_pc_1_rd_status_flags_ss : entity is "rd_status_flags_ss";
end system_auto_pc_1_rd_status_flags_ss;
architecture STRUCTURE of system_auto_pc_1_rd_status_flags_ss is
signal ram_empty_fb_i : STD_LOGIC;
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of ram_empty_fb_i : signal is std.standard.true;
signal ram_empty_i : STD_LOGIC;
attribute DONT_TOUCH of ram_empty_i : signal is std.standard.true;
attribute DONT_TOUCH of ram_empty_fb_i_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of ram_empty_fb_i_reg : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of ram_empty_fb_i_reg : label is "no";
attribute DONT_TOUCH of ram_empty_i_reg : label is std.standard.true;
attribute KEEP of ram_empty_i_reg : label is "yes";
attribute equivalent_register_removal of ram_empty_i_reg : label is "no";
begin
\out\ <= ram_empty_fb_i;
ram_empty_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => ram_full_fb_i_reg,
PRE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
Q => ram_empty_fb_i
);
ram_empty_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => ram_full_fb_i_reg,
PRE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
Q => ram_empty_i
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_pc_1_rd_status_flags_ss_17 is
port (
\out\ : out STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC;
clk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_pc_1_rd_status_flags_ss_17 : entity is "rd_status_flags_ss";
end system_auto_pc_1_rd_status_flags_ss_17;
architecture STRUCTURE of system_auto_pc_1_rd_status_flags_ss_17 is
signal ram_empty_fb_i : STD_LOGIC;
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of ram_empty_fb_i : signal is std.standard.true;
signal ram_empty_i : STD_LOGIC;
attribute DONT_TOUCH of ram_empty_i : signal is std.standard.true;
attribute DONT_TOUCH of ram_empty_fb_i_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of ram_empty_fb_i_reg : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of ram_empty_fb_i_reg : label is "no";
attribute DONT_TOUCH of ram_empty_i_reg : label is std.standard.true;
attribute KEEP of ram_empty_i_reg : label is "yes";
attribute equivalent_register_removal of ram_empty_i_reg : label is "no";
begin
\out\ <= ram_empty_fb_i;
ram_empty_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => ram_full_fb_i_reg,
PRE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
Q => ram_empty_fb_i
);
ram_empty_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => ram_full_fb_i_reg,
PRE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
Q => ram_empty_i
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_pc_1_rd_status_flags_ss_31 is
port (
\out\ : out STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC;
clk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_pc_1_rd_status_flags_ss_31 : entity is "rd_status_flags_ss";
end system_auto_pc_1_rd_status_flags_ss_31;
architecture STRUCTURE of system_auto_pc_1_rd_status_flags_ss_31 is
signal ram_empty_fb_i : STD_LOGIC;
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of ram_empty_fb_i : signal is std.standard.true;
signal ram_empty_i : STD_LOGIC;
attribute DONT_TOUCH of ram_empty_i : signal is std.standard.true;
attribute DONT_TOUCH of ram_empty_fb_i_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of ram_empty_fb_i_reg : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of ram_empty_fb_i_reg : label is "no";
attribute DONT_TOUCH of ram_empty_i_reg : label is std.standard.true;
attribute KEEP of ram_empty_i_reg : label is "yes";
attribute equivalent_register_removal of ram_empty_i_reg : label is "no";
begin
\out\ <= ram_empty_fb_i;
ram_empty_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => ram_full_fb_i_reg,
PRE => AR(0),
Q => ram_empty_fb_i
);
ram_empty_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => ram_full_fb_i_reg,
PRE => AR(0),
Q => ram_empty_i
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_pc_1_synchronizer_ff is
port (
\out\ : out STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 );
clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_pc_1_synchronizer_ff : entity is "synchronizer_ff";
end system_auto_pc_1_synchronizer_ff;
architecture STRUCTURE of system_auto_pc_1_synchronizer_ff is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\out\ <= Q_reg;
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => in0(0),
Q => Q_reg,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_pc_1_synchronizer_ff_0 is
port (
\out\ : out STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 );
clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_pc_1_synchronizer_ff_0 : entity is "synchronizer_ff";
end system_auto_pc_1_synchronizer_ff_0;
architecture STRUCTURE of system_auto_pc_1_synchronizer_ff_0 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\out\ <= Q_reg;
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => in0(0),
Q => Q_reg,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_pc_1_synchronizer_ff_1 is
port (
\Q_reg_reg[0]_0\ : out STD_LOGIC;
AS : out STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : in STD_LOGIC;
clk : in STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_pc_1_synchronizer_ff_1 : entity is "synchronizer_ff";
end system_auto_pc_1_synchronizer_ff_1;
architecture STRUCTURE of system_auto_pc_1_synchronizer_ff_1 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\Q_reg_reg[0]_0\ <= Q_reg;
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => \out\,
Q => Q_reg,
R => '0'
);
\ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => in0(0),
I1 => Q_reg,
O => AS(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_pc_1_synchronizer_ff_10 is
port (
\Q_reg_reg[0]_0\ : out STD_LOGIC;
AS : out STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : in STD_LOGIC;
clk : in STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_pc_1_synchronizer_ff_10 : entity is "synchronizer_ff";
end system_auto_pc_1_synchronizer_ff_10;
architecture STRUCTURE of system_auto_pc_1_synchronizer_ff_10 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\Q_reg_reg[0]_0\ <= Q_reg;
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => \out\,
Q => Q_reg,
R => '0'
);
\ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => in0(0),
I1 => Q_reg,
O => AS(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_pc_1_synchronizer_ff_11 is
port (
\Q_reg_reg[0]_0\ : out STD_LOGIC;
AS : out STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : in STD_LOGIC;
clk : in STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_pc_1_synchronizer_ff_11 : entity is "synchronizer_ff";
end system_auto_pc_1_synchronizer_ff_11;
architecture STRUCTURE of system_auto_pc_1_synchronizer_ff_11 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\Q_reg_reg[0]_0\ <= Q_reg;
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => \out\,
Q => Q_reg,
R => '0'
);
\ngwrdrst.grst.g7serrst.wr_rst_reg[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => in0(0),
I1 => Q_reg,
O => AS(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_pc_1_synchronizer_ff_12 is
port (
\Q_reg_reg[0]_0\ : in STD_LOGIC;
clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_pc_1_synchronizer_ff_12 : entity is "synchronizer_ff";
end system_auto_pc_1_synchronizer_ff_12;
architecture STRUCTURE of system_auto_pc_1_synchronizer_ff_12 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => \Q_reg_reg[0]_0\,
Q => Q_reg,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_pc_1_synchronizer_ff_13 is
port (
\Q_reg_reg[0]_0\ : in STD_LOGIC;
clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_pc_1_synchronizer_ff_13 : entity is "synchronizer_ff";
end system_auto_pc_1_synchronizer_ff_13;
architecture STRUCTURE of system_auto_pc_1_synchronizer_ff_13 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => \Q_reg_reg[0]_0\,
Q => Q_reg,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_pc_1_synchronizer_ff_2 is
port (
\Q_reg_reg[0]_0\ : out STD_LOGIC;
AS : out STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : in STD_LOGIC;
clk : in STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_pc_1_synchronizer_ff_2 : entity is "synchronizer_ff";
end system_auto_pc_1_synchronizer_ff_2;
architecture STRUCTURE of system_auto_pc_1_synchronizer_ff_2 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\Q_reg_reg[0]_0\ <= Q_reg;
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => \out\,
Q => Q_reg,
R => '0'
);
\ngwrdrst.grst.g7serrst.wr_rst_reg[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => in0(0),
I1 => Q_reg,
O => AS(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_pc_1_synchronizer_ff_22 is
port (
\out\ : out STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 );
clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_pc_1_synchronizer_ff_22 : entity is "synchronizer_ff";
end system_auto_pc_1_synchronizer_ff_22;
architecture STRUCTURE of system_auto_pc_1_synchronizer_ff_22 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\out\ <= Q_reg;
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => in0(0),
Q => Q_reg,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_pc_1_synchronizer_ff_23 is
port (
\out\ : out STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 );
clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_pc_1_synchronizer_ff_23 : entity is "synchronizer_ff";
end system_auto_pc_1_synchronizer_ff_23;
architecture STRUCTURE of system_auto_pc_1_synchronizer_ff_23 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\out\ <= Q_reg;
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => in0(0),
Q => Q_reg,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_pc_1_synchronizer_ff_24 is
port (
\Q_reg_reg[0]_0\ : out STD_LOGIC;
AS : out STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : in STD_LOGIC;
clk : in STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_pc_1_synchronizer_ff_24 : entity is "synchronizer_ff";
end system_auto_pc_1_synchronizer_ff_24;
architecture STRUCTURE of system_auto_pc_1_synchronizer_ff_24 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\Q_reg_reg[0]_0\ <= Q_reg;
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => \out\,
Q => Q_reg,
R => '0'
);
\ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => in0(0),
I1 => Q_reg,
O => AS(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_pc_1_synchronizer_ff_25 is
port (
\Q_reg_reg[0]_0\ : out STD_LOGIC;
AS : out STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : in STD_LOGIC;
clk : in STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_pc_1_synchronizer_ff_25 : entity is "synchronizer_ff";
end system_auto_pc_1_synchronizer_ff_25;
architecture STRUCTURE of system_auto_pc_1_synchronizer_ff_25 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\Q_reg_reg[0]_0\ <= Q_reg;
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => \out\,
Q => Q_reg,
R => '0'
);
\ngwrdrst.grst.g7serrst.wr_rst_reg[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => in0(0),
I1 => Q_reg,
O => AS(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_pc_1_synchronizer_ff_26 is
port (
\Q_reg_reg[0]_0\ : in STD_LOGIC;
clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_pc_1_synchronizer_ff_26 : entity is "synchronizer_ff";
end system_auto_pc_1_synchronizer_ff_26;
architecture STRUCTURE of system_auto_pc_1_synchronizer_ff_26 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => \Q_reg_reg[0]_0\,
Q => Q_reg,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_pc_1_synchronizer_ff_27 is
port (
\Q_reg_reg[0]_0\ : in STD_LOGIC;
clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_pc_1_synchronizer_ff_27 : entity is "synchronizer_ff";
end system_auto_pc_1_synchronizer_ff_27;
architecture STRUCTURE of system_auto_pc_1_synchronizer_ff_27 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => \Q_reg_reg[0]_0\,
Q => Q_reg,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_pc_1_synchronizer_ff_3 is
port (
\Q_reg_reg[0]_0\ : in STD_LOGIC;
clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_pc_1_synchronizer_ff_3 : entity is "synchronizer_ff";
end system_auto_pc_1_synchronizer_ff_3;
architecture STRUCTURE of system_auto_pc_1_synchronizer_ff_3 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => \Q_reg_reg[0]_0\,
Q => Q_reg,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_pc_1_synchronizer_ff_4 is
port (
\Q_reg_reg[0]_0\ : in STD_LOGIC;
clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_pc_1_synchronizer_ff_4 : entity is "synchronizer_ff";
end system_auto_pc_1_synchronizer_ff_4;
architecture STRUCTURE of system_auto_pc_1_synchronizer_ff_4 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => \Q_reg_reg[0]_0\,
Q => Q_reg,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_pc_1_synchronizer_ff_8 is
port (
\out\ : out STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 );
clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_pc_1_synchronizer_ff_8 : entity is "synchronizer_ff";
end system_auto_pc_1_synchronizer_ff_8;
architecture STRUCTURE of system_auto_pc_1_synchronizer_ff_8 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\out\ <= Q_reg;
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => in0(0),
Q => Q_reg,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_pc_1_synchronizer_ff_9 is
port (
\out\ : out STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 );
clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_pc_1_synchronizer_ff_9 : entity is "synchronizer_ff";
end system_auto_pc_1_synchronizer_ff_9;
architecture STRUCTURE of system_auto_pc_1_synchronizer_ff_9 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\out\ <= Q_reg;
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => in0(0),
Q => Q_reg,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_pc_1_wr_bin_cntr is
port (
ram_full_comb : out STD_LOGIC;
ram_empty_fb_i_reg : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 4 downto 0 );
\gpregsm1.curr_fwft_state_reg[0]\ : in STD_LOGIC;
\out\ : in STD_LOGIC;
\gc0.count_d1_reg[2]\ : in STD_LOGIC;
\gc0.count_reg[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
wr_en : in STD_LOGIC;
\gc0.count_d1_reg[4]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
clk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_pc_1_wr_bin_cntr : entity is "wr_bin_cntr";
end system_auto_pc_1_wr_bin_cntr;
architecture STRUCTURE of system_auto_pc_1_wr_bin_cntr is
signal \^q\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal p_12_out : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \plusOp__0\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal ram_full_fb_i_i_2_n_0 : STD_LOGIC;
signal ram_full_fb_i_i_4_n_0 : STD_LOGIC;
signal ram_full_fb_i_i_5_n_0 : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gcc0.gc0.count[2]_i_1\ : label is "soft_lutpair36";
attribute SOFT_HLUTNM of \gcc0.gc0.count[3]_i_1\ : label is "soft_lutpair35";
attribute SOFT_HLUTNM of \gcc0.gc0.count[4]_i_1\ : label is "soft_lutpair35";
attribute SOFT_HLUTNM of ram_full_fb_i_i_5 : label is "soft_lutpair36";
begin
Q(4 downto 0) <= \^q\(4 downto 0);
\gcc0.gc0.count[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => p_12_out(0),
O => \plusOp__0\(0)
);
\gcc0.gc0.count[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => p_12_out(0),
I1 => p_12_out(1),
O => \plusOp__0\(1)
);
\gcc0.gc0.count[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => p_12_out(1),
I1 => p_12_out(0),
I2 => p_12_out(2),
O => \plusOp__0\(2)
);
\gcc0.gc0.count[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => p_12_out(2),
I1 => p_12_out(0),
I2 => p_12_out(1),
I3 => p_12_out(3),
O => \plusOp__0\(3)
);
\gcc0.gc0.count[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => p_12_out(3),
I1 => p_12_out(1),
I2 => p_12_out(0),
I3 => p_12_out(2),
I4 => p_12_out(4),
O => \plusOp__0\(4)
);
\gcc0.gc0.count_d1_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => p_12_out(0),
Q => \^q\(0)
);
\gcc0.gc0.count_d1_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => p_12_out(1),
Q => \^q\(1)
);
\gcc0.gc0.count_d1_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => p_12_out(2),
Q => \^q\(2)
);
\gcc0.gc0.count_d1_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => p_12_out(3),
Q => \^q\(3)
);
\gcc0.gc0.count_d1_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => p_12_out(4),
Q => \^q\(4)
);
\gcc0.gc0.count_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => E(0),
D => \plusOp__0\(0),
PRE => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
Q => p_12_out(0)
);
\gcc0.gc0.count_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \plusOp__0\(1),
Q => p_12_out(1)
);
\gcc0.gc0.count_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \plusOp__0\(2),
Q => p_12_out(2)
);
\gcc0.gc0.count_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \plusOp__0\(3),
Q => p_12_out(3)
);
\gcc0.gc0.count_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \plusOp__0\(4),
Q => p_12_out(4)
);
ram_empty_fb_i_i_5: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^q\(2),
I1 => \gc0.count_reg[2]\(2),
I2 => \^q\(1),
I3 => \gc0.count_reg[2]\(1),
I4 => \gc0.count_reg[2]\(0),
I5 => \^q\(0),
O => ram_empty_fb_i_reg
);
ram_full_fb_i_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"F8C8"
)
port map (
I0 => ram_full_fb_i_i_2_n_0,
I1 => \gpregsm1.curr_fwft_state_reg[0]\,
I2 => \out\,
I3 => \gc0.count_d1_reg[2]\,
O => ram_full_comb
);
ram_full_fb_i_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"80000080"
)
port map (
I0 => ram_full_fb_i_i_4_n_0,
I1 => ram_full_fb_i_i_5_n_0,
I2 => wr_en,
I3 => \gc0.count_d1_reg[4]\(4),
I4 => p_12_out(4),
O => ram_full_fb_i_i_2_n_0
);
ram_full_fb_i_i_4: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_12_out(2),
I1 => \gc0.count_d1_reg[4]\(2),
I2 => p_12_out(3),
I3 => \gc0.count_d1_reg[4]\(3),
O => ram_full_fb_i_i_4_n_0
);
ram_full_fb_i_i_5: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_12_out(0),
I1 => \gc0.count_d1_reg[4]\(0),
I2 => p_12_out(1),
I3 => \gc0.count_d1_reg[4]\(1),
O => ram_full_fb_i_i_5_n_0
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_pc_1_wr_bin_cntr_15 is
port (
ram_full_comb : out STD_LOGIC;
ram_empty_fb_i_reg : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 4 downto 0 );
\gpregsm1.curr_fwft_state_reg[0]\ : in STD_LOGIC;
\out\ : in STD_LOGIC;
\gc0.count_d1_reg[2]\ : in STD_LOGIC;
\gc0.count_reg[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
wr_en : in STD_LOGIC;
\gc0.count_d1_reg[4]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
clk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_pc_1_wr_bin_cntr_15 : entity is "wr_bin_cntr";
end system_auto_pc_1_wr_bin_cntr_15;
architecture STRUCTURE of system_auto_pc_1_wr_bin_cntr_15 is
signal \^q\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal p_12_out : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \plusOp__0\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal ram_full_fb_i_i_2_n_0 : STD_LOGIC;
signal ram_full_fb_i_i_4_n_0 : STD_LOGIC;
signal ram_full_fb_i_i_5_n_0 : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gcc0.gc0.count[2]_i_1\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \gcc0.gc0.count[3]_i_1\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of \gcc0.gc0.count[4]_i_1\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of ram_full_fb_i_i_5 : label is "soft_lutpair31";
begin
Q(4 downto 0) <= \^q\(4 downto 0);
\gcc0.gc0.count[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => p_12_out(0),
O => \plusOp__0\(0)
);
\gcc0.gc0.count[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => p_12_out(0),
I1 => p_12_out(1),
O => \plusOp__0\(1)
);
\gcc0.gc0.count[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => p_12_out(1),
I1 => p_12_out(0),
I2 => p_12_out(2),
O => \plusOp__0\(2)
);
\gcc0.gc0.count[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => p_12_out(2),
I1 => p_12_out(0),
I2 => p_12_out(1),
I3 => p_12_out(3),
O => \plusOp__0\(3)
);
\gcc0.gc0.count[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => p_12_out(3),
I1 => p_12_out(1),
I2 => p_12_out(0),
I3 => p_12_out(2),
I4 => p_12_out(4),
O => \plusOp__0\(4)
);
\gcc0.gc0.count_d1_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => p_12_out(0),
Q => \^q\(0)
);
\gcc0.gc0.count_d1_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => p_12_out(1),
Q => \^q\(1)
);
\gcc0.gc0.count_d1_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => p_12_out(2),
Q => \^q\(2)
);
\gcc0.gc0.count_d1_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => p_12_out(3),
Q => \^q\(3)
);
\gcc0.gc0.count_d1_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => p_12_out(4),
Q => \^q\(4)
);
\gcc0.gc0.count_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => E(0),
D => \plusOp__0\(0),
PRE => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
Q => p_12_out(0)
);
\gcc0.gc0.count_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \plusOp__0\(1),
Q => p_12_out(1)
);
\gcc0.gc0.count_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \plusOp__0\(2),
Q => p_12_out(2)
);
\gcc0.gc0.count_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \plusOp__0\(3),
Q => p_12_out(3)
);
\gcc0.gc0.count_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \plusOp__0\(4),
Q => p_12_out(4)
);
ram_empty_fb_i_i_5: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^q\(2),
I1 => \gc0.count_reg[2]\(2),
I2 => \^q\(1),
I3 => \gc0.count_reg[2]\(1),
I4 => \gc0.count_reg[2]\(0),
I5 => \^q\(0),
O => ram_empty_fb_i_reg
);
ram_full_fb_i_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"F8C8"
)
port map (
I0 => ram_full_fb_i_i_2_n_0,
I1 => \gpregsm1.curr_fwft_state_reg[0]\,
I2 => \out\,
I3 => \gc0.count_d1_reg[2]\,
O => ram_full_comb
);
ram_full_fb_i_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"80000080"
)
port map (
I0 => ram_full_fb_i_i_4_n_0,
I1 => ram_full_fb_i_i_5_n_0,
I2 => wr_en,
I3 => \gc0.count_d1_reg[4]\(4),
I4 => p_12_out(4),
O => ram_full_fb_i_i_2_n_0
);
ram_full_fb_i_i_4: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_12_out(2),
I1 => \gc0.count_d1_reg[4]\(2),
I2 => p_12_out(3),
I3 => \gc0.count_d1_reg[4]\(3),
O => ram_full_fb_i_i_4_n_0
);
ram_full_fb_i_i_5: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_12_out(0),
I1 => \gc0.count_d1_reg[4]\(0),
I2 => p_12_out(1),
I3 => \gc0.count_d1_reg[4]\(1),
O => ram_full_fb_i_i_5_n_0
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_pc_1_wr_bin_cntr_29 is
port (
ram_full_comb : out STD_LOGIC;
ram_empty_fb_i_reg : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 4 downto 0 );
\gpregsm1.curr_fwft_state_reg[0]\ : in STD_LOGIC;
\out\ : in STD_LOGIC;
\gc0.count_d1_reg[2]\ : in STD_LOGIC;
\gc0.count_reg[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
wr_en : in STD_LOGIC;
\gc0.count_d1_reg[4]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
clk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_pc_1_wr_bin_cntr_29 : entity is "wr_bin_cntr";
end system_auto_pc_1_wr_bin_cntr_29;
architecture STRUCTURE of system_auto_pc_1_wr_bin_cntr_29 is
signal \^q\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal p_12_out : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \plusOp__0\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal ram_full_fb_i_i_2_n_0 : STD_LOGIC;
signal ram_full_fb_i_i_4_n_0 : STD_LOGIC;
signal ram_full_fb_i_i_5_n_0 : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gcc0.gc0.count[2]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \gcc0.gc0.count[3]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \gcc0.gc0.count[4]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of ram_full_fb_i_i_5 : label is "soft_lutpair3";
begin
Q(4 downto 0) <= \^q\(4 downto 0);
\gcc0.gc0.count[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => p_12_out(0),
O => \plusOp__0\(0)
);
\gcc0.gc0.count[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => p_12_out(0),
I1 => p_12_out(1),
O => \plusOp__0\(1)
);
\gcc0.gc0.count[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => p_12_out(1),
I1 => p_12_out(0),
I2 => p_12_out(2),
O => \plusOp__0\(2)
);
\gcc0.gc0.count[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => p_12_out(2),
I1 => p_12_out(0),
I2 => p_12_out(1),
I3 => p_12_out(3),
O => \plusOp__0\(3)
);
\gcc0.gc0.count[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => p_12_out(3),
I1 => p_12_out(1),
I2 => p_12_out(0),
I3 => p_12_out(2),
I4 => p_12_out(4),
O => \plusOp__0\(4)
);
\gcc0.gc0.count_d1_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => p_12_out(0),
Q => \^q\(0)
);
\gcc0.gc0.count_d1_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => p_12_out(1),
Q => \^q\(1)
);
\gcc0.gc0.count_d1_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => p_12_out(2),
Q => \^q\(2)
);
\gcc0.gc0.count_d1_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => p_12_out(3),
Q => \^q\(3)
);
\gcc0.gc0.count_d1_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => p_12_out(4),
Q => \^q\(4)
);
\gcc0.gc0.count_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => E(0),
D => \plusOp__0\(0),
PRE => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
Q => p_12_out(0)
);
\gcc0.gc0.count_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \plusOp__0\(1),
Q => p_12_out(1)
);
\gcc0.gc0.count_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \plusOp__0\(2),
Q => p_12_out(2)
);
\gcc0.gc0.count_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \plusOp__0\(3),
Q => p_12_out(3)
);
\gcc0.gc0.count_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \plusOp__0\(4),
Q => p_12_out(4)
);
ram_empty_fb_i_i_5: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^q\(2),
I1 => \gc0.count_reg[2]\(2),
I2 => \^q\(1),
I3 => \gc0.count_reg[2]\(1),
I4 => \gc0.count_reg[2]\(0),
I5 => \^q\(0),
O => ram_empty_fb_i_reg
);
ram_full_fb_i_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"F8C8"
)
port map (
I0 => ram_full_fb_i_i_2_n_0,
I1 => \gpregsm1.curr_fwft_state_reg[0]\,
I2 => \out\,
I3 => \gc0.count_d1_reg[2]\,
O => ram_full_comb
);
ram_full_fb_i_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"80000080"
)
port map (
I0 => ram_full_fb_i_i_4_n_0,
I1 => ram_full_fb_i_i_5_n_0,
I2 => wr_en,
I3 => \gc0.count_d1_reg[4]\(4),
I4 => p_12_out(4),
O => ram_full_fb_i_i_2_n_0
);
ram_full_fb_i_i_4: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_12_out(2),
I1 => \gc0.count_d1_reg[4]\(2),
I2 => p_12_out(3),
I3 => \gc0.count_d1_reg[4]\(3),
O => ram_full_fb_i_i_4_n_0
);
ram_full_fb_i_i_5: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_12_out(0),
I1 => \gc0.count_d1_reg[4]\(0),
I2 => p_12_out(1),
I3 => \gc0.count_d1_reg[4]\(1),
O => ram_full_fb_i_i_5_n_0
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_pc_1_wr_status_flags_ss is
port (
\out\ : out STD_LOGIC;
full : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
ram_full_comb : in STD_LOGIC;
clk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
wr_en : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_pc_1_wr_status_flags_ss : entity is "wr_status_flags_ss";
end system_auto_pc_1_wr_status_flags_ss;
architecture STRUCTURE of system_auto_pc_1_wr_status_flags_ss is
signal ram_afull_fb : STD_LOGIC;
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of ram_afull_fb : signal is std.standard.true;
signal ram_afull_i : STD_LOGIC;
attribute DONT_TOUCH of ram_afull_i : signal is std.standard.true;
signal ram_full_fb_i : STD_LOGIC;
attribute DONT_TOUCH of ram_full_fb_i : signal is std.standard.true;
signal ram_full_i : STD_LOGIC;
attribute DONT_TOUCH of ram_full_i : signal is std.standard.true;
attribute DONT_TOUCH of ram_full_fb_i_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of ram_full_fb_i_reg : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of ram_full_fb_i_reg : label is "no";
attribute DONT_TOUCH of ram_full_i_reg : label is std.standard.true;
attribute KEEP of ram_full_i_reg : label is "yes";
attribute equivalent_register_removal of ram_full_i_reg : label is "no";
begin
full <= ram_full_i;
\out\ <= ram_full_fb_i;
\gcc0.gc0.count_d1[4]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => wr_en,
I1 => ram_full_fb_i,
O => E(0)
);
i_0: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => ram_afull_i
);
i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => ram_afull_fb
);
ram_full_fb_i_reg: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => ram_full_comb,
Q => ram_full_fb_i
);
ram_full_i_reg: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => ram_full_comb,
Q => ram_full_i
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_pc_1_wr_status_flags_ss_14 is
port (
\out\ : out STD_LOGIC;
full : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
ram_full_comb : in STD_LOGIC;
clk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
wr_en : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_pc_1_wr_status_flags_ss_14 : entity is "wr_status_flags_ss";
end system_auto_pc_1_wr_status_flags_ss_14;
architecture STRUCTURE of system_auto_pc_1_wr_status_flags_ss_14 is
signal ram_afull_fb : STD_LOGIC;
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of ram_afull_fb : signal is std.standard.true;
signal ram_afull_i : STD_LOGIC;
attribute DONT_TOUCH of ram_afull_i : signal is std.standard.true;
signal ram_full_fb_i : STD_LOGIC;
attribute DONT_TOUCH of ram_full_fb_i : signal is std.standard.true;
signal ram_full_i : STD_LOGIC;
attribute DONT_TOUCH of ram_full_i : signal is std.standard.true;
attribute DONT_TOUCH of ram_full_fb_i_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of ram_full_fb_i_reg : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of ram_full_fb_i_reg : label is "no";
attribute DONT_TOUCH of ram_full_i_reg : label is std.standard.true;
attribute KEEP of ram_full_i_reg : label is "yes";
attribute equivalent_register_removal of ram_full_i_reg : label is "no";
begin
full <= ram_full_i;
\out\ <= ram_full_fb_i;
\gcc0.gc0.count_d1[4]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => wr_en,
I1 => ram_full_fb_i,
O => E(0)
);
i_0: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => ram_afull_i
);
i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => ram_afull_fb
);
ram_full_fb_i_reg: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => ram_full_comb,
Q => ram_full_fb_i
);
ram_full_i_reg: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => ram_full_comb,
Q => ram_full_i
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_pc_1_wr_status_flags_ss_28 is
port (
\out\ : out STD_LOGIC;
full : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
ram_full_comb : in STD_LOGIC;
clk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
wr_en : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_pc_1_wr_status_flags_ss_28 : entity is "wr_status_flags_ss";
end system_auto_pc_1_wr_status_flags_ss_28;
architecture STRUCTURE of system_auto_pc_1_wr_status_flags_ss_28 is
signal ram_afull_fb : STD_LOGIC;
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of ram_afull_fb : signal is std.standard.true;
signal ram_afull_i : STD_LOGIC;
attribute DONT_TOUCH of ram_afull_i : signal is std.standard.true;
signal ram_full_fb_i : STD_LOGIC;
attribute DONT_TOUCH of ram_full_fb_i : signal is std.standard.true;
signal ram_full_i : STD_LOGIC;
attribute DONT_TOUCH of ram_full_i : signal is std.standard.true;
attribute DONT_TOUCH of ram_full_fb_i_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of ram_full_fb_i_reg : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of ram_full_fb_i_reg : label is "no";
attribute DONT_TOUCH of ram_full_i_reg : label is std.standard.true;
attribute KEEP of ram_full_i_reg : label is "yes";
attribute equivalent_register_removal of ram_full_i_reg : label is "no";
begin
full <= ram_full_i;
\out\ <= ram_full_fb_i;
\gcc0.gc0.count_d1[4]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => wr_en,
I1 => ram_full_fb_i,
O => E(0)
);
i_0: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => ram_afull_i
);
i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => ram_afull_fb
);
ram_full_fb_i_reg: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => ram_full_comb,
Q => ram_full_fb_i
);
ram_full_i_reg: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => ram_full_comb,
Q => ram_full_i
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_pc_1_memory is
port (
dout : out STD_LOGIC_VECTOR ( 5 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
clk : in STD_LOGIC;
EN : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 5 downto 0 );
\gc0.count_d1_reg[4]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
I54 : in STD_LOGIC_VECTOR ( 4 downto 0 );
\gpregsm1.curr_fwft_state_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_pc_1_memory : entity is "memory";
end system_auto_pc_1_memory;
architecture STRUCTURE of system_auto_pc_1_memory is
signal dout_i : STD_LOGIC_VECTOR ( 5 downto 0 );
begin
\gdm.dm_gen.dm\: entity work.system_auto_pc_1_dmem
port map (
EN => EN,
I54(4 downto 0) => I54(4 downto 0),
clk => clk,
din(5 downto 0) => din(5 downto 0),
dout_i(5 downto 0) => dout_i(5 downto 0),
\gc0.count_d1_reg[4]\(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0),
\gpregsm1.curr_fwft_state_reg[1]\(0) => \gpregsm1.curr_fwft_state_reg[1]\(0)
);
\goreg_dm.dout_i_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => dout_i(0),
Q => dout(0),
R => '0'
);
\goreg_dm.dout_i_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => dout_i(1),
Q => dout(1),
R => '0'
);
\goreg_dm.dout_i_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => dout_i(2),
Q => dout(2),
R => '0'
);
\goreg_dm.dout_i_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => dout_i(3),
Q => dout(3),
R => '0'
);
\goreg_dm.dout_i_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => dout_i(4),
Q => dout(4),
R => '0'
);
\goreg_dm.dout_i_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => dout_i(5),
Q => dout(5),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_auto_pc_1_memory__parameterized0\ is
port (
dout : out STD_LOGIC_VECTOR ( 4 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
clk : in STD_LOGIC;
EN : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 4 downto 0 );
\gc0.count_d1_reg[4]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
I55 : in STD_LOGIC_VECTOR ( 4 downto 0 );
\gpregsm1.curr_fwft_state_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_auto_pc_1_memory__parameterized0\ : entity is "memory";
end \system_auto_pc_1_memory__parameterized0\;
architecture STRUCTURE of \system_auto_pc_1_memory__parameterized0\ is
signal dout_i : STD_LOGIC_VECTOR ( 4 downto 0 );
begin
\gdm.dm_gen.dm\: entity work.\system_auto_pc_1_dmem__parameterized0\
port map (
EN => EN,
I55(4 downto 0) => I55(4 downto 0),
clk => clk,
din(4 downto 0) => din(4 downto 0),
dout_i(4 downto 0) => dout_i(4 downto 0),
\gc0.count_d1_reg[4]\(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0),
\gpregsm1.curr_fwft_state_reg[1]\(0) => \gpregsm1.curr_fwft_state_reg[1]\(0)
);
\goreg_dm.dout_i_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => dout_i(0),
Q => dout(0),
R => '0'
);
\goreg_dm.dout_i_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => dout_i(1),
Q => dout(1),
R => '0'
);
\goreg_dm.dout_i_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => dout_i(2),
Q => dout(2),
R => '0'
);
\goreg_dm.dout_i_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => dout_i(3),
Q => dout(3),
R => '0'
);
\goreg_dm.dout_i_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => dout_i(4),
Q => dout(4),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_auto_pc_1_memory__parameterized1\ is
port (
p_0_out : out STD_LOGIC;
dout_i : out STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 0 to 0 );
clk : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 0 to 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 4 downto 0 );
\gc0.count_d1_reg[4]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
\gpregsm1.curr_fwft_state_reg[1]\ : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\gpregsm1.curr_fwft_state_reg[1]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
rd_en : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_auto_pc_1_memory__parameterized1\ : entity is "memory";
end \system_auto_pc_1_memory__parameterized1\;
architecture STRUCTURE of \system_auto_pc_1_memory__parameterized1\ is
signal \^dout\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \gdm.dm_gen.dm_n_2\ : STD_LOGIC;
begin
dout(0) <= \^dout\(0);
\gdm.dm_gen.dm\: entity work.\system_auto_pc_1_dmem__parameterized1\
port map (
E(0) => E(0),
Q(4 downto 0) => Q(4 downto 0),
clk => clk,
din(0) => din(0),
dout(0) => \^dout\(0),
dout_i => dout_i,
\gc0.count_d1_reg[4]\(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0),
\goreg_dm.dout_i_reg[0]\ => \gdm.dm_gen.dm_n_2\,
\gpregsm1.curr_fwft_state_reg[1]\ => \gpregsm1.curr_fwft_state_reg[1]\,
\gpregsm1.curr_fwft_state_reg[1]_0\(1 downto 0) => \gpregsm1.curr_fwft_state_reg[1]_0\(1 downto 0),
\out\(0) => \out\(0),
p_0_out => p_0_out,
rd_en => rd_en
);
\goreg_dm.dout_i_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => \gdm.dm_gen.dm_n_2\,
Q => \^dout\(0),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_pc_1_rd_logic is
port (
empty : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 2 downto 0 );
ram_empty_fb_i_reg : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\goreg_dm.dout_i_reg[4]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gpr1.dout_i_reg[1]\ : out STD_LOGIC_VECTOR ( 4 downto 0 );
ram_full_fb_i_reg : out STD_LOGIC;
clk : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
rd_en : in STD_LOGIC;
wr_en : in STD_LOGIC;
ram_full_fb_i_reg_0 : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[4]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
\gcc0.gc0.count_d1_reg[2]\ : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_pc_1_rd_logic : entity is "rd_logic";
end system_auto_pc_1_rd_logic;
architecture STRUCTURE of system_auto_pc_1_rd_logic is
signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \gr1.gr1_int.rfwft_n_2\ : STD_LOGIC;
signal p_2_out : STD_LOGIC;
signal rpntr_n_3 : STD_LOGIC;
begin
E(0) <= \^e\(0);
\gr1.gr1_int.rfwft\: entity work.system_auto_pc_1_rd_fwft
port map (
E(0) => \^e\(0),
clk => clk,
empty => empty,
\goreg_dm.dout_i_reg[4]\(0) => \goreg_dm.dout_i_reg[4]\(0),
\out\(1 downto 0) => \out\(1 downto 0),
ram_empty_fb_i_reg => \gr1.gr1_int.rfwft_n_2\,
ram_empty_fb_i_reg_0 => p_2_out,
ram_full_fb_i_reg => ram_full_fb_i_reg,
rd_en => rd_en
);
\grss.rsts\: entity work.system_auto_pc_1_rd_status_flags_ss
port map (
clk => clk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0) => \out\(1),
\out\ => p_2_out,
ram_full_fb_i_reg => rpntr_n_3
);
rpntr: entity work.system_auto_pc_1_rd_bin_cntr
port map (
E(0) => \^e\(0),
Q(2 downto 0) => Q(2 downto 0),
clk => clk,
\gcc0.gc0.count_d1_reg[2]\ => \gcc0.gc0.count_d1_reg[2]\,
\gcc0.gc0.count_d1_reg[4]\(4 downto 0) => \gcc0.gc0.count_d1_reg[4]\(4 downto 0),
\gpr1.dout_i_reg[1]\(4 downto 0) => \gpr1.dout_i_reg[1]\(4 downto 0),
\gpregsm1.curr_fwft_state_reg[0]\ => \gr1.gr1_int.rfwft_n_2\,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0) => \out\(1),
\out\ => p_2_out,
ram_empty_fb_i_reg => rpntr_n_3,
ram_empty_fb_i_reg_0 => ram_empty_fb_i_reg,
ram_full_fb_i_reg => ram_full_fb_i_reg_0,
wr_en => wr_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_pc_1_rd_logic_19 is
port (
\out\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
empty : out STD_LOGIC;
\gpr1.dout_i_reg[0]\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 2 downto 0 );
ram_empty_fb_i_reg : out STD_LOGIC;
\gpr1.dout_i_reg[0]_0\ : out STD_LOGIC_VECTOR ( 4 downto 0 );
ram_full_fb_i_reg : out STD_LOGIC;
clk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 );
p_0_out : in STD_LOGIC;
rd_en : in STD_LOGIC;
dout_i : in STD_LOGIC;
wr_en : in STD_LOGIC;
ram_full_fb_i_reg_0 : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[4]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
\gcc0.gc0.count_d1_reg[2]\ : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_pc_1_rd_logic_19 : entity is "rd_logic";
end system_auto_pc_1_rd_logic_19;
architecture STRUCTURE of system_auto_pc_1_rd_logic_19 is
signal \gntv_or_sync_fifo.mem/ram_rd_en_i\ : STD_LOGIC;
signal \gr1.gr1_int.rfwft_n_5\ : STD_LOGIC;
signal p_2_out : STD_LOGIC;
signal rpntr_n_3 : STD_LOGIC;
begin
\gr1.gr1_int.rfwft\: entity work.system_auto_pc_1_rd_fwft_30
port map (
AR(0) => AR(0),
E(0) => \gntv_or_sync_fifo.mem/ram_rd_en_i\,
clk => clk,
dout_i => dout_i,
empty => empty,
\gpr1.dout_i_reg[0]\ => \gpr1.dout_i_reg[0]\,
\out\(1 downto 0) => \out\(1 downto 0),
p_0_out => p_0_out,
ram_empty_fb_i_reg => \gr1.gr1_int.rfwft_n_5\,
ram_empty_fb_i_reg_0 => p_2_out,
ram_full_fb_i_reg => ram_full_fb_i_reg,
rd_en => rd_en
);
\grss.rsts\: entity work.system_auto_pc_1_rd_status_flags_ss_31
port map (
AR(0) => AR(0),
clk => clk,
\out\ => p_2_out,
ram_full_fb_i_reg => rpntr_n_3
);
rpntr: entity work.system_auto_pc_1_rd_bin_cntr_32
port map (
AR(0) => AR(0),
E(0) => \gntv_or_sync_fifo.mem/ram_rd_en_i\,
Q(2 downto 0) => Q(2 downto 0),
clk => clk,
\gcc0.gc0.count_d1_reg[2]\ => \gcc0.gc0.count_d1_reg[2]\,
\gcc0.gc0.count_d1_reg[4]\(4 downto 0) => \gcc0.gc0.count_d1_reg[4]\(4 downto 0),
\gpr1.dout_i_reg[0]\(4 downto 0) => \gpr1.dout_i_reg[0]_0\(4 downto 0),
\gpregsm1.curr_fwft_state_reg[0]\ => \gr1.gr1_int.rfwft_n_5\,
\out\ => p_2_out,
ram_empty_fb_i_reg => rpntr_n_3,
ram_empty_fb_i_reg_0 => ram_empty_fb_i_reg,
ram_full_fb_i_reg => ram_full_fb_i_reg_0,
wr_en => wr_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_pc_1_rd_logic_5 is
port (
empty : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 2 downto 0 );
ram_empty_fb_i_reg : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\goreg_dm.dout_i_reg[5]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gpr1.dout_i_reg[1]\ : out STD_LOGIC_VECTOR ( 4 downto 0 );
ram_full_fb_i_reg : out STD_LOGIC;
clk : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
rd_en : in STD_LOGIC;
wr_en : in STD_LOGIC;
ram_full_fb_i_reg_0 : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[4]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
\gcc0.gc0.count_d1_reg[2]\ : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_pc_1_rd_logic_5 : entity is "rd_logic";
end system_auto_pc_1_rd_logic_5;
architecture STRUCTURE of system_auto_pc_1_rd_logic_5 is
signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \gr1.gr1_int.rfwft_n_2\ : STD_LOGIC;
signal p_2_out : STD_LOGIC;
signal rpntr_n_3 : STD_LOGIC;
begin
E(0) <= \^e\(0);
\gr1.gr1_int.rfwft\: entity work.system_auto_pc_1_rd_fwft_16
port map (
E(0) => \^e\(0),
clk => clk,
empty => empty,
\goreg_dm.dout_i_reg[5]\(0) => \goreg_dm.dout_i_reg[5]\(0),
\out\(1 downto 0) => \out\(1 downto 0),
ram_empty_fb_i_reg => \gr1.gr1_int.rfwft_n_2\,
ram_empty_fb_i_reg_0 => p_2_out,
ram_full_fb_i_reg => ram_full_fb_i_reg,
rd_en => rd_en
);
\grss.rsts\: entity work.system_auto_pc_1_rd_status_flags_ss_17
port map (
clk => clk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0) => \out\(1),
\out\ => p_2_out,
ram_full_fb_i_reg => rpntr_n_3
);
rpntr: entity work.system_auto_pc_1_rd_bin_cntr_18
port map (
E(0) => \^e\(0),
Q(2 downto 0) => Q(2 downto 0),
clk => clk,
\gcc0.gc0.count_d1_reg[2]\ => \gcc0.gc0.count_d1_reg[2]\,
\gcc0.gc0.count_d1_reg[4]\(4 downto 0) => \gcc0.gc0.count_d1_reg[4]\(4 downto 0),
\gpr1.dout_i_reg[1]\(4 downto 0) => \gpr1.dout_i_reg[1]\(4 downto 0),
\gpregsm1.curr_fwft_state_reg[0]\ => \gr1.gr1_int.rfwft_n_2\,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0) => \out\(1),
\out\ => p_2_out,
ram_empty_fb_i_reg => rpntr_n_3,
ram_empty_fb_i_reg_0 => ram_empty_fb_i_reg,
ram_full_fb_i_reg => ram_full_fb_i_reg_0,
wr_en => wr_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_pc_1_reset_blk_ramfifo is
port (
\out\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
\gc0.count_reg[1]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
clk : in STD_LOGIC;
rst : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_pc_1_reset_blk_ramfifo : entity is "reset_blk_ramfifo";
end system_auto_pc_1_reset_blk_ramfifo;
architecture STRUCTURE of system_auto_pc_1_reset_blk_ramfifo is
signal \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\ : STD_LOGIC;
signal \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\ : STD_LOGIC;
signal p_6_out : STD_LOGIC;
signal p_7_out : STD_LOGIC;
signal p_8_out : STD_LOGIC;
signal p_9_out : STD_LOGIC;
signal rd_rst_asreg : STD_LOGIC;
signal rd_rst_reg : STD_LOGIC_VECTOR ( 2 downto 0 );
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of rd_rst_reg : signal is std.standard.true;
signal rst_rd_reg1 : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of rst_rd_reg1 : signal is "true";
attribute msgon : string;
attribute msgon of rst_rd_reg1 : signal is "true";
signal rst_rd_reg2 : STD_LOGIC;
attribute async_reg of rst_rd_reg2 : signal is "true";
attribute msgon of rst_rd_reg2 : signal is "true";
signal rst_wr_reg1 : STD_LOGIC;
attribute async_reg of rst_wr_reg1 : signal is "true";
attribute msgon of rst_wr_reg1 : signal is "true";
signal rst_wr_reg2 : STD_LOGIC;
attribute async_reg of rst_wr_reg2 : signal is "true";
attribute msgon of rst_wr_reg2 : signal is "true";
signal wr_rst_asreg : STD_LOGIC;
signal wr_rst_reg : STD_LOGIC_VECTOR ( 2 downto 0 );
attribute DONT_TOUCH of wr_rst_reg : signal is std.standard.true;
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is "no";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is "true";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is "no";
begin
\gc0.count_reg[1]\(1) <= rd_rst_reg(2);
\gc0.count_reg[1]\(0) <= rd_rst_reg(0);
\out\(1 downto 0) <= wr_rst_reg(1 downto 0);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst\: entity work.system_auto_pc_1_synchronizer_ff
port map (
clk => clk,
in0(0) => rd_rst_asreg,
\out\ => p_6_out
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst\: entity work.system_auto_pc_1_synchronizer_ff_0
port map (
clk => clk,
in0(0) => wr_rst_asreg,
\out\ => p_7_out
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst\: entity work.system_auto_pc_1_synchronizer_ff_1
port map (
AS(0) => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\,
\Q_reg_reg[0]_0\ => p_8_out,
clk => clk,
in0(0) => rd_rst_asreg,
\out\ => p_6_out
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst\: entity work.system_auto_pc_1_synchronizer_ff_2
port map (
AS(0) => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\,
\Q_reg_reg[0]_0\ => p_9_out,
clk => clk,
in0(0) => wr_rst_asreg,
\out\ => p_7_out
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[3].rrst_inst\: entity work.system_auto_pc_1_synchronizer_ff_3
port map (
\Q_reg_reg[0]_0\ => p_8_out,
clk => clk
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[3].wrst_inst\: entity work.system_auto_pc_1_synchronizer_ff_4
port map (
\Q_reg_reg[0]_0\ => p_9_out,
clk => clk
);
\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\,
PRE => rst_rd_reg2,
Q => rd_rst_asreg
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\,
Q => rd_rst_reg(0)
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\,
Q => rd_rst_reg(1)
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\,
Q => rd_rst_reg(2)
);
\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => rst,
Q => rst_rd_reg1
);
\ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => rst_rd_reg1,
PRE => rst,
Q => rst_rd_reg2
);
\ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => rst,
Q => rst_wr_reg1
);
\ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => rst_wr_reg1,
PRE => rst,
Q => rst_wr_reg2
);
\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\,
PRE => rst_wr_reg2,
Q => wr_rst_asreg
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\,
Q => wr_rst_reg(0)
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\,
Q => wr_rst_reg(1)
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\,
Q => wr_rst_reg(2)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_pc_1_reset_blk_ramfifo_21 is
port (
\out\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
\gc0.count_reg[1]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
clk : in STD_LOGIC;
rst : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_pc_1_reset_blk_ramfifo_21 : entity is "reset_blk_ramfifo";
end system_auto_pc_1_reset_blk_ramfifo_21;
architecture STRUCTURE of system_auto_pc_1_reset_blk_ramfifo_21 is
signal \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\ : STD_LOGIC;
signal \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\ : STD_LOGIC;
signal p_6_out : STD_LOGIC;
signal p_7_out : STD_LOGIC;
signal p_8_out : STD_LOGIC;
signal p_9_out : STD_LOGIC;
signal rd_rst_asreg : STD_LOGIC;
signal rd_rst_reg : STD_LOGIC_VECTOR ( 2 downto 0 );
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of rd_rst_reg : signal is std.standard.true;
signal rst_rd_reg1 : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of rst_rd_reg1 : signal is "true";
attribute msgon : string;
attribute msgon of rst_rd_reg1 : signal is "true";
signal rst_rd_reg2 : STD_LOGIC;
attribute async_reg of rst_rd_reg2 : signal is "true";
attribute msgon of rst_rd_reg2 : signal is "true";
signal rst_wr_reg1 : STD_LOGIC;
attribute async_reg of rst_wr_reg1 : signal is "true";
attribute msgon of rst_wr_reg1 : signal is "true";
signal rst_wr_reg2 : STD_LOGIC;
attribute async_reg of rst_wr_reg2 : signal is "true";
attribute msgon of rst_wr_reg2 : signal is "true";
signal wr_rst_asreg : STD_LOGIC;
signal wr_rst_reg : STD_LOGIC_VECTOR ( 2 downto 0 );
attribute DONT_TOUCH of wr_rst_reg : signal is std.standard.true;
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is "no";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is "true";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is "no";
begin
\gc0.count_reg[1]\(1) <= rd_rst_reg(2);
\gc0.count_reg[1]\(0) <= rd_rst_reg(0);
\out\(1 downto 0) <= wr_rst_reg(1 downto 0);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst\: entity work.system_auto_pc_1_synchronizer_ff_22
port map (
clk => clk,
in0(0) => rd_rst_asreg,
\out\ => p_6_out
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst\: entity work.system_auto_pc_1_synchronizer_ff_23
port map (
clk => clk,
in0(0) => wr_rst_asreg,
\out\ => p_7_out
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst\: entity work.system_auto_pc_1_synchronizer_ff_24
port map (
AS(0) => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\,
\Q_reg_reg[0]_0\ => p_8_out,
clk => clk,
in0(0) => rd_rst_asreg,
\out\ => p_6_out
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst\: entity work.system_auto_pc_1_synchronizer_ff_25
port map (
AS(0) => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\,
\Q_reg_reg[0]_0\ => p_9_out,
clk => clk,
in0(0) => wr_rst_asreg,
\out\ => p_7_out
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[3].rrst_inst\: entity work.system_auto_pc_1_synchronizer_ff_26
port map (
\Q_reg_reg[0]_0\ => p_8_out,
clk => clk
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[3].wrst_inst\: entity work.system_auto_pc_1_synchronizer_ff_27
port map (
\Q_reg_reg[0]_0\ => p_9_out,
clk => clk
);
\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\,
PRE => rst_rd_reg2,
Q => rd_rst_asreg
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\,
Q => rd_rst_reg(0)
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\,
Q => rd_rst_reg(1)
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\,
Q => rd_rst_reg(2)
);
\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => rst,
Q => rst_rd_reg1
);
\ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => rst_rd_reg1,
PRE => rst,
Q => rst_rd_reg2
);
\ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => rst,
Q => rst_wr_reg1
);
\ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => rst_wr_reg1,
PRE => rst,
Q => rst_wr_reg2
);
\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\,
PRE => rst_wr_reg2,
Q => wr_rst_asreg
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\,
Q => wr_rst_reg(0)
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\,
Q => wr_rst_reg(1)
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\,
Q => wr_rst_reg(2)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_pc_1_reset_blk_ramfifo_7 is
port (
\out\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
\gc0.count_reg[1]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
clk : in STD_LOGIC;
rst : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_pc_1_reset_blk_ramfifo_7 : entity is "reset_blk_ramfifo";
end system_auto_pc_1_reset_blk_ramfifo_7;
architecture STRUCTURE of system_auto_pc_1_reset_blk_ramfifo_7 is
signal \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\ : STD_LOGIC;
signal \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\ : STD_LOGIC;
signal p_6_out : STD_LOGIC;
signal p_7_out : STD_LOGIC;
signal p_8_out : STD_LOGIC;
signal p_9_out : STD_LOGIC;
signal rd_rst_asreg : STD_LOGIC;
signal rd_rst_reg : STD_LOGIC_VECTOR ( 2 downto 0 );
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of rd_rst_reg : signal is std.standard.true;
signal rst_rd_reg1 : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of rst_rd_reg1 : signal is "true";
attribute msgon : string;
attribute msgon of rst_rd_reg1 : signal is "true";
signal rst_rd_reg2 : STD_LOGIC;
attribute async_reg of rst_rd_reg2 : signal is "true";
attribute msgon of rst_rd_reg2 : signal is "true";
signal rst_wr_reg1 : STD_LOGIC;
attribute async_reg of rst_wr_reg1 : signal is "true";
attribute msgon of rst_wr_reg1 : signal is "true";
signal rst_wr_reg2 : STD_LOGIC;
attribute async_reg of rst_wr_reg2 : signal is "true";
attribute msgon of rst_wr_reg2 : signal is "true";
signal wr_rst_asreg : STD_LOGIC;
signal wr_rst_reg : STD_LOGIC_VECTOR ( 2 downto 0 );
attribute DONT_TOUCH of wr_rst_reg : signal is std.standard.true;
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is "no";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is "true";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is "no";
begin
\gc0.count_reg[1]\(1) <= rd_rst_reg(2);
\gc0.count_reg[1]\(0) <= rd_rst_reg(0);
\out\(1 downto 0) <= wr_rst_reg(1 downto 0);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst\: entity work.system_auto_pc_1_synchronizer_ff_8
port map (
clk => clk,
in0(0) => rd_rst_asreg,
\out\ => p_6_out
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst\: entity work.system_auto_pc_1_synchronizer_ff_9
port map (
clk => clk,
in0(0) => wr_rst_asreg,
\out\ => p_7_out
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst\: entity work.system_auto_pc_1_synchronizer_ff_10
port map (
AS(0) => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\,
\Q_reg_reg[0]_0\ => p_8_out,
clk => clk,
in0(0) => rd_rst_asreg,
\out\ => p_6_out
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst\: entity work.system_auto_pc_1_synchronizer_ff_11
port map (
AS(0) => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\,
\Q_reg_reg[0]_0\ => p_9_out,
clk => clk,
in0(0) => wr_rst_asreg,
\out\ => p_7_out
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[3].rrst_inst\: entity work.system_auto_pc_1_synchronizer_ff_12
port map (
\Q_reg_reg[0]_0\ => p_8_out,
clk => clk
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[3].wrst_inst\: entity work.system_auto_pc_1_synchronizer_ff_13
port map (
\Q_reg_reg[0]_0\ => p_9_out,
clk => clk
);
\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\,
PRE => rst_rd_reg2,
Q => rd_rst_asreg
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\,
Q => rd_rst_reg(0)
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\,
Q => rd_rst_reg(1)
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\,
Q => rd_rst_reg(2)
);
\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => rst,
Q => rst_rd_reg1
);
\ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => rst_rd_reg1,
PRE => rst,
Q => rst_rd_reg2
);
\ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => rst,
Q => rst_wr_reg1
);
\ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => rst_wr_reg1,
PRE => rst,
Q => rst_wr_reg2
);
\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\,
PRE => rst_wr_reg2,
Q => wr_rst_asreg
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\,
Q => wr_rst_reg(0)
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\,
Q => wr_rst_reg(1)
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\,
Q => wr_rst_reg(2)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_pc_1_wr_logic is
port (
\out\ : out STD_LOGIC;
full : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
ram_empty_fb_i_reg : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 4 downto 0 );
clk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
wr_en : in STD_LOGIC;
\gpregsm1.curr_fwft_state_reg[0]\ : in STD_LOGIC;
\gc0.count_d1_reg[2]\ : in STD_LOGIC;
\gc0.count_reg[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\gc0.count_d1_reg[4]\ : in STD_LOGIC_VECTOR ( 4 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_pc_1_wr_logic : entity is "wr_logic";
end system_auto_pc_1_wr_logic;
architecture STRUCTURE of system_auto_pc_1_wr_logic is
signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^out\ : STD_LOGIC;
signal ram_full_comb : STD_LOGIC;
begin
E(0) <= \^e\(0);
\out\ <= \^out\;
\gwss.wsts\: entity work.system_auto_pc_1_wr_status_flags_ss
port map (
E(0) => \^e\(0),
clk => clk,
full => full,
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0) => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
\out\ => \^out\,
ram_full_comb => ram_full_comb,
wr_en => wr_en
);
wpntr: entity work.system_auto_pc_1_wr_bin_cntr
port map (
E(0) => \^e\(0),
Q(4 downto 0) => Q(4 downto 0),
clk => clk,
\gc0.count_d1_reg[2]\ => \gc0.count_d1_reg[2]\,
\gc0.count_d1_reg[4]\(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0),
\gc0.count_reg[2]\(2 downto 0) => \gc0.count_reg[2]\(2 downto 0),
\gpregsm1.curr_fwft_state_reg[0]\ => \gpregsm1.curr_fwft_state_reg[0]\,
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0) => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(1),
\out\ => \^out\,
ram_empty_fb_i_reg => ram_empty_fb_i_reg,
ram_full_comb => ram_full_comb,
wr_en => wr_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_pc_1_wr_logic_20 is
port (
\out\ : out STD_LOGIC;
full : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
ram_empty_fb_i_reg : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 4 downto 0 );
clk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
wr_en : in STD_LOGIC;
\gpregsm1.curr_fwft_state_reg[0]\ : in STD_LOGIC;
\gc0.count_d1_reg[2]\ : in STD_LOGIC;
\gc0.count_reg[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\gc0.count_d1_reg[4]\ : in STD_LOGIC_VECTOR ( 4 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_pc_1_wr_logic_20 : entity is "wr_logic";
end system_auto_pc_1_wr_logic_20;
architecture STRUCTURE of system_auto_pc_1_wr_logic_20 is
signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^out\ : STD_LOGIC;
signal ram_full_comb : STD_LOGIC;
begin
E(0) <= \^e\(0);
\out\ <= \^out\;
\gwss.wsts\: entity work.system_auto_pc_1_wr_status_flags_ss_28
port map (
E(0) => \^e\(0),
clk => clk,
full => full,
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0) => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
\out\ => \^out\,
ram_full_comb => ram_full_comb,
wr_en => wr_en
);
wpntr: entity work.system_auto_pc_1_wr_bin_cntr_29
port map (
E(0) => \^e\(0),
Q(4 downto 0) => Q(4 downto 0),
clk => clk,
\gc0.count_d1_reg[2]\ => \gc0.count_d1_reg[2]\,
\gc0.count_d1_reg[4]\(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0),
\gc0.count_reg[2]\(2 downto 0) => \gc0.count_reg[2]\(2 downto 0),
\gpregsm1.curr_fwft_state_reg[0]\ => \gpregsm1.curr_fwft_state_reg[0]\,
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0) => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(1),
\out\ => \^out\,
ram_empty_fb_i_reg => ram_empty_fb_i_reg,
ram_full_comb => ram_full_comb,
wr_en => wr_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_pc_1_wr_logic_6 is
port (
\out\ : out STD_LOGIC;
full : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
ram_empty_fb_i_reg : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 4 downto 0 );
clk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
wr_en : in STD_LOGIC;
\gpregsm1.curr_fwft_state_reg[0]\ : in STD_LOGIC;
\gc0.count_d1_reg[2]\ : in STD_LOGIC;
\gc0.count_reg[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\gc0.count_d1_reg[4]\ : in STD_LOGIC_VECTOR ( 4 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_pc_1_wr_logic_6 : entity is "wr_logic";
end system_auto_pc_1_wr_logic_6;
architecture STRUCTURE of system_auto_pc_1_wr_logic_6 is
signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^out\ : STD_LOGIC;
signal ram_full_comb : STD_LOGIC;
begin
E(0) <= \^e\(0);
\out\ <= \^out\;
\gwss.wsts\: entity work.system_auto_pc_1_wr_status_flags_ss_14
port map (
E(0) => \^e\(0),
clk => clk,
full => full,
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0) => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
\out\ => \^out\,
ram_full_comb => ram_full_comb,
wr_en => wr_en
);
wpntr: entity work.system_auto_pc_1_wr_bin_cntr_15
port map (
E(0) => \^e\(0),
Q(4 downto 0) => Q(4 downto 0),
clk => clk,
\gc0.count_d1_reg[2]\ => \gc0.count_d1_reg[2]\,
\gc0.count_d1_reg[4]\(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0),
\gc0.count_reg[2]\(2 downto 0) => \gc0.count_reg[2]\(2 downto 0),
\gpregsm1.curr_fwft_state_reg[0]\ => \gpregsm1.curr_fwft_state_reg[0]\,
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0) => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(1),
\out\ => \^out\,
ram_empty_fb_i_reg => ram_empty_fb_i_reg,
ram_full_comb => ram_full_comb,
wr_en => wr_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_pc_1_fifo_generator_ramfifo is
port (
empty : out STD_LOGIC;
full : out STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 5 downto 0 );
clk : in STD_LOGIC;
rst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 5 downto 0 );
rd_en : in STD_LOGIC;
wr_en : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_pc_1_fifo_generator_ramfifo : entity is "fifo_generator_ramfifo";
end system_auto_pc_1_fifo_generator_ramfifo;
architecture STRUCTURE of system_auto_pc_1_fifo_generator_ramfifo is
signal \gntv_or_sync_fifo.gl0.rd_n_12\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.rd_n_4\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.rd_n_6\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.wr_n_0\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.wr_n_3\ : STD_LOGIC;
signal p_0_out_0 : STD_LOGIC_VECTOR ( 4 downto 0 );
signal p_11_out : STD_LOGIC_VECTOR ( 4 downto 0 );
signal p_17_out : STD_LOGIC;
signal ram_rd_en_i : STD_LOGIC;
signal rd_pntr_plus1 : STD_LOGIC_VECTOR ( 2 downto 0 );
signal rd_rst_i : STD_LOGIC_VECTOR ( 2 downto 0 );
signal rst_full_ff_i : STD_LOGIC;
signal wr_rst_i : STD_LOGIC_VECTOR ( 1 to 1 );
begin
\gntv_or_sync_fifo.gl0.rd\: entity work.system_auto_pc_1_rd_logic_5
port map (
E(0) => ram_rd_en_i,
Q(2 downto 0) => rd_pntr_plus1(2 downto 0),
clk => clk,
empty => empty,
\gcc0.gc0.count_d1_reg[2]\ => \gntv_or_sync_fifo.gl0.wr_n_3\,
\gcc0.gc0.count_d1_reg[4]\(4 downto 0) => p_11_out(4 downto 0),
\goreg_dm.dout_i_reg[5]\(0) => \gntv_or_sync_fifo.gl0.rd_n_6\,
\gpr1.dout_i_reg[1]\(4 downto 0) => p_0_out_0(4 downto 0),
\out\(1) => rd_rst_i(2),
\out\(0) => rd_rst_i(0),
ram_empty_fb_i_reg => \gntv_or_sync_fifo.gl0.rd_n_4\,
ram_full_fb_i_reg => \gntv_or_sync_fifo.gl0.rd_n_12\,
ram_full_fb_i_reg_0 => \gntv_or_sync_fifo.gl0.wr_n_0\,
rd_en => rd_en,
wr_en => wr_en
);
\gntv_or_sync_fifo.gl0.wr\: entity work.system_auto_pc_1_wr_logic_6
port map (
E(0) => p_17_out,
Q(4 downto 0) => p_11_out(4 downto 0),
clk => clk,
full => full,
\gc0.count_d1_reg[2]\ => \gntv_or_sync_fifo.gl0.rd_n_4\,
\gc0.count_d1_reg[4]\(4 downto 0) => p_0_out_0(4 downto 0),
\gc0.count_reg[2]\(2 downto 0) => rd_pntr_plus1(2 downto 0),
\gpregsm1.curr_fwft_state_reg[0]\ => \gntv_or_sync_fifo.gl0.rd_n_12\,
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(1) => wr_rst_i(1),
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0) => rst_full_ff_i,
\out\ => \gntv_or_sync_fifo.gl0.wr_n_0\,
ram_empty_fb_i_reg => \gntv_or_sync_fifo.gl0.wr_n_3\,
wr_en => wr_en
);
\gntv_or_sync_fifo.mem\: entity work.system_auto_pc_1_memory
port map (
E(0) => \gntv_or_sync_fifo.gl0.rd_n_6\,
EN => p_17_out,
I54(4 downto 0) => p_11_out(4 downto 0),
clk => clk,
din(5 downto 0) => din(5 downto 0),
dout(5 downto 0) => dout(5 downto 0),
\gc0.count_d1_reg[4]\(4 downto 0) => p_0_out_0(4 downto 0),
\gpregsm1.curr_fwft_state_reg[1]\(0) => ram_rd_en_i
);
rstblk: entity work.system_auto_pc_1_reset_blk_ramfifo_7
port map (
clk => clk,
\gc0.count_reg[1]\(1) => rd_rst_i(2),
\gc0.count_reg[1]\(0) => rd_rst_i(0),
\out\(1) => wr_rst_i(1),
\out\(0) => rst_full_ff_i,
rst => rst
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_auto_pc_1_fifo_generator_ramfifo__parameterized0\ is
port (
empty : out STD_LOGIC;
full : out STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 4 downto 0 );
clk : in STD_LOGIC;
rst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 4 downto 0 );
rd_en : in STD_LOGIC;
wr_en : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_auto_pc_1_fifo_generator_ramfifo__parameterized0\ : entity is "fifo_generator_ramfifo";
end \system_auto_pc_1_fifo_generator_ramfifo__parameterized0\;
architecture STRUCTURE of \system_auto_pc_1_fifo_generator_ramfifo__parameterized0\ is
signal \gntv_or_sync_fifo.gl0.rd_n_12\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.rd_n_4\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.rd_n_6\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.wr_n_0\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.wr_n_3\ : STD_LOGIC;
signal p_0_out_0 : STD_LOGIC_VECTOR ( 4 downto 0 );
signal p_11_out : STD_LOGIC_VECTOR ( 4 downto 0 );
signal p_17_out : STD_LOGIC;
signal ram_rd_en_i : STD_LOGIC;
signal rd_pntr_plus1 : STD_LOGIC_VECTOR ( 2 downto 0 );
signal rd_rst_i : STD_LOGIC_VECTOR ( 2 downto 0 );
signal rst_full_ff_i : STD_LOGIC;
signal wr_rst_i : STD_LOGIC_VECTOR ( 1 to 1 );
begin
\gntv_or_sync_fifo.gl0.rd\: entity work.system_auto_pc_1_rd_logic
port map (
E(0) => ram_rd_en_i,
Q(2 downto 0) => rd_pntr_plus1(2 downto 0),
clk => clk,
empty => empty,
\gcc0.gc0.count_d1_reg[2]\ => \gntv_or_sync_fifo.gl0.wr_n_3\,
\gcc0.gc0.count_d1_reg[4]\(4 downto 0) => p_11_out(4 downto 0),
\goreg_dm.dout_i_reg[4]\(0) => \gntv_or_sync_fifo.gl0.rd_n_6\,
\gpr1.dout_i_reg[1]\(4 downto 0) => p_0_out_0(4 downto 0),
\out\(1) => rd_rst_i(2),
\out\(0) => rd_rst_i(0),
ram_empty_fb_i_reg => \gntv_or_sync_fifo.gl0.rd_n_4\,
ram_full_fb_i_reg => \gntv_or_sync_fifo.gl0.rd_n_12\,
ram_full_fb_i_reg_0 => \gntv_or_sync_fifo.gl0.wr_n_0\,
rd_en => rd_en,
wr_en => wr_en
);
\gntv_or_sync_fifo.gl0.wr\: entity work.system_auto_pc_1_wr_logic
port map (
E(0) => p_17_out,
Q(4 downto 0) => p_11_out(4 downto 0),
clk => clk,
full => full,
\gc0.count_d1_reg[2]\ => \gntv_or_sync_fifo.gl0.rd_n_4\,
\gc0.count_d1_reg[4]\(4 downto 0) => p_0_out_0(4 downto 0),
\gc0.count_reg[2]\(2 downto 0) => rd_pntr_plus1(2 downto 0),
\gpregsm1.curr_fwft_state_reg[0]\ => \gntv_or_sync_fifo.gl0.rd_n_12\,
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(1) => wr_rst_i(1),
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0) => rst_full_ff_i,
\out\ => \gntv_or_sync_fifo.gl0.wr_n_0\,
ram_empty_fb_i_reg => \gntv_or_sync_fifo.gl0.wr_n_3\,
wr_en => wr_en
);
\gntv_or_sync_fifo.mem\: entity work.\system_auto_pc_1_memory__parameterized0\
port map (
E(0) => \gntv_or_sync_fifo.gl0.rd_n_6\,
EN => p_17_out,
I55(4 downto 0) => p_11_out(4 downto 0),
clk => clk,
din(4 downto 0) => din(4 downto 0),
dout(4 downto 0) => dout(4 downto 0),
\gc0.count_d1_reg[4]\(4 downto 0) => p_0_out_0(4 downto 0),
\gpregsm1.curr_fwft_state_reg[1]\(0) => ram_rd_en_i
);
rstblk: entity work.system_auto_pc_1_reset_blk_ramfifo
port map (
clk => clk,
\gc0.count_reg[1]\(1) => rd_rst_i(2),
\gc0.count_reg[1]\(0) => rd_rst_i(0),
\out\(1) => wr_rst_i(1),
\out\(0) => rst_full_ff_i,
rst => rst
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_auto_pc_1_fifo_generator_ramfifo__parameterized1\ is
port (
empty : out STD_LOGIC;
full : out STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 0 to 0 );
clk : in STD_LOGIC;
rst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 0 to 0 );
rd_en : in STD_LOGIC;
wr_en : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_auto_pc_1_fifo_generator_ramfifo__parameterized1\ : entity is "fifo_generator_ramfifo";
end \system_auto_pc_1_fifo_generator_ramfifo__parameterized1\;
architecture STRUCTURE of \system_auto_pc_1_fifo_generator_ramfifo__parameterized1\ is
signal dout_i : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.rd_n_0\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.rd_n_13\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.rd_n_3\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.rd_n_7\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.wr_n_0\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.wr_n_3\ : STD_LOGIC;
signal \gr1.gr1_int.rfwft/p_0_in\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal p_0_out : STD_LOGIC;
signal p_0_out_0 : STD_LOGIC_VECTOR ( 4 downto 0 );
signal p_11_out : STD_LOGIC_VECTOR ( 4 downto 0 );
signal p_17_out : STD_LOGIC;
signal rd_pntr_plus1 : STD_LOGIC_VECTOR ( 2 downto 0 );
signal rd_rst_i : STD_LOGIC_VECTOR ( 2 downto 0 );
signal rst_full_ff_i : STD_LOGIC;
signal wr_rst_i : STD_LOGIC_VECTOR ( 1 to 1 );
begin
\gntv_or_sync_fifo.gl0.rd\: entity work.system_auto_pc_1_rd_logic_19
port map (
AR(0) => rd_rst_i(2),
Q(2 downto 0) => rd_pntr_plus1(2 downto 0),
clk => clk,
dout_i => dout_i,
empty => empty,
\gcc0.gc0.count_d1_reg[2]\ => \gntv_or_sync_fifo.gl0.wr_n_3\,
\gcc0.gc0.count_d1_reg[4]\(4 downto 0) => p_11_out(4 downto 0),
\gpr1.dout_i_reg[0]\ => \gntv_or_sync_fifo.gl0.rd_n_3\,
\gpr1.dout_i_reg[0]_0\(4 downto 0) => p_0_out_0(4 downto 0),
\out\(1) => \gntv_or_sync_fifo.gl0.rd_n_0\,
\out\(0) => \gr1.gr1_int.rfwft/p_0_in\(0),
p_0_out => p_0_out,
ram_empty_fb_i_reg => \gntv_or_sync_fifo.gl0.rd_n_7\,
ram_full_fb_i_reg => \gntv_or_sync_fifo.gl0.rd_n_13\,
ram_full_fb_i_reg_0 => \gntv_or_sync_fifo.gl0.wr_n_0\,
rd_en => rd_en,
wr_en => wr_en
);
\gntv_or_sync_fifo.gl0.wr\: entity work.system_auto_pc_1_wr_logic_20
port map (
E(0) => p_17_out,
Q(4 downto 0) => p_11_out(4 downto 0),
clk => clk,
full => full,
\gc0.count_d1_reg[2]\ => \gntv_or_sync_fifo.gl0.rd_n_7\,
\gc0.count_d1_reg[4]\(4 downto 0) => p_0_out_0(4 downto 0),
\gc0.count_reg[2]\(2 downto 0) => rd_pntr_plus1(2 downto 0),
\gpregsm1.curr_fwft_state_reg[0]\ => \gntv_or_sync_fifo.gl0.rd_n_13\,
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(1) => wr_rst_i(1),
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0) => rst_full_ff_i,
\out\ => \gntv_or_sync_fifo.gl0.wr_n_0\,
ram_empty_fb_i_reg => \gntv_or_sync_fifo.gl0.wr_n_3\,
wr_en => wr_en
);
\gntv_or_sync_fifo.mem\: entity work.\system_auto_pc_1_memory__parameterized1\
port map (
E(0) => p_17_out,
Q(4 downto 0) => p_11_out(4 downto 0),
clk => clk,
din(0) => din(0),
dout(0) => dout(0),
dout_i => dout_i,
\gc0.count_d1_reg[4]\(4 downto 0) => p_0_out_0(4 downto 0),
\gpregsm1.curr_fwft_state_reg[1]\ => \gntv_or_sync_fifo.gl0.rd_n_3\,
\gpregsm1.curr_fwft_state_reg[1]_0\(1) => \gntv_or_sync_fifo.gl0.rd_n_0\,
\gpregsm1.curr_fwft_state_reg[1]_0\(0) => \gr1.gr1_int.rfwft/p_0_in\(0),
\out\(0) => rd_rst_i(0),
p_0_out => p_0_out,
rd_en => rd_en
);
rstblk: entity work.system_auto_pc_1_reset_blk_ramfifo_21
port map (
clk => clk,
\gc0.count_reg[1]\(1) => rd_rst_i(2),
\gc0.count_reg[1]\(0) => rd_rst_i(0),
\out\(1) => wr_rst_i(1),
\out\(0) => rst_full_ff_i,
rst => rst
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_pc_1_fifo_generator_top is
port (
empty : out STD_LOGIC;
full : out STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 5 downto 0 );
clk : in STD_LOGIC;
rst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 5 downto 0 );
rd_en : in STD_LOGIC;
wr_en : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_pc_1_fifo_generator_top : entity is "fifo_generator_top";
end system_auto_pc_1_fifo_generator_top;
architecture STRUCTURE of system_auto_pc_1_fifo_generator_top is
begin
\grf.rf\: entity work.system_auto_pc_1_fifo_generator_ramfifo
port map (
clk => clk,
din(5 downto 0) => din(5 downto 0),
dout(5 downto 0) => dout(5 downto 0),
empty => empty,
full => full,
rd_en => rd_en,
rst => rst,
wr_en => wr_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_auto_pc_1_fifo_generator_top__parameterized0\ is
port (
empty : out STD_LOGIC;
full : out STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 4 downto 0 );
clk : in STD_LOGIC;
rst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 4 downto 0 );
rd_en : in STD_LOGIC;
wr_en : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_auto_pc_1_fifo_generator_top__parameterized0\ : entity is "fifo_generator_top";
end \system_auto_pc_1_fifo_generator_top__parameterized0\;
architecture STRUCTURE of \system_auto_pc_1_fifo_generator_top__parameterized0\ is
begin
\grf.rf\: entity work.\system_auto_pc_1_fifo_generator_ramfifo__parameterized0\
port map (
clk => clk,
din(4 downto 0) => din(4 downto 0),
dout(4 downto 0) => dout(4 downto 0),
empty => empty,
full => full,
rd_en => rd_en,
rst => rst,
wr_en => wr_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_auto_pc_1_fifo_generator_top__parameterized1\ is
port (
empty : out STD_LOGIC;
full : out STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 0 to 0 );
clk : in STD_LOGIC;
rst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 0 to 0 );
rd_en : in STD_LOGIC;
wr_en : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_auto_pc_1_fifo_generator_top__parameterized1\ : entity is "fifo_generator_top";
end \system_auto_pc_1_fifo_generator_top__parameterized1\;
architecture STRUCTURE of \system_auto_pc_1_fifo_generator_top__parameterized1\ is
begin
\grf.rf\: entity work.\system_auto_pc_1_fifo_generator_ramfifo__parameterized1\
port map (
clk => clk,
din(0) => din(0),
dout(0) => dout(0),
empty => empty,
full => full,
rd_en => rd_en,
rst => rst,
wr_en => wr_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_pc_1_fifo_generator_v13_1_3_synth is
port (
empty : out STD_LOGIC;
full : out STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 5 downto 0 );
clk : in STD_LOGIC;
rst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 5 downto 0 );
rd_en : in STD_LOGIC;
wr_en : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_pc_1_fifo_generator_v13_1_3_synth : entity is "fifo_generator_v13_1_3_synth";
end system_auto_pc_1_fifo_generator_v13_1_3_synth;
architecture STRUCTURE of system_auto_pc_1_fifo_generator_v13_1_3_synth is
begin
\gconvfifo.rf\: entity work.system_auto_pc_1_fifo_generator_top
port map (
clk => clk,
din(5 downto 0) => din(5 downto 0),
dout(5 downto 0) => dout(5 downto 0),
empty => empty,
full => full,
rd_en => rd_en,
rst => rst,
wr_en => wr_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_auto_pc_1_fifo_generator_v13_1_3_synth__parameterized0\ is
port (
empty : out STD_LOGIC;
full : out STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 4 downto 0 );
clk : in STD_LOGIC;
rst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 4 downto 0 );
rd_en : in STD_LOGIC;
wr_en : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_auto_pc_1_fifo_generator_v13_1_3_synth__parameterized0\ : entity is "fifo_generator_v13_1_3_synth";
end \system_auto_pc_1_fifo_generator_v13_1_3_synth__parameterized0\;
architecture STRUCTURE of \system_auto_pc_1_fifo_generator_v13_1_3_synth__parameterized0\ is
begin
\gconvfifo.rf\: entity work.\system_auto_pc_1_fifo_generator_top__parameterized0\
port map (
clk => clk,
din(4 downto 0) => din(4 downto 0),
dout(4 downto 0) => dout(4 downto 0),
empty => empty,
full => full,
rd_en => rd_en,
rst => rst,
wr_en => wr_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_auto_pc_1_fifo_generator_v13_1_3_synth__parameterized1\ is
port (
empty : out STD_LOGIC;
full : out STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 0 to 0 );
clk : in STD_LOGIC;
rst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 0 to 0 );
rd_en : in STD_LOGIC;
wr_en : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_auto_pc_1_fifo_generator_v13_1_3_synth__parameterized1\ : entity is "fifo_generator_v13_1_3_synth";
end \system_auto_pc_1_fifo_generator_v13_1_3_synth__parameterized1\;
architecture STRUCTURE of \system_auto_pc_1_fifo_generator_v13_1_3_synth__parameterized1\ is
begin
\gconvfifo.rf\: entity work.\system_auto_pc_1_fifo_generator_top__parameterized1\
port map (
clk => clk,
din(0) => din(0),
dout(0) => dout(0),
empty => empty,
full => full,
rd_en => rd_en,
rst => rst,
wr_en => wr_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_pc_1_fifo_generator_v13_1_3 is
port (
backup : in STD_LOGIC;
backup_marker : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
srst : in STD_LOGIC;
wr_clk : in STD_LOGIC;
wr_rst : in STD_LOGIC;
rd_clk : in STD_LOGIC;
rd_rst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 5 downto 0 );
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
prog_empty_thresh : in STD_LOGIC_VECTOR ( 4 downto 0 );
prog_empty_thresh_assert : in STD_LOGIC_VECTOR ( 4 downto 0 );
prog_empty_thresh_negate : in STD_LOGIC_VECTOR ( 4 downto 0 );
prog_full_thresh : in STD_LOGIC_VECTOR ( 4 downto 0 );
prog_full_thresh_assert : in STD_LOGIC_VECTOR ( 4 downto 0 );
prog_full_thresh_negate : in STD_LOGIC_VECTOR ( 4 downto 0 );
int_clk : in STD_LOGIC;
injectdbiterr : in STD_LOGIC;
injectsbiterr : in STD_LOGIC;
sleep : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 5 downto 0 );
full : out STD_LOGIC;
almost_full : out STD_LOGIC;
wr_ack : out STD_LOGIC;
overflow : out STD_LOGIC;
empty : out STD_LOGIC;
almost_empty : out STD_LOGIC;
valid : out STD_LOGIC;
underflow : out STD_LOGIC;
data_count : out STD_LOGIC_VECTOR ( 5 downto 0 );
rd_data_count : out STD_LOGIC_VECTOR ( 5 downto 0 );
wr_data_count : out STD_LOGIC_VECTOR ( 5 downto 0 );
prog_full : out STD_LOGIC;
prog_empty : out STD_LOGIC;
sbiterr : out STD_LOGIC;
dbiterr : out STD_LOGIC;
wr_rst_busy : out STD_LOGIC;
rd_rst_busy : out STD_LOGIC;
m_aclk : in STD_LOGIC;
s_aclk : in STD_LOGIC;
s_aresetn : in STD_LOGIC;
m_aclk_en : in STD_LOGIC;
s_aclk_en : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_buser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
m_axi_awid : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wid : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_wlast : out STD_LOGIC;
m_axi_wuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bid : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_buser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_aruser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_ruser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_arid : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_aruser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_ruser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC;
s_axis_tvalid : in STD_LOGIC;
s_axis_tready : out STD_LOGIC;
s_axis_tdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
s_axis_tstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axis_tkeep : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axis_tlast : in STD_LOGIC;
s_axis_tid : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axis_tdest : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axis_tuser : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axis_tvalid : out STD_LOGIC;
m_axis_tready : in STD_LOGIC;
m_axis_tdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
m_axis_tstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axis_tkeep : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axis_tlast : out STD_LOGIC;
m_axis_tid : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axis_tdest : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axis_tuser : out STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_injectsbiterr : in STD_LOGIC;
axi_aw_injectdbiterr : in STD_LOGIC;
axi_aw_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_sbiterr : out STD_LOGIC;
axi_aw_dbiterr : out STD_LOGIC;
axi_aw_overflow : out STD_LOGIC;
axi_aw_underflow : out STD_LOGIC;
axi_aw_prog_full : out STD_LOGIC;
axi_aw_prog_empty : out STD_LOGIC;
axi_w_injectsbiterr : in STD_LOGIC;
axi_w_injectdbiterr : in STD_LOGIC;
axi_w_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_w_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_w_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_w_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_w_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_w_sbiterr : out STD_LOGIC;
axi_w_dbiterr : out STD_LOGIC;
axi_w_overflow : out STD_LOGIC;
axi_w_underflow : out STD_LOGIC;
axi_w_prog_full : out STD_LOGIC;
axi_w_prog_empty : out STD_LOGIC;
axi_b_injectsbiterr : in STD_LOGIC;
axi_b_injectdbiterr : in STD_LOGIC;
axi_b_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_b_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_b_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_sbiterr : out STD_LOGIC;
axi_b_dbiterr : out STD_LOGIC;
axi_b_overflow : out STD_LOGIC;
axi_b_underflow : out STD_LOGIC;
axi_b_prog_full : out STD_LOGIC;
axi_b_prog_empty : out STD_LOGIC;
axi_ar_injectsbiterr : in STD_LOGIC;
axi_ar_injectdbiterr : in STD_LOGIC;
axi_ar_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_ar_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_ar_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_sbiterr : out STD_LOGIC;
axi_ar_dbiterr : out STD_LOGIC;
axi_ar_overflow : out STD_LOGIC;
axi_ar_underflow : out STD_LOGIC;
axi_ar_prog_full : out STD_LOGIC;
axi_ar_prog_empty : out STD_LOGIC;
axi_r_injectsbiterr : in STD_LOGIC;
axi_r_injectdbiterr : in STD_LOGIC;
axi_r_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_r_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_r_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_r_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_r_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_r_sbiterr : out STD_LOGIC;
axi_r_dbiterr : out STD_LOGIC;
axi_r_overflow : out STD_LOGIC;
axi_r_underflow : out STD_LOGIC;
axi_r_prog_full : out STD_LOGIC;
axi_r_prog_empty : out STD_LOGIC;
axis_injectsbiterr : in STD_LOGIC;
axis_injectdbiterr : in STD_LOGIC;
axis_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axis_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axis_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_sbiterr : out STD_LOGIC;
axis_dbiterr : out STD_LOGIC;
axis_overflow : out STD_LOGIC;
axis_underflow : out STD_LOGIC;
axis_prog_full : out STD_LOGIC;
axis_prog_empty : out STD_LOGIC
);
attribute C_ADD_NGC_CONSTRAINT : integer;
attribute C_ADD_NGC_CONSTRAINT of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_APPLICATION_TYPE_AXIS : integer;
attribute C_APPLICATION_TYPE_AXIS of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_APPLICATION_TYPE_RACH : integer;
attribute C_APPLICATION_TYPE_RACH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_APPLICATION_TYPE_RDCH : integer;
attribute C_APPLICATION_TYPE_RDCH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_APPLICATION_TYPE_WACH : integer;
attribute C_APPLICATION_TYPE_WACH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_APPLICATION_TYPE_WDCH : integer;
attribute C_APPLICATION_TYPE_WDCH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_APPLICATION_TYPE_WRCH : integer;
attribute C_APPLICATION_TYPE_WRCH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_AXIS_TDATA_WIDTH : integer;
attribute C_AXIS_TDATA_WIDTH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 64;
attribute C_AXIS_TDEST_WIDTH : integer;
attribute C_AXIS_TDEST_WIDTH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 4;
attribute C_AXIS_TID_WIDTH : integer;
attribute C_AXIS_TID_WIDTH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 8;
attribute C_AXIS_TKEEP_WIDTH : integer;
attribute C_AXIS_TKEEP_WIDTH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 4;
attribute C_AXIS_TSTRB_WIDTH : integer;
attribute C_AXIS_TSTRB_WIDTH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 4;
attribute C_AXIS_TUSER_WIDTH : integer;
attribute C_AXIS_TUSER_WIDTH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 4;
attribute C_AXIS_TYPE : integer;
attribute C_AXIS_TYPE of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 64;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 4;
attribute C_AXI_LEN_WIDTH : integer;
attribute C_AXI_LEN_WIDTH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 8;
attribute C_AXI_LOCK_WIDTH : integer;
attribute C_AXI_LOCK_WIDTH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 2;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 1;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 1;
attribute C_COMMON_CLOCK : integer;
attribute C_COMMON_CLOCK of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 1;
attribute C_COUNT_TYPE : integer;
attribute C_COUNT_TYPE of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_DATA_COUNT_WIDTH : integer;
attribute C_DATA_COUNT_WIDTH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 6;
attribute C_DEFAULT_VALUE : string;
attribute C_DEFAULT_VALUE of system_auto_pc_1_fifo_generator_v13_1_3 : entity is "BlankString";
attribute C_DIN_WIDTH : integer;
attribute C_DIN_WIDTH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 6;
attribute C_DIN_WIDTH_AXIS : integer;
attribute C_DIN_WIDTH_AXIS of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 1;
attribute C_DIN_WIDTH_RACH : integer;
attribute C_DIN_WIDTH_RACH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 32;
attribute C_DIN_WIDTH_RDCH : integer;
attribute C_DIN_WIDTH_RDCH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 64;
attribute C_DIN_WIDTH_WACH : integer;
attribute C_DIN_WIDTH_WACH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 32;
attribute C_DIN_WIDTH_WDCH : integer;
attribute C_DIN_WIDTH_WDCH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 64;
attribute C_DIN_WIDTH_WRCH : integer;
attribute C_DIN_WIDTH_WRCH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 2;
attribute C_DOUT_RST_VAL : string;
attribute C_DOUT_RST_VAL of system_auto_pc_1_fifo_generator_v13_1_3 : entity is "0";
attribute C_DOUT_WIDTH : integer;
attribute C_DOUT_WIDTH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 6;
attribute C_ENABLE_RLOCS : integer;
attribute C_ENABLE_RLOCS of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_ENABLE_RST_SYNC : integer;
attribute C_ENABLE_RST_SYNC of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 1;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_ERROR_INJECTION_TYPE : integer;
attribute C_ERROR_INJECTION_TYPE of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_AXIS : integer;
attribute C_ERROR_INJECTION_TYPE_AXIS of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_RACH : integer;
attribute C_ERROR_INJECTION_TYPE_RACH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_RDCH : integer;
attribute C_ERROR_INJECTION_TYPE_RDCH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WACH : integer;
attribute C_ERROR_INJECTION_TYPE_WACH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WDCH : integer;
attribute C_ERROR_INJECTION_TYPE_WDCH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WRCH : integer;
attribute C_ERROR_INJECTION_TYPE_WRCH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of system_auto_pc_1_fifo_generator_v13_1_3 : entity is "zynq";
attribute C_FULL_FLAGS_RST_VAL : integer;
attribute C_FULL_FLAGS_RST_VAL of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_ALMOST_EMPTY : integer;
attribute C_HAS_ALMOST_EMPTY of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_ALMOST_FULL : integer;
attribute C_HAS_ALMOST_FULL of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_AXIS_TDATA : integer;
attribute C_HAS_AXIS_TDATA of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_AXIS_TDEST : integer;
attribute C_HAS_AXIS_TDEST of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_AXIS_TID : integer;
attribute C_HAS_AXIS_TID of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_AXIS_TKEEP : integer;
attribute C_HAS_AXIS_TKEEP of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_AXIS_TLAST : integer;
attribute C_HAS_AXIS_TLAST of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_AXIS_TREADY : integer;
attribute C_HAS_AXIS_TREADY of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 1;
attribute C_HAS_AXIS_TSTRB : integer;
attribute C_HAS_AXIS_TSTRB of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_AXIS_TUSER : integer;
attribute C_HAS_AXIS_TUSER of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_AXI_ARUSER : integer;
attribute C_HAS_AXI_ARUSER of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_AXI_AWUSER : integer;
attribute C_HAS_AXI_AWUSER of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_AXI_BUSER : integer;
attribute C_HAS_AXI_BUSER of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_AXI_RD_CHANNEL : integer;
attribute C_HAS_AXI_RD_CHANNEL of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_AXI_RUSER : integer;
attribute C_HAS_AXI_RUSER of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_AXI_WR_CHANNEL : integer;
attribute C_HAS_AXI_WR_CHANNEL of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_AXI_WUSER : integer;
attribute C_HAS_AXI_WUSER of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_BACKUP : integer;
attribute C_HAS_BACKUP of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_DATA_COUNT : integer;
attribute C_HAS_DATA_COUNT of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_DATA_COUNTS_AXIS : integer;
attribute C_HAS_DATA_COUNTS_AXIS of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_DATA_COUNTS_RACH : integer;
attribute C_HAS_DATA_COUNTS_RACH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_DATA_COUNTS_RDCH : integer;
attribute C_HAS_DATA_COUNTS_RDCH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_DATA_COUNTS_WACH : integer;
attribute C_HAS_DATA_COUNTS_WACH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_DATA_COUNTS_WDCH : integer;
attribute C_HAS_DATA_COUNTS_WDCH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_DATA_COUNTS_WRCH : integer;
attribute C_HAS_DATA_COUNTS_WRCH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_INT_CLK : integer;
attribute C_HAS_INT_CLK of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_MASTER_CE : integer;
attribute C_HAS_MASTER_CE of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_MEMINIT_FILE : integer;
attribute C_HAS_MEMINIT_FILE of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_OVERFLOW : integer;
attribute C_HAS_OVERFLOW of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_PROG_FLAGS_AXIS : integer;
attribute C_HAS_PROG_FLAGS_AXIS of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_PROG_FLAGS_RACH : integer;
attribute C_HAS_PROG_FLAGS_RACH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_PROG_FLAGS_RDCH : integer;
attribute C_HAS_PROG_FLAGS_RDCH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_PROG_FLAGS_WACH : integer;
attribute C_HAS_PROG_FLAGS_WACH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_PROG_FLAGS_WDCH : integer;
attribute C_HAS_PROG_FLAGS_WDCH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_PROG_FLAGS_WRCH : integer;
attribute C_HAS_PROG_FLAGS_WRCH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_RD_DATA_COUNT : integer;
attribute C_HAS_RD_DATA_COUNT of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_RD_RST : integer;
attribute C_HAS_RD_RST of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_RST : integer;
attribute C_HAS_RST of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 1;
attribute C_HAS_SLAVE_CE : integer;
attribute C_HAS_SLAVE_CE of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_SRST : integer;
attribute C_HAS_SRST of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_UNDERFLOW : integer;
attribute C_HAS_UNDERFLOW of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_VALID : integer;
attribute C_HAS_VALID of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_WR_ACK : integer;
attribute C_HAS_WR_ACK of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_WR_DATA_COUNT : integer;
attribute C_HAS_WR_DATA_COUNT of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_WR_RST : integer;
attribute C_HAS_WR_RST of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_IMPLEMENTATION_TYPE : integer;
attribute C_IMPLEMENTATION_TYPE of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_IMPLEMENTATION_TYPE_AXIS : integer;
attribute C_IMPLEMENTATION_TYPE_AXIS of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_RACH : integer;
attribute C_IMPLEMENTATION_TYPE_RACH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_RDCH : integer;
attribute C_IMPLEMENTATION_TYPE_RDCH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_WACH : integer;
attribute C_IMPLEMENTATION_TYPE_WACH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_WDCH : integer;
attribute C_IMPLEMENTATION_TYPE_WDCH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_WRCH : integer;
attribute C_IMPLEMENTATION_TYPE_WRCH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 1;
attribute C_INIT_WR_PNTR_VAL : integer;
attribute C_INIT_WR_PNTR_VAL of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_MEMORY_TYPE : integer;
attribute C_MEMORY_TYPE of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 2;
attribute C_MIF_FILE_NAME : string;
attribute C_MIF_FILE_NAME of system_auto_pc_1_fifo_generator_v13_1_3 : entity is "BlankString";
attribute C_MSGON_VAL : integer;
attribute C_MSGON_VAL of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 1;
attribute C_OPTIMIZATION_MODE : integer;
attribute C_OPTIMIZATION_MODE of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_OVERFLOW_LOW : integer;
attribute C_OVERFLOW_LOW of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_POWER_SAVING_MODE : integer;
attribute C_POWER_SAVING_MODE of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_PRELOAD_LATENCY : integer;
attribute C_PRELOAD_LATENCY of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_PRELOAD_REGS : integer;
attribute C_PRELOAD_REGS of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 1;
attribute C_PRIM_FIFO_TYPE : string;
attribute C_PRIM_FIFO_TYPE of system_auto_pc_1_fifo_generator_v13_1_3 : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_AXIS : string;
attribute C_PRIM_FIFO_TYPE_AXIS of system_auto_pc_1_fifo_generator_v13_1_3 : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_RACH : string;
attribute C_PRIM_FIFO_TYPE_RACH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_RDCH : string;
attribute C_PRIM_FIFO_TYPE_RDCH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_WACH : string;
attribute C_PRIM_FIFO_TYPE_WACH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_WDCH : string;
attribute C_PRIM_FIFO_TYPE_WDCH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_WRCH : string;
attribute C_PRIM_FIFO_TYPE_WRCH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is "512x36";
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 4;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL : integer;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 5;
attribute C_PROG_EMPTY_TYPE : integer;
attribute C_PROG_EMPTY_TYPE of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_PROG_EMPTY_TYPE_AXIS : integer;
attribute C_PROG_EMPTY_TYPE_AXIS of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_PROG_EMPTY_TYPE_RACH : integer;
attribute C_PROG_EMPTY_TYPE_RACH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_PROG_EMPTY_TYPE_RDCH : integer;
attribute C_PROG_EMPTY_TYPE_RDCH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_PROG_EMPTY_TYPE_WACH : integer;
attribute C_PROG_EMPTY_TYPE_WACH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_PROG_EMPTY_TYPE_WDCH : integer;
attribute C_PROG_EMPTY_TYPE_WDCH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_PROG_EMPTY_TYPE_WRCH : integer;
attribute C_PROG_EMPTY_TYPE_WRCH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_PROG_FULL_THRESH_ASSERT_VAL : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 31;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 1023;
attribute C_PROG_FULL_THRESH_NEGATE_VAL : integer;
attribute C_PROG_FULL_THRESH_NEGATE_VAL of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 30;
attribute C_PROG_FULL_TYPE : integer;
attribute C_PROG_FULL_TYPE of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_PROG_FULL_TYPE_AXIS : integer;
attribute C_PROG_FULL_TYPE_AXIS of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_PROG_FULL_TYPE_RACH : integer;
attribute C_PROG_FULL_TYPE_RACH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_PROG_FULL_TYPE_RDCH : integer;
attribute C_PROG_FULL_TYPE_RDCH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_PROG_FULL_TYPE_WACH : integer;
attribute C_PROG_FULL_TYPE_WACH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_PROG_FULL_TYPE_WDCH : integer;
attribute C_PROG_FULL_TYPE_WDCH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_PROG_FULL_TYPE_WRCH : integer;
attribute C_PROG_FULL_TYPE_WRCH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_RACH_TYPE : integer;
attribute C_RACH_TYPE of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_RDCH_TYPE : integer;
attribute C_RDCH_TYPE of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_RD_DATA_COUNT_WIDTH : integer;
attribute C_RD_DATA_COUNT_WIDTH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 6;
attribute C_RD_DEPTH : integer;
attribute C_RD_DEPTH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 32;
attribute C_RD_FREQ : integer;
attribute C_RD_FREQ of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 1;
attribute C_RD_PNTR_WIDTH : integer;
attribute C_RD_PNTR_WIDTH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 5;
attribute C_REG_SLICE_MODE_AXIS : integer;
attribute C_REG_SLICE_MODE_AXIS of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_REG_SLICE_MODE_RACH : integer;
attribute C_REG_SLICE_MODE_RACH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_REG_SLICE_MODE_RDCH : integer;
attribute C_REG_SLICE_MODE_RDCH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_REG_SLICE_MODE_WACH : integer;
attribute C_REG_SLICE_MODE_WACH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_REG_SLICE_MODE_WDCH : integer;
attribute C_REG_SLICE_MODE_WDCH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_REG_SLICE_MODE_WRCH : integer;
attribute C_REG_SLICE_MODE_WRCH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_SELECT_XPM : integer;
attribute C_SELECT_XPM of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_SYNCHRONIZER_STAGE : integer;
attribute C_SYNCHRONIZER_STAGE of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 3;
attribute C_UNDERFLOW_LOW : integer;
attribute C_UNDERFLOW_LOW of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_USE_COMMON_OVERFLOW : integer;
attribute C_USE_COMMON_OVERFLOW of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_USE_COMMON_UNDERFLOW : integer;
attribute C_USE_COMMON_UNDERFLOW of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_USE_DEFAULT_SETTINGS : integer;
attribute C_USE_DEFAULT_SETTINGS of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_USE_DOUT_RST : integer;
attribute C_USE_DOUT_RST of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_USE_ECC_AXIS : integer;
attribute C_USE_ECC_AXIS of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_USE_ECC_RACH : integer;
attribute C_USE_ECC_RACH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_USE_ECC_RDCH : integer;
attribute C_USE_ECC_RDCH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_USE_ECC_WACH : integer;
attribute C_USE_ECC_WACH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_USE_ECC_WDCH : integer;
attribute C_USE_ECC_WDCH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_USE_ECC_WRCH : integer;
attribute C_USE_ECC_WRCH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_USE_EMBEDDED_REG : integer;
attribute C_USE_EMBEDDED_REG of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_USE_FIFO16_FLAGS : integer;
attribute C_USE_FIFO16_FLAGS of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_USE_FWFT_DATA_COUNT : integer;
attribute C_USE_FWFT_DATA_COUNT of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 1;
attribute C_USE_PIPELINE_REG : integer;
attribute C_USE_PIPELINE_REG of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_VALID_LOW : integer;
attribute C_VALID_LOW of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_WACH_TYPE : integer;
attribute C_WACH_TYPE of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_WDCH_TYPE : integer;
attribute C_WDCH_TYPE of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_WRCH_TYPE : integer;
attribute C_WRCH_TYPE of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_WR_ACK_LOW : integer;
attribute C_WR_ACK_LOW of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 0;
attribute C_WR_DATA_COUNT_WIDTH : integer;
attribute C_WR_DATA_COUNT_WIDTH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 6;
attribute C_WR_DEPTH : integer;
attribute C_WR_DEPTH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 32;
attribute C_WR_DEPTH_AXIS : integer;
attribute C_WR_DEPTH_AXIS of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 1024;
attribute C_WR_DEPTH_RACH : integer;
attribute C_WR_DEPTH_RACH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 16;
attribute C_WR_DEPTH_RDCH : integer;
attribute C_WR_DEPTH_RDCH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 1024;
attribute C_WR_DEPTH_WACH : integer;
attribute C_WR_DEPTH_WACH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 16;
attribute C_WR_DEPTH_WDCH : integer;
attribute C_WR_DEPTH_WDCH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 1024;
attribute C_WR_DEPTH_WRCH : integer;
attribute C_WR_DEPTH_WRCH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 16;
attribute C_WR_FREQ : integer;
attribute C_WR_FREQ of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 1;
attribute C_WR_PNTR_WIDTH : integer;
attribute C_WR_PNTR_WIDTH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 5;
attribute C_WR_PNTR_WIDTH_AXIS : integer;
attribute C_WR_PNTR_WIDTH_AXIS of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 10;
attribute C_WR_PNTR_WIDTH_RACH : integer;
attribute C_WR_PNTR_WIDTH_RACH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 4;
attribute C_WR_PNTR_WIDTH_RDCH : integer;
attribute C_WR_PNTR_WIDTH_RDCH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 10;
attribute C_WR_PNTR_WIDTH_WACH : integer;
attribute C_WR_PNTR_WIDTH_WACH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 4;
attribute C_WR_PNTR_WIDTH_WDCH : integer;
attribute C_WR_PNTR_WIDTH_WDCH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 10;
attribute C_WR_PNTR_WIDTH_WRCH : integer;
attribute C_WR_PNTR_WIDTH_WRCH of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 4;
attribute C_WR_RESPONSE_LATENCY : integer;
attribute C_WR_RESPONSE_LATENCY of system_auto_pc_1_fifo_generator_v13_1_3 : entity is 1;
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_pc_1_fifo_generator_v13_1_3 : entity is "fifo_generator_v13_1_3";
end system_auto_pc_1_fifo_generator_v13_1_3;
architecture STRUCTURE of system_auto_pc_1_fifo_generator_v13_1_3 is
signal \<const0>\ : STD_LOGIC;
begin
almost_empty <= \<const0>\;
almost_full <= \<const0>\;
axi_ar_data_count(4) <= \<const0>\;
axi_ar_data_count(3) <= \<const0>\;
axi_ar_data_count(2) <= \<const0>\;
axi_ar_data_count(1) <= \<const0>\;
axi_ar_data_count(0) <= \<const0>\;
axi_ar_dbiterr <= \<const0>\;
axi_ar_overflow <= \<const0>\;
axi_ar_prog_empty <= \<const0>\;
axi_ar_prog_full <= \<const0>\;
axi_ar_rd_data_count(4) <= \<const0>\;
axi_ar_rd_data_count(3) <= \<const0>\;
axi_ar_rd_data_count(2) <= \<const0>\;
axi_ar_rd_data_count(1) <= \<const0>\;
axi_ar_rd_data_count(0) <= \<const0>\;
axi_ar_sbiterr <= \<const0>\;
axi_ar_underflow <= \<const0>\;
axi_ar_wr_data_count(4) <= \<const0>\;
axi_ar_wr_data_count(3) <= \<const0>\;
axi_ar_wr_data_count(2) <= \<const0>\;
axi_ar_wr_data_count(1) <= \<const0>\;
axi_ar_wr_data_count(0) <= \<const0>\;
axi_aw_data_count(4) <= \<const0>\;
axi_aw_data_count(3) <= \<const0>\;
axi_aw_data_count(2) <= \<const0>\;
axi_aw_data_count(1) <= \<const0>\;
axi_aw_data_count(0) <= \<const0>\;
axi_aw_dbiterr <= \<const0>\;
axi_aw_overflow <= \<const0>\;
axi_aw_prog_empty <= \<const0>\;
axi_aw_prog_full <= \<const0>\;
axi_aw_rd_data_count(4) <= \<const0>\;
axi_aw_rd_data_count(3) <= \<const0>\;
axi_aw_rd_data_count(2) <= \<const0>\;
axi_aw_rd_data_count(1) <= \<const0>\;
axi_aw_rd_data_count(0) <= \<const0>\;
axi_aw_sbiterr <= \<const0>\;
axi_aw_underflow <= \<const0>\;
axi_aw_wr_data_count(4) <= \<const0>\;
axi_aw_wr_data_count(3) <= \<const0>\;
axi_aw_wr_data_count(2) <= \<const0>\;
axi_aw_wr_data_count(1) <= \<const0>\;
axi_aw_wr_data_count(0) <= \<const0>\;
axi_b_data_count(4) <= \<const0>\;
axi_b_data_count(3) <= \<const0>\;
axi_b_data_count(2) <= \<const0>\;
axi_b_data_count(1) <= \<const0>\;
axi_b_data_count(0) <= \<const0>\;
axi_b_dbiterr <= \<const0>\;
axi_b_overflow <= \<const0>\;
axi_b_prog_empty <= \<const0>\;
axi_b_prog_full <= \<const0>\;
axi_b_rd_data_count(4) <= \<const0>\;
axi_b_rd_data_count(3) <= \<const0>\;
axi_b_rd_data_count(2) <= \<const0>\;
axi_b_rd_data_count(1) <= \<const0>\;
axi_b_rd_data_count(0) <= \<const0>\;
axi_b_sbiterr <= \<const0>\;
axi_b_underflow <= \<const0>\;
axi_b_wr_data_count(4) <= \<const0>\;
axi_b_wr_data_count(3) <= \<const0>\;
axi_b_wr_data_count(2) <= \<const0>\;
axi_b_wr_data_count(1) <= \<const0>\;
axi_b_wr_data_count(0) <= \<const0>\;
axi_r_data_count(10) <= \<const0>\;
axi_r_data_count(9) <= \<const0>\;
axi_r_data_count(8) <= \<const0>\;
axi_r_data_count(7) <= \<const0>\;
axi_r_data_count(6) <= \<const0>\;
axi_r_data_count(5) <= \<const0>\;
axi_r_data_count(4) <= \<const0>\;
axi_r_data_count(3) <= \<const0>\;
axi_r_data_count(2) <= \<const0>\;
axi_r_data_count(1) <= \<const0>\;
axi_r_data_count(0) <= \<const0>\;
axi_r_dbiterr <= \<const0>\;
axi_r_overflow <= \<const0>\;
axi_r_prog_empty <= \<const0>\;
axi_r_prog_full <= \<const0>\;
axi_r_rd_data_count(10) <= \<const0>\;
axi_r_rd_data_count(9) <= \<const0>\;
axi_r_rd_data_count(8) <= \<const0>\;
axi_r_rd_data_count(7) <= \<const0>\;
axi_r_rd_data_count(6) <= \<const0>\;
axi_r_rd_data_count(5) <= \<const0>\;
axi_r_rd_data_count(4) <= \<const0>\;
axi_r_rd_data_count(3) <= \<const0>\;
axi_r_rd_data_count(2) <= \<const0>\;
axi_r_rd_data_count(1) <= \<const0>\;
axi_r_rd_data_count(0) <= \<const0>\;
axi_r_sbiterr <= \<const0>\;
axi_r_underflow <= \<const0>\;
axi_r_wr_data_count(10) <= \<const0>\;
axi_r_wr_data_count(9) <= \<const0>\;
axi_r_wr_data_count(8) <= \<const0>\;
axi_r_wr_data_count(7) <= \<const0>\;
axi_r_wr_data_count(6) <= \<const0>\;
axi_r_wr_data_count(5) <= \<const0>\;
axi_r_wr_data_count(4) <= \<const0>\;
axi_r_wr_data_count(3) <= \<const0>\;
axi_r_wr_data_count(2) <= \<const0>\;
axi_r_wr_data_count(1) <= \<const0>\;
axi_r_wr_data_count(0) <= \<const0>\;
axi_w_data_count(10) <= \<const0>\;
axi_w_data_count(9) <= \<const0>\;
axi_w_data_count(8) <= \<const0>\;
axi_w_data_count(7) <= \<const0>\;
axi_w_data_count(6) <= \<const0>\;
axi_w_data_count(5) <= \<const0>\;
axi_w_data_count(4) <= \<const0>\;
axi_w_data_count(3) <= \<const0>\;
axi_w_data_count(2) <= \<const0>\;
axi_w_data_count(1) <= \<const0>\;
axi_w_data_count(0) <= \<const0>\;
axi_w_dbiterr <= \<const0>\;
axi_w_overflow <= \<const0>\;
axi_w_prog_empty <= \<const0>\;
axi_w_prog_full <= \<const0>\;
axi_w_rd_data_count(10) <= \<const0>\;
axi_w_rd_data_count(9) <= \<const0>\;
axi_w_rd_data_count(8) <= \<const0>\;
axi_w_rd_data_count(7) <= \<const0>\;
axi_w_rd_data_count(6) <= \<const0>\;
axi_w_rd_data_count(5) <= \<const0>\;
axi_w_rd_data_count(4) <= \<const0>\;
axi_w_rd_data_count(3) <= \<const0>\;
axi_w_rd_data_count(2) <= \<const0>\;
axi_w_rd_data_count(1) <= \<const0>\;
axi_w_rd_data_count(0) <= \<const0>\;
axi_w_sbiterr <= \<const0>\;
axi_w_underflow <= \<const0>\;
axi_w_wr_data_count(10) <= \<const0>\;
axi_w_wr_data_count(9) <= \<const0>\;
axi_w_wr_data_count(8) <= \<const0>\;
axi_w_wr_data_count(7) <= \<const0>\;
axi_w_wr_data_count(6) <= \<const0>\;
axi_w_wr_data_count(5) <= \<const0>\;
axi_w_wr_data_count(4) <= \<const0>\;
axi_w_wr_data_count(3) <= \<const0>\;
axi_w_wr_data_count(2) <= \<const0>\;
axi_w_wr_data_count(1) <= \<const0>\;
axi_w_wr_data_count(0) <= \<const0>\;
axis_data_count(10) <= \<const0>\;
axis_data_count(9) <= \<const0>\;
axis_data_count(8) <= \<const0>\;
axis_data_count(7) <= \<const0>\;
axis_data_count(6) <= \<const0>\;
axis_data_count(5) <= \<const0>\;
axis_data_count(4) <= \<const0>\;
axis_data_count(3) <= \<const0>\;
axis_data_count(2) <= \<const0>\;
axis_data_count(1) <= \<const0>\;
axis_data_count(0) <= \<const0>\;
axis_dbiterr <= \<const0>\;
axis_overflow <= \<const0>\;
axis_prog_empty <= \<const0>\;
axis_prog_full <= \<const0>\;
axis_rd_data_count(10) <= \<const0>\;
axis_rd_data_count(9) <= \<const0>\;
axis_rd_data_count(8) <= \<const0>\;
axis_rd_data_count(7) <= \<const0>\;
axis_rd_data_count(6) <= \<const0>\;
axis_rd_data_count(5) <= \<const0>\;
axis_rd_data_count(4) <= \<const0>\;
axis_rd_data_count(3) <= \<const0>\;
axis_rd_data_count(2) <= \<const0>\;
axis_rd_data_count(1) <= \<const0>\;
axis_rd_data_count(0) <= \<const0>\;
axis_sbiterr <= \<const0>\;
axis_underflow <= \<const0>\;
axis_wr_data_count(10) <= \<const0>\;
axis_wr_data_count(9) <= \<const0>\;
axis_wr_data_count(8) <= \<const0>\;
axis_wr_data_count(7) <= \<const0>\;
axis_wr_data_count(6) <= \<const0>\;
axis_wr_data_count(5) <= \<const0>\;
axis_wr_data_count(4) <= \<const0>\;
axis_wr_data_count(3) <= \<const0>\;
axis_wr_data_count(2) <= \<const0>\;
axis_wr_data_count(1) <= \<const0>\;
axis_wr_data_count(0) <= \<const0>\;
data_count(5) <= \<const0>\;
data_count(4) <= \<const0>\;
data_count(3) <= \<const0>\;
data_count(2) <= \<const0>\;
data_count(1) <= \<const0>\;
data_count(0) <= \<const0>\;
dbiterr <= \<const0>\;
m_axi_araddr(31) <= \<const0>\;
m_axi_araddr(30) <= \<const0>\;
m_axi_araddr(29) <= \<const0>\;
m_axi_araddr(28) <= \<const0>\;
m_axi_araddr(27) <= \<const0>\;
m_axi_araddr(26) <= \<const0>\;
m_axi_araddr(25) <= \<const0>\;
m_axi_araddr(24) <= \<const0>\;
m_axi_araddr(23) <= \<const0>\;
m_axi_araddr(22) <= \<const0>\;
m_axi_araddr(21) <= \<const0>\;
m_axi_araddr(20) <= \<const0>\;
m_axi_araddr(19) <= \<const0>\;
m_axi_araddr(18) <= \<const0>\;
m_axi_araddr(17) <= \<const0>\;
m_axi_araddr(16) <= \<const0>\;
m_axi_araddr(15) <= \<const0>\;
m_axi_araddr(14) <= \<const0>\;
m_axi_araddr(13) <= \<const0>\;
m_axi_araddr(12) <= \<const0>\;
m_axi_araddr(11) <= \<const0>\;
m_axi_araddr(10) <= \<const0>\;
m_axi_araddr(9) <= \<const0>\;
m_axi_araddr(8) <= \<const0>\;
m_axi_araddr(7) <= \<const0>\;
m_axi_araddr(6) <= \<const0>\;
m_axi_araddr(5) <= \<const0>\;
m_axi_araddr(4) <= \<const0>\;
m_axi_araddr(3) <= \<const0>\;
m_axi_araddr(2) <= \<const0>\;
m_axi_araddr(1) <= \<const0>\;
m_axi_araddr(0) <= \<const0>\;
m_axi_arburst(1) <= \<const0>\;
m_axi_arburst(0) <= \<const0>\;
m_axi_arcache(3) <= \<const0>\;
m_axi_arcache(2) <= \<const0>\;
m_axi_arcache(1) <= \<const0>\;
m_axi_arcache(0) <= \<const0>\;
m_axi_arid(3) <= \<const0>\;
m_axi_arid(2) <= \<const0>\;
m_axi_arid(1) <= \<const0>\;
m_axi_arid(0) <= \<const0>\;
m_axi_arlen(7) <= \<const0>\;
m_axi_arlen(6) <= \<const0>\;
m_axi_arlen(5) <= \<const0>\;
m_axi_arlen(4) <= \<const0>\;
m_axi_arlen(3) <= \<const0>\;
m_axi_arlen(2) <= \<const0>\;
m_axi_arlen(1) <= \<const0>\;
m_axi_arlen(0) <= \<const0>\;
m_axi_arlock(1) <= \<const0>\;
m_axi_arlock(0) <= \<const0>\;
m_axi_arprot(2) <= \<const0>\;
m_axi_arprot(1) <= \<const0>\;
m_axi_arprot(0) <= \<const0>\;
m_axi_arqos(3) <= \<const0>\;
m_axi_arqos(2) <= \<const0>\;
m_axi_arqos(1) <= \<const0>\;
m_axi_arqos(0) <= \<const0>\;
m_axi_arregion(3) <= \<const0>\;
m_axi_arregion(2) <= \<const0>\;
m_axi_arregion(1) <= \<const0>\;
m_axi_arregion(0) <= \<const0>\;
m_axi_arsize(2) <= \<const0>\;
m_axi_arsize(1) <= \<const0>\;
m_axi_arsize(0) <= \<const0>\;
m_axi_aruser(0) <= \<const0>\;
m_axi_arvalid <= \<const0>\;
m_axi_awaddr(31) <= \<const0>\;
m_axi_awaddr(30) <= \<const0>\;
m_axi_awaddr(29) <= \<const0>\;
m_axi_awaddr(28) <= \<const0>\;
m_axi_awaddr(27) <= \<const0>\;
m_axi_awaddr(26) <= \<const0>\;
m_axi_awaddr(25) <= \<const0>\;
m_axi_awaddr(24) <= \<const0>\;
m_axi_awaddr(23) <= \<const0>\;
m_axi_awaddr(22) <= \<const0>\;
m_axi_awaddr(21) <= \<const0>\;
m_axi_awaddr(20) <= \<const0>\;
m_axi_awaddr(19) <= \<const0>\;
m_axi_awaddr(18) <= \<const0>\;
m_axi_awaddr(17) <= \<const0>\;
m_axi_awaddr(16) <= \<const0>\;
m_axi_awaddr(15) <= \<const0>\;
m_axi_awaddr(14) <= \<const0>\;
m_axi_awaddr(13) <= \<const0>\;
m_axi_awaddr(12) <= \<const0>\;
m_axi_awaddr(11) <= \<const0>\;
m_axi_awaddr(10) <= \<const0>\;
m_axi_awaddr(9) <= \<const0>\;
m_axi_awaddr(8) <= \<const0>\;
m_axi_awaddr(7) <= \<const0>\;
m_axi_awaddr(6) <= \<const0>\;
m_axi_awaddr(5) <= \<const0>\;
m_axi_awaddr(4) <= \<const0>\;
m_axi_awaddr(3) <= \<const0>\;
m_axi_awaddr(2) <= \<const0>\;
m_axi_awaddr(1) <= \<const0>\;
m_axi_awaddr(0) <= \<const0>\;
m_axi_awburst(1) <= \<const0>\;
m_axi_awburst(0) <= \<const0>\;
m_axi_awcache(3) <= \<const0>\;
m_axi_awcache(2) <= \<const0>\;
m_axi_awcache(1) <= \<const0>\;
m_axi_awcache(0) <= \<const0>\;
m_axi_awid(3) <= \<const0>\;
m_axi_awid(2) <= \<const0>\;
m_axi_awid(1) <= \<const0>\;
m_axi_awid(0) <= \<const0>\;
m_axi_awlen(7) <= \<const0>\;
m_axi_awlen(6) <= \<const0>\;
m_axi_awlen(5) <= \<const0>\;
m_axi_awlen(4) <= \<const0>\;
m_axi_awlen(3) <= \<const0>\;
m_axi_awlen(2) <= \<const0>\;
m_axi_awlen(1) <= \<const0>\;
m_axi_awlen(0) <= \<const0>\;
m_axi_awlock(1) <= \<const0>\;
m_axi_awlock(0) <= \<const0>\;
m_axi_awprot(2) <= \<const0>\;
m_axi_awprot(1) <= \<const0>\;
m_axi_awprot(0) <= \<const0>\;
m_axi_awqos(3) <= \<const0>\;
m_axi_awqos(2) <= \<const0>\;
m_axi_awqos(1) <= \<const0>\;
m_axi_awqos(0) <= \<const0>\;
m_axi_awregion(3) <= \<const0>\;
m_axi_awregion(2) <= \<const0>\;
m_axi_awregion(1) <= \<const0>\;
m_axi_awregion(0) <= \<const0>\;
m_axi_awsize(2) <= \<const0>\;
m_axi_awsize(1) <= \<const0>\;
m_axi_awsize(0) <= \<const0>\;
m_axi_awuser(0) <= \<const0>\;
m_axi_awvalid <= \<const0>\;
m_axi_bready <= \<const0>\;
m_axi_rready <= \<const0>\;
m_axi_wdata(63) <= \<const0>\;
m_axi_wdata(62) <= \<const0>\;
m_axi_wdata(61) <= \<const0>\;
m_axi_wdata(60) <= \<const0>\;
m_axi_wdata(59) <= \<const0>\;
m_axi_wdata(58) <= \<const0>\;
m_axi_wdata(57) <= \<const0>\;
m_axi_wdata(56) <= \<const0>\;
m_axi_wdata(55) <= \<const0>\;
m_axi_wdata(54) <= \<const0>\;
m_axi_wdata(53) <= \<const0>\;
m_axi_wdata(52) <= \<const0>\;
m_axi_wdata(51) <= \<const0>\;
m_axi_wdata(50) <= \<const0>\;
m_axi_wdata(49) <= \<const0>\;
m_axi_wdata(48) <= \<const0>\;
m_axi_wdata(47) <= \<const0>\;
m_axi_wdata(46) <= \<const0>\;
m_axi_wdata(45) <= \<const0>\;
m_axi_wdata(44) <= \<const0>\;
m_axi_wdata(43) <= \<const0>\;
m_axi_wdata(42) <= \<const0>\;
m_axi_wdata(41) <= \<const0>\;
m_axi_wdata(40) <= \<const0>\;
m_axi_wdata(39) <= \<const0>\;
m_axi_wdata(38) <= \<const0>\;
m_axi_wdata(37) <= \<const0>\;
m_axi_wdata(36) <= \<const0>\;
m_axi_wdata(35) <= \<const0>\;
m_axi_wdata(34) <= \<const0>\;
m_axi_wdata(33) <= \<const0>\;
m_axi_wdata(32) <= \<const0>\;
m_axi_wdata(31) <= \<const0>\;
m_axi_wdata(30) <= \<const0>\;
m_axi_wdata(29) <= \<const0>\;
m_axi_wdata(28) <= \<const0>\;
m_axi_wdata(27) <= \<const0>\;
m_axi_wdata(26) <= \<const0>\;
m_axi_wdata(25) <= \<const0>\;
m_axi_wdata(24) <= \<const0>\;
m_axi_wdata(23) <= \<const0>\;
m_axi_wdata(22) <= \<const0>\;
m_axi_wdata(21) <= \<const0>\;
m_axi_wdata(20) <= \<const0>\;
m_axi_wdata(19) <= \<const0>\;
m_axi_wdata(18) <= \<const0>\;
m_axi_wdata(17) <= \<const0>\;
m_axi_wdata(16) <= \<const0>\;
m_axi_wdata(15) <= \<const0>\;
m_axi_wdata(14) <= \<const0>\;
m_axi_wdata(13) <= \<const0>\;
m_axi_wdata(12) <= \<const0>\;
m_axi_wdata(11) <= \<const0>\;
m_axi_wdata(10) <= \<const0>\;
m_axi_wdata(9) <= \<const0>\;
m_axi_wdata(8) <= \<const0>\;
m_axi_wdata(7) <= \<const0>\;
m_axi_wdata(6) <= \<const0>\;
m_axi_wdata(5) <= \<const0>\;
m_axi_wdata(4) <= \<const0>\;
m_axi_wdata(3) <= \<const0>\;
m_axi_wdata(2) <= \<const0>\;
m_axi_wdata(1) <= \<const0>\;
m_axi_wdata(0) <= \<const0>\;
m_axi_wid(3) <= \<const0>\;
m_axi_wid(2) <= \<const0>\;
m_axi_wid(1) <= \<const0>\;
m_axi_wid(0) <= \<const0>\;
m_axi_wlast <= \<const0>\;
m_axi_wstrb(7) <= \<const0>\;
m_axi_wstrb(6) <= \<const0>\;
m_axi_wstrb(5) <= \<const0>\;
m_axi_wstrb(4) <= \<const0>\;
m_axi_wstrb(3) <= \<const0>\;
m_axi_wstrb(2) <= \<const0>\;
m_axi_wstrb(1) <= \<const0>\;
m_axi_wstrb(0) <= \<const0>\;
m_axi_wuser(0) <= \<const0>\;
m_axi_wvalid <= \<const0>\;
m_axis_tdata(63) <= \<const0>\;
m_axis_tdata(62) <= \<const0>\;
m_axis_tdata(61) <= \<const0>\;
m_axis_tdata(60) <= \<const0>\;
m_axis_tdata(59) <= \<const0>\;
m_axis_tdata(58) <= \<const0>\;
m_axis_tdata(57) <= \<const0>\;
m_axis_tdata(56) <= \<const0>\;
m_axis_tdata(55) <= \<const0>\;
m_axis_tdata(54) <= \<const0>\;
m_axis_tdata(53) <= \<const0>\;
m_axis_tdata(52) <= \<const0>\;
m_axis_tdata(51) <= \<const0>\;
m_axis_tdata(50) <= \<const0>\;
m_axis_tdata(49) <= \<const0>\;
m_axis_tdata(48) <= \<const0>\;
m_axis_tdata(47) <= \<const0>\;
m_axis_tdata(46) <= \<const0>\;
m_axis_tdata(45) <= \<const0>\;
m_axis_tdata(44) <= \<const0>\;
m_axis_tdata(43) <= \<const0>\;
m_axis_tdata(42) <= \<const0>\;
m_axis_tdata(41) <= \<const0>\;
m_axis_tdata(40) <= \<const0>\;
m_axis_tdata(39) <= \<const0>\;
m_axis_tdata(38) <= \<const0>\;
m_axis_tdata(37) <= \<const0>\;
m_axis_tdata(36) <= \<const0>\;
m_axis_tdata(35) <= \<const0>\;
m_axis_tdata(34) <= \<const0>\;
m_axis_tdata(33) <= \<const0>\;
m_axis_tdata(32) <= \<const0>\;
m_axis_tdata(31) <= \<const0>\;
m_axis_tdata(30) <= \<const0>\;
m_axis_tdata(29) <= \<const0>\;
m_axis_tdata(28) <= \<const0>\;
m_axis_tdata(27) <= \<const0>\;
m_axis_tdata(26) <= \<const0>\;
m_axis_tdata(25) <= \<const0>\;
m_axis_tdata(24) <= \<const0>\;
m_axis_tdata(23) <= \<const0>\;
m_axis_tdata(22) <= \<const0>\;
m_axis_tdata(21) <= \<const0>\;
m_axis_tdata(20) <= \<const0>\;
m_axis_tdata(19) <= \<const0>\;
m_axis_tdata(18) <= \<const0>\;
m_axis_tdata(17) <= \<const0>\;
m_axis_tdata(16) <= \<const0>\;
m_axis_tdata(15) <= \<const0>\;
m_axis_tdata(14) <= \<const0>\;
m_axis_tdata(13) <= \<const0>\;
m_axis_tdata(12) <= \<const0>\;
m_axis_tdata(11) <= \<const0>\;
m_axis_tdata(10) <= \<const0>\;
m_axis_tdata(9) <= \<const0>\;
m_axis_tdata(8) <= \<const0>\;
m_axis_tdata(7) <= \<const0>\;
m_axis_tdata(6) <= \<const0>\;
m_axis_tdata(5) <= \<const0>\;
m_axis_tdata(4) <= \<const0>\;
m_axis_tdata(3) <= \<const0>\;
m_axis_tdata(2) <= \<const0>\;
m_axis_tdata(1) <= \<const0>\;
m_axis_tdata(0) <= \<const0>\;
m_axis_tdest(3) <= \<const0>\;
m_axis_tdest(2) <= \<const0>\;
m_axis_tdest(1) <= \<const0>\;
m_axis_tdest(0) <= \<const0>\;
m_axis_tid(7) <= \<const0>\;
m_axis_tid(6) <= \<const0>\;
m_axis_tid(5) <= \<const0>\;
m_axis_tid(4) <= \<const0>\;
m_axis_tid(3) <= \<const0>\;
m_axis_tid(2) <= \<const0>\;
m_axis_tid(1) <= \<const0>\;
m_axis_tid(0) <= \<const0>\;
m_axis_tkeep(3) <= \<const0>\;
m_axis_tkeep(2) <= \<const0>\;
m_axis_tkeep(1) <= \<const0>\;
m_axis_tkeep(0) <= \<const0>\;
m_axis_tlast <= \<const0>\;
m_axis_tstrb(3) <= \<const0>\;
m_axis_tstrb(2) <= \<const0>\;
m_axis_tstrb(1) <= \<const0>\;
m_axis_tstrb(0) <= \<const0>\;
m_axis_tuser(3) <= \<const0>\;
m_axis_tuser(2) <= \<const0>\;
m_axis_tuser(1) <= \<const0>\;
m_axis_tuser(0) <= \<const0>\;
m_axis_tvalid <= \<const0>\;
overflow <= \<const0>\;
prog_empty <= \<const0>\;
prog_full <= \<const0>\;
rd_data_count(5) <= \<const0>\;
rd_data_count(4) <= \<const0>\;
rd_data_count(3) <= \<const0>\;
rd_data_count(2) <= \<const0>\;
rd_data_count(1) <= \<const0>\;
rd_data_count(0) <= \<const0>\;
rd_rst_busy <= \<const0>\;
s_axi_arready <= \<const0>\;
s_axi_awready <= \<const0>\;
s_axi_bid(3) <= \<const0>\;
s_axi_bid(2) <= \<const0>\;
s_axi_bid(1) <= \<const0>\;
s_axi_bid(0) <= \<const0>\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_buser(0) <= \<const0>\;
s_axi_bvalid <= \<const0>\;
s_axi_rdata(63) <= \<const0>\;
s_axi_rdata(62) <= \<const0>\;
s_axi_rdata(61) <= \<const0>\;
s_axi_rdata(60) <= \<const0>\;
s_axi_rdata(59) <= \<const0>\;
s_axi_rdata(58) <= \<const0>\;
s_axi_rdata(57) <= \<const0>\;
s_axi_rdata(56) <= \<const0>\;
s_axi_rdata(55) <= \<const0>\;
s_axi_rdata(54) <= \<const0>\;
s_axi_rdata(53) <= \<const0>\;
s_axi_rdata(52) <= \<const0>\;
s_axi_rdata(51) <= \<const0>\;
s_axi_rdata(50) <= \<const0>\;
s_axi_rdata(49) <= \<const0>\;
s_axi_rdata(48) <= \<const0>\;
s_axi_rdata(47) <= \<const0>\;
s_axi_rdata(46) <= \<const0>\;
s_axi_rdata(45) <= \<const0>\;
s_axi_rdata(44) <= \<const0>\;
s_axi_rdata(43) <= \<const0>\;
s_axi_rdata(42) <= \<const0>\;
s_axi_rdata(41) <= \<const0>\;
s_axi_rdata(40) <= \<const0>\;
s_axi_rdata(39) <= \<const0>\;
s_axi_rdata(38) <= \<const0>\;
s_axi_rdata(37) <= \<const0>\;
s_axi_rdata(36) <= \<const0>\;
s_axi_rdata(35) <= \<const0>\;
s_axi_rdata(34) <= \<const0>\;
s_axi_rdata(33) <= \<const0>\;
s_axi_rdata(32) <= \<const0>\;
s_axi_rdata(31) <= \<const0>\;
s_axi_rdata(30) <= \<const0>\;
s_axi_rdata(29) <= \<const0>\;
s_axi_rdata(28) <= \<const0>\;
s_axi_rdata(27) <= \<const0>\;
s_axi_rdata(26) <= \<const0>\;
s_axi_rdata(25) <= \<const0>\;
s_axi_rdata(24) <= \<const0>\;
s_axi_rdata(23) <= \<const0>\;
s_axi_rdata(22) <= \<const0>\;
s_axi_rdata(21) <= \<const0>\;
s_axi_rdata(20) <= \<const0>\;
s_axi_rdata(19) <= \<const0>\;
s_axi_rdata(18) <= \<const0>\;
s_axi_rdata(17) <= \<const0>\;
s_axi_rdata(16) <= \<const0>\;
s_axi_rdata(15) <= \<const0>\;
s_axi_rdata(14) <= \<const0>\;
s_axi_rdata(13) <= \<const0>\;
s_axi_rdata(12) <= \<const0>\;
s_axi_rdata(11) <= \<const0>\;
s_axi_rdata(10) <= \<const0>\;
s_axi_rdata(9) <= \<const0>\;
s_axi_rdata(8) <= \<const0>\;
s_axi_rdata(7) <= \<const0>\;
s_axi_rdata(6) <= \<const0>\;
s_axi_rdata(5) <= \<const0>\;
s_axi_rdata(4) <= \<const0>\;
s_axi_rdata(3) <= \<const0>\;
s_axi_rdata(2) <= \<const0>\;
s_axi_rdata(1) <= \<const0>\;
s_axi_rdata(0) <= \<const0>\;
s_axi_rid(3) <= \<const0>\;
s_axi_rid(2) <= \<const0>\;
s_axi_rid(1) <= \<const0>\;
s_axi_rid(0) <= \<const0>\;
s_axi_rlast <= \<const0>\;
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
s_axi_ruser(0) <= \<const0>\;
s_axi_rvalid <= \<const0>\;
s_axi_wready <= \<const0>\;
s_axis_tready <= \<const0>\;
sbiterr <= \<const0>\;
underflow <= \<const0>\;
valid <= \<const0>\;
wr_ack <= \<const0>\;
wr_data_count(5) <= \<const0>\;
wr_data_count(4) <= \<const0>\;
wr_data_count(3) <= \<const0>\;
wr_data_count(2) <= \<const0>\;
wr_data_count(1) <= \<const0>\;
wr_data_count(0) <= \<const0>\;
wr_rst_busy <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
inst_fifo_gen: entity work.system_auto_pc_1_fifo_generator_v13_1_3_synth
port map (
clk => clk,
din(5 downto 0) => din(5 downto 0),
dout(5 downto 0) => dout(5 downto 0),
empty => empty,
full => full,
rd_en => rd_en,
rst => rst,
wr_en => wr_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ is
port (
backup : in STD_LOGIC;
backup_marker : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
srst : in STD_LOGIC;
wr_clk : in STD_LOGIC;
wr_rst : in STD_LOGIC;
rd_clk : in STD_LOGIC;
rd_rst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 4 downto 0 );
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
prog_empty_thresh : in STD_LOGIC_VECTOR ( 4 downto 0 );
prog_empty_thresh_assert : in STD_LOGIC_VECTOR ( 4 downto 0 );
prog_empty_thresh_negate : in STD_LOGIC_VECTOR ( 4 downto 0 );
prog_full_thresh : in STD_LOGIC_VECTOR ( 4 downto 0 );
prog_full_thresh_assert : in STD_LOGIC_VECTOR ( 4 downto 0 );
prog_full_thresh_negate : in STD_LOGIC_VECTOR ( 4 downto 0 );
int_clk : in STD_LOGIC;
injectdbiterr : in STD_LOGIC;
injectsbiterr : in STD_LOGIC;
sleep : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 4 downto 0 );
full : out STD_LOGIC;
almost_full : out STD_LOGIC;
wr_ack : out STD_LOGIC;
overflow : out STD_LOGIC;
empty : out STD_LOGIC;
almost_empty : out STD_LOGIC;
valid : out STD_LOGIC;
underflow : out STD_LOGIC;
data_count : out STD_LOGIC_VECTOR ( 5 downto 0 );
rd_data_count : out STD_LOGIC_VECTOR ( 5 downto 0 );
wr_data_count : out STD_LOGIC_VECTOR ( 5 downto 0 );
prog_full : out STD_LOGIC;
prog_empty : out STD_LOGIC;
sbiterr : out STD_LOGIC;
dbiterr : out STD_LOGIC;
wr_rst_busy : out STD_LOGIC;
rd_rst_busy : out STD_LOGIC;
m_aclk : in STD_LOGIC;
s_aclk : in STD_LOGIC;
s_aresetn : in STD_LOGIC;
m_aclk_en : in STD_LOGIC;
s_aclk_en : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_buser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
m_axi_awid : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wid : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_wlast : out STD_LOGIC;
m_axi_wuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bid : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_buser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_aruser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_ruser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_arid : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_aruser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_ruser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC;
s_axis_tvalid : in STD_LOGIC;
s_axis_tready : out STD_LOGIC;
s_axis_tdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
s_axis_tstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axis_tkeep : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axis_tlast : in STD_LOGIC;
s_axis_tid : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axis_tdest : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axis_tuser : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axis_tvalid : out STD_LOGIC;
m_axis_tready : in STD_LOGIC;
m_axis_tdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
m_axis_tstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axis_tkeep : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axis_tlast : out STD_LOGIC;
m_axis_tid : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axis_tdest : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axis_tuser : out STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_injectsbiterr : in STD_LOGIC;
axi_aw_injectdbiterr : in STD_LOGIC;
axi_aw_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_sbiterr : out STD_LOGIC;
axi_aw_dbiterr : out STD_LOGIC;
axi_aw_overflow : out STD_LOGIC;
axi_aw_underflow : out STD_LOGIC;
axi_aw_prog_full : out STD_LOGIC;
axi_aw_prog_empty : out STD_LOGIC;
axi_w_injectsbiterr : in STD_LOGIC;
axi_w_injectdbiterr : in STD_LOGIC;
axi_w_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_w_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_w_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_w_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_w_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_w_sbiterr : out STD_LOGIC;
axi_w_dbiterr : out STD_LOGIC;
axi_w_overflow : out STD_LOGIC;
axi_w_underflow : out STD_LOGIC;
axi_w_prog_full : out STD_LOGIC;
axi_w_prog_empty : out STD_LOGIC;
axi_b_injectsbiterr : in STD_LOGIC;
axi_b_injectdbiterr : in STD_LOGIC;
axi_b_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_b_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_b_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_sbiterr : out STD_LOGIC;
axi_b_dbiterr : out STD_LOGIC;
axi_b_overflow : out STD_LOGIC;
axi_b_underflow : out STD_LOGIC;
axi_b_prog_full : out STD_LOGIC;
axi_b_prog_empty : out STD_LOGIC;
axi_ar_injectsbiterr : in STD_LOGIC;
axi_ar_injectdbiterr : in STD_LOGIC;
axi_ar_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_ar_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_ar_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_sbiterr : out STD_LOGIC;
axi_ar_dbiterr : out STD_LOGIC;
axi_ar_overflow : out STD_LOGIC;
axi_ar_underflow : out STD_LOGIC;
axi_ar_prog_full : out STD_LOGIC;
axi_ar_prog_empty : out STD_LOGIC;
axi_r_injectsbiterr : in STD_LOGIC;
axi_r_injectdbiterr : in STD_LOGIC;
axi_r_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_r_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_r_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_r_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_r_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_r_sbiterr : out STD_LOGIC;
axi_r_dbiterr : out STD_LOGIC;
axi_r_overflow : out STD_LOGIC;
axi_r_underflow : out STD_LOGIC;
axi_r_prog_full : out STD_LOGIC;
axi_r_prog_empty : out STD_LOGIC;
axis_injectsbiterr : in STD_LOGIC;
axis_injectdbiterr : in STD_LOGIC;
axis_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axis_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axis_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_sbiterr : out STD_LOGIC;
axis_dbiterr : out STD_LOGIC;
axis_overflow : out STD_LOGIC;
axis_underflow : out STD_LOGIC;
axis_prog_full : out STD_LOGIC;
axis_prog_empty : out STD_LOGIC
);
attribute C_ADD_NGC_CONSTRAINT : integer;
attribute C_ADD_NGC_CONSTRAINT of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_APPLICATION_TYPE_AXIS : integer;
attribute C_APPLICATION_TYPE_AXIS of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_APPLICATION_TYPE_RACH : integer;
attribute C_APPLICATION_TYPE_RACH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_APPLICATION_TYPE_RDCH : integer;
attribute C_APPLICATION_TYPE_RDCH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_APPLICATION_TYPE_WACH : integer;
attribute C_APPLICATION_TYPE_WACH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_APPLICATION_TYPE_WDCH : integer;
attribute C_APPLICATION_TYPE_WDCH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_APPLICATION_TYPE_WRCH : integer;
attribute C_APPLICATION_TYPE_WRCH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_AXIS_TDATA_WIDTH : integer;
attribute C_AXIS_TDATA_WIDTH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 64;
attribute C_AXIS_TDEST_WIDTH : integer;
attribute C_AXIS_TDEST_WIDTH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 4;
attribute C_AXIS_TID_WIDTH : integer;
attribute C_AXIS_TID_WIDTH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 8;
attribute C_AXIS_TKEEP_WIDTH : integer;
attribute C_AXIS_TKEEP_WIDTH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 4;
attribute C_AXIS_TSTRB_WIDTH : integer;
attribute C_AXIS_TSTRB_WIDTH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 4;
attribute C_AXIS_TUSER_WIDTH : integer;
attribute C_AXIS_TUSER_WIDTH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 4;
attribute C_AXIS_TYPE : integer;
attribute C_AXIS_TYPE of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 64;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 4;
attribute C_AXI_LEN_WIDTH : integer;
attribute C_AXI_LEN_WIDTH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 8;
attribute C_AXI_LOCK_WIDTH : integer;
attribute C_AXI_LOCK_WIDTH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 2;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 1;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 1;
attribute C_COMMON_CLOCK : integer;
attribute C_COMMON_CLOCK of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 1;
attribute C_COUNT_TYPE : integer;
attribute C_COUNT_TYPE of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_DATA_COUNT_WIDTH : integer;
attribute C_DATA_COUNT_WIDTH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 6;
attribute C_DEFAULT_VALUE : string;
attribute C_DEFAULT_VALUE of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is "BlankString";
attribute C_DIN_WIDTH : integer;
attribute C_DIN_WIDTH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 5;
attribute C_DIN_WIDTH_AXIS : integer;
attribute C_DIN_WIDTH_AXIS of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 1;
attribute C_DIN_WIDTH_RACH : integer;
attribute C_DIN_WIDTH_RACH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 32;
attribute C_DIN_WIDTH_RDCH : integer;
attribute C_DIN_WIDTH_RDCH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 64;
attribute C_DIN_WIDTH_WACH : integer;
attribute C_DIN_WIDTH_WACH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 32;
attribute C_DIN_WIDTH_WDCH : integer;
attribute C_DIN_WIDTH_WDCH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 64;
attribute C_DIN_WIDTH_WRCH : integer;
attribute C_DIN_WIDTH_WRCH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 2;
attribute C_DOUT_RST_VAL : string;
attribute C_DOUT_RST_VAL of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is "0";
attribute C_DOUT_WIDTH : integer;
attribute C_DOUT_WIDTH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 5;
attribute C_ENABLE_RLOCS : integer;
attribute C_ENABLE_RLOCS of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_ENABLE_RST_SYNC : integer;
attribute C_ENABLE_RST_SYNC of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 1;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_ERROR_INJECTION_TYPE : integer;
attribute C_ERROR_INJECTION_TYPE of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_ERROR_INJECTION_TYPE_AXIS : integer;
attribute C_ERROR_INJECTION_TYPE_AXIS of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_ERROR_INJECTION_TYPE_RACH : integer;
attribute C_ERROR_INJECTION_TYPE_RACH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_ERROR_INJECTION_TYPE_RDCH : integer;
attribute C_ERROR_INJECTION_TYPE_RDCH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WACH : integer;
attribute C_ERROR_INJECTION_TYPE_WACH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WDCH : integer;
attribute C_ERROR_INJECTION_TYPE_WDCH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WRCH : integer;
attribute C_ERROR_INJECTION_TYPE_WRCH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is "zynq";
attribute C_FULL_FLAGS_RST_VAL : integer;
attribute C_FULL_FLAGS_RST_VAL of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_HAS_ALMOST_EMPTY : integer;
attribute C_HAS_ALMOST_EMPTY of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_HAS_ALMOST_FULL : integer;
attribute C_HAS_ALMOST_FULL of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_HAS_AXIS_TDATA : integer;
attribute C_HAS_AXIS_TDATA of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_HAS_AXIS_TDEST : integer;
attribute C_HAS_AXIS_TDEST of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_HAS_AXIS_TID : integer;
attribute C_HAS_AXIS_TID of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_HAS_AXIS_TKEEP : integer;
attribute C_HAS_AXIS_TKEEP of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_HAS_AXIS_TLAST : integer;
attribute C_HAS_AXIS_TLAST of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_HAS_AXIS_TREADY : integer;
attribute C_HAS_AXIS_TREADY of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 1;
attribute C_HAS_AXIS_TSTRB : integer;
attribute C_HAS_AXIS_TSTRB of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_HAS_AXIS_TUSER : integer;
attribute C_HAS_AXIS_TUSER of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_HAS_AXI_ARUSER : integer;
attribute C_HAS_AXI_ARUSER of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_HAS_AXI_AWUSER : integer;
attribute C_HAS_AXI_AWUSER of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_HAS_AXI_BUSER : integer;
attribute C_HAS_AXI_BUSER of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_HAS_AXI_RD_CHANNEL : integer;
attribute C_HAS_AXI_RD_CHANNEL of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_HAS_AXI_RUSER : integer;
attribute C_HAS_AXI_RUSER of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_HAS_AXI_WR_CHANNEL : integer;
attribute C_HAS_AXI_WR_CHANNEL of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_HAS_AXI_WUSER : integer;
attribute C_HAS_AXI_WUSER of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_HAS_BACKUP : integer;
attribute C_HAS_BACKUP of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_HAS_DATA_COUNT : integer;
attribute C_HAS_DATA_COUNT of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_HAS_DATA_COUNTS_AXIS : integer;
attribute C_HAS_DATA_COUNTS_AXIS of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_HAS_DATA_COUNTS_RACH : integer;
attribute C_HAS_DATA_COUNTS_RACH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_HAS_DATA_COUNTS_RDCH : integer;
attribute C_HAS_DATA_COUNTS_RDCH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_HAS_DATA_COUNTS_WACH : integer;
attribute C_HAS_DATA_COUNTS_WACH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_HAS_DATA_COUNTS_WDCH : integer;
attribute C_HAS_DATA_COUNTS_WDCH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_HAS_DATA_COUNTS_WRCH : integer;
attribute C_HAS_DATA_COUNTS_WRCH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_HAS_INT_CLK : integer;
attribute C_HAS_INT_CLK of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_HAS_MASTER_CE : integer;
attribute C_HAS_MASTER_CE of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_HAS_MEMINIT_FILE : integer;
attribute C_HAS_MEMINIT_FILE of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_HAS_OVERFLOW : integer;
attribute C_HAS_OVERFLOW of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_HAS_PROG_FLAGS_AXIS : integer;
attribute C_HAS_PROG_FLAGS_AXIS of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_HAS_PROG_FLAGS_RACH : integer;
attribute C_HAS_PROG_FLAGS_RACH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_HAS_PROG_FLAGS_RDCH : integer;
attribute C_HAS_PROG_FLAGS_RDCH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_HAS_PROG_FLAGS_WACH : integer;
attribute C_HAS_PROG_FLAGS_WACH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_HAS_PROG_FLAGS_WDCH : integer;
attribute C_HAS_PROG_FLAGS_WDCH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_HAS_PROG_FLAGS_WRCH : integer;
attribute C_HAS_PROG_FLAGS_WRCH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_HAS_RD_DATA_COUNT : integer;
attribute C_HAS_RD_DATA_COUNT of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_HAS_RD_RST : integer;
attribute C_HAS_RD_RST of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_HAS_RST : integer;
attribute C_HAS_RST of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 1;
attribute C_HAS_SLAVE_CE : integer;
attribute C_HAS_SLAVE_CE of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_HAS_SRST : integer;
attribute C_HAS_SRST of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_HAS_UNDERFLOW : integer;
attribute C_HAS_UNDERFLOW of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_HAS_VALID : integer;
attribute C_HAS_VALID of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_HAS_WR_ACK : integer;
attribute C_HAS_WR_ACK of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_HAS_WR_DATA_COUNT : integer;
attribute C_HAS_WR_DATA_COUNT of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_HAS_WR_RST : integer;
attribute C_HAS_WR_RST of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_IMPLEMENTATION_TYPE : integer;
attribute C_IMPLEMENTATION_TYPE of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_IMPLEMENTATION_TYPE_AXIS : integer;
attribute C_IMPLEMENTATION_TYPE_AXIS of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 1;
attribute C_IMPLEMENTATION_TYPE_RACH : integer;
attribute C_IMPLEMENTATION_TYPE_RACH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 1;
attribute C_IMPLEMENTATION_TYPE_RDCH : integer;
attribute C_IMPLEMENTATION_TYPE_RDCH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 1;
attribute C_IMPLEMENTATION_TYPE_WACH : integer;
attribute C_IMPLEMENTATION_TYPE_WACH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 1;
attribute C_IMPLEMENTATION_TYPE_WDCH : integer;
attribute C_IMPLEMENTATION_TYPE_WDCH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 1;
attribute C_IMPLEMENTATION_TYPE_WRCH : integer;
attribute C_IMPLEMENTATION_TYPE_WRCH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 1;
attribute C_INIT_WR_PNTR_VAL : integer;
attribute C_INIT_WR_PNTR_VAL of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_MEMORY_TYPE : integer;
attribute C_MEMORY_TYPE of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 2;
attribute C_MIF_FILE_NAME : string;
attribute C_MIF_FILE_NAME of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is "BlankString";
attribute C_MSGON_VAL : integer;
attribute C_MSGON_VAL of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 1;
attribute C_OPTIMIZATION_MODE : integer;
attribute C_OPTIMIZATION_MODE of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_OVERFLOW_LOW : integer;
attribute C_OVERFLOW_LOW of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_POWER_SAVING_MODE : integer;
attribute C_POWER_SAVING_MODE of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_PRELOAD_LATENCY : integer;
attribute C_PRELOAD_LATENCY of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_PRELOAD_REGS : integer;
attribute C_PRELOAD_REGS of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 1;
attribute C_PRIM_FIFO_TYPE : string;
attribute C_PRIM_FIFO_TYPE of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_AXIS : string;
attribute C_PRIM_FIFO_TYPE_AXIS of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_RACH : string;
attribute C_PRIM_FIFO_TYPE_RACH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_RDCH : string;
attribute C_PRIM_FIFO_TYPE_RDCH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_WACH : string;
attribute C_PRIM_FIFO_TYPE_WACH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_WDCH : string;
attribute C_PRIM_FIFO_TYPE_WDCH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_WRCH : string;
attribute C_PRIM_FIFO_TYPE_WRCH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is "512x36";
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 4;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 1022;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL : integer;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 5;
attribute C_PROG_EMPTY_TYPE : integer;
attribute C_PROG_EMPTY_TYPE of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_PROG_EMPTY_TYPE_AXIS : integer;
attribute C_PROG_EMPTY_TYPE_AXIS of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_PROG_EMPTY_TYPE_RACH : integer;
attribute C_PROG_EMPTY_TYPE_RACH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_PROG_EMPTY_TYPE_RDCH : integer;
attribute C_PROG_EMPTY_TYPE_RDCH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_PROG_EMPTY_TYPE_WACH : integer;
attribute C_PROG_EMPTY_TYPE_WACH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_PROG_EMPTY_TYPE_WDCH : integer;
attribute C_PROG_EMPTY_TYPE_WDCH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_PROG_EMPTY_TYPE_WRCH : integer;
attribute C_PROG_EMPTY_TYPE_WRCH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_PROG_FULL_THRESH_ASSERT_VAL : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 31;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 1023;
attribute C_PROG_FULL_THRESH_NEGATE_VAL : integer;
attribute C_PROG_FULL_THRESH_NEGATE_VAL of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 30;
attribute C_PROG_FULL_TYPE : integer;
attribute C_PROG_FULL_TYPE of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_PROG_FULL_TYPE_AXIS : integer;
attribute C_PROG_FULL_TYPE_AXIS of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_PROG_FULL_TYPE_RACH : integer;
attribute C_PROG_FULL_TYPE_RACH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_PROG_FULL_TYPE_RDCH : integer;
attribute C_PROG_FULL_TYPE_RDCH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_PROG_FULL_TYPE_WACH : integer;
attribute C_PROG_FULL_TYPE_WACH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_PROG_FULL_TYPE_WDCH : integer;
attribute C_PROG_FULL_TYPE_WDCH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_PROG_FULL_TYPE_WRCH : integer;
attribute C_PROG_FULL_TYPE_WRCH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_RACH_TYPE : integer;
attribute C_RACH_TYPE of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_RDCH_TYPE : integer;
attribute C_RDCH_TYPE of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_RD_DATA_COUNT_WIDTH : integer;
attribute C_RD_DATA_COUNT_WIDTH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 6;
attribute C_RD_DEPTH : integer;
attribute C_RD_DEPTH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 32;
attribute C_RD_FREQ : integer;
attribute C_RD_FREQ of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 1;
attribute C_RD_PNTR_WIDTH : integer;
attribute C_RD_PNTR_WIDTH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 5;
attribute C_REG_SLICE_MODE_AXIS : integer;
attribute C_REG_SLICE_MODE_AXIS of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_REG_SLICE_MODE_RACH : integer;
attribute C_REG_SLICE_MODE_RACH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_REG_SLICE_MODE_RDCH : integer;
attribute C_REG_SLICE_MODE_RDCH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_REG_SLICE_MODE_WACH : integer;
attribute C_REG_SLICE_MODE_WACH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_REG_SLICE_MODE_WDCH : integer;
attribute C_REG_SLICE_MODE_WDCH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_REG_SLICE_MODE_WRCH : integer;
attribute C_REG_SLICE_MODE_WRCH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_SELECT_XPM : integer;
attribute C_SELECT_XPM of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_SYNCHRONIZER_STAGE : integer;
attribute C_SYNCHRONIZER_STAGE of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 3;
attribute C_UNDERFLOW_LOW : integer;
attribute C_UNDERFLOW_LOW of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_USE_COMMON_OVERFLOW : integer;
attribute C_USE_COMMON_OVERFLOW of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_USE_COMMON_UNDERFLOW : integer;
attribute C_USE_COMMON_UNDERFLOW of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_USE_DEFAULT_SETTINGS : integer;
attribute C_USE_DEFAULT_SETTINGS of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_USE_DOUT_RST : integer;
attribute C_USE_DOUT_RST of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_USE_ECC_AXIS : integer;
attribute C_USE_ECC_AXIS of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_USE_ECC_RACH : integer;
attribute C_USE_ECC_RACH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_USE_ECC_RDCH : integer;
attribute C_USE_ECC_RDCH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_USE_ECC_WACH : integer;
attribute C_USE_ECC_WACH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_USE_ECC_WDCH : integer;
attribute C_USE_ECC_WDCH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_USE_ECC_WRCH : integer;
attribute C_USE_ECC_WRCH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_USE_EMBEDDED_REG : integer;
attribute C_USE_EMBEDDED_REG of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_USE_FIFO16_FLAGS : integer;
attribute C_USE_FIFO16_FLAGS of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_USE_FWFT_DATA_COUNT : integer;
attribute C_USE_FWFT_DATA_COUNT of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 1;
attribute C_USE_PIPELINE_REG : integer;
attribute C_USE_PIPELINE_REG of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_VALID_LOW : integer;
attribute C_VALID_LOW of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_WACH_TYPE : integer;
attribute C_WACH_TYPE of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_WDCH_TYPE : integer;
attribute C_WDCH_TYPE of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_WRCH_TYPE : integer;
attribute C_WRCH_TYPE of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_WR_ACK_LOW : integer;
attribute C_WR_ACK_LOW of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 0;
attribute C_WR_DATA_COUNT_WIDTH : integer;
attribute C_WR_DATA_COUNT_WIDTH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 6;
attribute C_WR_DEPTH : integer;
attribute C_WR_DEPTH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 32;
attribute C_WR_DEPTH_AXIS : integer;
attribute C_WR_DEPTH_AXIS of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 1024;
attribute C_WR_DEPTH_RACH : integer;
attribute C_WR_DEPTH_RACH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 16;
attribute C_WR_DEPTH_RDCH : integer;
attribute C_WR_DEPTH_RDCH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 1024;
attribute C_WR_DEPTH_WACH : integer;
attribute C_WR_DEPTH_WACH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 16;
attribute C_WR_DEPTH_WDCH : integer;
attribute C_WR_DEPTH_WDCH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 1024;
attribute C_WR_DEPTH_WRCH : integer;
attribute C_WR_DEPTH_WRCH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 16;
attribute C_WR_FREQ : integer;
attribute C_WR_FREQ of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 1;
attribute C_WR_PNTR_WIDTH : integer;
attribute C_WR_PNTR_WIDTH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 5;
attribute C_WR_PNTR_WIDTH_AXIS : integer;
attribute C_WR_PNTR_WIDTH_AXIS of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 10;
attribute C_WR_PNTR_WIDTH_RACH : integer;
attribute C_WR_PNTR_WIDTH_RACH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 4;
attribute C_WR_PNTR_WIDTH_RDCH : integer;
attribute C_WR_PNTR_WIDTH_RDCH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 10;
attribute C_WR_PNTR_WIDTH_WACH : integer;
attribute C_WR_PNTR_WIDTH_WACH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 4;
attribute C_WR_PNTR_WIDTH_WDCH : integer;
attribute C_WR_PNTR_WIDTH_WDCH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 10;
attribute C_WR_PNTR_WIDTH_WRCH : integer;
attribute C_WR_PNTR_WIDTH_WRCH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 4;
attribute C_WR_RESPONSE_LATENCY : integer;
attribute C_WR_RESPONSE_LATENCY of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is 1;
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ : entity is "fifo_generator_v13_1_3";
end \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\;
architecture STRUCTURE of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\ is
signal \<const0>\ : STD_LOGIC;
begin
almost_empty <= \<const0>\;
almost_full <= \<const0>\;
axi_ar_data_count(4) <= \<const0>\;
axi_ar_data_count(3) <= \<const0>\;
axi_ar_data_count(2) <= \<const0>\;
axi_ar_data_count(1) <= \<const0>\;
axi_ar_data_count(0) <= \<const0>\;
axi_ar_dbiterr <= \<const0>\;
axi_ar_overflow <= \<const0>\;
axi_ar_prog_empty <= \<const0>\;
axi_ar_prog_full <= \<const0>\;
axi_ar_rd_data_count(4) <= \<const0>\;
axi_ar_rd_data_count(3) <= \<const0>\;
axi_ar_rd_data_count(2) <= \<const0>\;
axi_ar_rd_data_count(1) <= \<const0>\;
axi_ar_rd_data_count(0) <= \<const0>\;
axi_ar_sbiterr <= \<const0>\;
axi_ar_underflow <= \<const0>\;
axi_ar_wr_data_count(4) <= \<const0>\;
axi_ar_wr_data_count(3) <= \<const0>\;
axi_ar_wr_data_count(2) <= \<const0>\;
axi_ar_wr_data_count(1) <= \<const0>\;
axi_ar_wr_data_count(0) <= \<const0>\;
axi_aw_data_count(4) <= \<const0>\;
axi_aw_data_count(3) <= \<const0>\;
axi_aw_data_count(2) <= \<const0>\;
axi_aw_data_count(1) <= \<const0>\;
axi_aw_data_count(0) <= \<const0>\;
axi_aw_dbiterr <= \<const0>\;
axi_aw_overflow <= \<const0>\;
axi_aw_prog_empty <= \<const0>\;
axi_aw_prog_full <= \<const0>\;
axi_aw_rd_data_count(4) <= \<const0>\;
axi_aw_rd_data_count(3) <= \<const0>\;
axi_aw_rd_data_count(2) <= \<const0>\;
axi_aw_rd_data_count(1) <= \<const0>\;
axi_aw_rd_data_count(0) <= \<const0>\;
axi_aw_sbiterr <= \<const0>\;
axi_aw_underflow <= \<const0>\;
axi_aw_wr_data_count(4) <= \<const0>\;
axi_aw_wr_data_count(3) <= \<const0>\;
axi_aw_wr_data_count(2) <= \<const0>\;
axi_aw_wr_data_count(1) <= \<const0>\;
axi_aw_wr_data_count(0) <= \<const0>\;
axi_b_data_count(4) <= \<const0>\;
axi_b_data_count(3) <= \<const0>\;
axi_b_data_count(2) <= \<const0>\;
axi_b_data_count(1) <= \<const0>\;
axi_b_data_count(0) <= \<const0>\;
axi_b_dbiterr <= \<const0>\;
axi_b_overflow <= \<const0>\;
axi_b_prog_empty <= \<const0>\;
axi_b_prog_full <= \<const0>\;
axi_b_rd_data_count(4) <= \<const0>\;
axi_b_rd_data_count(3) <= \<const0>\;
axi_b_rd_data_count(2) <= \<const0>\;
axi_b_rd_data_count(1) <= \<const0>\;
axi_b_rd_data_count(0) <= \<const0>\;
axi_b_sbiterr <= \<const0>\;
axi_b_underflow <= \<const0>\;
axi_b_wr_data_count(4) <= \<const0>\;
axi_b_wr_data_count(3) <= \<const0>\;
axi_b_wr_data_count(2) <= \<const0>\;
axi_b_wr_data_count(1) <= \<const0>\;
axi_b_wr_data_count(0) <= \<const0>\;
axi_r_data_count(10) <= \<const0>\;
axi_r_data_count(9) <= \<const0>\;
axi_r_data_count(8) <= \<const0>\;
axi_r_data_count(7) <= \<const0>\;
axi_r_data_count(6) <= \<const0>\;
axi_r_data_count(5) <= \<const0>\;
axi_r_data_count(4) <= \<const0>\;
axi_r_data_count(3) <= \<const0>\;
axi_r_data_count(2) <= \<const0>\;
axi_r_data_count(1) <= \<const0>\;
axi_r_data_count(0) <= \<const0>\;
axi_r_dbiterr <= \<const0>\;
axi_r_overflow <= \<const0>\;
axi_r_prog_empty <= \<const0>\;
axi_r_prog_full <= \<const0>\;
axi_r_rd_data_count(10) <= \<const0>\;
axi_r_rd_data_count(9) <= \<const0>\;
axi_r_rd_data_count(8) <= \<const0>\;
axi_r_rd_data_count(7) <= \<const0>\;
axi_r_rd_data_count(6) <= \<const0>\;
axi_r_rd_data_count(5) <= \<const0>\;
axi_r_rd_data_count(4) <= \<const0>\;
axi_r_rd_data_count(3) <= \<const0>\;
axi_r_rd_data_count(2) <= \<const0>\;
axi_r_rd_data_count(1) <= \<const0>\;
axi_r_rd_data_count(0) <= \<const0>\;
axi_r_sbiterr <= \<const0>\;
axi_r_underflow <= \<const0>\;
axi_r_wr_data_count(10) <= \<const0>\;
axi_r_wr_data_count(9) <= \<const0>\;
axi_r_wr_data_count(8) <= \<const0>\;
axi_r_wr_data_count(7) <= \<const0>\;
axi_r_wr_data_count(6) <= \<const0>\;
axi_r_wr_data_count(5) <= \<const0>\;
axi_r_wr_data_count(4) <= \<const0>\;
axi_r_wr_data_count(3) <= \<const0>\;
axi_r_wr_data_count(2) <= \<const0>\;
axi_r_wr_data_count(1) <= \<const0>\;
axi_r_wr_data_count(0) <= \<const0>\;
axi_w_data_count(10) <= \<const0>\;
axi_w_data_count(9) <= \<const0>\;
axi_w_data_count(8) <= \<const0>\;
axi_w_data_count(7) <= \<const0>\;
axi_w_data_count(6) <= \<const0>\;
axi_w_data_count(5) <= \<const0>\;
axi_w_data_count(4) <= \<const0>\;
axi_w_data_count(3) <= \<const0>\;
axi_w_data_count(2) <= \<const0>\;
axi_w_data_count(1) <= \<const0>\;
axi_w_data_count(0) <= \<const0>\;
axi_w_dbiterr <= \<const0>\;
axi_w_overflow <= \<const0>\;
axi_w_prog_empty <= \<const0>\;
axi_w_prog_full <= \<const0>\;
axi_w_rd_data_count(10) <= \<const0>\;
axi_w_rd_data_count(9) <= \<const0>\;
axi_w_rd_data_count(8) <= \<const0>\;
axi_w_rd_data_count(7) <= \<const0>\;
axi_w_rd_data_count(6) <= \<const0>\;
axi_w_rd_data_count(5) <= \<const0>\;
axi_w_rd_data_count(4) <= \<const0>\;
axi_w_rd_data_count(3) <= \<const0>\;
axi_w_rd_data_count(2) <= \<const0>\;
axi_w_rd_data_count(1) <= \<const0>\;
axi_w_rd_data_count(0) <= \<const0>\;
axi_w_sbiterr <= \<const0>\;
axi_w_underflow <= \<const0>\;
axi_w_wr_data_count(10) <= \<const0>\;
axi_w_wr_data_count(9) <= \<const0>\;
axi_w_wr_data_count(8) <= \<const0>\;
axi_w_wr_data_count(7) <= \<const0>\;
axi_w_wr_data_count(6) <= \<const0>\;
axi_w_wr_data_count(5) <= \<const0>\;
axi_w_wr_data_count(4) <= \<const0>\;
axi_w_wr_data_count(3) <= \<const0>\;
axi_w_wr_data_count(2) <= \<const0>\;
axi_w_wr_data_count(1) <= \<const0>\;
axi_w_wr_data_count(0) <= \<const0>\;
axis_data_count(10) <= \<const0>\;
axis_data_count(9) <= \<const0>\;
axis_data_count(8) <= \<const0>\;
axis_data_count(7) <= \<const0>\;
axis_data_count(6) <= \<const0>\;
axis_data_count(5) <= \<const0>\;
axis_data_count(4) <= \<const0>\;
axis_data_count(3) <= \<const0>\;
axis_data_count(2) <= \<const0>\;
axis_data_count(1) <= \<const0>\;
axis_data_count(0) <= \<const0>\;
axis_dbiterr <= \<const0>\;
axis_overflow <= \<const0>\;
axis_prog_empty <= \<const0>\;
axis_prog_full <= \<const0>\;
axis_rd_data_count(10) <= \<const0>\;
axis_rd_data_count(9) <= \<const0>\;
axis_rd_data_count(8) <= \<const0>\;
axis_rd_data_count(7) <= \<const0>\;
axis_rd_data_count(6) <= \<const0>\;
axis_rd_data_count(5) <= \<const0>\;
axis_rd_data_count(4) <= \<const0>\;
axis_rd_data_count(3) <= \<const0>\;
axis_rd_data_count(2) <= \<const0>\;
axis_rd_data_count(1) <= \<const0>\;
axis_rd_data_count(0) <= \<const0>\;
axis_sbiterr <= \<const0>\;
axis_underflow <= \<const0>\;
axis_wr_data_count(10) <= \<const0>\;
axis_wr_data_count(9) <= \<const0>\;
axis_wr_data_count(8) <= \<const0>\;
axis_wr_data_count(7) <= \<const0>\;
axis_wr_data_count(6) <= \<const0>\;
axis_wr_data_count(5) <= \<const0>\;
axis_wr_data_count(4) <= \<const0>\;
axis_wr_data_count(3) <= \<const0>\;
axis_wr_data_count(2) <= \<const0>\;
axis_wr_data_count(1) <= \<const0>\;
axis_wr_data_count(0) <= \<const0>\;
data_count(5) <= \<const0>\;
data_count(4) <= \<const0>\;
data_count(3) <= \<const0>\;
data_count(2) <= \<const0>\;
data_count(1) <= \<const0>\;
data_count(0) <= \<const0>\;
dbiterr <= \<const0>\;
m_axi_araddr(31) <= \<const0>\;
m_axi_araddr(30) <= \<const0>\;
m_axi_araddr(29) <= \<const0>\;
m_axi_araddr(28) <= \<const0>\;
m_axi_araddr(27) <= \<const0>\;
m_axi_araddr(26) <= \<const0>\;
m_axi_araddr(25) <= \<const0>\;
m_axi_araddr(24) <= \<const0>\;
m_axi_araddr(23) <= \<const0>\;
m_axi_araddr(22) <= \<const0>\;
m_axi_araddr(21) <= \<const0>\;
m_axi_araddr(20) <= \<const0>\;
m_axi_araddr(19) <= \<const0>\;
m_axi_araddr(18) <= \<const0>\;
m_axi_araddr(17) <= \<const0>\;
m_axi_araddr(16) <= \<const0>\;
m_axi_araddr(15) <= \<const0>\;
m_axi_araddr(14) <= \<const0>\;
m_axi_araddr(13) <= \<const0>\;
m_axi_araddr(12) <= \<const0>\;
m_axi_araddr(11) <= \<const0>\;
m_axi_araddr(10) <= \<const0>\;
m_axi_araddr(9) <= \<const0>\;
m_axi_araddr(8) <= \<const0>\;
m_axi_araddr(7) <= \<const0>\;
m_axi_araddr(6) <= \<const0>\;
m_axi_araddr(5) <= \<const0>\;
m_axi_araddr(4) <= \<const0>\;
m_axi_araddr(3) <= \<const0>\;
m_axi_araddr(2) <= \<const0>\;
m_axi_araddr(1) <= \<const0>\;
m_axi_araddr(0) <= \<const0>\;
m_axi_arburst(1) <= \<const0>\;
m_axi_arburst(0) <= \<const0>\;
m_axi_arcache(3) <= \<const0>\;
m_axi_arcache(2) <= \<const0>\;
m_axi_arcache(1) <= \<const0>\;
m_axi_arcache(0) <= \<const0>\;
m_axi_arid(3) <= \<const0>\;
m_axi_arid(2) <= \<const0>\;
m_axi_arid(1) <= \<const0>\;
m_axi_arid(0) <= \<const0>\;
m_axi_arlen(7) <= \<const0>\;
m_axi_arlen(6) <= \<const0>\;
m_axi_arlen(5) <= \<const0>\;
m_axi_arlen(4) <= \<const0>\;
m_axi_arlen(3) <= \<const0>\;
m_axi_arlen(2) <= \<const0>\;
m_axi_arlen(1) <= \<const0>\;
m_axi_arlen(0) <= \<const0>\;
m_axi_arlock(1) <= \<const0>\;
m_axi_arlock(0) <= \<const0>\;
m_axi_arprot(2) <= \<const0>\;
m_axi_arprot(1) <= \<const0>\;
m_axi_arprot(0) <= \<const0>\;
m_axi_arqos(3) <= \<const0>\;
m_axi_arqos(2) <= \<const0>\;
m_axi_arqos(1) <= \<const0>\;
m_axi_arqos(0) <= \<const0>\;
m_axi_arregion(3) <= \<const0>\;
m_axi_arregion(2) <= \<const0>\;
m_axi_arregion(1) <= \<const0>\;
m_axi_arregion(0) <= \<const0>\;
m_axi_arsize(2) <= \<const0>\;
m_axi_arsize(1) <= \<const0>\;
m_axi_arsize(0) <= \<const0>\;
m_axi_aruser(0) <= \<const0>\;
m_axi_arvalid <= \<const0>\;
m_axi_awaddr(31) <= \<const0>\;
m_axi_awaddr(30) <= \<const0>\;
m_axi_awaddr(29) <= \<const0>\;
m_axi_awaddr(28) <= \<const0>\;
m_axi_awaddr(27) <= \<const0>\;
m_axi_awaddr(26) <= \<const0>\;
m_axi_awaddr(25) <= \<const0>\;
m_axi_awaddr(24) <= \<const0>\;
m_axi_awaddr(23) <= \<const0>\;
m_axi_awaddr(22) <= \<const0>\;
m_axi_awaddr(21) <= \<const0>\;
m_axi_awaddr(20) <= \<const0>\;
m_axi_awaddr(19) <= \<const0>\;
m_axi_awaddr(18) <= \<const0>\;
m_axi_awaddr(17) <= \<const0>\;
m_axi_awaddr(16) <= \<const0>\;
m_axi_awaddr(15) <= \<const0>\;
m_axi_awaddr(14) <= \<const0>\;
m_axi_awaddr(13) <= \<const0>\;
m_axi_awaddr(12) <= \<const0>\;
m_axi_awaddr(11) <= \<const0>\;
m_axi_awaddr(10) <= \<const0>\;
m_axi_awaddr(9) <= \<const0>\;
m_axi_awaddr(8) <= \<const0>\;
m_axi_awaddr(7) <= \<const0>\;
m_axi_awaddr(6) <= \<const0>\;
m_axi_awaddr(5) <= \<const0>\;
m_axi_awaddr(4) <= \<const0>\;
m_axi_awaddr(3) <= \<const0>\;
m_axi_awaddr(2) <= \<const0>\;
m_axi_awaddr(1) <= \<const0>\;
m_axi_awaddr(0) <= \<const0>\;
m_axi_awburst(1) <= \<const0>\;
m_axi_awburst(0) <= \<const0>\;
m_axi_awcache(3) <= \<const0>\;
m_axi_awcache(2) <= \<const0>\;
m_axi_awcache(1) <= \<const0>\;
m_axi_awcache(0) <= \<const0>\;
m_axi_awid(3) <= \<const0>\;
m_axi_awid(2) <= \<const0>\;
m_axi_awid(1) <= \<const0>\;
m_axi_awid(0) <= \<const0>\;
m_axi_awlen(7) <= \<const0>\;
m_axi_awlen(6) <= \<const0>\;
m_axi_awlen(5) <= \<const0>\;
m_axi_awlen(4) <= \<const0>\;
m_axi_awlen(3) <= \<const0>\;
m_axi_awlen(2) <= \<const0>\;
m_axi_awlen(1) <= \<const0>\;
m_axi_awlen(0) <= \<const0>\;
m_axi_awlock(1) <= \<const0>\;
m_axi_awlock(0) <= \<const0>\;
m_axi_awprot(2) <= \<const0>\;
m_axi_awprot(1) <= \<const0>\;
m_axi_awprot(0) <= \<const0>\;
m_axi_awqos(3) <= \<const0>\;
m_axi_awqos(2) <= \<const0>\;
m_axi_awqos(1) <= \<const0>\;
m_axi_awqos(0) <= \<const0>\;
m_axi_awregion(3) <= \<const0>\;
m_axi_awregion(2) <= \<const0>\;
m_axi_awregion(1) <= \<const0>\;
m_axi_awregion(0) <= \<const0>\;
m_axi_awsize(2) <= \<const0>\;
m_axi_awsize(1) <= \<const0>\;
m_axi_awsize(0) <= \<const0>\;
m_axi_awuser(0) <= \<const0>\;
m_axi_awvalid <= \<const0>\;
m_axi_bready <= \<const0>\;
m_axi_rready <= \<const0>\;
m_axi_wdata(63) <= \<const0>\;
m_axi_wdata(62) <= \<const0>\;
m_axi_wdata(61) <= \<const0>\;
m_axi_wdata(60) <= \<const0>\;
m_axi_wdata(59) <= \<const0>\;
m_axi_wdata(58) <= \<const0>\;
m_axi_wdata(57) <= \<const0>\;
m_axi_wdata(56) <= \<const0>\;
m_axi_wdata(55) <= \<const0>\;
m_axi_wdata(54) <= \<const0>\;
m_axi_wdata(53) <= \<const0>\;
m_axi_wdata(52) <= \<const0>\;
m_axi_wdata(51) <= \<const0>\;
m_axi_wdata(50) <= \<const0>\;
m_axi_wdata(49) <= \<const0>\;
m_axi_wdata(48) <= \<const0>\;
m_axi_wdata(47) <= \<const0>\;
m_axi_wdata(46) <= \<const0>\;
m_axi_wdata(45) <= \<const0>\;
m_axi_wdata(44) <= \<const0>\;
m_axi_wdata(43) <= \<const0>\;
m_axi_wdata(42) <= \<const0>\;
m_axi_wdata(41) <= \<const0>\;
m_axi_wdata(40) <= \<const0>\;
m_axi_wdata(39) <= \<const0>\;
m_axi_wdata(38) <= \<const0>\;
m_axi_wdata(37) <= \<const0>\;
m_axi_wdata(36) <= \<const0>\;
m_axi_wdata(35) <= \<const0>\;
m_axi_wdata(34) <= \<const0>\;
m_axi_wdata(33) <= \<const0>\;
m_axi_wdata(32) <= \<const0>\;
m_axi_wdata(31) <= \<const0>\;
m_axi_wdata(30) <= \<const0>\;
m_axi_wdata(29) <= \<const0>\;
m_axi_wdata(28) <= \<const0>\;
m_axi_wdata(27) <= \<const0>\;
m_axi_wdata(26) <= \<const0>\;
m_axi_wdata(25) <= \<const0>\;
m_axi_wdata(24) <= \<const0>\;
m_axi_wdata(23) <= \<const0>\;
m_axi_wdata(22) <= \<const0>\;
m_axi_wdata(21) <= \<const0>\;
m_axi_wdata(20) <= \<const0>\;
m_axi_wdata(19) <= \<const0>\;
m_axi_wdata(18) <= \<const0>\;
m_axi_wdata(17) <= \<const0>\;
m_axi_wdata(16) <= \<const0>\;
m_axi_wdata(15) <= \<const0>\;
m_axi_wdata(14) <= \<const0>\;
m_axi_wdata(13) <= \<const0>\;
m_axi_wdata(12) <= \<const0>\;
m_axi_wdata(11) <= \<const0>\;
m_axi_wdata(10) <= \<const0>\;
m_axi_wdata(9) <= \<const0>\;
m_axi_wdata(8) <= \<const0>\;
m_axi_wdata(7) <= \<const0>\;
m_axi_wdata(6) <= \<const0>\;
m_axi_wdata(5) <= \<const0>\;
m_axi_wdata(4) <= \<const0>\;
m_axi_wdata(3) <= \<const0>\;
m_axi_wdata(2) <= \<const0>\;
m_axi_wdata(1) <= \<const0>\;
m_axi_wdata(0) <= \<const0>\;
m_axi_wid(3) <= \<const0>\;
m_axi_wid(2) <= \<const0>\;
m_axi_wid(1) <= \<const0>\;
m_axi_wid(0) <= \<const0>\;
m_axi_wlast <= \<const0>\;
m_axi_wstrb(7) <= \<const0>\;
m_axi_wstrb(6) <= \<const0>\;
m_axi_wstrb(5) <= \<const0>\;
m_axi_wstrb(4) <= \<const0>\;
m_axi_wstrb(3) <= \<const0>\;
m_axi_wstrb(2) <= \<const0>\;
m_axi_wstrb(1) <= \<const0>\;
m_axi_wstrb(0) <= \<const0>\;
m_axi_wuser(0) <= \<const0>\;
m_axi_wvalid <= \<const0>\;
m_axis_tdata(63) <= \<const0>\;
m_axis_tdata(62) <= \<const0>\;
m_axis_tdata(61) <= \<const0>\;
m_axis_tdata(60) <= \<const0>\;
m_axis_tdata(59) <= \<const0>\;
m_axis_tdata(58) <= \<const0>\;
m_axis_tdata(57) <= \<const0>\;
m_axis_tdata(56) <= \<const0>\;
m_axis_tdata(55) <= \<const0>\;
m_axis_tdata(54) <= \<const0>\;
m_axis_tdata(53) <= \<const0>\;
m_axis_tdata(52) <= \<const0>\;
m_axis_tdata(51) <= \<const0>\;
m_axis_tdata(50) <= \<const0>\;
m_axis_tdata(49) <= \<const0>\;
m_axis_tdata(48) <= \<const0>\;
m_axis_tdata(47) <= \<const0>\;
m_axis_tdata(46) <= \<const0>\;
m_axis_tdata(45) <= \<const0>\;
m_axis_tdata(44) <= \<const0>\;
m_axis_tdata(43) <= \<const0>\;
m_axis_tdata(42) <= \<const0>\;
m_axis_tdata(41) <= \<const0>\;
m_axis_tdata(40) <= \<const0>\;
m_axis_tdata(39) <= \<const0>\;
m_axis_tdata(38) <= \<const0>\;
m_axis_tdata(37) <= \<const0>\;
m_axis_tdata(36) <= \<const0>\;
m_axis_tdata(35) <= \<const0>\;
m_axis_tdata(34) <= \<const0>\;
m_axis_tdata(33) <= \<const0>\;
m_axis_tdata(32) <= \<const0>\;
m_axis_tdata(31) <= \<const0>\;
m_axis_tdata(30) <= \<const0>\;
m_axis_tdata(29) <= \<const0>\;
m_axis_tdata(28) <= \<const0>\;
m_axis_tdata(27) <= \<const0>\;
m_axis_tdata(26) <= \<const0>\;
m_axis_tdata(25) <= \<const0>\;
m_axis_tdata(24) <= \<const0>\;
m_axis_tdata(23) <= \<const0>\;
m_axis_tdata(22) <= \<const0>\;
m_axis_tdata(21) <= \<const0>\;
m_axis_tdata(20) <= \<const0>\;
m_axis_tdata(19) <= \<const0>\;
m_axis_tdata(18) <= \<const0>\;
m_axis_tdata(17) <= \<const0>\;
m_axis_tdata(16) <= \<const0>\;
m_axis_tdata(15) <= \<const0>\;
m_axis_tdata(14) <= \<const0>\;
m_axis_tdata(13) <= \<const0>\;
m_axis_tdata(12) <= \<const0>\;
m_axis_tdata(11) <= \<const0>\;
m_axis_tdata(10) <= \<const0>\;
m_axis_tdata(9) <= \<const0>\;
m_axis_tdata(8) <= \<const0>\;
m_axis_tdata(7) <= \<const0>\;
m_axis_tdata(6) <= \<const0>\;
m_axis_tdata(5) <= \<const0>\;
m_axis_tdata(4) <= \<const0>\;
m_axis_tdata(3) <= \<const0>\;
m_axis_tdata(2) <= \<const0>\;
m_axis_tdata(1) <= \<const0>\;
m_axis_tdata(0) <= \<const0>\;
m_axis_tdest(3) <= \<const0>\;
m_axis_tdest(2) <= \<const0>\;
m_axis_tdest(1) <= \<const0>\;
m_axis_tdest(0) <= \<const0>\;
m_axis_tid(7) <= \<const0>\;
m_axis_tid(6) <= \<const0>\;
m_axis_tid(5) <= \<const0>\;
m_axis_tid(4) <= \<const0>\;
m_axis_tid(3) <= \<const0>\;
m_axis_tid(2) <= \<const0>\;
m_axis_tid(1) <= \<const0>\;
m_axis_tid(0) <= \<const0>\;
m_axis_tkeep(3) <= \<const0>\;
m_axis_tkeep(2) <= \<const0>\;
m_axis_tkeep(1) <= \<const0>\;
m_axis_tkeep(0) <= \<const0>\;
m_axis_tlast <= \<const0>\;
m_axis_tstrb(3) <= \<const0>\;
m_axis_tstrb(2) <= \<const0>\;
m_axis_tstrb(1) <= \<const0>\;
m_axis_tstrb(0) <= \<const0>\;
m_axis_tuser(3) <= \<const0>\;
m_axis_tuser(2) <= \<const0>\;
m_axis_tuser(1) <= \<const0>\;
m_axis_tuser(0) <= \<const0>\;
m_axis_tvalid <= \<const0>\;
overflow <= \<const0>\;
prog_empty <= \<const0>\;
prog_full <= \<const0>\;
rd_data_count(5) <= \<const0>\;
rd_data_count(4) <= \<const0>\;
rd_data_count(3) <= \<const0>\;
rd_data_count(2) <= \<const0>\;
rd_data_count(1) <= \<const0>\;
rd_data_count(0) <= \<const0>\;
rd_rst_busy <= \<const0>\;
s_axi_arready <= \<const0>\;
s_axi_awready <= \<const0>\;
s_axi_bid(3) <= \<const0>\;
s_axi_bid(2) <= \<const0>\;
s_axi_bid(1) <= \<const0>\;
s_axi_bid(0) <= \<const0>\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_buser(0) <= \<const0>\;
s_axi_bvalid <= \<const0>\;
s_axi_rdata(63) <= \<const0>\;
s_axi_rdata(62) <= \<const0>\;
s_axi_rdata(61) <= \<const0>\;
s_axi_rdata(60) <= \<const0>\;
s_axi_rdata(59) <= \<const0>\;
s_axi_rdata(58) <= \<const0>\;
s_axi_rdata(57) <= \<const0>\;
s_axi_rdata(56) <= \<const0>\;
s_axi_rdata(55) <= \<const0>\;
s_axi_rdata(54) <= \<const0>\;
s_axi_rdata(53) <= \<const0>\;
s_axi_rdata(52) <= \<const0>\;
s_axi_rdata(51) <= \<const0>\;
s_axi_rdata(50) <= \<const0>\;
s_axi_rdata(49) <= \<const0>\;
s_axi_rdata(48) <= \<const0>\;
s_axi_rdata(47) <= \<const0>\;
s_axi_rdata(46) <= \<const0>\;
s_axi_rdata(45) <= \<const0>\;
s_axi_rdata(44) <= \<const0>\;
s_axi_rdata(43) <= \<const0>\;
s_axi_rdata(42) <= \<const0>\;
s_axi_rdata(41) <= \<const0>\;
s_axi_rdata(40) <= \<const0>\;
s_axi_rdata(39) <= \<const0>\;
s_axi_rdata(38) <= \<const0>\;
s_axi_rdata(37) <= \<const0>\;
s_axi_rdata(36) <= \<const0>\;
s_axi_rdata(35) <= \<const0>\;
s_axi_rdata(34) <= \<const0>\;
s_axi_rdata(33) <= \<const0>\;
s_axi_rdata(32) <= \<const0>\;
s_axi_rdata(31) <= \<const0>\;
s_axi_rdata(30) <= \<const0>\;
s_axi_rdata(29) <= \<const0>\;
s_axi_rdata(28) <= \<const0>\;
s_axi_rdata(27) <= \<const0>\;
s_axi_rdata(26) <= \<const0>\;
s_axi_rdata(25) <= \<const0>\;
s_axi_rdata(24) <= \<const0>\;
s_axi_rdata(23) <= \<const0>\;
s_axi_rdata(22) <= \<const0>\;
s_axi_rdata(21) <= \<const0>\;
s_axi_rdata(20) <= \<const0>\;
s_axi_rdata(19) <= \<const0>\;
s_axi_rdata(18) <= \<const0>\;
s_axi_rdata(17) <= \<const0>\;
s_axi_rdata(16) <= \<const0>\;
s_axi_rdata(15) <= \<const0>\;
s_axi_rdata(14) <= \<const0>\;
s_axi_rdata(13) <= \<const0>\;
s_axi_rdata(12) <= \<const0>\;
s_axi_rdata(11) <= \<const0>\;
s_axi_rdata(10) <= \<const0>\;
s_axi_rdata(9) <= \<const0>\;
s_axi_rdata(8) <= \<const0>\;
s_axi_rdata(7) <= \<const0>\;
s_axi_rdata(6) <= \<const0>\;
s_axi_rdata(5) <= \<const0>\;
s_axi_rdata(4) <= \<const0>\;
s_axi_rdata(3) <= \<const0>\;
s_axi_rdata(2) <= \<const0>\;
s_axi_rdata(1) <= \<const0>\;
s_axi_rdata(0) <= \<const0>\;
s_axi_rid(3) <= \<const0>\;
s_axi_rid(2) <= \<const0>\;
s_axi_rid(1) <= \<const0>\;
s_axi_rid(0) <= \<const0>\;
s_axi_rlast <= \<const0>\;
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
s_axi_ruser(0) <= \<const0>\;
s_axi_rvalid <= \<const0>\;
s_axi_wready <= \<const0>\;
s_axis_tready <= \<const0>\;
sbiterr <= \<const0>\;
underflow <= \<const0>\;
valid <= \<const0>\;
wr_ack <= \<const0>\;
wr_data_count(5) <= \<const0>\;
wr_data_count(4) <= \<const0>\;
wr_data_count(3) <= \<const0>\;
wr_data_count(2) <= \<const0>\;
wr_data_count(1) <= \<const0>\;
wr_data_count(0) <= \<const0>\;
wr_rst_busy <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
inst_fifo_gen: entity work.\system_auto_pc_1_fifo_generator_v13_1_3_synth__parameterized0\
port map (
clk => clk,
din(4 downto 0) => din(4 downto 0),
dout(4 downto 0) => dout(4 downto 0),
empty => empty,
full => full,
rd_en => rd_en,
rst => rst,
wr_en => wr_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ is
port (
backup : in STD_LOGIC;
backup_marker : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
srst : in STD_LOGIC;
wr_clk : in STD_LOGIC;
wr_rst : in STD_LOGIC;
rd_clk : in STD_LOGIC;
rd_rst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 0 to 0 );
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
prog_empty_thresh : in STD_LOGIC_VECTOR ( 4 downto 0 );
prog_empty_thresh_assert : in STD_LOGIC_VECTOR ( 4 downto 0 );
prog_empty_thresh_negate : in STD_LOGIC_VECTOR ( 4 downto 0 );
prog_full_thresh : in STD_LOGIC_VECTOR ( 4 downto 0 );
prog_full_thresh_assert : in STD_LOGIC_VECTOR ( 4 downto 0 );
prog_full_thresh_negate : in STD_LOGIC_VECTOR ( 4 downto 0 );
int_clk : in STD_LOGIC;
injectdbiterr : in STD_LOGIC;
injectsbiterr : in STD_LOGIC;
sleep : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 0 to 0 );
full : out STD_LOGIC;
almost_full : out STD_LOGIC;
wr_ack : out STD_LOGIC;
overflow : out STD_LOGIC;
empty : out STD_LOGIC;
almost_empty : out STD_LOGIC;
valid : out STD_LOGIC;
underflow : out STD_LOGIC;
data_count : out STD_LOGIC_VECTOR ( 5 downto 0 );
rd_data_count : out STD_LOGIC_VECTOR ( 5 downto 0 );
wr_data_count : out STD_LOGIC_VECTOR ( 5 downto 0 );
prog_full : out STD_LOGIC;
prog_empty : out STD_LOGIC;
sbiterr : out STD_LOGIC;
dbiterr : out STD_LOGIC;
wr_rst_busy : out STD_LOGIC;
rd_rst_busy : out STD_LOGIC;
m_aclk : in STD_LOGIC;
s_aclk : in STD_LOGIC;
s_aresetn : in STD_LOGIC;
m_aclk_en : in STD_LOGIC;
s_aclk_en : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_buser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
m_axi_awid : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wid : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_wlast : out STD_LOGIC;
m_axi_wuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bid : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_buser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_aruser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_ruser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_arid : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_aruser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_ruser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC;
s_axis_tvalid : in STD_LOGIC;
s_axis_tready : out STD_LOGIC;
s_axis_tdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
s_axis_tstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axis_tkeep : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axis_tlast : in STD_LOGIC;
s_axis_tid : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axis_tdest : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axis_tuser : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axis_tvalid : out STD_LOGIC;
m_axis_tready : in STD_LOGIC;
m_axis_tdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
m_axis_tstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axis_tkeep : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axis_tlast : out STD_LOGIC;
m_axis_tid : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axis_tdest : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axis_tuser : out STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_injectsbiterr : in STD_LOGIC;
axi_aw_injectdbiterr : in STD_LOGIC;
axi_aw_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_sbiterr : out STD_LOGIC;
axi_aw_dbiterr : out STD_LOGIC;
axi_aw_overflow : out STD_LOGIC;
axi_aw_underflow : out STD_LOGIC;
axi_aw_prog_full : out STD_LOGIC;
axi_aw_prog_empty : out STD_LOGIC;
axi_w_injectsbiterr : in STD_LOGIC;
axi_w_injectdbiterr : in STD_LOGIC;
axi_w_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_w_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_w_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_w_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_w_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_w_sbiterr : out STD_LOGIC;
axi_w_dbiterr : out STD_LOGIC;
axi_w_overflow : out STD_LOGIC;
axi_w_underflow : out STD_LOGIC;
axi_w_prog_full : out STD_LOGIC;
axi_w_prog_empty : out STD_LOGIC;
axi_b_injectsbiterr : in STD_LOGIC;
axi_b_injectdbiterr : in STD_LOGIC;
axi_b_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_b_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_b_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_sbiterr : out STD_LOGIC;
axi_b_dbiterr : out STD_LOGIC;
axi_b_overflow : out STD_LOGIC;
axi_b_underflow : out STD_LOGIC;
axi_b_prog_full : out STD_LOGIC;
axi_b_prog_empty : out STD_LOGIC;
axi_ar_injectsbiterr : in STD_LOGIC;
axi_ar_injectdbiterr : in STD_LOGIC;
axi_ar_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_ar_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_ar_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_sbiterr : out STD_LOGIC;
axi_ar_dbiterr : out STD_LOGIC;
axi_ar_overflow : out STD_LOGIC;
axi_ar_underflow : out STD_LOGIC;
axi_ar_prog_full : out STD_LOGIC;
axi_ar_prog_empty : out STD_LOGIC;
axi_r_injectsbiterr : in STD_LOGIC;
axi_r_injectdbiterr : in STD_LOGIC;
axi_r_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_r_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_r_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_r_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_r_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_r_sbiterr : out STD_LOGIC;
axi_r_dbiterr : out STD_LOGIC;
axi_r_overflow : out STD_LOGIC;
axi_r_underflow : out STD_LOGIC;
axi_r_prog_full : out STD_LOGIC;
axi_r_prog_empty : out STD_LOGIC;
axis_injectsbiterr : in STD_LOGIC;
axis_injectdbiterr : in STD_LOGIC;
axis_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axis_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axis_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_sbiterr : out STD_LOGIC;
axis_dbiterr : out STD_LOGIC;
axis_overflow : out STD_LOGIC;
axis_underflow : out STD_LOGIC;
axis_prog_full : out STD_LOGIC;
axis_prog_empty : out STD_LOGIC
);
attribute C_ADD_NGC_CONSTRAINT : integer;
attribute C_ADD_NGC_CONSTRAINT of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_APPLICATION_TYPE_AXIS : integer;
attribute C_APPLICATION_TYPE_AXIS of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_APPLICATION_TYPE_RACH : integer;
attribute C_APPLICATION_TYPE_RACH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_APPLICATION_TYPE_RDCH : integer;
attribute C_APPLICATION_TYPE_RDCH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_APPLICATION_TYPE_WACH : integer;
attribute C_APPLICATION_TYPE_WACH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_APPLICATION_TYPE_WDCH : integer;
attribute C_APPLICATION_TYPE_WDCH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_APPLICATION_TYPE_WRCH : integer;
attribute C_APPLICATION_TYPE_WRCH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_AXIS_TDATA_WIDTH : integer;
attribute C_AXIS_TDATA_WIDTH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 64;
attribute C_AXIS_TDEST_WIDTH : integer;
attribute C_AXIS_TDEST_WIDTH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 4;
attribute C_AXIS_TID_WIDTH : integer;
attribute C_AXIS_TID_WIDTH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 8;
attribute C_AXIS_TKEEP_WIDTH : integer;
attribute C_AXIS_TKEEP_WIDTH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 4;
attribute C_AXIS_TSTRB_WIDTH : integer;
attribute C_AXIS_TSTRB_WIDTH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 4;
attribute C_AXIS_TUSER_WIDTH : integer;
attribute C_AXIS_TUSER_WIDTH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 4;
attribute C_AXIS_TYPE : integer;
attribute C_AXIS_TYPE of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 64;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 4;
attribute C_AXI_LEN_WIDTH : integer;
attribute C_AXI_LEN_WIDTH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 8;
attribute C_AXI_LOCK_WIDTH : integer;
attribute C_AXI_LOCK_WIDTH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 2;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 1;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 1;
attribute C_COMMON_CLOCK : integer;
attribute C_COMMON_CLOCK of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 1;
attribute C_COUNT_TYPE : integer;
attribute C_COUNT_TYPE of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_DATA_COUNT_WIDTH : integer;
attribute C_DATA_COUNT_WIDTH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 6;
attribute C_DEFAULT_VALUE : string;
attribute C_DEFAULT_VALUE of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is "BlankString";
attribute C_DIN_WIDTH : integer;
attribute C_DIN_WIDTH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 1;
attribute C_DIN_WIDTH_AXIS : integer;
attribute C_DIN_WIDTH_AXIS of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 1;
attribute C_DIN_WIDTH_RACH : integer;
attribute C_DIN_WIDTH_RACH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 32;
attribute C_DIN_WIDTH_RDCH : integer;
attribute C_DIN_WIDTH_RDCH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 64;
attribute C_DIN_WIDTH_WACH : integer;
attribute C_DIN_WIDTH_WACH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 32;
attribute C_DIN_WIDTH_WDCH : integer;
attribute C_DIN_WIDTH_WDCH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 64;
attribute C_DIN_WIDTH_WRCH : integer;
attribute C_DIN_WIDTH_WRCH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 2;
attribute C_DOUT_RST_VAL : string;
attribute C_DOUT_RST_VAL of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is "0";
attribute C_DOUT_WIDTH : integer;
attribute C_DOUT_WIDTH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 1;
attribute C_ENABLE_RLOCS : integer;
attribute C_ENABLE_RLOCS of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_ENABLE_RST_SYNC : integer;
attribute C_ENABLE_RST_SYNC of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 1;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_ERROR_INJECTION_TYPE : integer;
attribute C_ERROR_INJECTION_TYPE of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_ERROR_INJECTION_TYPE_AXIS : integer;
attribute C_ERROR_INJECTION_TYPE_AXIS of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_ERROR_INJECTION_TYPE_RACH : integer;
attribute C_ERROR_INJECTION_TYPE_RACH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_ERROR_INJECTION_TYPE_RDCH : integer;
attribute C_ERROR_INJECTION_TYPE_RDCH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WACH : integer;
attribute C_ERROR_INJECTION_TYPE_WACH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WDCH : integer;
attribute C_ERROR_INJECTION_TYPE_WDCH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WRCH : integer;
attribute C_ERROR_INJECTION_TYPE_WRCH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is "zynq";
attribute C_FULL_FLAGS_RST_VAL : integer;
attribute C_FULL_FLAGS_RST_VAL of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_HAS_ALMOST_EMPTY : integer;
attribute C_HAS_ALMOST_EMPTY of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_HAS_ALMOST_FULL : integer;
attribute C_HAS_ALMOST_FULL of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_HAS_AXIS_TDATA : integer;
attribute C_HAS_AXIS_TDATA of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_HAS_AXIS_TDEST : integer;
attribute C_HAS_AXIS_TDEST of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_HAS_AXIS_TID : integer;
attribute C_HAS_AXIS_TID of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_HAS_AXIS_TKEEP : integer;
attribute C_HAS_AXIS_TKEEP of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_HAS_AXIS_TLAST : integer;
attribute C_HAS_AXIS_TLAST of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_HAS_AXIS_TREADY : integer;
attribute C_HAS_AXIS_TREADY of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 1;
attribute C_HAS_AXIS_TSTRB : integer;
attribute C_HAS_AXIS_TSTRB of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_HAS_AXIS_TUSER : integer;
attribute C_HAS_AXIS_TUSER of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_HAS_AXI_ARUSER : integer;
attribute C_HAS_AXI_ARUSER of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_HAS_AXI_AWUSER : integer;
attribute C_HAS_AXI_AWUSER of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_HAS_AXI_BUSER : integer;
attribute C_HAS_AXI_BUSER of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_HAS_AXI_RD_CHANNEL : integer;
attribute C_HAS_AXI_RD_CHANNEL of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_HAS_AXI_RUSER : integer;
attribute C_HAS_AXI_RUSER of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_HAS_AXI_WR_CHANNEL : integer;
attribute C_HAS_AXI_WR_CHANNEL of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_HAS_AXI_WUSER : integer;
attribute C_HAS_AXI_WUSER of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_HAS_BACKUP : integer;
attribute C_HAS_BACKUP of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_HAS_DATA_COUNT : integer;
attribute C_HAS_DATA_COUNT of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_HAS_DATA_COUNTS_AXIS : integer;
attribute C_HAS_DATA_COUNTS_AXIS of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_HAS_DATA_COUNTS_RACH : integer;
attribute C_HAS_DATA_COUNTS_RACH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_HAS_DATA_COUNTS_RDCH : integer;
attribute C_HAS_DATA_COUNTS_RDCH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_HAS_DATA_COUNTS_WACH : integer;
attribute C_HAS_DATA_COUNTS_WACH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_HAS_DATA_COUNTS_WDCH : integer;
attribute C_HAS_DATA_COUNTS_WDCH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_HAS_DATA_COUNTS_WRCH : integer;
attribute C_HAS_DATA_COUNTS_WRCH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_HAS_INT_CLK : integer;
attribute C_HAS_INT_CLK of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_HAS_MASTER_CE : integer;
attribute C_HAS_MASTER_CE of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_HAS_MEMINIT_FILE : integer;
attribute C_HAS_MEMINIT_FILE of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_HAS_OVERFLOW : integer;
attribute C_HAS_OVERFLOW of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_HAS_PROG_FLAGS_AXIS : integer;
attribute C_HAS_PROG_FLAGS_AXIS of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_HAS_PROG_FLAGS_RACH : integer;
attribute C_HAS_PROG_FLAGS_RACH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_HAS_PROG_FLAGS_RDCH : integer;
attribute C_HAS_PROG_FLAGS_RDCH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_HAS_PROG_FLAGS_WACH : integer;
attribute C_HAS_PROG_FLAGS_WACH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_HAS_PROG_FLAGS_WDCH : integer;
attribute C_HAS_PROG_FLAGS_WDCH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_HAS_PROG_FLAGS_WRCH : integer;
attribute C_HAS_PROG_FLAGS_WRCH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_HAS_RD_DATA_COUNT : integer;
attribute C_HAS_RD_DATA_COUNT of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_HAS_RD_RST : integer;
attribute C_HAS_RD_RST of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_HAS_RST : integer;
attribute C_HAS_RST of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 1;
attribute C_HAS_SLAVE_CE : integer;
attribute C_HAS_SLAVE_CE of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_HAS_SRST : integer;
attribute C_HAS_SRST of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_HAS_UNDERFLOW : integer;
attribute C_HAS_UNDERFLOW of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_HAS_VALID : integer;
attribute C_HAS_VALID of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_HAS_WR_ACK : integer;
attribute C_HAS_WR_ACK of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_HAS_WR_DATA_COUNT : integer;
attribute C_HAS_WR_DATA_COUNT of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_HAS_WR_RST : integer;
attribute C_HAS_WR_RST of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_IMPLEMENTATION_TYPE : integer;
attribute C_IMPLEMENTATION_TYPE of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_IMPLEMENTATION_TYPE_AXIS : integer;
attribute C_IMPLEMENTATION_TYPE_AXIS of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 1;
attribute C_IMPLEMENTATION_TYPE_RACH : integer;
attribute C_IMPLEMENTATION_TYPE_RACH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 1;
attribute C_IMPLEMENTATION_TYPE_RDCH : integer;
attribute C_IMPLEMENTATION_TYPE_RDCH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 1;
attribute C_IMPLEMENTATION_TYPE_WACH : integer;
attribute C_IMPLEMENTATION_TYPE_WACH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 1;
attribute C_IMPLEMENTATION_TYPE_WDCH : integer;
attribute C_IMPLEMENTATION_TYPE_WDCH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 1;
attribute C_IMPLEMENTATION_TYPE_WRCH : integer;
attribute C_IMPLEMENTATION_TYPE_WRCH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 1;
attribute C_INIT_WR_PNTR_VAL : integer;
attribute C_INIT_WR_PNTR_VAL of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_MEMORY_TYPE : integer;
attribute C_MEMORY_TYPE of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 2;
attribute C_MIF_FILE_NAME : string;
attribute C_MIF_FILE_NAME of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is "BlankString";
attribute C_MSGON_VAL : integer;
attribute C_MSGON_VAL of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 1;
attribute C_OPTIMIZATION_MODE : integer;
attribute C_OPTIMIZATION_MODE of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_OVERFLOW_LOW : integer;
attribute C_OVERFLOW_LOW of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_POWER_SAVING_MODE : integer;
attribute C_POWER_SAVING_MODE of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_PRELOAD_LATENCY : integer;
attribute C_PRELOAD_LATENCY of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_PRELOAD_REGS : integer;
attribute C_PRELOAD_REGS of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 1;
attribute C_PRIM_FIFO_TYPE : string;
attribute C_PRIM_FIFO_TYPE of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_AXIS : string;
attribute C_PRIM_FIFO_TYPE_AXIS of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_RACH : string;
attribute C_PRIM_FIFO_TYPE_RACH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_RDCH : string;
attribute C_PRIM_FIFO_TYPE_RDCH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_WACH : string;
attribute C_PRIM_FIFO_TYPE_WACH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_WDCH : string;
attribute C_PRIM_FIFO_TYPE_WDCH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_WRCH : string;
attribute C_PRIM_FIFO_TYPE_WRCH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is "512x36";
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 4;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 1022;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL : integer;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 5;
attribute C_PROG_EMPTY_TYPE : integer;
attribute C_PROG_EMPTY_TYPE of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_PROG_EMPTY_TYPE_AXIS : integer;
attribute C_PROG_EMPTY_TYPE_AXIS of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_PROG_EMPTY_TYPE_RACH : integer;
attribute C_PROG_EMPTY_TYPE_RACH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_PROG_EMPTY_TYPE_RDCH : integer;
attribute C_PROG_EMPTY_TYPE_RDCH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_PROG_EMPTY_TYPE_WACH : integer;
attribute C_PROG_EMPTY_TYPE_WACH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_PROG_EMPTY_TYPE_WDCH : integer;
attribute C_PROG_EMPTY_TYPE_WDCH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_PROG_EMPTY_TYPE_WRCH : integer;
attribute C_PROG_EMPTY_TYPE_WRCH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_PROG_FULL_THRESH_ASSERT_VAL : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 31;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 1023;
attribute C_PROG_FULL_THRESH_NEGATE_VAL : integer;
attribute C_PROG_FULL_THRESH_NEGATE_VAL of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 30;
attribute C_PROG_FULL_TYPE : integer;
attribute C_PROG_FULL_TYPE of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_PROG_FULL_TYPE_AXIS : integer;
attribute C_PROG_FULL_TYPE_AXIS of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_PROG_FULL_TYPE_RACH : integer;
attribute C_PROG_FULL_TYPE_RACH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_PROG_FULL_TYPE_RDCH : integer;
attribute C_PROG_FULL_TYPE_RDCH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_PROG_FULL_TYPE_WACH : integer;
attribute C_PROG_FULL_TYPE_WACH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_PROG_FULL_TYPE_WDCH : integer;
attribute C_PROG_FULL_TYPE_WDCH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_PROG_FULL_TYPE_WRCH : integer;
attribute C_PROG_FULL_TYPE_WRCH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_RACH_TYPE : integer;
attribute C_RACH_TYPE of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_RDCH_TYPE : integer;
attribute C_RDCH_TYPE of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_RD_DATA_COUNT_WIDTH : integer;
attribute C_RD_DATA_COUNT_WIDTH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 6;
attribute C_RD_DEPTH : integer;
attribute C_RD_DEPTH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 32;
attribute C_RD_FREQ : integer;
attribute C_RD_FREQ of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 1;
attribute C_RD_PNTR_WIDTH : integer;
attribute C_RD_PNTR_WIDTH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 5;
attribute C_REG_SLICE_MODE_AXIS : integer;
attribute C_REG_SLICE_MODE_AXIS of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_REG_SLICE_MODE_RACH : integer;
attribute C_REG_SLICE_MODE_RACH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_REG_SLICE_MODE_RDCH : integer;
attribute C_REG_SLICE_MODE_RDCH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_REG_SLICE_MODE_WACH : integer;
attribute C_REG_SLICE_MODE_WACH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_REG_SLICE_MODE_WDCH : integer;
attribute C_REG_SLICE_MODE_WDCH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_REG_SLICE_MODE_WRCH : integer;
attribute C_REG_SLICE_MODE_WRCH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_SELECT_XPM : integer;
attribute C_SELECT_XPM of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_SYNCHRONIZER_STAGE : integer;
attribute C_SYNCHRONIZER_STAGE of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 3;
attribute C_UNDERFLOW_LOW : integer;
attribute C_UNDERFLOW_LOW of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_USE_COMMON_OVERFLOW : integer;
attribute C_USE_COMMON_OVERFLOW of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_USE_COMMON_UNDERFLOW : integer;
attribute C_USE_COMMON_UNDERFLOW of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_USE_DEFAULT_SETTINGS : integer;
attribute C_USE_DEFAULT_SETTINGS of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_USE_DOUT_RST : integer;
attribute C_USE_DOUT_RST of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_USE_ECC_AXIS : integer;
attribute C_USE_ECC_AXIS of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_USE_ECC_RACH : integer;
attribute C_USE_ECC_RACH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_USE_ECC_RDCH : integer;
attribute C_USE_ECC_RDCH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_USE_ECC_WACH : integer;
attribute C_USE_ECC_WACH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_USE_ECC_WDCH : integer;
attribute C_USE_ECC_WDCH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_USE_ECC_WRCH : integer;
attribute C_USE_ECC_WRCH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_USE_EMBEDDED_REG : integer;
attribute C_USE_EMBEDDED_REG of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_USE_FIFO16_FLAGS : integer;
attribute C_USE_FIFO16_FLAGS of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_USE_FWFT_DATA_COUNT : integer;
attribute C_USE_FWFT_DATA_COUNT of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 1;
attribute C_USE_PIPELINE_REG : integer;
attribute C_USE_PIPELINE_REG of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_VALID_LOW : integer;
attribute C_VALID_LOW of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_WACH_TYPE : integer;
attribute C_WACH_TYPE of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_WDCH_TYPE : integer;
attribute C_WDCH_TYPE of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_WRCH_TYPE : integer;
attribute C_WRCH_TYPE of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_WR_ACK_LOW : integer;
attribute C_WR_ACK_LOW of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 0;
attribute C_WR_DATA_COUNT_WIDTH : integer;
attribute C_WR_DATA_COUNT_WIDTH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 6;
attribute C_WR_DEPTH : integer;
attribute C_WR_DEPTH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 32;
attribute C_WR_DEPTH_AXIS : integer;
attribute C_WR_DEPTH_AXIS of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 1024;
attribute C_WR_DEPTH_RACH : integer;
attribute C_WR_DEPTH_RACH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 16;
attribute C_WR_DEPTH_RDCH : integer;
attribute C_WR_DEPTH_RDCH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 1024;
attribute C_WR_DEPTH_WACH : integer;
attribute C_WR_DEPTH_WACH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 16;
attribute C_WR_DEPTH_WDCH : integer;
attribute C_WR_DEPTH_WDCH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 1024;
attribute C_WR_DEPTH_WRCH : integer;
attribute C_WR_DEPTH_WRCH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 16;
attribute C_WR_FREQ : integer;
attribute C_WR_FREQ of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 1;
attribute C_WR_PNTR_WIDTH : integer;
attribute C_WR_PNTR_WIDTH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 5;
attribute C_WR_PNTR_WIDTH_AXIS : integer;
attribute C_WR_PNTR_WIDTH_AXIS of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 10;
attribute C_WR_PNTR_WIDTH_RACH : integer;
attribute C_WR_PNTR_WIDTH_RACH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 4;
attribute C_WR_PNTR_WIDTH_RDCH : integer;
attribute C_WR_PNTR_WIDTH_RDCH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 10;
attribute C_WR_PNTR_WIDTH_WACH : integer;
attribute C_WR_PNTR_WIDTH_WACH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 4;
attribute C_WR_PNTR_WIDTH_WDCH : integer;
attribute C_WR_PNTR_WIDTH_WDCH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 10;
attribute C_WR_PNTR_WIDTH_WRCH : integer;
attribute C_WR_PNTR_WIDTH_WRCH of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 4;
attribute C_WR_RESPONSE_LATENCY : integer;
attribute C_WR_RESPONSE_LATENCY of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is 1;
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ : entity is "fifo_generator_v13_1_3";
end \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\;
architecture STRUCTURE of \system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\ is
signal \<const0>\ : STD_LOGIC;
begin
almost_empty <= \<const0>\;
almost_full <= \<const0>\;
axi_ar_data_count(4) <= \<const0>\;
axi_ar_data_count(3) <= \<const0>\;
axi_ar_data_count(2) <= \<const0>\;
axi_ar_data_count(1) <= \<const0>\;
axi_ar_data_count(0) <= \<const0>\;
axi_ar_dbiterr <= \<const0>\;
axi_ar_overflow <= \<const0>\;
axi_ar_prog_empty <= \<const0>\;
axi_ar_prog_full <= \<const0>\;
axi_ar_rd_data_count(4) <= \<const0>\;
axi_ar_rd_data_count(3) <= \<const0>\;
axi_ar_rd_data_count(2) <= \<const0>\;
axi_ar_rd_data_count(1) <= \<const0>\;
axi_ar_rd_data_count(0) <= \<const0>\;
axi_ar_sbiterr <= \<const0>\;
axi_ar_underflow <= \<const0>\;
axi_ar_wr_data_count(4) <= \<const0>\;
axi_ar_wr_data_count(3) <= \<const0>\;
axi_ar_wr_data_count(2) <= \<const0>\;
axi_ar_wr_data_count(1) <= \<const0>\;
axi_ar_wr_data_count(0) <= \<const0>\;
axi_aw_data_count(4) <= \<const0>\;
axi_aw_data_count(3) <= \<const0>\;
axi_aw_data_count(2) <= \<const0>\;
axi_aw_data_count(1) <= \<const0>\;
axi_aw_data_count(0) <= \<const0>\;
axi_aw_dbiterr <= \<const0>\;
axi_aw_overflow <= \<const0>\;
axi_aw_prog_empty <= \<const0>\;
axi_aw_prog_full <= \<const0>\;
axi_aw_rd_data_count(4) <= \<const0>\;
axi_aw_rd_data_count(3) <= \<const0>\;
axi_aw_rd_data_count(2) <= \<const0>\;
axi_aw_rd_data_count(1) <= \<const0>\;
axi_aw_rd_data_count(0) <= \<const0>\;
axi_aw_sbiterr <= \<const0>\;
axi_aw_underflow <= \<const0>\;
axi_aw_wr_data_count(4) <= \<const0>\;
axi_aw_wr_data_count(3) <= \<const0>\;
axi_aw_wr_data_count(2) <= \<const0>\;
axi_aw_wr_data_count(1) <= \<const0>\;
axi_aw_wr_data_count(0) <= \<const0>\;
axi_b_data_count(4) <= \<const0>\;
axi_b_data_count(3) <= \<const0>\;
axi_b_data_count(2) <= \<const0>\;
axi_b_data_count(1) <= \<const0>\;
axi_b_data_count(0) <= \<const0>\;
axi_b_dbiterr <= \<const0>\;
axi_b_overflow <= \<const0>\;
axi_b_prog_empty <= \<const0>\;
axi_b_prog_full <= \<const0>\;
axi_b_rd_data_count(4) <= \<const0>\;
axi_b_rd_data_count(3) <= \<const0>\;
axi_b_rd_data_count(2) <= \<const0>\;
axi_b_rd_data_count(1) <= \<const0>\;
axi_b_rd_data_count(0) <= \<const0>\;
axi_b_sbiterr <= \<const0>\;
axi_b_underflow <= \<const0>\;
axi_b_wr_data_count(4) <= \<const0>\;
axi_b_wr_data_count(3) <= \<const0>\;
axi_b_wr_data_count(2) <= \<const0>\;
axi_b_wr_data_count(1) <= \<const0>\;
axi_b_wr_data_count(0) <= \<const0>\;
axi_r_data_count(10) <= \<const0>\;
axi_r_data_count(9) <= \<const0>\;
axi_r_data_count(8) <= \<const0>\;
axi_r_data_count(7) <= \<const0>\;
axi_r_data_count(6) <= \<const0>\;
axi_r_data_count(5) <= \<const0>\;
axi_r_data_count(4) <= \<const0>\;
axi_r_data_count(3) <= \<const0>\;
axi_r_data_count(2) <= \<const0>\;
axi_r_data_count(1) <= \<const0>\;
axi_r_data_count(0) <= \<const0>\;
axi_r_dbiterr <= \<const0>\;
axi_r_overflow <= \<const0>\;
axi_r_prog_empty <= \<const0>\;
axi_r_prog_full <= \<const0>\;
axi_r_rd_data_count(10) <= \<const0>\;
axi_r_rd_data_count(9) <= \<const0>\;
axi_r_rd_data_count(8) <= \<const0>\;
axi_r_rd_data_count(7) <= \<const0>\;
axi_r_rd_data_count(6) <= \<const0>\;
axi_r_rd_data_count(5) <= \<const0>\;
axi_r_rd_data_count(4) <= \<const0>\;
axi_r_rd_data_count(3) <= \<const0>\;
axi_r_rd_data_count(2) <= \<const0>\;
axi_r_rd_data_count(1) <= \<const0>\;
axi_r_rd_data_count(0) <= \<const0>\;
axi_r_sbiterr <= \<const0>\;
axi_r_underflow <= \<const0>\;
axi_r_wr_data_count(10) <= \<const0>\;
axi_r_wr_data_count(9) <= \<const0>\;
axi_r_wr_data_count(8) <= \<const0>\;
axi_r_wr_data_count(7) <= \<const0>\;
axi_r_wr_data_count(6) <= \<const0>\;
axi_r_wr_data_count(5) <= \<const0>\;
axi_r_wr_data_count(4) <= \<const0>\;
axi_r_wr_data_count(3) <= \<const0>\;
axi_r_wr_data_count(2) <= \<const0>\;
axi_r_wr_data_count(1) <= \<const0>\;
axi_r_wr_data_count(0) <= \<const0>\;
axi_w_data_count(10) <= \<const0>\;
axi_w_data_count(9) <= \<const0>\;
axi_w_data_count(8) <= \<const0>\;
axi_w_data_count(7) <= \<const0>\;
axi_w_data_count(6) <= \<const0>\;
axi_w_data_count(5) <= \<const0>\;
axi_w_data_count(4) <= \<const0>\;
axi_w_data_count(3) <= \<const0>\;
axi_w_data_count(2) <= \<const0>\;
axi_w_data_count(1) <= \<const0>\;
axi_w_data_count(0) <= \<const0>\;
axi_w_dbiterr <= \<const0>\;
axi_w_overflow <= \<const0>\;
axi_w_prog_empty <= \<const0>\;
axi_w_prog_full <= \<const0>\;
axi_w_rd_data_count(10) <= \<const0>\;
axi_w_rd_data_count(9) <= \<const0>\;
axi_w_rd_data_count(8) <= \<const0>\;
axi_w_rd_data_count(7) <= \<const0>\;
axi_w_rd_data_count(6) <= \<const0>\;
axi_w_rd_data_count(5) <= \<const0>\;
axi_w_rd_data_count(4) <= \<const0>\;
axi_w_rd_data_count(3) <= \<const0>\;
axi_w_rd_data_count(2) <= \<const0>\;
axi_w_rd_data_count(1) <= \<const0>\;
axi_w_rd_data_count(0) <= \<const0>\;
axi_w_sbiterr <= \<const0>\;
axi_w_underflow <= \<const0>\;
axi_w_wr_data_count(10) <= \<const0>\;
axi_w_wr_data_count(9) <= \<const0>\;
axi_w_wr_data_count(8) <= \<const0>\;
axi_w_wr_data_count(7) <= \<const0>\;
axi_w_wr_data_count(6) <= \<const0>\;
axi_w_wr_data_count(5) <= \<const0>\;
axi_w_wr_data_count(4) <= \<const0>\;
axi_w_wr_data_count(3) <= \<const0>\;
axi_w_wr_data_count(2) <= \<const0>\;
axi_w_wr_data_count(1) <= \<const0>\;
axi_w_wr_data_count(0) <= \<const0>\;
axis_data_count(10) <= \<const0>\;
axis_data_count(9) <= \<const0>\;
axis_data_count(8) <= \<const0>\;
axis_data_count(7) <= \<const0>\;
axis_data_count(6) <= \<const0>\;
axis_data_count(5) <= \<const0>\;
axis_data_count(4) <= \<const0>\;
axis_data_count(3) <= \<const0>\;
axis_data_count(2) <= \<const0>\;
axis_data_count(1) <= \<const0>\;
axis_data_count(0) <= \<const0>\;
axis_dbiterr <= \<const0>\;
axis_overflow <= \<const0>\;
axis_prog_empty <= \<const0>\;
axis_prog_full <= \<const0>\;
axis_rd_data_count(10) <= \<const0>\;
axis_rd_data_count(9) <= \<const0>\;
axis_rd_data_count(8) <= \<const0>\;
axis_rd_data_count(7) <= \<const0>\;
axis_rd_data_count(6) <= \<const0>\;
axis_rd_data_count(5) <= \<const0>\;
axis_rd_data_count(4) <= \<const0>\;
axis_rd_data_count(3) <= \<const0>\;
axis_rd_data_count(2) <= \<const0>\;
axis_rd_data_count(1) <= \<const0>\;
axis_rd_data_count(0) <= \<const0>\;
axis_sbiterr <= \<const0>\;
axis_underflow <= \<const0>\;
axis_wr_data_count(10) <= \<const0>\;
axis_wr_data_count(9) <= \<const0>\;
axis_wr_data_count(8) <= \<const0>\;
axis_wr_data_count(7) <= \<const0>\;
axis_wr_data_count(6) <= \<const0>\;
axis_wr_data_count(5) <= \<const0>\;
axis_wr_data_count(4) <= \<const0>\;
axis_wr_data_count(3) <= \<const0>\;
axis_wr_data_count(2) <= \<const0>\;
axis_wr_data_count(1) <= \<const0>\;
axis_wr_data_count(0) <= \<const0>\;
data_count(5) <= \<const0>\;
data_count(4) <= \<const0>\;
data_count(3) <= \<const0>\;
data_count(2) <= \<const0>\;
data_count(1) <= \<const0>\;
data_count(0) <= \<const0>\;
dbiterr <= \<const0>\;
m_axi_araddr(31) <= \<const0>\;
m_axi_araddr(30) <= \<const0>\;
m_axi_araddr(29) <= \<const0>\;
m_axi_araddr(28) <= \<const0>\;
m_axi_araddr(27) <= \<const0>\;
m_axi_araddr(26) <= \<const0>\;
m_axi_araddr(25) <= \<const0>\;
m_axi_araddr(24) <= \<const0>\;
m_axi_araddr(23) <= \<const0>\;
m_axi_araddr(22) <= \<const0>\;
m_axi_araddr(21) <= \<const0>\;
m_axi_araddr(20) <= \<const0>\;
m_axi_araddr(19) <= \<const0>\;
m_axi_araddr(18) <= \<const0>\;
m_axi_araddr(17) <= \<const0>\;
m_axi_araddr(16) <= \<const0>\;
m_axi_araddr(15) <= \<const0>\;
m_axi_araddr(14) <= \<const0>\;
m_axi_araddr(13) <= \<const0>\;
m_axi_araddr(12) <= \<const0>\;
m_axi_araddr(11) <= \<const0>\;
m_axi_araddr(10) <= \<const0>\;
m_axi_araddr(9) <= \<const0>\;
m_axi_araddr(8) <= \<const0>\;
m_axi_araddr(7) <= \<const0>\;
m_axi_araddr(6) <= \<const0>\;
m_axi_araddr(5) <= \<const0>\;
m_axi_araddr(4) <= \<const0>\;
m_axi_araddr(3) <= \<const0>\;
m_axi_araddr(2) <= \<const0>\;
m_axi_araddr(1) <= \<const0>\;
m_axi_araddr(0) <= \<const0>\;
m_axi_arburst(1) <= \<const0>\;
m_axi_arburst(0) <= \<const0>\;
m_axi_arcache(3) <= \<const0>\;
m_axi_arcache(2) <= \<const0>\;
m_axi_arcache(1) <= \<const0>\;
m_axi_arcache(0) <= \<const0>\;
m_axi_arid(3) <= \<const0>\;
m_axi_arid(2) <= \<const0>\;
m_axi_arid(1) <= \<const0>\;
m_axi_arid(0) <= \<const0>\;
m_axi_arlen(7) <= \<const0>\;
m_axi_arlen(6) <= \<const0>\;
m_axi_arlen(5) <= \<const0>\;
m_axi_arlen(4) <= \<const0>\;
m_axi_arlen(3) <= \<const0>\;
m_axi_arlen(2) <= \<const0>\;
m_axi_arlen(1) <= \<const0>\;
m_axi_arlen(0) <= \<const0>\;
m_axi_arlock(1) <= \<const0>\;
m_axi_arlock(0) <= \<const0>\;
m_axi_arprot(2) <= \<const0>\;
m_axi_arprot(1) <= \<const0>\;
m_axi_arprot(0) <= \<const0>\;
m_axi_arqos(3) <= \<const0>\;
m_axi_arqos(2) <= \<const0>\;
m_axi_arqos(1) <= \<const0>\;
m_axi_arqos(0) <= \<const0>\;
m_axi_arregion(3) <= \<const0>\;
m_axi_arregion(2) <= \<const0>\;
m_axi_arregion(1) <= \<const0>\;
m_axi_arregion(0) <= \<const0>\;
m_axi_arsize(2) <= \<const0>\;
m_axi_arsize(1) <= \<const0>\;
m_axi_arsize(0) <= \<const0>\;
m_axi_aruser(0) <= \<const0>\;
m_axi_arvalid <= \<const0>\;
m_axi_awaddr(31) <= \<const0>\;
m_axi_awaddr(30) <= \<const0>\;
m_axi_awaddr(29) <= \<const0>\;
m_axi_awaddr(28) <= \<const0>\;
m_axi_awaddr(27) <= \<const0>\;
m_axi_awaddr(26) <= \<const0>\;
m_axi_awaddr(25) <= \<const0>\;
m_axi_awaddr(24) <= \<const0>\;
m_axi_awaddr(23) <= \<const0>\;
m_axi_awaddr(22) <= \<const0>\;
m_axi_awaddr(21) <= \<const0>\;
m_axi_awaddr(20) <= \<const0>\;
m_axi_awaddr(19) <= \<const0>\;
m_axi_awaddr(18) <= \<const0>\;
m_axi_awaddr(17) <= \<const0>\;
m_axi_awaddr(16) <= \<const0>\;
m_axi_awaddr(15) <= \<const0>\;
m_axi_awaddr(14) <= \<const0>\;
m_axi_awaddr(13) <= \<const0>\;
m_axi_awaddr(12) <= \<const0>\;
m_axi_awaddr(11) <= \<const0>\;
m_axi_awaddr(10) <= \<const0>\;
m_axi_awaddr(9) <= \<const0>\;
m_axi_awaddr(8) <= \<const0>\;
m_axi_awaddr(7) <= \<const0>\;
m_axi_awaddr(6) <= \<const0>\;
m_axi_awaddr(5) <= \<const0>\;
m_axi_awaddr(4) <= \<const0>\;
m_axi_awaddr(3) <= \<const0>\;
m_axi_awaddr(2) <= \<const0>\;
m_axi_awaddr(1) <= \<const0>\;
m_axi_awaddr(0) <= \<const0>\;
m_axi_awburst(1) <= \<const0>\;
m_axi_awburst(0) <= \<const0>\;
m_axi_awcache(3) <= \<const0>\;
m_axi_awcache(2) <= \<const0>\;
m_axi_awcache(1) <= \<const0>\;
m_axi_awcache(0) <= \<const0>\;
m_axi_awid(3) <= \<const0>\;
m_axi_awid(2) <= \<const0>\;
m_axi_awid(1) <= \<const0>\;
m_axi_awid(0) <= \<const0>\;
m_axi_awlen(7) <= \<const0>\;
m_axi_awlen(6) <= \<const0>\;
m_axi_awlen(5) <= \<const0>\;
m_axi_awlen(4) <= \<const0>\;
m_axi_awlen(3) <= \<const0>\;
m_axi_awlen(2) <= \<const0>\;
m_axi_awlen(1) <= \<const0>\;
m_axi_awlen(0) <= \<const0>\;
m_axi_awlock(1) <= \<const0>\;
m_axi_awlock(0) <= \<const0>\;
m_axi_awprot(2) <= \<const0>\;
m_axi_awprot(1) <= \<const0>\;
m_axi_awprot(0) <= \<const0>\;
m_axi_awqos(3) <= \<const0>\;
m_axi_awqos(2) <= \<const0>\;
m_axi_awqos(1) <= \<const0>\;
m_axi_awqos(0) <= \<const0>\;
m_axi_awregion(3) <= \<const0>\;
m_axi_awregion(2) <= \<const0>\;
m_axi_awregion(1) <= \<const0>\;
m_axi_awregion(0) <= \<const0>\;
m_axi_awsize(2) <= \<const0>\;
m_axi_awsize(1) <= \<const0>\;
m_axi_awsize(0) <= \<const0>\;
m_axi_awuser(0) <= \<const0>\;
m_axi_awvalid <= \<const0>\;
m_axi_bready <= \<const0>\;
m_axi_rready <= \<const0>\;
m_axi_wdata(63) <= \<const0>\;
m_axi_wdata(62) <= \<const0>\;
m_axi_wdata(61) <= \<const0>\;
m_axi_wdata(60) <= \<const0>\;
m_axi_wdata(59) <= \<const0>\;
m_axi_wdata(58) <= \<const0>\;
m_axi_wdata(57) <= \<const0>\;
m_axi_wdata(56) <= \<const0>\;
m_axi_wdata(55) <= \<const0>\;
m_axi_wdata(54) <= \<const0>\;
m_axi_wdata(53) <= \<const0>\;
m_axi_wdata(52) <= \<const0>\;
m_axi_wdata(51) <= \<const0>\;
m_axi_wdata(50) <= \<const0>\;
m_axi_wdata(49) <= \<const0>\;
m_axi_wdata(48) <= \<const0>\;
m_axi_wdata(47) <= \<const0>\;
m_axi_wdata(46) <= \<const0>\;
m_axi_wdata(45) <= \<const0>\;
m_axi_wdata(44) <= \<const0>\;
m_axi_wdata(43) <= \<const0>\;
m_axi_wdata(42) <= \<const0>\;
m_axi_wdata(41) <= \<const0>\;
m_axi_wdata(40) <= \<const0>\;
m_axi_wdata(39) <= \<const0>\;
m_axi_wdata(38) <= \<const0>\;
m_axi_wdata(37) <= \<const0>\;
m_axi_wdata(36) <= \<const0>\;
m_axi_wdata(35) <= \<const0>\;
m_axi_wdata(34) <= \<const0>\;
m_axi_wdata(33) <= \<const0>\;
m_axi_wdata(32) <= \<const0>\;
m_axi_wdata(31) <= \<const0>\;
m_axi_wdata(30) <= \<const0>\;
m_axi_wdata(29) <= \<const0>\;
m_axi_wdata(28) <= \<const0>\;
m_axi_wdata(27) <= \<const0>\;
m_axi_wdata(26) <= \<const0>\;
m_axi_wdata(25) <= \<const0>\;
m_axi_wdata(24) <= \<const0>\;
m_axi_wdata(23) <= \<const0>\;
m_axi_wdata(22) <= \<const0>\;
m_axi_wdata(21) <= \<const0>\;
m_axi_wdata(20) <= \<const0>\;
m_axi_wdata(19) <= \<const0>\;
m_axi_wdata(18) <= \<const0>\;
m_axi_wdata(17) <= \<const0>\;
m_axi_wdata(16) <= \<const0>\;
m_axi_wdata(15) <= \<const0>\;
m_axi_wdata(14) <= \<const0>\;
m_axi_wdata(13) <= \<const0>\;
m_axi_wdata(12) <= \<const0>\;
m_axi_wdata(11) <= \<const0>\;
m_axi_wdata(10) <= \<const0>\;
m_axi_wdata(9) <= \<const0>\;
m_axi_wdata(8) <= \<const0>\;
m_axi_wdata(7) <= \<const0>\;
m_axi_wdata(6) <= \<const0>\;
m_axi_wdata(5) <= \<const0>\;
m_axi_wdata(4) <= \<const0>\;
m_axi_wdata(3) <= \<const0>\;
m_axi_wdata(2) <= \<const0>\;
m_axi_wdata(1) <= \<const0>\;
m_axi_wdata(0) <= \<const0>\;
m_axi_wid(3) <= \<const0>\;
m_axi_wid(2) <= \<const0>\;
m_axi_wid(1) <= \<const0>\;
m_axi_wid(0) <= \<const0>\;
m_axi_wlast <= \<const0>\;
m_axi_wstrb(7) <= \<const0>\;
m_axi_wstrb(6) <= \<const0>\;
m_axi_wstrb(5) <= \<const0>\;
m_axi_wstrb(4) <= \<const0>\;
m_axi_wstrb(3) <= \<const0>\;
m_axi_wstrb(2) <= \<const0>\;
m_axi_wstrb(1) <= \<const0>\;
m_axi_wstrb(0) <= \<const0>\;
m_axi_wuser(0) <= \<const0>\;
m_axi_wvalid <= \<const0>\;
m_axis_tdata(63) <= \<const0>\;
m_axis_tdata(62) <= \<const0>\;
m_axis_tdata(61) <= \<const0>\;
m_axis_tdata(60) <= \<const0>\;
m_axis_tdata(59) <= \<const0>\;
m_axis_tdata(58) <= \<const0>\;
m_axis_tdata(57) <= \<const0>\;
m_axis_tdata(56) <= \<const0>\;
m_axis_tdata(55) <= \<const0>\;
m_axis_tdata(54) <= \<const0>\;
m_axis_tdata(53) <= \<const0>\;
m_axis_tdata(52) <= \<const0>\;
m_axis_tdata(51) <= \<const0>\;
m_axis_tdata(50) <= \<const0>\;
m_axis_tdata(49) <= \<const0>\;
m_axis_tdata(48) <= \<const0>\;
m_axis_tdata(47) <= \<const0>\;
m_axis_tdata(46) <= \<const0>\;
m_axis_tdata(45) <= \<const0>\;
m_axis_tdata(44) <= \<const0>\;
m_axis_tdata(43) <= \<const0>\;
m_axis_tdata(42) <= \<const0>\;
m_axis_tdata(41) <= \<const0>\;
m_axis_tdata(40) <= \<const0>\;
m_axis_tdata(39) <= \<const0>\;
m_axis_tdata(38) <= \<const0>\;
m_axis_tdata(37) <= \<const0>\;
m_axis_tdata(36) <= \<const0>\;
m_axis_tdata(35) <= \<const0>\;
m_axis_tdata(34) <= \<const0>\;
m_axis_tdata(33) <= \<const0>\;
m_axis_tdata(32) <= \<const0>\;
m_axis_tdata(31) <= \<const0>\;
m_axis_tdata(30) <= \<const0>\;
m_axis_tdata(29) <= \<const0>\;
m_axis_tdata(28) <= \<const0>\;
m_axis_tdata(27) <= \<const0>\;
m_axis_tdata(26) <= \<const0>\;
m_axis_tdata(25) <= \<const0>\;
m_axis_tdata(24) <= \<const0>\;
m_axis_tdata(23) <= \<const0>\;
m_axis_tdata(22) <= \<const0>\;
m_axis_tdata(21) <= \<const0>\;
m_axis_tdata(20) <= \<const0>\;
m_axis_tdata(19) <= \<const0>\;
m_axis_tdata(18) <= \<const0>\;
m_axis_tdata(17) <= \<const0>\;
m_axis_tdata(16) <= \<const0>\;
m_axis_tdata(15) <= \<const0>\;
m_axis_tdata(14) <= \<const0>\;
m_axis_tdata(13) <= \<const0>\;
m_axis_tdata(12) <= \<const0>\;
m_axis_tdata(11) <= \<const0>\;
m_axis_tdata(10) <= \<const0>\;
m_axis_tdata(9) <= \<const0>\;
m_axis_tdata(8) <= \<const0>\;
m_axis_tdata(7) <= \<const0>\;
m_axis_tdata(6) <= \<const0>\;
m_axis_tdata(5) <= \<const0>\;
m_axis_tdata(4) <= \<const0>\;
m_axis_tdata(3) <= \<const0>\;
m_axis_tdata(2) <= \<const0>\;
m_axis_tdata(1) <= \<const0>\;
m_axis_tdata(0) <= \<const0>\;
m_axis_tdest(3) <= \<const0>\;
m_axis_tdest(2) <= \<const0>\;
m_axis_tdest(1) <= \<const0>\;
m_axis_tdest(0) <= \<const0>\;
m_axis_tid(7) <= \<const0>\;
m_axis_tid(6) <= \<const0>\;
m_axis_tid(5) <= \<const0>\;
m_axis_tid(4) <= \<const0>\;
m_axis_tid(3) <= \<const0>\;
m_axis_tid(2) <= \<const0>\;
m_axis_tid(1) <= \<const0>\;
m_axis_tid(0) <= \<const0>\;
m_axis_tkeep(3) <= \<const0>\;
m_axis_tkeep(2) <= \<const0>\;
m_axis_tkeep(1) <= \<const0>\;
m_axis_tkeep(0) <= \<const0>\;
m_axis_tlast <= \<const0>\;
m_axis_tstrb(3) <= \<const0>\;
m_axis_tstrb(2) <= \<const0>\;
m_axis_tstrb(1) <= \<const0>\;
m_axis_tstrb(0) <= \<const0>\;
m_axis_tuser(3) <= \<const0>\;
m_axis_tuser(2) <= \<const0>\;
m_axis_tuser(1) <= \<const0>\;
m_axis_tuser(0) <= \<const0>\;
m_axis_tvalid <= \<const0>\;
overflow <= \<const0>\;
prog_empty <= \<const0>\;
prog_full <= \<const0>\;
rd_data_count(5) <= \<const0>\;
rd_data_count(4) <= \<const0>\;
rd_data_count(3) <= \<const0>\;
rd_data_count(2) <= \<const0>\;
rd_data_count(1) <= \<const0>\;
rd_data_count(0) <= \<const0>\;
rd_rst_busy <= \<const0>\;
s_axi_arready <= \<const0>\;
s_axi_awready <= \<const0>\;
s_axi_bid(3) <= \<const0>\;
s_axi_bid(2) <= \<const0>\;
s_axi_bid(1) <= \<const0>\;
s_axi_bid(0) <= \<const0>\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_buser(0) <= \<const0>\;
s_axi_bvalid <= \<const0>\;
s_axi_rdata(63) <= \<const0>\;
s_axi_rdata(62) <= \<const0>\;
s_axi_rdata(61) <= \<const0>\;
s_axi_rdata(60) <= \<const0>\;
s_axi_rdata(59) <= \<const0>\;
s_axi_rdata(58) <= \<const0>\;
s_axi_rdata(57) <= \<const0>\;
s_axi_rdata(56) <= \<const0>\;
s_axi_rdata(55) <= \<const0>\;
s_axi_rdata(54) <= \<const0>\;
s_axi_rdata(53) <= \<const0>\;
s_axi_rdata(52) <= \<const0>\;
s_axi_rdata(51) <= \<const0>\;
s_axi_rdata(50) <= \<const0>\;
s_axi_rdata(49) <= \<const0>\;
s_axi_rdata(48) <= \<const0>\;
s_axi_rdata(47) <= \<const0>\;
s_axi_rdata(46) <= \<const0>\;
s_axi_rdata(45) <= \<const0>\;
s_axi_rdata(44) <= \<const0>\;
s_axi_rdata(43) <= \<const0>\;
s_axi_rdata(42) <= \<const0>\;
s_axi_rdata(41) <= \<const0>\;
s_axi_rdata(40) <= \<const0>\;
s_axi_rdata(39) <= \<const0>\;
s_axi_rdata(38) <= \<const0>\;
s_axi_rdata(37) <= \<const0>\;
s_axi_rdata(36) <= \<const0>\;
s_axi_rdata(35) <= \<const0>\;
s_axi_rdata(34) <= \<const0>\;
s_axi_rdata(33) <= \<const0>\;
s_axi_rdata(32) <= \<const0>\;
s_axi_rdata(31) <= \<const0>\;
s_axi_rdata(30) <= \<const0>\;
s_axi_rdata(29) <= \<const0>\;
s_axi_rdata(28) <= \<const0>\;
s_axi_rdata(27) <= \<const0>\;
s_axi_rdata(26) <= \<const0>\;
s_axi_rdata(25) <= \<const0>\;
s_axi_rdata(24) <= \<const0>\;
s_axi_rdata(23) <= \<const0>\;
s_axi_rdata(22) <= \<const0>\;
s_axi_rdata(21) <= \<const0>\;
s_axi_rdata(20) <= \<const0>\;
s_axi_rdata(19) <= \<const0>\;
s_axi_rdata(18) <= \<const0>\;
s_axi_rdata(17) <= \<const0>\;
s_axi_rdata(16) <= \<const0>\;
s_axi_rdata(15) <= \<const0>\;
s_axi_rdata(14) <= \<const0>\;
s_axi_rdata(13) <= \<const0>\;
s_axi_rdata(12) <= \<const0>\;
s_axi_rdata(11) <= \<const0>\;
s_axi_rdata(10) <= \<const0>\;
s_axi_rdata(9) <= \<const0>\;
s_axi_rdata(8) <= \<const0>\;
s_axi_rdata(7) <= \<const0>\;
s_axi_rdata(6) <= \<const0>\;
s_axi_rdata(5) <= \<const0>\;
s_axi_rdata(4) <= \<const0>\;
s_axi_rdata(3) <= \<const0>\;
s_axi_rdata(2) <= \<const0>\;
s_axi_rdata(1) <= \<const0>\;
s_axi_rdata(0) <= \<const0>\;
s_axi_rid(3) <= \<const0>\;
s_axi_rid(2) <= \<const0>\;
s_axi_rid(1) <= \<const0>\;
s_axi_rid(0) <= \<const0>\;
s_axi_rlast <= \<const0>\;
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
s_axi_ruser(0) <= \<const0>\;
s_axi_rvalid <= \<const0>\;
s_axi_wready <= \<const0>\;
s_axis_tready <= \<const0>\;
sbiterr <= \<const0>\;
underflow <= \<const0>\;
valid <= \<const0>\;
wr_ack <= \<const0>\;
wr_data_count(5) <= \<const0>\;
wr_data_count(4) <= \<const0>\;
wr_data_count(3) <= \<const0>\;
wr_data_count(2) <= \<const0>\;
wr_data_count(1) <= \<const0>\;
wr_data_count(0) <= \<const0>\;
wr_rst_busy <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
inst_fifo_gen: entity work.\system_auto_pc_1_fifo_generator_v13_1_3_synth__parameterized1\
port map (
clk => clk,
din(0) => din(0),
dout(0) => dout(0),
empty => empty,
full => full,
rd_en => rd_en,
rst => rst,
wr_en => wr_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_pc_1_axi_data_fifo_v2_1_10_fifo_gen is
port (
dout : out STD_LOGIC_VECTOR ( 5 downto 0 );
full : out STD_LOGIC;
empty : out STD_LOGIC;
SR : out STD_LOGIC_VECTOR ( 0 to 0 );
din : out STD_LOGIC_VECTOR ( 3 downto 0 );
\USE_B_CHANNEL.cmd_b_empty_reg\ : out STD_LOGIC;
\USE_B_CHANNEL.cmd_b_empty_reg_0\ : out STD_LOGIC;
\length_counter_1_reg_0__s_port_]\ : out STD_LOGIC;
s_axi_wready : out STD_LOGIC;
m_axi_wvalid : out STD_LOGIC;
aclk : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
wr_en : in STD_LOGIC;
wr_cmd_ready : in STD_LOGIC;
cmd_empty : in STD_LOGIC;
cmd_b_empty : in STD_LOGIC;
queue_id : in STD_LOGIC_VECTOR ( 1 downto 0 );
cmd_push_block : in STD_LOGIC;
command_ongoing : in STD_LOGIC;
aresetn : in STD_LOGIC;
first_mi_word : in STD_LOGIC;
length_counter_1_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wready : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
\S_AXI_ALEN_Q_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\pushed_commands_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
need_to_split_q : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_pc_1_axi_data_fifo_v2_1_10_fifo_gen : entity is "axi_data_fifo_v2_1_10_fifo_gen";
end system_auto_pc_1_axi_data_fifo_v2_1_10_fifo_gen;
architecture STRUCTURE of system_auto_pc_1_axi_data_fifo_v2_1_10_fifo_gen is
signal \^sr\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^din\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^dout\ : STD_LOGIC_VECTOR ( 5 downto 0 );
signal \^empty\ : STD_LOGIC;
signal \length_counter_1_reg_0__s_net_1\ : STD_LOGIC;
signal NLW_fifo_gen_inst_almost_empty_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_almost_full_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axi_ar_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axi_ar_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axi_ar_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axi_ar_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axi_ar_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axi_ar_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axi_aw_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axi_aw_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axi_aw_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axi_aw_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axi_aw_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axi_aw_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axi_b_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axi_b_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axi_b_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axi_b_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axi_b_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axi_b_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axi_r_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axi_r_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axi_r_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axi_r_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axi_r_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axi_r_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axi_w_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axi_w_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axi_w_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axi_w_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axi_w_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axi_w_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axis_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axis_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axis_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axis_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axis_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axis_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_m_axi_arvalid_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_m_axi_awvalid_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_m_axi_bready_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_m_axi_rready_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_m_axi_wlast_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_m_axi_wvalid_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_m_axis_tlast_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_m_axis_tvalid_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_rd_rst_busy_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_s_axi_arready_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_s_axi_awready_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_s_axi_rlast_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_s_axi_wready_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_s_axis_tready_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_valid_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_wr_ack_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_wr_rst_busy_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axi_ar_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_fifo_gen_inst_axi_ar_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_fifo_gen_inst_axi_ar_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_fifo_gen_inst_axi_aw_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_fifo_gen_inst_axi_aw_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_fifo_gen_inst_axi_aw_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_fifo_gen_inst_axi_b_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_fifo_gen_inst_axi_b_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_fifo_gen_inst_axi_b_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_fifo_gen_inst_axi_r_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_fifo_gen_inst_axi_r_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_fifo_gen_inst_axi_r_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_fifo_gen_inst_axi_w_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_fifo_gen_inst_axi_w_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_fifo_gen_inst_axi_w_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_fifo_gen_inst_axis_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_fifo_gen_inst_axis_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_fifo_gen_inst_axis_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_fifo_gen_inst_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_fifo_gen_inst_m_axi_araddr_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_fifo_gen_inst_m_axi_arburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_fifo_gen_inst_m_axi_arcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_fifo_gen_inst_m_axi_arid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_fifo_gen_inst_m_axi_arlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_fifo_gen_inst_m_axi_arlock_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_fifo_gen_inst_m_axi_arprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_fifo_gen_inst_m_axi_arqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_fifo_gen_inst_m_axi_arregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_fifo_gen_inst_m_axi_arsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_fifo_gen_inst_m_axi_aruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_fifo_gen_inst_m_axi_awaddr_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_fifo_gen_inst_m_axi_awburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_fifo_gen_inst_m_axi_awcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_fifo_gen_inst_m_axi_awid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_fifo_gen_inst_m_axi_awlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_fifo_gen_inst_m_axi_awlock_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_fifo_gen_inst_m_axi_awprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_fifo_gen_inst_m_axi_awqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_fifo_gen_inst_m_axi_awregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_fifo_gen_inst_m_axi_awsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_fifo_gen_inst_m_axi_awuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_fifo_gen_inst_m_axi_wdata_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_fifo_gen_inst_m_axi_wid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_fifo_gen_inst_m_axi_wstrb_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_fifo_gen_inst_m_axi_wuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_fifo_gen_inst_m_axis_tdata_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_fifo_gen_inst_m_axis_tdest_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_fifo_gen_inst_m_axis_tid_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_fifo_gen_inst_m_axis_tkeep_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_fifo_gen_inst_m_axis_tstrb_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_fifo_gen_inst_m_axis_tuser_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_fifo_gen_inst_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_fifo_gen_inst_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_fifo_gen_inst_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_fifo_gen_inst_s_axi_buser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_fifo_gen_inst_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_fifo_gen_inst_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_fifo_gen_inst_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_fifo_gen_inst_s_axi_ruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_fifo_gen_inst_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
attribute C_ADD_NGC_CONSTRAINT : integer;
attribute C_ADD_NGC_CONSTRAINT of fifo_gen_inst : label is 0;
attribute C_APPLICATION_TYPE_AXIS : integer;
attribute C_APPLICATION_TYPE_AXIS of fifo_gen_inst : label is 0;
attribute C_APPLICATION_TYPE_RACH : integer;
attribute C_APPLICATION_TYPE_RACH of fifo_gen_inst : label is 0;
attribute C_APPLICATION_TYPE_RDCH : integer;
attribute C_APPLICATION_TYPE_RDCH of fifo_gen_inst : label is 0;
attribute C_APPLICATION_TYPE_WACH : integer;
attribute C_APPLICATION_TYPE_WACH of fifo_gen_inst : label is 0;
attribute C_APPLICATION_TYPE_WDCH : integer;
attribute C_APPLICATION_TYPE_WDCH of fifo_gen_inst : label is 0;
attribute C_APPLICATION_TYPE_WRCH : integer;
attribute C_APPLICATION_TYPE_WRCH of fifo_gen_inst : label is 0;
attribute C_AXIS_TDATA_WIDTH : integer;
attribute C_AXIS_TDATA_WIDTH of fifo_gen_inst : label is 64;
attribute C_AXIS_TDEST_WIDTH : integer;
attribute C_AXIS_TDEST_WIDTH of fifo_gen_inst : label is 4;
attribute C_AXIS_TID_WIDTH : integer;
attribute C_AXIS_TID_WIDTH of fifo_gen_inst : label is 8;
attribute C_AXIS_TKEEP_WIDTH : integer;
attribute C_AXIS_TKEEP_WIDTH of fifo_gen_inst : label is 4;
attribute C_AXIS_TSTRB_WIDTH : integer;
attribute C_AXIS_TSTRB_WIDTH of fifo_gen_inst : label is 4;
attribute C_AXIS_TUSER_WIDTH : integer;
attribute C_AXIS_TUSER_WIDTH of fifo_gen_inst : label is 4;
attribute C_AXIS_TYPE : integer;
attribute C_AXIS_TYPE of fifo_gen_inst : label is 0;
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of fifo_gen_inst : label is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of fifo_gen_inst : label is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of fifo_gen_inst : label is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of fifo_gen_inst : label is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of fifo_gen_inst : label is 64;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of fifo_gen_inst : label is 4;
attribute C_AXI_LEN_WIDTH : integer;
attribute C_AXI_LEN_WIDTH of fifo_gen_inst : label is 8;
attribute C_AXI_LOCK_WIDTH : integer;
attribute C_AXI_LOCK_WIDTH of fifo_gen_inst : label is 2;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of fifo_gen_inst : label is 1;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of fifo_gen_inst : label is 0;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of fifo_gen_inst : label is 1;
attribute C_COMMON_CLOCK : integer;
attribute C_COMMON_CLOCK of fifo_gen_inst : label is 1;
attribute C_COUNT_TYPE : integer;
attribute C_COUNT_TYPE of fifo_gen_inst : label is 0;
attribute C_DATA_COUNT_WIDTH : integer;
attribute C_DATA_COUNT_WIDTH of fifo_gen_inst : label is 6;
attribute C_DEFAULT_VALUE : string;
attribute C_DEFAULT_VALUE of fifo_gen_inst : label is "BlankString";
attribute C_DIN_WIDTH : integer;
attribute C_DIN_WIDTH of fifo_gen_inst : label is 6;
attribute C_DIN_WIDTH_AXIS : integer;
attribute C_DIN_WIDTH_AXIS of fifo_gen_inst : label is 1;
attribute C_DIN_WIDTH_RACH : integer;
attribute C_DIN_WIDTH_RACH of fifo_gen_inst : label is 32;
attribute C_DIN_WIDTH_RDCH : integer;
attribute C_DIN_WIDTH_RDCH of fifo_gen_inst : label is 64;
attribute C_DIN_WIDTH_WACH : integer;
attribute C_DIN_WIDTH_WACH of fifo_gen_inst : label is 32;
attribute C_DIN_WIDTH_WDCH : integer;
attribute C_DIN_WIDTH_WDCH of fifo_gen_inst : label is 64;
attribute C_DIN_WIDTH_WRCH : integer;
attribute C_DIN_WIDTH_WRCH of fifo_gen_inst : label is 2;
attribute C_DOUT_RST_VAL : string;
attribute C_DOUT_RST_VAL of fifo_gen_inst : label is "0";
attribute C_DOUT_WIDTH : integer;
attribute C_DOUT_WIDTH of fifo_gen_inst : label is 6;
attribute C_ENABLE_RLOCS : integer;
attribute C_ENABLE_RLOCS of fifo_gen_inst : label is 0;
attribute C_ENABLE_RST_SYNC : integer;
attribute C_ENABLE_RST_SYNC of fifo_gen_inst : label is 1;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of fifo_gen_inst : label is 0;
attribute C_ERROR_INJECTION_TYPE : integer;
attribute C_ERROR_INJECTION_TYPE of fifo_gen_inst : label is 0;
attribute C_ERROR_INJECTION_TYPE_AXIS : integer;
attribute C_ERROR_INJECTION_TYPE_AXIS of fifo_gen_inst : label is 0;
attribute C_ERROR_INJECTION_TYPE_RACH : integer;
attribute C_ERROR_INJECTION_TYPE_RACH of fifo_gen_inst : label is 0;
attribute C_ERROR_INJECTION_TYPE_RDCH : integer;
attribute C_ERROR_INJECTION_TYPE_RDCH of fifo_gen_inst : label is 0;
attribute C_ERROR_INJECTION_TYPE_WACH : integer;
attribute C_ERROR_INJECTION_TYPE_WACH of fifo_gen_inst : label is 0;
attribute C_ERROR_INJECTION_TYPE_WDCH : integer;
attribute C_ERROR_INJECTION_TYPE_WDCH of fifo_gen_inst : label is 0;
attribute C_ERROR_INJECTION_TYPE_WRCH : integer;
attribute C_ERROR_INJECTION_TYPE_WRCH of fifo_gen_inst : label is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of fifo_gen_inst : label is "zynq";
attribute C_FULL_FLAGS_RST_VAL : integer;
attribute C_FULL_FLAGS_RST_VAL of fifo_gen_inst : label is 0;
attribute C_HAS_ALMOST_EMPTY : integer;
attribute C_HAS_ALMOST_EMPTY of fifo_gen_inst : label is 0;
attribute C_HAS_ALMOST_FULL : integer;
attribute C_HAS_ALMOST_FULL of fifo_gen_inst : label is 0;
attribute C_HAS_AXIS_TDATA : integer;
attribute C_HAS_AXIS_TDATA of fifo_gen_inst : label is 0;
attribute C_HAS_AXIS_TDEST : integer;
attribute C_HAS_AXIS_TDEST of fifo_gen_inst : label is 0;
attribute C_HAS_AXIS_TID : integer;
attribute C_HAS_AXIS_TID of fifo_gen_inst : label is 0;
attribute C_HAS_AXIS_TKEEP : integer;
attribute C_HAS_AXIS_TKEEP of fifo_gen_inst : label is 0;
attribute C_HAS_AXIS_TLAST : integer;
attribute C_HAS_AXIS_TLAST of fifo_gen_inst : label is 0;
attribute C_HAS_AXIS_TREADY : integer;
attribute C_HAS_AXIS_TREADY of fifo_gen_inst : label is 1;
attribute C_HAS_AXIS_TSTRB : integer;
attribute C_HAS_AXIS_TSTRB of fifo_gen_inst : label is 0;
attribute C_HAS_AXIS_TUSER : integer;
attribute C_HAS_AXIS_TUSER of fifo_gen_inst : label is 0;
attribute C_HAS_AXI_ARUSER : integer;
attribute C_HAS_AXI_ARUSER of fifo_gen_inst : label is 0;
attribute C_HAS_AXI_AWUSER : integer;
attribute C_HAS_AXI_AWUSER of fifo_gen_inst : label is 0;
attribute C_HAS_AXI_BUSER : integer;
attribute C_HAS_AXI_BUSER of fifo_gen_inst : label is 0;
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of fifo_gen_inst : label is 0;
attribute C_HAS_AXI_RD_CHANNEL : integer;
attribute C_HAS_AXI_RD_CHANNEL of fifo_gen_inst : label is 0;
attribute C_HAS_AXI_RUSER : integer;
attribute C_HAS_AXI_RUSER of fifo_gen_inst : label is 0;
attribute C_HAS_AXI_WR_CHANNEL : integer;
attribute C_HAS_AXI_WR_CHANNEL of fifo_gen_inst : label is 0;
attribute C_HAS_AXI_WUSER : integer;
attribute C_HAS_AXI_WUSER of fifo_gen_inst : label is 0;
attribute C_HAS_BACKUP : integer;
attribute C_HAS_BACKUP of fifo_gen_inst : label is 0;
attribute C_HAS_DATA_COUNT : integer;
attribute C_HAS_DATA_COUNT of fifo_gen_inst : label is 0;
attribute C_HAS_DATA_COUNTS_AXIS : integer;
attribute C_HAS_DATA_COUNTS_AXIS of fifo_gen_inst : label is 0;
attribute C_HAS_DATA_COUNTS_RACH : integer;
attribute C_HAS_DATA_COUNTS_RACH of fifo_gen_inst : label is 0;
attribute C_HAS_DATA_COUNTS_RDCH : integer;
attribute C_HAS_DATA_COUNTS_RDCH of fifo_gen_inst : label is 0;
attribute C_HAS_DATA_COUNTS_WACH : integer;
attribute C_HAS_DATA_COUNTS_WACH of fifo_gen_inst : label is 0;
attribute C_HAS_DATA_COUNTS_WDCH : integer;
attribute C_HAS_DATA_COUNTS_WDCH of fifo_gen_inst : label is 0;
attribute C_HAS_DATA_COUNTS_WRCH : integer;
attribute C_HAS_DATA_COUNTS_WRCH of fifo_gen_inst : label is 0;
attribute C_HAS_INT_CLK : integer;
attribute C_HAS_INT_CLK of fifo_gen_inst : label is 0;
attribute C_HAS_MASTER_CE : integer;
attribute C_HAS_MASTER_CE of fifo_gen_inst : label is 0;
attribute C_HAS_MEMINIT_FILE : integer;
attribute C_HAS_MEMINIT_FILE of fifo_gen_inst : label is 0;
attribute C_HAS_OVERFLOW : integer;
attribute C_HAS_OVERFLOW of fifo_gen_inst : label is 0;
attribute C_HAS_PROG_FLAGS_AXIS : integer;
attribute C_HAS_PROG_FLAGS_AXIS of fifo_gen_inst : label is 0;
attribute C_HAS_PROG_FLAGS_RACH : integer;
attribute C_HAS_PROG_FLAGS_RACH of fifo_gen_inst : label is 0;
attribute C_HAS_PROG_FLAGS_RDCH : integer;
attribute C_HAS_PROG_FLAGS_RDCH of fifo_gen_inst : label is 0;
attribute C_HAS_PROG_FLAGS_WACH : integer;
attribute C_HAS_PROG_FLAGS_WACH of fifo_gen_inst : label is 0;
attribute C_HAS_PROG_FLAGS_WDCH : integer;
attribute C_HAS_PROG_FLAGS_WDCH of fifo_gen_inst : label is 0;
attribute C_HAS_PROG_FLAGS_WRCH : integer;
attribute C_HAS_PROG_FLAGS_WRCH of fifo_gen_inst : label is 0;
attribute C_HAS_RD_DATA_COUNT : integer;
attribute C_HAS_RD_DATA_COUNT of fifo_gen_inst : label is 0;
attribute C_HAS_RD_RST : integer;
attribute C_HAS_RD_RST of fifo_gen_inst : label is 0;
attribute C_HAS_RST : integer;
attribute C_HAS_RST of fifo_gen_inst : label is 1;
attribute C_HAS_SLAVE_CE : integer;
attribute C_HAS_SLAVE_CE of fifo_gen_inst : label is 0;
attribute C_HAS_SRST : integer;
attribute C_HAS_SRST of fifo_gen_inst : label is 0;
attribute C_HAS_UNDERFLOW : integer;
attribute C_HAS_UNDERFLOW of fifo_gen_inst : label is 0;
attribute C_HAS_VALID : integer;
attribute C_HAS_VALID of fifo_gen_inst : label is 0;
attribute C_HAS_WR_ACK : integer;
attribute C_HAS_WR_ACK of fifo_gen_inst : label is 0;
attribute C_HAS_WR_DATA_COUNT : integer;
attribute C_HAS_WR_DATA_COUNT of fifo_gen_inst : label is 0;
attribute C_HAS_WR_RST : integer;
attribute C_HAS_WR_RST of fifo_gen_inst : label is 0;
attribute C_IMPLEMENTATION_TYPE : integer;
attribute C_IMPLEMENTATION_TYPE of fifo_gen_inst : label is 0;
attribute C_IMPLEMENTATION_TYPE_AXIS : integer;
attribute C_IMPLEMENTATION_TYPE_AXIS of fifo_gen_inst : label is 1;
attribute C_IMPLEMENTATION_TYPE_RACH : integer;
attribute C_IMPLEMENTATION_TYPE_RACH of fifo_gen_inst : label is 1;
attribute C_IMPLEMENTATION_TYPE_RDCH : integer;
attribute C_IMPLEMENTATION_TYPE_RDCH of fifo_gen_inst : label is 1;
attribute C_IMPLEMENTATION_TYPE_WACH : integer;
attribute C_IMPLEMENTATION_TYPE_WACH of fifo_gen_inst : label is 1;
attribute C_IMPLEMENTATION_TYPE_WDCH : integer;
attribute C_IMPLEMENTATION_TYPE_WDCH of fifo_gen_inst : label is 1;
attribute C_IMPLEMENTATION_TYPE_WRCH : integer;
attribute C_IMPLEMENTATION_TYPE_WRCH of fifo_gen_inst : label is 1;
attribute C_INIT_WR_PNTR_VAL : integer;
attribute C_INIT_WR_PNTR_VAL of fifo_gen_inst : label is 0;
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of fifo_gen_inst : label is 0;
attribute C_MEMORY_TYPE : integer;
attribute C_MEMORY_TYPE of fifo_gen_inst : label is 2;
attribute C_MIF_FILE_NAME : string;
attribute C_MIF_FILE_NAME of fifo_gen_inst : label is "BlankString";
attribute C_MSGON_VAL : integer;
attribute C_MSGON_VAL of fifo_gen_inst : label is 1;
attribute C_OPTIMIZATION_MODE : integer;
attribute C_OPTIMIZATION_MODE of fifo_gen_inst : label is 0;
attribute C_OVERFLOW_LOW : integer;
attribute C_OVERFLOW_LOW of fifo_gen_inst : label is 0;
attribute C_POWER_SAVING_MODE : integer;
attribute C_POWER_SAVING_MODE of fifo_gen_inst : label is 0;
attribute C_PRELOAD_LATENCY : integer;
attribute C_PRELOAD_LATENCY of fifo_gen_inst : label is 0;
attribute C_PRELOAD_REGS : integer;
attribute C_PRELOAD_REGS of fifo_gen_inst : label is 1;
attribute C_PRIM_FIFO_TYPE : string;
attribute C_PRIM_FIFO_TYPE of fifo_gen_inst : label is "512x36";
attribute C_PRIM_FIFO_TYPE_AXIS : string;
attribute C_PRIM_FIFO_TYPE_AXIS of fifo_gen_inst : label is "512x36";
attribute C_PRIM_FIFO_TYPE_RACH : string;
attribute C_PRIM_FIFO_TYPE_RACH of fifo_gen_inst : label is "512x36";
attribute C_PRIM_FIFO_TYPE_RDCH : string;
attribute C_PRIM_FIFO_TYPE_RDCH of fifo_gen_inst : label is "512x36";
attribute C_PRIM_FIFO_TYPE_WACH : string;
attribute C_PRIM_FIFO_TYPE_WACH of fifo_gen_inst : label is "512x36";
attribute C_PRIM_FIFO_TYPE_WDCH : string;
attribute C_PRIM_FIFO_TYPE_WDCH of fifo_gen_inst : label is "512x36";
attribute C_PRIM_FIFO_TYPE_WRCH : string;
attribute C_PRIM_FIFO_TYPE_WRCH of fifo_gen_inst : label is "512x36";
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL of fifo_gen_inst : label is 4;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS of fifo_gen_inst : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH of fifo_gen_inst : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH of fifo_gen_inst : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH of fifo_gen_inst : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH of fifo_gen_inst : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH of fifo_gen_inst : label is 1022;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL : integer;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL of fifo_gen_inst : label is 5;
attribute C_PROG_EMPTY_TYPE : integer;
attribute C_PROG_EMPTY_TYPE of fifo_gen_inst : label is 0;
attribute C_PROG_EMPTY_TYPE_AXIS : integer;
attribute C_PROG_EMPTY_TYPE_AXIS of fifo_gen_inst : label is 0;
attribute C_PROG_EMPTY_TYPE_RACH : integer;
attribute C_PROG_EMPTY_TYPE_RACH of fifo_gen_inst : label is 0;
attribute C_PROG_EMPTY_TYPE_RDCH : integer;
attribute C_PROG_EMPTY_TYPE_RDCH of fifo_gen_inst : label is 0;
attribute C_PROG_EMPTY_TYPE_WACH : integer;
attribute C_PROG_EMPTY_TYPE_WACH of fifo_gen_inst : label is 0;
attribute C_PROG_EMPTY_TYPE_WDCH : integer;
attribute C_PROG_EMPTY_TYPE_WDCH of fifo_gen_inst : label is 0;
attribute C_PROG_EMPTY_TYPE_WRCH : integer;
attribute C_PROG_EMPTY_TYPE_WRCH of fifo_gen_inst : label is 0;
attribute C_PROG_FULL_THRESH_ASSERT_VAL : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL of fifo_gen_inst : label is 31;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS of fifo_gen_inst : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH of fifo_gen_inst : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH of fifo_gen_inst : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH of fifo_gen_inst : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH of fifo_gen_inst : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH of fifo_gen_inst : label is 1023;
attribute C_PROG_FULL_THRESH_NEGATE_VAL : integer;
attribute C_PROG_FULL_THRESH_NEGATE_VAL of fifo_gen_inst : label is 30;
attribute C_PROG_FULL_TYPE : integer;
attribute C_PROG_FULL_TYPE of fifo_gen_inst : label is 0;
attribute C_PROG_FULL_TYPE_AXIS : integer;
attribute C_PROG_FULL_TYPE_AXIS of fifo_gen_inst : label is 0;
attribute C_PROG_FULL_TYPE_RACH : integer;
attribute C_PROG_FULL_TYPE_RACH of fifo_gen_inst : label is 0;
attribute C_PROG_FULL_TYPE_RDCH : integer;
attribute C_PROG_FULL_TYPE_RDCH of fifo_gen_inst : label is 0;
attribute C_PROG_FULL_TYPE_WACH : integer;
attribute C_PROG_FULL_TYPE_WACH of fifo_gen_inst : label is 0;
attribute C_PROG_FULL_TYPE_WDCH : integer;
attribute C_PROG_FULL_TYPE_WDCH of fifo_gen_inst : label is 0;
attribute C_PROG_FULL_TYPE_WRCH : integer;
attribute C_PROG_FULL_TYPE_WRCH of fifo_gen_inst : label is 0;
attribute C_RACH_TYPE : integer;
attribute C_RACH_TYPE of fifo_gen_inst : label is 0;
attribute C_RDCH_TYPE : integer;
attribute C_RDCH_TYPE of fifo_gen_inst : label is 0;
attribute C_RD_DATA_COUNT_WIDTH : integer;
attribute C_RD_DATA_COUNT_WIDTH of fifo_gen_inst : label is 6;
attribute C_RD_DEPTH : integer;
attribute C_RD_DEPTH of fifo_gen_inst : label is 32;
attribute C_RD_FREQ : integer;
attribute C_RD_FREQ of fifo_gen_inst : label is 1;
attribute C_RD_PNTR_WIDTH : integer;
attribute C_RD_PNTR_WIDTH of fifo_gen_inst : label is 5;
attribute C_REG_SLICE_MODE_AXIS : integer;
attribute C_REG_SLICE_MODE_AXIS of fifo_gen_inst : label is 0;
attribute C_REG_SLICE_MODE_RACH : integer;
attribute C_REG_SLICE_MODE_RACH of fifo_gen_inst : label is 0;
attribute C_REG_SLICE_MODE_RDCH : integer;
attribute C_REG_SLICE_MODE_RDCH of fifo_gen_inst : label is 0;
attribute C_REG_SLICE_MODE_WACH : integer;
attribute C_REG_SLICE_MODE_WACH of fifo_gen_inst : label is 0;
attribute C_REG_SLICE_MODE_WDCH : integer;
attribute C_REG_SLICE_MODE_WDCH of fifo_gen_inst : label is 0;
attribute C_REG_SLICE_MODE_WRCH : integer;
attribute C_REG_SLICE_MODE_WRCH of fifo_gen_inst : label is 0;
attribute C_SELECT_XPM : integer;
attribute C_SELECT_XPM of fifo_gen_inst : label is 0;
attribute C_SYNCHRONIZER_STAGE : integer;
attribute C_SYNCHRONIZER_STAGE of fifo_gen_inst : label is 3;
attribute C_UNDERFLOW_LOW : integer;
attribute C_UNDERFLOW_LOW of fifo_gen_inst : label is 0;
attribute C_USE_COMMON_OVERFLOW : integer;
attribute C_USE_COMMON_OVERFLOW of fifo_gen_inst : label is 0;
attribute C_USE_COMMON_UNDERFLOW : integer;
attribute C_USE_COMMON_UNDERFLOW of fifo_gen_inst : label is 0;
attribute C_USE_DEFAULT_SETTINGS : integer;
attribute C_USE_DEFAULT_SETTINGS of fifo_gen_inst : label is 0;
attribute C_USE_DOUT_RST : integer;
attribute C_USE_DOUT_RST of fifo_gen_inst : label is 0;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of fifo_gen_inst : label is 0;
attribute C_USE_ECC_AXIS : integer;
attribute C_USE_ECC_AXIS of fifo_gen_inst : label is 0;
attribute C_USE_ECC_RACH : integer;
attribute C_USE_ECC_RACH of fifo_gen_inst : label is 0;
attribute C_USE_ECC_RDCH : integer;
attribute C_USE_ECC_RDCH of fifo_gen_inst : label is 0;
attribute C_USE_ECC_WACH : integer;
attribute C_USE_ECC_WACH of fifo_gen_inst : label is 0;
attribute C_USE_ECC_WDCH : integer;
attribute C_USE_ECC_WDCH of fifo_gen_inst : label is 0;
attribute C_USE_ECC_WRCH : integer;
attribute C_USE_ECC_WRCH of fifo_gen_inst : label is 0;
attribute C_USE_EMBEDDED_REG : integer;
attribute C_USE_EMBEDDED_REG of fifo_gen_inst : label is 0;
attribute C_USE_FIFO16_FLAGS : integer;
attribute C_USE_FIFO16_FLAGS of fifo_gen_inst : label is 0;
attribute C_USE_FWFT_DATA_COUNT : integer;
attribute C_USE_FWFT_DATA_COUNT of fifo_gen_inst : label is 1;
attribute C_USE_PIPELINE_REG : integer;
attribute C_USE_PIPELINE_REG of fifo_gen_inst : label is 0;
attribute C_VALID_LOW : integer;
attribute C_VALID_LOW of fifo_gen_inst : label is 0;
attribute C_WACH_TYPE : integer;
attribute C_WACH_TYPE of fifo_gen_inst : label is 0;
attribute C_WDCH_TYPE : integer;
attribute C_WDCH_TYPE of fifo_gen_inst : label is 0;
attribute C_WRCH_TYPE : integer;
attribute C_WRCH_TYPE of fifo_gen_inst : label is 0;
attribute C_WR_ACK_LOW : integer;
attribute C_WR_ACK_LOW of fifo_gen_inst : label is 0;
attribute C_WR_DATA_COUNT_WIDTH : integer;
attribute C_WR_DATA_COUNT_WIDTH of fifo_gen_inst : label is 6;
attribute C_WR_DEPTH : integer;
attribute C_WR_DEPTH of fifo_gen_inst : label is 32;
attribute C_WR_DEPTH_AXIS : integer;
attribute C_WR_DEPTH_AXIS of fifo_gen_inst : label is 1024;
attribute C_WR_DEPTH_RACH : integer;
attribute C_WR_DEPTH_RACH of fifo_gen_inst : label is 16;
attribute C_WR_DEPTH_RDCH : integer;
attribute C_WR_DEPTH_RDCH of fifo_gen_inst : label is 1024;
attribute C_WR_DEPTH_WACH : integer;
attribute C_WR_DEPTH_WACH of fifo_gen_inst : label is 16;
attribute C_WR_DEPTH_WDCH : integer;
attribute C_WR_DEPTH_WDCH of fifo_gen_inst : label is 1024;
attribute C_WR_DEPTH_WRCH : integer;
attribute C_WR_DEPTH_WRCH of fifo_gen_inst : label is 16;
attribute C_WR_FREQ : integer;
attribute C_WR_FREQ of fifo_gen_inst : label is 1;
attribute C_WR_PNTR_WIDTH : integer;
attribute C_WR_PNTR_WIDTH of fifo_gen_inst : label is 5;
attribute C_WR_PNTR_WIDTH_AXIS : integer;
attribute C_WR_PNTR_WIDTH_AXIS of fifo_gen_inst : label is 10;
attribute C_WR_PNTR_WIDTH_RACH : integer;
attribute C_WR_PNTR_WIDTH_RACH of fifo_gen_inst : label is 4;
attribute C_WR_PNTR_WIDTH_RDCH : integer;
attribute C_WR_PNTR_WIDTH_RDCH of fifo_gen_inst : label is 10;
attribute C_WR_PNTR_WIDTH_WACH : integer;
attribute C_WR_PNTR_WIDTH_WACH of fifo_gen_inst : label is 4;
attribute C_WR_PNTR_WIDTH_WDCH : integer;
attribute C_WR_PNTR_WIDTH_WDCH of fifo_gen_inst : label is 10;
attribute C_WR_PNTR_WIDTH_WRCH : integer;
attribute C_WR_PNTR_WIDTH_WRCH of fifo_gen_inst : label is 4;
attribute C_WR_RESPONSE_LATENCY : integer;
attribute C_WR_RESPONSE_LATENCY of fifo_gen_inst : label is 1;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of m_axi_wvalid_INST_0 : label is "soft_lutpair32";
attribute SOFT_HLUTNM of s_axi_wready_INST_0 : label is "soft_lutpair32";
begin
SR(0) <= \^sr\(0);
din(3 downto 0) <= \^din\(3 downto 0);
dout(5 downto 0) <= \^dout\(5 downto 0);
empty <= \^empty\;
\length_counter_1_reg_0__s_port_]\ <= \length_counter_1_reg_0__s_net_1\;
S_AXI_AREADY_I_i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => aresetn,
O => \^sr\(0)
);
fifo_gen_inst: entity work.system_auto_pc_1_fifo_generator_v13_1_3
port map (
almost_empty => NLW_fifo_gen_inst_almost_empty_UNCONNECTED,
almost_full => NLW_fifo_gen_inst_almost_full_UNCONNECTED,
axi_ar_data_count(4 downto 0) => NLW_fifo_gen_inst_axi_ar_data_count_UNCONNECTED(4 downto 0),
axi_ar_dbiterr => NLW_fifo_gen_inst_axi_ar_dbiterr_UNCONNECTED,
axi_ar_injectdbiterr => '0',
axi_ar_injectsbiterr => '0',
axi_ar_overflow => NLW_fifo_gen_inst_axi_ar_overflow_UNCONNECTED,
axi_ar_prog_empty => NLW_fifo_gen_inst_axi_ar_prog_empty_UNCONNECTED,
axi_ar_prog_empty_thresh(3 downto 0) => B"0000",
axi_ar_prog_full => NLW_fifo_gen_inst_axi_ar_prog_full_UNCONNECTED,
axi_ar_prog_full_thresh(3 downto 0) => B"0000",
axi_ar_rd_data_count(4 downto 0) => NLW_fifo_gen_inst_axi_ar_rd_data_count_UNCONNECTED(4 downto 0),
axi_ar_sbiterr => NLW_fifo_gen_inst_axi_ar_sbiterr_UNCONNECTED,
axi_ar_underflow => NLW_fifo_gen_inst_axi_ar_underflow_UNCONNECTED,
axi_ar_wr_data_count(4 downto 0) => NLW_fifo_gen_inst_axi_ar_wr_data_count_UNCONNECTED(4 downto 0),
axi_aw_data_count(4 downto 0) => NLW_fifo_gen_inst_axi_aw_data_count_UNCONNECTED(4 downto 0),
axi_aw_dbiterr => NLW_fifo_gen_inst_axi_aw_dbiterr_UNCONNECTED,
axi_aw_injectdbiterr => '0',
axi_aw_injectsbiterr => '0',
axi_aw_overflow => NLW_fifo_gen_inst_axi_aw_overflow_UNCONNECTED,
axi_aw_prog_empty => NLW_fifo_gen_inst_axi_aw_prog_empty_UNCONNECTED,
axi_aw_prog_empty_thresh(3 downto 0) => B"0000",
axi_aw_prog_full => NLW_fifo_gen_inst_axi_aw_prog_full_UNCONNECTED,
axi_aw_prog_full_thresh(3 downto 0) => B"0000",
axi_aw_rd_data_count(4 downto 0) => NLW_fifo_gen_inst_axi_aw_rd_data_count_UNCONNECTED(4 downto 0),
axi_aw_sbiterr => NLW_fifo_gen_inst_axi_aw_sbiterr_UNCONNECTED,
axi_aw_underflow => NLW_fifo_gen_inst_axi_aw_underflow_UNCONNECTED,
axi_aw_wr_data_count(4 downto 0) => NLW_fifo_gen_inst_axi_aw_wr_data_count_UNCONNECTED(4 downto 0),
axi_b_data_count(4 downto 0) => NLW_fifo_gen_inst_axi_b_data_count_UNCONNECTED(4 downto 0),
axi_b_dbiterr => NLW_fifo_gen_inst_axi_b_dbiterr_UNCONNECTED,
axi_b_injectdbiterr => '0',
axi_b_injectsbiterr => '0',
axi_b_overflow => NLW_fifo_gen_inst_axi_b_overflow_UNCONNECTED,
axi_b_prog_empty => NLW_fifo_gen_inst_axi_b_prog_empty_UNCONNECTED,
axi_b_prog_empty_thresh(3 downto 0) => B"0000",
axi_b_prog_full => NLW_fifo_gen_inst_axi_b_prog_full_UNCONNECTED,
axi_b_prog_full_thresh(3 downto 0) => B"0000",
axi_b_rd_data_count(4 downto 0) => NLW_fifo_gen_inst_axi_b_rd_data_count_UNCONNECTED(4 downto 0),
axi_b_sbiterr => NLW_fifo_gen_inst_axi_b_sbiterr_UNCONNECTED,
axi_b_underflow => NLW_fifo_gen_inst_axi_b_underflow_UNCONNECTED,
axi_b_wr_data_count(4 downto 0) => NLW_fifo_gen_inst_axi_b_wr_data_count_UNCONNECTED(4 downto 0),
axi_r_data_count(10 downto 0) => NLW_fifo_gen_inst_axi_r_data_count_UNCONNECTED(10 downto 0),
axi_r_dbiterr => NLW_fifo_gen_inst_axi_r_dbiterr_UNCONNECTED,
axi_r_injectdbiterr => '0',
axi_r_injectsbiterr => '0',
axi_r_overflow => NLW_fifo_gen_inst_axi_r_overflow_UNCONNECTED,
axi_r_prog_empty => NLW_fifo_gen_inst_axi_r_prog_empty_UNCONNECTED,
axi_r_prog_empty_thresh(9 downto 0) => B"0000000000",
axi_r_prog_full => NLW_fifo_gen_inst_axi_r_prog_full_UNCONNECTED,
axi_r_prog_full_thresh(9 downto 0) => B"0000000000",
axi_r_rd_data_count(10 downto 0) => NLW_fifo_gen_inst_axi_r_rd_data_count_UNCONNECTED(10 downto 0),
axi_r_sbiterr => NLW_fifo_gen_inst_axi_r_sbiterr_UNCONNECTED,
axi_r_underflow => NLW_fifo_gen_inst_axi_r_underflow_UNCONNECTED,
axi_r_wr_data_count(10 downto 0) => NLW_fifo_gen_inst_axi_r_wr_data_count_UNCONNECTED(10 downto 0),
axi_w_data_count(10 downto 0) => NLW_fifo_gen_inst_axi_w_data_count_UNCONNECTED(10 downto 0),
axi_w_dbiterr => NLW_fifo_gen_inst_axi_w_dbiterr_UNCONNECTED,
axi_w_injectdbiterr => '0',
axi_w_injectsbiterr => '0',
axi_w_overflow => NLW_fifo_gen_inst_axi_w_overflow_UNCONNECTED,
axi_w_prog_empty => NLW_fifo_gen_inst_axi_w_prog_empty_UNCONNECTED,
axi_w_prog_empty_thresh(9 downto 0) => B"0000000000",
axi_w_prog_full => NLW_fifo_gen_inst_axi_w_prog_full_UNCONNECTED,
axi_w_prog_full_thresh(9 downto 0) => B"0000000000",
axi_w_rd_data_count(10 downto 0) => NLW_fifo_gen_inst_axi_w_rd_data_count_UNCONNECTED(10 downto 0),
axi_w_sbiterr => NLW_fifo_gen_inst_axi_w_sbiterr_UNCONNECTED,
axi_w_underflow => NLW_fifo_gen_inst_axi_w_underflow_UNCONNECTED,
axi_w_wr_data_count(10 downto 0) => NLW_fifo_gen_inst_axi_w_wr_data_count_UNCONNECTED(10 downto 0),
axis_data_count(10 downto 0) => NLW_fifo_gen_inst_axis_data_count_UNCONNECTED(10 downto 0),
axis_dbiterr => NLW_fifo_gen_inst_axis_dbiterr_UNCONNECTED,
axis_injectdbiterr => '0',
axis_injectsbiterr => '0',
axis_overflow => NLW_fifo_gen_inst_axis_overflow_UNCONNECTED,
axis_prog_empty => NLW_fifo_gen_inst_axis_prog_empty_UNCONNECTED,
axis_prog_empty_thresh(9 downto 0) => B"0000000000",
axis_prog_full => NLW_fifo_gen_inst_axis_prog_full_UNCONNECTED,
axis_prog_full_thresh(9 downto 0) => B"0000000000",
axis_rd_data_count(10 downto 0) => NLW_fifo_gen_inst_axis_rd_data_count_UNCONNECTED(10 downto 0),
axis_sbiterr => NLW_fifo_gen_inst_axis_sbiterr_UNCONNECTED,
axis_underflow => NLW_fifo_gen_inst_axis_underflow_UNCONNECTED,
axis_wr_data_count(10 downto 0) => NLW_fifo_gen_inst_axis_wr_data_count_UNCONNECTED(10 downto 0),
backup => '0',
backup_marker => '0',
clk => aclk,
data_count(5 downto 0) => NLW_fifo_gen_inst_data_count_UNCONNECTED(5 downto 0),
dbiterr => NLW_fifo_gen_inst_dbiterr_UNCONNECTED,
din(5 downto 4) => Q(1 downto 0),
din(3 downto 0) => \^din\(3 downto 0),
dout(5 downto 0) => \^dout\(5 downto 0),
empty => \^empty\,
full => full,
injectdbiterr => '0',
injectsbiterr => '0',
int_clk => '0',
m_aclk => '0',
m_aclk_en => '0',
m_axi_araddr(31 downto 0) => NLW_fifo_gen_inst_m_axi_araddr_UNCONNECTED(31 downto 0),
m_axi_arburst(1 downto 0) => NLW_fifo_gen_inst_m_axi_arburst_UNCONNECTED(1 downto 0),
m_axi_arcache(3 downto 0) => NLW_fifo_gen_inst_m_axi_arcache_UNCONNECTED(3 downto 0),
m_axi_arid(3 downto 0) => NLW_fifo_gen_inst_m_axi_arid_UNCONNECTED(3 downto 0),
m_axi_arlen(7 downto 0) => NLW_fifo_gen_inst_m_axi_arlen_UNCONNECTED(7 downto 0),
m_axi_arlock(1 downto 0) => NLW_fifo_gen_inst_m_axi_arlock_UNCONNECTED(1 downto 0),
m_axi_arprot(2 downto 0) => NLW_fifo_gen_inst_m_axi_arprot_UNCONNECTED(2 downto 0),
m_axi_arqos(3 downto 0) => NLW_fifo_gen_inst_m_axi_arqos_UNCONNECTED(3 downto 0),
m_axi_arready => '0',
m_axi_arregion(3 downto 0) => NLW_fifo_gen_inst_m_axi_arregion_UNCONNECTED(3 downto 0),
m_axi_arsize(2 downto 0) => NLW_fifo_gen_inst_m_axi_arsize_UNCONNECTED(2 downto 0),
m_axi_aruser(0) => NLW_fifo_gen_inst_m_axi_aruser_UNCONNECTED(0),
m_axi_arvalid => NLW_fifo_gen_inst_m_axi_arvalid_UNCONNECTED,
m_axi_awaddr(31 downto 0) => NLW_fifo_gen_inst_m_axi_awaddr_UNCONNECTED(31 downto 0),
m_axi_awburst(1 downto 0) => NLW_fifo_gen_inst_m_axi_awburst_UNCONNECTED(1 downto 0),
m_axi_awcache(3 downto 0) => NLW_fifo_gen_inst_m_axi_awcache_UNCONNECTED(3 downto 0),
m_axi_awid(3 downto 0) => NLW_fifo_gen_inst_m_axi_awid_UNCONNECTED(3 downto 0),
m_axi_awlen(7 downto 0) => NLW_fifo_gen_inst_m_axi_awlen_UNCONNECTED(7 downto 0),
m_axi_awlock(1 downto 0) => NLW_fifo_gen_inst_m_axi_awlock_UNCONNECTED(1 downto 0),
m_axi_awprot(2 downto 0) => NLW_fifo_gen_inst_m_axi_awprot_UNCONNECTED(2 downto 0),
m_axi_awqos(3 downto 0) => NLW_fifo_gen_inst_m_axi_awqos_UNCONNECTED(3 downto 0),
m_axi_awready => '0',
m_axi_awregion(3 downto 0) => NLW_fifo_gen_inst_m_axi_awregion_UNCONNECTED(3 downto 0),
m_axi_awsize(2 downto 0) => NLW_fifo_gen_inst_m_axi_awsize_UNCONNECTED(2 downto 0),
m_axi_awuser(0) => NLW_fifo_gen_inst_m_axi_awuser_UNCONNECTED(0),
m_axi_awvalid => NLW_fifo_gen_inst_m_axi_awvalid_UNCONNECTED,
m_axi_bid(3 downto 0) => B"0000",
m_axi_bready => NLW_fifo_gen_inst_m_axi_bready_UNCONNECTED,
m_axi_bresp(1 downto 0) => B"00",
m_axi_buser(0) => '0',
m_axi_bvalid => '0',
m_axi_rdata(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
m_axi_rid(3 downto 0) => B"0000",
m_axi_rlast => '0',
m_axi_rready => NLW_fifo_gen_inst_m_axi_rready_UNCONNECTED,
m_axi_rresp(1 downto 0) => B"00",
m_axi_ruser(0) => '0',
m_axi_rvalid => '0',
m_axi_wdata(63 downto 0) => NLW_fifo_gen_inst_m_axi_wdata_UNCONNECTED(63 downto 0),
m_axi_wid(3 downto 0) => NLW_fifo_gen_inst_m_axi_wid_UNCONNECTED(3 downto 0),
m_axi_wlast => NLW_fifo_gen_inst_m_axi_wlast_UNCONNECTED,
m_axi_wready => '0',
m_axi_wstrb(7 downto 0) => NLW_fifo_gen_inst_m_axi_wstrb_UNCONNECTED(7 downto 0),
m_axi_wuser(0) => NLW_fifo_gen_inst_m_axi_wuser_UNCONNECTED(0),
m_axi_wvalid => NLW_fifo_gen_inst_m_axi_wvalid_UNCONNECTED,
m_axis_tdata(63 downto 0) => NLW_fifo_gen_inst_m_axis_tdata_UNCONNECTED(63 downto 0),
m_axis_tdest(3 downto 0) => NLW_fifo_gen_inst_m_axis_tdest_UNCONNECTED(3 downto 0),
m_axis_tid(7 downto 0) => NLW_fifo_gen_inst_m_axis_tid_UNCONNECTED(7 downto 0),
m_axis_tkeep(3 downto 0) => NLW_fifo_gen_inst_m_axis_tkeep_UNCONNECTED(3 downto 0),
m_axis_tlast => NLW_fifo_gen_inst_m_axis_tlast_UNCONNECTED,
m_axis_tready => '0',
m_axis_tstrb(3 downto 0) => NLW_fifo_gen_inst_m_axis_tstrb_UNCONNECTED(3 downto 0),
m_axis_tuser(3 downto 0) => NLW_fifo_gen_inst_m_axis_tuser_UNCONNECTED(3 downto 0),
m_axis_tvalid => NLW_fifo_gen_inst_m_axis_tvalid_UNCONNECTED,
overflow => NLW_fifo_gen_inst_overflow_UNCONNECTED,
prog_empty => NLW_fifo_gen_inst_prog_empty_UNCONNECTED,
prog_empty_thresh(4 downto 0) => B"00000",
prog_empty_thresh_assert(4 downto 0) => B"00000",
prog_empty_thresh_negate(4 downto 0) => B"00000",
prog_full => NLW_fifo_gen_inst_prog_full_UNCONNECTED,
prog_full_thresh(4 downto 0) => B"00000",
prog_full_thresh_assert(4 downto 0) => B"00000",
prog_full_thresh_negate(4 downto 0) => B"00000",
rd_clk => '0',
rd_data_count(5 downto 0) => NLW_fifo_gen_inst_rd_data_count_UNCONNECTED(5 downto 0),
rd_en => wr_cmd_ready,
rd_rst => '0',
rd_rst_busy => NLW_fifo_gen_inst_rd_rst_busy_UNCONNECTED,
rst => \^sr\(0),
s_aclk => '0',
s_aclk_en => '0',
s_aresetn => '0',
s_axi_araddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_arburst(1 downto 0) => B"00",
s_axi_arcache(3 downto 0) => B"0000",
s_axi_arid(3 downto 0) => B"0000",
s_axi_arlen(7 downto 0) => B"00000000",
s_axi_arlock(1 downto 0) => B"00",
s_axi_arprot(2 downto 0) => B"000",
s_axi_arqos(3 downto 0) => B"0000",
s_axi_arready => NLW_fifo_gen_inst_s_axi_arready_UNCONNECTED,
s_axi_arregion(3 downto 0) => B"0000",
s_axi_arsize(2 downto 0) => B"000",
s_axi_aruser(0) => '0',
s_axi_arvalid => '0',
s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_awburst(1 downto 0) => B"00",
s_axi_awcache(3 downto 0) => B"0000",
s_axi_awid(3 downto 0) => B"0000",
s_axi_awlen(7 downto 0) => B"00000000",
s_axi_awlock(1 downto 0) => B"00",
s_axi_awprot(2 downto 0) => B"000",
s_axi_awqos(3 downto 0) => B"0000",
s_axi_awready => NLW_fifo_gen_inst_s_axi_awready_UNCONNECTED,
s_axi_awregion(3 downto 0) => B"0000",
s_axi_awsize(2 downto 0) => B"000",
s_axi_awuser(0) => '0',
s_axi_awvalid => '0',
s_axi_bid(3 downto 0) => NLW_fifo_gen_inst_s_axi_bid_UNCONNECTED(3 downto 0),
s_axi_bready => '0',
s_axi_bresp(1 downto 0) => NLW_fifo_gen_inst_s_axi_bresp_UNCONNECTED(1 downto 0),
s_axi_buser(0) => NLW_fifo_gen_inst_s_axi_buser_UNCONNECTED(0),
s_axi_bvalid => NLW_fifo_gen_inst_s_axi_bvalid_UNCONNECTED,
s_axi_rdata(63 downto 0) => NLW_fifo_gen_inst_s_axi_rdata_UNCONNECTED(63 downto 0),
s_axi_rid(3 downto 0) => NLW_fifo_gen_inst_s_axi_rid_UNCONNECTED(3 downto 0),
s_axi_rlast => NLW_fifo_gen_inst_s_axi_rlast_UNCONNECTED,
s_axi_rready => '0',
s_axi_rresp(1 downto 0) => NLW_fifo_gen_inst_s_axi_rresp_UNCONNECTED(1 downto 0),
s_axi_ruser(0) => NLW_fifo_gen_inst_s_axi_ruser_UNCONNECTED(0),
s_axi_rvalid => NLW_fifo_gen_inst_s_axi_rvalid_UNCONNECTED,
s_axi_wdata(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
s_axi_wid(3 downto 0) => B"0000",
s_axi_wlast => '0',
s_axi_wready => NLW_fifo_gen_inst_s_axi_wready_UNCONNECTED,
s_axi_wstrb(7 downto 0) => B"00000000",
s_axi_wuser(0) => '0',
s_axi_wvalid => '0',
s_axis_tdata(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
s_axis_tdest(3 downto 0) => B"0000",
s_axis_tid(7 downto 0) => B"00000000",
s_axis_tkeep(3 downto 0) => B"0000",
s_axis_tlast => '0',
s_axis_tready => NLW_fifo_gen_inst_s_axis_tready_UNCONNECTED,
s_axis_tstrb(3 downto 0) => B"0000",
s_axis_tuser(3 downto 0) => B"0000",
s_axis_tvalid => '0',
sbiterr => NLW_fifo_gen_inst_sbiterr_UNCONNECTED,
sleep => '0',
srst => '0',
underflow => NLW_fifo_gen_inst_underflow_UNCONNECTED,
valid => NLW_fifo_gen_inst_valid_UNCONNECTED,
wr_ack => NLW_fifo_gen_inst_wr_ack_UNCONNECTED,
wr_clk => '0',
wr_data_count(5 downto 0) => NLW_fifo_gen_inst_wr_data_count_UNCONNECTED(5 downto 0),
wr_en => wr_en,
wr_rst => '0',
wr_rst_busy => NLW_fifo_gen_inst_wr_rst_busy_UNCONNECTED
);
\length_counter_1[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0F047F0F0F0F0F0"
)
port map (
I0 => \^dout\(0),
I1 => first_mi_word,
I2 => length_counter_1_reg(0),
I3 => m_axi_wready,
I4 => \^empty\,
I5 => s_axi_wvalid,
O => \length_counter_1_reg_0__s_net_1\
);
\m_axi_awlen[0]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFEAAAAAAAA"
)
port map (
I0 => \S_AXI_ALEN_Q_reg[3]\(0),
I1 => \pushed_commands_reg[3]\(1),
I2 => \pushed_commands_reg[3]\(0),
I3 => \pushed_commands_reg[3]\(3),
I4 => \pushed_commands_reg[3]\(2),
I5 => need_to_split_q,
O => \^din\(0)
);
\m_axi_awlen[1]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFEAAAAAAAA"
)
port map (
I0 => \S_AXI_ALEN_Q_reg[3]\(1),
I1 => \pushed_commands_reg[3]\(1),
I2 => \pushed_commands_reg[3]\(0),
I3 => \pushed_commands_reg[3]\(3),
I4 => \pushed_commands_reg[3]\(2),
I5 => need_to_split_q,
O => \^din\(1)
);
\m_axi_awlen[2]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFEAAAAAAAA"
)
port map (
I0 => \S_AXI_ALEN_Q_reg[3]\(2),
I1 => \pushed_commands_reg[3]\(1),
I2 => \pushed_commands_reg[3]\(0),
I3 => \pushed_commands_reg[3]\(3),
I4 => \pushed_commands_reg[3]\(2),
I5 => need_to_split_q,
O => \^din\(2)
);
\m_axi_awlen[3]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFEAAAAAAAA"
)
port map (
I0 => \S_AXI_ALEN_Q_reg[3]\(3),
I1 => \pushed_commands_reg[3]\(1),
I2 => \pushed_commands_reg[3]\(0),
I3 => \pushed_commands_reg[3]\(3),
I4 => \pushed_commands_reg[3]\(2),
I5 => need_to_split_q,
O => \^din\(3)
);
m_axi_awvalid_INST_0_i_2: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => cmd_push_block,
I1 => command_ongoing,
O => \USE_B_CHANNEL.cmd_b_empty_reg_0\
);
m_axi_awvalid_INST_0_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"0770777777770770"
)
port map (
I0 => cmd_empty,
I1 => cmd_b_empty,
I2 => queue_id(1),
I3 => Q(1),
I4 => queue_id(0),
I5 => Q(0),
O => \USE_B_CHANNEL.cmd_b_empty_reg\
);
m_axi_wvalid_INST_0: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_wvalid,
I1 => \^empty\,
O => m_axi_wvalid
);
s_axi_wready_INST_0: unisim.vcomponents.LUT3
generic map(
INIT => X"20"
)
port map (
I0 => m_axi_wready,
I1 => \^empty\,
I2 => s_axi_wvalid,
O => s_axi_wready
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_auto_pc_1_axi_data_fifo_v2_1_10_fifo_gen__parameterized0\ is
port (
first_mi_word_reg : out STD_LOGIC_VECTOR ( 4 downto 0 );
\gpregsm1.user_valid_reg\ : out STD_LOGIC;
din : out STD_LOGIC_VECTOR ( 0 to 0 );
D : out STD_LOGIC_VECTOR ( 4 downto 0 );
wr_en : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
multiple_id_non_split_reg : out STD_LOGIC;
split_in_progress_reg : out STD_LOGIC;
cmd_push_block_reg : out STD_LOGIC;
\pushed_commands_reg[0]\ : out STD_LOGIC;
cmd_empty_reg : out STD_LOGIC;
\queue_id_reg[0]\ : out STD_LOGIC;
\queue_id_reg[1]\ : out STD_LOGIC;
cmd_b_push_block_reg : out STD_LOGIC;
\USE_B_CHANNEL.cmd_b_depth_reg[5]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\USE_B_CHANNEL.cmd_b_empty_reg\ : out STD_LOGIC;
\USE_B_CHANNEL.cmd_b_depth_reg[5]_0\ : out STD_LOGIC_VECTOR ( 4 downto 0 );
m_axi_awvalid : out STD_LOGIC;
S_AXI_AREADY_I_reg : out STD_LOGIC;
command_ongoing_reg : out STD_LOGIC;
aclk : in STD_LOGIC;
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
\num_transactions_q_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
wr_cmd_b_ready : in STD_LOGIC;
almost_empty : in STD_LOGIC;
wr_cmd_ready : in STD_LOGIC;
cmd_empty : in STD_LOGIC;
aresetn : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 5 downto 0 );
need_to_split_q : in STD_LOGIC;
cmd_push_block : in STD_LOGIC;
multiple_id_non_split : in STD_LOGIC;
\S_AXI_AID_Q_reg[0]\ : in STD_LOGIC;
incr_need_to_split_q_reg : in STD_LOGIC;
split_in_progress_reg_0 : in STD_LOGIC;
m_axi_awready : in STD_LOGIC;
\S_AXI_AID_Q_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
queue_id : in STD_LOGIC_VECTOR ( 1 downto 0 );
cmd_b_push_block : in STD_LOGIC;
S_AXI_AREADY_I_reg_0 : in STD_LOGIC;
almost_b_empty : in STD_LOGIC;
cmd_b_empty : in STD_LOGIC;
\USE_B_CHANNEL.cmd_b_depth_reg[5]_1\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
\goreg_dm.dout_i_reg[4]\ : in STD_LOGIC;
m_axi_bvalid : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
cmd_push_block_reg_0 : in STD_LOGIC;
cmd_empty_reg_0 : in STD_LOGIC;
command_ongoing : in STD_LOGIC;
full : in STD_LOGIC;
access_is_incr_q : in STD_LOGIC;
\pushed_commands_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\areset_d_reg[0]\ : in STD_LOGIC;
areset_d : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awvalid : in STD_LOGIC;
\areset_d_reg[1]\ : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_auto_pc_1_axi_data_fifo_v2_1_10_fifo_gen__parameterized0\ : entity is "axi_data_fifo_v2_1_10_fifo_gen";
end \system_auto_pc_1_axi_data_fifo_v2_1_10_fifo_gen__parameterized0\;
architecture STRUCTURE of \system_auto_pc_1_axi_data_fifo_v2_1_10_fifo_gen__parameterized0\ is
signal S_AXI_AREADY_I_i_3_n_0 : STD_LOGIC;
signal S_AXI_AREADY_I_i_4_n_0 : STD_LOGIC;
signal \USE_B_CHANNEL.cmd_b_depth[5]_i_3_n_0\ : STD_LOGIC;
signal cmd_b_empty0 : STD_LOGIC;
signal cmd_b_push : STD_LOGIC;
signal \cmd_depth[4]_i_2_n_0\ : STD_LOGIC;
signal \cmd_depth[5]_i_3_n_0\ : STD_LOGIC;
signal \cmd_depth[5]_i_4_n_0\ : STD_LOGIC;
signal \^din\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal full_0 : STD_LOGIC;
signal \^gpregsm1.user_valid_reg\ : STD_LOGIC;
signal m_axi_awvalid_INST_0_i_1_n_0 : STD_LOGIC;
signal m_axi_awvalid_INST_0_i_3_n_0 : STD_LOGIC;
signal \multiple_id_non_split_i_4__0_n_0\ : STD_LOGIC;
signal multiple_id_non_split_i_5_n_0 : STD_LOGIC;
signal \^pushed_commands_reg[0]\ : STD_LOGIC;
signal NLW_fifo_gen_inst_almost_empty_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_almost_full_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axi_ar_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axi_ar_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axi_ar_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axi_ar_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axi_ar_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axi_ar_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axi_aw_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axi_aw_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axi_aw_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axi_aw_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axi_aw_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axi_aw_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axi_b_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axi_b_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axi_b_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axi_b_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axi_b_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axi_b_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axi_r_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axi_r_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axi_r_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axi_r_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axi_r_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axi_r_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axi_w_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axi_w_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axi_w_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axi_w_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axi_w_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axi_w_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axis_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axis_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axis_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axis_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axis_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axis_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_m_axi_arvalid_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_m_axi_awvalid_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_m_axi_bready_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_m_axi_rready_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_m_axi_wlast_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_m_axi_wvalid_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_m_axis_tlast_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_m_axis_tvalid_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_rd_rst_busy_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_s_axi_arready_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_s_axi_awready_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_s_axi_rlast_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_s_axi_wready_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_s_axis_tready_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_valid_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_wr_ack_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_wr_rst_busy_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axi_ar_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_fifo_gen_inst_axi_ar_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_fifo_gen_inst_axi_ar_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_fifo_gen_inst_axi_aw_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_fifo_gen_inst_axi_aw_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_fifo_gen_inst_axi_aw_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_fifo_gen_inst_axi_b_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_fifo_gen_inst_axi_b_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_fifo_gen_inst_axi_b_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_fifo_gen_inst_axi_r_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_fifo_gen_inst_axi_r_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_fifo_gen_inst_axi_r_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_fifo_gen_inst_axi_w_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_fifo_gen_inst_axi_w_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_fifo_gen_inst_axi_w_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_fifo_gen_inst_axis_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_fifo_gen_inst_axis_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_fifo_gen_inst_axis_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_fifo_gen_inst_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_fifo_gen_inst_m_axi_araddr_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_fifo_gen_inst_m_axi_arburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_fifo_gen_inst_m_axi_arcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_fifo_gen_inst_m_axi_arid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_fifo_gen_inst_m_axi_arlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_fifo_gen_inst_m_axi_arlock_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_fifo_gen_inst_m_axi_arprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_fifo_gen_inst_m_axi_arqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_fifo_gen_inst_m_axi_arregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_fifo_gen_inst_m_axi_arsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_fifo_gen_inst_m_axi_aruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_fifo_gen_inst_m_axi_awaddr_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_fifo_gen_inst_m_axi_awburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_fifo_gen_inst_m_axi_awcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_fifo_gen_inst_m_axi_awid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_fifo_gen_inst_m_axi_awlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_fifo_gen_inst_m_axi_awlock_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_fifo_gen_inst_m_axi_awprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_fifo_gen_inst_m_axi_awqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_fifo_gen_inst_m_axi_awregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_fifo_gen_inst_m_axi_awsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_fifo_gen_inst_m_axi_awuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_fifo_gen_inst_m_axi_wdata_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_fifo_gen_inst_m_axi_wid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_fifo_gen_inst_m_axi_wstrb_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_fifo_gen_inst_m_axi_wuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_fifo_gen_inst_m_axis_tdata_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_fifo_gen_inst_m_axis_tdest_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_fifo_gen_inst_m_axis_tid_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_fifo_gen_inst_m_axis_tkeep_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_fifo_gen_inst_m_axis_tstrb_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_fifo_gen_inst_m_axis_tuser_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_fifo_gen_inst_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_fifo_gen_inst_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_fifo_gen_inst_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_fifo_gen_inst_s_axi_buser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_fifo_gen_inst_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_fifo_gen_inst_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_fifo_gen_inst_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_fifo_gen_inst_s_axi_ruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_fifo_gen_inst_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \USE_B_CHANNEL.cmd_b_depth[2]_i_1\ : label is "soft_lutpair43";
attribute SOFT_HLUTNM of \USE_B_CHANNEL.cmd_b_depth[3]_i_1\ : label is "soft_lutpair43";
attribute SOFT_HLUTNM of \USE_B_CHANNEL.cmd_b_depth[5]_i_1\ : label is "soft_lutpair39";
attribute SOFT_HLUTNM of \USE_B_CHANNEL.cmd_b_empty_i_1\ : label is "soft_lutpair39";
attribute SOFT_HLUTNM of cmd_b_push_block_i_1 : label is "soft_lutpair44";
attribute SOFT_HLUTNM of \cmd_depth[2]_i_1\ : label is "soft_lutpair40";
attribute SOFT_HLUTNM of \cmd_depth[3]_i_1\ : label is "soft_lutpair40";
attribute SOFT_HLUTNM of \cmd_depth[4]_i_2\ : label is "soft_lutpair42";
attribute SOFT_HLUTNM of \cmd_depth[5]_i_1__0\ : label is "soft_lutpair41";
attribute SOFT_HLUTNM of \cmd_depth[5]_i_4\ : label is "soft_lutpair41";
attribute SOFT_HLUTNM of cmd_empty_i_1 : label is "soft_lutpair42";
attribute SOFT_HLUTNM of \cmd_push_block_i_1__0\ : label is "soft_lutpair37";
attribute C_ADD_NGC_CONSTRAINT : integer;
attribute C_ADD_NGC_CONSTRAINT of fifo_gen_inst : label is 0;
attribute C_APPLICATION_TYPE_AXIS : integer;
attribute C_APPLICATION_TYPE_AXIS of fifo_gen_inst : label is 0;
attribute C_APPLICATION_TYPE_RACH : integer;
attribute C_APPLICATION_TYPE_RACH of fifo_gen_inst : label is 0;
attribute C_APPLICATION_TYPE_RDCH : integer;
attribute C_APPLICATION_TYPE_RDCH of fifo_gen_inst : label is 0;
attribute C_APPLICATION_TYPE_WACH : integer;
attribute C_APPLICATION_TYPE_WACH of fifo_gen_inst : label is 0;
attribute C_APPLICATION_TYPE_WDCH : integer;
attribute C_APPLICATION_TYPE_WDCH of fifo_gen_inst : label is 0;
attribute C_APPLICATION_TYPE_WRCH : integer;
attribute C_APPLICATION_TYPE_WRCH of fifo_gen_inst : label is 0;
attribute C_AXIS_TDATA_WIDTH : integer;
attribute C_AXIS_TDATA_WIDTH of fifo_gen_inst : label is 64;
attribute C_AXIS_TDEST_WIDTH : integer;
attribute C_AXIS_TDEST_WIDTH of fifo_gen_inst : label is 4;
attribute C_AXIS_TID_WIDTH : integer;
attribute C_AXIS_TID_WIDTH of fifo_gen_inst : label is 8;
attribute C_AXIS_TKEEP_WIDTH : integer;
attribute C_AXIS_TKEEP_WIDTH of fifo_gen_inst : label is 4;
attribute C_AXIS_TSTRB_WIDTH : integer;
attribute C_AXIS_TSTRB_WIDTH of fifo_gen_inst : label is 4;
attribute C_AXIS_TUSER_WIDTH : integer;
attribute C_AXIS_TUSER_WIDTH of fifo_gen_inst : label is 4;
attribute C_AXIS_TYPE : integer;
attribute C_AXIS_TYPE of fifo_gen_inst : label is 0;
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of fifo_gen_inst : label is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of fifo_gen_inst : label is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of fifo_gen_inst : label is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of fifo_gen_inst : label is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of fifo_gen_inst : label is 64;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of fifo_gen_inst : label is 4;
attribute C_AXI_LEN_WIDTH : integer;
attribute C_AXI_LEN_WIDTH of fifo_gen_inst : label is 8;
attribute C_AXI_LOCK_WIDTH : integer;
attribute C_AXI_LOCK_WIDTH of fifo_gen_inst : label is 2;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of fifo_gen_inst : label is 1;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of fifo_gen_inst : label is 0;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of fifo_gen_inst : label is 1;
attribute C_COMMON_CLOCK : integer;
attribute C_COMMON_CLOCK of fifo_gen_inst : label is 1;
attribute C_COUNT_TYPE : integer;
attribute C_COUNT_TYPE of fifo_gen_inst : label is 0;
attribute C_DATA_COUNT_WIDTH : integer;
attribute C_DATA_COUNT_WIDTH of fifo_gen_inst : label is 6;
attribute C_DEFAULT_VALUE : string;
attribute C_DEFAULT_VALUE of fifo_gen_inst : label is "BlankString";
attribute C_DIN_WIDTH : integer;
attribute C_DIN_WIDTH of fifo_gen_inst : label is 5;
attribute C_DIN_WIDTH_AXIS : integer;
attribute C_DIN_WIDTH_AXIS of fifo_gen_inst : label is 1;
attribute C_DIN_WIDTH_RACH : integer;
attribute C_DIN_WIDTH_RACH of fifo_gen_inst : label is 32;
attribute C_DIN_WIDTH_RDCH : integer;
attribute C_DIN_WIDTH_RDCH of fifo_gen_inst : label is 64;
attribute C_DIN_WIDTH_WACH : integer;
attribute C_DIN_WIDTH_WACH of fifo_gen_inst : label is 32;
attribute C_DIN_WIDTH_WDCH : integer;
attribute C_DIN_WIDTH_WDCH of fifo_gen_inst : label is 64;
attribute C_DIN_WIDTH_WRCH : integer;
attribute C_DIN_WIDTH_WRCH of fifo_gen_inst : label is 2;
attribute C_DOUT_RST_VAL : string;
attribute C_DOUT_RST_VAL of fifo_gen_inst : label is "0";
attribute C_DOUT_WIDTH : integer;
attribute C_DOUT_WIDTH of fifo_gen_inst : label is 5;
attribute C_ENABLE_RLOCS : integer;
attribute C_ENABLE_RLOCS of fifo_gen_inst : label is 0;
attribute C_ENABLE_RST_SYNC : integer;
attribute C_ENABLE_RST_SYNC of fifo_gen_inst : label is 1;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of fifo_gen_inst : label is 0;
attribute C_ERROR_INJECTION_TYPE : integer;
attribute C_ERROR_INJECTION_TYPE of fifo_gen_inst : label is 0;
attribute C_ERROR_INJECTION_TYPE_AXIS : integer;
attribute C_ERROR_INJECTION_TYPE_AXIS of fifo_gen_inst : label is 0;
attribute C_ERROR_INJECTION_TYPE_RACH : integer;
attribute C_ERROR_INJECTION_TYPE_RACH of fifo_gen_inst : label is 0;
attribute C_ERROR_INJECTION_TYPE_RDCH : integer;
attribute C_ERROR_INJECTION_TYPE_RDCH of fifo_gen_inst : label is 0;
attribute C_ERROR_INJECTION_TYPE_WACH : integer;
attribute C_ERROR_INJECTION_TYPE_WACH of fifo_gen_inst : label is 0;
attribute C_ERROR_INJECTION_TYPE_WDCH : integer;
attribute C_ERROR_INJECTION_TYPE_WDCH of fifo_gen_inst : label is 0;
attribute C_ERROR_INJECTION_TYPE_WRCH : integer;
attribute C_ERROR_INJECTION_TYPE_WRCH of fifo_gen_inst : label is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of fifo_gen_inst : label is "zynq";
attribute C_FULL_FLAGS_RST_VAL : integer;
attribute C_FULL_FLAGS_RST_VAL of fifo_gen_inst : label is 0;
attribute C_HAS_ALMOST_EMPTY : integer;
attribute C_HAS_ALMOST_EMPTY of fifo_gen_inst : label is 0;
attribute C_HAS_ALMOST_FULL : integer;
attribute C_HAS_ALMOST_FULL of fifo_gen_inst : label is 0;
attribute C_HAS_AXIS_TDATA : integer;
attribute C_HAS_AXIS_TDATA of fifo_gen_inst : label is 0;
attribute C_HAS_AXIS_TDEST : integer;
attribute C_HAS_AXIS_TDEST of fifo_gen_inst : label is 0;
attribute C_HAS_AXIS_TID : integer;
attribute C_HAS_AXIS_TID of fifo_gen_inst : label is 0;
attribute C_HAS_AXIS_TKEEP : integer;
attribute C_HAS_AXIS_TKEEP of fifo_gen_inst : label is 0;
attribute C_HAS_AXIS_TLAST : integer;
attribute C_HAS_AXIS_TLAST of fifo_gen_inst : label is 0;
attribute C_HAS_AXIS_TREADY : integer;
attribute C_HAS_AXIS_TREADY of fifo_gen_inst : label is 1;
attribute C_HAS_AXIS_TSTRB : integer;
attribute C_HAS_AXIS_TSTRB of fifo_gen_inst : label is 0;
attribute C_HAS_AXIS_TUSER : integer;
attribute C_HAS_AXIS_TUSER of fifo_gen_inst : label is 0;
attribute C_HAS_AXI_ARUSER : integer;
attribute C_HAS_AXI_ARUSER of fifo_gen_inst : label is 0;
attribute C_HAS_AXI_AWUSER : integer;
attribute C_HAS_AXI_AWUSER of fifo_gen_inst : label is 0;
attribute C_HAS_AXI_BUSER : integer;
attribute C_HAS_AXI_BUSER of fifo_gen_inst : label is 0;
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of fifo_gen_inst : label is 0;
attribute C_HAS_AXI_RD_CHANNEL : integer;
attribute C_HAS_AXI_RD_CHANNEL of fifo_gen_inst : label is 0;
attribute C_HAS_AXI_RUSER : integer;
attribute C_HAS_AXI_RUSER of fifo_gen_inst : label is 0;
attribute C_HAS_AXI_WR_CHANNEL : integer;
attribute C_HAS_AXI_WR_CHANNEL of fifo_gen_inst : label is 0;
attribute C_HAS_AXI_WUSER : integer;
attribute C_HAS_AXI_WUSER of fifo_gen_inst : label is 0;
attribute C_HAS_BACKUP : integer;
attribute C_HAS_BACKUP of fifo_gen_inst : label is 0;
attribute C_HAS_DATA_COUNT : integer;
attribute C_HAS_DATA_COUNT of fifo_gen_inst : label is 0;
attribute C_HAS_DATA_COUNTS_AXIS : integer;
attribute C_HAS_DATA_COUNTS_AXIS of fifo_gen_inst : label is 0;
attribute C_HAS_DATA_COUNTS_RACH : integer;
attribute C_HAS_DATA_COUNTS_RACH of fifo_gen_inst : label is 0;
attribute C_HAS_DATA_COUNTS_RDCH : integer;
attribute C_HAS_DATA_COUNTS_RDCH of fifo_gen_inst : label is 0;
attribute C_HAS_DATA_COUNTS_WACH : integer;
attribute C_HAS_DATA_COUNTS_WACH of fifo_gen_inst : label is 0;
attribute C_HAS_DATA_COUNTS_WDCH : integer;
attribute C_HAS_DATA_COUNTS_WDCH of fifo_gen_inst : label is 0;
attribute C_HAS_DATA_COUNTS_WRCH : integer;
attribute C_HAS_DATA_COUNTS_WRCH of fifo_gen_inst : label is 0;
attribute C_HAS_INT_CLK : integer;
attribute C_HAS_INT_CLK of fifo_gen_inst : label is 0;
attribute C_HAS_MASTER_CE : integer;
attribute C_HAS_MASTER_CE of fifo_gen_inst : label is 0;
attribute C_HAS_MEMINIT_FILE : integer;
attribute C_HAS_MEMINIT_FILE of fifo_gen_inst : label is 0;
attribute C_HAS_OVERFLOW : integer;
attribute C_HAS_OVERFLOW of fifo_gen_inst : label is 0;
attribute C_HAS_PROG_FLAGS_AXIS : integer;
attribute C_HAS_PROG_FLAGS_AXIS of fifo_gen_inst : label is 0;
attribute C_HAS_PROG_FLAGS_RACH : integer;
attribute C_HAS_PROG_FLAGS_RACH of fifo_gen_inst : label is 0;
attribute C_HAS_PROG_FLAGS_RDCH : integer;
attribute C_HAS_PROG_FLAGS_RDCH of fifo_gen_inst : label is 0;
attribute C_HAS_PROG_FLAGS_WACH : integer;
attribute C_HAS_PROG_FLAGS_WACH of fifo_gen_inst : label is 0;
attribute C_HAS_PROG_FLAGS_WDCH : integer;
attribute C_HAS_PROG_FLAGS_WDCH of fifo_gen_inst : label is 0;
attribute C_HAS_PROG_FLAGS_WRCH : integer;
attribute C_HAS_PROG_FLAGS_WRCH of fifo_gen_inst : label is 0;
attribute C_HAS_RD_DATA_COUNT : integer;
attribute C_HAS_RD_DATA_COUNT of fifo_gen_inst : label is 0;
attribute C_HAS_RD_RST : integer;
attribute C_HAS_RD_RST of fifo_gen_inst : label is 0;
attribute C_HAS_RST : integer;
attribute C_HAS_RST of fifo_gen_inst : label is 1;
attribute C_HAS_SLAVE_CE : integer;
attribute C_HAS_SLAVE_CE of fifo_gen_inst : label is 0;
attribute C_HAS_SRST : integer;
attribute C_HAS_SRST of fifo_gen_inst : label is 0;
attribute C_HAS_UNDERFLOW : integer;
attribute C_HAS_UNDERFLOW of fifo_gen_inst : label is 0;
attribute C_HAS_VALID : integer;
attribute C_HAS_VALID of fifo_gen_inst : label is 0;
attribute C_HAS_WR_ACK : integer;
attribute C_HAS_WR_ACK of fifo_gen_inst : label is 0;
attribute C_HAS_WR_DATA_COUNT : integer;
attribute C_HAS_WR_DATA_COUNT of fifo_gen_inst : label is 0;
attribute C_HAS_WR_RST : integer;
attribute C_HAS_WR_RST of fifo_gen_inst : label is 0;
attribute C_IMPLEMENTATION_TYPE : integer;
attribute C_IMPLEMENTATION_TYPE of fifo_gen_inst : label is 0;
attribute C_IMPLEMENTATION_TYPE_AXIS : integer;
attribute C_IMPLEMENTATION_TYPE_AXIS of fifo_gen_inst : label is 1;
attribute C_IMPLEMENTATION_TYPE_RACH : integer;
attribute C_IMPLEMENTATION_TYPE_RACH of fifo_gen_inst : label is 1;
attribute C_IMPLEMENTATION_TYPE_RDCH : integer;
attribute C_IMPLEMENTATION_TYPE_RDCH of fifo_gen_inst : label is 1;
attribute C_IMPLEMENTATION_TYPE_WACH : integer;
attribute C_IMPLEMENTATION_TYPE_WACH of fifo_gen_inst : label is 1;
attribute C_IMPLEMENTATION_TYPE_WDCH : integer;
attribute C_IMPLEMENTATION_TYPE_WDCH of fifo_gen_inst : label is 1;
attribute C_IMPLEMENTATION_TYPE_WRCH : integer;
attribute C_IMPLEMENTATION_TYPE_WRCH of fifo_gen_inst : label is 1;
attribute C_INIT_WR_PNTR_VAL : integer;
attribute C_INIT_WR_PNTR_VAL of fifo_gen_inst : label is 0;
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of fifo_gen_inst : label is 0;
attribute C_MEMORY_TYPE : integer;
attribute C_MEMORY_TYPE of fifo_gen_inst : label is 2;
attribute C_MIF_FILE_NAME : string;
attribute C_MIF_FILE_NAME of fifo_gen_inst : label is "BlankString";
attribute C_MSGON_VAL : integer;
attribute C_MSGON_VAL of fifo_gen_inst : label is 1;
attribute C_OPTIMIZATION_MODE : integer;
attribute C_OPTIMIZATION_MODE of fifo_gen_inst : label is 0;
attribute C_OVERFLOW_LOW : integer;
attribute C_OVERFLOW_LOW of fifo_gen_inst : label is 0;
attribute C_POWER_SAVING_MODE : integer;
attribute C_POWER_SAVING_MODE of fifo_gen_inst : label is 0;
attribute C_PRELOAD_LATENCY : integer;
attribute C_PRELOAD_LATENCY of fifo_gen_inst : label is 0;
attribute C_PRELOAD_REGS : integer;
attribute C_PRELOAD_REGS of fifo_gen_inst : label is 1;
attribute C_PRIM_FIFO_TYPE : string;
attribute C_PRIM_FIFO_TYPE of fifo_gen_inst : label is "512x36";
attribute C_PRIM_FIFO_TYPE_AXIS : string;
attribute C_PRIM_FIFO_TYPE_AXIS of fifo_gen_inst : label is "512x36";
attribute C_PRIM_FIFO_TYPE_RACH : string;
attribute C_PRIM_FIFO_TYPE_RACH of fifo_gen_inst : label is "512x36";
attribute C_PRIM_FIFO_TYPE_RDCH : string;
attribute C_PRIM_FIFO_TYPE_RDCH of fifo_gen_inst : label is "512x36";
attribute C_PRIM_FIFO_TYPE_WACH : string;
attribute C_PRIM_FIFO_TYPE_WACH of fifo_gen_inst : label is "512x36";
attribute C_PRIM_FIFO_TYPE_WDCH : string;
attribute C_PRIM_FIFO_TYPE_WDCH of fifo_gen_inst : label is "512x36";
attribute C_PRIM_FIFO_TYPE_WRCH : string;
attribute C_PRIM_FIFO_TYPE_WRCH of fifo_gen_inst : label is "512x36";
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL of fifo_gen_inst : label is 4;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS of fifo_gen_inst : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH of fifo_gen_inst : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH of fifo_gen_inst : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH of fifo_gen_inst : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH of fifo_gen_inst : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH of fifo_gen_inst : label is 1022;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL : integer;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL of fifo_gen_inst : label is 5;
attribute C_PROG_EMPTY_TYPE : integer;
attribute C_PROG_EMPTY_TYPE of fifo_gen_inst : label is 0;
attribute C_PROG_EMPTY_TYPE_AXIS : integer;
attribute C_PROG_EMPTY_TYPE_AXIS of fifo_gen_inst : label is 0;
attribute C_PROG_EMPTY_TYPE_RACH : integer;
attribute C_PROG_EMPTY_TYPE_RACH of fifo_gen_inst : label is 0;
attribute C_PROG_EMPTY_TYPE_RDCH : integer;
attribute C_PROG_EMPTY_TYPE_RDCH of fifo_gen_inst : label is 0;
attribute C_PROG_EMPTY_TYPE_WACH : integer;
attribute C_PROG_EMPTY_TYPE_WACH of fifo_gen_inst : label is 0;
attribute C_PROG_EMPTY_TYPE_WDCH : integer;
attribute C_PROG_EMPTY_TYPE_WDCH of fifo_gen_inst : label is 0;
attribute C_PROG_EMPTY_TYPE_WRCH : integer;
attribute C_PROG_EMPTY_TYPE_WRCH of fifo_gen_inst : label is 0;
attribute C_PROG_FULL_THRESH_ASSERT_VAL : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL of fifo_gen_inst : label is 31;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS of fifo_gen_inst : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH of fifo_gen_inst : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH of fifo_gen_inst : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH of fifo_gen_inst : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH of fifo_gen_inst : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH of fifo_gen_inst : label is 1023;
attribute C_PROG_FULL_THRESH_NEGATE_VAL : integer;
attribute C_PROG_FULL_THRESH_NEGATE_VAL of fifo_gen_inst : label is 30;
attribute C_PROG_FULL_TYPE : integer;
attribute C_PROG_FULL_TYPE of fifo_gen_inst : label is 0;
attribute C_PROG_FULL_TYPE_AXIS : integer;
attribute C_PROG_FULL_TYPE_AXIS of fifo_gen_inst : label is 0;
attribute C_PROG_FULL_TYPE_RACH : integer;
attribute C_PROG_FULL_TYPE_RACH of fifo_gen_inst : label is 0;
attribute C_PROG_FULL_TYPE_RDCH : integer;
attribute C_PROG_FULL_TYPE_RDCH of fifo_gen_inst : label is 0;
attribute C_PROG_FULL_TYPE_WACH : integer;
attribute C_PROG_FULL_TYPE_WACH of fifo_gen_inst : label is 0;
attribute C_PROG_FULL_TYPE_WDCH : integer;
attribute C_PROG_FULL_TYPE_WDCH of fifo_gen_inst : label is 0;
attribute C_PROG_FULL_TYPE_WRCH : integer;
attribute C_PROG_FULL_TYPE_WRCH of fifo_gen_inst : label is 0;
attribute C_RACH_TYPE : integer;
attribute C_RACH_TYPE of fifo_gen_inst : label is 0;
attribute C_RDCH_TYPE : integer;
attribute C_RDCH_TYPE of fifo_gen_inst : label is 0;
attribute C_RD_DATA_COUNT_WIDTH : integer;
attribute C_RD_DATA_COUNT_WIDTH of fifo_gen_inst : label is 6;
attribute C_RD_DEPTH : integer;
attribute C_RD_DEPTH of fifo_gen_inst : label is 32;
attribute C_RD_FREQ : integer;
attribute C_RD_FREQ of fifo_gen_inst : label is 1;
attribute C_RD_PNTR_WIDTH : integer;
attribute C_RD_PNTR_WIDTH of fifo_gen_inst : label is 5;
attribute C_REG_SLICE_MODE_AXIS : integer;
attribute C_REG_SLICE_MODE_AXIS of fifo_gen_inst : label is 0;
attribute C_REG_SLICE_MODE_RACH : integer;
attribute C_REG_SLICE_MODE_RACH of fifo_gen_inst : label is 0;
attribute C_REG_SLICE_MODE_RDCH : integer;
attribute C_REG_SLICE_MODE_RDCH of fifo_gen_inst : label is 0;
attribute C_REG_SLICE_MODE_WACH : integer;
attribute C_REG_SLICE_MODE_WACH of fifo_gen_inst : label is 0;
attribute C_REG_SLICE_MODE_WDCH : integer;
attribute C_REG_SLICE_MODE_WDCH of fifo_gen_inst : label is 0;
attribute C_REG_SLICE_MODE_WRCH : integer;
attribute C_REG_SLICE_MODE_WRCH of fifo_gen_inst : label is 0;
attribute C_SELECT_XPM : integer;
attribute C_SELECT_XPM of fifo_gen_inst : label is 0;
attribute C_SYNCHRONIZER_STAGE : integer;
attribute C_SYNCHRONIZER_STAGE of fifo_gen_inst : label is 3;
attribute C_UNDERFLOW_LOW : integer;
attribute C_UNDERFLOW_LOW of fifo_gen_inst : label is 0;
attribute C_USE_COMMON_OVERFLOW : integer;
attribute C_USE_COMMON_OVERFLOW of fifo_gen_inst : label is 0;
attribute C_USE_COMMON_UNDERFLOW : integer;
attribute C_USE_COMMON_UNDERFLOW of fifo_gen_inst : label is 0;
attribute C_USE_DEFAULT_SETTINGS : integer;
attribute C_USE_DEFAULT_SETTINGS of fifo_gen_inst : label is 0;
attribute C_USE_DOUT_RST : integer;
attribute C_USE_DOUT_RST of fifo_gen_inst : label is 0;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of fifo_gen_inst : label is 0;
attribute C_USE_ECC_AXIS : integer;
attribute C_USE_ECC_AXIS of fifo_gen_inst : label is 0;
attribute C_USE_ECC_RACH : integer;
attribute C_USE_ECC_RACH of fifo_gen_inst : label is 0;
attribute C_USE_ECC_RDCH : integer;
attribute C_USE_ECC_RDCH of fifo_gen_inst : label is 0;
attribute C_USE_ECC_WACH : integer;
attribute C_USE_ECC_WACH of fifo_gen_inst : label is 0;
attribute C_USE_ECC_WDCH : integer;
attribute C_USE_ECC_WDCH of fifo_gen_inst : label is 0;
attribute C_USE_ECC_WRCH : integer;
attribute C_USE_ECC_WRCH of fifo_gen_inst : label is 0;
attribute C_USE_EMBEDDED_REG : integer;
attribute C_USE_EMBEDDED_REG of fifo_gen_inst : label is 0;
attribute C_USE_FIFO16_FLAGS : integer;
attribute C_USE_FIFO16_FLAGS of fifo_gen_inst : label is 0;
attribute C_USE_FWFT_DATA_COUNT : integer;
attribute C_USE_FWFT_DATA_COUNT of fifo_gen_inst : label is 1;
attribute C_USE_PIPELINE_REG : integer;
attribute C_USE_PIPELINE_REG of fifo_gen_inst : label is 0;
attribute C_VALID_LOW : integer;
attribute C_VALID_LOW of fifo_gen_inst : label is 0;
attribute C_WACH_TYPE : integer;
attribute C_WACH_TYPE of fifo_gen_inst : label is 0;
attribute C_WDCH_TYPE : integer;
attribute C_WDCH_TYPE of fifo_gen_inst : label is 0;
attribute C_WRCH_TYPE : integer;
attribute C_WRCH_TYPE of fifo_gen_inst : label is 0;
attribute C_WR_ACK_LOW : integer;
attribute C_WR_ACK_LOW of fifo_gen_inst : label is 0;
attribute C_WR_DATA_COUNT_WIDTH : integer;
attribute C_WR_DATA_COUNT_WIDTH of fifo_gen_inst : label is 6;
attribute C_WR_DEPTH : integer;
attribute C_WR_DEPTH of fifo_gen_inst : label is 32;
attribute C_WR_DEPTH_AXIS : integer;
attribute C_WR_DEPTH_AXIS of fifo_gen_inst : label is 1024;
attribute C_WR_DEPTH_RACH : integer;
attribute C_WR_DEPTH_RACH of fifo_gen_inst : label is 16;
attribute C_WR_DEPTH_RDCH : integer;
attribute C_WR_DEPTH_RDCH of fifo_gen_inst : label is 1024;
attribute C_WR_DEPTH_WACH : integer;
attribute C_WR_DEPTH_WACH of fifo_gen_inst : label is 16;
attribute C_WR_DEPTH_WDCH : integer;
attribute C_WR_DEPTH_WDCH of fifo_gen_inst : label is 1024;
attribute C_WR_DEPTH_WRCH : integer;
attribute C_WR_DEPTH_WRCH of fifo_gen_inst : label is 16;
attribute C_WR_FREQ : integer;
attribute C_WR_FREQ of fifo_gen_inst : label is 1;
attribute C_WR_PNTR_WIDTH : integer;
attribute C_WR_PNTR_WIDTH of fifo_gen_inst : label is 5;
attribute C_WR_PNTR_WIDTH_AXIS : integer;
attribute C_WR_PNTR_WIDTH_AXIS of fifo_gen_inst : label is 10;
attribute C_WR_PNTR_WIDTH_RACH : integer;
attribute C_WR_PNTR_WIDTH_RACH of fifo_gen_inst : label is 4;
attribute C_WR_PNTR_WIDTH_RDCH : integer;
attribute C_WR_PNTR_WIDTH_RDCH of fifo_gen_inst : label is 10;
attribute C_WR_PNTR_WIDTH_WACH : integer;
attribute C_WR_PNTR_WIDTH_WACH of fifo_gen_inst : label is 4;
attribute C_WR_PNTR_WIDTH_WDCH : integer;
attribute C_WR_PNTR_WIDTH_WDCH of fifo_gen_inst : label is 10;
attribute C_WR_PNTR_WIDTH_WRCH : integer;
attribute C_WR_PNTR_WIDTH_WRCH of fifo_gen_inst : label is 4;
attribute C_WR_RESPONSE_LATENCY : integer;
attribute C_WR_RESPONSE_LATENCY of fifo_gen_inst : label is 1;
attribute SOFT_HLUTNM of \fifo_gen_inst_i_1__1\ : label is "soft_lutpair37";
attribute SOFT_HLUTNM of fifo_gen_inst_i_2 : label is "soft_lutpair44";
attribute SOFT_HLUTNM of m_axi_awvalid_INST_0 : label is "soft_lutpair38";
attribute SOFT_HLUTNM of \queue_id[1]_i_1\ : label is "soft_lutpair45";
attribute SOFT_HLUTNM of \split_in_progress_i_1__0\ : label is "soft_lutpair38";
attribute SOFT_HLUTNM of split_ongoing_i_1 : label is "soft_lutpair45";
begin
din(0) <= \^din\(0);
\gpregsm1.user_valid_reg\ <= \^gpregsm1.user_valid_reg\;
\pushed_commands_reg[0]\ <= \^pushed_commands_reg[0]\;
\S_AXI_AREADY_I_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"444444F4FFFF44F4"
)
port map (
I0 => \areset_d_reg[0]\,
I1 => areset_d(0),
I2 => \^pushed_commands_reg[0]\,
I3 => S_AXI_AREADY_I_i_3_n_0,
I4 => S_AXI_AREADY_I_reg_0,
I5 => s_axi_awvalid,
O => S_AXI_AREADY_I_reg
);
S_AXI_AREADY_I_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"8AA8AAAAAAAA8AA8"
)
port map (
I0 => access_is_incr_q,
I1 => S_AXI_AREADY_I_i_4_n_0,
I2 => \num_transactions_q_reg[3]\(1),
I3 => \pushed_commands_reg[3]\(1),
I4 => \num_transactions_q_reg[3]\(3),
I5 => \pushed_commands_reg[3]\(3),
O => S_AXI_AREADY_I_i_3_n_0
);
S_AXI_AREADY_I_i_4: unisim.vcomponents.LUT4
generic map(
INIT => X"6FF6"
)
port map (
I0 => \num_transactions_q_reg[3]\(2),
I1 => \pushed_commands_reg[3]\(2),
I2 => \num_transactions_q_reg[3]\(0),
I3 => \pushed_commands_reg[3]\(0),
O => S_AXI_AREADY_I_i_4_n_0
);
\USE_B_CHANNEL.cmd_b_depth[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => cmd_b_empty0,
I1 => \USE_B_CHANNEL.cmd_b_depth_reg[5]_1\(0),
I2 => \USE_B_CHANNEL.cmd_b_depth_reg[5]_1\(1),
O => \USE_B_CHANNEL.cmd_b_depth_reg[5]_0\(0)
);
\USE_B_CHANNEL.cmd_b_depth[2]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AA9"
)
port map (
I0 => \USE_B_CHANNEL.cmd_b_depth_reg[5]_1\(2),
I1 => cmd_b_empty0,
I2 => \USE_B_CHANNEL.cmd_b_depth_reg[5]_1\(0),
I3 => \USE_B_CHANNEL.cmd_b_depth_reg[5]_1\(1),
O => \USE_B_CHANNEL.cmd_b_depth_reg[5]_0\(1)
);
\USE_B_CHANNEL.cmd_b_depth[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFE8001"
)
port map (
I0 => \USE_B_CHANNEL.cmd_b_depth_reg[5]_1\(1),
I1 => \USE_B_CHANNEL.cmd_b_depth_reg[5]_1\(0),
I2 => cmd_b_empty0,
I3 => \USE_B_CHANNEL.cmd_b_depth_reg[5]_1\(2),
I4 => \USE_B_CHANNEL.cmd_b_depth_reg[5]_1\(3),
O => \USE_B_CHANNEL.cmd_b_depth_reg[5]_0\(2)
);
\USE_B_CHANNEL.cmd_b_depth[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6AAAAAAAAAAAAAA9"
)
port map (
I0 => \USE_B_CHANNEL.cmd_b_depth_reg[5]_1\(4),
I1 => \USE_B_CHANNEL.cmd_b_depth_reg[5]_1\(3),
I2 => \USE_B_CHANNEL.cmd_b_depth_reg[5]_1\(2),
I3 => \USE_B_CHANNEL.cmd_b_depth_reg[5]_1\(1),
I4 => \USE_B_CHANNEL.cmd_b_depth_reg[5]_1\(0),
I5 => cmd_b_empty0,
O => \USE_B_CHANNEL.cmd_b_depth_reg[5]_0\(3)
);
\USE_B_CHANNEL.cmd_b_depth[4]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"01"
)
port map (
I0 => m_axi_awvalid_INST_0_i_1_n_0,
I1 => cmd_b_push_block,
I2 => wr_cmd_b_ready,
O => cmd_b_empty0
);
\USE_B_CHANNEL.cmd_b_depth[5]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E1"
)
port map (
I0 => cmd_b_push_block,
I1 => m_axi_awvalid_INST_0_i_1_n_0,
I2 => wr_cmd_b_ready,
O => \USE_B_CHANNEL.cmd_b_depth_reg[5]\(0)
);
\USE_B_CHANNEL.cmd_b_depth[5]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AA6AA9AAAAAAA9AA"
)
port map (
I0 => \USE_B_CHANNEL.cmd_b_depth_reg[5]_1\(5),
I1 => \USE_B_CHANNEL.cmd_b_depth_reg[5]_1\(3),
I2 => \USE_B_CHANNEL.cmd_b_depth_reg[5]_1\(2),
I3 => \USE_B_CHANNEL.cmd_b_depth[5]_i_3_n_0\,
I4 => \USE_B_CHANNEL.cmd_b_depth_reg[5]_1\(4),
I5 => \USE_B_CHANNEL.cmd_b_depth_reg[5]_1\(1),
O => \USE_B_CHANNEL.cmd_b_depth_reg[5]_0\(4)
);
\USE_B_CHANNEL.cmd_b_depth[5]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"ABABABABABABAB08"
)
port map (
I0 => \USE_B_CHANNEL.cmd_b_depth_reg[5]_1\(2),
I1 => \USE_B_CHANNEL.cmd_b_depth_reg[5]_1\(1),
I2 => \USE_B_CHANNEL.cmd_b_depth_reg[5]_1\(0),
I3 => m_axi_awvalid_INST_0_i_1_n_0,
I4 => cmd_b_push_block,
I5 => wr_cmd_b_ready,
O => \USE_B_CHANNEL.cmd_b_depth[5]_i_3_n_0\
);
\USE_B_CHANNEL.cmd_b_empty_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F1EEE000"
)
port map (
I0 => cmd_b_push_block,
I1 => m_axi_awvalid_INST_0_i_1_n_0,
I2 => almost_b_empty,
I3 => wr_cmd_b_ready,
I4 => cmd_b_empty,
O => \USE_B_CHANNEL.cmd_b_empty_reg\
);
cmd_b_push_block_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"00B0"
)
port map (
I0 => cmd_b_push_block,
I1 => m_axi_awvalid_INST_0_i_1_n_0,
I2 => aresetn,
I3 => S_AXI_AREADY_I_reg_0,
O => cmd_b_push_block_reg
);
\cmd_depth[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cmd_depth[4]_i_2_n_0\,
I1 => Q(0),
I2 => Q(1),
O => D(0)
);
\cmd_depth[2]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9AA6"
)
port map (
I0 => Q(2),
I1 => \cmd_depth[4]_i_2_n_0\,
I2 => Q(0),
I3 => Q(1),
O => D(1)
);
\cmd_depth[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F7EF0810"
)
port map (
I0 => Q(1),
I1 => Q(0),
I2 => \cmd_depth[4]_i_2_n_0\,
I3 => Q(2),
I4 => Q(3),
O => D(2)
);
\cmd_depth[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"9AAAAAAAAAAAAAA6"
)
port map (
I0 => Q(4),
I1 => \cmd_depth[4]_i_2_n_0\,
I2 => Q(0),
I3 => Q(1),
I4 => Q(2),
I5 => Q(3),
O => D(3)
);
\cmd_depth[4]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"FE"
)
port map (
I0 => wr_cmd_ready,
I1 => m_axi_awvalid_INST_0_i_1_n_0,
I2 => cmd_push_block,
O => \cmd_depth[4]_i_2_n_0\
);
\cmd_depth[5]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"E1"
)
port map (
I0 => cmd_push_block,
I1 => m_axi_awvalid_INST_0_i_1_n_0,
I2 => wr_cmd_ready,
O => E(0)
);
\cmd_depth[5]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAA65AAAAAA6"
)
port map (
I0 => Q(5),
I1 => \cmd_depth[5]_i_3_n_0\,
I2 => Q(3),
I3 => Q(2),
I4 => Q(4),
I5 => \cmd_depth[5]_i_4_n_0\,
O => D(4)
);
\cmd_depth[5]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FEFFFFFF000000FE"
)
port map (
I0 => cmd_push_block,
I1 => m_axi_awvalid_INST_0_i_1_n_0,
I2 => wr_cmd_ready,
I3 => Q(0),
I4 => Q(1),
I5 => Q(2),
O => \cmd_depth[5]_i_3_n_0\
);
\cmd_depth[5]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"FEFFFFFF"
)
port map (
I0 => cmd_push_block,
I1 => m_axi_awvalid_INST_0_i_1_n_0,
I2 => wr_cmd_ready,
I3 => Q(0),
I4 => Q(1),
O => \cmd_depth[5]_i_4_n_0\
);
cmd_empty_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"F1EEE000"
)
port map (
I0 => cmd_push_block,
I1 => m_axi_awvalid_INST_0_i_1_n_0,
I2 => almost_empty,
I3 => wr_cmd_ready,
I4 => cmd_empty,
O => cmd_empty_reg
);
\cmd_push_block_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"0000AB00"
)
port map (
I0 => cmd_push_block,
I1 => m_axi_awvalid_INST_0_i_1_n_0,
I2 => m_axi_awready,
I3 => aresetn,
I4 => \^pushed_commands_reg[0]\,
O => cmd_push_block_reg
);
command_ongoing_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFDDD0000F000"
)
port map (
I0 => \^pushed_commands_reg[0]\,
I1 => S_AXI_AREADY_I_i_3_n_0,
I2 => S_AXI_AREADY_I_reg_0,
I3 => s_axi_awvalid,
I4 => \areset_d_reg[1]\,
I5 => command_ongoing,
O => command_ongoing_reg
);
fifo_gen_inst: entity work.\system_auto_pc_1_fifo_generator_v13_1_3__parameterized0\
port map (
almost_empty => NLW_fifo_gen_inst_almost_empty_UNCONNECTED,
almost_full => NLW_fifo_gen_inst_almost_full_UNCONNECTED,
axi_ar_data_count(4 downto 0) => NLW_fifo_gen_inst_axi_ar_data_count_UNCONNECTED(4 downto 0),
axi_ar_dbiterr => NLW_fifo_gen_inst_axi_ar_dbiterr_UNCONNECTED,
axi_ar_injectdbiterr => '0',
axi_ar_injectsbiterr => '0',
axi_ar_overflow => NLW_fifo_gen_inst_axi_ar_overflow_UNCONNECTED,
axi_ar_prog_empty => NLW_fifo_gen_inst_axi_ar_prog_empty_UNCONNECTED,
axi_ar_prog_empty_thresh(3 downto 0) => B"0000",
axi_ar_prog_full => NLW_fifo_gen_inst_axi_ar_prog_full_UNCONNECTED,
axi_ar_prog_full_thresh(3 downto 0) => B"0000",
axi_ar_rd_data_count(4 downto 0) => NLW_fifo_gen_inst_axi_ar_rd_data_count_UNCONNECTED(4 downto 0),
axi_ar_sbiterr => NLW_fifo_gen_inst_axi_ar_sbiterr_UNCONNECTED,
axi_ar_underflow => NLW_fifo_gen_inst_axi_ar_underflow_UNCONNECTED,
axi_ar_wr_data_count(4 downto 0) => NLW_fifo_gen_inst_axi_ar_wr_data_count_UNCONNECTED(4 downto 0),
axi_aw_data_count(4 downto 0) => NLW_fifo_gen_inst_axi_aw_data_count_UNCONNECTED(4 downto 0),
axi_aw_dbiterr => NLW_fifo_gen_inst_axi_aw_dbiterr_UNCONNECTED,
axi_aw_injectdbiterr => '0',
axi_aw_injectsbiterr => '0',
axi_aw_overflow => NLW_fifo_gen_inst_axi_aw_overflow_UNCONNECTED,
axi_aw_prog_empty => NLW_fifo_gen_inst_axi_aw_prog_empty_UNCONNECTED,
axi_aw_prog_empty_thresh(3 downto 0) => B"0000",
axi_aw_prog_full => NLW_fifo_gen_inst_axi_aw_prog_full_UNCONNECTED,
axi_aw_prog_full_thresh(3 downto 0) => B"0000",
axi_aw_rd_data_count(4 downto 0) => NLW_fifo_gen_inst_axi_aw_rd_data_count_UNCONNECTED(4 downto 0),
axi_aw_sbiterr => NLW_fifo_gen_inst_axi_aw_sbiterr_UNCONNECTED,
axi_aw_underflow => NLW_fifo_gen_inst_axi_aw_underflow_UNCONNECTED,
axi_aw_wr_data_count(4 downto 0) => NLW_fifo_gen_inst_axi_aw_wr_data_count_UNCONNECTED(4 downto 0),
axi_b_data_count(4 downto 0) => NLW_fifo_gen_inst_axi_b_data_count_UNCONNECTED(4 downto 0),
axi_b_dbiterr => NLW_fifo_gen_inst_axi_b_dbiterr_UNCONNECTED,
axi_b_injectdbiterr => '0',
axi_b_injectsbiterr => '0',
axi_b_overflow => NLW_fifo_gen_inst_axi_b_overflow_UNCONNECTED,
axi_b_prog_empty => NLW_fifo_gen_inst_axi_b_prog_empty_UNCONNECTED,
axi_b_prog_empty_thresh(3 downto 0) => B"0000",
axi_b_prog_full => NLW_fifo_gen_inst_axi_b_prog_full_UNCONNECTED,
axi_b_prog_full_thresh(3 downto 0) => B"0000",
axi_b_rd_data_count(4 downto 0) => NLW_fifo_gen_inst_axi_b_rd_data_count_UNCONNECTED(4 downto 0),
axi_b_sbiterr => NLW_fifo_gen_inst_axi_b_sbiterr_UNCONNECTED,
axi_b_underflow => NLW_fifo_gen_inst_axi_b_underflow_UNCONNECTED,
axi_b_wr_data_count(4 downto 0) => NLW_fifo_gen_inst_axi_b_wr_data_count_UNCONNECTED(4 downto 0),
axi_r_data_count(10 downto 0) => NLW_fifo_gen_inst_axi_r_data_count_UNCONNECTED(10 downto 0),
axi_r_dbiterr => NLW_fifo_gen_inst_axi_r_dbiterr_UNCONNECTED,
axi_r_injectdbiterr => '0',
axi_r_injectsbiterr => '0',
axi_r_overflow => NLW_fifo_gen_inst_axi_r_overflow_UNCONNECTED,
axi_r_prog_empty => NLW_fifo_gen_inst_axi_r_prog_empty_UNCONNECTED,
axi_r_prog_empty_thresh(9 downto 0) => B"0000000000",
axi_r_prog_full => NLW_fifo_gen_inst_axi_r_prog_full_UNCONNECTED,
axi_r_prog_full_thresh(9 downto 0) => B"0000000000",
axi_r_rd_data_count(10 downto 0) => NLW_fifo_gen_inst_axi_r_rd_data_count_UNCONNECTED(10 downto 0),
axi_r_sbiterr => NLW_fifo_gen_inst_axi_r_sbiterr_UNCONNECTED,
axi_r_underflow => NLW_fifo_gen_inst_axi_r_underflow_UNCONNECTED,
axi_r_wr_data_count(10 downto 0) => NLW_fifo_gen_inst_axi_r_wr_data_count_UNCONNECTED(10 downto 0),
axi_w_data_count(10 downto 0) => NLW_fifo_gen_inst_axi_w_data_count_UNCONNECTED(10 downto 0),
axi_w_dbiterr => NLW_fifo_gen_inst_axi_w_dbiterr_UNCONNECTED,
axi_w_injectdbiterr => '0',
axi_w_injectsbiterr => '0',
axi_w_overflow => NLW_fifo_gen_inst_axi_w_overflow_UNCONNECTED,
axi_w_prog_empty => NLW_fifo_gen_inst_axi_w_prog_empty_UNCONNECTED,
axi_w_prog_empty_thresh(9 downto 0) => B"0000000000",
axi_w_prog_full => NLW_fifo_gen_inst_axi_w_prog_full_UNCONNECTED,
axi_w_prog_full_thresh(9 downto 0) => B"0000000000",
axi_w_rd_data_count(10 downto 0) => NLW_fifo_gen_inst_axi_w_rd_data_count_UNCONNECTED(10 downto 0),
axi_w_sbiterr => NLW_fifo_gen_inst_axi_w_sbiterr_UNCONNECTED,
axi_w_underflow => NLW_fifo_gen_inst_axi_w_underflow_UNCONNECTED,
axi_w_wr_data_count(10 downto 0) => NLW_fifo_gen_inst_axi_w_wr_data_count_UNCONNECTED(10 downto 0),
axis_data_count(10 downto 0) => NLW_fifo_gen_inst_axis_data_count_UNCONNECTED(10 downto 0),
axis_dbiterr => NLW_fifo_gen_inst_axis_dbiterr_UNCONNECTED,
axis_injectdbiterr => '0',
axis_injectsbiterr => '0',
axis_overflow => NLW_fifo_gen_inst_axis_overflow_UNCONNECTED,
axis_prog_empty => NLW_fifo_gen_inst_axis_prog_empty_UNCONNECTED,
axis_prog_empty_thresh(9 downto 0) => B"0000000000",
axis_prog_full => NLW_fifo_gen_inst_axis_prog_full_UNCONNECTED,
axis_prog_full_thresh(9 downto 0) => B"0000000000",
axis_rd_data_count(10 downto 0) => NLW_fifo_gen_inst_axis_rd_data_count_UNCONNECTED(10 downto 0),
axis_sbiterr => NLW_fifo_gen_inst_axis_sbiterr_UNCONNECTED,
axis_underflow => NLW_fifo_gen_inst_axis_underflow_UNCONNECTED,
axis_wr_data_count(10 downto 0) => NLW_fifo_gen_inst_axis_wr_data_count_UNCONNECTED(10 downto 0),
backup => '0',
backup_marker => '0',
clk => aclk,
data_count(5 downto 0) => NLW_fifo_gen_inst_data_count_UNCONNECTED(5 downto 0),
dbiterr => NLW_fifo_gen_inst_dbiterr_UNCONNECTED,
din(4) => \^din\(0),
din(3 downto 0) => \num_transactions_q_reg[3]\(3 downto 0),
dout(4 downto 0) => first_mi_word_reg(4 downto 0),
empty => \^gpregsm1.user_valid_reg\,
full => full_0,
injectdbiterr => '0',
injectsbiterr => '0',
int_clk => '0',
m_aclk => '0',
m_aclk_en => '0',
m_axi_araddr(31 downto 0) => NLW_fifo_gen_inst_m_axi_araddr_UNCONNECTED(31 downto 0),
m_axi_arburst(1 downto 0) => NLW_fifo_gen_inst_m_axi_arburst_UNCONNECTED(1 downto 0),
m_axi_arcache(3 downto 0) => NLW_fifo_gen_inst_m_axi_arcache_UNCONNECTED(3 downto 0),
m_axi_arid(3 downto 0) => NLW_fifo_gen_inst_m_axi_arid_UNCONNECTED(3 downto 0),
m_axi_arlen(7 downto 0) => NLW_fifo_gen_inst_m_axi_arlen_UNCONNECTED(7 downto 0),
m_axi_arlock(1 downto 0) => NLW_fifo_gen_inst_m_axi_arlock_UNCONNECTED(1 downto 0),
m_axi_arprot(2 downto 0) => NLW_fifo_gen_inst_m_axi_arprot_UNCONNECTED(2 downto 0),
m_axi_arqos(3 downto 0) => NLW_fifo_gen_inst_m_axi_arqos_UNCONNECTED(3 downto 0),
m_axi_arready => '0',
m_axi_arregion(3 downto 0) => NLW_fifo_gen_inst_m_axi_arregion_UNCONNECTED(3 downto 0),
m_axi_arsize(2 downto 0) => NLW_fifo_gen_inst_m_axi_arsize_UNCONNECTED(2 downto 0),
m_axi_aruser(0) => NLW_fifo_gen_inst_m_axi_aruser_UNCONNECTED(0),
m_axi_arvalid => NLW_fifo_gen_inst_m_axi_arvalid_UNCONNECTED,
m_axi_awaddr(31 downto 0) => NLW_fifo_gen_inst_m_axi_awaddr_UNCONNECTED(31 downto 0),
m_axi_awburst(1 downto 0) => NLW_fifo_gen_inst_m_axi_awburst_UNCONNECTED(1 downto 0),
m_axi_awcache(3 downto 0) => NLW_fifo_gen_inst_m_axi_awcache_UNCONNECTED(3 downto 0),
m_axi_awid(3 downto 0) => NLW_fifo_gen_inst_m_axi_awid_UNCONNECTED(3 downto 0),
m_axi_awlen(7 downto 0) => NLW_fifo_gen_inst_m_axi_awlen_UNCONNECTED(7 downto 0),
m_axi_awlock(1 downto 0) => NLW_fifo_gen_inst_m_axi_awlock_UNCONNECTED(1 downto 0),
m_axi_awprot(2 downto 0) => NLW_fifo_gen_inst_m_axi_awprot_UNCONNECTED(2 downto 0),
m_axi_awqos(3 downto 0) => NLW_fifo_gen_inst_m_axi_awqos_UNCONNECTED(3 downto 0),
m_axi_awready => '0',
m_axi_awregion(3 downto 0) => NLW_fifo_gen_inst_m_axi_awregion_UNCONNECTED(3 downto 0),
m_axi_awsize(2 downto 0) => NLW_fifo_gen_inst_m_axi_awsize_UNCONNECTED(2 downto 0),
m_axi_awuser(0) => NLW_fifo_gen_inst_m_axi_awuser_UNCONNECTED(0),
m_axi_awvalid => NLW_fifo_gen_inst_m_axi_awvalid_UNCONNECTED,
m_axi_bid(3 downto 0) => B"0000",
m_axi_bready => NLW_fifo_gen_inst_m_axi_bready_UNCONNECTED,
m_axi_bresp(1 downto 0) => B"00",
m_axi_buser(0) => '0',
m_axi_bvalid => '0',
m_axi_rdata(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
m_axi_rid(3 downto 0) => B"0000",
m_axi_rlast => '0',
m_axi_rready => NLW_fifo_gen_inst_m_axi_rready_UNCONNECTED,
m_axi_rresp(1 downto 0) => B"00",
m_axi_ruser(0) => '0',
m_axi_rvalid => '0',
m_axi_wdata(63 downto 0) => NLW_fifo_gen_inst_m_axi_wdata_UNCONNECTED(63 downto 0),
m_axi_wid(3 downto 0) => NLW_fifo_gen_inst_m_axi_wid_UNCONNECTED(3 downto 0),
m_axi_wlast => NLW_fifo_gen_inst_m_axi_wlast_UNCONNECTED,
m_axi_wready => '0',
m_axi_wstrb(7 downto 0) => NLW_fifo_gen_inst_m_axi_wstrb_UNCONNECTED(7 downto 0),
m_axi_wuser(0) => NLW_fifo_gen_inst_m_axi_wuser_UNCONNECTED(0),
m_axi_wvalid => NLW_fifo_gen_inst_m_axi_wvalid_UNCONNECTED,
m_axis_tdata(63 downto 0) => NLW_fifo_gen_inst_m_axis_tdata_UNCONNECTED(63 downto 0),
m_axis_tdest(3 downto 0) => NLW_fifo_gen_inst_m_axis_tdest_UNCONNECTED(3 downto 0),
m_axis_tid(7 downto 0) => NLW_fifo_gen_inst_m_axis_tid_UNCONNECTED(7 downto 0),
m_axis_tkeep(3 downto 0) => NLW_fifo_gen_inst_m_axis_tkeep_UNCONNECTED(3 downto 0),
m_axis_tlast => NLW_fifo_gen_inst_m_axis_tlast_UNCONNECTED,
m_axis_tready => '0',
m_axis_tstrb(3 downto 0) => NLW_fifo_gen_inst_m_axis_tstrb_UNCONNECTED(3 downto 0),
m_axis_tuser(3 downto 0) => NLW_fifo_gen_inst_m_axis_tuser_UNCONNECTED(3 downto 0),
m_axis_tvalid => NLW_fifo_gen_inst_m_axis_tvalid_UNCONNECTED,
overflow => NLW_fifo_gen_inst_overflow_UNCONNECTED,
prog_empty => NLW_fifo_gen_inst_prog_empty_UNCONNECTED,
prog_empty_thresh(4 downto 0) => B"00000",
prog_empty_thresh_assert(4 downto 0) => B"00000",
prog_empty_thresh_negate(4 downto 0) => B"00000",
prog_full => NLW_fifo_gen_inst_prog_full_UNCONNECTED,
prog_full_thresh(4 downto 0) => B"00000",
prog_full_thresh_assert(4 downto 0) => B"00000",
prog_full_thresh_negate(4 downto 0) => B"00000",
rd_clk => '0',
rd_data_count(5 downto 0) => NLW_fifo_gen_inst_rd_data_count_UNCONNECTED(5 downto 0),
rd_en => wr_cmd_b_ready,
rd_rst => '0',
rd_rst_busy => NLW_fifo_gen_inst_rd_rst_busy_UNCONNECTED,
rst => SR(0),
s_aclk => '0',
s_aclk_en => '0',
s_aresetn => '0',
s_axi_araddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_arburst(1 downto 0) => B"00",
s_axi_arcache(3 downto 0) => B"0000",
s_axi_arid(3 downto 0) => B"0000",
s_axi_arlen(7 downto 0) => B"00000000",
s_axi_arlock(1 downto 0) => B"00",
s_axi_arprot(2 downto 0) => B"000",
s_axi_arqos(3 downto 0) => B"0000",
s_axi_arready => NLW_fifo_gen_inst_s_axi_arready_UNCONNECTED,
s_axi_arregion(3 downto 0) => B"0000",
s_axi_arsize(2 downto 0) => B"000",
s_axi_aruser(0) => '0',
s_axi_arvalid => '0',
s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_awburst(1 downto 0) => B"00",
s_axi_awcache(3 downto 0) => B"0000",
s_axi_awid(3 downto 0) => B"0000",
s_axi_awlen(7 downto 0) => B"00000000",
s_axi_awlock(1 downto 0) => B"00",
s_axi_awprot(2 downto 0) => B"000",
s_axi_awqos(3 downto 0) => B"0000",
s_axi_awready => NLW_fifo_gen_inst_s_axi_awready_UNCONNECTED,
s_axi_awregion(3 downto 0) => B"0000",
s_axi_awsize(2 downto 0) => B"000",
s_axi_awuser(0) => '0',
s_axi_awvalid => '0',
s_axi_bid(3 downto 0) => NLW_fifo_gen_inst_s_axi_bid_UNCONNECTED(3 downto 0),
s_axi_bready => '0',
s_axi_bresp(1 downto 0) => NLW_fifo_gen_inst_s_axi_bresp_UNCONNECTED(1 downto 0),
s_axi_buser(0) => NLW_fifo_gen_inst_s_axi_buser_UNCONNECTED(0),
s_axi_bvalid => NLW_fifo_gen_inst_s_axi_bvalid_UNCONNECTED,
s_axi_rdata(63 downto 0) => NLW_fifo_gen_inst_s_axi_rdata_UNCONNECTED(63 downto 0),
s_axi_rid(3 downto 0) => NLW_fifo_gen_inst_s_axi_rid_UNCONNECTED(3 downto 0),
s_axi_rlast => NLW_fifo_gen_inst_s_axi_rlast_UNCONNECTED,
s_axi_rready => '0',
s_axi_rresp(1 downto 0) => NLW_fifo_gen_inst_s_axi_rresp_UNCONNECTED(1 downto 0),
s_axi_ruser(0) => NLW_fifo_gen_inst_s_axi_ruser_UNCONNECTED(0),
s_axi_rvalid => NLW_fifo_gen_inst_s_axi_rvalid_UNCONNECTED,
s_axi_wdata(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
s_axi_wid(3 downto 0) => B"0000",
s_axi_wlast => '0',
s_axi_wready => NLW_fifo_gen_inst_s_axi_wready_UNCONNECTED,
s_axi_wstrb(7 downto 0) => B"00000000",
s_axi_wuser(0) => '0',
s_axi_wvalid => '0',
s_axis_tdata(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
s_axis_tdest(3 downto 0) => B"0000",
s_axis_tid(7 downto 0) => B"00000000",
s_axis_tkeep(3 downto 0) => B"0000",
s_axis_tlast => '0',
s_axis_tready => NLW_fifo_gen_inst_s_axis_tready_UNCONNECTED,
s_axis_tstrb(3 downto 0) => B"0000",
s_axis_tuser(3 downto 0) => B"0000",
s_axis_tvalid => '0',
sbiterr => NLW_fifo_gen_inst_sbiterr_UNCONNECTED,
sleep => '0',
srst => '0',
underflow => NLW_fifo_gen_inst_underflow_UNCONNECTED,
valid => NLW_fifo_gen_inst_valid_UNCONNECTED,
wr_ack => NLW_fifo_gen_inst_wr_ack_UNCONNECTED,
wr_clk => '0',
wr_data_count(5 downto 0) => NLW_fifo_gen_inst_wr_data_count_UNCONNECTED(5 downto 0),
wr_en => cmd_b_push,
wr_rst => '0',
wr_rst_busy => NLW_fifo_gen_inst_wr_rst_busy_UNCONNECTED
);
fifo_gen_inst_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => S_AXI_AREADY_I_i_3_n_0,
I1 => need_to_split_q,
O => \^din\(0)
);
\fifo_gen_inst_i_1__1\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => cmd_push_block,
I1 => m_axi_awvalid_INST_0_i_1_n_0,
O => wr_en
);
fifo_gen_inst_i_2: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => cmd_b_push_block,
I1 => m_axi_awvalid_INST_0_i_1_n_0,
O => cmd_b_push
);
m_axi_awvalid_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => m_axi_awvalid_INST_0_i_1_n_0,
O => m_axi_awvalid
);
m_axi_awvalid_INST_0_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"5554554455544444"
)
port map (
I0 => cmd_push_block_reg_0,
I1 => m_axi_awvalid_INST_0_i_3_n_0,
I2 => split_in_progress_reg_0,
I3 => need_to_split_q,
I4 => cmd_empty_reg_0,
I5 => multiple_id_non_split,
O => m_axi_awvalid_INST_0_i_1_n_0
);
m_axi_awvalid_INST_0_i_3: unisim.vcomponents.LUT3
generic map(
INIT => X"FD"
)
port map (
I0 => command_ongoing,
I1 => full_0,
I2 => full,
O => m_axi_awvalid_INST_0_i_3_n_0
);
\multiple_id_non_split_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000F0F1F0F0"
)
port map (
I0 => cmd_push_block,
I1 => m_axi_awvalid_INST_0_i_1_n_0,
I2 => multiple_id_non_split,
I3 => \S_AXI_AID_Q_reg[0]\,
I4 => incr_need_to_split_q_reg,
I5 => \multiple_id_non_split_i_4__0_n_0\,
O => multiple_id_non_split_reg
);
\multiple_id_non_split_i_4__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"F800FFFF"
)
port map (
I0 => almost_empty,
I1 => wr_cmd_ready,
I2 => cmd_empty,
I3 => multiple_id_non_split_i_5_n_0,
I4 => aresetn,
O => \multiple_id_non_split_i_4__0_n_0\
);
multiple_id_non_split_i_5: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAAAEAAAAAA"
)
port map (
I0 => cmd_b_empty,
I1 => almost_b_empty,
I2 => \goreg_dm.dout_i_reg[4]\,
I3 => m_axi_bvalid,
I4 => s_axi_bready,
I5 => \^gpregsm1.user_valid_reg\,
O => multiple_id_non_split_i_5_n_0
);
\queue_id[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FE10"
)
port map (
I0 => cmd_push_block,
I1 => m_axi_awvalid_INST_0_i_1_n_0,
I2 => \S_AXI_AID_Q_reg[1]\(0),
I3 => queue_id(0),
O => \queue_id_reg[0]\
);
\queue_id[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FE10"
)
port map (
I0 => cmd_push_block,
I1 => m_axi_awvalid_INST_0_i_1_n_0,
I2 => \S_AXI_AID_Q_reg[1]\(1),
I3 => queue_id(1),
O => \queue_id_reg[1]\
);
\split_in_progress_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"0000F1F0"
)
port map (
I0 => cmd_push_block,
I1 => m_axi_awvalid_INST_0_i_1_n_0,
I2 => split_in_progress_reg_0,
I3 => need_to_split_q,
I4 => \multiple_id_non_split_i_4__0_n_0\,
O => split_in_progress_reg
);
split_ongoing_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => m_axi_awready,
I1 => m_axi_awvalid_INST_0_i_1_n_0,
O => \^pushed_commands_reg[0]\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_auto_pc_1_axi_data_fifo_v2_1_10_fifo_gen__parameterized1\ is
port (
din : out STD_LOGIC_VECTOR ( 0 to 0 );
wr_en : out STD_LOGIC;
rd_en : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 4 downto 0 );
m_axi_arvalid : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\pushed_commands_reg[0]\ : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rlast : out STD_LOGIC;
m_axi_rready : out STD_LOGIC;
S_AXI_AREADY_I_reg : out STD_LOGIC;
cmd_push_block_reg : out STD_LOGIC;
command_ongoing_reg : out STD_LOGIC;
split_in_progress_reg : out STD_LOGIC;
multiple_id_non_split_reg : out STD_LOGIC;
aclk : in STD_LOGIC;
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 5 downto 0 );
need_to_split_q : in STD_LOGIC;
m_axi_rlast : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC;
command_ongoing : in STD_LOGIC;
cmd_push_block : in STD_LOGIC;
m_axi_arready : in STD_LOGIC;
multiple_id_non_split : in STD_LOGIC;
\S_AXI_AID_Q_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\queue_id_reg[0]\ : in STD_LOGIC;
\queue_id_reg[1]\ : in STD_LOGIC;
cmd_empty : in STD_LOGIC;
split_in_progress_reg_0 : in STD_LOGIC;
almost_empty : in STD_LOGIC;
aresetn : in STD_LOGIC;
access_is_incr_q : in STD_LOGIC;
\num_transactions_q_reg[3]\ : in STD_LOGIC;
\pushed_commands_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\num_transactions_q_reg[0]\ : in STD_LOGIC;
\num_transactions_q_reg[1]\ : in STD_LOGIC;
\num_transactions_q_reg[2]\ : in STD_LOGIC;
areset_d : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_AREADY_I_reg_0 : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
\areset_d_reg[1]\ : in STD_LOGIC;
split_in_progress_reg_1 : in STD_LOGIC;
\S_AXI_AID_Q_reg[0]\ : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_auto_pc_1_axi_data_fifo_v2_1_10_fifo_gen__parameterized1\ : entity is "axi_data_fifo_v2_1_10_fifo_gen";
end \system_auto_pc_1_axi_data_fifo_v2_1_10_fifo_gen__parameterized1\;
architecture STRUCTURE of \system_auto_pc_1_axi_data_fifo_v2_1_10_fifo_gen__parameterized1\ is
signal S_AXI_AREADY_I_i_2_n_0 : STD_LOGIC;
signal \S_AXI_AREADY_I_i_3__0_n_0\ : STD_LOGIC;
signal \cmd_depth[4]_i_2__0_n_0\ : STD_LOGIC;
signal \cmd_depth[5]_i_3__0_n_0\ : STD_LOGIC;
signal \cmd_depth[5]_i_4__0_n_0\ : STD_LOGIC;
signal \^din\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal empty : STD_LOGIC;
signal full : STD_LOGIC;
signal m_axi_arvalid_INST_0_i_1_n_0 : STD_LOGIC;
signal m_axi_arvalid_INST_0_i_2_n_0 : STD_LOGIC;
signal m_axi_arvalid_INST_0_i_3_n_0 : STD_LOGIC;
signal \^pushed_commands_reg[0]\ : STD_LOGIC;
signal rd_cmd_split : STD_LOGIC;
signal \^rd_en\ : STD_LOGIC;
signal split_in_progress : STD_LOGIC;
signal \^wr_en\ : STD_LOGIC;
signal NLW_fifo_gen_inst_almost_empty_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_almost_full_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axi_ar_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axi_ar_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axi_ar_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axi_ar_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axi_ar_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axi_ar_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axi_aw_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axi_aw_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axi_aw_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axi_aw_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axi_aw_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axi_aw_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axi_b_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axi_b_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axi_b_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axi_b_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axi_b_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axi_b_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axi_r_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axi_r_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axi_r_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axi_r_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axi_r_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axi_r_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axi_w_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axi_w_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axi_w_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axi_w_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axi_w_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axi_w_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axis_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axis_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axis_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axis_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axis_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axis_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_m_axi_arvalid_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_m_axi_awvalid_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_m_axi_bready_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_m_axi_rready_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_m_axi_wlast_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_m_axi_wvalid_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_m_axis_tlast_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_m_axis_tvalid_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_rd_rst_busy_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_s_axi_arready_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_s_axi_awready_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_s_axi_rlast_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_s_axi_wready_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_s_axis_tready_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_valid_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_wr_ack_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_wr_rst_busy_UNCONNECTED : STD_LOGIC;
signal NLW_fifo_gen_inst_axi_ar_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_fifo_gen_inst_axi_ar_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_fifo_gen_inst_axi_ar_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_fifo_gen_inst_axi_aw_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_fifo_gen_inst_axi_aw_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_fifo_gen_inst_axi_aw_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_fifo_gen_inst_axi_b_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_fifo_gen_inst_axi_b_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_fifo_gen_inst_axi_b_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_fifo_gen_inst_axi_r_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_fifo_gen_inst_axi_r_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_fifo_gen_inst_axi_r_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_fifo_gen_inst_axi_w_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_fifo_gen_inst_axi_w_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_fifo_gen_inst_axi_w_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_fifo_gen_inst_axis_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_fifo_gen_inst_axis_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_fifo_gen_inst_axis_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_fifo_gen_inst_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_fifo_gen_inst_m_axi_araddr_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_fifo_gen_inst_m_axi_arburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_fifo_gen_inst_m_axi_arcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_fifo_gen_inst_m_axi_arid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_fifo_gen_inst_m_axi_arlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_fifo_gen_inst_m_axi_arlock_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_fifo_gen_inst_m_axi_arprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_fifo_gen_inst_m_axi_arqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_fifo_gen_inst_m_axi_arregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_fifo_gen_inst_m_axi_arsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_fifo_gen_inst_m_axi_aruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_fifo_gen_inst_m_axi_awaddr_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_fifo_gen_inst_m_axi_awburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_fifo_gen_inst_m_axi_awcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_fifo_gen_inst_m_axi_awid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_fifo_gen_inst_m_axi_awlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_fifo_gen_inst_m_axi_awlock_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_fifo_gen_inst_m_axi_awprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_fifo_gen_inst_m_axi_awqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_fifo_gen_inst_m_axi_awregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_fifo_gen_inst_m_axi_awsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_fifo_gen_inst_m_axi_awuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_fifo_gen_inst_m_axi_wdata_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_fifo_gen_inst_m_axi_wid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_fifo_gen_inst_m_axi_wstrb_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_fifo_gen_inst_m_axi_wuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_fifo_gen_inst_m_axis_tdata_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_fifo_gen_inst_m_axis_tdest_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_fifo_gen_inst_m_axis_tid_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_fifo_gen_inst_m_axis_tkeep_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_fifo_gen_inst_m_axis_tstrb_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_fifo_gen_inst_m_axis_tuser_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_fifo_gen_inst_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_fifo_gen_inst_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_fifo_gen_inst_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_fifo_gen_inst_s_axi_buser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_fifo_gen_inst_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_fifo_gen_inst_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_fifo_gen_inst_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_fifo_gen_inst_s_axi_ruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_fifo_gen_inst_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \cmd_depth[2]_i_1__0\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \cmd_depth[3]_i_1__0\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \cmd_depth[4]_i_2__0\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \cmd_depth[5]_i_1\ : label is "soft_lutpair4";
attribute C_ADD_NGC_CONSTRAINT : integer;
attribute C_ADD_NGC_CONSTRAINT of fifo_gen_inst : label is 0;
attribute C_APPLICATION_TYPE_AXIS : integer;
attribute C_APPLICATION_TYPE_AXIS of fifo_gen_inst : label is 0;
attribute C_APPLICATION_TYPE_RACH : integer;
attribute C_APPLICATION_TYPE_RACH of fifo_gen_inst : label is 0;
attribute C_APPLICATION_TYPE_RDCH : integer;
attribute C_APPLICATION_TYPE_RDCH of fifo_gen_inst : label is 0;
attribute C_APPLICATION_TYPE_WACH : integer;
attribute C_APPLICATION_TYPE_WACH of fifo_gen_inst : label is 0;
attribute C_APPLICATION_TYPE_WDCH : integer;
attribute C_APPLICATION_TYPE_WDCH of fifo_gen_inst : label is 0;
attribute C_APPLICATION_TYPE_WRCH : integer;
attribute C_APPLICATION_TYPE_WRCH of fifo_gen_inst : label is 0;
attribute C_AXIS_TDATA_WIDTH : integer;
attribute C_AXIS_TDATA_WIDTH of fifo_gen_inst : label is 64;
attribute C_AXIS_TDEST_WIDTH : integer;
attribute C_AXIS_TDEST_WIDTH of fifo_gen_inst : label is 4;
attribute C_AXIS_TID_WIDTH : integer;
attribute C_AXIS_TID_WIDTH of fifo_gen_inst : label is 8;
attribute C_AXIS_TKEEP_WIDTH : integer;
attribute C_AXIS_TKEEP_WIDTH of fifo_gen_inst : label is 4;
attribute C_AXIS_TSTRB_WIDTH : integer;
attribute C_AXIS_TSTRB_WIDTH of fifo_gen_inst : label is 4;
attribute C_AXIS_TUSER_WIDTH : integer;
attribute C_AXIS_TUSER_WIDTH of fifo_gen_inst : label is 4;
attribute C_AXIS_TYPE : integer;
attribute C_AXIS_TYPE of fifo_gen_inst : label is 0;
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of fifo_gen_inst : label is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of fifo_gen_inst : label is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of fifo_gen_inst : label is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of fifo_gen_inst : label is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of fifo_gen_inst : label is 64;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of fifo_gen_inst : label is 4;
attribute C_AXI_LEN_WIDTH : integer;
attribute C_AXI_LEN_WIDTH of fifo_gen_inst : label is 8;
attribute C_AXI_LOCK_WIDTH : integer;
attribute C_AXI_LOCK_WIDTH of fifo_gen_inst : label is 2;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of fifo_gen_inst : label is 1;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of fifo_gen_inst : label is 0;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of fifo_gen_inst : label is 1;
attribute C_COMMON_CLOCK : integer;
attribute C_COMMON_CLOCK of fifo_gen_inst : label is 1;
attribute C_COUNT_TYPE : integer;
attribute C_COUNT_TYPE of fifo_gen_inst : label is 0;
attribute C_DATA_COUNT_WIDTH : integer;
attribute C_DATA_COUNT_WIDTH of fifo_gen_inst : label is 6;
attribute C_DEFAULT_VALUE : string;
attribute C_DEFAULT_VALUE of fifo_gen_inst : label is "BlankString";
attribute C_DIN_WIDTH : integer;
attribute C_DIN_WIDTH of fifo_gen_inst : label is 1;
attribute C_DIN_WIDTH_AXIS : integer;
attribute C_DIN_WIDTH_AXIS of fifo_gen_inst : label is 1;
attribute C_DIN_WIDTH_RACH : integer;
attribute C_DIN_WIDTH_RACH of fifo_gen_inst : label is 32;
attribute C_DIN_WIDTH_RDCH : integer;
attribute C_DIN_WIDTH_RDCH of fifo_gen_inst : label is 64;
attribute C_DIN_WIDTH_WACH : integer;
attribute C_DIN_WIDTH_WACH of fifo_gen_inst : label is 32;
attribute C_DIN_WIDTH_WDCH : integer;
attribute C_DIN_WIDTH_WDCH of fifo_gen_inst : label is 64;
attribute C_DIN_WIDTH_WRCH : integer;
attribute C_DIN_WIDTH_WRCH of fifo_gen_inst : label is 2;
attribute C_DOUT_RST_VAL : string;
attribute C_DOUT_RST_VAL of fifo_gen_inst : label is "0";
attribute C_DOUT_WIDTH : integer;
attribute C_DOUT_WIDTH of fifo_gen_inst : label is 1;
attribute C_ENABLE_RLOCS : integer;
attribute C_ENABLE_RLOCS of fifo_gen_inst : label is 0;
attribute C_ENABLE_RST_SYNC : integer;
attribute C_ENABLE_RST_SYNC of fifo_gen_inst : label is 1;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of fifo_gen_inst : label is 0;
attribute C_ERROR_INJECTION_TYPE : integer;
attribute C_ERROR_INJECTION_TYPE of fifo_gen_inst : label is 0;
attribute C_ERROR_INJECTION_TYPE_AXIS : integer;
attribute C_ERROR_INJECTION_TYPE_AXIS of fifo_gen_inst : label is 0;
attribute C_ERROR_INJECTION_TYPE_RACH : integer;
attribute C_ERROR_INJECTION_TYPE_RACH of fifo_gen_inst : label is 0;
attribute C_ERROR_INJECTION_TYPE_RDCH : integer;
attribute C_ERROR_INJECTION_TYPE_RDCH of fifo_gen_inst : label is 0;
attribute C_ERROR_INJECTION_TYPE_WACH : integer;
attribute C_ERROR_INJECTION_TYPE_WACH of fifo_gen_inst : label is 0;
attribute C_ERROR_INJECTION_TYPE_WDCH : integer;
attribute C_ERROR_INJECTION_TYPE_WDCH of fifo_gen_inst : label is 0;
attribute C_ERROR_INJECTION_TYPE_WRCH : integer;
attribute C_ERROR_INJECTION_TYPE_WRCH of fifo_gen_inst : label is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of fifo_gen_inst : label is "zynq";
attribute C_FULL_FLAGS_RST_VAL : integer;
attribute C_FULL_FLAGS_RST_VAL of fifo_gen_inst : label is 0;
attribute C_HAS_ALMOST_EMPTY : integer;
attribute C_HAS_ALMOST_EMPTY of fifo_gen_inst : label is 0;
attribute C_HAS_ALMOST_FULL : integer;
attribute C_HAS_ALMOST_FULL of fifo_gen_inst : label is 0;
attribute C_HAS_AXIS_TDATA : integer;
attribute C_HAS_AXIS_TDATA of fifo_gen_inst : label is 0;
attribute C_HAS_AXIS_TDEST : integer;
attribute C_HAS_AXIS_TDEST of fifo_gen_inst : label is 0;
attribute C_HAS_AXIS_TID : integer;
attribute C_HAS_AXIS_TID of fifo_gen_inst : label is 0;
attribute C_HAS_AXIS_TKEEP : integer;
attribute C_HAS_AXIS_TKEEP of fifo_gen_inst : label is 0;
attribute C_HAS_AXIS_TLAST : integer;
attribute C_HAS_AXIS_TLAST of fifo_gen_inst : label is 0;
attribute C_HAS_AXIS_TREADY : integer;
attribute C_HAS_AXIS_TREADY of fifo_gen_inst : label is 1;
attribute C_HAS_AXIS_TSTRB : integer;
attribute C_HAS_AXIS_TSTRB of fifo_gen_inst : label is 0;
attribute C_HAS_AXIS_TUSER : integer;
attribute C_HAS_AXIS_TUSER of fifo_gen_inst : label is 0;
attribute C_HAS_AXI_ARUSER : integer;
attribute C_HAS_AXI_ARUSER of fifo_gen_inst : label is 0;
attribute C_HAS_AXI_AWUSER : integer;
attribute C_HAS_AXI_AWUSER of fifo_gen_inst : label is 0;
attribute C_HAS_AXI_BUSER : integer;
attribute C_HAS_AXI_BUSER of fifo_gen_inst : label is 0;
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of fifo_gen_inst : label is 0;
attribute C_HAS_AXI_RD_CHANNEL : integer;
attribute C_HAS_AXI_RD_CHANNEL of fifo_gen_inst : label is 0;
attribute C_HAS_AXI_RUSER : integer;
attribute C_HAS_AXI_RUSER of fifo_gen_inst : label is 0;
attribute C_HAS_AXI_WR_CHANNEL : integer;
attribute C_HAS_AXI_WR_CHANNEL of fifo_gen_inst : label is 0;
attribute C_HAS_AXI_WUSER : integer;
attribute C_HAS_AXI_WUSER of fifo_gen_inst : label is 0;
attribute C_HAS_BACKUP : integer;
attribute C_HAS_BACKUP of fifo_gen_inst : label is 0;
attribute C_HAS_DATA_COUNT : integer;
attribute C_HAS_DATA_COUNT of fifo_gen_inst : label is 0;
attribute C_HAS_DATA_COUNTS_AXIS : integer;
attribute C_HAS_DATA_COUNTS_AXIS of fifo_gen_inst : label is 0;
attribute C_HAS_DATA_COUNTS_RACH : integer;
attribute C_HAS_DATA_COUNTS_RACH of fifo_gen_inst : label is 0;
attribute C_HAS_DATA_COUNTS_RDCH : integer;
attribute C_HAS_DATA_COUNTS_RDCH of fifo_gen_inst : label is 0;
attribute C_HAS_DATA_COUNTS_WACH : integer;
attribute C_HAS_DATA_COUNTS_WACH of fifo_gen_inst : label is 0;
attribute C_HAS_DATA_COUNTS_WDCH : integer;
attribute C_HAS_DATA_COUNTS_WDCH of fifo_gen_inst : label is 0;
attribute C_HAS_DATA_COUNTS_WRCH : integer;
attribute C_HAS_DATA_COUNTS_WRCH of fifo_gen_inst : label is 0;
attribute C_HAS_INT_CLK : integer;
attribute C_HAS_INT_CLK of fifo_gen_inst : label is 0;
attribute C_HAS_MASTER_CE : integer;
attribute C_HAS_MASTER_CE of fifo_gen_inst : label is 0;
attribute C_HAS_MEMINIT_FILE : integer;
attribute C_HAS_MEMINIT_FILE of fifo_gen_inst : label is 0;
attribute C_HAS_OVERFLOW : integer;
attribute C_HAS_OVERFLOW of fifo_gen_inst : label is 0;
attribute C_HAS_PROG_FLAGS_AXIS : integer;
attribute C_HAS_PROG_FLAGS_AXIS of fifo_gen_inst : label is 0;
attribute C_HAS_PROG_FLAGS_RACH : integer;
attribute C_HAS_PROG_FLAGS_RACH of fifo_gen_inst : label is 0;
attribute C_HAS_PROG_FLAGS_RDCH : integer;
attribute C_HAS_PROG_FLAGS_RDCH of fifo_gen_inst : label is 0;
attribute C_HAS_PROG_FLAGS_WACH : integer;
attribute C_HAS_PROG_FLAGS_WACH of fifo_gen_inst : label is 0;
attribute C_HAS_PROG_FLAGS_WDCH : integer;
attribute C_HAS_PROG_FLAGS_WDCH of fifo_gen_inst : label is 0;
attribute C_HAS_PROG_FLAGS_WRCH : integer;
attribute C_HAS_PROG_FLAGS_WRCH of fifo_gen_inst : label is 0;
attribute C_HAS_RD_DATA_COUNT : integer;
attribute C_HAS_RD_DATA_COUNT of fifo_gen_inst : label is 0;
attribute C_HAS_RD_RST : integer;
attribute C_HAS_RD_RST of fifo_gen_inst : label is 0;
attribute C_HAS_RST : integer;
attribute C_HAS_RST of fifo_gen_inst : label is 1;
attribute C_HAS_SLAVE_CE : integer;
attribute C_HAS_SLAVE_CE of fifo_gen_inst : label is 0;
attribute C_HAS_SRST : integer;
attribute C_HAS_SRST of fifo_gen_inst : label is 0;
attribute C_HAS_UNDERFLOW : integer;
attribute C_HAS_UNDERFLOW of fifo_gen_inst : label is 0;
attribute C_HAS_VALID : integer;
attribute C_HAS_VALID of fifo_gen_inst : label is 0;
attribute C_HAS_WR_ACK : integer;
attribute C_HAS_WR_ACK of fifo_gen_inst : label is 0;
attribute C_HAS_WR_DATA_COUNT : integer;
attribute C_HAS_WR_DATA_COUNT of fifo_gen_inst : label is 0;
attribute C_HAS_WR_RST : integer;
attribute C_HAS_WR_RST of fifo_gen_inst : label is 0;
attribute C_IMPLEMENTATION_TYPE : integer;
attribute C_IMPLEMENTATION_TYPE of fifo_gen_inst : label is 0;
attribute C_IMPLEMENTATION_TYPE_AXIS : integer;
attribute C_IMPLEMENTATION_TYPE_AXIS of fifo_gen_inst : label is 1;
attribute C_IMPLEMENTATION_TYPE_RACH : integer;
attribute C_IMPLEMENTATION_TYPE_RACH of fifo_gen_inst : label is 1;
attribute C_IMPLEMENTATION_TYPE_RDCH : integer;
attribute C_IMPLEMENTATION_TYPE_RDCH of fifo_gen_inst : label is 1;
attribute C_IMPLEMENTATION_TYPE_WACH : integer;
attribute C_IMPLEMENTATION_TYPE_WACH of fifo_gen_inst : label is 1;
attribute C_IMPLEMENTATION_TYPE_WDCH : integer;
attribute C_IMPLEMENTATION_TYPE_WDCH of fifo_gen_inst : label is 1;
attribute C_IMPLEMENTATION_TYPE_WRCH : integer;
attribute C_IMPLEMENTATION_TYPE_WRCH of fifo_gen_inst : label is 1;
attribute C_INIT_WR_PNTR_VAL : integer;
attribute C_INIT_WR_PNTR_VAL of fifo_gen_inst : label is 0;
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of fifo_gen_inst : label is 0;
attribute C_MEMORY_TYPE : integer;
attribute C_MEMORY_TYPE of fifo_gen_inst : label is 2;
attribute C_MIF_FILE_NAME : string;
attribute C_MIF_FILE_NAME of fifo_gen_inst : label is "BlankString";
attribute C_MSGON_VAL : integer;
attribute C_MSGON_VAL of fifo_gen_inst : label is 1;
attribute C_OPTIMIZATION_MODE : integer;
attribute C_OPTIMIZATION_MODE of fifo_gen_inst : label is 0;
attribute C_OVERFLOW_LOW : integer;
attribute C_OVERFLOW_LOW of fifo_gen_inst : label is 0;
attribute C_POWER_SAVING_MODE : integer;
attribute C_POWER_SAVING_MODE of fifo_gen_inst : label is 0;
attribute C_PRELOAD_LATENCY : integer;
attribute C_PRELOAD_LATENCY of fifo_gen_inst : label is 0;
attribute C_PRELOAD_REGS : integer;
attribute C_PRELOAD_REGS of fifo_gen_inst : label is 1;
attribute C_PRIM_FIFO_TYPE : string;
attribute C_PRIM_FIFO_TYPE of fifo_gen_inst : label is "512x36";
attribute C_PRIM_FIFO_TYPE_AXIS : string;
attribute C_PRIM_FIFO_TYPE_AXIS of fifo_gen_inst : label is "512x36";
attribute C_PRIM_FIFO_TYPE_RACH : string;
attribute C_PRIM_FIFO_TYPE_RACH of fifo_gen_inst : label is "512x36";
attribute C_PRIM_FIFO_TYPE_RDCH : string;
attribute C_PRIM_FIFO_TYPE_RDCH of fifo_gen_inst : label is "512x36";
attribute C_PRIM_FIFO_TYPE_WACH : string;
attribute C_PRIM_FIFO_TYPE_WACH of fifo_gen_inst : label is "512x36";
attribute C_PRIM_FIFO_TYPE_WDCH : string;
attribute C_PRIM_FIFO_TYPE_WDCH of fifo_gen_inst : label is "512x36";
attribute C_PRIM_FIFO_TYPE_WRCH : string;
attribute C_PRIM_FIFO_TYPE_WRCH of fifo_gen_inst : label is "512x36";
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL of fifo_gen_inst : label is 4;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS of fifo_gen_inst : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH of fifo_gen_inst : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH of fifo_gen_inst : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH of fifo_gen_inst : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH of fifo_gen_inst : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH of fifo_gen_inst : label is 1022;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL : integer;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL of fifo_gen_inst : label is 5;
attribute C_PROG_EMPTY_TYPE : integer;
attribute C_PROG_EMPTY_TYPE of fifo_gen_inst : label is 0;
attribute C_PROG_EMPTY_TYPE_AXIS : integer;
attribute C_PROG_EMPTY_TYPE_AXIS of fifo_gen_inst : label is 0;
attribute C_PROG_EMPTY_TYPE_RACH : integer;
attribute C_PROG_EMPTY_TYPE_RACH of fifo_gen_inst : label is 0;
attribute C_PROG_EMPTY_TYPE_RDCH : integer;
attribute C_PROG_EMPTY_TYPE_RDCH of fifo_gen_inst : label is 0;
attribute C_PROG_EMPTY_TYPE_WACH : integer;
attribute C_PROG_EMPTY_TYPE_WACH of fifo_gen_inst : label is 0;
attribute C_PROG_EMPTY_TYPE_WDCH : integer;
attribute C_PROG_EMPTY_TYPE_WDCH of fifo_gen_inst : label is 0;
attribute C_PROG_EMPTY_TYPE_WRCH : integer;
attribute C_PROG_EMPTY_TYPE_WRCH of fifo_gen_inst : label is 0;
attribute C_PROG_FULL_THRESH_ASSERT_VAL : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL of fifo_gen_inst : label is 31;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS of fifo_gen_inst : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH of fifo_gen_inst : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH of fifo_gen_inst : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH of fifo_gen_inst : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH of fifo_gen_inst : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH of fifo_gen_inst : label is 1023;
attribute C_PROG_FULL_THRESH_NEGATE_VAL : integer;
attribute C_PROG_FULL_THRESH_NEGATE_VAL of fifo_gen_inst : label is 30;
attribute C_PROG_FULL_TYPE : integer;
attribute C_PROG_FULL_TYPE of fifo_gen_inst : label is 0;
attribute C_PROG_FULL_TYPE_AXIS : integer;
attribute C_PROG_FULL_TYPE_AXIS of fifo_gen_inst : label is 0;
attribute C_PROG_FULL_TYPE_RACH : integer;
attribute C_PROG_FULL_TYPE_RACH of fifo_gen_inst : label is 0;
attribute C_PROG_FULL_TYPE_RDCH : integer;
attribute C_PROG_FULL_TYPE_RDCH of fifo_gen_inst : label is 0;
attribute C_PROG_FULL_TYPE_WACH : integer;
attribute C_PROG_FULL_TYPE_WACH of fifo_gen_inst : label is 0;
attribute C_PROG_FULL_TYPE_WDCH : integer;
attribute C_PROG_FULL_TYPE_WDCH of fifo_gen_inst : label is 0;
attribute C_PROG_FULL_TYPE_WRCH : integer;
attribute C_PROG_FULL_TYPE_WRCH of fifo_gen_inst : label is 0;
attribute C_RACH_TYPE : integer;
attribute C_RACH_TYPE of fifo_gen_inst : label is 0;
attribute C_RDCH_TYPE : integer;
attribute C_RDCH_TYPE of fifo_gen_inst : label is 0;
attribute C_RD_DATA_COUNT_WIDTH : integer;
attribute C_RD_DATA_COUNT_WIDTH of fifo_gen_inst : label is 6;
attribute C_RD_DEPTH : integer;
attribute C_RD_DEPTH of fifo_gen_inst : label is 32;
attribute C_RD_FREQ : integer;
attribute C_RD_FREQ of fifo_gen_inst : label is 1;
attribute C_RD_PNTR_WIDTH : integer;
attribute C_RD_PNTR_WIDTH of fifo_gen_inst : label is 5;
attribute C_REG_SLICE_MODE_AXIS : integer;
attribute C_REG_SLICE_MODE_AXIS of fifo_gen_inst : label is 0;
attribute C_REG_SLICE_MODE_RACH : integer;
attribute C_REG_SLICE_MODE_RACH of fifo_gen_inst : label is 0;
attribute C_REG_SLICE_MODE_RDCH : integer;
attribute C_REG_SLICE_MODE_RDCH of fifo_gen_inst : label is 0;
attribute C_REG_SLICE_MODE_WACH : integer;
attribute C_REG_SLICE_MODE_WACH of fifo_gen_inst : label is 0;
attribute C_REG_SLICE_MODE_WDCH : integer;
attribute C_REG_SLICE_MODE_WDCH of fifo_gen_inst : label is 0;
attribute C_REG_SLICE_MODE_WRCH : integer;
attribute C_REG_SLICE_MODE_WRCH of fifo_gen_inst : label is 0;
attribute C_SELECT_XPM : integer;
attribute C_SELECT_XPM of fifo_gen_inst : label is 0;
attribute C_SYNCHRONIZER_STAGE : integer;
attribute C_SYNCHRONIZER_STAGE of fifo_gen_inst : label is 3;
attribute C_UNDERFLOW_LOW : integer;
attribute C_UNDERFLOW_LOW of fifo_gen_inst : label is 0;
attribute C_USE_COMMON_OVERFLOW : integer;
attribute C_USE_COMMON_OVERFLOW of fifo_gen_inst : label is 0;
attribute C_USE_COMMON_UNDERFLOW : integer;
attribute C_USE_COMMON_UNDERFLOW of fifo_gen_inst : label is 0;
attribute C_USE_DEFAULT_SETTINGS : integer;
attribute C_USE_DEFAULT_SETTINGS of fifo_gen_inst : label is 0;
attribute C_USE_DOUT_RST : integer;
attribute C_USE_DOUT_RST of fifo_gen_inst : label is 0;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of fifo_gen_inst : label is 0;
attribute C_USE_ECC_AXIS : integer;
attribute C_USE_ECC_AXIS of fifo_gen_inst : label is 0;
attribute C_USE_ECC_RACH : integer;
attribute C_USE_ECC_RACH of fifo_gen_inst : label is 0;
attribute C_USE_ECC_RDCH : integer;
attribute C_USE_ECC_RDCH of fifo_gen_inst : label is 0;
attribute C_USE_ECC_WACH : integer;
attribute C_USE_ECC_WACH of fifo_gen_inst : label is 0;
attribute C_USE_ECC_WDCH : integer;
attribute C_USE_ECC_WDCH of fifo_gen_inst : label is 0;
attribute C_USE_ECC_WRCH : integer;
attribute C_USE_ECC_WRCH of fifo_gen_inst : label is 0;
attribute C_USE_EMBEDDED_REG : integer;
attribute C_USE_EMBEDDED_REG of fifo_gen_inst : label is 0;
attribute C_USE_FIFO16_FLAGS : integer;
attribute C_USE_FIFO16_FLAGS of fifo_gen_inst : label is 0;
attribute C_USE_FWFT_DATA_COUNT : integer;
attribute C_USE_FWFT_DATA_COUNT of fifo_gen_inst : label is 1;
attribute C_USE_PIPELINE_REG : integer;
attribute C_USE_PIPELINE_REG of fifo_gen_inst : label is 0;
attribute C_VALID_LOW : integer;
attribute C_VALID_LOW of fifo_gen_inst : label is 0;
attribute C_WACH_TYPE : integer;
attribute C_WACH_TYPE of fifo_gen_inst : label is 0;
attribute C_WDCH_TYPE : integer;
attribute C_WDCH_TYPE of fifo_gen_inst : label is 0;
attribute C_WRCH_TYPE : integer;
attribute C_WRCH_TYPE of fifo_gen_inst : label is 0;
attribute C_WR_ACK_LOW : integer;
attribute C_WR_ACK_LOW of fifo_gen_inst : label is 0;
attribute C_WR_DATA_COUNT_WIDTH : integer;
attribute C_WR_DATA_COUNT_WIDTH of fifo_gen_inst : label is 6;
attribute C_WR_DEPTH : integer;
attribute C_WR_DEPTH of fifo_gen_inst : label is 32;
attribute C_WR_DEPTH_AXIS : integer;
attribute C_WR_DEPTH_AXIS of fifo_gen_inst : label is 1024;
attribute C_WR_DEPTH_RACH : integer;
attribute C_WR_DEPTH_RACH of fifo_gen_inst : label is 16;
attribute C_WR_DEPTH_RDCH : integer;
attribute C_WR_DEPTH_RDCH of fifo_gen_inst : label is 1024;
attribute C_WR_DEPTH_WACH : integer;
attribute C_WR_DEPTH_WACH of fifo_gen_inst : label is 16;
attribute C_WR_DEPTH_WDCH : integer;
attribute C_WR_DEPTH_WDCH of fifo_gen_inst : label is 1024;
attribute C_WR_DEPTH_WRCH : integer;
attribute C_WR_DEPTH_WRCH of fifo_gen_inst : label is 16;
attribute C_WR_FREQ : integer;
attribute C_WR_FREQ of fifo_gen_inst : label is 1;
attribute C_WR_PNTR_WIDTH : integer;
attribute C_WR_PNTR_WIDTH of fifo_gen_inst : label is 5;
attribute C_WR_PNTR_WIDTH_AXIS : integer;
attribute C_WR_PNTR_WIDTH_AXIS of fifo_gen_inst : label is 10;
attribute C_WR_PNTR_WIDTH_RACH : integer;
attribute C_WR_PNTR_WIDTH_RACH of fifo_gen_inst : label is 4;
attribute C_WR_PNTR_WIDTH_RDCH : integer;
attribute C_WR_PNTR_WIDTH_RDCH of fifo_gen_inst : label is 10;
attribute C_WR_PNTR_WIDTH_WACH : integer;
attribute C_WR_PNTR_WIDTH_WACH of fifo_gen_inst : label is 4;
attribute C_WR_PNTR_WIDTH_WDCH : integer;
attribute C_WR_PNTR_WIDTH_WDCH of fifo_gen_inst : label is 10;
attribute C_WR_PNTR_WIDTH_WRCH : integer;
attribute C_WR_PNTR_WIDTH_WRCH of fifo_gen_inst : label is 4;
attribute C_WR_RESPONSE_LATENCY : integer;
attribute C_WR_RESPONSE_LATENCY of fifo_gen_inst : label is 1;
attribute SOFT_HLUTNM of \fifo_gen_inst_i_3__1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of m_axi_arvalid_INST_0 : label is "soft_lutpair7";
attribute SOFT_HLUTNM of m_axi_rready_INST_0 : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \split_ongoing_i_1__0\ : label is "soft_lutpair7";
begin
din(0) <= \^din\(0);
\pushed_commands_reg[0]\ <= \^pushed_commands_reg[0]\;
rd_en <= \^rd_en\;
wr_en <= \^wr_en\;
\S_AXI_AREADY_I_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"444444F4FFFF44F4"
)
port map (
I0 => areset_d(0),
I1 => areset_d(1),
I2 => \^pushed_commands_reg[0]\,
I3 => S_AXI_AREADY_I_i_2_n_0,
I4 => S_AXI_AREADY_I_reg_0,
I5 => s_axi_arvalid,
O => S_AXI_AREADY_I_reg
);
S_AXI_AREADY_I_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"8AA8AAAAAAAA8AA8"
)
port map (
I0 => access_is_incr_q,
I1 => \S_AXI_AREADY_I_i_3__0_n_0\,
I2 => \num_transactions_q_reg[3]\,
I3 => \pushed_commands_reg[3]\(3),
I4 => \num_transactions_q_reg[0]\,
I5 => \pushed_commands_reg[3]\(0),
O => S_AXI_AREADY_I_i_2_n_0
);
\S_AXI_AREADY_I_i_3__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"6FF6"
)
port map (
I0 => \num_transactions_q_reg[1]\,
I1 => \pushed_commands_reg[3]\(1),
I2 => \num_transactions_q_reg[2]\,
I3 => \pushed_commands_reg[3]\(2),
O => \S_AXI_AREADY_I_i_3__0_n_0\
);
\cmd_depth[1]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cmd_depth[4]_i_2__0_n_0\,
I1 => Q(0),
I2 => Q(1),
O => D(0)
);
\cmd_depth[2]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9AA6"
)
port map (
I0 => Q(2),
I1 => \cmd_depth[4]_i_2__0_n_0\,
I2 => Q(0),
I3 => Q(1),
O => D(1)
);
\cmd_depth[3]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"F7EF0810"
)
port map (
I0 => Q(1),
I1 => Q(0),
I2 => \cmd_depth[4]_i_2__0_n_0\,
I3 => Q(2),
I4 => Q(3),
O => D(2)
);
\cmd_depth[4]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9AAAAAAAAAAAAAA6"
)
port map (
I0 => Q(4),
I1 => \cmd_depth[4]_i_2__0_n_0\,
I2 => Q(0),
I3 => Q(1),
I4 => Q(2),
I5 => Q(3),
O => D(3)
);
\cmd_depth[4]_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"0080FFFF"
)
port map (
I0 => m_axi_rlast,
I1 => s_axi_rready,
I2 => m_axi_rvalid,
I3 => empty,
I4 => \^wr_en\,
O => \cmd_depth[4]_i_2__0_n_0\
);
\cmd_depth[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF7F0080"
)
port map (
I0 => m_axi_rlast,
I1 => s_axi_rready,
I2 => m_axi_rvalid,
I3 => empty,
I4 => \^wr_en\,
O => E(0)
);
\cmd_depth[5]_i_2__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"56A6"
)
port map (
I0 => Q(5),
I1 => \cmd_depth[5]_i_3__0_n_0\,
I2 => Q(4),
I3 => \cmd_depth[5]_i_4__0_n_0\,
O => D(4)
);
\cmd_depth[5]_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0001000000010001"
)
port map (
I0 => Q(3),
I1 => Q(2),
I2 => Q(1),
I3 => Q(0),
I4 => \^rd_en\,
I5 => \^wr_en\,
O => \cmd_depth[5]_i_3__0_n_0\
);
\cmd_depth[5]_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0800000000000000"
)
port map (
I0 => Q(1),
I1 => Q(0),
I2 => \^rd_en\,
I3 => \^wr_en\,
I4 => Q(2),
I5 => Q(3),
O => \cmd_depth[5]_i_4__0_n_0\
);
cmd_push_block_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"0000AE00"
)
port map (
I0 => cmd_push_block,
I1 => \^wr_en\,
I2 => m_axi_arready,
I3 => aresetn,
I4 => \^pushed_commands_reg[0]\,
O => cmd_push_block_reg
);
\command_ongoing_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFDDD0000F000"
)
port map (
I0 => \^pushed_commands_reg[0]\,
I1 => S_AXI_AREADY_I_i_2_n_0,
I2 => S_AXI_AREADY_I_reg_0,
I3 => s_axi_arvalid,
I4 => \areset_d_reg[1]\,
I5 => command_ongoing,
O => command_ongoing_reg
);
fifo_gen_inst: entity work.\system_auto_pc_1_fifo_generator_v13_1_3__parameterized1\
port map (
almost_empty => NLW_fifo_gen_inst_almost_empty_UNCONNECTED,
almost_full => NLW_fifo_gen_inst_almost_full_UNCONNECTED,
axi_ar_data_count(4 downto 0) => NLW_fifo_gen_inst_axi_ar_data_count_UNCONNECTED(4 downto 0),
axi_ar_dbiterr => NLW_fifo_gen_inst_axi_ar_dbiterr_UNCONNECTED,
axi_ar_injectdbiterr => '0',
axi_ar_injectsbiterr => '0',
axi_ar_overflow => NLW_fifo_gen_inst_axi_ar_overflow_UNCONNECTED,
axi_ar_prog_empty => NLW_fifo_gen_inst_axi_ar_prog_empty_UNCONNECTED,
axi_ar_prog_empty_thresh(3 downto 0) => B"0000",
axi_ar_prog_full => NLW_fifo_gen_inst_axi_ar_prog_full_UNCONNECTED,
axi_ar_prog_full_thresh(3 downto 0) => B"0000",
axi_ar_rd_data_count(4 downto 0) => NLW_fifo_gen_inst_axi_ar_rd_data_count_UNCONNECTED(4 downto 0),
axi_ar_sbiterr => NLW_fifo_gen_inst_axi_ar_sbiterr_UNCONNECTED,
axi_ar_underflow => NLW_fifo_gen_inst_axi_ar_underflow_UNCONNECTED,
axi_ar_wr_data_count(4 downto 0) => NLW_fifo_gen_inst_axi_ar_wr_data_count_UNCONNECTED(4 downto 0),
axi_aw_data_count(4 downto 0) => NLW_fifo_gen_inst_axi_aw_data_count_UNCONNECTED(4 downto 0),
axi_aw_dbiterr => NLW_fifo_gen_inst_axi_aw_dbiterr_UNCONNECTED,
axi_aw_injectdbiterr => '0',
axi_aw_injectsbiterr => '0',
axi_aw_overflow => NLW_fifo_gen_inst_axi_aw_overflow_UNCONNECTED,
axi_aw_prog_empty => NLW_fifo_gen_inst_axi_aw_prog_empty_UNCONNECTED,
axi_aw_prog_empty_thresh(3 downto 0) => B"0000",
axi_aw_prog_full => NLW_fifo_gen_inst_axi_aw_prog_full_UNCONNECTED,
axi_aw_prog_full_thresh(3 downto 0) => B"0000",
axi_aw_rd_data_count(4 downto 0) => NLW_fifo_gen_inst_axi_aw_rd_data_count_UNCONNECTED(4 downto 0),
axi_aw_sbiterr => NLW_fifo_gen_inst_axi_aw_sbiterr_UNCONNECTED,
axi_aw_underflow => NLW_fifo_gen_inst_axi_aw_underflow_UNCONNECTED,
axi_aw_wr_data_count(4 downto 0) => NLW_fifo_gen_inst_axi_aw_wr_data_count_UNCONNECTED(4 downto 0),
axi_b_data_count(4 downto 0) => NLW_fifo_gen_inst_axi_b_data_count_UNCONNECTED(4 downto 0),
axi_b_dbiterr => NLW_fifo_gen_inst_axi_b_dbiterr_UNCONNECTED,
axi_b_injectdbiterr => '0',
axi_b_injectsbiterr => '0',
axi_b_overflow => NLW_fifo_gen_inst_axi_b_overflow_UNCONNECTED,
axi_b_prog_empty => NLW_fifo_gen_inst_axi_b_prog_empty_UNCONNECTED,
axi_b_prog_empty_thresh(3 downto 0) => B"0000",
axi_b_prog_full => NLW_fifo_gen_inst_axi_b_prog_full_UNCONNECTED,
axi_b_prog_full_thresh(3 downto 0) => B"0000",
axi_b_rd_data_count(4 downto 0) => NLW_fifo_gen_inst_axi_b_rd_data_count_UNCONNECTED(4 downto 0),
axi_b_sbiterr => NLW_fifo_gen_inst_axi_b_sbiterr_UNCONNECTED,
axi_b_underflow => NLW_fifo_gen_inst_axi_b_underflow_UNCONNECTED,
axi_b_wr_data_count(4 downto 0) => NLW_fifo_gen_inst_axi_b_wr_data_count_UNCONNECTED(4 downto 0),
axi_r_data_count(10 downto 0) => NLW_fifo_gen_inst_axi_r_data_count_UNCONNECTED(10 downto 0),
axi_r_dbiterr => NLW_fifo_gen_inst_axi_r_dbiterr_UNCONNECTED,
axi_r_injectdbiterr => '0',
axi_r_injectsbiterr => '0',
axi_r_overflow => NLW_fifo_gen_inst_axi_r_overflow_UNCONNECTED,
axi_r_prog_empty => NLW_fifo_gen_inst_axi_r_prog_empty_UNCONNECTED,
axi_r_prog_empty_thresh(9 downto 0) => B"0000000000",
axi_r_prog_full => NLW_fifo_gen_inst_axi_r_prog_full_UNCONNECTED,
axi_r_prog_full_thresh(9 downto 0) => B"0000000000",
axi_r_rd_data_count(10 downto 0) => NLW_fifo_gen_inst_axi_r_rd_data_count_UNCONNECTED(10 downto 0),
axi_r_sbiterr => NLW_fifo_gen_inst_axi_r_sbiterr_UNCONNECTED,
axi_r_underflow => NLW_fifo_gen_inst_axi_r_underflow_UNCONNECTED,
axi_r_wr_data_count(10 downto 0) => NLW_fifo_gen_inst_axi_r_wr_data_count_UNCONNECTED(10 downto 0),
axi_w_data_count(10 downto 0) => NLW_fifo_gen_inst_axi_w_data_count_UNCONNECTED(10 downto 0),
axi_w_dbiterr => NLW_fifo_gen_inst_axi_w_dbiterr_UNCONNECTED,
axi_w_injectdbiterr => '0',
axi_w_injectsbiterr => '0',
axi_w_overflow => NLW_fifo_gen_inst_axi_w_overflow_UNCONNECTED,
axi_w_prog_empty => NLW_fifo_gen_inst_axi_w_prog_empty_UNCONNECTED,
axi_w_prog_empty_thresh(9 downto 0) => B"0000000000",
axi_w_prog_full => NLW_fifo_gen_inst_axi_w_prog_full_UNCONNECTED,
axi_w_prog_full_thresh(9 downto 0) => B"0000000000",
axi_w_rd_data_count(10 downto 0) => NLW_fifo_gen_inst_axi_w_rd_data_count_UNCONNECTED(10 downto 0),
axi_w_sbiterr => NLW_fifo_gen_inst_axi_w_sbiterr_UNCONNECTED,
axi_w_underflow => NLW_fifo_gen_inst_axi_w_underflow_UNCONNECTED,
axi_w_wr_data_count(10 downto 0) => NLW_fifo_gen_inst_axi_w_wr_data_count_UNCONNECTED(10 downto 0),
axis_data_count(10 downto 0) => NLW_fifo_gen_inst_axis_data_count_UNCONNECTED(10 downto 0),
axis_dbiterr => NLW_fifo_gen_inst_axis_dbiterr_UNCONNECTED,
axis_injectdbiterr => '0',
axis_injectsbiterr => '0',
axis_overflow => NLW_fifo_gen_inst_axis_overflow_UNCONNECTED,
axis_prog_empty => NLW_fifo_gen_inst_axis_prog_empty_UNCONNECTED,
axis_prog_empty_thresh(9 downto 0) => B"0000000000",
axis_prog_full => NLW_fifo_gen_inst_axis_prog_full_UNCONNECTED,
axis_prog_full_thresh(9 downto 0) => B"0000000000",
axis_rd_data_count(10 downto 0) => NLW_fifo_gen_inst_axis_rd_data_count_UNCONNECTED(10 downto 0),
axis_sbiterr => NLW_fifo_gen_inst_axis_sbiterr_UNCONNECTED,
axis_underflow => NLW_fifo_gen_inst_axis_underflow_UNCONNECTED,
axis_wr_data_count(10 downto 0) => NLW_fifo_gen_inst_axis_wr_data_count_UNCONNECTED(10 downto 0),
backup => '0',
backup_marker => '0',
clk => aclk,
data_count(5 downto 0) => NLW_fifo_gen_inst_data_count_UNCONNECTED(5 downto 0),
dbiterr => NLW_fifo_gen_inst_dbiterr_UNCONNECTED,
din(0) => \^din\(0),
dout(0) => rd_cmd_split,
empty => empty,
full => full,
injectdbiterr => '0',
injectsbiterr => '0',
int_clk => '0',
m_aclk => '0',
m_aclk_en => '0',
m_axi_araddr(31 downto 0) => NLW_fifo_gen_inst_m_axi_araddr_UNCONNECTED(31 downto 0),
m_axi_arburst(1 downto 0) => NLW_fifo_gen_inst_m_axi_arburst_UNCONNECTED(1 downto 0),
m_axi_arcache(3 downto 0) => NLW_fifo_gen_inst_m_axi_arcache_UNCONNECTED(3 downto 0),
m_axi_arid(3 downto 0) => NLW_fifo_gen_inst_m_axi_arid_UNCONNECTED(3 downto 0),
m_axi_arlen(7 downto 0) => NLW_fifo_gen_inst_m_axi_arlen_UNCONNECTED(7 downto 0),
m_axi_arlock(1 downto 0) => NLW_fifo_gen_inst_m_axi_arlock_UNCONNECTED(1 downto 0),
m_axi_arprot(2 downto 0) => NLW_fifo_gen_inst_m_axi_arprot_UNCONNECTED(2 downto 0),
m_axi_arqos(3 downto 0) => NLW_fifo_gen_inst_m_axi_arqos_UNCONNECTED(3 downto 0),
m_axi_arready => '0',
m_axi_arregion(3 downto 0) => NLW_fifo_gen_inst_m_axi_arregion_UNCONNECTED(3 downto 0),
m_axi_arsize(2 downto 0) => NLW_fifo_gen_inst_m_axi_arsize_UNCONNECTED(2 downto 0),
m_axi_aruser(0) => NLW_fifo_gen_inst_m_axi_aruser_UNCONNECTED(0),
m_axi_arvalid => NLW_fifo_gen_inst_m_axi_arvalid_UNCONNECTED,
m_axi_awaddr(31 downto 0) => NLW_fifo_gen_inst_m_axi_awaddr_UNCONNECTED(31 downto 0),
m_axi_awburst(1 downto 0) => NLW_fifo_gen_inst_m_axi_awburst_UNCONNECTED(1 downto 0),
m_axi_awcache(3 downto 0) => NLW_fifo_gen_inst_m_axi_awcache_UNCONNECTED(3 downto 0),
m_axi_awid(3 downto 0) => NLW_fifo_gen_inst_m_axi_awid_UNCONNECTED(3 downto 0),
m_axi_awlen(7 downto 0) => NLW_fifo_gen_inst_m_axi_awlen_UNCONNECTED(7 downto 0),
m_axi_awlock(1 downto 0) => NLW_fifo_gen_inst_m_axi_awlock_UNCONNECTED(1 downto 0),
m_axi_awprot(2 downto 0) => NLW_fifo_gen_inst_m_axi_awprot_UNCONNECTED(2 downto 0),
m_axi_awqos(3 downto 0) => NLW_fifo_gen_inst_m_axi_awqos_UNCONNECTED(3 downto 0),
m_axi_awready => '0',
m_axi_awregion(3 downto 0) => NLW_fifo_gen_inst_m_axi_awregion_UNCONNECTED(3 downto 0),
m_axi_awsize(2 downto 0) => NLW_fifo_gen_inst_m_axi_awsize_UNCONNECTED(2 downto 0),
m_axi_awuser(0) => NLW_fifo_gen_inst_m_axi_awuser_UNCONNECTED(0),
m_axi_awvalid => NLW_fifo_gen_inst_m_axi_awvalid_UNCONNECTED,
m_axi_bid(3 downto 0) => B"0000",
m_axi_bready => NLW_fifo_gen_inst_m_axi_bready_UNCONNECTED,
m_axi_bresp(1 downto 0) => B"00",
m_axi_buser(0) => '0',
m_axi_bvalid => '0',
m_axi_rdata(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
m_axi_rid(3 downto 0) => B"0000",
m_axi_rlast => '0',
m_axi_rready => NLW_fifo_gen_inst_m_axi_rready_UNCONNECTED,
m_axi_rresp(1 downto 0) => B"00",
m_axi_ruser(0) => '0',
m_axi_rvalid => '0',
m_axi_wdata(63 downto 0) => NLW_fifo_gen_inst_m_axi_wdata_UNCONNECTED(63 downto 0),
m_axi_wid(3 downto 0) => NLW_fifo_gen_inst_m_axi_wid_UNCONNECTED(3 downto 0),
m_axi_wlast => NLW_fifo_gen_inst_m_axi_wlast_UNCONNECTED,
m_axi_wready => '0',
m_axi_wstrb(7 downto 0) => NLW_fifo_gen_inst_m_axi_wstrb_UNCONNECTED(7 downto 0),
m_axi_wuser(0) => NLW_fifo_gen_inst_m_axi_wuser_UNCONNECTED(0),
m_axi_wvalid => NLW_fifo_gen_inst_m_axi_wvalid_UNCONNECTED,
m_axis_tdata(63 downto 0) => NLW_fifo_gen_inst_m_axis_tdata_UNCONNECTED(63 downto 0),
m_axis_tdest(3 downto 0) => NLW_fifo_gen_inst_m_axis_tdest_UNCONNECTED(3 downto 0),
m_axis_tid(7 downto 0) => NLW_fifo_gen_inst_m_axis_tid_UNCONNECTED(7 downto 0),
m_axis_tkeep(3 downto 0) => NLW_fifo_gen_inst_m_axis_tkeep_UNCONNECTED(3 downto 0),
m_axis_tlast => NLW_fifo_gen_inst_m_axis_tlast_UNCONNECTED,
m_axis_tready => '0',
m_axis_tstrb(3 downto 0) => NLW_fifo_gen_inst_m_axis_tstrb_UNCONNECTED(3 downto 0),
m_axis_tuser(3 downto 0) => NLW_fifo_gen_inst_m_axis_tuser_UNCONNECTED(3 downto 0),
m_axis_tvalid => NLW_fifo_gen_inst_m_axis_tvalid_UNCONNECTED,
overflow => NLW_fifo_gen_inst_overflow_UNCONNECTED,
prog_empty => NLW_fifo_gen_inst_prog_empty_UNCONNECTED,
prog_empty_thresh(4 downto 0) => B"00000",
prog_empty_thresh_assert(4 downto 0) => B"00000",
prog_empty_thresh_negate(4 downto 0) => B"00000",
prog_full => NLW_fifo_gen_inst_prog_full_UNCONNECTED,
prog_full_thresh(4 downto 0) => B"00000",
prog_full_thresh_assert(4 downto 0) => B"00000",
prog_full_thresh_negate(4 downto 0) => B"00000",
rd_clk => '0',
rd_data_count(5 downto 0) => NLW_fifo_gen_inst_rd_data_count_UNCONNECTED(5 downto 0),
rd_en => \^rd_en\,
rd_rst => '0',
rd_rst_busy => NLW_fifo_gen_inst_rd_rst_busy_UNCONNECTED,
rst => SR(0),
s_aclk => '0',
s_aclk_en => '0',
s_aresetn => '0',
s_axi_araddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_arburst(1 downto 0) => B"00",
s_axi_arcache(3 downto 0) => B"0000",
s_axi_arid(3 downto 0) => B"0000",
s_axi_arlen(7 downto 0) => B"00000000",
s_axi_arlock(1 downto 0) => B"00",
s_axi_arprot(2 downto 0) => B"000",
s_axi_arqos(3 downto 0) => B"0000",
s_axi_arready => NLW_fifo_gen_inst_s_axi_arready_UNCONNECTED,
s_axi_arregion(3 downto 0) => B"0000",
s_axi_arsize(2 downto 0) => B"000",
s_axi_aruser(0) => '0',
s_axi_arvalid => '0',
s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_awburst(1 downto 0) => B"00",
s_axi_awcache(3 downto 0) => B"0000",
s_axi_awid(3 downto 0) => B"0000",
s_axi_awlen(7 downto 0) => B"00000000",
s_axi_awlock(1 downto 0) => B"00",
s_axi_awprot(2 downto 0) => B"000",
s_axi_awqos(3 downto 0) => B"0000",
s_axi_awready => NLW_fifo_gen_inst_s_axi_awready_UNCONNECTED,
s_axi_awregion(3 downto 0) => B"0000",
s_axi_awsize(2 downto 0) => B"000",
s_axi_awuser(0) => '0',
s_axi_awvalid => '0',
s_axi_bid(3 downto 0) => NLW_fifo_gen_inst_s_axi_bid_UNCONNECTED(3 downto 0),
s_axi_bready => '0',
s_axi_bresp(1 downto 0) => NLW_fifo_gen_inst_s_axi_bresp_UNCONNECTED(1 downto 0),
s_axi_buser(0) => NLW_fifo_gen_inst_s_axi_buser_UNCONNECTED(0),
s_axi_bvalid => NLW_fifo_gen_inst_s_axi_bvalid_UNCONNECTED,
s_axi_rdata(63 downto 0) => NLW_fifo_gen_inst_s_axi_rdata_UNCONNECTED(63 downto 0),
s_axi_rid(3 downto 0) => NLW_fifo_gen_inst_s_axi_rid_UNCONNECTED(3 downto 0),
s_axi_rlast => NLW_fifo_gen_inst_s_axi_rlast_UNCONNECTED,
s_axi_rready => '0',
s_axi_rresp(1 downto 0) => NLW_fifo_gen_inst_s_axi_rresp_UNCONNECTED(1 downto 0),
s_axi_ruser(0) => NLW_fifo_gen_inst_s_axi_ruser_UNCONNECTED(0),
s_axi_rvalid => NLW_fifo_gen_inst_s_axi_rvalid_UNCONNECTED,
s_axi_wdata(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
s_axi_wid(3 downto 0) => B"0000",
s_axi_wlast => '0',
s_axi_wready => NLW_fifo_gen_inst_s_axi_wready_UNCONNECTED,
s_axi_wstrb(7 downto 0) => B"00000000",
s_axi_wuser(0) => '0',
s_axi_wvalid => '0',
s_axis_tdata(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
s_axis_tdest(3 downto 0) => B"0000",
s_axis_tid(7 downto 0) => B"00000000",
s_axis_tkeep(3 downto 0) => B"0000",
s_axis_tlast => '0',
s_axis_tready => NLW_fifo_gen_inst_s_axis_tready_UNCONNECTED,
s_axis_tstrb(3 downto 0) => B"0000",
s_axis_tuser(3 downto 0) => B"0000",
s_axis_tvalid => '0',
sbiterr => NLW_fifo_gen_inst_sbiterr_UNCONNECTED,
sleep => '0',
srst => '0',
underflow => NLW_fifo_gen_inst_underflow_UNCONNECTED,
valid => NLW_fifo_gen_inst_valid_UNCONNECTED,
wr_ack => NLW_fifo_gen_inst_wr_ack_UNCONNECTED,
wr_clk => '0',
wr_data_count(5 downto 0) => NLW_fifo_gen_inst_wr_data_count_UNCONNECTED(5 downto 0),
wr_en => \^wr_en\,
wr_rst => '0',
wr_rst_busy => NLW_fifo_gen_inst_wr_rst_busy_UNCONNECTED
);
\fifo_gen_inst_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => S_AXI_AREADY_I_i_2_n_0,
I1 => need_to_split_q,
O => \^din\(0)
);
\fifo_gen_inst_i_2__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000001F00"
)
port map (
I0 => need_to_split_q,
I1 => m_axi_arvalid_INST_0_i_3_n_0,
I2 => m_axi_arvalid_INST_0_i_2_n_0,
I3 => command_ongoing,
I4 => full,
I5 => cmd_push_block,
O => \^wr_en\
);
\fifo_gen_inst_i_3__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"4000"
)
port map (
I0 => empty,
I1 => m_axi_rvalid,
I2 => s_axi_rready,
I3 => m_axi_rlast,
O => \^rd_en\
);
m_axi_arvalid_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => m_axi_arvalid_INST_0_i_1_n_0,
O => m_axi_arvalid
);
m_axi_arvalid_INST_0_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"5F4F5F4F5F4F4F4F"
)
port map (
I0 => cmd_push_block,
I1 => full,
I2 => command_ongoing,
I3 => m_axi_arvalid_INST_0_i_2_n_0,
I4 => m_axi_arvalid_INST_0_i_3_n_0,
I5 => need_to_split_q,
O => m_axi_arvalid_INST_0_i_1_n_0
);
m_axi_arvalid_INST_0_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAABEFFFFBE"
)
port map (
I0 => multiple_id_non_split,
I1 => \S_AXI_AID_Q_reg[1]\(0),
I2 => \queue_id_reg[0]\,
I3 => \S_AXI_AID_Q_reg[1]\(1),
I4 => \queue_id_reg[1]\,
I5 => cmd_empty,
O => m_axi_arvalid_INST_0_i_2_n_0
);
m_axi_arvalid_INST_0_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"0440444444440440"
)
port map (
I0 => cmd_empty,
I1 => split_in_progress_reg_0,
I2 => \queue_id_reg[1]\,
I3 => \S_AXI_AID_Q_reg[1]\(1),
I4 => \queue_id_reg[0]\,
I5 => \S_AXI_AID_Q_reg[1]\(0),
O => m_axi_arvalid_INST_0_i_3_n_0
);
m_axi_rready_INST_0: unisim.vcomponents.LUT3
generic map(
INIT => X"0D"
)
port map (
I0 => m_axi_rvalid,
I1 => s_axi_rready,
I2 => empty,
O => m_axi_rready
);
multiple_id_non_split_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000AAAAAAAE"
)
port map (
I0 => multiple_id_non_split,
I1 => \^wr_en\,
I2 => need_to_split_q,
I3 => split_in_progress_reg_1,
I4 => \S_AXI_AID_Q_reg[0]\,
I5 => split_in_progress,
O => multiple_id_non_split_reg
);
multiple_id_non_split_i_4: unisim.vcomponents.LUT4
generic map(
INIT => X"FF8F"
)
port map (
I0 => almost_empty,
I1 => \^rd_en\,
I2 => aresetn,
I3 => cmd_empty,
O => split_in_progress
);
s_axi_rlast_INST_0: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => m_axi_rlast,
I1 => rd_cmd_split,
O => s_axi_rlast
);
s_axi_rvalid_INST_0: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => m_axi_rvalid,
I1 => empty,
O => s_axi_rvalid
);
split_in_progress_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"0000AAEA"
)
port map (
I0 => split_in_progress_reg_0,
I1 => \^wr_en\,
I2 => need_to_split_q,
I3 => m_axi_arvalid_INST_0_i_2_n_0,
I4 => split_in_progress,
O => split_in_progress_reg
);
\split_ongoing_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => m_axi_arready,
I1 => m_axi_arvalid_INST_0_i_1_n_0,
O => \^pushed_commands_reg[0]\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_pc_1_axi_data_fifo_v2_1_10_axic_fifo is
port (
dout : out STD_LOGIC_VECTOR ( 5 downto 0 );
full : out STD_LOGIC;
empty : out STD_LOGIC;
SR : out STD_LOGIC_VECTOR ( 0 to 0 );
din : out STD_LOGIC_VECTOR ( 3 downto 0 );
\USE_B_CHANNEL.cmd_b_empty_reg\ : out STD_LOGIC;
\USE_B_CHANNEL.cmd_b_empty_reg_0\ : out STD_LOGIC;
\length_counter_1_reg_0__s_port_]\ : out STD_LOGIC;
s_axi_wready : out STD_LOGIC;
m_axi_wvalid : out STD_LOGIC;
aclk : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
wr_en : in STD_LOGIC;
wr_cmd_ready : in STD_LOGIC;
cmd_empty : in STD_LOGIC;
cmd_b_empty : in STD_LOGIC;
queue_id : in STD_LOGIC_VECTOR ( 1 downto 0 );
cmd_push_block : in STD_LOGIC;
command_ongoing : in STD_LOGIC;
aresetn : in STD_LOGIC;
first_mi_word : in STD_LOGIC;
length_counter_1_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wready : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
\S_AXI_ALEN_Q_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\pushed_commands_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
need_to_split_q : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_pc_1_axi_data_fifo_v2_1_10_axic_fifo : entity is "axi_data_fifo_v2_1_10_axic_fifo";
end system_auto_pc_1_axi_data_fifo_v2_1_10_axic_fifo;
architecture STRUCTURE of system_auto_pc_1_axi_data_fifo_v2_1_10_axic_fifo is
signal \length_counter_1_reg_0__s_net_1\ : STD_LOGIC;
begin
\length_counter_1_reg_0__s_port_]\ <= \length_counter_1_reg_0__s_net_1\;
inst: entity work.system_auto_pc_1_axi_data_fifo_v2_1_10_fifo_gen
port map (
Q(1 downto 0) => Q(1 downto 0),
SR(0) => SR(0),
\S_AXI_ALEN_Q_reg[3]\(3 downto 0) => \S_AXI_ALEN_Q_reg[3]\(3 downto 0),
\USE_B_CHANNEL.cmd_b_empty_reg\ => \USE_B_CHANNEL.cmd_b_empty_reg\,
\USE_B_CHANNEL.cmd_b_empty_reg_0\ => \USE_B_CHANNEL.cmd_b_empty_reg_0\,
aclk => aclk,
aresetn => aresetn,
cmd_b_empty => cmd_b_empty,
cmd_empty => cmd_empty,
cmd_push_block => cmd_push_block,
command_ongoing => command_ongoing,
din(3 downto 0) => din(3 downto 0),
dout(5 downto 0) => dout(5 downto 0),
empty => empty,
first_mi_word => first_mi_word,
full => full,
length_counter_1_reg(0) => length_counter_1_reg(0),
\length_counter_1_reg_0__s_port_]\ => \length_counter_1_reg_0__s_net_1\,
m_axi_wready => m_axi_wready,
m_axi_wvalid => m_axi_wvalid,
need_to_split_q => need_to_split_q,
\pushed_commands_reg[3]\(3 downto 0) => \pushed_commands_reg[3]\(3 downto 0),
queue_id(1 downto 0) => queue_id(1 downto 0),
s_axi_wready => s_axi_wready,
s_axi_wvalid => s_axi_wvalid,
wr_cmd_ready => wr_cmd_ready,
wr_en => wr_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_auto_pc_1_axi_data_fifo_v2_1_10_axic_fifo__parameterized0\ is
port (
first_mi_word_reg : out STD_LOGIC_VECTOR ( 4 downto 0 );
\gpregsm1.user_valid_reg\ : out STD_LOGIC;
din : out STD_LOGIC_VECTOR ( 0 to 0 );
D : out STD_LOGIC_VECTOR ( 4 downto 0 );
wr_en : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
multiple_id_non_split_reg : out STD_LOGIC;
split_in_progress_reg : out STD_LOGIC;
cmd_push_block_reg : out STD_LOGIC;
pushed_new_cmd : out STD_LOGIC;
cmd_empty_reg : out STD_LOGIC;
\queue_id_reg[0]\ : out STD_LOGIC;
\queue_id_reg[1]\ : out STD_LOGIC;
cmd_b_push_block_reg : out STD_LOGIC;
\USE_B_CHANNEL.cmd_b_depth_reg[5]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\USE_B_CHANNEL.cmd_b_empty_reg\ : out STD_LOGIC;
\USE_B_CHANNEL.cmd_b_depth_reg[5]_0\ : out STD_LOGIC_VECTOR ( 4 downto 0 );
m_axi_awvalid : out STD_LOGIC;
S_AXI_AREADY_I_reg : out STD_LOGIC;
command_ongoing_reg : out STD_LOGIC;
aclk : in STD_LOGIC;
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
\num_transactions_q_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
wr_cmd_b_ready : in STD_LOGIC;
almost_empty : in STD_LOGIC;
wr_cmd_ready : in STD_LOGIC;
cmd_empty : in STD_LOGIC;
aresetn : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 5 downto 0 );
need_to_split_q : in STD_LOGIC;
cmd_push_block : in STD_LOGIC;
multiple_id_non_split : in STD_LOGIC;
\S_AXI_AID_Q_reg[0]\ : in STD_LOGIC;
incr_need_to_split_q_reg : in STD_LOGIC;
split_in_progress_reg_0 : in STD_LOGIC;
m_axi_awready : in STD_LOGIC;
\S_AXI_AID_Q_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
queue_id : in STD_LOGIC_VECTOR ( 1 downto 0 );
cmd_b_push_block : in STD_LOGIC;
S_AXI_AREADY_I_reg_0 : in STD_LOGIC;
almost_b_empty : in STD_LOGIC;
cmd_b_empty : in STD_LOGIC;
\USE_B_CHANNEL.cmd_b_depth_reg[5]_1\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
\goreg_dm.dout_i_reg[4]\ : in STD_LOGIC;
m_axi_bvalid : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
cmd_push_block_reg_0 : in STD_LOGIC;
cmd_empty_reg_0 : in STD_LOGIC;
command_ongoing : in STD_LOGIC;
full : in STD_LOGIC;
access_is_incr_q : in STD_LOGIC;
\pushed_commands_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\areset_d_reg[0]\ : in STD_LOGIC;
areset_d : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awvalid : in STD_LOGIC;
\areset_d_reg[1]\ : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_auto_pc_1_axi_data_fifo_v2_1_10_axic_fifo__parameterized0\ : entity is "axi_data_fifo_v2_1_10_axic_fifo";
end \system_auto_pc_1_axi_data_fifo_v2_1_10_axic_fifo__parameterized0\;
architecture STRUCTURE of \system_auto_pc_1_axi_data_fifo_v2_1_10_axic_fifo__parameterized0\ is
begin
inst: entity work.\system_auto_pc_1_axi_data_fifo_v2_1_10_fifo_gen__parameterized0\
port map (
D(4 downto 0) => D(4 downto 0),
E(0) => E(0),
Q(5 downto 0) => Q(5 downto 0),
SR(0) => SR(0),
\S_AXI_AID_Q_reg[0]\ => \S_AXI_AID_Q_reg[0]\,
\S_AXI_AID_Q_reg[1]\(1 downto 0) => \S_AXI_AID_Q_reg[1]\(1 downto 0),
S_AXI_AREADY_I_reg => S_AXI_AREADY_I_reg,
S_AXI_AREADY_I_reg_0 => S_AXI_AREADY_I_reg_0,
\USE_B_CHANNEL.cmd_b_depth_reg[5]\(0) => \USE_B_CHANNEL.cmd_b_depth_reg[5]\(0),
\USE_B_CHANNEL.cmd_b_depth_reg[5]_0\(4 downto 0) => \USE_B_CHANNEL.cmd_b_depth_reg[5]_0\(4 downto 0),
\USE_B_CHANNEL.cmd_b_depth_reg[5]_1\(5 downto 0) => \USE_B_CHANNEL.cmd_b_depth_reg[5]_1\(5 downto 0),
\USE_B_CHANNEL.cmd_b_empty_reg\ => \USE_B_CHANNEL.cmd_b_empty_reg\,
access_is_incr_q => access_is_incr_q,
aclk => aclk,
almost_b_empty => almost_b_empty,
almost_empty => almost_empty,
areset_d(0) => areset_d(0),
\areset_d_reg[0]\ => \areset_d_reg[0]\,
\areset_d_reg[1]\ => \areset_d_reg[1]\,
aresetn => aresetn,
cmd_b_empty => cmd_b_empty,
cmd_b_push_block => cmd_b_push_block,
cmd_b_push_block_reg => cmd_b_push_block_reg,
cmd_empty => cmd_empty,
cmd_empty_reg => cmd_empty_reg,
cmd_empty_reg_0 => cmd_empty_reg_0,
cmd_push_block => cmd_push_block,
cmd_push_block_reg => cmd_push_block_reg,
cmd_push_block_reg_0 => cmd_push_block_reg_0,
command_ongoing => command_ongoing,
command_ongoing_reg => command_ongoing_reg,
din(0) => din(0),
first_mi_word_reg(4 downto 0) => first_mi_word_reg(4 downto 0),
full => full,
\goreg_dm.dout_i_reg[4]\ => \goreg_dm.dout_i_reg[4]\,
\gpregsm1.user_valid_reg\ => \gpregsm1.user_valid_reg\,
incr_need_to_split_q_reg => incr_need_to_split_q_reg,
m_axi_awready => m_axi_awready,
m_axi_awvalid => m_axi_awvalid,
m_axi_bvalid => m_axi_bvalid,
multiple_id_non_split => multiple_id_non_split,
multiple_id_non_split_reg => multiple_id_non_split_reg,
need_to_split_q => need_to_split_q,
\num_transactions_q_reg[3]\(3 downto 0) => \num_transactions_q_reg[3]\(3 downto 0),
\pushed_commands_reg[0]\ => pushed_new_cmd,
\pushed_commands_reg[3]\(3 downto 0) => \pushed_commands_reg[3]\(3 downto 0),
queue_id(1 downto 0) => queue_id(1 downto 0),
\queue_id_reg[0]\ => \queue_id_reg[0]\,
\queue_id_reg[1]\ => \queue_id_reg[1]\,
s_axi_awvalid => s_axi_awvalid,
s_axi_bready => s_axi_bready,
split_in_progress_reg => split_in_progress_reg,
split_in_progress_reg_0 => split_in_progress_reg_0,
wr_cmd_b_ready => wr_cmd_b_ready,
wr_cmd_ready => wr_cmd_ready,
wr_en => wr_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_auto_pc_1_axi_data_fifo_v2_1_10_axic_fifo__parameterized1\ is
port (
din : out STD_LOGIC_VECTOR ( 0 to 0 );
cmd_push : out STD_LOGIC;
rd_cmd_ready : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 4 downto 0 );
m_axi_arvalid : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
pushed_new_cmd : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rlast : out STD_LOGIC;
m_axi_rready : out STD_LOGIC;
S_AXI_AREADY_I_reg : out STD_LOGIC;
cmd_push_block_reg : out STD_LOGIC;
command_ongoing_reg : out STD_LOGIC;
split_in_progress_reg : out STD_LOGIC;
multiple_id_non_split_reg : out STD_LOGIC;
aclk : in STD_LOGIC;
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 5 downto 0 );
need_to_split_q : in STD_LOGIC;
m_axi_rlast : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC;
command_ongoing : in STD_LOGIC;
cmd_push_block : in STD_LOGIC;
m_axi_arready : in STD_LOGIC;
multiple_id_non_split : in STD_LOGIC;
\S_AXI_AID_Q_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\queue_id_reg[0]\ : in STD_LOGIC;
\queue_id_reg[1]\ : in STD_LOGIC;
cmd_empty : in STD_LOGIC;
split_in_progress_reg_0 : in STD_LOGIC;
almost_empty : in STD_LOGIC;
aresetn : in STD_LOGIC;
access_is_incr_q : in STD_LOGIC;
\num_transactions_q_reg[3]\ : in STD_LOGIC;
\pushed_commands_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\num_transactions_q_reg[0]\ : in STD_LOGIC;
\num_transactions_q_reg[1]\ : in STD_LOGIC;
\num_transactions_q_reg[2]\ : in STD_LOGIC;
areset_d : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_AREADY_I_reg_0 : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
\areset_d_reg[1]\ : in STD_LOGIC;
split_in_progress_reg_1 : in STD_LOGIC;
\S_AXI_AID_Q_reg[0]\ : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_auto_pc_1_axi_data_fifo_v2_1_10_axic_fifo__parameterized1\ : entity is "axi_data_fifo_v2_1_10_axic_fifo";
end \system_auto_pc_1_axi_data_fifo_v2_1_10_axic_fifo__parameterized1\;
architecture STRUCTURE of \system_auto_pc_1_axi_data_fifo_v2_1_10_axic_fifo__parameterized1\ is
begin
inst: entity work.\system_auto_pc_1_axi_data_fifo_v2_1_10_fifo_gen__parameterized1\
port map (
D(4 downto 0) => D(4 downto 0),
E(0) => E(0),
Q(5 downto 0) => Q(5 downto 0),
SR(0) => SR(0),
\S_AXI_AID_Q_reg[0]\ => \S_AXI_AID_Q_reg[0]\,
\S_AXI_AID_Q_reg[1]\(1 downto 0) => \S_AXI_AID_Q_reg[1]\(1 downto 0),
S_AXI_AREADY_I_reg => S_AXI_AREADY_I_reg,
S_AXI_AREADY_I_reg_0 => S_AXI_AREADY_I_reg_0,
access_is_incr_q => access_is_incr_q,
aclk => aclk,
almost_empty => almost_empty,
areset_d(1 downto 0) => areset_d(1 downto 0),
\areset_d_reg[1]\ => \areset_d_reg[1]\,
aresetn => aresetn,
cmd_empty => cmd_empty,
cmd_push_block => cmd_push_block,
cmd_push_block_reg => cmd_push_block_reg,
command_ongoing => command_ongoing,
command_ongoing_reg => command_ongoing_reg,
din(0) => din(0),
m_axi_arready => m_axi_arready,
m_axi_arvalid => m_axi_arvalid,
m_axi_rlast => m_axi_rlast,
m_axi_rready => m_axi_rready,
m_axi_rvalid => m_axi_rvalid,
multiple_id_non_split => multiple_id_non_split,
multiple_id_non_split_reg => multiple_id_non_split_reg,
need_to_split_q => need_to_split_q,
\num_transactions_q_reg[0]\ => \num_transactions_q_reg[0]\,
\num_transactions_q_reg[1]\ => \num_transactions_q_reg[1]\,
\num_transactions_q_reg[2]\ => \num_transactions_q_reg[2]\,
\num_transactions_q_reg[3]\ => \num_transactions_q_reg[3]\,
\pushed_commands_reg[0]\ => pushed_new_cmd,
\pushed_commands_reg[3]\(3 downto 0) => \pushed_commands_reg[3]\(3 downto 0),
\queue_id_reg[0]\ => \queue_id_reg[0]\,
\queue_id_reg[1]\ => \queue_id_reg[1]\,
rd_en => rd_cmd_ready,
s_axi_arvalid => s_axi_arvalid,
s_axi_rlast => s_axi_rlast,
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid,
split_in_progress_reg => split_in_progress_reg,
split_in_progress_reg_0 => split_in_progress_reg_0,
split_in_progress_reg_1 => split_in_progress_reg_1,
wr_en => cmd_push
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_pc_1_axi_protocol_converter_v2_1_11_a_axi3_conv is
port (
dout : out STD_LOGIC_VECTOR ( 5 downto 0 );
empty : out STD_LOGIC;
SR : out STD_LOGIC_VECTOR ( 0 to 0 );
din : out STD_LOGIC_VECTOR ( 5 downto 0 );
first_mi_word_reg : out STD_LOGIC_VECTOR ( 4 downto 0 );
\gpregsm1.user_valid_reg\ : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
areset_d : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awvalid : out STD_LOGIC;
\length_counter_1_reg_0__s_port_]\ : out STD_LOGIC;
s_axi_wready : out STD_LOGIC;
m_axi_wvalid : out STD_LOGIC;
command_ongoing_reg_0 : out STD_LOGIC;
m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
aclk : in STD_LOGIC;
wr_cmd_ready : in STD_LOGIC;
wr_cmd_b_ready : in STD_LOGIC;
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
aresetn : in STD_LOGIC;
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awready : in STD_LOGIC;
\goreg_dm.dout_i_reg[4]\ : in STD_LOGIC;
m_axi_bvalid : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
first_mi_word : in STD_LOGIC;
length_counter_1_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wready : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_pc_1_axi_protocol_converter_v2_1_11_a_axi3_conv : entity is "axi_protocol_converter_v2_1_11_a_axi3_conv";
end system_auto_pc_1_axi_protocol_converter_v2_1_11_a_axi3_conv;
architecture STRUCTURE of system_auto_pc_1_axi_protocol_converter_v2_1_11_a_axi3_conv is
signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^sr\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal S_AXI_AADDR_Q : STD_LOGIC_VECTOR ( 31 downto 0 );
signal S_AXI_ALEN_Q : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \S_AXI_ALOCK_Q_reg_n_0_[0]\ : STD_LOGIC;
signal \USE_BURSTS.cmd_queue_n_13\ : STD_LOGIC;
signal \USE_BURSTS.cmd_queue_n_14\ : STD_LOGIC;
signal \USE_B_CHANNEL.cmd_b_depth[0]_i_1_n_0\ : STD_LOGIC;
signal \USE_B_CHANNEL.cmd_b_depth_reg__0\ : STD_LOGIC_VECTOR ( 5 downto 0 );
signal \USE_B_CHANNEL.cmd_b_queue_n_10\ : STD_LOGIC;
signal \USE_B_CHANNEL.cmd_b_queue_n_11\ : STD_LOGIC;
signal \USE_B_CHANNEL.cmd_b_queue_n_13\ : STD_LOGIC;
signal \USE_B_CHANNEL.cmd_b_queue_n_14\ : STD_LOGIC;
signal \USE_B_CHANNEL.cmd_b_queue_n_15\ : STD_LOGIC;
signal \USE_B_CHANNEL.cmd_b_queue_n_16\ : STD_LOGIC;
signal \USE_B_CHANNEL.cmd_b_queue_n_18\ : STD_LOGIC;
signal \USE_B_CHANNEL.cmd_b_queue_n_19\ : STD_LOGIC;
signal \USE_B_CHANNEL.cmd_b_queue_n_20\ : STD_LOGIC;
signal \USE_B_CHANNEL.cmd_b_queue_n_21\ : STD_LOGIC;
signal \USE_B_CHANNEL.cmd_b_queue_n_22\ : STD_LOGIC;
signal \USE_B_CHANNEL.cmd_b_queue_n_23\ : STD_LOGIC;
signal \USE_B_CHANNEL.cmd_b_queue_n_24\ : STD_LOGIC;
signal \USE_B_CHANNEL.cmd_b_queue_n_25\ : STD_LOGIC;
signal \USE_B_CHANNEL.cmd_b_queue_n_26\ : STD_LOGIC;
signal \USE_B_CHANNEL.cmd_b_queue_n_27\ : STD_LOGIC;
signal \USE_B_CHANNEL.cmd_b_queue_n_28\ : STD_LOGIC;
signal \USE_B_CHANNEL.cmd_b_queue_n_30\ : STD_LOGIC;
signal \USE_B_CHANNEL.cmd_b_queue_n_31\ : STD_LOGIC;
signal \USE_B_CHANNEL.cmd_b_queue_n_6\ : STD_LOGIC;
signal \USE_B_CHANNEL.cmd_b_queue_n_7\ : STD_LOGIC;
signal \USE_B_CHANNEL.cmd_b_queue_n_8\ : STD_LOGIC;
signal \USE_B_CHANNEL.cmd_b_queue_n_9\ : STD_LOGIC;
signal access_is_incr : STD_LOGIC;
signal access_is_incr_q : STD_LOGIC;
signal addr_step : STD_LOGIC_VECTOR ( 11 downto 5 );
signal addr_step_q : STD_LOGIC_VECTOR ( 11 downto 5 );
signal almost_b_empty : STD_LOGIC;
signal almost_empty : STD_LOGIC;
signal \^areset_d\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal cmd_b_empty : STD_LOGIC;
signal cmd_b_push_block : STD_LOGIC;
signal \cmd_depth[0]_i_1_n_0\ : STD_LOGIC;
signal \cmd_depth_reg__0\ : STD_LOGIC_VECTOR ( 5 downto 0 );
signal cmd_empty : STD_LOGIC;
signal cmd_push : STD_LOGIC;
signal cmd_push_block : STD_LOGIC;
signal command_ongoing : STD_LOGIC;
signal \^command_ongoing_reg_0\ : STD_LOGIC;
signal \^din\ : STD_LOGIC_VECTOR ( 5 downto 0 );
signal first_step : STD_LOGIC_VECTOR ( 11 downto 4 );
signal first_step_q : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \first_step_q[0]_i_1_n_0\ : STD_LOGIC;
signal \first_step_q[10]_i_2_n_0\ : STD_LOGIC;
signal \first_step_q[11]_i_2_n_0\ : STD_LOGIC;
signal \first_step_q[1]_i_1_n_0\ : STD_LOGIC;
signal \first_step_q[2]_i_1_n_0\ : STD_LOGIC;
signal \first_step_q[3]_i_1_n_0\ : STD_LOGIC;
signal \first_step_q[6]_i_2_n_0\ : STD_LOGIC;
signal \first_step_q[7]_i_2_n_0\ : STD_LOGIC;
signal \first_step_q[8]_i_2_n_0\ : STD_LOGIC;
signal \first_step_q[9]_i_2_n_0\ : STD_LOGIC;
signal \incr_need_to_split__0\ : STD_LOGIC;
signal \inst/full\ : STD_LOGIC;
signal \length_counter_1_reg_0__s_net_1\ : STD_LOGIC;
signal \^m_axi_awaddr\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal multiple_id_non_split : STD_LOGIC;
signal multiple_id_non_split_i_2_n_0 : STD_LOGIC;
signal \multiple_id_non_split_i_3__0_n_0\ : STD_LOGIC;
signal need_to_split_q : STD_LOGIC;
signal next_mi_addr : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \next_mi_addr[11]_i_2_n_0\ : STD_LOGIC;
signal \next_mi_addr[11]_i_3_n_0\ : STD_LOGIC;
signal \next_mi_addr[11]_i_4_n_0\ : STD_LOGIC;
signal \next_mi_addr[11]_i_5_n_0\ : STD_LOGIC;
signal \next_mi_addr[11]_i_6_n_0\ : STD_LOGIC;
signal \next_mi_addr[15]_i_2_n_0\ : STD_LOGIC;
signal \next_mi_addr[15]_i_3_n_0\ : STD_LOGIC;
signal \next_mi_addr[15]_i_4_n_0\ : STD_LOGIC;
signal \next_mi_addr[15]_i_5_n_0\ : STD_LOGIC;
signal \next_mi_addr[15]_i_6_n_0\ : STD_LOGIC;
signal \next_mi_addr[15]_i_7_n_0\ : STD_LOGIC;
signal \next_mi_addr[15]_i_8_n_0\ : STD_LOGIC;
signal \next_mi_addr[15]_i_9_n_0\ : STD_LOGIC;
signal \next_mi_addr[19]_i_2_n_0\ : STD_LOGIC;
signal \next_mi_addr[19]_i_3_n_0\ : STD_LOGIC;
signal \next_mi_addr[19]_i_4_n_0\ : STD_LOGIC;
signal \next_mi_addr[19]_i_5_n_0\ : STD_LOGIC;
signal \next_mi_addr[23]_i_2_n_0\ : STD_LOGIC;
signal \next_mi_addr[23]_i_3_n_0\ : STD_LOGIC;
signal \next_mi_addr[23]_i_4_n_0\ : STD_LOGIC;
signal \next_mi_addr[23]_i_5_n_0\ : STD_LOGIC;
signal \next_mi_addr[27]_i_2_n_0\ : STD_LOGIC;
signal \next_mi_addr[27]_i_3_n_0\ : STD_LOGIC;
signal \next_mi_addr[27]_i_4_n_0\ : STD_LOGIC;
signal \next_mi_addr[27]_i_5_n_0\ : STD_LOGIC;
signal \next_mi_addr[31]_i_2_n_0\ : STD_LOGIC;
signal \next_mi_addr[31]_i_3_n_0\ : STD_LOGIC;
signal \next_mi_addr[31]_i_4_n_0\ : STD_LOGIC;
signal \next_mi_addr[31]_i_5_n_0\ : STD_LOGIC;
signal \next_mi_addr[3]_i_2_n_0\ : STD_LOGIC;
signal \next_mi_addr[3]_i_3_n_0\ : STD_LOGIC;
signal \next_mi_addr[3]_i_4_n_0\ : STD_LOGIC;
signal \next_mi_addr[3]_i_5_n_0\ : STD_LOGIC;
signal \next_mi_addr[3]_i_6_n_0\ : STD_LOGIC;
signal \next_mi_addr[7]_i_2_n_0\ : STD_LOGIC;
signal \next_mi_addr[7]_i_3_n_0\ : STD_LOGIC;
signal \next_mi_addr[7]_i_4_n_0\ : STD_LOGIC;
signal \next_mi_addr[7]_i_5_n_0\ : STD_LOGIC;
signal \next_mi_addr_reg[11]_i_1_n_0\ : STD_LOGIC;
signal \next_mi_addr_reg[11]_i_1_n_1\ : STD_LOGIC;
signal \next_mi_addr_reg[11]_i_1_n_2\ : STD_LOGIC;
signal \next_mi_addr_reg[11]_i_1_n_3\ : STD_LOGIC;
signal \next_mi_addr_reg[11]_i_1_n_4\ : STD_LOGIC;
signal \next_mi_addr_reg[11]_i_1_n_5\ : STD_LOGIC;
signal \next_mi_addr_reg[11]_i_1_n_6\ : STD_LOGIC;
signal \next_mi_addr_reg[11]_i_1_n_7\ : STD_LOGIC;
signal \next_mi_addr_reg[15]_i_1_n_0\ : STD_LOGIC;
signal \next_mi_addr_reg[15]_i_1_n_1\ : STD_LOGIC;
signal \next_mi_addr_reg[15]_i_1_n_2\ : STD_LOGIC;
signal \next_mi_addr_reg[15]_i_1_n_3\ : STD_LOGIC;
signal \next_mi_addr_reg[15]_i_1_n_4\ : STD_LOGIC;
signal \next_mi_addr_reg[15]_i_1_n_5\ : STD_LOGIC;
signal \next_mi_addr_reg[15]_i_1_n_6\ : STD_LOGIC;
signal \next_mi_addr_reg[15]_i_1_n_7\ : STD_LOGIC;
signal \next_mi_addr_reg[19]_i_1_n_0\ : STD_LOGIC;
signal \next_mi_addr_reg[19]_i_1_n_1\ : STD_LOGIC;
signal \next_mi_addr_reg[19]_i_1_n_2\ : STD_LOGIC;
signal \next_mi_addr_reg[19]_i_1_n_3\ : STD_LOGIC;
signal \next_mi_addr_reg[19]_i_1_n_4\ : STD_LOGIC;
signal \next_mi_addr_reg[19]_i_1_n_5\ : STD_LOGIC;
signal \next_mi_addr_reg[19]_i_1_n_6\ : STD_LOGIC;
signal \next_mi_addr_reg[19]_i_1_n_7\ : STD_LOGIC;
signal \next_mi_addr_reg[23]_i_1_n_0\ : STD_LOGIC;
signal \next_mi_addr_reg[23]_i_1_n_1\ : STD_LOGIC;
signal \next_mi_addr_reg[23]_i_1_n_2\ : STD_LOGIC;
signal \next_mi_addr_reg[23]_i_1_n_3\ : STD_LOGIC;
signal \next_mi_addr_reg[23]_i_1_n_4\ : STD_LOGIC;
signal \next_mi_addr_reg[23]_i_1_n_5\ : STD_LOGIC;
signal \next_mi_addr_reg[23]_i_1_n_6\ : STD_LOGIC;
signal \next_mi_addr_reg[23]_i_1_n_7\ : STD_LOGIC;
signal \next_mi_addr_reg[27]_i_1_n_0\ : STD_LOGIC;
signal \next_mi_addr_reg[27]_i_1_n_1\ : STD_LOGIC;
signal \next_mi_addr_reg[27]_i_1_n_2\ : STD_LOGIC;
signal \next_mi_addr_reg[27]_i_1_n_3\ : STD_LOGIC;
signal \next_mi_addr_reg[27]_i_1_n_4\ : STD_LOGIC;
signal \next_mi_addr_reg[27]_i_1_n_5\ : STD_LOGIC;
signal \next_mi_addr_reg[27]_i_1_n_6\ : STD_LOGIC;
signal \next_mi_addr_reg[27]_i_1_n_7\ : STD_LOGIC;
signal \next_mi_addr_reg[31]_i_1_n_1\ : STD_LOGIC;
signal \next_mi_addr_reg[31]_i_1_n_2\ : STD_LOGIC;
signal \next_mi_addr_reg[31]_i_1_n_3\ : STD_LOGIC;
signal \next_mi_addr_reg[31]_i_1_n_4\ : STD_LOGIC;
signal \next_mi_addr_reg[31]_i_1_n_5\ : STD_LOGIC;
signal \next_mi_addr_reg[31]_i_1_n_6\ : STD_LOGIC;
signal \next_mi_addr_reg[31]_i_1_n_7\ : STD_LOGIC;
signal \next_mi_addr_reg[3]_i_1_n_0\ : STD_LOGIC;
signal \next_mi_addr_reg[3]_i_1_n_1\ : STD_LOGIC;
signal \next_mi_addr_reg[3]_i_1_n_2\ : STD_LOGIC;
signal \next_mi_addr_reg[3]_i_1_n_3\ : STD_LOGIC;
signal \next_mi_addr_reg[3]_i_1_n_4\ : STD_LOGIC;
signal \next_mi_addr_reg[3]_i_1_n_5\ : STD_LOGIC;
signal \next_mi_addr_reg[3]_i_1_n_6\ : STD_LOGIC;
signal \next_mi_addr_reg[3]_i_1_n_7\ : STD_LOGIC;
signal \next_mi_addr_reg[7]_i_1_n_0\ : STD_LOGIC;
signal \next_mi_addr_reg[7]_i_1_n_1\ : STD_LOGIC;
signal \next_mi_addr_reg[7]_i_1_n_2\ : STD_LOGIC;
signal \next_mi_addr_reg[7]_i_1_n_3\ : STD_LOGIC;
signal \next_mi_addr_reg[7]_i_1_n_4\ : STD_LOGIC;
signal \next_mi_addr_reg[7]_i_1_n_5\ : STD_LOGIC;
signal \next_mi_addr_reg[7]_i_1_n_6\ : STD_LOGIC;
signal \next_mi_addr_reg[7]_i_1_n_7\ : STD_LOGIC;
signal num_transactions_q : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_0_in : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \pushed_commands[3]_i_1_n_0\ : STD_LOGIC;
signal \pushed_commands_reg__0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal pushed_new_cmd : STD_LOGIC;
signal queue_id : STD_LOGIC_VECTOR ( 1 downto 0 );
signal size_mask : STD_LOGIC_VECTOR ( 6 downto 0 );
signal size_mask_q : STD_LOGIC_VECTOR ( 31 downto 0 );
signal split_in_progress_reg_n_0 : STD_LOGIC;
signal split_ongoing : STD_LOGIC;
signal \NLW_next_mi_addr_reg[31]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \addr_step_q[10]_i_1\ : label is "soft_lutpair53";
attribute SOFT_HLUTNM of \addr_step_q[11]_i_1\ : label is "soft_lutpair52";
attribute SOFT_HLUTNM of \addr_step_q[5]_i_1\ : label is "soft_lutpair55";
attribute SOFT_HLUTNM of \addr_step_q[6]_i_1\ : label is "soft_lutpair55";
attribute SOFT_HLUTNM of \addr_step_q[7]_i_1\ : label is "soft_lutpair56";
attribute SOFT_HLUTNM of \addr_step_q[8]_i_1\ : label is "soft_lutpair56";
attribute SOFT_HLUTNM of \addr_step_q[9]_i_1\ : label is "soft_lutpair48";
attribute SOFT_HLUTNM of \first_step_q[0]_i_1\ : label is "soft_lutpair47";
attribute SOFT_HLUTNM of \first_step_q[10]_i_1\ : label is "soft_lutpair57";
attribute SOFT_HLUTNM of \first_step_q[11]_i_1\ : label is "soft_lutpair61";
attribute SOFT_HLUTNM of \first_step_q[1]_i_1\ : label is "soft_lutpair47";
attribute SOFT_HLUTNM of \first_step_q[3]_i_1\ : label is "soft_lutpair58";
attribute SOFT_HLUTNM of \first_step_q[4]_i_1\ : label is "soft_lutpair48";
attribute SOFT_HLUTNM of \first_step_q[6]_i_1\ : label is "soft_lutpair57";
attribute SOFT_HLUTNM of \first_step_q[7]_i_1\ : label is "soft_lutpair58";
attribute SOFT_HLUTNM of \first_step_q[8]_i_1\ : label is "soft_lutpair61";
attribute SOFT_HLUTNM of \first_step_q[9]_i_1\ : label is "soft_lutpair60";
attribute SOFT_HLUTNM of \m_axi_awaddr[28]_INST_0\ : label is "soft_lutpair46";
attribute SOFT_HLUTNM of \m_axi_awlock[0]_INST_0\ : label is "soft_lutpair51";
attribute SOFT_HLUTNM of \multiple_id_non_split_i_3__0\ : label is "soft_lutpair51";
attribute SOFT_HLUTNM of \next_mi_addr[11]_i_6\ : label is "soft_lutpair49";
attribute SOFT_HLUTNM of \next_mi_addr[3]_i_6\ : label is "soft_lutpair46";
attribute SOFT_HLUTNM of \pushed_commands[1]_i_1\ : label is "soft_lutpair50";
attribute SOFT_HLUTNM of \pushed_commands[2]_i_1\ : label is "soft_lutpair50";
attribute SOFT_HLUTNM of \pushed_commands[3]_i_2\ : label is "soft_lutpair49";
attribute SOFT_HLUTNM of \size_mask_q[0]_i_1\ : label is "soft_lutpair54";
attribute SOFT_HLUTNM of \size_mask_q[1]_i_1\ : label is "soft_lutpair59";
attribute SOFT_HLUTNM of \size_mask_q[2]_i_1\ : label is "soft_lutpair52";
attribute SOFT_HLUTNM of \size_mask_q[3]_i_1\ : label is "soft_lutpair60";
attribute SOFT_HLUTNM of \size_mask_q[4]_i_1\ : label is "soft_lutpair54";
attribute SOFT_HLUTNM of \size_mask_q[5]_i_1\ : label is "soft_lutpair59";
attribute SOFT_HLUTNM of \size_mask_q[6]_i_1\ : label is "soft_lutpair53";
begin
E(0) <= \^e\(0);
SR(0) <= \^sr\(0);
areset_d(1 downto 0) <= \^areset_d\(1 downto 0);
command_ongoing_reg_0 <= \^command_ongoing_reg_0\;
din(5 downto 0) <= \^din\(5 downto 0);
\length_counter_1_reg_0__s_port_]\ <= \length_counter_1_reg_0__s_net_1\;
m_axi_awaddr(31 downto 0) <= \^m_axi_awaddr\(31 downto 0);
\S_AXI_AADDR_Q_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_awaddr(0),
Q => S_AXI_AADDR_Q(0),
R => \^sr\(0)
);
\S_AXI_AADDR_Q_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_awaddr(10),
Q => S_AXI_AADDR_Q(10),
R => \^sr\(0)
);
\S_AXI_AADDR_Q_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_awaddr(11),
Q => S_AXI_AADDR_Q(11),
R => \^sr\(0)
);
\S_AXI_AADDR_Q_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_awaddr(12),
Q => S_AXI_AADDR_Q(12),
R => \^sr\(0)
);
\S_AXI_AADDR_Q_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_awaddr(13),
Q => S_AXI_AADDR_Q(13),
R => \^sr\(0)
);
\S_AXI_AADDR_Q_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_awaddr(14),
Q => S_AXI_AADDR_Q(14),
R => \^sr\(0)
);
\S_AXI_AADDR_Q_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_awaddr(15),
Q => S_AXI_AADDR_Q(15),
R => \^sr\(0)
);
\S_AXI_AADDR_Q_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_awaddr(16),
Q => S_AXI_AADDR_Q(16),
R => \^sr\(0)
);
\S_AXI_AADDR_Q_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_awaddr(17),
Q => S_AXI_AADDR_Q(17),
R => \^sr\(0)
);
\S_AXI_AADDR_Q_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_awaddr(18),
Q => S_AXI_AADDR_Q(18),
R => \^sr\(0)
);
\S_AXI_AADDR_Q_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_awaddr(19),
Q => S_AXI_AADDR_Q(19),
R => \^sr\(0)
);
\S_AXI_AADDR_Q_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_awaddr(1),
Q => S_AXI_AADDR_Q(1),
R => \^sr\(0)
);
\S_AXI_AADDR_Q_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_awaddr(20),
Q => S_AXI_AADDR_Q(20),
R => \^sr\(0)
);
\S_AXI_AADDR_Q_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_awaddr(21),
Q => S_AXI_AADDR_Q(21),
R => \^sr\(0)
);
\S_AXI_AADDR_Q_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_awaddr(22),
Q => S_AXI_AADDR_Q(22),
R => \^sr\(0)
);
\S_AXI_AADDR_Q_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_awaddr(23),
Q => S_AXI_AADDR_Q(23),
R => \^sr\(0)
);
\S_AXI_AADDR_Q_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_awaddr(24),
Q => S_AXI_AADDR_Q(24),
R => \^sr\(0)
);
\S_AXI_AADDR_Q_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_awaddr(25),
Q => S_AXI_AADDR_Q(25),
R => \^sr\(0)
);
\S_AXI_AADDR_Q_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_awaddr(26),
Q => S_AXI_AADDR_Q(26),
R => \^sr\(0)
);
\S_AXI_AADDR_Q_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_awaddr(27),
Q => S_AXI_AADDR_Q(27),
R => \^sr\(0)
);
\S_AXI_AADDR_Q_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_awaddr(28),
Q => S_AXI_AADDR_Q(28),
R => \^sr\(0)
);
\S_AXI_AADDR_Q_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_awaddr(29),
Q => S_AXI_AADDR_Q(29),
R => \^sr\(0)
);
\S_AXI_AADDR_Q_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_awaddr(2),
Q => S_AXI_AADDR_Q(2),
R => \^sr\(0)
);
\S_AXI_AADDR_Q_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_awaddr(30),
Q => S_AXI_AADDR_Q(30),
R => \^sr\(0)
);
\S_AXI_AADDR_Q_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_awaddr(31),
Q => S_AXI_AADDR_Q(31),
R => \^sr\(0)
);
\S_AXI_AADDR_Q_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_awaddr(3),
Q => S_AXI_AADDR_Q(3),
R => \^sr\(0)
);
\S_AXI_AADDR_Q_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_awaddr(4),
Q => S_AXI_AADDR_Q(4),
R => \^sr\(0)
);
\S_AXI_AADDR_Q_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_awaddr(5),
Q => S_AXI_AADDR_Q(5),
R => \^sr\(0)
);
\S_AXI_AADDR_Q_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_awaddr(6),
Q => S_AXI_AADDR_Q(6),
R => \^sr\(0)
);
\S_AXI_AADDR_Q_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_awaddr(7),
Q => S_AXI_AADDR_Q(7),
R => \^sr\(0)
);
\S_AXI_AADDR_Q_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_awaddr(8),
Q => S_AXI_AADDR_Q(8),
R => \^sr\(0)
);
\S_AXI_AADDR_Q_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_awaddr(9),
Q => S_AXI_AADDR_Q(9),
R => \^sr\(0)
);
\S_AXI_ABURST_Q_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_awburst(0),
Q => m_axi_awburst(0),
R => \^sr\(0)
);
\S_AXI_ABURST_Q_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_awburst(1),
Q => m_axi_awburst(1),
R => \^sr\(0)
);
\S_AXI_ACACHE_Q_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_awcache(0),
Q => m_axi_awcache(0),
R => \^sr\(0)
);
\S_AXI_ACACHE_Q_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_awcache(1),
Q => m_axi_awcache(1),
R => \^sr\(0)
);
\S_AXI_ACACHE_Q_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_awcache(2),
Q => m_axi_awcache(2),
R => \^sr\(0)
);
\S_AXI_ACACHE_Q_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_awcache(3),
Q => m_axi_awcache(3),
R => \^sr\(0)
);
\S_AXI_AID_Q_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_awid(0),
Q => \^din\(4),
R => \^sr\(0)
);
\S_AXI_AID_Q_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_awid(1),
Q => \^din\(5),
R => \^sr\(0)
);
\S_AXI_ALEN_Q_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_awlen(0),
Q => S_AXI_ALEN_Q(0),
R => \^sr\(0)
);
\S_AXI_ALEN_Q_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_awlen(1),
Q => S_AXI_ALEN_Q(1),
R => \^sr\(0)
);
\S_AXI_ALEN_Q_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_awlen(2),
Q => S_AXI_ALEN_Q(2),
R => \^sr\(0)
);
\S_AXI_ALEN_Q_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_awlen(3),
Q => S_AXI_ALEN_Q(3),
R => \^sr\(0)
);
\S_AXI_ALOCK_Q_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_awlock(0),
Q => \S_AXI_ALOCK_Q_reg_n_0_[0]\,
R => \^sr\(0)
);
\S_AXI_APROT_Q_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_awprot(0),
Q => m_axi_awprot(0),
R => \^sr\(0)
);
\S_AXI_APROT_Q_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_awprot(1),
Q => m_axi_awprot(1),
R => \^sr\(0)
);
\S_AXI_APROT_Q_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_awprot(2),
Q => m_axi_awprot(2),
R => \^sr\(0)
);
\S_AXI_AQOS_Q_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_awqos(0),
Q => m_axi_awqos(0),
R => \^sr\(0)
);
\S_AXI_AQOS_Q_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_awqos(1),
Q => m_axi_awqos(1),
R => \^sr\(0)
);
\S_AXI_AQOS_Q_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_awqos(2),
Q => m_axi_awqos(2),
R => \^sr\(0)
);
\S_AXI_AQOS_Q_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_awqos(3),
Q => m_axi_awqos(3),
R => \^sr\(0)
);
S_AXI_AREADY_I_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \USE_B_CHANNEL.cmd_b_queue_n_30\,
Q => \^e\(0),
R => \^sr\(0)
);
\S_AXI_ASIZE_Q_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_awsize(0),
Q => m_axi_awsize(0),
R => \^sr\(0)
);
\S_AXI_ASIZE_Q_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_awsize(1),
Q => m_axi_awsize(1),
R => \^sr\(0)
);
\S_AXI_ASIZE_Q_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_awsize(2),
Q => m_axi_awsize(2),
R => \^sr\(0)
);
\USE_BURSTS.cmd_queue\: entity work.system_auto_pc_1_axi_data_fifo_v2_1_10_axic_fifo
port map (
Q(1 downto 0) => \^din\(5 downto 4),
SR(0) => \^sr\(0),
\S_AXI_ALEN_Q_reg[3]\(3 downto 0) => S_AXI_ALEN_Q(3 downto 0),
\USE_B_CHANNEL.cmd_b_empty_reg\ => \USE_BURSTS.cmd_queue_n_13\,
\USE_B_CHANNEL.cmd_b_empty_reg_0\ => \USE_BURSTS.cmd_queue_n_14\,
aclk => aclk,
aresetn => aresetn,
cmd_b_empty => cmd_b_empty,
cmd_empty => cmd_empty,
cmd_push_block => cmd_push_block,
command_ongoing => command_ongoing,
din(3 downto 0) => \^din\(3 downto 0),
dout(5 downto 0) => dout(5 downto 0),
empty => empty,
first_mi_word => first_mi_word,
full => \inst/full\,
length_counter_1_reg(0) => length_counter_1_reg(0),
\length_counter_1_reg_0__s_port_]\ => \length_counter_1_reg_0__s_net_1\,
m_axi_wready => m_axi_wready,
m_axi_wvalid => m_axi_wvalid,
need_to_split_q => need_to_split_q,
\pushed_commands_reg[3]\(3 downto 0) => \pushed_commands_reg__0\(3 downto 0),
queue_id(1 downto 0) => queue_id(1 downto 0),
s_axi_wready => s_axi_wready,
s_axi_wvalid => s_axi_wvalid,
wr_cmd_ready => wr_cmd_ready,
wr_en => cmd_push
);
\USE_B_CHANNEL.cmd_b_depth[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \USE_B_CHANNEL.cmd_b_depth_reg__0\(0),
O => \USE_B_CHANNEL.cmd_b_depth[0]_i_1_n_0\
);
\USE_B_CHANNEL.cmd_b_depth_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \USE_B_CHANNEL.cmd_b_queue_n_22\,
D => \USE_B_CHANNEL.cmd_b_depth[0]_i_1_n_0\,
Q => \USE_B_CHANNEL.cmd_b_depth_reg__0\(0),
R => \^sr\(0)
);
\USE_B_CHANNEL.cmd_b_depth_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \USE_B_CHANNEL.cmd_b_queue_n_22\,
D => \USE_B_CHANNEL.cmd_b_queue_n_28\,
Q => \USE_B_CHANNEL.cmd_b_depth_reg__0\(1),
R => \^sr\(0)
);
\USE_B_CHANNEL.cmd_b_depth_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \USE_B_CHANNEL.cmd_b_queue_n_22\,
D => \USE_B_CHANNEL.cmd_b_queue_n_27\,
Q => \USE_B_CHANNEL.cmd_b_depth_reg__0\(2),
R => \^sr\(0)
);
\USE_B_CHANNEL.cmd_b_depth_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \USE_B_CHANNEL.cmd_b_queue_n_22\,
D => \USE_B_CHANNEL.cmd_b_queue_n_26\,
Q => \USE_B_CHANNEL.cmd_b_depth_reg__0\(3),
R => \^sr\(0)
);
\USE_B_CHANNEL.cmd_b_depth_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \USE_B_CHANNEL.cmd_b_queue_n_22\,
D => \USE_B_CHANNEL.cmd_b_queue_n_25\,
Q => \USE_B_CHANNEL.cmd_b_depth_reg__0\(4),
R => \^sr\(0)
);
\USE_B_CHANNEL.cmd_b_depth_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \USE_B_CHANNEL.cmd_b_queue_n_22\,
D => \USE_B_CHANNEL.cmd_b_queue_n_24\,
Q => \USE_B_CHANNEL.cmd_b_depth_reg__0\(5),
R => \^sr\(0)
);
\USE_B_CHANNEL.cmd_b_empty_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000004"
)
port map (
I0 => \USE_B_CHANNEL.cmd_b_depth_reg__0\(1),
I1 => \USE_B_CHANNEL.cmd_b_depth_reg__0\(0),
I2 => \USE_B_CHANNEL.cmd_b_depth_reg__0\(5),
I3 => \USE_B_CHANNEL.cmd_b_depth_reg__0\(4),
I4 => \USE_B_CHANNEL.cmd_b_depth_reg__0\(3),
I5 => \USE_B_CHANNEL.cmd_b_depth_reg__0\(2),
O => almost_b_empty
);
\USE_B_CHANNEL.cmd_b_empty_reg\: unisim.vcomponents.FDSE
port map (
C => aclk,
CE => '1',
D => \USE_B_CHANNEL.cmd_b_queue_n_23\,
Q => cmd_b_empty,
S => \^sr\(0)
);
\USE_B_CHANNEL.cmd_b_queue\: entity work.\system_auto_pc_1_axi_data_fifo_v2_1_10_axic_fifo__parameterized0\
port map (
D(4) => \USE_B_CHANNEL.cmd_b_queue_n_7\,
D(3) => \USE_B_CHANNEL.cmd_b_queue_n_8\,
D(2) => \USE_B_CHANNEL.cmd_b_queue_n_9\,
D(1) => \USE_B_CHANNEL.cmd_b_queue_n_10\,
D(0) => \USE_B_CHANNEL.cmd_b_queue_n_11\,
E(0) => \USE_B_CHANNEL.cmd_b_queue_n_13\,
Q(5 downto 0) => \cmd_depth_reg__0\(5 downto 0),
SR(0) => \^sr\(0),
\S_AXI_AID_Q_reg[0]\ => multiple_id_non_split_i_2_n_0,
\S_AXI_AID_Q_reg[1]\(1 downto 0) => \^din\(5 downto 4),
S_AXI_AREADY_I_reg => \USE_B_CHANNEL.cmd_b_queue_n_30\,
S_AXI_AREADY_I_reg_0 => \^e\(0),
\USE_B_CHANNEL.cmd_b_depth_reg[5]\(0) => \USE_B_CHANNEL.cmd_b_queue_n_22\,
\USE_B_CHANNEL.cmd_b_depth_reg[5]_0\(4) => \USE_B_CHANNEL.cmd_b_queue_n_24\,
\USE_B_CHANNEL.cmd_b_depth_reg[5]_0\(3) => \USE_B_CHANNEL.cmd_b_queue_n_25\,
\USE_B_CHANNEL.cmd_b_depth_reg[5]_0\(2) => \USE_B_CHANNEL.cmd_b_queue_n_26\,
\USE_B_CHANNEL.cmd_b_depth_reg[5]_0\(1) => \USE_B_CHANNEL.cmd_b_queue_n_27\,
\USE_B_CHANNEL.cmd_b_depth_reg[5]_0\(0) => \USE_B_CHANNEL.cmd_b_queue_n_28\,
\USE_B_CHANNEL.cmd_b_depth_reg[5]_1\(5 downto 0) => \USE_B_CHANNEL.cmd_b_depth_reg__0\(5 downto 0),
\USE_B_CHANNEL.cmd_b_empty_reg\ => \USE_B_CHANNEL.cmd_b_queue_n_23\,
access_is_incr_q => access_is_incr_q,
aclk => aclk,
almost_b_empty => almost_b_empty,
almost_empty => almost_empty,
areset_d(0) => \^areset_d\(1),
\areset_d_reg[0]\ => \^areset_d\(0),
\areset_d_reg[1]\ => \^command_ongoing_reg_0\,
aresetn => aresetn,
cmd_b_empty => cmd_b_empty,
cmd_b_push_block => cmd_b_push_block,
cmd_b_push_block_reg => \USE_B_CHANNEL.cmd_b_queue_n_21\,
cmd_empty => cmd_empty,
cmd_empty_reg => \USE_B_CHANNEL.cmd_b_queue_n_18\,
cmd_empty_reg_0 => \USE_BURSTS.cmd_queue_n_13\,
cmd_push_block => cmd_push_block,
cmd_push_block_reg => \USE_B_CHANNEL.cmd_b_queue_n_16\,
cmd_push_block_reg_0 => \USE_BURSTS.cmd_queue_n_14\,
command_ongoing => command_ongoing,
command_ongoing_reg => \USE_B_CHANNEL.cmd_b_queue_n_31\,
din(0) => \USE_B_CHANNEL.cmd_b_queue_n_6\,
first_mi_word_reg(4 downto 0) => first_mi_word_reg(4 downto 0),
full => \inst/full\,
\goreg_dm.dout_i_reg[4]\ => \goreg_dm.dout_i_reg[4]\,
\gpregsm1.user_valid_reg\ => \gpregsm1.user_valid_reg\,
incr_need_to_split_q_reg => \multiple_id_non_split_i_3__0_n_0\,
m_axi_awready => m_axi_awready,
m_axi_awvalid => m_axi_awvalid,
m_axi_bvalid => m_axi_bvalid,
multiple_id_non_split => multiple_id_non_split,
multiple_id_non_split_reg => \USE_B_CHANNEL.cmd_b_queue_n_14\,
need_to_split_q => need_to_split_q,
\num_transactions_q_reg[3]\(3 downto 0) => num_transactions_q(3 downto 0),
\pushed_commands_reg[3]\(3 downto 0) => \pushed_commands_reg__0\(3 downto 0),
pushed_new_cmd => pushed_new_cmd,
queue_id(1 downto 0) => queue_id(1 downto 0),
\queue_id_reg[0]\ => \USE_B_CHANNEL.cmd_b_queue_n_19\,
\queue_id_reg[1]\ => \USE_B_CHANNEL.cmd_b_queue_n_20\,
s_axi_awvalid => s_axi_awvalid,
s_axi_bready => s_axi_bready,
split_in_progress_reg => \USE_B_CHANNEL.cmd_b_queue_n_15\,
split_in_progress_reg_0 => split_in_progress_reg_n_0,
wr_cmd_b_ready => wr_cmd_b_ready,
wr_cmd_ready => wr_cmd_ready,
wr_en => cmd_push
);
access_is_incr_q_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_awburst(0),
I1 => s_axi_awburst(1),
O => access_is_incr
);
access_is_incr_q_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => access_is_incr,
Q => access_is_incr_q,
R => \^sr\(0)
);
\addr_step_q[10]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => s_axi_awsize(1),
I1 => s_axi_awsize(2),
I2 => s_axi_awsize(0),
O => addr_step(10)
);
\addr_step_q[11]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => s_axi_awsize(1),
I1 => s_axi_awsize(0),
I2 => s_axi_awsize(2),
O => addr_step(11)
);
\addr_step_q[5]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => s_axi_awsize(2),
I1 => s_axi_awsize(0),
I2 => s_axi_awsize(1),
O => addr_step(5)
);
\addr_step_q[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => s_axi_awsize(0),
I1 => s_axi_awsize(1),
I2 => s_axi_awsize(2),
O => addr_step(6)
);
\addr_step_q[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => s_axi_awsize(1),
I1 => s_axi_awsize(0),
I2 => s_axi_awsize(2),
O => addr_step(7)
);
\addr_step_q[8]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => s_axi_awsize(0),
I1 => s_axi_awsize(2),
I2 => s_axi_awsize(1),
O => addr_step(8)
);
\addr_step_q[9]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => s_axi_awsize(2),
I1 => s_axi_awsize(0),
I2 => s_axi_awsize(1),
O => addr_step(9)
);
\addr_step_q_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => addr_step(10),
Q => addr_step_q(10),
R => \^sr\(0)
);
\addr_step_q_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => addr_step(11),
Q => addr_step_q(11),
R => \^sr\(0)
);
\addr_step_q_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => addr_step(5),
Q => addr_step_q(5),
R => \^sr\(0)
);
\addr_step_q_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => addr_step(6),
Q => addr_step_q(6),
R => \^sr\(0)
);
\addr_step_q_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => addr_step(7),
Q => addr_step_q(7),
R => \^sr\(0)
);
\addr_step_q_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => addr_step(8),
Q => addr_step_q(8),
R => \^sr\(0)
);
\addr_step_q_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => addr_step(9),
Q => addr_step_q(9),
R => \^sr\(0)
);
\areset_d_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \^sr\(0),
Q => \^areset_d\(0),
R => '0'
);
\areset_d_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \^areset_d\(0),
Q => \^areset_d\(1),
R => '0'
);
cmd_b_push_block_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \USE_B_CHANNEL.cmd_b_queue_n_21\,
Q => cmd_b_push_block,
R => '0'
);
\cmd_depth[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cmd_depth_reg__0\(0),
O => \cmd_depth[0]_i_1_n_0\
);
\cmd_depth_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \USE_B_CHANNEL.cmd_b_queue_n_13\,
D => \cmd_depth[0]_i_1_n_0\,
Q => \cmd_depth_reg__0\(0),
R => \^sr\(0)
);
\cmd_depth_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \USE_B_CHANNEL.cmd_b_queue_n_13\,
D => \USE_B_CHANNEL.cmd_b_queue_n_11\,
Q => \cmd_depth_reg__0\(1),
R => \^sr\(0)
);
\cmd_depth_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \USE_B_CHANNEL.cmd_b_queue_n_13\,
D => \USE_B_CHANNEL.cmd_b_queue_n_10\,
Q => \cmd_depth_reg__0\(2),
R => \^sr\(0)
);
\cmd_depth_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \USE_B_CHANNEL.cmd_b_queue_n_13\,
D => \USE_B_CHANNEL.cmd_b_queue_n_9\,
Q => \cmd_depth_reg__0\(3),
R => \^sr\(0)
);
\cmd_depth_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \USE_B_CHANNEL.cmd_b_queue_n_13\,
D => \USE_B_CHANNEL.cmd_b_queue_n_8\,
Q => \cmd_depth_reg__0\(4),
R => \^sr\(0)
);
\cmd_depth_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \USE_B_CHANNEL.cmd_b_queue_n_13\,
D => \USE_B_CHANNEL.cmd_b_queue_n_7\,
Q => \cmd_depth_reg__0\(5),
R => \^sr\(0)
);
cmd_empty_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000100000000"
)
port map (
I0 => \cmd_depth_reg__0\(2),
I1 => \cmd_depth_reg__0\(3),
I2 => \cmd_depth_reg__0\(5),
I3 => \cmd_depth_reg__0\(4),
I4 => \cmd_depth_reg__0\(1),
I5 => \cmd_depth_reg__0\(0),
O => almost_empty
);
cmd_empty_reg: unisim.vcomponents.FDSE
port map (
C => aclk,
CE => '1',
D => \USE_B_CHANNEL.cmd_b_queue_n_18\,
Q => cmd_empty,
S => \^sr\(0)
);
cmd_push_block_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \USE_B_CHANNEL.cmd_b_queue_n_16\,
Q => cmd_push_block,
R => '0'
);
command_ongoing_i_2: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^areset_d\(1),
I1 => \^areset_d\(0),
O => \^command_ongoing_reg_0\
);
command_ongoing_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \USE_B_CHANNEL.cmd_b_queue_n_31\,
Q => command_ongoing,
R => \^sr\(0)
);
\first_step_q[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => s_axi_awsize(1),
I1 => s_axi_awsize(0),
I2 => s_axi_awlen(0),
I3 => s_axi_awsize(2),
O => \first_step_q[0]_i_1_n_0\
);
\first_step_q[10]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => s_axi_awsize(2),
I1 => \first_step_q[10]_i_2_n_0\,
O => first_step(10)
);
\first_step_q[10]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"2AAA800080000000"
)
port map (
I0 => s_axi_awsize(1),
I1 => s_axi_awlen(2),
I2 => s_axi_awlen(0),
I3 => s_axi_awlen(1),
I4 => s_axi_awlen(3),
I5 => s_axi_awsize(0),
O => \first_step_q[10]_i_2_n_0\
);
\first_step_q[11]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => s_axi_awsize(2),
I1 => \first_step_q[11]_i_2_n_0\,
O => first_step(11)
);
\first_step_q[11]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"8000000000000000"
)
port map (
I0 => s_axi_awsize(1),
I1 => s_axi_awlen(3),
I2 => s_axi_awlen(1),
I3 => s_axi_awlen(0),
I4 => s_axi_awlen(2),
I5 => s_axi_awsize(0),
O => \first_step_q[11]_i_2_n_0\
);
\first_step_q[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000514"
)
port map (
I0 => s_axi_awsize(1),
I1 => s_axi_awsize(0),
I2 => s_axi_awlen(0),
I3 => s_axi_awlen(1),
I4 => s_axi_awsize(2),
O => \first_step_q[1]_i_1_n_0\
);
\first_step_q[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000000F3C6A"
)
port map (
I0 => s_axi_awlen(2),
I1 => s_axi_awlen(1),
I2 => s_axi_awlen(0),
I3 => s_axi_awsize(0),
I4 => s_axi_awsize(1),
I5 => s_axi_awsize(2),
O => \first_step_q[2]_i_1_n_0\
);
\first_step_q[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \first_step_q[7]_i_2_n_0\,
I1 => s_axi_awsize(2),
O => \first_step_q[3]_i_1_n_0\
);
\first_step_q[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"01FF0100"
)
port map (
I0 => s_axi_awlen(0),
I1 => s_axi_awsize(0),
I2 => s_axi_awsize(1),
I3 => s_axi_awsize(2),
I4 => \first_step_q[8]_i_2_n_0\,
O => first_step(4)
);
\first_step_q[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0036FFFF00360000"
)
port map (
I0 => s_axi_awlen(1),
I1 => s_axi_awlen(0),
I2 => s_axi_awsize(0),
I3 => s_axi_awsize(1),
I4 => s_axi_awsize(2),
I5 => \first_step_q[9]_i_2_n_0\,
O => first_step(5)
);
\first_step_q[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \first_step_q[6]_i_2_n_0\,
I1 => s_axi_awsize(2),
I2 => \first_step_q[10]_i_2_n_0\,
O => first_step(6)
);
\first_step_q[6]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"07531642"
)
port map (
I0 => s_axi_awsize(1),
I1 => s_axi_awsize(0),
I2 => s_axi_awlen(0),
I3 => s_axi_awlen(1),
I4 => s_axi_awlen(2),
O => \first_step_q[6]_i_2_n_0\
);
\first_step_q[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \first_step_q[7]_i_2_n_0\,
I1 => s_axi_awsize(2),
I2 => \first_step_q[11]_i_2_n_0\,
O => first_step(7)
);
\first_step_q[7]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"07FD53B916EC42A8"
)
port map (
I0 => s_axi_awsize(1),
I1 => s_axi_awsize(0),
I2 => s_axi_awlen(1),
I3 => s_axi_awlen(0),
I4 => s_axi_awlen(2),
I5 => s_axi_awlen(3),
O => \first_step_q[7]_i_2_n_0\
);
\first_step_q[8]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => s_axi_awsize(2),
I1 => \first_step_q[8]_i_2_n_0\,
O => first_step(8)
);
\first_step_q[8]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"14EAEA6262C8C840"
)
port map (
I0 => s_axi_awsize(1),
I1 => s_axi_awsize(0),
I2 => s_axi_awlen(3),
I3 => s_axi_awlen(1),
I4 => s_axi_awlen(0),
I5 => s_axi_awlen(2),
O => \first_step_q[8]_i_2_n_0\
);
\first_step_q[9]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => s_axi_awsize(2),
I1 => \first_step_q[9]_i_2_n_0\,
O => first_step(9)
);
\first_step_q[9]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"4AA2A2A228808080"
)
port map (
I0 => s_axi_awsize(1),
I1 => s_axi_awsize(0),
I2 => s_axi_awlen(2),
I3 => s_axi_awlen(0),
I4 => s_axi_awlen(1),
I5 => s_axi_awlen(3),
O => \first_step_q[9]_i_2_n_0\
);
\first_step_q_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => \first_step_q[0]_i_1_n_0\,
Q => first_step_q(0),
R => \^sr\(0)
);
\first_step_q_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => first_step(10),
Q => first_step_q(10),
R => \^sr\(0)
);
\first_step_q_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => first_step(11),
Q => first_step_q(11),
R => \^sr\(0)
);
\first_step_q_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => \first_step_q[1]_i_1_n_0\,
Q => first_step_q(1),
R => \^sr\(0)
);
\first_step_q_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => \first_step_q[2]_i_1_n_0\,
Q => first_step_q(2),
R => \^sr\(0)
);
\first_step_q_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => \first_step_q[3]_i_1_n_0\,
Q => first_step_q(3),
R => \^sr\(0)
);
\first_step_q_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => first_step(4),
Q => first_step_q(4),
R => \^sr\(0)
);
\first_step_q_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => first_step(5),
Q => first_step_q(5),
R => \^sr\(0)
);
\first_step_q_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => first_step(6),
Q => first_step_q(6),
R => \^sr\(0)
);
\first_step_q_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => first_step(7),
Q => first_step_q(7),
R => \^sr\(0)
);
\first_step_q_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => first_step(8),
Q => first_step_q(8),
R => \^sr\(0)
);
\first_step_q_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => first_step(9),
Q => first_step_q(9),
R => \^sr\(0)
);
incr_need_to_split: unisim.vcomponents.LUT6
generic map(
INIT => X"4444444444444440"
)
port map (
I0 => s_axi_awburst(1),
I1 => s_axi_awburst(0),
I2 => s_axi_awlen(5),
I3 => s_axi_awlen(4),
I4 => s_axi_awlen(6),
I5 => s_axi_awlen(7),
O => \incr_need_to_split__0\
);
incr_need_to_split_q_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => \incr_need_to_split__0\,
Q => need_to_split_q,
R => \^sr\(0)
);
\m_axi_awaddr[0]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"8FFF8000"
)
port map (
I0 => size_mask_q(0),
I1 => next_mi_addr(0),
I2 => access_is_incr_q,
I3 => split_ongoing,
I4 => S_AXI_AADDR_Q(0),
O => \^m_axi_awaddr\(0)
);
\m_axi_awaddr[10]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => S_AXI_AADDR_Q(10),
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(10),
O => \^m_axi_awaddr\(10)
);
\m_axi_awaddr[11]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => S_AXI_AADDR_Q(11),
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(11),
O => \^m_axi_awaddr\(11)
);
\m_axi_awaddr[12]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => S_AXI_AADDR_Q(12),
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(12),
O => \^m_axi_awaddr\(12)
);
\m_axi_awaddr[13]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => S_AXI_AADDR_Q(13),
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(13),
O => \^m_axi_awaddr\(13)
);
\m_axi_awaddr[14]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => S_AXI_AADDR_Q(14),
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(14),
O => \^m_axi_awaddr\(14)
);
\m_axi_awaddr[15]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => S_AXI_AADDR_Q(15),
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(15),
O => \^m_axi_awaddr\(15)
);
\m_axi_awaddr[16]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => S_AXI_AADDR_Q(16),
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(16),
O => \^m_axi_awaddr\(16)
);
\m_axi_awaddr[17]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => S_AXI_AADDR_Q(17),
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(17),
O => \^m_axi_awaddr\(17)
);
\m_axi_awaddr[18]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => S_AXI_AADDR_Q(18),
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(18),
O => \^m_axi_awaddr\(18)
);
\m_axi_awaddr[19]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => S_AXI_AADDR_Q(19),
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(19),
O => \^m_axi_awaddr\(19)
);
\m_axi_awaddr[1]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"8FFF8000"
)
port map (
I0 => size_mask_q(1),
I1 => next_mi_addr(1),
I2 => access_is_incr_q,
I3 => split_ongoing,
I4 => S_AXI_AADDR_Q(1),
O => \^m_axi_awaddr\(1)
);
\m_axi_awaddr[20]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => S_AXI_AADDR_Q(20),
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(20),
O => \^m_axi_awaddr\(20)
);
\m_axi_awaddr[21]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => S_AXI_AADDR_Q(21),
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(21),
O => \^m_axi_awaddr\(21)
);
\m_axi_awaddr[22]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => S_AXI_AADDR_Q(22),
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(22),
O => \^m_axi_awaddr\(22)
);
\m_axi_awaddr[23]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => S_AXI_AADDR_Q(23),
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(23),
O => \^m_axi_awaddr\(23)
);
\m_axi_awaddr[24]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => S_AXI_AADDR_Q(24),
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(24),
O => \^m_axi_awaddr\(24)
);
\m_axi_awaddr[25]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => S_AXI_AADDR_Q(25),
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(25),
O => \^m_axi_awaddr\(25)
);
\m_axi_awaddr[26]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => S_AXI_AADDR_Q(26),
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(26),
O => \^m_axi_awaddr\(26)
);
\m_axi_awaddr[27]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => S_AXI_AADDR_Q(27),
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(27),
O => \^m_axi_awaddr\(27)
);
\m_axi_awaddr[28]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => S_AXI_AADDR_Q(28),
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(28),
O => \^m_axi_awaddr\(28)
);
\m_axi_awaddr[29]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => S_AXI_AADDR_Q(29),
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(29),
O => \^m_axi_awaddr\(29)
);
\m_axi_awaddr[2]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"8FFF8000"
)
port map (
I0 => size_mask_q(2),
I1 => next_mi_addr(2),
I2 => access_is_incr_q,
I3 => split_ongoing,
I4 => S_AXI_AADDR_Q(2),
O => \^m_axi_awaddr\(2)
);
\m_axi_awaddr[30]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => S_AXI_AADDR_Q(30),
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(30),
O => \^m_axi_awaddr\(30)
);
\m_axi_awaddr[31]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => S_AXI_AADDR_Q(31),
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(31),
O => \^m_axi_awaddr\(31)
);
\m_axi_awaddr[3]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"8FFF8000"
)
port map (
I0 => size_mask_q(3),
I1 => next_mi_addr(3),
I2 => access_is_incr_q,
I3 => split_ongoing,
I4 => S_AXI_AADDR_Q(3),
O => \^m_axi_awaddr\(3)
);
\m_axi_awaddr[4]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"8FFF8000"
)
port map (
I0 => size_mask_q(4),
I1 => next_mi_addr(4),
I2 => access_is_incr_q,
I3 => split_ongoing,
I4 => S_AXI_AADDR_Q(4),
O => \^m_axi_awaddr\(4)
);
\m_axi_awaddr[5]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"8FFF8000"
)
port map (
I0 => size_mask_q(5),
I1 => next_mi_addr(5),
I2 => access_is_incr_q,
I3 => split_ongoing,
I4 => S_AXI_AADDR_Q(5),
O => \^m_axi_awaddr\(5)
);
\m_axi_awaddr[6]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"8FFF8000"
)
port map (
I0 => size_mask_q(6),
I1 => next_mi_addr(6),
I2 => access_is_incr_q,
I3 => split_ongoing,
I4 => S_AXI_AADDR_Q(6),
O => \^m_axi_awaddr\(6)
);
\m_axi_awaddr[7]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => S_AXI_AADDR_Q(7),
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(7),
O => \^m_axi_awaddr\(7)
);
\m_axi_awaddr[8]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => S_AXI_AADDR_Q(8),
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(8),
O => \^m_axi_awaddr\(8)
);
\m_axi_awaddr[9]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => S_AXI_AADDR_Q(9),
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(9),
O => \^m_axi_awaddr\(9)
);
\m_axi_awlock[0]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \S_AXI_ALOCK_Q_reg_n_0_[0]\,
I1 => need_to_split_q,
O => m_axi_awlock(0)
);
multiple_id_non_split_i_2: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^din\(4),
I1 => queue_id(0),
I2 => \^din\(5),
I3 => queue_id(1),
O => multiple_id_non_split_i_2_n_0
);
\multiple_id_non_split_i_3__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"15"
)
port map (
I0 => need_to_split_q,
I1 => \USE_BURSTS.cmd_queue_n_13\,
I2 => split_in_progress_reg_n_0,
O => \multiple_id_non_split_i_3__0_n_0\
);
multiple_id_non_split_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \USE_B_CHANNEL.cmd_b_queue_n_14\,
Q => multiple_id_non_split,
R => '0'
);
\next_mi_addr[11]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"56A6"
)
port map (
I0 => \^m_axi_awaddr\(11),
I1 => addr_step_q(11),
I2 => \next_mi_addr[11]_i_6_n_0\,
I3 => first_step_q(11),
O => \next_mi_addr[11]_i_2_n_0\
);
\next_mi_addr[11]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"56A6"
)
port map (
I0 => \^m_axi_awaddr\(10),
I1 => addr_step_q(10),
I2 => \next_mi_addr[11]_i_6_n_0\,
I3 => first_step_q(10),
O => \next_mi_addr[11]_i_3_n_0\
);
\next_mi_addr[11]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"56A6"
)
port map (
I0 => \^m_axi_awaddr\(9),
I1 => addr_step_q(9),
I2 => \next_mi_addr[11]_i_6_n_0\,
I3 => first_step_q(9),
O => \next_mi_addr[11]_i_4_n_0\
);
\next_mi_addr[11]_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"56A6"
)
port map (
I0 => \^m_axi_awaddr\(8),
I1 => addr_step_q(8),
I2 => \next_mi_addr[11]_i_6_n_0\,
I3 => first_step_q(8),
O => \next_mi_addr[11]_i_5_n_0\
);
\next_mi_addr[11]_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => \pushed_commands_reg__0\(1),
I1 => \pushed_commands_reg__0\(0),
I2 => \pushed_commands_reg__0\(3),
I3 => \pushed_commands_reg__0\(2),
O => \next_mi_addr[11]_i_6_n_0\
);
\next_mi_addr[15]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => S_AXI_AADDR_Q(15),
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(15),
O => \next_mi_addr[15]_i_2_n_0\
);
\next_mi_addr[15]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => S_AXI_AADDR_Q(14),
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(14),
O => \next_mi_addr[15]_i_3_n_0\
);
\next_mi_addr[15]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => S_AXI_AADDR_Q(13),
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(13),
O => \next_mi_addr[15]_i_4_n_0\
);
\next_mi_addr[15]_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => S_AXI_AADDR_Q(12),
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(12),
O => \next_mi_addr[15]_i_5_n_0\
);
\next_mi_addr[15]_i_6\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => S_AXI_AADDR_Q(15),
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(15),
O => \next_mi_addr[15]_i_6_n_0\
);
\next_mi_addr[15]_i_7\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => S_AXI_AADDR_Q(14),
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(14),
O => \next_mi_addr[15]_i_7_n_0\
);
\next_mi_addr[15]_i_8\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => S_AXI_AADDR_Q(13),
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(13),
O => \next_mi_addr[15]_i_8_n_0\
);
\next_mi_addr[15]_i_9\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => S_AXI_AADDR_Q(12),
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(12),
O => \next_mi_addr[15]_i_9_n_0\
);
\next_mi_addr[19]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => S_AXI_AADDR_Q(19),
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(19),
O => \next_mi_addr[19]_i_2_n_0\
);
\next_mi_addr[19]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => S_AXI_AADDR_Q(18),
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(18),
O => \next_mi_addr[19]_i_3_n_0\
);
\next_mi_addr[19]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => S_AXI_AADDR_Q(17),
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(17),
O => \next_mi_addr[19]_i_4_n_0\
);
\next_mi_addr[19]_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => S_AXI_AADDR_Q(16),
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(16),
O => \next_mi_addr[19]_i_5_n_0\
);
\next_mi_addr[23]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => S_AXI_AADDR_Q(23),
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(23),
O => \next_mi_addr[23]_i_2_n_0\
);
\next_mi_addr[23]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => S_AXI_AADDR_Q(22),
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(22),
O => \next_mi_addr[23]_i_3_n_0\
);
\next_mi_addr[23]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => S_AXI_AADDR_Q(21),
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(21),
O => \next_mi_addr[23]_i_4_n_0\
);
\next_mi_addr[23]_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => S_AXI_AADDR_Q(20),
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(20),
O => \next_mi_addr[23]_i_5_n_0\
);
\next_mi_addr[27]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => S_AXI_AADDR_Q(27),
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(27),
O => \next_mi_addr[27]_i_2_n_0\
);
\next_mi_addr[27]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => S_AXI_AADDR_Q(26),
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(26),
O => \next_mi_addr[27]_i_3_n_0\
);
\next_mi_addr[27]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => S_AXI_AADDR_Q(25),
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(25),
O => \next_mi_addr[27]_i_4_n_0\
);
\next_mi_addr[27]_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => S_AXI_AADDR_Q(24),
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(24),
O => \next_mi_addr[27]_i_5_n_0\
);
\next_mi_addr[31]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => S_AXI_AADDR_Q(31),
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(31),
O => \next_mi_addr[31]_i_2_n_0\
);
\next_mi_addr[31]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => S_AXI_AADDR_Q(30),
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(30),
O => \next_mi_addr[31]_i_3_n_0\
);
\next_mi_addr[31]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => S_AXI_AADDR_Q(29),
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(29),
O => \next_mi_addr[31]_i_4_n_0\
);
\next_mi_addr[31]_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => S_AXI_AADDR_Q(28),
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(28),
O => \next_mi_addr[31]_i_5_n_0\
);
\next_mi_addr[3]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"1DDDE222E222E222"
)
port map (
I0 => S_AXI_AADDR_Q(3),
I1 => \next_mi_addr[3]_i_6_n_0\,
I2 => next_mi_addr(3),
I3 => size_mask_q(3),
I4 => \next_mi_addr[11]_i_6_n_0\,
I5 => first_step_q(3),
O => \next_mi_addr[3]_i_2_n_0\
);
\next_mi_addr[3]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"1DDDE222E222E222"
)
port map (
I0 => S_AXI_AADDR_Q(2),
I1 => \next_mi_addr[3]_i_6_n_0\,
I2 => next_mi_addr(2),
I3 => size_mask_q(2),
I4 => \next_mi_addr[11]_i_6_n_0\,
I5 => first_step_q(2),
O => \next_mi_addr[3]_i_3_n_0\
);
\next_mi_addr[3]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"1DDDE222E222E222"
)
port map (
I0 => S_AXI_AADDR_Q(1),
I1 => \next_mi_addr[3]_i_6_n_0\,
I2 => next_mi_addr(1),
I3 => size_mask_q(1),
I4 => \next_mi_addr[11]_i_6_n_0\,
I5 => first_step_q(1),
O => \next_mi_addr[3]_i_4_n_0\
);
\next_mi_addr[3]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"1DDDE222E222E222"
)
port map (
I0 => S_AXI_AADDR_Q(0),
I1 => \next_mi_addr[3]_i_6_n_0\,
I2 => next_mi_addr(0),
I3 => size_mask_q(0),
I4 => \next_mi_addr[11]_i_6_n_0\,
I5 => first_step_q(0),
O => \next_mi_addr[3]_i_5_n_0\
);
\next_mi_addr[3]_i_6\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => access_is_incr_q,
I1 => split_ongoing,
O => \next_mi_addr[3]_i_6_n_0\
);
\next_mi_addr[7]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"56A6"
)
port map (
I0 => \^m_axi_awaddr\(7),
I1 => addr_step_q(7),
I2 => \next_mi_addr[11]_i_6_n_0\,
I3 => first_step_q(7),
O => \next_mi_addr[7]_i_2_n_0\
);
\next_mi_addr[7]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"56A6"
)
port map (
I0 => \^m_axi_awaddr\(6),
I1 => addr_step_q(6),
I2 => \next_mi_addr[11]_i_6_n_0\,
I3 => first_step_q(6),
O => \next_mi_addr[7]_i_3_n_0\
);
\next_mi_addr[7]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"56A6"
)
port map (
I0 => \^m_axi_awaddr\(5),
I1 => addr_step_q(5),
I2 => \next_mi_addr[11]_i_6_n_0\,
I3 => first_step_q(5),
O => \next_mi_addr[7]_i_4_n_0\
);
\next_mi_addr[7]_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"56A6"
)
port map (
I0 => \^m_axi_awaddr\(4),
I1 => size_mask_q(0),
I2 => \next_mi_addr[11]_i_6_n_0\,
I3 => first_step_q(4),
O => \next_mi_addr[7]_i_5_n_0\
);
\next_mi_addr_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => pushed_new_cmd,
D => \next_mi_addr_reg[3]_i_1_n_7\,
Q => next_mi_addr(0),
R => \^sr\(0)
);
\next_mi_addr_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => pushed_new_cmd,
D => \next_mi_addr_reg[11]_i_1_n_5\,
Q => next_mi_addr(10),
R => \^sr\(0)
);
\next_mi_addr_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => pushed_new_cmd,
D => \next_mi_addr_reg[11]_i_1_n_4\,
Q => next_mi_addr(11),
R => \^sr\(0)
);
\next_mi_addr_reg[11]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \next_mi_addr_reg[7]_i_1_n_0\,
CO(3) => \next_mi_addr_reg[11]_i_1_n_0\,
CO(2) => \next_mi_addr_reg[11]_i_1_n_1\,
CO(1) => \next_mi_addr_reg[11]_i_1_n_2\,
CO(0) => \next_mi_addr_reg[11]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => \^m_axi_awaddr\(11 downto 8),
O(3) => \next_mi_addr_reg[11]_i_1_n_4\,
O(2) => \next_mi_addr_reg[11]_i_1_n_5\,
O(1) => \next_mi_addr_reg[11]_i_1_n_6\,
O(0) => \next_mi_addr_reg[11]_i_1_n_7\,
S(3) => \next_mi_addr[11]_i_2_n_0\,
S(2) => \next_mi_addr[11]_i_3_n_0\,
S(1) => \next_mi_addr[11]_i_4_n_0\,
S(0) => \next_mi_addr[11]_i_5_n_0\
);
\next_mi_addr_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => pushed_new_cmd,
D => \next_mi_addr_reg[15]_i_1_n_7\,
Q => next_mi_addr(12),
R => \^sr\(0)
);
\next_mi_addr_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => pushed_new_cmd,
D => \next_mi_addr_reg[15]_i_1_n_6\,
Q => next_mi_addr(13),
R => \^sr\(0)
);
\next_mi_addr_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => pushed_new_cmd,
D => \next_mi_addr_reg[15]_i_1_n_5\,
Q => next_mi_addr(14),
R => \^sr\(0)
);
\next_mi_addr_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => pushed_new_cmd,
D => \next_mi_addr_reg[15]_i_1_n_4\,
Q => next_mi_addr(15),
R => \^sr\(0)
);
\next_mi_addr_reg[15]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \next_mi_addr_reg[11]_i_1_n_0\,
CO(3) => \next_mi_addr_reg[15]_i_1_n_0\,
CO(2) => \next_mi_addr_reg[15]_i_1_n_1\,
CO(1) => \next_mi_addr_reg[15]_i_1_n_2\,
CO(0) => \next_mi_addr_reg[15]_i_1_n_3\,
CYINIT => '0',
DI(3) => \next_mi_addr[15]_i_2_n_0\,
DI(2) => \next_mi_addr[15]_i_3_n_0\,
DI(1) => \next_mi_addr[15]_i_4_n_0\,
DI(0) => \next_mi_addr[15]_i_5_n_0\,
O(3) => \next_mi_addr_reg[15]_i_1_n_4\,
O(2) => \next_mi_addr_reg[15]_i_1_n_5\,
O(1) => \next_mi_addr_reg[15]_i_1_n_6\,
O(0) => \next_mi_addr_reg[15]_i_1_n_7\,
S(3) => \next_mi_addr[15]_i_6_n_0\,
S(2) => \next_mi_addr[15]_i_7_n_0\,
S(1) => \next_mi_addr[15]_i_8_n_0\,
S(0) => \next_mi_addr[15]_i_9_n_0\
);
\next_mi_addr_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => pushed_new_cmd,
D => \next_mi_addr_reg[19]_i_1_n_7\,
Q => next_mi_addr(16),
R => \^sr\(0)
);
\next_mi_addr_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => pushed_new_cmd,
D => \next_mi_addr_reg[19]_i_1_n_6\,
Q => next_mi_addr(17),
R => \^sr\(0)
);
\next_mi_addr_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => pushed_new_cmd,
D => \next_mi_addr_reg[19]_i_1_n_5\,
Q => next_mi_addr(18),
R => \^sr\(0)
);
\next_mi_addr_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => pushed_new_cmd,
D => \next_mi_addr_reg[19]_i_1_n_4\,
Q => next_mi_addr(19),
R => \^sr\(0)
);
\next_mi_addr_reg[19]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \next_mi_addr_reg[15]_i_1_n_0\,
CO(3) => \next_mi_addr_reg[19]_i_1_n_0\,
CO(2) => \next_mi_addr_reg[19]_i_1_n_1\,
CO(1) => \next_mi_addr_reg[19]_i_1_n_2\,
CO(0) => \next_mi_addr_reg[19]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \next_mi_addr_reg[19]_i_1_n_4\,
O(2) => \next_mi_addr_reg[19]_i_1_n_5\,
O(1) => \next_mi_addr_reg[19]_i_1_n_6\,
O(0) => \next_mi_addr_reg[19]_i_1_n_7\,
S(3) => \next_mi_addr[19]_i_2_n_0\,
S(2) => \next_mi_addr[19]_i_3_n_0\,
S(1) => \next_mi_addr[19]_i_4_n_0\,
S(0) => \next_mi_addr[19]_i_5_n_0\
);
\next_mi_addr_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => pushed_new_cmd,
D => \next_mi_addr_reg[3]_i_1_n_6\,
Q => next_mi_addr(1),
R => \^sr\(0)
);
\next_mi_addr_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => pushed_new_cmd,
D => \next_mi_addr_reg[23]_i_1_n_7\,
Q => next_mi_addr(20),
R => \^sr\(0)
);
\next_mi_addr_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => pushed_new_cmd,
D => \next_mi_addr_reg[23]_i_1_n_6\,
Q => next_mi_addr(21),
R => \^sr\(0)
);
\next_mi_addr_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => pushed_new_cmd,
D => \next_mi_addr_reg[23]_i_1_n_5\,
Q => next_mi_addr(22),
R => \^sr\(0)
);
\next_mi_addr_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => pushed_new_cmd,
D => \next_mi_addr_reg[23]_i_1_n_4\,
Q => next_mi_addr(23),
R => \^sr\(0)
);
\next_mi_addr_reg[23]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \next_mi_addr_reg[19]_i_1_n_0\,
CO(3) => \next_mi_addr_reg[23]_i_1_n_0\,
CO(2) => \next_mi_addr_reg[23]_i_1_n_1\,
CO(1) => \next_mi_addr_reg[23]_i_1_n_2\,
CO(0) => \next_mi_addr_reg[23]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \next_mi_addr_reg[23]_i_1_n_4\,
O(2) => \next_mi_addr_reg[23]_i_1_n_5\,
O(1) => \next_mi_addr_reg[23]_i_1_n_6\,
O(0) => \next_mi_addr_reg[23]_i_1_n_7\,
S(3) => \next_mi_addr[23]_i_2_n_0\,
S(2) => \next_mi_addr[23]_i_3_n_0\,
S(1) => \next_mi_addr[23]_i_4_n_0\,
S(0) => \next_mi_addr[23]_i_5_n_0\
);
\next_mi_addr_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => pushed_new_cmd,
D => \next_mi_addr_reg[27]_i_1_n_7\,
Q => next_mi_addr(24),
R => \^sr\(0)
);
\next_mi_addr_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => pushed_new_cmd,
D => \next_mi_addr_reg[27]_i_1_n_6\,
Q => next_mi_addr(25),
R => \^sr\(0)
);
\next_mi_addr_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => pushed_new_cmd,
D => \next_mi_addr_reg[27]_i_1_n_5\,
Q => next_mi_addr(26),
R => \^sr\(0)
);
\next_mi_addr_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => pushed_new_cmd,
D => \next_mi_addr_reg[27]_i_1_n_4\,
Q => next_mi_addr(27),
R => \^sr\(0)
);
\next_mi_addr_reg[27]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \next_mi_addr_reg[23]_i_1_n_0\,
CO(3) => \next_mi_addr_reg[27]_i_1_n_0\,
CO(2) => \next_mi_addr_reg[27]_i_1_n_1\,
CO(1) => \next_mi_addr_reg[27]_i_1_n_2\,
CO(0) => \next_mi_addr_reg[27]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \next_mi_addr_reg[27]_i_1_n_4\,
O(2) => \next_mi_addr_reg[27]_i_1_n_5\,
O(1) => \next_mi_addr_reg[27]_i_1_n_6\,
O(0) => \next_mi_addr_reg[27]_i_1_n_7\,
S(3) => \next_mi_addr[27]_i_2_n_0\,
S(2) => \next_mi_addr[27]_i_3_n_0\,
S(1) => \next_mi_addr[27]_i_4_n_0\,
S(0) => \next_mi_addr[27]_i_5_n_0\
);
\next_mi_addr_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => pushed_new_cmd,
D => \next_mi_addr_reg[31]_i_1_n_7\,
Q => next_mi_addr(28),
R => \^sr\(0)
);
\next_mi_addr_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => pushed_new_cmd,
D => \next_mi_addr_reg[31]_i_1_n_6\,
Q => next_mi_addr(29),
R => \^sr\(0)
);
\next_mi_addr_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => pushed_new_cmd,
D => \next_mi_addr_reg[3]_i_1_n_5\,
Q => next_mi_addr(2),
R => \^sr\(0)
);
\next_mi_addr_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => pushed_new_cmd,
D => \next_mi_addr_reg[31]_i_1_n_5\,
Q => next_mi_addr(30),
R => \^sr\(0)
);
\next_mi_addr_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => pushed_new_cmd,
D => \next_mi_addr_reg[31]_i_1_n_4\,
Q => next_mi_addr(31),
R => \^sr\(0)
);
\next_mi_addr_reg[31]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \next_mi_addr_reg[27]_i_1_n_0\,
CO(3) => \NLW_next_mi_addr_reg[31]_i_1_CO_UNCONNECTED\(3),
CO(2) => \next_mi_addr_reg[31]_i_1_n_1\,
CO(1) => \next_mi_addr_reg[31]_i_1_n_2\,
CO(0) => \next_mi_addr_reg[31]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \next_mi_addr_reg[31]_i_1_n_4\,
O(2) => \next_mi_addr_reg[31]_i_1_n_5\,
O(1) => \next_mi_addr_reg[31]_i_1_n_6\,
O(0) => \next_mi_addr_reg[31]_i_1_n_7\,
S(3) => \next_mi_addr[31]_i_2_n_0\,
S(2) => \next_mi_addr[31]_i_3_n_0\,
S(1) => \next_mi_addr[31]_i_4_n_0\,
S(0) => \next_mi_addr[31]_i_5_n_0\
);
\next_mi_addr_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => pushed_new_cmd,
D => \next_mi_addr_reg[3]_i_1_n_4\,
Q => next_mi_addr(3),
R => \^sr\(0)
);
\next_mi_addr_reg[3]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \next_mi_addr_reg[3]_i_1_n_0\,
CO(2) => \next_mi_addr_reg[3]_i_1_n_1\,
CO(1) => \next_mi_addr_reg[3]_i_1_n_2\,
CO(0) => \next_mi_addr_reg[3]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => \^m_axi_awaddr\(3 downto 0),
O(3) => \next_mi_addr_reg[3]_i_1_n_4\,
O(2) => \next_mi_addr_reg[3]_i_1_n_5\,
O(1) => \next_mi_addr_reg[3]_i_1_n_6\,
O(0) => \next_mi_addr_reg[3]_i_1_n_7\,
S(3) => \next_mi_addr[3]_i_2_n_0\,
S(2) => \next_mi_addr[3]_i_3_n_0\,
S(1) => \next_mi_addr[3]_i_4_n_0\,
S(0) => \next_mi_addr[3]_i_5_n_0\
);
\next_mi_addr_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => pushed_new_cmd,
D => \next_mi_addr_reg[7]_i_1_n_7\,
Q => next_mi_addr(4),
R => \^sr\(0)
);
\next_mi_addr_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => pushed_new_cmd,
D => \next_mi_addr_reg[7]_i_1_n_6\,
Q => next_mi_addr(5),
R => \^sr\(0)
);
\next_mi_addr_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => pushed_new_cmd,
D => \next_mi_addr_reg[7]_i_1_n_5\,
Q => next_mi_addr(6),
R => \^sr\(0)
);
\next_mi_addr_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => pushed_new_cmd,
D => \next_mi_addr_reg[7]_i_1_n_4\,
Q => next_mi_addr(7),
R => \^sr\(0)
);
\next_mi_addr_reg[7]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \next_mi_addr_reg[3]_i_1_n_0\,
CO(3) => \next_mi_addr_reg[7]_i_1_n_0\,
CO(2) => \next_mi_addr_reg[7]_i_1_n_1\,
CO(1) => \next_mi_addr_reg[7]_i_1_n_2\,
CO(0) => \next_mi_addr_reg[7]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => \^m_axi_awaddr\(7 downto 4),
O(3) => \next_mi_addr_reg[7]_i_1_n_4\,
O(2) => \next_mi_addr_reg[7]_i_1_n_5\,
O(1) => \next_mi_addr_reg[7]_i_1_n_6\,
O(0) => \next_mi_addr_reg[7]_i_1_n_7\,
S(3) => \next_mi_addr[7]_i_2_n_0\,
S(2) => \next_mi_addr[7]_i_3_n_0\,
S(1) => \next_mi_addr[7]_i_4_n_0\,
S(0) => \next_mi_addr[7]_i_5_n_0\
);
\next_mi_addr_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => pushed_new_cmd,
D => \next_mi_addr_reg[11]_i_1_n_7\,
Q => next_mi_addr(8),
R => \^sr\(0)
);
\next_mi_addr_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => pushed_new_cmd,
D => \next_mi_addr_reg[11]_i_1_n_6\,
Q => next_mi_addr(9),
R => \^sr\(0)
);
\num_transactions_q_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_awlen(4),
Q => num_transactions_q(0),
R => \^sr\(0)
);
\num_transactions_q_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_awlen(5),
Q => num_transactions_q(1),
R => \^sr\(0)
);
\num_transactions_q_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_awlen(6),
Q => num_transactions_q(2),
R => \^sr\(0)
);
\num_transactions_q_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_awlen(7),
Q => num_transactions_q(3),
R => \^sr\(0)
);
\pushed_commands[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \pushed_commands_reg__0\(0),
O => p_0_in(0)
);
\pushed_commands[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \pushed_commands_reg__0\(0),
I1 => \pushed_commands_reg__0\(1),
O => p_0_in(1)
);
\pushed_commands[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => \pushed_commands_reg__0\(2),
I1 => \pushed_commands_reg__0\(1),
I2 => \pushed_commands_reg__0\(0),
O => p_0_in(2)
);
\pushed_commands[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \^e\(0),
I1 => aresetn,
O => \pushed_commands[3]_i_1_n_0\
);
\pushed_commands[3]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => \pushed_commands_reg__0\(3),
I1 => \pushed_commands_reg__0\(0),
I2 => \pushed_commands_reg__0\(1),
I3 => \pushed_commands_reg__0\(2),
O => p_0_in(3)
);
\pushed_commands_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => pushed_new_cmd,
D => p_0_in(0),
Q => \pushed_commands_reg__0\(0),
R => \pushed_commands[3]_i_1_n_0\
);
\pushed_commands_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => pushed_new_cmd,
D => p_0_in(1),
Q => \pushed_commands_reg__0\(1),
R => \pushed_commands[3]_i_1_n_0\
);
\pushed_commands_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => pushed_new_cmd,
D => p_0_in(2),
Q => \pushed_commands_reg__0\(2),
R => \pushed_commands[3]_i_1_n_0\
);
\pushed_commands_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => pushed_new_cmd,
D => p_0_in(3),
Q => \pushed_commands_reg__0\(3),
R => \pushed_commands[3]_i_1_n_0\
);
\queue_id_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \USE_B_CHANNEL.cmd_b_queue_n_19\,
Q => queue_id(0),
R => \^sr\(0)
);
\queue_id_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \USE_B_CHANNEL.cmd_b_queue_n_20\,
Q => queue_id(1),
R => \^sr\(0)
);
\size_mask_q[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"01"
)
port map (
I0 => s_axi_awsize(2),
I1 => s_axi_awsize(0),
I2 => s_axi_awsize(1),
O => size_mask(0)
);
\size_mask_q[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => s_axi_awsize(2),
I1 => s_axi_awsize(1),
O => size_mask(1)
);
\size_mask_q[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"07"
)
port map (
I0 => s_axi_awsize(0),
I1 => s_axi_awsize(1),
I2 => s_axi_awsize(2),
O => size_mask(2)
);
\size_mask_q[3]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => s_axi_awsize(2),
O => size_mask(3)
);
\size_mask_q[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"57"
)
port map (
I0 => s_axi_awsize(2),
I1 => s_axi_awsize(0),
I2 => s_axi_awsize(1),
O => size_mask(4)
);
\size_mask_q[5]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => s_axi_awsize(2),
I1 => s_axi_awsize(1),
O => size_mask(5)
);
\size_mask_q[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"7F"
)
port map (
I0 => s_axi_awsize(2),
I1 => s_axi_awsize(0),
I2 => s_axi_awsize(1),
O => size_mask(6)
);
\size_mask_q_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => size_mask(0),
Q => size_mask_q(0),
R => \^sr\(0)
);
\size_mask_q_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => size_mask(1),
Q => size_mask_q(1),
R => \^sr\(0)
);
\size_mask_q_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => size_mask(2),
Q => size_mask_q(2),
R => \^sr\(0)
);
\size_mask_q_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => '1',
Q => size_mask_q(31),
R => \^sr\(0)
);
\size_mask_q_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => size_mask(3),
Q => size_mask_q(3),
R => \^sr\(0)
);
\size_mask_q_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => size_mask(4),
Q => size_mask_q(4),
R => \^sr\(0)
);
\size_mask_q_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => size_mask(5),
Q => size_mask_q(5),
R => \^sr\(0)
);
\size_mask_q_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => size_mask(6),
Q => size_mask_q(6),
R => \^sr\(0)
);
split_in_progress_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \USE_B_CHANNEL.cmd_b_queue_n_15\,
Q => split_in_progress_reg_n_0,
R => '0'
);
split_ongoing_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => pushed_new_cmd,
D => \USE_B_CHANNEL.cmd_b_queue_n_6\,
Q => split_ongoing,
R => \^sr\(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_auto_pc_1_axi_protocol_converter_v2_1_11_a_axi3_conv__parameterized0\ is
port (
E : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arvalid : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
m_axi_arlen : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rlast : out STD_LOGIC;
m_axi_rready : out STD_LOGIC;
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
aclk : in STD_LOGIC;
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_rlast : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC;
m_axi_arready : in STD_LOGIC;
aresetn : in STD_LOGIC;
areset_d : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arvalid : in STD_LOGIC;
\areset_d_reg[1]\ : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_auto_pc_1_axi_protocol_converter_v2_1_11_a_axi3_conv__parameterized0\ : entity is "axi_protocol_converter_v2_1_11_a_axi3_conv";
end \system_auto_pc_1_axi_protocol_converter_v2_1_11_a_axi3_conv__parameterized0\;
architecture STRUCTURE of \system_auto_pc_1_axi_protocol_converter_v2_1_11_a_axi3_conv__parameterized0\ is
signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \S_AXI_AADDR_Q_reg_n_0_[0]\ : STD_LOGIC;
signal \S_AXI_AADDR_Q_reg_n_0_[10]\ : STD_LOGIC;
signal \S_AXI_AADDR_Q_reg_n_0_[11]\ : STD_LOGIC;
signal \S_AXI_AADDR_Q_reg_n_0_[12]\ : STD_LOGIC;
signal \S_AXI_AADDR_Q_reg_n_0_[13]\ : STD_LOGIC;
signal \S_AXI_AADDR_Q_reg_n_0_[14]\ : STD_LOGIC;
signal \S_AXI_AADDR_Q_reg_n_0_[15]\ : STD_LOGIC;
signal \S_AXI_AADDR_Q_reg_n_0_[16]\ : STD_LOGIC;
signal \S_AXI_AADDR_Q_reg_n_0_[17]\ : STD_LOGIC;
signal \S_AXI_AADDR_Q_reg_n_0_[18]\ : STD_LOGIC;
signal \S_AXI_AADDR_Q_reg_n_0_[19]\ : STD_LOGIC;
signal \S_AXI_AADDR_Q_reg_n_0_[1]\ : STD_LOGIC;
signal \S_AXI_AADDR_Q_reg_n_0_[20]\ : STD_LOGIC;
signal \S_AXI_AADDR_Q_reg_n_0_[21]\ : STD_LOGIC;
signal \S_AXI_AADDR_Q_reg_n_0_[22]\ : STD_LOGIC;
signal \S_AXI_AADDR_Q_reg_n_0_[23]\ : STD_LOGIC;
signal \S_AXI_AADDR_Q_reg_n_0_[24]\ : STD_LOGIC;
signal \S_AXI_AADDR_Q_reg_n_0_[25]\ : STD_LOGIC;
signal \S_AXI_AADDR_Q_reg_n_0_[26]\ : STD_LOGIC;
signal \S_AXI_AADDR_Q_reg_n_0_[27]\ : STD_LOGIC;
signal \S_AXI_AADDR_Q_reg_n_0_[28]\ : STD_LOGIC;
signal \S_AXI_AADDR_Q_reg_n_0_[29]\ : STD_LOGIC;
signal \S_AXI_AADDR_Q_reg_n_0_[2]\ : STD_LOGIC;
signal \S_AXI_AADDR_Q_reg_n_0_[30]\ : STD_LOGIC;
signal \S_AXI_AADDR_Q_reg_n_0_[31]\ : STD_LOGIC;
signal \S_AXI_AADDR_Q_reg_n_0_[3]\ : STD_LOGIC;
signal \S_AXI_AADDR_Q_reg_n_0_[4]\ : STD_LOGIC;
signal \S_AXI_AADDR_Q_reg_n_0_[5]\ : STD_LOGIC;
signal \S_AXI_AADDR_Q_reg_n_0_[6]\ : STD_LOGIC;
signal \S_AXI_AADDR_Q_reg_n_0_[7]\ : STD_LOGIC;
signal \S_AXI_AADDR_Q_reg_n_0_[8]\ : STD_LOGIC;
signal \S_AXI_AADDR_Q_reg_n_0_[9]\ : STD_LOGIC;
signal S_AXI_ALEN_Q : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \S_AXI_ALOCK_Q_reg_n_0_[0]\ : STD_LOGIC;
signal \USE_R_CHANNEL.cmd_queue_n_0\ : STD_LOGIC;
signal \USE_R_CHANNEL.cmd_queue_n_14\ : STD_LOGIC;
signal \USE_R_CHANNEL.cmd_queue_n_15\ : STD_LOGIC;
signal \USE_R_CHANNEL.cmd_queue_n_16\ : STD_LOGIC;
signal \USE_R_CHANNEL.cmd_queue_n_17\ : STD_LOGIC;
signal \USE_R_CHANNEL.cmd_queue_n_18\ : STD_LOGIC;
signal \USE_R_CHANNEL.cmd_queue_n_3\ : STD_LOGIC;
signal \USE_R_CHANNEL.cmd_queue_n_4\ : STD_LOGIC;
signal \USE_R_CHANNEL.cmd_queue_n_5\ : STD_LOGIC;
signal \USE_R_CHANNEL.cmd_queue_n_6\ : STD_LOGIC;
signal \USE_R_CHANNEL.cmd_queue_n_7\ : STD_LOGIC;
signal \USE_R_CHANNEL.cmd_queue_n_9\ : STD_LOGIC;
signal access_is_incr : STD_LOGIC;
signal access_is_incr_q : STD_LOGIC;
signal \addr_step_q[10]_i_1__0_n_0\ : STD_LOGIC;
signal \addr_step_q[11]_i_1__0_n_0\ : STD_LOGIC;
signal \addr_step_q[5]_i_1__0_n_0\ : STD_LOGIC;
signal \addr_step_q[6]_i_1__0_n_0\ : STD_LOGIC;
signal \addr_step_q[7]_i_1__0_n_0\ : STD_LOGIC;
signal \addr_step_q[8]_i_1__0_n_0\ : STD_LOGIC;
signal \addr_step_q[9]_i_1__0_n_0\ : STD_LOGIC;
signal \addr_step_q_reg_n_0_[10]\ : STD_LOGIC;
signal \addr_step_q_reg_n_0_[11]\ : STD_LOGIC;
signal \addr_step_q_reg_n_0_[5]\ : STD_LOGIC;
signal \addr_step_q_reg_n_0_[6]\ : STD_LOGIC;
signal \addr_step_q_reg_n_0_[7]\ : STD_LOGIC;
signal \addr_step_q_reg_n_0_[8]\ : STD_LOGIC;
signal \addr_step_q_reg_n_0_[9]\ : STD_LOGIC;
signal almost_empty : STD_LOGIC;
signal \cmd_depth[0]_i_1__0_n_0\ : STD_LOGIC;
signal \cmd_depth_reg__0\ : STD_LOGIC_VECTOR ( 5 downto 0 );
signal cmd_empty : STD_LOGIC;
signal cmd_empty_i_1_n_0 : STD_LOGIC;
signal cmd_push : STD_LOGIC;
signal cmd_push_block : STD_LOGIC;
signal command_ongoing : STD_LOGIC;
signal first_step : STD_LOGIC_VECTOR ( 11 downto 4 );
signal \first_step_q[0]_i_1__0_n_0\ : STD_LOGIC;
signal \first_step_q[10]_i_2__0_n_0\ : STD_LOGIC;
signal \first_step_q[11]_i_2__0_n_0\ : STD_LOGIC;
signal \first_step_q[1]_i_1__0_n_0\ : STD_LOGIC;
signal \first_step_q[2]_i_1__0_n_0\ : STD_LOGIC;
signal \first_step_q[3]_i_1__0_n_0\ : STD_LOGIC;
signal \first_step_q[6]_i_2__0_n_0\ : STD_LOGIC;
signal \first_step_q[7]_i_2__0_n_0\ : STD_LOGIC;
signal \first_step_q[8]_i_2__0_n_0\ : STD_LOGIC;
signal \first_step_q[9]_i_2__0_n_0\ : STD_LOGIC;
signal \first_step_q_reg_n_0_[0]\ : STD_LOGIC;
signal \first_step_q_reg_n_0_[10]\ : STD_LOGIC;
signal \first_step_q_reg_n_0_[11]\ : STD_LOGIC;
signal \first_step_q_reg_n_0_[1]\ : STD_LOGIC;
signal \first_step_q_reg_n_0_[2]\ : STD_LOGIC;
signal \first_step_q_reg_n_0_[3]\ : STD_LOGIC;
signal \first_step_q_reg_n_0_[4]\ : STD_LOGIC;
signal \first_step_q_reg_n_0_[5]\ : STD_LOGIC;
signal \first_step_q_reg_n_0_[6]\ : STD_LOGIC;
signal \first_step_q_reg_n_0_[7]\ : STD_LOGIC;
signal \first_step_q_reg_n_0_[8]\ : STD_LOGIC;
signal \first_step_q_reg_n_0_[9]\ : STD_LOGIC;
signal \incr_need_to_split__0\ : STD_LOGIC;
signal \^m_axi_araddr\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal multiple_id_non_split : STD_LOGIC;
signal \multiple_id_non_split_i_2__0_n_0\ : STD_LOGIC;
signal multiple_id_non_split_i_3_n_0 : STD_LOGIC;
signal need_to_split_q : STD_LOGIC;
signal next_mi_addr : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \next_mi_addr[11]_i_2_n_0\ : STD_LOGIC;
signal \next_mi_addr[11]_i_3_n_0\ : STD_LOGIC;
signal \next_mi_addr[11]_i_4_n_0\ : STD_LOGIC;
signal \next_mi_addr[11]_i_5_n_0\ : STD_LOGIC;
signal \next_mi_addr[11]_i_6__0_n_0\ : STD_LOGIC;
signal \next_mi_addr[15]_i_2__0_n_0\ : STD_LOGIC;
signal \next_mi_addr[15]_i_3__0_n_0\ : STD_LOGIC;
signal \next_mi_addr[15]_i_4__0_n_0\ : STD_LOGIC;
signal \next_mi_addr[15]_i_5__0_n_0\ : STD_LOGIC;
signal \next_mi_addr[15]_i_6__0_n_0\ : STD_LOGIC;
signal \next_mi_addr[15]_i_7__0_n_0\ : STD_LOGIC;
signal \next_mi_addr[15]_i_8__0_n_0\ : STD_LOGIC;
signal \next_mi_addr[15]_i_9__0_n_0\ : STD_LOGIC;
signal \next_mi_addr[19]_i_2__0_n_0\ : STD_LOGIC;
signal \next_mi_addr[19]_i_3__0_n_0\ : STD_LOGIC;
signal \next_mi_addr[19]_i_4__0_n_0\ : STD_LOGIC;
signal \next_mi_addr[19]_i_5__0_n_0\ : STD_LOGIC;
signal \next_mi_addr[23]_i_2__0_n_0\ : STD_LOGIC;
signal \next_mi_addr[23]_i_3__0_n_0\ : STD_LOGIC;
signal \next_mi_addr[23]_i_4__0_n_0\ : STD_LOGIC;
signal \next_mi_addr[23]_i_5__0_n_0\ : STD_LOGIC;
signal \next_mi_addr[27]_i_2__0_n_0\ : STD_LOGIC;
signal \next_mi_addr[27]_i_3__0_n_0\ : STD_LOGIC;
signal \next_mi_addr[27]_i_4__0_n_0\ : STD_LOGIC;
signal \next_mi_addr[27]_i_5__0_n_0\ : STD_LOGIC;
signal \next_mi_addr[31]_i_2__0_n_0\ : STD_LOGIC;
signal \next_mi_addr[31]_i_3__0_n_0\ : STD_LOGIC;
signal \next_mi_addr[31]_i_4__0_n_0\ : STD_LOGIC;
signal \next_mi_addr[31]_i_5__0_n_0\ : STD_LOGIC;
signal \next_mi_addr[3]_i_2_n_0\ : STD_LOGIC;
signal \next_mi_addr[3]_i_3_n_0\ : STD_LOGIC;
signal \next_mi_addr[3]_i_4_n_0\ : STD_LOGIC;
signal \next_mi_addr[3]_i_5_n_0\ : STD_LOGIC;
signal \next_mi_addr[3]_i_6__0_n_0\ : STD_LOGIC;
signal \next_mi_addr[7]_i_2_n_0\ : STD_LOGIC;
signal \next_mi_addr[7]_i_3_n_0\ : STD_LOGIC;
signal \next_mi_addr[7]_i_4_n_0\ : STD_LOGIC;
signal \next_mi_addr[7]_i_5_n_0\ : STD_LOGIC;
signal \next_mi_addr_reg[11]_i_1__0_n_0\ : STD_LOGIC;
signal \next_mi_addr_reg[11]_i_1__0_n_1\ : STD_LOGIC;
signal \next_mi_addr_reg[11]_i_1__0_n_2\ : STD_LOGIC;
signal \next_mi_addr_reg[11]_i_1__0_n_3\ : STD_LOGIC;
signal \next_mi_addr_reg[11]_i_1__0_n_4\ : STD_LOGIC;
signal \next_mi_addr_reg[11]_i_1__0_n_5\ : STD_LOGIC;
signal \next_mi_addr_reg[11]_i_1__0_n_6\ : STD_LOGIC;
signal \next_mi_addr_reg[11]_i_1__0_n_7\ : STD_LOGIC;
signal \next_mi_addr_reg[15]_i_1__0_n_0\ : STD_LOGIC;
signal \next_mi_addr_reg[15]_i_1__0_n_1\ : STD_LOGIC;
signal \next_mi_addr_reg[15]_i_1__0_n_2\ : STD_LOGIC;
signal \next_mi_addr_reg[15]_i_1__0_n_3\ : STD_LOGIC;
signal \next_mi_addr_reg[15]_i_1__0_n_4\ : STD_LOGIC;
signal \next_mi_addr_reg[15]_i_1__0_n_5\ : STD_LOGIC;
signal \next_mi_addr_reg[15]_i_1__0_n_6\ : STD_LOGIC;
signal \next_mi_addr_reg[15]_i_1__0_n_7\ : STD_LOGIC;
signal \next_mi_addr_reg[19]_i_1__0_n_0\ : STD_LOGIC;
signal \next_mi_addr_reg[19]_i_1__0_n_1\ : STD_LOGIC;
signal \next_mi_addr_reg[19]_i_1__0_n_2\ : STD_LOGIC;
signal \next_mi_addr_reg[19]_i_1__0_n_3\ : STD_LOGIC;
signal \next_mi_addr_reg[19]_i_1__0_n_4\ : STD_LOGIC;
signal \next_mi_addr_reg[19]_i_1__0_n_5\ : STD_LOGIC;
signal \next_mi_addr_reg[19]_i_1__0_n_6\ : STD_LOGIC;
signal \next_mi_addr_reg[19]_i_1__0_n_7\ : STD_LOGIC;
signal \next_mi_addr_reg[23]_i_1__0_n_0\ : STD_LOGIC;
signal \next_mi_addr_reg[23]_i_1__0_n_1\ : STD_LOGIC;
signal \next_mi_addr_reg[23]_i_1__0_n_2\ : STD_LOGIC;
signal \next_mi_addr_reg[23]_i_1__0_n_3\ : STD_LOGIC;
signal \next_mi_addr_reg[23]_i_1__0_n_4\ : STD_LOGIC;
signal \next_mi_addr_reg[23]_i_1__0_n_5\ : STD_LOGIC;
signal \next_mi_addr_reg[23]_i_1__0_n_6\ : STD_LOGIC;
signal \next_mi_addr_reg[23]_i_1__0_n_7\ : STD_LOGIC;
signal \next_mi_addr_reg[27]_i_1__0_n_0\ : STD_LOGIC;
signal \next_mi_addr_reg[27]_i_1__0_n_1\ : STD_LOGIC;
signal \next_mi_addr_reg[27]_i_1__0_n_2\ : STD_LOGIC;
signal \next_mi_addr_reg[27]_i_1__0_n_3\ : STD_LOGIC;
signal \next_mi_addr_reg[27]_i_1__0_n_4\ : STD_LOGIC;
signal \next_mi_addr_reg[27]_i_1__0_n_5\ : STD_LOGIC;
signal \next_mi_addr_reg[27]_i_1__0_n_6\ : STD_LOGIC;
signal \next_mi_addr_reg[27]_i_1__0_n_7\ : STD_LOGIC;
signal \next_mi_addr_reg[31]_i_1__0_n_1\ : STD_LOGIC;
signal \next_mi_addr_reg[31]_i_1__0_n_2\ : STD_LOGIC;
signal \next_mi_addr_reg[31]_i_1__0_n_3\ : STD_LOGIC;
signal \next_mi_addr_reg[31]_i_1__0_n_4\ : STD_LOGIC;
signal \next_mi_addr_reg[31]_i_1__0_n_5\ : STD_LOGIC;
signal \next_mi_addr_reg[31]_i_1__0_n_6\ : STD_LOGIC;
signal \next_mi_addr_reg[31]_i_1__0_n_7\ : STD_LOGIC;
signal \next_mi_addr_reg[3]_i_1__0_n_0\ : STD_LOGIC;
signal \next_mi_addr_reg[3]_i_1__0_n_1\ : STD_LOGIC;
signal \next_mi_addr_reg[3]_i_1__0_n_2\ : STD_LOGIC;
signal \next_mi_addr_reg[3]_i_1__0_n_3\ : STD_LOGIC;
signal \next_mi_addr_reg[3]_i_1__0_n_4\ : STD_LOGIC;
signal \next_mi_addr_reg[3]_i_1__0_n_5\ : STD_LOGIC;
signal \next_mi_addr_reg[3]_i_1__0_n_6\ : STD_LOGIC;
signal \next_mi_addr_reg[3]_i_1__0_n_7\ : STD_LOGIC;
signal \next_mi_addr_reg[7]_i_1__0_n_0\ : STD_LOGIC;
signal \next_mi_addr_reg[7]_i_1__0_n_1\ : STD_LOGIC;
signal \next_mi_addr_reg[7]_i_1__0_n_2\ : STD_LOGIC;
signal \next_mi_addr_reg[7]_i_1__0_n_3\ : STD_LOGIC;
signal \next_mi_addr_reg[7]_i_1__0_n_4\ : STD_LOGIC;
signal \next_mi_addr_reg[7]_i_1__0_n_5\ : STD_LOGIC;
signal \next_mi_addr_reg[7]_i_1__0_n_6\ : STD_LOGIC;
signal \next_mi_addr_reg[7]_i_1__0_n_7\ : STD_LOGIC;
signal \num_transactions_q_reg_n_0_[0]\ : STD_LOGIC;
signal \num_transactions_q_reg_n_0_[1]\ : STD_LOGIC;
signal \num_transactions_q_reg_n_0_[2]\ : STD_LOGIC;
signal \num_transactions_q_reg_n_0_[3]\ : STD_LOGIC;
signal \p_0_in__0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \pushed_commands[3]_i_1__0_n_0\ : STD_LOGIC;
signal \pushed_commands_reg__0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal pushed_new_cmd : STD_LOGIC;
signal \queue_id[0]_i_1_n_0\ : STD_LOGIC;
signal \queue_id[1]_i_1_n_0\ : STD_LOGIC;
signal \queue_id_reg_n_0_[0]\ : STD_LOGIC;
signal \queue_id_reg_n_0_[1]\ : STD_LOGIC;
signal rd_cmd_ready : STD_LOGIC;
signal size_mask_q : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \size_mask_q[0]_i_1__0_n_0\ : STD_LOGIC;
signal \size_mask_q[1]_i_1__0_n_0\ : STD_LOGIC;
signal \size_mask_q[2]_i_1__0_n_0\ : STD_LOGIC;
signal \size_mask_q[3]_i_1__0_n_0\ : STD_LOGIC;
signal \size_mask_q[4]_i_1__0_n_0\ : STD_LOGIC;
signal \size_mask_q[5]_i_1__0_n_0\ : STD_LOGIC;
signal \size_mask_q[6]_i_1__0_n_0\ : STD_LOGIC;
signal split_in_progress_reg_n_0 : STD_LOGIC;
signal split_ongoing : STD_LOGIC;
signal \NLW_next_mi_addr_reg[31]_i_1__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \addr_step_q[10]_i_1__0\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \addr_step_q[11]_i_1__0\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \addr_step_q[5]_i_1__0\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \addr_step_q[6]_i_1__0\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \addr_step_q[7]_i_1__0\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \addr_step_q[8]_i_1__0\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \addr_step_q[9]_i_1__0\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of cmd_empty_i_1 : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \first_step_q[0]_i_1__0\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \first_step_q[10]_i_1__0\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \first_step_q[11]_i_1__0\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \first_step_q[1]_i_1__0\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \first_step_q[3]_i_1__0\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \first_step_q[4]_i_1__0\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \first_step_q[6]_i_1__0\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \first_step_q[7]_i_1__0\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \first_step_q[8]_i_1__0\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \first_step_q[9]_i_1__0\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \m_axi_araddr[26]_INST_0\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \multiple_id_non_split_i_2__0\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of multiple_id_non_split_i_3 : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \next_mi_addr[11]_i_6__0\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \next_mi_addr[3]_i_6__0\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \pushed_commands[1]_i_1__0\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \pushed_commands[2]_i_1__0\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \pushed_commands[3]_i_2__0\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \queue_id[0]_i_1\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \size_mask_q[0]_i_1__0\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \size_mask_q[1]_i_1__0\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \size_mask_q[2]_i_1__0\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \size_mask_q[3]_i_1__0\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \size_mask_q[4]_i_1__0\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \size_mask_q[5]_i_1__0\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \size_mask_q[6]_i_1__0\ : label is "soft_lutpair16";
begin
E(0) <= \^e\(0);
Q(1 downto 0) <= \^q\(1 downto 0);
m_axi_araddr(31 downto 0) <= \^m_axi_araddr\(31 downto 0);
\S_AXI_AADDR_Q_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_araddr(0),
Q => \S_AXI_AADDR_Q_reg_n_0_[0]\,
R => SR(0)
);
\S_AXI_AADDR_Q_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_araddr(10),
Q => \S_AXI_AADDR_Q_reg_n_0_[10]\,
R => SR(0)
);
\S_AXI_AADDR_Q_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_araddr(11),
Q => \S_AXI_AADDR_Q_reg_n_0_[11]\,
R => SR(0)
);
\S_AXI_AADDR_Q_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_araddr(12),
Q => \S_AXI_AADDR_Q_reg_n_0_[12]\,
R => SR(0)
);
\S_AXI_AADDR_Q_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_araddr(13),
Q => \S_AXI_AADDR_Q_reg_n_0_[13]\,
R => SR(0)
);
\S_AXI_AADDR_Q_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_araddr(14),
Q => \S_AXI_AADDR_Q_reg_n_0_[14]\,
R => SR(0)
);
\S_AXI_AADDR_Q_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_araddr(15),
Q => \S_AXI_AADDR_Q_reg_n_0_[15]\,
R => SR(0)
);
\S_AXI_AADDR_Q_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_araddr(16),
Q => \S_AXI_AADDR_Q_reg_n_0_[16]\,
R => SR(0)
);
\S_AXI_AADDR_Q_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_araddr(17),
Q => \S_AXI_AADDR_Q_reg_n_0_[17]\,
R => SR(0)
);
\S_AXI_AADDR_Q_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_araddr(18),
Q => \S_AXI_AADDR_Q_reg_n_0_[18]\,
R => SR(0)
);
\S_AXI_AADDR_Q_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_araddr(19),
Q => \S_AXI_AADDR_Q_reg_n_0_[19]\,
R => SR(0)
);
\S_AXI_AADDR_Q_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_araddr(1),
Q => \S_AXI_AADDR_Q_reg_n_0_[1]\,
R => SR(0)
);
\S_AXI_AADDR_Q_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_araddr(20),
Q => \S_AXI_AADDR_Q_reg_n_0_[20]\,
R => SR(0)
);
\S_AXI_AADDR_Q_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_araddr(21),
Q => \S_AXI_AADDR_Q_reg_n_0_[21]\,
R => SR(0)
);
\S_AXI_AADDR_Q_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_araddr(22),
Q => \S_AXI_AADDR_Q_reg_n_0_[22]\,
R => SR(0)
);
\S_AXI_AADDR_Q_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_araddr(23),
Q => \S_AXI_AADDR_Q_reg_n_0_[23]\,
R => SR(0)
);
\S_AXI_AADDR_Q_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_araddr(24),
Q => \S_AXI_AADDR_Q_reg_n_0_[24]\,
R => SR(0)
);
\S_AXI_AADDR_Q_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_araddr(25),
Q => \S_AXI_AADDR_Q_reg_n_0_[25]\,
R => SR(0)
);
\S_AXI_AADDR_Q_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_araddr(26),
Q => \S_AXI_AADDR_Q_reg_n_0_[26]\,
R => SR(0)
);
\S_AXI_AADDR_Q_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_araddr(27),
Q => \S_AXI_AADDR_Q_reg_n_0_[27]\,
R => SR(0)
);
\S_AXI_AADDR_Q_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_araddr(28),
Q => \S_AXI_AADDR_Q_reg_n_0_[28]\,
R => SR(0)
);
\S_AXI_AADDR_Q_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_araddr(29),
Q => \S_AXI_AADDR_Q_reg_n_0_[29]\,
R => SR(0)
);
\S_AXI_AADDR_Q_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_araddr(2),
Q => \S_AXI_AADDR_Q_reg_n_0_[2]\,
R => SR(0)
);
\S_AXI_AADDR_Q_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_araddr(30),
Q => \S_AXI_AADDR_Q_reg_n_0_[30]\,
R => SR(0)
);
\S_AXI_AADDR_Q_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_araddr(31),
Q => \S_AXI_AADDR_Q_reg_n_0_[31]\,
R => SR(0)
);
\S_AXI_AADDR_Q_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_araddr(3),
Q => \S_AXI_AADDR_Q_reg_n_0_[3]\,
R => SR(0)
);
\S_AXI_AADDR_Q_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_araddr(4),
Q => \S_AXI_AADDR_Q_reg_n_0_[4]\,
R => SR(0)
);
\S_AXI_AADDR_Q_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_araddr(5),
Q => \S_AXI_AADDR_Q_reg_n_0_[5]\,
R => SR(0)
);
\S_AXI_AADDR_Q_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_araddr(6),
Q => \S_AXI_AADDR_Q_reg_n_0_[6]\,
R => SR(0)
);
\S_AXI_AADDR_Q_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_araddr(7),
Q => \S_AXI_AADDR_Q_reg_n_0_[7]\,
R => SR(0)
);
\S_AXI_AADDR_Q_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_araddr(8),
Q => \S_AXI_AADDR_Q_reg_n_0_[8]\,
R => SR(0)
);
\S_AXI_AADDR_Q_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_araddr(9),
Q => \S_AXI_AADDR_Q_reg_n_0_[9]\,
R => SR(0)
);
\S_AXI_ABURST_Q_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_arburst(0),
Q => m_axi_arburst(0),
R => SR(0)
);
\S_AXI_ABURST_Q_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_arburst(1),
Q => m_axi_arburst(1),
R => SR(0)
);
\S_AXI_ACACHE_Q_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_arcache(0),
Q => m_axi_arcache(0),
R => SR(0)
);
\S_AXI_ACACHE_Q_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_arcache(1),
Q => m_axi_arcache(1),
R => SR(0)
);
\S_AXI_ACACHE_Q_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_arcache(2),
Q => m_axi_arcache(2),
R => SR(0)
);
\S_AXI_ACACHE_Q_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_arcache(3),
Q => m_axi_arcache(3),
R => SR(0)
);
\S_AXI_AID_Q_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_arid(0),
Q => \^q\(0),
R => SR(0)
);
\S_AXI_AID_Q_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_arid(1),
Q => \^q\(1),
R => SR(0)
);
\S_AXI_ALEN_Q_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_arlen(0),
Q => S_AXI_ALEN_Q(0),
R => SR(0)
);
\S_AXI_ALEN_Q_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_arlen(1),
Q => S_AXI_ALEN_Q(1),
R => SR(0)
);
\S_AXI_ALEN_Q_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_arlen(2),
Q => S_AXI_ALEN_Q(2),
R => SR(0)
);
\S_AXI_ALEN_Q_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_arlen(3),
Q => S_AXI_ALEN_Q(3),
R => SR(0)
);
\S_AXI_ALOCK_Q_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_arlock(0),
Q => \S_AXI_ALOCK_Q_reg_n_0_[0]\,
R => SR(0)
);
\S_AXI_APROT_Q_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_arprot(0),
Q => m_axi_arprot(0),
R => SR(0)
);
\S_AXI_APROT_Q_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_arprot(1),
Q => m_axi_arprot(1),
R => SR(0)
);
\S_AXI_APROT_Q_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_arprot(2),
Q => m_axi_arprot(2),
R => SR(0)
);
\S_AXI_AQOS_Q_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_arqos(0),
Q => m_axi_arqos(0),
R => SR(0)
);
\S_AXI_AQOS_Q_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_arqos(1),
Q => m_axi_arqos(1),
R => SR(0)
);
\S_AXI_AQOS_Q_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_arqos(2),
Q => m_axi_arqos(2),
R => SR(0)
);
\S_AXI_AQOS_Q_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_arqos(3),
Q => m_axi_arqos(3),
R => SR(0)
);
S_AXI_AREADY_I_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \USE_R_CHANNEL.cmd_queue_n_14\,
Q => \^e\(0),
R => SR(0)
);
\S_AXI_ASIZE_Q_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_arsize(0),
Q => m_axi_arsize(0),
R => SR(0)
);
\S_AXI_ASIZE_Q_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_arsize(1),
Q => m_axi_arsize(1),
R => SR(0)
);
\S_AXI_ASIZE_Q_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_arsize(2),
Q => m_axi_arsize(2),
R => SR(0)
);
\USE_R_CHANNEL.cmd_queue\: entity work.\system_auto_pc_1_axi_data_fifo_v2_1_10_axic_fifo__parameterized1\
port map (
D(4) => \USE_R_CHANNEL.cmd_queue_n_3\,
D(3) => \USE_R_CHANNEL.cmd_queue_n_4\,
D(2) => \USE_R_CHANNEL.cmd_queue_n_5\,
D(1) => \USE_R_CHANNEL.cmd_queue_n_6\,
D(0) => \USE_R_CHANNEL.cmd_queue_n_7\,
E(0) => \USE_R_CHANNEL.cmd_queue_n_9\,
Q(5 downto 0) => \cmd_depth_reg__0\(5 downto 0),
SR(0) => SR(0),
\S_AXI_AID_Q_reg[0]\ => multiple_id_non_split_i_3_n_0,
\S_AXI_AID_Q_reg[1]\(1 downto 0) => \^q\(1 downto 0),
S_AXI_AREADY_I_reg => \USE_R_CHANNEL.cmd_queue_n_14\,
S_AXI_AREADY_I_reg_0 => \^e\(0),
access_is_incr_q => access_is_incr_q,
aclk => aclk,
almost_empty => almost_empty,
areset_d(1 downto 0) => areset_d(1 downto 0),
\areset_d_reg[1]\ => \areset_d_reg[1]\,
aresetn => aresetn,
cmd_empty => cmd_empty,
cmd_push => cmd_push,
cmd_push_block => cmd_push_block,
cmd_push_block_reg => \USE_R_CHANNEL.cmd_queue_n_15\,
command_ongoing => command_ongoing,
command_ongoing_reg => \USE_R_CHANNEL.cmd_queue_n_16\,
din(0) => \USE_R_CHANNEL.cmd_queue_n_0\,
m_axi_arready => m_axi_arready,
m_axi_arvalid => m_axi_arvalid,
m_axi_rlast => m_axi_rlast,
m_axi_rready => m_axi_rready,
m_axi_rvalid => m_axi_rvalid,
multiple_id_non_split => multiple_id_non_split,
multiple_id_non_split_reg => \USE_R_CHANNEL.cmd_queue_n_18\,
need_to_split_q => need_to_split_q,
\num_transactions_q_reg[0]\ => \num_transactions_q_reg_n_0_[0]\,
\num_transactions_q_reg[1]\ => \num_transactions_q_reg_n_0_[1]\,
\num_transactions_q_reg[2]\ => \num_transactions_q_reg_n_0_[2]\,
\num_transactions_q_reg[3]\ => \num_transactions_q_reg_n_0_[3]\,
\pushed_commands_reg[3]\(3 downto 0) => \pushed_commands_reg__0\(3 downto 0),
pushed_new_cmd => pushed_new_cmd,
\queue_id_reg[0]\ => \queue_id_reg_n_0_[0]\,
\queue_id_reg[1]\ => \queue_id_reg_n_0_[1]\,
rd_cmd_ready => rd_cmd_ready,
s_axi_arvalid => s_axi_arvalid,
s_axi_rlast => s_axi_rlast,
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid,
split_in_progress_reg => \USE_R_CHANNEL.cmd_queue_n_17\,
split_in_progress_reg_0 => split_in_progress_reg_n_0,
split_in_progress_reg_1 => \multiple_id_non_split_i_2__0_n_0\
);
\access_is_incr_q_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_arburst(0),
I1 => s_axi_arburst(1),
O => access_is_incr
);
access_is_incr_q_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => access_is_incr,
Q => access_is_incr_q,
R => SR(0)
);
\addr_step_q[10]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => s_axi_arsize(1),
I1 => s_axi_arsize(2),
I2 => s_axi_arsize(0),
O => \addr_step_q[10]_i_1__0_n_0\
);
\addr_step_q[11]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => s_axi_arsize(1),
I1 => s_axi_arsize(0),
I2 => s_axi_arsize(2),
O => \addr_step_q[11]_i_1__0_n_0\
);
\addr_step_q[5]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => s_axi_arsize(2),
I1 => s_axi_arsize(0),
I2 => s_axi_arsize(1),
O => \addr_step_q[5]_i_1__0_n_0\
);
\addr_step_q[6]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => s_axi_arsize(0),
I1 => s_axi_arsize(1),
I2 => s_axi_arsize(2),
O => \addr_step_q[6]_i_1__0_n_0\
);
\addr_step_q[7]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => s_axi_arsize(1),
I1 => s_axi_arsize(0),
I2 => s_axi_arsize(2),
O => \addr_step_q[7]_i_1__0_n_0\
);
\addr_step_q[8]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => s_axi_arsize(0),
I1 => s_axi_arsize(2),
I2 => s_axi_arsize(1),
O => \addr_step_q[8]_i_1__0_n_0\
);
\addr_step_q[9]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => s_axi_arsize(2),
I1 => s_axi_arsize(0),
I2 => s_axi_arsize(1),
O => \addr_step_q[9]_i_1__0_n_0\
);
\addr_step_q_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => \addr_step_q[10]_i_1__0_n_0\,
Q => \addr_step_q_reg_n_0_[10]\,
R => SR(0)
);
\addr_step_q_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => \addr_step_q[11]_i_1__0_n_0\,
Q => \addr_step_q_reg_n_0_[11]\,
R => SR(0)
);
\addr_step_q_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => \addr_step_q[5]_i_1__0_n_0\,
Q => \addr_step_q_reg_n_0_[5]\,
R => SR(0)
);
\addr_step_q_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => \addr_step_q[6]_i_1__0_n_0\,
Q => \addr_step_q_reg_n_0_[6]\,
R => SR(0)
);
\addr_step_q_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => \addr_step_q[7]_i_1__0_n_0\,
Q => \addr_step_q_reg_n_0_[7]\,
R => SR(0)
);
\addr_step_q_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => \addr_step_q[8]_i_1__0_n_0\,
Q => \addr_step_q_reg_n_0_[8]\,
R => SR(0)
);
\addr_step_q_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => \addr_step_q[9]_i_1__0_n_0\,
Q => \addr_step_q_reg_n_0_[9]\,
R => SR(0)
);
\cmd_depth[0]_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cmd_depth_reg__0\(0),
O => \cmd_depth[0]_i_1__0_n_0\
);
\cmd_depth_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \USE_R_CHANNEL.cmd_queue_n_9\,
D => \cmd_depth[0]_i_1__0_n_0\,
Q => \cmd_depth_reg__0\(0),
R => SR(0)
);
\cmd_depth_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \USE_R_CHANNEL.cmd_queue_n_9\,
D => \USE_R_CHANNEL.cmd_queue_n_7\,
Q => \cmd_depth_reg__0\(1),
R => SR(0)
);
\cmd_depth_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \USE_R_CHANNEL.cmd_queue_n_9\,
D => \USE_R_CHANNEL.cmd_queue_n_6\,
Q => \cmd_depth_reg__0\(2),
R => SR(0)
);
\cmd_depth_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \USE_R_CHANNEL.cmd_queue_n_9\,
D => \USE_R_CHANNEL.cmd_queue_n_5\,
Q => \cmd_depth_reg__0\(3),
R => SR(0)
);
\cmd_depth_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \USE_R_CHANNEL.cmd_queue_n_9\,
D => \USE_R_CHANNEL.cmd_queue_n_4\,
Q => \cmd_depth_reg__0\(4),
R => SR(0)
);
\cmd_depth_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \USE_R_CHANNEL.cmd_queue_n_9\,
D => \USE_R_CHANNEL.cmd_queue_n_3\,
Q => \cmd_depth_reg__0\(5),
R => SR(0)
);
cmd_empty_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"E320"
)
port map (
I0 => almost_empty,
I1 => cmd_push,
I2 => rd_cmd_ready,
I3 => cmd_empty,
O => cmd_empty_i_1_n_0
);
\cmd_empty_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000100000000"
)
port map (
I0 => \cmd_depth_reg__0\(2),
I1 => \cmd_depth_reg__0\(3),
I2 => \cmd_depth_reg__0\(5),
I3 => \cmd_depth_reg__0\(4),
I4 => \cmd_depth_reg__0\(1),
I5 => \cmd_depth_reg__0\(0),
O => almost_empty
);
cmd_empty_reg: unisim.vcomponents.FDSE
port map (
C => aclk,
CE => '1',
D => cmd_empty_i_1_n_0,
Q => cmd_empty,
S => SR(0)
);
cmd_push_block_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \USE_R_CHANNEL.cmd_queue_n_15\,
Q => cmd_push_block,
R => '0'
);
command_ongoing_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \USE_R_CHANNEL.cmd_queue_n_16\,
Q => command_ongoing,
R => SR(0)
);
\first_step_q[0]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => s_axi_arsize(1),
I1 => s_axi_arsize(0),
I2 => s_axi_arlen(0),
I3 => s_axi_arsize(2),
O => \first_step_q[0]_i_1__0_n_0\
);
\first_step_q[10]_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => s_axi_arsize(2),
I1 => \first_step_q[10]_i_2__0_n_0\,
O => first_step(10)
);
\first_step_q[10]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"2AAA800080000000"
)
port map (
I0 => s_axi_arsize(1),
I1 => s_axi_arlen(2),
I2 => s_axi_arlen(0),
I3 => s_axi_arlen(1),
I4 => s_axi_arlen(3),
I5 => s_axi_arsize(0),
O => \first_step_q[10]_i_2__0_n_0\
);
\first_step_q[11]_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => s_axi_arsize(2),
I1 => \first_step_q[11]_i_2__0_n_0\,
O => first_step(11)
);
\first_step_q[11]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"8000000000000000"
)
port map (
I0 => s_axi_arsize(1),
I1 => s_axi_arlen(3),
I2 => s_axi_arlen(1),
I3 => s_axi_arlen(0),
I4 => s_axi_arlen(2),
I5 => s_axi_arsize(0),
O => \first_step_q[11]_i_2__0_n_0\
);
\first_step_q[1]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000514"
)
port map (
I0 => s_axi_arsize(1),
I1 => s_axi_arsize(0),
I2 => s_axi_arlen(0),
I3 => s_axi_arlen(1),
I4 => s_axi_arsize(2),
O => \first_step_q[1]_i_1__0_n_0\
);
\first_step_q[2]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000000F3C6A"
)
port map (
I0 => s_axi_arlen(2),
I1 => s_axi_arlen(1),
I2 => s_axi_arlen(0),
I3 => s_axi_arsize(0),
I4 => s_axi_arsize(1),
I5 => s_axi_arsize(2),
O => \first_step_q[2]_i_1__0_n_0\
);
\first_step_q[3]_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \first_step_q[7]_i_2__0_n_0\,
I1 => s_axi_arsize(2),
O => \first_step_q[3]_i_1__0_n_0\
);
\first_step_q[4]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"01FF0100"
)
port map (
I0 => s_axi_arlen(0),
I1 => s_axi_arsize(0),
I2 => s_axi_arsize(1),
I3 => s_axi_arsize(2),
I4 => \first_step_q[8]_i_2__0_n_0\,
O => first_step(4)
);
\first_step_q[5]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0036FFFF00360000"
)
port map (
I0 => s_axi_arlen(1),
I1 => s_axi_arlen(0),
I2 => s_axi_arsize(0),
I3 => s_axi_arsize(1),
I4 => s_axi_arsize(2),
I5 => \first_step_q[9]_i_2__0_n_0\,
O => first_step(5)
);
\first_step_q[6]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \first_step_q[6]_i_2__0_n_0\,
I1 => s_axi_arsize(2),
I2 => \first_step_q[10]_i_2__0_n_0\,
O => first_step(6)
);
\first_step_q[6]_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"07531642"
)
port map (
I0 => s_axi_arsize(1),
I1 => s_axi_arsize(0),
I2 => s_axi_arlen(0),
I3 => s_axi_arlen(1),
I4 => s_axi_arlen(2),
O => \first_step_q[6]_i_2__0_n_0\
);
\first_step_q[7]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \first_step_q[7]_i_2__0_n_0\,
I1 => s_axi_arsize(2),
I2 => \first_step_q[11]_i_2__0_n_0\,
O => first_step(7)
);
\first_step_q[7]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"07FD53B916EC42A8"
)
port map (
I0 => s_axi_arsize(1),
I1 => s_axi_arsize(0),
I2 => s_axi_arlen(1),
I3 => s_axi_arlen(0),
I4 => s_axi_arlen(2),
I5 => s_axi_arlen(3),
O => \first_step_q[7]_i_2__0_n_0\
);
\first_step_q[8]_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => s_axi_arsize(2),
I1 => \first_step_q[8]_i_2__0_n_0\,
O => first_step(8)
);
\first_step_q[8]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"14EAEA6262C8C840"
)
port map (
I0 => s_axi_arsize(1),
I1 => s_axi_arsize(0),
I2 => s_axi_arlen(3),
I3 => s_axi_arlen(1),
I4 => s_axi_arlen(0),
I5 => s_axi_arlen(2),
O => \first_step_q[8]_i_2__0_n_0\
);
\first_step_q[9]_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => s_axi_arsize(2),
I1 => \first_step_q[9]_i_2__0_n_0\,
O => first_step(9)
);
\first_step_q[9]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"4AA2A2A228808080"
)
port map (
I0 => s_axi_arsize(1),
I1 => s_axi_arsize(0),
I2 => s_axi_arlen(2),
I3 => s_axi_arlen(0),
I4 => s_axi_arlen(1),
I5 => s_axi_arlen(3),
O => \first_step_q[9]_i_2__0_n_0\
);
\first_step_q_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => \first_step_q[0]_i_1__0_n_0\,
Q => \first_step_q_reg_n_0_[0]\,
R => SR(0)
);
\first_step_q_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => first_step(10),
Q => \first_step_q_reg_n_0_[10]\,
R => SR(0)
);
\first_step_q_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => first_step(11),
Q => \first_step_q_reg_n_0_[11]\,
R => SR(0)
);
\first_step_q_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => \first_step_q[1]_i_1__0_n_0\,
Q => \first_step_q_reg_n_0_[1]\,
R => SR(0)
);
\first_step_q_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => \first_step_q[2]_i_1__0_n_0\,
Q => \first_step_q_reg_n_0_[2]\,
R => SR(0)
);
\first_step_q_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => \first_step_q[3]_i_1__0_n_0\,
Q => \first_step_q_reg_n_0_[3]\,
R => SR(0)
);
\first_step_q_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => first_step(4),
Q => \first_step_q_reg_n_0_[4]\,
R => SR(0)
);
\first_step_q_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => first_step(5),
Q => \first_step_q_reg_n_0_[5]\,
R => SR(0)
);
\first_step_q_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => first_step(6),
Q => \first_step_q_reg_n_0_[6]\,
R => SR(0)
);
\first_step_q_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => first_step(7),
Q => \first_step_q_reg_n_0_[7]\,
R => SR(0)
);
\first_step_q_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => first_step(8),
Q => \first_step_q_reg_n_0_[8]\,
R => SR(0)
);
\first_step_q_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => first_step(9),
Q => \first_step_q_reg_n_0_[9]\,
R => SR(0)
);
incr_need_to_split: unisim.vcomponents.LUT6
generic map(
INIT => X"4444444444444440"
)
port map (
I0 => s_axi_arburst(1),
I1 => s_axi_arburst(0),
I2 => s_axi_arlen(5),
I3 => s_axi_arlen(4),
I4 => s_axi_arlen(6),
I5 => s_axi_arlen(7),
O => \incr_need_to_split__0\
);
incr_need_to_split_q_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => \incr_need_to_split__0\,
Q => need_to_split_q,
R => SR(0)
);
\m_axi_araddr[0]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"8FFF8000"
)
port map (
I0 => size_mask_q(0),
I1 => next_mi_addr(0),
I2 => access_is_incr_q,
I3 => split_ongoing,
I4 => \S_AXI_AADDR_Q_reg_n_0_[0]\,
O => \^m_axi_araddr\(0)
);
\m_axi_araddr[10]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => \S_AXI_AADDR_Q_reg_n_0_[10]\,
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(10),
O => \^m_axi_araddr\(10)
);
\m_axi_araddr[11]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => \S_AXI_AADDR_Q_reg_n_0_[11]\,
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(11),
O => \^m_axi_araddr\(11)
);
\m_axi_araddr[12]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => \S_AXI_AADDR_Q_reg_n_0_[12]\,
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(12),
O => \^m_axi_araddr\(12)
);
\m_axi_araddr[13]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => \S_AXI_AADDR_Q_reg_n_0_[13]\,
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(13),
O => \^m_axi_araddr\(13)
);
\m_axi_araddr[14]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => \S_AXI_AADDR_Q_reg_n_0_[14]\,
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(14),
O => \^m_axi_araddr\(14)
);
\m_axi_araddr[15]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => \S_AXI_AADDR_Q_reg_n_0_[15]\,
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(15),
O => \^m_axi_araddr\(15)
);
\m_axi_araddr[16]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => \S_AXI_AADDR_Q_reg_n_0_[16]\,
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(16),
O => \^m_axi_araddr\(16)
);
\m_axi_araddr[17]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => \S_AXI_AADDR_Q_reg_n_0_[17]\,
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(17),
O => \^m_axi_araddr\(17)
);
\m_axi_araddr[18]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => \S_AXI_AADDR_Q_reg_n_0_[18]\,
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(18),
O => \^m_axi_araddr\(18)
);
\m_axi_araddr[19]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => \S_AXI_AADDR_Q_reg_n_0_[19]\,
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(19),
O => \^m_axi_araddr\(19)
);
\m_axi_araddr[1]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"8FFF8000"
)
port map (
I0 => size_mask_q(1),
I1 => next_mi_addr(1),
I2 => access_is_incr_q,
I3 => split_ongoing,
I4 => \S_AXI_AADDR_Q_reg_n_0_[1]\,
O => \^m_axi_araddr\(1)
);
\m_axi_araddr[20]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => \S_AXI_AADDR_Q_reg_n_0_[20]\,
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(20),
O => \^m_axi_araddr\(20)
);
\m_axi_araddr[21]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => \S_AXI_AADDR_Q_reg_n_0_[21]\,
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(21),
O => \^m_axi_araddr\(21)
);
\m_axi_araddr[22]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => \S_AXI_AADDR_Q_reg_n_0_[22]\,
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(22),
O => \^m_axi_araddr\(22)
);
\m_axi_araddr[23]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => \S_AXI_AADDR_Q_reg_n_0_[23]\,
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(23),
O => \^m_axi_araddr\(23)
);
\m_axi_araddr[24]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => \S_AXI_AADDR_Q_reg_n_0_[24]\,
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(24),
O => \^m_axi_araddr\(24)
);
\m_axi_araddr[25]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => \S_AXI_AADDR_Q_reg_n_0_[25]\,
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(25),
O => \^m_axi_araddr\(25)
);
\m_axi_araddr[26]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => \S_AXI_AADDR_Q_reg_n_0_[26]\,
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(26),
O => \^m_axi_araddr\(26)
);
\m_axi_araddr[27]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => \S_AXI_AADDR_Q_reg_n_0_[27]\,
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(27),
O => \^m_axi_araddr\(27)
);
\m_axi_araddr[28]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => \S_AXI_AADDR_Q_reg_n_0_[28]\,
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(28),
O => \^m_axi_araddr\(28)
);
\m_axi_araddr[29]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => \S_AXI_AADDR_Q_reg_n_0_[29]\,
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(29),
O => \^m_axi_araddr\(29)
);
\m_axi_araddr[2]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"8FFF8000"
)
port map (
I0 => size_mask_q(2),
I1 => next_mi_addr(2),
I2 => access_is_incr_q,
I3 => split_ongoing,
I4 => \S_AXI_AADDR_Q_reg_n_0_[2]\,
O => \^m_axi_araddr\(2)
);
\m_axi_araddr[30]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => \S_AXI_AADDR_Q_reg_n_0_[30]\,
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(30),
O => \^m_axi_araddr\(30)
);
\m_axi_araddr[31]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => \S_AXI_AADDR_Q_reg_n_0_[31]\,
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(31),
O => \^m_axi_araddr\(31)
);
\m_axi_araddr[3]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"8FFF8000"
)
port map (
I0 => size_mask_q(3),
I1 => next_mi_addr(3),
I2 => access_is_incr_q,
I3 => split_ongoing,
I4 => \S_AXI_AADDR_Q_reg_n_0_[3]\,
O => \^m_axi_araddr\(3)
);
\m_axi_araddr[4]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"8FFF8000"
)
port map (
I0 => size_mask_q(4),
I1 => next_mi_addr(4),
I2 => access_is_incr_q,
I3 => split_ongoing,
I4 => \S_AXI_AADDR_Q_reg_n_0_[4]\,
O => \^m_axi_araddr\(4)
);
\m_axi_araddr[5]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"8FFF8000"
)
port map (
I0 => size_mask_q(5),
I1 => next_mi_addr(5),
I2 => access_is_incr_q,
I3 => split_ongoing,
I4 => \S_AXI_AADDR_Q_reg_n_0_[5]\,
O => \^m_axi_araddr\(5)
);
\m_axi_araddr[6]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"8FFF8000"
)
port map (
I0 => size_mask_q(6),
I1 => next_mi_addr(6),
I2 => access_is_incr_q,
I3 => split_ongoing,
I4 => \S_AXI_AADDR_Q_reg_n_0_[6]\,
O => \^m_axi_araddr\(6)
);
\m_axi_araddr[7]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => \S_AXI_AADDR_Q_reg_n_0_[7]\,
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(7),
O => \^m_axi_araddr\(7)
);
\m_axi_araddr[8]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => \S_AXI_AADDR_Q_reg_n_0_[8]\,
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(8),
O => \^m_axi_araddr\(8)
);
\m_axi_araddr[9]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => \S_AXI_AADDR_Q_reg_n_0_[9]\,
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(9),
O => \^m_axi_araddr\(9)
);
\m_axi_arlen[0]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFEAAAAAAAA"
)
port map (
I0 => S_AXI_ALEN_Q(0),
I1 => \pushed_commands_reg__0\(1),
I2 => \pushed_commands_reg__0\(0),
I3 => \pushed_commands_reg__0\(3),
I4 => \pushed_commands_reg__0\(2),
I5 => need_to_split_q,
O => m_axi_arlen(0)
);
\m_axi_arlen[1]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFEAAAAAAAA"
)
port map (
I0 => S_AXI_ALEN_Q(1),
I1 => \pushed_commands_reg__0\(1),
I2 => \pushed_commands_reg__0\(0),
I3 => \pushed_commands_reg__0\(3),
I4 => \pushed_commands_reg__0\(2),
I5 => need_to_split_q,
O => m_axi_arlen(1)
);
\m_axi_arlen[2]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFEAAAAAAAA"
)
port map (
I0 => S_AXI_ALEN_Q(2),
I1 => \pushed_commands_reg__0\(1),
I2 => \pushed_commands_reg__0\(0),
I3 => \pushed_commands_reg__0\(3),
I4 => \pushed_commands_reg__0\(2),
I5 => need_to_split_q,
O => m_axi_arlen(2)
);
\m_axi_arlen[3]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFEAAAAAAAA"
)
port map (
I0 => S_AXI_ALEN_Q(3),
I1 => \pushed_commands_reg__0\(1),
I2 => \pushed_commands_reg__0\(0),
I3 => \pushed_commands_reg__0\(3),
I4 => \pushed_commands_reg__0\(2),
I5 => need_to_split_q,
O => m_axi_arlen(3)
);
\m_axi_arlock[0]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \S_AXI_ALOCK_Q_reg_n_0_[0]\,
I1 => need_to_split_q,
O => m_axi_arlock(0)
);
\multiple_id_non_split_i_2__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => split_in_progress_reg_n_0,
I1 => cmd_empty,
O => \multiple_id_non_split_i_2__0_n_0\
);
multiple_id_non_split_i_3: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(0),
I1 => \queue_id_reg_n_0_[0]\,
I2 => \^q\(1),
I3 => \queue_id_reg_n_0_[1]\,
O => multiple_id_non_split_i_3_n_0
);
multiple_id_non_split_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \USE_R_CHANNEL.cmd_queue_n_18\,
Q => multiple_id_non_split,
R => '0'
);
\next_mi_addr[11]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"56A6"
)
port map (
I0 => \^m_axi_araddr\(11),
I1 => \addr_step_q_reg_n_0_[11]\,
I2 => \next_mi_addr[11]_i_6__0_n_0\,
I3 => \first_step_q_reg_n_0_[11]\,
O => \next_mi_addr[11]_i_2_n_0\
);
\next_mi_addr[11]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"56A6"
)
port map (
I0 => \^m_axi_araddr\(10),
I1 => \addr_step_q_reg_n_0_[10]\,
I2 => \next_mi_addr[11]_i_6__0_n_0\,
I3 => \first_step_q_reg_n_0_[10]\,
O => \next_mi_addr[11]_i_3_n_0\
);
\next_mi_addr[11]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"56A6"
)
port map (
I0 => \^m_axi_araddr\(9),
I1 => \addr_step_q_reg_n_0_[9]\,
I2 => \next_mi_addr[11]_i_6__0_n_0\,
I3 => \first_step_q_reg_n_0_[9]\,
O => \next_mi_addr[11]_i_4_n_0\
);
\next_mi_addr[11]_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"56A6"
)
port map (
I0 => \^m_axi_araddr\(8),
I1 => \addr_step_q_reg_n_0_[8]\,
I2 => \next_mi_addr[11]_i_6__0_n_0\,
I3 => \first_step_q_reg_n_0_[8]\,
O => \next_mi_addr[11]_i_5_n_0\
);
\next_mi_addr[11]_i_6__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => \pushed_commands_reg__0\(1),
I1 => \pushed_commands_reg__0\(0),
I2 => \pushed_commands_reg__0\(3),
I3 => \pushed_commands_reg__0\(2),
O => \next_mi_addr[11]_i_6__0_n_0\
);
\next_mi_addr[15]_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => \S_AXI_AADDR_Q_reg_n_0_[15]\,
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(15),
O => \next_mi_addr[15]_i_2__0_n_0\
);
\next_mi_addr[15]_i_3__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => \S_AXI_AADDR_Q_reg_n_0_[14]\,
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(14),
O => \next_mi_addr[15]_i_3__0_n_0\
);
\next_mi_addr[15]_i_4__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => \S_AXI_AADDR_Q_reg_n_0_[13]\,
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(13),
O => \next_mi_addr[15]_i_4__0_n_0\
);
\next_mi_addr[15]_i_5__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => \S_AXI_AADDR_Q_reg_n_0_[12]\,
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(12),
O => \next_mi_addr[15]_i_5__0_n_0\
);
\next_mi_addr[15]_i_6__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => \S_AXI_AADDR_Q_reg_n_0_[15]\,
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(15),
O => \next_mi_addr[15]_i_6__0_n_0\
);
\next_mi_addr[15]_i_7__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => \S_AXI_AADDR_Q_reg_n_0_[14]\,
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(14),
O => \next_mi_addr[15]_i_7__0_n_0\
);
\next_mi_addr[15]_i_8__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => \S_AXI_AADDR_Q_reg_n_0_[13]\,
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(13),
O => \next_mi_addr[15]_i_8__0_n_0\
);
\next_mi_addr[15]_i_9__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => \S_AXI_AADDR_Q_reg_n_0_[12]\,
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(12),
O => \next_mi_addr[15]_i_9__0_n_0\
);
\next_mi_addr[19]_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => \S_AXI_AADDR_Q_reg_n_0_[19]\,
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(19),
O => \next_mi_addr[19]_i_2__0_n_0\
);
\next_mi_addr[19]_i_3__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => \S_AXI_AADDR_Q_reg_n_0_[18]\,
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(18),
O => \next_mi_addr[19]_i_3__0_n_0\
);
\next_mi_addr[19]_i_4__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => \S_AXI_AADDR_Q_reg_n_0_[17]\,
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(17),
O => \next_mi_addr[19]_i_4__0_n_0\
);
\next_mi_addr[19]_i_5__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => \S_AXI_AADDR_Q_reg_n_0_[16]\,
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(16),
O => \next_mi_addr[19]_i_5__0_n_0\
);
\next_mi_addr[23]_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => \S_AXI_AADDR_Q_reg_n_0_[23]\,
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(23),
O => \next_mi_addr[23]_i_2__0_n_0\
);
\next_mi_addr[23]_i_3__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => \S_AXI_AADDR_Q_reg_n_0_[22]\,
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(22),
O => \next_mi_addr[23]_i_3__0_n_0\
);
\next_mi_addr[23]_i_4__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => \S_AXI_AADDR_Q_reg_n_0_[21]\,
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(21),
O => \next_mi_addr[23]_i_4__0_n_0\
);
\next_mi_addr[23]_i_5__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => \S_AXI_AADDR_Q_reg_n_0_[20]\,
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(20),
O => \next_mi_addr[23]_i_5__0_n_0\
);
\next_mi_addr[27]_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => \S_AXI_AADDR_Q_reg_n_0_[27]\,
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(27),
O => \next_mi_addr[27]_i_2__0_n_0\
);
\next_mi_addr[27]_i_3__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => \S_AXI_AADDR_Q_reg_n_0_[26]\,
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(26),
O => \next_mi_addr[27]_i_3__0_n_0\
);
\next_mi_addr[27]_i_4__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => \S_AXI_AADDR_Q_reg_n_0_[25]\,
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(25),
O => \next_mi_addr[27]_i_4__0_n_0\
);
\next_mi_addr[27]_i_5__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => \S_AXI_AADDR_Q_reg_n_0_[24]\,
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(24),
O => \next_mi_addr[27]_i_5__0_n_0\
);
\next_mi_addr[31]_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => \S_AXI_AADDR_Q_reg_n_0_[31]\,
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(31),
O => \next_mi_addr[31]_i_2__0_n_0\
);
\next_mi_addr[31]_i_3__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => \S_AXI_AADDR_Q_reg_n_0_[30]\,
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(30),
O => \next_mi_addr[31]_i_3__0_n_0\
);
\next_mi_addr[31]_i_4__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => \S_AXI_AADDR_Q_reg_n_0_[29]\,
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(29),
O => \next_mi_addr[31]_i_4__0_n_0\
);
\next_mi_addr[31]_i_5__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAAA0AAA"
)
port map (
I0 => \S_AXI_AADDR_Q_reg_n_0_[28]\,
I1 => size_mask_q(31),
I2 => split_ongoing,
I3 => access_is_incr_q,
I4 => next_mi_addr(28),
O => \next_mi_addr[31]_i_5__0_n_0\
);
\next_mi_addr[3]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"1DDDE222E222E222"
)
port map (
I0 => \S_AXI_AADDR_Q_reg_n_0_[3]\,
I1 => \next_mi_addr[3]_i_6__0_n_0\,
I2 => next_mi_addr(3),
I3 => size_mask_q(3),
I4 => \next_mi_addr[11]_i_6__0_n_0\,
I5 => \first_step_q_reg_n_0_[3]\,
O => \next_mi_addr[3]_i_2_n_0\
);
\next_mi_addr[3]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"1DDDE222E222E222"
)
port map (
I0 => \S_AXI_AADDR_Q_reg_n_0_[2]\,
I1 => \next_mi_addr[3]_i_6__0_n_0\,
I2 => next_mi_addr(2),
I3 => size_mask_q(2),
I4 => \next_mi_addr[11]_i_6__0_n_0\,
I5 => \first_step_q_reg_n_0_[2]\,
O => \next_mi_addr[3]_i_3_n_0\
);
\next_mi_addr[3]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"1DDDE222E222E222"
)
port map (
I0 => \S_AXI_AADDR_Q_reg_n_0_[1]\,
I1 => \next_mi_addr[3]_i_6__0_n_0\,
I2 => next_mi_addr(1),
I3 => size_mask_q(1),
I4 => \next_mi_addr[11]_i_6__0_n_0\,
I5 => \first_step_q_reg_n_0_[1]\,
O => \next_mi_addr[3]_i_4_n_0\
);
\next_mi_addr[3]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"1DDDE222E222E222"
)
port map (
I0 => \S_AXI_AADDR_Q_reg_n_0_[0]\,
I1 => \next_mi_addr[3]_i_6__0_n_0\,
I2 => next_mi_addr(0),
I3 => size_mask_q(0),
I4 => \next_mi_addr[11]_i_6__0_n_0\,
I5 => \first_step_q_reg_n_0_[0]\,
O => \next_mi_addr[3]_i_5_n_0\
);
\next_mi_addr[3]_i_6__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => access_is_incr_q,
I1 => split_ongoing,
O => \next_mi_addr[3]_i_6__0_n_0\
);
\next_mi_addr[7]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"56A6"
)
port map (
I0 => \^m_axi_araddr\(7),
I1 => \addr_step_q_reg_n_0_[7]\,
I2 => \next_mi_addr[11]_i_6__0_n_0\,
I3 => \first_step_q_reg_n_0_[7]\,
O => \next_mi_addr[7]_i_2_n_0\
);
\next_mi_addr[7]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"56A6"
)
port map (
I0 => \^m_axi_araddr\(6),
I1 => \addr_step_q_reg_n_0_[6]\,
I2 => \next_mi_addr[11]_i_6__0_n_0\,
I3 => \first_step_q_reg_n_0_[6]\,
O => \next_mi_addr[7]_i_3_n_0\
);
\next_mi_addr[7]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"56A6"
)
port map (
I0 => \^m_axi_araddr\(5),
I1 => \addr_step_q_reg_n_0_[5]\,
I2 => \next_mi_addr[11]_i_6__0_n_0\,
I3 => \first_step_q_reg_n_0_[5]\,
O => \next_mi_addr[7]_i_4_n_0\
);
\next_mi_addr[7]_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"56A6"
)
port map (
I0 => \^m_axi_araddr\(4),
I1 => size_mask_q(0),
I2 => \next_mi_addr[11]_i_6__0_n_0\,
I3 => \first_step_q_reg_n_0_[4]\,
O => \next_mi_addr[7]_i_5_n_0\
);
\next_mi_addr_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => pushed_new_cmd,
D => \next_mi_addr_reg[3]_i_1__0_n_7\,
Q => next_mi_addr(0),
R => SR(0)
);
\next_mi_addr_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => pushed_new_cmd,
D => \next_mi_addr_reg[11]_i_1__0_n_5\,
Q => next_mi_addr(10),
R => SR(0)
);
\next_mi_addr_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => pushed_new_cmd,
D => \next_mi_addr_reg[11]_i_1__0_n_4\,
Q => next_mi_addr(11),
R => SR(0)
);
\next_mi_addr_reg[11]_i_1__0\: unisim.vcomponents.CARRY4
port map (
CI => \next_mi_addr_reg[7]_i_1__0_n_0\,
CO(3) => \next_mi_addr_reg[11]_i_1__0_n_0\,
CO(2) => \next_mi_addr_reg[11]_i_1__0_n_1\,
CO(1) => \next_mi_addr_reg[11]_i_1__0_n_2\,
CO(0) => \next_mi_addr_reg[11]_i_1__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => \^m_axi_araddr\(11 downto 8),
O(3) => \next_mi_addr_reg[11]_i_1__0_n_4\,
O(2) => \next_mi_addr_reg[11]_i_1__0_n_5\,
O(1) => \next_mi_addr_reg[11]_i_1__0_n_6\,
O(0) => \next_mi_addr_reg[11]_i_1__0_n_7\,
S(3) => \next_mi_addr[11]_i_2_n_0\,
S(2) => \next_mi_addr[11]_i_3_n_0\,
S(1) => \next_mi_addr[11]_i_4_n_0\,
S(0) => \next_mi_addr[11]_i_5_n_0\
);
\next_mi_addr_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => pushed_new_cmd,
D => \next_mi_addr_reg[15]_i_1__0_n_7\,
Q => next_mi_addr(12),
R => SR(0)
);
\next_mi_addr_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => pushed_new_cmd,
D => \next_mi_addr_reg[15]_i_1__0_n_6\,
Q => next_mi_addr(13),
R => SR(0)
);
\next_mi_addr_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => pushed_new_cmd,
D => \next_mi_addr_reg[15]_i_1__0_n_5\,
Q => next_mi_addr(14),
R => SR(0)
);
\next_mi_addr_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => pushed_new_cmd,
D => \next_mi_addr_reg[15]_i_1__0_n_4\,
Q => next_mi_addr(15),
R => SR(0)
);
\next_mi_addr_reg[15]_i_1__0\: unisim.vcomponents.CARRY4
port map (
CI => \next_mi_addr_reg[11]_i_1__0_n_0\,
CO(3) => \next_mi_addr_reg[15]_i_1__0_n_0\,
CO(2) => \next_mi_addr_reg[15]_i_1__0_n_1\,
CO(1) => \next_mi_addr_reg[15]_i_1__0_n_2\,
CO(0) => \next_mi_addr_reg[15]_i_1__0_n_3\,
CYINIT => '0',
DI(3) => \next_mi_addr[15]_i_2__0_n_0\,
DI(2) => \next_mi_addr[15]_i_3__0_n_0\,
DI(1) => \next_mi_addr[15]_i_4__0_n_0\,
DI(0) => \next_mi_addr[15]_i_5__0_n_0\,
O(3) => \next_mi_addr_reg[15]_i_1__0_n_4\,
O(2) => \next_mi_addr_reg[15]_i_1__0_n_5\,
O(1) => \next_mi_addr_reg[15]_i_1__0_n_6\,
O(0) => \next_mi_addr_reg[15]_i_1__0_n_7\,
S(3) => \next_mi_addr[15]_i_6__0_n_0\,
S(2) => \next_mi_addr[15]_i_7__0_n_0\,
S(1) => \next_mi_addr[15]_i_8__0_n_0\,
S(0) => \next_mi_addr[15]_i_9__0_n_0\
);
\next_mi_addr_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => pushed_new_cmd,
D => \next_mi_addr_reg[19]_i_1__0_n_7\,
Q => next_mi_addr(16),
R => SR(0)
);
\next_mi_addr_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => pushed_new_cmd,
D => \next_mi_addr_reg[19]_i_1__0_n_6\,
Q => next_mi_addr(17),
R => SR(0)
);
\next_mi_addr_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => pushed_new_cmd,
D => \next_mi_addr_reg[19]_i_1__0_n_5\,
Q => next_mi_addr(18),
R => SR(0)
);
\next_mi_addr_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => pushed_new_cmd,
D => \next_mi_addr_reg[19]_i_1__0_n_4\,
Q => next_mi_addr(19),
R => SR(0)
);
\next_mi_addr_reg[19]_i_1__0\: unisim.vcomponents.CARRY4
port map (
CI => \next_mi_addr_reg[15]_i_1__0_n_0\,
CO(3) => \next_mi_addr_reg[19]_i_1__0_n_0\,
CO(2) => \next_mi_addr_reg[19]_i_1__0_n_1\,
CO(1) => \next_mi_addr_reg[19]_i_1__0_n_2\,
CO(0) => \next_mi_addr_reg[19]_i_1__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \next_mi_addr_reg[19]_i_1__0_n_4\,
O(2) => \next_mi_addr_reg[19]_i_1__0_n_5\,
O(1) => \next_mi_addr_reg[19]_i_1__0_n_6\,
O(0) => \next_mi_addr_reg[19]_i_1__0_n_7\,
S(3) => \next_mi_addr[19]_i_2__0_n_0\,
S(2) => \next_mi_addr[19]_i_3__0_n_0\,
S(1) => \next_mi_addr[19]_i_4__0_n_0\,
S(0) => \next_mi_addr[19]_i_5__0_n_0\
);
\next_mi_addr_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => pushed_new_cmd,
D => \next_mi_addr_reg[3]_i_1__0_n_6\,
Q => next_mi_addr(1),
R => SR(0)
);
\next_mi_addr_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => pushed_new_cmd,
D => \next_mi_addr_reg[23]_i_1__0_n_7\,
Q => next_mi_addr(20),
R => SR(0)
);
\next_mi_addr_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => pushed_new_cmd,
D => \next_mi_addr_reg[23]_i_1__0_n_6\,
Q => next_mi_addr(21),
R => SR(0)
);
\next_mi_addr_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => pushed_new_cmd,
D => \next_mi_addr_reg[23]_i_1__0_n_5\,
Q => next_mi_addr(22),
R => SR(0)
);
\next_mi_addr_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => pushed_new_cmd,
D => \next_mi_addr_reg[23]_i_1__0_n_4\,
Q => next_mi_addr(23),
R => SR(0)
);
\next_mi_addr_reg[23]_i_1__0\: unisim.vcomponents.CARRY4
port map (
CI => \next_mi_addr_reg[19]_i_1__0_n_0\,
CO(3) => \next_mi_addr_reg[23]_i_1__0_n_0\,
CO(2) => \next_mi_addr_reg[23]_i_1__0_n_1\,
CO(1) => \next_mi_addr_reg[23]_i_1__0_n_2\,
CO(0) => \next_mi_addr_reg[23]_i_1__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \next_mi_addr_reg[23]_i_1__0_n_4\,
O(2) => \next_mi_addr_reg[23]_i_1__0_n_5\,
O(1) => \next_mi_addr_reg[23]_i_1__0_n_6\,
O(0) => \next_mi_addr_reg[23]_i_1__0_n_7\,
S(3) => \next_mi_addr[23]_i_2__0_n_0\,
S(2) => \next_mi_addr[23]_i_3__0_n_0\,
S(1) => \next_mi_addr[23]_i_4__0_n_0\,
S(0) => \next_mi_addr[23]_i_5__0_n_0\
);
\next_mi_addr_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => pushed_new_cmd,
D => \next_mi_addr_reg[27]_i_1__0_n_7\,
Q => next_mi_addr(24),
R => SR(0)
);
\next_mi_addr_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => pushed_new_cmd,
D => \next_mi_addr_reg[27]_i_1__0_n_6\,
Q => next_mi_addr(25),
R => SR(0)
);
\next_mi_addr_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => pushed_new_cmd,
D => \next_mi_addr_reg[27]_i_1__0_n_5\,
Q => next_mi_addr(26),
R => SR(0)
);
\next_mi_addr_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => pushed_new_cmd,
D => \next_mi_addr_reg[27]_i_1__0_n_4\,
Q => next_mi_addr(27),
R => SR(0)
);
\next_mi_addr_reg[27]_i_1__0\: unisim.vcomponents.CARRY4
port map (
CI => \next_mi_addr_reg[23]_i_1__0_n_0\,
CO(3) => \next_mi_addr_reg[27]_i_1__0_n_0\,
CO(2) => \next_mi_addr_reg[27]_i_1__0_n_1\,
CO(1) => \next_mi_addr_reg[27]_i_1__0_n_2\,
CO(0) => \next_mi_addr_reg[27]_i_1__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \next_mi_addr_reg[27]_i_1__0_n_4\,
O(2) => \next_mi_addr_reg[27]_i_1__0_n_5\,
O(1) => \next_mi_addr_reg[27]_i_1__0_n_6\,
O(0) => \next_mi_addr_reg[27]_i_1__0_n_7\,
S(3) => \next_mi_addr[27]_i_2__0_n_0\,
S(2) => \next_mi_addr[27]_i_3__0_n_0\,
S(1) => \next_mi_addr[27]_i_4__0_n_0\,
S(0) => \next_mi_addr[27]_i_5__0_n_0\
);
\next_mi_addr_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => pushed_new_cmd,
D => \next_mi_addr_reg[31]_i_1__0_n_7\,
Q => next_mi_addr(28),
R => SR(0)
);
\next_mi_addr_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => pushed_new_cmd,
D => \next_mi_addr_reg[31]_i_1__0_n_6\,
Q => next_mi_addr(29),
R => SR(0)
);
\next_mi_addr_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => pushed_new_cmd,
D => \next_mi_addr_reg[3]_i_1__0_n_5\,
Q => next_mi_addr(2),
R => SR(0)
);
\next_mi_addr_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => pushed_new_cmd,
D => \next_mi_addr_reg[31]_i_1__0_n_5\,
Q => next_mi_addr(30),
R => SR(0)
);
\next_mi_addr_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => pushed_new_cmd,
D => \next_mi_addr_reg[31]_i_1__0_n_4\,
Q => next_mi_addr(31),
R => SR(0)
);
\next_mi_addr_reg[31]_i_1__0\: unisim.vcomponents.CARRY4
port map (
CI => \next_mi_addr_reg[27]_i_1__0_n_0\,
CO(3) => \NLW_next_mi_addr_reg[31]_i_1__0_CO_UNCONNECTED\(3),
CO(2) => \next_mi_addr_reg[31]_i_1__0_n_1\,
CO(1) => \next_mi_addr_reg[31]_i_1__0_n_2\,
CO(0) => \next_mi_addr_reg[31]_i_1__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \next_mi_addr_reg[31]_i_1__0_n_4\,
O(2) => \next_mi_addr_reg[31]_i_1__0_n_5\,
O(1) => \next_mi_addr_reg[31]_i_1__0_n_6\,
O(0) => \next_mi_addr_reg[31]_i_1__0_n_7\,
S(3) => \next_mi_addr[31]_i_2__0_n_0\,
S(2) => \next_mi_addr[31]_i_3__0_n_0\,
S(1) => \next_mi_addr[31]_i_4__0_n_0\,
S(0) => \next_mi_addr[31]_i_5__0_n_0\
);
\next_mi_addr_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => pushed_new_cmd,
D => \next_mi_addr_reg[3]_i_1__0_n_4\,
Q => next_mi_addr(3),
R => SR(0)
);
\next_mi_addr_reg[3]_i_1__0\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \next_mi_addr_reg[3]_i_1__0_n_0\,
CO(2) => \next_mi_addr_reg[3]_i_1__0_n_1\,
CO(1) => \next_mi_addr_reg[3]_i_1__0_n_2\,
CO(0) => \next_mi_addr_reg[3]_i_1__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => \^m_axi_araddr\(3 downto 0),
O(3) => \next_mi_addr_reg[3]_i_1__0_n_4\,
O(2) => \next_mi_addr_reg[3]_i_1__0_n_5\,
O(1) => \next_mi_addr_reg[3]_i_1__0_n_6\,
O(0) => \next_mi_addr_reg[3]_i_1__0_n_7\,
S(3) => \next_mi_addr[3]_i_2_n_0\,
S(2) => \next_mi_addr[3]_i_3_n_0\,
S(1) => \next_mi_addr[3]_i_4_n_0\,
S(0) => \next_mi_addr[3]_i_5_n_0\
);
\next_mi_addr_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => pushed_new_cmd,
D => \next_mi_addr_reg[7]_i_1__0_n_7\,
Q => next_mi_addr(4),
R => SR(0)
);
\next_mi_addr_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => pushed_new_cmd,
D => \next_mi_addr_reg[7]_i_1__0_n_6\,
Q => next_mi_addr(5),
R => SR(0)
);
\next_mi_addr_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => pushed_new_cmd,
D => \next_mi_addr_reg[7]_i_1__0_n_5\,
Q => next_mi_addr(6),
R => SR(0)
);
\next_mi_addr_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => pushed_new_cmd,
D => \next_mi_addr_reg[7]_i_1__0_n_4\,
Q => next_mi_addr(7),
R => SR(0)
);
\next_mi_addr_reg[7]_i_1__0\: unisim.vcomponents.CARRY4
port map (
CI => \next_mi_addr_reg[3]_i_1__0_n_0\,
CO(3) => \next_mi_addr_reg[7]_i_1__0_n_0\,
CO(2) => \next_mi_addr_reg[7]_i_1__0_n_1\,
CO(1) => \next_mi_addr_reg[7]_i_1__0_n_2\,
CO(0) => \next_mi_addr_reg[7]_i_1__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => \^m_axi_araddr\(7 downto 4),
O(3) => \next_mi_addr_reg[7]_i_1__0_n_4\,
O(2) => \next_mi_addr_reg[7]_i_1__0_n_5\,
O(1) => \next_mi_addr_reg[7]_i_1__0_n_6\,
O(0) => \next_mi_addr_reg[7]_i_1__0_n_7\,
S(3) => \next_mi_addr[7]_i_2_n_0\,
S(2) => \next_mi_addr[7]_i_3_n_0\,
S(1) => \next_mi_addr[7]_i_4_n_0\,
S(0) => \next_mi_addr[7]_i_5_n_0\
);
\next_mi_addr_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => pushed_new_cmd,
D => \next_mi_addr_reg[11]_i_1__0_n_7\,
Q => next_mi_addr(8),
R => SR(0)
);
\next_mi_addr_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => pushed_new_cmd,
D => \next_mi_addr_reg[11]_i_1__0_n_6\,
Q => next_mi_addr(9),
R => SR(0)
);
\num_transactions_q_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_arlen(4),
Q => \num_transactions_q_reg_n_0_[0]\,
R => SR(0)
);
\num_transactions_q_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_arlen(5),
Q => \num_transactions_q_reg_n_0_[1]\,
R => SR(0)
);
\num_transactions_q_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_arlen(6),
Q => \num_transactions_q_reg_n_0_[2]\,
R => SR(0)
);
\num_transactions_q_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => s_axi_arlen(7),
Q => \num_transactions_q_reg_n_0_[3]\,
R => SR(0)
);
\pushed_commands[0]_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \pushed_commands_reg__0\(0),
O => \p_0_in__0\(0)
);
\pushed_commands[1]_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \pushed_commands_reg__0\(0),
I1 => \pushed_commands_reg__0\(1),
O => \p_0_in__0\(1)
);
\pushed_commands[2]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => \pushed_commands_reg__0\(2),
I1 => \pushed_commands_reg__0\(1),
I2 => \pushed_commands_reg__0\(0),
O => \p_0_in__0\(2)
);
\pushed_commands[3]_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \^e\(0),
I1 => aresetn,
O => \pushed_commands[3]_i_1__0_n_0\
);
\pushed_commands[3]_i_2__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => \pushed_commands_reg__0\(3),
I1 => \pushed_commands_reg__0\(0),
I2 => \pushed_commands_reg__0\(1),
I3 => \pushed_commands_reg__0\(2),
O => \p_0_in__0\(3)
);
\pushed_commands_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => pushed_new_cmd,
D => \p_0_in__0\(0),
Q => \pushed_commands_reg__0\(0),
R => \pushed_commands[3]_i_1__0_n_0\
);
\pushed_commands_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => pushed_new_cmd,
D => \p_0_in__0\(1),
Q => \pushed_commands_reg__0\(1),
R => \pushed_commands[3]_i_1__0_n_0\
);
\pushed_commands_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => pushed_new_cmd,
D => \p_0_in__0\(2),
Q => \pushed_commands_reg__0\(2),
R => \pushed_commands[3]_i_1__0_n_0\
);
\pushed_commands_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => pushed_new_cmd,
D => \p_0_in__0\(3),
Q => \pushed_commands_reg__0\(3),
R => \pushed_commands[3]_i_1__0_n_0\
);
\queue_id[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^q\(0),
I1 => cmd_push,
I2 => \queue_id_reg_n_0_[0]\,
O => \queue_id[0]_i_1_n_0\
);
\queue_id[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^q\(1),
I1 => cmd_push,
I2 => \queue_id_reg_n_0_[1]\,
O => \queue_id[1]_i_1_n_0\
);
\queue_id_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \queue_id[0]_i_1_n_0\,
Q => \queue_id_reg_n_0_[0]\,
R => SR(0)
);
\queue_id_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \queue_id[1]_i_1_n_0\,
Q => \queue_id_reg_n_0_[1]\,
R => SR(0)
);
\size_mask_q[0]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"01"
)
port map (
I0 => s_axi_arsize(2),
I1 => s_axi_arsize(0),
I2 => s_axi_arsize(1),
O => \size_mask_q[0]_i_1__0_n_0\
);
\size_mask_q[1]_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => s_axi_arsize(2),
I1 => s_axi_arsize(1),
O => \size_mask_q[1]_i_1__0_n_0\
);
\size_mask_q[2]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"07"
)
port map (
I0 => s_axi_arsize(0),
I1 => s_axi_arsize(1),
I2 => s_axi_arsize(2),
O => \size_mask_q[2]_i_1__0_n_0\
);
\size_mask_q[3]_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => s_axi_arsize(2),
O => \size_mask_q[3]_i_1__0_n_0\
);
\size_mask_q[4]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"57"
)
port map (
I0 => s_axi_arsize(2),
I1 => s_axi_arsize(0),
I2 => s_axi_arsize(1),
O => \size_mask_q[4]_i_1__0_n_0\
);
\size_mask_q[5]_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => s_axi_arsize(2),
I1 => s_axi_arsize(1),
O => \size_mask_q[5]_i_1__0_n_0\
);
\size_mask_q[6]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"7F"
)
port map (
I0 => s_axi_arsize(2),
I1 => s_axi_arsize(0),
I2 => s_axi_arsize(1),
O => \size_mask_q[6]_i_1__0_n_0\
);
\size_mask_q_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => \size_mask_q[0]_i_1__0_n_0\,
Q => size_mask_q(0),
R => SR(0)
);
\size_mask_q_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => \size_mask_q[1]_i_1__0_n_0\,
Q => size_mask_q(1),
R => SR(0)
);
\size_mask_q_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => \size_mask_q[2]_i_1__0_n_0\,
Q => size_mask_q(2),
R => SR(0)
);
\size_mask_q_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => '1',
Q => size_mask_q(31),
R => SR(0)
);
\size_mask_q_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => \size_mask_q[3]_i_1__0_n_0\,
Q => size_mask_q(3),
R => SR(0)
);
\size_mask_q_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => \size_mask_q[4]_i_1__0_n_0\,
Q => size_mask_q(4),
R => SR(0)
);
\size_mask_q_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => \size_mask_q[5]_i_1__0_n_0\,
Q => size_mask_q(5),
R => SR(0)
);
\size_mask_q_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => \size_mask_q[6]_i_1__0_n_0\,
Q => size_mask_q(6),
R => SR(0)
);
split_in_progress_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \USE_R_CHANNEL.cmd_queue_n_17\,
Q => split_in_progress_reg_n_0,
R => '0'
);
split_ongoing_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => pushed_new_cmd,
D => \USE_R_CHANNEL.cmd_queue_n_0\,
Q => split_ongoing,
R => SR(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_pc_1_axi_protocol_converter_v2_1_11_axi3_conv is
port (
Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awready : out STD_LOGIC;
m_axi_wid : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_bready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arready : out STD_LOGIC;
\m_axi_arid[1]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_bvalid : out STD_LOGIC;
m_axi_awvalid : out STD_LOGIC;
s_axi_wready : out STD_LOGIC;
m_axi_wlast : out STD_LOGIC;
m_axi_wvalid : out STD_LOGIC;
m_axi_arvalid : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rlast : out STD_LOGIC;
m_axi_rready : out STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awready : in STD_LOGIC;
aclk : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arid : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_bvalid : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_rlast : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_pc_1_axi_protocol_converter_v2_1_11_axi3_conv : entity is "axi_protocol_converter_v2_1_11_axi3_conv";
end system_auto_pc_1_axi_protocol_converter_v2_1_11_axi3_conv;
architecture STRUCTURE of system_auto_pc_1_axi_protocol_converter_v2_1_11_axi3_conv is
signal \USE_BURSTS.cmd_queue/inst/empty\ : STD_LOGIC;
signal \USE_B_CHANNEL.cmd_b_queue/inst/empty\ : STD_LOGIC;
signal \USE_WRITE.USE_SPLIT_W.write_resp_inst_n_2\ : STD_LOGIC;
signal \USE_WRITE.write_addr_inst_n_56\ : STD_LOGIC;
signal \USE_WRITE.write_addr_inst_n_59\ : STD_LOGIC;
signal \USE_WRITE.write_addr_inst_n_7\ : STD_LOGIC;
signal areset_d : STD_LOGIC_VECTOR ( 1 downto 0 );
signal first_mi_word : STD_LOGIC;
signal length_counter_1_reg : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^s_axi_wready\ : STD_LOGIC;
signal wr_cmd_b_ready : STD_LOGIC;
signal wr_cmd_b_repeat : STD_LOGIC_VECTOR ( 3 downto 0 );
signal wr_cmd_b_split : STD_LOGIC;
signal wr_cmd_length : STD_LOGIC_VECTOR ( 3 downto 0 );
signal wr_cmd_ready : STD_LOGIC;
begin
s_axi_wready <= \^s_axi_wready\;
\USE_READ.USE_SPLIT_R.read_addr_inst\: entity work.\system_auto_pc_1_axi_protocol_converter_v2_1_11_a_axi3_conv__parameterized0\
port map (
E(0) => s_axi_arready,
Q(1 downto 0) => \m_axi_arid[1]\(1 downto 0),
SR(0) => \USE_WRITE.write_addr_inst_n_7\,
aclk => aclk,
areset_d(1 downto 0) => areset_d(1 downto 0),
\areset_d_reg[1]\ => \USE_WRITE.write_addr_inst_n_59\,
aresetn => aresetn,
m_axi_araddr(31 downto 0) => m_axi_araddr(31 downto 0),
m_axi_arburst(1 downto 0) => m_axi_arburst(1 downto 0),
m_axi_arcache(3 downto 0) => m_axi_arcache(3 downto 0),
m_axi_arlen(3 downto 0) => m_axi_arlen(3 downto 0),
m_axi_arlock(0) => m_axi_arlock(0),
m_axi_arprot(2 downto 0) => m_axi_arprot(2 downto 0),
m_axi_arqos(3 downto 0) => m_axi_arqos(3 downto 0),
m_axi_arready => m_axi_arready,
m_axi_arsize(2 downto 0) => m_axi_arsize(2 downto 0),
m_axi_arvalid => m_axi_arvalid,
m_axi_rlast => m_axi_rlast,
m_axi_rready => m_axi_rready,
m_axi_rvalid => m_axi_rvalid,
s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0),
s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
s_axi_arcache(3 downto 0) => s_axi_arcache(3 downto 0),
s_axi_arid(1 downto 0) => s_axi_arid(1 downto 0),
s_axi_arlen(7 downto 0) => s_axi_arlen(7 downto 0),
s_axi_arlock(0) => s_axi_arlock(0),
s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0),
s_axi_arqos(3 downto 0) => s_axi_arqos(3 downto 0),
s_axi_arsize(2 downto 0) => s_axi_arsize(2 downto 0),
s_axi_arvalid => s_axi_arvalid,
s_axi_rlast => s_axi_rlast,
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid
);
\USE_WRITE.USE_SPLIT_W.write_resp_inst\: entity work.system_auto_pc_1_axi_protocol_converter_v2_1_11_b_downsizer
port map (
E(0) => m_axi_bready,
SR(0) => \USE_WRITE.write_addr_inst_n_7\,
\S_AXI_BRESP_ACC_reg[0]_0\ => \USE_WRITE.USE_SPLIT_W.write_resp_inst_n_2\,
aclk => aclk,
dout(4) => wr_cmd_b_split,
dout(3 downto 0) => wr_cmd_b_repeat(3 downto 0),
empty => \USE_B_CHANNEL.cmd_b_queue/inst/empty\,
m_axi_bresp(1 downto 0) => m_axi_bresp(1 downto 0),
m_axi_bvalid => m_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0),
s_axi_bvalid => s_axi_bvalid,
wr_cmd_b_ready => wr_cmd_b_ready
);
\USE_WRITE.write_addr_inst\: entity work.system_auto_pc_1_axi_protocol_converter_v2_1_11_a_axi3_conv
port map (
E(0) => s_axi_awready,
SR(0) => \USE_WRITE.write_addr_inst_n_7\,
aclk => aclk,
areset_d(1 downto 0) => areset_d(1 downto 0),
aresetn => aresetn,
command_ongoing_reg_0 => \USE_WRITE.write_addr_inst_n_59\,
din(5 downto 4) => Q(1 downto 0),
din(3 downto 0) => m_axi_awlen(3 downto 0),
dout(5 downto 4) => m_axi_wid(1 downto 0),
dout(3 downto 0) => wr_cmd_length(3 downto 0),
empty => \USE_BURSTS.cmd_queue/inst/empty\,
first_mi_word => first_mi_word,
first_mi_word_reg(4) => wr_cmd_b_split,
first_mi_word_reg(3 downto 0) => wr_cmd_b_repeat(3 downto 0),
\goreg_dm.dout_i_reg[4]\ => \USE_WRITE.USE_SPLIT_W.write_resp_inst_n_2\,
\gpregsm1.user_valid_reg\ => \USE_B_CHANNEL.cmd_b_queue/inst/empty\,
length_counter_1_reg(0) => length_counter_1_reg(0),
\length_counter_1_reg_0__s_port_]\ => \USE_WRITE.write_addr_inst_n_56\,
m_axi_awaddr(31 downto 0) => m_axi_awaddr(31 downto 0),
m_axi_awburst(1 downto 0) => m_axi_awburst(1 downto 0),
m_axi_awcache(3 downto 0) => m_axi_awcache(3 downto 0),
m_axi_awlock(0) => m_axi_awlock(0),
m_axi_awprot(2 downto 0) => m_axi_awprot(2 downto 0),
m_axi_awqos(3 downto 0) => m_axi_awqos(3 downto 0),
m_axi_awready => m_axi_awready,
m_axi_awsize(2 downto 0) => m_axi_awsize(2 downto 0),
m_axi_awvalid => m_axi_awvalid,
m_axi_bvalid => m_axi_bvalid,
m_axi_wready => m_axi_wready,
m_axi_wvalid => m_axi_wvalid,
s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0),
s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
s_axi_awcache(3 downto 0) => s_axi_awcache(3 downto 0),
s_axi_awid(1 downto 0) => s_axi_awid(1 downto 0),
s_axi_awlen(7 downto 0) => s_axi_awlen(7 downto 0),
s_axi_awlock(0) => s_axi_awlock(0),
s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0),
s_axi_awqos(3 downto 0) => s_axi_awqos(3 downto 0),
s_axi_awsize(2 downto 0) => s_axi_awsize(2 downto 0),
s_axi_awvalid => s_axi_awvalid,
s_axi_bready => s_axi_bready,
s_axi_wready => \^s_axi_wready\,
s_axi_wvalid => s_axi_wvalid,
wr_cmd_b_ready => wr_cmd_b_ready,
wr_cmd_ready => wr_cmd_ready
);
\USE_WRITE.write_data_inst\: entity work.system_auto_pc_1_axi_protocol_converter_v2_1_11_w_axi3_conv
port map (
SR(0) => \USE_WRITE.write_addr_inst_n_7\,
aclk => aclk,
dout(3 downto 0) => wr_cmd_length(3 downto 0),
empty => \USE_BURSTS.cmd_queue/inst/empty\,
empty_fwft_i_reg => \^s_axi_wready\,
first_mi_word => first_mi_word,
\goreg_dm.dout_i_reg[0]\ => \USE_WRITE.write_addr_inst_n_56\,
\length_counter_1_reg[1]_0\(0) => length_counter_1_reg(0),
m_axi_wlast => m_axi_wlast,
m_axi_wready => m_axi_wready,
s_axi_wvalid => s_axi_wvalid,
wr_cmd_ready => wr_cmd_ready
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_pc_1_axi_protocol_converter_v2_1_11_axi_protocol_converter is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wid : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_buser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_aruser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_ruser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_awid : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wid : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_wlast : out STD_LOGIC;
m_axi_wuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bid : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_buser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_arid : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_aruser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_ruser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of system_auto_pc_1_axi_protocol_converter_v2_1_11_axi_protocol_converter : entity is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of system_auto_pc_1_axi_protocol_converter_v2_1_11_axi_protocol_converter : entity is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of system_auto_pc_1_axi_protocol_converter_v2_1_11_axi_protocol_converter : entity is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of system_auto_pc_1_axi_protocol_converter_v2_1_11_axi_protocol_converter : entity is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of system_auto_pc_1_axi_protocol_converter_v2_1_11_axi_protocol_converter : entity is 64;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of system_auto_pc_1_axi_protocol_converter_v2_1_11_axi_protocol_converter : entity is 2;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of system_auto_pc_1_axi_protocol_converter_v2_1_11_axi_protocol_converter : entity is 1;
attribute C_AXI_SUPPORTS_READ : integer;
attribute C_AXI_SUPPORTS_READ of system_auto_pc_1_axi_protocol_converter_v2_1_11_axi_protocol_converter : entity is 1;
attribute C_AXI_SUPPORTS_USER_SIGNALS : integer;
attribute C_AXI_SUPPORTS_USER_SIGNALS of system_auto_pc_1_axi_protocol_converter_v2_1_11_axi_protocol_converter : entity is 0;
attribute C_AXI_SUPPORTS_WRITE : integer;
attribute C_AXI_SUPPORTS_WRITE of system_auto_pc_1_axi_protocol_converter_v2_1_11_axi_protocol_converter : entity is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of system_auto_pc_1_axi_protocol_converter_v2_1_11_axi_protocol_converter : entity is 1;
attribute C_FAMILY : string;
attribute C_FAMILY of system_auto_pc_1_axi_protocol_converter_v2_1_11_axi_protocol_converter : entity is "zynq";
attribute C_IGNORE_ID : integer;
attribute C_IGNORE_ID of system_auto_pc_1_axi_protocol_converter_v2_1_11_axi_protocol_converter : entity is 0;
attribute C_M_AXI_PROTOCOL : integer;
attribute C_M_AXI_PROTOCOL of system_auto_pc_1_axi_protocol_converter_v2_1_11_axi_protocol_converter : entity is 1;
attribute C_S_AXI_PROTOCOL : integer;
attribute C_S_AXI_PROTOCOL of system_auto_pc_1_axi_protocol_converter_v2_1_11_axi_protocol_converter : entity is 0;
attribute C_TRANSLATION_MODE : integer;
attribute C_TRANSLATION_MODE of system_auto_pc_1_axi_protocol_converter_v2_1_11_axi_protocol_converter : entity is 2;
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of system_auto_pc_1_axi_protocol_converter_v2_1_11_axi_protocol_converter : entity is "yes";
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_pc_1_axi_protocol_converter_v2_1_11_axi_protocol_converter : entity is "axi_protocol_converter_v2_1_11_axi_protocol_converter";
attribute P_AXI3 : integer;
attribute P_AXI3 of system_auto_pc_1_axi_protocol_converter_v2_1_11_axi_protocol_converter : entity is 1;
attribute P_AXI4 : integer;
attribute P_AXI4 of system_auto_pc_1_axi_protocol_converter_v2_1_11_axi_protocol_converter : entity is 0;
attribute P_AXILITE : integer;
attribute P_AXILITE of system_auto_pc_1_axi_protocol_converter_v2_1_11_axi_protocol_converter : entity is 2;
attribute P_AXILITE_SIZE : string;
attribute P_AXILITE_SIZE of system_auto_pc_1_axi_protocol_converter_v2_1_11_axi_protocol_converter : entity is "3'b011";
attribute P_CONVERSION : integer;
attribute P_CONVERSION of system_auto_pc_1_axi_protocol_converter_v2_1_11_axi_protocol_converter : entity is 2;
attribute P_DECERR : string;
attribute P_DECERR of system_auto_pc_1_axi_protocol_converter_v2_1_11_axi_protocol_converter : entity is "2'b11";
attribute P_INCR : string;
attribute P_INCR of system_auto_pc_1_axi_protocol_converter_v2_1_11_axi_protocol_converter : entity is "2'b01";
attribute P_PROTECTION : integer;
attribute P_PROTECTION of system_auto_pc_1_axi_protocol_converter_v2_1_11_axi_protocol_converter : entity is 1;
attribute P_SLVERR : string;
attribute P_SLVERR of system_auto_pc_1_axi_protocol_converter_v2_1_11_axi_protocol_converter : entity is "2'b10";
end system_auto_pc_1_axi_protocol_converter_v2_1_11_axi_protocol_converter;
architecture STRUCTURE of system_auto_pc_1_axi_protocol_converter_v2_1_11_axi_protocol_converter is
signal \<const0>\ : STD_LOGIC;
signal \^m_axi_arlock\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^m_axi_awlock\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^m_axi_bid\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^m_axi_rdata\ : STD_LOGIC_VECTOR ( 63 downto 0 );
signal \^m_axi_rid\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^m_axi_rresp\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^m_axi_ruser\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^s_axi_wdata\ : STD_LOGIC_VECTOR ( 63 downto 0 );
signal \^s_axi_wstrb\ : STD_LOGIC_VECTOR ( 7 downto 0 );
begin
\^m_axi_bid\(1 downto 0) <= m_axi_bid(1 downto 0);
\^m_axi_rdata\(63 downto 0) <= m_axi_rdata(63 downto 0);
\^m_axi_rid\(1 downto 0) <= m_axi_rid(1 downto 0);
\^m_axi_rresp\(1 downto 0) <= m_axi_rresp(1 downto 0);
\^m_axi_ruser\(0) <= m_axi_ruser(0);
\^s_axi_wdata\(63 downto 0) <= s_axi_wdata(63 downto 0);
\^s_axi_wstrb\(7 downto 0) <= s_axi_wstrb(7 downto 0);
m_axi_arlock(1) <= \<const0>\;
m_axi_arlock(0) <= \^m_axi_arlock\(0);
m_axi_arregion(3) <= \<const0>\;
m_axi_arregion(2) <= \<const0>\;
m_axi_arregion(1) <= \<const0>\;
m_axi_arregion(0) <= \<const0>\;
m_axi_aruser(0) <= \<const0>\;
m_axi_awlock(1) <= \<const0>\;
m_axi_awlock(0) <= \^m_axi_awlock\(0);
m_axi_awregion(3) <= \<const0>\;
m_axi_awregion(2) <= \<const0>\;
m_axi_awregion(1) <= \<const0>\;
m_axi_awregion(0) <= \<const0>\;
m_axi_awuser(0) <= \<const0>\;
m_axi_wdata(63 downto 0) <= \^s_axi_wdata\(63 downto 0);
m_axi_wstrb(7 downto 0) <= \^s_axi_wstrb\(7 downto 0);
m_axi_wuser(0) <= \<const0>\;
s_axi_bid(1 downto 0) <= \^m_axi_bid\(1 downto 0);
s_axi_buser(0) <= \<const0>\;
s_axi_rdata(63 downto 0) <= \^m_axi_rdata\(63 downto 0);
s_axi_rid(1 downto 0) <= \^m_axi_rid\(1 downto 0);
s_axi_rresp(1 downto 0) <= \^m_axi_rresp\(1 downto 0);
s_axi_ruser(0) <= \^m_axi_ruser\(0);
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
\gen_axi4_axi3.axi3_conv_inst\: entity work.system_auto_pc_1_axi_protocol_converter_v2_1_11_axi3_conv
port map (
Q(1 downto 0) => m_axi_awid(1 downto 0),
aclk => aclk,
aresetn => aresetn,
m_axi_araddr(31 downto 0) => m_axi_araddr(31 downto 0),
m_axi_arburst(1 downto 0) => m_axi_arburst(1 downto 0),
m_axi_arcache(3 downto 0) => m_axi_arcache(3 downto 0),
\m_axi_arid[1]\(1 downto 0) => m_axi_arid(1 downto 0),
m_axi_arlen(3 downto 0) => m_axi_arlen(3 downto 0),
m_axi_arlock(0) => \^m_axi_arlock\(0),
m_axi_arprot(2 downto 0) => m_axi_arprot(2 downto 0),
m_axi_arqos(3 downto 0) => m_axi_arqos(3 downto 0),
m_axi_arready => m_axi_arready,
m_axi_arsize(2 downto 0) => m_axi_arsize(2 downto 0),
m_axi_arvalid => m_axi_arvalid,
m_axi_awaddr(31 downto 0) => m_axi_awaddr(31 downto 0),
m_axi_awburst(1 downto 0) => m_axi_awburst(1 downto 0),
m_axi_awcache(3 downto 0) => m_axi_awcache(3 downto 0),
m_axi_awlen(3 downto 0) => m_axi_awlen(3 downto 0),
m_axi_awlock(0) => \^m_axi_awlock\(0),
m_axi_awprot(2 downto 0) => m_axi_awprot(2 downto 0),
m_axi_awqos(3 downto 0) => m_axi_awqos(3 downto 0),
m_axi_awready => m_axi_awready,
m_axi_awsize(2 downto 0) => m_axi_awsize(2 downto 0),
m_axi_awvalid => m_axi_awvalid,
m_axi_bready => m_axi_bready,
m_axi_bresp(1 downto 0) => m_axi_bresp(1 downto 0),
m_axi_bvalid => m_axi_bvalid,
m_axi_rlast => m_axi_rlast,
m_axi_rready => m_axi_rready,
m_axi_rvalid => m_axi_rvalid,
m_axi_wid(1 downto 0) => m_axi_wid(1 downto 0),
m_axi_wlast => m_axi_wlast,
m_axi_wready => m_axi_wready,
m_axi_wvalid => m_axi_wvalid,
s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0),
s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
s_axi_arcache(3 downto 0) => s_axi_arcache(3 downto 0),
s_axi_arid(1 downto 0) => s_axi_arid(1 downto 0),
s_axi_arlen(7 downto 0) => s_axi_arlen(7 downto 0),
s_axi_arlock(0) => s_axi_arlock(0),
s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0),
s_axi_arqos(3 downto 0) => s_axi_arqos(3 downto 0),
s_axi_arready => s_axi_arready,
s_axi_arsize(2 downto 0) => s_axi_arsize(2 downto 0),
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0),
s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
s_axi_awcache(3 downto 0) => s_axi_awcache(3 downto 0),
s_axi_awid(1 downto 0) => s_axi_awid(1 downto 0),
s_axi_awlen(7 downto 0) => s_axi_awlen(7 downto 0),
s_axi_awlock(0) => s_axi_awlock(0),
s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0),
s_axi_awqos(3 downto 0) => s_axi_awqos(3 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awsize(2 downto 0) => s_axi_awsize(2 downto 0),
s_axi_awvalid => s_axi_awvalid,
s_axi_bready => s_axi_bready,
s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0),
s_axi_bvalid => s_axi_bvalid,
s_axi_rlast => s_axi_rlast,
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid,
s_axi_wready => s_axi_wready,
s_axi_wvalid => s_axi_wvalid
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_pc_1 is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_awid : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wid : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_wlast : out STD_LOGIC;
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bid : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_arid : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_auto_pc_1 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_auto_pc_1 : entity is "system_auto_pc_1,axi_protocol_converter_v2_1_11_axi_protocol_converter,{}";
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of system_auto_pc_1 : entity is "yes";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of system_auto_pc_1 : entity is "axi_protocol_converter_v2_1_11_axi_protocol_converter,Vivado 2016.4";
end system_auto_pc_1;
architecture STRUCTURE of system_auto_pc_1 is
signal NLW_inst_m_axi_arregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_m_axi_aruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_m_axi_awregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_m_axi_awuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_m_axi_wuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_s_axi_buser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_s_axi_ruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of inst : label is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of inst : label is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of inst : label is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of inst : label is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of inst : label is 64;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of inst : label is 2;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of inst : label is 1;
attribute C_AXI_SUPPORTS_READ : integer;
attribute C_AXI_SUPPORTS_READ of inst : label is 1;
attribute C_AXI_SUPPORTS_USER_SIGNALS : integer;
attribute C_AXI_SUPPORTS_USER_SIGNALS of inst : label is 0;
attribute C_AXI_SUPPORTS_WRITE : integer;
attribute C_AXI_SUPPORTS_WRITE of inst : label is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of inst : label is 1;
attribute C_FAMILY : string;
attribute C_FAMILY of inst : label is "zynq";
attribute C_IGNORE_ID : integer;
attribute C_IGNORE_ID of inst : label is 0;
attribute C_M_AXI_PROTOCOL : integer;
attribute C_M_AXI_PROTOCOL of inst : label is 1;
attribute C_S_AXI_PROTOCOL : integer;
attribute C_S_AXI_PROTOCOL of inst : label is 0;
attribute C_TRANSLATION_MODE : integer;
attribute C_TRANSLATION_MODE of inst : label is 2;
attribute DowngradeIPIdentifiedWarnings of inst : label is "yes";
attribute P_AXI3 : integer;
attribute P_AXI3 of inst : label is 1;
attribute P_AXI4 : integer;
attribute P_AXI4 of inst : label is 0;
attribute P_AXILITE : integer;
attribute P_AXILITE of inst : label is 2;
attribute P_AXILITE_SIZE : string;
attribute P_AXILITE_SIZE of inst : label is "3'b011";
attribute P_CONVERSION : integer;
attribute P_CONVERSION of inst : label is 2;
attribute P_DECERR : string;
attribute P_DECERR of inst : label is "2'b11";
attribute P_INCR : string;
attribute P_INCR of inst : label is "2'b01";
attribute P_PROTECTION : integer;
attribute P_PROTECTION of inst : label is 1;
attribute P_SLVERR : string;
attribute P_SLVERR of inst : label is "2'b10";
begin
inst: entity work.system_auto_pc_1_axi_protocol_converter_v2_1_11_axi_protocol_converter
port map (
aclk => aclk,
aresetn => aresetn,
m_axi_araddr(31 downto 0) => m_axi_araddr(31 downto 0),
m_axi_arburst(1 downto 0) => m_axi_arburst(1 downto 0),
m_axi_arcache(3 downto 0) => m_axi_arcache(3 downto 0),
m_axi_arid(1 downto 0) => m_axi_arid(1 downto 0),
m_axi_arlen(3 downto 0) => m_axi_arlen(3 downto 0),
m_axi_arlock(1 downto 0) => m_axi_arlock(1 downto 0),
m_axi_arprot(2 downto 0) => m_axi_arprot(2 downto 0),
m_axi_arqos(3 downto 0) => m_axi_arqos(3 downto 0),
m_axi_arready => m_axi_arready,
m_axi_arregion(3 downto 0) => NLW_inst_m_axi_arregion_UNCONNECTED(3 downto 0),
m_axi_arsize(2 downto 0) => m_axi_arsize(2 downto 0),
m_axi_aruser(0) => NLW_inst_m_axi_aruser_UNCONNECTED(0),
m_axi_arvalid => m_axi_arvalid,
m_axi_awaddr(31 downto 0) => m_axi_awaddr(31 downto 0),
m_axi_awburst(1 downto 0) => m_axi_awburst(1 downto 0),
m_axi_awcache(3 downto 0) => m_axi_awcache(3 downto 0),
m_axi_awid(1 downto 0) => m_axi_awid(1 downto 0),
m_axi_awlen(3 downto 0) => m_axi_awlen(3 downto 0),
m_axi_awlock(1 downto 0) => m_axi_awlock(1 downto 0),
m_axi_awprot(2 downto 0) => m_axi_awprot(2 downto 0),
m_axi_awqos(3 downto 0) => m_axi_awqos(3 downto 0),
m_axi_awready => m_axi_awready,
m_axi_awregion(3 downto 0) => NLW_inst_m_axi_awregion_UNCONNECTED(3 downto 0),
m_axi_awsize(2 downto 0) => m_axi_awsize(2 downto 0),
m_axi_awuser(0) => NLW_inst_m_axi_awuser_UNCONNECTED(0),
m_axi_awvalid => m_axi_awvalid,
m_axi_bid(1 downto 0) => m_axi_bid(1 downto 0),
m_axi_bready => m_axi_bready,
m_axi_bresp(1 downto 0) => m_axi_bresp(1 downto 0),
m_axi_buser(0) => '0',
m_axi_bvalid => m_axi_bvalid,
m_axi_rdata(63 downto 0) => m_axi_rdata(63 downto 0),
m_axi_rid(1 downto 0) => m_axi_rid(1 downto 0),
m_axi_rlast => m_axi_rlast,
m_axi_rready => m_axi_rready,
m_axi_rresp(1 downto 0) => m_axi_rresp(1 downto 0),
m_axi_ruser(0) => '0',
m_axi_rvalid => m_axi_rvalid,
m_axi_wdata(63 downto 0) => m_axi_wdata(63 downto 0),
m_axi_wid(1 downto 0) => m_axi_wid(1 downto 0),
m_axi_wlast => m_axi_wlast,
m_axi_wready => m_axi_wready,
m_axi_wstrb(7 downto 0) => m_axi_wstrb(7 downto 0),
m_axi_wuser(0) => NLW_inst_m_axi_wuser_UNCONNECTED(0),
m_axi_wvalid => m_axi_wvalid,
s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0),
s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
s_axi_arcache(3 downto 0) => s_axi_arcache(3 downto 0),
s_axi_arid(1 downto 0) => s_axi_arid(1 downto 0),
s_axi_arlen(7 downto 0) => s_axi_arlen(7 downto 0),
s_axi_arlock(0) => s_axi_arlock(0),
s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0),
s_axi_arqos(3 downto 0) => s_axi_arqos(3 downto 0),
s_axi_arready => s_axi_arready,
s_axi_arregion(3 downto 0) => s_axi_arregion(3 downto 0),
s_axi_arsize(2 downto 0) => s_axi_arsize(2 downto 0),
s_axi_aruser(0) => '0',
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0),
s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
s_axi_awcache(3 downto 0) => s_axi_awcache(3 downto 0),
s_axi_awid(1 downto 0) => s_axi_awid(1 downto 0),
s_axi_awlen(7 downto 0) => s_axi_awlen(7 downto 0),
s_axi_awlock(0) => s_axi_awlock(0),
s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0),
s_axi_awqos(3 downto 0) => s_axi_awqos(3 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awregion(3 downto 0) => s_axi_awregion(3 downto 0),
s_axi_awsize(2 downto 0) => s_axi_awsize(2 downto 0),
s_axi_awuser(0) => '0',
s_axi_awvalid => s_axi_awvalid,
s_axi_bid(1 downto 0) => s_axi_bid(1 downto 0),
s_axi_bready => s_axi_bready,
s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0),
s_axi_buser(0) => NLW_inst_s_axi_buser_UNCONNECTED(0),
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(63 downto 0) => s_axi_rdata(63 downto 0),
s_axi_rid(1 downto 0) => s_axi_rid(1 downto 0),
s_axi_rlast => s_axi_rlast,
s_axi_rready => s_axi_rready,
s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0),
s_axi_ruser(0) => NLW_inst_s_axi_ruser_UNCONNECTED(0),
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(63 downto 0) => s_axi_wdata(63 downto 0),
s_axi_wid(1 downto 0) => B"00",
s_axi_wlast => s_axi_wlast,
s_axi_wready => s_axi_wready,
s_axi_wstrb(7 downto 0) => s_axi_wstrb(7 downto 0),
s_axi_wuser(0) => '0',
s_axi_wvalid => s_axi_wvalid
);
end STRUCTURE;
| mit |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_camera_hessian/zed_camera_hessian.srcs/sources_1/bd/system/ip/system_zed_hdmi_0_0/system_zed_hdmi_0_0_sim_netlist.vhdl | 1 | 804429 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Sun May 28 18:34:41 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim -rename_top system_zed_hdmi_0_0 -prefix
-- system_zed_hdmi_0_0_ system_zed_hdmi_0_0_sim_netlist.vhdl
-- Design : system_zed_hdmi_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_zed_hdmi_0_0_i2c_sender is
port (
hdmi_sda : out STD_LOGIC;
hdmi_scl : out STD_LOGIC;
clk_100 : in STD_LOGIC
);
end system_zed_hdmi_0_0_i2c_sender;
architecture STRUCTURE of system_zed_hdmi_0_0_i2c_sender is
signal address : STD_LOGIC_VECTOR ( 5 downto 0 );
signal \address[0]_i_1_n_0\ : STD_LOGIC;
signal \address[1]_i_1_n_0\ : STD_LOGIC;
signal \address[2]_i_1_n_0\ : STD_LOGIC;
signal \address[3]_i_1_n_0\ : STD_LOGIC;
signal \address[3]_i_2_n_0\ : STD_LOGIC;
signal \address[4]_i_1_n_0\ : STD_LOGIC;
signal \address[5]_i_1_n_0\ : STD_LOGIC;
signal \address[5]_i_2_n_0\ : STD_LOGIC;
signal \address[5]_i_3_n_0\ : STD_LOGIC;
signal \address[5]_i_4_n_0\ : STD_LOGIC;
signal \address[5]_i_5_n_0\ : STD_LOGIC;
signal \address[5]_i_6_n_0\ : STD_LOGIC;
signal \address[5]_i_7_n_0\ : STD_LOGIC;
signal busy_sr : STD_LOGIC;
signal \busy_sr[10]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[11]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[12]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[13]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[14]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[15]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[16]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[17]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[18]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[19]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[1]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[20]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[21]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[22]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[23]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[24]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[25]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[26]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[27]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[28]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[28]_i_2_n_0\ : STD_LOGIC;
signal \busy_sr[2]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[3]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[4]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[5]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[6]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[7]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[8]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[9]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[0]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[10]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[11]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[12]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[13]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[14]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[15]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[16]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[17]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[18]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[19]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[1]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[20]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[21]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[22]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[23]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[24]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[25]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[26]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[27]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[2]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[3]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[4]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[5]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[6]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[7]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[8]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[9]\ : STD_LOGIC;
signal clk_first_quarter : STD_LOGIC_VECTOR ( 28 to 28 );
signal \clk_first_quarter[28]_i_1_n_0\ : STD_LOGIC;
signal clk_last_quarter : STD_LOGIC_VECTOR ( 28 downto 1 );
signal \clk_last_quarter[2]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[0]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[0]_i_2_n_0\ : STD_LOGIC;
signal \data_sr_reg_n_0_[0]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[10]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[11]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[12]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[13]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[14]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[15]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[16]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[17]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[18]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[19]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[1]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[20]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[21]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[22]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[23]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[24]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[25]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[26]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[27]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[28]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[2]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[3]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[4]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[5]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[6]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[7]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[8]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[9]\ : STD_LOGIC;
signal divider : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \divider[0]_i_1_n_0\ : STD_LOGIC;
signal \divider[1]_i_1_n_0\ : STD_LOGIC;
signal \divider[2]_i_1_n_0\ : STD_LOGIC;
signal \divider[3]_i_1_n_0\ : STD_LOGIC;
signal \divider[4]_i_1_n_0\ : STD_LOGIC;
signal \divider[5]_i_1_n_0\ : STD_LOGIC;
signal \divider[5]_i_2_n_0\ : STD_LOGIC;
signal \divider[6]_i_1_n_0\ : STD_LOGIC;
signal \divider[7]_i_1_n_0\ : STD_LOGIC;
signal \divider[7]_i_2_n_0\ : STD_LOGIC;
signal \divider[7]_i_3_n_0\ : STD_LOGIC;
signal finished_i_1_n_0 : STD_LOGIC;
signal finished_reg_n_0 : STD_LOGIC;
signal \initial_pause[5]_i_2_n_0\ : STD_LOGIC;
signal \initial_pause[7]_i_1_n_0\ : STD_LOGIC;
signal \initial_pause[7]_i_3_n_0\ : STD_LOGIC;
signal \initial_pause_reg_n_0_[0]\ : STD_LOGIC;
signal \initial_pause_reg_n_0_[1]\ : STD_LOGIC;
signal \initial_pause_reg_n_0_[2]\ : STD_LOGIC;
signal \initial_pause_reg_n_0_[3]\ : STD_LOGIC;
signal \initial_pause_reg_n_0_[4]\ : STD_LOGIC;
signal \initial_pause_reg_n_0_[5]\ : STD_LOGIC;
signal \initial_pause_reg_n_0_[6]\ : STD_LOGIC;
signal p_0_in : STD_LOGIC;
signal \p_0_in__0\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal p_1_in : STD_LOGIC;
signal \p_1_in__0\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal p_2_in : STD_LOGIC_VECTOR ( 18 downto 2 );
signal reg_value_reg_n_10 : STD_LOGIC;
signal reg_value_reg_n_11 : STD_LOGIC;
signal reg_value_reg_n_12 : STD_LOGIC;
signal reg_value_reg_n_13 : STD_LOGIC;
signal reg_value_reg_n_14 : STD_LOGIC;
signal reg_value_reg_n_15 : STD_LOGIC;
signal reg_value_reg_n_8 : STD_LOGIC;
signal reg_value_reg_n_9 : STD_LOGIC;
signal \tristate_sr[19]_i_1_n_0\ : STD_LOGIC;
signal \tristate_sr_reg[16]_srl6___U0_Inst_i2c_sender_tristate_sr_reg_r_4_n_0\ : STD_LOGIC;
signal \tristate_sr_reg[17]_U0_Inst_i2c_sender_tristate_sr_reg_r_5_n_0\ : STD_LOGIC;
signal \tristate_sr_reg[26]_srl7___U0_Inst_i2c_sender_tristate_sr_reg_r_5_n_0\ : STD_LOGIC;
signal \tristate_sr_reg[27]_U0_Inst_i2c_sender_tristate_sr_reg_r_6_n_0\ : STD_LOGIC;
signal \tristate_sr_reg[28]_inv_n_0\ : STD_LOGIC;
signal \tristate_sr_reg[7]_srl6___U0_Inst_i2c_sender_tristate_sr_reg_r_4_n_0\ : STD_LOGIC;
signal \tristate_sr_reg[8]_U0_Inst_i2c_sender_tristate_sr_reg_r_5_n_0\ : STD_LOGIC;
signal \tristate_sr_reg_gate__0_n_0\ : STD_LOGIC;
signal \tristate_sr_reg_gate__1_n_0\ : STD_LOGIC;
signal tristate_sr_reg_gate_n_0 : STD_LOGIC;
signal \tristate_sr_reg_n_0_[10]\ : STD_LOGIC;
signal \tristate_sr_reg_n_0_[18]\ : STD_LOGIC;
signal \tristate_sr_reg_n_0_[19]\ : STD_LOGIC;
signal \tristate_sr_reg_n_0_[1]\ : STD_LOGIC;
signal \tristate_sr_reg_n_0_[9]\ : STD_LOGIC;
signal tristate_sr_reg_r_0_n_0 : STD_LOGIC;
signal tristate_sr_reg_r_1_n_0 : STD_LOGIC;
signal tristate_sr_reg_r_2_n_0 : STD_LOGIC;
signal tristate_sr_reg_r_3_n_0 : STD_LOGIC;
signal tristate_sr_reg_r_4_n_0 : STD_LOGIC;
signal tristate_sr_reg_r_5_n_0 : STD_LOGIC;
signal tristate_sr_reg_r_6_n_0 : STD_LOGIC;
signal tristate_sr_reg_r_n_0 : STD_LOGIC;
signal NLW_reg_value_reg_DOBDO_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
signal NLW_reg_value_reg_DOPADOP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_reg_value_reg_DOPBDOP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \address[0]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \address[1]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \address[3]_i_2\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \address[5]_i_4\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \address[5]_i_6\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \busy_sr[5]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \busy_sr[6]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \data_sr[0]_i_2\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \data_sr[11]_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \data_sr[12]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \data_sr[13]_i_1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \data_sr[14]_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \data_sr[15]_i_1\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \data_sr[16]_i_1\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \data_sr[17]_i_1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \data_sr[18]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \data_sr[2]_i_1\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \data_sr[3]_i_1\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \data_sr[4]_i_1\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \data_sr[5]_i_1\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \data_sr[6]_i_1\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \data_sr[7]_i_1\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \data_sr[8]_i_1\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \data_sr[9]_i_1\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \divider[0]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \divider[1]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \initial_pause[0]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \initial_pause[1]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \initial_pause[2]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \initial_pause[5]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \initial_pause[6]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \initial_pause[7]_i_2\ : label is "soft_lutpair5";
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of reg_value_reg : label is "INDEPENDENT";
attribute \MEM.PORTA.DATA_BIT_LAYOUT\ : string;
attribute \MEM.PORTA.DATA_BIT_LAYOUT\ of reg_value_reg : label is "p0_d16";
attribute METHODOLOGY_DRC_VIOS : string;
attribute METHODOLOGY_DRC_VIOS of reg_value_reg : label is "{SYNTH-6 {cell *THIS*}}";
attribute RTL_RAM_BITS : integer;
attribute RTL_RAM_BITS of reg_value_reg : label is 1024;
attribute RTL_RAM_NAME : string;
attribute RTL_RAM_NAME of reg_value_reg : label is "reg_value";
attribute bram_addr_begin : integer;
attribute bram_addr_begin of reg_value_reg : label is 0;
attribute bram_addr_end : integer;
attribute bram_addr_end of reg_value_reg : label is 1023;
attribute bram_slice_begin : integer;
attribute bram_slice_begin of reg_value_reg : label is 0;
attribute bram_slice_end : integer;
attribute bram_slice_end of reg_value_reg : label is 15;
attribute srl_bus_name : string;
attribute srl_bus_name of \tristate_sr_reg[16]_srl6___U0_Inst_i2c_sender_tristate_sr_reg_r_4\ : label is "\U0/Inst_i2c_sender/tristate_sr_reg ";
attribute srl_name : string;
attribute srl_name of \tristate_sr_reg[16]_srl6___U0_Inst_i2c_sender_tristate_sr_reg_r_4\ : label is "\U0/Inst_i2c_sender/tristate_sr_reg[16]_srl6___U0_Inst_i2c_sender_tristate_sr_reg_r_4 ";
attribute srl_bus_name of \tristate_sr_reg[26]_srl7___U0_Inst_i2c_sender_tristate_sr_reg_r_5\ : label is "\U0/Inst_i2c_sender/tristate_sr_reg ";
attribute srl_name of \tristate_sr_reg[26]_srl7___U0_Inst_i2c_sender_tristate_sr_reg_r_5\ : label is "\U0/Inst_i2c_sender/tristate_sr_reg[26]_srl7___U0_Inst_i2c_sender_tristate_sr_reg_r_5 ";
attribute srl_bus_name of \tristate_sr_reg[7]_srl6___U0_Inst_i2c_sender_tristate_sr_reg_r_4\ : label is "\U0/Inst_i2c_sender/tristate_sr_reg ";
attribute srl_name of \tristate_sr_reg[7]_srl6___U0_Inst_i2c_sender_tristate_sr_reg_r_4\ : label is "\U0/Inst_i2c_sender/tristate_sr_reg[7]_srl6___U0_Inst_i2c_sender_tristate_sr_reg_r_4 ";
attribute SOFT_HLUTNM of \tristate_sr_reg_gate__0\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \tristate_sr_reg_gate__1\ : label is "soft_lutpair16";
begin
\address[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0040"
)
port map (
I0 => p_0_in,
I1 => \address[5]_i_5_n_0\,
I2 => \address[5]_i_3_n_0\,
I3 => address(0),
O => \address[0]_i_1_n_0\
);
\address[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00080800"
)
port map (
I0 => \address[5]_i_3_n_0\,
I1 => \address[5]_i_5_n_0\,
I2 => p_0_in,
I3 => address(0),
I4 => address(1),
O => \address[1]_i_1_n_0\
);
\address[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0008080808000000"
)
port map (
I0 => \address[5]_i_3_n_0\,
I1 => \address[5]_i_5_n_0\,
I2 => p_0_in,
I3 => address(1),
I4 => address(0),
I5 => address(2),
O => \address[2]_i_1_n_0\
);
\address[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"08000008"
)
port map (
I0 => \address[5]_i_3_n_0\,
I1 => \address[5]_i_5_n_0\,
I2 => p_0_in,
I3 => \address[3]_i_2_n_0\,
I4 => address(3),
O => \address[3]_i_1_n_0\
);
\address[3]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"7F"
)
port map (
I0 => address(1),
I1 => address(0),
I2 => address(2),
O => \address[3]_i_2_n_0\
);
\address[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"08000008"
)
port map (
I0 => \address[5]_i_3_n_0\,
I1 => \address[5]_i_5_n_0\,
I2 => p_0_in,
I3 => \address[5]_i_6_n_0\,
I4 => address(4),
O => \address[4]_i_1_n_0\
);
\address[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000200000"
)
port map (
I0 => \address[5]_i_3_n_0\,
I1 => finished_reg_n_0,
I2 => p_1_in,
I3 => \address[5]_i_4_n_0\,
I4 => divider(7),
I5 => p_0_in,
O => \address[5]_i_1_n_0\
);
\address[5]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0808000800000800"
)
port map (
I0 => \address[5]_i_3_n_0\,
I1 => \address[5]_i_5_n_0\,
I2 => p_0_in,
I3 => address(4),
I4 => \address[5]_i_6_n_0\,
I5 => address(5),
O => \address[5]_i_2_n_0\
);
\address[5]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFF7FFF"
)
port map (
I0 => \p_0_in__0\(2),
I1 => \p_0_in__0\(3),
I2 => \p_0_in__0\(0),
I3 => \p_0_in__0\(1),
I4 => \address[5]_i_7_n_0\,
O => \address[5]_i_3_n_0\
);
\address[5]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \divider[7]_i_3_n_0\,
I1 => divider(6),
O => \address[5]_i_4_n_0\
);
\address[5]_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"00400000"
)
port map (
I0 => finished_reg_n_0,
I1 => p_1_in,
I2 => divider(6),
I3 => \divider[7]_i_3_n_0\,
I4 => divider(7),
O => \address[5]_i_5_n_0\
);
\address[5]_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => address(2),
I1 => address(0),
I2 => address(1),
I3 => address(3),
O => \address[5]_i_6_n_0\
);
\address[5]_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => \p_0_in__0\(5),
I1 => \p_0_in__0\(4),
I2 => \p_0_in__0\(7),
I3 => \p_0_in__0\(6),
O => \address[5]_i_7_n_0\
);
\address_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_100,
CE => \address[5]_i_1_n_0\,
D => \address[0]_i_1_n_0\,
Q => address(0),
R => '0'
);
\address_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_100,
CE => \address[5]_i_1_n_0\,
D => \address[1]_i_1_n_0\,
Q => address(1),
R => '0'
);
\address_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_100,
CE => \address[5]_i_1_n_0\,
D => \address[2]_i_1_n_0\,
Q => address(2),
R => '0'
);
\address_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_100,
CE => \address[5]_i_1_n_0\,
D => \address[3]_i_1_n_0\,
Q => address(3),
R => '0'
);
\address_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_100,
CE => \address[5]_i_1_n_0\,
D => \address[4]_i_1_n_0\,
Q => address(4),
R => '0'
);
\address_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_100,
CE => \address[5]_i_1_n_0\,
D => \address[5]_i_2_n_0\,
Q => address(5),
R => '0'
);
\busy_sr[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000FF200000"
)
port map (
I0 => \address[5]_i_3_n_0\,
I1 => finished_reg_n_0,
I2 => p_1_in,
I3 => p_0_in,
I4 => divider(7),
I5 => \address[5]_i_4_n_0\,
O => busy_sr
);
\busy_sr[10]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[9]\,
O => \busy_sr[10]_i_1_n_0\
);
\busy_sr[11]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[10]\,
O => \busy_sr[11]_i_1_n_0\
);
\busy_sr[12]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[11]\,
O => \busy_sr[12]_i_1_n_0\
);
\busy_sr[13]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[12]\,
O => \busy_sr[13]_i_1_n_0\
);
\busy_sr[14]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[13]\,
O => \busy_sr[14]_i_1_n_0\
);
\busy_sr[15]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[14]\,
O => \busy_sr[15]_i_1_n_0\
);
\busy_sr[16]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[15]\,
O => \busy_sr[16]_i_1_n_0\
);
\busy_sr[17]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[16]\,
O => \busy_sr[17]_i_1_n_0\
);
\busy_sr[18]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[17]\,
O => \busy_sr[18]_i_1_n_0\
);
\busy_sr[19]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[18]\,
O => \busy_sr[19]_i_1_n_0\
);
\busy_sr[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[0]\,
O => \busy_sr[1]_i_1_n_0\
);
\busy_sr[20]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[19]\,
O => \busy_sr[20]_i_1_n_0\
);
\busy_sr[21]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[20]\,
O => \busy_sr[21]_i_1_n_0\
);
\busy_sr[22]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[21]\,
O => \busy_sr[22]_i_1_n_0\
);
\busy_sr[23]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[22]\,
O => \busy_sr[23]_i_1_n_0\
);
\busy_sr[24]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[23]\,
O => \busy_sr[24]_i_1_n_0\
);
\busy_sr[25]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[24]\,
O => \busy_sr[25]_i_1_n_0\
);
\busy_sr[26]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[25]\,
O => \busy_sr[26]_i_1_n_0\
);
\busy_sr[27]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[26]\,
O => \busy_sr[27]_i_1_n_0\
);
\busy_sr[28]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000040000000000"
)
port map (
I0 => \address[5]_i_4_n_0\,
I1 => divider(7),
I2 => p_0_in,
I3 => p_1_in,
I4 => finished_reg_n_0,
I5 => \address[5]_i_3_n_0\,
O => \busy_sr[28]_i_1_n_0\
);
\busy_sr[28]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[27]\,
O => \busy_sr[28]_i_2_n_0\
);
\busy_sr[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[1]\,
O => \busy_sr[2]_i_1_n_0\
);
\busy_sr[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[2]\,
O => \busy_sr[3]_i_1_n_0\
);
\busy_sr[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[3]\,
O => \busy_sr[4]_i_1_n_0\
);
\busy_sr[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[4]\,
O => \busy_sr[5]_i_1_n_0\
);
\busy_sr[6]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[5]\,
O => \busy_sr[6]_i_1_n_0\
);
\busy_sr[7]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[6]\,
O => \busy_sr[7]_i_1_n_0\
);
\busy_sr[8]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[7]\,
O => \busy_sr[8]_i_1_n_0\
);
\busy_sr[9]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[8]\,
O => \busy_sr[9]_i_1_n_0\
);
\busy_sr_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \address[5]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[0]\,
R => '0'
);
\busy_sr_reg[10]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[10]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[10]\,
S => \busy_sr[28]_i_1_n_0\
);
\busy_sr_reg[11]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[11]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[11]\,
S => \busy_sr[28]_i_1_n_0\
);
\busy_sr_reg[12]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[12]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[12]\,
S => \busy_sr[28]_i_1_n_0\
);
\busy_sr_reg[13]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[13]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[13]\,
S => \busy_sr[28]_i_1_n_0\
);
\busy_sr_reg[14]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[14]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[14]\,
S => \busy_sr[28]_i_1_n_0\
);
\busy_sr_reg[15]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[15]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[15]\,
S => \busy_sr[28]_i_1_n_0\
);
\busy_sr_reg[16]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[16]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[16]\,
S => \busy_sr[28]_i_1_n_0\
);
\busy_sr_reg[17]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[17]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[17]\,
S => \busy_sr[28]_i_1_n_0\
);
\busy_sr_reg[18]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[18]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[18]\,
S => \busy_sr[28]_i_1_n_0\
);
\busy_sr_reg[19]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[19]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[19]\,
S => \busy_sr[28]_i_1_n_0\
);
\busy_sr_reg[1]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[1]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[1]\,
S => \busy_sr[28]_i_1_n_0\
);
\busy_sr_reg[20]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[20]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[20]\,
S => \busy_sr[28]_i_1_n_0\
);
\busy_sr_reg[21]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[21]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[21]\,
S => \busy_sr[28]_i_1_n_0\
);
\busy_sr_reg[22]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[22]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[22]\,
S => \busy_sr[28]_i_1_n_0\
);
\busy_sr_reg[23]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[23]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[23]\,
S => \busy_sr[28]_i_1_n_0\
);
\busy_sr_reg[24]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[24]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[24]\,
S => \busy_sr[28]_i_1_n_0\
);
\busy_sr_reg[25]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[25]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[25]\,
S => \busy_sr[28]_i_1_n_0\
);
\busy_sr_reg[26]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[26]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[26]\,
S => \busy_sr[28]_i_1_n_0\
);
\busy_sr_reg[27]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[27]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[27]\,
S => \busy_sr[28]_i_1_n_0\
);
\busy_sr_reg[28]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[28]_i_2_n_0\,
Q => p_0_in,
S => \busy_sr[28]_i_1_n_0\
);
\busy_sr_reg[2]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[2]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[2]\,
S => \busy_sr[28]_i_1_n_0\
);
\busy_sr_reg[3]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[3]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[3]\,
S => \busy_sr[28]_i_1_n_0\
);
\busy_sr_reg[4]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[4]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[4]\,
S => \busy_sr[28]_i_1_n_0\
);
\busy_sr_reg[5]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[5]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[5]\,
S => \busy_sr[28]_i_1_n_0\
);
\busy_sr_reg[6]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[6]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[6]\,
S => \busy_sr[28]_i_1_n_0\
);
\busy_sr_reg[7]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[7]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[7]\,
S => \busy_sr[28]_i_1_n_0\
);
\busy_sr_reg[8]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[8]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[8]\,
S => \busy_sr[28]_i_1_n_0\
);
\busy_sr_reg[9]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[9]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[9]\,
S => \busy_sr[28]_i_1_n_0\
);
\clk_first_quarter[28]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => clk_last_quarter(28),
O => \clk_first_quarter[28]_i_1_n_0\
);
\clk_first_quarter_reg[28]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \clk_first_quarter[28]_i_1_n_0\,
Q => clk_first_quarter(28),
S => \busy_sr[28]_i_1_n_0\
);
\clk_last_quarter[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000200000"
)
port map (
I0 => p_1_in,
I1 => finished_reg_n_0,
I2 => \address[5]_i_3_n_0\,
I3 => p_0_in,
I4 => divider(7),
I5 => \address[5]_i_4_n_0\,
O => \clk_last_quarter[2]_i_1_n_0\
);
\clk_last_quarter_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => clk_last_quarter(9),
Q => clk_last_quarter(10),
R => \clk_last_quarter[2]_i_1_n_0\
);
\clk_last_quarter_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => clk_last_quarter(10),
Q => clk_last_quarter(11),
R => \clk_last_quarter[2]_i_1_n_0\
);
\clk_last_quarter_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => clk_last_quarter(11),
Q => clk_last_quarter(12),
R => \clk_last_quarter[2]_i_1_n_0\
);
\clk_last_quarter_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => clk_last_quarter(12),
Q => clk_last_quarter(13),
R => \clk_last_quarter[2]_i_1_n_0\
);
\clk_last_quarter_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => clk_last_quarter(13),
Q => clk_last_quarter(14),
R => \clk_last_quarter[2]_i_1_n_0\
);
\clk_last_quarter_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => clk_last_quarter(14),
Q => clk_last_quarter(15),
R => \clk_last_quarter[2]_i_1_n_0\
);
\clk_last_quarter_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => clk_last_quarter(15),
Q => clk_last_quarter(16),
R => \clk_last_quarter[2]_i_1_n_0\
);
\clk_last_quarter_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => clk_last_quarter(16),
Q => clk_last_quarter(17),
R => \clk_last_quarter[2]_i_1_n_0\
);
\clk_last_quarter_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => clk_last_quarter(17),
Q => clk_last_quarter(18),
R => \clk_last_quarter[2]_i_1_n_0\
);
\clk_last_quarter_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => clk_last_quarter(18),
Q => clk_last_quarter(19),
R => \clk_last_quarter[2]_i_1_n_0\
);
\clk_last_quarter_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \tristate_sr[19]_i_1_n_0\,
Q => clk_last_quarter(1),
R => '0'
);
\clk_last_quarter_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => clk_last_quarter(19),
Q => clk_last_quarter(20),
R => \clk_last_quarter[2]_i_1_n_0\
);
\clk_last_quarter_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => clk_last_quarter(20),
Q => clk_last_quarter(21),
R => \clk_last_quarter[2]_i_1_n_0\
);
\clk_last_quarter_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => clk_last_quarter(21),
Q => clk_last_quarter(22),
R => \clk_last_quarter[2]_i_1_n_0\
);
\clk_last_quarter_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => clk_last_quarter(22),
Q => clk_last_quarter(23),
R => \clk_last_quarter[2]_i_1_n_0\
);
\clk_last_quarter_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => clk_last_quarter(23),
Q => clk_last_quarter(24),
R => \clk_last_quarter[2]_i_1_n_0\
);
\clk_last_quarter_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => clk_last_quarter(24),
Q => clk_last_quarter(25),
R => \clk_last_quarter[2]_i_1_n_0\
);
\clk_last_quarter_reg[26]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => clk_last_quarter(25),
Q => clk_last_quarter(26),
R => \clk_last_quarter[2]_i_1_n_0\
);
\clk_last_quarter_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => clk_last_quarter(26),
Q => clk_last_quarter(27),
R => \clk_last_quarter[2]_i_1_n_0\
);
\clk_last_quarter_reg[28]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => clk_last_quarter(27),
Q => clk_last_quarter(28),
R => \clk_last_quarter[2]_i_1_n_0\
);
\clk_last_quarter_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => clk_last_quarter(1),
Q => clk_last_quarter(2),
R => \clk_last_quarter[2]_i_1_n_0\
);
\clk_last_quarter_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => clk_last_quarter(2),
Q => clk_last_quarter(3),
R => \clk_last_quarter[2]_i_1_n_0\
);
\clk_last_quarter_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => clk_last_quarter(3),
Q => clk_last_quarter(4),
R => \clk_last_quarter[2]_i_1_n_0\
);
\clk_last_quarter_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => clk_last_quarter(4),
Q => clk_last_quarter(5),
R => \clk_last_quarter[2]_i_1_n_0\
);
\clk_last_quarter_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => clk_last_quarter(5),
Q => clk_last_quarter(6),
R => \clk_last_quarter[2]_i_1_n_0\
);
\clk_last_quarter_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => clk_last_quarter(6),
Q => clk_last_quarter(7),
R => \clk_last_quarter[2]_i_1_n_0\
);
\clk_last_quarter_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => clk_last_quarter(7),
Q => clk_last_quarter(8),
R => \clk_last_quarter[2]_i_1_n_0\
);
\clk_last_quarter_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => clk_last_quarter(8),
Q => clk_last_quarter(9),
R => \clk_last_quarter[2]_i_1_n_0\
);
\data_sr[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"EAEACAEAEAEAEAEA"
)
port map (
I0 => \data_sr_reg_n_0_[0]\,
I1 => p_0_in,
I2 => \data_sr[0]_i_2_n_0\,
I3 => p_1_in,
I4 => finished_reg_n_0,
I5 => \address[5]_i_3_n_0\,
O => \data_sr[0]_i_1_n_0\
);
\data_sr[0]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"20"
)
port map (
I0 => divider(7),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(6),
O => \data_sr[0]_i_2_n_0\
);
\data_sr[11]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[10]\,
I1 => p_0_in,
I2 => \p_0_in__0\(0),
O => p_2_in(11)
);
\data_sr[12]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[11]\,
I1 => p_0_in,
I2 => \p_0_in__0\(1),
O => p_2_in(12)
);
\data_sr[13]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[12]\,
I1 => p_0_in,
I2 => \p_0_in__0\(2),
O => p_2_in(13)
);
\data_sr[14]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[13]\,
I1 => p_0_in,
I2 => \p_0_in__0\(3),
O => p_2_in(14)
);
\data_sr[15]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[14]\,
I1 => p_0_in,
I2 => \p_0_in__0\(4),
O => p_2_in(15)
);
\data_sr[16]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[15]\,
I1 => p_0_in,
I2 => \p_0_in__0\(5),
O => p_2_in(16)
);
\data_sr[17]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[16]\,
I1 => p_0_in,
I2 => \p_0_in__0\(6),
O => p_2_in(17)
);
\data_sr[18]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[17]\,
I1 => p_0_in,
I2 => \p_0_in__0\(7),
O => p_2_in(18)
);
\data_sr[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[1]\,
I1 => p_0_in,
I2 => reg_value_reg_n_15,
O => p_2_in(2)
);
\data_sr[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[2]\,
I1 => p_0_in,
I2 => reg_value_reg_n_14,
O => p_2_in(3)
);
\data_sr[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[3]\,
I1 => p_0_in,
I2 => reg_value_reg_n_13,
O => p_2_in(4)
);
\data_sr[5]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[4]\,
I1 => p_0_in,
I2 => reg_value_reg_n_12,
O => p_2_in(5)
);
\data_sr[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[5]\,
I1 => p_0_in,
I2 => reg_value_reg_n_11,
O => p_2_in(6)
);
\data_sr[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[6]\,
I1 => p_0_in,
I2 => reg_value_reg_n_10,
O => p_2_in(7)
);
\data_sr[8]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[7]\,
I1 => p_0_in,
I2 => reg_value_reg_n_9,
O => p_2_in(8)
);
\data_sr[9]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[8]\,
I1 => p_0_in,
I2 => reg_value_reg_n_8,
O => p_2_in(9)
);
\data_sr_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => '1',
D => \data_sr[0]_i_1_n_0\,
Q => \data_sr_reg_n_0_[0]\,
R => '0'
);
\data_sr_reg[10]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \data_sr_reg_n_0_[9]\,
Q => \data_sr_reg_n_0_[10]\,
S => \address[5]_i_1_n_0\
);
\data_sr_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => p_2_in(11),
Q => \data_sr_reg_n_0_[11]\,
R => '0'
);
\data_sr_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => p_2_in(12),
Q => \data_sr_reg_n_0_[12]\,
R => '0'
);
\data_sr_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => p_2_in(13),
Q => \data_sr_reg_n_0_[13]\,
R => '0'
);
\data_sr_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => p_2_in(14),
Q => \data_sr_reg_n_0_[14]\,
R => '0'
);
\data_sr_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => p_2_in(15),
Q => \data_sr_reg_n_0_[15]\,
R => '0'
);
\data_sr_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => p_2_in(16),
Q => \data_sr_reg_n_0_[16]\,
R => '0'
);
\data_sr_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => p_2_in(17),
Q => \data_sr_reg_n_0_[17]\,
R => '0'
);
\data_sr_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => p_2_in(18),
Q => \data_sr_reg_n_0_[18]\,
R => '0'
);
\data_sr_reg[19]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \data_sr_reg_n_0_[18]\,
Q => \data_sr_reg_n_0_[19]\,
S => \address[5]_i_1_n_0\
);
\data_sr_reg[1]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \data_sr_reg_n_0_[0]\,
Q => \data_sr_reg_n_0_[1]\,
S => \address[5]_i_1_n_0\
);
\data_sr_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \data_sr_reg_n_0_[19]\,
Q => \data_sr_reg_n_0_[20]\,
R => \address[5]_i_1_n_0\
);
\data_sr_reg[21]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \data_sr_reg_n_0_[20]\,
Q => \data_sr_reg_n_0_[21]\,
S => \address[5]_i_1_n_0\
);
\data_sr_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \data_sr_reg_n_0_[21]\,
Q => \data_sr_reg_n_0_[22]\,
R => \address[5]_i_1_n_0\
);
\data_sr_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \data_sr_reg_n_0_[22]\,
Q => \data_sr_reg_n_0_[23]\,
R => \address[5]_i_1_n_0\
);
\data_sr_reg[24]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \data_sr_reg_n_0_[23]\,
Q => \data_sr_reg_n_0_[24]\,
S => \address[5]_i_1_n_0\
);
\data_sr_reg[25]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \data_sr_reg_n_0_[24]\,
Q => \data_sr_reg_n_0_[25]\,
S => \address[5]_i_1_n_0\
);
\data_sr_reg[26]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \data_sr_reg_n_0_[25]\,
Q => \data_sr_reg_n_0_[26]\,
S => \address[5]_i_1_n_0\
);
\data_sr_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \data_sr_reg_n_0_[26]\,
Q => \data_sr_reg_n_0_[27]\,
R => \address[5]_i_1_n_0\
);
\data_sr_reg[28]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \data_sr_reg_n_0_[27]\,
Q => \data_sr_reg_n_0_[28]\,
R => \address[5]_i_1_n_0\
);
\data_sr_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => p_2_in(2),
Q => \data_sr_reg_n_0_[2]\,
R => '0'
);
\data_sr_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => p_2_in(3),
Q => \data_sr_reg_n_0_[3]\,
R => '0'
);
\data_sr_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => p_2_in(4),
Q => \data_sr_reg_n_0_[4]\,
R => '0'
);
\data_sr_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => p_2_in(5),
Q => \data_sr_reg_n_0_[5]\,
R => '0'
);
\data_sr_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => p_2_in(6),
Q => \data_sr_reg_n_0_[6]\,
R => '0'
);
\data_sr_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => p_2_in(7),
Q => \data_sr_reg_n_0_[7]\,
R => '0'
);
\data_sr_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => p_2_in(8),
Q => \data_sr_reg_n_0_[8]\,
R => '0'
);
\data_sr_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => p_2_in(9),
Q => \data_sr_reg_n_0_[9]\,
R => '0'
);
\divider[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"00AE"
)
port map (
I0 => p_0_in,
I1 => p_1_in,
I2 => finished_reg_n_0,
I3 => divider(0),
O => \divider[0]_i_1_n_0\
);
\divider[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00F4F400"
)
port map (
I0 => finished_reg_n_0,
I1 => p_1_in,
I2 => p_0_in,
I3 => divider(0),
I4 => divider(1),
O => \divider[1]_i_1_n_0\
);
\divider[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00F4F4F4F4000000"
)
port map (
I0 => finished_reg_n_0,
I1 => p_1_in,
I2 => p_0_in,
I3 => divider(1),
I4 => divider(0),
I5 => divider(2),
O => \divider[2]_i_1_n_0\
);
\divider[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"2AAA8000"
)
port map (
I0 => \divider[7]_i_1_n_0\,
I1 => divider(2),
I2 => divider(0),
I3 => divider(1),
I4 => divider(3),
O => \divider[3]_i_1_n_0\
);
\divider[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFF000080000000"
)
port map (
I0 => divider(2),
I1 => divider(0),
I2 => divider(1),
I3 => divider(3),
I4 => \divider[7]_i_1_n_0\,
I5 => divider(4),
O => \divider[4]_i_1_n_0\
);
\divider[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"88A84454"
)
port map (
I0 => \divider[5]_i_2_n_0\,
I1 => p_0_in,
I2 => p_1_in,
I3 => finished_reg_n_0,
I4 => divider(5),
O => \divider[5]_i_1_n_0\
);
\divider[5]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFFFFFF"
)
port map (
I0 => divider(3),
I1 => divider(1),
I2 => divider(0),
I3 => divider(2),
I4 => divider(4),
O => \divider[5]_i_2_n_0\
);
\divider[6]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"88A84454"
)
port map (
I0 => \divider[7]_i_3_n_0\,
I1 => p_0_in,
I2 => p_1_in,
I3 => finished_reg_n_0,
I4 => divider(6),
O => \divider[6]_i_1_n_0\
);
\divider[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"F4"
)
port map (
I0 => finished_reg_n_0,
I1 => p_1_in,
I2 => p_0_in,
O => \divider[7]_i_1_n_0\
);
\divider[7]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"B0B0BBB040404440"
)
port map (
I0 => \divider[7]_i_3_n_0\,
I1 => divider(6),
I2 => p_0_in,
I3 => p_1_in,
I4 => finished_reg_n_0,
I5 => divider(7),
O => \divider[7]_i_2_n_0\
);
\divider[7]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFFFFFFFFFF"
)
port map (
I0 => divider(4),
I1 => divider(2),
I2 => divider(0),
I3 => divider(1),
I4 => divider(3),
I5 => divider(5),
O => \divider[7]_i_3_n_0\
);
\divider_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_100,
CE => \divider[7]_i_1_n_0\,
D => \divider[0]_i_1_n_0\,
Q => divider(0),
R => '0'
);
\divider_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_100,
CE => \divider[7]_i_1_n_0\,
D => \divider[1]_i_1_n_0\,
Q => divider(1),
R => '0'
);
\divider_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_100,
CE => \divider[7]_i_1_n_0\,
D => \divider[2]_i_1_n_0\,
Q => divider(2),
R => '0'
);
\divider_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_100,
CE => \divider[7]_i_1_n_0\,
D => \divider[3]_i_1_n_0\,
Q => divider(3),
R => '0'
);
\divider_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_100,
CE => \divider[7]_i_1_n_0\,
D => \divider[4]_i_1_n_0\,
Q => divider(4),
R => '0'
);
\divider_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_100,
CE => \divider[7]_i_1_n_0\,
D => \divider[5]_i_1_n_0\,
Q => divider(5),
R => '0'
);
\divider_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_100,
CE => \divider[7]_i_1_n_0\,
D => \divider[6]_i_1_n_0\,
Q => divider(6),
R => '0'
);
\divider_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_100,
CE => \divider[7]_i_1_n_0\,
D => \divider[7]_i_2_n_0\,
Q => divider(7),
R => '0'
);
finished_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF00000020"
)
port map (
I0 => p_1_in,
I1 => \address[5]_i_4_n_0\,
I2 => divider(7),
I3 => \address[5]_i_3_n_0\,
I4 => p_0_in,
I5 => finished_reg_n_0,
O => finished_i_1_n_0
);
finished_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_100,
CE => '1',
D => finished_i_1_n_0,
Q => finished_reg_n_0,
R => '0'
);
hdmi_scl_INST_0: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => clk_first_quarter(28),
I1 => divider(7),
O => hdmi_scl
);
hdmi_sda_INST_0: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \data_sr_reg_n_0_[28]\,
I1 => \tristate_sr_reg[28]_inv_n_0\,
O => hdmi_sda
);
\initial_pause[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"01"
)
port map (
I0 => p_1_in,
I1 => p_0_in,
I2 => \initial_pause_reg_n_0_[0]\,
O => \p_1_in__0\(0)
);
\initial_pause[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0110"
)
port map (
I0 => p_0_in,
I1 => p_1_in,
I2 => \initial_pause_reg_n_0_[0]\,
I3 => \initial_pause_reg_n_0_[1]\,
O => \p_1_in__0\(1)
);
\initial_pause[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00070008"
)
port map (
I0 => \initial_pause_reg_n_0_[0]\,
I1 => \initial_pause_reg_n_0_[1]\,
I2 => p_1_in,
I3 => p_0_in,
I4 => \initial_pause_reg_n_0_[2]\,
O => \p_1_in__0\(2)
);
\initial_pause[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000007F00000080"
)
port map (
I0 => \initial_pause_reg_n_0_[1]\,
I1 => \initial_pause_reg_n_0_[0]\,
I2 => \initial_pause_reg_n_0_[2]\,
I3 => p_1_in,
I4 => p_0_in,
I5 => \initial_pause_reg_n_0_[3]\,
O => \p_1_in__0\(3)
);
\initial_pause[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFF000080000000"
)
port map (
I0 => \initial_pause_reg_n_0_[2]\,
I1 => \initial_pause_reg_n_0_[0]\,
I2 => \initial_pause_reg_n_0_[1]\,
I3 => \initial_pause_reg_n_0_[3]\,
I4 => \initial_pause[7]_i_1_n_0\,
I5 => \initial_pause_reg_n_0_[4]\,
O => \p_1_in__0\(4)
);
\initial_pause[5]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0201"
)
port map (
I0 => \initial_pause[5]_i_2_n_0\,
I1 => p_1_in,
I2 => p_0_in,
I3 => \initial_pause_reg_n_0_[5]\,
O => \p_1_in__0\(5)
);
\initial_pause[5]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFFFFFF"
)
port map (
I0 => \initial_pause_reg_n_0_[3]\,
I1 => \initial_pause_reg_n_0_[1]\,
I2 => \initial_pause_reg_n_0_[0]\,
I3 => \initial_pause_reg_n_0_[2]\,
I4 => \initial_pause_reg_n_0_[4]\,
O => \initial_pause[5]_i_2_n_0\
);
\initial_pause[6]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0201"
)
port map (
I0 => \initial_pause[7]_i_3_n_0\,
I1 => p_1_in,
I2 => p_0_in,
I3 => \initial_pause_reg_n_0_[6]\,
O => \p_1_in__0\(6)
);
\initial_pause[7]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => p_0_in,
I1 => p_1_in,
O => \initial_pause[7]_i_1_n_0\
);
\initial_pause[7]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"0002"
)
port map (
I0 => \initial_pause_reg_n_0_[6]\,
I1 => p_0_in,
I2 => p_1_in,
I3 => \initial_pause[7]_i_3_n_0\,
O => \p_1_in__0\(7)
);
\initial_pause[7]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFFFFFFFFFF"
)
port map (
I0 => \initial_pause_reg_n_0_[4]\,
I1 => \initial_pause_reg_n_0_[2]\,
I2 => \initial_pause_reg_n_0_[0]\,
I3 => \initial_pause_reg_n_0_[1]\,
I4 => \initial_pause_reg_n_0_[3]\,
I5 => \initial_pause_reg_n_0_[5]\,
O => \initial_pause[7]_i_3_n_0\
);
\initial_pause_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_100,
CE => \initial_pause[7]_i_1_n_0\,
D => \p_1_in__0\(0),
Q => \initial_pause_reg_n_0_[0]\,
R => '0'
);
\initial_pause_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_100,
CE => \initial_pause[7]_i_1_n_0\,
D => \p_1_in__0\(1),
Q => \initial_pause_reg_n_0_[1]\,
R => '0'
);
\initial_pause_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_100,
CE => \initial_pause[7]_i_1_n_0\,
D => \p_1_in__0\(2),
Q => \initial_pause_reg_n_0_[2]\,
R => '0'
);
\initial_pause_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_100,
CE => \initial_pause[7]_i_1_n_0\,
D => \p_1_in__0\(3),
Q => \initial_pause_reg_n_0_[3]\,
R => '0'
);
\initial_pause_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_100,
CE => \initial_pause[7]_i_1_n_0\,
D => \p_1_in__0\(4),
Q => \initial_pause_reg_n_0_[4]\,
R => '0'
);
\initial_pause_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_100,
CE => \initial_pause[7]_i_1_n_0\,
D => \p_1_in__0\(5),
Q => \initial_pause_reg_n_0_[5]\,
R => '0'
);
\initial_pause_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_100,
CE => \initial_pause[7]_i_1_n_0\,
D => \p_1_in__0\(6),
Q => \initial_pause_reg_n_0_[6]\,
R => '0'
);
\initial_pause_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_100,
CE => \initial_pause[7]_i_1_n_0\,
D => \p_1_in__0\(7),
Q => p_1_in,
R => '0'
);
reg_value_reg: unisim.vcomponents.RAMB18E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"AF04D03C1700163748101506F9005512E0D0A3A4A2A49D619C309AE098034110",
INIT_01 => X"2524241F23AD220421DC201D1F1B1E1C1D001C001BAD1A04193418E740004C04",
INIT_02 => X"FFFFFFFFFFFFFFFFFFFFFFFF2F772E1B2D7C2C082BAD2A042900280027352601",
INIT_03 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"00000",
INIT_B => X"00000",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 18,
READ_WIDTH_B => 0,
RSTREG_PRIORITY_A => "RSTREG",
RSTREG_PRIORITY_B => "RSTREG",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"00000",
SRVAL_B => X"00000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 18,
WRITE_WIDTH_B => 0
)
port map (
ADDRARDADDR(13 downto 10) => B"0000",
ADDRARDADDR(9 downto 4) => address(5 downto 0),
ADDRARDADDR(3 downto 0) => B"0000",
ADDRBWRADDR(13 downto 0) => B"11111111111111",
CLKARDCLK => clk_100,
CLKBWRCLK => '0',
DIADI(15 downto 0) => B"1111111111111111",
DIBDI(15 downto 0) => B"1111111111111111",
DIPADIP(1 downto 0) => B"00",
DIPBDIP(1 downto 0) => B"11",
DOADO(15 downto 8) => \p_0_in__0\(7 downto 0),
DOADO(7) => reg_value_reg_n_8,
DOADO(6) => reg_value_reg_n_9,
DOADO(5) => reg_value_reg_n_10,
DOADO(4) => reg_value_reg_n_11,
DOADO(3) => reg_value_reg_n_12,
DOADO(2) => reg_value_reg_n_13,
DOADO(1) => reg_value_reg_n_14,
DOADO(0) => reg_value_reg_n_15,
DOBDO(15 downto 0) => NLW_reg_value_reg_DOBDO_UNCONNECTED(15 downto 0),
DOPADOP(1 downto 0) => NLW_reg_value_reg_DOPADOP_UNCONNECTED(1 downto 0),
DOPBDOP(1 downto 0) => NLW_reg_value_reg_DOPBDOP_UNCONNECTED(1 downto 0),
ENARDEN => '1',
ENBWREN => '0',
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
WEA(1 downto 0) => B"00",
WEBWE(3 downto 0) => B"0000"
);
\tristate_sr[19]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"2000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
O => \tristate_sr[19]_i_1_n_0\
);
\tristate_sr_reg[10]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk_100,
CE => \tristate_sr[19]_i_1_n_0\,
D => \tristate_sr_reg_n_0_[9]\,
Q => \tristate_sr_reg_n_0_[10]\,
S => \address[5]_i_1_n_0\
);
\tristate_sr_reg[16]_srl6___U0_Inst_i2c_sender_tristate_sr_reg_r_4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => '1',
A1 => '0',
A2 => '1',
A3 => '0',
CE => \tristate_sr[19]_i_1_n_0\,
CLK => clk_100,
D => \tristate_sr_reg_n_0_[10]\,
Q => \tristate_sr_reg[16]_srl6___U0_Inst_i2c_sender_tristate_sr_reg_r_4_n_0\
);
\tristate_sr_reg[17]_U0_Inst_i2c_sender_tristate_sr_reg_r_5\: unisim.vcomponents.FDRE
port map (
C => clk_100,
CE => \tristate_sr[19]_i_1_n_0\,
D => \tristate_sr_reg[16]_srl6___U0_Inst_i2c_sender_tristate_sr_reg_r_4_n_0\,
Q => \tristate_sr_reg[17]_U0_Inst_i2c_sender_tristate_sr_reg_r_5_n_0\,
R => '0'
);
\tristate_sr_reg[18]\: unisim.vcomponents.FDRE
port map (
C => clk_100,
CE => \tristate_sr[19]_i_1_n_0\,
D => \tristate_sr_reg_gate__0_n_0\,
Q => \tristate_sr_reg_n_0_[18]\,
R => \address[5]_i_1_n_0\
);
\tristate_sr_reg[19]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk_100,
CE => \tristate_sr[19]_i_1_n_0\,
D => \tristate_sr_reg_n_0_[18]\,
Q => \tristate_sr_reg_n_0_[19]\,
S => \address[5]_i_1_n_0\
);
\tristate_sr_reg[1]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk_100,
CE => \tristate_sr[19]_i_1_n_0\,
D => '0',
Q => \tristate_sr_reg_n_0_[1]\,
S => \address[5]_i_1_n_0\
);
\tristate_sr_reg[26]_srl7___U0_Inst_i2c_sender_tristate_sr_reg_r_5\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => '0',
A1 => '1',
A2 => '1',
A3 => '0',
CE => \tristate_sr[19]_i_1_n_0\,
CLK => clk_100,
D => \tristate_sr_reg_n_0_[19]\,
Q => \tristate_sr_reg[26]_srl7___U0_Inst_i2c_sender_tristate_sr_reg_r_5_n_0\
);
\tristate_sr_reg[27]_U0_Inst_i2c_sender_tristate_sr_reg_r_6\: unisim.vcomponents.FDRE
port map (
C => clk_100,
CE => \tristate_sr[19]_i_1_n_0\,
D => \tristate_sr_reg[26]_srl7___U0_Inst_i2c_sender_tristate_sr_reg_r_5_n_0\,
Q => \tristate_sr_reg[27]_U0_Inst_i2c_sender_tristate_sr_reg_r_6_n_0\,
R => '0'
);
\tristate_sr_reg[28]_inv\: unisim.vcomponents.FDSE
port map (
C => clk_100,
CE => \tristate_sr[19]_i_1_n_0\,
D => tristate_sr_reg_gate_n_0,
Q => \tristate_sr_reg[28]_inv_n_0\,
S => \address[5]_i_1_n_0\
);
\tristate_sr_reg[7]_srl6___U0_Inst_i2c_sender_tristate_sr_reg_r_4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => '1',
A1 => '0',
A2 => '1',
A3 => '0',
CE => \tristate_sr[19]_i_1_n_0\,
CLK => clk_100,
D => \tristate_sr_reg_n_0_[1]\,
Q => \tristate_sr_reg[7]_srl6___U0_Inst_i2c_sender_tristate_sr_reg_r_4_n_0\
);
\tristate_sr_reg[8]_U0_Inst_i2c_sender_tristate_sr_reg_r_5\: unisim.vcomponents.FDRE
port map (
C => clk_100,
CE => \tristate_sr[19]_i_1_n_0\,
D => \tristate_sr_reg[7]_srl6___U0_Inst_i2c_sender_tristate_sr_reg_r_4_n_0\,
Q => \tristate_sr_reg[8]_U0_Inst_i2c_sender_tristate_sr_reg_r_5_n_0\,
R => '0'
);
\tristate_sr_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk_100,
CE => \tristate_sr[19]_i_1_n_0\,
D => \tristate_sr_reg_gate__1_n_0\,
Q => \tristate_sr_reg_n_0_[9]\,
R => \address[5]_i_1_n_0\
);
tristate_sr_reg_gate: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => \tristate_sr_reg[27]_U0_Inst_i2c_sender_tristate_sr_reg_r_6_n_0\,
I1 => tristate_sr_reg_r_6_n_0,
O => tristate_sr_reg_gate_n_0
);
\tristate_sr_reg_gate__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \tristate_sr_reg[17]_U0_Inst_i2c_sender_tristate_sr_reg_r_5_n_0\,
I1 => tristate_sr_reg_r_5_n_0,
O => \tristate_sr_reg_gate__0_n_0\
);
\tristate_sr_reg_gate__1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \tristate_sr_reg[8]_U0_Inst_i2c_sender_tristate_sr_reg_r_5_n_0\,
I1 => tristate_sr_reg_r_5_n_0,
O => \tristate_sr_reg_gate__1_n_0\
);
tristate_sr_reg_r: unisim.vcomponents.FDRE
port map (
C => clk_100,
CE => \tristate_sr[19]_i_1_n_0\,
D => '1',
Q => tristate_sr_reg_r_n_0,
R => \address[5]_i_1_n_0\
);
tristate_sr_reg_r_0: unisim.vcomponents.FDRE
port map (
C => clk_100,
CE => \tristate_sr[19]_i_1_n_0\,
D => tristate_sr_reg_r_n_0,
Q => tristate_sr_reg_r_0_n_0,
R => \address[5]_i_1_n_0\
);
tristate_sr_reg_r_1: unisim.vcomponents.FDRE
port map (
C => clk_100,
CE => \tristate_sr[19]_i_1_n_0\,
D => tristate_sr_reg_r_0_n_0,
Q => tristate_sr_reg_r_1_n_0,
R => \address[5]_i_1_n_0\
);
tristate_sr_reg_r_2: unisim.vcomponents.FDRE
port map (
C => clk_100,
CE => \tristate_sr[19]_i_1_n_0\,
D => tristate_sr_reg_r_1_n_0,
Q => tristate_sr_reg_r_2_n_0,
R => \address[5]_i_1_n_0\
);
tristate_sr_reg_r_3: unisim.vcomponents.FDRE
port map (
C => clk_100,
CE => \tristate_sr[19]_i_1_n_0\,
D => tristate_sr_reg_r_2_n_0,
Q => tristate_sr_reg_r_3_n_0,
R => \address[5]_i_1_n_0\
);
tristate_sr_reg_r_4: unisim.vcomponents.FDRE
port map (
C => clk_100,
CE => \tristate_sr[19]_i_1_n_0\,
D => tristate_sr_reg_r_3_n_0,
Q => tristate_sr_reg_r_4_n_0,
R => \address[5]_i_1_n_0\
);
tristate_sr_reg_r_5: unisim.vcomponents.FDRE
port map (
C => clk_100,
CE => \tristate_sr[19]_i_1_n_0\,
D => tristate_sr_reg_r_4_n_0,
Q => tristate_sr_reg_r_5_n_0,
R => \address[5]_i_1_n_0\
);
tristate_sr_reg_r_6: unisim.vcomponents.FDRE
port map (
C => clk_100,
CE => \tristate_sr[19]_i_1_n_0\,
D => tristate_sr_reg_r_5_n_0,
Q => tristate_sr_reg_r_6_n_0,
R => \address[5]_i_1_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_zed_hdmi_0_0_zed_hdmi is
port (
hdmi_clk : out STD_LOGIC;
hdmi_hsync : out STD_LOGIC;
hdmi_vsync : out STD_LOGIC;
hdmi_de : out STD_LOGIC;
DI : out STD_LOGIC_VECTOR ( 0 to 0 );
\cr_int_reg[31]_0\ : out STD_LOGIC;
\cr_int_reg[31]_1\ : out STD_LOGIC;
O : out STD_LOGIC_VECTOR ( 1 downto 0 );
\cb_int_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\cr_int_reg[27]_0\ : out STD_LOGIC;
\cr_int_reg[27]_1\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
CO : out STD_LOGIC_VECTOR ( 0 to 0 );
\cr_int_reg[31]_2\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
\cr_int_reg[7]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\cr_int_reg[3]_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\cr_int_reg[3]_1\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\cr_int_reg[3]_2\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
\cr_int_reg[27]_2\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\cr_int_reg[7]_1\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\cr_int_reg[11]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\cr_int_reg[15]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\cr_int_reg[19]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\cr_int_reg[23]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\cr_int_reg[23]_1\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\y_int_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\y_int_reg[23]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\y_int_reg[7]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\y_int_reg[3]_1\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\y_int_reg[23]_1\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
\y_int_reg[23]_2\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\y_int_reg[19]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\y_int_reg[15]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\cb_int_reg[3]_1\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\cb_int_reg[3]_2\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\cb_int_reg[3]_3\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\cb_int_reg[27]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\cb_int_reg[15]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\cr_int_reg[15]_1\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\y_int_reg[3]_2\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\y_int_reg[19]_1\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\y_int_reg[23]_3\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\y_int_reg[15]_1\ : out STD_LOGIC_VECTOR ( 0 to 0 );
hdmi_sda : out STD_LOGIC;
hdmi_d : out STD_LOGIC_VECTOR ( 7 downto 0 );
hdmi_scl : out STD_LOGIC;
clk_x2 : in STD_LOGIC;
active : in STD_LOGIC;
clk_100 : in STD_LOGIC;
rgb888 : in STD_LOGIC_VECTOR ( 23 downto 0 );
\rgb888[8]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[8]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[8]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\rgb888[0]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[0]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[13]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\rgb888[8]_2\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[13]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[8]_3\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[12]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[8]_4\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[12]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[8]_5\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[8]_6\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[8]_7\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[8]_8\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[8]_9\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\rgb888[8]_10\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\rgb888[0]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\rgb888[0]_2\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[0]_3\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[0]_4\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[8]_11\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\rgb888[8]_12\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[8]_13\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[0]_5\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[0]_6\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\rgb888[8]_14\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[8]_15\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[8]_16\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[8]_17\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\rgb888[8]_18\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\rgb888[8]_19\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\rgb888[14]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[8]_20\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[8]_21\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\rgb888[0]_7\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[14]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\rgb888[1]\ : in STD_LOGIC_VECTOR ( 13 downto 0 );
\rgb888[14]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[8]_22\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[8]_23\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\rgb888[8]_24\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\rgb888[8]_25\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[8]_26\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[8]_27\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[8]_28\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[8]_29\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[8]_30\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\rgb888[1]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\rgb888[8]_31\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\rgb888[0]_8\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\rgb888[8]_32\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\rgb888[0]_9\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
hsync : in STD_LOGIC;
vsync : in STD_LOGIC;
clk : in STD_LOGIC
);
end system_zed_hdmi_0_0_zed_hdmi;
architecture STRUCTURE of system_zed_hdmi_0_0_zed_hdmi is
signal \^co\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal D1 : STD_LOGIC;
signal \^di\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^o\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal cb : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \cb[0]_i_1_n_0\ : STD_LOGIC;
signal \cb[1]_i_1_n_0\ : STD_LOGIC;
signal \cb[2]_i_1_n_0\ : STD_LOGIC;
signal \cb[3]_i_1_n_0\ : STD_LOGIC;
signal \cb[4]_i_1_n_0\ : STD_LOGIC;
signal \cb[5]_i_1_n_0\ : STD_LOGIC;
signal \cb[6]_i_1_n_0\ : STD_LOGIC;
signal \cb[7]_i_10_n_0\ : STD_LOGIC;
signal \cb[7]_i_11_n_0\ : STD_LOGIC;
signal \cb[7]_i_13_n_0\ : STD_LOGIC;
signal \cb[7]_i_14_n_0\ : STD_LOGIC;
signal \cb[7]_i_15_n_0\ : STD_LOGIC;
signal \cb[7]_i_16_n_0\ : STD_LOGIC;
signal \cb[7]_i_17_n_0\ : STD_LOGIC;
signal \cb[7]_i_18_n_0\ : STD_LOGIC;
signal \cb[7]_i_19_n_0\ : STD_LOGIC;
signal \cb[7]_i_20_n_0\ : STD_LOGIC;
signal \cb[7]_i_21_n_0\ : STD_LOGIC;
signal \cb[7]_i_22_n_0\ : STD_LOGIC;
signal \cb[7]_i_23_n_0\ : STD_LOGIC;
signal \cb[7]_i_24_n_0\ : STD_LOGIC;
signal \cb[7]_i_25_n_0\ : STD_LOGIC;
signal \cb[7]_i_26_n_0\ : STD_LOGIC;
signal \cb[7]_i_27_n_0\ : STD_LOGIC;
signal \cb[7]_i_28_n_0\ : STD_LOGIC;
signal \cb[7]_i_2_n_0\ : STD_LOGIC;
signal \cb[7]_i_4_n_0\ : STD_LOGIC;
signal \cb[7]_i_5_n_0\ : STD_LOGIC;
signal \cb[7]_i_6_n_0\ : STD_LOGIC;
signal \cb[7]_i_7_n_0\ : STD_LOGIC;
signal \cb[7]_i_8_n_0\ : STD_LOGIC;
signal \cb[7]_i_9_n_0\ : STD_LOGIC;
signal cb_hold : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \cb_hold[7]_i_1_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_100_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_101_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_102_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_103_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_104_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_105_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_106_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_107_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_108_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_109_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_10_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_110_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_111_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_112_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_113_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_114_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_11_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_12_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_13_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_14_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_15_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_19_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_20_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_22_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_27_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_29_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_2_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_30_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_31_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_32_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_34_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_35_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_36_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_37_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_39_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_3_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_40_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_41_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_42_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_43_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_44_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_45_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_46_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_47_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_49_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_4_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_50_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_51_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_52_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_53_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_54_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_55_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_56_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_57_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_58_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_59_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_5_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_60_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_61_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_62_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_63_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_64_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_65_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_67_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_68_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_69_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_6_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_70_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_71_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_72_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_73_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_74_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_76_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_77_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_78_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_79_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_7_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_80_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_82_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_83_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_84_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_85_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_86_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_87_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_88_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_89_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_8_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_91_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_92_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_93_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_94_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_95_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_96_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_97_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_98_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_99_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_9_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_10_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_11_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_12_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_13_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_14_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_15_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_16_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_17_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_18_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_21_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_23_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_25_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_27_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_28_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_29_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_2_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_30_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_3_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_43_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_44_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_45_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_46_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_4_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_5_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_6_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_7_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_8_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_9_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_10_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_11_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_12_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_13_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_14_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_15_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_16_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_17_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_18_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_21_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_23_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_26_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_28_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_29_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_2_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_30_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_31_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_34_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_35_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_36_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_37_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_3_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_4_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_5_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_6_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_7_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_8_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_9_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_10_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_11_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_12_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_13_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_14_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_15_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_16_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_17_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_18_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_20_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_22_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_25_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_29_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_2_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_30_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_31_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_32_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_3_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_4_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_5_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_6_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_7_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_8_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_9_n_0\ : STD_LOGIC;
signal \cb_int[27]_i_10_n_0\ : STD_LOGIC;
signal \cb_int[27]_i_12_n_0\ : STD_LOGIC;
signal \cb_int[27]_i_13_n_0\ : STD_LOGIC;
signal \cb_int[27]_i_14_n_0\ : STD_LOGIC;
signal \cb_int[27]_i_15_n_0\ : STD_LOGIC;
signal \cb_int[27]_i_2_n_0\ : STD_LOGIC;
signal \cb_int[27]_i_3_n_0\ : STD_LOGIC;
signal \cb_int[27]_i_4_n_0\ : STD_LOGIC;
signal \cb_int[27]_i_5_n_0\ : STD_LOGIC;
signal \cb_int[27]_i_6_n_0\ : STD_LOGIC;
signal \cb_int[27]_i_7_n_0\ : STD_LOGIC;
signal \cb_int[27]_i_8_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_13_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_15_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_16_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_2_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_31_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_32_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_35_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_36_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_38_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_39_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_3_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_40_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_41_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_4_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_5_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_67_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_68_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_69_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_6_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_70_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_71_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_72_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_74_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_75_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_76_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_77_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_78_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_79_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_80_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_81_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_82_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_95_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_96_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_97_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_98_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_100_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_101_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_102_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_103_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_104_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_105_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_106_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_10_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_12_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_13_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_17_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_18_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_22_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_23_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_24_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_25_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_27_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_28_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_29_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_2_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_30_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_31_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_3_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_45_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_46_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_47_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_48_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_49_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_4_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_50_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_51_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_52_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_53_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_54_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_55_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_56_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_5_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_64_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_65_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_66_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_67_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_69_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_6_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_70_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_71_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_72_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_76_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_77_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_78_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_79_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_7_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_80_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_81_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_82_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_83_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_89_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_8_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_90_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_91_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_92_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_93_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_99_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_9_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_10_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_11_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_13_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_14_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_16_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_17_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_19_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_21_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_22_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_2_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_39_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_3_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_40_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_41_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_42_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_4_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_52_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_53_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_54_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_55_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_56_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_57_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_58_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_59_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_5_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_60_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_62_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_63_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_64_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_65_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_67_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_68_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_69_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_6_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_70_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_71_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_72_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_73_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_74_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_75_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_76_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_77_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_78_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_79_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_7_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_80_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_81_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_82_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_8_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_9_n_0\ : STD_LOGIC;
signal cb_int_reg2 : STD_LOGIC_VECTOR ( 22 downto 1 );
signal cb_int_reg3 : STD_LOGIC_VECTOR ( 22 downto 1 );
signal cb_int_reg5 : STD_LOGIC_VECTOR ( 22 downto 1 );
signal cb_int_reg7 : STD_LOGIC_VECTOR ( 30 downto 8 );
signal cb_int_reg8 : STD_LOGIC;
signal \cb_int_reg[11]_i_16_n_0\ : STD_LOGIC;
signal \cb_int_reg[11]_i_16_n_1\ : STD_LOGIC;
signal \cb_int_reg[11]_i_16_n_2\ : STD_LOGIC;
signal \cb_int_reg[11]_i_16_n_3\ : STD_LOGIC;
signal \cb_int_reg[11]_i_17_n_0\ : STD_LOGIC;
signal \cb_int_reg[11]_i_17_n_1\ : STD_LOGIC;
signal \cb_int_reg[11]_i_17_n_2\ : STD_LOGIC;
signal \cb_int_reg[11]_i_17_n_3\ : STD_LOGIC;
signal \cb_int_reg[11]_i_18_n_2\ : STD_LOGIC;
signal \cb_int_reg[11]_i_18_n_3\ : STD_LOGIC;
signal \cb_int_reg[11]_i_1_n_0\ : STD_LOGIC;
signal \cb_int_reg[11]_i_1_n_1\ : STD_LOGIC;
signal \cb_int_reg[11]_i_1_n_2\ : STD_LOGIC;
signal \cb_int_reg[11]_i_1_n_3\ : STD_LOGIC;
signal \cb_int_reg[11]_i_1_n_4\ : STD_LOGIC;
signal \cb_int_reg[11]_i_1_n_5\ : STD_LOGIC;
signal \cb_int_reg[11]_i_1_n_6\ : STD_LOGIC;
signal \cb_int_reg[11]_i_1_n_7\ : STD_LOGIC;
signal \cb_int_reg[11]_i_24_n_1\ : STD_LOGIC;
signal \cb_int_reg[11]_i_24_n_2\ : STD_LOGIC;
signal \cb_int_reg[11]_i_24_n_3\ : STD_LOGIC;
signal \cb_int_reg[11]_i_24_n_4\ : STD_LOGIC;
signal \cb_int_reg[11]_i_24_n_5\ : STD_LOGIC;
signal \cb_int_reg[11]_i_24_n_6\ : STD_LOGIC;
signal \cb_int_reg[11]_i_24_n_7\ : STD_LOGIC;
signal \cb_int_reg[11]_i_25_n_0\ : STD_LOGIC;
signal \cb_int_reg[11]_i_25_n_1\ : STD_LOGIC;
signal \cb_int_reg[11]_i_25_n_2\ : STD_LOGIC;
signal \cb_int_reg[11]_i_25_n_3\ : STD_LOGIC;
signal \cb_int_reg[11]_i_26_n_0\ : STD_LOGIC;
signal \cb_int_reg[11]_i_26_n_1\ : STD_LOGIC;
signal \cb_int_reg[11]_i_26_n_2\ : STD_LOGIC;
signal \cb_int_reg[11]_i_26_n_3\ : STD_LOGIC;
signal \cb_int_reg[11]_i_28_n_0\ : STD_LOGIC;
signal \cb_int_reg[11]_i_28_n_1\ : STD_LOGIC;
signal \cb_int_reg[11]_i_28_n_2\ : STD_LOGIC;
signal \cb_int_reg[11]_i_28_n_3\ : STD_LOGIC;
signal \cb_int_reg[11]_i_33_n_0\ : STD_LOGIC;
signal \cb_int_reg[11]_i_33_n_1\ : STD_LOGIC;
signal \cb_int_reg[11]_i_33_n_2\ : STD_LOGIC;
signal \cb_int_reg[11]_i_33_n_3\ : STD_LOGIC;
signal \cb_int_reg[11]_i_38_n_0\ : STD_LOGIC;
signal \cb_int_reg[11]_i_38_n_1\ : STD_LOGIC;
signal \cb_int_reg[11]_i_38_n_2\ : STD_LOGIC;
signal \cb_int_reg[11]_i_38_n_3\ : STD_LOGIC;
signal \cb_int_reg[11]_i_48_n_0\ : STD_LOGIC;
signal \cb_int_reg[11]_i_48_n_1\ : STD_LOGIC;
signal \cb_int_reg[11]_i_48_n_2\ : STD_LOGIC;
signal \cb_int_reg[11]_i_48_n_3\ : STD_LOGIC;
signal \cb_int_reg[11]_i_66_n_0\ : STD_LOGIC;
signal \cb_int_reg[11]_i_66_n_1\ : STD_LOGIC;
signal \cb_int_reg[11]_i_66_n_2\ : STD_LOGIC;
signal \cb_int_reg[11]_i_66_n_3\ : STD_LOGIC;
signal \cb_int_reg[11]_i_75_n_0\ : STD_LOGIC;
signal \cb_int_reg[11]_i_75_n_1\ : STD_LOGIC;
signal \cb_int_reg[11]_i_75_n_2\ : STD_LOGIC;
signal \cb_int_reg[11]_i_75_n_3\ : STD_LOGIC;
signal \cb_int_reg[11]_i_81_n_0\ : STD_LOGIC;
signal \cb_int_reg[11]_i_81_n_1\ : STD_LOGIC;
signal \cb_int_reg[11]_i_81_n_2\ : STD_LOGIC;
signal \cb_int_reg[11]_i_81_n_3\ : STD_LOGIC;
signal \cb_int_reg[11]_i_90_n_0\ : STD_LOGIC;
signal \cb_int_reg[11]_i_90_n_1\ : STD_LOGIC;
signal \cb_int_reg[11]_i_90_n_2\ : STD_LOGIC;
signal \cb_int_reg[11]_i_90_n_3\ : STD_LOGIC;
signal \cb_int_reg[15]_i_1_n_0\ : STD_LOGIC;
signal \cb_int_reg[15]_i_1_n_1\ : STD_LOGIC;
signal \cb_int_reg[15]_i_1_n_2\ : STD_LOGIC;
signal \cb_int_reg[15]_i_1_n_3\ : STD_LOGIC;
signal \cb_int_reg[15]_i_1_n_4\ : STD_LOGIC;
signal \cb_int_reg[15]_i_1_n_5\ : STD_LOGIC;
signal \cb_int_reg[15]_i_1_n_6\ : STD_LOGIC;
signal \cb_int_reg[15]_i_1_n_7\ : STD_LOGIC;
signal \cb_int_reg[15]_i_20_n_0\ : STD_LOGIC;
signal \cb_int_reg[15]_i_20_n_1\ : STD_LOGIC;
signal \cb_int_reg[15]_i_20_n_2\ : STD_LOGIC;
signal \cb_int_reg[15]_i_20_n_3\ : STD_LOGIC;
signal \cb_int_reg[15]_i_33_n_0\ : STD_LOGIC;
signal \cb_int_reg[15]_i_33_n_1\ : STD_LOGIC;
signal \cb_int_reg[15]_i_33_n_2\ : STD_LOGIC;
signal \cb_int_reg[15]_i_33_n_3\ : STD_LOGIC;
signal \cb_int_reg[19]_i_1_n_0\ : STD_LOGIC;
signal \cb_int_reg[19]_i_1_n_1\ : STD_LOGIC;
signal \cb_int_reg[19]_i_1_n_2\ : STD_LOGIC;
signal \cb_int_reg[19]_i_1_n_3\ : STD_LOGIC;
signal \cb_int_reg[19]_i_1_n_4\ : STD_LOGIC;
signal \cb_int_reg[19]_i_1_n_5\ : STD_LOGIC;
signal \cb_int_reg[19]_i_1_n_6\ : STD_LOGIC;
signal \cb_int_reg[19]_i_1_n_7\ : STD_LOGIC;
signal \cb_int_reg[19]_i_20_n_0\ : STD_LOGIC;
signal \cb_int_reg[19]_i_20_n_1\ : STD_LOGIC;
signal \cb_int_reg[19]_i_20_n_2\ : STD_LOGIC;
signal \cb_int_reg[19]_i_20_n_3\ : STD_LOGIC;
signal \cb_int_reg[19]_i_25_n_0\ : STD_LOGIC;
signal \cb_int_reg[19]_i_25_n_1\ : STD_LOGIC;
signal \cb_int_reg[19]_i_25_n_2\ : STD_LOGIC;
signal \cb_int_reg[19]_i_25_n_3\ : STD_LOGIC;
signal \cb_int_reg[23]_i_1_n_0\ : STD_LOGIC;
signal \cb_int_reg[23]_i_1_n_1\ : STD_LOGIC;
signal \cb_int_reg[23]_i_1_n_2\ : STD_LOGIC;
signal \cb_int_reg[23]_i_1_n_3\ : STD_LOGIC;
signal \cb_int_reg[23]_i_1_n_4\ : STD_LOGIC;
signal \cb_int_reg[23]_i_1_n_5\ : STD_LOGIC;
signal \cb_int_reg[23]_i_1_n_6\ : STD_LOGIC;
signal \cb_int_reg[23]_i_1_n_7\ : STD_LOGIC;
signal \cb_int_reg[23]_i_24_n_0\ : STD_LOGIC;
signal \cb_int_reg[23]_i_24_n_1\ : STD_LOGIC;
signal \cb_int_reg[23]_i_24_n_2\ : STD_LOGIC;
signal \cb_int_reg[23]_i_24_n_3\ : STD_LOGIC;
signal \cb_int_reg[27]_i_1_n_0\ : STD_LOGIC;
signal \cb_int_reg[27]_i_1_n_1\ : STD_LOGIC;
signal \cb_int_reg[27]_i_1_n_2\ : STD_LOGIC;
signal \cb_int_reg[27]_i_1_n_3\ : STD_LOGIC;
signal \cb_int_reg[27]_i_1_n_4\ : STD_LOGIC;
signal \cb_int_reg[27]_i_1_n_5\ : STD_LOGIC;
signal \cb_int_reg[27]_i_1_n_6\ : STD_LOGIC;
signal \cb_int_reg[27]_i_1_n_7\ : STD_LOGIC;
signal \cb_int_reg[27]_i_9_n_1\ : STD_LOGIC;
signal \cb_int_reg[27]_i_9_n_2\ : STD_LOGIC;
signal \cb_int_reg[27]_i_9_n_3\ : STD_LOGIC;
signal \cb_int_reg[31]_i_11_n_1\ : STD_LOGIC;
signal \cb_int_reg[31]_i_11_n_3\ : STD_LOGIC;
signal \cb_int_reg[31]_i_12_n_1\ : STD_LOGIC;
signal \cb_int_reg[31]_i_12_n_3\ : STD_LOGIC;
signal \cb_int_reg[31]_i_12_n_6\ : STD_LOGIC;
signal \cb_int_reg[31]_i_12_n_7\ : STD_LOGIC;
signal \cb_int_reg[31]_i_14_n_0\ : STD_LOGIC;
signal \cb_int_reg[31]_i_14_n_1\ : STD_LOGIC;
signal \cb_int_reg[31]_i_14_n_2\ : STD_LOGIC;
signal \cb_int_reg[31]_i_14_n_3\ : STD_LOGIC;
signal \cb_int_reg[31]_i_1_n_1\ : STD_LOGIC;
signal \cb_int_reg[31]_i_1_n_2\ : STD_LOGIC;
signal \cb_int_reg[31]_i_1_n_3\ : STD_LOGIC;
signal \cb_int_reg[31]_i_1_n_4\ : STD_LOGIC;
signal \cb_int_reg[31]_i_1_n_5\ : STD_LOGIC;
signal \cb_int_reg[31]_i_1_n_6\ : STD_LOGIC;
signal \cb_int_reg[31]_i_1_n_7\ : STD_LOGIC;
signal \cb_int_reg[31]_i_30_n_0\ : STD_LOGIC;
signal \cb_int_reg[31]_i_30_n_1\ : STD_LOGIC;
signal \cb_int_reg[31]_i_30_n_2\ : STD_LOGIC;
signal \cb_int_reg[31]_i_30_n_3\ : STD_LOGIC;
signal \cb_int_reg[31]_i_33_n_0\ : STD_LOGIC;
signal \cb_int_reg[31]_i_33_n_1\ : STD_LOGIC;
signal \cb_int_reg[31]_i_33_n_2\ : STD_LOGIC;
signal \cb_int_reg[31]_i_33_n_3\ : STD_LOGIC;
signal \cb_int_reg[31]_i_33_n_4\ : STD_LOGIC;
signal \cb_int_reg[31]_i_33_n_5\ : STD_LOGIC;
signal \cb_int_reg[31]_i_33_n_6\ : STD_LOGIC;
signal \cb_int_reg[31]_i_33_n_7\ : STD_LOGIC;
signal \cb_int_reg[31]_i_34_n_2\ : STD_LOGIC;
signal \cb_int_reg[31]_i_34_n_7\ : STD_LOGIC;
signal \cb_int_reg[31]_i_37_n_0\ : STD_LOGIC;
signal \cb_int_reg[31]_i_37_n_1\ : STD_LOGIC;
signal \cb_int_reg[31]_i_37_n_2\ : STD_LOGIC;
signal \cb_int_reg[31]_i_37_n_3\ : STD_LOGIC;
signal \cb_int_reg[31]_i_73_n_0\ : STD_LOGIC;
signal \cb_int_reg[31]_i_73_n_1\ : STD_LOGIC;
signal \cb_int_reg[31]_i_73_n_2\ : STD_LOGIC;
signal \cb_int_reg[31]_i_73_n_3\ : STD_LOGIC;
signal \cb_int_reg[31]_i_73_n_4\ : STD_LOGIC;
signal \cb_int_reg[31]_i_73_n_5\ : STD_LOGIC;
signal \cb_int_reg[31]_i_73_n_6\ : STD_LOGIC;
signal \cb_int_reg[31]_i_73_n_7\ : STD_LOGIC;
signal \cb_int_reg[31]_i_7_n_1\ : STD_LOGIC;
signal \cb_int_reg[31]_i_7_n_3\ : STD_LOGIC;
signal \^cb_int_reg[3]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \cb_int_reg[3]_i_15_n_0\ : STD_LOGIC;
signal \cb_int_reg[3]_i_15_n_1\ : STD_LOGIC;
signal \cb_int_reg[3]_i_15_n_2\ : STD_LOGIC;
signal \cb_int_reg[3]_i_15_n_3\ : STD_LOGIC;
signal \cb_int_reg[3]_i_16_n_0\ : STD_LOGIC;
signal \cb_int_reg[3]_i_16_n_1\ : STD_LOGIC;
signal \cb_int_reg[3]_i_16_n_2\ : STD_LOGIC;
signal \cb_int_reg[3]_i_16_n_3\ : STD_LOGIC;
signal \cb_int_reg[3]_i_16_n_4\ : STD_LOGIC;
signal \cb_int_reg[3]_i_16_n_5\ : STD_LOGIC;
signal \cb_int_reg[3]_i_16_n_6\ : STD_LOGIC;
signal \cb_int_reg[3]_i_16_n_7\ : STD_LOGIC;
signal \cb_int_reg[3]_i_1_n_0\ : STD_LOGIC;
signal \cb_int_reg[3]_i_1_n_1\ : STD_LOGIC;
signal \cb_int_reg[3]_i_1_n_2\ : STD_LOGIC;
signal \cb_int_reg[3]_i_1_n_3\ : STD_LOGIC;
signal \cb_int_reg[3]_i_1_n_4\ : STD_LOGIC;
signal \cb_int_reg[3]_i_1_n_5\ : STD_LOGIC;
signal \cb_int_reg[3]_i_1_n_6\ : STD_LOGIC;
signal \cb_int_reg[3]_i_1_n_7\ : STD_LOGIC;
signal \cb_int_reg[3]_i_20_n_1\ : STD_LOGIC;
signal \cb_int_reg[3]_i_20_n_2\ : STD_LOGIC;
signal \cb_int_reg[3]_i_20_n_3\ : STD_LOGIC;
signal \cb_int_reg[3]_i_20_n_4\ : STD_LOGIC;
signal \cb_int_reg[3]_i_20_n_5\ : STD_LOGIC;
signal \cb_int_reg[3]_i_20_n_6\ : STD_LOGIC;
signal \cb_int_reg[3]_i_20_n_7\ : STD_LOGIC;
signal \cb_int_reg[3]_i_21_n_0\ : STD_LOGIC;
signal \cb_int_reg[3]_i_21_n_1\ : STD_LOGIC;
signal \cb_int_reg[3]_i_21_n_2\ : STD_LOGIC;
signal \cb_int_reg[3]_i_21_n_3\ : STD_LOGIC;
signal \cb_int_reg[3]_i_26_n_0\ : STD_LOGIC;
signal \cb_int_reg[3]_i_26_n_1\ : STD_LOGIC;
signal \cb_int_reg[3]_i_26_n_2\ : STD_LOGIC;
signal \cb_int_reg[3]_i_26_n_3\ : STD_LOGIC;
signal \cb_int_reg[3]_i_26_n_4\ : STD_LOGIC;
signal \cb_int_reg[3]_i_26_n_5\ : STD_LOGIC;
signal \cb_int_reg[3]_i_26_n_6\ : STD_LOGIC;
signal \cb_int_reg[3]_i_33_n_0\ : STD_LOGIC;
signal \cb_int_reg[3]_i_33_n_1\ : STD_LOGIC;
signal \cb_int_reg[3]_i_33_n_2\ : STD_LOGIC;
signal \cb_int_reg[3]_i_33_n_3\ : STD_LOGIC;
signal \cb_int_reg[3]_i_33_n_4\ : STD_LOGIC;
signal \cb_int_reg[3]_i_34_n_1\ : STD_LOGIC;
signal \cb_int_reg[3]_i_34_n_2\ : STD_LOGIC;
signal \cb_int_reg[3]_i_34_n_3\ : STD_LOGIC;
signal \cb_int_reg[3]_i_44_n_1\ : STD_LOGIC;
signal \cb_int_reg[3]_i_44_n_2\ : STD_LOGIC;
signal \cb_int_reg[3]_i_44_n_3\ : STD_LOGIC;
signal \cb_int_reg[3]_i_44_n_4\ : STD_LOGIC;
signal \cb_int_reg[3]_i_44_n_5\ : STD_LOGIC;
signal \cb_int_reg[3]_i_44_n_6\ : STD_LOGIC;
signal \cb_int_reg[3]_i_44_n_7\ : STD_LOGIC;
signal \cb_int_reg[3]_i_57_n_0\ : STD_LOGIC;
signal \cb_int_reg[3]_i_57_n_1\ : STD_LOGIC;
signal \cb_int_reg[3]_i_57_n_2\ : STD_LOGIC;
signal \cb_int_reg[3]_i_57_n_3\ : STD_LOGIC;
signal \cb_int_reg[3]_i_57_n_4\ : STD_LOGIC;
signal \cb_int_reg[3]_i_57_n_5\ : STD_LOGIC;
signal \cb_int_reg[3]_i_57_n_6\ : STD_LOGIC;
signal \cb_int_reg[3]_i_57_n_7\ : STD_LOGIC;
signal \cb_int_reg[3]_i_63_n_0\ : STD_LOGIC;
signal \cb_int_reg[3]_i_63_n_1\ : STD_LOGIC;
signal \cb_int_reg[3]_i_63_n_2\ : STD_LOGIC;
signal \cb_int_reg[3]_i_63_n_3\ : STD_LOGIC;
signal \cb_int_reg[3]_i_75_n_0\ : STD_LOGIC;
signal \cb_int_reg[3]_i_75_n_1\ : STD_LOGIC;
signal \cb_int_reg[3]_i_75_n_2\ : STD_LOGIC;
signal \cb_int_reg[3]_i_75_n_3\ : STD_LOGIC;
signal \cb_int_reg[3]_i_75_n_4\ : STD_LOGIC;
signal \cb_int_reg[3]_i_75_n_5\ : STD_LOGIC;
signal \cb_int_reg[3]_i_75_n_6\ : STD_LOGIC;
signal \cb_int_reg[3]_i_75_n_7\ : STD_LOGIC;
signal \cb_int_reg[3]_i_94_n_1\ : STD_LOGIC;
signal \cb_int_reg[3]_i_94_n_2\ : STD_LOGIC;
signal \cb_int_reg[3]_i_94_n_3\ : STD_LOGIC;
signal \cb_int_reg[3]_i_94_n_4\ : STD_LOGIC;
signal \cb_int_reg[3]_i_94_n_7\ : STD_LOGIC;
signal \cb_int_reg[7]_i_1_n_0\ : STD_LOGIC;
signal \cb_int_reg[7]_i_1_n_1\ : STD_LOGIC;
signal \cb_int_reg[7]_i_1_n_2\ : STD_LOGIC;
signal \cb_int_reg[7]_i_1_n_3\ : STD_LOGIC;
signal \cb_int_reg[7]_i_1_n_4\ : STD_LOGIC;
signal \cb_int_reg[7]_i_1_n_5\ : STD_LOGIC;
signal \cb_int_reg[7]_i_1_n_6\ : STD_LOGIC;
signal \cb_int_reg[7]_i_1_n_7\ : STD_LOGIC;
signal \cb_int_reg[7]_i_25_n_1\ : STD_LOGIC;
signal \cb_int_reg[7]_i_25_n_2\ : STD_LOGIC;
signal \cb_int_reg[7]_i_25_n_3\ : STD_LOGIC;
signal \cb_int_reg[7]_i_28_n_0\ : STD_LOGIC;
signal \cb_int_reg[7]_i_28_n_1\ : STD_LOGIC;
signal \cb_int_reg[7]_i_28_n_2\ : STD_LOGIC;
signal \cb_int_reg[7]_i_28_n_3\ : STD_LOGIC;
signal \cb_int_reg[7]_i_29_n_0\ : STD_LOGIC;
signal \cb_int_reg[7]_i_29_n_1\ : STD_LOGIC;
signal \cb_int_reg[7]_i_29_n_2\ : STD_LOGIC;
signal \cb_int_reg[7]_i_29_n_3\ : STD_LOGIC;
signal \cb_int_reg[7]_i_29_n_4\ : STD_LOGIC;
signal \cb_int_reg[7]_i_29_n_5\ : STD_LOGIC;
signal \cb_int_reg[7]_i_29_n_6\ : STD_LOGIC;
signal \cb_int_reg[7]_i_29_n_7\ : STD_LOGIC;
signal \cb_int_reg[7]_i_38_n_0\ : STD_LOGIC;
signal \cb_int_reg[7]_i_38_n_1\ : STD_LOGIC;
signal \cb_int_reg[7]_i_38_n_2\ : STD_LOGIC;
signal \cb_int_reg[7]_i_38_n_3\ : STD_LOGIC;
signal \cb_int_reg[7]_i_61_n_0\ : STD_LOGIC;
signal \cb_int_reg[7]_i_61_n_1\ : STD_LOGIC;
signal \cb_int_reg[7]_i_61_n_2\ : STD_LOGIC;
signal \cb_int_reg[7]_i_61_n_3\ : STD_LOGIC;
signal \cb_int_reg[7]_i_66_n_0\ : STD_LOGIC;
signal \cb_int_reg[7]_i_66_n_1\ : STD_LOGIC;
signal \cb_int_reg[7]_i_66_n_2\ : STD_LOGIC;
signal \cb_int_reg[7]_i_66_n_3\ : STD_LOGIC;
signal \cb_int_reg__0\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \cb_int_reg_n_0_[0]\ : STD_LOGIC;
signal \cb_int_reg_n_0_[1]\ : STD_LOGIC;
signal \cb_int_reg_n_0_[2]\ : STD_LOGIC;
signal \cb_int_reg_n_0_[3]\ : STD_LOGIC;
signal \cb_int_reg_n_0_[4]\ : STD_LOGIC;
signal \cb_int_reg_n_0_[5]\ : STD_LOGIC;
signal \cb_int_reg_n_0_[6]\ : STD_LOGIC;
signal \cb_int_reg_n_0_[7]\ : STD_LOGIC;
signal \cb_reg[7]_i_12_n_0\ : STD_LOGIC;
signal \cb_reg[7]_i_12_n_1\ : STD_LOGIC;
signal \cb_reg[7]_i_12_n_2\ : STD_LOGIC;
signal \cb_reg[7]_i_12_n_3\ : STD_LOGIC;
signal \cb_reg[7]_i_1_n_0\ : STD_LOGIC;
signal \cb_reg[7]_i_1_n_1\ : STD_LOGIC;
signal \cb_reg[7]_i_1_n_2\ : STD_LOGIC;
signal \cb_reg[7]_i_1_n_3\ : STD_LOGIC;
signal \cb_reg[7]_i_3_n_0\ : STD_LOGIC;
signal \cb_reg[7]_i_3_n_1\ : STD_LOGIC;
signal \cb_reg[7]_i_3_n_2\ : STD_LOGIC;
signal \cb_reg[7]_i_3_n_3\ : STD_LOGIC;
signal cb_regn_0_0 : STD_LOGIC;
signal cr : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \cr[0]_i_1_n_0\ : STD_LOGIC;
signal \cr[1]_i_1_n_0\ : STD_LOGIC;
signal \cr[2]_i_1_n_0\ : STD_LOGIC;
signal \cr[3]_i_1_n_0\ : STD_LOGIC;
signal \cr[4]_i_1_n_0\ : STD_LOGIC;
signal \cr[5]_i_1_n_0\ : STD_LOGIC;
signal \cr[6]_i_1_n_0\ : STD_LOGIC;
signal \cr[7]_i_10_n_0\ : STD_LOGIC;
signal \cr[7]_i_11_n_0\ : STD_LOGIC;
signal \cr[7]_i_13_n_0\ : STD_LOGIC;
signal \cr[7]_i_14_n_0\ : STD_LOGIC;
signal \cr[7]_i_15_n_0\ : STD_LOGIC;
signal \cr[7]_i_16_n_0\ : STD_LOGIC;
signal \cr[7]_i_17_n_0\ : STD_LOGIC;
signal \cr[7]_i_18_n_0\ : STD_LOGIC;
signal \cr[7]_i_19_n_0\ : STD_LOGIC;
signal \cr[7]_i_20_n_0\ : STD_LOGIC;
signal \cr[7]_i_21_n_0\ : STD_LOGIC;
signal \cr[7]_i_22_n_0\ : STD_LOGIC;
signal \cr[7]_i_23_n_0\ : STD_LOGIC;
signal \cr[7]_i_24_n_0\ : STD_LOGIC;
signal \cr[7]_i_25_n_0\ : STD_LOGIC;
signal \cr[7]_i_26_n_0\ : STD_LOGIC;
signal \cr[7]_i_27_n_0\ : STD_LOGIC;
signal \cr[7]_i_28_n_0\ : STD_LOGIC;
signal \cr[7]_i_2_n_0\ : STD_LOGIC;
signal \cr[7]_i_4_n_0\ : STD_LOGIC;
signal \cr[7]_i_5_n_0\ : STD_LOGIC;
signal \cr[7]_i_6_n_0\ : STD_LOGIC;
signal \cr[7]_i_7_n_0\ : STD_LOGIC;
signal \cr[7]_i_8_n_0\ : STD_LOGIC;
signal \cr[7]_i_9_n_0\ : STD_LOGIC;
signal \cr_hold_reg_n_0_[0]\ : STD_LOGIC;
signal \cr_hold_reg_n_0_[1]\ : STD_LOGIC;
signal \cr_hold_reg_n_0_[2]\ : STD_LOGIC;
signal \cr_hold_reg_n_0_[3]\ : STD_LOGIC;
signal \cr_hold_reg_n_0_[4]\ : STD_LOGIC;
signal \cr_hold_reg_n_0_[5]\ : STD_LOGIC;
signal \cr_hold_reg_n_0_[6]\ : STD_LOGIC;
signal \cr_hold_reg_n_0_[7]\ : STD_LOGIC;
signal \cr_int[11]_i_100_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_101_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_102_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_104_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_105_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_106_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_107_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_109_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_10_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_110_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_111_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_112_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_113_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_114_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_115_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_117_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_118_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_119_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_11_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_120_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_121_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_122_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_123_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_124_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_126_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_127_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_128_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_129_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_12_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_130_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_131_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_132_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_133_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_134_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_135_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_136_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_137_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_138_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_139_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_13_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_140_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_141_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_142_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_143_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_144_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_145_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_146_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_147_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_148_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_149_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_14_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_150_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_151_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_152_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_153_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_154_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_155_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_156_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_15_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_22_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_23_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_24_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_25_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_27_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_2_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_32_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_33_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_34_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_35_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_37_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_38_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_39_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_3_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_40_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_42_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_43_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_44_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_45_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_47_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_48_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_49_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_4_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_50_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_52_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_53_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_54_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_55_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_57_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_58_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_59_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_5_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_60_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_65_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_66_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_67_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_68_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_6_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_70_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_71_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_72_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_73_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_74_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_75_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_76_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_77_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_78_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_7_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_80_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_81_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_82_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_83_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_84_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_85_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_86_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_87_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_88_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_89_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_8_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_90_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_91_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_93_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_94_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_95_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_96_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_97_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_98_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_99_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_9_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_10_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_11_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_12_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_13_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_14_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_15_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_16_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_17_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_18_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_19_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_22_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_23_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_24_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_25_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_26_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_27_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_29_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_2_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_30_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_31_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_32_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_33_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_34_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_35_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_36_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_3_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_40_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_41_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_42_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_43_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_48_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_49_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_4_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_50_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_51_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_5_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_6_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_7_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_8_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_9_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_10_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_11_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_12_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_13_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_14_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_15_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_16_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_17_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_18_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_19_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_22_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_23_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_24_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_25_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_26_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_27_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_29_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_2_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_30_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_31_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_32_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_33_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_34_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_35_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_36_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_38_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_39_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_3_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_40_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_41_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_4_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_5_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_6_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_7_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_8_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_9_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_10_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_11_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_12_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_13_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_14_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_15_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_16_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_17_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_18_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_19_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_21_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_22_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_23_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_24_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_25_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_26_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_27_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_28_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_29_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_2_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_30_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_3_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_4_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_5_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_6_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_7_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_8_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_9_n_0\ : STD_LOGIC;
signal \cr_int[27]_i_10_n_0\ : STD_LOGIC;
signal \cr_int[27]_i_11_n_0\ : STD_LOGIC;
signal \cr_int[27]_i_12_n_0\ : STD_LOGIC;
signal \cr_int[27]_i_13_n_0\ : STD_LOGIC;
signal \cr_int[27]_i_2_n_0\ : STD_LOGIC;
signal \cr_int[27]_i_3_n_0\ : STD_LOGIC;
signal \cr_int[27]_i_4_n_0\ : STD_LOGIC;
signal \cr_int[27]_i_5_n_0\ : STD_LOGIC;
signal \cr_int[27]_i_6_n_0\ : STD_LOGIC;
signal \cr_int[27]_i_7_n_0\ : STD_LOGIC;
signal \cr_int[27]_i_8_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_100_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_103_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_108_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_109_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_110_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_111_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_112_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_113_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_114_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_115_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_116_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_117_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_118_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_119_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_120_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_121_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_122_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_123_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_124_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_125_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_126_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_13_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_15_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_16_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_17_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_18_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_19_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_20_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_22_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_23_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_25_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_26_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_2_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_31_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_32_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_33_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_34_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_35_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_37_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_38_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_3_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_40_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_41_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_42_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_43_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_44_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_45_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_46_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_47_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_4_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_50_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_51_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_52_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_53_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_55_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_56_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_57_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_58_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_59_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_5_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_60_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_61_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_62_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_6_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_71_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_72_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_73_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_74_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_75_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_76_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_77_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_78_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_79_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_80_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_81_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_82_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_83_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_84_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_85_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_87_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_88_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_89_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_90_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_92_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_93_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_94_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_95_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_96_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_97_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_10_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_11_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_13_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_14_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_17_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_18_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_22_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_23_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_24_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_25_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_28_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_29_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_2_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_30_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_31_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_34_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_35_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_36_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_37_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_38_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_39_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_3_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_40_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_41_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_43_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_44_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_45_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_46_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_47_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_48_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_49_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_4_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_50_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_51_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_52_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_53_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_55_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_56_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_57_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_58_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_5_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_60_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_61_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_62_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_63_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_66_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_67_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_68_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_69_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_6_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_71_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_72_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_73_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_74_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_75_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_76_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_77_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_78_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_79_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_7_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_80_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_81_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_82_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_83_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_84_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_85_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_86_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_87_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_88_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_89_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_8_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_90_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_91_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_92_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_93_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_94_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_95_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_96_n_0\ : STD_LOGIC;
signal \cr_int[7]_i_11_n_0\ : STD_LOGIC;
signal \cr_int[7]_i_12_n_0\ : STD_LOGIC;
signal \cr_int[7]_i_14_n_0\ : STD_LOGIC;
signal \cr_int[7]_i_15_n_0\ : STD_LOGIC;
signal \cr_int[7]_i_17_n_0\ : STD_LOGIC;
signal \cr_int[7]_i_18_n_0\ : STD_LOGIC;
signal \cr_int[7]_i_20_n_0\ : STD_LOGIC;
signal \cr_int[7]_i_21_n_0\ : STD_LOGIC;
signal \cr_int[7]_i_25_n_0\ : STD_LOGIC;
signal \cr_int[7]_i_26_n_0\ : STD_LOGIC;
signal \cr_int[7]_i_27_n_0\ : STD_LOGIC;
signal \cr_int[7]_i_28_n_0\ : STD_LOGIC;
signal \cr_int[7]_i_2_n_0\ : STD_LOGIC;
signal \cr_int[7]_i_3_n_0\ : STD_LOGIC;
signal \cr_int[7]_i_4_n_0\ : STD_LOGIC;
signal \cr_int[7]_i_5_n_0\ : STD_LOGIC;
signal \cr_int[7]_i_6_n_0\ : STD_LOGIC;
signal \cr_int[7]_i_7_n_0\ : STD_LOGIC;
signal \cr_int[7]_i_8_n_0\ : STD_LOGIC;
signal \cr_int[7]_i_9_n_0\ : STD_LOGIC;
signal cr_int_reg3 : STD_LOGIC_VECTOR ( 7 to 7 );
signal \cr_int_reg3__0\ : STD_LOGIC_VECTOR ( 8 downto 1 );
signal cr_int_reg4 : STD_LOGIC_VECTOR ( 22 downto 1 );
signal cr_int_reg6 : STD_LOGIC_VECTOR ( 30 downto 8 );
signal cr_int_reg7 : STD_LOGIC;
signal \^cr_int_reg[11]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \cr_int_reg[11]_i_103_n_0\ : STD_LOGIC;
signal \cr_int_reg[11]_i_103_n_1\ : STD_LOGIC;
signal \cr_int_reg[11]_i_103_n_2\ : STD_LOGIC;
signal \cr_int_reg[11]_i_103_n_3\ : STD_LOGIC;
signal \cr_int_reg[11]_i_108_n_0\ : STD_LOGIC;
signal \cr_int_reg[11]_i_108_n_1\ : STD_LOGIC;
signal \cr_int_reg[11]_i_108_n_2\ : STD_LOGIC;
signal \cr_int_reg[11]_i_108_n_3\ : STD_LOGIC;
signal \cr_int_reg[11]_i_116_n_0\ : STD_LOGIC;
signal \cr_int_reg[11]_i_116_n_1\ : STD_LOGIC;
signal \cr_int_reg[11]_i_116_n_2\ : STD_LOGIC;
signal \cr_int_reg[11]_i_116_n_3\ : STD_LOGIC;
signal \cr_int_reg[11]_i_125_n_0\ : STD_LOGIC;
signal \cr_int_reg[11]_i_125_n_1\ : STD_LOGIC;
signal \cr_int_reg[11]_i_125_n_2\ : STD_LOGIC;
signal \cr_int_reg[11]_i_125_n_3\ : STD_LOGIC;
signal \cr_int_reg[11]_i_16_n_0\ : STD_LOGIC;
signal \cr_int_reg[11]_i_16_n_1\ : STD_LOGIC;
signal \cr_int_reg[11]_i_16_n_2\ : STD_LOGIC;
signal \cr_int_reg[11]_i_16_n_3\ : STD_LOGIC;
signal \cr_int_reg[11]_i_16_n_4\ : STD_LOGIC;
signal \cr_int_reg[11]_i_16_n_5\ : STD_LOGIC;
signal \cr_int_reg[11]_i_16_n_6\ : STD_LOGIC;
signal \cr_int_reg[11]_i_16_n_7\ : STD_LOGIC;
signal \cr_int_reg[11]_i_17_n_0\ : STD_LOGIC;
signal \cr_int_reg[11]_i_17_n_1\ : STD_LOGIC;
signal \cr_int_reg[11]_i_17_n_2\ : STD_LOGIC;
signal \cr_int_reg[11]_i_17_n_3\ : STD_LOGIC;
signal \cr_int_reg[11]_i_18_n_1\ : STD_LOGIC;
signal \cr_int_reg[11]_i_18_n_2\ : STD_LOGIC;
signal \cr_int_reg[11]_i_18_n_3\ : STD_LOGIC;
signal \cr_int_reg[11]_i_18_n_4\ : STD_LOGIC;
signal \cr_int_reg[11]_i_18_n_5\ : STD_LOGIC;
signal \cr_int_reg[11]_i_18_n_6\ : STD_LOGIC;
signal \cr_int_reg[11]_i_18_n_7\ : STD_LOGIC;
signal \cr_int_reg[11]_i_19_n_0\ : STD_LOGIC;
signal \cr_int_reg[11]_i_19_n_1\ : STD_LOGIC;
signal \cr_int_reg[11]_i_19_n_2\ : STD_LOGIC;
signal \cr_int_reg[11]_i_19_n_3\ : STD_LOGIC;
signal \cr_int_reg[11]_i_1_n_0\ : STD_LOGIC;
signal \cr_int_reg[11]_i_1_n_1\ : STD_LOGIC;
signal \cr_int_reg[11]_i_1_n_2\ : STD_LOGIC;
signal \cr_int_reg[11]_i_1_n_3\ : STD_LOGIC;
signal \cr_int_reg[11]_i_1_n_4\ : STD_LOGIC;
signal \cr_int_reg[11]_i_1_n_5\ : STD_LOGIC;
signal \cr_int_reg[11]_i_1_n_6\ : STD_LOGIC;
signal \cr_int_reg[11]_i_1_n_7\ : STD_LOGIC;
signal \cr_int_reg[11]_i_20_n_1\ : STD_LOGIC;
signal \cr_int_reg[11]_i_20_n_2\ : STD_LOGIC;
signal \cr_int_reg[11]_i_20_n_3\ : STD_LOGIC;
signal \cr_int_reg[11]_i_21_n_0\ : STD_LOGIC;
signal \cr_int_reg[11]_i_21_n_1\ : STD_LOGIC;
signal \cr_int_reg[11]_i_21_n_2\ : STD_LOGIC;
signal \cr_int_reg[11]_i_21_n_3\ : STD_LOGIC;
signal \cr_int_reg[11]_i_29_n_0\ : STD_LOGIC;
signal \cr_int_reg[11]_i_29_n_1\ : STD_LOGIC;
signal \cr_int_reg[11]_i_29_n_2\ : STD_LOGIC;
signal \cr_int_reg[11]_i_29_n_3\ : STD_LOGIC;
signal \cr_int_reg[11]_i_30_n_1\ : STD_LOGIC;
signal \cr_int_reg[11]_i_30_n_2\ : STD_LOGIC;
signal \cr_int_reg[11]_i_30_n_3\ : STD_LOGIC;
signal \cr_int_reg[11]_i_31_n_0\ : STD_LOGIC;
signal \cr_int_reg[11]_i_31_n_1\ : STD_LOGIC;
signal \cr_int_reg[11]_i_31_n_2\ : STD_LOGIC;
signal \cr_int_reg[11]_i_31_n_3\ : STD_LOGIC;
signal \cr_int_reg[11]_i_31_n_4\ : STD_LOGIC;
signal \cr_int_reg[11]_i_31_n_5\ : STD_LOGIC;
signal \cr_int_reg[11]_i_31_n_6\ : STD_LOGIC;
signal \cr_int_reg[11]_i_31_n_7\ : STD_LOGIC;
signal \cr_int_reg[11]_i_36_n_0\ : STD_LOGIC;
signal \cr_int_reg[11]_i_36_n_1\ : STD_LOGIC;
signal \cr_int_reg[11]_i_36_n_2\ : STD_LOGIC;
signal \cr_int_reg[11]_i_36_n_3\ : STD_LOGIC;
signal \cr_int_reg[11]_i_41_n_0\ : STD_LOGIC;
signal \cr_int_reg[11]_i_41_n_1\ : STD_LOGIC;
signal \cr_int_reg[11]_i_41_n_2\ : STD_LOGIC;
signal \cr_int_reg[11]_i_41_n_3\ : STD_LOGIC;
signal \cr_int_reg[11]_i_41_n_4\ : STD_LOGIC;
signal \cr_int_reg[11]_i_41_n_5\ : STD_LOGIC;
signal \cr_int_reg[11]_i_41_n_6\ : STD_LOGIC;
signal \cr_int_reg[11]_i_41_n_7\ : STD_LOGIC;
signal \cr_int_reg[11]_i_46_n_0\ : STD_LOGIC;
signal \cr_int_reg[11]_i_46_n_1\ : STD_LOGIC;
signal \cr_int_reg[11]_i_46_n_2\ : STD_LOGIC;
signal \cr_int_reg[11]_i_46_n_3\ : STD_LOGIC;
signal \cr_int_reg[11]_i_51_n_0\ : STD_LOGIC;
signal \cr_int_reg[11]_i_51_n_1\ : STD_LOGIC;
signal \cr_int_reg[11]_i_51_n_2\ : STD_LOGIC;
signal \cr_int_reg[11]_i_51_n_3\ : STD_LOGIC;
signal \cr_int_reg[11]_i_56_n_0\ : STD_LOGIC;
signal \cr_int_reg[11]_i_56_n_1\ : STD_LOGIC;
signal \cr_int_reg[11]_i_56_n_2\ : STD_LOGIC;
signal \cr_int_reg[11]_i_56_n_3\ : STD_LOGIC;
signal \cr_int_reg[11]_i_69_n_0\ : STD_LOGIC;
signal \cr_int_reg[11]_i_69_n_1\ : STD_LOGIC;
signal \cr_int_reg[11]_i_69_n_2\ : STD_LOGIC;
signal \cr_int_reg[11]_i_69_n_3\ : STD_LOGIC;
signal \cr_int_reg[11]_i_79_n_0\ : STD_LOGIC;
signal \cr_int_reg[11]_i_79_n_1\ : STD_LOGIC;
signal \cr_int_reg[11]_i_79_n_2\ : STD_LOGIC;
signal \cr_int_reg[11]_i_79_n_3\ : STD_LOGIC;
signal \cr_int_reg[11]_i_92_n_0\ : STD_LOGIC;
signal \cr_int_reg[11]_i_92_n_1\ : STD_LOGIC;
signal \cr_int_reg[11]_i_92_n_2\ : STD_LOGIC;
signal \cr_int_reg[11]_i_92_n_3\ : STD_LOGIC;
signal \^cr_int_reg[15]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \cr_int_reg[15]_i_1_n_0\ : STD_LOGIC;
signal \cr_int_reg[15]_i_1_n_1\ : STD_LOGIC;
signal \cr_int_reg[15]_i_1_n_2\ : STD_LOGIC;
signal \cr_int_reg[15]_i_1_n_3\ : STD_LOGIC;
signal \cr_int_reg[15]_i_1_n_4\ : STD_LOGIC;
signal \cr_int_reg[15]_i_1_n_5\ : STD_LOGIC;
signal \cr_int_reg[15]_i_1_n_6\ : STD_LOGIC;
signal \cr_int_reg[15]_i_1_n_7\ : STD_LOGIC;
signal \cr_int_reg[15]_i_20_n_0\ : STD_LOGIC;
signal \cr_int_reg[15]_i_20_n_1\ : STD_LOGIC;
signal \cr_int_reg[15]_i_20_n_2\ : STD_LOGIC;
signal \cr_int_reg[15]_i_20_n_3\ : STD_LOGIC;
signal \cr_int_reg[15]_i_21_n_0\ : STD_LOGIC;
signal \cr_int_reg[15]_i_21_n_1\ : STD_LOGIC;
signal \cr_int_reg[15]_i_21_n_2\ : STD_LOGIC;
signal \cr_int_reg[15]_i_21_n_3\ : STD_LOGIC;
signal \cr_int_reg[15]_i_28_n_0\ : STD_LOGIC;
signal \cr_int_reg[15]_i_28_n_1\ : STD_LOGIC;
signal \cr_int_reg[15]_i_28_n_2\ : STD_LOGIC;
signal \cr_int_reg[15]_i_28_n_3\ : STD_LOGIC;
signal \cr_int_reg[15]_i_38_n_0\ : STD_LOGIC;
signal \cr_int_reg[15]_i_38_n_1\ : STD_LOGIC;
signal \cr_int_reg[15]_i_38_n_2\ : STD_LOGIC;
signal \cr_int_reg[15]_i_38_n_3\ : STD_LOGIC;
signal \cr_int_reg[15]_i_38_n_4\ : STD_LOGIC;
signal \cr_int_reg[15]_i_38_n_5\ : STD_LOGIC;
signal \cr_int_reg[15]_i_38_n_6\ : STD_LOGIC;
signal \cr_int_reg[15]_i_38_n_7\ : STD_LOGIC;
signal \^cr_int_reg[19]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \cr_int_reg[19]_i_1_n_0\ : STD_LOGIC;
signal \cr_int_reg[19]_i_1_n_1\ : STD_LOGIC;
signal \cr_int_reg[19]_i_1_n_2\ : STD_LOGIC;
signal \cr_int_reg[19]_i_1_n_3\ : STD_LOGIC;
signal \cr_int_reg[19]_i_1_n_4\ : STD_LOGIC;
signal \cr_int_reg[19]_i_1_n_5\ : STD_LOGIC;
signal \cr_int_reg[19]_i_1_n_6\ : STD_LOGIC;
signal \cr_int_reg[19]_i_1_n_7\ : STD_LOGIC;
signal \cr_int_reg[19]_i_20_n_0\ : STD_LOGIC;
signal \cr_int_reg[19]_i_20_n_1\ : STD_LOGIC;
signal \cr_int_reg[19]_i_20_n_2\ : STD_LOGIC;
signal \cr_int_reg[19]_i_20_n_3\ : STD_LOGIC;
signal \cr_int_reg[19]_i_21_n_0\ : STD_LOGIC;
signal \cr_int_reg[19]_i_21_n_1\ : STD_LOGIC;
signal \cr_int_reg[19]_i_21_n_2\ : STD_LOGIC;
signal \cr_int_reg[19]_i_21_n_3\ : STD_LOGIC;
signal \cr_int_reg[19]_i_28_n_0\ : STD_LOGIC;
signal \cr_int_reg[19]_i_28_n_1\ : STD_LOGIC;
signal \cr_int_reg[19]_i_28_n_2\ : STD_LOGIC;
signal \cr_int_reg[19]_i_28_n_3\ : STD_LOGIC;
signal \^cr_int_reg[23]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^cr_int_reg[23]_1\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \cr_int_reg[23]_i_1_n_0\ : STD_LOGIC;
signal \cr_int_reg[23]_i_1_n_1\ : STD_LOGIC;
signal \cr_int_reg[23]_i_1_n_2\ : STD_LOGIC;
signal \cr_int_reg[23]_i_1_n_3\ : STD_LOGIC;
signal \cr_int_reg[23]_i_1_n_4\ : STD_LOGIC;
signal \cr_int_reg[23]_i_1_n_5\ : STD_LOGIC;
signal \cr_int_reg[23]_i_1_n_6\ : STD_LOGIC;
signal \cr_int_reg[23]_i_1_n_7\ : STD_LOGIC;
signal \cr_int_reg[23]_i_20_n_0\ : STD_LOGIC;
signal \cr_int_reg[23]_i_20_n_1\ : STD_LOGIC;
signal \cr_int_reg[23]_i_20_n_2\ : STD_LOGIC;
signal \cr_int_reg[23]_i_20_n_3\ : STD_LOGIC;
signal \^cr_int_reg[27]_0\ : STD_LOGIC;
signal \^cr_int_reg[27]_1\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^cr_int_reg[27]_2\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \cr_int_reg[27]_i_1_n_0\ : STD_LOGIC;
signal \cr_int_reg[27]_i_1_n_1\ : STD_LOGIC;
signal \cr_int_reg[27]_i_1_n_2\ : STD_LOGIC;
signal \cr_int_reg[27]_i_1_n_3\ : STD_LOGIC;
signal \cr_int_reg[27]_i_1_n_4\ : STD_LOGIC;
signal \cr_int_reg[27]_i_1_n_5\ : STD_LOGIC;
signal \cr_int_reg[27]_i_1_n_6\ : STD_LOGIC;
signal \cr_int_reg[27]_i_1_n_7\ : STD_LOGIC;
signal \cr_int_reg[27]_i_9_n_3\ : STD_LOGIC;
signal \^cr_int_reg[31]_0\ : STD_LOGIC;
signal \^cr_int_reg[31]_1\ : STD_LOGIC;
signal \^cr_int_reg[31]_2\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \cr_int_reg[31]_i_101_n_1\ : STD_LOGIC;
signal \cr_int_reg[31]_i_101_n_3\ : STD_LOGIC;
signal \cr_int_reg[31]_i_101_n_6\ : STD_LOGIC;
signal \cr_int_reg[31]_i_101_n_7\ : STD_LOGIC;
signal \cr_int_reg[31]_i_102_n_0\ : STD_LOGIC;
signal \cr_int_reg[31]_i_102_n_1\ : STD_LOGIC;
signal \cr_int_reg[31]_i_102_n_2\ : STD_LOGIC;
signal \cr_int_reg[31]_i_102_n_3\ : STD_LOGIC;
signal \cr_int_reg[31]_i_102_n_4\ : STD_LOGIC;
signal \cr_int_reg[31]_i_102_n_5\ : STD_LOGIC;
signal \cr_int_reg[31]_i_102_n_6\ : STD_LOGIC;
signal \cr_int_reg[31]_i_102_n_7\ : STD_LOGIC;
signal \cr_int_reg[31]_i_11_n_1\ : STD_LOGIC;
signal \cr_int_reg[31]_i_11_n_2\ : STD_LOGIC;
signal \cr_int_reg[31]_i_11_n_3\ : STD_LOGIC;
signal \cr_int_reg[31]_i_11_n_4\ : STD_LOGIC;
signal \cr_int_reg[31]_i_11_n_5\ : STD_LOGIC;
signal \cr_int_reg[31]_i_11_n_6\ : STD_LOGIC;
signal \cr_int_reg[31]_i_11_n_7\ : STD_LOGIC;
signal \cr_int_reg[31]_i_12_n_1\ : STD_LOGIC;
signal \cr_int_reg[31]_i_12_n_3\ : STD_LOGIC;
signal \cr_int_reg[31]_i_14_n_0\ : STD_LOGIC;
signal \cr_int_reg[31]_i_14_n_1\ : STD_LOGIC;
signal \cr_int_reg[31]_i_14_n_2\ : STD_LOGIC;
signal \cr_int_reg[31]_i_14_n_3\ : STD_LOGIC;
signal \cr_int_reg[31]_i_14_n_4\ : STD_LOGIC;
signal \cr_int_reg[31]_i_14_n_5\ : STD_LOGIC;
signal \cr_int_reg[31]_i_14_n_6\ : STD_LOGIC;
signal \cr_int_reg[31]_i_14_n_7\ : STD_LOGIC;
signal \cr_int_reg[31]_i_1_n_1\ : STD_LOGIC;
signal \cr_int_reg[31]_i_1_n_2\ : STD_LOGIC;
signal \cr_int_reg[31]_i_1_n_3\ : STD_LOGIC;
signal \cr_int_reg[31]_i_1_n_4\ : STD_LOGIC;
signal \cr_int_reg[31]_i_1_n_5\ : STD_LOGIC;
signal \cr_int_reg[31]_i_1_n_6\ : STD_LOGIC;
signal \cr_int_reg[31]_i_1_n_7\ : STD_LOGIC;
signal \cr_int_reg[31]_i_21_n_0\ : STD_LOGIC;
signal \cr_int_reg[31]_i_21_n_1\ : STD_LOGIC;
signal \cr_int_reg[31]_i_21_n_2\ : STD_LOGIC;
signal \cr_int_reg[31]_i_21_n_3\ : STD_LOGIC;
signal \cr_int_reg[31]_i_21_n_4\ : STD_LOGIC;
signal \cr_int_reg[31]_i_21_n_5\ : STD_LOGIC;
signal \cr_int_reg[31]_i_21_n_6\ : STD_LOGIC;
signal \cr_int_reg[31]_i_21_n_7\ : STD_LOGIC;
signal \cr_int_reg[31]_i_24_n_0\ : STD_LOGIC;
signal \cr_int_reg[31]_i_24_n_1\ : STD_LOGIC;
signal \cr_int_reg[31]_i_24_n_2\ : STD_LOGIC;
signal \cr_int_reg[31]_i_24_n_3\ : STD_LOGIC;
signal \cr_int_reg[31]_i_30_n_0\ : STD_LOGIC;
signal \cr_int_reg[31]_i_30_n_1\ : STD_LOGIC;
signal \cr_int_reg[31]_i_30_n_2\ : STD_LOGIC;
signal \cr_int_reg[31]_i_30_n_3\ : STD_LOGIC;
signal \cr_int_reg[31]_i_30_n_4\ : STD_LOGIC;
signal \cr_int_reg[31]_i_30_n_5\ : STD_LOGIC;
signal \cr_int_reg[31]_i_30_n_6\ : STD_LOGIC;
signal \cr_int_reg[31]_i_30_n_7\ : STD_LOGIC;
signal \cr_int_reg[31]_i_36_n_0\ : STD_LOGIC;
signal \cr_int_reg[31]_i_36_n_1\ : STD_LOGIC;
signal \cr_int_reg[31]_i_36_n_2\ : STD_LOGIC;
signal \cr_int_reg[31]_i_36_n_3\ : STD_LOGIC;
signal \cr_int_reg[31]_i_39_n_0\ : STD_LOGIC;
signal \cr_int_reg[31]_i_39_n_1\ : STD_LOGIC;
signal \cr_int_reg[31]_i_39_n_2\ : STD_LOGIC;
signal \cr_int_reg[31]_i_39_n_3\ : STD_LOGIC;
signal \cr_int_reg[31]_i_39_n_4\ : STD_LOGIC;
signal \cr_int_reg[31]_i_39_n_5\ : STD_LOGIC;
signal \cr_int_reg[31]_i_39_n_6\ : STD_LOGIC;
signal \cr_int_reg[31]_i_39_n_7\ : STD_LOGIC;
signal \cr_int_reg[31]_i_48_n_2\ : STD_LOGIC;
signal \cr_int_reg[31]_i_48_n_7\ : STD_LOGIC;
signal \cr_int_reg[31]_i_49_n_0\ : STD_LOGIC;
signal \cr_int_reg[31]_i_49_n_1\ : STD_LOGIC;
signal \cr_int_reg[31]_i_49_n_2\ : STD_LOGIC;
signal \cr_int_reg[31]_i_49_n_3\ : STD_LOGIC;
signal \cr_int_reg[31]_i_49_n_4\ : STD_LOGIC;
signal \cr_int_reg[31]_i_49_n_5\ : STD_LOGIC;
signal \cr_int_reg[31]_i_49_n_6\ : STD_LOGIC;
signal \cr_int_reg[31]_i_49_n_7\ : STD_LOGIC;
signal \cr_int_reg[31]_i_63_n_2\ : STD_LOGIC;
signal \cr_int_reg[31]_i_63_n_7\ : STD_LOGIC;
signal \cr_int_reg[31]_i_70_n_0\ : STD_LOGIC;
signal \cr_int_reg[31]_i_70_n_1\ : STD_LOGIC;
signal \cr_int_reg[31]_i_70_n_2\ : STD_LOGIC;
signal \cr_int_reg[31]_i_70_n_3\ : STD_LOGIC;
signal \cr_int_reg[31]_i_7_n_1\ : STD_LOGIC;
signal \cr_int_reg[31]_i_7_n_2\ : STD_LOGIC;
signal \cr_int_reg[31]_i_7_n_3\ : STD_LOGIC;
signal \cr_int_reg[31]_i_7_n_5\ : STD_LOGIC;
signal \cr_int_reg[31]_i_7_n_6\ : STD_LOGIC;
signal \cr_int_reg[31]_i_7_n_7\ : STD_LOGIC;
signal \cr_int_reg[31]_i_86_n_0\ : STD_LOGIC;
signal \cr_int_reg[31]_i_86_n_1\ : STD_LOGIC;
signal \cr_int_reg[31]_i_86_n_2\ : STD_LOGIC;
signal \cr_int_reg[31]_i_86_n_3\ : STD_LOGIC;
signal \cr_int_reg[31]_i_86_n_4\ : STD_LOGIC;
signal \cr_int_reg[31]_i_86_n_5\ : STD_LOGIC;
signal \cr_int_reg[31]_i_86_n_6\ : STD_LOGIC;
signal \cr_int_reg[31]_i_86_n_7\ : STD_LOGIC;
signal \cr_int_reg[31]_i_8_n_1\ : STD_LOGIC;
signal \cr_int_reg[31]_i_8_n_3\ : STD_LOGIC;
signal \cr_int_reg[31]_i_8_n_6\ : STD_LOGIC;
signal \cr_int_reg[31]_i_8_n_7\ : STD_LOGIC;
signal \cr_int_reg[31]_i_91_n_0\ : STD_LOGIC;
signal \cr_int_reg[31]_i_91_n_1\ : STD_LOGIC;
signal \cr_int_reg[31]_i_91_n_2\ : STD_LOGIC;
signal \cr_int_reg[31]_i_91_n_3\ : STD_LOGIC;
signal \cr_int_reg[31]_i_91_n_4\ : STD_LOGIC;
signal \cr_int_reg[31]_i_91_n_5\ : STD_LOGIC;
signal \cr_int_reg[31]_i_91_n_6\ : STD_LOGIC;
signal \cr_int_reg[31]_i_91_n_7\ : STD_LOGIC;
signal \cr_int_reg[31]_i_9_n_3\ : STD_LOGIC;
signal \^cr_int_reg[3]_0\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \^cr_int_reg[3]_1\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^cr_int_reg[3]_2\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \cr_int_reg[3]_i_15_n_0\ : STD_LOGIC;
signal \cr_int_reg[3]_i_15_n_1\ : STD_LOGIC;
signal \cr_int_reg[3]_i_15_n_2\ : STD_LOGIC;
signal \cr_int_reg[3]_i_15_n_3\ : STD_LOGIC;
signal \cr_int_reg[3]_i_16_n_0\ : STD_LOGIC;
signal \cr_int_reg[3]_i_16_n_1\ : STD_LOGIC;
signal \cr_int_reg[3]_i_16_n_2\ : STD_LOGIC;
signal \cr_int_reg[3]_i_16_n_3\ : STD_LOGIC;
signal \cr_int_reg[3]_i_16_n_4\ : STD_LOGIC;
signal \cr_int_reg[3]_i_16_n_5\ : STD_LOGIC;
signal \cr_int_reg[3]_i_16_n_6\ : STD_LOGIC;
signal \cr_int_reg[3]_i_16_n_7\ : STD_LOGIC;
signal \cr_int_reg[3]_i_19_n_0\ : STD_LOGIC;
signal \cr_int_reg[3]_i_19_n_1\ : STD_LOGIC;
signal \cr_int_reg[3]_i_19_n_2\ : STD_LOGIC;
signal \cr_int_reg[3]_i_19_n_3\ : STD_LOGIC;
signal \cr_int_reg[3]_i_19_n_7\ : STD_LOGIC;
signal \cr_int_reg[3]_i_1_n_0\ : STD_LOGIC;
signal \cr_int_reg[3]_i_1_n_1\ : STD_LOGIC;
signal \cr_int_reg[3]_i_1_n_2\ : STD_LOGIC;
signal \cr_int_reg[3]_i_1_n_3\ : STD_LOGIC;
signal \cr_int_reg[3]_i_1_n_4\ : STD_LOGIC;
signal \cr_int_reg[3]_i_1_n_5\ : STD_LOGIC;
signal \cr_int_reg[3]_i_1_n_6\ : STD_LOGIC;
signal \cr_int_reg[3]_i_1_n_7\ : STD_LOGIC;
signal \cr_int_reg[3]_i_20_n_0\ : STD_LOGIC;
signal \cr_int_reg[3]_i_20_n_1\ : STD_LOGIC;
signal \cr_int_reg[3]_i_20_n_2\ : STD_LOGIC;
signal \cr_int_reg[3]_i_20_n_3\ : STD_LOGIC;
signal \cr_int_reg[3]_i_21_n_0\ : STD_LOGIC;
signal \cr_int_reg[3]_i_21_n_1\ : STD_LOGIC;
signal \cr_int_reg[3]_i_21_n_2\ : STD_LOGIC;
signal \cr_int_reg[3]_i_21_n_3\ : STD_LOGIC;
signal \cr_int_reg[3]_i_26_n_1\ : STD_LOGIC;
signal \cr_int_reg[3]_i_26_n_3\ : STD_LOGIC;
signal \cr_int_reg[3]_i_26_n_6\ : STD_LOGIC;
signal \cr_int_reg[3]_i_26_n_7\ : STD_LOGIC;
signal \cr_int_reg[3]_i_27_n_0\ : STD_LOGIC;
signal \cr_int_reg[3]_i_27_n_1\ : STD_LOGIC;
signal \cr_int_reg[3]_i_27_n_2\ : STD_LOGIC;
signal \cr_int_reg[3]_i_27_n_3\ : STD_LOGIC;
signal \cr_int_reg[3]_i_27_n_4\ : STD_LOGIC;
signal \cr_int_reg[3]_i_27_n_5\ : STD_LOGIC;
signal \cr_int_reg[3]_i_27_n_6\ : STD_LOGIC;
signal \cr_int_reg[3]_i_27_n_7\ : STD_LOGIC;
signal \cr_int_reg[3]_i_32_n_0\ : STD_LOGIC;
signal \cr_int_reg[3]_i_32_n_1\ : STD_LOGIC;
signal \cr_int_reg[3]_i_32_n_2\ : STD_LOGIC;
signal \cr_int_reg[3]_i_32_n_3\ : STD_LOGIC;
signal \cr_int_reg[3]_i_32_n_4\ : STD_LOGIC;
signal \cr_int_reg[3]_i_33_n_0\ : STD_LOGIC;
signal \cr_int_reg[3]_i_33_n_1\ : STD_LOGIC;
signal \cr_int_reg[3]_i_33_n_2\ : STD_LOGIC;
signal \cr_int_reg[3]_i_33_n_3\ : STD_LOGIC;
signal \cr_int_reg[3]_i_33_n_4\ : STD_LOGIC;
signal \cr_int_reg[3]_i_33_n_5\ : STD_LOGIC;
signal \cr_int_reg[3]_i_33_n_6\ : STD_LOGIC;
signal \cr_int_reg[3]_i_42_n_0\ : STD_LOGIC;
signal \cr_int_reg[3]_i_42_n_1\ : STD_LOGIC;
signal \cr_int_reg[3]_i_42_n_2\ : STD_LOGIC;
signal \cr_int_reg[3]_i_42_n_3\ : STD_LOGIC;
signal \cr_int_reg[3]_i_54_n_0\ : STD_LOGIC;
signal \cr_int_reg[3]_i_54_n_1\ : STD_LOGIC;
signal \cr_int_reg[3]_i_54_n_2\ : STD_LOGIC;
signal \cr_int_reg[3]_i_54_n_3\ : STD_LOGIC;
signal \cr_int_reg[3]_i_54_n_4\ : STD_LOGIC;
signal \cr_int_reg[3]_i_54_n_5\ : STD_LOGIC;
signal \cr_int_reg[3]_i_54_n_6\ : STD_LOGIC;
signal \cr_int_reg[3]_i_54_n_7\ : STD_LOGIC;
signal \cr_int_reg[3]_i_59_n_0\ : STD_LOGIC;
signal \cr_int_reg[3]_i_59_n_1\ : STD_LOGIC;
signal \cr_int_reg[3]_i_59_n_2\ : STD_LOGIC;
signal \cr_int_reg[3]_i_59_n_3\ : STD_LOGIC;
signal \cr_int_reg[3]_i_64_n_0\ : STD_LOGIC;
signal \cr_int_reg[3]_i_64_n_1\ : STD_LOGIC;
signal \cr_int_reg[3]_i_64_n_2\ : STD_LOGIC;
signal \cr_int_reg[3]_i_64_n_3\ : STD_LOGIC;
signal \cr_int_reg[3]_i_64_n_4\ : STD_LOGIC;
signal \cr_int_reg[3]_i_64_n_5\ : STD_LOGIC;
signal \cr_int_reg[3]_i_64_n_6\ : STD_LOGIC;
signal \cr_int_reg[3]_i_64_n_7\ : STD_LOGIC;
signal \cr_int_reg[3]_i_65_n_0\ : STD_LOGIC;
signal \cr_int_reg[3]_i_65_n_1\ : STD_LOGIC;
signal \cr_int_reg[3]_i_65_n_2\ : STD_LOGIC;
signal \cr_int_reg[3]_i_65_n_3\ : STD_LOGIC;
signal \cr_int_reg[3]_i_65_n_4\ : STD_LOGIC;
signal \cr_int_reg[3]_i_65_n_5\ : STD_LOGIC;
signal \cr_int_reg[3]_i_65_n_6\ : STD_LOGIC;
signal \cr_int_reg[3]_i_70_n_0\ : STD_LOGIC;
signal \cr_int_reg[3]_i_70_n_1\ : STD_LOGIC;
signal \cr_int_reg[3]_i_70_n_2\ : STD_LOGIC;
signal \cr_int_reg[3]_i_70_n_3\ : STD_LOGIC;
signal \cr_int_reg[3]_i_70_n_4\ : STD_LOGIC;
signal \cr_int_reg[3]_i_70_n_5\ : STD_LOGIC;
signal \cr_int_reg[3]_i_70_n_6\ : STD_LOGIC;
signal \cr_int_reg[3]_i_70_n_7\ : STD_LOGIC;
signal \^cr_int_reg[7]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^cr_int_reg[7]_1\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \cr_int_reg[7]_i_1_n_0\ : STD_LOGIC;
signal \cr_int_reg[7]_i_1_n_1\ : STD_LOGIC;
signal \cr_int_reg[7]_i_1_n_2\ : STD_LOGIC;
signal \cr_int_reg[7]_i_1_n_3\ : STD_LOGIC;
signal \cr_int_reg[7]_i_1_n_4\ : STD_LOGIC;
signal \cr_int_reg[7]_i_1_n_5\ : STD_LOGIC;
signal \cr_int_reg[7]_i_1_n_6\ : STD_LOGIC;
signal \cr_int_reg[7]_i_1_n_7\ : STD_LOGIC;
signal \cr_int_reg[7]_i_23_n_0\ : STD_LOGIC;
signal \cr_int_reg[7]_i_23_n_1\ : STD_LOGIC;
signal \cr_int_reg[7]_i_23_n_2\ : STD_LOGIC;
signal \cr_int_reg[7]_i_23_n_3\ : STD_LOGIC;
signal \cr_int_reg__0\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \cr_int_reg_n_0_[0]\ : STD_LOGIC;
signal \cr_int_reg_n_0_[1]\ : STD_LOGIC;
signal \cr_int_reg_n_0_[2]\ : STD_LOGIC;
signal \cr_int_reg_n_0_[3]\ : STD_LOGIC;
signal \cr_int_reg_n_0_[4]\ : STD_LOGIC;
signal \cr_int_reg_n_0_[5]\ : STD_LOGIC;
signal \cr_int_reg_n_0_[6]\ : STD_LOGIC;
signal \cr_int_reg_n_0_[7]\ : STD_LOGIC;
signal \cr_reg[7]_i_12_n_0\ : STD_LOGIC;
signal \cr_reg[7]_i_12_n_1\ : STD_LOGIC;
signal \cr_reg[7]_i_12_n_2\ : STD_LOGIC;
signal \cr_reg[7]_i_12_n_3\ : STD_LOGIC;
signal \cr_reg[7]_i_1_n_0\ : STD_LOGIC;
signal \cr_reg[7]_i_1_n_1\ : STD_LOGIC;
signal \cr_reg[7]_i_1_n_2\ : STD_LOGIC;
signal \cr_reg[7]_i_1_n_3\ : STD_LOGIC;
signal \cr_reg[7]_i_3_n_0\ : STD_LOGIC;
signal \cr_reg[7]_i_3_n_1\ : STD_LOGIC;
signal \cr_reg[7]_i_3_n_2\ : STD_LOGIC;
signal \cr_reg[7]_i_3_n_3\ : STD_LOGIC;
signal edge : STD_LOGIC;
signal edge_i_1_n_0 : STD_LOGIC;
signal edge_rb : STD_LOGIC;
signal edge_rb_i_1_n_0 : STD_LOGIC;
signal \hdmi_d[10]_i_1_n_0\ : STD_LOGIC;
signal \hdmi_d[11]_i_1_n_0\ : STD_LOGIC;
signal \hdmi_d[12]_i_1_n_0\ : STD_LOGIC;
signal \hdmi_d[13]_i_1_n_0\ : STD_LOGIC;
signal \hdmi_d[14]_i_1_n_0\ : STD_LOGIC;
signal \hdmi_d[15]_i_1_n_0\ : STD_LOGIC;
signal \hdmi_d[15]_i_2_n_0\ : STD_LOGIC;
signal \hdmi_d[8]_i_1_n_0\ : STD_LOGIC;
signal \hdmi_d[9]_i_1_n_0\ : STD_LOGIC;
signal hdmi_vsync_i_1_n_0 : STD_LOGIC;
signal p_0_in : STD_LOGIC;
signal p_1_in : STD_LOGIC_VECTOR ( 7 downto 0 );
signal y : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \y[0]_i_1_n_0\ : STD_LOGIC;
signal \y[1]_i_1_n_0\ : STD_LOGIC;
signal \y[2]_i_1_n_0\ : STD_LOGIC;
signal \y[3]_i_1_n_0\ : STD_LOGIC;
signal \y[4]_i_1_n_0\ : STD_LOGIC;
signal \y[5]_i_1_n_0\ : STD_LOGIC;
signal \y[6]_i_1_n_0\ : STD_LOGIC;
signal \y[7]_i_10_n_0\ : STD_LOGIC;
signal \y[7]_i_11_n_0\ : STD_LOGIC;
signal \y[7]_i_13_n_0\ : STD_LOGIC;
signal \y[7]_i_14_n_0\ : STD_LOGIC;
signal \y[7]_i_15_n_0\ : STD_LOGIC;
signal \y[7]_i_16_n_0\ : STD_LOGIC;
signal \y[7]_i_17_n_0\ : STD_LOGIC;
signal \y[7]_i_18_n_0\ : STD_LOGIC;
signal \y[7]_i_19_n_0\ : STD_LOGIC;
signal \y[7]_i_20_n_0\ : STD_LOGIC;
signal \y[7]_i_21_n_0\ : STD_LOGIC;
signal \y[7]_i_22_n_0\ : STD_LOGIC;
signal \y[7]_i_23_n_0\ : STD_LOGIC;
signal \y[7]_i_24_n_0\ : STD_LOGIC;
signal \y[7]_i_25_n_0\ : STD_LOGIC;
signal \y[7]_i_26_n_0\ : STD_LOGIC;
signal \y[7]_i_27_n_0\ : STD_LOGIC;
signal \y[7]_i_28_n_0\ : STD_LOGIC;
signal \y[7]_i_2_n_0\ : STD_LOGIC;
signal \y[7]_i_4_n_0\ : STD_LOGIC;
signal \y[7]_i_5_n_0\ : STD_LOGIC;
signal \y[7]_i_6_n_0\ : STD_LOGIC;
signal \y[7]_i_7_n_0\ : STD_LOGIC;
signal \y[7]_i_8_n_0\ : STD_LOGIC;
signal \y[7]_i_9_n_0\ : STD_LOGIC;
signal y_hold : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \y_int[11]_i_100_n_0\ : STD_LOGIC;
signal \y_int[11]_i_10_n_0\ : STD_LOGIC;
signal \y_int[11]_i_12_n_0\ : STD_LOGIC;
signal \y_int[11]_i_16_n_0\ : STD_LOGIC;
signal \y_int[11]_i_19_n_0\ : STD_LOGIC;
signal \y_int[11]_i_29_n_0\ : STD_LOGIC;
signal \y_int[11]_i_2_n_0\ : STD_LOGIC;
signal \y_int[11]_i_30_n_0\ : STD_LOGIC;
signal \y_int[11]_i_31_n_0\ : STD_LOGIC;
signal \y_int[11]_i_32_n_0\ : STD_LOGIC;
signal \y_int[11]_i_34_n_0\ : STD_LOGIC;
signal \y_int[11]_i_35_n_0\ : STD_LOGIC;
signal \y_int[11]_i_36_n_0\ : STD_LOGIC;
signal \y_int[11]_i_37_n_0\ : STD_LOGIC;
signal \y_int[11]_i_3_n_0\ : STD_LOGIC;
signal \y_int[11]_i_40_n_0\ : STD_LOGIC;
signal \y_int[11]_i_41_n_0\ : STD_LOGIC;
signal \y_int[11]_i_42_n_0\ : STD_LOGIC;
signal \y_int[11]_i_43_n_0\ : STD_LOGIC;
signal \y_int[11]_i_45_n_0\ : STD_LOGIC;
signal \y_int[11]_i_46_n_0\ : STD_LOGIC;
signal \y_int[11]_i_47_n_0\ : STD_LOGIC;
signal \y_int[11]_i_48_n_0\ : STD_LOGIC;
signal \y_int[11]_i_4_n_0\ : STD_LOGIC;
signal \y_int[11]_i_50_n_0\ : STD_LOGIC;
signal \y_int[11]_i_51_n_0\ : STD_LOGIC;
signal \y_int[11]_i_52_n_0\ : STD_LOGIC;
signal \y_int[11]_i_53_n_0\ : STD_LOGIC;
signal \y_int[11]_i_58_n_0\ : STD_LOGIC;
signal \y_int[11]_i_59_n_0\ : STD_LOGIC;
signal \y_int[11]_i_5_n_0\ : STD_LOGIC;
signal \y_int[11]_i_60_n_0\ : STD_LOGIC;
signal \y_int[11]_i_61_n_0\ : STD_LOGIC;
signal \y_int[11]_i_62_n_0\ : STD_LOGIC;
signal \y_int[11]_i_63_n_0\ : STD_LOGIC;
signal \y_int[11]_i_64_n_0\ : STD_LOGIC;
signal \y_int[11]_i_65_n_0\ : STD_LOGIC;
signal \y_int[11]_i_66_n_0\ : STD_LOGIC;
signal \y_int[11]_i_67_n_0\ : STD_LOGIC;
signal \y_int[11]_i_68_n_0\ : STD_LOGIC;
signal \y_int[11]_i_69_n_0\ : STD_LOGIC;
signal \y_int[11]_i_6_n_0\ : STD_LOGIC;
signal \y_int[11]_i_70_n_0\ : STD_LOGIC;
signal \y_int[11]_i_71_n_0\ : STD_LOGIC;
signal \y_int[11]_i_72_n_0\ : STD_LOGIC;
signal \y_int[11]_i_73_n_0\ : STD_LOGIC;
signal \y_int[11]_i_74_n_0\ : STD_LOGIC;
signal \y_int[11]_i_75_n_0\ : STD_LOGIC;
signal \y_int[11]_i_76_n_0\ : STD_LOGIC;
signal \y_int[11]_i_77_n_0\ : STD_LOGIC;
signal \y_int[11]_i_78_n_0\ : STD_LOGIC;
signal \y_int[11]_i_79_n_0\ : STD_LOGIC;
signal \y_int[11]_i_7_n_0\ : STD_LOGIC;
signal \y_int[11]_i_81_n_0\ : STD_LOGIC;
signal \y_int[11]_i_82_n_0\ : STD_LOGIC;
signal \y_int[11]_i_83_n_0\ : STD_LOGIC;
signal \y_int[11]_i_84_n_0\ : STD_LOGIC;
signal \y_int[11]_i_86_n_0\ : STD_LOGIC;
signal \y_int[11]_i_87_n_0\ : STD_LOGIC;
signal \y_int[11]_i_88_n_0\ : STD_LOGIC;
signal \y_int[11]_i_89_n_0\ : STD_LOGIC;
signal \y_int[11]_i_8_n_0\ : STD_LOGIC;
signal \y_int[11]_i_90_n_0\ : STD_LOGIC;
signal \y_int[11]_i_91_n_0\ : STD_LOGIC;
signal \y_int[11]_i_92_n_0\ : STD_LOGIC;
signal \y_int[11]_i_93_n_0\ : STD_LOGIC;
signal \y_int[11]_i_94_n_0\ : STD_LOGIC;
signal \y_int[11]_i_95_n_0\ : STD_LOGIC;
signal \y_int[11]_i_96_n_0\ : STD_LOGIC;
signal \y_int[11]_i_97_n_0\ : STD_LOGIC;
signal \y_int[11]_i_98_n_0\ : STD_LOGIC;
signal \y_int[11]_i_99_n_0\ : STD_LOGIC;
signal \y_int[11]_i_9_n_0\ : STD_LOGIC;
signal \y_int[15]_i_10_n_0\ : STD_LOGIC;
signal \y_int[15]_i_12_n_0\ : STD_LOGIC;
signal \y_int[15]_i_16_n_0\ : STD_LOGIC;
signal \y_int[15]_i_18_n_0\ : STD_LOGIC;
signal \y_int[15]_i_25_n_0\ : STD_LOGIC;
signal \y_int[15]_i_26_n_0\ : STD_LOGIC;
signal \y_int[15]_i_27_n_0\ : STD_LOGIC;
signal \y_int[15]_i_28_n_0\ : STD_LOGIC;
signal \y_int[15]_i_29_n_0\ : STD_LOGIC;
signal \y_int[15]_i_2_n_0\ : STD_LOGIC;
signal \y_int[15]_i_30_n_0\ : STD_LOGIC;
signal \y_int[15]_i_31_n_0\ : STD_LOGIC;
signal \y_int[15]_i_32_n_0\ : STD_LOGIC;
signal \y_int[15]_i_3_n_0\ : STD_LOGIC;
signal \y_int[15]_i_40_n_0\ : STD_LOGIC;
signal \y_int[15]_i_41_n_0\ : STD_LOGIC;
signal \y_int[15]_i_42_n_0\ : STD_LOGIC;
signal \y_int[15]_i_43_n_0\ : STD_LOGIC;
signal \y_int[15]_i_48_n_0\ : STD_LOGIC;
signal \y_int[15]_i_49_n_0\ : STD_LOGIC;
signal \y_int[15]_i_4_n_0\ : STD_LOGIC;
signal \y_int[15]_i_50_n_0\ : STD_LOGIC;
signal \y_int[15]_i_51_n_0\ : STD_LOGIC;
signal \y_int[15]_i_5_n_0\ : STD_LOGIC;
signal \y_int[15]_i_6_n_0\ : STD_LOGIC;
signal \y_int[15]_i_7_n_0\ : STD_LOGIC;
signal \y_int[15]_i_8_n_0\ : STD_LOGIC;
signal \y_int[15]_i_9_n_0\ : STD_LOGIC;
signal \y_int[19]_i_10_n_0\ : STD_LOGIC;
signal \y_int[19]_i_12_n_0\ : STD_LOGIC;
signal \y_int[19]_i_16_n_0\ : STD_LOGIC;
signal \y_int[19]_i_18_n_0\ : STD_LOGIC;
signal \y_int[19]_i_25_n_0\ : STD_LOGIC;
signal \y_int[19]_i_26_n_0\ : STD_LOGIC;
signal \y_int[19]_i_27_n_0\ : STD_LOGIC;
signal \y_int[19]_i_28_n_0\ : STD_LOGIC;
signal \y_int[19]_i_29_n_0\ : STD_LOGIC;
signal \y_int[19]_i_2_n_0\ : STD_LOGIC;
signal \y_int[19]_i_30_n_0\ : STD_LOGIC;
signal \y_int[19]_i_31_n_0\ : STD_LOGIC;
signal \y_int[19]_i_32_n_0\ : STD_LOGIC;
signal \y_int[19]_i_3_n_0\ : STD_LOGIC;
signal \y_int[19]_i_48_n_0\ : STD_LOGIC;
signal \y_int[19]_i_49_n_0\ : STD_LOGIC;
signal \y_int[19]_i_4_n_0\ : STD_LOGIC;
signal \y_int[19]_i_50_n_0\ : STD_LOGIC;
signal \y_int[19]_i_51_n_0\ : STD_LOGIC;
signal \y_int[19]_i_5_n_0\ : STD_LOGIC;
signal \y_int[19]_i_6_n_0\ : STD_LOGIC;
signal \y_int[19]_i_7_n_0\ : STD_LOGIC;
signal \y_int[19]_i_8_n_0\ : STD_LOGIC;
signal \y_int[19]_i_9_n_0\ : STD_LOGIC;
signal \y_int[23]_i_100_n_0\ : STD_LOGIC;
signal \y_int[23]_i_101_n_0\ : STD_LOGIC;
signal \y_int[23]_i_102_n_0\ : STD_LOGIC;
signal \y_int[23]_i_103_n_0\ : STD_LOGIC;
signal \y_int[23]_i_104_n_0\ : STD_LOGIC;
signal \y_int[23]_i_12_n_0\ : STD_LOGIC;
signal \y_int[23]_i_14_n_0\ : STD_LOGIC;
signal \y_int[23]_i_18_n_0\ : STD_LOGIC;
signal \y_int[23]_i_20_n_0\ : STD_LOGIC;
signal \y_int[23]_i_26_n_0\ : STD_LOGIC;
signal \y_int[23]_i_27_n_0\ : STD_LOGIC;
signal \y_int[23]_i_28_n_0\ : STD_LOGIC;
signal \y_int[23]_i_29_n_0\ : STD_LOGIC;
signal \y_int[23]_i_2_n_0\ : STD_LOGIC;
signal \y_int[23]_i_30_n_0\ : STD_LOGIC;
signal \y_int[23]_i_31_n_0\ : STD_LOGIC;
signal \y_int[23]_i_36_n_0\ : STD_LOGIC;
signal \y_int[23]_i_37_n_0\ : STD_LOGIC;
signal \y_int[23]_i_38_n_0\ : STD_LOGIC;
signal \y_int[23]_i_39_n_0\ : STD_LOGIC;
signal \y_int[23]_i_3_n_0\ : STD_LOGIC;
signal \y_int[23]_i_40_n_0\ : STD_LOGIC;
signal \y_int[23]_i_41_n_0\ : STD_LOGIC;
signal \y_int[23]_i_42_n_0\ : STD_LOGIC;
signal \y_int[23]_i_43_n_0\ : STD_LOGIC;
signal \y_int[23]_i_46_n_0\ : STD_LOGIC;
signal \y_int[23]_i_47_n_0\ : STD_LOGIC;
signal \y_int[23]_i_48_n_0\ : STD_LOGIC;
signal \y_int[23]_i_49_n_0\ : STD_LOGIC;
signal \y_int[23]_i_4_n_0\ : STD_LOGIC;
signal \y_int[23]_i_52_n_0\ : STD_LOGIC;
signal \y_int[23]_i_53_n_0\ : STD_LOGIC;
signal \y_int[23]_i_54_n_0\ : STD_LOGIC;
signal \y_int[23]_i_55_n_0\ : STD_LOGIC;
signal \y_int[23]_i_56_n_0\ : STD_LOGIC;
signal \y_int[23]_i_57_n_0\ : STD_LOGIC;
signal \y_int[23]_i_5_n_0\ : STD_LOGIC;
signal \y_int[23]_i_62_n_0\ : STD_LOGIC;
signal \y_int[23]_i_63_n_0\ : STD_LOGIC;
signal \y_int[23]_i_64_n_0\ : STD_LOGIC;
signal \y_int[23]_i_65_n_0\ : STD_LOGIC;
signal \y_int[23]_i_67_n_0\ : STD_LOGIC;
signal \y_int[23]_i_68_n_0\ : STD_LOGIC;
signal \y_int[23]_i_69_n_0\ : STD_LOGIC;
signal \y_int[23]_i_6_n_0\ : STD_LOGIC;
signal \y_int[23]_i_70_n_0\ : STD_LOGIC;
signal \y_int[23]_i_71_n_0\ : STD_LOGIC;
signal \y_int[23]_i_72_n_0\ : STD_LOGIC;
signal \y_int[23]_i_73_n_0\ : STD_LOGIC;
signal \y_int[23]_i_74_n_0\ : STD_LOGIC;
signal \y_int[23]_i_76_n_0\ : STD_LOGIC;
signal \y_int[23]_i_77_n_0\ : STD_LOGIC;
signal \y_int[23]_i_78_n_0\ : STD_LOGIC;
signal \y_int[23]_i_79_n_0\ : STD_LOGIC;
signal \y_int[23]_i_7_n_0\ : STD_LOGIC;
signal \y_int[23]_i_80_n_0\ : STD_LOGIC;
signal \y_int[23]_i_81_n_0\ : STD_LOGIC;
signal \y_int[23]_i_82_n_0\ : STD_LOGIC;
signal \y_int[23]_i_83_n_0\ : STD_LOGIC;
signal \y_int[23]_i_84_n_0\ : STD_LOGIC;
signal \y_int[23]_i_85_n_0\ : STD_LOGIC;
signal \y_int[23]_i_86_n_0\ : STD_LOGIC;
signal \y_int[23]_i_87_n_0\ : STD_LOGIC;
signal \y_int[23]_i_88_n_0\ : STD_LOGIC;
signal \y_int[23]_i_8_n_0\ : STD_LOGIC;
signal \y_int[23]_i_90_n_0\ : STD_LOGIC;
signal \y_int[23]_i_91_n_0\ : STD_LOGIC;
signal \y_int[23]_i_92_n_0\ : STD_LOGIC;
signal \y_int[23]_i_93_n_0\ : STD_LOGIC;
signal \y_int[23]_i_94_n_0\ : STD_LOGIC;
signal \y_int[23]_i_95_n_0\ : STD_LOGIC;
signal \y_int[23]_i_96_n_0\ : STD_LOGIC;
signal \y_int[23]_i_97_n_0\ : STD_LOGIC;
signal \y_int[23]_i_98_n_0\ : STD_LOGIC;
signal \y_int[23]_i_99_n_0\ : STD_LOGIC;
signal \y_int[23]_i_9_n_0\ : STD_LOGIC;
signal \y_int[27]_i_2_n_0\ : STD_LOGIC;
signal \y_int[27]_i_3_n_0\ : STD_LOGIC;
signal \y_int[27]_i_4_n_0\ : STD_LOGIC;
signal \y_int[27]_i_5_n_0\ : STD_LOGIC;
signal \y_int[31]_i_101_n_0\ : STD_LOGIC;
signal \y_int[31]_i_104_n_0\ : STD_LOGIC;
signal \y_int[31]_i_105_n_0\ : STD_LOGIC;
signal \y_int[31]_i_106_n_0\ : STD_LOGIC;
signal \y_int[31]_i_107_n_0\ : STD_LOGIC;
signal \y_int[31]_i_108_n_0\ : STD_LOGIC;
signal \y_int[31]_i_109_n_0\ : STD_LOGIC;
signal \y_int[31]_i_110_n_0\ : STD_LOGIC;
signal \y_int[31]_i_111_n_0\ : STD_LOGIC;
signal \y_int[31]_i_112_n_0\ : STD_LOGIC;
signal \y_int[31]_i_113_n_0\ : STD_LOGIC;
signal \y_int[31]_i_114_n_0\ : STD_LOGIC;
signal \y_int[31]_i_115_n_0\ : STD_LOGIC;
signal \y_int[31]_i_116_n_0\ : STD_LOGIC;
signal \y_int[31]_i_13_n_0\ : STD_LOGIC;
signal \y_int[31]_i_14_n_0\ : STD_LOGIC;
signal \y_int[31]_i_15_n_0\ : STD_LOGIC;
signal \y_int[31]_i_17_n_0\ : STD_LOGIC;
signal \y_int[31]_i_18_n_0\ : STD_LOGIC;
signal \y_int[31]_i_19_n_0\ : STD_LOGIC;
signal \y_int[31]_i_20_n_0\ : STD_LOGIC;
signal \y_int[31]_i_2_n_0\ : STD_LOGIC;
signal \y_int[31]_i_32_n_0\ : STD_LOGIC;
signal \y_int[31]_i_33_n_0\ : STD_LOGIC;
signal \y_int[31]_i_34_n_0\ : STD_LOGIC;
signal \y_int[31]_i_35_n_0\ : STD_LOGIC;
signal \y_int[31]_i_36_n_0\ : STD_LOGIC;
signal \y_int[31]_i_3_n_0\ : STD_LOGIC;
signal \y_int[31]_i_40_n_0\ : STD_LOGIC;
signal \y_int[31]_i_41_n_0\ : STD_LOGIC;
signal \y_int[31]_i_42_n_0\ : STD_LOGIC;
signal \y_int[31]_i_43_n_0\ : STD_LOGIC;
signal \y_int[31]_i_44_n_0\ : STD_LOGIC;
signal \y_int[31]_i_45_n_0\ : STD_LOGIC;
signal \y_int[31]_i_46_n_0\ : STD_LOGIC;
signal \y_int[31]_i_47_n_0\ : STD_LOGIC;
signal \y_int[31]_i_4_n_0\ : STD_LOGIC;
signal \y_int[31]_i_5_n_0\ : STD_LOGIC;
signal \y_int[31]_i_63_n_0\ : STD_LOGIC;
signal \y_int[31]_i_64_n_0\ : STD_LOGIC;
signal \y_int[31]_i_65_n_0\ : STD_LOGIC;
signal \y_int[31]_i_66_n_0\ : STD_LOGIC;
signal \y_int[31]_i_67_n_0\ : STD_LOGIC;
signal \y_int[31]_i_68_n_0\ : STD_LOGIC;
signal \y_int[31]_i_69_n_0\ : STD_LOGIC;
signal \y_int[31]_i_6_n_0\ : STD_LOGIC;
signal \y_int[31]_i_70_n_0\ : STD_LOGIC;
signal \y_int[31]_i_89_n_0\ : STD_LOGIC;
signal \y_int[31]_i_90_n_0\ : STD_LOGIC;
signal \y_int[31]_i_91_n_0\ : STD_LOGIC;
signal \y_int[31]_i_92_n_0\ : STD_LOGIC;
signal \y_int[3]_i_10_n_0\ : STD_LOGIC;
signal \y_int[3]_i_13_n_0\ : STD_LOGIC;
signal \y_int[3]_i_17_n_0\ : STD_LOGIC;
signal \y_int[3]_i_18_n_0\ : STD_LOGIC;
signal \y_int[3]_i_22_n_0\ : STD_LOGIC;
signal \y_int[3]_i_23_n_0\ : STD_LOGIC;
signal \y_int[3]_i_24_n_0\ : STD_LOGIC;
signal \y_int[3]_i_25_n_0\ : STD_LOGIC;
signal \y_int[3]_i_27_n_0\ : STD_LOGIC;
signal \y_int[3]_i_28_n_0\ : STD_LOGIC;
signal \y_int[3]_i_29_n_0\ : STD_LOGIC;
signal \y_int[3]_i_2_n_0\ : STD_LOGIC;
signal \y_int[3]_i_31_n_0\ : STD_LOGIC;
signal \y_int[3]_i_32_n_0\ : STD_LOGIC;
signal \y_int[3]_i_33_n_0\ : STD_LOGIC;
signal \y_int[3]_i_34_n_0\ : STD_LOGIC;
signal \y_int[3]_i_3_n_0\ : STD_LOGIC;
signal \y_int[3]_i_4_n_0\ : STD_LOGIC;
signal \y_int[3]_i_50_n_0\ : STD_LOGIC;
signal \y_int[3]_i_51_n_0\ : STD_LOGIC;
signal \y_int[3]_i_52_n_0\ : STD_LOGIC;
signal \y_int[3]_i_53_n_0\ : STD_LOGIC;
signal \y_int[3]_i_54_n_0\ : STD_LOGIC;
signal \y_int[3]_i_56_n_0\ : STD_LOGIC;
signal \y_int[3]_i_57_n_0\ : STD_LOGIC;
signal \y_int[3]_i_58_n_0\ : STD_LOGIC;
signal \y_int[3]_i_59_n_0\ : STD_LOGIC;
signal \y_int[3]_i_5_n_0\ : STD_LOGIC;
signal \y_int[3]_i_60_n_0\ : STD_LOGIC;
signal \y_int[3]_i_61_n_0\ : STD_LOGIC;
signal \y_int[3]_i_62_n_0\ : STD_LOGIC;
signal \y_int[3]_i_63_n_0\ : STD_LOGIC;
signal \y_int[3]_i_66_n_0\ : STD_LOGIC;
signal \y_int[3]_i_67_n_0\ : STD_LOGIC;
signal \y_int[3]_i_68_n_0\ : STD_LOGIC;
signal \y_int[3]_i_69_n_0\ : STD_LOGIC;
signal \y_int[3]_i_6_n_0\ : STD_LOGIC;
signal \y_int[3]_i_71_n_0\ : STD_LOGIC;
signal \y_int[3]_i_72_n_0\ : STD_LOGIC;
signal \y_int[3]_i_73_n_0\ : STD_LOGIC;
signal \y_int[3]_i_74_n_0\ : STD_LOGIC;
signal \y_int[3]_i_7_n_0\ : STD_LOGIC;
signal \y_int[3]_i_84_n_0\ : STD_LOGIC;
signal \y_int[3]_i_85_n_0\ : STD_LOGIC;
signal \y_int[3]_i_86_n_0\ : STD_LOGIC;
signal \y_int[3]_i_87_n_0\ : STD_LOGIC;
signal \y_int[3]_i_88_n_0\ : STD_LOGIC;
signal \y_int[3]_i_89_n_0\ : STD_LOGIC;
signal \y_int[3]_i_8_n_0\ : STD_LOGIC;
signal \y_int[3]_i_90_n_0\ : STD_LOGIC;
signal \y_int[3]_i_91_n_0\ : STD_LOGIC;
signal \y_int[3]_i_92_n_0\ : STD_LOGIC;
signal \y_int[7]_i_11_n_0\ : STD_LOGIC;
signal \y_int[7]_i_13_n_0\ : STD_LOGIC;
signal \y_int[7]_i_16_n_0\ : STD_LOGIC;
signal \y_int[7]_i_19_n_0\ : STD_LOGIC;
signal \y_int[7]_i_29_n_0\ : STD_LOGIC;
signal \y_int[7]_i_2_n_0\ : STD_LOGIC;
signal \y_int[7]_i_30_n_0\ : STD_LOGIC;
signal \y_int[7]_i_31_n_0\ : STD_LOGIC;
signal \y_int[7]_i_32_n_0\ : STD_LOGIC;
signal \y_int[7]_i_33_n_0\ : STD_LOGIC;
signal \y_int[7]_i_3_n_0\ : STD_LOGIC;
signal \y_int[7]_i_4_n_0\ : STD_LOGIC;
signal \y_int[7]_i_5_n_0\ : STD_LOGIC;
signal \y_int[7]_i_6_n_0\ : STD_LOGIC;
signal \y_int[7]_i_7_n_0\ : STD_LOGIC;
signal \y_int[7]_i_8_n_0\ : STD_LOGIC;
signal \y_int[7]_i_9_n_0\ : STD_LOGIC;
signal y_int_reg1 : STD_LOGIC_VECTOR ( 22 downto 1 );
signal y_int_reg2 : STD_LOGIC_VECTOR ( 8 downto 1 );
signal y_int_reg20_in : STD_LOGIC_VECTOR ( 22 downto 1 );
signal y_int_reg3 : STD_LOGIC_VECTOR ( 22 downto 1 );
signal y_int_reg5 : STD_LOGIC_VECTOR ( 30 downto 8 );
signal y_int_reg6 : STD_LOGIC;
signal \y_int_reg[11]_i_14_n_0\ : STD_LOGIC;
signal \y_int_reg[11]_i_14_n_1\ : STD_LOGIC;
signal \y_int_reg[11]_i_14_n_2\ : STD_LOGIC;
signal \y_int_reg[11]_i_14_n_3\ : STD_LOGIC;
signal \y_int_reg[11]_i_15_n_0\ : STD_LOGIC;
signal \y_int_reg[11]_i_15_n_1\ : STD_LOGIC;
signal \y_int_reg[11]_i_15_n_2\ : STD_LOGIC;
signal \y_int_reg[11]_i_15_n_3\ : STD_LOGIC;
signal \y_int_reg[11]_i_1_n_0\ : STD_LOGIC;
signal \y_int_reg[11]_i_1_n_1\ : STD_LOGIC;
signal \y_int_reg[11]_i_1_n_2\ : STD_LOGIC;
signal \y_int_reg[11]_i_1_n_3\ : STD_LOGIC;
signal \y_int_reg[11]_i_1_n_4\ : STD_LOGIC;
signal \y_int_reg[11]_i_1_n_5\ : STD_LOGIC;
signal \y_int_reg[11]_i_1_n_6\ : STD_LOGIC;
signal \y_int_reg[11]_i_1_n_7\ : STD_LOGIC;
signal \y_int_reg[11]_i_20_n_1\ : STD_LOGIC;
signal \y_int_reg[11]_i_20_n_2\ : STD_LOGIC;
signal \y_int_reg[11]_i_20_n_3\ : STD_LOGIC;
signal \y_int_reg[11]_i_21_n_0\ : STD_LOGIC;
signal \y_int_reg[11]_i_21_n_1\ : STD_LOGIC;
signal \y_int_reg[11]_i_21_n_2\ : STD_LOGIC;
signal \y_int_reg[11]_i_21_n_3\ : STD_LOGIC;
signal \y_int_reg[11]_i_21_n_4\ : STD_LOGIC;
signal \y_int_reg[11]_i_21_n_5\ : STD_LOGIC;
signal \y_int_reg[11]_i_21_n_6\ : STD_LOGIC;
signal \y_int_reg[11]_i_21_n_7\ : STD_LOGIC;
signal \y_int_reg[11]_i_22_n_1\ : STD_LOGIC;
signal \y_int_reg[11]_i_22_n_2\ : STD_LOGIC;
signal \y_int_reg[11]_i_22_n_3\ : STD_LOGIC;
signal \y_int_reg[11]_i_28_n_0\ : STD_LOGIC;
signal \y_int_reg[11]_i_28_n_1\ : STD_LOGIC;
signal \y_int_reg[11]_i_28_n_2\ : STD_LOGIC;
signal \y_int_reg[11]_i_28_n_3\ : STD_LOGIC;
signal \y_int_reg[11]_i_33_n_0\ : STD_LOGIC;
signal \y_int_reg[11]_i_33_n_1\ : STD_LOGIC;
signal \y_int_reg[11]_i_33_n_2\ : STD_LOGIC;
signal \y_int_reg[11]_i_33_n_3\ : STD_LOGIC;
signal \y_int_reg[11]_i_38_n_0\ : STD_LOGIC;
signal \y_int_reg[11]_i_38_n_1\ : STD_LOGIC;
signal \y_int_reg[11]_i_38_n_2\ : STD_LOGIC;
signal \y_int_reg[11]_i_38_n_3\ : STD_LOGIC;
signal \y_int_reg[11]_i_38_n_4\ : STD_LOGIC;
signal \y_int_reg[11]_i_38_n_5\ : STD_LOGIC;
signal \y_int_reg[11]_i_38_n_6\ : STD_LOGIC;
signal \y_int_reg[11]_i_38_n_7\ : STD_LOGIC;
signal \y_int_reg[11]_i_39_n_0\ : STD_LOGIC;
signal \y_int_reg[11]_i_39_n_1\ : STD_LOGIC;
signal \y_int_reg[11]_i_39_n_2\ : STD_LOGIC;
signal \y_int_reg[11]_i_39_n_3\ : STD_LOGIC;
signal \y_int_reg[11]_i_44_n_0\ : STD_LOGIC;
signal \y_int_reg[11]_i_44_n_1\ : STD_LOGIC;
signal \y_int_reg[11]_i_44_n_2\ : STD_LOGIC;
signal \y_int_reg[11]_i_44_n_3\ : STD_LOGIC;
signal \y_int_reg[11]_i_44_n_4\ : STD_LOGIC;
signal \y_int_reg[11]_i_44_n_5\ : STD_LOGIC;
signal \y_int_reg[11]_i_44_n_6\ : STD_LOGIC;
signal \y_int_reg[11]_i_44_n_7\ : STD_LOGIC;
signal \y_int_reg[11]_i_49_n_0\ : STD_LOGIC;
signal \y_int_reg[11]_i_49_n_1\ : STD_LOGIC;
signal \y_int_reg[11]_i_49_n_2\ : STD_LOGIC;
signal \y_int_reg[11]_i_49_n_3\ : STD_LOGIC;
signal \y_int_reg[11]_i_80_n_0\ : STD_LOGIC;
signal \y_int_reg[11]_i_80_n_1\ : STD_LOGIC;
signal \y_int_reg[11]_i_80_n_2\ : STD_LOGIC;
signal \y_int_reg[11]_i_80_n_3\ : STD_LOGIC;
signal \y_int_reg[11]_i_85_n_0\ : STD_LOGIC;
signal \y_int_reg[11]_i_85_n_1\ : STD_LOGIC;
signal \y_int_reg[11]_i_85_n_2\ : STD_LOGIC;
signal \y_int_reg[11]_i_85_n_3\ : STD_LOGIC;
signal \^y_int_reg[15]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \y_int_reg[15]_i_14_n_0\ : STD_LOGIC;
signal \y_int_reg[15]_i_14_n_1\ : STD_LOGIC;
signal \y_int_reg[15]_i_14_n_2\ : STD_LOGIC;
signal \y_int_reg[15]_i_14_n_3\ : STD_LOGIC;
signal \y_int_reg[15]_i_15_n_0\ : STD_LOGIC;
signal \y_int_reg[15]_i_15_n_1\ : STD_LOGIC;
signal \y_int_reg[15]_i_15_n_2\ : STD_LOGIC;
signal \y_int_reg[15]_i_15_n_3\ : STD_LOGIC;
signal \y_int_reg[15]_i_1_n_0\ : STD_LOGIC;
signal \y_int_reg[15]_i_1_n_1\ : STD_LOGIC;
signal \y_int_reg[15]_i_1_n_2\ : STD_LOGIC;
signal \y_int_reg[15]_i_1_n_3\ : STD_LOGIC;
signal \y_int_reg[15]_i_1_n_4\ : STD_LOGIC;
signal \y_int_reg[15]_i_1_n_5\ : STD_LOGIC;
signal \y_int_reg[15]_i_1_n_6\ : STD_LOGIC;
signal \y_int_reg[15]_i_1_n_7\ : STD_LOGIC;
signal \y_int_reg[15]_i_33_n_1\ : STD_LOGIC;
signal \y_int_reg[15]_i_33_n_2\ : STD_LOGIC;
signal \y_int_reg[15]_i_33_n_3\ : STD_LOGIC;
signal \y_int_reg[15]_i_33_n_4\ : STD_LOGIC;
signal \y_int_reg[15]_i_33_n_5\ : STD_LOGIC;
signal \y_int_reg[15]_i_33_n_6\ : STD_LOGIC;
signal \y_int_reg[15]_i_33_n_7\ : STD_LOGIC;
signal \y_int_reg[15]_i_35_n_0\ : STD_LOGIC;
signal \y_int_reg[15]_i_35_n_1\ : STD_LOGIC;
signal \y_int_reg[15]_i_35_n_2\ : STD_LOGIC;
signal \y_int_reg[15]_i_35_n_3\ : STD_LOGIC;
signal \^y_int_reg[19]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \y_int_reg[19]_i_14_n_0\ : STD_LOGIC;
signal \y_int_reg[19]_i_14_n_1\ : STD_LOGIC;
signal \y_int_reg[19]_i_14_n_2\ : STD_LOGIC;
signal \y_int_reg[19]_i_14_n_3\ : STD_LOGIC;
signal \y_int_reg[19]_i_15_n_0\ : STD_LOGIC;
signal \y_int_reg[19]_i_15_n_1\ : STD_LOGIC;
signal \y_int_reg[19]_i_15_n_2\ : STD_LOGIC;
signal \y_int_reg[19]_i_15_n_3\ : STD_LOGIC;
signal \y_int_reg[19]_i_1_n_0\ : STD_LOGIC;
signal \y_int_reg[19]_i_1_n_1\ : STD_LOGIC;
signal \y_int_reg[19]_i_1_n_2\ : STD_LOGIC;
signal \y_int_reg[19]_i_1_n_3\ : STD_LOGIC;
signal \y_int_reg[19]_i_1_n_4\ : STD_LOGIC;
signal \y_int_reg[19]_i_1_n_5\ : STD_LOGIC;
signal \y_int_reg[19]_i_1_n_6\ : STD_LOGIC;
signal \y_int_reg[19]_i_1_n_7\ : STD_LOGIC;
signal \y_int_reg[19]_i_35_n_0\ : STD_LOGIC;
signal \y_int_reg[19]_i_35_n_1\ : STD_LOGIC;
signal \y_int_reg[19]_i_35_n_2\ : STD_LOGIC;
signal \y_int_reg[19]_i_35_n_3\ : STD_LOGIC;
signal \^y_int_reg[23]_0\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^y_int_reg[23]_1\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^y_int_reg[23]_2\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \y_int_reg[23]_i_10_n_1\ : STD_LOGIC;
signal \y_int_reg[23]_i_10_n_2\ : STD_LOGIC;
signal \y_int_reg[23]_i_10_n_3\ : STD_LOGIC;
signal \y_int_reg[23]_i_11_n_3\ : STD_LOGIC;
signal \y_int_reg[23]_i_16_n_0\ : STD_LOGIC;
signal \y_int_reg[23]_i_16_n_1\ : STD_LOGIC;
signal \y_int_reg[23]_i_16_n_2\ : STD_LOGIC;
signal \y_int_reg[23]_i_16_n_3\ : STD_LOGIC;
signal \y_int_reg[23]_i_17_n_0\ : STD_LOGIC;
signal \y_int_reg[23]_i_17_n_1\ : STD_LOGIC;
signal \y_int_reg[23]_i_17_n_2\ : STD_LOGIC;
signal \y_int_reg[23]_i_17_n_3\ : STD_LOGIC;
signal \y_int_reg[23]_i_1_n_0\ : STD_LOGIC;
signal \y_int_reg[23]_i_1_n_1\ : STD_LOGIC;
signal \y_int_reg[23]_i_1_n_2\ : STD_LOGIC;
signal \y_int_reg[23]_i_1_n_3\ : STD_LOGIC;
signal \y_int_reg[23]_i_1_n_4\ : STD_LOGIC;
signal \y_int_reg[23]_i_1_n_5\ : STD_LOGIC;
signal \y_int_reg[23]_i_1_n_6\ : STD_LOGIC;
signal \y_int_reg[23]_i_1_n_7\ : STD_LOGIC;
signal \y_int_reg[23]_i_25_n_0\ : STD_LOGIC;
signal \y_int_reg[23]_i_25_n_1\ : STD_LOGIC;
signal \y_int_reg[23]_i_25_n_2\ : STD_LOGIC;
signal \y_int_reg[23]_i_25_n_3\ : STD_LOGIC;
signal \y_int_reg[23]_i_33_n_1\ : STD_LOGIC;
signal \y_int_reg[23]_i_33_n_2\ : STD_LOGIC;
signal \y_int_reg[23]_i_33_n_3\ : STD_LOGIC;
signal \y_int_reg[23]_i_34_n_3\ : STD_LOGIC;
signal \y_int_reg[23]_i_44_n_0\ : STD_LOGIC;
signal \y_int_reg[23]_i_44_n_1\ : STD_LOGIC;
signal \y_int_reg[23]_i_44_n_2\ : STD_LOGIC;
signal \y_int_reg[23]_i_44_n_3\ : STD_LOGIC;
signal \y_int_reg[23]_i_45_n_0\ : STD_LOGIC;
signal \y_int_reg[23]_i_45_n_1\ : STD_LOGIC;
signal \y_int_reg[23]_i_45_n_2\ : STD_LOGIC;
signal \y_int_reg[23]_i_45_n_3\ : STD_LOGIC;
signal \y_int_reg[23]_i_51_n_0\ : STD_LOGIC;
signal \y_int_reg[23]_i_51_n_1\ : STD_LOGIC;
signal \y_int_reg[23]_i_51_n_2\ : STD_LOGIC;
signal \y_int_reg[23]_i_51_n_3\ : STD_LOGIC;
signal \y_int_reg[23]_i_66_n_0\ : STD_LOGIC;
signal \y_int_reg[23]_i_66_n_1\ : STD_LOGIC;
signal \y_int_reg[23]_i_66_n_2\ : STD_LOGIC;
signal \y_int_reg[23]_i_66_n_3\ : STD_LOGIC;
signal \y_int_reg[23]_i_75_n_0\ : STD_LOGIC;
signal \y_int_reg[23]_i_75_n_1\ : STD_LOGIC;
signal \y_int_reg[23]_i_75_n_2\ : STD_LOGIC;
signal \y_int_reg[23]_i_75_n_3\ : STD_LOGIC;
signal \y_int_reg[23]_i_89_n_0\ : STD_LOGIC;
signal \y_int_reg[23]_i_89_n_1\ : STD_LOGIC;
signal \y_int_reg[23]_i_89_n_2\ : STD_LOGIC;
signal \y_int_reg[23]_i_89_n_3\ : STD_LOGIC;
signal \y_int_reg[27]_i_1_n_0\ : STD_LOGIC;
signal \y_int_reg[27]_i_1_n_1\ : STD_LOGIC;
signal \y_int_reg[27]_i_1_n_2\ : STD_LOGIC;
signal \y_int_reg[27]_i_1_n_3\ : STD_LOGIC;
signal \y_int_reg[27]_i_1_n_4\ : STD_LOGIC;
signal \y_int_reg[27]_i_1_n_5\ : STD_LOGIC;
signal \y_int_reg[27]_i_1_n_6\ : STD_LOGIC;
signal \y_int_reg[27]_i_1_n_7\ : STD_LOGIC;
signal \y_int_reg[31]_i_11_n_1\ : STD_LOGIC;
signal \y_int_reg[31]_i_11_n_2\ : STD_LOGIC;
signal \y_int_reg[31]_i_11_n_3\ : STD_LOGIC;
signal \y_int_reg[31]_i_11_n_5\ : STD_LOGIC;
signal \y_int_reg[31]_i_11_n_6\ : STD_LOGIC;
signal \y_int_reg[31]_i_11_n_7\ : STD_LOGIC;
signal \y_int_reg[31]_i_16_n_0\ : STD_LOGIC;
signal \y_int_reg[31]_i_16_n_1\ : STD_LOGIC;
signal \y_int_reg[31]_i_16_n_2\ : STD_LOGIC;
signal \y_int_reg[31]_i_16_n_3\ : STD_LOGIC;
signal \y_int_reg[31]_i_16_n_4\ : STD_LOGIC;
signal \y_int_reg[31]_i_16_n_5\ : STD_LOGIC;
signal \y_int_reg[31]_i_16_n_6\ : STD_LOGIC;
signal \y_int_reg[31]_i_16_n_7\ : STD_LOGIC;
signal \y_int_reg[31]_i_1_n_1\ : STD_LOGIC;
signal \y_int_reg[31]_i_1_n_2\ : STD_LOGIC;
signal \y_int_reg[31]_i_1_n_3\ : STD_LOGIC;
signal \y_int_reg[31]_i_1_n_4\ : STD_LOGIC;
signal \y_int_reg[31]_i_1_n_5\ : STD_LOGIC;
signal \y_int_reg[31]_i_1_n_6\ : STD_LOGIC;
signal \y_int_reg[31]_i_1_n_7\ : STD_LOGIC;
signal \y_int_reg[31]_i_30_n_0\ : STD_LOGIC;
signal \y_int_reg[31]_i_30_n_1\ : STD_LOGIC;
signal \y_int_reg[31]_i_30_n_2\ : STD_LOGIC;
signal \y_int_reg[31]_i_30_n_3\ : STD_LOGIC;
signal \y_int_reg[31]_i_30_n_4\ : STD_LOGIC;
signal \y_int_reg[31]_i_30_n_5\ : STD_LOGIC;
signal \y_int_reg[31]_i_30_n_6\ : STD_LOGIC;
signal \y_int_reg[31]_i_30_n_7\ : STD_LOGIC;
signal \y_int_reg[31]_i_62_n_0\ : STD_LOGIC;
signal \y_int_reg[31]_i_62_n_1\ : STD_LOGIC;
signal \y_int_reg[31]_i_62_n_2\ : STD_LOGIC;
signal \y_int_reg[31]_i_62_n_3\ : STD_LOGIC;
signal \y_int_reg[31]_i_62_n_4\ : STD_LOGIC;
signal \y_int_reg[31]_i_62_n_5\ : STD_LOGIC;
signal \y_int_reg[31]_i_62_n_6\ : STD_LOGIC;
signal \y_int_reg[31]_i_75_n_2\ : STD_LOGIC;
signal \y_int_reg[31]_i_75_n_7\ : STD_LOGIC;
signal \y_int_reg[31]_i_7_n_1\ : STD_LOGIC;
signal \y_int_reg[31]_i_7_n_3\ : STD_LOGIC;
signal \y_int_reg[31]_i_86_n_1\ : STD_LOGIC;
signal \y_int_reg[31]_i_86_n_2\ : STD_LOGIC;
signal \y_int_reg[31]_i_86_n_3\ : STD_LOGIC;
signal \y_int_reg[31]_i_86_n_4\ : STD_LOGIC;
signal \y_int_reg[31]_i_86_n_5\ : STD_LOGIC;
signal \y_int_reg[31]_i_86_n_6\ : STD_LOGIC;
signal \y_int_reg[31]_i_87_n_0\ : STD_LOGIC;
signal \y_int_reg[31]_i_87_n_1\ : STD_LOGIC;
signal \y_int_reg[31]_i_87_n_2\ : STD_LOGIC;
signal \y_int_reg[31]_i_87_n_3\ : STD_LOGIC;
signal \y_int_reg[31]_i_87_n_4\ : STD_LOGIC;
signal \y_int_reg[31]_i_87_n_5\ : STD_LOGIC;
signal \y_int_reg[31]_i_87_n_6\ : STD_LOGIC;
signal \y_int_reg[31]_i_87_n_7\ : STD_LOGIC;
signal \y_int_reg[31]_i_88_n_0\ : STD_LOGIC;
signal \y_int_reg[31]_i_88_n_1\ : STD_LOGIC;
signal \y_int_reg[31]_i_88_n_2\ : STD_LOGIC;
signal \y_int_reg[31]_i_88_n_3\ : STD_LOGIC;
signal \y_int_reg[31]_i_88_n_4\ : STD_LOGIC;
signal \y_int_reg[31]_i_88_n_5\ : STD_LOGIC;
signal \y_int_reg[31]_i_88_n_6\ : STD_LOGIC;
signal \y_int_reg[31]_i_8_n_2\ : STD_LOGIC;
signal \y_int_reg[31]_i_8_n_3\ : STD_LOGIC;
signal \y_int_reg[31]_i_8_n_5\ : STD_LOGIC;
signal \y_int_reg[31]_i_8_n_6\ : STD_LOGIC;
signal \y_int_reg[31]_i_8_n_7\ : STD_LOGIC;
signal \^y_int_reg[3]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^y_int_reg[3]_1\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \y_int_reg[3]_i_15_n_0\ : STD_LOGIC;
signal \y_int_reg[3]_i_15_n_1\ : STD_LOGIC;
signal \y_int_reg[3]_i_15_n_2\ : STD_LOGIC;
signal \y_int_reg[3]_i_15_n_3\ : STD_LOGIC;
signal \y_int_reg[3]_i_16_n_0\ : STD_LOGIC;
signal \y_int_reg[3]_i_16_n_1\ : STD_LOGIC;
signal \y_int_reg[3]_i_16_n_2\ : STD_LOGIC;
signal \y_int_reg[3]_i_16_n_3\ : STD_LOGIC;
signal \y_int_reg[3]_i_16_n_4\ : STD_LOGIC;
signal \y_int_reg[3]_i_16_n_5\ : STD_LOGIC;
signal \y_int_reg[3]_i_16_n_6\ : STD_LOGIC;
signal \y_int_reg[3]_i_16_n_7\ : STD_LOGIC;
signal \y_int_reg[3]_i_1_n_0\ : STD_LOGIC;
signal \y_int_reg[3]_i_1_n_1\ : STD_LOGIC;
signal \y_int_reg[3]_i_1_n_2\ : STD_LOGIC;
signal \y_int_reg[3]_i_1_n_3\ : STD_LOGIC;
signal \y_int_reg[3]_i_1_n_4\ : STD_LOGIC;
signal \y_int_reg[3]_i_1_n_5\ : STD_LOGIC;
signal \y_int_reg[3]_i_1_n_6\ : STD_LOGIC;
signal \y_int_reg[3]_i_1_n_7\ : STD_LOGIC;
signal \y_int_reg[3]_i_21_n_0\ : STD_LOGIC;
signal \y_int_reg[3]_i_21_n_1\ : STD_LOGIC;
signal \y_int_reg[3]_i_21_n_2\ : STD_LOGIC;
signal \y_int_reg[3]_i_21_n_3\ : STD_LOGIC;
signal \y_int_reg[3]_i_26_n_0\ : STD_LOGIC;
signal \y_int_reg[3]_i_26_n_1\ : STD_LOGIC;
signal \y_int_reg[3]_i_26_n_2\ : STD_LOGIC;
signal \y_int_reg[3]_i_26_n_3\ : STD_LOGIC;
signal \y_int_reg[3]_i_26_n_4\ : STD_LOGIC;
signal \y_int_reg[3]_i_26_n_5\ : STD_LOGIC;
signal \y_int_reg[3]_i_26_n_6\ : STD_LOGIC;
signal \y_int_reg[3]_i_26_n_7\ : STD_LOGIC;
signal \y_int_reg[3]_i_30_n_0\ : STD_LOGIC;
signal \y_int_reg[3]_i_30_n_1\ : STD_LOGIC;
signal \y_int_reg[3]_i_30_n_2\ : STD_LOGIC;
signal \y_int_reg[3]_i_30_n_3\ : STD_LOGIC;
signal \y_int_reg[3]_i_30_n_4\ : STD_LOGIC;
signal \y_int_reg[3]_i_30_n_5\ : STD_LOGIC;
signal \y_int_reg[3]_i_30_n_6\ : STD_LOGIC;
signal \y_int_reg[3]_i_30_n_7\ : STD_LOGIC;
signal \y_int_reg[3]_i_35_n_0\ : STD_LOGIC;
signal \y_int_reg[3]_i_35_n_1\ : STD_LOGIC;
signal \y_int_reg[3]_i_35_n_2\ : STD_LOGIC;
signal \y_int_reg[3]_i_35_n_3\ : STD_LOGIC;
signal \y_int_reg[3]_i_35_n_4\ : STD_LOGIC;
signal \y_int_reg[3]_i_36_n_1\ : STD_LOGIC;
signal \y_int_reg[3]_i_36_n_2\ : STD_LOGIC;
signal \y_int_reg[3]_i_36_n_3\ : STD_LOGIC;
signal \y_int_reg[3]_i_55_n_0\ : STD_LOGIC;
signal \y_int_reg[3]_i_55_n_1\ : STD_LOGIC;
signal \y_int_reg[3]_i_55_n_2\ : STD_LOGIC;
signal \y_int_reg[3]_i_55_n_3\ : STD_LOGIC;
signal \y_int_reg[3]_i_55_n_4\ : STD_LOGIC;
signal \y_int_reg[3]_i_55_n_5\ : STD_LOGIC;
signal \y_int_reg[3]_i_55_n_6\ : STD_LOGIC;
signal \y_int_reg[3]_i_64_n_2\ : STD_LOGIC;
signal \y_int_reg[3]_i_64_n_7\ : STD_LOGIC;
signal \y_int_reg[3]_i_65_n_0\ : STD_LOGIC;
signal \y_int_reg[3]_i_65_n_1\ : STD_LOGIC;
signal \y_int_reg[3]_i_65_n_2\ : STD_LOGIC;
signal \y_int_reg[3]_i_65_n_3\ : STD_LOGIC;
signal \^y_int_reg[7]_0\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \y_int_reg[7]_i_1_n_0\ : STD_LOGIC;
signal \y_int_reg[7]_i_1_n_1\ : STD_LOGIC;
signal \y_int_reg[7]_i_1_n_2\ : STD_LOGIC;
signal \y_int_reg[7]_i_1_n_3\ : STD_LOGIC;
signal \y_int_reg[7]_i_1_n_4\ : STD_LOGIC;
signal \y_int_reg[7]_i_1_n_5\ : STD_LOGIC;
signal \y_int_reg[7]_i_1_n_6\ : STD_LOGIC;
signal \y_int_reg[7]_i_1_n_7\ : STD_LOGIC;
signal \y_int_reg[7]_i_24_n_0\ : STD_LOGIC;
signal \y_int_reg[7]_i_24_n_1\ : STD_LOGIC;
signal \y_int_reg[7]_i_24_n_2\ : STD_LOGIC;
signal \y_int_reg[7]_i_24_n_3\ : STD_LOGIC;
signal \y_int_reg[7]_i_24_n_4\ : STD_LOGIC;
signal \y_int_reg[7]_i_24_n_5\ : STD_LOGIC;
signal \y_int_reg[7]_i_24_n_6\ : STD_LOGIC;
signal \y_int_reg[7]_i_24_n_7\ : STD_LOGIC;
signal \y_int_reg__0\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \y_int_reg_n_0_[0]\ : STD_LOGIC;
signal \y_int_reg_n_0_[1]\ : STD_LOGIC;
signal \y_int_reg_n_0_[2]\ : STD_LOGIC;
signal \y_int_reg_n_0_[3]\ : STD_LOGIC;
signal \y_int_reg_n_0_[4]\ : STD_LOGIC;
signal \y_int_reg_n_0_[5]\ : STD_LOGIC;
signal \y_int_reg_n_0_[6]\ : STD_LOGIC;
signal \y_int_reg_n_0_[7]\ : STD_LOGIC;
signal \y_reg[7]_i_12_n_0\ : STD_LOGIC;
signal \y_reg[7]_i_12_n_1\ : STD_LOGIC;
signal \y_reg[7]_i_12_n_2\ : STD_LOGIC;
signal \y_reg[7]_i_12_n_3\ : STD_LOGIC;
signal \y_reg[7]_i_1_n_0\ : STD_LOGIC;
signal \y_reg[7]_i_1_n_1\ : STD_LOGIC;
signal \y_reg[7]_i_1_n_2\ : STD_LOGIC;
signal \y_reg[7]_i_1_n_3\ : STD_LOGIC;
signal \y_reg[7]_i_3_n_0\ : STD_LOGIC;
signal \y_reg[7]_i_3_n_1\ : STD_LOGIC;
signal \y_reg[7]_i_3_n_2\ : STD_LOGIC;
signal \y_reg[7]_i_3_n_3\ : STD_LOGIC;
signal NLW_ODDR_inst_R_UNCONNECTED : STD_LOGIC;
signal NLW_ODDR_inst_S_UNCONNECTED : STD_LOGIC;
signal \NLW_cb_int_reg[11]_i_18_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_cb_int_reg[11]_i_18_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cb_int_reg[11]_i_25_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cb_int_reg[11]_i_38_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cb_int_reg[11]_i_48_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cb_int_reg[11]_i_66_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cb_int_reg[11]_i_75_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cb_int_reg[11]_i_81_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cb_int_reg[11]_i_90_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cb_int_reg[27]_i_9_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_cb_int_reg[31]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_cb_int_reg[31]_i_11_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_cb_int_reg[31]_i_11_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_cb_int_reg[31]_i_12_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_cb_int_reg[31]_i_12_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_cb_int_reg[31]_i_34_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cb_int_reg[31]_i_34_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_cb_int_reg[31]_i_7_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_cb_int_reg[31]_i_7_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_cb_int_reg[3]_i_15_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \NLW_cb_int_reg[3]_i_21_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cb_int_reg[3]_i_26_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \NLW_cb_int_reg[3]_i_33_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_cb_int_reg[3]_i_63_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cb_int_reg[7]_i_25_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cb_int_reg[7]_i_38_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cb_int_reg[7]_i_61_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cb_int_reg[7]_i_66_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cb_reg[7]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cb_reg[7]_i_12_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cb_reg[7]_i_3_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cr_int_reg[11]_i_103_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cr_int_reg[11]_i_108_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cr_int_reg[11]_i_116_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cr_int_reg[11]_i_125_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cr_int_reg[11]_i_17_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cr_int_reg[11]_i_20_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cr_int_reg[11]_i_30_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cr_int_reg[11]_i_36_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cr_int_reg[11]_i_51_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cr_int_reg[11]_i_69_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cr_int_reg[11]_i_79_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cr_int_reg[11]_i_92_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cr_int_reg[27]_i_9_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_cr_int_reg[27]_i_9_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_cr_int_reg[31]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_cr_int_reg[31]_i_101_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_cr_int_reg[31]_i_101_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_cr_int_reg[31]_i_11_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_cr_int_reg[31]_i_12_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_cr_int_reg[31]_i_12_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_cr_int_reg[31]_i_48_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cr_int_reg[31]_i_48_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_cr_int_reg[31]_i_63_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cr_int_reg[31]_i_63_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_cr_int_reg[31]_i_69_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cr_int_reg[31]_i_69_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_cr_int_reg[31]_i_7_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_cr_int_reg[31]_i_8_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_cr_int_reg[31]_i_8_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_cr_int_reg[31]_i_9_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_cr_int_reg[31]_i_9_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_cr_int_reg[3]_i_15_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_cr_int_reg[3]_i_20_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \NLW_cr_int_reg[3]_i_21_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cr_int_reg[3]_i_26_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_cr_int_reg[3]_i_26_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_cr_int_reg[3]_i_32_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_cr_int_reg[3]_i_33_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \NLW_cr_int_reg[3]_i_42_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cr_int_reg[3]_i_59_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cr_int_reg[3]_i_65_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \NLW_cr_reg[7]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cr_reg[7]_i_12_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cr_reg[7]_i_3_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_y_int_reg[11]_i_22_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_y_int_reg[11]_i_49_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_y_int_reg[11]_i_80_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_y_int_reg[11]_i_85_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_y_int_reg[23]_i_10_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_y_int_reg[23]_i_11_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_y_int_reg[23]_i_11_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_y_int_reg[23]_i_25_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_y_int_reg[23]_i_33_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_y_int_reg[23]_i_34_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_y_int_reg[23]_i_34_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_y_int_reg[23]_i_45_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_y_int_reg[23]_i_51_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_y_int_reg[23]_i_66_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_y_int_reg[23]_i_75_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_y_int_reg[23]_i_89_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_y_int_reg[31]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_y_int_reg[31]_i_11_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_y_int_reg[31]_i_62_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \NLW_y_int_reg[31]_i_7_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_y_int_reg[31]_i_7_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_y_int_reg[31]_i_75_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_y_int_reg[31]_i_75_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_y_int_reg[31]_i_8_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_y_int_reg[31]_i_8_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_y_int_reg[31]_i_86_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \NLW_y_int_reg[31]_i_88_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \NLW_y_int_reg[3]_i_15_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_y_int_reg[3]_i_21_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_y_int_reg[3]_i_35_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_y_int_reg[3]_i_55_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \NLW_y_int_reg[3]_i_64_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_y_int_reg[3]_i_64_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_y_int_reg[3]_i_65_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_y_reg[7]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_y_reg[7]_i_12_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_y_reg[7]_i_3_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute \__SRVAL\ : string;
attribute \__SRVAL\ of ODDR_inst : label is "TRUE";
attribute box_type : string;
attribute box_type of ODDR_inst : label is "PRIMITIVE";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \cb[0]_i_1\ : label is "soft_lutpair34";
attribute SOFT_HLUTNM of \cb[1]_i_1\ : label is "soft_lutpair35";
attribute SOFT_HLUTNM of \cb[2]_i_1\ : label is "soft_lutpair36";
attribute SOFT_HLUTNM of \cb[3]_i_1\ : label is "soft_lutpair37";
attribute SOFT_HLUTNM of \cb[4]_i_1\ : label is "soft_lutpair37";
attribute SOFT_HLUTNM of \cb[5]_i_1\ : label is "soft_lutpair36";
attribute SOFT_HLUTNM of \cb[6]_i_1\ : label is "soft_lutpair35";
attribute SOFT_HLUTNM of \cb[7]_i_2\ : label is "soft_lutpair34";
attribute HLUTNM : string;
attribute HLUTNM of \cb_int[11]_i_2\ : label is "lutpair8";
attribute HLUTNM of \cb_int[11]_i_3\ : label is "lutpair7";
attribute HLUTNM of \cb_int[11]_i_4\ : label is "lutpair6";
attribute HLUTNM of \cb_int[11]_i_6\ : label is "lutpair9";
attribute HLUTNM of \cb_int[11]_i_7\ : label is "lutpair8";
attribute HLUTNM of \cb_int[11]_i_8\ : label is "lutpair7";
attribute HLUTNM of \cb_int[11]_i_9\ : label is "lutpair6";
attribute HLUTNM of \cb_int[15]_i_2\ : label is "lutpair12";
attribute HLUTNM of \cb_int[15]_i_3\ : label is "lutpair11";
attribute HLUTNM of \cb_int[15]_i_4\ : label is "lutpair10";
attribute HLUTNM of \cb_int[15]_i_5\ : label is "lutpair9";
attribute HLUTNM of \cb_int[15]_i_6\ : label is "lutpair13";
attribute HLUTNM of \cb_int[15]_i_7\ : label is "lutpair12";
attribute HLUTNM of \cb_int[15]_i_8\ : label is "lutpair11";
attribute HLUTNM of \cb_int[15]_i_9\ : label is "lutpair10";
attribute HLUTNM of \cb_int[19]_i_2\ : label is "lutpair16";
attribute HLUTNM of \cb_int[19]_i_3\ : label is "lutpair15";
attribute HLUTNM of \cb_int[19]_i_4\ : label is "lutpair14";
attribute HLUTNM of \cb_int[19]_i_5\ : label is "lutpair13";
attribute HLUTNM of \cb_int[19]_i_6\ : label is "lutpair17";
attribute HLUTNM of \cb_int[19]_i_7\ : label is "lutpair16";
attribute HLUTNM of \cb_int[19]_i_8\ : label is "lutpair15";
attribute HLUTNM of \cb_int[19]_i_9\ : label is "lutpair14";
attribute HLUTNM of \cb_int[23]_i_2\ : label is "lutpair20";
attribute SOFT_HLUTNM of \cb_int[23]_i_20\ : label is "soft_lutpair19";
attribute HLUTNM of \cb_int[23]_i_3\ : label is "lutpair19";
attribute HLUTNM of \cb_int[23]_i_4\ : label is "lutpair18";
attribute HLUTNM of \cb_int[23]_i_5\ : label is "lutpair17";
attribute HLUTNM of \cb_int[23]_i_6\ : label is "lutpair21";
attribute HLUTNM of \cb_int[23]_i_7\ : label is "lutpair20";
attribute HLUTNM of \cb_int[23]_i_8\ : label is "lutpair19";
attribute HLUTNM of \cb_int[23]_i_9\ : label is "lutpair18";
attribute HLUTNM of \cb_int[27]_i_2\ : label is "lutpair21";
attribute SOFT_HLUTNM of \cb_int[31]_i_13\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \cb_int[31]_i_86\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \cb_int[31]_i_87\ : label is "soft_lutpair18";
attribute HLUTNM of \cb_int[3]_i_2\ : label is "lutpair2";
attribute HLUTNM of \cb_int[3]_i_3\ : label is "lutpair1";
attribute HLUTNM of \cb_int[3]_i_4\ : label is "lutpair39";
attribute HLUTNM of \cb_int[3]_i_5\ : label is "lutpair3";
attribute HLUTNM of \cb_int[3]_i_6\ : label is "lutpair2";
attribute HLUTNM of \cb_int[3]_i_7\ : label is "lutpair1";
attribute HLUTNM of \cb_int[3]_i_8\ : label is "lutpair39";
attribute HLUTNM of \cb_int[7]_i_3\ : label is "lutpair5";
attribute HLUTNM of \cb_int[7]_i_4\ : label is "lutpair4";
attribute HLUTNM of \cb_int[7]_i_5\ : label is "lutpair3";
attribute HLUTNM of \cb_int[7]_i_8\ : label is "lutpair5";
attribute HLUTNM of \cb_int[7]_i_9\ : label is "lutpair4";
attribute SOFT_HLUTNM of \cr[0]_i_1\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \cr[1]_i_1\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \cr[2]_i_1\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \cr[3]_i_1\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \cr[4]_i_1\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \cr[5]_i_1\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \cr[6]_i_1\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \cr[7]_i_2\ : label is "soft_lutpair26";
attribute HLUTNM of \cr_int[11]_i_2\ : label is "lutpair29";
attribute SOFT_HLUTNM of \cr_int[11]_i_22\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \cr_int[11]_i_23\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \cr_int[11]_i_27\ : label is "soft_lutpair20";
attribute HLUTNM of \cr_int[11]_i_7\ : label is "lutpair29";
attribute HLUTNM of \cr_int[15]_i_2\ : label is "lutpair30";
attribute HLUTNM of \cr_int[15]_i_7\ : label is "lutpair30";
attribute HLUTNM of \cr_int[19]_i_2\ : label is "lutpair31";
attribute HLUTNM of \cr_int[19]_i_7\ : label is "lutpair31";
attribute HLUTNM of \cr_int[23]_i_2\ : label is "lutpair32";
attribute HLUTNM of \cr_int[23]_i_7\ : label is "lutpair32";
attribute SOFT_HLUTNM of \cr_int[31]_i_13\ : label is "soft_lutpair20";
attribute HLUTNM of \cr_int[31]_i_16\ : label is "lutpair23";
attribute HLUTNM of \cr_int[31]_i_44\ : label is "lutpair23";
attribute HLUTNM of \cr_int[3]_i_2\ : label is "lutpair25";
attribute HLUTNM of \cr_int[3]_i_3\ : label is "lutpair24";
attribute HLUTNM of \cr_int[3]_i_34\ : label is "lutpair22";
attribute HLUTNM of \cr_int[3]_i_39\ : label is "lutpair22";
attribute HLUTNM of \cr_int[3]_i_4\ : label is "lutpair40";
attribute HLUTNM of \cr_int[3]_i_5\ : label is "lutpair26";
attribute HLUTNM of \cr_int[3]_i_6\ : label is "lutpair25";
attribute HLUTNM of \cr_int[3]_i_7\ : label is "lutpair24";
attribute HLUTNM of \cr_int[3]_i_8\ : label is "lutpair40";
attribute HLUTNM of \cr_int[7]_i_3\ : label is "lutpair28";
attribute HLUTNM of \cr_int[7]_i_4\ : label is "lutpair27";
attribute HLUTNM of \cr_int[7]_i_5\ : label is "lutpair26";
attribute HLUTNM of \cr_int[7]_i_8\ : label is "lutpair28";
attribute HLUTNM of \cr_int[7]_i_9\ : label is "lutpair27";
attribute SOFT_HLUTNM of \y[0]_i_1\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \y[1]_i_1\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \y[2]_i_1\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \y[3]_i_1\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \y[4]_i_1\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \y[5]_i_1\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \y[6]_i_1\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of \y[7]_i_2\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of \y_hold[0]_i_1\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \y_hold[1]_i_1\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \y_hold[2]_i_1\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \y_hold[3]_i_1\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \y_hold[4]_i_1\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \y_hold[5]_i_1\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \y_hold[6]_i_1\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \y_hold[7]_i_1\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \y_int[23]_i_12\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \y_int[31]_i_13\ : label is "soft_lutpair21";
attribute HLUTNM of \y_int[3]_i_2\ : label is "lutpair35";
attribute HLUTNM of \y_int[3]_i_3\ : label is "lutpair34";
attribute HLUTNM of \y_int[3]_i_4\ : label is "lutpair33";
attribute HLUTNM of \y_int[3]_i_5\ : label is "lutpair36";
attribute HLUTNM of \y_int[3]_i_6\ : label is "lutpair35";
attribute HLUTNM of \y_int[3]_i_7\ : label is "lutpair34";
attribute HLUTNM of \y_int[3]_i_8\ : label is "lutpair33";
attribute HLUTNM of \y_int[7]_i_3\ : label is "lutpair38";
attribute HLUTNM of \y_int[7]_i_4\ : label is "lutpair37";
attribute HLUTNM of \y_int[7]_i_5\ : label is "lutpair36";
attribute HLUTNM of \y_int[7]_i_8\ : label is "lutpair38";
attribute HLUTNM of \y_int[7]_i_9\ : label is "lutpair37";
begin
CO(0) <= \^co\(0);
DI(0) <= \^di\(0);
O(1 downto 0) <= \^o\(1 downto 0);
\cb_int_reg[3]_0\(3 downto 0) <= \^cb_int_reg[3]_0\(3 downto 0);
\cr_int_reg[11]_0\(3 downto 0) <= \^cr_int_reg[11]_0\(3 downto 0);
\cr_int_reg[15]_0\(3 downto 0) <= \^cr_int_reg[15]_0\(3 downto 0);
\cr_int_reg[19]_0\(3 downto 0) <= \^cr_int_reg[19]_0\(3 downto 0);
\cr_int_reg[23]_0\(3 downto 0) <= \^cr_int_reg[23]_0\(3 downto 0);
\cr_int_reg[23]_1\(0) <= \^cr_int_reg[23]_1\(0);
\cr_int_reg[27]_0\ <= \^cr_int_reg[27]_0\;
\cr_int_reg[27]_1\(1 downto 0) <= \^cr_int_reg[27]_1\(1 downto 0);
\cr_int_reg[27]_2\(0) <= \^cr_int_reg[27]_2\(0);
\cr_int_reg[31]_0\ <= \^cr_int_reg[31]_0\;
\cr_int_reg[31]_1\ <= \^cr_int_reg[31]_1\;
\cr_int_reg[31]_2\(1 downto 0) <= \^cr_int_reg[31]_2\(1 downto 0);
\cr_int_reg[3]_0\(2 downto 0) <= \^cr_int_reg[3]_0\(2 downto 0);
\cr_int_reg[3]_1\(0) <= \^cr_int_reg[3]_1\(0);
\cr_int_reg[3]_2\(1 downto 0) <= \^cr_int_reg[3]_2\(1 downto 0);
\cr_int_reg[7]_0\(3 downto 0) <= \^cr_int_reg[7]_0\(3 downto 0);
\cr_int_reg[7]_1\(3 downto 0) <= \^cr_int_reg[7]_1\(3 downto 0);
\y_int_reg[15]_0\(3 downto 0) <= \^y_int_reg[15]_0\(3 downto 0);
\y_int_reg[19]_0\(3 downto 0) <= \^y_int_reg[19]_0\(3 downto 0);
\y_int_reg[23]_0\(0) <= \^y_int_reg[23]_0\(0);
\y_int_reg[23]_1\(1 downto 0) <= \^y_int_reg[23]_1\(1 downto 0);
\y_int_reg[23]_2\(3 downto 0) <= \^y_int_reg[23]_2\(3 downto 0);
\y_int_reg[3]_0\(3 downto 0) <= \^y_int_reg[3]_0\(3 downto 0);
\y_int_reg[3]_1\(0) <= \^y_int_reg[3]_1\(0);
\y_int_reg[7]_0\(0) <= \^y_int_reg[7]_0\(0);
Inst_i2c_sender: entity work.system_zed_hdmi_0_0_i2c_sender
port map (
clk_100 => clk_100,
hdmi_scl => hdmi_scl,
hdmi_sda => hdmi_sda
);
ODDR_inst: unisim.vcomponents.ODDR
generic map(
DDR_CLK_EDGE => "OPPOSITE_EDGE",
INIT => '0',
IS_C_INVERTED => '0',
IS_D1_INVERTED => '0',
IS_D2_INVERTED => '0',
SRTYPE => "SYNC"
)
port map (
C => clk_x2,
CE => '1',
D1 => D1,
D2 => D1,
Q => hdmi_clk,
R => NLW_ODDR_inst_R_UNCONNECTED,
S => NLW_ODDR_inst_S_UNCONNECTED
);
\cb[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg_n_0_[0]\,
I1 => \cb_int_reg__0\(31),
O => \cb[0]_i_1_n_0\
);
\cb[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg_n_0_[1]\,
I1 => \cb_int_reg__0\(31),
O => \cb[1]_i_1_n_0\
);
\cb[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg_n_0_[2]\,
I1 => \cb_int_reg__0\(31),
O => \cb[2]_i_1_n_0\
);
\cb[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg_n_0_[3]\,
I1 => \cb_int_reg__0\(31),
O => \cb[3]_i_1_n_0\
);
\cb[4]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg_n_0_[4]\,
I1 => \cb_int_reg__0\(31),
O => \cb[4]_i_1_n_0\
);
\cb[5]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg_n_0_[5]\,
I1 => \cb_int_reg__0\(31),
O => \cb[5]_i_1_n_0\
);
\cb[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg_n_0_[6]\,
I1 => \cb_int_reg__0\(31),
O => \cb[6]_i_1_n_0\
);
\cb[7]_i_10\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg__0\(26),
I1 => \cb_int_reg__0\(27),
O => \cb[7]_i_10_n_0\
);
\cb[7]_i_11\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg__0\(24),
I1 => \cb_int_reg__0\(25),
O => \cb[7]_i_11_n_0\
);
\cb[7]_i_13\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cb_int_reg__0\(22),
I1 => \cb_int_reg__0\(23),
O => \cb[7]_i_13_n_0\
);
\cb[7]_i_14\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cb_int_reg__0\(20),
I1 => \cb_int_reg__0\(21),
O => \cb[7]_i_14_n_0\
);
\cb[7]_i_15\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cb_int_reg__0\(18),
I1 => \cb_int_reg__0\(19),
O => \cb[7]_i_15_n_0\
);
\cb[7]_i_16\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cb_int_reg__0\(16),
I1 => \cb_int_reg__0\(17),
O => \cb[7]_i_16_n_0\
);
\cb[7]_i_17\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg__0\(22),
I1 => \cb_int_reg__0\(23),
O => \cb[7]_i_17_n_0\
);
\cb[7]_i_18\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg__0\(20),
I1 => \cb_int_reg__0\(21),
O => \cb[7]_i_18_n_0\
);
\cb[7]_i_19\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg__0\(18),
I1 => \cb_int_reg__0\(19),
O => \cb[7]_i_19_n_0\
);
\cb[7]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg_n_0_[7]\,
I1 => \cb_int_reg__0\(31),
O => \cb[7]_i_2_n_0\
);
\cb[7]_i_20\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg__0\(16),
I1 => \cb_int_reg__0\(17),
O => \cb[7]_i_20_n_0\
);
\cb[7]_i_21\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cb_int_reg__0\(14),
I1 => \cb_int_reg__0\(15),
O => \cb[7]_i_21_n_0\
);
\cb[7]_i_22\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cb_int_reg__0\(12),
I1 => \cb_int_reg__0\(13),
O => \cb[7]_i_22_n_0\
);
\cb[7]_i_23\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cb_int_reg__0\(10),
I1 => \cb_int_reg__0\(11),
O => \cb[7]_i_23_n_0\
);
\cb[7]_i_24\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cb_int_reg__0\(8),
I1 => \cb_int_reg__0\(9),
O => \cb[7]_i_24_n_0\
);
\cb[7]_i_25\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg__0\(14),
I1 => \cb_int_reg__0\(15),
O => \cb[7]_i_25_n_0\
);
\cb[7]_i_26\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg__0\(12),
I1 => \cb_int_reg__0\(13),
O => \cb[7]_i_26_n_0\
);
\cb[7]_i_27\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg__0\(10),
I1 => \cb_int_reg__0\(11),
O => \cb[7]_i_27_n_0\
);
\cb[7]_i_28\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg__0\(8),
I1 => \cb_int_reg__0\(9),
O => \cb[7]_i_28_n_0\
);
\cb[7]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg__0\(30),
I1 => \cb_int_reg__0\(31),
O => \cb[7]_i_4_n_0\
);
\cb[7]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cb_int_reg__0\(28),
I1 => \cb_int_reg__0\(29),
O => \cb[7]_i_5_n_0\
);
\cb[7]_i_6\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cb_int_reg__0\(26),
I1 => \cb_int_reg__0\(27),
O => \cb[7]_i_6_n_0\
);
\cb[7]_i_7\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cb_int_reg__0\(24),
I1 => \cb_int_reg__0\(25),
O => \cb[7]_i_7_n_0\
);
\cb[7]_i_8\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg__0\(30),
I1 => \cb_int_reg__0\(31),
O => \cb[7]_i_8_n_0\
);
\cb[7]_i_9\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg__0\(28),
I1 => \cb_int_reg__0\(29),
O => \cb[7]_i_9_n_0\
);
\cb_hold[7]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => edge,
I1 => edge_rb,
O => \cb_hold[7]_i_1_n_0\
);
\cb_hold_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \cb_hold[7]_i_1_n_0\,
D => cb(0),
Q => cb_hold(0),
R => '0'
);
\cb_hold_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \cb_hold[7]_i_1_n_0\,
D => cb(1),
Q => cb_hold(1),
R => '0'
);
\cb_hold_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \cb_hold[7]_i_1_n_0\,
D => cb(2),
Q => cb_hold(2),
R => '0'
);
\cb_hold_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \cb_hold[7]_i_1_n_0\,
D => cb(3),
Q => cb_hold(3),
R => '0'
);
\cb_hold_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \cb_hold[7]_i_1_n_0\,
D => cb(4),
Q => cb_hold(4),
R => '0'
);
\cb_hold_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \cb_hold[7]_i_1_n_0\,
D => cb(5),
Q => cb_hold(5),
R => '0'
);
\cb_hold_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \cb_hold[7]_i_1_n_0\,
D => cb(6),
Q => cb_hold(6),
R => '0'
);
\cb_hold_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \cb_hold[7]_i_1_n_0\,
D => cb(7),
Q => cb_hold(7),
R => '0'
);
\cb_int[11]_i_10\: unisim.vcomponents.LUT6
generic map(
INIT => X"DD1D22E222E2DD1D"
)
port map (
I0 => cb_int_reg5(10),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(18),
I3 => cb_int_reg8,
I4 => \cb_int[15]_i_25_n_0\,
I5 => cb_int_reg2(10),
O => \cb_int[11]_i_10_n_0\
);
\cb_int[11]_i_100\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cb_int_reg[3]_i_16_n_6\,
I1 => \cb_int_reg[3]_i_16_n_5\,
O => \cb_int[11]_i_100_n_0\
);
\cb_int[11]_i_101\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cb_int_reg[3]_i_26_n_4\,
I1 => \cb_int_reg[3]_i_16_n_7\,
O => \cb_int[11]_i_101_n_0\
);
\cb_int[11]_i_102\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cb_int_reg[3]_i_26_n_6\,
I1 => \cb_int_reg[3]_i_26_n_5\,
O => \cb_int[11]_i_102_n_0\
);
\cb_int[11]_i_103\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_33_n_7\,
I1 => \cb_int_reg[3]_i_16_n_4\,
O => \cb_int[11]_i_103_n_0\
);
\cb_int[11]_i_104\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_16_n_5\,
I1 => \cb_int_reg[3]_i_16_n_6\,
O => \cb_int[11]_i_104_n_0\
);
\cb_int[11]_i_105\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_16_n_7\,
I1 => \cb_int_reg[3]_i_26_n_4\,
O => \cb_int[11]_i_105_n_0\
);
\cb_int[11]_i_106\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_26_n_5\,
I1 => \cb_int_reg[3]_i_26_n_6\,
O => \cb_int[11]_i_106_n_0\
);
\cb_int[11]_i_107\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cb_int_reg[3]_i_20_n_7\,
I1 => \cb_int_reg[3]_i_20_n_6\,
O => \cb_int[11]_i_107_n_0\
);
\cb_int[11]_i_108\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cb_int_reg[3]_i_44_n_7\,
I1 => \cb_int_reg[3]_i_44_n_6\,
O => \cb_int[11]_i_108_n_0\
);
\cb_int[11]_i_109\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cb_int_reg[3]_i_75_n_5\,
I1 => \cb_int_reg[3]_i_75_n_4\,
O => \cb_int[11]_i_109_n_0\
);
\cb_int[11]_i_11\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFDD1DDD1D0000"
)
port map (
I0 => cb_int_reg5(9),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(17),
I3 => cb_int_reg8,
I4 => \cb_int[11]_i_20_n_0\,
I5 => cb_int_reg2(9),
O => \cb_int[11]_i_11_n_0\
);
\cb_int[11]_i_110\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cb_int_reg[3]_i_75_n_7\,
I1 => \cb_int_reg[3]_i_75_n_6\,
O => \cb_int[11]_i_110_n_0\
);
\cb_int[11]_i_111\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_20_n_6\,
I1 => \cb_int_reg[3]_i_20_n_7\,
O => \cb_int[11]_i_111_n_0\
);
\cb_int[11]_i_112\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_44_n_6\,
I1 => \cb_int_reg[3]_i_44_n_7\,
O => \cb_int[11]_i_112_n_0\
);
\cb_int[11]_i_113\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_75_n_4\,
I1 => \cb_int_reg[3]_i_75_n_5\,
O => \cb_int[11]_i_113_n_0\
);
\cb_int[11]_i_114\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_75_n_6\,
I1 => \cb_int_reg[3]_i_75_n_7\,
O => \cb_int[11]_i_114_n_0\
);
\cb_int[11]_i_12\: unisim.vcomponents.LUT6
generic map(
INIT => X"DD1D22E222E2DD1D"
)
port map (
I0 => cb_int_reg5(9),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(17),
I3 => cb_int_reg8,
I4 => \cb_int[11]_i_20_n_0\,
I5 => cb_int_reg2(9),
O => \cb_int[11]_i_12_n_0\
);
\cb_int[11]_i_13\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFDD1DDD1D0000"
)
port map (
I0 => cb_int_reg5(8),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(16),
I3 => cb_int_reg8,
I4 => \cb_int[11]_i_22_n_0\,
I5 => cb_int_reg2(8),
O => \cb_int[11]_i_13_n_0\
);
\cb_int[11]_i_14\: unisim.vcomponents.LUT6
generic map(
INIT => X"DD1D22E222E2DD1D"
)
port map (
I0 => cb_int_reg5(8),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(16),
I3 => cb_int_reg8,
I4 => \cb_int[11]_i_22_n_0\,
I5 => cb_int_reg2(8),
O => \cb_int[11]_i_14_n_0\
);
\cb_int[11]_i_15\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFE200E2"
)
port map (
I0 => \cb_int_reg[11]_i_24_n_5\,
I1 => \cb_int_reg[11]_i_25_n_0\,
I2 => \rgb888[0]\(1),
I3 => \rgb888[0]\(3),
I4 => cb_int_reg3(7),
I5 => \cb_int[11]_i_27_n_0\,
O => \cb_int[11]_i_15_n_0\
);
\cb_int[11]_i_19\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFE200E2001DFF1D"
)
port map (
I0 => \cb_int_reg[11]_i_24_n_5\,
I1 => \cb_int_reg[11]_i_25_n_0\,
I2 => \rgb888[0]\(1),
I3 => \rgb888[0]\(3),
I4 => cb_int_reg3(7),
I5 => \cb_int[11]_i_27_n_0\,
O => \cb_int[11]_i_19_n_0\
);
\cb_int[11]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cb_int[11]_i_10_n_0\,
I1 => \cb_int[11]_i_11_n_0\,
O => \cb_int[11]_i_2_n_0\
);
\cb_int[11]_i_20\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_4\(0),
I1 => \rgb888[8]_1\(1),
I2 => \^co\(0),
I3 => \rgb888[12]_0\(0),
O => \cb_int[11]_i_20_n_0\
);
\cb_int[11]_i_21\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => cb_int_reg3(9),
I1 => \rgb888[0]\(3),
I2 => \rgb888[0]_4\(0),
I3 => \cb_int_reg[11]_i_25_n_0\,
O => cb_int_reg2(9)
);
\cb_int[11]_i_22\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_3\(3),
I1 => \rgb888[8]_1\(1),
I2 => \^co\(0),
I3 => \rgb888[12]\(3),
O => \cb_int[11]_i_22_n_0\
);
\cb_int[11]_i_23\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => cb_int_reg3(8),
I1 => \rgb888[0]\(3),
I2 => \rgb888[0]\(2),
I3 => \cb_int_reg[11]_i_25_n_0\,
I4 => \cb_int_reg[11]_i_24_n_4\,
O => cb_int_reg2(8)
);
\cb_int[11]_i_27\: unisim.vcomponents.LUT5
generic map(
INIT => X"44477747"
)
port map (
I0 => \rgb888[8]_3\(2),
I1 => \rgb888[8]_1\(1),
I2 => \rgb888[12]\(2),
I3 => \^co\(0),
I4 => \rgb888[8]_1\(0),
O => \cb_int[11]_i_27_n_0\
);
\cb_int[11]_i_29\: unisim.vcomponents.LUT3
generic map(
INIT => X"8B"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
I1 => cb_int_reg8,
I2 => cb_int_reg7(16),
O => \cb_int[11]_i_29_n_0\
);
\cb_int[11]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cb_int[11]_i_12_n_0\,
I1 => \cb_int[11]_i_13_n_0\,
O => \cb_int[11]_i_3_n_0\
);
\cb_int[11]_i_30\: unisim.vcomponents.LUT3
generic map(
INIT => X"8B"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
I1 => cb_int_reg8,
I2 => cb_int_reg7(15),
O => \cb_int[11]_i_30_n_0\
);
\cb_int[11]_i_31\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => cb_int_reg7(14),
I1 => cb_int_reg8,
I2 => \cb_int_reg[31]_i_12_n_6\,
O => \cb_int[11]_i_31_n_0\
);
\cb_int[11]_i_32\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => cb_int_reg7(13),
I1 => cb_int_reg8,
I2 => \cb_int_reg[31]_i_12_n_7\,
O => \cb_int[11]_i_32_n_0\
);
\cb_int[11]_i_34\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[11]_i_34_n_0\
);
\cb_int[11]_i_35\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[11]_i_35_n_0\
);
\cb_int[11]_i_36\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[11]_i_36_n_0\
);
\cb_int[11]_i_37\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[11]_i_37_n_0\
);
\cb_int[11]_i_39\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[11]_i_39_n_0\
);
\cb_int[11]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cb_int[11]_i_14_n_0\,
I1 => \cb_int[11]_i_15_n_0\,
O => \cb_int[11]_i_4_n_0\
);
\cb_int[11]_i_40\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[11]_i_40_n_0\
);
\cb_int[11]_i_41\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[11]_i_41_n_0\
);
\cb_int[11]_i_42\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[11]_i_42_n_0\
);
\cb_int[11]_i_43\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[11]_i_43_n_0\
);
\cb_int[11]_i_44\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[0]\(2),
O => \cb_int[11]_i_44_n_0\
);
\cb_int[11]_i_45\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[0]\(1),
O => \cb_int[11]_i_45_n_0\
);
\cb_int[11]_i_46\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[0]\(0),
O => \cb_int[11]_i_46_n_0\
);
\cb_int[11]_i_47\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[0]_0\(3),
O => \cb_int[11]_i_47_n_0\
);
\cb_int[11]_i_49\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[0]\(3),
O => \cb_int[11]_i_49_n_0\
);
\cb_int[11]_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"DD1D0000"
)
port map (
I0 => cb_int_reg5(7),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(15),
I3 => cb_int_reg8,
I4 => \cb_int[11]_i_19_n_0\,
O => \cb_int[11]_i_5_n_0\
);
\cb_int[11]_i_50\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[0]\(3),
O => \cb_int[11]_i_50_n_0\
);
\cb_int[11]_i_51\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[0]\(3),
O => \cb_int[11]_i_51_n_0\
);
\cb_int[11]_i_52\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[0]\(3),
O => \cb_int[11]_i_52_n_0\
);
\cb_int[11]_i_53\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \cb_int_reg[11]_i_24_n_4\,
I1 => \cb_int_reg[11]_i_25_n_0\,
I2 => \rgb888[0]\(2),
O => \cb_int[11]_i_53_n_0\
);
\cb_int[11]_i_54\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \cb_int_reg[11]_i_24_n_5\,
I1 => \cb_int_reg[11]_i_25_n_0\,
I2 => \rgb888[0]\(1),
O => \cb_int[11]_i_54_n_0\
);
\cb_int[11]_i_55\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \cb_int_reg[11]_i_24_n_6\,
I1 => \cb_int_reg[11]_i_25_n_0\,
I2 => \rgb888[0]\(0),
O => \cb_int[11]_i_55_n_0\
);
\cb_int[11]_i_56\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \cb_int_reg[11]_i_24_n_7\,
I1 => \cb_int_reg[11]_i_25_n_0\,
I2 => \rgb888[0]_0\(3),
O => \cb_int[11]_i_56_n_0\
);
\cb_int[11]_i_57\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => cb_int_reg7(8),
I1 => cb_int_reg8,
I2 => \cb_int_reg[3]_i_16_n_4\,
O => \cb_int[11]_i_57_n_0\
);
\cb_int[11]_i_58\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => cb_int_reg7(12),
I1 => cb_int_reg8,
I2 => \cb_int_reg[31]_i_33_n_4\,
O => \cb_int[11]_i_58_n_0\
);
\cb_int[11]_i_59\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => cb_int_reg7(11),
I1 => cb_int_reg8,
I2 => \cb_int_reg[31]_i_33_n_5\,
O => \cb_int[11]_i_59_n_0\
);
\cb_int[11]_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cb_int[15]_i_16_n_0\,
I1 => \cb_int[15]_i_17_n_0\,
I2 => \cb_int[11]_i_2_n_0\,
O => \cb_int[11]_i_6_n_0\
);
\cb_int[11]_i_60\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => cb_int_reg7(10),
I1 => cb_int_reg8,
I2 => \cb_int_reg[31]_i_33_n_6\,
O => \cb_int[11]_i_60_n_0\
);
\cb_int[11]_i_61\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => cb_int_reg7(9),
I1 => cb_int_reg8,
I2 => \cb_int_reg[31]_i_33_n_7\,
O => \cb_int[11]_i_61_n_0\
);
\cb_int[11]_i_62\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_6\,
O => \cb_int[11]_i_62_n_0\
);
\cb_int[11]_i_63\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_7\,
O => \cb_int[11]_i_63_n_0\
);
\cb_int[11]_i_64\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_33_n_4\,
O => \cb_int[11]_i_64_n_0\
);
\cb_int[11]_i_65\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_33_n_5\,
O => \cb_int[11]_i_65_n_0\
);
\cb_int[11]_i_67\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[11]_i_67_n_0\
);
\cb_int[11]_i_68\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[11]_i_68_n_0\
);
\cb_int[11]_i_69\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[11]_i_69_n_0\
);
\cb_int[11]_i_7\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cb_int[11]_i_10_n_0\,
I1 => \cb_int[11]_i_11_n_0\,
I2 => \cb_int[11]_i_3_n_0\,
O => \cb_int[11]_i_7_n_0\
);
\cb_int[11]_i_70\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[11]_i_70_n_0\
);
\cb_int[11]_i_71\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[11]_i_71_n_0\
);
\cb_int[11]_i_72\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[11]_i_72_n_0\
);
\cb_int[11]_i_73\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[11]_i_73_n_0\
);
\cb_int[11]_i_74\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[11]_i_74_n_0\
);
\cb_int[11]_i_76\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \rgb888[0]\(2),
I1 => \rgb888[0]\(3),
O => \cb_int[11]_i_76_n_0\
);
\cb_int[11]_i_77\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[0]\(3),
O => \cb_int[11]_i_77_n_0\
);
\cb_int[11]_i_78\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[0]\(3),
O => \cb_int[11]_i_78_n_0\
);
\cb_int[11]_i_79\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[0]\(3),
O => \cb_int[11]_i_79_n_0\
);
\cb_int[11]_i_8\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cb_int[11]_i_12_n_0\,
I1 => \cb_int[11]_i_13_n_0\,
I2 => \cb_int[11]_i_4_n_0\,
O => \cb_int[11]_i_8_n_0\
);
\cb_int[11]_i_80\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[0]\(3),
I1 => \rgb888[0]\(2),
O => \cb_int[11]_i_80_n_0\
);
\cb_int[11]_i_82\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[11]_i_82_n_0\
);
\cb_int[11]_i_83\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_6\,
I1 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[11]_i_83_n_0\
);
\cb_int[11]_i_84\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cb_int_reg[31]_i_33_n_4\,
I1 => \cb_int_reg[31]_i_12_n_7\,
O => \cb_int[11]_i_84_n_0\
);
\cb_int[11]_i_85\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cb_int_reg[31]_i_33_n_6\,
I1 => \cb_int_reg[31]_i_33_n_5\,
O => \cb_int[11]_i_85_n_0\
);
\cb_int[11]_i_86\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[11]_i_86_n_0\
);
\cb_int[11]_i_87\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
I1 => \cb_int_reg[31]_i_12_n_6\,
O => \cb_int[11]_i_87_n_0\
);
\cb_int[11]_i_88\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_7\,
I1 => \cb_int_reg[31]_i_33_n_4\,
O => \cb_int[11]_i_88_n_0\
);
\cb_int[11]_i_89\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_33_n_5\,
I1 => \cb_int_reg[31]_i_33_n_6\,
O => \cb_int[11]_i_89_n_0\
);
\cb_int[11]_i_9\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cb_int[11]_i_14_n_0\,
I1 => \cb_int[11]_i_15_n_0\,
I2 => \cb_int[11]_i_5_n_0\,
O => \cb_int[11]_i_9_n_0\
);
\cb_int[11]_i_91\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \rgb888[0]\(0),
I1 => \rgb888[0]\(1),
O => \cb_int[11]_i_91_n_0\
);
\cb_int[11]_i_92\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \rgb888[0]_0\(2),
I1 => \rgb888[0]_0\(3),
O => \cb_int[11]_i_92_n_0\
);
\cb_int[11]_i_93\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \rgb888[0]_0\(0),
I1 => \rgb888[0]_0\(1),
O => \cb_int[11]_i_93_n_0\
);
\cb_int[11]_i_94\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cb_int_reg[3]_i_20_n_5\,
I1 => \cb_int_reg[3]_i_20_n_4\,
O => \cb_int[11]_i_94_n_0\
);
\cb_int[11]_i_95\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[0]\(1),
I1 => \rgb888[0]\(0),
O => \cb_int[11]_i_95_n_0\
);
\cb_int[11]_i_96\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[0]_0\(3),
I1 => \rgb888[0]_0\(2),
O => \cb_int[11]_i_96_n_0\
);
\cb_int[11]_i_97\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[0]_0\(1),
I1 => \rgb888[0]_0\(0),
O => \cb_int[11]_i_97_n_0\
);
\cb_int[11]_i_98\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_20_n_4\,
I1 => \cb_int_reg[3]_i_20_n_5\,
O => \cb_int[11]_i_98_n_0\
);
\cb_int[11]_i_99\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cb_int_reg[3]_i_16_n_4\,
I1 => \cb_int_reg[31]_i_33_n_7\,
O => \cb_int[11]_i_99_n_0\
);
\cb_int[15]_i_10\: unisim.vcomponents.LUT6
generic map(
INIT => X"DD1D22E222E2DD1D"
)
port map (
I0 => cb_int_reg5(14),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(22),
I3 => cb_int_reg8,
I4 => \cb_int[19]_i_26_n_0\,
I5 => cb_int_reg2(14),
O => \cb_int[15]_i_10_n_0\
);
\cb_int[15]_i_11\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFDD1DDD1D0000"
)
port map (
I0 => cb_int_reg5(13),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(21),
I3 => cb_int_reg8,
I4 => \cb_int[15]_i_18_n_0\,
I5 => cb_int_reg2(13),
O => \cb_int[15]_i_11_n_0\
);
\cb_int[15]_i_12\: unisim.vcomponents.LUT6
generic map(
INIT => X"DD1D22E222E2DD1D"
)
port map (
I0 => cb_int_reg5(13),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(21),
I3 => cb_int_reg8,
I4 => \cb_int[15]_i_18_n_0\,
I5 => cb_int_reg2(13),
O => \cb_int[15]_i_12_n_0\
);
\cb_int[15]_i_13\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFDD1DDD1D0000"
)
port map (
I0 => cb_int_reg5(12),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(20),
I3 => cb_int_reg8,
I4 => \cb_int[15]_i_21_n_0\,
I5 => cb_int_reg2(12),
O => \cb_int[15]_i_13_n_0\
);
\cb_int[15]_i_14\: unisim.vcomponents.LUT6
generic map(
INIT => X"DD1D22E222E2DD1D"
)
port map (
I0 => cb_int_reg5(12),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(20),
I3 => cb_int_reg8,
I4 => \cb_int[15]_i_21_n_0\,
I5 => cb_int_reg2(12),
O => \cb_int[15]_i_14_n_0\
);
\cb_int[15]_i_15\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFDD1DDD1D0000"
)
port map (
I0 => cb_int_reg5(11),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(19),
I3 => cb_int_reg8,
I4 => \cb_int[15]_i_23_n_0\,
I5 => cb_int_reg2(11),
O => \cb_int[15]_i_15_n_0\
);
\cb_int[15]_i_16\: unisim.vcomponents.LUT6
generic map(
INIT => X"DD1D22E222E2DD1D"
)
port map (
I0 => cb_int_reg5(11),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(19),
I3 => cb_int_reg8,
I4 => \cb_int[15]_i_23_n_0\,
I5 => cb_int_reg2(11),
O => \cb_int[15]_i_16_n_0\
);
\cb_int[15]_i_17\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFDD1DDD1D0000"
)
port map (
I0 => cb_int_reg5(10),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(18),
I3 => cb_int_reg8,
I4 => \cb_int[15]_i_25_n_0\,
I5 => cb_int_reg2(10),
O => \cb_int[15]_i_17_n_0\
);
\cb_int[15]_i_18\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_5\(0),
I1 => \rgb888[8]_1\(1),
I2 => \^co\(0),
I3 => \rgb888[8]_6\(0),
O => \cb_int[15]_i_18_n_0\
);
\cb_int[15]_i_19\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => cb_int_reg3(13),
I1 => \rgb888[0]\(3),
I2 => \rgb888[0]_3\(0),
I3 => \cb_int_reg[11]_i_25_n_0\,
O => cb_int_reg2(13)
);
\cb_int[15]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cb_int[15]_i_10_n_0\,
I1 => \cb_int[15]_i_11_n_0\,
O => \cb_int[15]_i_2_n_0\
);
\cb_int[15]_i_21\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_4\(3),
I1 => \rgb888[8]_1\(1),
I2 => \^co\(0),
I3 => \rgb888[12]_0\(3),
O => \cb_int[15]_i_21_n_0\
);
\cb_int[15]_i_22\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => cb_int_reg3(12),
I1 => \rgb888[0]\(3),
I2 => \rgb888[0]_4\(3),
I3 => \cb_int_reg[11]_i_25_n_0\,
O => cb_int_reg2(12)
);
\cb_int[15]_i_23\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_4\(2),
I1 => \rgb888[8]_1\(1),
I2 => \^co\(0),
I3 => \rgb888[12]_0\(2),
O => \cb_int[15]_i_23_n_0\
);
\cb_int[15]_i_24\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => cb_int_reg3(11),
I1 => \rgb888[0]\(3),
I2 => \rgb888[0]_4\(2),
I3 => \cb_int_reg[11]_i_25_n_0\,
O => cb_int_reg2(11)
);
\cb_int[15]_i_25\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_4\(1),
I1 => \rgb888[8]_1\(1),
I2 => \^co\(0),
I3 => \rgb888[12]_0\(1),
O => \cb_int[15]_i_25_n_0\
);
\cb_int[15]_i_26\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => cb_int_reg3(10),
I1 => \rgb888[0]\(3),
I2 => \rgb888[0]_4\(1),
I3 => \cb_int_reg[11]_i_25_n_0\,
O => cb_int_reg2(10)
);
\cb_int[15]_i_27\: unisim.vcomponents.LUT3
generic map(
INIT => X"8B"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
I1 => cb_int_reg8,
I2 => cb_int_reg7(20),
O => \cb_int[15]_i_27_n_0\
);
\cb_int[15]_i_28\: unisim.vcomponents.LUT3
generic map(
INIT => X"8B"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
I1 => cb_int_reg8,
I2 => cb_int_reg7(19),
O => \cb_int[15]_i_28_n_0\
);
\cb_int[15]_i_29\: unisim.vcomponents.LUT3
generic map(
INIT => X"8B"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
I1 => cb_int_reg8,
I2 => cb_int_reg7(18),
O => \cb_int[15]_i_29_n_0\
);
\cb_int[15]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cb_int[15]_i_12_n_0\,
I1 => \cb_int[15]_i_13_n_0\,
O => \cb_int[15]_i_3_n_0\
);
\cb_int[15]_i_30\: unisim.vcomponents.LUT3
generic map(
INIT => X"8B"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
I1 => cb_int_reg8,
I2 => cb_int_reg7(17),
O => \cb_int[15]_i_30_n_0\
);
\cb_int[15]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cb_int[15]_i_14_n_0\,
I1 => \cb_int[15]_i_15_n_0\,
O => \cb_int[15]_i_4_n_0\
);
\cb_int[15]_i_43\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \rgb888[0]\(3),
I1 => \cb_int_reg[11]_i_25_n_0\,
I2 => \rgb888[0]_4\(3),
O => \cb_int[15]_i_43_n_0\
);
\cb_int[15]_i_44\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \rgb888[0]\(3),
I1 => \cb_int_reg[11]_i_25_n_0\,
I2 => \rgb888[0]_4\(2),
O => \cb_int[15]_i_44_n_0\
);
\cb_int[15]_i_45\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \rgb888[0]\(3),
I1 => \cb_int_reg[11]_i_25_n_0\,
I2 => \rgb888[0]_4\(1),
O => \cb_int[15]_i_45_n_0\
);
\cb_int[15]_i_46\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \rgb888[0]\(3),
I1 => \cb_int_reg[11]_i_25_n_0\,
I2 => \rgb888[0]_4\(0),
O => \cb_int[15]_i_46_n_0\
);
\cb_int[15]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cb_int[15]_i_16_n_0\,
I1 => \cb_int[15]_i_17_n_0\,
O => \cb_int[15]_i_5_n_0\
);
\cb_int[15]_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cb_int[19]_i_16_n_0\,
I1 => \cb_int[19]_i_17_n_0\,
I2 => \cb_int[15]_i_2_n_0\,
O => \cb_int[15]_i_6_n_0\
);
\cb_int[15]_i_7\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cb_int[15]_i_10_n_0\,
I1 => \cb_int[15]_i_11_n_0\,
I2 => \cb_int[15]_i_3_n_0\,
O => \cb_int[15]_i_7_n_0\
);
\cb_int[15]_i_8\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cb_int[15]_i_12_n_0\,
I1 => \cb_int[15]_i_13_n_0\,
I2 => \cb_int[15]_i_4_n_0\,
O => \cb_int[15]_i_8_n_0\
);
\cb_int[15]_i_9\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cb_int[15]_i_14_n_0\,
I1 => \cb_int[15]_i_15_n_0\,
I2 => \cb_int[15]_i_5_n_0\,
O => \cb_int[15]_i_9_n_0\
);
\cb_int[19]_i_10\: unisim.vcomponents.LUT6
generic map(
INIT => X"DD1D22E222E2DD1D"
)
port map (
I0 => cb_int_reg5(18),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(26),
I3 => cb_int_reg8,
I4 => \cb_int[23]_i_25_n_0\,
I5 => cb_int_reg2(18),
O => \cb_int[19]_i_10_n_0\
);
\cb_int[19]_i_11\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFDD1DDD1D0000"
)
port map (
I0 => cb_int_reg5(17),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(25),
I3 => cb_int_reg8,
I4 => \cb_int[19]_i_18_n_0\,
I5 => cb_int_reg2(17),
O => \cb_int[19]_i_11_n_0\
);
\cb_int[19]_i_12\: unisim.vcomponents.LUT6
generic map(
INIT => X"DD1D22E222E2DD1D"
)
port map (
I0 => cb_int_reg5(17),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(25),
I3 => cb_int_reg8,
I4 => \cb_int[19]_i_18_n_0\,
I5 => cb_int_reg2(17),
O => \cb_int[19]_i_12_n_0\
);
\cb_int[19]_i_13\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFDD1DDD1D0000"
)
port map (
I0 => cb_int_reg5(16),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(24),
I3 => cb_int_reg8,
I4 => \cb_int[19]_i_21_n_0\,
I5 => cb_int_reg2(16),
O => \cb_int[19]_i_13_n_0\
);
\cb_int[19]_i_14\: unisim.vcomponents.LUT6
generic map(
INIT => X"DD1D22E222E2DD1D"
)
port map (
I0 => cb_int_reg5(16),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(24),
I3 => cb_int_reg8,
I4 => \cb_int[19]_i_21_n_0\,
I5 => cb_int_reg2(16),
O => \cb_int[19]_i_14_n_0\
);
\cb_int[19]_i_15\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFDD1DDD1D0000"
)
port map (
I0 => cb_int_reg5(15),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(23),
I3 => cb_int_reg8,
I4 => \cb_int[19]_i_23_n_0\,
I5 => cb_int_reg2(15),
O => \cb_int[19]_i_15_n_0\
);
\cb_int[19]_i_16\: unisim.vcomponents.LUT6
generic map(
INIT => X"DD1D22E222E2DD1D"
)
port map (
I0 => cb_int_reg5(15),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(23),
I3 => cb_int_reg8,
I4 => \cb_int[19]_i_23_n_0\,
I5 => cb_int_reg2(15),
O => \cb_int[19]_i_16_n_0\
);
\cb_int[19]_i_17\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFDD1DDD1D0000"
)
port map (
I0 => cb_int_reg5(14),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(22),
I3 => cb_int_reg8,
I4 => \cb_int[19]_i_26_n_0\,
I5 => cb_int_reg2(14),
O => \cb_int[19]_i_17_n_0\
);
\cb_int[19]_i_18\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_7\(0),
I1 => \rgb888[8]_1\(1),
I2 => \^co\(0),
I3 => \rgb888[8]_8\(0),
O => \cb_int[19]_i_18_n_0\
);
\cb_int[19]_i_19\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => cb_int_reg3(17),
I1 => \rgb888[0]\(3),
I2 => \rgb888[0]_2\(0),
I3 => \cb_int_reg[11]_i_25_n_0\,
O => cb_int_reg2(17)
);
\cb_int[19]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cb_int[19]_i_10_n_0\,
I1 => \cb_int[19]_i_11_n_0\,
O => \cb_int[19]_i_2_n_0\
);
\cb_int[19]_i_21\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_5\(3),
I1 => \rgb888[8]_1\(1),
I2 => \^co\(0),
I3 => \rgb888[8]_6\(3),
O => \cb_int[19]_i_21_n_0\
);
\cb_int[19]_i_22\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => cb_int_reg3(16),
I1 => \rgb888[0]\(3),
I2 => \rgb888[0]_3\(3),
I3 => \cb_int_reg[11]_i_25_n_0\,
O => cb_int_reg2(16)
);
\cb_int[19]_i_23\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_5\(2),
I1 => \rgb888[8]_1\(1),
I2 => \^co\(0),
I3 => \rgb888[8]_6\(2),
O => \cb_int[19]_i_23_n_0\
);
\cb_int[19]_i_24\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => cb_int_reg3(15),
I1 => \rgb888[0]\(3),
I2 => \rgb888[0]_3\(2),
I3 => \cb_int_reg[11]_i_25_n_0\,
O => cb_int_reg2(15)
);
\cb_int[19]_i_26\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_5\(1),
I1 => \rgb888[8]_1\(1),
I2 => \^co\(0),
I3 => \rgb888[8]_6\(1),
O => \cb_int[19]_i_26_n_0\
);
\cb_int[19]_i_27\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => cb_int_reg3(14),
I1 => \rgb888[0]\(3),
I2 => \rgb888[0]_3\(1),
I3 => \cb_int_reg[11]_i_25_n_0\,
O => cb_int_reg2(14)
);
\cb_int[19]_i_28\: unisim.vcomponents.LUT3
generic map(
INIT => X"8B"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
I1 => cb_int_reg8,
I2 => cb_int_reg7(24),
O => \cb_int[19]_i_28_n_0\
);
\cb_int[19]_i_29\: unisim.vcomponents.LUT3
generic map(
INIT => X"8B"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
I1 => cb_int_reg8,
I2 => cb_int_reg7(23),
O => \cb_int[19]_i_29_n_0\
);
\cb_int[19]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cb_int[19]_i_12_n_0\,
I1 => \cb_int[19]_i_13_n_0\,
O => \cb_int[19]_i_3_n_0\
);
\cb_int[19]_i_30\: unisim.vcomponents.LUT3
generic map(
INIT => X"8B"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
I1 => cb_int_reg8,
I2 => cb_int_reg7(22),
O => \cb_int[19]_i_30_n_0\
);
\cb_int[19]_i_31\: unisim.vcomponents.LUT3
generic map(
INIT => X"8B"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
I1 => cb_int_reg8,
I2 => cb_int_reg7(21),
O => \cb_int[19]_i_31_n_0\
);
\cb_int[19]_i_34\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[19]_i_34_n_0\
);
\cb_int[19]_i_35\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[19]_i_35_n_0\
);
\cb_int[19]_i_36\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[19]_i_36_n_0\
);
\cb_int[19]_i_37\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[19]_i_37_n_0\
);
\cb_int[19]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cb_int[19]_i_14_n_0\,
I1 => \cb_int[19]_i_15_n_0\,
O => \cb_int[19]_i_4_n_0\
);
\cb_int[19]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cb_int[19]_i_16_n_0\,
I1 => \cb_int[19]_i_17_n_0\,
O => \cb_int[19]_i_5_n_0\
);
\cb_int[19]_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cb_int[23]_i_16_n_0\,
I1 => \cb_int[23]_i_17_n_0\,
I2 => \cb_int[19]_i_2_n_0\,
O => \cb_int[19]_i_6_n_0\
);
\cb_int[19]_i_7\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cb_int[19]_i_10_n_0\,
I1 => \cb_int[19]_i_11_n_0\,
I2 => \cb_int[19]_i_3_n_0\,
O => \cb_int[19]_i_7_n_0\
);
\cb_int[19]_i_8\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cb_int[19]_i_12_n_0\,
I1 => \cb_int[19]_i_13_n_0\,
I2 => \cb_int[19]_i_4_n_0\,
O => \cb_int[19]_i_8_n_0\
);
\cb_int[19]_i_9\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cb_int[19]_i_14_n_0\,
I1 => \cb_int[19]_i_15_n_0\,
I2 => \cb_int[19]_i_5_n_0\,
O => \cb_int[19]_i_9_n_0\
);
\cb_int[23]_i_10\: unisim.vcomponents.LUT6
generic map(
INIT => X"DD1D22E222E2DD1D"
)
port map (
I0 => cb_int_reg5(22),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(30),
I3 => cb_int_reg8,
I4 => \cb_int[27]_i_10_n_0\,
I5 => cb_int_reg2(22),
O => \cb_int[23]_i_10_n_0\
);
\cb_int[23]_i_11\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFDD1DDD1D0000"
)
port map (
I0 => cb_int_reg5(21),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(29),
I3 => cb_int_reg8,
I4 => \cb_int[23]_i_18_n_0\,
I5 => cb_int_reg2(21),
O => \cb_int[23]_i_11_n_0\
);
\cb_int[23]_i_12\: unisim.vcomponents.LUT6
generic map(
INIT => X"DD1D22E222E2DD1D"
)
port map (
I0 => cb_int_reg5(21),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(29),
I3 => cb_int_reg8,
I4 => \cb_int[23]_i_18_n_0\,
I5 => cb_int_reg2(21),
O => \cb_int[23]_i_12_n_0\
);
\cb_int[23]_i_13\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFDD1DDD1D0000"
)
port map (
I0 => cb_int_reg5(20),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(28),
I3 => cb_int_reg8,
I4 => \cb_int[23]_i_20_n_0\,
I5 => cb_int_reg2(20),
O => \cb_int[23]_i_13_n_0\
);
\cb_int[23]_i_14\: unisim.vcomponents.LUT6
generic map(
INIT => X"DD1D22E222E2DD1D"
)
port map (
I0 => cb_int_reg5(20),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(28),
I3 => cb_int_reg8,
I4 => \cb_int[23]_i_20_n_0\,
I5 => cb_int_reg2(20),
O => \cb_int[23]_i_14_n_0\
);
\cb_int[23]_i_15\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFDD1DDD1D0000"
)
port map (
I0 => cb_int_reg5(19),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(27),
I3 => cb_int_reg8,
I4 => \cb_int[23]_i_22_n_0\,
I5 => cb_int_reg2(19),
O => \cb_int[23]_i_15_n_0\
);
\cb_int[23]_i_16\: unisim.vcomponents.LUT6
generic map(
INIT => X"DD1D22E222E2DD1D"
)
port map (
I0 => cb_int_reg5(19),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(27),
I3 => cb_int_reg8,
I4 => \cb_int[23]_i_22_n_0\,
I5 => cb_int_reg2(19),
O => \cb_int[23]_i_16_n_0\
);
\cb_int[23]_i_17\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFDD1DDD1D0000"
)
port map (
I0 => cb_int_reg5(18),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(26),
I3 => cb_int_reg8,
I4 => \cb_int[23]_i_25_n_0\,
I5 => cb_int_reg2(18),
O => \cb_int[23]_i_17_n_0\
);
\cb_int[23]_i_18\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_9\(0),
I1 => \rgb888[8]_1\(1),
I2 => \^co\(0),
I3 => \rgb888[8]_10\(0),
O => \cb_int[23]_i_18_n_0\
);
\cb_int[23]_i_19\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => cb_int_reg3(21),
I1 => \rgb888[0]\(3),
I2 => \rgb888[0]_1\(0),
I3 => \cb_int_reg[11]_i_25_n_0\,
O => cb_int_reg2(21)
);
\cb_int[23]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cb_int[23]_i_10_n_0\,
I1 => \cb_int[23]_i_11_n_0\,
O => \cb_int[23]_i_2_n_0\
);
\cb_int[23]_i_20\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_7\(3),
I1 => \rgb888[8]_1\(1),
I2 => \^co\(0),
I3 => \rgb888[8]_8\(3),
O => \cb_int[23]_i_20_n_0\
);
\cb_int[23]_i_21\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => cb_int_reg3(20),
I1 => \rgb888[0]\(3),
I2 => \rgb888[0]_2\(3),
I3 => \cb_int_reg[11]_i_25_n_0\,
O => cb_int_reg2(20)
);
\cb_int[23]_i_22\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_7\(2),
I1 => \rgb888[8]_1\(1),
I2 => \^co\(0),
I3 => \rgb888[8]_8\(2),
O => \cb_int[23]_i_22_n_0\
);
\cb_int[23]_i_23\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => cb_int_reg3(19),
I1 => \rgb888[0]\(3),
I2 => \rgb888[0]_2\(2),
I3 => \cb_int_reg[11]_i_25_n_0\,
O => cb_int_reg2(19)
);
\cb_int[23]_i_25\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_7\(1),
I1 => \rgb888[8]_1\(1),
I2 => \^co\(0),
I3 => \rgb888[8]_8\(1),
O => \cb_int[23]_i_25_n_0\
);
\cb_int[23]_i_26\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => cb_int_reg3(18),
I1 => \rgb888[0]\(3),
I2 => \rgb888[0]_2\(1),
I3 => \cb_int_reg[11]_i_25_n_0\,
O => cb_int_reg2(18)
);
\cb_int[23]_i_29\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[23]_i_29_n_0\
);
\cb_int[23]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cb_int[23]_i_12_n_0\,
I1 => \cb_int[23]_i_13_n_0\,
O => \cb_int[23]_i_3_n_0\
);
\cb_int[23]_i_30\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[23]_i_30_n_0\
);
\cb_int[23]_i_31\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[23]_i_31_n_0\
);
\cb_int[23]_i_32\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[23]_i_32_n_0\
);
\cb_int[23]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cb_int[23]_i_14_n_0\,
I1 => \cb_int[23]_i_15_n_0\,
O => \cb_int[23]_i_4_n_0\
);
\cb_int[23]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cb_int[23]_i_16_n_0\,
I1 => \cb_int[23]_i_17_n_0\,
O => \cb_int[23]_i_5_n_0\
);
\cb_int[23]_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cb_int[27]_i_7_n_0\,
I1 => \cb_int[27]_i_8_n_0\,
I2 => \cb_int[23]_i_2_n_0\,
O => \cb_int[23]_i_6_n_0\
);
\cb_int[23]_i_7\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cb_int[23]_i_10_n_0\,
I1 => \cb_int[23]_i_11_n_0\,
I2 => \cb_int[23]_i_3_n_0\,
O => \cb_int[23]_i_7_n_0\
);
\cb_int[23]_i_8\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cb_int[23]_i_12_n_0\,
I1 => \cb_int[23]_i_13_n_0\,
I2 => \cb_int[23]_i_4_n_0\,
O => \cb_int[23]_i_8_n_0\
);
\cb_int[23]_i_9\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cb_int[23]_i_14_n_0\,
I1 => \cb_int[23]_i_15_n_0\,
I2 => \cb_int[23]_i_5_n_0\,
O => \cb_int[23]_i_9_n_0\
);
\cb_int[27]_i_10\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_9\(1),
I1 => \rgb888[8]_1\(1),
I2 => \^co\(0),
I3 => \rgb888[8]_10\(1),
O => \cb_int[27]_i_10_n_0\
);
\cb_int[27]_i_11\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => cb_int_reg3(22),
I1 => \rgb888[0]\(3),
I2 => \rgb888[0]_1\(1),
I3 => \cb_int_reg[11]_i_25_n_0\,
O => cb_int_reg2(22)
);
\cb_int[27]_i_12\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[27]_i_12_n_0\
);
\cb_int[27]_i_13\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[27]_i_13_n_0\
);
\cb_int[27]_i_14\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[27]_i_14_n_0\
);
\cb_int[27]_i_15\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[27]_i_15_n_0\
);
\cb_int[27]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cb_int[27]_i_7_n_0\,
I1 => \cb_int[27]_i_8_n_0\,
O => \cb_int[27]_i_2_n_0\
);
\cb_int[27]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"55565556A9555556"
)
port map (
I0 => \cb_int[31]_i_2_n_0\,
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => \cb_int_reg[31]_i_11_n_1\,
I3 => \cb_int[31]_i_13_n_0\,
I4 => \rgb888[0]\(3),
I5 => \cb_int_reg[31]_i_7_n_1\,
O => \cb_int[27]_i_3_n_0\
);
\cb_int[27]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"55565556A9555556"
)
port map (
I0 => \cb_int[31]_i_2_n_0\,
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => \cb_int_reg[31]_i_11_n_1\,
I3 => \cb_int[31]_i_13_n_0\,
I4 => \rgb888[0]\(3),
I5 => \cb_int_reg[31]_i_7_n_1\,
O => \cb_int[27]_i_4_n_0\
);
\cb_int[27]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"55565556A9555556"
)
port map (
I0 => \cb_int[31]_i_2_n_0\,
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => \cb_int_reg[31]_i_11_n_1\,
I3 => \cb_int[31]_i_13_n_0\,
I4 => \rgb888[0]\(3),
I5 => \cb_int_reg[31]_i_7_n_1\,
O => \cb_int[27]_i_5_n_0\
);
\cb_int[27]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"55565556A9555556"
)
port map (
I0 => \cb_int[27]_i_2_n_0\,
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => \cb_int_reg[31]_i_11_n_1\,
I3 => \cb_int[31]_i_13_n_0\,
I4 => \rgb888[0]\(3),
I5 => \cb_int_reg[31]_i_7_n_1\,
O => \cb_int[27]_i_6_n_0\
);
\cb_int[27]_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"1E111E11E1EE1E11"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
I1 => \cb_int_reg[31]_i_11_n_1\,
I2 => \rgb888[8]_11\(0),
I3 => \rgb888[8]_1\(1),
I4 => \rgb888[0]\(3),
I5 => \cb_int_reg[31]_i_7_n_1\,
O => \cb_int[27]_i_7_n_0\
);
\cb_int[27]_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFDD1DDD1D0000"
)
port map (
I0 => cb_int_reg5(22),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(30),
I3 => cb_int_reg8,
I4 => \cb_int[27]_i_10_n_0\,
I5 => cb_int_reg2(22),
O => \cb_int[27]_i_8_n_0\
);
\cb_int[31]_i_13\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \rgb888[8]_11\(0),
I1 => \rgb888[8]_1\(1),
O => \cb_int[31]_i_13_n_0\
);
\cb_int[31]_i_15\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \rgb888[0]\(3),
I1 => \cb_int_reg[11]_i_25_n_0\,
I2 => \rgb888[0]_1\(1),
O => \cb_int[31]_i_15_n_0\
);
\cb_int[31]_i_16\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \rgb888[0]\(3),
I1 => \cb_int_reg[11]_i_25_n_0\,
I2 => \rgb888[0]_1\(0),
O => \cb_int[31]_i_16_n_0\
);
\cb_int[31]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"4404440444040000"
)
port map (
I0 => \cb_int_reg[31]_i_7_n_1\,
I1 => \rgb888[0]\(3),
I2 => \rgb888[8]_1\(1),
I3 => \rgb888[8]_11\(0),
I4 => \cb_int_reg[31]_i_11_n_1\,
I5 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[31]_i_2_n_0\
);
\cb_int[31]_i_24\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFFFFFFFFFF"
)
port map (
I0 => rgb888(15),
I1 => rgb888(13),
I2 => rgb888(11),
I3 => rgb888(10),
I4 => rgb888(12),
I5 => rgb888(14),
O => \^di\(0)
);
\cb_int[31]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"55565556A9555556"
)
port map (
I0 => \cb_int[31]_i_2_n_0\,
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => \cb_int_reg[31]_i_11_n_1\,
I3 => \cb_int[31]_i_13_n_0\,
I4 => \rgb888[0]\(3),
I5 => \cb_int_reg[31]_i_7_n_1\,
O => \cb_int[31]_i_3_n_0\
);
\cb_int[31]_i_31\: unisim.vcomponents.LUT3
generic map(
INIT => X"8B"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
I1 => cb_int_reg8,
I2 => cb_int_reg7(30),
O => \cb_int[31]_i_31_n_0\
);
\cb_int[31]_i_32\: unisim.vcomponents.LUT3
generic map(
INIT => X"8B"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
I1 => cb_int_reg8,
I2 => cb_int_reg7(29),
O => \cb_int[31]_i_32_n_0\
);
\cb_int[31]_i_35\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_34_n_2\,
O => \cb_int[31]_i_35_n_0\
);
\cb_int[31]_i_36\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_34_n_2\,
O => \cb_int[31]_i_36_n_0\
);
\cb_int[31]_i_38\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \rgb888[0]\(3),
I1 => \cb_int_reg[11]_i_25_n_0\,
I2 => \rgb888[0]_2\(3),
O => \cb_int[31]_i_38_n_0\
);
\cb_int[31]_i_39\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \rgb888[0]\(3),
I1 => \cb_int_reg[11]_i_25_n_0\,
I2 => \rgb888[0]_2\(2),
O => \cb_int[31]_i_39_n_0\
);
\cb_int[31]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"55565556A9555556"
)
port map (
I0 => \cb_int[31]_i_2_n_0\,
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => \cb_int_reg[31]_i_11_n_1\,
I3 => \cb_int[31]_i_13_n_0\,
I4 => \rgb888[0]\(3),
I5 => \cb_int_reg[31]_i_7_n_1\,
O => \cb_int[31]_i_4_n_0\
);
\cb_int[31]_i_40\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \rgb888[0]\(3),
I1 => \cb_int_reg[11]_i_25_n_0\,
I2 => \rgb888[0]_2\(1),
O => \cb_int[31]_i_40_n_0\
);
\cb_int[31]_i_41\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \rgb888[0]\(3),
I1 => \cb_int_reg[11]_i_25_n_0\,
I2 => \rgb888[0]_2\(0),
O => \cb_int[31]_i_41_n_0\
);
\cb_int[31]_i_43\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000001FFFFFFFE"
)
port map (
I0 => rgb888(5),
I1 => rgb888(3),
I2 => rgb888(1),
I3 => rgb888(2),
I4 => rgb888(4),
I5 => rgb888(6),
O => \^cr_int_reg[27]_1\(1)
);
\cb_int[31]_i_44\: unisim.vcomponents.LUT5
generic map(
INIT => X"0001FFFE"
)
port map (
I0 => rgb888(4),
I1 => rgb888(2),
I2 => rgb888(1),
I3 => rgb888(3),
I4 => rgb888(5),
O => \^cr_int_reg[27]_1\(0)
);
\cb_int[31]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"55565556A9555556"
)
port map (
I0 => \cb_int[31]_i_2_n_0\,
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => \cb_int_reg[31]_i_11_n_1\,
I3 => \cb_int[31]_i_13_n_0\,
I4 => \rgb888[0]\(3),
I5 => \cb_int_reg[31]_i_7_n_1\,
O => \cb_int[31]_i_5_n_0\
);
\cb_int[31]_i_51\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => rgb888(5),
I1 => rgb888(3),
I2 => rgb888(1),
I3 => rgb888(2),
I4 => rgb888(4),
I5 => rgb888(6),
O => \^cr_int_reg[27]_0\
);
\cb_int[31]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"55565556A9555556"
)
port map (
I0 => \cb_int[31]_i_2_n_0\,
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => \cb_int_reg[31]_i_11_n_1\,
I3 => \cb_int[31]_i_13_n_0\,
I4 => \rgb888[0]\(3),
I5 => \cb_int_reg[31]_i_7_n_1\,
O => \cb_int[31]_i_6_n_0\
);
\cb_int[31]_i_67\: unisim.vcomponents.LUT3
generic map(
INIT => X"8B"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
I1 => cb_int_reg8,
I2 => cb_int_reg7(28),
O => \cb_int[31]_i_67_n_0\
);
\cb_int[31]_i_68\: unisim.vcomponents.LUT3
generic map(
INIT => X"8B"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
I1 => cb_int_reg8,
I2 => cb_int_reg7(27),
O => \cb_int[31]_i_68_n_0\
);
\cb_int[31]_i_69\: unisim.vcomponents.LUT3
generic map(
INIT => X"8B"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
I1 => cb_int_reg8,
I2 => cb_int_reg7(26),
O => \cb_int[31]_i_69_n_0\
);
\cb_int[31]_i_70\: unisim.vcomponents.LUT3
generic map(
INIT => X"8B"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
I1 => cb_int_reg8,
I2 => cb_int_reg7(25),
O => \cb_int[31]_i_70_n_0\
);
\cb_int[31]_i_71\: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => \cb_int_reg[31]_i_73_n_5\,
I1 => rgb888(23),
I2 => rgb888(22),
O => \cb_int[31]_i_71_n_0\
);
\cb_int[31]_i_72\: unisim.vcomponents.LUT3
generic map(
INIT => X"82"
)
port map (
I0 => \cb_int_reg[31]_i_73_n_6\,
I1 => rgb888(23),
I2 => rgb888(22),
O => \cb_int[31]_i_72_n_0\
);
\cb_int[31]_i_74\: unisim.vcomponents.LUT4
generic map(
INIT => X"1FE0"
)
port map (
I0 => rgb888(22),
I1 => rgb888(23),
I2 => \cb_int_reg[31]_i_73_n_4\,
I3 => \cb_int_reg[31]_i_34_n_7\,
O => \cb_int[31]_i_74_n_0\
);
\cb_int[31]_i_75\: unisim.vcomponents.LUT4
generic map(
INIT => X"3336"
)
port map (
I0 => \cb_int_reg[31]_i_73_n_5\,
I1 => \cb_int_reg[31]_i_73_n_4\,
I2 => rgb888(22),
I3 => rgb888(23),
O => \cb_int[31]_i_75_n_0\
);
\cb_int[31]_i_76\: unisim.vcomponents.LUT4
generic map(
INIT => X"7E81"
)
port map (
I0 => \cb_int_reg[31]_i_73_n_6\,
I1 => rgb888(22),
I2 => rgb888(23),
I3 => \cb_int_reg[31]_i_73_n_5\,
O => \cb_int[31]_i_76_n_0\
);
\cb_int[31]_i_77\: unisim.vcomponents.LUT4
generic map(
INIT => X"9669"
)
port map (
I0 => \cb_int_reg[31]_i_73_n_7\,
I1 => \cb_int_reg[31]_i_73_n_6\,
I2 => rgb888(22),
I3 => rgb888(23),
O => \cb_int[31]_i_77_n_0\
);
\cb_int[31]_i_78\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(23),
O => \cb_int[31]_i_78_n_0\
);
\cb_int[31]_i_79\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \rgb888[0]\(3),
I1 => \cb_int_reg[11]_i_25_n_0\,
I2 => \rgb888[0]_3\(3),
O => \cb_int[31]_i_79_n_0\
);
\cb_int[31]_i_80\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \rgb888[0]\(3),
I1 => \cb_int_reg[11]_i_25_n_0\,
I2 => \rgb888[0]_3\(2),
O => \cb_int[31]_i_80_n_0\
);
\cb_int[31]_i_81\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \rgb888[0]\(3),
I1 => \cb_int_reg[11]_i_25_n_0\,
I2 => \rgb888[0]_3\(1),
O => \cb_int[31]_i_81_n_0\
);
\cb_int[31]_i_82\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \rgb888[0]\(3),
I1 => \cb_int_reg[11]_i_25_n_0\,
I2 => \rgb888[0]_3\(0),
O => \cb_int[31]_i_82_n_0\
);
\cb_int[31]_i_86\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => rgb888(11),
I1 => rgb888(10),
I2 => rgb888(12),
I3 => rgb888(13),
O => \^cr_int_reg[31]_1\
);
\cb_int[31]_i_87\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => rgb888(12),
I1 => rgb888(10),
I2 => rgb888(11),
I3 => rgb888(13),
I4 => rgb888(14),
O => \^cr_int_reg[31]_0\
);
\cb_int[31]_i_95\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(22),
O => \cb_int[31]_i_95_n_0\
);
\cb_int[31]_i_96\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(23),
I1 => rgb888(21),
O => \cb_int[31]_i_96_n_0\
);
\cb_int[31]_i_97\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(22),
I1 => rgb888(20),
O => \cb_int[31]_i_97_n_0\
);
\cb_int[31]_i_98\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(21),
I1 => rgb888(19),
O => \cb_int[31]_i_98_n_0\
);
\cb_int[3]_i_10\: unisim.vcomponents.LUT5
generic map(
INIT => X"44477747"
)
port map (
I0 => \rgb888[8]_2\(1),
I1 => \rgb888[8]_1\(1),
I2 => \rgb888[13]_0\(1),
I3 => \^co\(0),
I4 => \rgb888[8]\(3),
O => \cb_int[3]_i_10_n_0\
);
\cb_int[3]_i_100\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(0),
I1 => rgb888(2),
O => \cb_int[3]_i_100_n_0\
);
\cb_int[3]_i_101\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(1),
O => \cb_int[3]_i_101_n_0\
);
\cb_int[3]_i_102\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => rgb888(0),
O => \cb_int[3]_i_102_n_0\
);
\cb_int[3]_i_103\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(8),
I1 => rgb888(11),
O => \cb_int[3]_i_103_n_0\
);
\cb_int[3]_i_104\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(10),
O => \cb_int[3]_i_104_n_0\
);
\cb_int[3]_i_105\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(9),
O => \cb_int[3]_i_105_n_0\
);
\cb_int[3]_i_106\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => rgb888(8),
O => \cb_int[3]_i_106_n_0\
);
\cb_int[3]_i_11\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => cb_int_reg3(2),
I1 => \rgb888[0]\(3),
I2 => \rgb888[0]_0\(0),
I3 => \cb_int_reg[11]_i_25_n_0\,
I4 => \cb_int_reg[7]_i_29_n_6\,
O => cb_int_reg2(2)
);
\cb_int[3]_i_12\: unisim.vcomponents.LUT5
generic map(
INIT => X"1D001DFF"
)
port map (
I0 => cb_int_reg7(9),
I1 => cb_int_reg8,
I2 => \cb_int_reg[31]_i_33_n_7\,
I3 => \cb_int_reg[31]_i_12_n_1\,
I4 => cb_int_reg5(1),
O => \cb_int[3]_i_12_n_0\
);
\cb_int[3]_i_13\: unisim.vcomponents.LUT5
generic map(
INIT => X"44477747"
)
port map (
I0 => \rgb888[8]_2\(0),
I1 => \rgb888[8]_1\(1),
I2 => \rgb888[13]_0\(0),
I3 => \^co\(0),
I4 => \rgb888[8]\(2),
O => \cb_int[3]_i_13_n_0\
);
\cb_int[3]_i_14\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => cb_int_reg3(1),
I1 => \rgb888[0]\(3),
I2 => \cb_int_reg[3]_i_20_n_4\,
I3 => \cb_int_reg[11]_i_25_n_0\,
I4 => \cb_int_reg[7]_i_29_n_7\,
O => cb_int_reg2(1)
);
\cb_int[3]_i_17\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \rgb888[8]\(1),
I1 => \^co\(0),
I2 => \rgb888[13]\(0),
O => \cb_int[3]_i_17_n_0\
);
\cb_int[3]_i_18\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cb_int_reg[3]_i_20_n_5\,
I1 => \cb_int_reg[11]_i_25_n_0\,
I2 => \cb_int_reg[3]_i_33_n_4\,
O => \cb_int[3]_i_18_n_0\
);
\cb_int[3]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \cb_int[3]_i_9_n_0\,
I1 => \cb_int[3]_i_10_n_0\,
I2 => cb_int_reg2(2),
O => \cb_int[3]_i_2_n_0\
);
\cb_int[3]_i_22\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_33_n_6\,
O => \cb_int[3]_i_22_n_0\
);
\cb_int[3]_i_23\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_33_n_7\,
O => \cb_int[3]_i_23_n_0\
);
\cb_int[3]_i_24\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_16_n_4\,
O => \cb_int[3]_i_24_n_0\
);
\cb_int[3]_i_25\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_16_n_5\,
O => \cb_int[3]_i_25_n_0\
);
\cb_int[3]_i_27\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_73_n_7\,
O => \cb_int[3]_i_27_n_0\
);
\cb_int[3]_i_28\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \cb_int_reg[31]_i_73_n_7\,
I1 => rgb888(22),
O => \cb_int[3]_i_28_n_0\
);
\cb_int[3]_i_29\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(21),
I1 => \cb_int_reg[3]_i_57_n_4\,
O => \cb_int[3]_i_29_n_0\
);
\cb_int[3]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \cb_int[3]_i_12_n_0\,
I1 => \cb_int[3]_i_13_n_0\,
I2 => cb_int_reg2(1),
O => \cb_int[3]_i_3_n_0\
);
\cb_int[3]_i_30\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(20),
I1 => \cb_int_reg[3]_i_57_n_5\,
O => \cb_int[3]_i_30_n_0\
);
\cb_int[3]_i_31\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(19),
I1 => \cb_int_reg[3]_i_57_n_6\,
O => \cb_int[3]_i_31_n_0\
);
\cb_int[3]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"1DFF001D"
)
port map (
I0 => cb_int_reg7(8),
I1 => cb_int_reg8,
I2 => \cb_int_reg[3]_i_16_n_4\,
I3 => \cb_int[3]_i_17_n_0\,
I4 => \cb_int[3]_i_18_n_0\,
O => \cb_int[3]_i_4_n_0\
);
\cb_int[3]_i_45\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => rgb888(2),
I1 => rgb888(1),
I2 => \rgb888[0]_8\(1),
O => \cb_int[3]_i_45_n_0\
);
\cb_int[3]_i_46\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \rgb888[0]_8\(0),
I1 => rgb888(1),
O => \cb_int[3]_i_46_n_0\
);
\cb_int[3]_i_47\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \cb_int_reg[3]_i_44_n_4\,
I1 => rgb888(0),
O => \cb_int[3]_i_47_n_0\
);
\cb_int[3]_i_48\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg[3]_i_44_n_5\,
O => \cb_int[3]_i_48_n_0\
);
\cb_int[3]_i_49\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_26_n_6\,
O => \cb_int[3]_i_49_n_0\
);
\cb_int[3]_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \cb_int[7]_i_16_n_0\,
I1 => \cb_int[7]_i_17_n_0\,
I2 => cb_int_reg2(3),
I3 => \cb_int[3]_i_2_n_0\,
O => \cb_int[3]_i_5_n_0\
);
\cb_int[3]_i_50\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_16_n_6\,
O => \cb_int[3]_i_50_n_0\
);
\cb_int[3]_i_51\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_16_n_7\,
O => \cb_int[3]_i_51_n_0\
);
\cb_int[3]_i_52\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_26_n_4\,
O => \cb_int[3]_i_52_n_0\
);
\cb_int[3]_i_53\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_26_n_5\,
O => \cb_int[3]_i_53_n_0\
);
\cb_int[3]_i_54\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(18),
I1 => \cb_int_reg[3]_i_57_n_7\,
O => \cb_int[3]_i_54_n_0\
);
\cb_int[3]_i_55\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(17),
I1 => rgb888(16),
O => \cb_int[3]_i_55_n_0\
);
\cb_int[3]_i_56\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => rgb888(16),
O => \cb_int[3]_i_56_n_0\
);
\cb_int[3]_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \cb_int[3]_i_9_n_0\,
I1 => \cb_int[3]_i_10_n_0\,
I2 => cb_int_reg2(2),
I3 => \cb_int[3]_i_3_n_0\,
O => \cb_int[3]_i_6_n_0\
);
\cb_int[3]_i_64\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_20_n_5\,
O => \cb_int[3]_i_64_n_0\
);
\cb_int[3]_i_65\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_20_n_6\,
O => \cb_int[3]_i_65_n_0\
);
\cb_int[3]_i_66\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_20_n_7\,
O => \cb_int[3]_i_66_n_0\
);
\cb_int[3]_i_67\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_44_n_6\,
O => \cb_int[3]_i_67_n_0\
);
\cb_int[3]_i_69\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => rgb888(8),
I1 => rgb888(10),
I2 => \rgb888[8]_31\(2),
O => \cb_int[3]_i_69_n_0\
);
\cb_int[3]_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \cb_int[3]_i_12_n_0\,
I1 => \cb_int[3]_i_13_n_0\,
I2 => cb_int_reg2(1),
I3 => \cb_int[3]_i_4_n_0\,
O => \cb_int[3]_i_7_n_0\
);
\cb_int[3]_i_70\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \rgb888[8]_31\(1),
I1 => rgb888(9),
O => \cb_int[3]_i_70_n_0\
);
\cb_int[3]_i_71\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \rgb888[8]_31\(0),
I1 => rgb888(8),
O => \cb_int[3]_i_71_n_0\
);
\cb_int[3]_i_72\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg[3]_i_94_n_4\,
O => \cb_int[3]_i_72_n_0\
);
\cb_int[3]_i_76\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(7),
I1 => rgb888(5),
O => \cb_int[3]_i_76_n_0\
);
\cb_int[3]_i_77\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(6),
I1 => rgb888(4),
O => \cb_int[3]_i_77_n_0\
);
\cb_int[3]_i_78\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(5),
I1 => rgb888(3),
O => \cb_int[3]_i_78_n_0\
);
\cb_int[3]_i_79\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(4),
I1 => rgb888(2),
O => \cb_int[3]_i_79_n_0\
);
\cb_int[3]_i_8\: unisim.vcomponents.LUT5
generic map(
INIT => X"1DE2E21D"
)
port map (
I0 => cb_int_reg7(8),
I1 => cb_int_reg8,
I2 => \cb_int_reg[3]_i_16_n_4\,
I3 => \cb_int[3]_i_17_n_0\,
I4 => \cb_int[3]_i_18_n_0\,
O => \cb_int[3]_i_8_n_0\
);
\cb_int[3]_i_80\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(20),
I1 => rgb888(18),
O => \cb_int[3]_i_80_n_0\
);
\cb_int[3]_i_81\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(19),
I1 => rgb888(17),
O => \cb_int[3]_i_81_n_0\
);
\cb_int[3]_i_82\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(18),
I1 => rgb888(16),
O => \cb_int[3]_i_82_n_0\
);
\cb_int[3]_i_83\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => rgb888(17),
O => \cb_int[3]_i_83_n_0\
);
\cb_int[3]_i_89\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_75_n_7\,
O => \cb_int[3]_i_89_n_0\
);
\cb_int[3]_i_9\: unisim.vcomponents.LUT5
generic map(
INIT => X"1D001DFF"
)
port map (
I0 => cb_int_reg7(10),
I1 => cb_int_reg8,
I2 => \cb_int_reg[31]_i_33_n_6\,
I3 => \cb_int_reg[31]_i_12_n_1\,
I4 => cb_int_reg5(2),
O => \cb_int[3]_i_9_n_0\
);
\cb_int[3]_i_90\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_44_n_7\,
O => \cb_int[3]_i_90_n_0\
);
\cb_int[3]_i_91\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_75_n_4\,
O => \cb_int[3]_i_91_n_0\
);
\cb_int[3]_i_92\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_75_n_5\,
O => \cb_int[3]_i_92_n_0\
);
\cb_int[3]_i_93\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_75_n_6\,
O => \cb_int[3]_i_93_n_0\
);
\cb_int[3]_i_99\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(3),
I1 => rgb888(1),
O => \cb_int[3]_i_99_n_0\
);
\cb_int[7]_i_10\: unisim.vcomponents.LUT5
generic map(
INIT => X"1D001DFF"
)
port map (
I0 => cb_int_reg7(13),
I1 => cb_int_reg8,
I2 => \cb_int_reg[31]_i_12_n_7\,
I3 => \cb_int_reg[31]_i_12_n_1\,
I4 => cb_int_reg5(5),
O => \cb_int[7]_i_10_n_0\
);
\cb_int[7]_i_11\: unisim.vcomponents.LUT5
generic map(
INIT => X"44477747"
)
port map (
I0 => \rgb888[8]_3\(0),
I1 => \rgb888[8]_1\(1),
I2 => \rgb888[12]\(0),
I3 => \^co\(0),
I4 => \rgb888[8]_0\(2),
O => \cb_int[7]_i_11_n_0\
);
\cb_int[7]_i_12\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => cb_int_reg3(5),
I1 => \rgb888[0]\(3),
I2 => \rgb888[0]_0\(3),
I3 => \cb_int_reg[11]_i_25_n_0\,
I4 => \cb_int_reg[11]_i_24_n_7\,
O => cb_int_reg2(5)
);
\cb_int[7]_i_13\: unisim.vcomponents.LUT5
generic map(
INIT => X"1D001DFF"
)
port map (
I0 => cb_int_reg7(12),
I1 => cb_int_reg8,
I2 => \cb_int_reg[31]_i_33_n_4\,
I3 => \cb_int_reg[31]_i_12_n_1\,
I4 => cb_int_reg5(4),
O => \cb_int[7]_i_13_n_0\
);
\cb_int[7]_i_14\: unisim.vcomponents.LUT5
generic map(
INIT => X"44477747"
)
port map (
I0 => \rgb888[8]_2\(3),
I1 => \rgb888[8]_1\(1),
I2 => \rgb888[13]_0\(3),
I3 => \^co\(0),
I4 => \rgb888[8]_0\(1),
O => \cb_int[7]_i_14_n_0\
);
\cb_int[7]_i_15\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => cb_int_reg3(4),
I1 => \rgb888[0]\(3),
I2 => \rgb888[0]_0\(2),
I3 => \cb_int_reg[11]_i_25_n_0\,
I4 => \cb_int_reg[7]_i_29_n_4\,
O => cb_int_reg2(4)
);
\cb_int[7]_i_16\: unisim.vcomponents.LUT5
generic map(
INIT => X"1D001DFF"
)
port map (
I0 => cb_int_reg7(11),
I1 => cb_int_reg8,
I2 => \cb_int_reg[31]_i_33_n_5\,
I3 => \cb_int_reg[31]_i_12_n_1\,
I4 => cb_int_reg5(3),
O => \cb_int[7]_i_16_n_0\
);
\cb_int[7]_i_17\: unisim.vcomponents.LUT5
generic map(
INIT => X"44477747"
)
port map (
I0 => \rgb888[8]_2\(2),
I1 => \rgb888[8]_1\(1),
I2 => \rgb888[13]_0\(2),
I3 => \^co\(0),
I4 => \rgb888[8]_0\(0),
O => \cb_int[7]_i_17_n_0\
);
\cb_int[7]_i_18\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => cb_int_reg3(3),
I1 => \rgb888[0]\(3),
I2 => \rgb888[0]_0\(1),
I3 => \cb_int_reg[11]_i_25_n_0\,
I4 => \cb_int_reg[7]_i_29_n_5\,
O => cb_int_reg2(3)
);
\cb_int[7]_i_19\: unisim.vcomponents.LUT4
generic map(
INIT => X"B0BF"
)
port map (
I0 => cb_int_reg8,
I1 => cb_int_reg7(15),
I2 => \cb_int_reg[31]_i_12_n_1\,
I3 => cb_int_reg5(7),
O => \cb_int[7]_i_19_n_0\
);
\cb_int[7]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"5959A959"
)
port map (
I0 => \cb_int[11]_i_19_n_0\,
I1 => cb_int_reg5(7),
I2 => \cb_int_reg[31]_i_12_n_1\,
I3 => cb_int_reg7(15),
I4 => cb_int_reg8,
O => \cb_int[7]_i_2_n_0\
);
\cb_int[7]_i_20\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => cb_int_reg3(6),
I1 => \rgb888[0]\(3),
I2 => \rgb888[0]\(0),
I3 => \cb_int_reg[11]_i_25_n_0\,
I4 => \cb_int_reg[11]_i_24_n_6\,
O => cb_int_reg2(6)
);
\cb_int[7]_i_21\: unisim.vcomponents.LUT5
generic map(
INIT => X"44477747"
)
port map (
I0 => \rgb888[8]_3\(1),
I1 => \rgb888[8]_1\(1),
I2 => \rgb888[12]\(1),
I3 => \^co\(0),
I4 => \rgb888[8]_0\(3),
O => \cb_int[7]_i_21_n_0\
);
\cb_int[7]_i_22\: unisim.vcomponents.LUT5
generic map(
INIT => X"1D001DFF"
)
port map (
I0 => cb_int_reg7(14),
I1 => cb_int_reg8,
I2 => \cb_int_reg[31]_i_12_n_6\,
I3 => \cb_int_reg[31]_i_12_n_1\,
I4 => cb_int_reg5(6),
O => \cb_int[7]_i_22_n_0\
);
\cb_int[7]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \cb_int[7]_i_10_n_0\,
I1 => \cb_int[7]_i_11_n_0\,
I2 => cb_int_reg2(5),
O => \cb_int[7]_i_3_n_0\
);
\cb_int[7]_i_39\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[8]_1\(1),
O => \cb_int[7]_i_39_n_0\
);
\cb_int[7]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \cb_int[7]_i_13_n_0\,
I1 => \cb_int[7]_i_14_n_0\,
I2 => cb_int_reg2(4),
O => \cb_int[7]_i_4_n_0\
);
\cb_int[7]_i_40\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[8]_1\(1),
O => \cb_int[7]_i_40_n_0\
);
\cb_int[7]_i_41\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[8]_1\(1),
O => \cb_int[7]_i_41_n_0\
);
\cb_int[7]_i_42\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[8]_1\(1),
O => \cb_int[7]_i_42_n_0\
);
\cb_int[7]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \cb_int[7]_i_16_n_0\,
I1 => \cb_int[7]_i_17_n_0\,
I2 => cb_int_reg2(3),
O => \cb_int[7]_i_5_n_0\
);
\cb_int[7]_i_52\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \cb_int_reg[3]_i_33_n_4\,
I1 => \cb_int_reg[11]_i_25_n_0\,
I2 => \cb_int_reg[3]_i_20_n_5\,
O => \cb_int[7]_i_52_n_0\
);
\cb_int[7]_i_53\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \cb_int_reg[7]_i_29_n_4\,
I1 => \cb_int_reg[11]_i_25_n_0\,
I2 => \rgb888[0]_0\(2),
O => \cb_int[7]_i_53_n_0\
);
\cb_int[7]_i_54\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \cb_int_reg[7]_i_29_n_5\,
I1 => \cb_int_reg[11]_i_25_n_0\,
I2 => \rgb888[0]_0\(1),
O => \cb_int[7]_i_54_n_0\
);
\cb_int[7]_i_55\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \cb_int_reg[7]_i_29_n_6\,
I1 => \cb_int_reg[11]_i_25_n_0\,
I2 => \rgb888[0]_0\(0),
O => \cb_int[7]_i_55_n_0\
);
\cb_int[7]_i_56\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \cb_int_reg[7]_i_29_n_7\,
I1 => \cb_int_reg[11]_i_25_n_0\,
I2 => \cb_int_reg[3]_i_20_n_4\,
O => \cb_int[7]_i_56_n_0\
);
\cb_int[7]_i_57\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[0]_0\(2),
O => \cb_int[7]_i_57_n_0\
);
\cb_int[7]_i_58\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[0]_0\(1),
O => \cb_int[7]_i_58_n_0\
);
\cb_int[7]_i_59\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[0]_0\(0),
O => \cb_int[7]_i_59_n_0\
);
\cb_int[7]_i_6\: unisim.vcomponents.LUT5
generic map(
INIT => X"99969666"
)
port map (
I0 => \cb_int[7]_i_19_n_0\,
I1 => \cb_int[11]_i_19_n_0\,
I2 => cb_int_reg2(6),
I3 => \cb_int[7]_i_21_n_0\,
I4 => \cb_int[7]_i_22_n_0\,
O => \cb_int[7]_i_6_n_0\
);
\cb_int[7]_i_60\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_20_n_4\,
O => \cb_int[7]_i_60_n_0\
);
\cb_int[7]_i_62\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[8]_1\(1),
O => \cb_int[7]_i_62_n_0\
);
\cb_int[7]_i_63\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[8]_1\(1),
O => \cb_int[7]_i_63_n_0\
);
\cb_int[7]_i_64\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[8]_1\(1),
O => \cb_int[7]_i_64_n_0\
);
\cb_int[7]_i_65\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[8]_1\(1),
O => \cb_int[7]_i_65_n_0\
);
\cb_int[7]_i_67\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \rgb888[8]_0\(3),
I1 => \rgb888[8]_1\(0),
O => \cb_int[7]_i_67_n_0\
);
\cb_int[7]_i_68\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \rgb888[8]_0\(1),
I1 => \rgb888[8]_0\(2),
O => \cb_int[7]_i_68_n_0\
);
\cb_int[7]_i_69\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \rgb888[8]\(3),
I1 => \rgb888[8]_0\(0),
O => \cb_int[7]_i_69_n_0\
);
\cb_int[7]_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \cb_int[7]_i_3_n_0\,
I1 => cb_int_reg2(6),
I2 => \cb_int[7]_i_21_n_0\,
I3 => \cb_int[7]_i_22_n_0\,
O => \cb_int[7]_i_7_n_0\
);
\cb_int[7]_i_70\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \rgb888[8]\(1),
I1 => \rgb888[8]\(2),
O => \cb_int[7]_i_70_n_0\
);
\cb_int[7]_i_71\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[8]_1\(0),
I1 => \rgb888[8]_0\(3),
O => \cb_int[7]_i_71_n_0\
);
\cb_int[7]_i_72\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[8]_0\(2),
I1 => \rgb888[8]_0\(1),
O => \cb_int[7]_i_72_n_0\
);
\cb_int[7]_i_73\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[8]_0\(0),
I1 => \rgb888[8]\(3),
O => \cb_int[7]_i_73_n_0\
);
\cb_int[7]_i_74\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[8]\(2),
I1 => \rgb888[8]\(1),
O => \cb_int[7]_i_74_n_0\
);
\cb_int[7]_i_75\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \^cb_int_reg[3]_0\(3),
I1 => \rgb888[8]\(0),
O => \cb_int[7]_i_75_n_0\
);
\cb_int[7]_i_76\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \^cb_int_reg[3]_0\(1),
I1 => \^cb_int_reg[3]_0\(2),
O => \cb_int[7]_i_76_n_0\
);
\cb_int[7]_i_77\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \^o\(1),
I1 => \^cb_int_reg[3]_0\(0),
O => \cb_int[7]_i_77_n_0\
);
\cb_int[7]_i_78\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => rgb888(8),
I1 => \^o\(0),
O => \cb_int[7]_i_78_n_0\
);
\cb_int[7]_i_79\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[8]\(0),
I1 => \^cb_int_reg[3]_0\(3),
O => \cb_int[7]_i_79_n_0\
);
\cb_int[7]_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \cb_int[7]_i_10_n_0\,
I1 => \cb_int[7]_i_11_n_0\,
I2 => cb_int_reg2(5),
I3 => \cb_int[7]_i_4_n_0\,
O => \cb_int[7]_i_8_n_0\
);
\cb_int[7]_i_80\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \^cb_int_reg[3]_0\(2),
I1 => \^cb_int_reg[3]_0\(1),
O => \cb_int[7]_i_80_n_0\
);
\cb_int[7]_i_81\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \^cb_int_reg[3]_0\(0),
I1 => \^o\(1),
O => \cb_int[7]_i_81_n_0\
);
\cb_int[7]_i_82\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \^o\(0),
I1 => rgb888(8),
O => \cb_int[7]_i_82_n_0\
);
\cb_int[7]_i_9\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \cb_int[7]_i_13_n_0\,
I1 => \cb_int[7]_i_14_n_0\,
I2 => cb_int_reg2(4),
I3 => \cb_int[7]_i_5_n_0\,
O => \cb_int[7]_i_9_n_0\
);
\cb_int_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[3]_i_1_n_7\,
Q => \cb_int_reg_n_0_[0]\,
R => '0'
);
\cb_int_reg[10]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[11]_i_1_n_5\,
Q => \cb_int_reg__0\(10),
R => '0'
);
\cb_int_reg[11]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[11]_i_1_n_4\,
Q => \cb_int_reg__0\(11),
R => '0'
);
\cb_int_reg[11]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[7]_i_1_n_0\,
CO(3) => \cb_int_reg[11]_i_1_n_0\,
CO(2) => \cb_int_reg[11]_i_1_n_1\,
CO(1) => \cb_int_reg[11]_i_1_n_2\,
CO(0) => \cb_int_reg[11]_i_1_n_3\,
CYINIT => '0',
DI(3) => \cb_int[11]_i_2_n_0\,
DI(2) => \cb_int[11]_i_3_n_0\,
DI(1) => \cb_int[11]_i_4_n_0\,
DI(0) => \cb_int[11]_i_5_n_0\,
O(3) => \cb_int_reg[11]_i_1_n_4\,
O(2) => \cb_int_reg[11]_i_1_n_5\,
O(1) => \cb_int_reg[11]_i_1_n_6\,
O(0) => \cb_int_reg[11]_i_1_n_7\,
S(3) => \cb_int[11]_i_6_n_0\,
S(2) => \cb_int[11]_i_7_n_0\,
S(1) => \cb_int[11]_i_8_n_0\,
S(0) => \cb_int[11]_i_9_n_0\
);
\cb_int_reg[11]_i_16\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[11]_i_28_n_0\,
CO(3) => \cb_int_reg[11]_i_16_n_0\,
CO(2) => \cb_int_reg[11]_i_16_n_1\,
CO(1) => \cb_int_reg[11]_i_16_n_2\,
CO(0) => \cb_int_reg[11]_i_16_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => cb_int_reg5(8 downto 5),
S(3) => \cb_int[11]_i_29_n_0\,
S(2) => \cb_int[11]_i_30_n_0\,
S(1) => \cb_int[11]_i_31_n_0\,
S(0) => \cb_int[11]_i_32_n_0\
);
\cb_int_reg[11]_i_17\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[11]_i_33_n_0\,
CO(3) => \cb_int_reg[11]_i_17_n_0\,
CO(2) => \cb_int_reg[11]_i_17_n_1\,
CO(1) => \cb_int_reg[11]_i_17_n_2\,
CO(0) => \cb_int_reg[11]_i_17_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => cb_int_reg7(18 downto 15),
S(3) => \cb_int[11]_i_34_n_0\,
S(2) => \cb_int[11]_i_35_n_0\,
S(1) => \cb_int[11]_i_36_n_0\,
S(0) => \cb_int[11]_i_37_n_0\
);
\cb_int_reg[11]_i_18\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[11]_i_38_n_0\,
CO(3) => \NLW_cb_int_reg[11]_i_18_CO_UNCONNECTED\(3),
CO(2) => cb_int_reg8,
CO(1) => \cb_int_reg[11]_i_18_n_2\,
CO(0) => \cb_int_reg[11]_i_18_n_3\,
CYINIT => '0',
DI(3 downto 2) => B"00",
DI(1) => \cb_int[11]_i_39_n_0\,
DI(0) => \cb_int[11]_i_40_n_0\,
O(3 downto 0) => \NLW_cb_int_reg[11]_i_18_O_UNCONNECTED\(3 downto 0),
S(3) => '0',
S(2) => \cb_int[11]_i_41_n_0\,
S(1) => \cb_int[11]_i_42_n_0\,
S(0) => \cb_int[11]_i_43_n_0\
);
\cb_int_reg[11]_i_24\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[7]_i_29_n_0\,
CO(3) => \cb_int_reg[15]_0\(0),
CO(2) => \cb_int_reg[11]_i_24_n_1\,
CO(1) => \cb_int_reg[11]_i_24_n_2\,
CO(0) => \cb_int_reg[11]_i_24_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cb_int_reg[11]_i_24_n_4\,
O(2) => \cb_int_reg[11]_i_24_n_5\,
O(1) => \cb_int_reg[11]_i_24_n_6\,
O(0) => \cb_int_reg[11]_i_24_n_7\,
S(3) => \cb_int[11]_i_44_n_0\,
S(2) => \cb_int[11]_i_45_n_0\,
S(1) => \cb_int[11]_i_46_n_0\,
S(0) => \cb_int[11]_i_47_n_0\
);
\cb_int_reg[11]_i_25\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[11]_i_48_n_0\,
CO(3) => \cb_int_reg[11]_i_25_n_0\,
CO(2) => \cb_int_reg[11]_i_25_n_1\,
CO(1) => \cb_int_reg[11]_i_25_n_2\,
CO(0) => \cb_int_reg[11]_i_25_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \rgb888[0]\(3),
DI(1) => \rgb888[0]\(3),
DI(0) => \rgb888[0]\(3),
O(3 downto 0) => \NLW_cb_int_reg[11]_i_25_O_UNCONNECTED\(3 downto 0),
S(3) => \cb_int[11]_i_49_n_0\,
S(2) => \cb_int[11]_i_50_n_0\,
S(1) => \cb_int[11]_i_51_n_0\,
S(0) => \cb_int[11]_i_52_n_0\
);
\cb_int_reg[11]_i_26\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[7]_i_28_n_0\,
CO(3) => \cb_int_reg[11]_i_26_n_0\,
CO(2) => \cb_int_reg[11]_i_26_n_1\,
CO(1) => \cb_int_reg[11]_i_26_n_2\,
CO(0) => \cb_int_reg[11]_i_26_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => cb_int_reg3(8 downto 5),
S(3) => \cb_int[11]_i_53_n_0\,
S(2) => \cb_int[11]_i_54_n_0\,
S(1) => \cb_int[11]_i_55_n_0\,
S(0) => \cb_int[11]_i_56_n_0\
);
\cb_int_reg[11]_i_28\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cb_int_reg[11]_i_28_n_0\,
CO(2) => \cb_int_reg[11]_i_28_n_1\,
CO(1) => \cb_int_reg[11]_i_28_n_2\,
CO(0) => \cb_int_reg[11]_i_28_n_3\,
CYINIT => \cb_int[11]_i_57_n_0\,
DI(3 downto 0) => B"0000",
O(3 downto 0) => cb_int_reg5(4 downto 1),
S(3) => \cb_int[11]_i_58_n_0\,
S(2) => \cb_int[11]_i_59_n_0\,
S(1) => \cb_int[11]_i_60_n_0\,
S(0) => \cb_int[11]_i_61_n_0\
);
\cb_int_reg[11]_i_33\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[3]_i_15_n_0\,
CO(3) => \cb_int_reg[11]_i_33_n_0\,
CO(2) => \cb_int_reg[11]_i_33_n_1\,
CO(1) => \cb_int_reg[11]_i_33_n_2\,
CO(0) => \cb_int_reg[11]_i_33_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => cb_int_reg7(14 downto 11),
S(3) => \cb_int[11]_i_62_n_0\,
S(2) => \cb_int[11]_i_63_n_0\,
S(1) => \cb_int[11]_i_64_n_0\,
S(0) => \cb_int[11]_i_65_n_0\
);
\cb_int_reg[11]_i_38\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[11]_i_66_n_0\,
CO(3) => \cb_int_reg[11]_i_38_n_0\,
CO(2) => \cb_int_reg[11]_i_38_n_1\,
CO(1) => \cb_int_reg[11]_i_38_n_2\,
CO(0) => \cb_int_reg[11]_i_38_n_3\,
CYINIT => '0',
DI(3) => \cb_int[11]_i_67_n_0\,
DI(2) => \cb_int[11]_i_68_n_0\,
DI(1) => \cb_int[11]_i_69_n_0\,
DI(0) => \cb_int[11]_i_70_n_0\,
O(3 downto 0) => \NLW_cb_int_reg[11]_i_38_O_UNCONNECTED\(3 downto 0),
S(3) => \cb_int[11]_i_71_n_0\,
S(2) => \cb_int[11]_i_72_n_0\,
S(1) => \cb_int[11]_i_73_n_0\,
S(0) => \cb_int[11]_i_74_n_0\
);
\cb_int_reg[11]_i_48\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[11]_i_75_n_0\,
CO(3) => \cb_int_reg[11]_i_48_n_0\,
CO(2) => \cb_int_reg[11]_i_48_n_1\,
CO(1) => \cb_int_reg[11]_i_48_n_2\,
CO(0) => \cb_int_reg[11]_i_48_n_3\,
CYINIT => '0',
DI(3) => \rgb888[0]\(3),
DI(2) => \rgb888[0]\(3),
DI(1) => \rgb888[0]\(3),
DI(0) => \cb_int[11]_i_76_n_0\,
O(3 downto 0) => \NLW_cb_int_reg[11]_i_48_O_UNCONNECTED\(3 downto 0),
S(3) => \cb_int[11]_i_77_n_0\,
S(2) => \cb_int[11]_i_78_n_0\,
S(1) => \cb_int[11]_i_79_n_0\,
S(0) => \cb_int[11]_i_80_n_0\
);
\cb_int_reg[11]_i_66\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[11]_i_81_n_0\,
CO(3) => \cb_int_reg[11]_i_66_n_0\,
CO(2) => \cb_int_reg[11]_i_66_n_1\,
CO(1) => \cb_int_reg[11]_i_66_n_2\,
CO(0) => \cb_int_reg[11]_i_66_n_3\,
CYINIT => '0',
DI(3) => \cb_int[11]_i_82_n_0\,
DI(2) => \cb_int[11]_i_83_n_0\,
DI(1) => \cb_int[11]_i_84_n_0\,
DI(0) => \cb_int[11]_i_85_n_0\,
O(3 downto 0) => \NLW_cb_int_reg[11]_i_66_O_UNCONNECTED\(3 downto 0),
S(3) => \cb_int[11]_i_86_n_0\,
S(2) => \cb_int[11]_i_87_n_0\,
S(1) => \cb_int[11]_i_88_n_0\,
S(0) => \cb_int[11]_i_89_n_0\
);
\cb_int_reg[11]_i_75\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[11]_i_90_n_0\,
CO(3) => \cb_int_reg[11]_i_75_n_0\,
CO(2) => \cb_int_reg[11]_i_75_n_1\,
CO(1) => \cb_int_reg[11]_i_75_n_2\,
CO(0) => \cb_int_reg[11]_i_75_n_3\,
CYINIT => '0',
DI(3) => \cb_int[11]_i_91_n_0\,
DI(2) => \cb_int[11]_i_92_n_0\,
DI(1) => \cb_int[11]_i_93_n_0\,
DI(0) => \cb_int[11]_i_94_n_0\,
O(3 downto 0) => \NLW_cb_int_reg[11]_i_75_O_UNCONNECTED\(3 downto 0),
S(3) => \cb_int[11]_i_95_n_0\,
S(2) => \cb_int[11]_i_96_n_0\,
S(1) => \cb_int[11]_i_97_n_0\,
S(0) => \cb_int[11]_i_98_n_0\
);
\cb_int_reg[11]_i_81\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cb_int_reg[11]_i_81_n_0\,
CO(2) => \cb_int_reg[11]_i_81_n_1\,
CO(1) => \cb_int_reg[11]_i_81_n_2\,
CO(0) => \cb_int_reg[11]_i_81_n_3\,
CYINIT => '1',
DI(3) => \cb_int[11]_i_99_n_0\,
DI(2) => \cb_int[11]_i_100_n_0\,
DI(1) => \cb_int[11]_i_101_n_0\,
DI(0) => \cb_int[11]_i_102_n_0\,
O(3 downto 0) => \NLW_cb_int_reg[11]_i_81_O_UNCONNECTED\(3 downto 0),
S(3) => \cb_int[11]_i_103_n_0\,
S(2) => \cb_int[11]_i_104_n_0\,
S(1) => \cb_int[11]_i_105_n_0\,
S(0) => \cb_int[11]_i_106_n_0\
);
\cb_int_reg[11]_i_90\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cb_int_reg[11]_i_90_n_0\,
CO(2) => \cb_int_reg[11]_i_90_n_1\,
CO(1) => \cb_int_reg[11]_i_90_n_2\,
CO(0) => \cb_int_reg[11]_i_90_n_3\,
CYINIT => '1',
DI(3) => \cb_int[11]_i_107_n_0\,
DI(2) => \cb_int[11]_i_108_n_0\,
DI(1) => \cb_int[11]_i_109_n_0\,
DI(0) => \cb_int[11]_i_110_n_0\,
O(3 downto 0) => \NLW_cb_int_reg[11]_i_90_O_UNCONNECTED\(3 downto 0),
S(3) => \cb_int[11]_i_111_n_0\,
S(2) => \cb_int[11]_i_112_n_0\,
S(1) => \cb_int[11]_i_113_n_0\,
S(0) => \cb_int[11]_i_114_n_0\
);
\cb_int_reg[12]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[15]_i_1_n_7\,
Q => \cb_int_reg__0\(12),
R => '0'
);
\cb_int_reg[13]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[15]_i_1_n_6\,
Q => \cb_int_reg__0\(13),
R => '0'
);
\cb_int_reg[14]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[15]_i_1_n_5\,
Q => \cb_int_reg__0\(14),
R => '0'
);
\cb_int_reg[15]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[15]_i_1_n_4\,
Q => \cb_int_reg__0\(15),
R => '0'
);
\cb_int_reg[15]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[11]_i_1_n_0\,
CO(3) => \cb_int_reg[15]_i_1_n_0\,
CO(2) => \cb_int_reg[15]_i_1_n_1\,
CO(1) => \cb_int_reg[15]_i_1_n_2\,
CO(0) => \cb_int_reg[15]_i_1_n_3\,
CYINIT => '0',
DI(3) => \cb_int[15]_i_2_n_0\,
DI(2) => \cb_int[15]_i_3_n_0\,
DI(1) => \cb_int[15]_i_4_n_0\,
DI(0) => \cb_int[15]_i_5_n_0\,
O(3) => \cb_int_reg[15]_i_1_n_4\,
O(2) => \cb_int_reg[15]_i_1_n_5\,
O(1) => \cb_int_reg[15]_i_1_n_6\,
O(0) => \cb_int_reg[15]_i_1_n_7\,
S(3) => \cb_int[15]_i_6_n_0\,
S(2) => \cb_int[15]_i_7_n_0\,
S(1) => \cb_int[15]_i_8_n_0\,
S(0) => \cb_int[15]_i_9_n_0\
);
\cb_int_reg[15]_i_20\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[11]_i_16_n_0\,
CO(3) => \cb_int_reg[15]_i_20_n_0\,
CO(2) => \cb_int_reg[15]_i_20_n_1\,
CO(1) => \cb_int_reg[15]_i_20_n_2\,
CO(0) => \cb_int_reg[15]_i_20_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => cb_int_reg5(12 downto 9),
S(3) => \cb_int[15]_i_27_n_0\,
S(2) => \cb_int[15]_i_28_n_0\,
S(1) => \cb_int[15]_i_29_n_0\,
S(0) => \cb_int[15]_i_30_n_0\
);
\cb_int_reg[15]_i_33\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[11]_i_26_n_0\,
CO(3) => \cb_int_reg[15]_i_33_n_0\,
CO(2) => \cb_int_reg[15]_i_33_n_1\,
CO(1) => \cb_int_reg[15]_i_33_n_2\,
CO(0) => \cb_int_reg[15]_i_33_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => cb_int_reg3(12 downto 9),
S(3) => \cb_int[15]_i_43_n_0\,
S(2) => \cb_int[15]_i_44_n_0\,
S(1) => \cb_int[15]_i_45_n_0\,
S(0) => \cb_int[15]_i_46_n_0\
);
\cb_int_reg[16]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[19]_i_1_n_7\,
Q => \cb_int_reg__0\(16),
R => '0'
);
\cb_int_reg[17]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[19]_i_1_n_6\,
Q => \cb_int_reg__0\(17),
R => '0'
);
\cb_int_reg[18]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[19]_i_1_n_5\,
Q => \cb_int_reg__0\(18),
R => '0'
);
\cb_int_reg[19]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[19]_i_1_n_4\,
Q => \cb_int_reg__0\(19),
R => '0'
);
\cb_int_reg[19]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[15]_i_1_n_0\,
CO(3) => \cb_int_reg[19]_i_1_n_0\,
CO(2) => \cb_int_reg[19]_i_1_n_1\,
CO(1) => \cb_int_reg[19]_i_1_n_2\,
CO(0) => \cb_int_reg[19]_i_1_n_3\,
CYINIT => '0',
DI(3) => \cb_int[19]_i_2_n_0\,
DI(2) => \cb_int[19]_i_3_n_0\,
DI(1) => \cb_int[19]_i_4_n_0\,
DI(0) => \cb_int[19]_i_5_n_0\,
O(3) => \cb_int_reg[19]_i_1_n_4\,
O(2) => \cb_int_reg[19]_i_1_n_5\,
O(1) => \cb_int_reg[19]_i_1_n_6\,
O(0) => \cb_int_reg[19]_i_1_n_7\,
S(3) => \cb_int[19]_i_6_n_0\,
S(2) => \cb_int[19]_i_7_n_0\,
S(1) => \cb_int[19]_i_8_n_0\,
S(0) => \cb_int[19]_i_9_n_0\
);
\cb_int_reg[19]_i_20\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[15]_i_20_n_0\,
CO(3) => \cb_int_reg[19]_i_20_n_0\,
CO(2) => \cb_int_reg[19]_i_20_n_1\,
CO(1) => \cb_int_reg[19]_i_20_n_2\,
CO(0) => \cb_int_reg[19]_i_20_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => cb_int_reg5(16 downto 13),
S(3) => \cb_int[19]_i_28_n_0\,
S(2) => \cb_int[19]_i_29_n_0\,
S(1) => \cb_int[19]_i_30_n_0\,
S(0) => \cb_int[19]_i_31_n_0\
);
\cb_int_reg[19]_i_25\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[11]_i_17_n_0\,
CO(3) => \cb_int_reg[19]_i_25_n_0\,
CO(2) => \cb_int_reg[19]_i_25_n_1\,
CO(1) => \cb_int_reg[19]_i_25_n_2\,
CO(0) => \cb_int_reg[19]_i_25_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => cb_int_reg7(22 downto 19),
S(3) => \cb_int[19]_i_34_n_0\,
S(2) => \cb_int[19]_i_35_n_0\,
S(1) => \cb_int[19]_i_36_n_0\,
S(0) => \cb_int[19]_i_37_n_0\
);
\cb_int_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[3]_i_1_n_6\,
Q => \cb_int_reg_n_0_[1]\,
R => '0'
);
\cb_int_reg[20]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[23]_i_1_n_7\,
Q => \cb_int_reg__0\(20),
R => '0'
);
\cb_int_reg[21]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[23]_i_1_n_6\,
Q => \cb_int_reg__0\(21),
R => '0'
);
\cb_int_reg[22]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[23]_i_1_n_5\,
Q => \cb_int_reg__0\(22),
R => '0'
);
\cb_int_reg[23]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[23]_i_1_n_4\,
Q => \cb_int_reg__0\(23),
R => '0'
);
\cb_int_reg[23]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[19]_i_1_n_0\,
CO(3) => \cb_int_reg[23]_i_1_n_0\,
CO(2) => \cb_int_reg[23]_i_1_n_1\,
CO(1) => \cb_int_reg[23]_i_1_n_2\,
CO(0) => \cb_int_reg[23]_i_1_n_3\,
CYINIT => '0',
DI(3) => \cb_int[23]_i_2_n_0\,
DI(2) => \cb_int[23]_i_3_n_0\,
DI(1) => \cb_int[23]_i_4_n_0\,
DI(0) => \cb_int[23]_i_5_n_0\,
O(3) => \cb_int_reg[23]_i_1_n_4\,
O(2) => \cb_int_reg[23]_i_1_n_5\,
O(1) => \cb_int_reg[23]_i_1_n_6\,
O(0) => \cb_int_reg[23]_i_1_n_7\,
S(3) => \cb_int[23]_i_6_n_0\,
S(2) => \cb_int[23]_i_7_n_0\,
S(1) => \cb_int[23]_i_8_n_0\,
S(0) => \cb_int[23]_i_9_n_0\
);
\cb_int_reg[23]_i_24\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[19]_i_25_n_0\,
CO(3) => \cb_int_reg[23]_i_24_n_0\,
CO(2) => \cb_int_reg[23]_i_24_n_1\,
CO(1) => \cb_int_reg[23]_i_24_n_2\,
CO(0) => \cb_int_reg[23]_i_24_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => cb_int_reg7(26 downto 23),
S(3) => \cb_int[23]_i_29_n_0\,
S(2) => \cb_int[23]_i_30_n_0\,
S(1) => \cb_int[23]_i_31_n_0\,
S(0) => \cb_int[23]_i_32_n_0\
);
\cb_int_reg[24]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[27]_i_1_n_7\,
Q => \cb_int_reg__0\(24),
R => '0'
);
\cb_int_reg[25]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[27]_i_1_n_6\,
Q => \cb_int_reg__0\(25),
R => '0'
);
\cb_int_reg[26]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[27]_i_1_n_5\,
Q => \cb_int_reg__0\(26),
R => '0'
);
\cb_int_reg[27]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[27]_i_1_n_4\,
Q => \cb_int_reg__0\(27),
R => '0'
);
\cb_int_reg[27]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[23]_i_1_n_0\,
CO(3) => \cb_int_reg[27]_i_1_n_0\,
CO(2) => \cb_int_reg[27]_i_1_n_1\,
CO(1) => \cb_int_reg[27]_i_1_n_2\,
CO(0) => \cb_int_reg[27]_i_1_n_3\,
CYINIT => '0',
DI(3) => \cb_int[31]_i_2_n_0\,
DI(2) => \cb_int[31]_i_2_n_0\,
DI(1) => \cb_int[31]_i_2_n_0\,
DI(0) => \cb_int[27]_i_2_n_0\,
O(3) => \cb_int_reg[27]_i_1_n_4\,
O(2) => \cb_int_reg[27]_i_1_n_5\,
O(1) => \cb_int_reg[27]_i_1_n_6\,
O(0) => \cb_int_reg[27]_i_1_n_7\,
S(3) => \cb_int[27]_i_3_n_0\,
S(2) => \cb_int[27]_i_4_n_0\,
S(1) => \cb_int[27]_i_5_n_0\,
S(0) => \cb_int[27]_i_6_n_0\
);
\cb_int_reg[27]_i_9\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[23]_i_24_n_0\,
CO(3) => \NLW_cb_int_reg[27]_i_9_CO_UNCONNECTED\(3),
CO(2) => \cb_int_reg[27]_i_9_n_1\,
CO(1) => \cb_int_reg[27]_i_9_n_2\,
CO(0) => \cb_int_reg[27]_i_9_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => cb_int_reg7(30 downto 27),
S(3) => \cb_int[27]_i_12_n_0\,
S(2) => \cb_int[27]_i_13_n_0\,
S(1) => \cb_int[27]_i_14_n_0\,
S(0) => \cb_int[27]_i_15_n_0\
);
\cb_int_reg[28]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[31]_i_1_n_7\,
Q => \cb_int_reg__0\(28),
R => '0'
);
\cb_int_reg[29]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[31]_i_1_n_6\,
Q => \cb_int_reg__0\(29),
R => '0'
);
\cb_int_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[3]_i_1_n_5\,
Q => \cb_int_reg_n_0_[2]\,
R => '0'
);
\cb_int_reg[30]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[31]_i_1_n_5\,
Q => \cb_int_reg__0\(30),
R => '0'
);
\cb_int_reg[31]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[31]_i_1_n_4\,
Q => \cb_int_reg__0\(31),
R => '0'
);
\cb_int_reg[31]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[27]_i_1_n_0\,
CO(3) => \NLW_cb_int_reg[31]_i_1_CO_UNCONNECTED\(3),
CO(2) => \cb_int_reg[31]_i_1_n_1\,
CO(1) => \cb_int_reg[31]_i_1_n_2\,
CO(0) => \cb_int_reg[31]_i_1_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \cb_int[31]_i_2_n_0\,
DI(1) => \cb_int[31]_i_2_n_0\,
DI(0) => \cb_int[31]_i_2_n_0\,
O(3) => \cb_int_reg[31]_i_1_n_4\,
O(2) => \cb_int_reg[31]_i_1_n_5\,
O(1) => \cb_int_reg[31]_i_1_n_6\,
O(0) => \cb_int_reg[31]_i_1_n_7\,
S(3) => \cb_int[31]_i_3_n_0\,
S(2) => \cb_int[31]_i_4_n_0\,
S(1) => \cb_int[31]_i_5_n_0\,
S(0) => \cb_int[31]_i_6_n_0\
);
\cb_int_reg[31]_i_11\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[31]_i_30_n_0\,
CO(3) => \NLW_cb_int_reg[31]_i_11_CO_UNCONNECTED\(3),
CO(2) => \cb_int_reg[31]_i_11_n_1\,
CO(1) => \NLW_cb_int_reg[31]_i_11_CO_UNCONNECTED\(1),
CO(0) => \cb_int_reg[31]_i_11_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 2) => \NLW_cb_int_reg[31]_i_11_O_UNCONNECTED\(3 downto 2),
O(1 downto 0) => cb_int_reg5(22 downto 21),
S(3 downto 2) => B"01",
S(1) => \cb_int[31]_i_31_n_0\,
S(0) => \cb_int[31]_i_32_n_0\
);
\cb_int_reg[31]_i_12\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[31]_i_33_n_0\,
CO(3) => \NLW_cb_int_reg[31]_i_12_CO_UNCONNECTED\(3),
CO(2) => \cb_int_reg[31]_i_12_n_1\,
CO(1) => \NLW_cb_int_reg[31]_i_12_CO_UNCONNECTED\(1),
CO(0) => \cb_int_reg[31]_i_12_n_3\,
CYINIT => '0',
DI(3 downto 2) => B"00",
DI(1) => \cb_int_reg[31]_i_34_n_2\,
DI(0) => '0',
O(3 downto 2) => \NLW_cb_int_reg[31]_i_12_O_UNCONNECTED\(3 downto 2),
O(1) => \cb_int_reg[31]_i_12_n_6\,
O(0) => \cb_int_reg[31]_i_12_n_7\,
S(3 downto 2) => B"01",
S(1) => \cb_int[31]_i_35_n_0\,
S(0) => \cb_int[31]_i_36_n_0\
);
\cb_int_reg[31]_i_14\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[31]_i_37_n_0\,
CO(3) => \cb_int_reg[31]_i_14_n_0\,
CO(2) => \cb_int_reg[31]_i_14_n_1\,
CO(1) => \cb_int_reg[31]_i_14_n_2\,
CO(0) => \cb_int_reg[31]_i_14_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => cb_int_reg3(20 downto 17),
S(3) => \cb_int[31]_i_38_n_0\,
S(2) => \cb_int[31]_i_39_n_0\,
S(1) => \cb_int[31]_i_40_n_0\,
S(0) => \cb_int[31]_i_41_n_0\
);
\cb_int_reg[31]_i_30\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[19]_i_20_n_0\,
CO(3) => \cb_int_reg[31]_i_30_n_0\,
CO(2) => \cb_int_reg[31]_i_30_n_1\,
CO(1) => \cb_int_reg[31]_i_30_n_2\,
CO(0) => \cb_int_reg[31]_i_30_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => cb_int_reg5(20 downto 17),
S(3) => \cb_int[31]_i_67_n_0\,
S(2) => \cb_int[31]_i_68_n_0\,
S(1) => \cb_int[31]_i_69_n_0\,
S(0) => \cb_int[31]_i_70_n_0\
);
\cb_int_reg[31]_i_33\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[3]_i_16_n_0\,
CO(3) => \cb_int_reg[31]_i_33_n_0\,
CO(2) => \cb_int_reg[31]_i_33_n_1\,
CO(1) => \cb_int_reg[31]_i_33_n_2\,
CO(0) => \cb_int_reg[31]_i_33_n_3\,
CYINIT => '0',
DI(3) => \cb_int_reg[31]_i_34_n_7\,
DI(2) => \cb_int[31]_i_71_n_0\,
DI(1) => \cb_int[31]_i_72_n_0\,
DI(0) => \cb_int_reg[31]_i_73_n_7\,
O(3) => \cb_int_reg[31]_i_33_n_4\,
O(2) => \cb_int_reg[31]_i_33_n_5\,
O(1) => \cb_int_reg[31]_i_33_n_6\,
O(0) => \cb_int_reg[31]_i_33_n_7\,
S(3) => \cb_int[31]_i_74_n_0\,
S(2) => \cb_int[31]_i_75_n_0\,
S(1) => \cb_int[31]_i_76_n_0\,
S(0) => \cb_int[31]_i_77_n_0\
);
\cb_int_reg[31]_i_34\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[31]_i_73_n_0\,
CO(3 downto 2) => \NLW_cb_int_reg[31]_i_34_CO_UNCONNECTED\(3 downto 2),
CO(1) => \cb_int_reg[31]_i_34_n_2\,
CO(0) => \NLW_cb_int_reg[31]_i_34_CO_UNCONNECTED\(0),
CYINIT => '0',
DI(3 downto 1) => B"000",
DI(0) => rgb888(23),
O(3 downto 1) => \NLW_cb_int_reg[31]_i_34_O_UNCONNECTED\(3 downto 1),
O(0) => \cb_int_reg[31]_i_34_n_7\,
S(3 downto 1) => B"001",
S(0) => \cb_int[31]_i_78_n_0\
);
\cb_int_reg[31]_i_37\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[15]_i_33_n_0\,
CO(3) => \cb_int_reg[31]_i_37_n_0\,
CO(2) => \cb_int_reg[31]_i_37_n_1\,
CO(1) => \cb_int_reg[31]_i_37_n_2\,
CO(0) => \cb_int_reg[31]_i_37_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => cb_int_reg3(16 downto 13),
S(3) => \cb_int[31]_i_79_n_0\,
S(2) => \cb_int[31]_i_80_n_0\,
S(1) => \cb_int[31]_i_81_n_0\,
S(0) => \cb_int[31]_i_82_n_0\
);
\cb_int_reg[31]_i_7\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[31]_i_14_n_0\,
CO(3) => \NLW_cb_int_reg[31]_i_7_CO_UNCONNECTED\(3),
CO(2) => \cb_int_reg[31]_i_7_n_1\,
CO(1) => \NLW_cb_int_reg[31]_i_7_CO_UNCONNECTED\(1),
CO(0) => \cb_int_reg[31]_i_7_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 2) => \NLW_cb_int_reg[31]_i_7_O_UNCONNECTED\(3 downto 2),
O(1 downto 0) => cb_int_reg3(22 downto 21),
S(3 downto 2) => B"01",
S(1) => \cb_int[31]_i_15_n_0\,
S(0) => \cb_int[31]_i_16_n_0\
);
\cb_int_reg[31]_i_73\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[3]_i_57_n_0\,
CO(3) => \cb_int_reg[31]_i_73_n_0\,
CO(2) => \cb_int_reg[31]_i_73_n_1\,
CO(1) => \cb_int_reg[31]_i_73_n_2\,
CO(0) => \cb_int_reg[31]_i_73_n_3\,
CYINIT => '0',
DI(3) => rgb888(22),
DI(2 downto 0) => rgb888(23 downto 21),
O(3) => \cb_int_reg[31]_i_73_n_4\,
O(2) => \cb_int_reg[31]_i_73_n_5\,
O(1) => \cb_int_reg[31]_i_73_n_6\,
O(0) => \cb_int_reg[31]_i_73_n_7\,
S(3) => \cb_int[31]_i_95_n_0\,
S(2) => \cb_int[31]_i_96_n_0\,
S(1) => \cb_int[31]_i_97_n_0\,
S(0) => \cb_int[31]_i_98_n_0\
);
\cb_int_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[3]_i_1_n_4\,
Q => \cb_int_reg_n_0_[3]\,
R => '0'
);
\cb_int_reg[3]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cb_int_reg[3]_i_1_n_0\,
CO(2) => \cb_int_reg[3]_i_1_n_1\,
CO(1) => \cb_int_reg[3]_i_1_n_2\,
CO(0) => \cb_int_reg[3]_i_1_n_3\,
CYINIT => '1',
DI(3) => \cb_int[3]_i_2_n_0\,
DI(2) => \cb_int[3]_i_3_n_0\,
DI(1) => \cb_int[3]_i_4_n_0\,
DI(0) => '1',
O(3) => \cb_int_reg[3]_i_1_n_4\,
O(2) => \cb_int_reg[3]_i_1_n_5\,
O(1) => \cb_int_reg[3]_i_1_n_6\,
O(0) => \cb_int_reg[3]_i_1_n_7\,
S(3) => \cb_int[3]_i_5_n_0\,
S(2) => \cb_int[3]_i_6_n_0\,
S(1) => \cb_int[3]_i_7_n_0\,
S(0) => \cb_int[3]_i_8_n_0\
);
\cb_int_reg[3]_i_15\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[3]_i_21_n_0\,
CO(3) => \cb_int_reg[3]_i_15_n_0\,
CO(2) => \cb_int_reg[3]_i_15_n_1\,
CO(1) => \cb_int_reg[3]_i_15_n_2\,
CO(0) => \cb_int_reg[3]_i_15_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 1) => cb_int_reg7(10 downto 8),
O(0) => \NLW_cb_int_reg[3]_i_15_O_UNCONNECTED\(0),
S(3) => \cb_int[3]_i_22_n_0\,
S(2) => \cb_int[3]_i_23_n_0\,
S(1) => \cb_int[3]_i_24_n_0\,
S(0) => \cb_int[3]_i_25_n_0\
);
\cb_int_reg[3]_i_16\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[3]_i_26_n_0\,
CO(3) => \cb_int_reg[3]_i_16_n_0\,
CO(2) => \cb_int_reg[3]_i_16_n_1\,
CO(1) => \cb_int_reg[3]_i_16_n_2\,
CO(0) => \cb_int_reg[3]_i_16_n_3\,
CYINIT => '0',
DI(3) => \cb_int[3]_i_27_n_0\,
DI(2 downto 0) => rgb888(21 downto 19),
O(3) => \cb_int_reg[3]_i_16_n_4\,
O(2) => \cb_int_reg[3]_i_16_n_5\,
O(1) => \cb_int_reg[3]_i_16_n_6\,
O(0) => \cb_int_reg[3]_i_16_n_7\,
S(3) => \cb_int[3]_i_28_n_0\,
S(2) => \cb_int[3]_i_29_n_0\,
S(1) => \cb_int[3]_i_30_n_0\,
S(0) => \cb_int[3]_i_31_n_0\
);
\cb_int_reg[3]_i_20\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cb_int_reg[27]_0\(0),
CO(2) => \cb_int_reg[3]_i_20_n_1\,
CO(1) => \cb_int_reg[3]_i_20_n_2\,
CO(0) => \cb_int_reg[3]_i_20_n_3\,
CYINIT => '0',
DI(3 downto 2) => \rgb888[0]_8\(1 downto 0),
DI(1) => \cb_int_reg[3]_i_44_n_4\,
DI(0) => '0',
O(3) => \cb_int_reg[3]_i_20_n_4\,
O(2) => \cb_int_reg[3]_i_20_n_5\,
O(1) => \cb_int_reg[3]_i_20_n_6\,
O(0) => \cb_int_reg[3]_i_20_n_7\,
S(3) => \cb_int[3]_i_45_n_0\,
S(2) => \cb_int[3]_i_46_n_0\,
S(1) => \cb_int[3]_i_47_n_0\,
S(0) => \cb_int[3]_i_48_n_0\
);
\cb_int_reg[3]_i_21\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cb_int_reg[3]_i_21_n_0\,
CO(2) => \cb_int_reg[3]_i_21_n_1\,
CO(1) => \cb_int_reg[3]_i_21_n_2\,
CO(0) => \cb_int_reg[3]_i_21_n_3\,
CYINIT => \cb_int[3]_i_49_n_0\,
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_cb_int_reg[3]_i_21_O_UNCONNECTED\(3 downto 0),
S(3) => \cb_int[3]_i_50_n_0\,
S(2) => \cb_int[3]_i_51_n_0\,
S(1) => \cb_int[3]_i_52_n_0\,
S(0) => \cb_int[3]_i_53_n_0\
);
\cb_int_reg[3]_i_26\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cb_int_reg[3]_i_26_n_0\,
CO(2) => \cb_int_reg[3]_i_26_n_1\,
CO(1) => \cb_int_reg[3]_i_26_n_2\,
CO(0) => \cb_int_reg[3]_i_26_n_3\,
CYINIT => '0',
DI(3 downto 1) => rgb888(18 downto 16),
DI(0) => '0',
O(3) => \cb_int_reg[3]_i_26_n_4\,
O(2) => \cb_int_reg[3]_i_26_n_5\,
O(1) => \cb_int_reg[3]_i_26_n_6\,
O(0) => \NLW_cb_int_reg[3]_i_26_O_UNCONNECTED\(0),
S(3) => \cb_int[3]_i_54_n_0\,
S(2) => \cb_int[3]_i_55_n_0\,
S(1) => \cb_int[3]_i_56_n_0\,
S(0) => '0'
);
\cb_int_reg[3]_i_33\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[3]_i_63_n_0\,
CO(3) => \cb_int_reg[3]_i_33_n_0\,
CO(2) => \cb_int_reg[3]_i_33_n_1\,
CO(1) => \cb_int_reg[3]_i_33_n_2\,
CO(0) => \cb_int_reg[3]_i_33_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cb_int_reg[3]_i_33_n_4\,
O(2 downto 0) => \NLW_cb_int_reg[3]_i_33_O_UNCONNECTED\(2 downto 0),
S(3) => \cb_int[3]_i_64_n_0\,
S(2) => \cb_int[3]_i_65_n_0\,
S(1) => \cb_int[3]_i_66_n_0\,
S(0) => \cb_int[3]_i_67_n_0\
);
\cb_int_reg[3]_i_34\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cb_int_reg[3]_2\(0),
CO(2) => \cb_int_reg[3]_i_34_n_1\,
CO(1) => \cb_int_reg[3]_i_34_n_2\,
CO(0) => \cb_int_reg[3]_i_34_n_3\,
CYINIT => '0',
DI(3 downto 1) => \rgb888[8]_31\(2 downto 0),
DI(0) => '0',
O(3 downto 0) => \^cb_int_reg[3]_0\(3 downto 0),
S(3) => \cb_int[3]_i_69_n_0\,
S(2) => \cb_int[3]_i_70_n_0\,
S(1) => \cb_int[3]_i_71_n_0\,
S(0) => \cb_int[3]_i_72_n_0\
);
\cb_int_reg[3]_i_44\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[3]_i_75_n_0\,
CO(3) => \cb_int_reg[3]_3\(0),
CO(2) => \cb_int_reg[3]_i_44_n_1\,
CO(1) => \cb_int_reg[3]_i_44_n_2\,
CO(0) => \cb_int_reg[3]_i_44_n_3\,
CYINIT => '0',
DI(3 downto 0) => rgb888(5 downto 2),
O(3) => \cb_int_reg[3]_i_44_n_4\,
O(2) => \cb_int_reg[3]_i_44_n_5\,
O(1) => \cb_int_reg[3]_i_44_n_6\,
O(0) => \cb_int_reg[3]_i_44_n_7\,
S(3) => \cb_int[3]_i_76_n_0\,
S(2) => \cb_int[3]_i_77_n_0\,
S(1) => \cb_int[3]_i_78_n_0\,
S(0) => \cb_int[3]_i_79_n_0\
);
\cb_int_reg[3]_i_57\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cb_int_reg[3]_i_57_n_0\,
CO(2) => \cb_int_reg[3]_i_57_n_1\,
CO(1) => \cb_int_reg[3]_i_57_n_2\,
CO(0) => \cb_int_reg[3]_i_57_n_3\,
CYINIT => '0',
DI(3 downto 1) => rgb888(20 downto 18),
DI(0) => '0',
O(3) => \cb_int_reg[3]_i_57_n_4\,
O(2) => \cb_int_reg[3]_i_57_n_5\,
O(1) => \cb_int_reg[3]_i_57_n_6\,
O(0) => \cb_int_reg[3]_i_57_n_7\,
S(3) => \cb_int[3]_i_80_n_0\,
S(2) => \cb_int[3]_i_81_n_0\,
S(1) => \cb_int[3]_i_82_n_0\,
S(0) => \cb_int[3]_i_83_n_0\
);
\cb_int_reg[3]_i_63\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cb_int_reg[3]_i_63_n_0\,
CO(2) => \cb_int_reg[3]_i_63_n_1\,
CO(1) => \cb_int_reg[3]_i_63_n_2\,
CO(0) => \cb_int_reg[3]_i_63_n_3\,
CYINIT => \cb_int[3]_i_89_n_0\,
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_cb_int_reg[3]_i_63_O_UNCONNECTED\(3 downto 0),
S(3) => \cb_int[3]_i_90_n_0\,
S(2) => \cb_int[3]_i_91_n_0\,
S(1) => \cb_int[3]_i_92_n_0\,
S(0) => \cb_int[3]_i_93_n_0\
);
\cb_int_reg[3]_i_75\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cb_int_reg[3]_i_75_n_0\,
CO(2) => \cb_int_reg[3]_i_75_n_1\,
CO(1) => \cb_int_reg[3]_i_75_n_2\,
CO(0) => \cb_int_reg[3]_i_75_n_3\,
CYINIT => '0',
DI(3 downto 2) => rgb888(1 downto 0),
DI(1 downto 0) => B"01",
O(3) => \cb_int_reg[3]_i_75_n_4\,
O(2) => \cb_int_reg[3]_i_75_n_5\,
O(1) => \cb_int_reg[3]_i_75_n_6\,
O(0) => \cb_int_reg[3]_i_75_n_7\,
S(3) => \cb_int[3]_i_99_n_0\,
S(2) => \cb_int[3]_i_100_n_0\,
S(1) => \cb_int[3]_i_101_n_0\,
S(0) => \cb_int[3]_i_102_n_0\
);
\cb_int_reg[3]_i_94\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cb_int_reg[3]_1\(0),
CO(2) => \cb_int_reg[3]_i_94_n_1\,
CO(1) => \cb_int_reg[3]_i_94_n_2\,
CO(0) => \cb_int_reg[3]_i_94_n_3\,
CYINIT => '0',
DI(3) => rgb888(8),
DI(2 downto 0) => B"001",
O(3) => \cb_int_reg[3]_i_94_n_4\,
O(2 downto 1) => \^o\(1 downto 0),
O(0) => \cb_int_reg[3]_i_94_n_7\,
S(3) => \cb_int[3]_i_103_n_0\,
S(2) => \cb_int[3]_i_104_n_0\,
S(1) => \cb_int[3]_i_105_n_0\,
S(0) => \cb_int[3]_i_106_n_0\
);
\cb_int_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[7]_i_1_n_7\,
Q => \cb_int_reg_n_0_[4]\,
R => '0'
);
\cb_int_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[7]_i_1_n_6\,
Q => \cb_int_reg_n_0_[5]\,
R => '0'
);
\cb_int_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[7]_i_1_n_5\,
Q => \cb_int_reg_n_0_[6]\,
R => '0'
);
\cb_int_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[7]_i_1_n_4\,
Q => \cb_int_reg_n_0_[7]\,
R => '0'
);
\cb_int_reg[7]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[3]_i_1_n_0\,
CO(3) => \cb_int_reg[7]_i_1_n_0\,
CO(2) => \cb_int_reg[7]_i_1_n_1\,
CO(1) => \cb_int_reg[7]_i_1_n_2\,
CO(0) => \cb_int_reg[7]_i_1_n_3\,
CYINIT => '0',
DI(3) => \cb_int[7]_i_2_n_0\,
DI(2) => \cb_int[7]_i_3_n_0\,
DI(1) => \cb_int[7]_i_4_n_0\,
DI(0) => \cb_int[7]_i_5_n_0\,
O(3) => \cb_int_reg[7]_i_1_n_4\,
O(2) => \cb_int_reg[7]_i_1_n_5\,
O(1) => \cb_int_reg[7]_i_1_n_6\,
O(0) => \cb_int_reg[7]_i_1_n_7\,
S(3) => \cb_int[7]_i_6_n_0\,
S(2) => \cb_int[7]_i_7_n_0\,
S(1) => \cb_int[7]_i_8_n_0\,
S(0) => \cb_int[7]_i_9_n_0\
);
\cb_int_reg[7]_i_25\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[7]_i_38_n_0\,
CO(3) => \^co\(0),
CO(2) => \cb_int_reg[7]_i_25_n_1\,
CO(1) => \cb_int_reg[7]_i_25_n_2\,
CO(0) => \cb_int_reg[7]_i_25_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \rgb888[8]_1\(1),
DI(1) => \rgb888[8]_1\(1),
DI(0) => \rgb888[8]_1\(1),
O(3 downto 0) => \NLW_cb_int_reg[7]_i_25_O_UNCONNECTED\(3 downto 0),
S(3) => \cb_int[7]_i_39_n_0\,
S(2) => \cb_int[7]_i_40_n_0\,
S(1) => \cb_int[7]_i_41_n_0\,
S(0) => \cb_int[7]_i_42_n_0\
);
\cb_int_reg[7]_i_28\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cb_int_reg[7]_i_28_n_0\,
CO(2) => \cb_int_reg[7]_i_28_n_1\,
CO(1) => \cb_int_reg[7]_i_28_n_2\,
CO(0) => \cb_int_reg[7]_i_28_n_3\,
CYINIT => \cb_int[7]_i_52_n_0\,
DI(3 downto 0) => B"0000",
O(3 downto 0) => cb_int_reg3(4 downto 1),
S(3) => \cb_int[7]_i_53_n_0\,
S(2) => \cb_int[7]_i_54_n_0\,
S(1) => \cb_int[7]_i_55_n_0\,
S(0) => \cb_int[7]_i_56_n_0\
);
\cb_int_reg[7]_i_29\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[3]_i_33_n_0\,
CO(3) => \cb_int_reg[7]_i_29_n_0\,
CO(2) => \cb_int_reg[7]_i_29_n_1\,
CO(1) => \cb_int_reg[7]_i_29_n_2\,
CO(0) => \cb_int_reg[7]_i_29_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cb_int_reg[7]_i_29_n_4\,
O(2) => \cb_int_reg[7]_i_29_n_5\,
O(1) => \cb_int_reg[7]_i_29_n_6\,
O(0) => \cb_int_reg[7]_i_29_n_7\,
S(3) => \cb_int[7]_i_57_n_0\,
S(2) => \cb_int[7]_i_58_n_0\,
S(1) => \cb_int[7]_i_59_n_0\,
S(0) => \cb_int[7]_i_60_n_0\
);
\cb_int_reg[7]_i_38\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[7]_i_61_n_0\,
CO(3) => \cb_int_reg[7]_i_38_n_0\,
CO(2) => \cb_int_reg[7]_i_38_n_1\,
CO(1) => \cb_int_reg[7]_i_38_n_2\,
CO(0) => \cb_int_reg[7]_i_38_n_3\,
CYINIT => '0',
DI(3) => \rgb888[8]_1\(1),
DI(2) => \rgb888[8]_1\(1),
DI(1) => \rgb888[8]_1\(1),
DI(0) => \rgb888[8]_1\(1),
O(3 downto 0) => \NLW_cb_int_reg[7]_i_38_O_UNCONNECTED\(3 downto 0),
S(3) => \cb_int[7]_i_62_n_0\,
S(2) => \cb_int[7]_i_63_n_0\,
S(1) => \cb_int[7]_i_64_n_0\,
S(0) => \cb_int[7]_i_65_n_0\
);
\cb_int_reg[7]_i_61\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[7]_i_66_n_0\,
CO(3) => \cb_int_reg[7]_i_61_n_0\,
CO(2) => \cb_int_reg[7]_i_61_n_1\,
CO(1) => \cb_int_reg[7]_i_61_n_2\,
CO(0) => \cb_int_reg[7]_i_61_n_3\,
CYINIT => '0',
DI(3) => \cb_int[7]_i_67_n_0\,
DI(2) => \cb_int[7]_i_68_n_0\,
DI(1) => \cb_int[7]_i_69_n_0\,
DI(0) => \cb_int[7]_i_70_n_0\,
O(3 downto 0) => \NLW_cb_int_reg[7]_i_61_O_UNCONNECTED\(3 downto 0),
S(3) => \cb_int[7]_i_71_n_0\,
S(2) => \cb_int[7]_i_72_n_0\,
S(1) => \cb_int[7]_i_73_n_0\,
S(0) => \cb_int[7]_i_74_n_0\
);
\cb_int_reg[7]_i_66\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cb_int_reg[7]_i_66_n_0\,
CO(2) => \cb_int_reg[7]_i_66_n_1\,
CO(1) => \cb_int_reg[7]_i_66_n_2\,
CO(0) => \cb_int_reg[7]_i_66_n_3\,
CYINIT => '1',
DI(3) => \cb_int[7]_i_75_n_0\,
DI(2) => \cb_int[7]_i_76_n_0\,
DI(1) => \cb_int[7]_i_77_n_0\,
DI(0) => \cb_int[7]_i_78_n_0\,
O(3 downto 0) => \NLW_cb_int_reg[7]_i_66_O_UNCONNECTED\(3 downto 0),
S(3) => \cb_int[7]_i_79_n_0\,
S(2) => \cb_int[7]_i_80_n_0\,
S(1) => \cb_int[7]_i_81_n_0\,
S(0) => \cb_int[7]_i_82_n_0\
);
\cb_int_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[11]_i_1_n_7\,
Q => \cb_int_reg__0\(8),
R => '0'
);
\cb_int_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[11]_i_1_n_6\,
Q => \cb_int_reg__0\(9),
R => '0'
);
\cb_reg[0]\: unisim.vcomponents.FDSE
port map (
C => cb_regn_0_0,
CE => '1',
D => \cb[0]_i_1_n_0\,
Q => cb(0),
S => \cb_reg[7]_i_1_n_0\
);
\cb_reg[1]\: unisim.vcomponents.FDSE
port map (
C => cb_regn_0_0,
CE => '1',
D => \cb[1]_i_1_n_0\,
Q => cb(1),
S => \cb_reg[7]_i_1_n_0\
);
\cb_reg[2]\: unisim.vcomponents.FDSE
port map (
C => cb_regn_0_0,
CE => '1',
D => \cb[2]_i_1_n_0\,
Q => cb(2),
S => \cb_reg[7]_i_1_n_0\
);
\cb_reg[3]\: unisim.vcomponents.FDSE
port map (
C => cb_regn_0_0,
CE => '1',
D => \cb[3]_i_1_n_0\,
Q => cb(3),
S => \cb_reg[7]_i_1_n_0\
);
\cb_reg[4]\: unisim.vcomponents.FDSE
port map (
C => cb_regn_0_0,
CE => '1',
D => \cb[4]_i_1_n_0\,
Q => cb(4),
S => \cb_reg[7]_i_1_n_0\
);
\cb_reg[5]\: unisim.vcomponents.FDSE
port map (
C => cb_regn_0_0,
CE => '1',
D => \cb[5]_i_1_n_0\,
Q => cb(5),
S => \cb_reg[7]_i_1_n_0\
);
\cb_reg[6]\: unisim.vcomponents.FDSE
port map (
C => cb_regn_0_0,
CE => '1',
D => \cb[6]_i_1_n_0\,
Q => cb(6),
S => \cb_reg[7]_i_1_n_0\
);
\cb_reg[7]\: unisim.vcomponents.FDSE
port map (
C => cb_regn_0_0,
CE => '1',
D => \cb[7]_i_2_n_0\,
Q => cb(7),
S => \cb_reg[7]_i_1_n_0\
);
\cb_reg[7]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \cb_reg[7]_i_3_n_0\,
CO(3) => \cb_reg[7]_i_1_n_0\,
CO(2) => \cb_reg[7]_i_1_n_1\,
CO(1) => \cb_reg[7]_i_1_n_2\,
CO(0) => \cb_reg[7]_i_1_n_3\,
CYINIT => '0',
DI(3) => \cb[7]_i_4_n_0\,
DI(2) => \cb[7]_i_5_n_0\,
DI(1) => \cb[7]_i_6_n_0\,
DI(0) => \cb[7]_i_7_n_0\,
O(3 downto 0) => \NLW_cb_reg[7]_i_1_O_UNCONNECTED\(3 downto 0),
S(3) => \cb[7]_i_8_n_0\,
S(2) => \cb[7]_i_9_n_0\,
S(1) => \cb[7]_i_10_n_0\,
S(0) => \cb[7]_i_11_n_0\
);
\cb_reg[7]_i_12\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cb_reg[7]_i_12_n_0\,
CO(2) => \cb_reg[7]_i_12_n_1\,
CO(1) => \cb_reg[7]_i_12_n_2\,
CO(0) => \cb_reg[7]_i_12_n_3\,
CYINIT => '0',
DI(3) => \cb[7]_i_21_n_0\,
DI(2) => \cb[7]_i_22_n_0\,
DI(1) => \cb[7]_i_23_n_0\,
DI(0) => \cb[7]_i_24_n_0\,
O(3 downto 0) => \NLW_cb_reg[7]_i_12_O_UNCONNECTED\(3 downto 0),
S(3) => \cb[7]_i_25_n_0\,
S(2) => \cb[7]_i_26_n_0\,
S(1) => \cb[7]_i_27_n_0\,
S(0) => \cb[7]_i_28_n_0\
);
\cb_reg[7]_i_3\: unisim.vcomponents.CARRY4
port map (
CI => \cb_reg[7]_i_12_n_0\,
CO(3) => \cb_reg[7]_i_3_n_0\,
CO(2) => \cb_reg[7]_i_3_n_1\,
CO(1) => \cb_reg[7]_i_3_n_2\,
CO(0) => \cb_reg[7]_i_3_n_3\,
CYINIT => '0',
DI(3) => \cb[7]_i_13_n_0\,
DI(2) => \cb[7]_i_14_n_0\,
DI(1) => \cb[7]_i_15_n_0\,
DI(0) => \cb[7]_i_16_n_0\,
O(3 downto 0) => \NLW_cb_reg[7]_i_3_O_UNCONNECTED\(3 downto 0),
S(3) => \cb[7]_i_17_n_0\,
S(2) => \cb[7]_i_18_n_0\,
S(1) => \cb[7]_i_19_n_0\,
S(0) => \cb[7]_i_20_n_0\
);
cb_regi_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => clk,
O => cb_regn_0_0
);
\cr[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \cr_int_reg_n_0_[0]\,
I1 => \cr_int_reg__0\(31),
O => \cr[0]_i_1_n_0\
);
\cr[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \cr_int_reg_n_0_[1]\,
I1 => \cr_int_reg__0\(31),
O => \cr[1]_i_1_n_0\
);
\cr[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \cr_int_reg_n_0_[2]\,
I1 => \cr_int_reg__0\(31),
O => \cr[2]_i_1_n_0\
);
\cr[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \cr_int_reg_n_0_[3]\,
I1 => \cr_int_reg__0\(31),
O => \cr[3]_i_1_n_0\
);
\cr[4]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \cr_int_reg_n_0_[4]\,
I1 => \cr_int_reg__0\(31),
O => \cr[4]_i_1_n_0\
);
\cr[5]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \cr_int_reg_n_0_[5]\,
I1 => \cr_int_reg__0\(31),
O => \cr[5]_i_1_n_0\
);
\cr[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \cr_int_reg_n_0_[6]\,
I1 => \cr_int_reg__0\(31),
O => \cr[6]_i_1_n_0\
);
\cr[7]_i_10\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg__0\(26),
I1 => \cr_int_reg__0\(27),
O => \cr[7]_i_10_n_0\
);
\cr[7]_i_11\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg__0\(24),
I1 => \cr_int_reg__0\(25),
O => \cr[7]_i_11_n_0\
);
\cr[7]_i_13\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg__0\(22),
I1 => \cr_int_reg__0\(23),
O => \cr[7]_i_13_n_0\
);
\cr[7]_i_14\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg__0\(20),
I1 => \cr_int_reg__0\(21),
O => \cr[7]_i_14_n_0\
);
\cr[7]_i_15\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg__0\(18),
I1 => \cr_int_reg__0\(19),
O => \cr[7]_i_15_n_0\
);
\cr[7]_i_16\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg__0\(16),
I1 => \cr_int_reg__0\(17),
O => \cr[7]_i_16_n_0\
);
\cr[7]_i_17\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg__0\(22),
I1 => \cr_int_reg__0\(23),
O => \cr[7]_i_17_n_0\
);
\cr[7]_i_18\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg__0\(20),
I1 => \cr_int_reg__0\(21),
O => \cr[7]_i_18_n_0\
);
\cr[7]_i_19\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg__0\(18),
I1 => \cr_int_reg__0\(19),
O => \cr[7]_i_19_n_0\
);
\cr[7]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \cr_int_reg_n_0_[7]\,
I1 => \cr_int_reg__0\(31),
O => \cr[7]_i_2_n_0\
);
\cr[7]_i_20\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg__0\(16),
I1 => \cr_int_reg__0\(17),
O => \cr[7]_i_20_n_0\
);
\cr[7]_i_21\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg__0\(14),
I1 => \cr_int_reg__0\(15),
O => \cr[7]_i_21_n_0\
);
\cr[7]_i_22\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg__0\(12),
I1 => \cr_int_reg__0\(13),
O => \cr[7]_i_22_n_0\
);
\cr[7]_i_23\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg__0\(10),
I1 => \cr_int_reg__0\(11),
O => \cr[7]_i_23_n_0\
);
\cr[7]_i_24\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg__0\(8),
I1 => \cr_int_reg__0\(9),
O => \cr[7]_i_24_n_0\
);
\cr[7]_i_25\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg__0\(14),
I1 => \cr_int_reg__0\(15),
O => \cr[7]_i_25_n_0\
);
\cr[7]_i_26\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg__0\(12),
I1 => \cr_int_reg__0\(13),
O => \cr[7]_i_26_n_0\
);
\cr[7]_i_27\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg__0\(10),
I1 => \cr_int_reg__0\(11),
O => \cr[7]_i_27_n_0\
);
\cr[7]_i_28\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg__0\(8),
I1 => \cr_int_reg__0\(9),
O => \cr[7]_i_28_n_0\
);
\cr[7]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \cr_int_reg__0\(30),
I1 => \cr_int_reg__0\(31),
O => \cr[7]_i_4_n_0\
);
\cr[7]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg__0\(28),
I1 => \cr_int_reg__0\(29),
O => \cr[7]_i_5_n_0\
);
\cr[7]_i_6\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg__0\(26),
I1 => \cr_int_reg__0\(27),
O => \cr[7]_i_6_n_0\
);
\cr[7]_i_7\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg__0\(24),
I1 => \cr_int_reg__0\(25),
O => \cr[7]_i_7_n_0\
);
\cr[7]_i_8\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg__0\(30),
I1 => \cr_int_reg__0\(31),
O => \cr[7]_i_8_n_0\
);
\cr[7]_i_9\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg__0\(28),
I1 => \cr_int_reg__0\(29),
O => \cr[7]_i_9_n_0\
);
\cr_hold_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \cb_hold[7]_i_1_n_0\,
D => cr(0),
Q => \cr_hold_reg_n_0_[0]\,
R => '0'
);
\cr_hold_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \cb_hold[7]_i_1_n_0\,
D => cr(1),
Q => \cr_hold_reg_n_0_[1]\,
R => '0'
);
\cr_hold_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \cb_hold[7]_i_1_n_0\,
D => cr(2),
Q => \cr_hold_reg_n_0_[2]\,
R => '0'
);
\cr_hold_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \cb_hold[7]_i_1_n_0\,
D => cr(3),
Q => \cr_hold_reg_n_0_[3]\,
R => '0'
);
\cr_hold_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \cb_hold[7]_i_1_n_0\,
D => cr(4),
Q => \cr_hold_reg_n_0_[4]\,
R => '0'
);
\cr_hold_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \cb_hold[7]_i_1_n_0\,
D => cr(5),
Q => \cr_hold_reg_n_0_[5]\,
R => '0'
);
\cr_hold_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \cb_hold[7]_i_1_n_0\,
D => cr(6),
Q => \cr_hold_reg_n_0_[6]\,
R => '0'
);
\cr_hold_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \cb_hold[7]_i_1_n_0\,
D => cr(7),
Q => \cr_hold_reg_n_0_[7]\,
R => '0'
);
\cr_int[11]_i_10\: unisim.vcomponents.LUT6
generic map(
INIT => X"F4040BFB0BFBF404"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(18),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(10),
I4 => \cr_int[15]_i_26_n_0\,
I5 => \cr_int[15]_i_27_n_0\,
O => \cr_int[11]_i_10_n_0\
);
\cr_int[11]_i_100\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => cr_int_reg6(11),
I1 => cr_int_reg7,
I2 => \cr_int_reg[31]_i_30_n_6\,
O => \cr_int[11]_i_100_n_0\
);
\cr_int[11]_i_101\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => cr_int_reg6(10),
I1 => cr_int_reg7,
I2 => \cr_int_reg[31]_i_30_n_7\,
O => \cr_int[11]_i_101_n_0\
);
\cr_int[11]_i_102\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => cr_int_reg6(9),
I1 => cr_int_reg7,
I2 => \cr_int_reg[3]_i_16_n_4\,
O => \cr_int[11]_i_102_n_0\
);
\cr_int[11]_i_104\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[31]_2\(1),
O => \cr_int[11]_i_104_n_0\
);
\cr_int[11]_i_105\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[31]_2\(1),
O => \cr_int[11]_i_105_n_0\
);
\cr_int[11]_i_106\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[31]_2\(1),
O => \cr_int[11]_i_106_n_0\
);
\cr_int[11]_i_107\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[31]_2\(1),
O => \cr_int[11]_i_107_n_0\
);
\cr_int[11]_i_109\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg[31]_i_7_n_6\,
I1 => \cr_int_reg[31]_i_7_n_5\,
O => \cr_int[11]_i_109_n_0\
);
\cr_int[11]_i_11\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(17),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(9),
I4 => \cr_int[11]_i_24_n_0\,
I5 => \cr_int[11]_i_25_n_0\,
O => \cr_int[11]_i_11_n_0\
);
\cr_int[11]_i_110\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg[31]_i_14_n_4\,
I1 => \cr_int_reg[31]_i_7_n_7\,
O => \cr_int[11]_i_110_n_0\
);
\cr_int[11]_i_111\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg[31]_i_14_n_6\,
I1 => \cr_int_reg[31]_i_14_n_5\,
O => \cr_int[11]_i_111_n_0\
);
\cr_int[11]_i_112\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
O => \cr_int[11]_i_112_n_0\
);
\cr_int[11]_i_113\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_7_n_5\,
I1 => \cr_int_reg[31]_i_7_n_6\,
O => \cr_int[11]_i_113_n_0\
);
\cr_int[11]_i_114\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_7_n_7\,
I1 => \cr_int_reg[31]_i_14_n_4\,
O => \cr_int[11]_i_114_n_0\
);
\cr_int[11]_i_115\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_14_n_5\,
I1 => \cr_int_reg[31]_i_14_n_6\,
O => \cr_int[11]_i_115_n_0\
);
\cr_int[11]_i_117\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_7\,
I1 => \cr_int_reg[31]_i_11_n_6\,
O => \cr_int[11]_i_117_n_0\
);
\cr_int[11]_i_118\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg[31]_i_30_n_5\,
I1 => \cr_int_reg[31]_i_30_n_4\,
O => \cr_int[11]_i_118_n_0\
);
\cr_int[11]_i_119\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg[31]_i_30_n_7\,
I1 => \cr_int_reg[31]_i_30_n_6\,
O => \cr_int[11]_i_119_n_0\
);
\cr_int[11]_i_12\: unisim.vcomponents.LUT6
generic map(
INIT => X"F4040BFB0BFBF404"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(17),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(9),
I4 => \cr_int[11]_i_24_n_0\,
I5 => \cr_int[11]_i_25_n_0\,
O => \cr_int[11]_i_12_n_0\
);
\cr_int[11]_i_120\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg[3]_i_16_n_5\,
I1 => \cr_int_reg[3]_i_16_n_4\,
O => \cr_int[11]_i_120_n_0\
);
\cr_int[11]_i_121\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_6\,
I1 => \cr_int_reg[31]_i_11_n_7\,
O => \cr_int[11]_i_121_n_0\
);
\cr_int[11]_i_122\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_30_n_4\,
I1 => \cr_int_reg[31]_i_30_n_5\,
O => \cr_int[11]_i_122_n_0\
);
\cr_int[11]_i_123\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_30_n_6\,
I1 => \cr_int_reg[31]_i_30_n_7\,
O => \cr_int[11]_i_123_n_0\
);
\cr_int[11]_i_124\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[3]_i_16_n_4\,
I1 => \cr_int_reg[3]_i_16_n_5\,
O => \cr_int[11]_i_124_n_0\
);
\cr_int[11]_i_126\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \^cr_int_reg[7]_0\(3),
I1 => \^cr_int_reg[31]_2\(0),
O => \cr_int[11]_i_126_n_0\
);
\cr_int[11]_i_127\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \^cr_int_reg[7]_0\(1),
I1 => \^cr_int_reg[7]_0\(2),
O => \cr_int[11]_i_127_n_0\
);
\cr_int[11]_i_128\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \^cr_int_reg[3]_0\(2),
I1 => \^cr_int_reg[7]_0\(0),
O => \cr_int[11]_i_128_n_0\
);
\cr_int[11]_i_129\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \^cr_int_reg[3]_0\(0),
I1 => \^cr_int_reg[3]_0\(1),
O => \cr_int[11]_i_129_n_0\
);
\cr_int[11]_i_13\: unisim.vcomponents.LUT6
generic map(
INIT => X"8EEE8E888EEE8EEE"
)
port map (
I0 => \cr_int_reg3__0\(8),
I1 => \cr_int[11]_i_27_n_0\,
I2 => \cr_int_reg[11]_i_16_n_4\,
I3 => \^cr_int_reg[27]_2\(0),
I4 => \cr_int_reg[11]_i_17_n_0\,
I5 => \cr_int_reg[11]_i_18_n_4\,
O => \cr_int[11]_i_13_n_0\
);
\cr_int[11]_i_130\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[31]_2\(0),
I1 => \^cr_int_reg[7]_0\(3),
O => \cr_int[11]_i_130_n_0\
);
\cr_int[11]_i_131\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[7]_0\(2),
I1 => \^cr_int_reg[7]_0\(1),
O => \cr_int[11]_i_131_n_0\
);
\cr_int[11]_i_132\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[7]_0\(0),
I1 => \^cr_int_reg[3]_0\(2),
O => \cr_int[11]_i_132_n_0\
);
\cr_int[11]_i_133\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[3]_0\(1),
I1 => \^cr_int_reg[3]_0\(0),
O => \cr_int[11]_i_133_n_0\
);
\cr_int[11]_i_134\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg[31]_i_39_n_4\,
I1 => \cr_int_reg[31]_i_14_n_7\,
O => \cr_int[11]_i_134_n_0\
);
\cr_int[11]_i_135\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg[31]_i_39_n_6\,
I1 => \cr_int_reg[31]_i_39_n_5\,
O => \cr_int[11]_i_135_n_0\
);
\cr_int[11]_i_136\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg[31]_i_86_n_6\,
I1 => \cr_int_reg[31]_i_39_n_7\,
O => \cr_int[11]_i_136_n_0\
);
\cr_int[11]_i_137\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => rgb888(0),
I1 => \cr_int_reg[31]_i_86_n_7\,
O => \cr_int[11]_i_137_n_0\
);
\cr_int[11]_i_138\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_14_n_7\,
I1 => \cr_int_reg[31]_i_39_n_4\,
O => \cr_int[11]_i_138_n_0\
);
\cr_int[11]_i_139\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_39_n_5\,
I1 => \cr_int_reg[31]_i_39_n_6\,
O => \cr_int[11]_i_139_n_0\
);
\cr_int[11]_i_14\: unisim.vcomponents.LUT6
generic map(
INIT => X"6999696669996999"
)
port map (
I0 => \cr_int_reg3__0\(8),
I1 => \cr_int[11]_i_27_n_0\,
I2 => \cr_int_reg[11]_i_16_n_4\,
I3 => \^cr_int_reg[27]_2\(0),
I4 => \cr_int_reg[11]_i_17_n_0\,
I5 => \cr_int_reg[11]_i_18_n_4\,
O => \cr_int[11]_i_14_n_0\
);
\cr_int[11]_i_140\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_39_n_7\,
I1 => \cr_int_reg[31]_i_86_n_6\,
O => \cr_int[11]_i_140_n_0\
);
\cr_int[11]_i_141\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_86_n_7\,
I1 => rgb888(0),
O => \cr_int[11]_i_141_n_0\
);
\cr_int[11]_i_142\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg[3]_i_16_n_7\,
I1 => \cr_int_reg[3]_i_16_n_6\,
O => \cr_int[11]_i_142_n_0\
);
\cr_int[11]_i_143\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg[3]_i_27_n_7\,
I1 => \cr_int_reg[3]_i_27_n_6\,
O => \cr_int[11]_i_143_n_0\
);
\cr_int[11]_i_144\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg[3]_i_54_n_5\,
I1 => \cr_int_reg[3]_i_54_n_4\,
O => \cr_int[11]_i_144_n_0\
);
\cr_int[11]_i_145\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg[3]_i_54_n_7\,
I1 => \cr_int_reg[3]_i_54_n_6\,
O => \cr_int[11]_i_145_n_0\
);
\cr_int[11]_i_146\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[3]_i_16_n_6\,
I1 => \cr_int_reg[3]_i_16_n_7\,
O => \cr_int[11]_i_146_n_0\
);
\cr_int[11]_i_147\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[3]_i_27_n_6\,
I1 => \cr_int_reg[3]_i_27_n_7\,
O => \cr_int[11]_i_147_n_0\
);
\cr_int[11]_i_148\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[3]_i_54_n_4\,
I1 => \cr_int_reg[3]_i_54_n_5\,
O => \cr_int[11]_i_148_n_0\
);
\cr_int[11]_i_149\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[3]_i_54_n_6\,
I1 => \cr_int_reg[3]_i_54_n_7\,
O => \cr_int[11]_i_149_n_0\
);
\cr_int[11]_i_15\: unisim.vcomponents.LUT5
generic map(
INIT => X"44477747"
)
port map (
I0 => \rgb888[8]_13\(2),
I1 => \^cr_int_reg[31]_2\(1),
I2 => \^cr_int_reg[11]_0\(1),
I3 => \^cr_int_reg[3]_1\(0),
I4 => \^cr_int_reg[31]_2\(0),
O => \cr_int[11]_i_15_n_0\
);
\cr_int[11]_i_150\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg[3]_i_33_n_4\,
I1 => \cr_int_reg[3]_i_19_n_7\,
O => \cr_int[11]_i_150_n_0\
);
\cr_int[11]_i_151\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg[3]_i_33_n_6\,
I1 => \cr_int_reg[3]_i_33_n_5\,
O => \cr_int[11]_i_151_n_0\
);
\cr_int[11]_i_152\: unisim.vcomponents.LUT3
generic map(
INIT => X"BE"
)
port map (
I0 => \cr_int_reg[3]_i_65_n_6\,
I1 => \cr_int_reg[3]_i_65_n_5\,
I2 => rgb888(8),
O => \cr_int[11]_i_152_n_0\
);
\cr_int[11]_i_153\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[3]_i_19_n_7\,
I1 => \cr_int_reg[3]_i_33_n_4\,
O => \cr_int[11]_i_153_n_0\
);
\cr_int[11]_i_154\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[3]_i_33_n_5\,
I1 => \cr_int_reg[3]_i_33_n_6\,
O => \cr_int[11]_i_154_n_0\
);
\cr_int[11]_i_155\: unisim.vcomponents.LUT3
generic map(
INIT => X"09"
)
port map (
I0 => rgb888(8),
I1 => \cr_int_reg[3]_i_65_n_5\,
I2 => \cr_int_reg[3]_i_65_n_6\,
O => \cr_int[11]_i_155_n_0\
);
\cr_int[11]_i_156\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_94_n_7\,
O => \cr_int[11]_i_156_n_0\
);
\cr_int[11]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cr_int[11]_i_10_n_0\,
I1 => \cr_int[11]_i_11_n_0\,
O => \cr_int[11]_i_2_n_0\
);
\cr_int[11]_i_22\: unisim.vcomponents.LUT5
generic map(
INIT => X"0DFDF202"
)
port map (
I0 => \cr_int_reg[11]_i_18_n_5\,
I1 => \cr_int_reg[11]_i_17_n_0\,
I2 => \^cr_int_reg[27]_2\(0),
I3 => \cr_int_reg[11]_i_16_n_5\,
I4 => \cr_int[11]_i_15_n_0\,
O => \cr_int[11]_i_22_n_0\
);
\cr_int[11]_i_23\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFF0DFD"
)
port map (
I0 => \cr_int_reg[11]_i_18_n_5\,
I1 => \cr_int_reg[11]_i_17_n_0\,
I2 => \^cr_int_reg[27]_2\(0),
I3 => \cr_int_reg[11]_i_16_n_5\,
I4 => \cr_int[11]_i_15_n_0\,
O => \cr_int[11]_i_23_n_0\
);
\cr_int[11]_i_24\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_14\(0),
I1 => \^cr_int_reg[31]_2\(1),
I2 => \^cr_int_reg[3]_1\(0),
I3 => \^cr_int_reg[11]_0\(3),
O => \cr_int[11]_i_24_n_0\
);
\cr_int[11]_i_25\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \cr_int_reg[15]_i_38_n_7\,
I1 => \^cr_int_reg[27]_2\(0),
I2 => \cr_int_reg[11]_i_17_n_0\,
I3 => \rgb888[3]\(0),
O => \cr_int[11]_i_25_n_0\
);
\cr_int[11]_i_26\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => cr_int_reg4(8),
I1 => \cr_int_reg[31]_i_11_n_4\,
I2 => \cr_int_reg[31]_i_11_n_5\,
I3 => cr_int_reg7,
I4 => cr_int_reg6(16),
O => \cr_int_reg3__0\(8)
);
\cr_int[11]_i_27\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_13\(3),
I1 => \^cr_int_reg[31]_2\(1),
I2 => \^cr_int_reg[3]_1\(0),
I3 => \^cr_int_reg[11]_0\(2),
O => \cr_int[11]_i_27_n_0\
);
\cr_int[11]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cr_int[11]_i_12_n_0\,
I1 => \cr_int[11]_i_13_n_0\,
O => \cr_int[11]_i_3_n_0\
);
\cr_int[11]_i_32\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
I1 => \cr_int_reg[11]_i_17_n_0\,
I2 => \cr_int_reg[11]_i_18_n_4\,
O => \cr_int[11]_i_32_n_0\
);
\cr_int[11]_i_33\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
I1 => \cr_int_reg[11]_i_17_n_0\,
I2 => \cr_int_reg[11]_i_18_n_5\,
O => \cr_int[11]_i_33_n_0\
);
\cr_int[11]_i_34\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
I1 => \cr_int_reg[11]_i_17_n_0\,
I2 => \cr_int_reg[11]_i_18_n_6\,
O => \cr_int[11]_i_34_n_0\
);
\cr_int[11]_i_35\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \cr_int_reg[11]_i_18_n_7\,
I1 => \cr_int_reg[11]_i_17_n_0\,
I2 => \cr_int_reg[31]_i_7_n_5\,
O => \cr_int[11]_i_35_n_0\
);
\cr_int[11]_i_37\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
O => \cr_int[11]_i_37_n_0\
);
\cr_int[11]_i_38\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
O => \cr_int[11]_i_38_n_0\
);
\cr_int[11]_i_39\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
O => \cr_int[11]_i_39_n_0\
);
\cr_int[11]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"8AAA8A888AAA8AAA"
)
port map (
I0 => \cr_int[11]_i_14_n_0\,
I1 => \cr_int[11]_i_15_n_0\,
I2 => \cr_int_reg[11]_i_16_n_5\,
I3 => \^cr_int_reg[27]_2\(0),
I4 => \cr_int_reg[11]_i_17_n_0\,
I5 => \cr_int_reg[11]_i_18_n_5\,
O => \cr_int[11]_i_4_n_0\
);
\cr_int[11]_i_40\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
O => \cr_int[11]_i_40_n_0\
);
\cr_int[11]_i_42\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
O => \cr_int[11]_i_42_n_0\
);
\cr_int[11]_i_43\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
O => \cr_int[11]_i_43_n_0\
);
\cr_int[11]_i_44\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
O => \cr_int[11]_i_44_n_0\
);
\cr_int[11]_i_45\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_7_n_5\,
O => \cr_int[11]_i_45_n_0\
);
\cr_int[11]_i_47\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_5\,
O => \cr_int[11]_i_47_n_0\
);
\cr_int[11]_i_48\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_6\,
O => \cr_int[11]_i_48_n_0\
);
\cr_int[11]_i_49\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_7\,
O => \cr_int[11]_i_49_n_0\
);
\cr_int[11]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFE200E200000000"
)
port map (
I0 => cr_int_reg6(15),
I1 => cr_int_reg7,
I2 => \cr_int_reg[31]_i_11_n_6\,
I3 => \cr_int_reg[31]_i_11_n_4\,
I4 => cr_int_reg4(7),
I5 => \cr_int[11]_i_22_n_0\,
O => \cr_int[11]_i_5_n_0\
);
\cr_int[11]_i_50\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_30_n_4\,
O => \cr_int[11]_i_50_n_0\
);
\cr_int[11]_i_52\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
O => \cr_int[11]_i_52_n_0\
);
\cr_int[11]_i_53\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
O => \cr_int[11]_i_53_n_0\
);
\cr_int[11]_i_54\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
O => \cr_int[11]_i_54_n_0\
);
\cr_int[11]_i_55\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
O => \cr_int[11]_i_55_n_0\
);
\cr_int[11]_i_57\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => cr_int_reg6(16),
I1 => cr_int_reg7,
I2 => \cr_int_reg[31]_i_11_n_5\,
O => \cr_int[11]_i_57_n_0\
);
\cr_int[11]_i_58\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => cr_int_reg6(15),
I1 => cr_int_reg7,
I2 => \cr_int_reg[31]_i_11_n_6\,
O => \cr_int[11]_i_58_n_0\
);
\cr_int[11]_i_59\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => cr_int_reg6(14),
I1 => cr_int_reg7,
I2 => \cr_int_reg[31]_i_11_n_7\,
O => \cr_int[11]_i_59_n_0\
);
\cr_int[11]_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cr_int[15]_i_16_n_0\,
I1 => \cr_int[15]_i_17_n_0\,
I2 => \cr_int[11]_i_2_n_0\,
O => \cr_int[11]_i_6_n_0\
);
\cr_int[11]_i_60\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => cr_int_reg6(13),
I1 => cr_int_reg7,
I2 => \cr_int_reg[31]_i_30_n_4\,
O => \cr_int[11]_i_60_n_0\
);
\cr_int[11]_i_65\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[31]_2\(1),
O => \cr_int[11]_i_65_n_0\
);
\cr_int[11]_i_66\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[31]_2\(1),
O => \cr_int[11]_i_66_n_0\
);
\cr_int[11]_i_67\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[31]_2\(0),
O => \cr_int[11]_i_67_n_0\
);
\cr_int[11]_i_68\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[7]_0\(3),
O => \cr_int[11]_i_68_n_0\
);
\cr_int[11]_i_7\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cr_int[11]_i_10_n_0\,
I1 => \cr_int[11]_i_11_n_0\,
I2 => \cr_int[11]_i_3_n_0\,
O => \cr_int[11]_i_7_n_0\
);
\cr_int[11]_i_70\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[31]_2\(1),
O => \cr_int[11]_i_70_n_0\
);
\cr_int[11]_i_71\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[31]_2\(1),
O => \cr_int[11]_i_71_n_0\
);
\cr_int[11]_i_72\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[31]_2\(1),
O => \cr_int[11]_i_72_n_0\
);
\cr_int[11]_i_73\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[31]_2\(1),
O => \cr_int[11]_i_73_n_0\
);
\cr_int[11]_i_74\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \cr_int_reg[3]_i_32_n_4\,
I1 => \cr_int_reg[11]_i_17_n_0\,
I2 => \cr_int_reg[31]_i_14_n_6\,
O => \cr_int[11]_i_74_n_0\
);
\cr_int[11]_i_75\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \cr_int_reg[11]_i_41_n_4\,
I1 => \cr_int_reg[11]_i_17_n_0\,
I2 => \cr_int_reg[31]_i_7_n_6\,
O => \cr_int[11]_i_75_n_0\
);
\cr_int[11]_i_76\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \cr_int_reg[11]_i_41_n_5\,
I1 => \cr_int_reg[11]_i_17_n_0\,
I2 => \cr_int_reg[31]_i_7_n_7\,
O => \cr_int[11]_i_76_n_0\
);
\cr_int[11]_i_77\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \cr_int_reg[11]_i_41_n_6\,
I1 => \cr_int_reg[11]_i_17_n_0\,
I2 => \cr_int_reg[31]_i_14_n_4\,
O => \cr_int[11]_i_77_n_0\
);
\cr_int[11]_i_78\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \cr_int_reg[11]_i_41_n_7\,
I1 => \cr_int_reg[11]_i_17_n_0\,
I2 => \cr_int_reg[31]_i_14_n_5\,
O => \cr_int[11]_i_78_n_0\
);
\cr_int[11]_i_8\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cr_int[11]_i_12_n_0\,
I1 => \cr_int[11]_i_13_n_0\,
I2 => \cr_int[11]_i_4_n_0\,
O => \cr_int[11]_i_8_n_0\
);
\cr_int[11]_i_80\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
O => \cr_int[11]_i_80_n_0\
);
\cr_int[11]_i_81\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
O => \cr_int[11]_i_81_n_0\
);
\cr_int[11]_i_82\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
O => \cr_int[11]_i_82_n_0\
);
\cr_int[11]_i_83\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
O => \cr_int[11]_i_83_n_0\
);
\cr_int[11]_i_84\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_7_n_6\,
O => \cr_int[11]_i_84_n_0\
);
\cr_int[11]_i_85\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_7_n_7\,
O => \cr_int[11]_i_85_n_0\
);
\cr_int[11]_i_86\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_14_n_4\,
O => \cr_int[11]_i_86_n_0\
);
\cr_int[11]_i_87\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_14_n_5\,
O => \cr_int[11]_i_87_n_0\
);
\cr_int[11]_i_88\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_30_n_5\,
O => \cr_int[11]_i_88_n_0\
);
\cr_int[11]_i_89\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_30_n_6\,
O => \cr_int[11]_i_89_n_0\
);
\cr_int[11]_i_9\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cr_int[11]_i_5_n_0\,
I1 => \cr_int[11]_i_14_n_0\,
I2 => \cr_int[11]_i_23_n_0\,
O => \cr_int[11]_i_9_n_0\
);
\cr_int[11]_i_90\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_30_n_7\,
O => \cr_int[11]_i_90_n_0\
);
\cr_int[11]_i_91\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[3]_i_16_n_4\,
O => \cr_int[11]_i_91_n_0\
);
\cr_int[11]_i_93\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_5\,
I1 => \cr_int_reg[31]_i_11_n_4\,
O => \cr_int[11]_i_93_n_0\
);
\cr_int[11]_i_94\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
O => \cr_int[11]_i_94_n_0\
);
\cr_int[11]_i_95\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
O => \cr_int[11]_i_95_n_0\
);
\cr_int[11]_i_96\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
O => \cr_int[11]_i_96_n_0\
);
\cr_int[11]_i_97\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
I1 => \cr_int_reg[31]_i_11_n_5\,
O => \cr_int[11]_i_97_n_0\
);
\cr_int[11]_i_98\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => cr_int_reg6(8),
I1 => cr_int_reg7,
I2 => \cr_int_reg[3]_i_16_n_5\,
O => \cr_int[11]_i_98_n_0\
);
\cr_int[11]_i_99\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => cr_int_reg6(12),
I1 => cr_int_reg7,
I2 => \cr_int_reg[31]_i_30_n_5\,
O => \cr_int[11]_i_99_n_0\
);
\cr_int[15]_i_10\: unisim.vcomponents.LUT6
generic map(
INIT => X"F4040BFB0BFBF404"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(22),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(14),
I4 => \cr_int[19]_i_26_n_0\,
I5 => \cr_int[19]_i_27_n_0\,
O => \cr_int[15]_i_10_n_0\
);
\cr_int[15]_i_11\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(21),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(13),
I4 => \cr_int[15]_i_18_n_0\,
I5 => \cr_int[15]_i_19_n_0\,
O => \cr_int[15]_i_11_n_0\
);
\cr_int[15]_i_12\: unisim.vcomponents.LUT6
generic map(
INIT => X"F4040BFB0BFBF404"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(21),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(13),
I4 => \cr_int[15]_i_18_n_0\,
I5 => \cr_int[15]_i_19_n_0\,
O => \cr_int[15]_i_12_n_0\
);
\cr_int[15]_i_13\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(20),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(12),
I4 => \cr_int[15]_i_22_n_0\,
I5 => \cr_int[15]_i_23_n_0\,
O => \cr_int[15]_i_13_n_0\
);
\cr_int[15]_i_14\: unisim.vcomponents.LUT6
generic map(
INIT => X"F4040BFB0BFBF404"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(20),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(12),
I4 => \cr_int[15]_i_22_n_0\,
I5 => \cr_int[15]_i_23_n_0\,
O => \cr_int[15]_i_14_n_0\
);
\cr_int[15]_i_15\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(19),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(11),
I4 => \cr_int[15]_i_24_n_0\,
I5 => \cr_int[15]_i_25_n_0\,
O => \cr_int[15]_i_15_n_0\
);
\cr_int[15]_i_16\: unisim.vcomponents.LUT6
generic map(
INIT => X"F4040BFB0BFBF404"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(19),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(11),
I4 => \cr_int[15]_i_24_n_0\,
I5 => \cr_int[15]_i_25_n_0\,
O => \cr_int[15]_i_16_n_0\
);
\cr_int[15]_i_17\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(18),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(10),
I4 => \cr_int[15]_i_26_n_0\,
I5 => \cr_int[15]_i_27_n_0\,
O => \cr_int[15]_i_17_n_0\
);
\cr_int[15]_i_18\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_15\(0),
I1 => \^cr_int_reg[31]_2\(1),
I2 => \^cr_int_reg[3]_1\(0),
I3 => \^cr_int_reg[15]_0\(3),
O => \cr_int[15]_i_18_n_0\
);
\cr_int[15]_i_19\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \cr_int_reg[31]_i_49_n_7\,
I1 => \^cr_int_reg[27]_2\(0),
I2 => \cr_int_reg[11]_i_17_n_0\,
I3 => \rgb888[3]_0\(0),
O => \cr_int[15]_i_19_n_0\
);
\cr_int[15]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cr_int[15]_i_10_n_0\,
I1 => \cr_int[15]_i_11_n_0\,
O => \cr_int[15]_i_2_n_0\
);
\cr_int[15]_i_22\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_14\(3),
I1 => \^cr_int_reg[31]_2\(1),
I2 => \^cr_int_reg[3]_1\(0),
I3 => \^cr_int_reg[15]_0\(2),
O => \cr_int[15]_i_22_n_0\
);
\cr_int[15]_i_23\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \cr_int_reg[15]_i_38_n_4\,
I1 => \^cr_int_reg[27]_2\(0),
I2 => \cr_int_reg[11]_i_17_n_0\,
I3 => \rgb888[3]\(3),
O => \cr_int[15]_i_23_n_0\
);
\cr_int[15]_i_24\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_14\(2),
I1 => \^cr_int_reg[31]_2\(1),
I2 => \^cr_int_reg[3]_1\(0),
I3 => \^cr_int_reg[15]_0\(1),
O => \cr_int[15]_i_24_n_0\
);
\cr_int[15]_i_25\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \cr_int_reg[15]_i_38_n_5\,
I1 => \^cr_int_reg[27]_2\(0),
I2 => \cr_int_reg[11]_i_17_n_0\,
I3 => \rgb888[3]\(2),
O => \cr_int[15]_i_25_n_0\
);
\cr_int[15]_i_26\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_14\(1),
I1 => \^cr_int_reg[31]_2\(1),
I2 => \^cr_int_reg[3]_1\(0),
I3 => \^cr_int_reg[15]_0\(0),
O => \cr_int[15]_i_26_n_0\
);
\cr_int[15]_i_27\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \cr_int_reg[15]_i_38_n_6\,
I1 => \^cr_int_reg[27]_2\(0),
I2 => \cr_int_reg[11]_i_17_n_0\,
I3 => \rgb888[3]\(1),
O => \cr_int[15]_i_27_n_0\
);
\cr_int[15]_i_29\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
O => \cr_int[15]_i_29_n_0\
);
\cr_int[15]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cr_int[15]_i_12_n_0\,
I1 => \cr_int[15]_i_13_n_0\,
O => \cr_int[15]_i_3_n_0\
);
\cr_int[15]_i_30\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
O => \cr_int[15]_i_30_n_0\
);
\cr_int[15]_i_31\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
O => \cr_int[15]_i_31_n_0\
);
\cr_int[15]_i_32\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
O => \cr_int[15]_i_32_n_0\
);
\cr_int[15]_i_33\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
I1 => cr_int_reg7,
I2 => cr_int_reg6(20),
O => \cr_int[15]_i_33_n_0\
);
\cr_int[15]_i_34\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
I1 => cr_int_reg7,
I2 => cr_int_reg6(19),
O => \cr_int[15]_i_34_n_0\
);
\cr_int[15]_i_35\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
I1 => cr_int_reg7,
I2 => cr_int_reg6(18),
O => \cr_int[15]_i_35_n_0\
);
\cr_int[15]_i_36\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
I1 => cr_int_reg7,
I2 => cr_int_reg6(17),
O => \cr_int[15]_i_36_n_0\
);
\cr_int[15]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cr_int[15]_i_14_n_0\,
I1 => \cr_int[15]_i_15_n_0\,
O => \cr_int[15]_i_4_n_0\
);
\cr_int[15]_i_40\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[31]_2\(1),
O => \cr_int[15]_i_40_n_0\
);
\cr_int[15]_i_41\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[31]_2\(1),
O => \cr_int[15]_i_41_n_0\
);
\cr_int[15]_i_42\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[31]_2\(1),
O => \cr_int[15]_i_42_n_0\
);
\cr_int[15]_i_43\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[31]_2\(1),
O => \cr_int[15]_i_43_n_0\
);
\cr_int[15]_i_48\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
I1 => \cr_int_reg[11]_i_17_n_0\,
I2 => \rgb888[3]\(3),
O => \cr_int[15]_i_48_n_0\
);
\cr_int[15]_i_49\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
I1 => \cr_int_reg[11]_i_17_n_0\,
I2 => \rgb888[3]\(2),
O => \cr_int[15]_i_49_n_0\
);
\cr_int[15]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cr_int[15]_i_16_n_0\,
I1 => \cr_int[15]_i_17_n_0\,
O => \cr_int[15]_i_5_n_0\
);
\cr_int[15]_i_50\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
I1 => \cr_int_reg[11]_i_17_n_0\,
I2 => \rgb888[3]\(1),
O => \cr_int[15]_i_50_n_0\
);
\cr_int[15]_i_51\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
I1 => \cr_int_reg[11]_i_17_n_0\,
I2 => \rgb888[3]\(0),
O => \cr_int[15]_i_51_n_0\
);
\cr_int[15]_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cr_int[19]_i_16_n_0\,
I1 => \cr_int[19]_i_17_n_0\,
I2 => \cr_int[15]_i_2_n_0\,
O => \cr_int[15]_i_6_n_0\
);
\cr_int[15]_i_7\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cr_int[15]_i_10_n_0\,
I1 => \cr_int[15]_i_11_n_0\,
I2 => \cr_int[15]_i_3_n_0\,
O => \cr_int[15]_i_7_n_0\
);
\cr_int[15]_i_8\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cr_int[15]_i_12_n_0\,
I1 => \cr_int[15]_i_13_n_0\,
I2 => \cr_int[15]_i_4_n_0\,
O => \cr_int[15]_i_8_n_0\
);
\cr_int[15]_i_9\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cr_int[15]_i_14_n_0\,
I1 => \cr_int[15]_i_15_n_0\,
I2 => \cr_int[15]_i_5_n_0\,
O => \cr_int[15]_i_9_n_0\
);
\cr_int[19]_i_10\: unisim.vcomponents.LUT6
generic map(
INIT => X"F4040BFB0BFBF404"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(26),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(18),
I4 => \cr_int[23]_i_25_n_0\,
I5 => \cr_int[23]_i_26_n_0\,
O => \cr_int[19]_i_10_n_0\
);
\cr_int[19]_i_11\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(25),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(17),
I4 => \cr_int[19]_i_18_n_0\,
I5 => \cr_int[19]_i_19_n_0\,
O => \cr_int[19]_i_11_n_0\
);
\cr_int[19]_i_12\: unisim.vcomponents.LUT6
generic map(
INIT => X"F4040BFB0BFBF404"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(25),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(17),
I4 => \cr_int[19]_i_18_n_0\,
I5 => \cr_int[19]_i_19_n_0\,
O => \cr_int[19]_i_12_n_0\
);
\cr_int[19]_i_13\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(24),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(16),
I4 => \cr_int[19]_i_22_n_0\,
I5 => \cr_int[19]_i_23_n_0\,
O => \cr_int[19]_i_13_n_0\
);
\cr_int[19]_i_14\: unisim.vcomponents.LUT6
generic map(
INIT => X"F4040BFB0BFBF404"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(24),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(16),
I4 => \cr_int[19]_i_22_n_0\,
I5 => \cr_int[19]_i_23_n_0\,
O => \cr_int[19]_i_14_n_0\
);
\cr_int[19]_i_15\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(23),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(15),
I4 => \cr_int[19]_i_24_n_0\,
I5 => \cr_int[19]_i_25_n_0\,
O => \cr_int[19]_i_15_n_0\
);
\cr_int[19]_i_16\: unisim.vcomponents.LUT6
generic map(
INIT => X"F4040BFB0BFBF404"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(23),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(15),
I4 => \cr_int[19]_i_24_n_0\,
I5 => \cr_int[19]_i_25_n_0\,
O => \cr_int[19]_i_16_n_0\
);
\cr_int[19]_i_17\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(22),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(14),
I4 => \cr_int[19]_i_26_n_0\,
I5 => \cr_int[19]_i_27_n_0\,
O => \cr_int[19]_i_17_n_0\
);
\cr_int[19]_i_18\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_16\(0),
I1 => \^cr_int_reg[31]_2\(1),
I2 => \^cr_int_reg[3]_1\(0),
I3 => \^cr_int_reg[19]_0\(3),
O => \cr_int[19]_i_18_n_0\
);
\cr_int[19]_i_19\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \cr_int_reg[31]_i_21_n_7\,
I1 => \^cr_int_reg[27]_2\(0),
I2 => \cr_int_reg[11]_i_17_n_0\,
I3 => \rgb888[0]_5\(0),
O => \cr_int[19]_i_19_n_0\
);
\cr_int[19]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cr_int[19]_i_10_n_0\,
I1 => \cr_int[19]_i_11_n_0\,
O => \cr_int[19]_i_2_n_0\
);
\cr_int[19]_i_22\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_15\(3),
I1 => \^cr_int_reg[31]_2\(1),
I2 => \^cr_int_reg[3]_1\(0),
I3 => \^cr_int_reg[19]_0\(2),
O => \cr_int[19]_i_22_n_0\
);
\cr_int[19]_i_23\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \cr_int_reg[31]_i_49_n_4\,
I1 => \^cr_int_reg[27]_2\(0),
I2 => \cr_int_reg[11]_i_17_n_0\,
I3 => \rgb888[3]_0\(3),
O => \cr_int[19]_i_23_n_0\
);
\cr_int[19]_i_24\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_15\(2),
I1 => \^cr_int_reg[31]_2\(1),
I2 => \^cr_int_reg[3]_1\(0),
I3 => \^cr_int_reg[19]_0\(1),
O => \cr_int[19]_i_24_n_0\
);
\cr_int[19]_i_25\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \cr_int_reg[31]_i_49_n_5\,
I1 => \^cr_int_reg[27]_2\(0),
I2 => \cr_int_reg[11]_i_17_n_0\,
I3 => \rgb888[3]_0\(2),
O => \cr_int[19]_i_25_n_0\
);
\cr_int[19]_i_26\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_15\(1),
I1 => \^cr_int_reg[31]_2\(1),
I2 => \^cr_int_reg[3]_1\(0),
I3 => \^cr_int_reg[19]_0\(0),
O => \cr_int[19]_i_26_n_0\
);
\cr_int[19]_i_27\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \cr_int_reg[31]_i_49_n_6\,
I1 => \^cr_int_reg[27]_2\(0),
I2 => \cr_int_reg[11]_i_17_n_0\,
I3 => \rgb888[3]_0\(1),
O => \cr_int[19]_i_27_n_0\
);
\cr_int[19]_i_29\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
O => \cr_int[19]_i_29_n_0\
);
\cr_int[19]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cr_int[19]_i_12_n_0\,
I1 => \cr_int[19]_i_13_n_0\,
O => \cr_int[19]_i_3_n_0\
);
\cr_int[19]_i_30\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
O => \cr_int[19]_i_30_n_0\
);
\cr_int[19]_i_31\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
O => \cr_int[19]_i_31_n_0\
);
\cr_int[19]_i_32\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
O => \cr_int[19]_i_32_n_0\
);
\cr_int[19]_i_33\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
I1 => cr_int_reg7,
I2 => cr_int_reg6(24),
O => \cr_int[19]_i_33_n_0\
);
\cr_int[19]_i_34\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
I1 => cr_int_reg7,
I2 => cr_int_reg6(23),
O => \cr_int[19]_i_34_n_0\
);
\cr_int[19]_i_35\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
I1 => cr_int_reg7,
I2 => cr_int_reg6(22),
O => \cr_int[19]_i_35_n_0\
);
\cr_int[19]_i_36\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
I1 => cr_int_reg7,
I2 => cr_int_reg6(21),
O => \cr_int[19]_i_36_n_0\
);
\cr_int[19]_i_38\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[31]_2\(1),
O => \cr_int[19]_i_38_n_0\
);
\cr_int[19]_i_39\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[31]_2\(1),
O => \cr_int[19]_i_39_n_0\
);
\cr_int[19]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cr_int[19]_i_14_n_0\,
I1 => \cr_int[19]_i_15_n_0\,
O => \cr_int[19]_i_4_n_0\
);
\cr_int[19]_i_40\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[31]_2\(1),
O => \cr_int[19]_i_40_n_0\
);
\cr_int[19]_i_41\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[31]_2\(1),
O => \cr_int[19]_i_41_n_0\
);
\cr_int[19]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cr_int[19]_i_16_n_0\,
I1 => \cr_int[19]_i_17_n_0\,
O => \cr_int[19]_i_5_n_0\
);
\cr_int[19]_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cr_int[23]_i_16_n_0\,
I1 => \cr_int[23]_i_17_n_0\,
I2 => \cr_int[19]_i_2_n_0\,
O => \cr_int[19]_i_6_n_0\
);
\cr_int[19]_i_7\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cr_int[19]_i_10_n_0\,
I1 => \cr_int[19]_i_11_n_0\,
I2 => \cr_int[19]_i_3_n_0\,
O => \cr_int[19]_i_7_n_0\
);
\cr_int[19]_i_8\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cr_int[19]_i_12_n_0\,
I1 => \cr_int[19]_i_13_n_0\,
I2 => \cr_int[19]_i_4_n_0\,
O => \cr_int[19]_i_8_n_0\
);
\cr_int[19]_i_9\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cr_int[19]_i_14_n_0\,
I1 => \cr_int[19]_i_15_n_0\,
I2 => \cr_int[19]_i_5_n_0\,
O => \cr_int[19]_i_9_n_0\
);
\cr_int[23]_i_10\: unisim.vcomponents.LUT6
generic map(
INIT => X"F4040BFB0BFBF404"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(30),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(22),
I4 => \cr_int[27]_i_10_n_0\,
I5 => \cr_int[27]_i_11_n_0\,
O => \cr_int[23]_i_10_n_0\
);
\cr_int[23]_i_11\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(29),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(21),
I4 => \cr_int[23]_i_18_n_0\,
I5 => \cr_int[23]_i_19_n_0\,
O => \cr_int[23]_i_11_n_0\
);
\cr_int[23]_i_12\: unisim.vcomponents.LUT6
generic map(
INIT => X"F4040BFB0BFBF404"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(29),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(21),
I4 => \cr_int[23]_i_18_n_0\,
I5 => \cr_int[23]_i_19_n_0\,
O => \cr_int[23]_i_12_n_0\
);
\cr_int[23]_i_13\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(28),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(20),
I4 => \cr_int[23]_i_21_n_0\,
I5 => \cr_int[23]_i_22_n_0\,
O => \cr_int[23]_i_13_n_0\
);
\cr_int[23]_i_14\: unisim.vcomponents.LUT6
generic map(
INIT => X"F4040BFB0BFBF404"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(28),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(20),
I4 => \cr_int[23]_i_21_n_0\,
I5 => \cr_int[23]_i_22_n_0\,
O => \cr_int[23]_i_14_n_0\
);
\cr_int[23]_i_15\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(27),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(19),
I4 => \cr_int[23]_i_23_n_0\,
I5 => \cr_int[23]_i_24_n_0\,
O => \cr_int[23]_i_15_n_0\
);
\cr_int[23]_i_16\: unisim.vcomponents.LUT6
generic map(
INIT => X"F4040BFB0BFBF404"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(27),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(19),
I4 => \cr_int[23]_i_23_n_0\,
I5 => \cr_int[23]_i_24_n_0\,
O => \cr_int[23]_i_16_n_0\
);
\cr_int[23]_i_17\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(26),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(18),
I4 => \cr_int[23]_i_25_n_0\,
I5 => \cr_int[23]_i_26_n_0\,
O => \cr_int[23]_i_17_n_0\
);
\cr_int[23]_i_18\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_17\(0),
I1 => \^cr_int_reg[31]_2\(1),
I2 => \^cr_int_reg[3]_1\(0),
I3 => \^cr_int_reg[23]_0\(3),
O => \cr_int[23]_i_18_n_0\
);
\cr_int[23]_i_19\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \cr_int_reg[31]_i_8_n_7\,
I1 => \^cr_int_reg[27]_2\(0),
I2 => \cr_int_reg[11]_i_17_n_0\,
I3 => \rgb888[0]_6\(0),
O => \cr_int[23]_i_19_n_0\
);
\cr_int[23]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cr_int[23]_i_10_n_0\,
I1 => \cr_int[23]_i_11_n_0\,
O => \cr_int[23]_i_2_n_0\
);
\cr_int[23]_i_21\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_16\(3),
I1 => \^cr_int_reg[31]_2\(1),
I2 => \^cr_int_reg[3]_1\(0),
I3 => \^cr_int_reg[23]_0\(2),
O => \cr_int[23]_i_21_n_0\
);
\cr_int[23]_i_22\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \cr_int_reg[31]_i_21_n_4\,
I1 => \^cr_int_reg[27]_2\(0),
I2 => \cr_int_reg[11]_i_17_n_0\,
I3 => \rgb888[0]_5\(3),
O => \cr_int[23]_i_22_n_0\
);
\cr_int[23]_i_23\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_16\(2),
I1 => \^cr_int_reg[31]_2\(1),
I2 => \^cr_int_reg[3]_1\(0),
I3 => \^cr_int_reg[23]_0\(1),
O => \cr_int[23]_i_23_n_0\
);
\cr_int[23]_i_24\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \cr_int_reg[31]_i_21_n_5\,
I1 => \^cr_int_reg[27]_2\(0),
I2 => \cr_int_reg[11]_i_17_n_0\,
I3 => \rgb888[0]_5\(2),
O => \cr_int[23]_i_24_n_0\
);
\cr_int[23]_i_25\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_16\(1),
I1 => \^cr_int_reg[31]_2\(1),
I2 => \^cr_int_reg[3]_1\(0),
I3 => \^cr_int_reg[23]_0\(0),
O => \cr_int[23]_i_25_n_0\
);
\cr_int[23]_i_26\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \cr_int_reg[31]_i_21_n_6\,
I1 => \^cr_int_reg[27]_2\(0),
I2 => \cr_int_reg[11]_i_17_n_0\,
I3 => \rgb888[0]_5\(1),
O => \cr_int[23]_i_26_n_0\
);
\cr_int[23]_i_27\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
O => \cr_int[23]_i_27_n_0\
);
\cr_int[23]_i_28\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
O => \cr_int[23]_i_28_n_0\
);
\cr_int[23]_i_29\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
O => \cr_int[23]_i_29_n_0\
);
\cr_int[23]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cr_int[23]_i_12_n_0\,
I1 => \cr_int[23]_i_13_n_0\,
O => \cr_int[23]_i_3_n_0\
);
\cr_int[23]_i_30\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
O => \cr_int[23]_i_30_n_0\
);
\cr_int[23]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cr_int[23]_i_14_n_0\,
I1 => \cr_int[23]_i_15_n_0\,
O => \cr_int[23]_i_4_n_0\
);
\cr_int[23]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cr_int[23]_i_16_n_0\,
I1 => \cr_int[23]_i_17_n_0\,
O => \cr_int[23]_i_5_n_0\
);
\cr_int[23]_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cr_int[27]_i_7_n_0\,
I1 => \cr_int[27]_i_8_n_0\,
I2 => \cr_int[23]_i_2_n_0\,
O => \cr_int[23]_i_6_n_0\
);
\cr_int[23]_i_7\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cr_int[23]_i_10_n_0\,
I1 => \cr_int[23]_i_11_n_0\,
I2 => \cr_int[23]_i_3_n_0\,
O => \cr_int[23]_i_7_n_0\
);
\cr_int[23]_i_8\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cr_int[23]_i_12_n_0\,
I1 => \cr_int[23]_i_13_n_0\,
I2 => \cr_int[23]_i_4_n_0\,
O => \cr_int[23]_i_8_n_0\
);
\cr_int[23]_i_9\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cr_int[23]_i_14_n_0\,
I1 => \cr_int[23]_i_15_n_0\,
I2 => \cr_int[23]_i_5_n_0\,
O => \cr_int[23]_i_9_n_0\
);
\cr_int[27]_i_10\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_17\(1),
I1 => \^cr_int_reg[31]_2\(1),
I2 => \^cr_int_reg[3]_1\(0),
I3 => \^cr_int_reg[23]_1\(0),
O => \cr_int[27]_i_10_n_0\
);
\cr_int[27]_i_11\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \cr_int_reg[31]_i_8_n_6\,
I1 => \^cr_int_reg[27]_2\(0),
I2 => \cr_int_reg[11]_i_17_n_0\,
I3 => \rgb888[0]_6\(1),
O => \cr_int[27]_i_11_n_0\
);
\cr_int[27]_i_12\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
O => \cr_int[27]_i_12_n_0\
);
\cr_int[27]_i_13\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
O => \cr_int[27]_i_13_n_0\
);
\cr_int[27]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cr_int[27]_i_7_n_0\,
I1 => \cr_int[27]_i_8_n_0\,
O => \cr_int[27]_i_2_n_0\
);
\cr_int[27]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"6555559A65556555"
)
port map (
I0 => \cr_int[31]_i_2_n_0\,
I1 => \cr_int_reg[31]_i_12_n_1\,
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => \cr_int[31]_i_13_n_0\,
I4 => \cr_int_reg[31]_i_8_n_1\,
I5 => \^cr_int_reg[27]_2\(0),
O => \cr_int[27]_i_3_n_0\
);
\cr_int[27]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"6555559A65556555"
)
port map (
I0 => \cr_int[31]_i_2_n_0\,
I1 => \cr_int_reg[31]_i_12_n_1\,
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => \cr_int[31]_i_13_n_0\,
I4 => \cr_int_reg[31]_i_8_n_1\,
I5 => \^cr_int_reg[27]_2\(0),
O => \cr_int[27]_i_4_n_0\
);
\cr_int[27]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"6555559A65556555"
)
port map (
I0 => \cr_int[31]_i_2_n_0\,
I1 => \cr_int_reg[31]_i_12_n_1\,
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => \cr_int[31]_i_13_n_0\,
I4 => \cr_int_reg[31]_i_8_n_1\,
I5 => \^cr_int_reg[27]_2\(0),
O => \cr_int[27]_i_5_n_0\
);
\cr_int[27]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"6555559A65556555"
)
port map (
I0 => \cr_int[27]_i_2_n_0\,
I1 => \cr_int_reg[31]_i_12_n_1\,
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => \cr_int[31]_i_13_n_0\,
I4 => \cr_int_reg[31]_i_8_n_1\,
I5 => \^cr_int_reg[27]_2\(0),
O => \cr_int[27]_i_6_n_0\
);
\cr_int[27]_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"4B44B4BB4B444B44"
)
port map (
I0 => \cr_int_reg[31]_i_12_n_1\,
I1 => \cr_int_reg[31]_i_11_n_4\,
I2 => \rgb888[8]_18\(0),
I3 => \^cr_int_reg[31]_2\(1),
I4 => \cr_int_reg[31]_i_8_n_1\,
I5 => \^cr_int_reg[27]_2\(0),
O => \cr_int[27]_i_7_n_0\
);
\cr_int[27]_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(30),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(22),
I4 => \cr_int[27]_i_10_n_0\,
I5 => \cr_int[27]_i_11_n_0\,
O => \cr_int[27]_i_8_n_0\
);
\cr_int[31]_i_100\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFF80000000"
)
port map (
I0 => rgb888(13),
I1 => rgb888(11),
I2 => rgb888(10),
I3 => rgb888(12),
I4 => rgb888(14),
I5 => rgb888(15),
O => \cr_int[31]_i_100_n_0\
);
\cr_int[31]_i_103\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(15),
O => \cr_int[31]_i_103_n_0\
);
\cr_int[31]_i_108\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[31]_2\(1),
O => \cr_int[31]_i_108_n_0\
);
\cr_int[31]_i_109\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[31]_2\(1),
O => \cr_int[31]_i_109_n_0\
);
\cr_int[31]_i_110\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[31]_2\(1),
O => \cr_int[31]_i_110_n_0\
);
\cr_int[31]_i_111\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[31]_2\(1),
O => \cr_int[31]_i_111_n_0\
);
\cr_int[31]_i_112\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[31]_2\(1),
O => \cr_int[31]_i_112_n_0\
);
\cr_int[31]_i_113\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(4),
I1 => rgb888(2),
O => \cr_int[31]_i_113_n_0\
);
\cr_int[31]_i_114\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(3),
I1 => rgb888(1),
O => \cr_int[31]_i_114_n_0\
);
\cr_int[31]_i_115\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(2),
I1 => rgb888(0),
O => \cr_int[31]_i_115_n_0\
);
\cr_int[31]_i_116\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => rgb888(1),
O => \cr_int[31]_i_116_n_0\
);
\cr_int[31]_i_117\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(6),
O => \cr_int[31]_i_117_n_0\
);
\cr_int[31]_i_118\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(7),
I1 => rgb888(5),
O => \cr_int[31]_i_118_n_0\
);
\cr_int[31]_i_119\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(6),
I1 => rgb888(4),
O => \cr_int[31]_i_119_n_0\
);
\cr_int[31]_i_120\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(5),
I1 => rgb888(3),
O => \cr_int[31]_i_120_n_0\
);
\cr_int[31]_i_121\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(15),
O => \cr_int[31]_i_121_n_0\
);
\cr_int[31]_i_122\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(15),
I1 => rgb888(14),
O => \cr_int[31]_i_122_n_0\
);
\cr_int[31]_i_123\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(14),
O => \cr_int[31]_i_123_n_0\
);
\cr_int[31]_i_124\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(15),
I1 => rgb888(13),
O => \cr_int[31]_i_124_n_0\
);
\cr_int[31]_i_125\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(14),
I1 => rgb888(12),
O => \cr_int[31]_i_125_n_0\
);
\cr_int[31]_i_126\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(13),
I1 => rgb888(11),
O => \cr_int[31]_i_126_n_0\
);
\cr_int[31]_i_13\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \rgb888[8]_18\(0),
I1 => \^cr_int_reg[31]_2\(1),
O => \cr_int[31]_i_13_n_0\
);
\cr_int[31]_i_15\: unisim.vcomponents.LUT3
generic map(
INIT => X"60"
)
port map (
I0 => \^cr_int_reg[27]_0\,
I1 => rgb888(7),
I2 => \cr_int_reg[31]_i_48_n_2\,
O => \cr_int[31]_i_15_n_0\
);
\cr_int[31]_i_16\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[27]_1\(1),
I1 => \cr_int_reg[31]_i_48_n_2\,
O => \cr_int[31]_i_16_n_0\
);
\cr_int[31]_i_17\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => rgb888(7),
I1 => \^cr_int_reg[27]_0\,
O => \cr_int[31]_i_17_n_0\
);
\cr_int[31]_i_18\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => rgb888(7),
I1 => \^cr_int_reg[27]_0\,
O => \cr_int[31]_i_18_n_0\
);
\cr_int[31]_i_19\: unisim.vcomponents.LUT3
generic map(
INIT => X"17"
)
port map (
I0 => \cr_int_reg[31]_i_48_n_2\,
I1 => \^cr_int_reg[27]_0\,
I2 => rgb888(7),
O => \cr_int[31]_i_19_n_0\
);
\cr_int[31]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000DD0D0000"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
I1 => \cr_int_reg[31]_i_8_n_1\,
I2 => \^cr_int_reg[31]_2\(1),
I3 => \rgb888[8]_18\(0),
I4 => \cr_int_reg[31]_i_11_n_4\,
I5 => \cr_int_reg[31]_i_12_n_1\,
O => \cr_int[31]_i_2_n_0\
);
\cr_int[31]_i_20\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \^cr_int_reg[27]_0\,
I1 => rgb888(7),
I2 => \cr_int[31]_i_16_n_0\,
I3 => \cr_int_reg[31]_i_48_n_2\,
O => \cr_int[31]_i_20_n_0\
);
\cr_int[31]_i_22\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
I1 => \cr_int_reg[11]_i_17_n_0\,
I2 => \rgb888[0]_6\(1),
O => \cr_int[31]_i_22_n_0\
);
\cr_int[31]_i_23\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
I1 => \cr_int_reg[11]_i_17_n_0\,
I2 => \rgb888[0]_6\(0),
O => \cr_int[31]_i_23_n_0\
);
\cr_int[31]_i_25\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFFFFFFFFFF"
)
port map (
I0 => rgb888(15),
I1 => rgb888(13),
I2 => rgb888(11),
I3 => rgb888(10),
I4 => rgb888(12),
I5 => rgb888(14),
O => \cr_int[31]_i_25_n_0\
);
\cr_int[31]_i_26\: unisim.vcomponents.LUT2
generic map(
INIT => X"4"
)
port map (
I0 => \cr_int_reg[31]_i_63_n_2\,
I1 => \^di\(0),
O => \cr_int[31]_i_26_n_0\
);
\cr_int[31]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"6555559A65556555"
)
port map (
I0 => \cr_int[31]_i_2_n_0\,
I1 => \cr_int_reg[31]_i_12_n_1\,
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => \cr_int[31]_i_13_n_0\,
I4 => \cr_int_reg[31]_i_8_n_1\,
I5 => \^cr_int_reg[27]_2\(0),
O => \cr_int[31]_i_3_n_0\
);
\cr_int[31]_i_31\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAAAAAAAAA9"
)
port map (
I0 => rgb888(22),
I1 => rgb888(20),
I2 => rgb888(18),
I3 => rgb888(17),
I4 => rgb888(19),
I5 => rgb888(21),
O => \cr_int[31]_i_31_n_0\
);
\cr_int[31]_i_32\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => rgb888(23),
I1 => \cr_int[31]_i_79_n_0\,
O => \cr_int[31]_i_32_n_0\
);
\cr_int[31]_i_33\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => rgb888(23),
I1 => \cr_int[31]_i_79_n_0\,
O => \cr_int[31]_i_33_n_0\
);
\cr_int[31]_i_34\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => rgb888(23),
I1 => \cr_int[31]_i_79_n_0\,
O => \cr_int[31]_i_34_n_0\
);
\cr_int[31]_i_35\: unisim.vcomponents.LUT3
generic map(
INIT => X"95"
)
port map (
I0 => rgb888(23),
I1 => \cr_int[31]_i_80_n_0\,
I2 => rgb888(22),
O => \cr_int[31]_i_35_n_0\
);
\cr_int[31]_i_37\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
I1 => cr_int_reg7,
I2 => cr_int_reg6(30),
O => \cr_int[31]_i_37_n_0\
);
\cr_int[31]_i_38\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
I1 => cr_int_reg7,
I2 => cr_int_reg6(29),
O => \cr_int[31]_i_38_n_0\
);
\cr_int[31]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"6555559A65556555"
)
port map (
I0 => \cr_int[31]_i_2_n_0\,
I1 => \cr_int_reg[31]_i_12_n_1\,
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => \cr_int[31]_i_13_n_0\,
I4 => \cr_int_reg[31]_i_8_n_1\,
I5 => \^cr_int_reg[27]_2\(0),
O => \cr_int[31]_i_4_n_0\
);
\cr_int[31]_i_40\: unisim.vcomponents.LUT6
generic map(
INIT => X"8888888888888882"
)
port map (
I0 => \cr_int_reg[31]_i_48_n_7\,
I1 => rgb888(5),
I2 => rgb888(3),
I3 => rgb888(1),
I4 => rgb888(2),
I5 => rgb888(4),
O => \cr_int[31]_i_40_n_0\
);
\cr_int[31]_i_41\: unisim.vcomponents.LUT5
generic map(
INIT => X"EEEEEEEB"
)
port map (
I0 => \cr_int_reg[31]_i_91_n_4\,
I1 => rgb888(4),
I2 => rgb888(2),
I3 => rgb888(1),
I4 => rgb888(3),
O => \cr_int[31]_i_41_n_0\
);
\cr_int[31]_i_42\: unisim.vcomponents.LUT5
generic map(
INIT => X"99999996"
)
port map (
I0 => \cr_int_reg[31]_i_91_n_4\,
I1 => rgb888(4),
I2 => rgb888(2),
I3 => rgb888(1),
I4 => rgb888(3),
O => \cr_int[31]_i_42_n_0\
);
\cr_int[31]_i_43\: unisim.vcomponents.LUT3
generic map(
INIT => X"82"
)
port map (
I0 => \cr_int_reg[31]_i_91_n_6\,
I1 => rgb888(2),
I2 => rgb888(1),
O => \cr_int[31]_i_43_n_0\
);
\cr_int[31]_i_44\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \^cr_int_reg[27]_1\(1),
I1 => \cr_int_reg[31]_i_48_n_2\,
I2 => \cr_int[31]_i_40_n_0\,
O => \cr_int[31]_i_44_n_0\
);
\cr_int[31]_i_45\: unisim.vcomponents.LUT4
generic map(
INIT => X"1EE1"
)
port map (
I0 => \cr_int[31]_i_92_n_0\,
I1 => \cr_int_reg[31]_i_91_n_4\,
I2 => \^cr_int_reg[27]_1\(0),
I3 => \cr_int_reg[31]_i_48_n_7\,
O => \cr_int[31]_i_45_n_0\
);
\cr_int[31]_i_46\: unisim.vcomponents.LUT6
generic map(
INIT => X"6969699999999996"
)
port map (
I0 => rgb888(4),
I1 => \cr_int_reg[31]_i_91_n_4\,
I2 => \cr_int_reg[31]_i_91_n_5\,
I3 => rgb888(2),
I4 => rgb888(1),
I5 => rgb888(3),
O => \cr_int[31]_i_46_n_0\
);
\cr_int[31]_i_47\: unisim.vcomponents.LUT5
generic map(
INIT => X"817E7E81"
)
port map (
I0 => \cr_int_reg[31]_i_91_n_6\,
I1 => rgb888(2),
I2 => rgb888(1),
I3 => rgb888(3),
I4 => \cr_int_reg[31]_i_91_n_5\,
O => \cr_int[31]_i_47_n_0\
);
\cr_int[31]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"6555559A65556555"
)
port map (
I0 => \cr_int[31]_i_2_n_0\,
I1 => \cr_int_reg[31]_i_12_n_1\,
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => \cr_int[31]_i_13_n_0\,
I4 => \cr_int_reg[31]_i_8_n_1\,
I5 => \^cr_int_reg[27]_2\(0),
O => \cr_int[31]_i_5_n_0\
);
\cr_int[31]_i_50\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
I1 => \cr_int_reg[11]_i_17_n_0\,
I2 => \rgb888[0]_5\(3),
O => \cr_int[31]_i_50_n_0\
);
\cr_int[31]_i_51\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
I1 => \cr_int_reg[11]_i_17_n_0\,
I2 => \rgb888[0]_5\(2),
O => \cr_int[31]_i_51_n_0\
);
\cr_int[31]_i_52\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
I1 => \cr_int_reg[11]_i_17_n_0\,
I2 => \rgb888[0]_5\(1),
O => \cr_int[31]_i_52_n_0\
);
\cr_int[31]_i_53\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
I1 => \cr_int_reg[11]_i_17_n_0\,
I2 => \rgb888[0]_5\(0),
O => \cr_int[31]_i_53_n_0\
);
\cr_int[31]_i_55\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \cr_int[31]_i_100_n_0\,
I1 => \cr_int_reg[31]_i_63_n_2\,
O => \cr_int[31]_i_55_n_0\
);
\cr_int[31]_i_56\: unisim.vcomponents.LUT6
generic map(
INIT => X"6AAAAAAA00000000"
)
port map (
I0 => rgb888(14),
I1 => rgb888(13),
I2 => rgb888(11),
I3 => rgb888(10),
I4 => rgb888(12),
I5 => \cr_int_reg[31]_i_63_n_7\,
O => \cr_int[31]_i_56_n_0\
);
\cr_int[31]_i_57\: unisim.vcomponents.LUT6
generic map(
INIT => X"BFFFEAAA2AAA8000"
)
port map (
I0 => \cr_int_reg[31]_i_101_n_1\,
I1 => rgb888(11),
I2 => rgb888(10),
I3 => rgb888(12),
I4 => rgb888(13),
I5 => \cr_int_reg[31]_i_102_n_4\,
O => \cr_int[31]_i_57_n_0\
);
\cr_int[31]_i_58\: unisim.vcomponents.LUT5
generic map(
INIT => X"BFEA2A80"
)
port map (
I0 => \cr_int_reg[31]_i_101_n_6\,
I1 => rgb888(10),
I2 => rgb888(11),
I3 => rgb888(12),
I4 => \cr_int_reg[31]_i_102_n_5\,
O => \cr_int[31]_i_58_n_0\
);
\cr_int[31]_i_59\: unisim.vcomponents.LUT3
generic map(
INIT => X"36"
)
port map (
I0 => \cr_int[31]_i_100_n_0\,
I1 => \^di\(0),
I2 => \cr_int_reg[31]_i_63_n_2\,
O => \cr_int[31]_i_59_n_0\
);
\cr_int[31]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"6555559A65556555"
)
port map (
I0 => \cr_int[31]_i_2_n_0\,
I1 => \cr_int_reg[31]_i_12_n_1\,
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => \cr_int[31]_i_13_n_0\,
I4 => \cr_int_reg[31]_i_8_n_1\,
I5 => \^cr_int_reg[27]_2\(0),
O => \cr_int[31]_i_6_n_0\
);
\cr_int[31]_i_60\: unisim.vcomponents.LUT4
generic map(
INIT => X"7887"
)
port map (
I0 => \cr_int_reg[31]_i_63_n_7\,
I1 => \^cr_int_reg[31]_0\,
I2 => \cr_int_reg[31]_i_63_n_2\,
I3 => \cr_int[31]_i_100_n_0\,
O => \cr_int[31]_i_60_n_0\
);
\cr_int[31]_i_61\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cr_int[31]_i_57_n_0\,
I1 => \^cr_int_reg[31]_0\,
I2 => \cr_int_reg[31]_i_63_n_7\,
O => \cr_int[31]_i_61_n_0\
);
\cr_int[31]_i_62\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \cr_int[31]_i_58_n_0\,
I1 => \cr_int_reg[31]_i_102_n_4\,
I2 => \^cr_int_reg[31]_1\,
I3 => \cr_int_reg[31]_i_101_n_1\,
O => \cr_int[31]_i_62_n_0\
);
\cr_int[31]_i_71\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000001FFFFFFFE"
)
port map (
I0 => rgb888(21),
I1 => rgb888(19),
I2 => rgb888(17),
I3 => rgb888(18),
I4 => rgb888(20),
I5 => rgb888(22),
O => \cr_int[31]_i_71_n_0\
);
\cr_int[31]_i_72\: unisim.vcomponents.LUT5
generic map(
INIT => X"0001FFFE"
)
port map (
I0 => rgb888(20),
I1 => rgb888(18),
I2 => rgb888(17),
I3 => rgb888(19),
I4 => rgb888(21),
O => \cr_int[31]_i_72_n_0\
);
\cr_int[31]_i_73\: unisim.vcomponents.LUT5
generic map(
INIT => X"99999996"
)
port map (
I0 => \cr_int_reg[3]_i_26_n_1\,
I1 => rgb888(20),
I2 => rgb888(18),
I3 => rgb888(17),
I4 => rgb888(19),
O => \cr_int[31]_i_73_n_0\
);
\cr_int[31]_i_74\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(18),
I1 => rgb888(17),
O => \cr_int[31]_i_74_n_0\
);
\cr_int[31]_i_75\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAA955555555"
)
port map (
I0 => rgb888(22),
I1 => rgb888(20),
I2 => rgb888(18),
I3 => rgb888(17),
I4 => rgb888(19),
I5 => rgb888(21),
O => \cr_int[31]_i_75_n_0\
);
\cr_int[31]_i_76\: unisim.vcomponents.LUT6
generic map(
INIT => X"CCCCCCC999999993"
)
port map (
I0 => \cr_int_reg[3]_i_26_n_1\,
I1 => rgb888(21),
I2 => rgb888(19),
I3 => rgb888(17),
I4 => rgb888(18),
I5 => rgb888(20),
O => \cr_int[31]_i_76_n_0\
);
\cr_int[31]_i_77\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAA99995"
)
port map (
I0 => rgb888(20),
I1 => \cr_int_reg[3]_i_26_n_1\,
I2 => rgb888(18),
I3 => rgb888(17),
I4 => rgb888(19),
O => \cr_int[31]_i_77_n_0\
);
\cr_int[31]_i_78\: unisim.vcomponents.LUT4
generic map(
INIT => X"6A95"
)
port map (
I0 => \cr_int_reg[3]_i_26_n_1\,
I1 => rgb888(18),
I2 => rgb888(17),
I3 => rgb888(19),
O => \cr_int[31]_i_78_n_0\
);
\cr_int[31]_i_79\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => rgb888(21),
I1 => rgb888(19),
I2 => rgb888(17),
I3 => rgb888(18),
I4 => rgb888(20),
I5 => rgb888(22),
O => \cr_int[31]_i_79_n_0\
);
\cr_int[31]_i_80\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => rgb888(20),
I1 => rgb888(18),
I2 => rgb888(17),
I3 => rgb888(19),
I4 => rgb888(21),
O => \cr_int[31]_i_80_n_0\
);
\cr_int[31]_i_81\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
I1 => cr_int_reg7,
I2 => cr_int_reg6(28),
O => \cr_int[31]_i_81_n_0\
);
\cr_int[31]_i_82\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
I1 => cr_int_reg7,
I2 => cr_int_reg6(27),
O => \cr_int[31]_i_82_n_0\
);
\cr_int[31]_i_83\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
I1 => cr_int_reg7,
I2 => cr_int_reg6(26),
O => \cr_int[31]_i_83_n_0\
);
\cr_int[31]_i_84\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
I1 => cr_int_reg7,
I2 => cr_int_reg6(25),
O => \cr_int[31]_i_84_n_0\
);
\cr_int[31]_i_85\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(1),
O => \cr_int[31]_i_85_n_0\
);
\cr_int[31]_i_87\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(2),
I1 => \cr_int_reg[31]_i_91_n_6\,
O => \cr_int[31]_i_87_n_0\
);
\cr_int[31]_i_88\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(1),
I1 => \cr_int_reg[31]_i_91_n_7\,
O => \cr_int[31]_i_88_n_0\
);
\cr_int[31]_i_89\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \cr_int_reg[31]_i_86_n_4\,
I1 => rgb888(0),
O => \cr_int[31]_i_89_n_0\
);
\cr_int[31]_i_90\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cr_int_reg[31]_i_86_n_5\,
O => \cr_int[31]_i_90_n_0\
);
\cr_int[31]_i_92\: unisim.vcomponents.LUT4
generic map(
INIT => X"FE01"
)
port map (
I0 => rgb888(3),
I1 => rgb888(1),
I2 => rgb888(2),
I3 => rgb888(4),
O => \cr_int[31]_i_92_n_0\
);
\cr_int[31]_i_93\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(7),
O => \cr_int[31]_i_93_n_0\
);
\cr_int[31]_i_94\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
I1 => \cr_int_reg[11]_i_17_n_0\,
I2 => \rgb888[3]_0\(3),
O => \cr_int[31]_i_94_n_0\
);
\cr_int[31]_i_95\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
I1 => \cr_int_reg[11]_i_17_n_0\,
I2 => \rgb888[3]_0\(2),
O => \cr_int[31]_i_95_n_0\
);
\cr_int[31]_i_96\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
I1 => \cr_int_reg[11]_i_17_n_0\,
I2 => \rgb888[3]_0\(1),
O => \cr_int[31]_i_96_n_0\
);
\cr_int[31]_i_97\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
I1 => \cr_int_reg[11]_i_17_n_0\,
I2 => \rgb888[3]_0\(0),
O => \cr_int[31]_i_97_n_0\
);
\cr_int[3]_i_10\: unisim.vcomponents.LUT5
generic map(
INIT => X"44477747"
)
port map (
I0 => \rgb888[8]_12\(1),
I1 => \^cr_int_reg[31]_2\(1),
I2 => \^cr_int_reg[7]_1\(0),
I3 => \^cr_int_reg[3]_1\(0),
I4 => \^cr_int_reg[3]_0\(2),
O => \cr_int[3]_i_10_n_0\
);
\cr_int[3]_i_11\: unisim.vcomponents.LUT5
generic map(
INIT => X"44477747"
)
port map (
I0 => \cr_int_reg[11]_i_31_n_6\,
I1 => \^cr_int_reg[27]_2\(0),
I2 => \cr_int_reg[11]_i_41_n_6\,
I3 => \cr_int_reg[11]_i_17_n_0\,
I4 => \cr_int_reg[31]_i_14_n_4\,
O => \cr_int[3]_i_11_n_0\
);
\cr_int[3]_i_12\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => cr_int_reg4(1),
I1 => \cr_int_reg[31]_i_11_n_4\,
I2 => \cr_int_reg[3]_i_16_n_4\,
I3 => cr_int_reg7,
I4 => cr_int_reg6(9),
O => \cr_int_reg3__0\(1)
);
\cr_int[3]_i_13\: unisim.vcomponents.LUT5
generic map(
INIT => X"44477747"
)
port map (
I0 => \rgb888[8]_12\(0),
I1 => \^cr_int_reg[31]_2\(1),
I2 => \^cr_int_reg[3]_2\(1),
I3 => \^cr_int_reg[3]_1\(0),
I4 => \^cr_int_reg[3]_0\(1),
O => \cr_int[3]_i_13_n_0\
);
\cr_int[3]_i_14\: unisim.vcomponents.LUT5
generic map(
INIT => X"44477747"
)
port map (
I0 => \cr_int_reg[11]_i_31_n_7\,
I1 => \^cr_int_reg[27]_2\(0),
I2 => \cr_int_reg[11]_i_41_n_7\,
I3 => \cr_int_reg[11]_i_17_n_0\,
I4 => \cr_int_reg[31]_i_14_n_5\,
O => \cr_int[3]_i_14_n_0\
);
\cr_int[3]_i_17\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^cr_int_reg[3]_0\(0),
I1 => \^cr_int_reg[3]_1\(0),
I2 => \^cr_int_reg[3]_2\(0),
O => \cr_int[3]_i_17_n_0\
);
\cr_int[3]_i_18\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cr_int_reg[31]_i_14_n_6\,
I1 => \cr_int_reg[11]_i_17_n_0\,
I2 => \cr_int_reg[3]_i_32_n_4\,
O => \cr_int[3]_i_18_n_0\
);
\cr_int[3]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \cr_int_reg3__0\(2),
I1 => \cr_int[3]_i_10_n_0\,
I2 => \cr_int[3]_i_11_n_0\,
O => \cr_int[3]_i_2_n_0\
);
\cr_int[3]_i_22\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[3]_i_16_n_5\,
O => \cr_int[3]_i_22_n_0\
);
\cr_int[3]_i_23\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[3]_i_16_n_6\,
O => \cr_int[3]_i_23_n_0\
);
\cr_int[3]_i_24\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[3]_i_16_n_7\,
O => \cr_int[3]_i_24_n_0\
);
\cr_int[3]_i_25\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[3]_i_27_n_6\,
O => \cr_int[3]_i_25_n_0\
);
\cr_int[3]_i_28\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => rgb888(18),
I1 => rgb888(17),
I2 => \cr_int_reg[3]_i_26_n_6\,
O => \cr_int[3]_i_28_n_0\
);
\cr_int[3]_i_29\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \cr_int_reg[3]_i_26_n_7\,
I1 => rgb888(17),
O => \cr_int[3]_i_29_n_0\
);
\cr_int[3]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \cr_int_reg3__0\(1),
I1 => \cr_int[3]_i_13_n_0\,
I2 => \cr_int[3]_i_14_n_0\,
O => \cr_int[3]_i_3_n_0\
);
\cr_int[3]_i_30\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \cr_int_reg[3]_i_27_n_4\,
I1 => rgb888(16),
O => \cr_int[3]_i_30_n_0\
);
\cr_int[3]_i_31\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cr_int_reg[3]_i_27_n_5\,
O => \cr_int[3]_i_31_n_0\
);
\cr_int[3]_i_34\: unisim.vcomponents.LUT4
generic map(
INIT => X"BE28"
)
port map (
I0 => \cr_int_reg[31]_i_101_n_7\,
I1 => rgb888(10),
I2 => rgb888(11),
I3 => \cr_int_reg[31]_i_102_n_6\,
O => \cr_int[3]_i_34_n_0\
);
\cr_int[3]_i_35\: unisim.vcomponents.LUT3
generic map(
INIT => X"D4"
)
port map (
I0 => rgb888(10),
I1 => \cr_int_reg[3]_i_64_n_4\,
I2 => \cr_int_reg[31]_i_102_n_7\,
O => \cr_int[3]_i_35_n_0\
);
\cr_int[3]_i_36\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \cr_int_reg[3]_i_64_n_5\,
I1 => rgb888(9),
I2 => \cr_int_reg[3]_i_70_n_4\,
O => \cr_int[3]_i_36_n_0\
);
\cr_int[3]_i_37\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cr_int_reg[3]_i_64_n_5\,
I1 => rgb888(9),
I2 => \cr_int_reg[3]_i_70_n_4\,
O => \cr_int[3]_i_37_n_0\
);
\cr_int[3]_i_38\: unisim.vcomponents.LUT6
generic map(
INIT => X"9669696969969696"
)
port map (
I0 => \cr_int[3]_i_34_n_0\,
I1 => \cr_int_reg[31]_i_102_n_5\,
I2 => rgb888(12),
I3 => rgb888(11),
I4 => rgb888(10),
I5 => \cr_int_reg[31]_i_101_n_6\,
O => \cr_int[3]_i_38_n_0\
);
\cr_int[3]_i_39\: unisim.vcomponents.LUT5
generic map(
INIT => X"96696996"
)
port map (
I0 => \cr_int_reg[31]_i_101_n_7\,
I1 => rgb888(10),
I2 => rgb888(11),
I3 => \cr_int_reg[31]_i_102_n_6\,
I4 => \cr_int[3]_i_35_n_0\,
O => \cr_int[3]_i_39_n_0\
);
\cr_int[3]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"00E2E2FF"
)
port map (
I0 => cr_int_reg6(8),
I1 => cr_int_reg7,
I2 => \cr_int_reg[3]_i_16_n_5\,
I3 => \cr_int[3]_i_17_n_0\,
I4 => \cr_int[3]_i_18_n_0\,
O => \cr_int[3]_i_4_n_0\
);
\cr_int[3]_i_40\: unisim.vcomponents.LUT6
generic map(
INIT => X"E81717E817E8E817"
)
port map (
I0 => \cr_int_reg[3]_i_70_n_4\,
I1 => rgb888(9),
I2 => \cr_int_reg[3]_i_64_n_5\,
I3 => \cr_int_reg[31]_i_102_n_7\,
I4 => rgb888(10),
I5 => \cr_int_reg[3]_i_64_n_4\,
O => \cr_int[3]_i_40_n_0\
);
\cr_int[3]_i_41\: unisim.vcomponents.LUT5
generic map(
INIT => X"69969696"
)
port map (
I0 => \cr_int_reg[3]_i_70_n_4\,
I1 => rgb888(9),
I2 => \cr_int_reg[3]_i_64_n_5\,
I3 => \cr_int_reg[3]_i_70_n_5\,
I4 => rgb888(8),
O => \cr_int[3]_i_41_n_0\
);
\cr_int[3]_i_43\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[3]_0\(1),
O => \cr_int[3]_i_43_n_0\
);
\cr_int[3]_i_44\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[3]_0\(0),
O => \cr_int[3]_i_44_n_0\
);
\cr_int[3]_i_45\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[3]_i_19_n_7\,
O => \cr_int[3]_i_45_n_0\
);
\cr_int[3]_i_46\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[3]_i_33_n_4\,
O => \cr_int[3]_i_46_n_0\
);
\cr_int[3]_i_47\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[3]_i_54_n_7\,
O => \cr_int[3]_i_47_n_0\
);
\cr_int[3]_i_48\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[3]_i_27_n_7\,
O => \cr_int[3]_i_48_n_0\
);
\cr_int[3]_i_49\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[3]_i_54_n_4\,
O => \cr_int[3]_i_49_n_0\
);
\cr_int[3]_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \cr_int_reg3__0\(3),
I1 => \cr_int[7]_i_17_n_0\,
I2 => \cr_int[7]_i_18_n_0\,
I3 => \cr_int[3]_i_2_n_0\,
O => \cr_int[3]_i_5_n_0\
);
\cr_int[3]_i_50\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[3]_i_54_n_5\,
O => \cr_int[3]_i_50_n_0\
);
\cr_int[3]_i_51\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[3]_i_54_n_6\,
O => \cr_int[3]_i_51_n_0\
);
\cr_int[3]_i_52\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(23),
O => \cr_int[3]_i_52_n_0\
);
\cr_int[3]_i_53\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => rgb888(22),
O => \cr_int[3]_i_53_n_0\
);
\cr_int[3]_i_55\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(21),
I1 => rgb888(23),
O => \cr_int[3]_i_55_n_0\
);
\cr_int[3]_i_56\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(20),
I1 => rgb888(22),
O => \cr_int[3]_i_56_n_0\
);
\cr_int[3]_i_57\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(19),
I1 => rgb888(21),
O => \cr_int[3]_i_57_n_0\
);
\cr_int[3]_i_58\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(18),
I1 => rgb888(20),
O => \cr_int[3]_i_58_n_0\
);
\cr_int[3]_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \cr_int_reg3__0\(2),
I1 => \cr_int[3]_i_10_n_0\,
I2 => \cr_int[3]_i_11_n_0\,
I3 => \cr_int[3]_i_3_n_0\,
O => \cr_int[3]_i_6_n_0\
);
\cr_int[3]_i_60\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_14_n_6\,
O => \cr_int[3]_i_60_n_0\
);
\cr_int[3]_i_61\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_14_n_7\,
O => \cr_int[3]_i_61_n_0\
);
\cr_int[3]_i_62\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_39_n_4\,
O => \cr_int[3]_i_62_n_0\
);
\cr_int[3]_i_63\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_39_n_5\,
O => \cr_int[3]_i_63_n_0\
);
\cr_int[3]_i_66\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => rgb888(8),
I1 => \cr_int_reg[3]_i_70_n_5\,
I2 => \cr_int_reg[3]_i_64_n_6\,
O => \cr_int[3]_i_66_n_0\
);
\cr_int[3]_i_67\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \cr_int_reg[3]_i_64_n_7\,
I1 => \cr_int_reg[3]_i_70_n_6\,
O => \cr_int[3]_i_67_n_0\
);
\cr_int[3]_i_68\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \cr_int_reg[3]_i_65_n_4\,
I1 => \cr_int_reg[3]_i_70_n_7\,
O => \cr_int[3]_i_68_n_0\
);
\cr_int[3]_i_69\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \cr_int_reg[3]_i_65_n_5\,
I1 => rgb888(8),
O => \cr_int[3]_i_69_n_0\
);
\cr_int[3]_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \cr_int_reg3__0\(1),
I1 => \cr_int[3]_i_13_n_0\,
I2 => \cr_int[3]_i_14_n_0\,
I3 => \cr_int[3]_i_4_n_0\,
O => \cr_int[3]_i_7_n_0\
);
\cr_int[3]_i_71\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_94_n_7\,
O => \cr_int[3]_i_71_n_0\
);
\cr_int[3]_i_72\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[3]_i_33_n_5\,
O => \cr_int[3]_i_72_n_0\
);
\cr_int[3]_i_73\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[3]_i_33_n_6\,
O => \cr_int[3]_i_73_n_0\
);
\cr_int[3]_i_74\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(8),
I1 => \cr_int_reg[3]_i_65_n_5\,
O => \cr_int[3]_i_74_n_0\
);
\cr_int[3]_i_75\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[3]_i_65_n_6\,
O => \cr_int[3]_i_75_n_0\
);
\cr_int[3]_i_76\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(17),
I1 => rgb888(19),
O => \cr_int[3]_i_76_n_0\
);
\cr_int[3]_i_77\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(16),
I1 => rgb888(18),
O => \cr_int[3]_i_77_n_0\
);
\cr_int[3]_i_78\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(17),
O => \cr_int[3]_i_78_n_0\
);
\cr_int[3]_i_79\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => rgb888(16),
O => \cr_int[3]_i_79_n_0\
);
\cr_int[3]_i_8\: unisim.vcomponents.LUT5
generic map(
INIT => X"1DE2E21D"
)
port map (
I0 => cr_int_reg6(8),
I1 => cr_int_reg7,
I2 => \cr_int_reg[3]_i_16_n_5\,
I3 => \cr_int[3]_i_17_n_0\,
I4 => \cr_int[3]_i_18_n_0\,
O => \cr_int[3]_i_8_n_0\
);
\cr_int[3]_i_80\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(0),
O => \cr_int[3]_i_80_n_0\
);
\cr_int[3]_i_81\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_39_n_6\,
O => \cr_int[3]_i_81_n_0\
);
\cr_int[3]_i_82\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_39_n_7\,
O => \cr_int[3]_i_82_n_0\
);
\cr_int[3]_i_83\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_86_n_6\,
O => \cr_int[3]_i_83_n_0\
);
\cr_int[3]_i_84\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_86_n_7\,
O => \cr_int[3]_i_84_n_0\
);
\cr_int[3]_i_85\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(15),
I1 => rgb888(13),
O => \cr_int[3]_i_85_n_0\
);
\cr_int[3]_i_86\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(12),
I1 => rgb888(14),
O => \cr_int[3]_i_86_n_0\
);
\cr_int[3]_i_87\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(11),
I1 => rgb888(13),
O => \cr_int[3]_i_87_n_0\
);
\cr_int[3]_i_88\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(10),
I1 => rgb888(12),
O => \cr_int[3]_i_88_n_0\
);
\cr_int[3]_i_89\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(9),
I1 => rgb888(11),
O => \cr_int[3]_i_89_n_0\
);
\cr_int[3]_i_9\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => cr_int_reg4(2),
I1 => \cr_int_reg[31]_i_11_n_4\,
I2 => \cr_int_reg[31]_i_30_n_7\,
I3 => cr_int_reg7,
I4 => cr_int_reg6(10),
O => \cr_int_reg3__0\(2)
);
\cr_int[3]_i_90\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(8),
I1 => rgb888(10),
O => \cr_int[3]_i_90_n_0\
);
\cr_int[3]_i_91\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(9),
O => \cr_int[3]_i_91_n_0\
);
\cr_int[3]_i_92\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => rgb888(8),
O => \cr_int[3]_i_92_n_0\
);
\cr_int[3]_i_93\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(12),
I1 => rgb888(10),
O => \cr_int[3]_i_93_n_0\
);
\cr_int[3]_i_94\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(11),
I1 => rgb888(9),
O => \cr_int[3]_i_94_n_0\
);
\cr_int[3]_i_95\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(10),
I1 => rgb888(8),
O => \cr_int[3]_i_95_n_0\
);
\cr_int[3]_i_96\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => rgb888(9),
O => \cr_int[3]_i_96_n_0\
);
\cr_int[7]_i_10\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => cr_int_reg4(5),
I1 => \cr_int_reg[31]_i_11_n_4\,
I2 => \cr_int_reg[31]_i_30_n_4\,
I3 => cr_int_reg7,
I4 => cr_int_reg6(13),
O => \cr_int_reg3__0\(5)
);
\cr_int[7]_i_11\: unisim.vcomponents.LUT5
generic map(
INIT => X"44477747"
)
port map (
I0 => \rgb888[8]_13\(0),
I1 => \^cr_int_reg[31]_2\(1),
I2 => \^cr_int_reg[7]_1\(3),
I3 => \^cr_int_reg[3]_1\(0),
I4 => \^cr_int_reg[7]_0\(2),
O => \cr_int[7]_i_11_n_0\
);
\cr_int[7]_i_12\: unisim.vcomponents.LUT5
generic map(
INIT => X"44477747"
)
port map (
I0 => \cr_int_reg[11]_i_16_n_7\,
I1 => \^cr_int_reg[27]_2\(0),
I2 => \cr_int_reg[11]_i_18_n_7\,
I3 => \cr_int_reg[11]_i_17_n_0\,
I4 => \cr_int_reg[31]_i_7_n_5\,
O => \cr_int[7]_i_12_n_0\
);
\cr_int[7]_i_13\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => cr_int_reg4(4),
I1 => \cr_int_reg[31]_i_11_n_4\,
I2 => \cr_int_reg[31]_i_30_n_5\,
I3 => cr_int_reg7,
I4 => cr_int_reg6(12),
O => \cr_int_reg3__0\(4)
);
\cr_int[7]_i_14\: unisim.vcomponents.LUT5
generic map(
INIT => X"44477747"
)
port map (
I0 => \rgb888[8]_12\(3),
I1 => \^cr_int_reg[31]_2\(1),
I2 => \^cr_int_reg[7]_1\(2),
I3 => \^cr_int_reg[3]_1\(0),
I4 => \^cr_int_reg[7]_0\(1),
O => \cr_int[7]_i_14_n_0\
);
\cr_int[7]_i_15\: unisim.vcomponents.LUT5
generic map(
INIT => X"44477747"
)
port map (
I0 => \cr_int_reg[11]_i_31_n_4\,
I1 => \^cr_int_reg[27]_2\(0),
I2 => \cr_int_reg[11]_i_41_n_4\,
I3 => \cr_int_reg[11]_i_17_n_0\,
I4 => \cr_int_reg[31]_i_7_n_6\,
O => \cr_int[7]_i_15_n_0\
);
\cr_int[7]_i_16\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => cr_int_reg4(3),
I1 => \cr_int_reg[31]_i_11_n_4\,
I2 => \cr_int_reg[31]_i_30_n_6\,
I3 => cr_int_reg7,
I4 => cr_int_reg6(11),
O => \cr_int_reg3__0\(3)
);
\cr_int[7]_i_17\: unisim.vcomponents.LUT5
generic map(
INIT => X"44477747"
)
port map (
I0 => \rgb888[8]_12\(2),
I1 => \^cr_int_reg[31]_2\(1),
I2 => \^cr_int_reg[7]_1\(1),
I3 => \^cr_int_reg[3]_1\(0),
I4 => \^cr_int_reg[7]_0\(0),
O => \cr_int[7]_i_17_n_0\
);
\cr_int[7]_i_18\: unisim.vcomponents.LUT5
generic map(
INIT => X"44477747"
)
port map (
I0 => \cr_int_reg[11]_i_31_n_5\,
I1 => \^cr_int_reg[27]_2\(0),
I2 => \cr_int_reg[11]_i_41_n_5\,
I3 => \cr_int_reg[11]_i_17_n_0\,
I4 => \cr_int_reg[31]_i_7_n_7\,
O => \cr_int[7]_i_18_n_0\
);
\cr_int[7]_i_19\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => cr_int_reg4(7),
I1 => \cr_int_reg[31]_i_11_n_4\,
I2 => \cr_int_reg[31]_i_11_n_6\,
I3 => cr_int_reg7,
I4 => cr_int_reg6(15),
O => cr_int_reg3(7)
);
\cr_int[7]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"555556A6AAAA56A6"
)
port map (
I0 => \cr_int[11]_i_22_n_0\,
I1 => cr_int_reg6(15),
I2 => cr_int_reg7,
I3 => \cr_int_reg[31]_i_11_n_6\,
I4 => \cr_int_reg[31]_i_11_n_4\,
I5 => cr_int_reg4(7),
O => \cr_int[7]_i_2_n_0\
);
\cr_int[7]_i_20\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \cr_int_reg[11]_i_16_n_6\,
I1 => \^cr_int_reg[27]_2\(0),
I2 => \cr_int_reg[11]_i_17_n_0\,
I3 => \cr_int_reg[11]_i_18_n_6\,
O => \cr_int[7]_i_20_n_0\
);
\cr_int[7]_i_21\: unisim.vcomponents.LUT5
generic map(
INIT => X"44477747"
)
port map (
I0 => \rgb888[8]_13\(1),
I1 => \^cr_int_reg[31]_2\(1),
I2 => \^cr_int_reg[11]_0\(0),
I3 => \^cr_int_reg[3]_1\(0),
I4 => \^cr_int_reg[7]_0\(3),
O => \cr_int[7]_i_21_n_0\
);
\cr_int[7]_i_22\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => cr_int_reg4(6),
I1 => \cr_int_reg[31]_i_11_n_4\,
I2 => \cr_int_reg[31]_i_11_n_7\,
I3 => cr_int_reg7,
I4 => cr_int_reg6(14),
O => \cr_int_reg3__0\(6)
);
\cr_int[7]_i_25\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[7]_0\(2),
O => \cr_int[7]_i_25_n_0\
);
\cr_int[7]_i_26\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[7]_0\(1),
O => \cr_int[7]_i_26_n_0\
);
\cr_int[7]_i_27\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[7]_0\(0),
O => \cr_int[7]_i_27_n_0\
);
\cr_int[7]_i_28\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[3]_0\(2),
O => \cr_int[7]_i_28_n_0\
);
\cr_int[7]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \cr_int_reg3__0\(5),
I1 => \cr_int[7]_i_11_n_0\,
I2 => \cr_int[7]_i_12_n_0\,
O => \cr_int[7]_i_3_n_0\
);
\cr_int[7]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \cr_int_reg3__0\(4),
I1 => \cr_int[7]_i_14_n_0\,
I2 => \cr_int[7]_i_15_n_0\,
O => \cr_int[7]_i_4_n_0\
);
\cr_int[7]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \cr_int_reg3__0\(3),
I1 => \cr_int[7]_i_17_n_0\,
I2 => \cr_int[7]_i_18_n_0\,
O => \cr_int[7]_i_5_n_0\
);
\cr_int[7]_i_6\: unisim.vcomponents.LUT5
generic map(
INIT => X"99969666"
)
port map (
I0 => cr_int_reg3(7),
I1 => \cr_int[11]_i_22_n_0\,
I2 => \cr_int[7]_i_20_n_0\,
I3 => \cr_int[7]_i_21_n_0\,
I4 => \cr_int_reg3__0\(6),
O => \cr_int[7]_i_6_n_0\
);
\cr_int[7]_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \cr_int[7]_i_3_n_0\,
I1 => \cr_int[7]_i_20_n_0\,
I2 => \cr_int[7]_i_21_n_0\,
I3 => \cr_int_reg3__0\(6),
O => \cr_int[7]_i_7_n_0\
);
\cr_int[7]_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \cr_int_reg3__0\(5),
I1 => \cr_int[7]_i_11_n_0\,
I2 => \cr_int[7]_i_12_n_0\,
I3 => \cr_int[7]_i_4_n_0\,
O => \cr_int[7]_i_8_n_0\
);
\cr_int[7]_i_9\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \cr_int_reg3__0\(4),
I1 => \cr_int[7]_i_14_n_0\,
I2 => \cr_int[7]_i_15_n_0\,
I3 => \cr_int[7]_i_5_n_0\,
O => \cr_int[7]_i_9_n_0\
);
\cr_int_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[3]_i_1_n_7\,
Q => \cr_int_reg_n_0_[0]\,
R => '0'
);
\cr_int_reg[10]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[11]_i_1_n_5\,
Q => \cr_int_reg__0\(10),
R => '0'
);
\cr_int_reg[11]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[11]_i_1_n_4\,
Q => \cr_int_reg__0\(11),
R => '0'
);
\cr_int_reg[11]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[7]_i_1_n_0\,
CO(3) => \cr_int_reg[11]_i_1_n_0\,
CO(2) => \cr_int_reg[11]_i_1_n_1\,
CO(1) => \cr_int_reg[11]_i_1_n_2\,
CO(0) => \cr_int_reg[11]_i_1_n_3\,
CYINIT => '0',
DI(3) => \cr_int[11]_i_2_n_0\,
DI(2) => \cr_int[11]_i_3_n_0\,
DI(1) => \cr_int[11]_i_4_n_0\,
DI(0) => \cr_int[11]_i_5_n_0\,
O(3) => \cr_int_reg[11]_i_1_n_4\,
O(2) => \cr_int_reg[11]_i_1_n_5\,
O(1) => \cr_int_reg[11]_i_1_n_6\,
O(0) => \cr_int_reg[11]_i_1_n_7\,
S(3) => \cr_int[11]_i_6_n_0\,
S(2) => \cr_int[11]_i_7_n_0\,
S(1) => \cr_int[11]_i_8_n_0\,
S(0) => \cr_int[11]_i_9_n_0\
);
\cr_int_reg[11]_i_103\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[11]_i_125_n_0\,
CO(3) => \cr_int_reg[11]_i_103_n_0\,
CO(2) => \cr_int_reg[11]_i_103_n_1\,
CO(1) => \cr_int_reg[11]_i_103_n_2\,
CO(0) => \cr_int_reg[11]_i_103_n_3\,
CYINIT => '0',
DI(3) => \cr_int[11]_i_126_n_0\,
DI(2) => \cr_int[11]_i_127_n_0\,
DI(1) => \cr_int[11]_i_128_n_0\,
DI(0) => \cr_int[11]_i_129_n_0\,
O(3 downto 0) => \NLW_cr_int_reg[11]_i_103_O_UNCONNECTED\(3 downto 0),
S(3) => \cr_int[11]_i_130_n_0\,
S(2) => \cr_int[11]_i_131_n_0\,
S(1) => \cr_int[11]_i_132_n_0\,
S(0) => \cr_int[11]_i_133_n_0\
);
\cr_int_reg[11]_i_108\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cr_int_reg[11]_i_108_n_0\,
CO(2) => \cr_int_reg[11]_i_108_n_1\,
CO(1) => \cr_int_reg[11]_i_108_n_2\,
CO(0) => \cr_int_reg[11]_i_108_n_3\,
CYINIT => '1',
DI(3) => \cr_int[11]_i_134_n_0\,
DI(2) => \cr_int[11]_i_135_n_0\,
DI(1) => \cr_int[11]_i_136_n_0\,
DI(0) => \cr_int[11]_i_137_n_0\,
O(3 downto 0) => \NLW_cr_int_reg[11]_i_108_O_UNCONNECTED\(3 downto 0),
S(3) => \cr_int[11]_i_138_n_0\,
S(2) => \cr_int[11]_i_139_n_0\,
S(1) => \cr_int[11]_i_140_n_0\,
S(0) => \cr_int[11]_i_141_n_0\
);
\cr_int_reg[11]_i_116\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cr_int_reg[11]_i_116_n_0\,
CO(2) => \cr_int_reg[11]_i_116_n_1\,
CO(1) => \cr_int_reg[11]_i_116_n_2\,
CO(0) => \cr_int_reg[11]_i_116_n_3\,
CYINIT => '1',
DI(3) => \cr_int[11]_i_142_n_0\,
DI(2) => \cr_int[11]_i_143_n_0\,
DI(1) => \cr_int[11]_i_144_n_0\,
DI(0) => \cr_int[11]_i_145_n_0\,
O(3 downto 0) => \NLW_cr_int_reg[11]_i_116_O_UNCONNECTED\(3 downto 0),
S(3) => \cr_int[11]_i_146_n_0\,
S(2) => \cr_int[11]_i_147_n_0\,
S(1) => \cr_int[11]_i_148_n_0\,
S(0) => \cr_int[11]_i_149_n_0\
);
\cr_int_reg[11]_i_125\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cr_int_reg[11]_i_125_n_0\,
CO(2) => \cr_int_reg[11]_i_125_n_1\,
CO(1) => \cr_int_reg[11]_i_125_n_2\,
CO(0) => \cr_int_reg[11]_i_125_n_3\,
CYINIT => '1',
DI(3) => \cr_int[11]_i_150_n_0\,
DI(2) => \cr_int[11]_i_151_n_0\,
DI(1) => \cr_int[11]_i_152_n_0\,
DI(0) => \cb_int_reg[3]_i_94_n_7\,
O(3 downto 0) => \NLW_cr_int_reg[11]_i_125_O_UNCONNECTED\(3 downto 0),
S(3) => \cr_int[11]_i_153_n_0\,
S(2) => \cr_int[11]_i_154_n_0\,
S(1) => \cr_int[11]_i_155_n_0\,
S(0) => \cr_int[11]_i_156_n_0\
);
\cr_int_reg[11]_i_16\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[11]_i_31_n_0\,
CO(3) => \cr_int_reg[11]_i_16_n_0\,
CO(2) => \cr_int_reg[11]_i_16_n_1\,
CO(1) => \cr_int_reg[11]_i_16_n_2\,
CO(0) => \cr_int_reg[11]_i_16_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cr_int_reg[11]_i_16_n_4\,
O(2) => \cr_int_reg[11]_i_16_n_5\,
O(1) => \cr_int_reg[11]_i_16_n_6\,
O(0) => \cr_int_reg[11]_i_16_n_7\,
S(3) => \cr_int[11]_i_32_n_0\,
S(2) => \cr_int[11]_i_33_n_0\,
S(1) => \cr_int[11]_i_34_n_0\,
S(0) => \cr_int[11]_i_35_n_0\
);
\cr_int_reg[11]_i_17\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[11]_i_36_n_0\,
CO(3) => \cr_int_reg[11]_i_17_n_0\,
CO(2) => \cr_int_reg[11]_i_17_n_1\,
CO(1) => \cr_int_reg[11]_i_17_n_2\,
CO(0) => \cr_int_reg[11]_i_17_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \^cr_int_reg[27]_2\(0),
DI(1) => \^cr_int_reg[27]_2\(0),
DI(0) => \^cr_int_reg[27]_2\(0),
O(3 downto 0) => \NLW_cr_int_reg[11]_i_17_O_UNCONNECTED\(3 downto 0),
S(3) => \cr_int[11]_i_37_n_0\,
S(2) => \cr_int[11]_i_38_n_0\,
S(1) => \cr_int[11]_i_39_n_0\,
S(0) => \cr_int[11]_i_40_n_0\
);
\cr_int_reg[11]_i_18\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[11]_i_41_n_0\,
CO(3) => \cr_int_reg[15]_1\(0),
CO(2) => \cr_int_reg[11]_i_18_n_1\,
CO(1) => \cr_int_reg[11]_i_18_n_2\,
CO(0) => \cr_int_reg[11]_i_18_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cr_int_reg[11]_i_18_n_4\,
O(2) => \cr_int_reg[11]_i_18_n_5\,
O(1) => \cr_int_reg[11]_i_18_n_6\,
O(0) => \cr_int_reg[11]_i_18_n_7\,
S(3) => \cr_int[11]_i_42_n_0\,
S(2) => \cr_int[11]_i_43_n_0\,
S(1) => \cr_int[11]_i_44_n_0\,
S(0) => \cr_int[11]_i_45_n_0\
);
\cr_int_reg[11]_i_19\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[11]_i_46_n_0\,
CO(3) => \cr_int_reg[11]_i_19_n_0\,
CO(2) => \cr_int_reg[11]_i_19_n_1\,
CO(1) => \cr_int_reg[11]_i_19_n_2\,
CO(0) => \cr_int_reg[11]_i_19_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => cr_int_reg6(16 downto 13),
S(3) => \cr_int[11]_i_47_n_0\,
S(2) => \cr_int[11]_i_48_n_0\,
S(1) => \cr_int[11]_i_49_n_0\,
S(0) => \cr_int[11]_i_50_n_0\
);
\cr_int_reg[11]_i_20\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[11]_i_51_n_0\,
CO(3) => cr_int_reg7,
CO(2) => \cr_int_reg[11]_i_20_n_1\,
CO(1) => \cr_int_reg[11]_i_20_n_2\,
CO(0) => \cr_int_reg[11]_i_20_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \cr_int_reg[31]_i_11_n_4\,
DI(1) => \cr_int_reg[31]_i_11_n_4\,
DI(0) => \cr_int_reg[31]_i_11_n_4\,
O(3 downto 0) => \NLW_cr_int_reg[11]_i_20_O_UNCONNECTED\(3 downto 0),
S(3) => \cr_int[11]_i_52_n_0\,
S(2) => \cr_int[11]_i_53_n_0\,
S(1) => \cr_int[11]_i_54_n_0\,
S(0) => \cr_int[11]_i_55_n_0\
);
\cr_int_reg[11]_i_21\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[11]_i_56_n_0\,
CO(3) => \cr_int_reg[11]_i_21_n_0\,
CO(2) => \cr_int_reg[11]_i_21_n_1\,
CO(1) => \cr_int_reg[11]_i_21_n_2\,
CO(0) => \cr_int_reg[11]_i_21_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => cr_int_reg4(8 downto 5),
S(3) => \cr_int[11]_i_57_n_0\,
S(2) => \cr_int[11]_i_58_n_0\,
S(1) => \cr_int[11]_i_59_n_0\,
S(0) => \cr_int[11]_i_60_n_0\
);
\cr_int_reg[11]_i_29\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[7]_i_23_n_0\,
CO(3) => \cr_int_reg[11]_i_29_n_0\,
CO(2) => \cr_int_reg[11]_i_29_n_1\,
CO(1) => \cr_int_reg[11]_i_29_n_2\,
CO(0) => \cr_int_reg[11]_i_29_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \^cr_int_reg[11]_0\(3 downto 0),
S(3) => \cr_int[11]_i_65_n_0\,
S(2) => \cr_int[11]_i_66_n_0\,
S(1) => \cr_int[11]_i_67_n_0\,
S(0) => \cr_int[11]_i_68_n_0\
);
\cr_int_reg[11]_i_30\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[11]_i_69_n_0\,
CO(3) => \^cr_int_reg[3]_1\(0),
CO(2) => \cr_int_reg[11]_i_30_n_1\,
CO(1) => \cr_int_reg[11]_i_30_n_2\,
CO(0) => \cr_int_reg[11]_i_30_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \^cr_int_reg[31]_2\(1),
DI(1) => \^cr_int_reg[31]_2\(1),
DI(0) => \^cr_int_reg[31]_2\(1),
O(3 downto 0) => \NLW_cr_int_reg[11]_i_30_O_UNCONNECTED\(3 downto 0),
S(3) => \cr_int[11]_i_70_n_0\,
S(2) => \cr_int[11]_i_71_n_0\,
S(1) => \cr_int[11]_i_72_n_0\,
S(0) => \cr_int[11]_i_73_n_0\
);
\cr_int_reg[11]_i_31\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cr_int_reg[11]_i_31_n_0\,
CO(2) => \cr_int_reg[11]_i_31_n_1\,
CO(1) => \cr_int_reg[11]_i_31_n_2\,
CO(0) => \cr_int_reg[11]_i_31_n_3\,
CYINIT => \cr_int[11]_i_74_n_0\,
DI(3 downto 0) => B"0000",
O(3) => \cr_int_reg[11]_i_31_n_4\,
O(2) => \cr_int_reg[11]_i_31_n_5\,
O(1) => \cr_int_reg[11]_i_31_n_6\,
O(0) => \cr_int_reg[11]_i_31_n_7\,
S(3) => \cr_int[11]_i_75_n_0\,
S(2) => \cr_int[11]_i_76_n_0\,
S(1) => \cr_int[11]_i_77_n_0\,
S(0) => \cr_int[11]_i_78_n_0\
);
\cr_int_reg[11]_i_36\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[11]_i_79_n_0\,
CO(3) => \cr_int_reg[11]_i_36_n_0\,
CO(2) => \cr_int_reg[11]_i_36_n_1\,
CO(1) => \cr_int_reg[11]_i_36_n_2\,
CO(0) => \cr_int_reg[11]_i_36_n_3\,
CYINIT => '0',
DI(3) => \^cr_int_reg[27]_2\(0),
DI(2) => \^cr_int_reg[27]_2\(0),
DI(1) => \^cr_int_reg[27]_2\(0),
DI(0) => \^cr_int_reg[27]_2\(0),
O(3 downto 0) => \NLW_cr_int_reg[11]_i_36_O_UNCONNECTED\(3 downto 0),
S(3) => \cr_int[11]_i_80_n_0\,
S(2) => \cr_int[11]_i_81_n_0\,
S(1) => \cr_int[11]_i_82_n_0\,
S(0) => \cr_int[11]_i_83_n_0\
);
\cr_int_reg[11]_i_41\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[3]_i_32_n_0\,
CO(3) => \cr_int_reg[11]_i_41_n_0\,
CO(2) => \cr_int_reg[11]_i_41_n_1\,
CO(1) => \cr_int_reg[11]_i_41_n_2\,
CO(0) => \cr_int_reg[11]_i_41_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cr_int_reg[11]_i_41_n_4\,
O(2) => \cr_int_reg[11]_i_41_n_5\,
O(1) => \cr_int_reg[11]_i_41_n_6\,
O(0) => \cr_int_reg[11]_i_41_n_7\,
S(3) => \cr_int[11]_i_84_n_0\,
S(2) => \cr_int[11]_i_85_n_0\,
S(1) => \cr_int[11]_i_86_n_0\,
S(0) => \cr_int[11]_i_87_n_0\
);
\cr_int_reg[11]_i_46\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[3]_i_15_n_0\,
CO(3) => \cr_int_reg[11]_i_46_n_0\,
CO(2) => \cr_int_reg[11]_i_46_n_1\,
CO(1) => \cr_int_reg[11]_i_46_n_2\,
CO(0) => \cr_int_reg[11]_i_46_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => cr_int_reg6(12 downto 9),
S(3) => \cr_int[11]_i_88_n_0\,
S(2) => \cr_int[11]_i_89_n_0\,
S(1) => \cr_int[11]_i_90_n_0\,
S(0) => \cr_int[11]_i_91_n_0\
);
\cr_int_reg[11]_i_51\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[11]_i_92_n_0\,
CO(3) => \cr_int_reg[11]_i_51_n_0\,
CO(2) => \cr_int_reg[11]_i_51_n_1\,
CO(1) => \cr_int_reg[11]_i_51_n_2\,
CO(0) => \cr_int_reg[11]_i_51_n_3\,
CYINIT => '0',
DI(3) => \cr_int_reg[31]_i_11_n_4\,
DI(2) => \cr_int_reg[31]_i_11_n_4\,
DI(1) => \cr_int_reg[31]_i_11_n_4\,
DI(0) => \cr_int[11]_i_93_n_0\,
O(3 downto 0) => \NLW_cr_int_reg[11]_i_51_O_UNCONNECTED\(3 downto 0),
S(3) => \cr_int[11]_i_94_n_0\,
S(2) => \cr_int[11]_i_95_n_0\,
S(1) => \cr_int[11]_i_96_n_0\,
S(0) => \cr_int[11]_i_97_n_0\
);
\cr_int_reg[11]_i_56\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cr_int_reg[11]_i_56_n_0\,
CO(2) => \cr_int_reg[11]_i_56_n_1\,
CO(1) => \cr_int_reg[11]_i_56_n_2\,
CO(0) => \cr_int_reg[11]_i_56_n_3\,
CYINIT => \cr_int[11]_i_98_n_0\,
DI(3 downto 0) => B"0000",
O(3 downto 0) => cr_int_reg4(4 downto 1),
S(3) => \cr_int[11]_i_99_n_0\,
S(2) => \cr_int[11]_i_100_n_0\,
S(1) => \cr_int[11]_i_101_n_0\,
S(0) => \cr_int[11]_i_102_n_0\
);
\cr_int_reg[11]_i_69\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[11]_i_103_n_0\,
CO(3) => \cr_int_reg[11]_i_69_n_0\,
CO(2) => \cr_int_reg[11]_i_69_n_1\,
CO(1) => \cr_int_reg[11]_i_69_n_2\,
CO(0) => \cr_int_reg[11]_i_69_n_3\,
CYINIT => '0',
DI(3) => \^cr_int_reg[31]_2\(1),
DI(2) => \^cr_int_reg[31]_2\(1),
DI(1) => \^cr_int_reg[31]_2\(1),
DI(0) => \^cr_int_reg[31]_2\(1),
O(3 downto 0) => \NLW_cr_int_reg[11]_i_69_O_UNCONNECTED\(3 downto 0),
S(3) => \cr_int[11]_i_104_n_0\,
S(2) => \cr_int[11]_i_105_n_0\,
S(1) => \cr_int[11]_i_106_n_0\,
S(0) => \cr_int[11]_i_107_n_0\
);
\cr_int_reg[11]_i_79\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[11]_i_108_n_0\,
CO(3) => \cr_int_reg[11]_i_79_n_0\,
CO(2) => \cr_int_reg[11]_i_79_n_1\,
CO(1) => \cr_int_reg[11]_i_79_n_2\,
CO(0) => \cr_int_reg[11]_i_79_n_3\,
CYINIT => '0',
DI(3) => \^cr_int_reg[27]_2\(0),
DI(2) => \cr_int[11]_i_109_n_0\,
DI(1) => \cr_int[11]_i_110_n_0\,
DI(0) => \cr_int[11]_i_111_n_0\,
O(3 downto 0) => \NLW_cr_int_reg[11]_i_79_O_UNCONNECTED\(3 downto 0),
S(3) => \cr_int[11]_i_112_n_0\,
S(2) => \cr_int[11]_i_113_n_0\,
S(1) => \cr_int[11]_i_114_n_0\,
S(0) => \cr_int[11]_i_115_n_0\
);
\cr_int_reg[11]_i_92\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[11]_i_116_n_0\,
CO(3) => \cr_int_reg[11]_i_92_n_0\,
CO(2) => \cr_int_reg[11]_i_92_n_1\,
CO(1) => \cr_int_reg[11]_i_92_n_2\,
CO(0) => \cr_int_reg[11]_i_92_n_3\,
CYINIT => '0',
DI(3) => \cr_int[11]_i_117_n_0\,
DI(2) => \cr_int[11]_i_118_n_0\,
DI(1) => \cr_int[11]_i_119_n_0\,
DI(0) => \cr_int[11]_i_120_n_0\,
O(3 downto 0) => \NLW_cr_int_reg[11]_i_92_O_UNCONNECTED\(3 downto 0),
S(3) => \cr_int[11]_i_121_n_0\,
S(2) => \cr_int[11]_i_122_n_0\,
S(1) => \cr_int[11]_i_123_n_0\,
S(0) => \cr_int[11]_i_124_n_0\
);
\cr_int_reg[12]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[15]_i_1_n_7\,
Q => \cr_int_reg__0\(12),
R => '0'
);
\cr_int_reg[13]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[15]_i_1_n_6\,
Q => \cr_int_reg__0\(13),
R => '0'
);
\cr_int_reg[14]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[15]_i_1_n_5\,
Q => \cr_int_reg__0\(14),
R => '0'
);
\cr_int_reg[15]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[15]_i_1_n_4\,
Q => \cr_int_reg__0\(15),
R => '0'
);
\cr_int_reg[15]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[11]_i_1_n_0\,
CO(3) => \cr_int_reg[15]_i_1_n_0\,
CO(2) => \cr_int_reg[15]_i_1_n_1\,
CO(1) => \cr_int_reg[15]_i_1_n_2\,
CO(0) => \cr_int_reg[15]_i_1_n_3\,
CYINIT => '0',
DI(3) => \cr_int[15]_i_2_n_0\,
DI(2) => \cr_int[15]_i_3_n_0\,
DI(1) => \cr_int[15]_i_4_n_0\,
DI(0) => \cr_int[15]_i_5_n_0\,
O(3) => \cr_int_reg[15]_i_1_n_4\,
O(2) => \cr_int_reg[15]_i_1_n_5\,
O(1) => \cr_int_reg[15]_i_1_n_6\,
O(0) => \cr_int_reg[15]_i_1_n_7\,
S(3) => \cr_int[15]_i_6_n_0\,
S(2) => \cr_int[15]_i_7_n_0\,
S(1) => \cr_int[15]_i_8_n_0\,
S(0) => \cr_int[15]_i_9_n_0\
);
\cr_int_reg[15]_i_20\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[11]_i_19_n_0\,
CO(3) => \cr_int_reg[15]_i_20_n_0\,
CO(2) => \cr_int_reg[15]_i_20_n_1\,
CO(1) => \cr_int_reg[15]_i_20_n_2\,
CO(0) => \cr_int_reg[15]_i_20_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => cr_int_reg6(20 downto 17),
S(3) => \cr_int[15]_i_29_n_0\,
S(2) => \cr_int[15]_i_30_n_0\,
S(1) => \cr_int[15]_i_31_n_0\,
S(0) => \cr_int[15]_i_32_n_0\
);
\cr_int_reg[15]_i_21\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[11]_i_21_n_0\,
CO(3) => \cr_int_reg[15]_i_21_n_0\,
CO(2) => \cr_int_reg[15]_i_21_n_1\,
CO(1) => \cr_int_reg[15]_i_21_n_2\,
CO(0) => \cr_int_reg[15]_i_21_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => cr_int_reg4(12 downto 9),
S(3) => \cr_int[15]_i_33_n_0\,
S(2) => \cr_int[15]_i_34_n_0\,
S(1) => \cr_int[15]_i_35_n_0\,
S(0) => \cr_int[15]_i_36_n_0\
);
\cr_int_reg[15]_i_28\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[11]_i_29_n_0\,
CO(3) => \cr_int_reg[15]_i_28_n_0\,
CO(2) => \cr_int_reg[15]_i_28_n_1\,
CO(1) => \cr_int_reg[15]_i_28_n_2\,
CO(0) => \cr_int_reg[15]_i_28_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \^cr_int_reg[15]_0\(3 downto 0),
S(3) => \cr_int[15]_i_40_n_0\,
S(2) => \cr_int[15]_i_41_n_0\,
S(1) => \cr_int[15]_i_42_n_0\,
S(0) => \cr_int[15]_i_43_n_0\
);
\cr_int_reg[15]_i_38\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[11]_i_16_n_0\,
CO(3) => \cr_int_reg[15]_i_38_n_0\,
CO(2) => \cr_int_reg[15]_i_38_n_1\,
CO(1) => \cr_int_reg[15]_i_38_n_2\,
CO(0) => \cr_int_reg[15]_i_38_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cr_int_reg[15]_i_38_n_4\,
O(2) => \cr_int_reg[15]_i_38_n_5\,
O(1) => \cr_int_reg[15]_i_38_n_6\,
O(0) => \cr_int_reg[15]_i_38_n_7\,
S(3) => \cr_int[15]_i_48_n_0\,
S(2) => \cr_int[15]_i_49_n_0\,
S(1) => \cr_int[15]_i_50_n_0\,
S(0) => \cr_int[15]_i_51_n_0\
);
\cr_int_reg[16]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[19]_i_1_n_7\,
Q => \cr_int_reg__0\(16),
R => '0'
);
\cr_int_reg[17]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[19]_i_1_n_6\,
Q => \cr_int_reg__0\(17),
R => '0'
);
\cr_int_reg[18]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[19]_i_1_n_5\,
Q => \cr_int_reg__0\(18),
R => '0'
);
\cr_int_reg[19]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[19]_i_1_n_4\,
Q => \cr_int_reg__0\(19),
R => '0'
);
\cr_int_reg[19]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[15]_i_1_n_0\,
CO(3) => \cr_int_reg[19]_i_1_n_0\,
CO(2) => \cr_int_reg[19]_i_1_n_1\,
CO(1) => \cr_int_reg[19]_i_1_n_2\,
CO(0) => \cr_int_reg[19]_i_1_n_3\,
CYINIT => '0',
DI(3) => \cr_int[19]_i_2_n_0\,
DI(2) => \cr_int[19]_i_3_n_0\,
DI(1) => \cr_int[19]_i_4_n_0\,
DI(0) => \cr_int[19]_i_5_n_0\,
O(3) => \cr_int_reg[19]_i_1_n_4\,
O(2) => \cr_int_reg[19]_i_1_n_5\,
O(1) => \cr_int_reg[19]_i_1_n_6\,
O(0) => \cr_int_reg[19]_i_1_n_7\,
S(3) => \cr_int[19]_i_6_n_0\,
S(2) => \cr_int[19]_i_7_n_0\,
S(1) => \cr_int[19]_i_8_n_0\,
S(0) => \cr_int[19]_i_9_n_0\
);
\cr_int_reg[19]_i_20\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[15]_i_20_n_0\,
CO(3) => \cr_int_reg[19]_i_20_n_0\,
CO(2) => \cr_int_reg[19]_i_20_n_1\,
CO(1) => \cr_int_reg[19]_i_20_n_2\,
CO(0) => \cr_int_reg[19]_i_20_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => cr_int_reg6(24 downto 21),
S(3) => \cr_int[19]_i_29_n_0\,
S(2) => \cr_int[19]_i_30_n_0\,
S(1) => \cr_int[19]_i_31_n_0\,
S(0) => \cr_int[19]_i_32_n_0\
);
\cr_int_reg[19]_i_21\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[15]_i_21_n_0\,
CO(3) => \cr_int_reg[19]_i_21_n_0\,
CO(2) => \cr_int_reg[19]_i_21_n_1\,
CO(1) => \cr_int_reg[19]_i_21_n_2\,
CO(0) => \cr_int_reg[19]_i_21_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => cr_int_reg4(16 downto 13),
S(3) => \cr_int[19]_i_33_n_0\,
S(2) => \cr_int[19]_i_34_n_0\,
S(1) => \cr_int[19]_i_35_n_0\,
S(0) => \cr_int[19]_i_36_n_0\
);
\cr_int_reg[19]_i_28\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[15]_i_28_n_0\,
CO(3) => \cr_int_reg[19]_i_28_n_0\,
CO(2) => \cr_int_reg[19]_i_28_n_1\,
CO(1) => \cr_int_reg[19]_i_28_n_2\,
CO(0) => \cr_int_reg[19]_i_28_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \^cr_int_reg[19]_0\(3 downto 0),
S(3) => \cr_int[19]_i_38_n_0\,
S(2) => \cr_int[19]_i_39_n_0\,
S(1) => \cr_int[19]_i_40_n_0\,
S(0) => \cr_int[19]_i_41_n_0\
);
\cr_int_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[3]_i_1_n_6\,
Q => \cr_int_reg_n_0_[1]\,
R => '0'
);
\cr_int_reg[20]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[23]_i_1_n_7\,
Q => \cr_int_reg__0\(20),
R => '0'
);
\cr_int_reg[21]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[23]_i_1_n_6\,
Q => \cr_int_reg__0\(21),
R => '0'
);
\cr_int_reg[22]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[23]_i_1_n_5\,
Q => \cr_int_reg__0\(22),
R => '0'
);
\cr_int_reg[23]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[23]_i_1_n_4\,
Q => \cr_int_reg__0\(23),
R => '0'
);
\cr_int_reg[23]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[19]_i_1_n_0\,
CO(3) => \cr_int_reg[23]_i_1_n_0\,
CO(2) => \cr_int_reg[23]_i_1_n_1\,
CO(1) => \cr_int_reg[23]_i_1_n_2\,
CO(0) => \cr_int_reg[23]_i_1_n_3\,
CYINIT => '0',
DI(3) => \cr_int[23]_i_2_n_0\,
DI(2) => \cr_int[23]_i_3_n_0\,
DI(1) => \cr_int[23]_i_4_n_0\,
DI(0) => \cr_int[23]_i_5_n_0\,
O(3) => \cr_int_reg[23]_i_1_n_4\,
O(2) => \cr_int_reg[23]_i_1_n_5\,
O(1) => \cr_int_reg[23]_i_1_n_6\,
O(0) => \cr_int_reg[23]_i_1_n_7\,
S(3) => \cr_int[23]_i_6_n_0\,
S(2) => \cr_int[23]_i_7_n_0\,
S(1) => \cr_int[23]_i_8_n_0\,
S(0) => \cr_int[23]_i_9_n_0\
);
\cr_int_reg[23]_i_20\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[19]_i_20_n_0\,
CO(3) => \cr_int_reg[23]_i_20_n_0\,
CO(2) => \cr_int_reg[23]_i_20_n_1\,
CO(1) => \cr_int_reg[23]_i_20_n_2\,
CO(0) => \cr_int_reg[23]_i_20_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => cr_int_reg6(28 downto 25),
S(3) => \cr_int[23]_i_27_n_0\,
S(2) => \cr_int[23]_i_28_n_0\,
S(1) => \cr_int[23]_i_29_n_0\,
S(0) => \cr_int[23]_i_30_n_0\
);
\cr_int_reg[24]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[27]_i_1_n_7\,
Q => \cr_int_reg__0\(24),
R => '0'
);
\cr_int_reg[25]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[27]_i_1_n_6\,
Q => \cr_int_reg__0\(25),
R => '0'
);
\cr_int_reg[26]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[27]_i_1_n_5\,
Q => \cr_int_reg__0\(26),
R => '0'
);
\cr_int_reg[27]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[27]_i_1_n_4\,
Q => \cr_int_reg__0\(27),
R => '0'
);
\cr_int_reg[27]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[23]_i_1_n_0\,
CO(3) => \cr_int_reg[27]_i_1_n_0\,
CO(2) => \cr_int_reg[27]_i_1_n_1\,
CO(1) => \cr_int_reg[27]_i_1_n_2\,
CO(0) => \cr_int_reg[27]_i_1_n_3\,
CYINIT => '0',
DI(3) => \cr_int[31]_i_2_n_0\,
DI(2) => \cr_int[31]_i_2_n_0\,
DI(1) => \cr_int[31]_i_2_n_0\,
DI(0) => \cr_int[27]_i_2_n_0\,
O(3) => \cr_int_reg[27]_i_1_n_4\,
O(2) => \cr_int_reg[27]_i_1_n_5\,
O(1) => \cr_int_reg[27]_i_1_n_6\,
O(0) => \cr_int_reg[27]_i_1_n_7\,
S(3) => \cr_int[27]_i_3_n_0\,
S(2) => \cr_int[27]_i_4_n_0\,
S(1) => \cr_int[27]_i_5_n_0\,
S(0) => \cr_int[27]_i_6_n_0\
);
\cr_int_reg[27]_i_9\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[23]_i_20_n_0\,
CO(3 downto 1) => \NLW_cr_int_reg[27]_i_9_CO_UNCONNECTED\(3 downto 1),
CO(0) => \cr_int_reg[27]_i_9_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 2) => \NLW_cr_int_reg[27]_i_9_O_UNCONNECTED\(3 downto 2),
O(1 downto 0) => cr_int_reg6(30 downto 29),
S(3 downto 2) => B"00",
S(1) => \cr_int[27]_i_12_n_0\,
S(0) => \cr_int[27]_i_13_n_0\
);
\cr_int_reg[28]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[31]_i_1_n_7\,
Q => \cr_int_reg__0\(28),
R => '0'
);
\cr_int_reg[29]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[31]_i_1_n_6\,
Q => \cr_int_reg__0\(29),
R => '0'
);
\cr_int_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[3]_i_1_n_5\,
Q => \cr_int_reg_n_0_[2]\,
R => '0'
);
\cr_int_reg[30]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[31]_i_1_n_5\,
Q => \cr_int_reg__0\(30),
R => '0'
);
\cr_int_reg[31]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[31]_i_1_n_4\,
Q => \cr_int_reg__0\(31),
R => '0'
);
\cr_int_reg[31]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[27]_i_1_n_0\,
CO(3) => \NLW_cr_int_reg[31]_i_1_CO_UNCONNECTED\(3),
CO(2) => \cr_int_reg[31]_i_1_n_1\,
CO(1) => \cr_int_reg[31]_i_1_n_2\,
CO(0) => \cr_int_reg[31]_i_1_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \cr_int[31]_i_2_n_0\,
DI(1) => \cr_int[31]_i_2_n_0\,
DI(0) => \cr_int[31]_i_2_n_0\,
O(3) => \cr_int_reg[31]_i_1_n_4\,
O(2) => \cr_int_reg[31]_i_1_n_5\,
O(1) => \cr_int_reg[31]_i_1_n_6\,
O(0) => \cr_int_reg[31]_i_1_n_7\,
S(3) => \cr_int[31]_i_3_n_0\,
S(2) => \cr_int[31]_i_4_n_0\,
S(1) => \cr_int[31]_i_5_n_0\,
S(0) => \cr_int[31]_i_6_n_0\
);
\cr_int_reg[31]_i_101\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[3]_i_64_n_0\,
CO(3) => \NLW_cr_int_reg[31]_i_101_CO_UNCONNECTED\(3),
CO(2) => \cr_int_reg[31]_i_101_n_1\,
CO(1) => \NLW_cr_int_reg[31]_i_101_CO_UNCONNECTED\(1),
CO(0) => \cr_int_reg[31]_i_101_n_3\,
CYINIT => '0',
DI(3 downto 2) => B"00",
DI(1 downto 0) => rgb888(15 downto 14),
O(3 downto 2) => \NLW_cr_int_reg[31]_i_101_O_UNCONNECTED\(3 downto 2),
O(1) => \cr_int_reg[31]_i_101_n_6\,
O(0) => \cr_int_reg[31]_i_101_n_7\,
S(3 downto 2) => B"01",
S(1) => \cr_int[31]_i_121_n_0\,
S(0) => \cr_int[31]_i_122_n_0\
);
\cr_int_reg[31]_i_102\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[3]_i_70_n_0\,
CO(3) => \cr_int_reg[31]_i_102_n_0\,
CO(2) => \cr_int_reg[31]_i_102_n_1\,
CO(1) => \cr_int_reg[31]_i_102_n_2\,
CO(0) => \cr_int_reg[31]_i_102_n_3\,
CYINIT => '0',
DI(3) => rgb888(14),
DI(2 downto 0) => rgb888(15 downto 13),
O(3) => \cr_int_reg[31]_i_102_n_4\,
O(2) => \cr_int_reg[31]_i_102_n_5\,
O(1) => \cr_int_reg[31]_i_102_n_6\,
O(0) => \cr_int_reg[31]_i_102_n_7\,
S(3) => \cr_int[31]_i_123_n_0\,
S(2) => \cr_int[31]_i_124_n_0\,
S(1) => \cr_int[31]_i_125_n_0\,
S(0) => \cr_int[31]_i_126_n_0\
);
\cr_int_reg[31]_i_11\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[31]_i_30_n_0\,
CO(3) => \NLW_cr_int_reg[31]_i_11_CO_UNCONNECTED\(3),
CO(2) => \cr_int_reg[31]_i_11_n_1\,
CO(1) => \cr_int_reg[31]_i_11_n_2\,
CO(0) => \cr_int_reg[31]_i_11_n_3\,
CYINIT => '0',
DI(3 downto 1) => B"000",
DI(0) => \cr_int[31]_i_31_n_0\,
O(3) => \cr_int_reg[31]_i_11_n_4\,
O(2) => \cr_int_reg[31]_i_11_n_5\,
O(1) => \cr_int_reg[31]_i_11_n_6\,
O(0) => \cr_int_reg[31]_i_11_n_7\,
S(3) => \cr_int[31]_i_32_n_0\,
S(2) => \cr_int[31]_i_33_n_0\,
S(1) => \cr_int[31]_i_34_n_0\,
S(0) => \cr_int[31]_i_35_n_0\
);
\cr_int_reg[31]_i_12\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[31]_i_36_n_0\,
CO(3) => \NLW_cr_int_reg[31]_i_12_CO_UNCONNECTED\(3),
CO(2) => \cr_int_reg[31]_i_12_n_1\,
CO(1) => \NLW_cr_int_reg[31]_i_12_CO_UNCONNECTED\(1),
CO(0) => \cr_int_reg[31]_i_12_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 2) => \NLW_cr_int_reg[31]_i_12_O_UNCONNECTED\(3 downto 2),
O(1 downto 0) => cr_int_reg4(22 downto 21),
S(3 downto 2) => B"01",
S(1) => \cr_int[31]_i_37_n_0\,
S(0) => \cr_int[31]_i_38_n_0\
);
\cr_int_reg[31]_i_14\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[31]_i_39_n_0\,
CO(3) => \cr_int_reg[31]_i_14_n_0\,
CO(2) => \cr_int_reg[31]_i_14_n_1\,
CO(1) => \cr_int_reg[31]_i_14_n_2\,
CO(0) => \cr_int_reg[31]_i_14_n_3\,
CYINIT => '0',
DI(3) => \cr_int[31]_i_40_n_0\,
DI(2) => \cr_int[31]_i_41_n_0\,
DI(1) => \cr_int[31]_i_42_n_0\,
DI(0) => \cr_int[31]_i_43_n_0\,
O(3) => \cr_int_reg[31]_i_14_n_4\,
O(2) => \cr_int_reg[31]_i_14_n_5\,
O(1) => \cr_int_reg[31]_i_14_n_6\,
O(0) => \cr_int_reg[31]_i_14_n_7\,
S(3) => \cr_int[31]_i_44_n_0\,
S(2) => \cr_int[31]_i_45_n_0\,
S(1) => \cr_int[31]_i_46_n_0\,
S(0) => \cr_int[31]_i_47_n_0\
);
\cr_int_reg[31]_i_21\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[31]_i_49_n_0\,
CO(3) => \cr_int_reg[31]_i_21_n_0\,
CO(2) => \cr_int_reg[31]_i_21_n_1\,
CO(1) => \cr_int_reg[31]_i_21_n_2\,
CO(0) => \cr_int_reg[31]_i_21_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cr_int_reg[31]_i_21_n_4\,
O(2) => \cr_int_reg[31]_i_21_n_5\,
O(1) => \cr_int_reg[31]_i_21_n_6\,
O(0) => \cr_int_reg[31]_i_21_n_7\,
S(3) => \cr_int[31]_i_50_n_0\,
S(2) => \cr_int[31]_i_51_n_0\,
S(1) => \cr_int[31]_i_52_n_0\,
S(0) => \cr_int[31]_i_53_n_0\
);
\cr_int_reg[31]_i_24\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[3]_i_19_n_0\,
CO(3) => \cr_int_reg[31]_i_24_n_0\,
CO(2) => \cr_int_reg[31]_i_24_n_1\,
CO(1) => \cr_int_reg[31]_i_24_n_2\,
CO(0) => \cr_int_reg[31]_i_24_n_3\,
CYINIT => '0',
DI(3) => \cr_int[31]_i_55_n_0\,
DI(2) => \cr_int[31]_i_56_n_0\,
DI(1) => \cr_int[31]_i_57_n_0\,
DI(0) => \cr_int[31]_i_58_n_0\,
O(3 downto 0) => \^cr_int_reg[7]_0\(3 downto 0),
S(3) => \cr_int[31]_i_59_n_0\,
S(2) => \cr_int[31]_i_60_n_0\,
S(1) => \cr_int[31]_i_61_n_0\,
S(0) => \cr_int[31]_i_62_n_0\
);
\cr_int_reg[31]_i_30\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[3]_i_16_n_0\,
CO(3) => \cr_int_reg[31]_i_30_n_0\,
CO(2) => \cr_int_reg[31]_i_30_n_1\,
CO(1) => \cr_int_reg[31]_i_30_n_2\,
CO(0) => \cr_int_reg[31]_i_30_n_3\,
CYINIT => '0',
DI(3) => \cr_int[31]_i_71_n_0\,
DI(2) => \cr_int[31]_i_72_n_0\,
DI(1) => \cr_int[31]_i_73_n_0\,
DI(0) => \cr_int[31]_i_74_n_0\,
O(3) => \cr_int_reg[31]_i_30_n_4\,
O(2) => \cr_int_reg[31]_i_30_n_5\,
O(1) => \cr_int_reg[31]_i_30_n_6\,
O(0) => \cr_int_reg[31]_i_30_n_7\,
S(3) => \cr_int[31]_i_75_n_0\,
S(2) => \cr_int[31]_i_76_n_0\,
S(1) => \cr_int[31]_i_77_n_0\,
S(0) => \cr_int[31]_i_78_n_0\
);
\cr_int_reg[31]_i_36\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[19]_i_21_n_0\,
CO(3) => \cr_int_reg[31]_i_36_n_0\,
CO(2) => \cr_int_reg[31]_i_36_n_1\,
CO(1) => \cr_int_reg[31]_i_36_n_2\,
CO(0) => \cr_int_reg[31]_i_36_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => cr_int_reg4(20 downto 17),
S(3) => \cr_int[31]_i_81_n_0\,
S(2) => \cr_int[31]_i_82_n_0\,
S(1) => \cr_int[31]_i_83_n_0\,
S(0) => \cr_int[31]_i_84_n_0\
);
\cr_int_reg[31]_i_39\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cr_int_reg[31]_i_39_n_0\,
CO(2) => \cr_int_reg[31]_i_39_n_1\,
CO(1) => \cr_int_reg[31]_i_39_n_2\,
CO(0) => \cr_int_reg[31]_i_39_n_3\,
CYINIT => '0',
DI(3) => \cr_int[31]_i_85_n_0\,
DI(2) => rgb888(1),
DI(1) => \cr_int_reg[31]_i_86_n_4\,
DI(0) => '0',
O(3) => \cr_int_reg[31]_i_39_n_4\,
O(2) => \cr_int_reg[31]_i_39_n_5\,
O(1) => \cr_int_reg[31]_i_39_n_6\,
O(0) => \cr_int_reg[31]_i_39_n_7\,
S(3) => \cr_int[31]_i_87_n_0\,
S(2) => \cr_int[31]_i_88_n_0\,
S(1) => \cr_int[31]_i_89_n_0\,
S(0) => \cr_int[31]_i_90_n_0\
);
\cr_int_reg[31]_i_48\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[31]_i_91_n_0\,
CO(3 downto 2) => \NLW_cr_int_reg[31]_i_48_CO_UNCONNECTED\(3 downto 2),
CO(1) => \cr_int_reg[31]_i_48_n_2\,
CO(0) => \NLW_cr_int_reg[31]_i_48_CO_UNCONNECTED\(0),
CYINIT => '0',
DI(3 downto 1) => B"000",
DI(0) => rgb888(7),
O(3 downto 1) => \NLW_cr_int_reg[31]_i_48_O_UNCONNECTED\(3 downto 1),
O(0) => \cr_int_reg[31]_i_48_n_7\,
S(3 downto 1) => B"001",
S(0) => \cr_int[31]_i_93_n_0\
);
\cr_int_reg[31]_i_49\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[15]_i_38_n_0\,
CO(3) => \cr_int_reg[31]_i_49_n_0\,
CO(2) => \cr_int_reg[31]_i_49_n_1\,
CO(1) => \cr_int_reg[31]_i_49_n_2\,
CO(0) => \cr_int_reg[31]_i_49_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cr_int_reg[31]_i_49_n_4\,
O(2) => \cr_int_reg[31]_i_49_n_5\,
O(1) => \cr_int_reg[31]_i_49_n_6\,
O(0) => \cr_int_reg[31]_i_49_n_7\,
S(3) => \cr_int[31]_i_94_n_0\,
S(2) => \cr_int[31]_i_95_n_0\,
S(1) => \cr_int[31]_i_96_n_0\,
S(0) => \cr_int[31]_i_97_n_0\
);
\cr_int_reg[31]_i_63\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[31]_i_102_n_0\,
CO(3 downto 2) => \NLW_cr_int_reg[31]_i_63_CO_UNCONNECTED\(3 downto 2),
CO(1) => \cr_int_reg[31]_i_63_n_2\,
CO(0) => \NLW_cr_int_reg[31]_i_63_CO_UNCONNECTED\(0),
CYINIT => '0',
DI(3 downto 1) => B"000",
DI(0) => rgb888(15),
O(3 downto 1) => \NLW_cr_int_reg[31]_i_63_O_UNCONNECTED\(3 downto 1),
O(0) => \cr_int_reg[31]_i_63_n_7\,
S(3 downto 1) => B"001",
S(0) => \cr_int[31]_i_103_n_0\
);
\cr_int_reg[31]_i_69\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[31]_i_70_n_0\,
CO(3 downto 0) => \NLW_cr_int_reg[31]_i_69_CO_UNCONNECTED\(3 downto 0),
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 1) => \NLW_cr_int_reg[31]_i_69_O_UNCONNECTED\(3 downto 1),
O(0) => \^cr_int_reg[23]_1\(0),
S(3 downto 1) => B"000",
S(0) => \cr_int[31]_i_108_n_0\
);
\cr_int_reg[31]_i_7\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[31]_i_14_n_0\,
CO(3) => \NLW_cr_int_reg[31]_i_7_CO_UNCONNECTED\(3),
CO(2) => \cr_int_reg[31]_i_7_n_1\,
CO(1) => \cr_int_reg[31]_i_7_n_2\,
CO(0) => \cr_int_reg[31]_i_7_n_3\,
CYINIT => '0',
DI(3 downto 2) => B"00",
DI(1) => \cr_int[31]_i_15_n_0\,
DI(0) => \cr_int[31]_i_16_n_0\,
O(3) => \^cr_int_reg[27]_2\(0),
O(2) => \cr_int_reg[31]_i_7_n_5\,
O(1) => \cr_int_reg[31]_i_7_n_6\,
O(0) => \cr_int_reg[31]_i_7_n_7\,
S(3) => \cr_int[31]_i_17_n_0\,
S(2) => \cr_int[31]_i_18_n_0\,
S(1) => \cr_int[31]_i_19_n_0\,
S(0) => \cr_int[31]_i_20_n_0\
);
\cr_int_reg[31]_i_70\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[19]_i_28_n_0\,
CO(3) => \cr_int_reg[31]_i_70_n_0\,
CO(2) => \cr_int_reg[31]_i_70_n_1\,
CO(1) => \cr_int_reg[31]_i_70_n_2\,
CO(0) => \cr_int_reg[31]_i_70_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \^cr_int_reg[23]_0\(3 downto 0),
S(3) => \cr_int[31]_i_109_n_0\,
S(2) => \cr_int[31]_i_110_n_0\,
S(1) => \cr_int[31]_i_111_n_0\,
S(0) => \cr_int[31]_i_112_n_0\
);
\cr_int_reg[31]_i_8\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[31]_i_21_n_0\,
CO(3) => \NLW_cr_int_reg[31]_i_8_CO_UNCONNECTED\(3),
CO(2) => \cr_int_reg[31]_i_8_n_1\,
CO(1) => \NLW_cr_int_reg[31]_i_8_CO_UNCONNECTED\(1),
CO(0) => \cr_int_reg[31]_i_8_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 2) => \NLW_cr_int_reg[31]_i_8_O_UNCONNECTED\(3 downto 2),
O(1) => \cr_int_reg[31]_i_8_n_6\,
O(0) => \cr_int_reg[31]_i_8_n_7\,
S(3 downto 2) => B"01",
S(1) => \cr_int[31]_i_22_n_0\,
S(0) => \cr_int[31]_i_23_n_0\
);
\cr_int_reg[31]_i_86\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cr_int_reg[31]_i_86_n_0\,
CO(2) => \cr_int_reg[31]_i_86_n_1\,
CO(1) => \cr_int_reg[31]_i_86_n_2\,
CO(0) => \cr_int_reg[31]_i_86_n_3\,
CYINIT => '0',
DI(3 downto 1) => rgb888(4 downto 2),
DI(0) => '0',
O(3) => \cr_int_reg[31]_i_86_n_4\,
O(2) => \cr_int_reg[31]_i_86_n_5\,
O(1) => \cr_int_reg[31]_i_86_n_6\,
O(0) => \cr_int_reg[31]_i_86_n_7\,
S(3) => \cr_int[31]_i_113_n_0\,
S(2) => \cr_int[31]_i_114_n_0\,
S(1) => \cr_int[31]_i_115_n_0\,
S(0) => \cr_int[31]_i_116_n_0\
);
\cr_int_reg[31]_i_9\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[31]_i_24_n_0\,
CO(3 downto 1) => \NLW_cr_int_reg[31]_i_9_CO_UNCONNECTED\(3 downto 1),
CO(0) => \cr_int_reg[31]_i_9_n_3\,
CYINIT => '0',
DI(3 downto 1) => B"000",
DI(0) => \^di\(0),
O(3 downto 2) => \NLW_cr_int_reg[31]_i_9_O_UNCONNECTED\(3 downto 2),
O(1 downto 0) => \^cr_int_reg[31]_2\(1 downto 0),
S(3 downto 2) => B"00",
S(1) => \cr_int[31]_i_25_n_0\,
S(0) => \cr_int[31]_i_26_n_0\
);
\cr_int_reg[31]_i_91\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[31]_i_86_n_0\,
CO(3) => \cr_int_reg[31]_i_91_n_0\,
CO(2) => \cr_int_reg[31]_i_91_n_1\,
CO(1) => \cr_int_reg[31]_i_91_n_2\,
CO(0) => \cr_int_reg[31]_i_91_n_3\,
CYINIT => '0',
DI(3) => rgb888(6),
DI(2 downto 0) => rgb888(7 downto 5),
O(3) => \cr_int_reg[31]_i_91_n_4\,
O(2) => \cr_int_reg[31]_i_91_n_5\,
O(1) => \cr_int_reg[31]_i_91_n_6\,
O(0) => \cr_int_reg[31]_i_91_n_7\,
S(3) => \cr_int[31]_i_117_n_0\,
S(2) => \cr_int[31]_i_118_n_0\,
S(1) => \cr_int[31]_i_119_n_0\,
S(0) => \cr_int[31]_i_120_n_0\
);
\cr_int_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[3]_i_1_n_4\,
Q => \cr_int_reg_n_0_[3]\,
R => '0'
);
\cr_int_reg[3]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cr_int_reg[3]_i_1_n_0\,
CO(2) => \cr_int_reg[3]_i_1_n_1\,
CO(1) => \cr_int_reg[3]_i_1_n_2\,
CO(0) => \cr_int_reg[3]_i_1_n_3\,
CYINIT => '1',
DI(3) => \cr_int[3]_i_2_n_0\,
DI(2) => \cr_int[3]_i_3_n_0\,
DI(1) => \cr_int[3]_i_4_n_0\,
DI(0) => '1',
O(3) => \cr_int_reg[3]_i_1_n_4\,
O(2) => \cr_int_reg[3]_i_1_n_5\,
O(1) => \cr_int_reg[3]_i_1_n_6\,
O(0) => \cr_int_reg[3]_i_1_n_7\,
S(3) => \cr_int[3]_i_5_n_0\,
S(2) => \cr_int[3]_i_6_n_0\,
S(1) => \cr_int[3]_i_7_n_0\,
S(0) => \cr_int[3]_i_8_n_0\
);
\cr_int_reg[3]_i_15\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[3]_i_21_n_0\,
CO(3) => \cr_int_reg[3]_i_15_n_0\,
CO(2) => \cr_int_reg[3]_i_15_n_1\,
CO(1) => \cr_int_reg[3]_i_15_n_2\,
CO(0) => \cr_int_reg[3]_i_15_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => cr_int_reg6(8),
O(2 downto 0) => \NLW_cr_int_reg[3]_i_15_O_UNCONNECTED\(2 downto 0),
S(3) => \cr_int[3]_i_22_n_0\,
S(2) => \cr_int[3]_i_23_n_0\,
S(1) => \cr_int[3]_i_24_n_0\,
S(0) => \cr_int[3]_i_25_n_0\
);
\cr_int_reg[3]_i_16\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cr_int_reg[3]_i_16_n_0\,
CO(2) => \cr_int_reg[3]_i_16_n_1\,
CO(1) => \cr_int_reg[3]_i_16_n_2\,
CO(0) => \cr_int_reg[3]_i_16_n_3\,
CYINIT => '0',
DI(3) => \cr_int_reg[3]_i_26_n_6\,
DI(2) => \cr_int_reg[3]_i_26_n_7\,
DI(1) => \cr_int_reg[3]_i_27_n_4\,
DI(0) => '0',
O(3) => \cr_int_reg[3]_i_16_n_4\,
O(2) => \cr_int_reg[3]_i_16_n_5\,
O(1) => \cr_int_reg[3]_i_16_n_6\,
O(0) => \cr_int_reg[3]_i_16_n_7\,
S(3) => \cr_int[3]_i_28_n_0\,
S(2) => \cr_int[3]_i_29_n_0\,
S(1) => \cr_int[3]_i_30_n_0\,
S(0) => \cr_int[3]_i_31_n_0\
);
\cr_int_reg[3]_i_19\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[3]_i_33_n_0\,
CO(3) => \cr_int_reg[3]_i_19_n_0\,
CO(2) => \cr_int_reg[3]_i_19_n_1\,
CO(1) => \cr_int_reg[3]_i_19_n_2\,
CO(0) => \cr_int_reg[3]_i_19_n_3\,
CYINIT => '0',
DI(3) => \cr_int[3]_i_34_n_0\,
DI(2) => \cr_int[3]_i_35_n_0\,
DI(1) => \cr_int[3]_i_36_n_0\,
DI(0) => \cr_int[3]_i_37_n_0\,
O(3 downto 1) => \^cr_int_reg[3]_0\(2 downto 0),
O(0) => \cr_int_reg[3]_i_19_n_7\,
S(3) => \cr_int[3]_i_38_n_0\,
S(2) => \cr_int[3]_i_39_n_0\,
S(1) => \cr_int[3]_i_40_n_0\,
S(0) => \cr_int[3]_i_41_n_0\
);
\cr_int_reg[3]_i_20\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[3]_i_42_n_0\,
CO(3) => \cr_int_reg[3]_i_20_n_0\,
CO(2) => \cr_int_reg[3]_i_20_n_1\,
CO(1) => \cr_int_reg[3]_i_20_n_2\,
CO(0) => \cr_int_reg[3]_i_20_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 2) => \^cr_int_reg[3]_2\(1 downto 0),
O(1 downto 0) => \NLW_cr_int_reg[3]_i_20_O_UNCONNECTED\(1 downto 0),
S(3) => \cr_int[3]_i_43_n_0\,
S(2) => \cr_int[3]_i_44_n_0\,
S(1) => \cr_int[3]_i_45_n_0\,
S(0) => \cr_int[3]_i_46_n_0\
);
\cr_int_reg[3]_i_21\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cr_int_reg[3]_i_21_n_0\,
CO(2) => \cr_int_reg[3]_i_21_n_1\,
CO(1) => \cr_int_reg[3]_i_21_n_2\,
CO(0) => \cr_int_reg[3]_i_21_n_3\,
CYINIT => \cr_int[3]_i_47_n_0\,
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_cr_int_reg[3]_i_21_O_UNCONNECTED\(3 downto 0),
S(3) => \cr_int[3]_i_48_n_0\,
S(2) => \cr_int[3]_i_49_n_0\,
S(1) => \cr_int[3]_i_50_n_0\,
S(0) => \cr_int[3]_i_51_n_0\
);
\cr_int_reg[3]_i_26\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[3]_i_27_n_0\,
CO(3) => \NLW_cr_int_reg[3]_i_26_CO_UNCONNECTED\(3),
CO(2) => \cr_int_reg[3]_i_26_n_1\,
CO(1) => \NLW_cr_int_reg[3]_i_26_CO_UNCONNECTED\(1),
CO(0) => \cr_int_reg[3]_i_26_n_3\,
CYINIT => '0',
DI(3 downto 2) => B"00",
DI(1) => rgb888(23),
DI(0) => '0',
O(3 downto 2) => \NLW_cr_int_reg[3]_i_26_O_UNCONNECTED\(3 downto 2),
O(1) => \cr_int_reg[3]_i_26_n_6\,
O(0) => \cr_int_reg[3]_i_26_n_7\,
S(3 downto 2) => B"01",
S(1) => \cr_int[3]_i_52_n_0\,
S(0) => \cr_int[3]_i_53_n_0\
);
\cr_int_reg[3]_i_27\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[3]_i_54_n_0\,
CO(3) => \cr_int_reg[3]_i_27_n_0\,
CO(2) => \cr_int_reg[3]_i_27_n_1\,
CO(1) => \cr_int_reg[3]_i_27_n_2\,
CO(0) => \cr_int_reg[3]_i_27_n_3\,
CYINIT => '0',
DI(3 downto 0) => rgb888(21 downto 18),
O(3) => \cr_int_reg[3]_i_27_n_4\,
O(2) => \cr_int_reg[3]_i_27_n_5\,
O(1) => \cr_int_reg[3]_i_27_n_6\,
O(0) => \cr_int_reg[3]_i_27_n_7\,
S(3) => \cr_int[3]_i_55_n_0\,
S(2) => \cr_int[3]_i_56_n_0\,
S(1) => \cr_int[3]_i_57_n_0\,
S(0) => \cr_int[3]_i_58_n_0\
);
\cr_int_reg[3]_i_32\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[3]_i_59_n_0\,
CO(3) => \cr_int_reg[3]_i_32_n_0\,
CO(2) => \cr_int_reg[3]_i_32_n_1\,
CO(1) => \cr_int_reg[3]_i_32_n_2\,
CO(0) => \cr_int_reg[3]_i_32_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cr_int_reg[3]_i_32_n_4\,
O(2 downto 0) => \NLW_cr_int_reg[3]_i_32_O_UNCONNECTED\(2 downto 0),
S(3) => \cr_int[3]_i_60_n_0\,
S(2) => \cr_int[3]_i_61_n_0\,
S(1) => \cr_int[3]_i_62_n_0\,
S(0) => \cr_int[3]_i_63_n_0\
);
\cr_int_reg[3]_i_33\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cr_int_reg[3]_i_33_n_0\,
CO(2) => \cr_int_reg[3]_i_33_n_1\,
CO(1) => \cr_int_reg[3]_i_33_n_2\,
CO(0) => \cr_int_reg[3]_i_33_n_3\,
CYINIT => '0',
DI(3) => \cr_int_reg[3]_i_64_n_6\,
DI(2) => \cr_int_reg[3]_i_64_n_7\,
DI(1) => \cr_int_reg[3]_i_65_n_4\,
DI(0) => \cr_int_reg[3]_i_65_n_5\,
O(3) => \cr_int_reg[3]_i_33_n_4\,
O(2) => \cr_int_reg[3]_i_33_n_5\,
O(1) => \cr_int_reg[3]_i_33_n_6\,
O(0) => \NLW_cr_int_reg[3]_i_33_O_UNCONNECTED\(0),
S(3) => \cr_int[3]_i_66_n_0\,
S(2) => \cr_int[3]_i_67_n_0\,
S(1) => \cr_int[3]_i_68_n_0\,
S(0) => \cr_int[3]_i_69_n_0\
);
\cr_int_reg[3]_i_42\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cr_int_reg[3]_i_42_n_0\,
CO(2) => \cr_int_reg[3]_i_42_n_1\,
CO(1) => \cr_int_reg[3]_i_42_n_2\,
CO(0) => \cr_int_reg[3]_i_42_n_3\,
CYINIT => \cr_int[3]_i_71_n_0\,
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_cr_int_reg[3]_i_42_O_UNCONNECTED\(3 downto 0),
S(3) => \cr_int[3]_i_72_n_0\,
S(2) => \cr_int[3]_i_73_n_0\,
S(1) => \cr_int[3]_i_74_n_0\,
S(0) => \cr_int[3]_i_75_n_0\
);
\cr_int_reg[3]_i_54\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cr_int_reg[3]_i_54_n_0\,
CO(2) => \cr_int_reg[3]_i_54_n_1\,
CO(1) => \cr_int_reg[3]_i_54_n_2\,
CO(0) => \cr_int_reg[3]_i_54_n_3\,
CYINIT => '0',
DI(3 downto 2) => rgb888(17 downto 16),
DI(1 downto 0) => B"01",
O(3) => \cr_int_reg[3]_i_54_n_4\,
O(2) => \cr_int_reg[3]_i_54_n_5\,
O(1) => \cr_int_reg[3]_i_54_n_6\,
O(0) => \cr_int_reg[3]_i_54_n_7\,
S(3) => \cr_int[3]_i_76_n_0\,
S(2) => \cr_int[3]_i_77_n_0\,
S(1) => \cr_int[3]_i_78_n_0\,
S(0) => \cr_int[3]_i_79_n_0\
);
\cr_int_reg[3]_i_59\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cr_int_reg[3]_i_59_n_0\,
CO(2) => \cr_int_reg[3]_i_59_n_1\,
CO(1) => \cr_int_reg[3]_i_59_n_2\,
CO(0) => \cr_int_reg[3]_i_59_n_3\,
CYINIT => \cr_int[3]_i_80_n_0\,
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_cr_int_reg[3]_i_59_O_UNCONNECTED\(3 downto 0),
S(3) => \cr_int[3]_i_81_n_0\,
S(2) => \cr_int[3]_i_82_n_0\,
S(1) => \cr_int[3]_i_83_n_0\,
S(0) => \cr_int[3]_i_84_n_0\
);
\cr_int_reg[3]_i_64\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[3]_i_65_n_0\,
CO(3) => \cr_int_reg[3]_i_64_n_0\,
CO(2) => \cr_int_reg[3]_i_64_n_1\,
CO(1) => \cr_int_reg[3]_i_64_n_2\,
CO(0) => \cr_int_reg[3]_i_64_n_3\,
CYINIT => '0',
DI(3) => rgb888(15),
DI(2 downto 0) => rgb888(12 downto 10),
O(3) => \cr_int_reg[3]_i_64_n_4\,
O(2) => \cr_int_reg[3]_i_64_n_5\,
O(1) => \cr_int_reg[3]_i_64_n_6\,
O(0) => \cr_int_reg[3]_i_64_n_7\,
S(3) => \cr_int[3]_i_85_n_0\,
S(2) => \cr_int[3]_i_86_n_0\,
S(1) => \cr_int[3]_i_87_n_0\,
S(0) => \cr_int[3]_i_88_n_0\
);
\cr_int_reg[3]_i_65\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cr_int_reg[3]_i_65_n_0\,
CO(2) => \cr_int_reg[3]_i_65_n_1\,
CO(1) => \cr_int_reg[3]_i_65_n_2\,
CO(0) => \cr_int_reg[3]_i_65_n_3\,
CYINIT => '0',
DI(3 downto 2) => rgb888(9 downto 8),
DI(1 downto 0) => B"01",
O(3) => \cr_int_reg[3]_i_65_n_4\,
O(2) => \cr_int_reg[3]_i_65_n_5\,
O(1) => \cr_int_reg[3]_i_65_n_6\,
O(0) => \NLW_cr_int_reg[3]_i_65_O_UNCONNECTED\(0),
S(3) => \cr_int[3]_i_89_n_0\,
S(2) => \cr_int[3]_i_90_n_0\,
S(1) => \cr_int[3]_i_91_n_0\,
S(0) => \cr_int[3]_i_92_n_0\
);
\cr_int_reg[3]_i_70\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cr_int_reg[3]_i_70_n_0\,
CO(2) => \cr_int_reg[3]_i_70_n_1\,
CO(1) => \cr_int_reg[3]_i_70_n_2\,
CO(0) => \cr_int_reg[3]_i_70_n_3\,
CYINIT => '0',
DI(3 downto 1) => rgb888(12 downto 10),
DI(0) => '0',
O(3) => \cr_int_reg[3]_i_70_n_4\,
O(2) => \cr_int_reg[3]_i_70_n_5\,
O(1) => \cr_int_reg[3]_i_70_n_6\,
O(0) => \cr_int_reg[3]_i_70_n_7\,
S(3) => \cr_int[3]_i_93_n_0\,
S(2) => \cr_int[3]_i_94_n_0\,
S(1) => \cr_int[3]_i_95_n_0\,
S(0) => \cr_int[3]_i_96_n_0\
);
\cr_int_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[7]_i_1_n_7\,
Q => \cr_int_reg_n_0_[4]\,
R => '0'
);
\cr_int_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[7]_i_1_n_6\,
Q => \cr_int_reg_n_0_[5]\,
R => '0'
);
\cr_int_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[7]_i_1_n_5\,
Q => \cr_int_reg_n_0_[6]\,
R => '0'
);
\cr_int_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[7]_i_1_n_4\,
Q => \cr_int_reg_n_0_[7]\,
R => '0'
);
\cr_int_reg[7]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[3]_i_1_n_0\,
CO(3) => \cr_int_reg[7]_i_1_n_0\,
CO(2) => \cr_int_reg[7]_i_1_n_1\,
CO(1) => \cr_int_reg[7]_i_1_n_2\,
CO(0) => \cr_int_reg[7]_i_1_n_3\,
CYINIT => '0',
DI(3) => \cr_int[7]_i_2_n_0\,
DI(2) => \cr_int[7]_i_3_n_0\,
DI(1) => \cr_int[7]_i_4_n_0\,
DI(0) => \cr_int[7]_i_5_n_0\,
O(3) => \cr_int_reg[7]_i_1_n_4\,
O(2) => \cr_int_reg[7]_i_1_n_5\,
O(1) => \cr_int_reg[7]_i_1_n_6\,
O(0) => \cr_int_reg[7]_i_1_n_7\,
S(3) => \cr_int[7]_i_6_n_0\,
S(2) => \cr_int[7]_i_7_n_0\,
S(1) => \cr_int[7]_i_8_n_0\,
S(0) => \cr_int[7]_i_9_n_0\
);
\cr_int_reg[7]_i_23\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[3]_i_20_n_0\,
CO(3) => \cr_int_reg[7]_i_23_n_0\,
CO(2) => \cr_int_reg[7]_i_23_n_1\,
CO(1) => \cr_int_reg[7]_i_23_n_2\,
CO(0) => \cr_int_reg[7]_i_23_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \^cr_int_reg[7]_1\(3 downto 0),
S(3) => \cr_int[7]_i_25_n_0\,
S(2) => \cr_int[7]_i_26_n_0\,
S(1) => \cr_int[7]_i_27_n_0\,
S(0) => \cr_int[7]_i_28_n_0\
);
\cr_int_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[11]_i_1_n_7\,
Q => \cr_int_reg__0\(8),
R => '0'
);
\cr_int_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[11]_i_1_n_6\,
Q => \cr_int_reg__0\(9),
R => '0'
);
\cr_reg[0]\: unisim.vcomponents.FDSE
port map (
C => cb_regn_0_0,
CE => '1',
D => \cr[0]_i_1_n_0\,
Q => cr(0),
S => \cr_reg[7]_i_1_n_0\
);
\cr_reg[1]\: unisim.vcomponents.FDSE
port map (
C => cb_regn_0_0,
CE => '1',
D => \cr[1]_i_1_n_0\,
Q => cr(1),
S => \cr_reg[7]_i_1_n_0\
);
\cr_reg[2]\: unisim.vcomponents.FDSE
port map (
C => cb_regn_0_0,
CE => '1',
D => \cr[2]_i_1_n_0\,
Q => cr(2),
S => \cr_reg[7]_i_1_n_0\
);
\cr_reg[3]\: unisim.vcomponents.FDSE
port map (
C => cb_regn_0_0,
CE => '1',
D => \cr[3]_i_1_n_0\,
Q => cr(3),
S => \cr_reg[7]_i_1_n_0\
);
\cr_reg[4]\: unisim.vcomponents.FDSE
port map (
C => cb_regn_0_0,
CE => '1',
D => \cr[4]_i_1_n_0\,
Q => cr(4),
S => \cr_reg[7]_i_1_n_0\
);
\cr_reg[5]\: unisim.vcomponents.FDSE
port map (
C => cb_regn_0_0,
CE => '1',
D => \cr[5]_i_1_n_0\,
Q => cr(5),
S => \cr_reg[7]_i_1_n_0\
);
\cr_reg[6]\: unisim.vcomponents.FDSE
port map (
C => cb_regn_0_0,
CE => '1',
D => \cr[6]_i_1_n_0\,
Q => cr(6),
S => \cr_reg[7]_i_1_n_0\
);
\cr_reg[7]\: unisim.vcomponents.FDSE
port map (
C => cb_regn_0_0,
CE => '1',
D => \cr[7]_i_2_n_0\,
Q => cr(7),
S => \cr_reg[7]_i_1_n_0\
);
\cr_reg[7]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \cr_reg[7]_i_3_n_0\,
CO(3) => \cr_reg[7]_i_1_n_0\,
CO(2) => \cr_reg[7]_i_1_n_1\,
CO(1) => \cr_reg[7]_i_1_n_2\,
CO(0) => \cr_reg[7]_i_1_n_3\,
CYINIT => '0',
DI(3) => \cr[7]_i_4_n_0\,
DI(2) => \cr[7]_i_5_n_0\,
DI(1) => \cr[7]_i_6_n_0\,
DI(0) => \cr[7]_i_7_n_0\,
O(3 downto 0) => \NLW_cr_reg[7]_i_1_O_UNCONNECTED\(3 downto 0),
S(3) => \cr[7]_i_8_n_0\,
S(2) => \cr[7]_i_9_n_0\,
S(1) => \cr[7]_i_10_n_0\,
S(0) => \cr[7]_i_11_n_0\
);
\cr_reg[7]_i_12\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cr_reg[7]_i_12_n_0\,
CO(2) => \cr_reg[7]_i_12_n_1\,
CO(1) => \cr_reg[7]_i_12_n_2\,
CO(0) => \cr_reg[7]_i_12_n_3\,
CYINIT => '0',
DI(3) => \cr[7]_i_21_n_0\,
DI(2) => \cr[7]_i_22_n_0\,
DI(1) => \cr[7]_i_23_n_0\,
DI(0) => \cr[7]_i_24_n_0\,
O(3 downto 0) => \NLW_cr_reg[7]_i_12_O_UNCONNECTED\(3 downto 0),
S(3) => \cr[7]_i_25_n_0\,
S(2) => \cr[7]_i_26_n_0\,
S(1) => \cr[7]_i_27_n_0\,
S(0) => \cr[7]_i_28_n_0\
);
\cr_reg[7]_i_3\: unisim.vcomponents.CARRY4
port map (
CI => \cr_reg[7]_i_12_n_0\,
CO(3) => \cr_reg[7]_i_3_n_0\,
CO(2) => \cr_reg[7]_i_3_n_1\,
CO(1) => \cr_reg[7]_i_3_n_2\,
CO(0) => \cr_reg[7]_i_3_n_3\,
CYINIT => '0',
DI(3) => \cr[7]_i_13_n_0\,
DI(2) => \cr[7]_i_14_n_0\,
DI(1) => \cr[7]_i_15_n_0\,
DI(0) => \cr[7]_i_16_n_0\,
O(3 downto 0) => \NLW_cr_reg[7]_i_3_O_UNCONNECTED\(3 downto 0),
S(3) => \cr[7]_i_17_n_0\,
S(2) => \cr[7]_i_18_n_0\,
S(1) => \cr[7]_i_19_n_0\,
S(0) => \cr[7]_i_20_n_0\
);
edge_i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => edge,
O => edge_i_1_n_0
);
edge_rb_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => edge,
I1 => edge_rb,
O => edge_rb_i_1_n_0
);
edge_rb_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x2,
CE => '1',
D => edge_rb_i_1_n_0,
Q => edge_rb,
R => \hdmi_d[15]_i_1_n_0\
);
edge_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x2,
CE => '1',
D => edge_i_1_n_0,
Q => edge,
R => '0'
);
\hdmi_clk_bits_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => '1',
D => edge_i_1_n_0,
Q => D1,
R => '0'
);
\hdmi_d[10]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AACCAACCF0FFF000"
)
port map (
I0 => cb_hold(2),
I1 => \cr_hold_reg_n_0_[2]\,
I2 => y_hold(2),
I3 => edge_rb,
I4 => y(2),
I5 => edge,
O => \hdmi_d[10]_i_1_n_0\
);
\hdmi_d[11]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AACCAACCF0FFF000"
)
port map (
I0 => cb_hold(3),
I1 => \cr_hold_reg_n_0_[3]\,
I2 => y_hold(3),
I3 => edge_rb,
I4 => y(3),
I5 => edge,
O => \hdmi_d[11]_i_1_n_0\
);
\hdmi_d[12]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AACCAACCF0FFF000"
)
port map (
I0 => cb_hold(4),
I1 => \cr_hold_reg_n_0_[4]\,
I2 => y_hold(4),
I3 => edge_rb,
I4 => y(4),
I5 => edge,
O => \hdmi_d[12]_i_1_n_0\
);
\hdmi_d[13]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AACCAACCF0FFF000"
)
port map (
I0 => cb_hold(5),
I1 => \cr_hold_reg_n_0_[5]\,
I2 => y_hold(5),
I3 => edge_rb,
I4 => y(5),
I5 => edge,
O => \hdmi_d[13]_i_1_n_0\
);
\hdmi_d[14]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AACCAACCF0FFF000"
)
port map (
I0 => cb_hold(6),
I1 => \cr_hold_reg_n_0_[6]\,
I2 => y_hold(6),
I3 => edge_rb,
I4 => y(6),
I5 => edge,
O => \hdmi_d[14]_i_1_n_0\
);
\hdmi_d[15]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => active,
O => \hdmi_d[15]_i_1_n_0\
);
\hdmi_d[15]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AACCAACCF0FFF000"
)
port map (
I0 => cb_hold(7),
I1 => \cr_hold_reg_n_0_[7]\,
I2 => y_hold(7),
I3 => edge_rb,
I4 => y(7),
I5 => edge,
O => \hdmi_d[15]_i_2_n_0\
);
\hdmi_d[8]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AACCAACCF0FFF000"
)
port map (
I0 => cb_hold(0),
I1 => \cr_hold_reg_n_0_[0]\,
I2 => y_hold(0),
I3 => edge_rb,
I4 => y(0),
I5 => edge,
O => \hdmi_d[8]_i_1_n_0\
);
\hdmi_d[9]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AACCAACCF0FFF000"
)
port map (
I0 => cb_hold(1),
I1 => \cr_hold_reg_n_0_[1]\,
I2 => y_hold(1),
I3 => edge_rb,
I4 => y(1),
I5 => edge,
O => \hdmi_d[9]_i_1_n_0\
);
\hdmi_d_reg[10]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => '1',
D => \hdmi_d[10]_i_1_n_0\,
Q => hdmi_d(2),
R => \hdmi_d[15]_i_1_n_0\
);
\hdmi_d_reg[11]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => '1',
D => \hdmi_d[11]_i_1_n_0\,
Q => hdmi_d(3),
R => \hdmi_d[15]_i_1_n_0\
);
\hdmi_d_reg[12]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => '1',
D => \hdmi_d[12]_i_1_n_0\,
Q => hdmi_d(4),
R => \hdmi_d[15]_i_1_n_0\
);
\hdmi_d_reg[13]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => '1',
D => \hdmi_d[13]_i_1_n_0\,
Q => hdmi_d(5),
R => \hdmi_d[15]_i_1_n_0\
);
\hdmi_d_reg[14]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => '1',
D => \hdmi_d[14]_i_1_n_0\,
Q => hdmi_d(6),
R => \hdmi_d[15]_i_1_n_0\
);
\hdmi_d_reg[15]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => '1',
D => \hdmi_d[15]_i_2_n_0\,
Q => hdmi_d(7),
R => \hdmi_d[15]_i_1_n_0\
);
\hdmi_d_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => '1',
D => \hdmi_d[8]_i_1_n_0\,
Q => hdmi_d(0),
R => \hdmi_d[15]_i_1_n_0\
);
\hdmi_d_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => '1',
D => \hdmi_d[9]_i_1_n_0\,
Q => hdmi_d(1),
R => \hdmi_d[15]_i_1_n_0\
);
hdmi_de_reg: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => '1',
D => active,
Q => hdmi_de,
R => '0'
);
hdmi_hsync_i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => hsync,
O => p_0_in
);
hdmi_hsync_reg: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => '1',
D => p_0_in,
Q => hdmi_hsync,
R => '0'
);
hdmi_vsync_i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => vsync,
O => hdmi_vsync_i_1_n_0
);
hdmi_vsync_reg: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => '1',
D => hdmi_vsync_i_1_n_0,
Q => hdmi_vsync,
R => '0'
);
\y[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \y_int_reg_n_0_[0]\,
I1 => \y_int_reg__0\(31),
O => \y[0]_i_1_n_0\
);
\y[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \y_int_reg_n_0_[1]\,
I1 => \y_int_reg__0\(31),
O => \y[1]_i_1_n_0\
);
\y[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \y_int_reg_n_0_[2]\,
I1 => \y_int_reg__0\(31),
O => \y[2]_i_1_n_0\
);
\y[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \y_int_reg_n_0_[3]\,
I1 => \y_int_reg__0\(31),
O => \y[3]_i_1_n_0\
);
\y[4]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \y_int_reg_n_0_[4]\,
I1 => \y_int_reg__0\(31),
O => \y[4]_i_1_n_0\
);
\y[5]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \y_int_reg_n_0_[5]\,
I1 => \y_int_reg__0\(31),
O => \y[5]_i_1_n_0\
);
\y[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \y_int_reg_n_0_[6]\,
I1 => \y_int_reg__0\(31),
O => \y[6]_i_1_n_0\
);
\y[7]_i_10\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg__0\(26),
I1 => \y_int_reg__0\(27),
O => \y[7]_i_10_n_0\
);
\y[7]_i_11\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg__0\(24),
I1 => \y_int_reg__0\(25),
O => \y[7]_i_11_n_0\
);
\y[7]_i_13\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \y_int_reg__0\(22),
I1 => \y_int_reg__0\(23),
O => \y[7]_i_13_n_0\
);
\y[7]_i_14\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \y_int_reg__0\(20),
I1 => \y_int_reg__0\(21),
O => \y[7]_i_14_n_0\
);
\y[7]_i_15\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \y_int_reg__0\(18),
I1 => \y_int_reg__0\(19),
O => \y[7]_i_15_n_0\
);
\y[7]_i_16\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \y_int_reg__0\(16),
I1 => \y_int_reg__0\(17),
O => \y[7]_i_16_n_0\
);
\y[7]_i_17\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg__0\(22),
I1 => \y_int_reg__0\(23),
O => \y[7]_i_17_n_0\
);
\y[7]_i_18\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg__0\(20),
I1 => \y_int_reg__0\(21),
O => \y[7]_i_18_n_0\
);
\y[7]_i_19\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg__0\(18),
I1 => \y_int_reg__0\(19),
O => \y[7]_i_19_n_0\
);
\y[7]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \y_int_reg_n_0_[7]\,
I1 => \y_int_reg__0\(31),
O => \y[7]_i_2_n_0\
);
\y[7]_i_20\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg__0\(16),
I1 => \y_int_reg__0\(17),
O => \y[7]_i_20_n_0\
);
\y[7]_i_21\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \y_int_reg__0\(14),
I1 => \y_int_reg__0\(15),
O => \y[7]_i_21_n_0\
);
\y[7]_i_22\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \y_int_reg__0\(12),
I1 => \y_int_reg__0\(13),
O => \y[7]_i_22_n_0\
);
\y[7]_i_23\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \y_int_reg__0\(10),
I1 => \y_int_reg__0\(11),
O => \y[7]_i_23_n_0\
);
\y[7]_i_24\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \y_int_reg__0\(8),
I1 => \y_int_reg__0\(9),
O => \y[7]_i_24_n_0\
);
\y[7]_i_25\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg__0\(14),
I1 => \y_int_reg__0\(15),
O => \y[7]_i_25_n_0\
);
\y[7]_i_26\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg__0\(12),
I1 => \y_int_reg__0\(13),
O => \y[7]_i_26_n_0\
);
\y[7]_i_27\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg__0\(10),
I1 => \y_int_reg__0\(11),
O => \y[7]_i_27_n_0\
);
\y[7]_i_28\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg__0\(8),
I1 => \y_int_reg__0\(9),
O => \y[7]_i_28_n_0\
);
\y[7]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \y_int_reg__0\(30),
I1 => \y_int_reg__0\(31),
O => \y[7]_i_4_n_0\
);
\y[7]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \y_int_reg__0\(28),
I1 => \y_int_reg__0\(29),
O => \y[7]_i_5_n_0\
);
\y[7]_i_6\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \y_int_reg__0\(26),
I1 => \y_int_reg__0\(27),
O => \y[7]_i_6_n_0\
);
\y[7]_i_7\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \y_int_reg__0\(24),
I1 => \y_int_reg__0\(25),
O => \y[7]_i_7_n_0\
);
\y[7]_i_8\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg__0\(30),
I1 => \y_int_reg__0\(31),
O => \y[7]_i_8_n_0\
);
\y[7]_i_9\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg__0\(28),
I1 => \y_int_reg__0\(29),
O => \y[7]_i_9_n_0\
);
\y_hold[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => y_hold(0),
I1 => y(0),
I2 => edge_rb,
O => p_1_in(0)
);
\y_hold[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => y_hold(1),
I1 => y(1),
I2 => edge_rb,
O => p_1_in(1)
);
\y_hold[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => y_hold(2),
I1 => y(2),
I2 => edge_rb,
O => p_1_in(2)
);
\y_hold[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => y_hold(3),
I1 => y(3),
I2 => edge_rb,
O => p_1_in(3)
);
\y_hold[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => y_hold(4),
I1 => y(4),
I2 => edge_rb,
O => p_1_in(4)
);
\y_hold[5]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => y_hold(5),
I1 => y(5),
I2 => edge_rb,
O => p_1_in(5)
);
\y_hold[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => y_hold(6),
I1 => y(6),
I2 => edge_rb,
O => p_1_in(6)
);
\y_hold[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => y_hold(7),
I1 => y(7),
I2 => edge_rb,
O => p_1_in(7)
);
\y_hold_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => edge_i_1_n_0,
D => p_1_in(0),
Q => y_hold(0),
R => '0'
);
\y_hold_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => edge_i_1_n_0,
D => p_1_in(1),
Q => y_hold(1),
R => '0'
);
\y_hold_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => edge_i_1_n_0,
D => p_1_in(2),
Q => y_hold(2),
R => '0'
);
\y_hold_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => edge_i_1_n_0,
D => p_1_in(3),
Q => y_hold(3),
R => '0'
);
\y_hold_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => edge_i_1_n_0,
D => p_1_in(4),
Q => y_hold(4),
R => '0'
);
\y_hold_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => edge_i_1_n_0,
D => p_1_in(5),
Q => y_hold(5),
R => '0'
);
\y_hold_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => edge_i_1_n_0,
D => p_1_in(6),
Q => y_hold(6),
R => '0'
);
\y_hold_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => edge_i_1_n_0,
D => p_1_in(7),
Q => y_hold(7),
R => '0'
);
\y_int[11]_i_10\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \y_int_reg[15]_i_33_n_6\,
I1 => \rgb888[8]_21\(2),
I2 => \rgb888[8]_29\(0),
I3 => \^y_int_reg[3]_1\(0),
O => \y_int[11]_i_10_n_0\
);
\y_int[11]_i_100\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(1),
I1 => rgb888(0),
O => \y_int[11]_i_100_n_0\
);
\y_int[11]_i_11\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \rgb888[1]\(1),
I1 => \^y_int_reg[23]_0\(0),
I2 => \^y_int_reg[15]_0\(1),
I3 => \^y_int_reg[7]_0\(0),
O => y_int_reg1(10)
);
\y_int[11]_i_12\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \y_int_reg[15]_i_33_n_7\,
I1 => \rgb888[8]_21\(2),
I2 => \rgb888[8]_22\(3),
I3 => \^y_int_reg[3]_1\(0),
O => \y_int[11]_i_12_n_0\
);
\y_int[11]_i_13\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \rgb888[1]\(0),
I1 => \^y_int_reg[23]_0\(0),
I2 => \^y_int_reg[15]_0\(0),
I3 => \^y_int_reg[7]_0\(0),
O => y_int_reg1(9)
);
\y_int[11]_i_16\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \y_int_reg[11]_i_38_n_4\,
I1 => \rgb888[8]_21\(2),
I2 => \rgb888[8]_21\(1),
I3 => \^y_int_reg[3]_1\(0),
I4 => \rgb888[8]_22\(2),
O => \y_int[11]_i_16_n_0\
);
\y_int[11]_i_17\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => y_int_reg2(8),
I1 => \^y_int_reg[23]_0\(0),
I2 => \y_int_reg[11]_i_21_n_4\,
I3 => \^y_int_reg[7]_0\(0),
O => y_int_reg1(8)
);
\y_int[11]_i_18\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => y_int_reg3(7),
I1 => \y_int_reg[31]_i_8_n_5\,
I2 => \y_int_reg[31]_i_8_n_6\,
I3 => y_int_reg6,
I4 => y_int_reg5(15),
O => y_int_reg20_in(7)
);
\y_int[11]_i_19\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \y_int_reg[11]_i_38_n_5\,
I1 => \rgb888[8]_21\(2),
I2 => \rgb888[8]_21\(0),
I3 => \^y_int_reg[3]_1\(0),
I4 => \rgb888[8]_22\(1),
O => \y_int[11]_i_19_n_0\
);
\y_int[11]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => y_int_reg6,
I1 => y_int_reg5(18),
I2 => \y_int_reg[31]_i_8_n_5\,
I3 => y_int_reg3(10),
I4 => \y_int[11]_i_10_n_0\,
I5 => y_int_reg1(10),
O => \y_int[11]_i_2_n_0\
);
\y_int[11]_i_23\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => y_int_reg3(11),
I1 => \y_int_reg[31]_i_8_n_5\,
I2 => y_int_reg5(19),
I3 => y_int_reg6,
O => y_int_reg20_in(11)
);
\y_int[11]_i_24\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => y_int_reg3(10),
I1 => \y_int_reg[31]_i_8_n_5\,
I2 => y_int_reg5(18),
I3 => y_int_reg6,
O => y_int_reg20_in(10)
);
\y_int[11]_i_25\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => y_int_reg3(9),
I1 => \y_int_reg[31]_i_8_n_5\,
I2 => y_int_reg5(17),
I3 => y_int_reg6,
O => y_int_reg20_in(9)
);
\y_int[11]_i_26\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => y_int_reg3(8),
I1 => \y_int_reg[31]_i_8_n_5\,
I2 => y_int_reg5(16),
I3 => y_int_reg6,
O => y_int_reg20_in(8)
);
\y_int[11]_i_29\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
O => \y_int[11]_i_29_n_0\
);
\y_int[11]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => y_int_reg6,
I1 => y_int_reg5(17),
I2 => \y_int_reg[31]_i_8_n_5\,
I3 => y_int_reg3(9),
I4 => \y_int[11]_i_12_n_0\,
I5 => y_int_reg1(9),
O => \y_int[11]_i_3_n_0\
);
\y_int[11]_i_30\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_8_n_6\,
O => \y_int[11]_i_30_n_0\
);
\y_int[11]_i_31\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_8_n_7\,
O => \y_int[11]_i_31_n_0\
);
\y_int[11]_i_32\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_16_n_4\,
O => \y_int[11]_i_32_n_0\
);
\y_int[11]_i_34\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
I1 => y_int_reg6,
I2 => y_int_reg5(16),
O => \y_int[11]_i_34_n_0\
);
\y_int[11]_i_35\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => y_int_reg5(15),
I1 => y_int_reg6,
I2 => \y_int_reg[31]_i_8_n_6\,
O => \y_int[11]_i_35_n_0\
);
\y_int[11]_i_36\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => y_int_reg5(14),
I1 => y_int_reg6,
I2 => \y_int_reg[31]_i_8_n_7\,
O => \y_int[11]_i_36_n_0\
);
\y_int[11]_i_37\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => y_int_reg5(13),
I1 => y_int_reg6,
I2 => \y_int_reg[31]_i_16_n_4\,
O => \y_int[11]_i_37_n_0\
);
\y_int[11]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => y_int_reg6,
I1 => y_int_reg5(16),
I2 => \y_int_reg[31]_i_8_n_5\,
I3 => y_int_reg3(8),
I4 => \y_int[11]_i_16_n_0\,
I5 => y_int_reg1(8),
O => \y_int[11]_i_4_n_0\
);
\y_int[11]_i_40\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
I1 => \^y_int_reg[7]_0\(0),
I2 => \y_int_reg[11]_i_21_n_4\,
O => \y_int[11]_i_40_n_0\
);
\y_int[11]_i_41\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
I1 => \^y_int_reg[7]_0\(0),
I2 => \y_int_reg[11]_i_21_n_5\,
O => \y_int[11]_i_41_n_0\
);
\y_int[11]_i_42\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
I1 => \^y_int_reg[7]_0\(0),
I2 => \y_int_reg[11]_i_21_n_6\,
O => \y_int[11]_i_42_n_0\
);
\y_int[11]_i_43\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \y_int_reg[11]_i_21_n_7\,
I1 => \^y_int_reg[7]_0\(0),
I2 => \y_int_reg[31]_i_11_n_5\,
O => \y_int[11]_i_43_n_0\
);
\y_int[11]_i_45\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
O => \y_int[11]_i_45_n_0\
);
\y_int[11]_i_46\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
O => \y_int[11]_i_46_n_0\
);
\y_int[11]_i_47\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
O => \y_int[11]_i_47_n_0\
);
\y_int[11]_i_48\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_11_n_5\,
O => \y_int[11]_i_48_n_0\
);
\y_int[11]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"E888E888E8EEE888"
)
port map (
I0 => y_int_reg20_in(7),
I1 => \y_int[11]_i_19_n_0\,
I2 => y_int_reg2(7),
I3 => \^y_int_reg[23]_0\(0),
I4 => \y_int_reg[11]_i_21_n_5\,
I5 => \^y_int_reg[7]_0\(0),
O => \y_int[11]_i_5_n_0\
);
\y_int[11]_i_50\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
O => \y_int[11]_i_50_n_0\
);
\y_int[11]_i_51\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
O => \y_int[11]_i_51_n_0\
);
\y_int[11]_i_52\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
O => \y_int[11]_i_52_n_0\
);
\y_int[11]_i_53\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
O => \y_int[11]_i_53_n_0\
);
\y_int[11]_i_58\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_16_n_5\,
O => \y_int[11]_i_58_n_0\
);
\y_int[11]_i_59\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_16_n_6\,
O => \y_int[11]_i_59_n_0\
);
\y_int[11]_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \y_int[11]_i_2_n_0\,
I1 => y_int_reg1(11),
I2 => \y_int[15]_i_18_n_0\,
I3 => y_int_reg20_in(11),
O => \y_int[11]_i_6_n_0\
);
\y_int[11]_i_60\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_16_n_7\,
O => \y_int[11]_i_60_n_0\
);
\y_int[11]_i_61\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[3]_i_16_n_4\,
O => \y_int[11]_i_61_n_0\
);
\y_int[11]_i_62\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => y_int_reg5(8),
I1 => y_int_reg6,
I2 => \y_int_reg[3]_i_16_n_5\,
O => \y_int[11]_i_62_n_0\
);
\y_int[11]_i_63\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => y_int_reg5(12),
I1 => y_int_reg6,
I2 => \y_int_reg[31]_i_16_n_5\,
O => \y_int[11]_i_63_n_0\
);
\y_int[11]_i_64\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => y_int_reg5(11),
I1 => y_int_reg6,
I2 => \y_int_reg[31]_i_16_n_6\,
O => \y_int[11]_i_64_n_0\
);
\y_int[11]_i_65\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => y_int_reg5(10),
I1 => y_int_reg6,
I2 => \y_int_reg[31]_i_16_n_7\,
O => \y_int[11]_i_65_n_0\
);
\y_int[11]_i_66\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => y_int_reg5(9),
I1 => y_int_reg6,
I2 => \y_int_reg[3]_i_16_n_4\,
O => \y_int[11]_i_66_n_0\
);
\y_int[11]_i_67\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \rgb888[8]_22\(2),
I1 => \^y_int_reg[3]_1\(0),
I2 => \rgb888[8]_21\(1),
O => \y_int[11]_i_67_n_0\
);
\y_int[11]_i_68\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \rgb888[8]_22\(1),
I1 => \^y_int_reg[3]_1\(0),
I2 => \rgb888[8]_21\(0),
O => \y_int[11]_i_68_n_0\
);
\y_int[11]_i_69\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \rgb888[8]_22\(0),
I1 => \^y_int_reg[3]_1\(0),
I2 => \rgb888[8]_20\(3),
O => \y_int[11]_i_69_n_0\
);
\y_int[11]_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \y_int[11]_i_3_n_0\,
I1 => y_int_reg1(10),
I2 => \y_int[11]_i_10_n_0\,
I3 => y_int_reg20_in(10),
O => \y_int[11]_i_7_n_0\
);
\y_int[11]_i_70\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \rgb888[14]_1\(3),
I1 => \^y_int_reg[3]_1\(0),
I2 => \rgb888[8]_20\(2),
O => \y_int[11]_i_70_n_0\
);
\y_int[11]_i_71\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \y_int_reg[3]_i_35_n_4\,
I1 => \^y_int_reg[7]_0\(0),
I2 => \y_int_reg[31]_i_30_n_6\,
O => \y_int[11]_i_71_n_0\
);
\y_int[11]_i_72\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \y_int_reg[11]_i_44_n_4\,
I1 => \^y_int_reg[7]_0\(0),
I2 => \y_int_reg[31]_i_11_n_6\,
O => \y_int[11]_i_72_n_0\
);
\y_int[11]_i_73\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \y_int_reg[11]_i_44_n_5\,
I1 => \^y_int_reg[7]_0\(0),
I2 => \y_int_reg[31]_i_11_n_7\,
O => \y_int[11]_i_73_n_0\
);
\y_int[11]_i_74\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \y_int_reg[11]_i_44_n_6\,
I1 => \^y_int_reg[7]_0\(0),
I2 => \y_int_reg[31]_i_30_n_4\,
O => \y_int[11]_i_74_n_0\
);
\y_int[11]_i_75\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \y_int_reg[11]_i_44_n_7\,
I1 => \^y_int_reg[7]_0\(0),
I2 => \y_int_reg[31]_i_30_n_5\,
O => \y_int[11]_i_75_n_0\
);
\y_int[11]_i_76\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_11_n_6\,
O => \y_int[11]_i_76_n_0\
);
\y_int[11]_i_77\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_11_n_7\,
O => \y_int[11]_i_77_n_0\
);
\y_int[11]_i_78\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_30_n_4\,
O => \y_int[11]_i_78_n_0\
);
\y_int[11]_i_79\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_30_n_5\,
O => \y_int[11]_i_79_n_0\
);
\y_int[11]_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \y_int[11]_i_4_n_0\,
I1 => y_int_reg1(9),
I2 => \y_int[11]_i_12_n_0\,
I3 => y_int_reg20_in(9),
O => \y_int[11]_i_8_n_0\
);
\y_int[11]_i_81\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
O => \y_int[11]_i_81_n_0\
);
\y_int[11]_i_82\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
O => \y_int[11]_i_82_n_0\
);
\y_int[11]_i_83\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
O => \y_int[11]_i_83_n_0\
);
\y_int[11]_i_84\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
O => \y_int[11]_i_84_n_0\
);
\y_int[11]_i_86\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \y_int_reg[31]_i_11_n_6\,
I1 => \y_int_reg[31]_i_11_n_5\,
O => \y_int[11]_i_86_n_0\
);
\y_int[11]_i_87\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \y_int_reg[31]_i_30_n_4\,
I1 => \y_int_reg[31]_i_11_n_7\,
O => \y_int[11]_i_87_n_0\
);
\y_int[11]_i_88\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \y_int_reg[31]_i_30_n_6\,
I1 => \y_int_reg[31]_i_30_n_5\,
O => \y_int[11]_i_88_n_0\
);
\y_int[11]_i_89\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
O => \y_int[11]_i_89_n_0\
);
\y_int[11]_i_9\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \y_int[11]_i_5_n_0\,
I1 => y_int_reg1(8),
I2 => \y_int[11]_i_16_n_0\,
I3 => y_int_reg20_in(8),
O => \y_int[11]_i_9_n_0\
);
\y_int[11]_i_90\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_11_n_5\,
I1 => \y_int_reg[31]_i_11_n_6\,
O => \y_int[11]_i_90_n_0\
);
\y_int[11]_i_91\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_11_n_7\,
I1 => \y_int_reg[31]_i_30_n_4\,
O => \y_int[11]_i_91_n_0\
);
\y_int[11]_i_92\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_30_n_5\,
I1 => \y_int_reg[31]_i_30_n_6\,
O => \y_int[11]_i_92_n_0\
);
\y_int[11]_i_93\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \y_int_reg[31]_i_62_n_4\,
I1 => \y_int_reg[31]_i_30_n_7\,
O => \y_int[11]_i_93_n_0\
);
\y_int[11]_i_94\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \y_int_reg[31]_i_62_n_6\,
I1 => \y_int_reg[31]_i_62_n_5\,
O => \y_int[11]_i_94_n_0\
);
\y_int[11]_i_95\: unisim.vcomponents.LUT3
generic map(
INIT => X"BE"
)
port map (
I0 => \y_int_reg[31]_i_88_n_6\,
I1 => \y_int_reg[31]_i_88_n_5\,
I2 => rgb888(0),
O => \y_int[11]_i_95_n_0\
);
\y_int[11]_i_96\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => rgb888(0),
I1 => rgb888(1),
O => \y_int[11]_i_96_n_0\
);
\y_int[11]_i_97\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_30_n_7\,
I1 => \y_int_reg[31]_i_62_n_4\,
O => \y_int[11]_i_97_n_0\
);
\y_int[11]_i_98\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_62_n_5\,
I1 => \y_int_reg[31]_i_62_n_6\,
O => \y_int[11]_i_98_n_0\
);
\y_int[11]_i_99\: unisim.vcomponents.LUT3
generic map(
INIT => X"09"
)
port map (
I0 => rgb888(0),
I1 => \y_int_reg[31]_i_88_n_5\,
I2 => \y_int_reg[31]_i_88_n_6\,
O => \y_int[11]_i_99_n_0\
);
\y_int[15]_i_10\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \rgb888[8]_28\(1),
I1 => \rgb888[8]_21\(2),
I2 => \rgb888[8]_27\(0),
I3 => \^y_int_reg[3]_1\(0),
O => \y_int[15]_i_10_n_0\
);
\y_int[15]_i_11\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \rgb888[1]\(5),
I1 => \^y_int_reg[23]_0\(0),
I2 => \^y_int_reg[19]_0\(1),
I3 => \^y_int_reg[7]_0\(0),
O => y_int_reg1(14)
);
\y_int[15]_i_12\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \rgb888[8]_28\(0),
I1 => \rgb888[8]_21\(2),
I2 => \rgb888[8]_29\(3),
I3 => \^y_int_reg[3]_1\(0),
O => \y_int[15]_i_12_n_0\
);
\y_int[15]_i_13\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \rgb888[1]\(4),
I1 => \^y_int_reg[23]_0\(0),
I2 => \^y_int_reg[19]_0\(0),
I3 => \^y_int_reg[7]_0\(0),
O => y_int_reg1(13)
);
\y_int[15]_i_16\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \y_int_reg[15]_i_33_n_4\,
I1 => \rgb888[8]_21\(2),
I2 => \rgb888[8]_29\(2),
I3 => \^y_int_reg[3]_1\(0),
O => \y_int[15]_i_16_n_0\
);
\y_int[15]_i_17\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \rgb888[1]\(3),
I1 => \^y_int_reg[23]_0\(0),
I2 => \^y_int_reg[15]_0\(3),
I3 => \^y_int_reg[7]_0\(0),
O => y_int_reg1(12)
);
\y_int[15]_i_18\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \y_int_reg[15]_i_33_n_5\,
I1 => \rgb888[8]_21\(2),
I2 => \rgb888[8]_29\(1),
I3 => \^y_int_reg[3]_1\(0),
O => \y_int[15]_i_18_n_0\
);
\y_int[15]_i_19\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \rgb888[1]\(2),
I1 => \^y_int_reg[23]_0\(0),
I2 => \^y_int_reg[15]_0\(2),
I3 => \^y_int_reg[7]_0\(0),
O => y_int_reg1(11)
);
\y_int[15]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => y_int_reg6,
I1 => y_int_reg5(22),
I2 => \y_int_reg[31]_i_8_n_5\,
I3 => y_int_reg3(14),
I4 => \y_int[15]_i_10_n_0\,
I5 => y_int_reg1(14),
O => \y_int[15]_i_2_n_0\
);
\y_int[15]_i_20\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => y_int_reg3(15),
I1 => \y_int_reg[31]_i_8_n_5\,
I2 => y_int_reg5(23),
I3 => y_int_reg6,
O => y_int_reg20_in(15)
);
\y_int[15]_i_21\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => y_int_reg3(14),
I1 => \y_int_reg[31]_i_8_n_5\,
I2 => y_int_reg5(22),
I3 => y_int_reg6,
O => y_int_reg20_in(14)
);
\y_int[15]_i_22\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => y_int_reg3(13),
I1 => \y_int_reg[31]_i_8_n_5\,
I2 => y_int_reg5(21),
I3 => y_int_reg6,
O => y_int_reg20_in(13)
);
\y_int[15]_i_23\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => y_int_reg3(12),
I1 => \y_int_reg[31]_i_8_n_5\,
I2 => y_int_reg5(20),
I3 => y_int_reg6,
O => y_int_reg20_in(12)
);
\y_int[15]_i_25\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
O => \y_int[15]_i_25_n_0\
);
\y_int[15]_i_26\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
O => \y_int[15]_i_26_n_0\
);
\y_int[15]_i_27\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
O => \y_int[15]_i_27_n_0\
);
\y_int[15]_i_28\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
O => \y_int[15]_i_28_n_0\
);
\y_int[15]_i_29\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
I1 => y_int_reg6,
I2 => y_int_reg5(20),
O => \y_int[15]_i_29_n_0\
);
\y_int[15]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => y_int_reg6,
I1 => y_int_reg5(21),
I2 => \y_int_reg[31]_i_8_n_5\,
I3 => y_int_reg3(13),
I4 => \y_int[15]_i_12_n_0\,
I5 => y_int_reg1(13),
O => \y_int[15]_i_3_n_0\
);
\y_int[15]_i_30\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
I1 => y_int_reg6,
I2 => y_int_reg5(19),
O => \y_int[15]_i_30_n_0\
);
\y_int[15]_i_31\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
I1 => y_int_reg6,
I2 => y_int_reg5(18),
O => \y_int[15]_i_31_n_0\
);
\y_int[15]_i_32\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
I1 => y_int_reg6,
I2 => y_int_reg5(17),
O => \y_int[15]_i_32_n_0\
);
\y_int[15]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => y_int_reg6,
I1 => y_int_reg5(20),
I2 => \y_int_reg[31]_i_8_n_5\,
I3 => y_int_reg3(12),
I4 => \y_int[15]_i_16_n_0\,
I5 => y_int_reg1(12),
O => \y_int[15]_i_4_n_0\
);
\y_int[15]_i_40\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \rgb888[8]_21\(2),
I1 => \^y_int_reg[3]_1\(0),
I2 => \rgb888[8]_29\(2),
O => \y_int[15]_i_40_n_0\
);
\y_int[15]_i_41\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \rgb888[8]_21\(2),
I1 => \^y_int_reg[3]_1\(0),
I2 => \rgb888[8]_29\(1),
O => \y_int[15]_i_41_n_0\
);
\y_int[15]_i_42\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \rgb888[8]_21\(2),
I1 => \^y_int_reg[3]_1\(0),
I2 => \rgb888[8]_29\(0),
O => \y_int[15]_i_42_n_0\
);
\y_int[15]_i_43\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \rgb888[8]_21\(2),
I1 => \^y_int_reg[3]_1\(0),
I2 => \rgb888[8]_22\(3),
O => \y_int[15]_i_43_n_0\
);
\y_int[15]_i_48\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
O => \y_int[15]_i_48_n_0\
);
\y_int[15]_i_49\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
O => \y_int[15]_i_49_n_0\
);
\y_int[15]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => y_int_reg6,
I1 => y_int_reg5(19),
I2 => \y_int_reg[31]_i_8_n_5\,
I3 => y_int_reg3(11),
I4 => \y_int[15]_i_18_n_0\,
I5 => y_int_reg1(11),
O => \y_int[15]_i_5_n_0\
);
\y_int[15]_i_50\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
O => \y_int[15]_i_50_n_0\
);
\y_int[15]_i_51\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
O => \y_int[15]_i_51_n_0\
);
\y_int[15]_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \y_int[15]_i_2_n_0\,
I1 => y_int_reg1(15),
I2 => \y_int[19]_i_18_n_0\,
I3 => y_int_reg20_in(15),
O => \y_int[15]_i_6_n_0\
);
\y_int[15]_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \y_int[15]_i_3_n_0\,
I1 => y_int_reg1(14),
I2 => \y_int[15]_i_10_n_0\,
I3 => y_int_reg20_in(14),
O => \y_int[15]_i_7_n_0\
);
\y_int[15]_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \y_int[15]_i_4_n_0\,
I1 => y_int_reg1(13),
I2 => \y_int[15]_i_12_n_0\,
I3 => y_int_reg20_in(13),
O => \y_int[15]_i_8_n_0\
);
\y_int[15]_i_9\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \y_int[15]_i_5_n_0\,
I1 => y_int_reg1(12),
I2 => \y_int[15]_i_16_n_0\,
I3 => y_int_reg20_in(12),
O => \y_int[15]_i_9_n_0\
);
\y_int[19]_i_10\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \rgb888[8]_26\(1),
I1 => \rgb888[8]_21\(2),
I2 => \rgb888[8]_25\(0),
I3 => \^y_int_reg[3]_1\(0),
O => \y_int[19]_i_10_n_0\
);
\y_int[19]_i_11\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \rgb888[1]\(9),
I1 => \^y_int_reg[23]_0\(0),
I2 => \^y_int_reg[23]_2\(1),
I3 => \^y_int_reg[7]_0\(0),
O => y_int_reg1(18)
);
\y_int[19]_i_12\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \rgb888[8]_26\(0),
I1 => \rgb888[8]_21\(2),
I2 => \rgb888[8]_27\(3),
I3 => \^y_int_reg[3]_1\(0),
O => \y_int[19]_i_12_n_0\
);
\y_int[19]_i_13\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \rgb888[1]\(8),
I1 => \^y_int_reg[23]_0\(0),
I2 => \^y_int_reg[23]_2\(0),
I3 => \^y_int_reg[7]_0\(0),
O => y_int_reg1(17)
);
\y_int[19]_i_16\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \rgb888[8]_28\(3),
I1 => \rgb888[8]_21\(2),
I2 => \rgb888[8]_27\(2),
I3 => \^y_int_reg[3]_1\(0),
O => \y_int[19]_i_16_n_0\
);
\y_int[19]_i_17\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \rgb888[1]\(7),
I1 => \^y_int_reg[23]_0\(0),
I2 => \^y_int_reg[19]_0\(3),
I3 => \^y_int_reg[7]_0\(0),
O => y_int_reg1(16)
);
\y_int[19]_i_18\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \rgb888[8]_28\(2),
I1 => \rgb888[8]_21\(2),
I2 => \rgb888[8]_27\(1),
I3 => \^y_int_reg[3]_1\(0),
O => \y_int[19]_i_18_n_0\
);
\y_int[19]_i_19\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \rgb888[1]\(6),
I1 => \^y_int_reg[23]_0\(0),
I2 => \^y_int_reg[19]_0\(2),
I3 => \^y_int_reg[7]_0\(0),
O => y_int_reg1(15)
);
\y_int[19]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => y_int_reg6,
I1 => y_int_reg5(26),
I2 => \y_int_reg[31]_i_8_n_5\,
I3 => y_int_reg3(18),
I4 => \y_int[19]_i_10_n_0\,
I5 => y_int_reg1(18),
O => \y_int[19]_i_2_n_0\
);
\y_int[19]_i_20\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => y_int_reg3(19),
I1 => \y_int_reg[31]_i_8_n_5\,
I2 => y_int_reg5(27),
I3 => y_int_reg6,
O => y_int_reg20_in(19)
);
\y_int[19]_i_21\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => y_int_reg3(18),
I1 => \y_int_reg[31]_i_8_n_5\,
I2 => y_int_reg5(26),
I3 => y_int_reg6,
O => y_int_reg20_in(18)
);
\y_int[19]_i_22\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => y_int_reg3(17),
I1 => \y_int_reg[31]_i_8_n_5\,
I2 => y_int_reg5(25),
I3 => y_int_reg6,
O => y_int_reg20_in(17)
);
\y_int[19]_i_23\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => y_int_reg3(16),
I1 => \y_int_reg[31]_i_8_n_5\,
I2 => y_int_reg5(24),
I3 => y_int_reg6,
O => y_int_reg20_in(16)
);
\y_int[19]_i_25\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
O => \y_int[19]_i_25_n_0\
);
\y_int[19]_i_26\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
O => \y_int[19]_i_26_n_0\
);
\y_int[19]_i_27\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
O => \y_int[19]_i_27_n_0\
);
\y_int[19]_i_28\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
O => \y_int[19]_i_28_n_0\
);
\y_int[19]_i_29\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
I1 => y_int_reg6,
I2 => y_int_reg5(24),
O => \y_int[19]_i_29_n_0\
);
\y_int[19]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => y_int_reg6,
I1 => y_int_reg5(25),
I2 => \y_int_reg[31]_i_8_n_5\,
I3 => y_int_reg3(17),
I4 => \y_int[19]_i_12_n_0\,
I5 => y_int_reg1(17),
O => \y_int[19]_i_3_n_0\
);
\y_int[19]_i_30\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
I1 => y_int_reg6,
I2 => y_int_reg5(23),
O => \y_int[19]_i_30_n_0\
);
\y_int[19]_i_31\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
I1 => y_int_reg6,
I2 => y_int_reg5(22),
O => \y_int[19]_i_31_n_0\
);
\y_int[19]_i_32\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
I1 => y_int_reg6,
I2 => y_int_reg5(21),
O => \y_int[19]_i_32_n_0\
);
\y_int[19]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => y_int_reg6,
I1 => y_int_reg5(24),
I2 => \y_int_reg[31]_i_8_n_5\,
I3 => y_int_reg3(16),
I4 => \y_int[19]_i_16_n_0\,
I5 => y_int_reg1(16),
O => \y_int[19]_i_4_n_0\
);
\y_int[19]_i_48\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
O => \y_int[19]_i_48_n_0\
);
\y_int[19]_i_49\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
O => \y_int[19]_i_49_n_0\
);
\y_int[19]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => y_int_reg6,
I1 => y_int_reg5(23),
I2 => \y_int_reg[31]_i_8_n_5\,
I3 => y_int_reg3(15),
I4 => \y_int[19]_i_18_n_0\,
I5 => y_int_reg1(15),
O => \y_int[19]_i_5_n_0\
);
\y_int[19]_i_50\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
O => \y_int[19]_i_50_n_0\
);
\y_int[19]_i_51\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
O => \y_int[19]_i_51_n_0\
);
\y_int[19]_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \y_int[19]_i_2_n_0\,
I1 => y_int_reg1(19),
I2 => \y_int[23]_i_20_n_0\,
I3 => y_int_reg20_in(19),
O => \y_int[19]_i_6_n_0\
);
\y_int[19]_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \y_int[19]_i_3_n_0\,
I1 => y_int_reg1(18),
I2 => \y_int[19]_i_10_n_0\,
I3 => y_int_reg20_in(18),
O => \y_int[19]_i_7_n_0\
);
\y_int[19]_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \y_int[19]_i_4_n_0\,
I1 => y_int_reg1(17),
I2 => \y_int[19]_i_12_n_0\,
I3 => y_int_reg20_in(17),
O => \y_int[19]_i_8_n_0\
);
\y_int[19]_i_9\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \y_int[19]_i_5_n_0\,
I1 => y_int_reg1(16),
I2 => \y_int[19]_i_16_n_0\,
I3 => y_int_reg20_in(16),
O => \y_int[19]_i_9_n_0\
);
\y_int[23]_i_100\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \rgb888[8]_19\(0),
I1 => \^y_int_reg[3]_0\(0),
O => \y_int[23]_i_100_n_0\
);
\y_int[23]_i_101\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[14]\(0),
I1 => \^y_int_reg[3]_0\(3),
O => \y_int[23]_i_101_n_0\
);
\y_int[23]_i_102\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[3]_0\(2),
I1 => \^y_int_reg[3]_0\(1),
O => \y_int[23]_i_102_n_0\
);
\y_int[23]_i_103\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[3]_0\(0),
I1 => \rgb888[8]_19\(0),
O => \y_int[23]_i_103_n_0\
);
\y_int[23]_i_104\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(8),
O => \y_int[23]_i_104_n_0\
);
\y_int[23]_i_12\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \rgb888[8]_23\(1),
I1 => \rgb888[8]_21\(2),
I2 => \rgb888[8]_24\(0),
I3 => \^y_int_reg[3]_1\(0),
O => \y_int[23]_i_12_n_0\
);
\y_int[23]_i_13\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \rgb888[1]\(13),
I1 => \^y_int_reg[23]_0\(0),
I2 => \^y_int_reg[23]_1\(1),
I3 => \^y_int_reg[7]_0\(0),
O => y_int_reg1(22)
);
\y_int[23]_i_14\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \rgb888[8]_23\(0),
I1 => \rgb888[8]_21\(2),
I2 => \rgb888[8]_25\(3),
I3 => \^y_int_reg[3]_1\(0),
O => \y_int[23]_i_14_n_0\
);
\y_int[23]_i_15\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \rgb888[1]\(12),
I1 => \^y_int_reg[23]_0\(0),
I2 => \^y_int_reg[23]_1\(0),
I3 => \^y_int_reg[7]_0\(0),
O => y_int_reg1(21)
);
\y_int[23]_i_18\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \rgb888[8]_26\(3),
I1 => \rgb888[8]_21\(2),
I2 => \rgb888[8]_25\(2),
I3 => \^y_int_reg[3]_1\(0),
O => \y_int[23]_i_18_n_0\
);
\y_int[23]_i_19\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \rgb888[1]\(11),
I1 => \^y_int_reg[23]_0\(0),
I2 => \^y_int_reg[23]_2\(3),
I3 => \^y_int_reg[7]_0\(0),
O => y_int_reg1(20)
);
\y_int[23]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => y_int_reg6,
I1 => y_int_reg5(30),
I2 => \y_int_reg[31]_i_8_n_5\,
I3 => y_int_reg3(22),
I4 => \y_int[23]_i_12_n_0\,
I5 => y_int_reg1(22),
O => \y_int[23]_i_2_n_0\
);
\y_int[23]_i_20\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \rgb888[8]_26\(2),
I1 => \rgb888[8]_21\(2),
I2 => \rgb888[8]_25\(1),
I3 => \^y_int_reg[3]_1\(0),
O => \y_int[23]_i_20_n_0\
);
\y_int[23]_i_21\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \rgb888[1]\(10),
I1 => \^y_int_reg[23]_0\(0),
I2 => \^y_int_reg[23]_2\(2),
I3 => \^y_int_reg[7]_0\(0),
O => y_int_reg1(19)
);
\y_int[23]_i_22\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => y_int_reg3(22),
I1 => \y_int_reg[31]_i_8_n_5\,
I2 => y_int_reg5(30),
I3 => y_int_reg6,
O => y_int_reg20_in(22)
);
\y_int[23]_i_23\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => y_int_reg3(21),
I1 => \y_int_reg[31]_i_8_n_5\,
I2 => y_int_reg5(29),
I3 => y_int_reg6,
O => y_int_reg20_in(21)
);
\y_int[23]_i_24\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => y_int_reg3(20),
I1 => \y_int_reg[31]_i_8_n_5\,
I2 => y_int_reg5(28),
I3 => y_int_reg6,
O => y_int_reg20_in(20)
);
\y_int[23]_i_26\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
O => \y_int[23]_i_26_n_0\
);
\y_int[23]_i_27\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
O => \y_int[23]_i_27_n_0\
);
\y_int[23]_i_28\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
O => \y_int[23]_i_28_n_0\
);
\y_int[23]_i_29\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
O => \y_int[23]_i_29_n_0\
);
\y_int[23]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => y_int_reg6,
I1 => y_int_reg5(29),
I2 => \y_int_reg[31]_i_8_n_5\,
I3 => y_int_reg3(21),
I4 => \y_int[23]_i_14_n_0\,
I5 => y_int_reg1(21),
O => \y_int[23]_i_3_n_0\
);
\y_int[23]_i_30\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
O => \y_int[23]_i_30_n_0\
);
\y_int[23]_i_31\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
O => \y_int[23]_i_31_n_0\
);
\y_int[23]_i_36\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
O => \y_int[23]_i_36_n_0\
);
\y_int[23]_i_37\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
O => \y_int[23]_i_37_n_0\
);
\y_int[23]_i_38\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
O => \y_int[23]_i_38_n_0\
);
\y_int[23]_i_39\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
O => \y_int[23]_i_39_n_0\
);
\y_int[23]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => y_int_reg6,
I1 => y_int_reg5(28),
I2 => \y_int_reg[31]_i_8_n_5\,
I3 => y_int_reg3(20),
I4 => \y_int[23]_i_18_n_0\,
I5 => y_int_reg1(20),
O => \y_int[23]_i_4_n_0\
);
\y_int[23]_i_40\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
I1 => y_int_reg6,
I2 => y_int_reg5(28),
O => \y_int[23]_i_40_n_0\
);
\y_int[23]_i_41\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
I1 => y_int_reg6,
I2 => y_int_reg5(27),
O => \y_int[23]_i_41_n_0\
);
\y_int[23]_i_42\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
I1 => y_int_reg6,
I2 => y_int_reg5(26),
O => \y_int[23]_i_42_n_0\
);
\y_int[23]_i_43\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
I1 => y_int_reg6,
I2 => y_int_reg5(25),
O => \y_int[23]_i_43_n_0\
);
\y_int[23]_i_46\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
O => \y_int[23]_i_46_n_0\
);
\y_int[23]_i_47\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
O => \y_int[23]_i_47_n_0\
);
\y_int[23]_i_48\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
O => \y_int[23]_i_48_n_0\
);
\y_int[23]_i_49\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
O => \y_int[23]_i_49_n_0\
);
\y_int[23]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => y_int_reg6,
I1 => y_int_reg5(27),
I2 => \y_int_reg[31]_i_8_n_5\,
I3 => y_int_reg3(19),
I4 => \y_int[23]_i_20_n_0\,
I5 => y_int_reg1(19),
O => \y_int[23]_i_5_n_0\
);
\y_int[23]_i_52\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[8]_21\(2),
O => \y_int[23]_i_52_n_0\
);
\y_int[23]_i_53\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[8]_21\(2),
O => \y_int[23]_i_53_n_0\
);
\y_int[23]_i_54\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[8]_21\(2),
O => \y_int[23]_i_54_n_0\
);
\y_int[23]_i_55\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[8]_21\(2),
O => \y_int[23]_i_55_n_0\
);
\y_int[23]_i_56\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
O => \y_int[23]_i_56_n_0\
);
\y_int[23]_i_57\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
O => \y_int[23]_i_57_n_0\
);
\y_int[23]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"659A659A9A65659A"
)
port map (
I0 => \y_int[23]_i_2_n_0\,
I1 => \rgb888[1]_0\(0),
I2 => \^y_int_reg[23]_0\(0),
I3 => \y_int[31]_i_13_n_0\,
I4 => \y_int_reg[31]_i_8_n_5\,
I5 => \y_int_reg[31]_i_7_n_1\,
O => \y_int[23]_i_6_n_0\
);
\y_int[23]_i_62\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
O => \y_int[23]_i_62_n_0\
);
\y_int[23]_i_63\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
O => \y_int[23]_i_63_n_0\
);
\y_int[23]_i_64\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
O => \y_int[23]_i_64_n_0\
);
\y_int[23]_i_65\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
O => \y_int[23]_i_65_n_0\
);
\y_int[23]_i_67\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \y_int_reg[31]_i_8_n_7\,
I1 => \y_int_reg[31]_i_8_n_6\,
O => \y_int[23]_i_67_n_0\
);
\y_int[23]_i_68\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \y_int_reg[31]_i_16_n_5\,
I1 => \y_int_reg[31]_i_16_n_4\,
O => \y_int[23]_i_68_n_0\
);
\y_int[23]_i_69\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \y_int_reg[31]_i_16_n_7\,
I1 => \y_int_reg[31]_i_16_n_6\,
O => \y_int[23]_i_69_n_0\
);
\y_int[23]_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \y_int[23]_i_3_n_0\,
I1 => y_int_reg1(22),
I2 => \y_int[23]_i_12_n_0\,
I3 => y_int_reg20_in(22),
O => \y_int[23]_i_7_n_0\
);
\y_int[23]_i_70\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \y_int_reg[3]_i_16_n_5\,
I1 => \y_int_reg[3]_i_16_n_4\,
O => \y_int[23]_i_70_n_0\
);
\y_int[23]_i_71\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_8_n_6\,
I1 => \y_int_reg[31]_i_8_n_7\,
O => \y_int[23]_i_71_n_0\
);
\y_int[23]_i_72\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_16_n_4\,
I1 => \y_int_reg[31]_i_16_n_5\,
O => \y_int[23]_i_72_n_0\
);
\y_int[23]_i_73\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_16_n_6\,
I1 => \y_int_reg[31]_i_16_n_7\,
O => \y_int[23]_i_73_n_0\
);
\y_int[23]_i_74\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[3]_i_16_n_4\,
I1 => \y_int_reg[3]_i_16_n_5\,
O => \y_int[23]_i_74_n_0\
);
\y_int[23]_i_76\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \rgb888[8]_21\(1),
I1 => \rgb888[8]_21\(2),
O => \y_int[23]_i_76_n_0\
);
\y_int[23]_i_77\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[8]_21\(2),
O => \y_int[23]_i_77_n_0\
);
\y_int[23]_i_78\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[8]_21\(2),
O => \y_int[23]_i_78_n_0\
);
\y_int[23]_i_79\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[8]_21\(2),
O => \y_int[23]_i_79_n_0\
);
\y_int[23]_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \y_int[23]_i_4_n_0\,
I1 => y_int_reg1(21),
I2 => \y_int[23]_i_14_n_0\,
I3 => y_int_reg20_in(21),
O => \y_int[23]_i_8_n_0\
);
\y_int[23]_i_80\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[8]_21\(2),
I1 => \rgb888[8]_21\(1),
O => \y_int[23]_i_80_n_0\
);
\y_int[23]_i_81\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \y_int_reg[3]_i_16_n_7\,
I1 => \y_int_reg[3]_i_16_n_6\,
O => \y_int[23]_i_81_n_0\
);
\y_int[23]_i_82\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \y_int_reg[3]_i_26_n_5\,
I1 => \y_int_reg[3]_i_26_n_4\,
O => \y_int[23]_i_82_n_0\
);
\y_int[23]_i_83\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \y_int_reg[3]_i_26_n_7\,
I1 => \y_int_reg[3]_i_26_n_6\,
O => \y_int[23]_i_83_n_0\
);
\y_int[23]_i_84\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => rgb888(16),
I1 => rgb888(17),
O => \y_int[23]_i_84_n_0\
);
\y_int[23]_i_85\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[3]_i_16_n_6\,
I1 => \y_int_reg[3]_i_16_n_7\,
O => \y_int[23]_i_85_n_0\
);
\y_int[23]_i_86\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[3]_i_26_n_4\,
I1 => \y_int_reg[3]_i_26_n_5\,
O => \y_int[23]_i_86_n_0\
);
\y_int[23]_i_87\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[3]_i_26_n_6\,
I1 => \y_int_reg[3]_i_26_n_7\,
O => \y_int[23]_i_87_n_0\
);
\y_int[23]_i_88\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(17),
I1 => rgb888(16),
O => \y_int[23]_i_88_n_0\
);
\y_int[23]_i_9\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \y_int[23]_i_5_n_0\,
I1 => y_int_reg1(20),
I2 => \y_int[23]_i_18_n_0\,
I3 => y_int_reg20_in(20),
O => \y_int[23]_i_9_n_0\
);
\y_int[23]_i_90\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \rgb888[8]_20\(3),
I1 => \rgb888[8]_21\(0),
O => \y_int[23]_i_90_n_0\
);
\y_int[23]_i_91\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \rgb888[8]_20\(1),
I1 => \rgb888[8]_20\(2),
O => \y_int[23]_i_91_n_0\
);
\y_int[23]_i_92\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \rgb888[14]\(3),
I1 => \rgb888[8]_20\(0),
O => \y_int[23]_i_92_n_0\
);
\y_int[23]_i_93\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \rgb888[14]\(1),
I1 => \rgb888[14]\(2),
O => \y_int[23]_i_93_n_0\
);
\y_int[23]_i_94\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[8]_21\(0),
I1 => \rgb888[8]_20\(3),
O => \y_int[23]_i_94_n_0\
);
\y_int[23]_i_95\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[8]_20\(2),
I1 => \rgb888[8]_20\(1),
O => \y_int[23]_i_95_n_0\
);
\y_int[23]_i_96\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[8]_20\(0),
I1 => \rgb888[14]\(3),
O => \y_int[23]_i_96_n_0\
);
\y_int[23]_i_97\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[14]\(2),
I1 => \rgb888[14]\(1),
O => \y_int[23]_i_97_n_0\
);
\y_int[23]_i_98\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \^y_int_reg[3]_0\(3),
I1 => \rgb888[14]\(0),
O => \y_int[23]_i_98_n_0\
);
\y_int[23]_i_99\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \^y_int_reg[3]_0\(1),
I1 => \^y_int_reg[3]_0\(2),
O => \y_int[23]_i_99_n_0\
);
\y_int[27]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"659A659A9A65659A"
)
port map (
I0 => \y_int[31]_i_2_n_0\,
I1 => \rgb888[1]_0\(0),
I2 => \^y_int_reg[23]_0\(0),
I3 => \y_int[31]_i_13_n_0\,
I4 => \y_int_reg[31]_i_8_n_5\,
I5 => \y_int_reg[31]_i_7_n_1\,
O => \y_int[27]_i_2_n_0\
);
\y_int[27]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"659A659A9A65659A"
)
port map (
I0 => \y_int[31]_i_2_n_0\,
I1 => \rgb888[1]_0\(0),
I2 => \^y_int_reg[23]_0\(0),
I3 => \y_int[31]_i_13_n_0\,
I4 => \y_int_reg[31]_i_8_n_5\,
I5 => \y_int_reg[31]_i_7_n_1\,
O => \y_int[27]_i_3_n_0\
);
\y_int[27]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"659A659A9A65659A"
)
port map (
I0 => \y_int[31]_i_2_n_0\,
I1 => \rgb888[1]_0\(0),
I2 => \^y_int_reg[23]_0\(0),
I3 => \y_int[31]_i_13_n_0\,
I4 => \y_int_reg[31]_i_8_n_5\,
I5 => \y_int_reg[31]_i_7_n_1\,
O => \y_int[27]_i_4_n_0\
);
\y_int[27]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"659A659A9A65659A"
)
port map (
I0 => \y_int[31]_i_2_n_0\,
I1 => \rgb888[1]_0\(0),
I2 => \^y_int_reg[23]_0\(0),
I3 => \y_int[31]_i_13_n_0\,
I4 => \y_int_reg[31]_i_8_n_5\,
I5 => \y_int_reg[31]_i_7_n_1\,
O => \y_int[27]_i_5_n_0\
);
\y_int[31]_i_101\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(7),
O => \y_int[31]_i_101_n_0\
);
\y_int[31]_i_104\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(1),
I1 => rgb888(3),
O => \y_int[31]_i_104_n_0\
);
\y_int[31]_i_105\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => rgb888(3),
I1 => rgb888(1),
I2 => rgb888(2),
O => \y_int[31]_i_105_n_0\
);
\y_int[31]_i_106\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(2),
I1 => rgb888(0),
O => \y_int[31]_i_106_n_0\
);
\y_int[31]_i_107\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(1),
O => \y_int[31]_i_107_n_0\
);
\y_int[31]_i_108\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => rgb888(0),
O => \y_int[31]_i_108_n_0\
);
\y_int[31]_i_109\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(6),
O => \y_int[31]_i_109_n_0\
);
\y_int[31]_i_110\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(7),
I1 => rgb888(5),
O => \y_int[31]_i_110_n_0\
);
\y_int[31]_i_111\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(6),
I1 => rgb888(4),
O => \y_int[31]_i_111_n_0\
);
\y_int[31]_i_112\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(5),
I1 => rgb888(3),
O => \y_int[31]_i_112_n_0\
);
\y_int[31]_i_113\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(4),
I1 => rgb888(2),
O => \y_int[31]_i_113_n_0\
);
\y_int[31]_i_114\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(3),
I1 => rgb888(1),
O => \y_int[31]_i_114_n_0\
);
\y_int[31]_i_115\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(2),
I1 => rgb888(0),
O => \y_int[31]_i_115_n_0\
);
\y_int[31]_i_116\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => rgb888(1),
O => \y_int[31]_i_116_n_0\
);
\y_int[31]_i_13\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \rgb888[8]_21\(2),
I1 => \rgb888[8]_30\(0),
O => \y_int[31]_i_13_n_0\
);
\y_int[31]_i_14\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
I1 => y_int_reg6,
I2 => y_int_reg5(30),
O => \y_int[31]_i_14_n_0\
);
\y_int[31]_i_15\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
I1 => y_int_reg6,
I2 => y_int_reg5(29),
O => \y_int[31]_i_15_n_0\
);
\y_int[31]_i_17\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFF80000000"
)
port map (
I0 => rgb888(20),
I1 => rgb888(18),
I2 => rgb888(19),
I3 => rgb888(21),
I4 => rgb888(22),
I5 => rgb888(23),
O => \y_int[31]_i_17_n_0\
);
\y_int[31]_i_18\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFFFFFFFFFF"
)
port map (
I0 => rgb888(23),
I1 => rgb888(20),
I2 => rgb888(18),
I3 => rgb888(19),
I4 => rgb888(21),
I5 => rgb888(22),
O => \y_int[31]_i_18_n_0\
);
\y_int[31]_i_19\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFFFFFFFFFF"
)
port map (
I0 => rgb888(23),
I1 => rgb888(20),
I2 => rgb888(18),
I3 => rgb888(19),
I4 => rgb888(21),
I5 => rgb888(22),
O => \y_int[31]_i_19_n_0\
);
\y_int[31]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0040004044F40040"
)
port map (
I0 => \y_int_reg[31]_i_7_n_1\,
I1 => \y_int_reg[31]_i_8_n_5\,
I2 => \rgb888[8]_21\(2),
I3 => \rgb888[8]_30\(0),
I4 => \^y_int_reg[23]_0\(0),
I5 => \rgb888[1]_0\(0),
O => \y_int[31]_i_2_n_0\
);
\y_int[31]_i_20\: unisim.vcomponents.LUT6
generic map(
INIT => X"000000007FFFFFFF"
)
port map (
I0 => rgb888(22),
I1 => rgb888(21),
I2 => rgb888(19),
I3 => rgb888(18),
I4 => rgb888(20),
I5 => rgb888(23),
O => \y_int[31]_i_20_n_0\
);
\y_int[31]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"659A659A9A65659A"
)
port map (
I0 => \y_int[31]_i_2_n_0\,
I1 => \rgb888[1]_0\(0),
I2 => \^y_int_reg[23]_0\(0),
I3 => \y_int[31]_i_13_n_0\,
I4 => \y_int_reg[31]_i_8_n_5\,
I5 => \y_int_reg[31]_i_7_n_1\,
O => \y_int[31]_i_3_n_0\
);
\y_int[31]_i_32\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \rgb888[0]_7\(3),
I1 => \y_int_reg[31]_i_75_n_2\,
O => \y_int[31]_i_32_n_0\
);
\y_int[31]_i_33\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \rgb888[0]_9\(2),
O => \y_int[31]_i_33_n_0\
);
\y_int[31]_i_34\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \rgb888[0]_9\(2),
O => \y_int[31]_i_34_n_0\
);
\y_int[31]_i_35\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \y_int_reg[31]_i_75_n_2\,
I1 => \rgb888[0]_9\(0),
I2 => \rgb888[0]_9\(1),
O => \y_int[31]_i_35_n_0\
);
\y_int[31]_i_36\: unisim.vcomponents.LUT3
generic map(
INIT => X"36"
)
port map (
I0 => \rgb888[0]_7\(3),
I1 => \rgb888[0]_9\(0),
I2 => \y_int_reg[31]_i_75_n_2\,
O => \y_int[31]_i_36_n_0\
);
\y_int[31]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"659A659A9A65659A"
)
port map (
I0 => \y_int[31]_i_2_n_0\,
I1 => \rgb888[1]_0\(0),
I2 => \^y_int_reg[23]_0\(0),
I3 => \y_int[31]_i_13_n_0\,
I4 => \y_int_reg[31]_i_8_n_5\,
I5 => \y_int_reg[31]_i_7_n_1\,
O => \y_int[31]_i_4_n_0\
);
\y_int[31]_i_40\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => rgb888(20),
I1 => rgb888(18),
I2 => rgb888(19),
I3 => rgb888(21),
I4 => rgb888(22),
O => \y_int[31]_i_40_n_0\
);
\y_int[31]_i_41\: unisim.vcomponents.LUT5
generic map(
INIT => X"BEEEEEEE"
)
port map (
I0 => \y_int_reg[3]_i_64_n_2\,
I1 => rgb888(21),
I2 => rgb888(20),
I3 => rgb888(18),
I4 => rgb888(19),
O => \y_int[31]_i_41_n_0\
);
\y_int[31]_i_42\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FD51540"
)
port map (
I0 => \y_int_reg[3]_i_64_n_2\,
I1 => rgb888(18),
I2 => rgb888(19),
I3 => rgb888(20),
I4 => rgb888(23),
O => \y_int[31]_i_42_n_0\
);
\y_int[31]_i_43\: unisim.vcomponents.LUT4
generic map(
INIT => X"BE28"
)
port map (
I0 => \y_int_reg[3]_i_64_n_7\,
I1 => rgb888(18),
I2 => rgb888(19),
I3 => rgb888(22),
O => \y_int[31]_i_43_n_0\
);
\y_int[31]_i_44\: unisim.vcomponents.LUT6
generic map(
INIT => X"A999999999999999"
)
port map (
I0 => rgb888(23),
I1 => rgb888(22),
I2 => rgb888(21),
I3 => rgb888(19),
I4 => rgb888(18),
I5 => rgb888(20),
O => \y_int[31]_i_44_n_0\
);
\y_int[31]_i_45\: unisim.vcomponents.LUT6
generic map(
INIT => X"6CC9C9C9C9C9C9C9"
)
port map (
I0 => \y_int_reg[3]_i_64_n_2\,
I1 => rgb888(22),
I2 => rgb888(21),
I3 => rgb888(19),
I4 => rgb888(18),
I5 => rgb888(20),
O => \y_int[31]_i_45_n_0\
);
\y_int[31]_i_46\: unisim.vcomponents.LUT6
generic map(
INIT => X"157FEA807FEA8015"
)
port map (
I0 => rgb888(23),
I1 => rgb888(19),
I2 => rgb888(18),
I3 => rgb888(20),
I4 => rgb888(21),
I5 => \y_int_reg[3]_i_64_n_2\,
O => \y_int[31]_i_46_n_0\
);
\y_int[31]_i_47\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996966996699669"
)
port map (
I0 => \y_int[31]_i_43_n_0\,
I1 => \y_int_reg[3]_i_64_n_2\,
I2 => rgb888(23),
I3 => rgb888(20),
I4 => rgb888(19),
I5 => rgb888(18),
O => \y_int[31]_i_47_n_0\
);
\y_int[31]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"659A659A9A65659A"
)
port map (
I0 => \y_int[31]_i_2_n_0\,
I1 => \rgb888[1]_0\(0),
I2 => \^y_int_reg[23]_0\(0),
I3 => \y_int[31]_i_13_n_0\,
I4 => \y_int_reg[31]_i_8_n_5\,
I5 => \y_int_reg[31]_i_7_n_1\,
O => \y_int[31]_i_5_n_0\
);
\y_int[31]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"659A659A9A65659A"
)
port map (
I0 => \y_int[31]_i_2_n_0\,
I1 => \rgb888[1]_0\(0),
I2 => \^y_int_reg[23]_0\(0),
I3 => \y_int[31]_i_13_n_0\,
I4 => \y_int_reg[31]_i_8_n_5\,
I5 => \y_int_reg[31]_i_7_n_1\,
O => \y_int[31]_i_6_n_0\
);
\y_int[31]_i_63\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \rgb888[0]_7\(2),
I1 => \y_int_reg[31]_i_75_n_7\,
O => \y_int[31]_i_63_n_0\
);
\y_int[31]_i_64\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \y_int_reg[31]_i_87_n_4\,
I1 => \rgb888[0]_7\(1),
O => \y_int[31]_i_64_n_0\
);
\y_int[31]_i_65\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \y_int_reg[31]_i_87_n_4\,
I1 => \rgb888[0]_7\(1),
O => \y_int[31]_i_65_n_0\
);
\y_int[31]_i_66\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \y_int_reg[31]_i_86_n_4\,
I1 => \y_int_reg[31]_i_87_n_6\,
O => \y_int[31]_i_66_n_0\
);
\y_int[31]_i_67\: unisim.vcomponents.LUT4
generic map(
INIT => X"7887"
)
port map (
I0 => \y_int_reg[31]_i_75_n_7\,
I1 => \rgb888[0]_7\(2),
I2 => \y_int_reg[31]_i_75_n_2\,
I3 => \rgb888[0]_7\(3),
O => \y_int[31]_i_67_n_0\
);
\y_int[31]_i_68\: unisim.vcomponents.LUT4
generic map(
INIT => X"E11E"
)
port map (
I0 => \rgb888[0]_7\(1),
I1 => \y_int_reg[31]_i_87_n_4\,
I2 => \rgb888[0]_7\(2),
I3 => \y_int_reg[31]_i_75_n_7\,
O => \y_int[31]_i_68_n_0\
);
\y_int[31]_i_69\: unisim.vcomponents.LUT4
generic map(
INIT => X"6999"
)
port map (
I0 => \rgb888[0]_7\(1),
I1 => \y_int_reg[31]_i_87_n_4\,
I2 => \y_int_reg[31]_i_87_n_5\,
I3 => \rgb888[0]_7\(0),
O => \y_int[31]_i_69_n_0\
);
\y_int[31]_i_70\: unisim.vcomponents.LUT4
generic map(
INIT => X"8778"
)
port map (
I0 => \y_int_reg[31]_i_87_n_6\,
I1 => \y_int_reg[31]_i_86_n_4\,
I2 => \rgb888[0]_7\(0),
I3 => \y_int_reg[31]_i_87_n_5\,
O => \y_int[31]_i_70_n_0\
);
\y_int[31]_i_89\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \y_int_reg[31]_i_86_n_5\,
I1 => \y_int_reg[31]_i_86_n_4\,
I2 => \y_int_reg[31]_i_87_n_6\,
O => \y_int[31]_i_89_n_0\
);
\y_int[31]_i_90\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \y_int_reg[31]_i_86_n_5\,
I1 => \y_int_reg[31]_i_87_n_7\,
O => \y_int[31]_i_90_n_0\
);
\y_int[31]_i_91\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \y_int_reg[31]_i_88_n_4\,
I1 => \y_int_reg[31]_i_86_n_6\,
O => \y_int[31]_i_91_n_0\
);
\y_int[31]_i_92\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \y_int_reg[31]_i_88_n_5\,
I1 => rgb888(0),
O => \y_int[31]_i_92_n_0\
);
\y_int[3]_i_10\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \y_int_reg[7]_i_24_n_6\,
I1 => \rgb888[8]_21\(2),
I2 => \rgb888[14]\(3),
I3 => \^y_int_reg[3]_1\(0),
I4 => \rgb888[14]_1\(0),
O => \y_int[3]_i_10_n_0\
);
\y_int[3]_i_11\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => y_int_reg2(2),
I1 => \^y_int_reg[23]_0\(0),
I2 => \y_int_reg[31]_i_30_n_4\,
I3 => \^y_int_reg[7]_0\(0),
I4 => \y_int_reg[11]_i_44_n_6\,
O => y_int_reg1(2)
);
\y_int[3]_i_12\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => y_int_reg3(1),
I1 => \y_int_reg[31]_i_8_n_5\,
I2 => \y_int_reg[3]_i_16_n_4\,
I3 => y_int_reg6,
I4 => y_int_reg5(9),
O => y_int_reg20_in(1)
);
\y_int[3]_i_13\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \y_int_reg[7]_i_24_n_7\,
I1 => \rgb888[8]_21\(2),
I2 => \rgb888[14]\(2),
I3 => \^y_int_reg[3]_1\(0),
I4 => \rgb888[14]_0\(1),
O => \y_int[3]_i_13_n_0\
);
\y_int[3]_i_14\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => y_int_reg2(1),
I1 => \^y_int_reg[23]_0\(0),
I2 => \y_int_reg[31]_i_30_n_5\,
I3 => \^y_int_reg[7]_0\(0),
I4 => \y_int_reg[11]_i_44_n_7\,
O => y_int_reg1(1)
);
\y_int[3]_i_17\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \rgb888[14]\(1),
I1 => \^y_int_reg[3]_1\(0),
I2 => \rgb888[14]_0\(0),
O => \y_int[3]_i_17_n_0\
);
\y_int[3]_i_18\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \y_int_reg[31]_i_30_n_6\,
I1 => \^y_int_reg[7]_0\(0),
I2 => \y_int_reg[3]_i_35_n_4\,
O => \y_int[3]_i_18_n_0\
);
\y_int[3]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => y_int_reg20_in(2),
I1 => \y_int[3]_i_10_n_0\,
I2 => y_int_reg1(2),
O => \y_int[3]_i_2_n_0\
);
\y_int[3]_i_22\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[3]_i_16_n_5\,
O => \y_int[3]_i_22_n_0\
);
\y_int[3]_i_23\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[3]_i_16_n_6\,
O => \y_int[3]_i_23_n_0\
);
\y_int[3]_i_24\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[3]_i_16_n_7\,
O => \y_int[3]_i_24_n_0\
);
\y_int[3]_i_25\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[3]_i_26_n_4\,
O => \y_int[3]_i_25_n_0\
);
\y_int[3]_i_27\: unisim.vcomponents.LUT3
generic map(
INIT => X"D4"
)
port map (
I0 => rgb888(18),
I1 => \y_int_reg[3]_i_30_n_4\,
I2 => rgb888(21),
O => \y_int[3]_i_27_n_0\
);
\y_int[3]_i_28\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \y_int_reg[3]_i_30_n_5\,
I1 => rgb888(17),
I2 => rgb888(20),
O => \y_int[3]_i_28_n_0\
);
\y_int[3]_i_29\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \y_int_reg[3]_i_30_n_5\,
I1 => rgb888(17),
I2 => rgb888(20),
O => \y_int[3]_i_29_n_0\
);
\y_int[3]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => y_int_reg20_in(1),
I1 => \y_int[3]_i_13_n_0\,
I2 => y_int_reg1(1),
O => \y_int[3]_i_3_n_0\
);
\y_int[3]_i_31\: unisim.vcomponents.LUT5
generic map(
INIT => X"96696996"
)
port map (
I0 => \y_int[3]_i_27_n_0\,
I1 => rgb888(22),
I2 => rgb888(19),
I3 => rgb888(18),
I4 => \y_int_reg[3]_i_64_n_7\,
O => \y_int[3]_i_31_n_0\
);
\y_int[3]_i_32\: unisim.vcomponents.LUT6
generic map(
INIT => X"E81717E817E8E817"
)
port map (
I0 => rgb888(20),
I1 => rgb888(17),
I2 => \y_int_reg[3]_i_30_n_5\,
I3 => rgb888(21),
I4 => rgb888(18),
I5 => \y_int_reg[3]_i_30_n_4\,
O => \y_int[3]_i_32_n_0\
);
\y_int[3]_i_33\: unisim.vcomponents.LUT5
generic map(
INIT => X"69969696"
)
port map (
I0 => rgb888(20),
I1 => rgb888(17),
I2 => \y_int_reg[3]_i_30_n_5\,
I3 => rgb888(19),
I4 => rgb888(16),
O => \y_int[3]_i_33_n_0\
);
\y_int[3]_i_34\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => rgb888(16),
I1 => rgb888(19),
I2 => \y_int_reg[3]_i_30_n_6\,
O => \y_int[3]_i_34_n_0\
);
\y_int[3]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFE2E200"
)
port map (
I0 => y_int_reg5(8),
I1 => y_int_reg6,
I2 => \y_int_reg[3]_i_16_n_5\,
I3 => \y_int[3]_i_17_n_0\,
I4 => \y_int[3]_i_18_n_0\,
O => \y_int[3]_i_4_n_0\
);
\y_int[3]_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => y_int_reg20_in(3),
I1 => \y_int[7]_i_19_n_0\,
I2 => y_int_reg1(3),
I3 => \y_int[3]_i_2_n_0\,
O => \y_int[3]_i_5_n_0\
);
\y_int[3]_i_50\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(16),
O => \y_int[3]_i_50_n_0\
);
\y_int[3]_i_51\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[3]_i_26_n_5\,
O => \y_int[3]_i_51_n_0\
);
\y_int[3]_i_52\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[3]_i_26_n_6\,
O => \y_int[3]_i_52_n_0\
);
\y_int[3]_i_53\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[3]_i_26_n_7\,
O => \y_int[3]_i_53_n_0\
);
\y_int[3]_i_54\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(17),
O => \y_int[3]_i_54_n_0\
);
\y_int[3]_i_56\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \y_int_reg[3]_i_30_n_7\,
I1 => rgb888(18),
O => \y_int[3]_i_56_n_0\
);
\y_int[3]_i_57\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \y_int_reg[3]_i_55_n_4\,
I1 => rgb888(17),
O => \y_int[3]_i_57_n_0\
);
\y_int[3]_i_58\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \y_int_reg[3]_i_55_n_5\,
I1 => rgb888(16),
O => \y_int[3]_i_58_n_0\
);
\y_int[3]_i_59\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \y_int_reg[3]_i_55_n_6\,
O => \y_int[3]_i_59_n_0\
);
\y_int[3]_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => y_int_reg20_in(2),
I1 => \y_int[3]_i_10_n_0\,
I2 => y_int_reg1(2),
I3 => \y_int[3]_i_3_n_0\,
O => \y_int[3]_i_6_n_0\
);
\y_int[3]_i_60\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(22),
O => \y_int[3]_i_60_n_0\
);
\y_int[3]_i_61\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(23),
I1 => rgb888(21),
O => \y_int[3]_i_61_n_0\
);
\y_int[3]_i_62\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(22),
I1 => rgb888(20),
O => \y_int[3]_i_62_n_0\
);
\y_int[3]_i_63\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(21),
I1 => rgb888(19),
O => \y_int[3]_i_63_n_0\
);
\y_int[3]_i_66\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_30_n_6\,
O => \y_int[3]_i_66_n_0\
);
\y_int[3]_i_67\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_30_n_7\,
O => \y_int[3]_i_67_n_0\
);
\y_int[3]_i_68\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_62_n_4\,
O => \y_int[3]_i_68_n_0\
);
\y_int[3]_i_69\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_62_n_5\,
O => \y_int[3]_i_69_n_0\
);
\y_int[3]_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => y_int_reg20_in(1),
I1 => \y_int[3]_i_13_n_0\,
I2 => y_int_reg1(1),
I3 => \y_int[3]_i_4_n_0\,
O => \y_int[3]_i_7_n_0\
);
\y_int[3]_i_71\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \rgb888[8]_32\(1),
I1 => rgb888(10),
O => \y_int[3]_i_71_n_0\
);
\y_int[3]_i_72\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \rgb888[8]_32\(0),
I1 => rgb888(9),
O => \y_int[3]_i_72_n_0\
);
\y_int[3]_i_73\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \rgb888[8]_19\(2),
I1 => rgb888(8),
O => \y_int[3]_i_73_n_0\
);
\y_int[3]_i_74\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \rgb888[8]_19\(1),
O => \y_int[3]_i_74_n_0\
);
\y_int[3]_i_8\: unisim.vcomponents.LUT5
generic map(
INIT => X"E21D1DE2"
)
port map (
I0 => y_int_reg5(8),
I1 => y_int_reg6,
I2 => \y_int_reg[3]_i_16_n_5\,
I3 => \y_int[3]_i_17_n_0\,
I4 => \y_int[3]_i_18_n_0\,
O => \y_int[3]_i_8_n_0\
);
\y_int[3]_i_84\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(20),
I1 => rgb888(18),
O => \y_int[3]_i_84_n_0\
);
\y_int[3]_i_85\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(19),
I1 => rgb888(17),
O => \y_int[3]_i_85_n_0\
);
\y_int[3]_i_86\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(18),
I1 => rgb888(16),
O => \y_int[3]_i_86_n_0\
);
\y_int[3]_i_87\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => rgb888(17),
O => \y_int[3]_i_87_n_0\
);
\y_int[3]_i_88\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(23),
O => \y_int[3]_i_88_n_0\
);
\y_int[3]_i_89\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_62_n_6\,
O => \y_int[3]_i_89_n_0\
);
\y_int[3]_i_9\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => y_int_reg3(2),
I1 => \y_int_reg[31]_i_8_n_5\,
I2 => \y_int_reg[31]_i_16_n_7\,
I3 => y_int_reg6,
I4 => y_int_reg5(10),
O => y_int_reg20_in(2)
);
\y_int[3]_i_90\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(0),
I1 => \y_int_reg[31]_i_88_n_5\,
O => \y_int[3]_i_90_n_0\
);
\y_int[3]_i_91\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_88_n_6\,
O => \y_int[3]_i_91_n_0\
);
\y_int[3]_i_92\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(1),
O => \y_int[3]_i_92_n_0\
);
\y_int[7]_i_10\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => y_int_reg3(6),
I1 => \y_int_reg[31]_i_8_n_5\,
I2 => \y_int_reg[31]_i_8_n_7\,
I3 => y_int_reg6,
I4 => y_int_reg5(14),
O => y_int_reg20_in(6)
);
\y_int[7]_i_11\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \y_int_reg[11]_i_38_n_6\,
I1 => \rgb888[8]_21\(2),
I2 => \rgb888[8]_20\(3),
I3 => \^y_int_reg[3]_1\(0),
I4 => \rgb888[8]_22\(0),
O => \y_int[7]_i_11_n_0\
);
\y_int[7]_i_12\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => y_int_reg3(5),
I1 => \y_int_reg[31]_i_8_n_5\,
I2 => \y_int_reg[31]_i_16_n_4\,
I3 => y_int_reg6,
I4 => y_int_reg5(13),
O => y_int_reg20_in(5)
);
\y_int[7]_i_13\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \y_int_reg[11]_i_38_n_7\,
I1 => \rgb888[8]_21\(2),
I2 => \rgb888[8]_20\(2),
I3 => \^y_int_reg[3]_1\(0),
I4 => \rgb888[14]_1\(3),
O => \y_int[7]_i_13_n_0\
);
\y_int[7]_i_14\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => y_int_reg2(5),
I1 => \^y_int_reg[23]_0\(0),
I2 => \y_int_reg[31]_i_11_n_5\,
I3 => \^y_int_reg[7]_0\(0),
I4 => \y_int_reg[11]_i_21_n_7\,
O => y_int_reg1(5)
);
\y_int[7]_i_15\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => y_int_reg3(4),
I1 => \y_int_reg[31]_i_8_n_5\,
I2 => \y_int_reg[31]_i_16_n_5\,
I3 => y_int_reg6,
I4 => y_int_reg5(12),
O => y_int_reg20_in(4)
);
\y_int[7]_i_16\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \y_int_reg[7]_i_24_n_4\,
I1 => \rgb888[8]_21\(2),
I2 => \rgb888[8]_20\(1),
I3 => \^y_int_reg[3]_1\(0),
I4 => \rgb888[14]_1\(2),
O => \y_int[7]_i_16_n_0\
);
\y_int[7]_i_17\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => y_int_reg2(4),
I1 => \^y_int_reg[23]_0\(0),
I2 => \y_int_reg[31]_i_11_n_6\,
I3 => \^y_int_reg[7]_0\(0),
I4 => \y_int_reg[11]_i_44_n_4\,
O => y_int_reg1(4)
);
\y_int[7]_i_18\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => y_int_reg3(3),
I1 => \y_int_reg[31]_i_8_n_5\,
I2 => \y_int_reg[31]_i_16_n_6\,
I3 => y_int_reg6,
I4 => y_int_reg5(11),
O => y_int_reg20_in(3)
);
\y_int[7]_i_19\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \y_int_reg[7]_i_24_n_5\,
I1 => \rgb888[8]_21\(2),
I2 => \rgb888[8]_20\(0),
I3 => \^y_int_reg[3]_1\(0),
I4 => \rgb888[14]_1\(1),
O => \y_int[7]_i_19_n_0\
);
\y_int[7]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"E888E888E8EEE888"
)
port map (
I0 => y_int_reg20_in(6),
I1 => \y_int[7]_i_11_n_0\,
I2 => y_int_reg2(6),
I3 => \^y_int_reg[23]_0\(0),
I4 => \y_int_reg[11]_i_21_n_6\,
I5 => \^y_int_reg[7]_0\(0),
O => \y_int[7]_i_2_n_0\
);
\y_int[7]_i_20\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => y_int_reg2(3),
I1 => \^y_int_reg[23]_0\(0),
I2 => \y_int_reg[31]_i_11_n_7\,
I3 => \^y_int_reg[7]_0\(0),
I4 => \y_int_reg[11]_i_44_n_5\,
O => y_int_reg1(3)
);
\y_int[7]_i_21\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => y_int_reg2(7),
I1 => \^y_int_reg[23]_0\(0),
I2 => \y_int_reg[11]_i_21_n_5\,
I3 => \^y_int_reg[7]_0\(0),
O => y_int_reg1(7)
);
\y_int[7]_i_22\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => y_int_reg2(6),
I1 => \^y_int_reg[23]_0\(0),
I2 => \y_int_reg[11]_i_21_n_6\,
I3 => \^y_int_reg[7]_0\(0),
O => y_int_reg1(6)
);
\y_int[7]_i_29\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \rgb888[14]_0\(0),
I1 => \^y_int_reg[3]_1\(0),
I2 => \rgb888[14]\(1),
O => \y_int[7]_i_29_n_0\
);
\y_int[7]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => y_int_reg20_in(5),
I1 => \y_int[7]_i_13_n_0\,
I2 => y_int_reg1(5),
O => \y_int[7]_i_3_n_0\
);
\y_int[7]_i_30\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \rgb888[14]_1\(2),
I1 => \^y_int_reg[3]_1\(0),
I2 => \rgb888[8]_20\(1),
O => \y_int[7]_i_30_n_0\
);
\y_int[7]_i_31\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \rgb888[14]_1\(1),
I1 => \^y_int_reg[3]_1\(0),
I2 => \rgb888[8]_20\(0),
O => \y_int[7]_i_31_n_0\
);
\y_int[7]_i_32\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \rgb888[14]_1\(0),
I1 => \^y_int_reg[3]_1\(0),
I2 => \rgb888[14]\(3),
O => \y_int[7]_i_32_n_0\
);
\y_int[7]_i_33\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \rgb888[14]_0\(1),
I1 => \^y_int_reg[3]_1\(0),
I2 => \rgb888[14]\(2),
O => \y_int[7]_i_33_n_0\
);
\y_int[7]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => y_int_reg20_in(4),
I1 => \y_int[7]_i_16_n_0\,
I2 => y_int_reg1(4),
O => \y_int[7]_i_4_n_0\
);
\y_int[7]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => y_int_reg20_in(3),
I1 => \y_int[7]_i_19_n_0\,
I2 => y_int_reg1(3),
O => \y_int[7]_i_5_n_0\
);
\y_int[7]_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \y_int[7]_i_2_n_0\,
I1 => y_int_reg1(7),
I2 => \y_int[11]_i_19_n_0\,
I3 => y_int_reg20_in(7),
O => \y_int[7]_i_6_n_0\
);
\y_int[7]_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \y_int[7]_i_3_n_0\,
I1 => y_int_reg1(6),
I2 => \y_int[7]_i_11_n_0\,
I3 => y_int_reg20_in(6),
O => \y_int[7]_i_7_n_0\
);
\y_int[7]_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => y_int_reg20_in(5),
I1 => \y_int[7]_i_13_n_0\,
I2 => y_int_reg1(5),
I3 => \y_int[7]_i_4_n_0\,
O => \y_int[7]_i_8_n_0\
);
\y_int[7]_i_9\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => y_int_reg20_in(4),
I1 => \y_int[7]_i_16_n_0\,
I2 => y_int_reg1(4),
I3 => \y_int[7]_i_5_n_0\,
O => \y_int[7]_i_9_n_0\
);
\y_int_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[3]_i_1_n_7\,
Q => \y_int_reg_n_0_[0]\,
R => '0'
);
\y_int_reg[10]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[11]_i_1_n_5\,
Q => \y_int_reg__0\(10),
R => '0'
);
\y_int_reg[11]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[11]_i_1_n_4\,
Q => \y_int_reg__0\(11),
R => '0'
);
\y_int_reg[11]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[7]_i_1_n_0\,
CO(3) => \y_int_reg[11]_i_1_n_0\,
CO(2) => \y_int_reg[11]_i_1_n_1\,
CO(1) => \y_int_reg[11]_i_1_n_2\,
CO(0) => \y_int_reg[11]_i_1_n_3\,
CYINIT => '0',
DI(3) => \y_int[11]_i_2_n_0\,
DI(2) => \y_int[11]_i_3_n_0\,
DI(1) => \y_int[11]_i_4_n_0\,
DI(0) => \y_int[11]_i_5_n_0\,
O(3) => \y_int_reg[11]_i_1_n_4\,
O(2) => \y_int_reg[11]_i_1_n_5\,
O(1) => \y_int_reg[11]_i_1_n_6\,
O(0) => \y_int_reg[11]_i_1_n_7\,
S(3) => \y_int[11]_i_6_n_0\,
S(2) => \y_int[11]_i_7_n_0\,
S(1) => \y_int[11]_i_8_n_0\,
S(0) => \y_int[11]_i_9_n_0\
);
\y_int_reg[11]_i_14\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[11]_i_28_n_0\,
CO(3) => \y_int_reg[11]_i_14_n_0\,
CO(2) => \y_int_reg[11]_i_14_n_1\,
CO(1) => \y_int_reg[11]_i_14_n_2\,
CO(0) => \y_int_reg[11]_i_14_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => y_int_reg5(16 downto 13),
S(3) => \y_int[11]_i_29_n_0\,
S(2) => \y_int[11]_i_30_n_0\,
S(1) => \y_int[11]_i_31_n_0\,
S(0) => \y_int[11]_i_32_n_0\
);
\y_int_reg[11]_i_15\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[11]_i_33_n_0\,
CO(3) => \y_int_reg[11]_i_15_n_0\,
CO(2) => \y_int_reg[11]_i_15_n_1\,
CO(1) => \y_int_reg[11]_i_15_n_2\,
CO(0) => \y_int_reg[11]_i_15_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => y_int_reg3(8 downto 5),
S(3) => \y_int[11]_i_34_n_0\,
S(2) => \y_int[11]_i_35_n_0\,
S(1) => \y_int[11]_i_36_n_0\,
S(0) => \y_int[11]_i_37_n_0\
);
\y_int_reg[11]_i_20\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[11]_i_39_n_0\,
CO(3) => \y_int_reg[15]_1\(0),
CO(2) => \y_int_reg[11]_i_20_n_1\,
CO(1) => \y_int_reg[11]_i_20_n_2\,
CO(0) => \y_int_reg[11]_i_20_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => y_int_reg2(8 downto 5),
S(3) => \y_int[11]_i_40_n_0\,
S(2) => \y_int[11]_i_41_n_0\,
S(1) => \y_int[11]_i_42_n_0\,
S(0) => \y_int[11]_i_43_n_0\
);
\y_int_reg[11]_i_21\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[11]_i_44_n_0\,
CO(3) => \y_int_reg[11]_i_21_n_0\,
CO(2) => \y_int_reg[11]_i_21_n_1\,
CO(1) => \y_int_reg[11]_i_21_n_2\,
CO(0) => \y_int_reg[11]_i_21_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \y_int_reg[11]_i_21_n_4\,
O(2) => \y_int_reg[11]_i_21_n_5\,
O(1) => \y_int_reg[11]_i_21_n_6\,
O(0) => \y_int_reg[11]_i_21_n_7\,
S(3) => \y_int[11]_i_45_n_0\,
S(2) => \y_int[11]_i_46_n_0\,
S(1) => \y_int[11]_i_47_n_0\,
S(0) => \y_int[11]_i_48_n_0\
);
\y_int_reg[11]_i_22\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[11]_i_49_n_0\,
CO(3) => \^y_int_reg[7]_0\(0),
CO(2) => \y_int_reg[11]_i_22_n_1\,
CO(1) => \y_int_reg[11]_i_22_n_2\,
CO(0) => \y_int_reg[11]_i_22_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \^y_int_reg[23]_0\(0),
DI(1) => \^y_int_reg[23]_0\(0),
DI(0) => \^y_int_reg[23]_0\(0),
O(3 downto 0) => \NLW_y_int_reg[11]_i_22_O_UNCONNECTED\(3 downto 0),
S(3) => \y_int[11]_i_50_n_0\,
S(2) => \y_int[11]_i_51_n_0\,
S(1) => \y_int[11]_i_52_n_0\,
S(0) => \y_int[11]_i_53_n_0\
);
\y_int_reg[11]_i_28\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[3]_i_15_n_0\,
CO(3) => \y_int_reg[11]_i_28_n_0\,
CO(2) => \y_int_reg[11]_i_28_n_1\,
CO(1) => \y_int_reg[11]_i_28_n_2\,
CO(0) => \y_int_reg[11]_i_28_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => y_int_reg5(12 downto 9),
S(3) => \y_int[11]_i_58_n_0\,
S(2) => \y_int[11]_i_59_n_0\,
S(1) => \y_int[11]_i_60_n_0\,
S(0) => \y_int[11]_i_61_n_0\
);
\y_int_reg[11]_i_33\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \y_int_reg[11]_i_33_n_0\,
CO(2) => \y_int_reg[11]_i_33_n_1\,
CO(1) => \y_int_reg[11]_i_33_n_2\,
CO(0) => \y_int_reg[11]_i_33_n_3\,
CYINIT => \y_int[11]_i_62_n_0\,
DI(3 downto 0) => B"0000",
O(3 downto 0) => y_int_reg3(4 downto 1),
S(3) => \y_int[11]_i_63_n_0\,
S(2) => \y_int[11]_i_64_n_0\,
S(1) => \y_int[11]_i_65_n_0\,
S(0) => \y_int[11]_i_66_n_0\
);
\y_int_reg[11]_i_38\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[7]_i_24_n_0\,
CO(3) => \y_int_reg[11]_i_38_n_0\,
CO(2) => \y_int_reg[11]_i_38_n_1\,
CO(1) => \y_int_reg[11]_i_38_n_2\,
CO(0) => \y_int_reg[11]_i_38_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \y_int_reg[11]_i_38_n_4\,
O(2) => \y_int_reg[11]_i_38_n_5\,
O(1) => \y_int_reg[11]_i_38_n_6\,
O(0) => \y_int_reg[11]_i_38_n_7\,
S(3) => \y_int[11]_i_67_n_0\,
S(2) => \y_int[11]_i_68_n_0\,
S(1) => \y_int[11]_i_69_n_0\,
S(0) => \y_int[11]_i_70_n_0\
);
\y_int_reg[11]_i_39\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \y_int_reg[11]_i_39_n_0\,
CO(2) => \y_int_reg[11]_i_39_n_1\,
CO(1) => \y_int_reg[11]_i_39_n_2\,
CO(0) => \y_int_reg[11]_i_39_n_3\,
CYINIT => \y_int[11]_i_71_n_0\,
DI(3 downto 0) => B"0000",
O(3 downto 0) => y_int_reg2(4 downto 1),
S(3) => \y_int[11]_i_72_n_0\,
S(2) => \y_int[11]_i_73_n_0\,
S(1) => \y_int[11]_i_74_n_0\,
S(0) => \y_int[11]_i_75_n_0\
);
\y_int_reg[11]_i_44\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[3]_i_35_n_0\,
CO(3) => \y_int_reg[11]_i_44_n_0\,
CO(2) => \y_int_reg[11]_i_44_n_1\,
CO(1) => \y_int_reg[11]_i_44_n_2\,
CO(0) => \y_int_reg[11]_i_44_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \y_int_reg[11]_i_44_n_4\,
O(2) => \y_int_reg[11]_i_44_n_5\,
O(1) => \y_int_reg[11]_i_44_n_6\,
O(0) => \y_int_reg[11]_i_44_n_7\,
S(3) => \y_int[11]_i_76_n_0\,
S(2) => \y_int[11]_i_77_n_0\,
S(1) => \y_int[11]_i_78_n_0\,
S(0) => \y_int[11]_i_79_n_0\
);
\y_int_reg[11]_i_49\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[11]_i_80_n_0\,
CO(3) => \y_int_reg[11]_i_49_n_0\,
CO(2) => \y_int_reg[11]_i_49_n_1\,
CO(1) => \y_int_reg[11]_i_49_n_2\,
CO(0) => \y_int_reg[11]_i_49_n_3\,
CYINIT => '0',
DI(3) => \^y_int_reg[23]_0\(0),
DI(2) => \^y_int_reg[23]_0\(0),
DI(1) => \^y_int_reg[23]_0\(0),
DI(0) => \^y_int_reg[23]_0\(0),
O(3 downto 0) => \NLW_y_int_reg[11]_i_49_O_UNCONNECTED\(3 downto 0),
S(3) => \y_int[11]_i_81_n_0\,
S(2) => \y_int[11]_i_82_n_0\,
S(1) => \y_int[11]_i_83_n_0\,
S(0) => \y_int[11]_i_84_n_0\
);
\y_int_reg[11]_i_80\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[11]_i_85_n_0\,
CO(3) => \y_int_reg[11]_i_80_n_0\,
CO(2) => \y_int_reg[11]_i_80_n_1\,
CO(1) => \y_int_reg[11]_i_80_n_2\,
CO(0) => \y_int_reg[11]_i_80_n_3\,
CYINIT => '0',
DI(3) => \^y_int_reg[23]_0\(0),
DI(2) => \y_int[11]_i_86_n_0\,
DI(1) => \y_int[11]_i_87_n_0\,
DI(0) => \y_int[11]_i_88_n_0\,
O(3 downto 0) => \NLW_y_int_reg[11]_i_80_O_UNCONNECTED\(3 downto 0),
S(3) => \y_int[11]_i_89_n_0\,
S(2) => \y_int[11]_i_90_n_0\,
S(1) => \y_int[11]_i_91_n_0\,
S(0) => \y_int[11]_i_92_n_0\
);
\y_int_reg[11]_i_85\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \y_int_reg[11]_i_85_n_0\,
CO(2) => \y_int_reg[11]_i_85_n_1\,
CO(1) => \y_int_reg[11]_i_85_n_2\,
CO(0) => \y_int_reg[11]_i_85_n_3\,
CYINIT => '1',
DI(3) => \y_int[11]_i_93_n_0\,
DI(2) => \y_int[11]_i_94_n_0\,
DI(1) => \y_int[11]_i_95_n_0\,
DI(0) => \y_int[11]_i_96_n_0\,
O(3 downto 0) => \NLW_y_int_reg[11]_i_85_O_UNCONNECTED\(3 downto 0),
S(3) => \y_int[11]_i_97_n_0\,
S(2) => \y_int[11]_i_98_n_0\,
S(1) => \y_int[11]_i_99_n_0\,
S(0) => \y_int[11]_i_100_n_0\
);
\y_int_reg[12]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[15]_i_1_n_7\,
Q => \y_int_reg__0\(12),
R => '0'
);
\y_int_reg[13]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[15]_i_1_n_6\,
Q => \y_int_reg__0\(13),
R => '0'
);
\y_int_reg[14]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[15]_i_1_n_5\,
Q => \y_int_reg__0\(14),
R => '0'
);
\y_int_reg[15]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[15]_i_1_n_4\,
Q => \y_int_reg__0\(15),
R => '0'
);
\y_int_reg[15]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[11]_i_1_n_0\,
CO(3) => \y_int_reg[15]_i_1_n_0\,
CO(2) => \y_int_reg[15]_i_1_n_1\,
CO(1) => \y_int_reg[15]_i_1_n_2\,
CO(0) => \y_int_reg[15]_i_1_n_3\,
CYINIT => '0',
DI(3) => \y_int[15]_i_2_n_0\,
DI(2) => \y_int[15]_i_3_n_0\,
DI(1) => \y_int[15]_i_4_n_0\,
DI(0) => \y_int[15]_i_5_n_0\,
O(3) => \y_int_reg[15]_i_1_n_4\,
O(2) => \y_int_reg[15]_i_1_n_5\,
O(1) => \y_int_reg[15]_i_1_n_6\,
O(0) => \y_int_reg[15]_i_1_n_7\,
S(3) => \y_int[15]_i_6_n_0\,
S(2) => \y_int[15]_i_7_n_0\,
S(1) => \y_int[15]_i_8_n_0\,
S(0) => \y_int[15]_i_9_n_0\
);
\y_int_reg[15]_i_14\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[11]_i_14_n_0\,
CO(3) => \y_int_reg[15]_i_14_n_0\,
CO(2) => \y_int_reg[15]_i_14_n_1\,
CO(1) => \y_int_reg[15]_i_14_n_2\,
CO(0) => \y_int_reg[15]_i_14_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => y_int_reg5(20 downto 17),
S(3) => \y_int[15]_i_25_n_0\,
S(2) => \y_int[15]_i_26_n_0\,
S(1) => \y_int[15]_i_27_n_0\,
S(0) => \y_int[15]_i_28_n_0\
);
\y_int_reg[15]_i_15\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[11]_i_15_n_0\,
CO(3) => \y_int_reg[15]_i_15_n_0\,
CO(2) => \y_int_reg[15]_i_15_n_1\,
CO(1) => \y_int_reg[15]_i_15_n_2\,
CO(0) => \y_int_reg[15]_i_15_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => y_int_reg3(12 downto 9),
S(3) => \y_int[15]_i_29_n_0\,
S(2) => \y_int[15]_i_30_n_0\,
S(1) => \y_int[15]_i_31_n_0\,
S(0) => \y_int[15]_i_32_n_0\
);
\y_int_reg[15]_i_33\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[11]_i_38_n_0\,
CO(3) => \y_int_reg[19]_1\(0),
CO(2) => \y_int_reg[15]_i_33_n_1\,
CO(1) => \y_int_reg[15]_i_33_n_2\,
CO(0) => \y_int_reg[15]_i_33_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \y_int_reg[15]_i_33_n_4\,
O(2) => \y_int_reg[15]_i_33_n_5\,
O(1) => \y_int_reg[15]_i_33_n_6\,
O(0) => \y_int_reg[15]_i_33_n_7\,
S(3) => \y_int[15]_i_40_n_0\,
S(2) => \y_int[15]_i_41_n_0\,
S(1) => \y_int[15]_i_42_n_0\,
S(0) => \y_int[15]_i_43_n_0\
);
\y_int_reg[15]_i_35\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[11]_i_21_n_0\,
CO(3) => \y_int_reg[15]_i_35_n_0\,
CO(2) => \y_int_reg[15]_i_35_n_1\,
CO(1) => \y_int_reg[15]_i_35_n_2\,
CO(0) => \y_int_reg[15]_i_35_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \^y_int_reg[15]_0\(3 downto 0),
S(3) => \y_int[15]_i_48_n_0\,
S(2) => \y_int[15]_i_49_n_0\,
S(1) => \y_int[15]_i_50_n_0\,
S(0) => \y_int[15]_i_51_n_0\
);
\y_int_reg[16]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[19]_i_1_n_7\,
Q => \y_int_reg__0\(16),
R => '0'
);
\y_int_reg[17]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[19]_i_1_n_6\,
Q => \y_int_reg__0\(17),
R => '0'
);
\y_int_reg[18]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[19]_i_1_n_5\,
Q => \y_int_reg__0\(18),
R => '0'
);
\y_int_reg[19]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[19]_i_1_n_4\,
Q => \y_int_reg__0\(19),
R => '0'
);
\y_int_reg[19]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[15]_i_1_n_0\,
CO(3) => \y_int_reg[19]_i_1_n_0\,
CO(2) => \y_int_reg[19]_i_1_n_1\,
CO(1) => \y_int_reg[19]_i_1_n_2\,
CO(0) => \y_int_reg[19]_i_1_n_3\,
CYINIT => '0',
DI(3) => \y_int[19]_i_2_n_0\,
DI(2) => \y_int[19]_i_3_n_0\,
DI(1) => \y_int[19]_i_4_n_0\,
DI(0) => \y_int[19]_i_5_n_0\,
O(3) => \y_int_reg[19]_i_1_n_4\,
O(2) => \y_int_reg[19]_i_1_n_5\,
O(1) => \y_int_reg[19]_i_1_n_6\,
O(0) => \y_int_reg[19]_i_1_n_7\,
S(3) => \y_int[19]_i_6_n_0\,
S(2) => \y_int[19]_i_7_n_0\,
S(1) => \y_int[19]_i_8_n_0\,
S(0) => \y_int[19]_i_9_n_0\
);
\y_int_reg[19]_i_14\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[15]_i_14_n_0\,
CO(3) => \y_int_reg[19]_i_14_n_0\,
CO(2) => \y_int_reg[19]_i_14_n_1\,
CO(1) => \y_int_reg[19]_i_14_n_2\,
CO(0) => \y_int_reg[19]_i_14_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => y_int_reg5(24 downto 21),
S(3) => \y_int[19]_i_25_n_0\,
S(2) => \y_int[19]_i_26_n_0\,
S(1) => \y_int[19]_i_27_n_0\,
S(0) => \y_int[19]_i_28_n_0\
);
\y_int_reg[19]_i_15\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[15]_i_15_n_0\,
CO(3) => \y_int_reg[19]_i_15_n_0\,
CO(2) => \y_int_reg[19]_i_15_n_1\,
CO(1) => \y_int_reg[19]_i_15_n_2\,
CO(0) => \y_int_reg[19]_i_15_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => y_int_reg3(16 downto 13),
S(3) => \y_int[19]_i_29_n_0\,
S(2) => \y_int[19]_i_30_n_0\,
S(1) => \y_int[19]_i_31_n_0\,
S(0) => \y_int[19]_i_32_n_0\
);
\y_int_reg[19]_i_35\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[15]_i_35_n_0\,
CO(3) => \y_int_reg[19]_i_35_n_0\,
CO(2) => \y_int_reg[19]_i_35_n_1\,
CO(1) => \y_int_reg[19]_i_35_n_2\,
CO(0) => \y_int_reg[19]_i_35_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \^y_int_reg[19]_0\(3 downto 0),
S(3) => \y_int[19]_i_48_n_0\,
S(2) => \y_int[19]_i_49_n_0\,
S(1) => \y_int[19]_i_50_n_0\,
S(0) => \y_int[19]_i_51_n_0\
);
\y_int_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[3]_i_1_n_6\,
Q => \y_int_reg_n_0_[1]\,
R => '0'
);
\y_int_reg[20]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[23]_i_1_n_7\,
Q => \y_int_reg__0\(20),
R => '0'
);
\y_int_reg[21]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[23]_i_1_n_6\,
Q => \y_int_reg__0\(21),
R => '0'
);
\y_int_reg[22]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[23]_i_1_n_5\,
Q => \y_int_reg__0\(22),
R => '0'
);
\y_int_reg[23]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[23]_i_1_n_4\,
Q => \y_int_reg__0\(23),
R => '0'
);
\y_int_reg[23]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[19]_i_1_n_0\,
CO(3) => \y_int_reg[23]_i_1_n_0\,
CO(2) => \y_int_reg[23]_i_1_n_1\,
CO(1) => \y_int_reg[23]_i_1_n_2\,
CO(0) => \y_int_reg[23]_i_1_n_3\,
CYINIT => '0',
DI(3) => \y_int[23]_i_2_n_0\,
DI(2) => \y_int[23]_i_3_n_0\,
DI(1) => \y_int[23]_i_4_n_0\,
DI(0) => \y_int[23]_i_5_n_0\,
O(3) => \y_int_reg[23]_i_1_n_4\,
O(2) => \y_int_reg[23]_i_1_n_5\,
O(1) => \y_int_reg[23]_i_1_n_6\,
O(0) => \y_int_reg[23]_i_1_n_7\,
S(3) => \y_int[23]_i_6_n_0\,
S(2) => \y_int[23]_i_7_n_0\,
S(1) => \y_int[23]_i_8_n_0\,
S(0) => \y_int[23]_i_9_n_0\
);
\y_int_reg[23]_i_10\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[23]_i_25_n_0\,
CO(3) => y_int_reg6,
CO(2) => \y_int_reg[23]_i_10_n_1\,
CO(1) => \y_int_reg[23]_i_10_n_2\,
CO(0) => \y_int_reg[23]_i_10_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \y_int_reg[31]_i_8_n_5\,
DI(1) => \y_int_reg[31]_i_8_n_5\,
DI(0) => \y_int_reg[31]_i_8_n_5\,
O(3 downto 0) => \NLW_y_int_reg[23]_i_10_O_UNCONNECTED\(3 downto 0),
S(3) => \y_int[23]_i_26_n_0\,
S(2) => \y_int[23]_i_27_n_0\,
S(1) => \y_int[23]_i_28_n_0\,
S(0) => \y_int[23]_i_29_n_0\
);
\y_int_reg[23]_i_11\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[23]_i_16_n_0\,
CO(3 downto 1) => \NLW_y_int_reg[23]_i_11_CO_UNCONNECTED\(3 downto 1),
CO(0) => \y_int_reg[23]_i_11_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 2) => \NLW_y_int_reg[23]_i_11_O_UNCONNECTED\(3 downto 2),
O(1 downto 0) => y_int_reg5(30 downto 29),
S(3 downto 2) => B"00",
S(1) => \y_int[23]_i_30_n_0\,
S(0) => \y_int[23]_i_31_n_0\
);
\y_int_reg[23]_i_16\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[19]_i_14_n_0\,
CO(3) => \y_int_reg[23]_i_16_n_0\,
CO(2) => \y_int_reg[23]_i_16_n_1\,
CO(1) => \y_int_reg[23]_i_16_n_2\,
CO(0) => \y_int_reg[23]_i_16_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => y_int_reg5(28 downto 25),
S(3) => \y_int[23]_i_36_n_0\,
S(2) => \y_int[23]_i_37_n_0\,
S(1) => \y_int[23]_i_38_n_0\,
S(0) => \y_int[23]_i_39_n_0\
);
\y_int_reg[23]_i_17\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[19]_i_15_n_0\,
CO(3) => \y_int_reg[23]_i_17_n_0\,
CO(2) => \y_int_reg[23]_i_17_n_1\,
CO(1) => \y_int_reg[23]_i_17_n_2\,
CO(0) => \y_int_reg[23]_i_17_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => y_int_reg3(20 downto 17),
S(3) => \y_int[23]_i_40_n_0\,
S(2) => \y_int[23]_i_41_n_0\,
S(1) => \y_int[23]_i_42_n_0\,
S(0) => \y_int[23]_i_43_n_0\
);
\y_int_reg[23]_i_25\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[23]_i_45_n_0\,
CO(3) => \y_int_reg[23]_i_25_n_0\,
CO(2) => \y_int_reg[23]_i_25_n_1\,
CO(1) => \y_int_reg[23]_i_25_n_2\,
CO(0) => \y_int_reg[23]_i_25_n_3\,
CYINIT => '0',
DI(3) => \y_int_reg[31]_i_8_n_5\,
DI(2) => \y_int_reg[31]_i_8_n_5\,
DI(1) => \y_int_reg[31]_i_8_n_5\,
DI(0) => \y_int_reg[31]_i_8_n_5\,
O(3 downto 0) => \NLW_y_int_reg[23]_i_25_O_UNCONNECTED\(3 downto 0),
S(3) => \y_int[23]_i_46_n_0\,
S(2) => \y_int[23]_i_47_n_0\,
S(1) => \y_int[23]_i_48_n_0\,
S(0) => \y_int[23]_i_49_n_0\
);
\y_int_reg[23]_i_33\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[23]_i_51_n_0\,
CO(3) => \^y_int_reg[3]_1\(0),
CO(2) => \y_int_reg[23]_i_33_n_1\,
CO(1) => \y_int_reg[23]_i_33_n_2\,
CO(0) => \y_int_reg[23]_i_33_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \rgb888[8]_21\(2),
DI(1) => \rgb888[8]_21\(2),
DI(0) => \rgb888[8]_21\(2),
O(3 downto 0) => \NLW_y_int_reg[23]_i_33_O_UNCONNECTED\(3 downto 0),
S(3) => \y_int[23]_i_52_n_0\,
S(2) => \y_int[23]_i_53_n_0\,
S(1) => \y_int[23]_i_54_n_0\,
S(0) => \y_int[23]_i_55_n_0\
);
\y_int_reg[23]_i_34\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[23]_i_44_n_0\,
CO(3 downto 1) => \NLW_y_int_reg[23]_i_34_CO_UNCONNECTED\(3 downto 1),
CO(0) => \y_int_reg[23]_i_34_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 2) => \NLW_y_int_reg[23]_i_34_O_UNCONNECTED\(3 downto 2),
O(1 downto 0) => \^y_int_reg[23]_1\(1 downto 0),
S(3 downto 2) => B"00",
S(1) => \y_int[23]_i_56_n_0\,
S(0) => \y_int[23]_i_57_n_0\
);
\y_int_reg[23]_i_44\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[19]_i_35_n_0\,
CO(3) => \y_int_reg[23]_i_44_n_0\,
CO(2) => \y_int_reg[23]_i_44_n_1\,
CO(1) => \y_int_reg[23]_i_44_n_2\,
CO(0) => \y_int_reg[23]_i_44_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \^y_int_reg[23]_2\(3 downto 0),
S(3) => \y_int[23]_i_62_n_0\,
S(2) => \y_int[23]_i_63_n_0\,
S(1) => \y_int[23]_i_64_n_0\,
S(0) => \y_int[23]_i_65_n_0\
);
\y_int_reg[23]_i_45\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[23]_i_66_n_0\,
CO(3) => \y_int_reg[23]_i_45_n_0\,
CO(2) => \y_int_reg[23]_i_45_n_1\,
CO(1) => \y_int_reg[23]_i_45_n_2\,
CO(0) => \y_int_reg[23]_i_45_n_3\,
CYINIT => '0',
DI(3) => \y_int[23]_i_67_n_0\,
DI(2) => \y_int[23]_i_68_n_0\,
DI(1) => \y_int[23]_i_69_n_0\,
DI(0) => \y_int[23]_i_70_n_0\,
O(3 downto 0) => \NLW_y_int_reg[23]_i_45_O_UNCONNECTED\(3 downto 0),
S(3) => \y_int[23]_i_71_n_0\,
S(2) => \y_int[23]_i_72_n_0\,
S(1) => \y_int[23]_i_73_n_0\,
S(0) => \y_int[23]_i_74_n_0\
);
\y_int_reg[23]_i_51\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[23]_i_75_n_0\,
CO(3) => \y_int_reg[23]_i_51_n_0\,
CO(2) => \y_int_reg[23]_i_51_n_1\,
CO(1) => \y_int_reg[23]_i_51_n_2\,
CO(0) => \y_int_reg[23]_i_51_n_3\,
CYINIT => '0',
DI(3) => \rgb888[8]_21\(2),
DI(2) => \rgb888[8]_21\(2),
DI(1) => \rgb888[8]_21\(2),
DI(0) => \y_int[23]_i_76_n_0\,
O(3 downto 0) => \NLW_y_int_reg[23]_i_51_O_UNCONNECTED\(3 downto 0),
S(3) => \y_int[23]_i_77_n_0\,
S(2) => \y_int[23]_i_78_n_0\,
S(1) => \y_int[23]_i_79_n_0\,
S(0) => \y_int[23]_i_80_n_0\
);
\y_int_reg[23]_i_66\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \y_int_reg[23]_i_66_n_0\,
CO(2) => \y_int_reg[23]_i_66_n_1\,
CO(1) => \y_int_reg[23]_i_66_n_2\,
CO(0) => \y_int_reg[23]_i_66_n_3\,
CYINIT => '1',
DI(3) => \y_int[23]_i_81_n_0\,
DI(2) => \y_int[23]_i_82_n_0\,
DI(1) => \y_int[23]_i_83_n_0\,
DI(0) => \y_int[23]_i_84_n_0\,
O(3 downto 0) => \NLW_y_int_reg[23]_i_66_O_UNCONNECTED\(3 downto 0),
S(3) => \y_int[23]_i_85_n_0\,
S(2) => \y_int[23]_i_86_n_0\,
S(1) => \y_int[23]_i_87_n_0\,
S(0) => \y_int[23]_i_88_n_0\
);
\y_int_reg[23]_i_75\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[23]_i_89_n_0\,
CO(3) => \y_int_reg[23]_i_75_n_0\,
CO(2) => \y_int_reg[23]_i_75_n_1\,
CO(1) => \y_int_reg[23]_i_75_n_2\,
CO(0) => \y_int_reg[23]_i_75_n_3\,
CYINIT => '0',
DI(3) => \y_int[23]_i_90_n_0\,
DI(2) => \y_int[23]_i_91_n_0\,
DI(1) => \y_int[23]_i_92_n_0\,
DI(0) => \y_int[23]_i_93_n_0\,
O(3 downto 0) => \NLW_y_int_reg[23]_i_75_O_UNCONNECTED\(3 downto 0),
S(3) => \y_int[23]_i_94_n_0\,
S(2) => \y_int[23]_i_95_n_0\,
S(1) => \y_int[23]_i_96_n_0\,
S(0) => \y_int[23]_i_97_n_0\
);
\y_int_reg[23]_i_89\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \y_int_reg[23]_i_89_n_0\,
CO(2) => \y_int_reg[23]_i_89_n_1\,
CO(1) => \y_int_reg[23]_i_89_n_2\,
CO(0) => \y_int_reg[23]_i_89_n_3\,
CYINIT => '1',
DI(3) => \y_int[23]_i_98_n_0\,
DI(2) => \y_int[23]_i_99_n_0\,
DI(1) => \y_int[23]_i_100_n_0\,
DI(0) => rgb888(8),
O(3 downto 0) => \NLW_y_int_reg[23]_i_89_O_UNCONNECTED\(3 downto 0),
S(3) => \y_int[23]_i_101_n_0\,
S(2) => \y_int[23]_i_102_n_0\,
S(1) => \y_int[23]_i_103_n_0\,
S(0) => \y_int[23]_i_104_n_0\
);
\y_int_reg[24]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[27]_i_1_n_7\,
Q => \y_int_reg__0\(24),
R => '0'
);
\y_int_reg[25]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[27]_i_1_n_6\,
Q => \y_int_reg__0\(25),
R => '0'
);
\y_int_reg[26]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[27]_i_1_n_5\,
Q => \y_int_reg__0\(26),
R => '0'
);
\y_int_reg[27]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[27]_i_1_n_4\,
Q => \y_int_reg__0\(27),
R => '0'
);
\y_int_reg[27]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[23]_i_1_n_0\,
CO(3) => \y_int_reg[27]_i_1_n_0\,
CO(2) => \y_int_reg[27]_i_1_n_1\,
CO(1) => \y_int_reg[27]_i_1_n_2\,
CO(0) => \y_int_reg[27]_i_1_n_3\,
CYINIT => '0',
DI(3) => \y_int[31]_i_2_n_0\,
DI(2) => \y_int[31]_i_2_n_0\,
DI(1) => \y_int[31]_i_2_n_0\,
DI(0) => \y_int[31]_i_2_n_0\,
O(3) => \y_int_reg[27]_i_1_n_4\,
O(2) => \y_int_reg[27]_i_1_n_5\,
O(1) => \y_int_reg[27]_i_1_n_6\,
O(0) => \y_int_reg[27]_i_1_n_7\,
S(3) => \y_int[27]_i_2_n_0\,
S(2) => \y_int[27]_i_3_n_0\,
S(1) => \y_int[27]_i_4_n_0\,
S(0) => \y_int[27]_i_5_n_0\
);
\y_int_reg[28]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[31]_i_1_n_7\,
Q => \y_int_reg__0\(28),
R => '0'
);
\y_int_reg[29]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[31]_i_1_n_6\,
Q => \y_int_reg__0\(29),
R => '0'
);
\y_int_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[3]_i_1_n_5\,
Q => \y_int_reg_n_0_[2]\,
R => '0'
);
\y_int_reg[30]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[31]_i_1_n_5\,
Q => \y_int_reg__0\(30),
R => '0'
);
\y_int_reg[31]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[31]_i_1_n_4\,
Q => \y_int_reg__0\(31),
R => '0'
);
\y_int_reg[31]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[27]_i_1_n_0\,
CO(3) => \NLW_y_int_reg[31]_i_1_CO_UNCONNECTED\(3),
CO(2) => \y_int_reg[31]_i_1_n_1\,
CO(1) => \y_int_reg[31]_i_1_n_2\,
CO(0) => \y_int_reg[31]_i_1_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \y_int[31]_i_2_n_0\,
DI(1) => \y_int[31]_i_2_n_0\,
DI(0) => \y_int[31]_i_2_n_0\,
O(3) => \y_int_reg[31]_i_1_n_4\,
O(2) => \y_int_reg[31]_i_1_n_5\,
O(1) => \y_int_reg[31]_i_1_n_6\,
O(0) => \y_int_reg[31]_i_1_n_7\,
S(3) => \y_int[31]_i_3_n_0\,
S(2) => \y_int[31]_i_4_n_0\,
S(1) => \y_int[31]_i_5_n_0\,
S(0) => \y_int[31]_i_6_n_0\
);
\y_int_reg[31]_i_11\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[31]_i_30_n_0\,
CO(3) => \NLW_y_int_reg[31]_i_11_CO_UNCONNECTED\(3),
CO(2) => \y_int_reg[31]_i_11_n_1\,
CO(1) => \y_int_reg[31]_i_11_n_2\,
CO(0) => \y_int_reg[31]_i_11_n_3\,
CYINIT => '0',
DI(3 downto 2) => B"00",
DI(1) => \rgb888[0]_9\(1),
DI(0) => \y_int[31]_i_32_n_0\,
O(3) => \^y_int_reg[23]_0\(0),
O(2) => \y_int_reg[31]_i_11_n_5\,
O(1) => \y_int_reg[31]_i_11_n_6\,
O(0) => \y_int_reg[31]_i_11_n_7\,
S(3) => \y_int[31]_i_33_n_0\,
S(2) => \y_int[31]_i_34_n_0\,
S(1) => \y_int[31]_i_35_n_0\,
S(0) => \y_int[31]_i_36_n_0\
);
\y_int_reg[31]_i_16\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[3]_i_16_n_0\,
CO(3) => \y_int_reg[31]_i_16_n_0\,
CO(2) => \y_int_reg[31]_i_16_n_1\,
CO(1) => \y_int_reg[31]_i_16_n_2\,
CO(0) => \y_int_reg[31]_i_16_n_3\,
CYINIT => '0',
DI(3) => \y_int[31]_i_40_n_0\,
DI(2) => \y_int[31]_i_41_n_0\,
DI(1) => \y_int[31]_i_42_n_0\,
DI(0) => \y_int[31]_i_43_n_0\,
O(3) => \y_int_reg[31]_i_16_n_4\,
O(2) => \y_int_reg[31]_i_16_n_5\,
O(1) => \y_int_reg[31]_i_16_n_6\,
O(0) => \y_int_reg[31]_i_16_n_7\,
S(3) => \y_int[31]_i_44_n_0\,
S(2) => \y_int[31]_i_45_n_0\,
S(1) => \y_int[31]_i_46_n_0\,
S(0) => \y_int[31]_i_47_n_0\
);
\y_int_reg[31]_i_30\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[31]_i_62_n_0\,
CO(3) => \y_int_reg[31]_i_30_n_0\,
CO(2) => \y_int_reg[31]_i_30_n_1\,
CO(1) => \y_int_reg[31]_i_30_n_2\,
CO(0) => \y_int_reg[31]_i_30_n_3\,
CYINIT => '0',
DI(3) => \y_int[31]_i_63_n_0\,
DI(2) => \y_int[31]_i_64_n_0\,
DI(1) => \y_int[31]_i_65_n_0\,
DI(0) => \y_int[31]_i_66_n_0\,
O(3) => \y_int_reg[31]_i_30_n_4\,
O(2) => \y_int_reg[31]_i_30_n_5\,
O(1) => \y_int_reg[31]_i_30_n_6\,
O(0) => \y_int_reg[31]_i_30_n_7\,
S(3) => \y_int[31]_i_67_n_0\,
S(2) => \y_int[31]_i_68_n_0\,
S(1) => \y_int[31]_i_69_n_0\,
S(0) => \y_int[31]_i_70_n_0\
);
\y_int_reg[31]_i_62\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \y_int_reg[31]_i_62_n_0\,
CO(2) => \y_int_reg[31]_i_62_n_1\,
CO(1) => \y_int_reg[31]_i_62_n_2\,
CO(0) => \y_int_reg[31]_i_62_n_3\,
CYINIT => '0',
DI(3) => \y_int_reg[31]_i_86_n_5\,
DI(2) => \y_int_reg[31]_i_87_n_7\,
DI(1) => \y_int_reg[31]_i_88_n_4\,
DI(0) => \y_int_reg[31]_i_88_n_5\,
O(3) => \y_int_reg[31]_i_62_n_4\,
O(2) => \y_int_reg[31]_i_62_n_5\,
O(1) => \y_int_reg[31]_i_62_n_6\,
O(0) => \NLW_y_int_reg[31]_i_62_O_UNCONNECTED\(0),
S(3) => \y_int[31]_i_89_n_0\,
S(2) => \y_int[31]_i_90_n_0\,
S(1) => \y_int[31]_i_91_n_0\,
S(0) => \y_int[31]_i_92_n_0\
);
\y_int_reg[31]_i_7\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[23]_i_17_n_0\,
CO(3) => \NLW_y_int_reg[31]_i_7_CO_UNCONNECTED\(3),
CO(2) => \y_int_reg[31]_i_7_n_1\,
CO(1) => \NLW_y_int_reg[31]_i_7_CO_UNCONNECTED\(1),
CO(0) => \y_int_reg[31]_i_7_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 2) => \NLW_y_int_reg[31]_i_7_O_UNCONNECTED\(3 downto 2),
O(1 downto 0) => y_int_reg3(22 downto 21),
S(3 downto 2) => B"01",
S(1) => \y_int[31]_i_14_n_0\,
S(0) => \y_int[31]_i_15_n_0\
);
\y_int_reg[31]_i_75\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[31]_i_87_n_0\,
CO(3 downto 2) => \NLW_y_int_reg[31]_i_75_CO_UNCONNECTED\(3 downto 2),
CO(1) => \y_int_reg[31]_i_75_n_2\,
CO(0) => \NLW_y_int_reg[31]_i_75_CO_UNCONNECTED\(0),
CYINIT => '0',
DI(3 downto 1) => B"000",
DI(0) => rgb888(7),
O(3 downto 1) => \NLW_y_int_reg[31]_i_75_O_UNCONNECTED\(3 downto 1),
O(0) => \y_int_reg[31]_i_75_n_7\,
S(3 downto 1) => B"001",
S(0) => \y_int[31]_i_101_n_0\
);
\y_int_reg[31]_i_8\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[31]_i_16_n_0\,
CO(3 downto 2) => \NLW_y_int_reg[31]_i_8_CO_UNCONNECTED\(3 downto 2),
CO(1) => \y_int_reg[31]_i_8_n_2\,
CO(0) => \y_int_reg[31]_i_8_n_3\,
CYINIT => '0',
DI(3 downto 1) => B"000",
DI(0) => \y_int[31]_i_17_n_0\,
O(3) => \NLW_y_int_reg[31]_i_8_O_UNCONNECTED\(3),
O(2) => \y_int_reg[31]_i_8_n_5\,
O(1) => \y_int_reg[31]_i_8_n_6\,
O(0) => \y_int_reg[31]_i_8_n_7\,
S(3) => '0',
S(2) => \y_int[31]_i_18_n_0\,
S(1) => \y_int[31]_i_19_n_0\,
S(0) => \y_int[31]_i_20_n_0\
);
\y_int_reg[31]_i_86\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \y_int_reg[23]_3\(0),
CO(2) => \y_int_reg[31]_i_86_n_1\,
CO(1) => \y_int_reg[31]_i_86_n_2\,
CO(0) => \y_int_reg[31]_i_86_n_3\,
CYINIT => '0',
DI(3) => \y_int[31]_i_104_n_0\,
DI(2) => rgb888(2),
DI(1 downto 0) => B"01",
O(3) => \y_int_reg[31]_i_86_n_4\,
O(2) => \y_int_reg[31]_i_86_n_5\,
O(1) => \y_int_reg[31]_i_86_n_6\,
O(0) => \NLW_y_int_reg[31]_i_86_O_UNCONNECTED\(0),
S(3) => \y_int[31]_i_105_n_0\,
S(2) => \y_int[31]_i_106_n_0\,
S(1) => \y_int[31]_i_107_n_0\,
S(0) => \y_int[31]_i_108_n_0\
);
\y_int_reg[31]_i_87\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[31]_i_88_n_0\,
CO(3) => \y_int_reg[31]_i_87_n_0\,
CO(2) => \y_int_reg[31]_i_87_n_1\,
CO(1) => \y_int_reg[31]_i_87_n_2\,
CO(0) => \y_int_reg[31]_i_87_n_3\,
CYINIT => '0',
DI(3) => rgb888(6),
DI(2 downto 0) => rgb888(7 downto 5),
O(3) => \y_int_reg[31]_i_87_n_4\,
O(2) => \y_int_reg[31]_i_87_n_5\,
O(1) => \y_int_reg[31]_i_87_n_6\,
O(0) => \y_int_reg[31]_i_87_n_7\,
S(3) => \y_int[31]_i_109_n_0\,
S(2) => \y_int[31]_i_110_n_0\,
S(1) => \y_int[31]_i_111_n_0\,
S(0) => \y_int[31]_i_112_n_0\
);
\y_int_reg[31]_i_88\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \y_int_reg[31]_i_88_n_0\,
CO(2) => \y_int_reg[31]_i_88_n_1\,
CO(1) => \y_int_reg[31]_i_88_n_2\,
CO(0) => \y_int_reg[31]_i_88_n_3\,
CYINIT => '0',
DI(3 downto 1) => rgb888(4 downto 2),
DI(0) => '0',
O(3) => \y_int_reg[31]_i_88_n_4\,
O(2) => \y_int_reg[31]_i_88_n_5\,
O(1) => \y_int_reg[31]_i_88_n_6\,
O(0) => \NLW_y_int_reg[31]_i_88_O_UNCONNECTED\(0),
S(3) => \y_int[31]_i_113_n_0\,
S(2) => \y_int[31]_i_114_n_0\,
S(1) => \y_int[31]_i_115_n_0\,
S(0) => \y_int[31]_i_116_n_0\
);
\y_int_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[3]_i_1_n_4\,
Q => \y_int_reg_n_0_[3]\,
R => '0'
);
\y_int_reg[3]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \y_int_reg[3]_i_1_n_0\,
CO(2) => \y_int_reg[3]_i_1_n_1\,
CO(1) => \y_int_reg[3]_i_1_n_2\,
CO(0) => \y_int_reg[3]_i_1_n_3\,
CYINIT => '0',
DI(3) => \y_int[3]_i_2_n_0\,
DI(2) => \y_int[3]_i_3_n_0\,
DI(1) => \y_int[3]_i_4_n_0\,
DI(0) => '0',
O(3) => \y_int_reg[3]_i_1_n_4\,
O(2) => \y_int_reg[3]_i_1_n_5\,
O(1) => \y_int_reg[3]_i_1_n_6\,
O(0) => \y_int_reg[3]_i_1_n_7\,
S(3) => \y_int[3]_i_5_n_0\,
S(2) => \y_int[3]_i_6_n_0\,
S(1) => \y_int[3]_i_7_n_0\,
S(0) => \y_int[3]_i_8_n_0\
);
\y_int_reg[3]_i_15\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[3]_i_21_n_0\,
CO(3) => \y_int_reg[3]_i_15_n_0\,
CO(2) => \y_int_reg[3]_i_15_n_1\,
CO(1) => \y_int_reg[3]_i_15_n_2\,
CO(0) => \y_int_reg[3]_i_15_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => y_int_reg5(8),
O(2 downto 0) => \NLW_y_int_reg[3]_i_15_O_UNCONNECTED\(2 downto 0),
S(3) => \y_int[3]_i_22_n_0\,
S(2) => \y_int[3]_i_23_n_0\,
S(1) => \y_int[3]_i_24_n_0\,
S(0) => \y_int[3]_i_25_n_0\
);
\y_int_reg[3]_i_16\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[3]_i_26_n_0\,
CO(3) => \y_int_reg[3]_i_16_n_0\,
CO(2) => \y_int_reg[3]_i_16_n_1\,
CO(1) => \y_int_reg[3]_i_16_n_2\,
CO(0) => \y_int_reg[3]_i_16_n_3\,
CYINIT => '0',
DI(3) => \y_int[3]_i_27_n_0\,
DI(2) => \y_int[3]_i_28_n_0\,
DI(1) => \y_int[3]_i_29_n_0\,
DI(0) => \y_int_reg[3]_i_30_n_6\,
O(3) => \y_int_reg[3]_i_16_n_4\,
O(2) => \y_int_reg[3]_i_16_n_5\,
O(1) => \y_int_reg[3]_i_16_n_6\,
O(0) => \y_int_reg[3]_i_16_n_7\,
S(3) => \y_int[3]_i_31_n_0\,
S(2) => \y_int[3]_i_32_n_0\,
S(1) => \y_int[3]_i_33_n_0\,
S(0) => \y_int[3]_i_34_n_0\
);
\y_int_reg[3]_i_21\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \y_int_reg[3]_i_21_n_0\,
CO(2) => \y_int_reg[3]_i_21_n_1\,
CO(1) => \y_int_reg[3]_i_21_n_2\,
CO(0) => \y_int_reg[3]_i_21_n_3\,
CYINIT => \y_int[3]_i_50_n_0\,
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_y_int_reg[3]_i_21_O_UNCONNECTED\(3 downto 0),
S(3) => \y_int[3]_i_51_n_0\,
S(2) => \y_int[3]_i_52_n_0\,
S(1) => \y_int[3]_i_53_n_0\,
S(0) => \y_int[3]_i_54_n_0\
);
\y_int_reg[3]_i_26\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \y_int_reg[3]_i_26_n_0\,
CO(2) => \y_int_reg[3]_i_26_n_1\,
CO(1) => \y_int_reg[3]_i_26_n_2\,
CO(0) => \y_int_reg[3]_i_26_n_3\,
CYINIT => '0',
DI(3) => \y_int_reg[3]_i_30_n_7\,
DI(2) => \y_int_reg[3]_i_55_n_4\,
DI(1) => \y_int_reg[3]_i_55_n_5\,
DI(0) => '0',
O(3) => \y_int_reg[3]_i_26_n_4\,
O(2) => \y_int_reg[3]_i_26_n_5\,
O(1) => \y_int_reg[3]_i_26_n_6\,
O(0) => \y_int_reg[3]_i_26_n_7\,
S(3) => \y_int[3]_i_56_n_0\,
S(2) => \y_int[3]_i_57_n_0\,
S(1) => \y_int[3]_i_58_n_0\,
S(0) => \y_int[3]_i_59_n_0\
);
\y_int_reg[3]_i_30\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[3]_i_55_n_0\,
CO(3) => \y_int_reg[3]_i_30_n_0\,
CO(2) => \y_int_reg[3]_i_30_n_1\,
CO(1) => \y_int_reg[3]_i_30_n_2\,
CO(0) => \y_int_reg[3]_i_30_n_3\,
CYINIT => '0',
DI(3) => rgb888(22),
DI(2 downto 0) => rgb888(23 downto 21),
O(3) => \y_int_reg[3]_i_30_n_4\,
O(2) => \y_int_reg[3]_i_30_n_5\,
O(1) => \y_int_reg[3]_i_30_n_6\,
O(0) => \y_int_reg[3]_i_30_n_7\,
S(3) => \y_int[3]_i_60_n_0\,
S(2) => \y_int[3]_i_61_n_0\,
S(1) => \y_int[3]_i_62_n_0\,
S(0) => \y_int[3]_i_63_n_0\
);
\y_int_reg[3]_i_35\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[3]_i_65_n_0\,
CO(3) => \y_int_reg[3]_i_35_n_0\,
CO(2) => \y_int_reg[3]_i_35_n_1\,
CO(1) => \y_int_reg[3]_i_35_n_2\,
CO(0) => \y_int_reg[3]_i_35_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \y_int_reg[3]_i_35_n_4\,
O(2 downto 0) => \NLW_y_int_reg[3]_i_35_O_UNCONNECTED\(2 downto 0),
S(3) => \y_int[3]_i_66_n_0\,
S(2) => \y_int[3]_i_67_n_0\,
S(1) => \y_int[3]_i_68_n_0\,
S(0) => \y_int[3]_i_69_n_0\
);
\y_int_reg[3]_i_36\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \y_int_reg[3]_2\(0),
CO(2) => \y_int_reg[3]_i_36_n_1\,
CO(1) => \y_int_reg[3]_i_36_n_2\,
CO(0) => \y_int_reg[3]_i_36_n_3\,
CYINIT => '0',
DI(3 downto 2) => \rgb888[8]_32\(1 downto 0),
DI(1) => \rgb888[8]_19\(2),
DI(0) => '0',
O(3 downto 0) => \^y_int_reg[3]_0\(3 downto 0),
S(3) => \y_int[3]_i_71_n_0\,
S(2) => \y_int[3]_i_72_n_0\,
S(1) => \y_int[3]_i_73_n_0\,
S(0) => \y_int[3]_i_74_n_0\
);
\y_int_reg[3]_i_55\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \y_int_reg[3]_i_55_n_0\,
CO(2) => \y_int_reg[3]_i_55_n_1\,
CO(1) => \y_int_reg[3]_i_55_n_2\,
CO(0) => \y_int_reg[3]_i_55_n_3\,
CYINIT => '0',
DI(3 downto 1) => rgb888(20 downto 18),
DI(0) => '0',
O(3) => \y_int_reg[3]_i_55_n_4\,
O(2) => \y_int_reg[3]_i_55_n_5\,
O(1) => \y_int_reg[3]_i_55_n_6\,
O(0) => \NLW_y_int_reg[3]_i_55_O_UNCONNECTED\(0),
S(3) => \y_int[3]_i_84_n_0\,
S(2) => \y_int[3]_i_85_n_0\,
S(1) => \y_int[3]_i_86_n_0\,
S(0) => \y_int[3]_i_87_n_0\
);
\y_int_reg[3]_i_64\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[3]_i_30_n_0\,
CO(3 downto 2) => \NLW_y_int_reg[3]_i_64_CO_UNCONNECTED\(3 downto 2),
CO(1) => \y_int_reg[3]_i_64_n_2\,
CO(0) => \NLW_y_int_reg[3]_i_64_CO_UNCONNECTED\(0),
CYINIT => '0',
DI(3 downto 1) => B"000",
DI(0) => rgb888(23),
O(3 downto 1) => \NLW_y_int_reg[3]_i_64_O_UNCONNECTED\(3 downto 1),
O(0) => \y_int_reg[3]_i_64_n_7\,
S(3 downto 1) => B"001",
S(0) => \y_int[3]_i_88_n_0\
);
\y_int_reg[3]_i_65\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \y_int_reg[3]_i_65_n_0\,
CO(2) => \y_int_reg[3]_i_65_n_1\,
CO(1) => \y_int_reg[3]_i_65_n_2\,
CO(0) => \y_int_reg[3]_i_65_n_3\,
CYINIT => \cr_int[3]_i_80_n_0\,
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_y_int_reg[3]_i_65_O_UNCONNECTED\(3 downto 0),
S(3) => \y_int[3]_i_89_n_0\,
S(2) => \y_int[3]_i_90_n_0\,
S(1) => \y_int[3]_i_91_n_0\,
S(0) => \y_int[3]_i_92_n_0\
);
\y_int_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[7]_i_1_n_7\,
Q => \y_int_reg_n_0_[4]\,
R => '0'
);
\y_int_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[7]_i_1_n_6\,
Q => \y_int_reg_n_0_[5]\,
R => '0'
);
\y_int_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[7]_i_1_n_5\,
Q => \y_int_reg_n_0_[6]\,
R => '0'
);
\y_int_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[7]_i_1_n_4\,
Q => \y_int_reg_n_0_[7]\,
R => '0'
);
\y_int_reg[7]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[3]_i_1_n_0\,
CO(3) => \y_int_reg[7]_i_1_n_0\,
CO(2) => \y_int_reg[7]_i_1_n_1\,
CO(1) => \y_int_reg[7]_i_1_n_2\,
CO(0) => \y_int_reg[7]_i_1_n_3\,
CYINIT => '0',
DI(3) => \y_int[7]_i_2_n_0\,
DI(2) => \y_int[7]_i_3_n_0\,
DI(1) => \y_int[7]_i_4_n_0\,
DI(0) => \y_int[7]_i_5_n_0\,
O(3) => \y_int_reg[7]_i_1_n_4\,
O(2) => \y_int_reg[7]_i_1_n_5\,
O(1) => \y_int_reg[7]_i_1_n_6\,
O(0) => \y_int_reg[7]_i_1_n_7\,
S(3) => \y_int[7]_i_6_n_0\,
S(2) => \y_int[7]_i_7_n_0\,
S(1) => \y_int[7]_i_8_n_0\,
S(0) => \y_int[7]_i_9_n_0\
);
\y_int_reg[7]_i_24\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \y_int_reg[7]_i_24_n_0\,
CO(2) => \y_int_reg[7]_i_24_n_1\,
CO(1) => \y_int_reg[7]_i_24_n_2\,
CO(0) => \y_int_reg[7]_i_24_n_3\,
CYINIT => \y_int[7]_i_29_n_0\,
DI(3 downto 0) => B"0000",
O(3) => \y_int_reg[7]_i_24_n_4\,
O(2) => \y_int_reg[7]_i_24_n_5\,
O(1) => \y_int_reg[7]_i_24_n_6\,
O(0) => \y_int_reg[7]_i_24_n_7\,
S(3) => \y_int[7]_i_30_n_0\,
S(2) => \y_int[7]_i_31_n_0\,
S(1) => \y_int[7]_i_32_n_0\,
S(0) => \y_int[7]_i_33_n_0\
);
\y_int_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[11]_i_1_n_7\,
Q => \y_int_reg__0\(8),
R => '0'
);
\y_int_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[11]_i_1_n_6\,
Q => \y_int_reg__0\(9),
R => '0'
);
\y_reg[0]\: unisim.vcomponents.FDSE
port map (
C => cb_regn_0_0,
CE => '1',
D => \y[0]_i_1_n_0\,
Q => y(0),
S => \y_reg[7]_i_1_n_0\
);
\y_reg[1]\: unisim.vcomponents.FDSE
port map (
C => cb_regn_0_0,
CE => '1',
D => \y[1]_i_1_n_0\,
Q => y(1),
S => \y_reg[7]_i_1_n_0\
);
\y_reg[2]\: unisim.vcomponents.FDSE
port map (
C => cb_regn_0_0,
CE => '1',
D => \y[2]_i_1_n_0\,
Q => y(2),
S => \y_reg[7]_i_1_n_0\
);
\y_reg[3]\: unisim.vcomponents.FDSE
port map (
C => cb_regn_0_0,
CE => '1',
D => \y[3]_i_1_n_0\,
Q => y(3),
S => \y_reg[7]_i_1_n_0\
);
\y_reg[4]\: unisim.vcomponents.FDSE
port map (
C => cb_regn_0_0,
CE => '1',
D => \y[4]_i_1_n_0\,
Q => y(4),
S => \y_reg[7]_i_1_n_0\
);
\y_reg[5]\: unisim.vcomponents.FDSE
port map (
C => cb_regn_0_0,
CE => '1',
D => \y[5]_i_1_n_0\,
Q => y(5),
S => \y_reg[7]_i_1_n_0\
);
\y_reg[6]\: unisim.vcomponents.FDSE
port map (
C => cb_regn_0_0,
CE => '1',
D => \y[6]_i_1_n_0\,
Q => y(6),
S => \y_reg[7]_i_1_n_0\
);
\y_reg[7]\: unisim.vcomponents.FDSE
port map (
C => cb_regn_0_0,
CE => '1',
D => \y[7]_i_2_n_0\,
Q => y(7),
S => \y_reg[7]_i_1_n_0\
);
\y_reg[7]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \y_reg[7]_i_3_n_0\,
CO(3) => \y_reg[7]_i_1_n_0\,
CO(2) => \y_reg[7]_i_1_n_1\,
CO(1) => \y_reg[7]_i_1_n_2\,
CO(0) => \y_reg[7]_i_1_n_3\,
CYINIT => '0',
DI(3) => \y[7]_i_4_n_0\,
DI(2) => \y[7]_i_5_n_0\,
DI(1) => \y[7]_i_6_n_0\,
DI(0) => \y[7]_i_7_n_0\,
O(3 downto 0) => \NLW_y_reg[7]_i_1_O_UNCONNECTED\(3 downto 0),
S(3) => \y[7]_i_8_n_0\,
S(2) => \y[7]_i_9_n_0\,
S(1) => \y[7]_i_10_n_0\,
S(0) => \y[7]_i_11_n_0\
);
\y_reg[7]_i_12\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \y_reg[7]_i_12_n_0\,
CO(2) => \y_reg[7]_i_12_n_1\,
CO(1) => \y_reg[7]_i_12_n_2\,
CO(0) => \y_reg[7]_i_12_n_3\,
CYINIT => '0',
DI(3) => \y[7]_i_21_n_0\,
DI(2) => \y[7]_i_22_n_0\,
DI(1) => \y[7]_i_23_n_0\,
DI(0) => \y[7]_i_24_n_0\,
O(3 downto 0) => \NLW_y_reg[7]_i_12_O_UNCONNECTED\(3 downto 0),
S(3) => \y[7]_i_25_n_0\,
S(2) => \y[7]_i_26_n_0\,
S(1) => \y[7]_i_27_n_0\,
S(0) => \y[7]_i_28_n_0\
);
\y_reg[7]_i_3\: unisim.vcomponents.CARRY4
port map (
CI => \y_reg[7]_i_12_n_0\,
CO(3) => \y_reg[7]_i_3_n_0\,
CO(2) => \y_reg[7]_i_3_n_1\,
CO(1) => \y_reg[7]_i_3_n_2\,
CO(0) => \y_reg[7]_i_3_n_3\,
CYINIT => '0',
DI(3) => \y[7]_i_13_n_0\,
DI(2) => \y[7]_i_14_n_0\,
DI(1) => \y[7]_i_15_n_0\,
DI(0) => \y[7]_i_16_n_0\,
O(3 downto 0) => \NLW_y_reg[7]_i_3_O_UNCONNECTED\(3 downto 0),
S(3) => \y[7]_i_17_n_0\,
S(2) => \y[7]_i_18_n_0\,
S(1) => \y[7]_i_19_n_0\,
S(0) => \y[7]_i_20_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_zed_hdmi_0_0 is
port (
clk : in STD_LOGIC;
clk_x2 : in STD_LOGIC;
clk_100 : in STD_LOGIC;
active : in STD_LOGIC;
hsync : in STD_LOGIC;
vsync : in STD_LOGIC;
rgb888 : in STD_LOGIC_VECTOR ( 23 downto 0 );
hdmi_clk : out STD_LOGIC;
hdmi_hsync : out STD_LOGIC;
hdmi_vsync : out STD_LOGIC;
hdmi_d : out STD_LOGIC_VECTOR ( 15 downto 0 );
hdmi_de : out STD_LOGIC;
hdmi_scl : out STD_LOGIC;
hdmi_sda : inout STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_zed_hdmi_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_zed_hdmi_0_0 : entity is "system_zed_hdmi_0_0,zed_hdmi,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_zed_hdmi_0_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_zed_hdmi_0_0 : entity is "zed_hdmi,Vivado 2016.4";
end system_zed_hdmi_0_0;
architecture STRUCTURE of system_zed_hdmi_0_0 is
signal \<const0>\ : STD_LOGIC;
signal U0_n_10 : STD_LOGIC;
signal U0_n_11 : STD_LOGIC;
signal U0_n_12 : STD_LOGIC;
signal U0_n_13 : STD_LOGIC;
signal U0_n_14 : STD_LOGIC;
signal U0_n_15 : STD_LOGIC;
signal U0_n_16 : STD_LOGIC;
signal U0_n_17 : STD_LOGIC;
signal U0_n_18 : STD_LOGIC;
signal U0_n_19 : STD_LOGIC;
signal U0_n_20 : STD_LOGIC;
signal U0_n_21 : STD_LOGIC;
signal U0_n_22 : STD_LOGIC;
signal U0_n_23 : STD_LOGIC;
signal U0_n_24 : STD_LOGIC;
signal U0_n_25 : STD_LOGIC;
signal U0_n_26 : STD_LOGIC;
signal U0_n_27 : STD_LOGIC;
signal U0_n_28 : STD_LOGIC;
signal U0_n_29 : STD_LOGIC;
signal U0_n_30 : STD_LOGIC;
signal U0_n_31 : STD_LOGIC;
signal U0_n_32 : STD_LOGIC;
signal U0_n_33 : STD_LOGIC;
signal U0_n_34 : STD_LOGIC;
signal U0_n_35 : STD_LOGIC;
signal U0_n_36 : STD_LOGIC;
signal U0_n_37 : STD_LOGIC;
signal U0_n_38 : STD_LOGIC;
signal U0_n_39 : STD_LOGIC;
signal U0_n_4 : STD_LOGIC;
signal U0_n_40 : STD_LOGIC;
signal U0_n_41 : STD_LOGIC;
signal U0_n_42 : STD_LOGIC;
signal U0_n_43 : STD_LOGIC;
signal U0_n_44 : STD_LOGIC;
signal U0_n_45 : STD_LOGIC;
signal U0_n_46 : STD_LOGIC;
signal U0_n_47 : STD_LOGIC;
signal U0_n_48 : STD_LOGIC;
signal U0_n_49 : STD_LOGIC;
signal U0_n_5 : STD_LOGIC;
signal U0_n_50 : STD_LOGIC;
signal U0_n_51 : STD_LOGIC;
signal U0_n_52 : STD_LOGIC;
signal U0_n_53 : STD_LOGIC;
signal U0_n_54 : STD_LOGIC;
signal U0_n_55 : STD_LOGIC;
signal U0_n_56 : STD_LOGIC;
signal U0_n_57 : STD_LOGIC;
signal U0_n_58 : STD_LOGIC;
signal U0_n_59 : STD_LOGIC;
signal U0_n_6 : STD_LOGIC;
signal U0_n_60 : STD_LOGIC;
signal U0_n_61 : STD_LOGIC;
signal U0_n_62 : STD_LOGIC;
signal U0_n_63 : STD_LOGIC;
signal U0_n_64 : STD_LOGIC;
signal U0_n_65 : STD_LOGIC;
signal U0_n_66 : STD_LOGIC;
signal U0_n_67 : STD_LOGIC;
signal U0_n_68 : STD_LOGIC;
signal U0_n_69 : STD_LOGIC;
signal U0_n_7 : STD_LOGIC;
signal U0_n_70 : STD_LOGIC;
signal U0_n_71 : STD_LOGIC;
signal U0_n_72 : STD_LOGIC;
signal U0_n_73 : STD_LOGIC;
signal U0_n_74 : STD_LOGIC;
signal U0_n_75 : STD_LOGIC;
signal U0_n_76 : STD_LOGIC;
signal U0_n_77 : STD_LOGIC;
signal U0_n_78 : STD_LOGIC;
signal U0_n_79 : STD_LOGIC;
signal U0_n_8 : STD_LOGIC;
signal U0_n_80 : STD_LOGIC;
signal U0_n_81 : STD_LOGIC;
signal U0_n_9 : STD_LOGIC;
signal \cb_int[15]_i_35_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_36_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_37_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_38_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_39_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_40_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_41_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_42_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_47_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_48_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_49_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_50_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_38_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_39_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_40_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_41_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_42_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_43_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_44_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_45_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_33_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_34_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_35_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_36_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_37_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_38_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_39_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_40_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_100_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_101_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_18_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_19_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_20_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_21_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_22_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_25_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_26_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_28_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_29_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_45_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_46_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_47_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_48_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_49_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_50_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_52_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_53_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_54_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_55_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_56_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_57_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_58_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_59_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_60_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_62_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_63_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_64_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_65_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_83_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_84_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_88_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_89_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_90_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_91_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_92_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_93_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_94_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_99_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_35_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_36_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_37_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_38_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_39_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_40_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_41_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_42_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_59_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_60_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_61_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_62_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_73_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_74_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_84_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_85_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_86_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_87_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_88_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_95_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_96_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_97_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_98_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_30_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_31_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_32_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_33_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_34_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_35_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_36_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_37_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_43_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_44_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_45_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_46_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_47_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_48_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_49_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_50_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_51_n_0\ : STD_LOGIC;
signal \cb_int_reg[15]_i_31_n_0\ : STD_LOGIC;
signal \cb_int_reg[15]_i_31_n_1\ : STD_LOGIC;
signal \cb_int_reg[15]_i_31_n_2\ : STD_LOGIC;
signal \cb_int_reg[15]_i_31_n_3\ : STD_LOGIC;
signal \cb_int_reg[15]_i_31_n_4\ : STD_LOGIC;
signal \cb_int_reg[15]_i_31_n_5\ : STD_LOGIC;
signal \cb_int_reg[15]_i_31_n_6\ : STD_LOGIC;
signal \cb_int_reg[15]_i_31_n_7\ : STD_LOGIC;
signal \cb_int_reg[15]_i_32_n_0\ : STD_LOGIC;
signal \cb_int_reg[15]_i_32_n_1\ : STD_LOGIC;
signal \cb_int_reg[15]_i_32_n_2\ : STD_LOGIC;
signal \cb_int_reg[15]_i_32_n_3\ : STD_LOGIC;
signal \cb_int_reg[15]_i_32_n_4\ : STD_LOGIC;
signal \cb_int_reg[15]_i_32_n_5\ : STD_LOGIC;
signal \cb_int_reg[15]_i_32_n_6\ : STD_LOGIC;
signal \cb_int_reg[15]_i_32_n_7\ : STD_LOGIC;
signal \cb_int_reg[15]_i_34_n_0\ : STD_LOGIC;
signal \cb_int_reg[15]_i_34_n_1\ : STD_LOGIC;
signal \cb_int_reg[15]_i_34_n_2\ : STD_LOGIC;
signal \cb_int_reg[15]_i_34_n_3\ : STD_LOGIC;
signal \cb_int_reg[15]_i_34_n_4\ : STD_LOGIC;
signal \cb_int_reg[15]_i_34_n_5\ : STD_LOGIC;
signal \cb_int_reg[15]_i_34_n_6\ : STD_LOGIC;
signal \cb_int_reg[15]_i_34_n_7\ : STD_LOGIC;
signal \cb_int_reg[19]_i_32_n_0\ : STD_LOGIC;
signal \cb_int_reg[19]_i_32_n_1\ : STD_LOGIC;
signal \cb_int_reg[19]_i_32_n_2\ : STD_LOGIC;
signal \cb_int_reg[19]_i_32_n_3\ : STD_LOGIC;
signal \cb_int_reg[19]_i_32_n_4\ : STD_LOGIC;
signal \cb_int_reg[19]_i_32_n_5\ : STD_LOGIC;
signal \cb_int_reg[19]_i_32_n_6\ : STD_LOGIC;
signal \cb_int_reg[19]_i_32_n_7\ : STD_LOGIC;
signal \cb_int_reg[19]_i_33_n_0\ : STD_LOGIC;
signal \cb_int_reg[19]_i_33_n_1\ : STD_LOGIC;
signal \cb_int_reg[19]_i_33_n_2\ : STD_LOGIC;
signal \cb_int_reg[19]_i_33_n_3\ : STD_LOGIC;
signal \cb_int_reg[19]_i_33_n_4\ : STD_LOGIC;
signal \cb_int_reg[19]_i_33_n_5\ : STD_LOGIC;
signal \cb_int_reg[19]_i_33_n_6\ : STD_LOGIC;
signal \cb_int_reg[19]_i_33_n_7\ : STD_LOGIC;
signal \cb_int_reg[23]_i_27_n_0\ : STD_LOGIC;
signal \cb_int_reg[23]_i_27_n_1\ : STD_LOGIC;
signal \cb_int_reg[23]_i_27_n_2\ : STD_LOGIC;
signal \cb_int_reg[23]_i_27_n_3\ : STD_LOGIC;
signal \cb_int_reg[23]_i_27_n_4\ : STD_LOGIC;
signal \cb_int_reg[23]_i_27_n_5\ : STD_LOGIC;
signal \cb_int_reg[23]_i_27_n_6\ : STD_LOGIC;
signal \cb_int_reg[23]_i_27_n_7\ : STD_LOGIC;
signal \cb_int_reg[23]_i_28_n_0\ : STD_LOGIC;
signal \cb_int_reg[23]_i_28_n_1\ : STD_LOGIC;
signal \cb_int_reg[23]_i_28_n_2\ : STD_LOGIC;
signal \cb_int_reg[23]_i_28_n_3\ : STD_LOGIC;
signal \cb_int_reg[23]_i_28_n_4\ : STD_LOGIC;
signal \cb_int_reg[23]_i_28_n_5\ : STD_LOGIC;
signal \cb_int_reg[23]_i_28_n_6\ : STD_LOGIC;
signal \cb_int_reg[23]_i_28_n_7\ : STD_LOGIC;
signal \cb_int_reg[31]_i_10_n_1\ : STD_LOGIC;
signal \cb_int_reg[31]_i_10_n_3\ : STD_LOGIC;
signal \cb_int_reg[31]_i_10_n_6\ : STD_LOGIC;
signal \cb_int_reg[31]_i_10_n_7\ : STD_LOGIC;
signal \cb_int_reg[31]_i_17_n_0\ : STD_LOGIC;
signal \cb_int_reg[31]_i_17_n_1\ : STD_LOGIC;
signal \cb_int_reg[31]_i_17_n_2\ : STD_LOGIC;
signal \cb_int_reg[31]_i_17_n_3\ : STD_LOGIC;
signal \cb_int_reg[31]_i_17_n_4\ : STD_LOGIC;
signal \cb_int_reg[31]_i_17_n_5\ : STD_LOGIC;
signal \cb_int_reg[31]_i_17_n_6\ : STD_LOGIC;
signal \cb_int_reg[31]_i_17_n_7\ : STD_LOGIC;
signal \cb_int_reg[31]_i_23_n_0\ : STD_LOGIC;
signal \cb_int_reg[31]_i_23_n_1\ : STD_LOGIC;
signal \cb_int_reg[31]_i_23_n_2\ : STD_LOGIC;
signal \cb_int_reg[31]_i_23_n_3\ : STD_LOGIC;
signal \cb_int_reg[31]_i_23_n_4\ : STD_LOGIC;
signal \cb_int_reg[31]_i_23_n_5\ : STD_LOGIC;
signal \cb_int_reg[31]_i_23_n_6\ : STD_LOGIC;
signal \cb_int_reg[31]_i_23_n_7\ : STD_LOGIC;
signal \cb_int_reg[31]_i_27_n_0\ : STD_LOGIC;
signal \cb_int_reg[31]_i_27_n_1\ : STD_LOGIC;
signal \cb_int_reg[31]_i_27_n_2\ : STD_LOGIC;
signal \cb_int_reg[31]_i_27_n_3\ : STD_LOGIC;
signal \cb_int_reg[31]_i_27_n_4\ : STD_LOGIC;
signal \cb_int_reg[31]_i_27_n_5\ : STD_LOGIC;
signal \cb_int_reg[31]_i_27_n_6\ : STD_LOGIC;
signal \cb_int_reg[31]_i_27_n_7\ : STD_LOGIC;
signal \cb_int_reg[31]_i_42_n_3\ : STD_LOGIC;
signal \cb_int_reg[31]_i_42_n_6\ : STD_LOGIC;
signal \cb_int_reg[31]_i_42_n_7\ : STD_LOGIC;
signal \cb_int_reg[31]_i_61_n_0\ : STD_LOGIC;
signal \cb_int_reg[31]_i_61_n_1\ : STD_LOGIC;
signal \cb_int_reg[31]_i_61_n_2\ : STD_LOGIC;
signal \cb_int_reg[31]_i_61_n_3\ : STD_LOGIC;
signal \cb_int_reg[31]_i_61_n_4\ : STD_LOGIC;
signal \cb_int_reg[31]_i_61_n_5\ : STD_LOGIC;
signal \cb_int_reg[31]_i_61_n_6\ : STD_LOGIC;
signal \cb_int_reg[31]_i_61_n_7\ : STD_LOGIC;
signal \cb_int_reg[31]_i_66_n_3\ : STD_LOGIC;
signal \cb_int_reg[31]_i_66_n_6\ : STD_LOGIC;
signal \cb_int_reg[31]_i_66_n_7\ : STD_LOGIC;
signal \cb_int_reg[31]_i_85_n_0\ : STD_LOGIC;
signal \cb_int_reg[31]_i_85_n_2\ : STD_LOGIC;
signal \cb_int_reg[31]_i_85_n_3\ : STD_LOGIC;
signal \cb_int_reg[31]_i_85_n_5\ : STD_LOGIC;
signal \cb_int_reg[31]_i_85_n_6\ : STD_LOGIC;
signal \cb_int_reg[31]_i_85_n_7\ : STD_LOGIC;
signal \cb_int_reg[31]_i_8_n_1\ : STD_LOGIC;
signal \cb_int_reg[31]_i_8_n_2\ : STD_LOGIC;
signal \cb_int_reg[31]_i_8_n_3\ : STD_LOGIC;
signal \cb_int_reg[31]_i_8_n_4\ : STD_LOGIC;
signal \cb_int_reg[31]_i_8_n_5\ : STD_LOGIC;
signal \cb_int_reg[31]_i_8_n_6\ : STD_LOGIC;
signal \cb_int_reg[31]_i_8_n_7\ : STD_LOGIC;
signal \cb_int_reg[31]_i_9_n_3\ : STD_LOGIC;
signal \cb_int_reg[31]_i_9_n_6\ : STD_LOGIC;
signal \cb_int_reg[31]_i_9_n_7\ : STD_LOGIC;
signal \cb_int_reg[3]_i_19_n_0\ : STD_LOGIC;
signal \cb_int_reg[3]_i_19_n_1\ : STD_LOGIC;
signal \cb_int_reg[3]_i_19_n_2\ : STD_LOGIC;
signal \cb_int_reg[3]_i_19_n_3\ : STD_LOGIC;
signal \cb_int_reg[3]_i_19_n_4\ : STD_LOGIC;
signal \cb_int_reg[3]_i_19_n_5\ : STD_LOGIC;
signal \cb_int_reg[3]_i_19_n_6\ : STD_LOGIC;
signal \cb_int_reg[3]_i_19_n_7\ : STD_LOGIC;
signal \cb_int_reg[3]_i_32_n_0\ : STD_LOGIC;
signal \cb_int_reg[3]_i_32_n_1\ : STD_LOGIC;
signal \cb_int_reg[3]_i_32_n_2\ : STD_LOGIC;
signal \cb_int_reg[3]_i_32_n_3\ : STD_LOGIC;
signal \cb_int_reg[3]_i_32_n_4\ : STD_LOGIC;
signal \cb_int_reg[3]_i_43_n_1\ : STD_LOGIC;
signal \cb_int_reg[3]_i_43_n_3\ : STD_LOGIC;
signal \cb_int_reg[3]_i_43_n_6\ : STD_LOGIC;
signal \cb_int_reg[3]_i_43_n_7\ : STD_LOGIC;
signal \cb_int_reg[3]_i_58_n_0\ : STD_LOGIC;
signal \cb_int_reg[3]_i_58_n_1\ : STD_LOGIC;
signal \cb_int_reg[3]_i_58_n_2\ : STD_LOGIC;
signal \cb_int_reg[3]_i_58_n_3\ : STD_LOGIC;
signal \cb_int_reg[3]_i_68_n_0\ : STD_LOGIC;
signal \cb_int_reg[3]_i_68_n_1\ : STD_LOGIC;
signal \cb_int_reg[3]_i_68_n_2\ : STD_LOGIC;
signal \cb_int_reg[3]_i_68_n_3\ : STD_LOGIC;
signal \cb_int_reg[3]_i_68_n_4\ : STD_LOGIC;
signal \cb_int_reg[3]_i_68_n_5\ : STD_LOGIC;
signal \cb_int_reg[3]_i_68_n_6\ : STD_LOGIC;
signal \cb_int_reg[3]_i_68_n_7\ : STD_LOGIC;
signal \cb_int_reg[7]_i_23_n_0\ : STD_LOGIC;
signal \cb_int_reg[7]_i_23_n_1\ : STD_LOGIC;
signal \cb_int_reg[7]_i_23_n_2\ : STD_LOGIC;
signal \cb_int_reg[7]_i_23_n_3\ : STD_LOGIC;
signal \cb_int_reg[7]_i_23_n_4\ : STD_LOGIC;
signal \cb_int_reg[7]_i_23_n_5\ : STD_LOGIC;
signal \cb_int_reg[7]_i_23_n_6\ : STD_LOGIC;
signal \cb_int_reg[7]_i_23_n_7\ : STD_LOGIC;
signal \cb_int_reg[7]_i_24_n_0\ : STD_LOGIC;
signal \cb_int_reg[7]_i_24_n_1\ : STD_LOGIC;
signal \cb_int_reg[7]_i_24_n_2\ : STD_LOGIC;
signal \cb_int_reg[7]_i_24_n_3\ : STD_LOGIC;
signal \cb_int_reg[7]_i_24_n_4\ : STD_LOGIC;
signal \cb_int_reg[7]_i_24_n_5\ : STD_LOGIC;
signal \cb_int_reg[7]_i_24_n_6\ : STD_LOGIC;
signal \cb_int_reg[7]_i_24_n_7\ : STD_LOGIC;
signal \cb_int_reg[7]_i_26_n_0\ : STD_LOGIC;
signal \cb_int_reg[7]_i_26_n_1\ : STD_LOGIC;
signal \cb_int_reg[7]_i_26_n_2\ : STD_LOGIC;
signal \cb_int_reg[7]_i_26_n_3\ : STD_LOGIC;
signal \cb_int_reg[7]_i_26_n_4\ : STD_LOGIC;
signal \cb_int_reg[7]_i_26_n_5\ : STD_LOGIC;
signal \cb_int_reg[7]_i_26_n_6\ : STD_LOGIC;
signal \cb_int_reg[7]_i_26_n_7\ : STD_LOGIC;
signal \cb_int_reg[7]_i_27_n_0\ : STD_LOGIC;
signal \cb_int_reg[7]_i_27_n_1\ : STD_LOGIC;
signal \cb_int_reg[7]_i_27_n_2\ : STD_LOGIC;
signal \cb_int_reg[7]_i_27_n_3\ : STD_LOGIC;
signal \cb_int_reg[7]_i_27_n_4\ : STD_LOGIC;
signal \cb_int_reg[7]_i_27_n_5\ : STD_LOGIC;
signal \cb_int_reg[7]_i_27_n_6\ : STD_LOGIC;
signal \cb_int_reg[7]_i_27_n_7\ : STD_LOGIC;
signal \cr_int[11]_i_61_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_62_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_63_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_64_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_44_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_45_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_46_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_47_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_52_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_53_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_54_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_55_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_42_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_43_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_44_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_45_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_32_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_33_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_34_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_35_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_104_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_105_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_106_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_107_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_28_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_29_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_65_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_66_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_67_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_68_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_98_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_99_n_0\ : STD_LOGIC;
signal \cr_int[7]_i_29_n_0\ : STD_LOGIC;
signal \cr_int[7]_i_30_n_0\ : STD_LOGIC;
signal \cr_int[7]_i_31_n_0\ : STD_LOGIC;
signal \cr_int[7]_i_32_n_0\ : STD_LOGIC;
signal \cr_int[7]_i_33_n_0\ : STD_LOGIC;
signal \cr_int_reg[11]_i_28_n_0\ : STD_LOGIC;
signal \cr_int_reg[11]_i_28_n_1\ : STD_LOGIC;
signal \cr_int_reg[11]_i_28_n_2\ : STD_LOGIC;
signal \cr_int_reg[11]_i_28_n_3\ : STD_LOGIC;
signal \cr_int_reg[11]_i_28_n_4\ : STD_LOGIC;
signal \cr_int_reg[11]_i_28_n_5\ : STD_LOGIC;
signal \cr_int_reg[11]_i_28_n_6\ : STD_LOGIC;
signal \cr_int_reg[11]_i_28_n_7\ : STD_LOGIC;
signal \cr_int_reg[15]_i_37_n_0\ : STD_LOGIC;
signal \cr_int_reg[15]_i_37_n_1\ : STD_LOGIC;
signal \cr_int_reg[15]_i_37_n_2\ : STD_LOGIC;
signal \cr_int_reg[15]_i_37_n_3\ : STD_LOGIC;
signal \cr_int_reg[15]_i_37_n_4\ : STD_LOGIC;
signal \cr_int_reg[15]_i_37_n_5\ : STD_LOGIC;
signal \cr_int_reg[15]_i_37_n_6\ : STD_LOGIC;
signal \cr_int_reg[15]_i_37_n_7\ : STD_LOGIC;
signal \cr_int_reg[15]_i_39_n_0\ : STD_LOGIC;
signal \cr_int_reg[15]_i_39_n_1\ : STD_LOGIC;
signal \cr_int_reg[15]_i_39_n_2\ : STD_LOGIC;
signal \cr_int_reg[15]_i_39_n_3\ : STD_LOGIC;
signal \cr_int_reg[15]_i_39_n_4\ : STD_LOGIC;
signal \cr_int_reg[15]_i_39_n_5\ : STD_LOGIC;
signal \cr_int_reg[15]_i_39_n_6\ : STD_LOGIC;
signal \cr_int_reg[15]_i_39_n_7\ : STD_LOGIC;
signal \cr_int_reg[19]_i_37_n_0\ : STD_LOGIC;
signal \cr_int_reg[19]_i_37_n_1\ : STD_LOGIC;
signal \cr_int_reg[19]_i_37_n_2\ : STD_LOGIC;
signal \cr_int_reg[19]_i_37_n_3\ : STD_LOGIC;
signal \cr_int_reg[19]_i_37_n_4\ : STD_LOGIC;
signal \cr_int_reg[19]_i_37_n_5\ : STD_LOGIC;
signal \cr_int_reg[19]_i_37_n_6\ : STD_LOGIC;
signal \cr_int_reg[19]_i_37_n_7\ : STD_LOGIC;
signal \cr_int_reg[23]_i_31_n_0\ : STD_LOGIC;
signal \cr_int_reg[23]_i_31_n_1\ : STD_LOGIC;
signal \cr_int_reg[23]_i_31_n_2\ : STD_LOGIC;
signal \cr_int_reg[23]_i_31_n_3\ : STD_LOGIC;
signal \cr_int_reg[23]_i_31_n_4\ : STD_LOGIC;
signal \cr_int_reg[23]_i_31_n_5\ : STD_LOGIC;
signal \cr_int_reg[23]_i_31_n_6\ : STD_LOGIC;
signal \cr_int_reg[23]_i_31_n_7\ : STD_LOGIC;
signal \cr_int_reg[31]_i_10_n_1\ : STD_LOGIC;
signal \cr_int_reg[31]_i_10_n_3\ : STD_LOGIC;
signal \cr_int_reg[31]_i_10_n_6\ : STD_LOGIC;
signal \cr_int_reg[31]_i_10_n_7\ : STD_LOGIC;
signal \cr_int_reg[31]_i_27_n_0\ : STD_LOGIC;
signal \cr_int_reg[31]_i_27_n_1\ : STD_LOGIC;
signal \cr_int_reg[31]_i_27_n_2\ : STD_LOGIC;
signal \cr_int_reg[31]_i_27_n_3\ : STD_LOGIC;
signal \cr_int_reg[31]_i_27_n_4\ : STD_LOGIC;
signal \cr_int_reg[31]_i_27_n_5\ : STD_LOGIC;
signal \cr_int_reg[31]_i_27_n_6\ : STD_LOGIC;
signal \cr_int_reg[31]_i_27_n_7\ : STD_LOGIC;
signal \cr_int_reg[31]_i_54_n_3\ : STD_LOGIC;
signal \cr_int_reg[31]_i_54_n_6\ : STD_LOGIC;
signal \cr_int_reg[31]_i_54_n_7\ : STD_LOGIC;
signal \cr_int_reg[31]_i_64_n_0\ : STD_LOGIC;
signal \cr_int_reg[31]_i_64_n_1\ : STD_LOGIC;
signal \cr_int_reg[31]_i_64_n_2\ : STD_LOGIC;
signal \cr_int_reg[31]_i_64_n_3\ : STD_LOGIC;
signal \cr_int_reg[31]_i_64_n_4\ : STD_LOGIC;
signal \cr_int_reg[31]_i_64_n_5\ : STD_LOGIC;
signal \cr_int_reg[31]_i_64_n_6\ : STD_LOGIC;
signal \cr_int_reg[31]_i_64_n_7\ : STD_LOGIC;
signal \cr_int_reg[7]_i_24_n_0\ : STD_LOGIC;
signal \cr_int_reg[7]_i_24_n_1\ : STD_LOGIC;
signal \cr_int_reg[7]_i_24_n_2\ : STD_LOGIC;
signal \cr_int_reg[7]_i_24_n_3\ : STD_LOGIC;
signal \cr_int_reg[7]_i_24_n_4\ : STD_LOGIC;
signal \cr_int_reg[7]_i_24_n_5\ : STD_LOGIC;
signal \cr_int_reg[7]_i_24_n_6\ : STD_LOGIC;
signal \cr_int_reg[7]_i_24_n_7\ : STD_LOGIC;
signal \^hdmi_d\ : STD_LOGIC_VECTOR ( 15 downto 8 );
signal \y_int[11]_i_54_n_0\ : STD_LOGIC;
signal \y_int[11]_i_55_n_0\ : STD_LOGIC;
signal \y_int[11]_i_56_n_0\ : STD_LOGIC;
signal \y_int[11]_i_57_n_0\ : STD_LOGIC;
signal \y_int[15]_i_36_n_0\ : STD_LOGIC;
signal \y_int[15]_i_37_n_0\ : STD_LOGIC;
signal \y_int[15]_i_38_n_0\ : STD_LOGIC;
signal \y_int[15]_i_39_n_0\ : STD_LOGIC;
signal \y_int[15]_i_44_n_0\ : STD_LOGIC;
signal \y_int[15]_i_45_n_0\ : STD_LOGIC;
signal \y_int[15]_i_46_n_0\ : STD_LOGIC;
signal \y_int[15]_i_47_n_0\ : STD_LOGIC;
signal \y_int[19]_i_36_n_0\ : STD_LOGIC;
signal \y_int[19]_i_37_n_0\ : STD_LOGIC;
signal \y_int[19]_i_38_n_0\ : STD_LOGIC;
signal \y_int[19]_i_39_n_0\ : STD_LOGIC;
signal \y_int[19]_i_40_n_0\ : STD_LOGIC;
signal \y_int[19]_i_41_n_0\ : STD_LOGIC;
signal \y_int[19]_i_42_n_0\ : STD_LOGIC;
signal \y_int[19]_i_43_n_0\ : STD_LOGIC;
signal \y_int[19]_i_44_n_0\ : STD_LOGIC;
signal \y_int[19]_i_45_n_0\ : STD_LOGIC;
signal \y_int[19]_i_46_n_0\ : STD_LOGIC;
signal \y_int[19]_i_47_n_0\ : STD_LOGIC;
signal \y_int[23]_i_50_n_0\ : STD_LOGIC;
signal \y_int[23]_i_58_n_0\ : STD_LOGIC;
signal \y_int[23]_i_59_n_0\ : STD_LOGIC;
signal \y_int[23]_i_60_n_0\ : STD_LOGIC;
signal \y_int[23]_i_61_n_0\ : STD_LOGIC;
signal \y_int[31]_i_100_n_0\ : STD_LOGIC;
signal \y_int[31]_i_102_n_0\ : STD_LOGIC;
signal \y_int[31]_i_103_n_0\ : STD_LOGIC;
signal \y_int[31]_i_22_n_0\ : STD_LOGIC;
signal \y_int[31]_i_23_n_0\ : STD_LOGIC;
signal \y_int[31]_i_24_n_0\ : STD_LOGIC;
signal \y_int[31]_i_25_n_0\ : STD_LOGIC;
signal \y_int[31]_i_26_n_0\ : STD_LOGIC;
signal \y_int[31]_i_28_n_0\ : STD_LOGIC;
signal \y_int[31]_i_29_n_0\ : STD_LOGIC;
signal \y_int[31]_i_38_n_0\ : STD_LOGIC;
signal \y_int[31]_i_39_n_0\ : STD_LOGIC;
signal \y_int[31]_i_48_n_0\ : STD_LOGIC;
signal \y_int[31]_i_49_n_0\ : STD_LOGIC;
signal \y_int[31]_i_50_n_0\ : STD_LOGIC;
signal \y_int[31]_i_51_n_0\ : STD_LOGIC;
signal \y_int[31]_i_52_n_0\ : STD_LOGIC;
signal \y_int[31]_i_53_n_0\ : STD_LOGIC;
signal \y_int[31]_i_54_n_0\ : STD_LOGIC;
signal \y_int[31]_i_55_n_0\ : STD_LOGIC;
signal \y_int[31]_i_56_n_0\ : STD_LOGIC;
signal \y_int[31]_i_57_n_0\ : STD_LOGIC;
signal \y_int[31]_i_58_n_0\ : STD_LOGIC;
signal \y_int[31]_i_59_n_0\ : STD_LOGIC;
signal \y_int[31]_i_60_n_0\ : STD_LOGIC;
signal \y_int[31]_i_61_n_0\ : STD_LOGIC;
signal \y_int[31]_i_72_n_0\ : STD_LOGIC;
signal \y_int[31]_i_73_n_0\ : STD_LOGIC;
signal \y_int[31]_i_74_n_0\ : STD_LOGIC;
signal \y_int[31]_i_76_n_0\ : STD_LOGIC;
signal \y_int[31]_i_77_n_0\ : STD_LOGIC;
signal \y_int[31]_i_78_n_0\ : STD_LOGIC;
signal \y_int[31]_i_79_n_0\ : STD_LOGIC;
signal \y_int[31]_i_80_n_0\ : STD_LOGIC;
signal \y_int[31]_i_81_n_0\ : STD_LOGIC;
signal \y_int[31]_i_83_n_0\ : STD_LOGIC;
signal \y_int[31]_i_84_n_0\ : STD_LOGIC;
signal \y_int[31]_i_85_n_0\ : STD_LOGIC;
signal \y_int[31]_i_93_n_0\ : STD_LOGIC;
signal \y_int[31]_i_94_n_0\ : STD_LOGIC;
signal \y_int[31]_i_95_n_0\ : STD_LOGIC;
signal \y_int[31]_i_96_n_0\ : STD_LOGIC;
signal \y_int[31]_i_97_n_0\ : STD_LOGIC;
signal \y_int[31]_i_98_n_0\ : STD_LOGIC;
signal \y_int[31]_i_99_n_0\ : STD_LOGIC;
signal \y_int[3]_i_37_n_0\ : STD_LOGIC;
signal \y_int[3]_i_38_n_0\ : STD_LOGIC;
signal \y_int[3]_i_39_n_0\ : STD_LOGIC;
signal \y_int[3]_i_41_n_0\ : STD_LOGIC;
signal \y_int[3]_i_42_n_0\ : STD_LOGIC;
signal \y_int[3]_i_43_n_0\ : STD_LOGIC;
signal \y_int[3]_i_44_n_0\ : STD_LOGIC;
signal \y_int[3]_i_46_n_0\ : STD_LOGIC;
signal \y_int[3]_i_47_n_0\ : STD_LOGIC;
signal \y_int[3]_i_48_n_0\ : STD_LOGIC;
signal \y_int[3]_i_49_n_0\ : STD_LOGIC;
signal \y_int[3]_i_75_n_0\ : STD_LOGIC;
signal \y_int[3]_i_76_n_0\ : STD_LOGIC;
signal \y_int[3]_i_77_n_0\ : STD_LOGIC;
signal \y_int[3]_i_78_n_0\ : STD_LOGIC;
signal \y_int[3]_i_79_n_0\ : STD_LOGIC;
signal \y_int[3]_i_80_n_0\ : STD_LOGIC;
signal \y_int[3]_i_81_n_0\ : STD_LOGIC;
signal \y_int[3]_i_82_n_0\ : STD_LOGIC;
signal \y_int[3]_i_83_n_0\ : STD_LOGIC;
signal \y_int[3]_i_93_n_0\ : STD_LOGIC;
signal \y_int[3]_i_94_n_0\ : STD_LOGIC;
signal \y_int[3]_i_95_n_0\ : STD_LOGIC;
signal \y_int[3]_i_96_n_0\ : STD_LOGIC;
signal \y_int[7]_i_25_n_0\ : STD_LOGIC;
signal \y_int[7]_i_26_n_0\ : STD_LOGIC;
signal \y_int[7]_i_27_n_0\ : STD_LOGIC;
signal \y_int[7]_i_28_n_0\ : STD_LOGIC;
signal y_int_reg2 : STD_LOGIC_VECTOR ( 22 downto 9 );
signal \y_int_reg[11]_i_27_n_0\ : STD_LOGIC;
signal \y_int_reg[11]_i_27_n_1\ : STD_LOGIC;
signal \y_int_reg[11]_i_27_n_2\ : STD_LOGIC;
signal \y_int_reg[11]_i_27_n_3\ : STD_LOGIC;
signal \y_int_reg[11]_i_27_n_4\ : STD_LOGIC;
signal \y_int_reg[11]_i_27_n_5\ : STD_LOGIC;
signal \y_int_reg[11]_i_27_n_6\ : STD_LOGIC;
signal \y_int_reg[11]_i_27_n_7\ : STD_LOGIC;
signal \y_int_reg[15]_i_24_n_0\ : STD_LOGIC;
signal \y_int_reg[15]_i_24_n_1\ : STD_LOGIC;
signal \y_int_reg[15]_i_24_n_2\ : STD_LOGIC;
signal \y_int_reg[15]_i_24_n_3\ : STD_LOGIC;
signal \y_int_reg[15]_i_24_n_4\ : STD_LOGIC;
signal \y_int_reg[15]_i_24_n_5\ : STD_LOGIC;
signal \y_int_reg[15]_i_24_n_6\ : STD_LOGIC;
signal \y_int_reg[15]_i_24_n_7\ : STD_LOGIC;
signal \y_int_reg[15]_i_34_n_0\ : STD_LOGIC;
signal \y_int_reg[15]_i_34_n_1\ : STD_LOGIC;
signal \y_int_reg[15]_i_34_n_2\ : STD_LOGIC;
signal \y_int_reg[15]_i_34_n_3\ : STD_LOGIC;
signal \y_int_reg[19]_i_24_n_0\ : STD_LOGIC;
signal \y_int_reg[19]_i_24_n_1\ : STD_LOGIC;
signal \y_int_reg[19]_i_24_n_2\ : STD_LOGIC;
signal \y_int_reg[19]_i_24_n_3\ : STD_LOGIC;
signal \y_int_reg[19]_i_24_n_4\ : STD_LOGIC;
signal \y_int_reg[19]_i_24_n_5\ : STD_LOGIC;
signal \y_int_reg[19]_i_24_n_6\ : STD_LOGIC;
signal \y_int_reg[19]_i_24_n_7\ : STD_LOGIC;
signal \y_int_reg[19]_i_33_n_0\ : STD_LOGIC;
signal \y_int_reg[19]_i_33_n_1\ : STD_LOGIC;
signal \y_int_reg[19]_i_33_n_2\ : STD_LOGIC;
signal \y_int_reg[19]_i_33_n_3\ : STD_LOGIC;
signal \y_int_reg[19]_i_33_n_4\ : STD_LOGIC;
signal \y_int_reg[19]_i_33_n_5\ : STD_LOGIC;
signal \y_int_reg[19]_i_33_n_6\ : STD_LOGIC;
signal \y_int_reg[19]_i_33_n_7\ : STD_LOGIC;
signal \y_int_reg[19]_i_34_n_0\ : STD_LOGIC;
signal \y_int_reg[19]_i_34_n_1\ : STD_LOGIC;
signal \y_int_reg[19]_i_34_n_2\ : STD_LOGIC;
signal \y_int_reg[19]_i_34_n_3\ : STD_LOGIC;
signal \y_int_reg[23]_i_32_n_7\ : STD_LOGIC;
signal \y_int_reg[23]_i_35_n_0\ : STD_LOGIC;
signal \y_int_reg[23]_i_35_n_1\ : STD_LOGIC;
signal \y_int_reg[23]_i_35_n_2\ : STD_LOGIC;
signal \y_int_reg[23]_i_35_n_3\ : STD_LOGIC;
signal \y_int_reg[23]_i_35_n_4\ : STD_LOGIC;
signal \y_int_reg[23]_i_35_n_5\ : STD_LOGIC;
signal \y_int_reg[23]_i_35_n_6\ : STD_LOGIC;
signal \y_int_reg[23]_i_35_n_7\ : STD_LOGIC;
signal \y_int_reg[31]_i_10_n_1\ : STD_LOGIC;
signal \y_int_reg[31]_i_10_n_3\ : STD_LOGIC;
signal \y_int_reg[31]_i_10_n_6\ : STD_LOGIC;
signal \y_int_reg[31]_i_10_n_7\ : STD_LOGIC;
signal \y_int_reg[31]_i_12_n_1\ : STD_LOGIC;
signal \y_int_reg[31]_i_12_n_3\ : STD_LOGIC;
signal \y_int_reg[31]_i_21_n_0\ : STD_LOGIC;
signal \y_int_reg[31]_i_21_n_1\ : STD_LOGIC;
signal \y_int_reg[31]_i_21_n_2\ : STD_LOGIC;
signal \y_int_reg[31]_i_21_n_3\ : STD_LOGIC;
signal \y_int_reg[31]_i_21_n_4\ : STD_LOGIC;
signal \y_int_reg[31]_i_21_n_5\ : STD_LOGIC;
signal \y_int_reg[31]_i_21_n_6\ : STD_LOGIC;
signal \y_int_reg[31]_i_21_n_7\ : STD_LOGIC;
signal \y_int_reg[31]_i_27_n_0\ : STD_LOGIC;
signal \y_int_reg[31]_i_27_n_1\ : STD_LOGIC;
signal \y_int_reg[31]_i_27_n_2\ : STD_LOGIC;
signal \y_int_reg[31]_i_27_n_3\ : STD_LOGIC;
signal \y_int_reg[31]_i_27_n_4\ : STD_LOGIC;
signal \y_int_reg[31]_i_27_n_5\ : STD_LOGIC;
signal \y_int_reg[31]_i_27_n_6\ : STD_LOGIC;
signal \y_int_reg[31]_i_27_n_7\ : STD_LOGIC;
signal \y_int_reg[31]_i_31_n_2\ : STD_LOGIC;
signal \y_int_reg[31]_i_31_n_3\ : STD_LOGIC;
signal \y_int_reg[31]_i_31_n_5\ : STD_LOGIC;
signal \y_int_reg[31]_i_31_n_6\ : STD_LOGIC;
signal \y_int_reg[31]_i_31_n_7\ : STD_LOGIC;
signal \y_int_reg[31]_i_37_n_0\ : STD_LOGIC;
signal \y_int_reg[31]_i_37_n_1\ : STD_LOGIC;
signal \y_int_reg[31]_i_37_n_2\ : STD_LOGIC;
signal \y_int_reg[31]_i_37_n_3\ : STD_LOGIC;
signal \y_int_reg[31]_i_71_n_0\ : STD_LOGIC;
signal \y_int_reg[31]_i_71_n_1\ : STD_LOGIC;
signal \y_int_reg[31]_i_71_n_2\ : STD_LOGIC;
signal \y_int_reg[31]_i_71_n_3\ : STD_LOGIC;
signal \y_int_reg[31]_i_71_n_4\ : STD_LOGIC;
signal \y_int_reg[31]_i_71_n_5\ : STD_LOGIC;
signal \y_int_reg[31]_i_71_n_6\ : STD_LOGIC;
signal \y_int_reg[31]_i_71_n_7\ : STD_LOGIC;
signal \y_int_reg[31]_i_82_n_1\ : STD_LOGIC;
signal \y_int_reg[31]_i_82_n_3\ : STD_LOGIC;
signal \y_int_reg[31]_i_82_n_6\ : STD_LOGIC;
signal \y_int_reg[31]_i_82_n_7\ : STD_LOGIC;
signal \y_int_reg[31]_i_9_n_2\ : STD_LOGIC;
signal \y_int_reg[31]_i_9_n_3\ : STD_LOGIC;
signal \y_int_reg[31]_i_9_n_5\ : STD_LOGIC;
signal \y_int_reg[31]_i_9_n_6\ : STD_LOGIC;
signal \y_int_reg[31]_i_9_n_7\ : STD_LOGIC;
signal \y_int_reg[3]_i_19_n_0\ : STD_LOGIC;
signal \y_int_reg[3]_i_19_n_1\ : STD_LOGIC;
signal \y_int_reg[3]_i_19_n_2\ : STD_LOGIC;
signal \y_int_reg[3]_i_19_n_3\ : STD_LOGIC;
signal \y_int_reg[3]_i_19_n_4\ : STD_LOGIC;
signal \y_int_reg[3]_i_19_n_5\ : STD_LOGIC;
signal \y_int_reg[3]_i_19_n_6\ : STD_LOGIC;
signal \y_int_reg[3]_i_19_n_7\ : STD_LOGIC;
signal \y_int_reg[3]_i_20_n_0\ : STD_LOGIC;
signal \y_int_reg[3]_i_20_n_1\ : STD_LOGIC;
signal \y_int_reg[3]_i_20_n_2\ : STD_LOGIC;
signal \y_int_reg[3]_i_20_n_3\ : STD_LOGIC;
signal \y_int_reg[3]_i_20_n_4\ : STD_LOGIC;
signal \y_int_reg[3]_i_20_n_5\ : STD_LOGIC;
signal \y_int_reg[3]_i_40_n_0\ : STD_LOGIC;
signal \y_int_reg[3]_i_40_n_1\ : STD_LOGIC;
signal \y_int_reg[3]_i_40_n_2\ : STD_LOGIC;
signal \y_int_reg[3]_i_40_n_3\ : STD_LOGIC;
signal \y_int_reg[3]_i_40_n_4\ : STD_LOGIC;
signal \y_int_reg[3]_i_40_n_5\ : STD_LOGIC;
signal \y_int_reg[3]_i_40_n_6\ : STD_LOGIC;
signal \y_int_reg[3]_i_40_n_7\ : STD_LOGIC;
signal \y_int_reg[3]_i_45_n_0\ : STD_LOGIC;
signal \y_int_reg[3]_i_45_n_1\ : STD_LOGIC;
signal \y_int_reg[3]_i_45_n_2\ : STD_LOGIC;
signal \y_int_reg[3]_i_45_n_3\ : STD_LOGIC;
signal \y_int_reg[3]_i_70_n_0\ : STD_LOGIC;
signal \y_int_reg[3]_i_70_n_1\ : STD_LOGIC;
signal \y_int_reg[3]_i_70_n_2\ : STD_LOGIC;
signal \y_int_reg[3]_i_70_n_3\ : STD_LOGIC;
signal \y_int_reg[3]_i_70_n_4\ : STD_LOGIC;
signal \y_int_reg[3]_i_70_n_5\ : STD_LOGIC;
signal \y_int_reg[3]_i_70_n_6\ : STD_LOGIC;
signal \y_int_reg[7]_i_23_n_0\ : STD_LOGIC;
signal \y_int_reg[7]_i_23_n_1\ : STD_LOGIC;
signal \y_int_reg[7]_i_23_n_2\ : STD_LOGIC;
signal \y_int_reg[7]_i_23_n_3\ : STD_LOGIC;
signal \y_int_reg[7]_i_23_n_4\ : STD_LOGIC;
signal \y_int_reg[7]_i_23_n_5\ : STD_LOGIC;
signal \y_int_reg[7]_i_23_n_6\ : STD_LOGIC;
signal \y_int_reg[7]_i_23_n_7\ : STD_LOGIC;
signal \NLW_cb_int_reg[31]_i_10_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_cb_int_reg[31]_i_10_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_cb_int_reg[31]_i_42_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_cb_int_reg[31]_i_42_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_cb_int_reg[31]_i_66_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_cb_int_reg[31]_i_66_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_cb_int_reg[31]_i_8_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_cb_int_reg[31]_i_85_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 to 2 );
signal \NLW_cb_int_reg[31]_i_85_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_cb_int_reg[31]_i_9_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_cb_int_reg[31]_i_9_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_cb_int_reg[3]_i_32_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_cb_int_reg[3]_i_43_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_cb_int_reg[3]_i_43_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_cb_int_reg[3]_i_58_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cr_int_reg[31]_i_10_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_cr_int_reg[31]_i_10_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_cr_int_reg[31]_i_54_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_cr_int_reg[31]_i_54_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_y_int_reg[23]_i_32_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_y_int_reg[23]_i_32_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_y_int_reg[31]_i_10_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_y_int_reg[31]_i_10_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_y_int_reg[31]_i_12_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_y_int_reg[31]_i_12_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_y_int_reg[31]_i_31_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_y_int_reg[31]_i_31_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_y_int_reg[31]_i_82_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_y_int_reg[31]_i_82_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_y_int_reg[31]_i_9_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_y_int_reg[31]_i_9_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_y_int_reg[3]_i_20_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \NLW_y_int_reg[3]_i_45_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_y_int_reg[3]_i_70_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
attribute HLUTNM : string;
attribute HLUTNM of \cb_int[3]_i_35\ : label is "lutpair0";
attribute HLUTNM of \cb_int[3]_i_40\ : label is "lutpair0";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \y_int[31]_i_57\ : label is "soft_lutpair39";
attribute SOFT_HLUTNM of \y_int[31]_i_80\ : label is "soft_lutpair39";
attribute SOFT_HLUTNM of \y_int[31]_i_81\ : label is "soft_lutpair40";
attribute SOFT_HLUTNM of \y_int[31]_i_84\ : label is "soft_lutpair38";
attribute SOFT_HLUTNM of \y_int[31]_i_85\ : label is "soft_lutpair40";
attribute SOFT_HLUTNM of \y_int[3]_i_79\ : label is "soft_lutpair38";
begin
hdmi_d(15 downto 8) <= \^hdmi_d\(15 downto 8);
hdmi_d(7) <= \<const0>\;
hdmi_d(6) <= \<const0>\;
hdmi_d(5) <= \<const0>\;
hdmi_d(4) <= \<const0>\;
hdmi_d(3) <= \<const0>\;
hdmi_d(2) <= \<const0>\;
hdmi_d(1) <= \<const0>\;
hdmi_d(0) <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
U0: entity work.system_zed_hdmi_0_0_zed_hdmi
port map (
CO(0) => U0_n_16,
DI(0) => U0_n_4,
O(1) => U0_n_7,
O(0) => U0_n_8,
active => active,
\cb_int_reg[15]_0\(0) => U0_n_76,
\cb_int_reg[27]_0\(0) => U0_n_75,
\cb_int_reg[3]_0\(3) => U0_n_9,
\cb_int_reg[3]_0\(2) => U0_n_10,
\cb_int_reg[3]_0\(1) => U0_n_11,
\cb_int_reg[3]_0\(0) => U0_n_12,
\cb_int_reg[3]_1\(0) => U0_n_72,
\cb_int_reg[3]_2\(0) => U0_n_73,
\cb_int_reg[3]_3\(0) => U0_n_74,
clk => clk,
clk_100 => clk_100,
clk_x2 => clk_x2,
\cr_int_reg[11]_0\(3) => U0_n_34,
\cr_int_reg[11]_0\(2) => U0_n_35,
\cr_int_reg[11]_0\(1) => U0_n_36,
\cr_int_reg[11]_0\(0) => U0_n_37,
\cr_int_reg[15]_0\(3) => U0_n_38,
\cr_int_reg[15]_0\(2) => U0_n_39,
\cr_int_reg[15]_0\(1) => U0_n_40,
\cr_int_reg[15]_0\(0) => U0_n_41,
\cr_int_reg[15]_1\(0) => U0_n_77,
\cr_int_reg[19]_0\(3) => U0_n_42,
\cr_int_reg[19]_0\(2) => U0_n_43,
\cr_int_reg[19]_0\(1) => U0_n_44,
\cr_int_reg[19]_0\(0) => U0_n_45,
\cr_int_reg[23]_0\(3) => U0_n_46,
\cr_int_reg[23]_0\(2) => U0_n_47,
\cr_int_reg[23]_0\(1) => U0_n_48,
\cr_int_reg[23]_0\(0) => U0_n_49,
\cr_int_reg[23]_1\(0) => U0_n_50,
\cr_int_reg[27]_0\ => U0_n_13,
\cr_int_reg[27]_1\(1) => U0_n_14,
\cr_int_reg[27]_1\(0) => U0_n_15,
\cr_int_reg[27]_2\(0) => U0_n_29,
\cr_int_reg[31]_0\ => U0_n_5,
\cr_int_reg[31]_1\ => U0_n_6,
\cr_int_reg[31]_2\(1) => U0_n_17,
\cr_int_reg[31]_2\(0) => U0_n_18,
\cr_int_reg[3]_0\(2) => U0_n_23,
\cr_int_reg[3]_0\(1) => U0_n_24,
\cr_int_reg[3]_0\(0) => U0_n_25,
\cr_int_reg[3]_1\(0) => U0_n_26,
\cr_int_reg[3]_2\(1) => U0_n_27,
\cr_int_reg[3]_2\(0) => U0_n_28,
\cr_int_reg[7]_0\(3) => U0_n_19,
\cr_int_reg[7]_0\(2) => U0_n_20,
\cr_int_reg[7]_0\(1) => U0_n_21,
\cr_int_reg[7]_0\(0) => U0_n_22,
\cr_int_reg[7]_1\(3) => U0_n_30,
\cr_int_reg[7]_1\(2) => U0_n_31,
\cr_int_reg[7]_1\(1) => U0_n_32,
\cr_int_reg[7]_1\(0) => U0_n_33,
hdmi_clk => hdmi_clk,
hdmi_d(7 downto 0) => \^hdmi_d\(15 downto 8),
hdmi_de => hdmi_de,
hdmi_hsync => hdmi_hsync,
hdmi_scl => hdmi_scl,
hdmi_sda => hdmi_sda,
hdmi_vsync => hdmi_vsync,
hsync => hsync,
rgb888(23 downto 0) => rgb888(23 downto 0),
\rgb888[0]\(3) => \cb_int_reg[31]_i_8_n_4\,
\rgb888[0]\(2) => \cb_int_reg[31]_i_8_n_5\,
\rgb888[0]\(1) => \cb_int_reg[31]_i_8_n_6\,
\rgb888[0]\(0) => \cb_int_reg[31]_i_8_n_7\,
\rgb888[0]_0\(3) => \cb_int_reg[31]_i_17_n_4\,
\rgb888[0]_0\(2) => \cb_int_reg[31]_i_17_n_5\,
\rgb888[0]_0\(1) => \cb_int_reg[31]_i_17_n_6\,
\rgb888[0]_0\(0) => \cb_int_reg[31]_i_17_n_7\,
\rgb888[0]_1\(1) => \cb_int_reg[31]_i_42_n_6\,
\rgb888[0]_1\(0) => \cb_int_reg[31]_i_42_n_7\,
\rgb888[0]_2\(3) => \cb_int_reg[23]_i_28_n_4\,
\rgb888[0]_2\(2) => \cb_int_reg[23]_i_28_n_5\,
\rgb888[0]_2\(1) => \cb_int_reg[23]_i_28_n_6\,
\rgb888[0]_2\(0) => \cb_int_reg[23]_i_28_n_7\,
\rgb888[0]_3\(3) => \cb_int_reg[19]_i_33_n_4\,
\rgb888[0]_3\(2) => \cb_int_reg[19]_i_33_n_5\,
\rgb888[0]_3\(1) => \cb_int_reg[19]_i_33_n_6\,
\rgb888[0]_3\(0) => \cb_int_reg[19]_i_33_n_7\,
\rgb888[0]_4\(3) => \cb_int_reg[15]_i_34_n_4\,
\rgb888[0]_4\(2) => \cb_int_reg[15]_i_34_n_5\,
\rgb888[0]_4\(1) => \cb_int_reg[15]_i_34_n_6\,
\rgb888[0]_4\(0) => \cb_int_reg[15]_i_34_n_7\,
\rgb888[0]_5\(3) => \cr_int_reg[23]_i_31_n_4\,
\rgb888[0]_5\(2) => \cr_int_reg[23]_i_31_n_5\,
\rgb888[0]_5\(1) => \cr_int_reg[23]_i_31_n_6\,
\rgb888[0]_5\(0) => \cr_int_reg[23]_i_31_n_7\,
\rgb888[0]_6\(1) => \cr_int_reg[31]_i_54_n_6\,
\rgb888[0]_6\(0) => \cr_int_reg[31]_i_54_n_7\,
\rgb888[0]_7\(3) => \y_int_reg[31]_i_71_n_4\,
\rgb888[0]_7\(2) => \y_int_reg[31]_i_71_n_5\,
\rgb888[0]_7\(1) => \y_int_reg[31]_i_71_n_6\,
\rgb888[0]_7\(0) => \y_int_reg[31]_i_71_n_7\,
\rgb888[0]_8\(1) => \cb_int_reg[3]_i_43_n_6\,
\rgb888[0]_8\(0) => \cb_int_reg[3]_i_43_n_7\,
\rgb888[0]_9\(2) => \y_int_reg[31]_i_31_n_5\,
\rgb888[0]_9\(1) => \y_int_reg[31]_i_31_n_6\,
\rgb888[0]_9\(0) => \y_int_reg[31]_i_31_n_7\,
\rgb888[12]\(3) => \cb_int_reg[7]_i_24_n_4\,
\rgb888[12]\(2) => \cb_int_reg[7]_i_24_n_5\,
\rgb888[12]\(1) => \cb_int_reg[7]_i_24_n_6\,
\rgb888[12]\(0) => \cb_int_reg[7]_i_24_n_7\,
\rgb888[12]_0\(3) => \cb_int_reg[15]_i_32_n_4\,
\rgb888[12]_0\(2) => \cb_int_reg[15]_i_32_n_5\,
\rgb888[12]_0\(1) => \cb_int_reg[15]_i_32_n_6\,
\rgb888[12]_0\(0) => \cb_int_reg[15]_i_32_n_7\,
\rgb888[13]\(0) => \cb_int_reg[3]_i_32_n_4\,
\rgb888[13]_0\(3) => \cb_int_reg[7]_i_27_n_4\,
\rgb888[13]_0\(2) => \cb_int_reg[7]_i_27_n_5\,
\rgb888[13]_0\(1) => \cb_int_reg[7]_i_27_n_6\,
\rgb888[13]_0\(0) => \cb_int_reg[7]_i_27_n_7\,
\rgb888[14]\(3) => \y_int_reg[3]_i_19_n_4\,
\rgb888[14]\(2) => \y_int_reg[3]_i_19_n_5\,
\rgb888[14]\(1) => \y_int_reg[3]_i_19_n_6\,
\rgb888[14]\(0) => \y_int_reg[3]_i_19_n_7\,
\rgb888[14]_0\(1) => \y_int_reg[3]_i_20_n_4\,
\rgb888[14]_0\(0) => \y_int_reg[3]_i_20_n_5\,
\rgb888[14]_1\(3) => \y_int_reg[7]_i_23_n_4\,
\rgb888[14]_1\(2) => \y_int_reg[7]_i_23_n_5\,
\rgb888[14]_1\(1) => \y_int_reg[7]_i_23_n_6\,
\rgb888[14]_1\(0) => \y_int_reg[7]_i_23_n_7\,
\rgb888[1]\(13 downto 0) => y_int_reg2(22 downto 9),
\rgb888[1]_0\(0) => \y_int_reg[31]_i_12_n_1\,
\rgb888[3]\(3) => \cr_int_reg[15]_i_39_n_4\,
\rgb888[3]\(2) => \cr_int_reg[15]_i_39_n_5\,
\rgb888[3]\(1) => \cr_int_reg[15]_i_39_n_6\,
\rgb888[3]\(0) => \cr_int_reg[15]_i_39_n_7\,
\rgb888[3]_0\(3) => \cr_int_reg[19]_i_37_n_4\,
\rgb888[3]_0\(2) => \cr_int_reg[19]_i_37_n_5\,
\rgb888[3]_0\(1) => \cr_int_reg[19]_i_37_n_6\,
\rgb888[3]_0\(0) => \cr_int_reg[19]_i_37_n_7\,
\rgb888[8]\(3) => \cb_int_reg[3]_i_19_n_4\,
\rgb888[8]\(2) => \cb_int_reg[3]_i_19_n_5\,
\rgb888[8]\(1) => \cb_int_reg[3]_i_19_n_6\,
\rgb888[8]\(0) => \cb_int_reg[3]_i_19_n_7\,
\rgb888[8]_0\(3) => \cb_int_reg[31]_i_23_n_4\,
\rgb888[8]_0\(2) => \cb_int_reg[31]_i_23_n_5\,
\rgb888[8]_0\(1) => \cb_int_reg[31]_i_23_n_6\,
\rgb888[8]_0\(0) => \cb_int_reg[31]_i_23_n_7\,
\rgb888[8]_1\(1) => \cb_int_reg[31]_i_9_n_6\,
\rgb888[8]_1\(0) => \cb_int_reg[31]_i_9_n_7\,
\rgb888[8]_10\(1) => \cb_int_reg[31]_i_66_n_6\,
\rgb888[8]_10\(0) => \cb_int_reg[31]_i_66_n_7\,
\rgb888[8]_11\(0) => \cb_int_reg[31]_i_10_n_1\,
\rgb888[8]_12\(3) => \cr_int_reg[7]_i_24_n_4\,
\rgb888[8]_12\(2) => \cr_int_reg[7]_i_24_n_5\,
\rgb888[8]_12\(1) => \cr_int_reg[7]_i_24_n_6\,
\rgb888[8]_12\(0) => \cr_int_reg[7]_i_24_n_7\,
\rgb888[8]_13\(3) => \cr_int_reg[11]_i_28_n_4\,
\rgb888[8]_13\(2) => \cr_int_reg[11]_i_28_n_5\,
\rgb888[8]_13\(1) => \cr_int_reg[11]_i_28_n_6\,
\rgb888[8]_13\(0) => \cr_int_reg[11]_i_28_n_7\,
\rgb888[8]_14\(3) => \cr_int_reg[15]_i_37_n_4\,
\rgb888[8]_14\(2) => \cr_int_reg[15]_i_37_n_5\,
\rgb888[8]_14\(1) => \cr_int_reg[15]_i_37_n_6\,
\rgb888[8]_14\(0) => \cr_int_reg[15]_i_37_n_7\,
\rgb888[8]_15\(3) => \cr_int_reg[31]_i_64_n_4\,
\rgb888[8]_15\(2) => \cr_int_reg[31]_i_64_n_5\,
\rgb888[8]_15\(1) => \cr_int_reg[31]_i_64_n_6\,
\rgb888[8]_15\(0) => \cr_int_reg[31]_i_64_n_7\,
\rgb888[8]_16\(3) => \cr_int_reg[31]_i_27_n_4\,
\rgb888[8]_16\(2) => \cr_int_reg[31]_i_27_n_5\,
\rgb888[8]_16\(1) => \cr_int_reg[31]_i_27_n_6\,
\rgb888[8]_16\(0) => \cr_int_reg[31]_i_27_n_7\,
\rgb888[8]_17\(1) => \cr_int_reg[31]_i_10_n_6\,
\rgb888[8]_17\(0) => \cr_int_reg[31]_i_10_n_7\,
\rgb888[8]_18\(0) => \cr_int_reg[31]_i_10_n_1\,
\rgb888[8]_19\(2) => \y_int_reg[3]_i_70_n_4\,
\rgb888[8]_19\(1) => \y_int_reg[3]_i_70_n_5\,
\rgb888[8]_19\(0) => \y_int_reg[3]_i_70_n_6\,
\rgb888[8]_2\(3) => \cb_int_reg[7]_i_26_n_4\,
\rgb888[8]_2\(2) => \cb_int_reg[7]_i_26_n_5\,
\rgb888[8]_2\(1) => \cb_int_reg[7]_i_26_n_6\,
\rgb888[8]_2\(0) => \cb_int_reg[7]_i_26_n_7\,
\rgb888[8]_20\(3) => \y_int_reg[31]_i_21_n_4\,
\rgb888[8]_20\(2) => \y_int_reg[31]_i_21_n_5\,
\rgb888[8]_20\(1) => \y_int_reg[31]_i_21_n_6\,
\rgb888[8]_20\(0) => \y_int_reg[31]_i_21_n_7\,
\rgb888[8]_21\(2) => \y_int_reg[31]_i_9_n_5\,
\rgb888[8]_21\(1) => \y_int_reg[31]_i_9_n_6\,
\rgb888[8]_21\(0) => \y_int_reg[31]_i_9_n_7\,
\rgb888[8]_22\(3) => \y_int_reg[11]_i_27_n_4\,
\rgb888[8]_22\(2) => \y_int_reg[11]_i_27_n_5\,
\rgb888[8]_22\(1) => \y_int_reg[11]_i_27_n_6\,
\rgb888[8]_22\(0) => \y_int_reg[11]_i_27_n_7\,
\rgb888[8]_23\(1) => \y_int_reg[31]_i_10_n_6\,
\rgb888[8]_23\(0) => \y_int_reg[31]_i_10_n_7\,
\rgb888[8]_24\(0) => \y_int_reg[23]_i_32_n_7\,
\rgb888[8]_25\(3) => \y_int_reg[23]_i_35_n_4\,
\rgb888[8]_25\(2) => \y_int_reg[23]_i_35_n_5\,
\rgb888[8]_25\(1) => \y_int_reg[23]_i_35_n_6\,
\rgb888[8]_25\(0) => \y_int_reg[23]_i_35_n_7\,
\rgb888[8]_26\(3) => \y_int_reg[31]_i_27_n_4\,
\rgb888[8]_26\(2) => \y_int_reg[31]_i_27_n_5\,
\rgb888[8]_26\(1) => \y_int_reg[31]_i_27_n_6\,
\rgb888[8]_26\(0) => \y_int_reg[31]_i_27_n_7\,
\rgb888[8]_27\(3) => \y_int_reg[19]_i_24_n_4\,
\rgb888[8]_27\(2) => \y_int_reg[19]_i_24_n_5\,
\rgb888[8]_27\(1) => \y_int_reg[19]_i_24_n_6\,
\rgb888[8]_27\(0) => \y_int_reg[19]_i_24_n_7\,
\rgb888[8]_28\(3) => \y_int_reg[19]_i_33_n_4\,
\rgb888[8]_28\(2) => \y_int_reg[19]_i_33_n_5\,
\rgb888[8]_28\(1) => \y_int_reg[19]_i_33_n_6\,
\rgb888[8]_28\(0) => \y_int_reg[19]_i_33_n_7\,
\rgb888[8]_29\(3) => \y_int_reg[15]_i_24_n_4\,
\rgb888[8]_29\(2) => \y_int_reg[15]_i_24_n_5\,
\rgb888[8]_29\(1) => \y_int_reg[15]_i_24_n_6\,
\rgb888[8]_29\(0) => \y_int_reg[15]_i_24_n_7\,
\rgb888[8]_3\(3) => \cb_int_reg[7]_i_23_n_4\,
\rgb888[8]_3\(2) => \cb_int_reg[7]_i_23_n_5\,
\rgb888[8]_3\(1) => \cb_int_reg[7]_i_23_n_6\,
\rgb888[8]_3\(0) => \cb_int_reg[7]_i_23_n_7\,
\rgb888[8]_30\(0) => \y_int_reg[31]_i_10_n_1\,
\rgb888[8]_31\(2) => \cb_int_reg[3]_i_68_n_5\,
\rgb888[8]_31\(1) => \cb_int_reg[3]_i_68_n_6\,
\rgb888[8]_31\(0) => \cb_int_reg[3]_i_68_n_7\,
\rgb888[8]_32\(1) => \y_int_reg[3]_i_40_n_6\,
\rgb888[8]_32\(0) => \y_int_reg[3]_i_40_n_7\,
\rgb888[8]_4\(3) => \cb_int_reg[15]_i_31_n_4\,
\rgb888[8]_4\(2) => \cb_int_reg[15]_i_31_n_5\,
\rgb888[8]_4\(1) => \cb_int_reg[15]_i_31_n_6\,
\rgb888[8]_4\(0) => \cb_int_reg[15]_i_31_n_7\,
\rgb888[8]_5\(3) => \cb_int_reg[31]_i_61_n_4\,
\rgb888[8]_5\(2) => \cb_int_reg[31]_i_61_n_5\,
\rgb888[8]_5\(1) => \cb_int_reg[31]_i_61_n_6\,
\rgb888[8]_5\(0) => \cb_int_reg[31]_i_61_n_7\,
\rgb888[8]_6\(3) => \cb_int_reg[19]_i_32_n_4\,
\rgb888[8]_6\(2) => \cb_int_reg[19]_i_32_n_5\,
\rgb888[8]_6\(1) => \cb_int_reg[19]_i_32_n_6\,
\rgb888[8]_6\(0) => \cb_int_reg[19]_i_32_n_7\,
\rgb888[8]_7\(3) => \cb_int_reg[31]_i_27_n_4\,
\rgb888[8]_7\(2) => \cb_int_reg[31]_i_27_n_5\,
\rgb888[8]_7\(1) => \cb_int_reg[31]_i_27_n_6\,
\rgb888[8]_7\(0) => \cb_int_reg[31]_i_27_n_7\,
\rgb888[8]_8\(3) => \cb_int_reg[23]_i_27_n_4\,
\rgb888[8]_8\(2) => \cb_int_reg[23]_i_27_n_5\,
\rgb888[8]_8\(1) => \cb_int_reg[23]_i_27_n_6\,
\rgb888[8]_8\(0) => \cb_int_reg[23]_i_27_n_7\,
\rgb888[8]_9\(1) => \cb_int_reg[31]_i_10_n_6\,
\rgb888[8]_9\(0) => \cb_int_reg[31]_i_10_n_7\,
vsync => vsync,
\y_int_reg[15]_0\(3) => U0_n_68,
\y_int_reg[15]_0\(2) => U0_n_69,
\y_int_reg[15]_0\(1) => U0_n_70,
\y_int_reg[15]_0\(0) => U0_n_71,
\y_int_reg[15]_1\(0) => U0_n_81,
\y_int_reg[19]_0\(3) => U0_n_64,
\y_int_reg[19]_0\(2) => U0_n_65,
\y_int_reg[19]_0\(1) => U0_n_66,
\y_int_reg[19]_0\(0) => U0_n_67,
\y_int_reg[19]_1\(0) => U0_n_79,
\y_int_reg[23]_0\(0) => U0_n_55,
\y_int_reg[23]_1\(1) => U0_n_58,
\y_int_reg[23]_1\(0) => U0_n_59,
\y_int_reg[23]_2\(3) => U0_n_60,
\y_int_reg[23]_2\(2) => U0_n_61,
\y_int_reg[23]_2\(1) => U0_n_62,
\y_int_reg[23]_2\(0) => U0_n_63,
\y_int_reg[23]_3\(0) => U0_n_80,
\y_int_reg[3]_0\(3) => U0_n_51,
\y_int_reg[3]_0\(2) => U0_n_52,
\y_int_reg[3]_0\(1) => U0_n_53,
\y_int_reg[3]_0\(0) => U0_n_54,
\y_int_reg[3]_1\(0) => U0_n_57,
\y_int_reg[3]_2\(0) => U0_n_78,
\y_int_reg[7]_0\(0) => U0_n_56
);
\cb_int[15]_i_35\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
I1 => U0_n_16,
I2 => \cb_int_reg[15]_i_32_n_4\,
O => \cb_int[15]_i_35_n_0\
);
\cb_int[15]_i_36\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
I1 => U0_n_16,
I2 => \cb_int_reg[15]_i_32_n_5\,
O => \cb_int[15]_i_36_n_0\
);
\cb_int[15]_i_37\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
I1 => U0_n_16,
I2 => \cb_int_reg[15]_i_32_n_6\,
O => \cb_int[15]_i_37_n_0\
);
\cb_int[15]_i_38\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
I1 => U0_n_16,
I2 => \cb_int_reg[15]_i_32_n_7\,
O => \cb_int[15]_i_38_n_0\
);
\cb_int[15]_i_39\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
O => \cb_int[15]_i_39_n_0\
);
\cb_int[15]_i_40\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
O => \cb_int[15]_i_40_n_0\
);
\cb_int[15]_i_41\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
O => \cb_int[15]_i_41_n_0\
);
\cb_int[15]_i_42\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
O => \cb_int[15]_i_42_n_0\
);
\cb_int[15]_i_47\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_8_n_4\,
O => \cb_int[15]_i_47_n_0\
);
\cb_int[15]_i_48\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_8_n_4\,
O => \cb_int[15]_i_48_n_0\
);
\cb_int[15]_i_49\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_8_n_4\,
O => \cb_int[15]_i_49_n_0\
);
\cb_int[15]_i_50\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_8_n_4\,
O => \cb_int[15]_i_50_n_0\
);
\cb_int[19]_i_38\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
O => \cb_int[19]_i_38_n_0\
);
\cb_int[19]_i_39\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
O => \cb_int[19]_i_39_n_0\
);
\cb_int[19]_i_40\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
O => \cb_int[19]_i_40_n_0\
);
\cb_int[19]_i_41\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
O => \cb_int[19]_i_41_n_0\
);
\cb_int[19]_i_42\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_8_n_4\,
O => \cb_int[19]_i_42_n_0\
);
\cb_int[19]_i_43\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_8_n_4\,
O => \cb_int[19]_i_43_n_0\
);
\cb_int[19]_i_44\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_8_n_4\,
O => \cb_int[19]_i_44_n_0\
);
\cb_int[19]_i_45\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_8_n_4\,
O => \cb_int[19]_i_45_n_0\
);
\cb_int[23]_i_33\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
O => \cb_int[23]_i_33_n_0\
);
\cb_int[23]_i_34\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
O => \cb_int[23]_i_34_n_0\
);
\cb_int[23]_i_35\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
O => \cb_int[23]_i_35_n_0\
);
\cb_int[23]_i_36\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
O => \cb_int[23]_i_36_n_0\
);
\cb_int[23]_i_37\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_8_n_4\,
O => \cb_int[23]_i_37_n_0\
);
\cb_int[23]_i_38\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_8_n_4\,
O => \cb_int[23]_i_38_n_0\
);
\cb_int[23]_i_39\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_8_n_4\,
O => \cb_int[23]_i_39_n_0\
);
\cb_int[23]_i_40\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_8_n_4\,
O => \cb_int[23]_i_40_n_0\
);
\cb_int[31]_i_100\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(14),
O => \cb_int[31]_i_100_n_0\
);
\cb_int[31]_i_101\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => rgb888(13),
O => \cb_int[31]_i_101_n_0\
);
\cb_int[31]_i_18\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => U0_n_13,
I1 => rgb888(7),
O => \cb_int[31]_i_18_n_0\
);
\cb_int[31]_i_19\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => rgb888(7),
I1 => U0_n_13,
O => \cb_int[31]_i_19_n_0\
);
\cb_int[31]_i_20\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => rgb888(7),
I1 => U0_n_13,
O => \cb_int[31]_i_20_n_0\
);
\cb_int[31]_i_21\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => rgb888(7),
I1 => U0_n_13,
O => \cb_int[31]_i_21_n_0\
);
\cb_int[31]_i_22\: unisim.vcomponents.LUT3
generic map(
INIT => X"95"
)
port map (
I0 => rgb888(7),
I1 => \cb_int[31]_i_52_n_0\,
I2 => rgb888(6),
O => \cb_int[31]_i_22_n_0\
);
\cb_int[31]_i_25\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFFFFFFFFFF"
)
port map (
I0 => rgb888(15),
I1 => rgb888(13),
I2 => rgb888(11),
I3 => rgb888(10),
I4 => rgb888(12),
I5 => rgb888(14),
O => \cb_int[31]_i_25_n_0\
);
\cb_int[31]_i_26\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(15),
O => \cb_int[31]_i_26_n_0\
);
\cb_int[31]_i_28\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
I1 => U0_n_16,
I2 => \cb_int_reg[31]_i_66_n_6\,
O => \cb_int[31]_i_28_n_0\
);
\cb_int[31]_i_29\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
I1 => U0_n_16,
I2 => \cb_int_reg[31]_i_66_n_7\,
O => \cb_int[31]_i_29_n_0\
);
\cb_int[31]_i_45\: unisim.vcomponents.LUT5
generic map(
INIT => X"99999996"
)
port map (
I0 => \cb_int_reg[3]_i_43_n_1\,
I1 => rgb888(4),
I2 => rgb888(2),
I3 => rgb888(1),
I4 => rgb888(3),
O => \cb_int[31]_i_45_n_0\
);
\cb_int[31]_i_46\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(2),
I1 => rgb888(1),
O => \cb_int[31]_i_46_n_0\
);
\cb_int[31]_i_47\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAA955555555"
)
port map (
I0 => rgb888(6),
I1 => rgb888(4),
I2 => rgb888(2),
I3 => rgb888(1),
I4 => rgb888(3),
I5 => rgb888(5),
O => \cb_int[31]_i_47_n_0\
);
\cb_int[31]_i_48\: unisim.vcomponents.LUT6
generic map(
INIT => X"CCCCCCC999999993"
)
port map (
I0 => \cb_int_reg[3]_i_43_n_1\,
I1 => rgb888(5),
I2 => rgb888(3),
I3 => rgb888(1),
I4 => rgb888(2),
I5 => rgb888(4),
O => \cb_int[31]_i_48_n_0\
);
\cb_int[31]_i_49\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAA99995"
)
port map (
I0 => rgb888(4),
I1 => \cb_int_reg[3]_i_43_n_1\,
I2 => rgb888(2),
I3 => rgb888(1),
I4 => rgb888(3),
O => \cb_int[31]_i_49_n_0\
);
\cb_int[31]_i_50\: unisim.vcomponents.LUT4
generic map(
INIT => X"6A95"
)
port map (
I0 => \cb_int_reg[3]_i_43_n_1\,
I1 => rgb888(2),
I2 => rgb888(1),
I3 => rgb888(3),
O => \cb_int[31]_i_50_n_0\
);
\cb_int[31]_i_52\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => rgb888(4),
I1 => rgb888(2),
I2 => rgb888(1),
I3 => rgb888(3),
I4 => rgb888(5),
O => \cb_int[31]_i_52_n_0\
);
\cb_int[31]_i_53\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000080000000"
)
port map (
I0 => rgb888(14),
I1 => rgb888(12),
I2 => rgb888(10),
I3 => rgb888(11),
I4 => rgb888(13),
I5 => rgb888(15),
O => \cb_int[31]_i_53_n_0\
);
\cb_int[31]_i_54\: unisim.vcomponents.LUT6
generic map(
INIT => X"000000006AAAAAAA"
)
port map (
I0 => rgb888(14),
I1 => rgb888(13),
I2 => rgb888(11),
I3 => rgb888(10),
I4 => rgb888(12),
I5 => rgb888(15),
O => \cb_int[31]_i_54_n_0\
);
\cb_int[31]_i_55\: unisim.vcomponents.LUT6
generic map(
INIT => X"2BBBBBBBB2222222"
)
port map (
I0 => \cb_int_reg[31]_i_85_n_0\,
I1 => rgb888(15),
I2 => rgb888(11),
I3 => rgb888(10),
I4 => rgb888(12),
I5 => rgb888(13),
O => \cb_int[31]_i_55_n_0\
);
\cb_int[31]_i_56\: unisim.vcomponents.LUT5
generic map(
INIT => X"BFEA2A80"
)
port map (
I0 => \cb_int_reg[31]_i_85_n_5\,
I1 => rgb888(10),
I2 => rgb888(11),
I3 => rgb888(12),
I4 => rgb888(14),
O => \cb_int[31]_i_56_n_0\
);
\cb_int[31]_i_57\: unisim.vcomponents.LUT6
generic map(
INIT => X"9555555555555555"
)
port map (
I0 => rgb888(15),
I1 => rgb888(13),
I2 => rgb888(11),
I3 => rgb888(10),
I4 => rgb888(12),
I5 => rgb888(14),
O => \cb_int[31]_i_57_n_0\
);
\cb_int[31]_i_58\: unisim.vcomponents.LUT6
generic map(
INIT => X"2AAAAAAABFFFFFFF"
)
port map (
I0 => rgb888(15),
I1 => rgb888(13),
I2 => rgb888(11),
I3 => rgb888(10),
I4 => rgb888(12),
I5 => rgb888(14),
O => \cb_int[31]_i_58_n_0\
);
\cb_int[31]_i_59\: unisim.vcomponents.LUT4
generic map(
INIT => X"7E81"
)
port map (
I0 => U0_n_6,
I1 => \cb_int_reg[31]_i_85_n_0\,
I2 => rgb888(15),
I3 => U0_n_5,
O => \cb_int[31]_i_59_n_0\
);
\cb_int[31]_i_60\: unisim.vcomponents.LUT6
generic map(
INIT => X"E81717E817E8E817"
)
port map (
I0 => rgb888(14),
I1 => \cb_int[31]_i_88_n_0\,
I2 => \cb_int_reg[31]_i_85_n_5\,
I3 => U0_n_6,
I4 => rgb888(15),
I5 => \cb_int_reg[31]_i_85_n_0\,
O => \cb_int[31]_i_60_n_0\
);
\cb_int[31]_i_62\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
I1 => U0_n_16,
I2 => \cb_int_reg[23]_i_27_n_4\,
O => \cb_int[31]_i_62_n_0\
);
\cb_int[31]_i_63\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
I1 => U0_n_16,
I2 => \cb_int_reg[23]_i_27_n_5\,
O => \cb_int[31]_i_63_n_0\
);
\cb_int[31]_i_64\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
I1 => U0_n_16,
I2 => \cb_int_reg[23]_i_27_n_6\,
O => \cb_int[31]_i_64_n_0\
);
\cb_int[31]_i_65\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
I1 => U0_n_16,
I2 => \cb_int_reg[23]_i_27_n_7\,
O => \cb_int[31]_i_65_n_0\
);
\cb_int[31]_i_83\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_8_n_4\,
O => \cb_int[31]_i_83_n_0\
);
\cb_int[31]_i_84\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_8_n_4\,
O => \cb_int[31]_i_84_n_0\
);
\cb_int[31]_i_88\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => rgb888(10),
I1 => rgb888(11),
I2 => rgb888(12),
O => \cb_int[31]_i_88_n_0\
);
\cb_int[31]_i_89\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
I1 => U0_n_16,
I2 => \cb_int_reg[19]_i_32_n_4\,
O => \cb_int[31]_i_89_n_0\
);
\cb_int[31]_i_90\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
I1 => U0_n_16,
I2 => \cb_int_reg[19]_i_32_n_5\,
O => \cb_int[31]_i_90_n_0\
);
\cb_int[31]_i_91\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
I1 => U0_n_16,
I2 => \cb_int_reg[19]_i_32_n_6\,
O => \cb_int[31]_i_91_n_0\
);
\cb_int[31]_i_92\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
I1 => U0_n_16,
I2 => \cb_int_reg[19]_i_32_n_7\,
O => \cb_int[31]_i_92_n_0\
);
\cb_int[31]_i_93\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
O => \cb_int[31]_i_93_n_0\
);
\cb_int[31]_i_94\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
O => \cb_int[31]_i_94_n_0\
);
\cb_int[31]_i_99\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(15),
O => \cb_int[31]_i_99_n_0\
);
\cb_int[3]_i_35\: unisim.vcomponents.LUT4
generic map(
INIT => X"BE28"
)
port map (
I0 => \cb_int_reg[31]_i_85_n_6\,
I1 => rgb888(10),
I2 => rgb888(11),
I3 => rgb888(13),
O => \cb_int[3]_i_35_n_0\
);
\cb_int[3]_i_36\: unisim.vcomponents.LUT3
generic map(
INIT => X"D4"
)
port map (
I0 => rgb888(10),
I1 => \cb_int_reg[31]_i_85_n_7\,
I2 => rgb888(12),
O => \cb_int[3]_i_36_n_0\
);
\cb_int[3]_i_37\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \cb_int_reg[3]_i_68_n_4\,
I1 => rgb888(9),
I2 => rgb888(11),
O => \cb_int[3]_i_37_n_0\
);
\cb_int[3]_i_38\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cb_int_reg[3]_i_68_n_4\,
I1 => rgb888(9),
I2 => rgb888(11),
O => \cb_int[3]_i_38_n_0\
);
\cb_int[3]_i_39\: unisim.vcomponents.LUT6
generic map(
INIT => X"9669696969969696"
)
port map (
I0 => \cb_int[3]_i_35_n_0\,
I1 => rgb888(14),
I2 => rgb888(12),
I3 => rgb888(11),
I4 => rgb888(10),
I5 => \cb_int_reg[31]_i_85_n_5\,
O => \cb_int[3]_i_39_n_0\
);
\cb_int[3]_i_40\: unisim.vcomponents.LUT5
generic map(
INIT => X"96696996"
)
port map (
I0 => \cb_int_reg[31]_i_85_n_6\,
I1 => rgb888(10),
I2 => rgb888(11),
I3 => rgb888(13),
I4 => \cb_int[3]_i_36_n_0\,
O => \cb_int[3]_i_40_n_0\
);
\cb_int[3]_i_41\: unisim.vcomponents.LUT6
generic map(
INIT => X"E81717E817E8E817"
)
port map (
I0 => rgb888(11),
I1 => rgb888(9),
I2 => \cb_int_reg[3]_i_68_n_4\,
I3 => rgb888(12),
I4 => rgb888(10),
I5 => \cb_int_reg[31]_i_85_n_7\,
O => \cb_int[3]_i_41_n_0\
);
\cb_int[3]_i_42\: unisim.vcomponents.LUT5
generic map(
INIT => X"69969696"
)
port map (
I0 => rgb888(11),
I1 => rgb888(9),
I2 => \cb_int_reg[3]_i_68_n_4\,
I3 => rgb888(10),
I4 => rgb888(8),
O => \cb_int[3]_i_42_n_0\
);
\cb_int[3]_i_59\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_19_n_6\,
O => \cb_int[3]_i_59_n_0\
);
\cb_int[3]_i_60\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_19_n_7\,
O => \cb_int[3]_i_60_n_0\
);
\cb_int[3]_i_61\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => U0_n_9,
O => \cb_int[3]_i_61_n_0\
);
\cb_int[3]_i_62\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => U0_n_10,
O => \cb_int[3]_i_62_n_0\
);
\cb_int[3]_i_73\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(7),
O => \cb_int[3]_i_73_n_0\
);
\cb_int[3]_i_74\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => rgb888(6),
O => \cb_int[3]_i_74_n_0\
);
\cb_int[3]_i_84\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(8),
O => \cb_int[3]_i_84_n_0\
);
\cb_int[3]_i_85\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => U0_n_11,
O => \cb_int[3]_i_85_n_0\
);
\cb_int[3]_i_86\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => U0_n_12,
O => \cb_int[3]_i_86_n_0\
);
\cb_int[3]_i_87\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => U0_n_7,
O => \cb_int[3]_i_87_n_0\
);
\cb_int[3]_i_88\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => U0_n_8,
O => \cb_int[3]_i_88_n_0\
);
\cb_int[3]_i_95\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(12),
I1 => rgb888(15),
O => \cb_int[3]_i_95_n_0\
);
\cb_int[3]_i_96\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(11),
I1 => rgb888(14),
O => \cb_int[3]_i_96_n_0\
);
\cb_int[3]_i_97\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(10),
I1 => rgb888(13),
O => \cb_int[3]_i_97_n_0\
);
\cb_int[3]_i_98\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(9),
I1 => rgb888(12),
O => \cb_int[3]_i_98_n_0\
);
\cb_int[7]_i_30\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
I1 => U0_n_16,
I2 => \cb_int_reg[7]_i_24_n_4\,
O => \cb_int[7]_i_30_n_0\
);
\cb_int[7]_i_31\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \cb_int_reg[7]_i_24_n_5\,
I1 => U0_n_16,
I2 => \cb_int_reg[31]_i_9_n_7\,
O => \cb_int[7]_i_31_n_0\
);
\cb_int[7]_i_32\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \cb_int_reg[7]_i_24_n_6\,
I1 => U0_n_16,
I2 => \cb_int_reg[31]_i_23_n_4\,
O => \cb_int[7]_i_32_n_0\
);
\cb_int[7]_i_33\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \cb_int_reg[7]_i_24_n_7\,
I1 => U0_n_16,
I2 => \cb_int_reg[31]_i_23_n_5\,
O => \cb_int[7]_i_33_n_0\
);
\cb_int[7]_i_34\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
O => \cb_int[7]_i_34_n_0\
);
\cb_int[7]_i_35\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_7\,
O => \cb_int[7]_i_35_n_0\
);
\cb_int[7]_i_36\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_23_n_4\,
O => \cb_int[7]_i_36_n_0\
);
\cb_int[7]_i_37\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_23_n_5\,
O => \cb_int[7]_i_37_n_0\
);
\cb_int[7]_i_43\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \cb_int_reg[3]_i_32_n_4\,
I1 => U0_n_16,
I2 => \cb_int_reg[3]_i_19_n_6\,
O => \cb_int[7]_i_43_n_0\
);
\cb_int[7]_i_44\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \cb_int_reg[7]_i_27_n_4\,
I1 => U0_n_16,
I2 => \cb_int_reg[31]_i_23_n_6\,
O => \cb_int[7]_i_44_n_0\
);
\cb_int[7]_i_45\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \cb_int_reg[7]_i_27_n_5\,
I1 => U0_n_16,
I2 => \cb_int_reg[31]_i_23_n_7\,
O => \cb_int[7]_i_45_n_0\
);
\cb_int[7]_i_46\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \cb_int_reg[7]_i_27_n_6\,
I1 => U0_n_16,
I2 => \cb_int_reg[3]_i_19_n_4\,
O => \cb_int[7]_i_46_n_0\
);
\cb_int[7]_i_47\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \cb_int_reg[7]_i_27_n_7\,
I1 => U0_n_16,
I2 => \cb_int_reg[3]_i_19_n_5\,
O => \cb_int[7]_i_47_n_0\
);
\cb_int[7]_i_48\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_23_n_6\,
O => \cb_int[7]_i_48_n_0\
);
\cb_int[7]_i_49\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_23_n_7\,
O => \cb_int[7]_i_49_n_0\
);
\cb_int[7]_i_50\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_19_n_4\,
O => \cb_int[7]_i_50_n_0\
);
\cb_int[7]_i_51\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_19_n_5\,
O => \cb_int[7]_i_51_n_0\
);
\cb_int_reg[15]_i_31\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[7]_i_23_n_0\,
CO(3) => \cb_int_reg[15]_i_31_n_0\,
CO(2) => \cb_int_reg[15]_i_31_n_1\,
CO(1) => \cb_int_reg[15]_i_31_n_2\,
CO(0) => \cb_int_reg[15]_i_31_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cb_int_reg[15]_i_31_n_4\,
O(2) => \cb_int_reg[15]_i_31_n_5\,
O(1) => \cb_int_reg[15]_i_31_n_6\,
O(0) => \cb_int_reg[15]_i_31_n_7\,
S(3) => \cb_int[15]_i_35_n_0\,
S(2) => \cb_int[15]_i_36_n_0\,
S(1) => \cb_int[15]_i_37_n_0\,
S(0) => \cb_int[15]_i_38_n_0\
);
\cb_int_reg[15]_i_32\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[7]_i_24_n_0\,
CO(3) => \cb_int_reg[15]_i_32_n_0\,
CO(2) => \cb_int_reg[15]_i_32_n_1\,
CO(1) => \cb_int_reg[15]_i_32_n_2\,
CO(0) => \cb_int_reg[15]_i_32_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cb_int_reg[15]_i_32_n_4\,
O(2) => \cb_int_reg[15]_i_32_n_5\,
O(1) => \cb_int_reg[15]_i_32_n_6\,
O(0) => \cb_int_reg[15]_i_32_n_7\,
S(3) => \cb_int[15]_i_39_n_0\,
S(2) => \cb_int[15]_i_40_n_0\,
S(1) => \cb_int[15]_i_41_n_0\,
S(0) => \cb_int[15]_i_42_n_0\
);
\cb_int_reg[15]_i_34\: unisim.vcomponents.CARRY4
port map (
CI => U0_n_76,
CO(3) => \cb_int_reg[15]_i_34_n_0\,
CO(2) => \cb_int_reg[15]_i_34_n_1\,
CO(1) => \cb_int_reg[15]_i_34_n_2\,
CO(0) => \cb_int_reg[15]_i_34_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cb_int_reg[15]_i_34_n_4\,
O(2) => \cb_int_reg[15]_i_34_n_5\,
O(1) => \cb_int_reg[15]_i_34_n_6\,
O(0) => \cb_int_reg[15]_i_34_n_7\,
S(3) => \cb_int[15]_i_47_n_0\,
S(2) => \cb_int[15]_i_48_n_0\,
S(1) => \cb_int[15]_i_49_n_0\,
S(0) => \cb_int[15]_i_50_n_0\
);
\cb_int_reg[19]_i_32\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[15]_i_32_n_0\,
CO(3) => \cb_int_reg[19]_i_32_n_0\,
CO(2) => \cb_int_reg[19]_i_32_n_1\,
CO(1) => \cb_int_reg[19]_i_32_n_2\,
CO(0) => \cb_int_reg[19]_i_32_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cb_int_reg[19]_i_32_n_4\,
O(2) => \cb_int_reg[19]_i_32_n_5\,
O(1) => \cb_int_reg[19]_i_32_n_6\,
O(0) => \cb_int_reg[19]_i_32_n_7\,
S(3) => \cb_int[19]_i_38_n_0\,
S(2) => \cb_int[19]_i_39_n_0\,
S(1) => \cb_int[19]_i_40_n_0\,
S(0) => \cb_int[19]_i_41_n_0\
);
\cb_int_reg[19]_i_33\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[15]_i_34_n_0\,
CO(3) => \cb_int_reg[19]_i_33_n_0\,
CO(2) => \cb_int_reg[19]_i_33_n_1\,
CO(1) => \cb_int_reg[19]_i_33_n_2\,
CO(0) => \cb_int_reg[19]_i_33_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cb_int_reg[19]_i_33_n_4\,
O(2) => \cb_int_reg[19]_i_33_n_5\,
O(1) => \cb_int_reg[19]_i_33_n_6\,
O(0) => \cb_int_reg[19]_i_33_n_7\,
S(3) => \cb_int[19]_i_42_n_0\,
S(2) => \cb_int[19]_i_43_n_0\,
S(1) => \cb_int[19]_i_44_n_0\,
S(0) => \cb_int[19]_i_45_n_0\
);
\cb_int_reg[23]_i_27\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[19]_i_32_n_0\,
CO(3) => \cb_int_reg[23]_i_27_n_0\,
CO(2) => \cb_int_reg[23]_i_27_n_1\,
CO(1) => \cb_int_reg[23]_i_27_n_2\,
CO(0) => \cb_int_reg[23]_i_27_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cb_int_reg[23]_i_27_n_4\,
O(2) => \cb_int_reg[23]_i_27_n_5\,
O(1) => \cb_int_reg[23]_i_27_n_6\,
O(0) => \cb_int_reg[23]_i_27_n_7\,
S(3) => \cb_int[23]_i_33_n_0\,
S(2) => \cb_int[23]_i_34_n_0\,
S(1) => \cb_int[23]_i_35_n_0\,
S(0) => \cb_int[23]_i_36_n_0\
);
\cb_int_reg[23]_i_28\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[19]_i_33_n_0\,
CO(3) => \cb_int_reg[23]_i_28_n_0\,
CO(2) => \cb_int_reg[23]_i_28_n_1\,
CO(1) => \cb_int_reg[23]_i_28_n_2\,
CO(0) => \cb_int_reg[23]_i_28_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cb_int_reg[23]_i_28_n_4\,
O(2) => \cb_int_reg[23]_i_28_n_5\,
O(1) => \cb_int_reg[23]_i_28_n_6\,
O(0) => \cb_int_reg[23]_i_28_n_7\,
S(3) => \cb_int[23]_i_37_n_0\,
S(2) => \cb_int[23]_i_38_n_0\,
S(1) => \cb_int[23]_i_39_n_0\,
S(0) => \cb_int[23]_i_40_n_0\
);
\cb_int_reg[31]_i_10\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[31]_i_27_n_0\,
CO(3) => \NLW_cb_int_reg[31]_i_10_CO_UNCONNECTED\(3),
CO(2) => \cb_int_reg[31]_i_10_n_1\,
CO(1) => \NLW_cb_int_reg[31]_i_10_CO_UNCONNECTED\(1),
CO(0) => \cb_int_reg[31]_i_10_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 2) => \NLW_cb_int_reg[31]_i_10_O_UNCONNECTED\(3 downto 2),
O(1) => \cb_int_reg[31]_i_10_n_6\,
O(0) => \cb_int_reg[31]_i_10_n_7\,
S(3 downto 2) => B"01",
S(1) => \cb_int[31]_i_28_n_0\,
S(0) => \cb_int[31]_i_29_n_0\
);
\cb_int_reg[31]_i_17\: unisim.vcomponents.CARRY4
port map (
CI => U0_n_75,
CO(3) => \cb_int_reg[31]_i_17_n_0\,
CO(2) => \cb_int_reg[31]_i_17_n_1\,
CO(1) => \cb_int_reg[31]_i_17_n_2\,
CO(0) => \cb_int_reg[31]_i_17_n_3\,
CYINIT => '0',
DI(3) => U0_n_14,
DI(2) => U0_n_15,
DI(1) => \cb_int[31]_i_45_n_0\,
DI(0) => \cb_int[31]_i_46_n_0\,
O(3) => \cb_int_reg[31]_i_17_n_4\,
O(2) => \cb_int_reg[31]_i_17_n_5\,
O(1) => \cb_int_reg[31]_i_17_n_6\,
O(0) => \cb_int_reg[31]_i_17_n_7\,
S(3) => \cb_int[31]_i_47_n_0\,
S(2) => \cb_int[31]_i_48_n_0\,
S(1) => \cb_int[31]_i_49_n_0\,
S(0) => \cb_int[31]_i_50_n_0\
);
\cb_int_reg[31]_i_23\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[3]_i_19_n_0\,
CO(3) => \cb_int_reg[31]_i_23_n_0\,
CO(2) => \cb_int_reg[31]_i_23_n_1\,
CO(1) => \cb_int_reg[31]_i_23_n_2\,
CO(0) => \cb_int_reg[31]_i_23_n_3\,
CYINIT => '0',
DI(3) => \cb_int[31]_i_53_n_0\,
DI(2) => \cb_int[31]_i_54_n_0\,
DI(1) => \cb_int[31]_i_55_n_0\,
DI(0) => \cb_int[31]_i_56_n_0\,
O(3) => \cb_int_reg[31]_i_23_n_4\,
O(2) => \cb_int_reg[31]_i_23_n_5\,
O(1) => \cb_int_reg[31]_i_23_n_6\,
O(0) => \cb_int_reg[31]_i_23_n_7\,
S(3) => \cb_int[31]_i_57_n_0\,
S(2) => \cb_int[31]_i_58_n_0\,
S(1) => \cb_int[31]_i_59_n_0\,
S(0) => \cb_int[31]_i_60_n_0\
);
\cb_int_reg[31]_i_27\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[31]_i_61_n_0\,
CO(3) => \cb_int_reg[31]_i_27_n_0\,
CO(2) => \cb_int_reg[31]_i_27_n_1\,
CO(1) => \cb_int_reg[31]_i_27_n_2\,
CO(0) => \cb_int_reg[31]_i_27_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cb_int_reg[31]_i_27_n_4\,
O(2) => \cb_int_reg[31]_i_27_n_5\,
O(1) => \cb_int_reg[31]_i_27_n_6\,
O(0) => \cb_int_reg[31]_i_27_n_7\,
S(3) => \cb_int[31]_i_62_n_0\,
S(2) => \cb_int[31]_i_63_n_0\,
S(1) => \cb_int[31]_i_64_n_0\,
S(0) => \cb_int[31]_i_65_n_0\
);
\cb_int_reg[31]_i_42\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[23]_i_28_n_0\,
CO(3 downto 1) => \NLW_cb_int_reg[31]_i_42_CO_UNCONNECTED\(3 downto 1),
CO(0) => \cb_int_reg[31]_i_42_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 2) => \NLW_cb_int_reg[31]_i_42_O_UNCONNECTED\(3 downto 2),
O(1) => \cb_int_reg[31]_i_42_n_6\,
O(0) => \cb_int_reg[31]_i_42_n_7\,
S(3 downto 2) => B"00",
S(1) => \cb_int[31]_i_83_n_0\,
S(0) => \cb_int[31]_i_84_n_0\
);
\cb_int_reg[31]_i_61\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[15]_i_31_n_0\,
CO(3) => \cb_int_reg[31]_i_61_n_0\,
CO(2) => \cb_int_reg[31]_i_61_n_1\,
CO(1) => \cb_int_reg[31]_i_61_n_2\,
CO(0) => \cb_int_reg[31]_i_61_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cb_int_reg[31]_i_61_n_4\,
O(2) => \cb_int_reg[31]_i_61_n_5\,
O(1) => \cb_int_reg[31]_i_61_n_6\,
O(0) => \cb_int_reg[31]_i_61_n_7\,
S(3) => \cb_int[31]_i_89_n_0\,
S(2) => \cb_int[31]_i_90_n_0\,
S(1) => \cb_int[31]_i_91_n_0\,
S(0) => \cb_int[31]_i_92_n_0\
);
\cb_int_reg[31]_i_66\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[23]_i_27_n_0\,
CO(3 downto 1) => \NLW_cb_int_reg[31]_i_66_CO_UNCONNECTED\(3 downto 1),
CO(0) => \cb_int_reg[31]_i_66_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 2) => \NLW_cb_int_reg[31]_i_66_O_UNCONNECTED\(3 downto 2),
O(1) => \cb_int_reg[31]_i_66_n_6\,
O(0) => \cb_int_reg[31]_i_66_n_7\,
S(3 downto 2) => B"00",
S(1) => \cb_int[31]_i_93_n_0\,
S(0) => \cb_int[31]_i_94_n_0\
);
\cb_int_reg[31]_i_8\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[31]_i_17_n_0\,
CO(3) => \NLW_cb_int_reg[31]_i_8_CO_UNCONNECTED\(3),
CO(2) => \cb_int_reg[31]_i_8_n_1\,
CO(1) => \cb_int_reg[31]_i_8_n_2\,
CO(0) => \cb_int_reg[31]_i_8_n_3\,
CYINIT => '0',
DI(3 downto 1) => B"000",
DI(0) => \cb_int[31]_i_18_n_0\,
O(3) => \cb_int_reg[31]_i_8_n_4\,
O(2) => \cb_int_reg[31]_i_8_n_5\,
O(1) => \cb_int_reg[31]_i_8_n_6\,
O(0) => \cb_int_reg[31]_i_8_n_7\,
S(3) => \cb_int[31]_i_19_n_0\,
S(2) => \cb_int[31]_i_20_n_0\,
S(1) => \cb_int[31]_i_21_n_0\,
S(0) => \cb_int[31]_i_22_n_0\
);
\cb_int_reg[31]_i_85\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[3]_i_68_n_0\,
CO(3) => \cb_int_reg[31]_i_85_n_0\,
CO(2) => \NLW_cb_int_reg[31]_i_85_CO_UNCONNECTED\(2),
CO(1) => \cb_int_reg[31]_i_85_n_2\,
CO(0) => \cb_int_reg[31]_i_85_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2 downto 1) => rgb888(15 downto 14),
DI(0) => '0',
O(3) => \NLW_cb_int_reg[31]_i_85_O_UNCONNECTED\(3),
O(2) => \cb_int_reg[31]_i_85_n_5\,
O(1) => \cb_int_reg[31]_i_85_n_6\,
O(0) => \cb_int_reg[31]_i_85_n_7\,
S(3) => '1',
S(2) => \cb_int[31]_i_99_n_0\,
S(1) => \cb_int[31]_i_100_n_0\,
S(0) => \cb_int[31]_i_101_n_0\
);
\cb_int_reg[31]_i_9\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[31]_i_23_n_0\,
CO(3 downto 1) => \NLW_cb_int_reg[31]_i_9_CO_UNCONNECTED\(3 downto 1),
CO(0) => \cb_int_reg[31]_i_9_n_3\,
CYINIT => '0',
DI(3 downto 1) => B"000",
DI(0) => U0_n_4,
O(3 downto 2) => \NLW_cb_int_reg[31]_i_9_O_UNCONNECTED\(3 downto 2),
O(1) => \cb_int_reg[31]_i_9_n_6\,
O(0) => \cb_int_reg[31]_i_9_n_7\,
S(3 downto 2) => B"00",
S(1) => \cb_int[31]_i_25_n_0\,
S(0) => \cb_int[31]_i_26_n_0\
);
\cb_int_reg[3]_i_19\: unisim.vcomponents.CARRY4
port map (
CI => U0_n_73,
CO(3) => \cb_int_reg[3]_i_19_n_0\,
CO(2) => \cb_int_reg[3]_i_19_n_1\,
CO(1) => \cb_int_reg[3]_i_19_n_2\,
CO(0) => \cb_int_reg[3]_i_19_n_3\,
CYINIT => '0',
DI(3) => \cb_int[3]_i_35_n_0\,
DI(2) => \cb_int[3]_i_36_n_0\,
DI(1) => \cb_int[3]_i_37_n_0\,
DI(0) => \cb_int[3]_i_38_n_0\,
O(3) => \cb_int_reg[3]_i_19_n_4\,
O(2) => \cb_int_reg[3]_i_19_n_5\,
O(1) => \cb_int_reg[3]_i_19_n_6\,
O(0) => \cb_int_reg[3]_i_19_n_7\,
S(3) => \cb_int[3]_i_39_n_0\,
S(2) => \cb_int[3]_i_40_n_0\,
S(1) => \cb_int[3]_i_41_n_0\,
S(0) => \cb_int[3]_i_42_n_0\
);
\cb_int_reg[3]_i_32\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[3]_i_58_n_0\,
CO(3) => \cb_int_reg[3]_i_32_n_0\,
CO(2) => \cb_int_reg[3]_i_32_n_1\,
CO(1) => \cb_int_reg[3]_i_32_n_2\,
CO(0) => \cb_int_reg[3]_i_32_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cb_int_reg[3]_i_32_n_4\,
O(2 downto 0) => \NLW_cb_int_reg[3]_i_32_O_UNCONNECTED\(2 downto 0),
S(3) => \cb_int[3]_i_59_n_0\,
S(2) => \cb_int[3]_i_60_n_0\,
S(1) => \cb_int[3]_i_61_n_0\,
S(0) => \cb_int[3]_i_62_n_0\
);
\cb_int_reg[3]_i_43\: unisim.vcomponents.CARRY4
port map (
CI => U0_n_74,
CO(3) => \NLW_cb_int_reg[3]_i_43_CO_UNCONNECTED\(3),
CO(2) => \cb_int_reg[3]_i_43_n_1\,
CO(1) => \NLW_cb_int_reg[3]_i_43_CO_UNCONNECTED\(1),
CO(0) => \cb_int_reg[3]_i_43_n_3\,
CYINIT => '0',
DI(3 downto 2) => B"00",
DI(1) => rgb888(7),
DI(0) => '0',
O(3 downto 2) => \NLW_cb_int_reg[3]_i_43_O_UNCONNECTED\(3 downto 2),
O(1) => \cb_int_reg[3]_i_43_n_6\,
O(0) => \cb_int_reg[3]_i_43_n_7\,
S(3 downto 2) => B"01",
S(1) => \cb_int[3]_i_73_n_0\,
S(0) => \cb_int[3]_i_74_n_0\
);
\cb_int_reg[3]_i_58\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cb_int_reg[3]_i_58_n_0\,
CO(2) => \cb_int_reg[3]_i_58_n_1\,
CO(1) => \cb_int_reg[3]_i_58_n_2\,
CO(0) => \cb_int_reg[3]_i_58_n_3\,
CYINIT => \cb_int[3]_i_84_n_0\,
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_cb_int_reg[3]_i_58_O_UNCONNECTED\(3 downto 0),
S(3) => \cb_int[3]_i_85_n_0\,
S(2) => \cb_int[3]_i_86_n_0\,
S(1) => \cb_int[3]_i_87_n_0\,
S(0) => \cb_int[3]_i_88_n_0\
);
\cb_int_reg[3]_i_68\: unisim.vcomponents.CARRY4
port map (
CI => U0_n_72,
CO(3) => \cb_int_reg[3]_i_68_n_0\,
CO(2) => \cb_int_reg[3]_i_68_n_1\,
CO(1) => \cb_int_reg[3]_i_68_n_2\,
CO(0) => \cb_int_reg[3]_i_68_n_3\,
CYINIT => '0',
DI(3 downto 0) => rgb888(12 downto 9),
O(3) => \cb_int_reg[3]_i_68_n_4\,
O(2) => \cb_int_reg[3]_i_68_n_5\,
O(1) => \cb_int_reg[3]_i_68_n_6\,
O(0) => \cb_int_reg[3]_i_68_n_7\,
S(3) => \cb_int[3]_i_95_n_0\,
S(2) => \cb_int[3]_i_96_n_0\,
S(1) => \cb_int[3]_i_97_n_0\,
S(0) => \cb_int[3]_i_98_n_0\
);
\cb_int_reg[7]_i_23\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[7]_i_26_n_0\,
CO(3) => \cb_int_reg[7]_i_23_n_0\,
CO(2) => \cb_int_reg[7]_i_23_n_1\,
CO(1) => \cb_int_reg[7]_i_23_n_2\,
CO(0) => \cb_int_reg[7]_i_23_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cb_int_reg[7]_i_23_n_4\,
O(2) => \cb_int_reg[7]_i_23_n_5\,
O(1) => \cb_int_reg[7]_i_23_n_6\,
O(0) => \cb_int_reg[7]_i_23_n_7\,
S(3) => \cb_int[7]_i_30_n_0\,
S(2) => \cb_int[7]_i_31_n_0\,
S(1) => \cb_int[7]_i_32_n_0\,
S(0) => \cb_int[7]_i_33_n_0\
);
\cb_int_reg[7]_i_24\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[7]_i_27_n_0\,
CO(3) => \cb_int_reg[7]_i_24_n_0\,
CO(2) => \cb_int_reg[7]_i_24_n_1\,
CO(1) => \cb_int_reg[7]_i_24_n_2\,
CO(0) => \cb_int_reg[7]_i_24_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cb_int_reg[7]_i_24_n_4\,
O(2) => \cb_int_reg[7]_i_24_n_5\,
O(1) => \cb_int_reg[7]_i_24_n_6\,
O(0) => \cb_int_reg[7]_i_24_n_7\,
S(3) => \cb_int[7]_i_34_n_0\,
S(2) => \cb_int[7]_i_35_n_0\,
S(1) => \cb_int[7]_i_36_n_0\,
S(0) => \cb_int[7]_i_37_n_0\
);
\cb_int_reg[7]_i_26\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cb_int_reg[7]_i_26_n_0\,
CO(2) => \cb_int_reg[7]_i_26_n_1\,
CO(1) => \cb_int_reg[7]_i_26_n_2\,
CO(0) => \cb_int_reg[7]_i_26_n_3\,
CYINIT => \cb_int[7]_i_43_n_0\,
DI(3 downto 0) => B"0000",
O(3) => \cb_int_reg[7]_i_26_n_4\,
O(2) => \cb_int_reg[7]_i_26_n_5\,
O(1) => \cb_int_reg[7]_i_26_n_6\,
O(0) => \cb_int_reg[7]_i_26_n_7\,
S(3) => \cb_int[7]_i_44_n_0\,
S(2) => \cb_int[7]_i_45_n_0\,
S(1) => \cb_int[7]_i_46_n_0\,
S(0) => \cb_int[7]_i_47_n_0\
);
\cb_int_reg[7]_i_27\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[3]_i_32_n_0\,
CO(3) => \cb_int_reg[7]_i_27_n_0\,
CO(2) => \cb_int_reg[7]_i_27_n_1\,
CO(1) => \cb_int_reg[7]_i_27_n_2\,
CO(0) => \cb_int_reg[7]_i_27_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cb_int_reg[7]_i_27_n_4\,
O(2) => \cb_int_reg[7]_i_27_n_5\,
O(1) => \cb_int_reg[7]_i_27_n_6\,
O(0) => \cb_int_reg[7]_i_27_n_7\,
S(3) => \cb_int[7]_i_48_n_0\,
S(2) => \cb_int[7]_i_49_n_0\,
S(1) => \cb_int[7]_i_50_n_0\,
S(0) => \cb_int[7]_i_51_n_0\
);
\cr_int[11]_i_61\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_17,
I1 => U0_n_26,
I2 => U0_n_35,
O => \cr_int[11]_i_61_n_0\
);
\cr_int[11]_i_62\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => U0_n_36,
I1 => U0_n_26,
I2 => U0_n_18,
O => \cr_int[11]_i_62_n_0\
);
\cr_int[11]_i_63\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => U0_n_37,
I1 => U0_n_26,
I2 => U0_n_19,
O => \cr_int[11]_i_63_n_0\
);
\cr_int[11]_i_64\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => U0_n_30,
I1 => U0_n_26,
I2 => U0_n_20,
O => \cr_int[11]_i_64_n_0\
);
\cr_int[15]_i_44\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_17,
I1 => U0_n_26,
I2 => U0_n_39,
O => \cr_int[15]_i_44_n_0\
);
\cr_int[15]_i_45\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_17,
I1 => U0_n_26,
I2 => U0_n_40,
O => \cr_int[15]_i_45_n_0\
);
\cr_int[15]_i_46\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_17,
I1 => U0_n_26,
I2 => U0_n_41,
O => \cr_int[15]_i_46_n_0\
);
\cr_int[15]_i_47\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_17,
I1 => U0_n_26,
I2 => U0_n_34,
O => \cr_int[15]_i_47_n_0\
);
\cr_int[15]_i_52\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => U0_n_29,
O => \cr_int[15]_i_52_n_0\
);
\cr_int[15]_i_53\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => U0_n_29,
O => \cr_int[15]_i_53_n_0\
);
\cr_int[15]_i_54\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => U0_n_29,
O => \cr_int[15]_i_54_n_0\
);
\cr_int[15]_i_55\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => U0_n_29,
O => \cr_int[15]_i_55_n_0\
);
\cr_int[19]_i_42\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => U0_n_29,
O => \cr_int[19]_i_42_n_0\
);
\cr_int[19]_i_43\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => U0_n_29,
O => \cr_int[19]_i_43_n_0\
);
\cr_int[19]_i_44\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => U0_n_29,
O => \cr_int[19]_i_44_n_0\
);
\cr_int[19]_i_45\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => U0_n_29,
O => \cr_int[19]_i_45_n_0\
);
\cr_int[23]_i_32\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => U0_n_29,
O => \cr_int[23]_i_32_n_0\
);
\cr_int[23]_i_33\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => U0_n_29,
O => \cr_int[23]_i_33_n_0\
);
\cr_int[23]_i_34\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => U0_n_29,
O => \cr_int[23]_i_34_n_0\
);
\cr_int[23]_i_35\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => U0_n_29,
O => \cr_int[23]_i_35_n_0\
);
\cr_int[31]_i_104\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_17,
I1 => U0_n_26,
I2 => U0_n_43,
O => \cr_int[31]_i_104_n_0\
);
\cr_int[31]_i_105\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_17,
I1 => U0_n_26,
I2 => U0_n_44,
O => \cr_int[31]_i_105_n_0\
);
\cr_int[31]_i_106\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_17,
I1 => U0_n_26,
I2 => U0_n_45,
O => \cr_int[31]_i_106_n_0\
);
\cr_int[31]_i_107\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_17,
I1 => U0_n_26,
I2 => U0_n_38,
O => \cr_int[31]_i_107_n_0\
);
\cr_int[31]_i_28\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_17,
I1 => U0_n_26,
I2 => U0_n_50,
O => \cr_int[31]_i_28_n_0\
);
\cr_int[31]_i_29\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_17,
I1 => U0_n_26,
I2 => U0_n_46,
O => \cr_int[31]_i_29_n_0\
);
\cr_int[31]_i_65\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_17,
I1 => U0_n_26,
I2 => U0_n_47,
O => \cr_int[31]_i_65_n_0\
);
\cr_int[31]_i_66\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_17,
I1 => U0_n_26,
I2 => U0_n_48,
O => \cr_int[31]_i_66_n_0\
);
\cr_int[31]_i_67\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_17,
I1 => U0_n_26,
I2 => U0_n_49,
O => \cr_int[31]_i_67_n_0\
);
\cr_int[31]_i_68\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_17,
I1 => U0_n_26,
I2 => U0_n_42,
O => \cr_int[31]_i_68_n_0\
);
\cr_int[31]_i_98\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => U0_n_29,
O => \cr_int[31]_i_98_n_0\
);
\cr_int[31]_i_99\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => U0_n_29,
O => \cr_int[31]_i_99_n_0\
);
\cr_int[7]_i_29\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => U0_n_28,
I1 => U0_n_26,
I2 => U0_n_25,
O => \cr_int[7]_i_29_n_0\
);
\cr_int[7]_i_30\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => U0_n_31,
I1 => U0_n_26,
I2 => U0_n_21,
O => \cr_int[7]_i_30_n_0\
);
\cr_int[7]_i_31\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => U0_n_32,
I1 => U0_n_26,
I2 => U0_n_22,
O => \cr_int[7]_i_31_n_0\
);
\cr_int[7]_i_32\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => U0_n_33,
I1 => U0_n_26,
I2 => U0_n_23,
O => \cr_int[7]_i_32_n_0\
);
\cr_int[7]_i_33\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => U0_n_27,
I1 => U0_n_26,
I2 => U0_n_24,
O => \cr_int[7]_i_33_n_0\
);
\cr_int_reg[11]_i_28\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[7]_i_24_n_0\,
CO(3) => \cr_int_reg[11]_i_28_n_0\,
CO(2) => \cr_int_reg[11]_i_28_n_1\,
CO(1) => \cr_int_reg[11]_i_28_n_2\,
CO(0) => \cr_int_reg[11]_i_28_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cr_int_reg[11]_i_28_n_4\,
O(2) => \cr_int_reg[11]_i_28_n_5\,
O(1) => \cr_int_reg[11]_i_28_n_6\,
O(0) => \cr_int_reg[11]_i_28_n_7\,
S(3) => \cr_int[11]_i_61_n_0\,
S(2) => \cr_int[11]_i_62_n_0\,
S(1) => \cr_int[11]_i_63_n_0\,
S(0) => \cr_int[11]_i_64_n_0\
);
\cr_int_reg[15]_i_37\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[11]_i_28_n_0\,
CO(3) => \cr_int_reg[15]_i_37_n_0\,
CO(2) => \cr_int_reg[15]_i_37_n_1\,
CO(1) => \cr_int_reg[15]_i_37_n_2\,
CO(0) => \cr_int_reg[15]_i_37_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cr_int_reg[15]_i_37_n_4\,
O(2) => \cr_int_reg[15]_i_37_n_5\,
O(1) => \cr_int_reg[15]_i_37_n_6\,
O(0) => \cr_int_reg[15]_i_37_n_7\,
S(3) => \cr_int[15]_i_44_n_0\,
S(2) => \cr_int[15]_i_45_n_0\,
S(1) => \cr_int[15]_i_46_n_0\,
S(0) => \cr_int[15]_i_47_n_0\
);
\cr_int_reg[15]_i_39\: unisim.vcomponents.CARRY4
port map (
CI => U0_n_77,
CO(3) => \cr_int_reg[15]_i_39_n_0\,
CO(2) => \cr_int_reg[15]_i_39_n_1\,
CO(1) => \cr_int_reg[15]_i_39_n_2\,
CO(0) => \cr_int_reg[15]_i_39_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cr_int_reg[15]_i_39_n_4\,
O(2) => \cr_int_reg[15]_i_39_n_5\,
O(1) => \cr_int_reg[15]_i_39_n_6\,
O(0) => \cr_int_reg[15]_i_39_n_7\,
S(3) => \cr_int[15]_i_52_n_0\,
S(2) => \cr_int[15]_i_53_n_0\,
S(1) => \cr_int[15]_i_54_n_0\,
S(0) => \cr_int[15]_i_55_n_0\
);
\cr_int_reg[19]_i_37\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[15]_i_39_n_0\,
CO(3) => \cr_int_reg[19]_i_37_n_0\,
CO(2) => \cr_int_reg[19]_i_37_n_1\,
CO(1) => \cr_int_reg[19]_i_37_n_2\,
CO(0) => \cr_int_reg[19]_i_37_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cr_int_reg[19]_i_37_n_4\,
O(2) => \cr_int_reg[19]_i_37_n_5\,
O(1) => \cr_int_reg[19]_i_37_n_6\,
O(0) => \cr_int_reg[19]_i_37_n_7\,
S(3) => \cr_int[19]_i_42_n_0\,
S(2) => \cr_int[19]_i_43_n_0\,
S(1) => \cr_int[19]_i_44_n_0\,
S(0) => \cr_int[19]_i_45_n_0\
);
\cr_int_reg[23]_i_31\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[19]_i_37_n_0\,
CO(3) => \cr_int_reg[23]_i_31_n_0\,
CO(2) => \cr_int_reg[23]_i_31_n_1\,
CO(1) => \cr_int_reg[23]_i_31_n_2\,
CO(0) => \cr_int_reg[23]_i_31_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cr_int_reg[23]_i_31_n_4\,
O(2) => \cr_int_reg[23]_i_31_n_5\,
O(1) => \cr_int_reg[23]_i_31_n_6\,
O(0) => \cr_int_reg[23]_i_31_n_7\,
S(3) => \cr_int[23]_i_32_n_0\,
S(2) => \cr_int[23]_i_33_n_0\,
S(1) => \cr_int[23]_i_34_n_0\,
S(0) => \cr_int[23]_i_35_n_0\
);
\cr_int_reg[31]_i_10\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[31]_i_27_n_0\,
CO(3) => \NLW_cr_int_reg[31]_i_10_CO_UNCONNECTED\(3),
CO(2) => \cr_int_reg[31]_i_10_n_1\,
CO(1) => \NLW_cr_int_reg[31]_i_10_CO_UNCONNECTED\(1),
CO(0) => \cr_int_reg[31]_i_10_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 2) => \NLW_cr_int_reg[31]_i_10_O_UNCONNECTED\(3 downto 2),
O(1) => \cr_int_reg[31]_i_10_n_6\,
O(0) => \cr_int_reg[31]_i_10_n_7\,
S(3 downto 2) => B"01",
S(1) => \cr_int[31]_i_28_n_0\,
S(0) => \cr_int[31]_i_29_n_0\
);
\cr_int_reg[31]_i_27\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[31]_i_64_n_0\,
CO(3) => \cr_int_reg[31]_i_27_n_0\,
CO(2) => \cr_int_reg[31]_i_27_n_1\,
CO(1) => \cr_int_reg[31]_i_27_n_2\,
CO(0) => \cr_int_reg[31]_i_27_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cr_int_reg[31]_i_27_n_4\,
O(2) => \cr_int_reg[31]_i_27_n_5\,
O(1) => \cr_int_reg[31]_i_27_n_6\,
O(0) => \cr_int_reg[31]_i_27_n_7\,
S(3) => \cr_int[31]_i_65_n_0\,
S(2) => \cr_int[31]_i_66_n_0\,
S(1) => \cr_int[31]_i_67_n_0\,
S(0) => \cr_int[31]_i_68_n_0\
);
\cr_int_reg[31]_i_54\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[23]_i_31_n_0\,
CO(3 downto 1) => \NLW_cr_int_reg[31]_i_54_CO_UNCONNECTED\(3 downto 1),
CO(0) => \cr_int_reg[31]_i_54_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 2) => \NLW_cr_int_reg[31]_i_54_O_UNCONNECTED\(3 downto 2),
O(1) => \cr_int_reg[31]_i_54_n_6\,
O(0) => \cr_int_reg[31]_i_54_n_7\,
S(3 downto 2) => B"00",
S(1) => \cr_int[31]_i_98_n_0\,
S(0) => \cr_int[31]_i_99_n_0\
);
\cr_int_reg[31]_i_64\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[15]_i_37_n_0\,
CO(3) => \cr_int_reg[31]_i_64_n_0\,
CO(2) => \cr_int_reg[31]_i_64_n_1\,
CO(1) => \cr_int_reg[31]_i_64_n_2\,
CO(0) => \cr_int_reg[31]_i_64_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cr_int_reg[31]_i_64_n_4\,
O(2) => \cr_int_reg[31]_i_64_n_5\,
O(1) => \cr_int_reg[31]_i_64_n_6\,
O(0) => \cr_int_reg[31]_i_64_n_7\,
S(3) => \cr_int[31]_i_104_n_0\,
S(2) => \cr_int[31]_i_105_n_0\,
S(1) => \cr_int[31]_i_106_n_0\,
S(0) => \cr_int[31]_i_107_n_0\
);
\cr_int_reg[7]_i_24\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cr_int_reg[7]_i_24_n_0\,
CO(2) => \cr_int_reg[7]_i_24_n_1\,
CO(1) => \cr_int_reg[7]_i_24_n_2\,
CO(0) => \cr_int_reg[7]_i_24_n_3\,
CYINIT => \cr_int[7]_i_29_n_0\,
DI(3 downto 0) => B"0000",
O(3) => \cr_int_reg[7]_i_24_n_4\,
O(2) => \cr_int_reg[7]_i_24_n_5\,
O(1) => \cr_int_reg[7]_i_24_n_6\,
O(0) => \cr_int_reg[7]_i_24_n_7\,
S(3) => \cr_int[7]_i_30_n_0\,
S(2) => \cr_int[7]_i_31_n_0\,
S(1) => \cr_int[7]_i_32_n_0\,
S(0) => \cr_int[7]_i_33_n_0\
);
\y_int[11]_i_54\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_9_n_5\,
O => \y_int[11]_i_54_n_0\
);
\y_int[11]_i_55\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_9_n_6\,
O => \y_int[11]_i_55_n_0\
);
\y_int[11]_i_56\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_9_n_7\,
O => \y_int[11]_i_56_n_0\
);
\y_int[11]_i_57\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_21_n_4\,
O => \y_int[11]_i_57_n_0\
);
\y_int[15]_i_36\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_9_n_5\,
O => \y_int[15]_i_36_n_0\
);
\y_int[15]_i_37\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_9_n_5\,
O => \y_int[15]_i_37_n_0\
);
\y_int[15]_i_38\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_9_n_5\,
O => \y_int[15]_i_38_n_0\
);
\y_int[15]_i_39\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_9_n_5\,
O => \y_int[15]_i_39_n_0\
);
\y_int[15]_i_44\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_55,
I1 => U0_n_56,
I2 => U0_n_68,
O => \y_int[15]_i_44_n_0\
);
\y_int[15]_i_45\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_55,
I1 => U0_n_56,
I2 => U0_n_69,
O => \y_int[15]_i_45_n_0\
);
\y_int[15]_i_46\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_55,
I1 => U0_n_56,
I2 => U0_n_70,
O => \y_int[15]_i_46_n_0\
);
\y_int[15]_i_47\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_55,
I1 => U0_n_56,
I2 => U0_n_71,
O => \y_int[15]_i_47_n_0\
);
\y_int[19]_i_36\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_9_n_5\,
O => \y_int[19]_i_36_n_0\
);
\y_int[19]_i_37\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_9_n_5\,
O => \y_int[19]_i_37_n_0\
);
\y_int[19]_i_38\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_9_n_5\,
O => \y_int[19]_i_38_n_0\
);
\y_int[19]_i_39\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_9_n_5\,
O => \y_int[19]_i_39_n_0\
);
\y_int[19]_i_40\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \y_int_reg[31]_i_9_n_5\,
I1 => U0_n_57,
I2 => \y_int_reg[19]_i_24_n_5\,
O => \y_int[19]_i_40_n_0\
);
\y_int[19]_i_41\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \y_int_reg[31]_i_9_n_5\,
I1 => U0_n_57,
I2 => \y_int_reg[19]_i_24_n_6\,
O => \y_int[19]_i_41_n_0\
);
\y_int[19]_i_42\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \y_int_reg[31]_i_9_n_5\,
I1 => U0_n_57,
I2 => \y_int_reg[19]_i_24_n_7\,
O => \y_int[19]_i_42_n_0\
);
\y_int[19]_i_43\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \y_int_reg[31]_i_9_n_5\,
I1 => U0_n_57,
I2 => \y_int_reg[15]_i_24_n_4\,
O => \y_int[19]_i_43_n_0\
);
\y_int[19]_i_44\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_55,
I1 => U0_n_56,
I2 => U0_n_64,
O => \y_int[19]_i_44_n_0\
);
\y_int[19]_i_45\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_55,
I1 => U0_n_56,
I2 => U0_n_65,
O => \y_int[19]_i_45_n_0\
);
\y_int[19]_i_46\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_55,
I1 => U0_n_56,
I2 => U0_n_66,
O => \y_int[19]_i_46_n_0\
);
\y_int[19]_i_47\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_55,
I1 => U0_n_56,
I2 => U0_n_67,
O => \y_int[19]_i_47_n_0\
);
\y_int[23]_i_50\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_9_n_5\,
O => \y_int[23]_i_50_n_0\
);
\y_int[23]_i_58\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_9_n_5\,
O => \y_int[23]_i_58_n_0\
);
\y_int[23]_i_59\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_9_n_5\,
O => \y_int[23]_i_59_n_0\
);
\y_int[23]_i_60\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_9_n_5\,
O => \y_int[23]_i_60_n_0\
);
\y_int[23]_i_61\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_9_n_5\,
O => \y_int[23]_i_61_n_0\
);
\y_int[31]_i_100\: unisim.vcomponents.LUT4
generic map(
INIT => X"D22D"
)
port map (
I0 => rgb888(3),
I1 => rgb888(1),
I2 => rgb888(4),
I3 => rgb888(2),
O => \y_int[31]_i_100_n_0\
);
\y_int[31]_i_102\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(15),
O => \y_int[31]_i_102_n_0\
);
\y_int[31]_i_103\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(15),
I1 => rgb888(14),
O => \y_int[31]_i_103_n_0\
);
\y_int[31]_i_22\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => rgb888(15),
I1 => \y_int[31]_i_56_n_0\,
O => \y_int[31]_i_22_n_0\
);
\y_int[31]_i_23\: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => rgb888(15),
I1 => \y_int[31]_i_57_n_0\,
I2 => rgb888(14),
O => \y_int[31]_i_23_n_0\
);
\y_int[31]_i_24\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => rgb888(15),
I1 => \y_int[31]_i_56_n_0\,
O => \y_int[31]_i_24_n_0\
);
\y_int[31]_i_25\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(15),
O => \y_int[31]_i_25_n_0\
);
\y_int[31]_i_26\: unisim.vcomponents.LUT3
generic map(
INIT => X"15"
)
port map (
I0 => rgb888(15),
I1 => rgb888(14),
I2 => \y_int[31]_i_57_n_0\,
O => \y_int[31]_i_26_n_0\
);
\y_int[31]_i_28\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \y_int_reg[31]_i_9_n_5\,
I1 => U0_n_57,
I2 => \y_int_reg[23]_i_32_n_7\,
O => \y_int[31]_i_28_n_0\
);
\y_int[31]_i_29\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \y_int_reg[31]_i_9_n_5\,
I1 => U0_n_57,
I2 => \y_int_reg[23]_i_35_n_4\,
O => \y_int[31]_i_29_n_0\
);
\y_int[31]_i_38\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_55,
I1 => U0_n_56,
I2 => U0_n_58,
O => \y_int[31]_i_38_n_0\
);
\y_int[31]_i_39\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_55,
I1 => U0_n_56,
I2 => U0_n_59,
O => \y_int[31]_i_39_n_0\
);
\y_int[31]_i_48\: unisim.vcomponents.LUT4
generic map(
INIT => X"1002"
)
port map (
I0 => rgb888(14),
I1 => rgb888(15),
I2 => \y_int[31]_i_80_n_0\,
I3 => rgb888(13),
O => \y_int[31]_i_48_n_0\
);
\y_int[31]_i_49\: unisim.vcomponents.LUT5
generic map(
INIT => X"81560042"
)
port map (
I0 => rgb888(13),
I1 => rgb888(12),
I2 => \y_int[31]_i_81_n_0\,
I3 => rgb888(15),
I4 => \y_int_reg[31]_i_82_n_1\,
O => \y_int[31]_i_49_n_0\
);
\y_int[31]_i_50\: unisim.vcomponents.LUT6
generic map(
INIT => X"A8A8A88A80808008"
)
port map (
I0 => \y_int[31]_i_83_n_0\,
I1 => rgb888(14),
I2 => rgb888(11),
I3 => rgb888(9),
I4 => rgb888(10),
I5 => \y_int_reg[31]_i_82_n_6\,
O => \y_int[31]_i_50_n_0\
);
\y_int[31]_i_51\: unisim.vcomponents.LUT6
generic map(
INIT => X"9696966996000069"
)
port map (
I0 => rgb888(14),
I1 => rgb888(11),
I2 => \y_int_reg[31]_i_82_n_6\,
I3 => rgb888(9),
I4 => rgb888(10),
I5 => rgb888(13),
O => \y_int[31]_i_51_n_0\
);
\y_int[31]_i_52\: unisim.vcomponents.LUT4
generic map(
INIT => X"6559"
)
port map (
I0 => \y_int[31]_i_48_n_0\,
I1 => rgb888(15),
I2 => \y_int[31]_i_57_n_0\,
I3 => rgb888(14),
O => \y_int[31]_i_52_n_0\
);
\y_int[31]_i_53\: unisim.vcomponents.LUT6
generic map(
INIT => X"6CCCCCC9CCCCC993"
)
port map (
I0 => \y_int_reg[31]_i_82_n_1\,
I1 => rgb888(14),
I2 => rgb888(12),
I3 => \y_int[31]_i_81_n_0\,
I4 => rgb888(13),
I5 => rgb888(15),
O => \y_int[31]_i_53_n_0\
);
\y_int[31]_i_54\: unisim.vcomponents.LUT6
generic map(
INIT => X"366C6CC96CC9C993"
)
port map (
I0 => \y_int[31]_i_84_n_0\,
I1 => rgb888(13),
I2 => \y_int[31]_i_81_n_0\,
I3 => rgb888(12),
I4 => rgb888(15),
I5 => \y_int_reg[31]_i_82_n_1\,
O => \y_int[31]_i_54_n_0\
);
\y_int[31]_i_55\: unisim.vcomponents.LUT5
generic map(
INIT => X"99969666"
)
port map (
I0 => \y_int[31]_i_51_n_0\,
I1 => \y_int[31]_i_83_n_0\,
I2 => \y_int_reg[31]_i_82_n_6\,
I3 => \y_int[31]_i_85_n_0\,
I4 => rgb888(14),
O => \y_int[31]_i_55_n_0\
);
\y_int[31]_i_56\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => rgb888(13),
I1 => rgb888(11),
I2 => rgb888(9),
I3 => rgb888(10),
I4 => rgb888(12),
I5 => rgb888(14),
O => \y_int[31]_i_56_n_0\
);
\y_int[31]_i_57\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => rgb888(12),
I1 => rgb888(10),
I2 => rgb888(9),
I3 => rgb888(11),
I4 => rgb888(13),
O => \y_int[31]_i_57_n_0\
);
\y_int[31]_i_58\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \y_int_reg[31]_i_9_n_5\,
I1 => U0_n_57,
I2 => \y_int_reg[23]_i_35_n_5\,
O => \y_int[31]_i_58_n_0\
);
\y_int[31]_i_59\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \y_int_reg[31]_i_9_n_5\,
I1 => U0_n_57,
I2 => \y_int_reg[23]_i_35_n_6\,
O => \y_int[31]_i_59_n_0\
);
\y_int[31]_i_60\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \y_int_reg[31]_i_9_n_5\,
I1 => U0_n_57,
I2 => \y_int_reg[23]_i_35_n_7\,
O => \y_int[31]_i_60_n_0\
);
\y_int[31]_i_61\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \y_int_reg[31]_i_9_n_5\,
I1 => U0_n_57,
I2 => \y_int_reg[19]_i_24_n_4\,
O => \y_int[31]_i_61_n_0\
);
\y_int[31]_i_72\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => rgb888(5),
I1 => rgb888(7),
O => \y_int[31]_i_72_n_0\
);
\y_int[31]_i_73\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(6),
I1 => rgb888(7),
O => \y_int[31]_i_73_n_0\
);
\y_int[31]_i_74\: unisim.vcomponents.LUT3
generic map(
INIT => X"D2"
)
port map (
I0 => rgb888(7),
I1 => rgb888(5),
I2 => rgb888(6),
O => \y_int[31]_i_74_n_0\
);
\y_int[31]_i_76\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_55,
I1 => U0_n_56,
I2 => U0_n_60,
O => \y_int[31]_i_76_n_0\
);
\y_int[31]_i_77\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_55,
I1 => U0_n_56,
I2 => U0_n_61,
O => \y_int[31]_i_77_n_0\
);
\y_int[31]_i_78\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_55,
I1 => U0_n_56,
I2 => U0_n_62,
O => \y_int[31]_i_78_n_0\
);
\y_int[31]_i_79\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_55,
I1 => U0_n_56,
I2 => U0_n_63,
O => \y_int[31]_i_79_n_0\
);
\y_int[31]_i_80\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => rgb888(11),
I1 => rgb888(9),
I2 => rgb888(10),
I3 => rgb888(12),
O => \y_int[31]_i_80_n_0\
);
\y_int[31]_i_81\: unisim.vcomponents.LUT3
generic map(
INIT => X"FE"
)
port map (
I0 => rgb888(10),
I1 => rgb888(9),
I2 => rgb888(11),
O => \y_int[31]_i_81_n_0\
);
\y_int[31]_i_83\: unisim.vcomponents.LUT6
generic map(
INIT => X"6666666999999996"
)
port map (
I0 => \y_int_reg[31]_i_82_n_1\,
I1 => rgb888(15),
I2 => rgb888(11),
I3 => rgb888(9),
I4 => rgb888(10),
I5 => rgb888(12),
O => \y_int[31]_i_83_n_0\
);
\y_int[31]_i_84\: unisim.vcomponents.LUT5
generic map(
INIT => X"FEABA802"
)
port map (
I0 => \y_int_reg[31]_i_82_n_6\,
I1 => rgb888(10),
I2 => rgb888(9),
I3 => rgb888(11),
I4 => rgb888(14),
O => \y_int[31]_i_84_n_0\
);
\y_int[31]_i_85\: unisim.vcomponents.LUT3
generic map(
INIT => X"E1"
)
port map (
I0 => rgb888(10),
I1 => rgb888(9),
I2 => rgb888(11),
O => \y_int[31]_i_85_n_0\
);
\y_int[31]_i_93\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => rgb888(4),
I1 => rgb888(6),
O => \y_int[31]_i_93_n_0\
);
\y_int[31]_i_94\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => rgb888(3),
I1 => rgb888(5),
O => \y_int[31]_i_94_n_0\
);
\y_int[31]_i_95\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => rgb888(2),
I1 => rgb888(4),
O => \y_int[31]_i_95_n_0\
);
\y_int[31]_i_96\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => rgb888(1),
I1 => rgb888(3),
O => \y_int[31]_i_96_n_0\
);
\y_int[31]_i_97\: unisim.vcomponents.LUT4
generic map(
INIT => X"D22D"
)
port map (
I0 => rgb888(6),
I1 => rgb888(4),
I2 => rgb888(7),
I3 => rgb888(5),
O => \y_int[31]_i_97_n_0\
);
\y_int[31]_i_98\: unisim.vcomponents.LUT4
generic map(
INIT => X"D22D"
)
port map (
I0 => rgb888(5),
I1 => rgb888(3),
I2 => rgb888(6),
I3 => rgb888(4),
O => \y_int[31]_i_98_n_0\
);
\y_int[31]_i_99\: unisim.vcomponents.LUT4
generic map(
INIT => X"D22D"
)
port map (
I0 => rgb888(4),
I1 => rgb888(2),
I2 => rgb888(5),
I3 => rgb888(3),
O => \y_int[31]_i_99_n_0\
);
\y_int[3]_i_37\: unisim.vcomponents.LUT4
generic map(
INIT => X"8228"
)
port map (
I0 => \y_int_reg[31]_i_82_n_7\,
I1 => rgb888(9),
I2 => rgb888(10),
I3 => rgb888(13),
O => \y_int[3]_i_37_n_0\
);
\y_int[3]_i_38\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => rgb888(9),
I1 => rgb888(10),
I2 => rgb888(13),
I3 => \y_int_reg[31]_i_82_n_7\,
O => \y_int[3]_i_38_n_0\
);
\y_int[3]_i_39\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => \y_int_reg[3]_i_40_n_4\,
I1 => rgb888(9),
I2 => rgb888(12),
O => \y_int[3]_i_39_n_0\
);
\y_int[3]_i_41\: unisim.vcomponents.LUT5
generic map(
INIT => X"99969699"
)
port map (
I0 => \y_int[3]_i_37_n_0\,
I1 => \y_int[3]_i_79_n_0\,
I2 => rgb888(13),
I3 => rgb888(10),
I4 => rgb888(9),
O => \y_int[3]_i_41_n_0\
);
\y_int[3]_i_42\: unisim.vcomponents.LUT6
generic map(
INIT => X"9669696969696996"
)
port map (
I0 => \y_int_reg[31]_i_82_n_7\,
I1 => rgb888(13),
I2 => rgb888(10),
I3 => rgb888(12),
I4 => \y_int_reg[3]_i_40_n_4\,
I5 => rgb888(9),
O => \y_int[3]_i_42_n_0\
);
\y_int[3]_i_43\: unisim.vcomponents.LUT5
generic map(
INIT => X"96696969"
)
port map (
I0 => rgb888(12),
I1 => rgb888(9),
I2 => \y_int_reg[3]_i_40_n_4\,
I3 => rgb888(11),
I4 => rgb888(8),
O => \y_int[3]_i_43_n_0\
);
\y_int[3]_i_44\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => rgb888(8),
I1 => rgb888(11),
I2 => \y_int_reg[3]_i_40_n_5\,
O => \y_int[3]_i_44_n_0\
);
\y_int[3]_i_46\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[3]_i_19_n_5\,
O => \y_int[3]_i_46_n_0\
);
\y_int[3]_i_47\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[3]_i_19_n_6\,
O => \y_int[3]_i_47_n_0\
);
\y_int[3]_i_48\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[3]_i_19_n_7\,
O => \y_int[3]_i_48_n_0\
);
\y_int[3]_i_49\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => U0_n_51,
O => \y_int[3]_i_49_n_0\
);
\y_int[3]_i_75\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(15),
I1 => rgb888(13),
O => \y_int[3]_i_75_n_0\
);
\y_int[3]_i_76\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(12),
I1 => rgb888(14),
O => \y_int[3]_i_76_n_0\
);
\y_int[3]_i_77\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(11),
I1 => rgb888(13),
O => \y_int[3]_i_77_n_0\
);
\y_int[3]_i_78\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(10),
I1 => rgb888(12),
O => \y_int[3]_i_78_n_0\
);
\y_int[3]_i_79\: unisim.vcomponents.LUT5
generic map(
INIT => X"A95656A9"
)
port map (
I0 => \y_int_reg[31]_i_82_n_6\,
I1 => rgb888(10),
I2 => rgb888(9),
I3 => rgb888(11),
I4 => rgb888(14),
O => \y_int[3]_i_79_n_0\
);
\y_int[3]_i_80\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => U0_n_52,
O => \y_int[3]_i_80_n_0\
);
\y_int[3]_i_81\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => U0_n_53,
O => \y_int[3]_i_81_n_0\
);
\y_int[3]_i_82\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => U0_n_54,
O => \y_int[3]_i_82_n_0\
);
\y_int[3]_i_83\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[3]_i_70_n_6\,
O => \y_int[3]_i_83_n_0\
);
\y_int[3]_i_93\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(9),
I1 => rgb888(11),
O => \y_int[3]_i_93_n_0\
);
\y_int[3]_i_94\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(8),
I1 => rgb888(10),
O => \y_int[3]_i_94_n_0\
);
\y_int[3]_i_95\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(9),
O => \y_int[3]_i_95_n_0\
);
\y_int[3]_i_96\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => rgb888(8),
O => \y_int[3]_i_96_n_0\
);
\y_int[7]_i_25\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_21_n_5\,
O => \y_int[7]_i_25_n_0\
);
\y_int[7]_i_26\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_21_n_6\,
O => \y_int[7]_i_26_n_0\
);
\y_int[7]_i_27\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_21_n_7\,
O => \y_int[7]_i_27_n_0\
);
\y_int[7]_i_28\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[3]_i_19_n_4\,
O => \y_int[7]_i_28_n_0\
);
\y_int_reg[11]_i_27\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[7]_i_23_n_0\,
CO(3) => \y_int_reg[11]_i_27_n_0\,
CO(2) => \y_int_reg[11]_i_27_n_1\,
CO(1) => \y_int_reg[11]_i_27_n_2\,
CO(0) => \y_int_reg[11]_i_27_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \y_int_reg[11]_i_27_n_4\,
O(2) => \y_int_reg[11]_i_27_n_5\,
O(1) => \y_int_reg[11]_i_27_n_6\,
O(0) => \y_int_reg[11]_i_27_n_7\,
S(3) => \y_int[11]_i_54_n_0\,
S(2) => \y_int[11]_i_55_n_0\,
S(1) => \y_int[11]_i_56_n_0\,
S(0) => \y_int[11]_i_57_n_0\
);
\y_int_reg[15]_i_24\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[11]_i_27_n_0\,
CO(3) => \y_int_reg[15]_i_24_n_0\,
CO(2) => \y_int_reg[15]_i_24_n_1\,
CO(1) => \y_int_reg[15]_i_24_n_2\,
CO(0) => \y_int_reg[15]_i_24_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \y_int_reg[15]_i_24_n_4\,
O(2) => \y_int_reg[15]_i_24_n_5\,
O(1) => \y_int_reg[15]_i_24_n_6\,
O(0) => \y_int_reg[15]_i_24_n_7\,
S(3) => \y_int[15]_i_36_n_0\,
S(2) => \y_int[15]_i_37_n_0\,
S(1) => \y_int[15]_i_38_n_0\,
S(0) => \y_int[15]_i_39_n_0\
);
\y_int_reg[15]_i_34\: unisim.vcomponents.CARRY4
port map (
CI => U0_n_81,
CO(3) => \y_int_reg[15]_i_34_n_0\,
CO(2) => \y_int_reg[15]_i_34_n_1\,
CO(1) => \y_int_reg[15]_i_34_n_2\,
CO(0) => \y_int_reg[15]_i_34_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => y_int_reg2(12 downto 9),
S(3) => \y_int[15]_i_44_n_0\,
S(2) => \y_int[15]_i_45_n_0\,
S(1) => \y_int[15]_i_46_n_0\,
S(0) => \y_int[15]_i_47_n_0\
);
\y_int_reg[19]_i_24\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[15]_i_24_n_0\,
CO(3) => \y_int_reg[19]_i_24_n_0\,
CO(2) => \y_int_reg[19]_i_24_n_1\,
CO(1) => \y_int_reg[19]_i_24_n_2\,
CO(0) => \y_int_reg[19]_i_24_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \y_int_reg[19]_i_24_n_4\,
O(2) => \y_int_reg[19]_i_24_n_5\,
O(1) => \y_int_reg[19]_i_24_n_6\,
O(0) => \y_int_reg[19]_i_24_n_7\,
S(3) => \y_int[19]_i_36_n_0\,
S(2) => \y_int[19]_i_37_n_0\,
S(1) => \y_int[19]_i_38_n_0\,
S(0) => \y_int[19]_i_39_n_0\
);
\y_int_reg[19]_i_33\: unisim.vcomponents.CARRY4
port map (
CI => U0_n_79,
CO(3) => \y_int_reg[19]_i_33_n_0\,
CO(2) => \y_int_reg[19]_i_33_n_1\,
CO(1) => \y_int_reg[19]_i_33_n_2\,
CO(0) => \y_int_reg[19]_i_33_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \y_int_reg[19]_i_33_n_4\,
O(2) => \y_int_reg[19]_i_33_n_5\,
O(1) => \y_int_reg[19]_i_33_n_6\,
O(0) => \y_int_reg[19]_i_33_n_7\,
S(3) => \y_int[19]_i_40_n_0\,
S(2) => \y_int[19]_i_41_n_0\,
S(1) => \y_int[19]_i_42_n_0\,
S(0) => \y_int[19]_i_43_n_0\
);
\y_int_reg[19]_i_34\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[15]_i_34_n_0\,
CO(3) => \y_int_reg[19]_i_34_n_0\,
CO(2) => \y_int_reg[19]_i_34_n_1\,
CO(1) => \y_int_reg[19]_i_34_n_2\,
CO(0) => \y_int_reg[19]_i_34_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => y_int_reg2(16 downto 13),
S(3) => \y_int[19]_i_44_n_0\,
S(2) => \y_int[19]_i_45_n_0\,
S(1) => \y_int[19]_i_46_n_0\,
S(0) => \y_int[19]_i_47_n_0\
);
\y_int_reg[23]_i_32\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[23]_i_35_n_0\,
CO(3 downto 0) => \NLW_y_int_reg[23]_i_32_CO_UNCONNECTED\(3 downto 0),
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 1) => \NLW_y_int_reg[23]_i_32_O_UNCONNECTED\(3 downto 1),
O(0) => \y_int_reg[23]_i_32_n_7\,
S(3 downto 1) => B"000",
S(0) => \y_int[23]_i_50_n_0\
);
\y_int_reg[23]_i_35\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[19]_i_24_n_0\,
CO(3) => \y_int_reg[23]_i_35_n_0\,
CO(2) => \y_int_reg[23]_i_35_n_1\,
CO(1) => \y_int_reg[23]_i_35_n_2\,
CO(0) => \y_int_reg[23]_i_35_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \y_int_reg[23]_i_35_n_4\,
O(2) => \y_int_reg[23]_i_35_n_5\,
O(1) => \y_int_reg[23]_i_35_n_6\,
O(0) => \y_int_reg[23]_i_35_n_7\,
S(3) => \y_int[23]_i_58_n_0\,
S(2) => \y_int[23]_i_59_n_0\,
S(1) => \y_int[23]_i_60_n_0\,
S(0) => \y_int[23]_i_61_n_0\
);
\y_int_reg[31]_i_10\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[31]_i_27_n_0\,
CO(3) => \NLW_y_int_reg[31]_i_10_CO_UNCONNECTED\(3),
CO(2) => \y_int_reg[31]_i_10_n_1\,
CO(1) => \NLW_y_int_reg[31]_i_10_CO_UNCONNECTED\(1),
CO(0) => \y_int_reg[31]_i_10_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 2) => \NLW_y_int_reg[31]_i_10_O_UNCONNECTED\(3 downto 2),
O(1) => \y_int_reg[31]_i_10_n_6\,
O(0) => \y_int_reg[31]_i_10_n_7\,
S(3 downto 2) => B"01",
S(1) => \y_int[31]_i_28_n_0\,
S(0) => \y_int[31]_i_29_n_0\
);
\y_int_reg[31]_i_12\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[31]_i_37_n_0\,
CO(3) => \NLW_y_int_reg[31]_i_12_CO_UNCONNECTED\(3),
CO(2) => \y_int_reg[31]_i_12_n_1\,
CO(1) => \NLW_y_int_reg[31]_i_12_CO_UNCONNECTED\(1),
CO(0) => \y_int_reg[31]_i_12_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 2) => \NLW_y_int_reg[31]_i_12_O_UNCONNECTED\(3 downto 2),
O(1 downto 0) => y_int_reg2(22 downto 21),
S(3 downto 2) => B"01",
S(1) => \y_int[31]_i_38_n_0\,
S(0) => \y_int[31]_i_39_n_0\
);
\y_int_reg[31]_i_21\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[3]_i_19_n_0\,
CO(3) => \y_int_reg[31]_i_21_n_0\,
CO(2) => \y_int_reg[31]_i_21_n_1\,
CO(1) => \y_int_reg[31]_i_21_n_2\,
CO(0) => \y_int_reg[31]_i_21_n_3\,
CYINIT => '0',
DI(3) => \y_int[31]_i_48_n_0\,
DI(2) => \y_int[31]_i_49_n_0\,
DI(1) => \y_int[31]_i_50_n_0\,
DI(0) => \y_int[31]_i_51_n_0\,
O(3) => \y_int_reg[31]_i_21_n_4\,
O(2) => \y_int_reg[31]_i_21_n_5\,
O(1) => \y_int_reg[31]_i_21_n_6\,
O(0) => \y_int_reg[31]_i_21_n_7\,
S(3) => \y_int[31]_i_52_n_0\,
S(2) => \y_int[31]_i_53_n_0\,
S(1) => \y_int[31]_i_54_n_0\,
S(0) => \y_int[31]_i_55_n_0\
);
\y_int_reg[31]_i_27\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[19]_i_33_n_0\,
CO(3) => \y_int_reg[31]_i_27_n_0\,
CO(2) => \y_int_reg[31]_i_27_n_1\,
CO(1) => \y_int_reg[31]_i_27_n_2\,
CO(0) => \y_int_reg[31]_i_27_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \y_int_reg[31]_i_27_n_4\,
O(2) => \y_int_reg[31]_i_27_n_5\,
O(1) => \y_int_reg[31]_i_27_n_6\,
O(0) => \y_int_reg[31]_i_27_n_7\,
S(3) => \y_int[31]_i_58_n_0\,
S(2) => \y_int[31]_i_59_n_0\,
S(1) => \y_int[31]_i_60_n_0\,
S(0) => \y_int[31]_i_61_n_0\
);
\y_int_reg[31]_i_31\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[31]_i_71_n_0\,
CO(3 downto 2) => \NLW_y_int_reg[31]_i_31_CO_UNCONNECTED\(3 downto 2),
CO(1) => \y_int_reg[31]_i_31_n_2\,
CO(0) => \y_int_reg[31]_i_31_n_3\,
CYINIT => '0',
DI(3 downto 2) => B"00",
DI(1) => rgb888(6),
DI(0) => \y_int[31]_i_72_n_0\,
O(3) => \NLW_y_int_reg[31]_i_31_O_UNCONNECTED\(3),
O(2) => \y_int_reg[31]_i_31_n_5\,
O(1) => \y_int_reg[31]_i_31_n_6\,
O(0) => \y_int_reg[31]_i_31_n_7\,
S(3 downto 2) => B"01",
S(1) => \y_int[31]_i_73_n_0\,
S(0) => \y_int[31]_i_74_n_0\
);
\y_int_reg[31]_i_37\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[19]_i_34_n_0\,
CO(3) => \y_int_reg[31]_i_37_n_0\,
CO(2) => \y_int_reg[31]_i_37_n_1\,
CO(1) => \y_int_reg[31]_i_37_n_2\,
CO(0) => \y_int_reg[31]_i_37_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => y_int_reg2(20 downto 17),
S(3) => \y_int[31]_i_76_n_0\,
S(2) => \y_int[31]_i_77_n_0\,
S(1) => \y_int[31]_i_78_n_0\,
S(0) => \y_int[31]_i_79_n_0\
);
\y_int_reg[31]_i_71\: unisim.vcomponents.CARRY4
port map (
CI => U0_n_80,
CO(3) => \y_int_reg[31]_i_71_n_0\,
CO(2) => \y_int_reg[31]_i_71_n_1\,
CO(1) => \y_int_reg[31]_i_71_n_2\,
CO(0) => \y_int_reg[31]_i_71_n_3\,
CYINIT => '0',
DI(3) => \y_int[31]_i_93_n_0\,
DI(2) => \y_int[31]_i_94_n_0\,
DI(1) => \y_int[31]_i_95_n_0\,
DI(0) => \y_int[31]_i_96_n_0\,
O(3) => \y_int_reg[31]_i_71_n_4\,
O(2) => \y_int_reg[31]_i_71_n_5\,
O(1) => \y_int_reg[31]_i_71_n_6\,
O(0) => \y_int_reg[31]_i_71_n_7\,
S(3) => \y_int[31]_i_97_n_0\,
S(2) => \y_int[31]_i_98_n_0\,
S(1) => \y_int[31]_i_99_n_0\,
S(0) => \y_int[31]_i_100_n_0\
);
\y_int_reg[31]_i_82\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[3]_i_40_n_0\,
CO(3) => \NLW_y_int_reg[31]_i_82_CO_UNCONNECTED\(3),
CO(2) => \y_int_reg[31]_i_82_n_1\,
CO(1) => \NLW_y_int_reg[31]_i_82_CO_UNCONNECTED\(1),
CO(0) => \y_int_reg[31]_i_82_n_3\,
CYINIT => '0',
DI(3 downto 2) => B"00",
DI(1 downto 0) => rgb888(15 downto 14),
O(3 downto 2) => \NLW_y_int_reg[31]_i_82_O_UNCONNECTED\(3 downto 2),
O(1) => \y_int_reg[31]_i_82_n_6\,
O(0) => \y_int_reg[31]_i_82_n_7\,
S(3 downto 2) => B"01",
S(1) => \y_int[31]_i_102_n_0\,
S(0) => \y_int[31]_i_103_n_0\
);
\y_int_reg[31]_i_9\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[31]_i_21_n_0\,
CO(3 downto 2) => \NLW_y_int_reg[31]_i_9_CO_UNCONNECTED\(3 downto 2),
CO(1) => \y_int_reg[31]_i_9_n_2\,
CO(0) => \y_int_reg[31]_i_9_n_3\,
CYINIT => '0',
DI(3 downto 2) => B"00",
DI(1) => \y_int[31]_i_22_n_0\,
DI(0) => \y_int[31]_i_23_n_0\,
O(3) => \NLW_y_int_reg[31]_i_9_O_UNCONNECTED\(3),
O(2) => \y_int_reg[31]_i_9_n_5\,
O(1) => \y_int_reg[31]_i_9_n_6\,
O(0) => \y_int_reg[31]_i_9_n_7\,
S(3) => '0',
S(2) => \y_int[31]_i_24_n_0\,
S(1) => \y_int[31]_i_25_n_0\,
S(0) => \y_int[31]_i_26_n_0\
);
\y_int_reg[3]_i_19\: unisim.vcomponents.CARRY4
port map (
CI => U0_n_78,
CO(3) => \y_int_reg[3]_i_19_n_0\,
CO(2) => \y_int_reg[3]_i_19_n_1\,
CO(1) => \y_int_reg[3]_i_19_n_2\,
CO(0) => \y_int_reg[3]_i_19_n_3\,
CYINIT => '0',
DI(3) => \y_int[3]_i_37_n_0\,
DI(2) => \y_int[3]_i_38_n_0\,
DI(1) => \y_int[3]_i_39_n_0\,
DI(0) => \y_int_reg[3]_i_40_n_5\,
O(3) => \y_int_reg[3]_i_19_n_4\,
O(2) => \y_int_reg[3]_i_19_n_5\,
O(1) => \y_int_reg[3]_i_19_n_6\,
O(0) => \y_int_reg[3]_i_19_n_7\,
S(3) => \y_int[3]_i_41_n_0\,
S(2) => \y_int[3]_i_42_n_0\,
S(1) => \y_int[3]_i_43_n_0\,
S(0) => \y_int[3]_i_44_n_0\
);
\y_int_reg[3]_i_20\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[3]_i_45_n_0\,
CO(3) => \y_int_reg[3]_i_20_n_0\,
CO(2) => \y_int_reg[3]_i_20_n_1\,
CO(1) => \y_int_reg[3]_i_20_n_2\,
CO(0) => \y_int_reg[3]_i_20_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \y_int_reg[3]_i_20_n_4\,
O(2) => \y_int_reg[3]_i_20_n_5\,
O(1 downto 0) => \NLW_y_int_reg[3]_i_20_O_UNCONNECTED\(1 downto 0),
S(3) => \y_int[3]_i_46_n_0\,
S(2) => \y_int[3]_i_47_n_0\,
S(1) => \y_int[3]_i_48_n_0\,
S(0) => \y_int[3]_i_49_n_0\
);
\y_int_reg[3]_i_40\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[3]_i_70_n_0\,
CO(3) => \y_int_reg[3]_i_40_n_0\,
CO(2) => \y_int_reg[3]_i_40_n_1\,
CO(1) => \y_int_reg[3]_i_40_n_2\,
CO(0) => \y_int_reg[3]_i_40_n_3\,
CYINIT => '0',
DI(3) => rgb888(15),
DI(2 downto 0) => rgb888(12 downto 10),
O(3) => \y_int_reg[3]_i_40_n_4\,
O(2) => \y_int_reg[3]_i_40_n_5\,
O(1) => \y_int_reg[3]_i_40_n_6\,
O(0) => \y_int_reg[3]_i_40_n_7\,
S(3) => \y_int[3]_i_75_n_0\,
S(2) => \y_int[3]_i_76_n_0\,
S(1) => \y_int[3]_i_77_n_0\,
S(0) => \y_int[3]_i_78_n_0\
);
\y_int_reg[3]_i_45\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \y_int_reg[3]_i_45_n_0\,
CO(2) => \y_int_reg[3]_i_45_n_1\,
CO(1) => \y_int_reg[3]_i_45_n_2\,
CO(0) => \y_int_reg[3]_i_45_n_3\,
CYINIT => \cb_int[3]_i_84_n_0\,
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_y_int_reg[3]_i_45_O_UNCONNECTED\(3 downto 0),
S(3) => \y_int[3]_i_80_n_0\,
S(2) => \y_int[3]_i_81_n_0\,
S(1) => \y_int[3]_i_82_n_0\,
S(0) => \y_int[3]_i_83_n_0\
);
\y_int_reg[3]_i_70\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \y_int_reg[3]_i_70_n_0\,
CO(2) => \y_int_reg[3]_i_70_n_1\,
CO(1) => \y_int_reg[3]_i_70_n_2\,
CO(0) => \y_int_reg[3]_i_70_n_3\,
CYINIT => '0',
DI(3 downto 2) => rgb888(9 downto 8),
DI(1 downto 0) => B"01",
O(3) => \y_int_reg[3]_i_70_n_4\,
O(2) => \y_int_reg[3]_i_70_n_5\,
O(1) => \y_int_reg[3]_i_70_n_6\,
O(0) => \NLW_y_int_reg[3]_i_70_O_UNCONNECTED\(0),
S(3) => \y_int[3]_i_93_n_0\,
S(2) => \y_int[3]_i_94_n_0\,
S(1) => \y_int[3]_i_95_n_0\,
S(0) => \y_int[3]_i_96_n_0\
);
\y_int_reg[7]_i_23\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[3]_i_20_n_0\,
CO(3) => \y_int_reg[7]_i_23_n_0\,
CO(2) => \y_int_reg[7]_i_23_n_1\,
CO(1) => \y_int_reg[7]_i_23_n_2\,
CO(0) => \y_int_reg[7]_i_23_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \y_int_reg[7]_i_23_n_4\,
O(2) => \y_int_reg[7]_i_23_n_5\,
O(1) => \y_int_reg[7]_i_23_n_6\,
O(0) => \y_int_reg[7]_i_23_n_7\,
S(3) => \y_int[7]_i_25_n_0\,
S(2) => \y_int[7]_i_26_n_0\,
S(1) => \y_int[7]_i_27_n_0\,
S(0) => \y_int[7]_i_28_n_0\
);
end STRUCTURE;
| mit |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_dual_fusion/zed_dual_fusion.srcs/sources_1/bd/system/ip/system_ov7670_vga_0_0/synth/system_ov7670_vga_0_0.vhd | 5 | 3941 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:ov7670_vga:1.0
-- IP Revision: 19
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_ov7670_vga_0_0 IS
PORT (
clk_x2 : IN STD_LOGIC;
active : IN STD_LOGIC;
data : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
rgb : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END system_ov7670_vga_0_0;
ARCHITECTURE system_ov7670_vga_0_0_arch OF system_ov7670_vga_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_ov7670_vga_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT ov7670_vga IS
PORT (
clk_x2 : IN STD_LOGIC;
active : IN STD_LOGIC;
data : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
rgb : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END COMPONENT ov7670_vga;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF system_ov7670_vga_0_0_arch: ARCHITECTURE IS "ov7670_vga,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF system_ov7670_vga_0_0_arch : ARCHITECTURE IS "system_ov7670_vga_0_0,ov7670_vga,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF system_ov7670_vga_0_0_arch: ARCHITECTURE IS "system_ov7670_vga_0_0,ov7670_vga,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=user,x_ipName=ov7670_vga,x_ipVersion=1.0,x_ipCoreRevision=19,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF active: SIGNAL IS "xilinx.com:signal:clock:1.0 clk CLK";
BEGIN
U0 : ov7670_vga
PORT MAP (
clk_x2 => clk_x2,
active => active,
data => data,
rgb => rgb
);
END system_ov7670_vga_0_0_arch;
| mit |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_dual_fusion/zed_dual_fusion.srcs/sources_1/bd/system/ip/system_vga_buffer_1_0/system_vga_buffer_1_0_sim_netlist.vhdl | 1 | 14056 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Wed May 31 03:26:46 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- C:/ZyboIP/examples/zed_dual_fusion/zed_dual_fusion.srcs/sources_1/bd/system/ip/system_vga_buffer_1_0/system_vga_buffer_1_0_sim_netlist.vhdl
-- Design : system_vga_buffer_1_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_vga_buffer_1_0_vga_buffer is
port (
data_r : out STD_LOGIC_VECTOR ( 23 downto 0 );
clk_w : in STD_LOGIC;
clk_r : in STD_LOGIC;
wen : in STD_LOGIC;
data_w : in STD_LOGIC_VECTOR ( 23 downto 0 );
x_addr_w : in STD_LOGIC_VECTOR ( 9 downto 0 );
x_addr_r : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_vga_buffer_1_0_vga_buffer : entity is "vga_buffer";
end system_vga_buffer_1_0_vga_buffer;
architecture STRUCTURE of system_vga_buffer_1_0_vga_buffer is
signal addr_r : STD_LOGIC_VECTOR ( 9 downto 0 );
signal addr_w : STD_LOGIC_VECTOR ( 9 downto 0 );
signal c_addr_r : STD_LOGIC_VECTOR ( 9 downto 0 );
signal c_addr_w : STD_LOGIC_VECTOR ( 9 downto 0 );
signal NLW_data_reg_CASCADEOUTA_UNCONNECTED : STD_LOGIC;
signal NLW_data_reg_CASCADEOUTB_UNCONNECTED : STD_LOGIC;
signal NLW_data_reg_DBITERR_UNCONNECTED : STD_LOGIC;
signal NLW_data_reg_INJECTDBITERR_UNCONNECTED : STD_LOGIC;
signal NLW_data_reg_INJECTSBITERR_UNCONNECTED : STD_LOGIC;
signal NLW_data_reg_SBITERR_UNCONNECTED : STD_LOGIC;
signal NLW_data_reg_DOADO_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_data_reg_DOBDO_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 24 );
signal NLW_data_reg_DOPADOP_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_data_reg_DOPBDOP_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_data_reg_ECCPARITY_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_data_reg_RDADDRECC_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of data_reg : label is "INDEPENDENT";
attribute \MEM.PORTA.DATA_BIT_LAYOUT\ : string;
attribute \MEM.PORTA.DATA_BIT_LAYOUT\ of data_reg : label is "p0_d24";
attribute \MEM.PORTB.DATA_BIT_LAYOUT\ : string;
attribute \MEM.PORTB.DATA_BIT_LAYOUT\ of data_reg : label is "p0_d24";
attribute METHODOLOGY_DRC_VIOS : string;
attribute METHODOLOGY_DRC_VIOS of data_reg : label is "{SYNTH-6 {cell *THIS*}}";
attribute RTL_RAM_BITS : integer;
attribute RTL_RAM_BITS of data_reg : label is 24576;
attribute RTL_RAM_NAME : string;
attribute RTL_RAM_NAME of data_reg : label is "data";
attribute bram_addr_begin : integer;
attribute bram_addr_begin of data_reg : label is 0;
attribute bram_addr_end : integer;
attribute bram_addr_end of data_reg : label is 1023;
attribute bram_slice_begin : integer;
attribute bram_slice_begin of data_reg : label is 0;
attribute bram_slice_end : integer;
attribute bram_slice_end of data_reg : label is 23;
begin
\addr_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk_r,
CE => '1',
D => c_addr_r(0),
Q => addr_r(0),
R => '0'
);
\addr_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk_r,
CE => '1',
D => c_addr_r(1),
Q => addr_r(1),
R => '0'
);
\addr_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk_r,
CE => '1',
D => c_addr_r(2),
Q => addr_r(2),
R => '0'
);
\addr_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk_r,
CE => '1',
D => c_addr_r(3),
Q => addr_r(3),
R => '0'
);
\addr_r_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk_r,
CE => '1',
D => c_addr_r(4),
Q => addr_r(4),
R => '0'
);
\addr_r_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk_r,
CE => '1',
D => c_addr_r(5),
Q => addr_r(5),
R => '0'
);
\addr_r_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk_r,
CE => '1',
D => c_addr_r(6),
Q => addr_r(6),
R => '0'
);
\addr_r_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk_r,
CE => '1',
D => c_addr_r(7),
Q => addr_r(7),
R => '0'
);
\addr_r_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk_r,
CE => '1',
D => c_addr_r(8),
Q => addr_r(8),
R => '0'
);
\addr_r_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk_r,
CE => '1',
D => c_addr_r(9),
Q => addr_r(9),
R => '0'
);
\addr_w_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk_w,
CE => wen,
D => c_addr_w(0),
Q => addr_w(0),
R => '0'
);
\addr_w_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk_w,
CE => wen,
D => c_addr_w(1),
Q => addr_w(1),
R => '0'
);
\addr_w_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk_w,
CE => wen,
D => c_addr_w(2),
Q => addr_w(2),
R => '0'
);
\addr_w_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk_w,
CE => wen,
D => c_addr_w(3),
Q => addr_w(3),
R => '0'
);
\addr_w_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk_w,
CE => wen,
D => c_addr_w(4),
Q => addr_w(4),
R => '0'
);
\addr_w_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk_w,
CE => wen,
D => c_addr_w(5),
Q => addr_w(5),
R => '0'
);
\addr_w_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk_w,
CE => wen,
D => c_addr_w(6),
Q => addr_w(6),
R => '0'
);
\addr_w_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk_w,
CE => wen,
D => c_addr_w(7),
Q => addr_w(7),
R => '0'
);
\addr_w_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk_w,
CE => wen,
D => c_addr_w(8),
Q => addr_w(8),
R => '0'
);
\addr_w_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk_w,
CE => wen,
D => c_addr_w(9),
Q => addr_w(9),
R => '0'
);
\c_addr_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk_r,
CE => '1',
D => x_addr_r(0),
Q => c_addr_r(0),
R => '0'
);
\c_addr_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk_r,
CE => '1',
D => x_addr_r(1),
Q => c_addr_r(1),
R => '0'
);
\c_addr_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk_r,
CE => '1',
D => x_addr_r(2),
Q => c_addr_r(2),
R => '0'
);
\c_addr_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk_r,
CE => '1',
D => x_addr_r(3),
Q => c_addr_r(3),
R => '0'
);
\c_addr_r_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk_r,
CE => '1',
D => x_addr_r(4),
Q => c_addr_r(4),
R => '0'
);
\c_addr_r_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk_r,
CE => '1',
D => x_addr_r(5),
Q => c_addr_r(5),
R => '0'
);
\c_addr_r_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk_r,
CE => '1',
D => x_addr_r(6),
Q => c_addr_r(6),
R => '0'
);
\c_addr_r_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk_r,
CE => '1',
D => x_addr_r(7),
Q => c_addr_r(7),
R => '0'
);
\c_addr_r_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk_r,
CE => '1',
D => x_addr_r(8),
Q => c_addr_r(8),
R => '0'
);
\c_addr_r_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk_r,
CE => '1',
D => x_addr_r(9),
Q => c_addr_r(9),
R => '0'
);
\c_addr_w_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk_w,
CE => wen,
D => x_addr_w(0),
Q => c_addr_w(0),
R => '0'
);
\c_addr_w_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk_w,
CE => wen,
D => x_addr_w(1),
Q => c_addr_w(1),
R => '0'
);
\c_addr_w_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk_w,
CE => wen,
D => x_addr_w(2),
Q => c_addr_w(2),
R => '0'
);
\c_addr_w_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk_w,
CE => wen,
D => x_addr_w(3),
Q => c_addr_w(3),
R => '0'
);
\c_addr_w_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk_w,
CE => wen,
D => x_addr_w(4),
Q => c_addr_w(4),
R => '0'
);
\c_addr_w_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk_w,
CE => wen,
D => x_addr_w(5),
Q => c_addr_w(5),
R => '0'
);
\c_addr_w_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk_w,
CE => wen,
D => x_addr_w(6),
Q => c_addr_w(6),
R => '0'
);
\c_addr_w_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk_w,
CE => wen,
D => x_addr_w(7),
Q => c_addr_w(7),
R => '0'
);
\c_addr_w_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk_w,
CE => wen,
D => x_addr_w(8),
Q => c_addr_w(8),
R => '0'
);
\c_addr_w_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk_w,
CE => wen,
D => x_addr_w(9),
Q => c_addr_w(9),
R => '0'
);
data_reg: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INIT_A => X"000000000",
INIT_B => X"000000000",
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 36,
READ_WIDTH_B => 36,
RSTREG_PRIORITY_A => "RSTREG",
RSTREG_PRIORITY_B => "RSTREG",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "NO_CHANGE",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 36,
WRITE_WIDTH_B => 36
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 5) => addr_w(9 downto 0),
ADDRARDADDR(4 downto 0) => B"11111",
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 5) => addr_r(9 downto 0),
ADDRBWRADDR(4 downto 0) => B"11111",
CASCADEINA => '1',
CASCADEINB => '1',
CASCADEOUTA => NLW_data_reg_CASCADEOUTA_UNCONNECTED,
CASCADEOUTB => NLW_data_reg_CASCADEOUTB_UNCONNECTED,
CLKARDCLK => clk_w,
CLKBWRCLK => clk_r,
DBITERR => NLW_data_reg_DBITERR_UNCONNECTED,
DIADI(31 downto 24) => B"00000000",
DIADI(23 downto 0) => data_w(23 downto 0),
DIBDI(31 downto 0) => B"00000000111111111111111111111111",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 0) => NLW_data_reg_DOADO_UNCONNECTED(31 downto 0),
DOBDO(31 downto 24) => NLW_data_reg_DOBDO_UNCONNECTED(31 downto 24),
DOBDO(23 downto 0) => data_r(23 downto 0),
DOPADOP(3 downto 0) => NLW_data_reg_DOPADOP_UNCONNECTED(3 downto 0),
DOPBDOP(3 downto 0) => NLW_data_reg_DOPBDOP_UNCONNECTED(3 downto 0),
ECCPARITY(7 downto 0) => NLW_data_reg_ECCPARITY_UNCONNECTED(7 downto 0),
ENARDEN => wen,
ENBWREN => '1',
INJECTDBITERR => NLW_data_reg_INJECTDBITERR_UNCONNECTED,
INJECTSBITERR => NLW_data_reg_INJECTSBITERR_UNCONNECTED,
RDADDRECC(8 downto 0) => NLW_data_reg_RDADDRECC_UNCONNECTED(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => NLW_data_reg_SBITERR_UNCONNECTED,
WEA(3 downto 0) => B"1111",
WEBWE(7 downto 0) => B"00000000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_vga_buffer_1_0 is
port (
clk_w : in STD_LOGIC;
clk_r : in STD_LOGIC;
wen : in STD_LOGIC;
x_addr_w : in STD_LOGIC_VECTOR ( 9 downto 0 );
y_addr_w : in STD_LOGIC_VECTOR ( 9 downto 0 );
x_addr_r : in STD_LOGIC_VECTOR ( 9 downto 0 );
y_addr_r : in STD_LOGIC_VECTOR ( 9 downto 0 );
data_w : in STD_LOGIC_VECTOR ( 23 downto 0 );
data_r : out STD_LOGIC_VECTOR ( 23 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_vga_buffer_1_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_vga_buffer_1_0 : entity is "system_vga_buffer_1_0,vga_buffer,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_vga_buffer_1_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_vga_buffer_1_0 : entity is "vga_buffer,Vivado 2016.4";
end system_vga_buffer_1_0;
architecture STRUCTURE of system_vga_buffer_1_0 is
begin
U0: entity work.system_vga_buffer_1_0_vga_buffer
port map (
clk_r => clk_r,
clk_w => clk_w,
data_r(23 downto 0) => data_r(23 downto 0),
data_w(23 downto 0) => data_w(23 downto 0),
wen => wen,
x_addr_r(9 downto 0) => x_addr_r(9 downto 0),
x_addr_w(9 downto 0) => x_addr_w(9 downto 0)
);
end STRUCTURE;
| mit |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | general_ip/svd_2x2/svd_2x2.srcs/sources_1/ip/arctan/demo_tb/tb_arctan.vhd | 1 | 15570 | --------------------------------------------------------------------------------
-- (c) Copyright 2011 - 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
-- Description:
-- This is an example testbench for the CORDIC IP core.
-- The testbench has been generated by Vivado to accompany the IP core
-- instance you have generated.
--
-- This testbench is for demonstration purposes only. See note below for
-- instructions on how to use it with your core.
--
-- See the CORDIC product guide for further information
-- about this core.
--
--------------------------------------------------------------------------------
-- Using this testbench
--
-- This testbench instantiates your generated CORDIC core
-- instance named "arctan".
--
-- Use Vivado's Run Simulation flow to run this testbench. See the Vivado
-- documentation for details.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
entity tb_arctan is
end tb_arctan;
architecture tb of tb_arctan is
-----------------------------------------------------------------------
-- Timing constants
-----------------------------------------------------------------------
constant CLOCK_PERIOD : time := 100 ns;
constant T_HOLD : time := 10 ns;
constant T_STROBE : time := CLOCK_PERIOD - (1 ns);
constant TEST_CYCLES : integer := 3000;
constant PHASE_CYCLES : integer := 1000;
-----------------------------------------------------------------------
-- DUT input signals
-----------------------------------------------------------------------
-- General inputs
signal aclk : std_logic := '0'; -- the master clock
-- Slave channel CARTESIAN inputs
signal s_axis_cartesian_tvalid : std_logic := '0'; -- TVALID for channel S_AXIS_CARTESIAN
signal s_axis_cartesian_tdata : std_logic_vector(31 downto 0) := (others => 'X'); -- TDATA for channel S_AXIS_CARTESIAN
-- Slave channel PHASE inputs
signal s_axis_phase_tvalid : std_logic := '0'; -- TVALID for channel S_AXIS_PHASE
signal s_axis_phase_tdata : std_logic_vector(15 downto 0) := (others => 'X'); -- TDATA for channel S_AXIS_PHASE
-----------------------------------------------------------------------
-- DUT output signals
-----------------------------------------------------------------------
-- Master channel DOUT outputs
signal m_axis_dout_tvalid : std_logic := '0'; -- TVALID for channel M_AXIS_DOUT
signal m_axis_dout_tdata : std_logic_vector(15 downto 0) := (others => '0'); -- TDATA for channel M_AXIS_DOUT
-----------------------------------------------------------------------
-- Aliases for AXI channel TDATA fields
-- These are a convenience for viewing data in a simulator waveform viewer.
-- If using ModelSim or Questa, add "-voptargs=+acc=n" to the vsim command
-- to prevent the simulator optimizing away these signals.
-----------------------------------------------------------------------
signal s_axis_cartesian_tdata_real : std_logic_vector(15 downto 0) := (others => '0');
signal s_axis_cartesian_tdata_imag : std_logic_vector(15 downto 0) := (others => '0');
signal s_axis_phase_tdata_real : std_logic_vector(15 downto 0) := (others => '0');
signal m_axis_dout_tdata_real : std_logic_vector(15 downto 0) := (others => '0');
signal m_axis_dout_tdata_imag : std_logic_vector(15 downto 0) := (others => '0');
signal m_axis_dout_tdata_phase : std_logic_vector(15 downto 0) := (others => '0');
-----------------------------------------------------------------------
-- Testbench signals
-----------------------------------------------------------------------
signal cycles : integer := 0; -- Clock cycle counter
-----------------------------------------------------------------------
-- Constants, types and functions to create input data
-- The CORDIC is fed two sinusoids exp(+/-jwt) of different frequencies and amplitudes:
-- channel CARTESIAN: exp(+jwt), frequency = clock / 30,
-- channel PHASE: exp(-jwt), frequency = clock / 32,
-----------------------------------------------------------------------
constant IP_CARTESIAN_DEPTH : integer := 30;
constant IP_CARTESIAN_WIDTH : integer := 16;
constant IP_CARTESIAN_SHIFT : integer := 3; -- bit shift for amplitude
constant IP_PHASE_DEPTH : integer := 32;
constant IP_PHASE_WIDTH : integer := 16;
constant IP_PHASE_SHIFT : integer := 0; -- no bit shift, max amplitude
type T_IP_INT_ENTRY is record
re : integer;
im : integer;
end record;
type T_IP_CARTESIAN_ENTRY is record
re : std_logic_vector(IP_CARTESIAN_WIDTH-1 downto 0);
im : std_logic_vector(IP_CARTESIAN_WIDTH-1 downto 0);
end record;
type T_IP_PHASE_ENTRY is record
re : std_logic_vector(IP_PHASE_WIDTH-1 downto 0);
end record;
type T_IP_CARTESIAN_TABLE is array (0 to IP_CARTESIAN_DEPTH-1) of T_IP_CARTESIAN_ENTRY;
type T_IP_PHASE_TABLE is array (0 to IP_PHASE_DEPTH-1) of T_IP_PHASE_ENTRY;
-- Common function to calculate sine and cosine values
function create_ip_entry(index, depth, width : integer) return T_IP_INT_ENTRY is
variable result : T_IP_INT_ENTRY;
variable theta : real;
variable limited_width : integer := width - 2;
begin
if limited_width > 30 then
limited_width := 30; --avoid integer overflow
end if;
theta := real(index) / real(depth) * 2.0 * MATH_PI;
result.re := integer(round(cos(theta) * real(2**limited_width)));
result.im := integer(round(sin(theta) * real(2**limited_width)));
return result;
end function create_ip_entry;
-- Use separate functions to calculate channel S_AXIS_CARTESIAN and S_AXIS_PHASE sinusoids as they return different types
function create_ip_cartesian_table return T_IP_CARTESIAN_TABLE is
variable result : T_IP_CARTESIAN_TABLE;
variable entry_int : T_IP_INT_ENTRY;
begin
for i in 0 to IP_CARTESIAN_DEPTH-1 loop
entry_int := create_ip_entry(i, IP_CARTESIAN_DEPTH, IP_CARTESIAN_WIDTH - IP_CARTESIAN_SHIFT);
result(i).re := std_logic_vector(to_signed(entry_int.re, IP_CARTESIAN_WIDTH));
result(i).im := std_logic_vector(to_signed(entry_int.im, IP_CARTESIAN_WIDTH));
end loop;
return result;
end function create_ip_cartesian_table;
function create_ip_phase_table return T_IP_PHASE_TABLE is
variable result : T_IP_PHASE_TABLE;
variable entry_int : T_IP_INT_ENTRY;
begin
for i in 0 to IP_PHASE_DEPTH-1 loop
entry_int := create_ip_entry(IP_PHASE_DEPTH-1-i, IP_PHASE_DEPTH, IP_PHASE_WIDTH - IP_PHASE_SHIFT); -- note rotation direction
result(i).re := std_logic_vector(to_signed(entry_int.re, IP_PHASE_WIDTH));
end loop;
return result;
end function create_ip_phase_table;
-- Call the functions to create the data
constant IP_CARTESIAN_DATA : T_IP_CARTESIAN_TABLE := create_ip_cartesian_table;
constant IP_PHASE_DATA : T_IP_PHASE_TABLE := create_ip_phase_table;
begin
-----------------------------------------------------------------------
-- Instantiate the DUT
-----------------------------------------------------------------------
dut : entity work.arctan
port map (
aclk => aclk,
s_axis_cartesian_tvalid => s_axis_cartesian_tvalid,
s_axis_cartesian_tdata => s_axis_cartesian_tdata,
m_axis_dout_tvalid => m_axis_dout_tvalid,
m_axis_dout_tdata => m_axis_dout_tdata
);
-----------------------------------------------------------------------
-- Generate clock
-----------------------------------------------------------------------
clock_gen : process
begin
aclk <= '0';
wait for CLOCK_PERIOD;
loop
cycles <= cycles + 1;
aclk <= '0';
wait for CLOCK_PERIOD/2;
aclk <= '1';
wait for CLOCK_PERIOD/2;
if cycles >= TEST_CYCLES then
report "Not a real failure. Simulation finished successfully. Test completed successfully" severity failure;
wait;
end if;
end loop;
end process clock_gen;
-----------------------------------------------------------------------
-- Generate inputs
-----------------------------------------------------------------------
stimuli : process
variable ip_cartesian_index : integer := 0;
variable ip_phase_index : integer := 0;
variable cartesian_tvalid_nxt : std_logic := '0';
variable phase_tvalid_nxt : std_logic := '0';
variable phase2_cycles : integer := 1;
variable phase2_count : integer := 0;
constant PHASE2_LIMIT : integer := 30;
begin
-- Test is stopped in clock_gen process, use endless loop here
loop
-- Drive inputs T_HOLD time after rising edge of clock
wait until rising_edge(aclk);
wait for T_HOLD;
-- Drive AXI TVALID signals to demonstrate different types of operation
case cycles is -- do different types of operation at different phases of the test
when 0 to PHASE_CYCLES * 1 - 1 =>
-- Phase 1: inputs always valid, no missing input data
cartesian_tvalid_nxt := '1';
phase_tvalid_nxt := '1';
when PHASE_CYCLES * 1 to PHASE_CYCLES * 2 - 1 =>
-- Phase 2: deprive channel S_AXIS_CARTESIAN of valid transactions at an increasing rate
phase_tvalid_nxt := '1';
if phase2_count < phase2_cycles then
cartesian_tvalid_nxt := '0';
else
cartesian_tvalid_nxt := '1';
end if;
phase2_count := phase2_count + 1;
if phase2_count >= PHASE2_LIMIT then
phase2_count := 0;
phase2_cycles := phase2_cycles + 1;
end if;
when PHASE_CYCLES * 2 to PHASE_CYCLES * 3 - 1 =>
-- Phase 3: deprive channel S_AXIS_CARTESIAN of 1 out of 2 transactions, and channel S_AXIS_PHASE of 1 out of 3 transactions
if cycles mod 2 = 0 then
cartesian_tvalid_nxt := '0';
else
cartesian_tvalid_nxt := '1';
end if;
if cycles mod 3 = 0 then
phase_tvalid_nxt := '0';
else
phase_tvalid_nxt := '1';
end if;
when others =>
-- Test will stop imminently - do nothing
null;
end case;
-- Drive handshake signals with local variable values
s_axis_cartesian_tvalid <= cartesian_tvalid_nxt;
s_axis_phase_tvalid <= phase_tvalid_nxt;
-- Drive AXI slave channel CARTESIAN payload
-- Drive 'X's on payload signals when not valid
if cartesian_tvalid_nxt /= '1' then
s_axis_cartesian_tdata <= (others => 'X');
else
-- TDATA: Real and imaginary components are each 16 bits wide and byte-aligned at their LSBs
s_axis_cartesian_tdata(15 downto 0) <= IP_CARTESIAN_DATA(ip_cartesian_index).re;
s_axis_cartesian_tdata(31 downto 16) <= IP_CARTESIAN_DATA(ip_cartesian_index).im;
end if;
-- Drive AXI slave channel PHASE payload
-- Drive 'X's on payload signals when not valid
if phase_tvalid_nxt /= '1' then
s_axis_phase_tdata <= (others => 'X');
else
-- TDATA: Real component is 16 bits wide and byte-aligned at its LSBs
s_axis_phase_tdata(15 downto 0) <= IP_PHASE_DATA(ip_phase_index).re;
end if;
-- Increment input data indices
if cartesian_tvalid_nxt = '1' then
ip_cartesian_index := ip_cartesian_index + 1;
if ip_cartesian_index = IP_CARTESIAN_DEPTH then
ip_cartesian_index := 0;
end if;
end if;
if phase_tvalid_nxt = '1' then
ip_phase_index := ip_phase_index + 1;
if ip_phase_index = IP_PHASE_DEPTH then
ip_phase_index := 0;
end if;
end if;
end loop;
end process stimuli;
-----------------------------------------------------------------------
-- Check outputs
-----------------------------------------------------------------------
check_outputs : process
variable check_ok : boolean := true;
begin
-- Check outputs T_STROBE time after rising edge of clock
wait until rising_edge(aclk);
wait for T_STROBE;
-- Do not check the output payload values, as this requires the behavioral model
-- which would make this demonstration testbench unwieldy.
-- Instead, check the protocol of the DOUT channel:
-- check that the payload is valid (not X) when TVALID is high
if m_axis_dout_tvalid = '1' then
if is_x(m_axis_dout_tdata) then
report "ERROR: m_axis_dout_tdata is invalid when m_axis_dout_tvalid is high" severity error;
check_ok := false;
end if;
end if;
assert check_ok
report "ERROR: terminating test with failures." severity failure;
end process check_outputs;
-----------------------------------------------------------------------
-- Assign TDATA fields to aliases, for easy simulator waveform viewing
-----------------------------------------------------------------------
s_axis_cartesian_tdata_real <= s_axis_cartesian_tdata(15 downto 0);
s_axis_cartesian_tdata_imag <= s_axis_cartesian_tdata(31 downto 16);
m_axis_dout_tdata_phase <= m_axis_dout_tdata(15 downto 0);
end tb;
| mit |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_dual_fusion/zed_dual_fusion.srcs/sources_1/bd/system/ip/system_buffer_register_0_0/system_buffer_register_0_0_stub.vhdl | 1 | 1392 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Tue May 30 22:30:26 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub -rename_top system_buffer_register_0_0 -prefix
-- system_buffer_register_0_0_ system_buffer_register_1_0_stub.vhdl
-- Design : system_buffer_register_1_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity system_buffer_register_0_0 is
Port (
clk : in STD_LOGIC;
val_in : in STD_LOGIC_VECTOR ( 31 downto 0 );
val_out : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
end system_buffer_register_0_0;
architecture stub of system_buffer_register_0_0 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clk,val_in[31:0],val_out[31:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "buffer_register,Vivado 2016.4";
begin
end;
| mit |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_dual_fusion/zed_dual_fusion.srcs/sources_1/bd/system/ip/system_clk_wiz_0_0/system_clk_wiz_0_0_sim_netlist.vhdl | 2 | 7148 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Sun May 28 19:58:38 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim -rename_top system_clk_wiz_0_0 -prefix
-- system_clk_wiz_0_0_ system_clk_wiz_0_0_sim_netlist.vhdl
-- Design : system_clk_wiz_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_clk_wiz_0_0_system_clk_wiz_0_0_clk_wiz is
port (
clk_out1 : out STD_LOGIC;
locked : out STD_LOGIC;
clk_in1 : in STD_LOGIC
);
end system_clk_wiz_0_0_system_clk_wiz_0_0_clk_wiz;
architecture STRUCTURE of system_clk_wiz_0_0_system_clk_wiz_0_0_clk_wiz is
signal clk_in1_system_clk_wiz_0_0 : STD_LOGIC;
signal clk_out1_system_clk_wiz_0_0 : STD_LOGIC;
signal clkfbout_buf_system_clk_wiz_0_0 : STD_LOGIC;
signal clkfbout_system_clk_wiz_0_0 : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_DRDY_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_PSDONE_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_DO_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
attribute BOX_TYPE : string;
attribute BOX_TYPE of clkf_buf : label is "PRIMITIVE";
attribute BOX_TYPE of clkin1_ibufg : label is "PRIMITIVE";
attribute CAPACITANCE : string;
attribute CAPACITANCE of clkin1_ibufg : label is "DONT_CARE";
attribute IBUF_DELAY_VALUE : string;
attribute IBUF_DELAY_VALUE of clkin1_ibufg : label is "0";
attribute IFD_DELAY_VALUE : string;
attribute IFD_DELAY_VALUE of clkin1_ibufg : label is "AUTO";
attribute BOX_TYPE of clkout1_buf : label is "PRIMITIVE";
attribute BOX_TYPE of mmcm_adv_inst : label is "PRIMITIVE";
begin
clkf_buf: unisim.vcomponents.BUFG
port map (
I => clkfbout_system_clk_wiz_0_0,
O => clkfbout_buf_system_clk_wiz_0_0
);
clkin1_ibufg: unisim.vcomponents.IBUF
generic map(
IOSTANDARD => "DEFAULT"
)
port map (
I => clk_in1,
O => clk_in1_system_clk_wiz_0_0
);
clkout1_buf: unisim.vcomponents.BUFG
port map (
I => clk_out1_system_clk_wiz_0_0,
O => clk_out1
);
mmcm_adv_inst: unisim.vcomponents.MMCME2_ADV
generic map(
BANDWIDTH => "OPTIMIZED",
CLKFBOUT_MULT_F => 44.625000,
CLKFBOUT_PHASE => 0.000000,
CLKFBOUT_USE_FINE_PS => false,
CLKIN1_PERIOD => 10.000000,
CLKIN2_PERIOD => 0.000000,
CLKOUT0_DIVIDE_F => 75.000000,
CLKOUT0_DUTY_CYCLE => 0.500000,
CLKOUT0_PHASE => 0.000000,
CLKOUT0_USE_FINE_PS => false,
CLKOUT1_DIVIDE => 1,
CLKOUT1_DUTY_CYCLE => 0.500000,
CLKOUT1_PHASE => 0.000000,
CLKOUT1_USE_FINE_PS => false,
CLKOUT2_DIVIDE => 1,
CLKOUT2_DUTY_CYCLE => 0.500000,
CLKOUT2_PHASE => 0.000000,
CLKOUT2_USE_FINE_PS => false,
CLKOUT3_DIVIDE => 1,
CLKOUT3_DUTY_CYCLE => 0.500000,
CLKOUT3_PHASE => 0.000000,
CLKOUT3_USE_FINE_PS => false,
CLKOUT4_CASCADE => false,
CLKOUT4_DIVIDE => 1,
CLKOUT4_DUTY_CYCLE => 0.500000,
CLKOUT4_PHASE => 0.000000,
CLKOUT4_USE_FINE_PS => false,
CLKOUT5_DIVIDE => 1,
CLKOUT5_DUTY_CYCLE => 0.500000,
CLKOUT5_PHASE => 0.000000,
CLKOUT5_USE_FINE_PS => false,
CLKOUT6_DIVIDE => 1,
CLKOUT6_DUTY_CYCLE => 0.500000,
CLKOUT6_PHASE => 0.000000,
CLKOUT6_USE_FINE_PS => false,
COMPENSATION => "ZHOLD",
DIVCLK_DIVIDE => 5,
IS_CLKINSEL_INVERTED => '0',
IS_PSEN_INVERTED => '0',
IS_PSINCDEC_INVERTED => '0',
IS_PWRDWN_INVERTED => '0',
IS_RST_INVERTED => '0',
REF_JITTER1 => 0.010000,
REF_JITTER2 => 0.010000,
SS_EN => "FALSE",
SS_MODE => "CENTER_HIGH",
SS_MOD_PERIOD => 10000,
STARTUP_WAIT => false
)
port map (
CLKFBIN => clkfbout_buf_system_clk_wiz_0_0,
CLKFBOUT => clkfbout_system_clk_wiz_0_0,
CLKFBOUTB => NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED,
CLKFBSTOPPED => NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED,
CLKIN1 => clk_in1_system_clk_wiz_0_0,
CLKIN2 => '0',
CLKINSEL => '1',
CLKINSTOPPED => NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED,
CLKOUT0 => clk_out1_system_clk_wiz_0_0,
CLKOUT0B => NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED,
CLKOUT1 => NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED,
CLKOUT1B => NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED,
CLKOUT2 => NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED,
CLKOUT2B => NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED,
CLKOUT3 => NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED,
CLKOUT3B => NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED,
CLKOUT4 => NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED,
CLKOUT5 => NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED,
CLKOUT6 => NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED,
DADDR(6 downto 0) => B"0000000",
DCLK => '0',
DEN => '0',
DI(15 downto 0) => B"0000000000000000",
DO(15 downto 0) => NLW_mmcm_adv_inst_DO_UNCONNECTED(15 downto 0),
DRDY => NLW_mmcm_adv_inst_DRDY_UNCONNECTED,
DWE => '0',
LOCKED => locked,
PSCLK => '0',
PSDONE => NLW_mmcm_adv_inst_PSDONE_UNCONNECTED,
PSEN => '0',
PSINCDEC => '0',
PWRDWN => '0',
RST => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_clk_wiz_0_0 is
port (
clk_out1 : out STD_LOGIC;
locked : out STD_LOGIC;
clk_in1 : in STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_clk_wiz_0_0 : entity is true;
end system_clk_wiz_0_0;
architecture STRUCTURE of system_clk_wiz_0_0 is
begin
inst: entity work.system_clk_wiz_0_0_system_clk_wiz_0_0_clk_wiz
port map (
clk_in1 => clk_in1,
clk_out1 => clk_out1,
locked => locked
);
end STRUCTURE;
| mit |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | video_ip/vga_feature_transform/vga_feature_transform.srcs/sources_1/new/feature_buffer_match_block.vhd | 1 | 5844 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity feature_buffer_match_block is
generic (
PARITY : std_logic := '0'
);
port (
clk : in std_logic;
mode : in std_logic_vector(1 downto 0);
x_in_left : in std_logic_vector(9 downto 0);
y_in_left : in std_logic_vector(9 downto 0);
hessian_in_left : in std_logic_vector(31 downto 0);
x_in_right : in std_logic_vector(9 downto 0);
y_in_right : in std_logic_vector(9 downto 0);
hessian_in_right : in std_logic_vector(31 downto 0);
x_in_match_0 : in std_logic_vector(9 downto 0);
y_in_match_0 : in std_logic_vector(9 downto 0);
x_in_match_1 : in std_logic_vector(9 downto 0);
y_in_match_1 : in std_logic_vector(9 downto 0);
x_out_left : out std_logic_vector(9 downto 0);
y_out_left : out std_logic_vector(9 downto 0);
hessian_out_left : out std_logic_vector(31 downto 0);
x_out_right : out std_logic_vector(9 downto 0);
y_out_right : out std_logic_vector(9 downto 0);
hessian_out_right : out std_logic_vector(31 downto 0)
);
end feature_buffer_match_block;
architecture Behavioral of feature_buffer_match_block is
signal hessian : unsigned(31 downto 0) := x"00000000";
signal x : std_logic_vector(9 downto 0) := "0000000000";
signal y : std_logic_vector(9 downto 0) := "0000000000";
begin
hessian_out_left <= std_logic_vector(hessian);
x_out_left <= x;
y_out_left <= y;
hessian_out_right <= std_logic_vector(hessian);
x_out_right <= x;
y_out_right <= y;
process(clk)
variable x_diff_0, x_diff_1, y_diff_0, y_diff_1 : signed(9 downto 0);
variable distance_0, distance_1 : unsigned(19 downto 0);
begin
if rising_edge(clk) then
if mode = "01" then
if PARITY = '0' then
if hessian > unsigned(hessian_in_right) then
hessian <= unsigned(hessian_in_right);
x <= x_in_right;
y <= y_in_right;
end if;
else
if hessian < unsigned(hessian_in_left) then
hessian <= unsigned(hessian_in_left);
x <= x_in_left;
y <= y_in_left;
end if;
end if;
elsif mode = "10" then
if PARITY = '0' then
x_diff_0 := signed(x_in_match_0) - signed(x);
y_diff_0 := signed(y_in_match_0) - signed(y);
distance_0 := unsigned(x_diff_0 * x_diff_0 + y_diff_0 * y_diff_0);
x_diff_1 := signed(x_in_match_0) - signed(x_in_right);
y_diff_1 := signed(y_in_match_0) - signed(y_in_right);
distance_1 := unsigned(x_diff_1 * x_diff_1 + y_diff_1 * y_diff_1);
if distance_1 < distance_0 then
x <= x_in_right;
y <= y_in_right;
end if;
else
x_diff_0 := signed(x_in_match_1) - signed(x);
y_diff_0 := signed(y_in_match_1) - signed(y);
distance_0 := unsigned(x_diff_0 * x_diff_0 + y_diff_0 * y_diff_0);
x_diff_1 := signed(x_in_match_1) - signed(x_in_left);
y_diff_1 := signed(y_in_match_1) - signed(y_in_left);
distance_1 := unsigned(x_diff_1 * x_diff_1 + y_diff_1 * y_diff_1);
if distance_1 < distance_0 then
x <= x_in_left;
y <= y_in_left;
end if;
end if;
end if;
end if;
if falling_edge(clk) then
if mode = "01" then
if PARITY = '1' then
if hessian > unsigned(hessian_in_right) then
hessian <= unsigned(hessian_in_right);
x <= x_in_right;
y <= y_in_right;
end if;
else
if hessian < unsigned(hessian_in_left) then
hessian <= unsigned(hessian_in_left);
x <= x_in_left;
y <= y_in_left;
end if;
end if;
elsif mode = "10" then
if PARITY = '1' then
x_diff_0 := signed(x_in_match_0) - signed(x);
y_diff_0 := signed(y_in_match_0) - signed(y);
distance_0 := unsigned(x_diff_0 * x_diff_0 + y_diff_0 * y_diff_0);
x_diff_1 := signed(x_in_match_0) - signed(x_in_right);
y_diff_1 := signed(y_in_match_0) - signed(y_in_right);
distance_1 := unsigned(x_diff_1 * x_diff_1 + y_diff_1 * y_diff_1);
if distance_1 < distance_0 then
x <= x_in_right;
y <= y_in_right;
end if;
else
x_diff_0 := signed(x_in_match_1) - signed(x);
y_diff_0 := signed(y_in_match_1) - signed(y);
distance_0 := unsigned(x_diff_0 * x_diff_0 + y_diff_0 * y_diff_0);
x_diff_1 := signed(x_in_match_1) - signed(x_in_left);
y_diff_1 := signed(y_in_match_1) - signed(y_in_left);
distance_1 := unsigned(x_diff_1 * x_diff_1 + y_diff_1 * y_diff_1);
if distance_1 < distance_0 then
x <= x_in_left;
y <= y_in_left;
end if;
end if;
end if;
end if;
end process;
end Behavioral;
| mit |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/ov7670_fusion/ov7670_fusion.srcs/sources_1/bd/system/ip/system_inverter_0_0/system_inverter_0_0_stub.vhdl | 1 | 1270 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Wed Mar 01 09:53:10 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub
-- C:/ZyboIP/examples/ov7670_fusion/ov7670_fusion.srcs/sources_1/bd/system/ip/system_inverter_0_0/system_inverter_0_0_stub.vhdl
-- Design : system_inverter_0_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z010clg400-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity system_inverter_0_0 is
Port (
x : in STD_LOGIC;
x_not : out STD_LOGIC
);
end system_inverter_0_0;
architecture stub of system_inverter_0_0 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "x,x_not";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "inverter,Vivado 2016.4";
begin
end;
| mit |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/affine_transform_demo/affine_transform_demo.srcs/sources_1/bd/system/ipshared/37f6/tmds_encoder.vhd | 6 | 4438 | ----------------------------------------------------------------------------------
-- Company: DBRSS
-- Engineer: Daniel Barcklow
-- Module: TOP level DVI-D
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-- Adapted by: Rob Taglang
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity TMDS_encoder is
port(
clk : in std_logic;
d_in : in std_logic_vector(7 downto 0); -- 8 bit d_in to be encoded
C : in std_logic_vector(1 downto 0); -- control bits (2)
video_on : in std_logic; -- BLANKING, is video on?
encoded : out std_logic_vector(9 downto 0)); -- output encoded
end TMDS_encoder;
architecture Behavioral of TMDS_encoder is
signal xored : std_logic_vector(8 downto 0);
signal xnored : std_logic_vector(8 downto 0);
signal ones : std_logic_vector(3 downto 0);
signal q_m : std_logic_vector(8 downto 0);
signal q_m_inv : std_logic_vector(8 downto 0);
signal data_word_disparity : std_logic_vector(3 downto 0);
signal dc_bias : std_logic_vector(3 downto 0) := (others => '0');
begin
-- Perform FALSE<1> computations
xored(0) <= d_in(0);
xored(1) <= d_in(1) xor xored(0);
xored(2) <= d_in(2) xor xored(1);
xored(3) <= d_in(3) xor xored(2);
xored(4) <= d_in(4) xor xored(3);
xored(5) <= d_in(5) xor xored(4);
xored(6) <= d_in(6) xor xored(5);
xored(7) <= d_in(7) xor xored(6);
xored(8) <= '1';
-- Perform TRUE<1> computations
xnored(0) <= d_in(0);
xnored(1) <= d_in(1) xnor xnored(0);
xnored(2) <= d_in(2) xnor xnored(1);
xnored(3) <= d_in(3) xnor xnored(2);
xnored(4) <= d_in(4) xnor xnored(3);
xnored(5) <= d_in(5) xnor xnored(4);
xnored(6) <= d_in(6) xnor xnored(5);
xnored(7) <= d_in(7) xnor xnored(6);
xnored(8) <= '0';
-- count all 1's by adding them (0 won't contribute)
ones <= "0000" + d_in(0) + d_in(1) + d_in(2) + d_in(3)
+ d_in(4) + d_in(5) + d_in(6) + d_in(7);
-- decide on encoding
decision0: process(ones, d_in(0), xnored, xored)
begin
-- FIRST CHOICE DIAMOND (https://www.eewiki.net/pages/viewpage.action?pageId=36569119) <1>
if ones > 4 or (ones = 4 and d_in(0) = '0') then
q_m <= xnored;
q_m_inv <= NOT(xnored);
else
q_m <= xored;
q_m_inv <= NOT(xored);
end if;
end process decision0;
-- Work out the DC bias of the dataword;
data_word_disparity <= "1100" + q_m(0) + q_m(1) + q_m(2) + q_m(3)
+ q_m(4) + q_m(5) + q_m(6) + q_m(7);
-- Now work out what the output should be
process(clk)
begin
-- "DISPLAY ENABLE = 1"
if rising_edge(clk) then
if video_on = '0' then
-- In the control periods, all values have and have balanced bit count
case C is
when "00" => encoded <= "1101010100";
when "01" => encoded <= "0010101011";
when "10" => encoded <= "0101010100";
when others => encoded <= "1010101011";
end case;
dc_bias <= (others => '0');
else
-- Ones#(d) = 4 OR disparity = 0
if dc_bias = "00000" or data_word_disparity = 0 then
-- dataword has no disparity
if q_m(8) = '0' then
encoded <= "10" & q_m_inv(7 downto 0);
dc_bias <= dc_bias - data_word_disparity;
else
encoded <= "01" & q_m(7 downto 0);
dc_bias <= dc_bias + data_word_disparity;
end if;
elsif (dc_bias(3) = '0' and data_word_disparity(3) = '0') or
(dc_bias(3) = '1' and data_word_disparity(3) = '1') then
encoded <= '1' & q_m(8) & q_m_inv(7 downto 0);
dc_bias <= dc_bias + q_m(8) - data_word_disparity;
else
encoded <= '0' & q_m;
dc_bias <= dc_bias - q_m_inv(8) + data_word_disparity;
end if;
end if;
end if;
end process;
end Behavioral; | mit |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/ov7670_passthrough/ov7670_passthrough.srcs/sources_1/bd/system/ipshared/37f6/tmds_encoder.vhd | 6 | 4438 | ----------------------------------------------------------------------------------
-- Company: DBRSS
-- Engineer: Daniel Barcklow
-- Module: TOP level DVI-D
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-- Adapted by: Rob Taglang
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity TMDS_encoder is
port(
clk : in std_logic;
d_in : in std_logic_vector(7 downto 0); -- 8 bit d_in to be encoded
C : in std_logic_vector(1 downto 0); -- control bits (2)
video_on : in std_logic; -- BLANKING, is video on?
encoded : out std_logic_vector(9 downto 0)); -- output encoded
end TMDS_encoder;
architecture Behavioral of TMDS_encoder is
signal xored : std_logic_vector(8 downto 0);
signal xnored : std_logic_vector(8 downto 0);
signal ones : std_logic_vector(3 downto 0);
signal q_m : std_logic_vector(8 downto 0);
signal q_m_inv : std_logic_vector(8 downto 0);
signal data_word_disparity : std_logic_vector(3 downto 0);
signal dc_bias : std_logic_vector(3 downto 0) := (others => '0');
begin
-- Perform FALSE<1> computations
xored(0) <= d_in(0);
xored(1) <= d_in(1) xor xored(0);
xored(2) <= d_in(2) xor xored(1);
xored(3) <= d_in(3) xor xored(2);
xored(4) <= d_in(4) xor xored(3);
xored(5) <= d_in(5) xor xored(4);
xored(6) <= d_in(6) xor xored(5);
xored(7) <= d_in(7) xor xored(6);
xored(8) <= '1';
-- Perform TRUE<1> computations
xnored(0) <= d_in(0);
xnored(1) <= d_in(1) xnor xnored(0);
xnored(2) <= d_in(2) xnor xnored(1);
xnored(3) <= d_in(3) xnor xnored(2);
xnored(4) <= d_in(4) xnor xnored(3);
xnored(5) <= d_in(5) xnor xnored(4);
xnored(6) <= d_in(6) xnor xnored(5);
xnored(7) <= d_in(7) xnor xnored(6);
xnored(8) <= '0';
-- count all 1's by adding them (0 won't contribute)
ones <= "0000" + d_in(0) + d_in(1) + d_in(2) + d_in(3)
+ d_in(4) + d_in(5) + d_in(6) + d_in(7);
-- decide on encoding
decision0: process(ones, d_in(0), xnored, xored)
begin
-- FIRST CHOICE DIAMOND (https://www.eewiki.net/pages/viewpage.action?pageId=36569119) <1>
if ones > 4 or (ones = 4 and d_in(0) = '0') then
q_m <= xnored;
q_m_inv <= NOT(xnored);
else
q_m <= xored;
q_m_inv <= NOT(xored);
end if;
end process decision0;
-- Work out the DC bias of the dataword;
data_word_disparity <= "1100" + q_m(0) + q_m(1) + q_m(2) + q_m(3)
+ q_m(4) + q_m(5) + q_m(6) + q_m(7);
-- Now work out what the output should be
process(clk)
begin
-- "DISPLAY ENABLE = 1"
if rising_edge(clk) then
if video_on = '0' then
-- In the control periods, all values have and have balanced bit count
case C is
when "00" => encoded <= "1101010100";
when "01" => encoded <= "0010101011";
when "10" => encoded <= "0101010100";
when others => encoded <= "1010101011";
end case;
dc_bias <= (others => '0');
else
-- Ones#(d) = 4 OR disparity = 0
if dc_bias = "00000" or data_word_disparity = 0 then
-- dataword has no disparity
if q_m(8) = '0' then
encoded <= "10" & q_m_inv(7 downto 0);
dc_bias <= dc_bias - data_word_disparity;
else
encoded <= "01" & q_m(7 downto 0);
dc_bias <= dc_bias + data_word_disparity;
end if;
elsif (dc_bias(3) = '0' and data_word_disparity(3) = '0') or
(dc_bias(3) = '1' and data_word_disparity(3) = '1') then
encoded <= '1' & q_m(8) & q_m_inv(7 downto 0);
dc_bias <= dc_bias + q_m(8) - data_word_disparity;
else
encoded <= '0' & q_m;
dc_bias <= dc_bias - q_m_inv(8) + data_word_disparity;
end if;
end if;
end if;
end process;
end Behavioral; | mit |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/dma_example/dma_example.srcs/sources_1/bd/system/ip/system_auto_us_1/system_auto_us_1_sim_netlist.vhdl | 1 | 267051 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Wed May 31 20:16:39 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- c:/ZyboIP/examples/dma_example/dma_example.srcs/sources_1/bd/system/ip/system_auto_us_1/system_auto_us_1_sim_netlist.vhdl
-- Design : system_auto_us_1
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_us_1_axi_dwidth_converter_v2_1_11_r_upsizer is
port (
first_word : out STD_LOGIC;
SR : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rlast : out STD_LOGIC;
use_wrap_buffer : out STD_LOGIC;
first_mi_word_q : out STD_LOGIC;
\m_payload_i_reg[0]\ : out STD_LOGIC;
\current_word_1_reg[2]_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_READY_I : out STD_LOGIC;
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg\ : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
\USE_RTL_ADDR.addr_q_reg[4]\ : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\out\ : in STD_LOGIC;
\m_payload_i_reg[66]\ : in STD_LOGIC;
use_wrap_buffer_reg_0 : in STD_LOGIC;
mr_rvalid : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 10 downto 0 );
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[18]\ : in STD_LOGIC;
rd_cmd_valid : in STD_LOGIC;
m_valid_i_reg : in STD_LOGIC;
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_1\ : in STD_LOGIC;
\m_payload_i_reg[65]\ : in STD_LOGIC_VECTOR ( 65 downto 0 );
\current_word_1_reg[2]_1\ : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 2 downto 0 );
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[13]\ : in STD_LOGIC_VECTOR ( 2 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_us_1_axi_dwidth_converter_v2_1_11_r_upsizer : entity is "axi_dwidth_converter_v2_1_11_r_upsizer";
end system_auto_us_1_axi_dwidth_converter_v2_1_11_r_upsizer;
architecture STRUCTURE of system_auto_us_1_axi_dwidth_converter_v2_1_11_r_upsizer is
signal M_AXI_RDATA_I : STD_LOGIC_VECTOR ( 63 downto 0 );
signal \^sr\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^use_ff_out.use_rtl_output_pipeline.m_valid_q_reg\ : STD_LOGIC;
signal \USE_RTL_LENGTH.length_counter_q[0]_i_1_n_0\ : STD_LOGIC;
signal \USE_RTL_LENGTH.length_counter_q[1]_i_1_n_0\ : STD_LOGIC;
signal \USE_RTL_LENGTH.length_counter_q[1]_i_2_n_0\ : STD_LOGIC;
signal \USE_RTL_LENGTH.length_counter_q[2]_i_1_n_0\ : STD_LOGIC;
signal \USE_RTL_LENGTH.length_counter_q[3]_i_1_n_0\ : STD_LOGIC;
signal \USE_RTL_LENGTH.length_counter_q[3]_i_2_n_0\ : STD_LOGIC;
signal \USE_RTL_LENGTH.length_counter_q[4]_i_1_n_0\ : STD_LOGIC;
signal \USE_RTL_LENGTH.length_counter_q[4]_i_2_n_0\ : STD_LOGIC;
signal \USE_RTL_LENGTH.length_counter_q[5]_i_1_n_0\ : STD_LOGIC;
signal \USE_RTL_LENGTH.length_counter_q[5]_i_2_n_0\ : STD_LOGIC;
signal \USE_RTL_LENGTH.length_counter_q[6]_i_1_n_0\ : STD_LOGIC;
signal \USE_RTL_LENGTH.length_counter_q[6]_i_2_n_0\ : STD_LOGIC;
signal \USE_RTL_LENGTH.length_counter_q[7]_i_1_n_0\ : STD_LOGIC;
signal \USE_RTL_LENGTH.length_counter_q[7]_i_2_n_0\ : STD_LOGIC;
signal \USE_RTL_LENGTH.length_counter_q[7]_i_3_n_0\ : STD_LOGIC;
signal \USE_RTL_LENGTH.length_counter_q[7]_i_4_n_0\ : STD_LOGIC;
signal \USE_RTL_LENGTH.length_counter_q_reg\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \^current_word_1_reg[2]_0\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \^first_mi_word_q\ : STD_LOGIC;
signal \^first_word\ : STD_LOGIC;
signal p_15_in : STD_LOGIC;
signal p_7_in : STD_LOGIC;
signal rresp_wrap_buffer : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^s_axi_rlast\ : STD_LOGIC;
signal s_axi_rlast_INST_0_i_1_n_0 : STD_LOGIC;
signal s_axi_rlast_INST_0_i_3_n_0 : STD_LOGIC;
signal s_axi_rlast_INST_0_i_4_n_0 : STD_LOGIC;
signal s_axi_rlast_INST_0_i_5_n_0 : STD_LOGIC;
signal s_axi_rlast_INST_0_i_6_n_0 : STD_LOGIC;
signal s_axi_rlast_INST_0_i_7_n_0 : STD_LOGIC;
signal s_axi_rlast_INST_0_i_8_n_0 : STD_LOGIC;
signal s_ready_i_i_9_n_0 : STD_LOGIC;
signal \^use_wrap_buffer\ : STD_LOGIC;
signal use_wrap_buffer_i_1_n_0 : STD_LOGIC;
signal use_wrap_buffer_i_3_n_0 : STD_LOGIC;
signal wrap_buffer_available : STD_LOGIC;
signal wrap_buffer_available_i_1_n_0 : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_3\ : label is "soft_lutpair37";
attribute SOFT_HLUTNM of \USE_RTL_LENGTH.length_counter_q[0]_i_1\ : label is "soft_lutpair35";
attribute SOFT_HLUTNM of \USE_RTL_LENGTH.length_counter_q[1]_i_2\ : label is "soft_lutpair35";
attribute SOFT_HLUTNM of \USE_RTL_LENGTH.length_counter_q[3]_i_2\ : label is "soft_lutpair38";
attribute SOFT_HLUTNM of \USE_RTL_LENGTH.length_counter_q[5]_i_2\ : label is "soft_lutpair36";
attribute SOFT_HLUTNM of \USE_RTL_LENGTH.length_counter_q[7]_i_3\ : label is "soft_lutpair39";
attribute SOFT_HLUTNM of \USE_RTL_LENGTH.length_counter_q[7]_i_4\ : label is "soft_lutpair34";
attribute SOFT_HLUTNM of s_axi_rlast_INST_0_i_4 : label is "soft_lutpair38";
attribute SOFT_HLUTNM of s_axi_rlast_INST_0_i_5 : label is "soft_lutpair39";
attribute SOFT_HLUTNM of s_axi_rlast_INST_0_i_6 : label is "soft_lutpair33";
attribute SOFT_HLUTNM of s_axi_rlast_INST_0_i_7 : label is "soft_lutpair36";
attribute SOFT_HLUTNM of s_axi_rlast_INST_0_i_8 : label is "soft_lutpair34";
attribute SOFT_HLUTNM of \s_axi_rresp[0]_INST_0\ : label is "soft_lutpair40";
attribute SOFT_HLUTNM of \s_axi_rresp[1]_INST_0\ : label is "soft_lutpair40";
attribute SOFT_HLUTNM of s_axi_rvalid_INST_0 : label is "soft_lutpair37";
attribute SOFT_HLUTNM of s_ready_i_i_9 : label is "soft_lutpair33";
begin
SR(0) <= \^sr\(0);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg\ <= \^use_ff_out.use_rtl_output_pipeline.m_valid_q_reg\;
\current_word_1_reg[2]_0\(2 downto 0) <= \^current_word_1_reg[2]_0\(2 downto 0);
first_mi_word_q <= \^first_mi_word_q\;
first_word <= \^first_word\;
s_axi_rlast <= \^s_axi_rlast\;
use_wrap_buffer <= \^use_wrap_buffer\;
\M_AXI_RDATA_I[63]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"40000000"
)
port map (
I0 => \^use_wrap_buffer\,
I1 => \^first_mi_word_q\,
I2 => Q(9),
I3 => mr_rvalid,
I4 => rd_cmd_valid,
O => p_7_in
);
\M_AXI_RDATA_I_reg[0]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[65]\(0),
Q => M_AXI_RDATA_I(0),
R => \^sr\(0)
);
\M_AXI_RDATA_I_reg[10]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[65]\(10),
Q => M_AXI_RDATA_I(10),
R => \^sr\(0)
);
\M_AXI_RDATA_I_reg[11]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[65]\(11),
Q => M_AXI_RDATA_I(11),
R => \^sr\(0)
);
\M_AXI_RDATA_I_reg[12]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[65]\(12),
Q => M_AXI_RDATA_I(12),
R => \^sr\(0)
);
\M_AXI_RDATA_I_reg[13]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[65]\(13),
Q => M_AXI_RDATA_I(13),
R => \^sr\(0)
);
\M_AXI_RDATA_I_reg[14]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[65]\(14),
Q => M_AXI_RDATA_I(14),
R => \^sr\(0)
);
\M_AXI_RDATA_I_reg[15]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[65]\(15),
Q => M_AXI_RDATA_I(15),
R => \^sr\(0)
);
\M_AXI_RDATA_I_reg[16]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[65]\(16),
Q => M_AXI_RDATA_I(16),
R => \^sr\(0)
);
\M_AXI_RDATA_I_reg[17]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[65]\(17),
Q => M_AXI_RDATA_I(17),
R => \^sr\(0)
);
\M_AXI_RDATA_I_reg[18]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[65]\(18),
Q => M_AXI_RDATA_I(18),
R => \^sr\(0)
);
\M_AXI_RDATA_I_reg[19]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[65]\(19),
Q => M_AXI_RDATA_I(19),
R => \^sr\(0)
);
\M_AXI_RDATA_I_reg[1]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[65]\(1),
Q => M_AXI_RDATA_I(1),
R => \^sr\(0)
);
\M_AXI_RDATA_I_reg[20]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[65]\(20),
Q => M_AXI_RDATA_I(20),
R => \^sr\(0)
);
\M_AXI_RDATA_I_reg[21]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[65]\(21),
Q => M_AXI_RDATA_I(21),
R => \^sr\(0)
);
\M_AXI_RDATA_I_reg[22]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[65]\(22),
Q => M_AXI_RDATA_I(22),
R => \^sr\(0)
);
\M_AXI_RDATA_I_reg[23]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[65]\(23),
Q => M_AXI_RDATA_I(23),
R => \^sr\(0)
);
\M_AXI_RDATA_I_reg[24]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[65]\(24),
Q => M_AXI_RDATA_I(24),
R => \^sr\(0)
);
\M_AXI_RDATA_I_reg[25]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[65]\(25),
Q => M_AXI_RDATA_I(25),
R => \^sr\(0)
);
\M_AXI_RDATA_I_reg[26]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[65]\(26),
Q => M_AXI_RDATA_I(26),
R => \^sr\(0)
);
\M_AXI_RDATA_I_reg[27]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[65]\(27),
Q => M_AXI_RDATA_I(27),
R => \^sr\(0)
);
\M_AXI_RDATA_I_reg[28]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[65]\(28),
Q => M_AXI_RDATA_I(28),
R => \^sr\(0)
);
\M_AXI_RDATA_I_reg[29]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[65]\(29),
Q => M_AXI_RDATA_I(29),
R => \^sr\(0)
);
\M_AXI_RDATA_I_reg[2]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[65]\(2),
Q => M_AXI_RDATA_I(2),
R => \^sr\(0)
);
\M_AXI_RDATA_I_reg[30]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[65]\(30),
Q => M_AXI_RDATA_I(30),
R => \^sr\(0)
);
\M_AXI_RDATA_I_reg[31]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[65]\(31),
Q => M_AXI_RDATA_I(31),
R => \^sr\(0)
);
\M_AXI_RDATA_I_reg[32]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[65]\(32),
Q => M_AXI_RDATA_I(32),
R => \^sr\(0)
);
\M_AXI_RDATA_I_reg[33]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[65]\(33),
Q => M_AXI_RDATA_I(33),
R => \^sr\(0)
);
\M_AXI_RDATA_I_reg[34]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[65]\(34),
Q => M_AXI_RDATA_I(34),
R => \^sr\(0)
);
\M_AXI_RDATA_I_reg[35]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[65]\(35),
Q => M_AXI_RDATA_I(35),
R => \^sr\(0)
);
\M_AXI_RDATA_I_reg[36]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[65]\(36),
Q => M_AXI_RDATA_I(36),
R => \^sr\(0)
);
\M_AXI_RDATA_I_reg[37]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[65]\(37),
Q => M_AXI_RDATA_I(37),
R => \^sr\(0)
);
\M_AXI_RDATA_I_reg[38]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[65]\(38),
Q => M_AXI_RDATA_I(38),
R => \^sr\(0)
);
\M_AXI_RDATA_I_reg[39]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[65]\(39),
Q => M_AXI_RDATA_I(39),
R => \^sr\(0)
);
\M_AXI_RDATA_I_reg[3]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[65]\(3),
Q => M_AXI_RDATA_I(3),
R => \^sr\(0)
);
\M_AXI_RDATA_I_reg[40]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[65]\(40),
Q => M_AXI_RDATA_I(40),
R => \^sr\(0)
);
\M_AXI_RDATA_I_reg[41]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[65]\(41),
Q => M_AXI_RDATA_I(41),
R => \^sr\(0)
);
\M_AXI_RDATA_I_reg[42]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[65]\(42),
Q => M_AXI_RDATA_I(42),
R => \^sr\(0)
);
\M_AXI_RDATA_I_reg[43]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[65]\(43),
Q => M_AXI_RDATA_I(43),
R => \^sr\(0)
);
\M_AXI_RDATA_I_reg[44]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[65]\(44),
Q => M_AXI_RDATA_I(44),
R => \^sr\(0)
);
\M_AXI_RDATA_I_reg[45]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[65]\(45),
Q => M_AXI_RDATA_I(45),
R => \^sr\(0)
);
\M_AXI_RDATA_I_reg[46]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[65]\(46),
Q => M_AXI_RDATA_I(46),
R => \^sr\(0)
);
\M_AXI_RDATA_I_reg[47]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[65]\(47),
Q => M_AXI_RDATA_I(47),
R => \^sr\(0)
);
\M_AXI_RDATA_I_reg[48]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[65]\(48),
Q => M_AXI_RDATA_I(48),
R => \^sr\(0)
);
\M_AXI_RDATA_I_reg[49]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[65]\(49),
Q => M_AXI_RDATA_I(49),
R => \^sr\(0)
);
\M_AXI_RDATA_I_reg[4]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[65]\(4),
Q => M_AXI_RDATA_I(4),
R => \^sr\(0)
);
\M_AXI_RDATA_I_reg[50]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[65]\(50),
Q => M_AXI_RDATA_I(50),
R => \^sr\(0)
);
\M_AXI_RDATA_I_reg[51]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[65]\(51),
Q => M_AXI_RDATA_I(51),
R => \^sr\(0)
);
\M_AXI_RDATA_I_reg[52]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[65]\(52),
Q => M_AXI_RDATA_I(52),
R => \^sr\(0)
);
\M_AXI_RDATA_I_reg[53]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[65]\(53),
Q => M_AXI_RDATA_I(53),
R => \^sr\(0)
);
\M_AXI_RDATA_I_reg[54]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[65]\(54),
Q => M_AXI_RDATA_I(54),
R => \^sr\(0)
);
\M_AXI_RDATA_I_reg[55]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[65]\(55),
Q => M_AXI_RDATA_I(55),
R => \^sr\(0)
);
\M_AXI_RDATA_I_reg[56]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[65]\(56),
Q => M_AXI_RDATA_I(56),
R => \^sr\(0)
);
\M_AXI_RDATA_I_reg[57]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[65]\(57),
Q => M_AXI_RDATA_I(57),
R => \^sr\(0)
);
\M_AXI_RDATA_I_reg[58]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[65]\(58),
Q => M_AXI_RDATA_I(58),
R => \^sr\(0)
);
\M_AXI_RDATA_I_reg[59]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[65]\(59),
Q => M_AXI_RDATA_I(59),
R => \^sr\(0)
);
\M_AXI_RDATA_I_reg[5]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[65]\(5),
Q => M_AXI_RDATA_I(5),
R => \^sr\(0)
);
\M_AXI_RDATA_I_reg[60]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[65]\(60),
Q => M_AXI_RDATA_I(60),
R => \^sr\(0)
);
\M_AXI_RDATA_I_reg[61]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[65]\(61),
Q => M_AXI_RDATA_I(61),
R => \^sr\(0)
);
\M_AXI_RDATA_I_reg[62]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[65]\(62),
Q => M_AXI_RDATA_I(62),
R => \^sr\(0)
);
\M_AXI_RDATA_I_reg[63]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[65]\(63),
Q => M_AXI_RDATA_I(63),
R => \^sr\(0)
);
\M_AXI_RDATA_I_reg[6]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[65]\(6),
Q => M_AXI_RDATA_I(6),
R => \^sr\(0)
);
\M_AXI_RDATA_I_reg[7]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[65]\(7),
Q => M_AXI_RDATA_I(7),
R => \^sr\(0)
);
\M_AXI_RDATA_I_reg[8]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[65]\(8),
Q => M_AXI_RDATA_I(8),
R => \^sr\(0)
);
\M_AXI_RDATA_I_reg[9]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[65]\(9),
Q => M_AXI_RDATA_I(9),
R => \^sr\(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => s_axi_aresetn,
O => \^sr\(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0F010000FFFFFFFF"
)
port map (
I0 => s_axi_rlast_INST_0_i_1_n_0,
I1 => wrap_buffer_available,
I2 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[18]\,
I3 => \^use_wrap_buffer\,
I4 => \^use_ff_out.use_rtl_output_pipeline.m_valid_q_reg\,
I5 => rd_cmd_valid,
O => M_READY_I
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"A080"
)
port map (
I0 => s_axi_rready,
I1 => \^use_wrap_buffer\,
I2 => rd_cmd_valid,
I3 => mr_rvalid,
O => \^use_ff_out.use_rtl_output_pipeline.m_valid_q_reg\
);
\USE_RTL_LENGTH.first_mi_word_q_reg\: unisim.vcomponents.FDSE
port map (
C => \out\,
CE => '1',
D => \m_payload_i_reg[66]\,
Q => \^first_mi_word_q\,
S => \^sr\(0)
);
\USE_RTL_LENGTH.length_counter_q[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"2FFF7000"
)
port map (
I0 => \^first_mi_word_q\,
I1 => Q(0),
I2 => use_wrap_buffer_reg_0,
I3 => mr_rvalid,
I4 => \USE_RTL_LENGTH.length_counter_q_reg\(0),
O => \USE_RTL_LENGTH.length_counter_q[0]_i_1_n_0\
);
\USE_RTL_LENGTH.length_counter_q[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F8F070F07078F878"
)
port map (
I0 => use_wrap_buffer_reg_0,
I1 => mr_rvalid,
I2 => \USE_RTL_LENGTH.length_counter_q_reg\(1),
I3 => \^first_mi_word_q\,
I4 => Q(1),
I5 => \USE_RTL_LENGTH.length_counter_q[1]_i_2_n_0\,
O => \USE_RTL_LENGTH.length_counter_q[1]_i_1_n_0\
);
\USE_RTL_LENGTH.length_counter_q[1]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(0),
I1 => \^first_mi_word_q\,
I2 => \USE_RTL_LENGTH.length_counter_q_reg\(0),
O => \USE_RTL_LENGTH.length_counter_q[1]_i_2_n_0\
);
\USE_RTL_LENGTH.length_counter_q[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"7078F878F8F070F0"
)
port map (
I0 => use_wrap_buffer_reg_0,
I1 => mr_rvalid,
I2 => \USE_RTL_LENGTH.length_counter_q_reg\(2),
I3 => \^first_mi_word_q\,
I4 => Q(2),
I5 => s_axi_rlast_INST_0_i_3_n_0,
O => \USE_RTL_LENGTH.length_counter_q[2]_i_1_n_0\
);
\USE_RTL_LENGTH.length_counter_q[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F7FF80007F770888"
)
port map (
I0 => use_wrap_buffer_reg_0,
I1 => mr_rvalid,
I2 => Q(3),
I3 => \^first_mi_word_q\,
I4 => \USE_RTL_LENGTH.length_counter_q_reg\(3),
I5 => \USE_RTL_LENGTH.length_counter_q[3]_i_2_n_0\,
O => \USE_RTL_LENGTH.length_counter_q[3]_i_1_n_0\
);
\USE_RTL_LENGTH.length_counter_q[3]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"E2FF"
)
port map (
I0 => \USE_RTL_LENGTH.length_counter_q_reg\(2),
I1 => \^first_mi_word_q\,
I2 => Q(2),
I3 => s_axi_rlast_INST_0_i_3_n_0,
O => \USE_RTL_LENGTH.length_counter_q[3]_i_2_n_0\
);
\USE_RTL_LENGTH.length_counter_q[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F780F7087F08F708"
)
port map (
I0 => use_wrap_buffer_reg_0,
I1 => mr_rvalid,
I2 => \USE_RTL_LENGTH.length_counter_q[4]_i_2_n_0\,
I3 => \USE_RTL_LENGTH.length_counter_q_reg\(4),
I4 => \^first_mi_word_q\,
I5 => Q(4),
O => \USE_RTL_LENGTH.length_counter_q[4]_i_1_n_0\
);
\USE_RTL_LENGTH.length_counter_q[4]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFF5DDDDFFF5"
)
port map (
I0 => s_axi_rlast_INST_0_i_3_n_0,
I1 => Q(2),
I2 => \USE_RTL_LENGTH.length_counter_q_reg\(2),
I3 => \USE_RTL_LENGTH.length_counter_q_reg\(3),
I4 => \^first_mi_word_q\,
I5 => Q(3),
O => \USE_RTL_LENGTH.length_counter_q[4]_i_2_n_0\
);
\USE_RTL_LENGTH.length_counter_q[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"7F087F80F7807F80"
)
port map (
I0 => use_wrap_buffer_reg_0,
I1 => mr_rvalid,
I2 => \USE_RTL_LENGTH.length_counter_q[5]_i_2_n_0\,
I3 => \USE_RTL_LENGTH.length_counter_q_reg\(5),
I4 => \^first_mi_word_q\,
I5 => Q(5),
O => \USE_RTL_LENGTH.length_counter_q[5]_i_1_n_0\
);
\USE_RTL_LENGTH.length_counter_q[5]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"0151"
)
port map (
I0 => \USE_RTL_LENGTH.length_counter_q[4]_i_2_n_0\,
I1 => \USE_RTL_LENGTH.length_counter_q_reg\(4),
I2 => \^first_mi_word_q\,
I3 => Q(4),
O => \USE_RTL_LENGTH.length_counter_q[5]_i_2_n_0\
);
\USE_RTL_LENGTH.length_counter_q[6]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"7F087F80F7807F80"
)
port map (
I0 => use_wrap_buffer_reg_0,
I1 => mr_rvalid,
I2 => \USE_RTL_LENGTH.length_counter_q[6]_i_2_n_0\,
I3 => \USE_RTL_LENGTH.length_counter_q_reg\(6),
I4 => \^first_mi_word_q\,
I5 => Q(6),
O => \USE_RTL_LENGTH.length_counter_q[6]_i_1_n_0\
);
\USE_RTL_LENGTH.length_counter_q[6]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000305050003"
)
port map (
I0 => Q(4),
I1 => \USE_RTL_LENGTH.length_counter_q_reg\(4),
I2 => \USE_RTL_LENGTH.length_counter_q[4]_i_2_n_0\,
I3 => \USE_RTL_LENGTH.length_counter_q_reg\(5),
I4 => \^first_mi_word_q\,
I5 => Q(5),
O => \USE_RTL_LENGTH.length_counter_q[6]_i_2_n_0\
);
\USE_RTL_LENGTH.length_counter_q[7]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"7F087F80F7807F80"
)
port map (
I0 => use_wrap_buffer_reg_0,
I1 => mr_rvalid,
I2 => \USE_RTL_LENGTH.length_counter_q[7]_i_2_n_0\,
I3 => \USE_RTL_LENGTH.length_counter_q_reg\(7),
I4 => \^first_mi_word_q\,
I5 => Q(7),
O => \USE_RTL_LENGTH.length_counter_q[7]_i_1_n_0\
);
\USE_RTL_LENGTH.length_counter_q[7]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000011101"
)
port map (
I0 => \USE_RTL_LENGTH.length_counter_q[7]_i_3_n_0\,
I1 => \USE_RTL_LENGTH.length_counter_q[4]_i_2_n_0\,
I2 => \USE_RTL_LENGTH.length_counter_q_reg\(4),
I3 => \^first_mi_word_q\,
I4 => Q(4),
I5 => \USE_RTL_LENGTH.length_counter_q[7]_i_4_n_0\,
O => \USE_RTL_LENGTH.length_counter_q[7]_i_2_n_0\
);
\USE_RTL_LENGTH.length_counter_q[7]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(5),
I1 => \^first_mi_word_q\,
I2 => \USE_RTL_LENGTH.length_counter_q_reg\(5),
O => \USE_RTL_LENGTH.length_counter_q[7]_i_3_n_0\
);
\USE_RTL_LENGTH.length_counter_q[7]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(6),
I1 => \^first_mi_word_q\,
I2 => \USE_RTL_LENGTH.length_counter_q_reg\(6),
O => \USE_RTL_LENGTH.length_counter_q[7]_i_4_n_0\
);
\USE_RTL_LENGTH.length_counter_q_reg[0]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \USE_RTL_LENGTH.length_counter_q[0]_i_1_n_0\,
Q => \USE_RTL_LENGTH.length_counter_q_reg\(0),
R => \^sr\(0)
);
\USE_RTL_LENGTH.length_counter_q_reg[1]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \USE_RTL_LENGTH.length_counter_q[1]_i_1_n_0\,
Q => \USE_RTL_LENGTH.length_counter_q_reg\(1),
R => \^sr\(0)
);
\USE_RTL_LENGTH.length_counter_q_reg[2]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \USE_RTL_LENGTH.length_counter_q[2]_i_1_n_0\,
Q => \USE_RTL_LENGTH.length_counter_q_reg\(2),
R => \^sr\(0)
);
\USE_RTL_LENGTH.length_counter_q_reg[3]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \USE_RTL_LENGTH.length_counter_q[3]_i_1_n_0\,
Q => \USE_RTL_LENGTH.length_counter_q_reg\(3),
R => \^sr\(0)
);
\USE_RTL_LENGTH.length_counter_q_reg[4]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \USE_RTL_LENGTH.length_counter_q[4]_i_1_n_0\,
Q => \USE_RTL_LENGTH.length_counter_q_reg\(4),
R => \^sr\(0)
);
\USE_RTL_LENGTH.length_counter_q_reg[5]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \USE_RTL_LENGTH.length_counter_q[5]_i_1_n_0\,
Q => \USE_RTL_LENGTH.length_counter_q_reg\(5),
R => \^sr\(0)
);
\USE_RTL_LENGTH.length_counter_q_reg[6]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \USE_RTL_LENGTH.length_counter_q[6]_i_1_n_0\,
Q => \USE_RTL_LENGTH.length_counter_q_reg\(6),
R => \^sr\(0)
);
\USE_RTL_LENGTH.length_counter_q_reg[7]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \USE_RTL_LENGTH.length_counter_q[7]_i_1_n_0\,
Q => \USE_RTL_LENGTH.length_counter_q_reg\(7),
R => \^sr\(0)
);
\current_word_1_reg[0]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_15_in,
D => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[13]\(0),
Q => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_0\(0),
R => \^sr\(0)
);
\current_word_1_reg[1]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_15_in,
D => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[13]\(1),
Q => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_0\(1),
R => \^sr\(0)
);
\current_word_1_reg[2]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_15_in,
D => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[13]\(2),
Q => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_0\(2),
R => \^sr\(0)
);
first_word_reg: unisim.vcomponents.FDSE
port map (
C => \out\,
CE => p_15_in,
D => \^s_axi_rlast\,
Q => \^first_word\,
S => \^sr\(0)
);
\pre_next_word_1[2]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"A888"
)
port map (
I0 => s_axi_rready,
I1 => \^use_wrap_buffer\,
I2 => rd_cmd_valid,
I3 => mr_rvalid,
O => p_15_in
);
\pre_next_word_1_reg[0]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_15_in,
D => D(0),
Q => \^current_word_1_reg[2]_0\(0),
R => \^sr\(0)
);
\pre_next_word_1_reg[1]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_15_in,
D => D(1),
Q => \^current_word_1_reg[2]_0\(1),
R => \^sr\(0)
);
\pre_next_word_1_reg[2]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_15_in,
D => D(2),
Q => \^current_word_1_reg[2]_0\(2),
R => \^sr\(0)
);
\rresp_wrap_buffer_reg[0]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[65]\(64),
Q => rresp_wrap_buffer(0),
R => \^sr\(0)
);
\rresp_wrap_buffer_reg[1]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[65]\(65),
Q => rresp_wrap_buffer(1),
R => \^sr\(0)
);
\s_axi_rdata[0]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"CAFFCAF0CA0FCA00"
)
port map (
I0 => \m_payload_i_reg[65]\(0),
I1 => M_AXI_RDATA_I(0),
I2 => \^use_wrap_buffer\,
I3 => \current_word_1_reg[2]_1\,
I4 => \m_payload_i_reg[65]\(32),
I5 => M_AXI_RDATA_I(32),
O => s_axi_rdata(0)
);
\s_axi_rdata[10]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"CAFFCAF0CA0FCA00"
)
port map (
I0 => \m_payload_i_reg[65]\(10),
I1 => M_AXI_RDATA_I(10),
I2 => \^use_wrap_buffer\,
I3 => \current_word_1_reg[2]_1\,
I4 => \m_payload_i_reg[65]\(42),
I5 => M_AXI_RDATA_I(42),
O => s_axi_rdata(10)
);
\s_axi_rdata[11]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"CAFFCAF0CA0FCA00"
)
port map (
I0 => \m_payload_i_reg[65]\(11),
I1 => M_AXI_RDATA_I(11),
I2 => \^use_wrap_buffer\,
I3 => \current_word_1_reg[2]_1\,
I4 => \m_payload_i_reg[65]\(43),
I5 => M_AXI_RDATA_I(43),
O => s_axi_rdata(11)
);
\s_axi_rdata[12]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"CAFFCAF0CA0FCA00"
)
port map (
I0 => \m_payload_i_reg[65]\(12),
I1 => M_AXI_RDATA_I(12),
I2 => \^use_wrap_buffer\,
I3 => \current_word_1_reg[2]_1\,
I4 => \m_payload_i_reg[65]\(44),
I5 => M_AXI_RDATA_I(44),
O => s_axi_rdata(12)
);
\s_axi_rdata[13]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"CAFFCAF0CA0FCA00"
)
port map (
I0 => \m_payload_i_reg[65]\(13),
I1 => M_AXI_RDATA_I(13),
I2 => \^use_wrap_buffer\,
I3 => \current_word_1_reg[2]_1\,
I4 => \m_payload_i_reg[65]\(45),
I5 => M_AXI_RDATA_I(45),
O => s_axi_rdata(13)
);
\s_axi_rdata[14]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"CAFFCAF0CA0FCA00"
)
port map (
I0 => \m_payload_i_reg[65]\(14),
I1 => M_AXI_RDATA_I(14),
I2 => \^use_wrap_buffer\,
I3 => \current_word_1_reg[2]_1\,
I4 => \m_payload_i_reg[65]\(46),
I5 => M_AXI_RDATA_I(46),
O => s_axi_rdata(14)
);
\s_axi_rdata[15]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"CAFFCAF0CA0FCA00"
)
port map (
I0 => \m_payload_i_reg[65]\(15),
I1 => M_AXI_RDATA_I(15),
I2 => \^use_wrap_buffer\,
I3 => \current_word_1_reg[2]_1\,
I4 => \m_payload_i_reg[65]\(47),
I5 => M_AXI_RDATA_I(47),
O => s_axi_rdata(15)
);
\s_axi_rdata[16]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"CAFFCAF0CA0FCA00"
)
port map (
I0 => \m_payload_i_reg[65]\(16),
I1 => M_AXI_RDATA_I(16),
I2 => \^use_wrap_buffer\,
I3 => \current_word_1_reg[2]_1\,
I4 => \m_payload_i_reg[65]\(48),
I5 => M_AXI_RDATA_I(48),
O => s_axi_rdata(16)
);
\s_axi_rdata[17]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"CAFFCAF0CA0FCA00"
)
port map (
I0 => \m_payload_i_reg[65]\(17),
I1 => M_AXI_RDATA_I(17),
I2 => \^use_wrap_buffer\,
I3 => \current_word_1_reg[2]_1\,
I4 => \m_payload_i_reg[65]\(49),
I5 => M_AXI_RDATA_I(49),
O => s_axi_rdata(17)
);
\s_axi_rdata[18]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"CAFFCAF0CA0FCA00"
)
port map (
I0 => \m_payload_i_reg[65]\(18),
I1 => M_AXI_RDATA_I(18),
I2 => \^use_wrap_buffer\,
I3 => \current_word_1_reg[2]_1\,
I4 => \m_payload_i_reg[65]\(50),
I5 => M_AXI_RDATA_I(50),
O => s_axi_rdata(18)
);
\s_axi_rdata[19]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"CAFFCAF0CA0FCA00"
)
port map (
I0 => \m_payload_i_reg[65]\(19),
I1 => M_AXI_RDATA_I(19),
I2 => \^use_wrap_buffer\,
I3 => \current_word_1_reg[2]_1\,
I4 => \m_payload_i_reg[65]\(51),
I5 => M_AXI_RDATA_I(51),
O => s_axi_rdata(19)
);
\s_axi_rdata[1]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"CAFFCAF0CA0FCA00"
)
port map (
I0 => \m_payload_i_reg[65]\(1),
I1 => M_AXI_RDATA_I(1),
I2 => \^use_wrap_buffer\,
I3 => \current_word_1_reg[2]_1\,
I4 => \m_payload_i_reg[65]\(33),
I5 => M_AXI_RDATA_I(33),
O => s_axi_rdata(1)
);
\s_axi_rdata[20]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"CAFFCAF0CA0FCA00"
)
port map (
I0 => \m_payload_i_reg[65]\(20),
I1 => M_AXI_RDATA_I(20),
I2 => \^use_wrap_buffer\,
I3 => \current_word_1_reg[2]_1\,
I4 => \m_payload_i_reg[65]\(52),
I5 => M_AXI_RDATA_I(52),
O => s_axi_rdata(20)
);
\s_axi_rdata[21]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"CAFFCAF0CA0FCA00"
)
port map (
I0 => \m_payload_i_reg[65]\(21),
I1 => M_AXI_RDATA_I(21),
I2 => \^use_wrap_buffer\,
I3 => \current_word_1_reg[2]_1\,
I4 => \m_payload_i_reg[65]\(53),
I5 => M_AXI_RDATA_I(53),
O => s_axi_rdata(21)
);
\s_axi_rdata[22]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"CAFFCAF0CA0FCA00"
)
port map (
I0 => \m_payload_i_reg[65]\(22),
I1 => M_AXI_RDATA_I(22),
I2 => \^use_wrap_buffer\,
I3 => \current_word_1_reg[2]_1\,
I4 => \m_payload_i_reg[65]\(54),
I5 => M_AXI_RDATA_I(54),
O => s_axi_rdata(22)
);
\s_axi_rdata[23]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"CAFFCAF0CA0FCA00"
)
port map (
I0 => \m_payload_i_reg[65]\(23),
I1 => M_AXI_RDATA_I(23),
I2 => \^use_wrap_buffer\,
I3 => \current_word_1_reg[2]_1\,
I4 => \m_payload_i_reg[65]\(55),
I5 => M_AXI_RDATA_I(55),
O => s_axi_rdata(23)
);
\s_axi_rdata[24]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"CAFFCAF0CA0FCA00"
)
port map (
I0 => \m_payload_i_reg[65]\(24),
I1 => M_AXI_RDATA_I(24),
I2 => \^use_wrap_buffer\,
I3 => \current_word_1_reg[2]_1\,
I4 => \m_payload_i_reg[65]\(56),
I5 => M_AXI_RDATA_I(56),
O => s_axi_rdata(24)
);
\s_axi_rdata[25]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"CAFFCAF0CA0FCA00"
)
port map (
I0 => \m_payload_i_reg[65]\(25),
I1 => M_AXI_RDATA_I(25),
I2 => \^use_wrap_buffer\,
I3 => \current_word_1_reg[2]_1\,
I4 => \m_payload_i_reg[65]\(57),
I5 => M_AXI_RDATA_I(57),
O => s_axi_rdata(25)
);
\s_axi_rdata[26]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"CAFFCAF0CA0FCA00"
)
port map (
I0 => \m_payload_i_reg[65]\(26),
I1 => M_AXI_RDATA_I(26),
I2 => \^use_wrap_buffer\,
I3 => \current_word_1_reg[2]_1\,
I4 => \m_payload_i_reg[65]\(58),
I5 => M_AXI_RDATA_I(58),
O => s_axi_rdata(26)
);
\s_axi_rdata[27]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"CAFFCAF0CA0FCA00"
)
port map (
I0 => \m_payload_i_reg[65]\(27),
I1 => M_AXI_RDATA_I(27),
I2 => \^use_wrap_buffer\,
I3 => \current_word_1_reg[2]_1\,
I4 => \m_payload_i_reg[65]\(59),
I5 => M_AXI_RDATA_I(59),
O => s_axi_rdata(27)
);
\s_axi_rdata[28]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"CAFFCAF0CA0FCA00"
)
port map (
I0 => \m_payload_i_reg[65]\(28),
I1 => M_AXI_RDATA_I(28),
I2 => \^use_wrap_buffer\,
I3 => \current_word_1_reg[2]_1\,
I4 => \m_payload_i_reg[65]\(60),
I5 => M_AXI_RDATA_I(60),
O => s_axi_rdata(28)
);
\s_axi_rdata[29]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"CAFFCAF0CA0FCA00"
)
port map (
I0 => \m_payload_i_reg[65]\(29),
I1 => M_AXI_RDATA_I(29),
I2 => \^use_wrap_buffer\,
I3 => \current_word_1_reg[2]_1\,
I4 => \m_payload_i_reg[65]\(61),
I5 => M_AXI_RDATA_I(61),
O => s_axi_rdata(29)
);
\s_axi_rdata[2]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"CAFFCAF0CA0FCA00"
)
port map (
I0 => \m_payload_i_reg[65]\(2),
I1 => M_AXI_RDATA_I(2),
I2 => \^use_wrap_buffer\,
I3 => \current_word_1_reg[2]_1\,
I4 => \m_payload_i_reg[65]\(34),
I5 => M_AXI_RDATA_I(34),
O => s_axi_rdata(2)
);
\s_axi_rdata[30]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"CAFFCAF0CA0FCA00"
)
port map (
I0 => \m_payload_i_reg[65]\(30),
I1 => M_AXI_RDATA_I(30),
I2 => \^use_wrap_buffer\,
I3 => \current_word_1_reg[2]_1\,
I4 => \m_payload_i_reg[65]\(62),
I5 => M_AXI_RDATA_I(62),
O => s_axi_rdata(30)
);
\s_axi_rdata[31]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"CAFFCAF0CA0FCA00"
)
port map (
I0 => \m_payload_i_reg[65]\(31),
I1 => M_AXI_RDATA_I(31),
I2 => \^use_wrap_buffer\,
I3 => \current_word_1_reg[2]_1\,
I4 => \m_payload_i_reg[65]\(63),
I5 => M_AXI_RDATA_I(63),
O => s_axi_rdata(31)
);
\s_axi_rdata[3]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"CAFFCAF0CA0FCA00"
)
port map (
I0 => \m_payload_i_reg[65]\(3),
I1 => M_AXI_RDATA_I(3),
I2 => \^use_wrap_buffer\,
I3 => \current_word_1_reg[2]_1\,
I4 => \m_payload_i_reg[65]\(35),
I5 => M_AXI_RDATA_I(35),
O => s_axi_rdata(3)
);
\s_axi_rdata[4]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"CAFFCAF0CA0FCA00"
)
port map (
I0 => \m_payload_i_reg[65]\(4),
I1 => M_AXI_RDATA_I(4),
I2 => \^use_wrap_buffer\,
I3 => \current_word_1_reg[2]_1\,
I4 => \m_payload_i_reg[65]\(36),
I5 => M_AXI_RDATA_I(36),
O => s_axi_rdata(4)
);
\s_axi_rdata[5]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"CAFFCAF0CA0FCA00"
)
port map (
I0 => \m_payload_i_reg[65]\(5),
I1 => M_AXI_RDATA_I(5),
I2 => \^use_wrap_buffer\,
I3 => \current_word_1_reg[2]_1\,
I4 => \m_payload_i_reg[65]\(37),
I5 => M_AXI_RDATA_I(37),
O => s_axi_rdata(5)
);
\s_axi_rdata[6]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"CAFFCAF0CA0FCA00"
)
port map (
I0 => \m_payload_i_reg[65]\(6),
I1 => M_AXI_RDATA_I(6),
I2 => \^use_wrap_buffer\,
I3 => \current_word_1_reg[2]_1\,
I4 => \m_payload_i_reg[65]\(38),
I5 => M_AXI_RDATA_I(38),
O => s_axi_rdata(6)
);
\s_axi_rdata[7]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"CAFFCAF0CA0FCA00"
)
port map (
I0 => \m_payload_i_reg[65]\(7),
I1 => M_AXI_RDATA_I(7),
I2 => \^use_wrap_buffer\,
I3 => \current_word_1_reg[2]_1\,
I4 => \m_payload_i_reg[65]\(39),
I5 => M_AXI_RDATA_I(39),
O => s_axi_rdata(7)
);
\s_axi_rdata[8]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"CAFFCAF0CA0FCA00"
)
port map (
I0 => \m_payload_i_reg[65]\(8),
I1 => M_AXI_RDATA_I(8),
I2 => \^use_wrap_buffer\,
I3 => \current_word_1_reg[2]_1\,
I4 => \m_payload_i_reg[65]\(40),
I5 => M_AXI_RDATA_I(40),
O => s_axi_rdata(8)
);
\s_axi_rdata[9]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"CAFFCAF0CA0FCA00"
)
port map (
I0 => \m_payload_i_reg[65]\(9),
I1 => M_AXI_RDATA_I(9),
I2 => \^use_wrap_buffer\,
I3 => \current_word_1_reg[2]_1\,
I4 => \m_payload_i_reg[65]\(41),
I5 => M_AXI_RDATA_I(41),
O => s_axi_rdata(9)
);
s_axi_rlast_INST_0: unisim.vcomponents.LUT4
generic map(
INIT => X"0F01"
)
port map (
I0 => s_axi_rlast_INST_0_i_1_n_0,
I1 => wrap_buffer_available,
I2 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[18]\,
I3 => \^use_wrap_buffer\,
O => \^s_axi_rlast\
);
s_axi_rlast_INST_0_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFD"
)
port map (
I0 => s_axi_rlast_INST_0_i_3_n_0,
I1 => s_axi_rlast_INST_0_i_4_n_0,
I2 => s_axi_rlast_INST_0_i_5_n_0,
I3 => s_axi_rlast_INST_0_i_6_n_0,
I4 => s_axi_rlast_INST_0_i_7_n_0,
I5 => s_axi_rlast_INST_0_i_8_n_0,
O => s_axi_rlast_INST_0_i_1_n_0
);
s_axi_rlast_INST_0_i_3: unisim.vcomponents.LUT5
generic map(
INIT => X"00053305"
)
port map (
I0 => \USE_RTL_LENGTH.length_counter_q_reg\(1),
I1 => Q(1),
I2 => \USE_RTL_LENGTH.length_counter_q_reg\(0),
I3 => \^first_mi_word_q\,
I4 => Q(0),
O => s_axi_rlast_INST_0_i_3_n_0
);
s_axi_rlast_INST_0_i_4: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(2),
I1 => \^first_mi_word_q\,
I2 => \USE_RTL_LENGTH.length_counter_q_reg\(2),
O => s_axi_rlast_INST_0_i_4_n_0
);
s_axi_rlast_INST_0_i_5: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(3),
I1 => \^first_mi_word_q\,
I2 => \USE_RTL_LENGTH.length_counter_q_reg\(3),
O => s_axi_rlast_INST_0_i_5_n_0
);
s_axi_rlast_INST_0_i_6: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(7),
I1 => \^first_mi_word_q\,
I2 => \USE_RTL_LENGTH.length_counter_q_reg\(7),
O => s_axi_rlast_INST_0_i_6_n_0
);
s_axi_rlast_INST_0_i_7: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(4),
I1 => \^first_mi_word_q\,
I2 => \USE_RTL_LENGTH.length_counter_q_reg\(4),
O => s_axi_rlast_INST_0_i_7_n_0
);
s_axi_rlast_INST_0_i_8: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFACCFA"
)
port map (
I0 => \USE_RTL_LENGTH.length_counter_q_reg\(6),
I1 => Q(6),
I2 => \USE_RTL_LENGTH.length_counter_q_reg\(5),
I3 => \^first_mi_word_q\,
I4 => Q(5),
O => s_axi_rlast_INST_0_i_8_n_0
);
\s_axi_rresp[0]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => rresp_wrap_buffer(0),
I1 => \^use_wrap_buffer\,
I2 => \m_payload_i_reg[65]\(64),
O => s_axi_rresp(0)
);
\s_axi_rresp[1]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => rresp_wrap_buffer(1),
I1 => \^use_wrap_buffer\,
I2 => \m_payload_i_reg[65]\(65),
O => s_axi_rresp(1)
);
s_axi_rvalid_INST_0: unisim.vcomponents.LUT3
generic map(
INIT => X"EA"
)
port map (
I0 => \^use_wrap_buffer\,
I1 => rd_cmd_valid,
I2 => mr_rvalid,
O => s_axi_rvalid
);
s_ready_i_i_6: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000010000"
)
port map (
I0 => s_axi_rlast_INST_0_i_8_n_0,
I1 => s_ready_i_i_9_n_0,
I2 => s_axi_rlast_INST_0_i_5_n_0,
I3 => s_axi_rlast_INST_0_i_4_n_0,
I4 => s_axi_rlast_INST_0_i_3_n_0,
I5 => wrap_buffer_available,
O => \USE_RTL_ADDR.addr_q_reg[4]\
);
s_ready_i_i_7: unisim.vcomponents.LUT4
generic map(
INIT => X"FE02"
)
port map (
I0 => \^current_word_1_reg[2]_0\(1),
I1 => Q(10),
I2 => \^first_word\,
I3 => Q(8),
O => \m_payload_i_reg[0]\
);
s_ready_i_i_9: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFACCFA"
)
port map (
I0 => \USE_RTL_LENGTH.length_counter_q_reg\(7),
I1 => Q(7),
I2 => \USE_RTL_LENGTH.length_counter_q_reg\(4),
I3 => \^first_mi_word_q\,
I4 => Q(4),
O => s_ready_i_i_9_n_0
);
use_wrap_buffer_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"1000FFFF10001000"
)
port map (
I0 => m_valid_i_reg,
I1 => s_axi_rlast_INST_0_i_1_n_0,
I2 => use_wrap_buffer_reg_0,
I3 => wrap_buffer_available,
I4 => use_wrap_buffer_i_3_n_0,
I5 => \^use_wrap_buffer\,
O => use_wrap_buffer_i_1_n_0
);
use_wrap_buffer_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"0040004000400044"
)
port map (
I0 => m_valid_i_reg,
I1 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_1\,
I2 => \^use_wrap_buffer\,
I3 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[18]\,
I4 => wrap_buffer_available,
I5 => s_axi_rlast_INST_0_i_1_n_0,
O => use_wrap_buffer_i_3_n_0
);
use_wrap_buffer_reg: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => use_wrap_buffer_i_1_n_0,
Q => \^use_wrap_buffer\,
R => \^sr\(0)
);
wrap_buffer_available_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFB8888"
)
port map (
I0 => p_7_in,
I1 => use_wrap_buffer_reg_0,
I2 => s_axi_rlast_INST_0_i_1_n_0,
I3 => m_valid_i_reg,
I4 => wrap_buffer_available,
O => wrap_buffer_available_i_1_n_0
);
wrap_buffer_available_reg: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => wrap_buffer_available_i_1_n_0,
Q => wrap_buffer_available,
R => \^sr\(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_us_1_axi_register_slice_v2_1_11_axic_register_slice is
port (
\aresetn_d_reg[1]_0\ : out STD_LOGIC;
s_ready_i_reg_0 : out STD_LOGIC;
sr_arvalid : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 44 downto 0 );
s_axi_arready : out STD_LOGIC;
\in\ : out STD_LOGIC_VECTOR ( 27 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 2 downto 0 );
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : in STD_LOGIC;
cmd_push_block_reg : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 60 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_us_1_axi_register_slice_v2_1_11_axic_register_slice : entity is "axi_register_slice_v2_1_11_axic_register_slice";
end system_auto_us_1_axi_register_slice_v2_1_11_axic_register_slice;
architecture STRUCTURE of system_auto_us_1_axi_register_slice_v2_1_11_axic_register_slice is
signal \^q\ : STD_LOGIC_VECTOR ( 44 downto 0 );
signal \USE_READ.read_addr_inst/access_need_extra_word__3\ : STD_LOGIC;
signal \USE_READ.read_addr_inst/cmd_next_word_ii__10\ : STD_LOGIC_VECTOR ( 2 to 2 );
signal \USE_READ.read_addr_inst/mi_word_intra_len__8\ : STD_LOGIC_VECTOR ( 2 to 2 );
signal \USE_RTL_FIFO.data_srl_reg[31][11]_srl32_i_2_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][11]_srl32_i_3_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][12]_srl32_i_2_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][16]_srl32_i_2_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][18]_srl32_i_2_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][18]_srl32_i_3_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][18]_srl32_i_4_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][18]_srl32_i_5_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][19]_srl32_i_3_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][19]_srl32_i_4_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][19]_srl32_i_5_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][26]_srl32_i_2_n_0\ : STD_LOGIC;
signal \^aresetn_d_reg[1]_0\ : STD_LOGIC;
signal \^in\ : STD_LOGIC_VECTOR ( 27 downto 0 );
signal \m_axi_araddr[0]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \m_axi_araddr[1]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \m_axi_araddr[1]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \m_axi_araddr[1]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \m_axi_araddr[1]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \m_axi_araddr[1]_INST_0_i_5_n_0\ : STD_LOGIC;
signal \m_axi_araddr[2]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \m_axi_araddr[2]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \m_axi_araddr[2]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \m_axi_arburst[0]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \m_axi_arburst[0]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \m_axi_arburst[1]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \m_axi_arburst[1]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \m_axi_arlen[0]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \m_axi_arlen[0]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \m_axi_arlen[0]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \m_axi_arlen[1]_INST_0_i_10_n_0\ : STD_LOGIC;
signal \m_axi_arlen[1]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \m_axi_arlen[1]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \m_axi_arlen[1]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \m_axi_arlen[1]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \m_axi_arlen[1]_INST_0_i_5_n_0\ : STD_LOGIC;
signal \m_axi_arlen[1]_INST_0_i_6_n_0\ : STD_LOGIC;
signal \m_axi_arlen[1]_INST_0_i_7_n_0\ : STD_LOGIC;
signal \m_axi_arlen[1]_INST_0_i_8_n_0\ : STD_LOGIC;
signal \m_axi_arlen[1]_INST_0_i_9_n_0\ : STD_LOGIC;
signal \m_axi_arlen[2]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \m_axi_arlen[2]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \m_axi_arlen[3]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \m_axi_arlen[3]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \m_axi_arlen[3]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \m_axi_arlen[3]_INST_0_i_5_n_0\ : STD_LOGIC;
signal \m_axi_arlen[3]_INST_0_i_6_n_0\ : STD_LOGIC;
signal \m_axi_arlen[3]_INST_0_i_7_n_0\ : STD_LOGIC;
signal \m_axi_arlen[4]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \m_axi_arlen[4]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \m_axi_arlen[5]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \m_axi_arlen[5]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \m_axi_arlen[6]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \m_axi_arlen[6]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \m_axi_arlen[7]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \m_axi_arlen[7]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \m_axi_arlen[7]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \m_payload_i[31]_i_1_n_0\ : STD_LOGIC;
signal m_valid_i_i_1_n_0 : STD_LOGIC;
signal s_axi_arlen_ii : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \^s_axi_arready\ : STD_LOGIC;
signal s_ready_i_i_1_n_0 : STD_LOGIC;
signal \^s_ready_i_reg_0\ : STD_LOGIC;
signal sr_araddr : STD_LOGIC_VECTOR ( 2 downto 0 );
signal sr_arburst : STD_LOGIC_VECTOR ( 1 downto 0 );
signal sr_arsize : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \^sr_arvalid\ : STD_LOGIC;
signal upsized_length : STD_LOGIC_VECTOR ( 3 to 3 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \USE_RTL_FIFO.data_srl_reg[31][10]_srl32_i_1\ : label is "soft_lutpair57";
attribute SOFT_HLUTNM of \USE_RTL_FIFO.data_srl_reg[31][11]_srl32_i_2\ : label is "soft_lutpair54";
attribute SOFT_HLUTNM of \USE_RTL_FIFO.data_srl_reg[31][12]_srl32_i_2\ : label is "soft_lutpair48";
attribute SOFT_HLUTNM of \USE_RTL_FIFO.data_srl_reg[31][16]_srl32_i_2\ : label is "soft_lutpair54";
attribute SOFT_HLUTNM of \USE_RTL_FIFO.data_srl_reg[31][18]_srl32_i_3\ : label is "soft_lutpair46";
attribute SOFT_HLUTNM of \USE_RTL_FIFO.data_srl_reg[31][18]_srl32_i_4\ : label is "soft_lutpair49";
attribute SOFT_HLUTNM of \USE_RTL_FIFO.data_srl_reg[31][18]_srl32_i_5\ : label is "soft_lutpair52";
attribute SOFT_HLUTNM of \USE_RTL_FIFO.data_srl_reg[31][19]_srl32_i_1\ : label is "soft_lutpair53";
attribute SOFT_HLUTNM of \USE_RTL_FIFO.data_srl_reg[31][19]_srl32_i_2\ : label is "soft_lutpair46";
attribute SOFT_HLUTNM of \USE_RTL_FIFO.data_srl_reg[31][19]_srl32_i_5\ : label is "soft_lutpair55";
attribute SOFT_HLUTNM of \USE_RTL_FIFO.data_srl_reg[31][25]_srl32_i_1\ : label is "soft_lutpair53";
attribute SOFT_HLUTNM of \USE_RTL_FIFO.data_srl_reg[31][26]_srl32_i_2\ : label is "soft_lutpair58";
attribute SOFT_HLUTNM of \USE_RTL_FIFO.data_srl_reg[31][29]_srl32_i_1\ : label is "soft_lutpair59";
attribute SOFT_HLUTNM of \USE_RTL_FIFO.data_srl_reg[31][8]_srl32_i_1\ : label is "soft_lutpair56";
attribute SOFT_HLUTNM of \USE_RTL_FIFO.data_srl_reg[31][9]_srl32_i_1\ : label is "soft_lutpair56";
attribute SOFT_HLUTNM of \m_axi_araddr[1]_INST_0_i_1\ : label is "soft_lutpair50";
attribute SOFT_HLUTNM of \m_axi_araddr[1]_INST_0_i_4\ : label is "soft_lutpair60";
attribute SOFT_HLUTNM of \m_axi_araddr[1]_INST_0_i_5\ : label is "soft_lutpair52";
attribute SOFT_HLUTNM of \m_axi_araddr[2]_INST_0_i_3\ : label is "soft_lutpair60";
attribute SOFT_HLUTNM of \m_axi_arburst[0]_INST_0_i_2\ : label is "soft_lutpair49";
attribute SOFT_HLUTNM of \m_axi_arburst[1]_INST_0_i_1\ : label is "soft_lutpair57";
attribute SOFT_HLUTNM of \m_axi_arlen[0]_INST_0_i_3\ : label is "soft_lutpair50";
attribute SOFT_HLUTNM of \m_axi_arlen[0]_INST_0_i_4\ : label is "soft_lutpair48";
attribute SOFT_HLUTNM of \m_axi_arlen[1]_INST_0_i_2\ : label is "soft_lutpair47";
attribute SOFT_HLUTNM of \m_axi_arlen[1]_INST_0_i_3\ : label is "soft_lutpair51";
attribute SOFT_HLUTNM of \m_axi_arlen[1]_INST_0_i_6\ : label is "soft_lutpair51";
attribute SOFT_HLUTNM of \m_axi_arlen[3]_INST_0_i_4\ : label is "soft_lutpair47";
attribute SOFT_HLUTNM of \m_axi_arlen[3]_INST_0_i_5\ : label is "soft_lutpair59";
attribute SOFT_HLUTNM of \m_axi_arlen[3]_INST_0_i_6\ : label is "soft_lutpair55";
attribute SOFT_HLUTNM of \m_axi_arlen[7]_INST_0_i_2\ : label is "soft_lutpair58";
begin
Q(44 downto 0) <= \^q\(44 downto 0);
\aresetn_d_reg[1]_0\ <= \^aresetn_d_reg[1]_0\;
\in\(27 downto 0) <= \^in\(27 downto 0);
s_axi_arready <= \^s_axi_arready\;
s_ready_i_reg_0 <= \^s_ready_i_reg_0\;
sr_arvalid <= \^sr_arvalid\;
\USE_RTL_FIFO.data_srl_reg[31][10]_srl32_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => sr_arsize(1),
I1 => sr_arsize(2),
I2 => sr_arsize(0),
O => \^in\(10)
);
\USE_RTL_FIFO.data_srl_reg[31][11]_srl32_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFAAAE"
)
port map (
I0 => \USE_RTL_FIFO.data_srl_reg[31][11]_srl32_i_2_n_0\,
I1 => s_axi_arlen_ii(0),
I2 => sr_arsize(1),
I3 => sr_arsize(0),
I4 => \USE_RTL_FIFO.data_srl_reg[31][11]_srl32_i_3_n_0\,
O => \^in\(11)
);
\USE_RTL_FIFO.data_srl_reg[31][11]_srl32_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"FD"
)
port map (
I0 => sr_arburst(1),
I1 => sr_arburst(0),
I2 => \m_axi_araddr[1]_INST_0_i_2_n_0\,
O => \USE_RTL_FIFO.data_srl_reg[31][11]_srl32_i_2_n_0\
);
\USE_RTL_FIFO.data_srl_reg[31][11]_srl32_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FEFEFCECFEAAFCA8"
)
port map (
I0 => s_axi_arlen_ii(2),
I1 => sr_arsize(2),
I2 => sr_arsize(1),
I3 => s_axi_arlen_ii(1),
I4 => sr_arsize(0),
I5 => s_axi_arlen_ii(0),
O => \USE_RTL_FIFO.data_srl_reg[31][11]_srl32_i_3_n_0\
);
\USE_RTL_FIFO.data_srl_reg[31][12]_srl32_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFF888"
)
port map (
I0 => \m_axi_araddr[1]_INST_0_i_4_n_0\,
I1 => s_axi_arlen_ii(0),
I2 => s_axi_arlen_ii(1),
I3 => \m_axi_araddr[1]_INST_0_i_5_n_0\,
I4 => \USE_RTL_FIFO.data_srl_reg[31][12]_srl32_i_2_n_0\,
I5 => \USE_RTL_FIFO.data_srl_reg[31][11]_srl32_i_2_n_0\,
O => \^in\(12)
);
\USE_RTL_FIFO.data_srl_reg[31][12]_srl32_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"FE00"
)
port map (
I0 => sr_arsize(0),
I1 => sr_arsize(1),
I2 => sr_arsize(2),
I3 => s_axi_arlen_ii(2),
O => \USE_RTL_FIFO.data_srl_reg[31][12]_srl32_i_2_n_0\
);
\USE_RTL_FIFO.data_srl_reg[31][13]_srl32_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFEFFEEFFFEEEEE"
)
port map (
I0 => s_axi_arlen_ii(2),
I1 => \USE_RTL_FIFO.data_srl_reg[31][11]_srl32_i_2_n_0\,
I2 => sr_arsize(0),
I3 => \m_axi_araddr[2]_INST_0_i_3_n_0\,
I4 => s_axi_arlen_ii(1),
I5 => s_axi_arlen_ii(0),
O => \^in\(13)
);
\USE_RTL_FIFO.data_srl_reg[31][16]_srl32_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000022202AA"
)
port map (
I0 => sr_araddr(2),
I1 => \m_axi_araddr[2]_INST_0_i_3_n_0\,
I2 => sr_arsize(0),
I3 => s_axi_arlen_ii(1),
I4 => s_axi_arlen_ii(0),
I5 => \USE_RTL_FIFO.data_srl_reg[31][16]_srl32_i_2_n_0\,
O => \^in\(14)
);
\USE_RTL_FIFO.data_srl_reg[31][16]_srl32_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFEF"
)
port map (
I0 => \m_axi_araddr[1]_INST_0_i_2_n_0\,
I1 => sr_arburst(0),
I2 => sr_arburst(1),
I3 => s_axi_arlen_ii(2),
O => \USE_RTL_FIFO.data_srl_reg[31][16]_srl32_i_2_n_0\
);
\USE_RTL_FIFO.data_srl_reg[31][17]_srl32_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"1414144414141044"
)
port map (
I0 => \m_axi_araddr[1]_INST_0_i_1_n_0\,
I1 => sr_araddr(0),
I2 => s_axi_arlen_ii(0),
I3 => sr_arburst(1),
I4 => sr_arburst(0),
I5 => \m_axi_araddr[1]_INST_0_i_2_n_0\,
O => \^in\(15)
);
\USE_RTL_FIFO.data_srl_reg[31][18]_srl32_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"8848488848884888"
)
port map (
I0 => sr_araddr(1),
I1 => \USE_RTL_FIFO.data_srl_reg[31][18]_srl32_i_2_n_0\,
I2 => \USE_RTL_FIFO.data_srl_reg[31][18]_srl32_i_3_n_0\,
I3 => \USE_RTL_FIFO.data_srl_reg[31][18]_srl32_i_4_n_0\,
I4 => s_axi_arlen_ii(0),
I5 => \USE_RTL_FIFO.data_srl_reg[31][18]_srl32_i_5_n_0\,
O => \^in\(16)
);
\USE_RTL_FIFO.data_srl_reg[31][18]_srl32_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FFFC0000EEFC"
)
port map (
I0 => s_axi_arlen_ii(2),
I1 => \USE_RTL_FIFO.data_srl_reg[31][11]_srl32_i_2_n_0\,
I2 => s_axi_arlen_ii(1),
I3 => sr_arsize(0),
I4 => \m_axi_araddr[2]_INST_0_i_3_n_0\,
I5 => s_axi_arlen_ii(0),
O => \USE_RTL_FIFO.data_srl_reg[31][18]_srl32_i_2_n_0\
);
\USE_RTL_FIFO.data_srl_reg[31][18]_srl32_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => sr_arburst(0),
I1 => sr_arburst(1),
O => \USE_RTL_FIFO.data_srl_reg[31][18]_srl32_i_3_n_0\
);
\USE_RTL_FIFO.data_srl_reg[31][18]_srl32_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"02030200"
)
port map (
I0 => s_axi_arlen_ii(0),
I1 => sr_arsize(2),
I2 => sr_arsize(1),
I3 => sr_arsize(0),
I4 => s_axi_arlen_ii(1),
O => \USE_RTL_FIFO.data_srl_reg[31][18]_srl32_i_4_n_0\
);
\USE_RTL_FIFO.data_srl_reg[31][18]_srl32_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"0002"
)
port map (
I0 => sr_araddr(0),
I1 => sr_arsize(0),
I2 => sr_arsize(1),
I3 => sr_arsize(2),
O => \USE_RTL_FIFO.data_srl_reg[31][18]_srl32_i_5_n_0\
);
\USE_RTL_FIFO.data_srl_reg[31][19]_srl32_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"8448"
)
port map (
I0 => sr_araddr(2),
I1 => \^in\(13),
I2 => \USE_READ.read_addr_inst/mi_word_intra_len__8\(2),
I3 => \USE_RTL_FIFO.data_srl_reg[31][19]_srl32_i_3_n_0\,
O => \^in\(17)
);
\USE_RTL_FIFO.data_srl_reg[31][19]_srl32_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFF04440"
)
port map (
I0 => \m_axi_araddr[1]_INST_0_i_5_n_0\,
I1 => s_axi_arlen_ii(1),
I2 => sr_arburst(0),
I3 => sr_arburst(1),
I4 => \m_axi_arlen[0]_INST_0_i_3_n_0\,
O => \USE_READ.read_addr_inst/mi_word_intra_len__8\(2)
);
\USE_RTL_FIFO.data_srl_reg[31][19]_srl32_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFEAAAAAEAEAAAAA"
)
port map (
I0 => \USE_RTL_FIFO.data_srl_reg[31][19]_srl32_i_4_n_0\,
I1 => \m_axi_arlen[1]_INST_0_i_6_n_0\,
I2 => \USE_RTL_FIFO.data_srl_reg[31][18]_srl32_i_5_n_0\,
I3 => \USE_RTL_FIFO.data_srl_reg[31][18]_srl32_i_4_n_0\,
I4 => \USE_RTL_FIFO.data_srl_reg[31][18]_srl32_i_3_n_0\,
I5 => sr_araddr(1),
O => \USE_RTL_FIFO.data_srl_reg[31][19]_srl32_i_3_n_0\
);
\USE_RTL_FIFO.data_srl_reg[31][19]_srl32_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"4040400040004000"
)
port map (
I0 => \m_axi_araddr[2]_INST_0_i_3_n_0\,
I1 => \USE_RTL_FIFO.data_srl_reg[31][19]_srl32_i_5_n_0\,
I2 => sr_araddr(0),
I3 => sr_arburst(0),
I4 => \m_axi_araddr[1]_INST_0_i_2_n_0\,
I5 => sr_arburst(1),
O => \USE_RTL_FIFO.data_srl_reg[31][19]_srl32_i_4_n_0\
);
\USE_RTL_FIFO.data_srl_reg[31][19]_srl32_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => sr_araddr(1),
I1 => s_axi_arlen_ii(0),
O => \USE_RTL_FIFO.data_srl_reg[31][19]_srl32_i_5_n_0\
);
\USE_RTL_FIFO.data_srl_reg[31][20]_srl32_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0001000100010000"
)
port map (
I0 => sr_arsize(2),
I1 => sr_arsize(1),
I2 => sr_arsize(0),
I3 => sr_araddr(0),
I4 => s_axi_arlen_ii(0),
I5 => \USE_RTL_FIFO.data_srl_reg[31][11]_srl32_i_2_n_0\,
O => \^in\(18)
);
\USE_RTL_FIFO.data_srl_reg[31][21]_srl32_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"8888882288888828"
)
port map (
I0 => \USE_RTL_FIFO.data_srl_reg[31][18]_srl32_i_2_n_0\,
I1 => sr_araddr(1),
I2 => sr_arsize(0),
I3 => sr_arsize(1),
I4 => sr_arsize(2),
I5 => sr_araddr(0),
O => \^in\(19)
);
\USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^in\(13),
I1 => \USE_READ.read_addr_inst/cmd_next_word_ii__10\(2),
O => \^in\(20)
);
\USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFF5FF07000A00F8"
)
port map (
I0 => sr_araddr(1),
I1 => sr_araddr(0),
I2 => sr_arsize(1),
I3 => sr_arsize(2),
I4 => sr_arsize(0),
I5 => sr_araddr(2),
O => \USE_READ.read_addr_inst/cmd_next_word_ii__10\(2)
);
\USE_RTL_FIFO.data_srl_reg[31][23]_srl32_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0100010001000000"
)
port map (
I0 => sr_arsize(2),
I1 => sr_arsize(1),
I2 => sr_arsize(0),
I3 => sr_araddr(0),
I4 => s_axi_arlen_ii(0),
I5 => \USE_RTL_FIFO.data_srl_reg[31][11]_srl32_i_2_n_0\,
O => \^in\(21)
);
\USE_RTL_FIFO.data_srl_reg[31][24]_srl32_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \USE_RTL_FIFO.data_srl_reg[31][18]_srl32_i_2_n_0\,
I1 => sr_araddr(1),
O => \^in\(22)
);
\USE_RTL_FIFO.data_srl_reg[31][25]_srl32_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^in\(13),
I1 => sr_araddr(2),
O => \^in\(23)
);
\USE_RTL_FIFO.data_srl_reg[31][26]_srl32_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"5554555455540000"
)
port map (
I0 => \USE_RTL_FIFO.data_srl_reg[31][26]_srl32_i_2_n_0\,
I1 => sr_araddr(2),
I2 => sr_araddr(1),
I3 => sr_araddr(0),
I4 => \m_axi_araddr[1]_INST_0_i_2_n_0\,
I5 => \USE_RTL_FIFO.data_srl_reg[31][11]_srl32_i_3_n_0\,
O => \^in\(24)
);
\USE_RTL_FIFO.data_srl_reg[31][26]_srl32_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"DF"
)
port map (
I0 => sr_arburst(1),
I1 => sr_arburst(0),
I2 => \^q\(33),
O => \USE_RTL_FIFO.data_srl_reg[31][26]_srl32_i_2_n_0\
);
\USE_RTL_FIFO.data_srl_reg[31][27]_srl32_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"13100000"
)
port map (
I0 => \m_axi_araddr[1]_INST_0_i_1_n_0\,
I1 => \USE_RTL_FIFO.data_srl_reg[31][11]_srl32_i_2_n_0\,
I2 => s_axi_arlen_ii(2),
I3 => \m_axi_arburst[0]_INST_0_i_2_n_0\,
I4 => \^q\(33),
O => \^in\(25)
);
\USE_RTL_FIFO.data_srl_reg[31][28]_srl32_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FEFEFE0000000000"
)
port map (
I0 => \m_axi_araddr[2]_INST_0_i_2_n_0\,
I1 => s_axi_arlen_ii(1),
I2 => s_axi_arlen_ii(0),
I3 => sr_arburst(1),
I4 => sr_arburst(0),
I5 => \^q\(33),
O => \^in\(26)
);
\USE_RTL_FIFO.data_srl_reg[31][29]_srl32_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => sr_arburst(1),
I1 => sr_arburst(0),
O => \^in\(27)
);
\USE_RTL_FIFO.data_srl_reg[31][8]_srl32_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"01"
)
port map (
I0 => sr_arsize(0),
I1 => sr_arsize(1),
I2 => sr_arsize(2),
O => \^in\(8)
);
\USE_RTL_FIFO.data_srl_reg[31][9]_srl32_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => sr_arsize(0),
I1 => sr_arsize(1),
I2 => sr_arsize(2),
O => \^in\(9)
);
\aresetn_d_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \out\,
CE => '1',
D => '1',
Q => \^aresetn_d_reg[1]_0\,
R => SR(0)
);
\aresetn_d_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \out\,
CE => '1',
D => \^aresetn_d_reg[1]_0\,
Q => \^s_ready_i_reg_0\,
R => SR(0)
);
\m_axi_araddr[0]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EEEEEEEFCCCCCCCC"
)
port map (
I0 => \m_axi_araddr[2]_INST_0_i_1_n_0\,
I1 => \m_axi_araddr[0]_INST_0_i_1_n_0\,
I2 => s_axi_arlen_ii(0),
I3 => \m_axi_araddr[1]_INST_0_i_2_n_0\,
I4 => \m_axi_araddr[1]_INST_0_i_1_n_0\,
I5 => sr_araddr(0),
O => m_axi_araddr(0)
);
\m_axi_araddr[0]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0004000000040400"
)
port map (
I0 => \m_axi_araddr[2]_INST_0_i_2_n_0\,
I1 => sr_araddr(0),
I2 => sr_arsize(2),
I3 => sr_arsize(1),
I4 => sr_arsize(0),
I5 => s_axi_arlen_ii(1),
O => \m_axi_araddr[0]_INST_0_i_1_n_0\
);
\m_axi_araddr[1]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFA0A0A0B0"
)
port map (
I0 => \m_axi_araddr[2]_INST_0_i_1_n_0\,
I1 => \m_axi_araddr[1]_INST_0_i_1_n_0\,
I2 => sr_araddr(1),
I3 => s_axi_arlen_ii(1),
I4 => \m_axi_araddr[1]_INST_0_i_2_n_0\,
I5 => \m_axi_araddr[1]_INST_0_i_3_n_0\,
O => m_axi_araddr(1)
);
\m_axi_araddr[1]_INST_0_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"FE"
)
port map (
I0 => sr_arsize(2),
I1 => sr_arsize(1),
I2 => sr_arsize(0),
O => \m_axi_araddr[1]_INST_0_i_1_n_0\
);
\m_axi_araddr[1]_INST_0_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => s_axi_arlen_ii(3),
I1 => s_axi_arlen_ii(6),
I2 => s_axi_arlen_ii(7),
I3 => s_axi_arlen_ii(5),
I4 => s_axi_arlen_ii(4),
O => \m_axi_araddr[1]_INST_0_i_2_n_0\
);
\m_axi_araddr[1]_INST_0_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0004000400044444"
)
port map (
I0 => \m_axi_araddr[2]_INST_0_i_2_n_0\,
I1 => sr_araddr(1),
I2 => \m_axi_araddr[1]_INST_0_i_4_n_0\,
I3 => s_axi_arlen_ii(1),
I4 => \m_axi_araddr[1]_INST_0_i_5_n_0\,
I5 => s_axi_arlen_ii(0),
O => \m_axi_araddr[1]_INST_0_i_3_n_0\
);
\m_axi_araddr[1]_INST_0_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => sr_arsize(0),
I1 => sr_arsize(2),
O => \m_axi_araddr[1]_INST_0_i_4_n_0\
);
\m_axi_araddr[1]_INST_0_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"EF"
)
port map (
I0 => sr_arsize(2),
I1 => sr_arsize(1),
I2 => sr_arsize(0),
O => \m_axi_araddr[1]_INST_0_i_5_n_0\
);
\m_axi_araddr[2]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAABABAB00000000"
)
port map (
I0 => \m_axi_araddr[2]_INST_0_i_1_n_0\,
I1 => \m_axi_araddr[2]_INST_0_i_2_n_0\,
I2 => \m_axi_araddr[2]_INST_0_i_3_n_0\,
I3 => sr_arsize(0),
I4 => s_axi_arlen_ii(1),
I5 => sr_araddr(2),
O => m_axi_araddr(2)
);
\m_axi_araddr[2]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"DFDFDFDFDFDFDFFF"
)
port map (
I0 => \^q\(33),
I1 => sr_arburst(0),
I2 => sr_arburst(1),
I3 => s_axi_arlen_ii(0),
I4 => s_axi_arlen_ii(1),
I5 => \m_axi_araddr[2]_INST_0_i_2_n_0\,
O => \m_axi_araddr[2]_INST_0_i_1_n_0\
);
\m_axi_araddr[2]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => s_axi_arlen_ii(4),
I1 => s_axi_arlen_ii(5),
I2 => s_axi_arlen_ii(7),
I3 => s_axi_arlen_ii(6),
I4 => s_axi_arlen_ii(3),
I5 => s_axi_arlen_ii(2),
O => \m_axi_araddr[2]_INST_0_i_2_n_0\
);
\m_axi_araddr[2]_INST_0_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => sr_arsize(1),
I1 => sr_arsize(2),
O => \m_axi_araddr[2]_INST_0_i_3_n_0\
);
\m_axi_arburst[0]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF00004000"
)
port map (
I0 => \m_axi_araddr[1]_INST_0_i_2_n_0\,
I1 => \^q\(33),
I2 => s_axi_arlen_ii(2),
I3 => sr_arburst(1),
I4 => \m_axi_araddr[1]_INST_0_i_1_n_0\,
I5 => \m_axi_arburst[0]_INST_0_i_1_n_0\,
O => m_axi_arburst(0)
);
\m_axi_arburst[0]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF10000000"
)
port map (
I0 => \m_axi_araddr[1]_INST_0_i_2_n_0\,
I1 => s_axi_arlen_ii(2),
I2 => \^q\(33),
I3 => sr_arburst(1),
I4 => \m_axi_arburst[0]_INST_0_i_2_n_0\,
I5 => sr_arburst(0),
O => \m_axi_arburst[0]_INST_0_i_1_n_0\
);
\m_axi_arburst[0]_INST_0_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"03030700"
)
port map (
I0 => sr_arsize(0),
I1 => sr_arsize(1),
I2 => sr_arsize(2),
I3 => s_axi_arlen_ii(0),
I4 => s_axi_arlen_ii(1),
O => \m_axi_arburst[0]_INST_0_i_2_n_0\
);
\m_axi_arburst[1]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFDFF00FF00"
)
port map (
I0 => \^q\(33),
I1 => \m_axi_araddr[1]_INST_0_i_2_n_0\,
I2 => \m_axi_arburst[1]_INST_0_i_1_n_0\,
I3 => \m_axi_arburst[1]_INST_0_i_2_n_0\,
I4 => sr_arburst(0),
I5 => sr_arburst(1),
O => m_axi_arburst(1)
);
\m_axi_arburst[1]_INST_0_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"F8"
)
port map (
I0 => sr_arsize(1),
I1 => sr_arsize(0),
I2 => sr_arsize(2),
O => \m_axi_arburst[1]_INST_0_i_1_n_0\
);
\m_axi_arburst[1]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF00A000BB00B100"
)
port map (
I0 => s_axi_arlen_ii(2),
I1 => s_axi_arlen_ii(0),
I2 => sr_arsize(0),
I3 => sr_arburst(1),
I4 => sr_arsize(1),
I5 => s_axi_arlen_ii(1),
O => \m_axi_arburst[1]_INST_0_i_2_n_0\
);
\m_axi_arlen[0]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"00151515FFEAEAEA"
)
port map (
I0 => \m_axi_arlen[0]_INST_0_i_1_n_0\,
I1 => s_axi_arlen_ii(1),
I2 => \m_axi_arlen[6]_INST_0_i_2_n_0\,
I3 => \m_axi_arlen[7]_INST_0_i_2_n_0\,
I4 => s_axi_arlen_ii(0),
I5 => \USE_READ.read_addr_inst/access_need_extra_word__3\,
O => \^in\(0)
);
\m_axi_arlen[0]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000A0C"
)
port map (
I0 => s_axi_arlen_ii(2),
I1 => s_axi_arlen_ii(3),
I2 => \m_axi_arlen[7]_INST_0_i_2_n_0\,
I3 => sr_arsize(0),
I4 => sr_arsize(1),
I5 => sr_arsize(2),
O => \m_axi_arlen[0]_INST_0_i_1_n_0\
);
\m_axi_arlen[0]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFF8F8F800000000"
)
port map (
I0 => sr_araddr(2),
I1 => \m_axi_arlen[0]_INST_0_i_3_n_0\,
I2 => \m_axi_arlen[1]_INST_0_i_3_n_0\,
I3 => \m_axi_arlen[0]_INST_0_i_4_n_0\,
I4 => \m_axi_arlen[3]_INST_0_i_6_n_0\,
I5 => \m_axi_arlen[3]_INST_0_i_5_n_0\,
O => \USE_READ.read_addr_inst/access_need_extra_word__3\
);
\m_axi_arlen[0]_INST_0_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"00230020"
)
port map (
I0 => s_axi_arlen_ii(0),
I1 => sr_arsize(2),
I2 => sr_arsize(1),
I3 => sr_arsize(0),
I4 => s_axi_arlen_ii(2),
O => \m_axi_arlen[0]_INST_0_i_3_n_0\
);
\m_axi_arlen[0]_INST_0_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"02030202"
)
port map (
I0 => sr_araddr(2),
I1 => sr_arsize(2),
I2 => sr_arsize(1),
I3 => sr_arsize(0),
I4 => s_axi_arlen_ii(2),
O => \m_axi_arlen[0]_INST_0_i_4_n_0\
);
\m_axi_arlen[1]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"151515EA15EA15EA"
)
port map (
I0 => \m_axi_arlen[1]_INST_0_i_1_n_0\,
I1 => \m_axi_arlen[1]_INST_0_i_2_n_0\,
I2 => \m_axi_arlen[1]_INST_0_i_3_n_0\,
I3 => \m_axi_arlen[1]_INST_0_i_4_n_0\,
I4 => \m_axi_arlen[7]_INST_0_i_2_n_0\,
I5 => s_axi_arlen_ii(1),
O => \^in\(1)
);
\m_axi_arlen[1]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAAFFAAEAAA"
)
port map (
I0 => \m_axi_arlen[1]_INST_0_i_5_n_0\,
I1 => \m_axi_arlen[1]_INST_0_i_6_n_0\,
I2 => sr_araddr(0),
I3 => \m_axi_arlen[3]_INST_0_i_4_n_0\,
I4 => sr_araddr(2),
I5 => \m_axi_araddr[1]_INST_0_i_1_n_0\,
O => \m_axi_arlen[1]_INST_0_i_1_n_0\
);
\m_axi_arlen[1]_INST_0_i_10\: unisim.vcomponents.LUT6
generic map(
INIT => X"1000000000000000"
)
port map (
I0 => sr_arsize(0),
I1 => sr_arsize(2),
I2 => sr_araddr(0),
I3 => sr_araddr(2),
I4 => s_axi_arlen_ii(0),
I5 => s_axi_arlen_ii(1),
O => \m_axi_arlen[1]_INST_0_i_10_n_0\
);
\m_axi_arlen[1]_INST_0_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"0800"
)
port map (
I0 => \^q\(33),
I1 => sr_arburst(0),
I2 => sr_arburst(1),
I3 => s_axi_arlen_ii(2),
O => \m_axi_arlen[1]_INST_0_i_2_n_0\
);
\m_axi_arlen[1]_INST_0_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"0000E888"
)
port map (
I0 => sr_araddr(2),
I1 => s_axi_arlen_ii(1),
I2 => s_axi_arlen_ii(0),
I3 => sr_araddr(1),
I4 => \m_axi_araddr[1]_INST_0_i_5_n_0\,
O => \m_axi_arlen[1]_INST_0_i_3_n_0\
);
\m_axi_arlen[1]_INST_0_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF888F888F888"
)
port map (
I0 => \m_axi_arlen[1]_INST_0_i_7_n_0\,
I1 => s_axi_arlen_ii(4),
I2 => \m_axi_arlen[1]_INST_0_i_8_n_0\,
I3 => s_axi_arlen_ii(3),
I4 => s_axi_arlen_ii(2),
I5 => \m_axi_arlen[6]_INST_0_i_2_n_0\,
O => \m_axi_arlen[1]_INST_0_i_4_n_0\
);
\m_axi_arlen[1]_INST_0_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF0000F4000000"
)
port map (
I0 => \m_axi_araddr[1]_INST_0_i_1_n_0\,
I1 => \m_axi_arlen[1]_INST_0_i_9_n_0\,
I2 => \m_axi_arlen[1]_INST_0_i_10_n_0\,
I3 => s_axi_arlen_ii(3),
I4 => \m_axi_arlen[3]_INST_0_i_5_n_0\,
I5 => \m_axi_arlen[7]_INST_0_i_3_n_0\,
O => \m_axi_arlen[1]_INST_0_i_5_n_0\
);
\m_axi_arlen[1]_INST_0_i_6\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => s_axi_arlen_ii(0),
I1 => s_axi_arlen_ii(1),
O => \m_axi_arlen[1]_INST_0_i_6_n_0\
);
\m_axi_arlen[1]_INST_0_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000000000A8"
)
port map (
I0 => \^q\(33),
I1 => sr_arburst(0),
I2 => sr_arburst(1),
I3 => sr_arsize(0),
I4 => sr_arsize(1),
I5 => sr_arsize(2),
O => \m_axi_arlen[1]_INST_0_i_7_n_0\
);
\m_axi_arlen[1]_INST_0_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"000000000000A800"
)
port map (
I0 => \^q\(33),
I1 => sr_arburst(0),
I2 => sr_arburst(1),
I3 => sr_arsize(0),
I4 => sr_arsize(1),
I5 => sr_arsize(2),
O => \m_axi_arlen[1]_INST_0_i_8_n_0\
);
\m_axi_arlen[1]_INST_0_i_9\: unisim.vcomponents.LUT6
generic map(
INIT => X"A8A8A800A800A800"
)
port map (
I0 => sr_araddr(1),
I1 => sr_araddr(2),
I2 => s_axi_arlen_ii(2),
I3 => s_axi_arlen_ii(1),
I4 => sr_araddr(0),
I5 => s_axi_arlen_ii(0),
O => \m_axi_arlen[1]_INST_0_i_9_n_0\
);
\m_axi_arlen[2]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"5555566656665666"
)
port map (
I0 => \m_axi_arlen[2]_INST_0_i_1_n_0\,
I1 => \m_axi_arlen[2]_INST_0_i_2_n_0\,
I2 => s_axi_arlen_ii(3),
I3 => \m_axi_arlen[6]_INST_0_i_2_n_0\,
I4 => \m_axi_arlen[7]_INST_0_i_2_n_0\,
I5 => s_axi_arlen_ii(2),
O => \^in\(2)
);
\m_axi_arlen[2]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFEAAAEAAAEAAA"
)
port map (
I0 => \m_axi_arlen[3]_INST_0_i_1_n_0\,
I1 => s_axi_arlen_ii(2),
I2 => \m_axi_arlen[3]_INST_0_i_5_n_0\,
I3 => \m_axi_arlen[7]_INST_0_i_3_n_0\,
I4 => s_axi_arlen_ii(4),
I5 => \m_axi_arlen[3]_INST_0_i_2_n_0\,
O => \m_axi_arlen[2]_INST_0_i_1_n_0\
);
\m_axi_arlen[2]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000A0C"
)
port map (
I0 => s_axi_arlen_ii(4),
I1 => s_axi_arlen_ii(5),
I2 => \m_axi_arlen[7]_INST_0_i_2_n_0\,
I3 => sr_arsize(0),
I4 => sr_arsize(1),
I5 => sr_arsize(2),
O => \m_axi_arlen[2]_INST_0_i_2_n_0\
);
\m_axi_arlen[3]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"00003777FFFFC888"
)
port map (
I0 => \m_axi_arlen[3]_INST_0_i_1_n_0\,
I1 => s_axi_arlen_ii(4),
I2 => s_axi_arlen_ii(5),
I3 => \m_axi_arlen[3]_INST_0_i_2_n_0\,
I4 => \m_axi_arlen[7]_INST_0_i_1_n_0\,
I5 => upsized_length(3),
O => \^in\(3)
);
\m_axi_arlen[3]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"5540400000000000"
)
port map (
I0 => \m_axi_araddr[1]_INST_0_i_5_n_0\,
I1 => sr_araddr(1),
I2 => s_axi_arlen_ii(0),
I3 => s_axi_arlen_ii(1),
I4 => sr_araddr(2),
I5 => \m_axi_arlen[3]_INST_0_i_4_n_0\,
O => \m_axi_arlen[3]_INST_0_i_1_n_0\
);
\m_axi_arlen[3]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"4040400040000000"
)
port map (
I0 => \m_axi_araddr[1]_INST_0_i_1_n_0\,
I1 => \m_axi_arlen[3]_INST_0_i_5_n_0\,
I2 => s_axi_arlen_ii(3),
I3 => sr_araddr(2),
I4 => s_axi_arlen_ii(2),
I5 => \m_axi_arlen[3]_INST_0_i_6_n_0\,
O => \m_axi_arlen[3]_INST_0_i_2_n_0\
);
\m_axi_arlen[3]_INST_0_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFF888"
)
port map (
I0 => s_axi_arlen_ii(3),
I1 => \m_axi_arlen[7]_INST_0_i_2_n_0\,
I2 => \m_axi_arlen[6]_INST_0_i_2_n_0\,
I3 => s_axi_arlen_ii(4),
I4 => \m_axi_arlen[3]_INST_0_i_7_n_0\,
O => upsized_length(3)
);
\m_axi_arlen[3]_INST_0_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => s_axi_arlen_ii(3),
I1 => sr_arburst(1),
I2 => sr_arburst(0),
I3 => \^q\(33),
I4 => s_axi_arlen_ii(2),
O => \m_axi_arlen[3]_INST_0_i_4_n_0\
);
\m_axi_arlen[3]_INST_0_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => sr_arburst(1),
I1 => sr_arburst(0),
I2 => \^q\(33),
O => \m_axi_arlen[3]_INST_0_i_5_n_0\
);
\m_axi_arlen[3]_INST_0_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"EA80"
)
port map (
I0 => sr_araddr(1),
I1 => s_axi_arlen_ii(0),
I2 => sr_araddr(0),
I3 => s_axi_arlen_ii(1),
O => \m_axi_arlen[3]_INST_0_i_6_n_0\
);
\m_axi_arlen[3]_INST_0_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000A0C"
)
port map (
I0 => s_axi_arlen_ii(5),
I1 => s_axi_arlen_ii(6),
I2 => \m_axi_arlen[7]_INST_0_i_2_n_0\,
I3 => sr_arsize(0),
I4 => sr_arsize(1),
I5 => sr_arsize(2),
O => \m_axi_arlen[3]_INST_0_i_7_n_0\
);
\m_axi_arlen[4]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"5555566656665666"
)
port map (
I0 => \m_axi_arlen[4]_INST_0_i_1_n_0\,
I1 => \m_axi_arlen[4]_INST_0_i_2_n_0\,
I2 => s_axi_arlen_ii(5),
I3 => \m_axi_arlen[6]_INST_0_i_2_n_0\,
I4 => \m_axi_arlen[7]_INST_0_i_2_n_0\,
I5 => s_axi_arlen_ii(4),
O => \^in\(4)
);
\m_axi_arlen[4]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF0000F0800000"
)
port map (
I0 => \m_axi_arlen[3]_INST_0_i_2_n_0\,
I1 => s_axi_arlen_ii(6),
I2 => s_axi_arlen_ii(5),
I3 => \m_axi_arlen[3]_INST_0_i_1_n_0\,
I4 => s_axi_arlen_ii(4),
I5 => \m_axi_arlen[7]_INST_0_i_1_n_0\,
O => \m_axi_arlen[4]_INST_0_i_1_n_0\
);
\m_axi_arlen[4]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000A0C"
)
port map (
I0 => s_axi_arlen_ii(6),
I1 => s_axi_arlen_ii(7),
I2 => \m_axi_arlen[7]_INST_0_i_2_n_0\,
I3 => sr_arsize(0),
I4 => sr_arsize(1),
I5 => sr_arsize(2),
O => \m_axi_arlen[4]_INST_0_i_2_n_0\
);
\m_axi_arlen[5]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"07070F0F07F8F0F0"
)
port map (
I0 => \m_axi_arlen[7]_INST_0_i_1_n_0\,
I1 => s_axi_arlen_ii(4),
I2 => \m_axi_arlen[5]_INST_0_i_1_n_0\,
I3 => \m_axi_arlen[7]_INST_0_i_2_n_0\,
I4 => s_axi_arlen_ii(5),
I5 => \m_axi_arlen[5]_INST_0_i_2_n_0\,
O => \^in\(5)
);
\m_axi_arlen[5]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"E0000000A0000000"
)
port map (
I0 => \m_axi_arlen[3]_INST_0_i_1_n_0\,
I1 => \m_axi_arlen[3]_INST_0_i_2_n_0\,
I2 => s_axi_arlen_ii(6),
I3 => s_axi_arlen_ii(4),
I4 => s_axi_arlen_ii(5),
I5 => s_axi_arlen_ii(7),
O => \m_axi_arlen[5]_INST_0_i_1_n_0\
);
\m_axi_arlen[5]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000000A0C00"
)
port map (
I0 => s_axi_arlen_ii(6),
I1 => s_axi_arlen_ii(7),
I2 => \m_axi_arlen[7]_INST_0_i_2_n_0\,
I3 => sr_arsize(0),
I4 => sr_arsize(1),
I5 => sr_arsize(2),
O => \m_axi_arlen[5]_INST_0_i_2_n_0\
);
\m_axi_arlen[6]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"556A6A6A"
)
port map (
I0 => \m_axi_arlen[6]_INST_0_i_1_n_0\,
I1 => \m_axi_arlen[6]_INST_0_i_2_n_0\,
I2 => s_axi_arlen_ii(7),
I3 => \m_axi_arlen[7]_INST_0_i_2_n_0\,
I4 => s_axi_arlen_ii(6),
O => \^in\(6)
);
\m_axi_arlen[6]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"E0000000A0000000"
)
port map (
I0 => \m_axi_arlen[7]_INST_0_i_1_n_0\,
I1 => \m_axi_arlen[3]_INST_0_i_1_n_0\,
I2 => s_axi_arlen_ii(6),
I3 => s_axi_arlen_ii(4),
I4 => s_axi_arlen_ii(5),
I5 => s_axi_arlen_ii(7),
O => \m_axi_arlen[6]_INST_0_i_1_n_0\
);
\m_axi_arlen[6]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"1000100010000000"
)
port map (
I0 => sr_arsize(0),
I1 => sr_arsize(2),
I2 => sr_arsize(1),
I3 => \^q\(33),
I4 => sr_arburst(0),
I5 => sr_arburst(1),
O => \m_axi_arlen[6]_INST_0_i_2_n_0\
);
\m_axi_arlen[7]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFF000080000000"
)
port map (
I0 => \m_axi_arlen[7]_INST_0_i_1_n_0\,
I1 => s_axi_arlen_ii(6),
I2 => s_axi_arlen_ii(4),
I3 => s_axi_arlen_ii(5),
I4 => s_axi_arlen_ii(7),
I5 => \m_axi_arlen[7]_INST_0_i_2_n_0\,
O => \^in\(7)
);
\m_axi_arlen[7]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000800000000000"
)
port map (
I0 => \m_axi_arlen[7]_INST_0_i_3_n_0\,
I1 => s_axi_arlen_ii(2),
I2 => \^q\(33),
I3 => sr_arburst(0),
I4 => sr_arburst(1),
I5 => s_axi_arlen_ii(3),
O => \m_axi_arlen[7]_INST_0_i_1_n_0\
);
\m_axi_arlen[7]_INST_0_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"1F"
)
port map (
I0 => sr_arburst(1),
I1 => sr_arburst(0),
I2 => \^q\(33),
O => \m_axi_arlen[7]_INST_0_i_2_n_0\
);
\m_axi_arlen[7]_INST_0_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000008000000000"
)
port map (
I0 => sr_araddr(2),
I1 => s_axi_arlen_ii(0),
I2 => s_axi_arlen_ii(1),
I3 => sr_arsize(0),
I4 => sr_arsize(2),
I5 => sr_arsize(1),
O => \m_axi_arlen[7]_INST_0_i_3_n_0\
);
\m_axi_arsize[0]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAAFFFFFFFE"
)
port map (
I0 => sr_arsize(0),
I1 => s_axi_arlen_ii(2),
I2 => \m_axi_araddr[1]_INST_0_i_2_n_0\,
I3 => s_axi_arlen_ii(1),
I4 => s_axi_arlen_ii(0),
I5 => \m_axi_arlen[7]_INST_0_i_2_n_0\,
O => m_axi_arsize(0)
);
\m_axi_arsize[1]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAAFFFFFFFE"
)
port map (
I0 => sr_arsize(1),
I1 => s_axi_arlen_ii(2),
I2 => \m_axi_araddr[1]_INST_0_i_2_n_0\,
I3 => s_axi_arlen_ii(1),
I4 => s_axi_arlen_ii(0),
I5 => \m_axi_arlen[7]_INST_0_i_2_n_0\,
O => m_axi_arsize(1)
);
\m_axi_arsize[2]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF000100000000"
)
port map (
I0 => s_axi_arlen_ii(2),
I1 => \m_axi_araddr[1]_INST_0_i_2_n_0\,
I2 => s_axi_arlen_ii(1),
I3 => s_axi_arlen_ii(0),
I4 => \m_axi_arlen[7]_INST_0_i_2_n_0\,
I5 => sr_arsize(2),
O => m_axi_arsize(2)
);
\m_payload_i[31]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^sr_arvalid\,
O => \m_payload_i[31]_i_1_n_0\
);
\m_payload_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(0),
Q => sr_araddr(0),
R => '0'
);
\m_payload_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(10),
Q => \^q\(7),
R => '0'
);
\m_payload_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(11),
Q => \^q\(8),
R => '0'
);
\m_payload_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(12),
Q => \^q\(9),
R => '0'
);
\m_payload_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(13),
Q => \^q\(10),
R => '0'
);
\m_payload_i_reg[14]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(14),
Q => \^q\(11),
R => '0'
);
\m_payload_i_reg[15]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(15),
Q => \^q\(12),
R => '0'
);
\m_payload_i_reg[16]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(16),
Q => \^q\(13),
R => '0'
);
\m_payload_i_reg[17]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(17),
Q => \^q\(14),
R => '0'
);
\m_payload_i_reg[18]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(18),
Q => \^q\(15),
R => '0'
);
\m_payload_i_reg[19]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(19),
Q => \^q\(16),
R => '0'
);
\m_payload_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(1),
Q => sr_araddr(1),
R => '0'
);
\m_payload_i_reg[20]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(20),
Q => \^q\(17),
R => '0'
);
\m_payload_i_reg[21]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(21),
Q => \^q\(18),
R => '0'
);
\m_payload_i_reg[22]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(22),
Q => \^q\(19),
R => '0'
);
\m_payload_i_reg[23]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(23),
Q => \^q\(20),
R => '0'
);
\m_payload_i_reg[24]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(24),
Q => \^q\(21),
R => '0'
);
\m_payload_i_reg[25]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(25),
Q => \^q\(22),
R => '0'
);
\m_payload_i_reg[26]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(26),
Q => \^q\(23),
R => '0'
);
\m_payload_i_reg[27]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(27),
Q => \^q\(24),
R => '0'
);
\m_payload_i_reg[28]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(28),
Q => \^q\(25),
R => '0'
);
\m_payload_i_reg[29]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(29),
Q => \^q\(26),
R => '0'
);
\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(2),
Q => sr_araddr(2),
R => '0'
);
\m_payload_i_reg[30]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(30),
Q => \^q\(27),
R => '0'
);
\m_payload_i_reg[31]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(31),
Q => \^q\(28),
R => '0'
);
\m_payload_i_reg[32]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(32),
Q => \^q\(29),
R => '0'
);
\m_payload_i_reg[33]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(33),
Q => \^q\(30),
R => '0'
);
\m_payload_i_reg[34]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(34),
Q => \^q\(31),
R => '0'
);
\m_payload_i_reg[35]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(35),
Q => sr_arsize(0),
R => '0'
);
\m_payload_i_reg[36]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(36),
Q => sr_arsize(1),
R => '0'
);
\m_payload_i_reg[37]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(37),
Q => sr_arsize(2),
R => '0'
);
\m_payload_i_reg[38]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(38),
Q => sr_arburst(0),
R => '0'
);
\m_payload_i_reg[39]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(39),
Q => sr_arburst(1),
R => '0'
);
\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(3),
Q => \^q\(0),
R => '0'
);
\m_payload_i_reg[40]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(40),
Q => \^q\(32),
R => '0'
);
\m_payload_i_reg[41]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(41),
Q => \^q\(33),
R => '0'
);
\m_payload_i_reg[42]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(42),
Q => \^q\(34),
R => '0'
);
\m_payload_i_reg[43]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(43),
Q => \^q\(35),
R => '0'
);
\m_payload_i_reg[44]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(44),
Q => s_axi_arlen_ii(0),
R => '0'
);
\m_payload_i_reg[45]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(45),
Q => s_axi_arlen_ii(1),
R => '0'
);
\m_payload_i_reg[46]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(46),
Q => s_axi_arlen_ii(2),
R => '0'
);
\m_payload_i_reg[47]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(47),
Q => s_axi_arlen_ii(3),
R => '0'
);
\m_payload_i_reg[48]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(48),
Q => s_axi_arlen_ii(4),
R => '0'
);
\m_payload_i_reg[49]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(49),
Q => s_axi_arlen_ii(5),
R => '0'
);
\m_payload_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(4),
Q => \^q\(1),
R => '0'
);
\m_payload_i_reg[50]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(50),
Q => s_axi_arlen_ii(6),
R => '0'
);
\m_payload_i_reg[51]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(51),
Q => s_axi_arlen_ii(7),
R => '0'
);
\m_payload_i_reg[52]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(52),
Q => \^q\(36),
R => '0'
);
\m_payload_i_reg[54]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(53),
Q => \^q\(37),
R => '0'
);
\m_payload_i_reg[55]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(54),
Q => \^q\(38),
R => '0'
);
\m_payload_i_reg[56]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(55),
Q => \^q\(39),
R => '0'
);
\m_payload_i_reg[57]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(56),
Q => \^q\(40),
R => '0'
);
\m_payload_i_reg[58]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(57),
Q => \^q\(41),
R => '0'
);
\m_payload_i_reg[59]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(58),
Q => \^q\(42),
R => '0'
);
\m_payload_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(5),
Q => \^q\(2),
R => '0'
);
\m_payload_i_reg[60]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(59),
Q => \^q\(43),
R => '0'
);
\m_payload_i_reg[61]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(60),
Q => \^q\(44),
R => '0'
);
\m_payload_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(6),
Q => \^q\(3),
R => '0'
);
\m_payload_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(7),
Q => \^q\(4),
R => '0'
);
\m_payload_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(8),
Q => \^q\(5),
R => '0'
);
\m_payload_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(9),
Q => \^q\(6),
R => '0'
);
m_valid_i_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"D100"
)
port map (
I0 => cmd_push_block_reg,
I1 => \^s_axi_arready\,
I2 => s_axi_arvalid,
I3 => \^s_ready_i_reg_0\,
O => m_valid_i_i_1_n_0
);
m_valid_i_reg: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => m_valid_i_i_1_n_0,
Q => \^sr_arvalid\,
R => '0'
);
s_ready_i_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"D5DF0000"
)
port map (
I0 => \^s_ready_i_reg_0\,
I1 => cmd_push_block_reg,
I2 => \^sr_arvalid\,
I3 => s_axi_arvalid,
I4 => \^aresetn_d_reg[1]_0\,
O => s_ready_i_i_1_n_0
);
s_ready_i_reg: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => s_ready_i_i_1_n_0,
Q => \^s_axi_arready\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_auto_us_1_axi_register_slice_v2_1_11_axic_register_slice__parameterized2\ is
port (
m_axi_rready : out STD_LOGIC;
\USE_RTL_LENGTH.first_mi_word_q_reg\ : out STD_LOGIC;
use_wrap_buffer_reg : out STD_LOGIC;
\USE_RTL_LENGTH.first_mi_word_q_reg_0\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 65 downto 0 );
\out\ : in STD_LOGIC;
rd_cmd_valid : in STD_LOGIC;
use_wrap_buffer : in STD_LOGIC;
m_axi_rlast : in STD_LOGIC;
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
use_wrap_buffer_reg_0 : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC;
\aresetn_d_reg[1]\ : in STD_LOGIC;
\aresetn_d_reg[0]\ : in STD_LOGIC;
first_mi_word_q : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_auto_us_1_axi_register_slice_v2_1_11_axic_register_slice__parameterized2\ : entity is "axi_register_slice_v2_1_11_axic_register_slice";
end \system_auto_us_1_axi_register_slice_v2_1_11_axic_register_slice__parameterized2\;
architecture STRUCTURE of \system_auto_us_1_axi_register_slice_v2_1_11_axic_register_slice__parameterized2\ is
signal \^m_axi_rlast\ : STD_LOGIC;
signal \^use_rtl_length.first_mi_word_q_reg\ : STD_LOGIC;
signal \^m_axi_rready\ : STD_LOGIC;
signal \m_valid_i_i_1__0_n_0\ : STD_LOGIC;
signal s_ready_i_i_1_n_0 : STD_LOGIC;
signal skid_buffer : STD_LOGIC_VECTOR ( 66 downto 0 );
signal \skid_buffer_reg_n_0_[0]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[10]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[11]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[12]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[13]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[14]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[15]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[16]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[17]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[18]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[19]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[1]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[20]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[21]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[22]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[23]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[24]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[25]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[26]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[27]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[28]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[29]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[2]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[30]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[31]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[32]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[33]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[34]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[35]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[36]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[37]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[38]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[39]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[3]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[40]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[41]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[42]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[43]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[44]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[45]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[46]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[47]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[48]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[49]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[4]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[50]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[51]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[52]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[53]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[54]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[55]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[56]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[57]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[58]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[59]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[5]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[60]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[61]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[62]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[63]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[64]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[65]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[66]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[6]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[7]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[8]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[9]\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \m_payload_i[10]_i_1\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \m_payload_i[11]_i_1\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \m_payload_i[12]_i_1\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \m_payload_i[13]_i_1\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \m_payload_i[14]_i_1\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \m_payload_i[15]_i_1\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \m_payload_i[16]_i_1\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \m_payload_i[17]_i_1\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \m_payload_i[18]_i_1\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \m_payload_i[19]_i_1\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \m_payload_i[1]_i_1\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \m_payload_i[20]_i_1\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \m_payload_i[21]_i_1\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \m_payload_i[22]_i_1\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \m_payload_i[23]_i_1\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \m_payload_i[24]_i_1\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \m_payload_i[25]_i_1\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \m_payload_i[26]_i_1\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \m_payload_i[27]_i_1\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \m_payload_i[28]_i_1\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \m_payload_i[29]_i_1\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \m_payload_i[2]_i_1\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \m_payload_i[30]_i_1\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \m_payload_i[31]_i_1__0\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \m_payload_i[32]_i_1\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \m_payload_i[33]_i_1\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \m_payload_i[34]_i_1\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \m_payload_i[35]_i_1\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \m_payload_i[36]_i_1\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \m_payload_i[37]_i_1\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \m_payload_i[38]_i_1\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \m_payload_i[39]_i_1\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \m_payload_i[3]_i_1\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \m_payload_i[40]_i_1\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \m_payload_i[41]_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \m_payload_i[42]_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \m_payload_i[43]_i_1\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \m_payload_i[44]_i_1\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \m_payload_i[45]_i_1\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \m_payload_i[46]_i_1\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \m_payload_i[47]_i_1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \m_payload_i[48]_i_1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \m_payload_i[49]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \m_payload_i[4]_i_1\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \m_payload_i[50]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \m_payload_i[51]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \m_payload_i[52]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \m_payload_i[53]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \m_payload_i[54]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \m_payload_i[55]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \m_payload_i[56]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \m_payload_i[57]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \m_payload_i[58]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \m_payload_i[59]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \m_payload_i[5]_i_1\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of \m_payload_i[60]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \m_payload_i[61]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \m_payload_i[62]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \m_payload_i[63]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \m_payload_i[64]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \m_payload_i[65]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \m_payload_i[66]_i_2\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \m_payload_i[6]_i_1\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of \m_payload_i[7]_i_1\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \m_payload_i[8]_i_1\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \m_payload_i[9]_i_1\ : label is "soft_lutpair28";
begin
\USE_RTL_LENGTH.first_mi_word_q_reg\ <= \^use_rtl_length.first_mi_word_q_reg\;
m_axi_rready <= \^m_axi_rready\;
\USE_RTL_LENGTH.first_mi_word_q_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"BF80"
)
port map (
I0 => \^m_axi_rlast\,
I1 => use_wrap_buffer_reg_0,
I2 => \^use_rtl_length.first_mi_word_q_reg\,
I3 => first_mi_word_q,
O => \USE_RTL_LENGTH.first_mi_word_q_reg_0\
);
\m_payload_i[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(0),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[0]\,
O => skid_buffer(0)
);
\m_payload_i[10]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(10),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[10]\,
O => skid_buffer(10)
);
\m_payload_i[11]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(11),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[11]\,
O => skid_buffer(11)
);
\m_payload_i[12]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(12),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[12]\,
O => skid_buffer(12)
);
\m_payload_i[13]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(13),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[13]\,
O => skid_buffer(13)
);
\m_payload_i[14]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(14),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[14]\,
O => skid_buffer(14)
);
\m_payload_i[15]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(15),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[15]\,
O => skid_buffer(15)
);
\m_payload_i[16]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(16),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[16]\,
O => skid_buffer(16)
);
\m_payload_i[17]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(17),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[17]\,
O => skid_buffer(17)
);
\m_payload_i[18]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(18),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[18]\,
O => skid_buffer(18)
);
\m_payload_i[19]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(19),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[19]\,
O => skid_buffer(19)
);
\m_payload_i[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(1),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[1]\,
O => skid_buffer(1)
);
\m_payload_i[20]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(20),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[20]\,
O => skid_buffer(20)
);
\m_payload_i[21]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(21),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[21]\,
O => skid_buffer(21)
);
\m_payload_i[22]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(22),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[22]\,
O => skid_buffer(22)
);
\m_payload_i[23]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(23),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[23]\,
O => skid_buffer(23)
);
\m_payload_i[24]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(24),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[24]\,
O => skid_buffer(24)
);
\m_payload_i[25]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(25),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[25]\,
O => skid_buffer(25)
);
\m_payload_i[26]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(26),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[26]\,
O => skid_buffer(26)
);
\m_payload_i[27]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(27),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[27]\,
O => skid_buffer(27)
);
\m_payload_i[28]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(28),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[28]\,
O => skid_buffer(28)
);
\m_payload_i[29]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(29),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[29]\,
O => skid_buffer(29)
);
\m_payload_i[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(2),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[2]\,
O => skid_buffer(2)
);
\m_payload_i[30]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(30),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[30]\,
O => skid_buffer(30)
);
\m_payload_i[31]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(31),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[31]\,
O => skid_buffer(31)
);
\m_payload_i[32]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(32),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[32]\,
O => skid_buffer(32)
);
\m_payload_i[33]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(33),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[33]\,
O => skid_buffer(33)
);
\m_payload_i[34]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(34),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[34]\,
O => skid_buffer(34)
);
\m_payload_i[35]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(35),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[35]\,
O => skid_buffer(35)
);
\m_payload_i[36]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(36),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[36]\,
O => skid_buffer(36)
);
\m_payload_i[37]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(37),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[37]\,
O => skid_buffer(37)
);
\m_payload_i[38]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(38),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[38]\,
O => skid_buffer(38)
);
\m_payload_i[39]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(39),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[39]\,
O => skid_buffer(39)
);
\m_payload_i[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(3),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[3]\,
O => skid_buffer(3)
);
\m_payload_i[40]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(40),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[40]\,
O => skid_buffer(40)
);
\m_payload_i[41]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(41),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[41]\,
O => skid_buffer(41)
);
\m_payload_i[42]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(42),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[42]\,
O => skid_buffer(42)
);
\m_payload_i[43]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(43),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[43]\,
O => skid_buffer(43)
);
\m_payload_i[44]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(44),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[44]\,
O => skid_buffer(44)
);
\m_payload_i[45]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(45),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[45]\,
O => skid_buffer(45)
);
\m_payload_i[46]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(46),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[46]\,
O => skid_buffer(46)
);
\m_payload_i[47]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(47),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[47]\,
O => skid_buffer(47)
);
\m_payload_i[48]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(48),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[48]\,
O => skid_buffer(48)
);
\m_payload_i[49]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(49),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[49]\,
O => skid_buffer(49)
);
\m_payload_i[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(4),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[4]\,
O => skid_buffer(4)
);
\m_payload_i[50]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(50),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[50]\,
O => skid_buffer(50)
);
\m_payload_i[51]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(51),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[51]\,
O => skid_buffer(51)
);
\m_payload_i[52]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(52),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[52]\,
O => skid_buffer(52)
);
\m_payload_i[53]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(53),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[53]\,
O => skid_buffer(53)
);
\m_payload_i[54]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(54),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[54]\,
O => skid_buffer(54)
);
\m_payload_i[55]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(55),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[55]\,
O => skid_buffer(55)
);
\m_payload_i[56]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(56),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[56]\,
O => skid_buffer(56)
);
\m_payload_i[57]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(57),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[57]\,
O => skid_buffer(57)
);
\m_payload_i[58]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(58),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[58]\,
O => skid_buffer(58)
);
\m_payload_i[59]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(59),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[59]\,
O => skid_buffer(59)
);
\m_payload_i[5]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(5),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[5]\,
O => skid_buffer(5)
);
\m_payload_i[60]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(60),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[60]\,
O => skid_buffer(60)
);
\m_payload_i[61]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(61),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[61]\,
O => skid_buffer(61)
);
\m_payload_i[62]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(62),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[62]\,
O => skid_buffer(62)
);
\m_payload_i[63]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(63),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[63]\,
O => skid_buffer(63)
);
\m_payload_i[64]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rresp(0),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[64]\,
O => skid_buffer(64)
);
\m_payload_i[65]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rresp(1),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[65]\,
O => skid_buffer(65)
);
\m_payload_i[66]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rlast,
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[66]\,
O => skid_buffer(66)
);
\m_payload_i[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(6),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[6]\,
O => skid_buffer(6)
);
\m_payload_i[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(7),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[7]\,
O => skid_buffer(7)
);
\m_payload_i[8]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(8),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[8]\,
O => skid_buffer(8)
);
\m_payload_i[9]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(9),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[9]\,
O => skid_buffer(9)
);
\m_payload_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(0),
Q => Q(0),
R => '0'
);
\m_payload_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(10),
Q => Q(10),
R => '0'
);
\m_payload_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(11),
Q => Q(11),
R => '0'
);
\m_payload_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(12),
Q => Q(12),
R => '0'
);
\m_payload_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(13),
Q => Q(13),
R => '0'
);
\m_payload_i_reg[14]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(14),
Q => Q(14),
R => '0'
);
\m_payload_i_reg[15]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(15),
Q => Q(15),
R => '0'
);
\m_payload_i_reg[16]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(16),
Q => Q(16),
R => '0'
);
\m_payload_i_reg[17]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(17),
Q => Q(17),
R => '0'
);
\m_payload_i_reg[18]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(18),
Q => Q(18),
R => '0'
);
\m_payload_i_reg[19]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(19),
Q => Q(19),
R => '0'
);
\m_payload_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(1),
Q => Q(1),
R => '0'
);
\m_payload_i_reg[20]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(20),
Q => Q(20),
R => '0'
);
\m_payload_i_reg[21]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(21),
Q => Q(21),
R => '0'
);
\m_payload_i_reg[22]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(22),
Q => Q(22),
R => '0'
);
\m_payload_i_reg[23]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(23),
Q => Q(23),
R => '0'
);
\m_payload_i_reg[24]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(24),
Q => Q(24),
R => '0'
);
\m_payload_i_reg[25]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(25),
Q => Q(25),
R => '0'
);
\m_payload_i_reg[26]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(26),
Q => Q(26),
R => '0'
);
\m_payload_i_reg[27]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(27),
Q => Q(27),
R => '0'
);
\m_payload_i_reg[28]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(28),
Q => Q(28),
R => '0'
);
\m_payload_i_reg[29]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(29),
Q => Q(29),
R => '0'
);
\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(2),
Q => Q(2),
R => '0'
);
\m_payload_i_reg[30]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(30),
Q => Q(30),
R => '0'
);
\m_payload_i_reg[31]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(31),
Q => Q(31),
R => '0'
);
\m_payload_i_reg[32]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(32),
Q => Q(32),
R => '0'
);
\m_payload_i_reg[33]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(33),
Q => Q(33),
R => '0'
);
\m_payload_i_reg[34]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(34),
Q => Q(34),
R => '0'
);
\m_payload_i_reg[35]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(35),
Q => Q(35),
R => '0'
);
\m_payload_i_reg[36]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(36),
Q => Q(36),
R => '0'
);
\m_payload_i_reg[37]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(37),
Q => Q(37),
R => '0'
);
\m_payload_i_reg[38]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(38),
Q => Q(38),
R => '0'
);
\m_payload_i_reg[39]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(39),
Q => Q(39),
R => '0'
);
\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(3),
Q => Q(3),
R => '0'
);
\m_payload_i_reg[40]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(40),
Q => Q(40),
R => '0'
);
\m_payload_i_reg[41]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(41),
Q => Q(41),
R => '0'
);
\m_payload_i_reg[42]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(42),
Q => Q(42),
R => '0'
);
\m_payload_i_reg[43]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(43),
Q => Q(43),
R => '0'
);
\m_payload_i_reg[44]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(44),
Q => Q(44),
R => '0'
);
\m_payload_i_reg[45]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(45),
Q => Q(45),
R => '0'
);
\m_payload_i_reg[46]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(46),
Q => Q(46),
R => '0'
);
\m_payload_i_reg[47]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(47),
Q => Q(47),
R => '0'
);
\m_payload_i_reg[48]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(48),
Q => Q(48),
R => '0'
);
\m_payload_i_reg[49]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(49),
Q => Q(49),
R => '0'
);
\m_payload_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(4),
Q => Q(4),
R => '0'
);
\m_payload_i_reg[50]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(50),
Q => Q(50),
R => '0'
);
\m_payload_i_reg[51]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(51),
Q => Q(51),
R => '0'
);
\m_payload_i_reg[52]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(52),
Q => Q(52),
R => '0'
);
\m_payload_i_reg[53]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(53),
Q => Q(53),
R => '0'
);
\m_payload_i_reg[54]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(54),
Q => Q(54),
R => '0'
);
\m_payload_i_reg[55]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(55),
Q => Q(55),
R => '0'
);
\m_payload_i_reg[56]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(56),
Q => Q(56),
R => '0'
);
\m_payload_i_reg[57]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(57),
Q => Q(57),
R => '0'
);
\m_payload_i_reg[58]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(58),
Q => Q(58),
R => '0'
);
\m_payload_i_reg[59]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(59),
Q => Q(59),
R => '0'
);
\m_payload_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(5),
Q => Q(5),
R => '0'
);
\m_payload_i_reg[60]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(60),
Q => Q(60),
R => '0'
);
\m_payload_i_reg[61]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(61),
Q => Q(61),
R => '0'
);
\m_payload_i_reg[62]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(62),
Q => Q(62),
R => '0'
);
\m_payload_i_reg[63]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(63),
Q => Q(63),
R => '0'
);
\m_payload_i_reg[64]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(64),
Q => Q(64),
R => '0'
);
\m_payload_i_reg[65]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(65),
Q => Q(65),
R => '0'
);
\m_payload_i_reg[66]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(66),
Q => \^m_axi_rlast\,
R => '0'
);
\m_payload_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(6),
Q => Q(6),
R => '0'
);
\m_payload_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(7),
Q => Q(7),
R => '0'
);
\m_payload_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(8),
Q => Q(8),
R => '0'
);
\m_payload_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(9),
Q => Q(9),
R => '0'
);
\m_valid_i_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"F4FF0000"
)
port map (
I0 => use_wrap_buffer_reg_0,
I1 => \^use_rtl_length.first_mi_word_q_reg\,
I2 => m_axi_rvalid,
I3 => \^m_axi_rready\,
I4 => \aresetn_d_reg[1]\,
O => \m_valid_i_i_1__0_n_0\
);
m_valid_i_reg: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \m_valid_i_i_1__0_n_0\,
Q => \^use_rtl_length.first_mi_word_q_reg\,
R => '0'
);
s_ready_i_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"F4FF0000"
)
port map (
I0 => m_axi_rvalid,
I1 => \^m_axi_rready\,
I2 => use_wrap_buffer_reg_0,
I3 => \^use_rtl_length.first_mi_word_q_reg\,
I4 => \aresetn_d_reg[0]\,
O => s_ready_i_i_1_n_0
);
s_ready_i_reg: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => s_ready_i_i_1_n_0,
Q => \^m_axi_rready\,
R => '0'
);
\skid_buffer_reg[0]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(0),
Q => \skid_buffer_reg_n_0_[0]\,
R => '0'
);
\skid_buffer_reg[10]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(10),
Q => \skid_buffer_reg_n_0_[10]\,
R => '0'
);
\skid_buffer_reg[11]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(11),
Q => \skid_buffer_reg_n_0_[11]\,
R => '0'
);
\skid_buffer_reg[12]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(12),
Q => \skid_buffer_reg_n_0_[12]\,
R => '0'
);
\skid_buffer_reg[13]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(13),
Q => \skid_buffer_reg_n_0_[13]\,
R => '0'
);
\skid_buffer_reg[14]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(14),
Q => \skid_buffer_reg_n_0_[14]\,
R => '0'
);
\skid_buffer_reg[15]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(15),
Q => \skid_buffer_reg_n_0_[15]\,
R => '0'
);
\skid_buffer_reg[16]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(16),
Q => \skid_buffer_reg_n_0_[16]\,
R => '0'
);
\skid_buffer_reg[17]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(17),
Q => \skid_buffer_reg_n_0_[17]\,
R => '0'
);
\skid_buffer_reg[18]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(18),
Q => \skid_buffer_reg_n_0_[18]\,
R => '0'
);
\skid_buffer_reg[19]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(19),
Q => \skid_buffer_reg_n_0_[19]\,
R => '0'
);
\skid_buffer_reg[1]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(1),
Q => \skid_buffer_reg_n_0_[1]\,
R => '0'
);
\skid_buffer_reg[20]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(20),
Q => \skid_buffer_reg_n_0_[20]\,
R => '0'
);
\skid_buffer_reg[21]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(21),
Q => \skid_buffer_reg_n_0_[21]\,
R => '0'
);
\skid_buffer_reg[22]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(22),
Q => \skid_buffer_reg_n_0_[22]\,
R => '0'
);
\skid_buffer_reg[23]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(23),
Q => \skid_buffer_reg_n_0_[23]\,
R => '0'
);
\skid_buffer_reg[24]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(24),
Q => \skid_buffer_reg_n_0_[24]\,
R => '0'
);
\skid_buffer_reg[25]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(25),
Q => \skid_buffer_reg_n_0_[25]\,
R => '0'
);
\skid_buffer_reg[26]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(26),
Q => \skid_buffer_reg_n_0_[26]\,
R => '0'
);
\skid_buffer_reg[27]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(27),
Q => \skid_buffer_reg_n_0_[27]\,
R => '0'
);
\skid_buffer_reg[28]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(28),
Q => \skid_buffer_reg_n_0_[28]\,
R => '0'
);
\skid_buffer_reg[29]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(29),
Q => \skid_buffer_reg_n_0_[29]\,
R => '0'
);
\skid_buffer_reg[2]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(2),
Q => \skid_buffer_reg_n_0_[2]\,
R => '0'
);
\skid_buffer_reg[30]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(30),
Q => \skid_buffer_reg_n_0_[30]\,
R => '0'
);
\skid_buffer_reg[31]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(31),
Q => \skid_buffer_reg_n_0_[31]\,
R => '0'
);
\skid_buffer_reg[32]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(32),
Q => \skid_buffer_reg_n_0_[32]\,
R => '0'
);
\skid_buffer_reg[33]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(33),
Q => \skid_buffer_reg_n_0_[33]\,
R => '0'
);
\skid_buffer_reg[34]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(34),
Q => \skid_buffer_reg_n_0_[34]\,
R => '0'
);
\skid_buffer_reg[35]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(35),
Q => \skid_buffer_reg_n_0_[35]\,
R => '0'
);
\skid_buffer_reg[36]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(36),
Q => \skid_buffer_reg_n_0_[36]\,
R => '0'
);
\skid_buffer_reg[37]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(37),
Q => \skid_buffer_reg_n_0_[37]\,
R => '0'
);
\skid_buffer_reg[38]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(38),
Q => \skid_buffer_reg_n_0_[38]\,
R => '0'
);
\skid_buffer_reg[39]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(39),
Q => \skid_buffer_reg_n_0_[39]\,
R => '0'
);
\skid_buffer_reg[3]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(3),
Q => \skid_buffer_reg_n_0_[3]\,
R => '0'
);
\skid_buffer_reg[40]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(40),
Q => \skid_buffer_reg_n_0_[40]\,
R => '0'
);
\skid_buffer_reg[41]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(41),
Q => \skid_buffer_reg_n_0_[41]\,
R => '0'
);
\skid_buffer_reg[42]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(42),
Q => \skid_buffer_reg_n_0_[42]\,
R => '0'
);
\skid_buffer_reg[43]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(43),
Q => \skid_buffer_reg_n_0_[43]\,
R => '0'
);
\skid_buffer_reg[44]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(44),
Q => \skid_buffer_reg_n_0_[44]\,
R => '0'
);
\skid_buffer_reg[45]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(45),
Q => \skid_buffer_reg_n_0_[45]\,
R => '0'
);
\skid_buffer_reg[46]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(46),
Q => \skid_buffer_reg_n_0_[46]\,
R => '0'
);
\skid_buffer_reg[47]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(47),
Q => \skid_buffer_reg_n_0_[47]\,
R => '0'
);
\skid_buffer_reg[48]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(48),
Q => \skid_buffer_reg_n_0_[48]\,
R => '0'
);
\skid_buffer_reg[49]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(49),
Q => \skid_buffer_reg_n_0_[49]\,
R => '0'
);
\skid_buffer_reg[4]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(4),
Q => \skid_buffer_reg_n_0_[4]\,
R => '0'
);
\skid_buffer_reg[50]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(50),
Q => \skid_buffer_reg_n_0_[50]\,
R => '0'
);
\skid_buffer_reg[51]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(51),
Q => \skid_buffer_reg_n_0_[51]\,
R => '0'
);
\skid_buffer_reg[52]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(52),
Q => \skid_buffer_reg_n_0_[52]\,
R => '0'
);
\skid_buffer_reg[53]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(53),
Q => \skid_buffer_reg_n_0_[53]\,
R => '0'
);
\skid_buffer_reg[54]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(54),
Q => \skid_buffer_reg_n_0_[54]\,
R => '0'
);
\skid_buffer_reg[55]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(55),
Q => \skid_buffer_reg_n_0_[55]\,
R => '0'
);
\skid_buffer_reg[56]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(56),
Q => \skid_buffer_reg_n_0_[56]\,
R => '0'
);
\skid_buffer_reg[57]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(57),
Q => \skid_buffer_reg_n_0_[57]\,
R => '0'
);
\skid_buffer_reg[58]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(58),
Q => \skid_buffer_reg_n_0_[58]\,
R => '0'
);
\skid_buffer_reg[59]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(59),
Q => \skid_buffer_reg_n_0_[59]\,
R => '0'
);
\skid_buffer_reg[5]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(5),
Q => \skid_buffer_reg_n_0_[5]\,
R => '0'
);
\skid_buffer_reg[60]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(60),
Q => \skid_buffer_reg_n_0_[60]\,
R => '0'
);
\skid_buffer_reg[61]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(61),
Q => \skid_buffer_reg_n_0_[61]\,
R => '0'
);
\skid_buffer_reg[62]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(62),
Q => \skid_buffer_reg_n_0_[62]\,
R => '0'
);
\skid_buffer_reg[63]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(63),
Q => \skid_buffer_reg_n_0_[63]\,
R => '0'
);
\skid_buffer_reg[64]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rresp(0),
Q => \skid_buffer_reg_n_0_[64]\,
R => '0'
);
\skid_buffer_reg[65]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rresp(1),
Q => \skid_buffer_reg_n_0_[65]\,
R => '0'
);
\skid_buffer_reg[66]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rlast,
Q => \skid_buffer_reg_n_0_[66]\,
R => '0'
);
\skid_buffer_reg[6]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(6),
Q => \skid_buffer_reg_n_0_[6]\,
R => '0'
);
\skid_buffer_reg[7]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(7),
Q => \skid_buffer_reg_n_0_[7]\,
R => '0'
);
\skid_buffer_reg[8]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(8),
Q => \skid_buffer_reg_n_0_[8]\,
R => '0'
);
\skid_buffer_reg[9]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(9),
Q => \skid_buffer_reg_n_0_[9]\,
R => '0'
);
use_wrap_buffer_i_2: unisim.vcomponents.LUT3
generic map(
INIT => X"07"
)
port map (
I0 => \^use_rtl_length.first_mi_word_q_reg\,
I1 => rd_cmd_valid,
I2 => use_wrap_buffer,
O => use_wrap_buffer_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_us_1_generic_baseblocks_v2_1_0_command_fifo is
port (
rd_cmd_valid : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[0]\ : out STD_LOGIC;
\m_payload_i_reg[0]_0\ : out STD_LOGIC;
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_0\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 10 downto 0 );
D : out STD_LOGIC_VECTOR ( 2 downto 0 );
\current_word_1_reg[2]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\s_axi_rdata[31]\ : out STD_LOGIC;
s_ready_i_reg : out STD_LOGIC;
cmd_push_block0 : out STD_LOGIC;
m_axi_arvalid : out STD_LOGIC;
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : in STD_LOGIC;
M_READY_I : in STD_LOGIC;
mr_rvalid : in STD_LOGIC;
use_wrap_buffer : in STD_LOGIC;
wrap_buffer_available_reg : in STD_LOGIC;
\pre_next_word_1_reg[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\pre_next_word_1_reg[1]\ : in STD_LOGIC;
first_word : in STD_LOGIC;
sr_arvalid : in STD_LOGIC;
cmd_push_block : in STD_LOGIC;
use_wrap_buffer_reg : in STD_LOGIC;
\current_word_1_reg[2]_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_rready : in STD_LOGIC;
m_axi_arready : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
\in\ : in STD_LOGIC_VECTOR ( 27 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_us_1_generic_baseblocks_v2_1_0_command_fifo : entity is "generic_baseblocks_v2_1_0_command_fifo";
end system_auto_us_1_generic_baseblocks_v2_1_0_command_fifo;
architecture STRUCTURE of system_auto_us_1_generic_baseblocks_v2_1_0_command_fifo is
signal \^q\ : STD_LOGIC_VECTOR ( 10 downto 0 );
signal \^use_ff_out.use_rtl_output_pipeline.m_valid_q_reg_0\ : STD_LOGIC;
signal \USE_RTL_ADDR.addr_q[0]_i_1_n_0\ : STD_LOGIC;
signal \USE_RTL_ADDR.addr_q[1]_i_1_n_0\ : STD_LOGIC;
signal \USE_RTL_ADDR.addr_q[2]_i_1_n_0\ : STD_LOGIC;
signal \USE_RTL_ADDR.addr_q[3]_i_1_n_0\ : STD_LOGIC;
signal \USE_RTL_ADDR.addr_q[4]_i_2_n_0\ : STD_LOGIC;
signal \USE_RTL_ADDR.addr_q[4]_i_3_n_0\ : STD_LOGIC;
signal \USE_RTL_ADDR.addr_q_reg__0\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \USE_RTL_FIFO.data_srl_reg[31][0]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][10]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][11]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][12]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][13]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][16]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][17]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][18]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][19]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][1]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][20]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][21]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][22]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][23]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][24]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][25]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][26]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][27]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][28]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][29]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][2]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][3]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][4]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][5]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][6]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][7]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][8]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][9]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_VALID_WRITE.buffer_Full_q_i_1_n_0\ : STD_LOGIC;
signal \USE_RTL_VALID_WRITE.buffer_Full_q_i_2_n_0\ : STD_LOGIC;
signal addr_q : STD_LOGIC;
signal buffer_Full_q : STD_LOGIC;
signal cmd_last_word : STD_LOGIC_VECTOR ( 2 downto 0 );
signal cmd_step : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \^current_word_1_reg[2]\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal data_Exists_I : STD_LOGIC;
signal data_Exists_I_i_2_n_0 : STD_LOGIC;
signal \^m_payload_i_reg[0]\ : STD_LOGIC;
signal \^m_payload_i_reg[0]_0\ : STD_LOGIC;
signal next_Data_Exists : STD_LOGIC;
signal \pre_next_word_1[1]_i_2_n_0\ : STD_LOGIC;
signal \pre_next_word_1[2]_i_3_n_0\ : STD_LOGIC;
signal rd_cmd_complete_wrap : STD_LOGIC;
signal rd_cmd_first_word : STD_LOGIC_VECTOR ( 2 downto 0 );
signal rd_cmd_mask : STD_LOGIC_VECTOR ( 2 downto 0 );
signal rd_cmd_modified : STD_LOGIC;
signal rd_cmd_next_word : STD_LOGIC_VECTOR ( 2 downto 0 );
signal rd_cmd_offset : STD_LOGIC_VECTOR ( 2 to 2 );
signal \^rd_cmd_valid\ : STD_LOGIC;
signal s_axi_rlast_INST_0_i_10_n_0 : STD_LOGIC;
signal s_axi_rlast_INST_0_i_11_n_0 : STD_LOGIC;
signal s_axi_rlast_INST_0_i_9_n_0 : STD_LOGIC;
signal s_ready_i_i_4_n_0 : STD_LOGIC;
signal s_ready_i_i_5_n_0 : STD_LOGIC;
signal s_ready_i_i_8_n_0 : STD_LOGIC;
signal valid_Write : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][0]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][10]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][11]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][12]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][13]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][16]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][17]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][18]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][19]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][1]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][20]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][21]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][22]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][23]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][24]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][25]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][26]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][27]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][28]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][29]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][2]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][3]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][4]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][5]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][6]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][7]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][8]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][9]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \USE_RTL_ADDR.addr_q[0]_i_1\ : label is "soft_lutpair43";
attribute SOFT_HLUTNM of \USE_RTL_ADDR.addr_q[2]_i_1\ : label is "soft_lutpair43";
attribute srl_bus_name : string;
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][0]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name : string;
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][0]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][0]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][10]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][10]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][10]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][11]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][11]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][11]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][12]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][12]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][12]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][13]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][13]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][13]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][16]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][16]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][16]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][17]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][17]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][17]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][18]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][18]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][18]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][19]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][19]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][19]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][1]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][1]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][1]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][20]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][20]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][20]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][21]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][21]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][21]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][22]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][22]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][22]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][23]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][23]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][23]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][24]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][24]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][24]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][25]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][25]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][25]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][26]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][26]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][26]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][27]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][27]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][27]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][28]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][28]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][28]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][29]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][29]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][29]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][2]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][2]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][2]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][3]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][3]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][3]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][4]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][4]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][4]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][5]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][5]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][5]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][6]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][6]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][6]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][7]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][7]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][7]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][8]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][8]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][8]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][9]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][9]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][9]_srl32 ";
attribute SOFT_HLUTNM of \USE_RTL_VALID_WRITE.buffer_Full_q_i_2\ : label is "soft_lutpair44";
attribute SOFT_HLUTNM of cmd_push_block_i_1 : label is "soft_lutpair45";
attribute SOFT_HLUTNM of \current_word_1[0]_i_1\ : label is "soft_lutpair42";
attribute SOFT_HLUTNM of \current_word_1[2]_i_1\ : label is "soft_lutpair41";
attribute SOFT_HLUTNM of data_Exists_I_i_2 : label is "soft_lutpair44";
attribute SOFT_HLUTNM of m_axi_arvalid_INST_0 : label is "soft_lutpair45";
attribute SOFT_HLUTNM of s_axi_rlast_INST_0_i_10 : label is "soft_lutpair41";
attribute SOFT_HLUTNM of s_ready_i_i_8 : label is "soft_lutpair42";
begin
Q(10 downto 0) <= \^q\(10 downto 0);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_0\ <= \^use_ff_out.use_rtl_output_pipeline.m_valid_q_reg_0\;
\current_word_1_reg[2]\(2 downto 0) <= \^current_word_1_reg[2]\(2 downto 0);
\m_payload_i_reg[0]\ <= \^m_payload_i_reg[0]\;
\m_payload_i_reg[0]_0\ <= \^m_payload_i_reg[0]_0\;
rd_cmd_valid <= \^rd_cmd_valid\;
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[0]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => M_READY_I,
D => \USE_RTL_FIFO.data_srl_reg[31][0]_srl32_n_0\,
Q => \^q\(0),
R => SR(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[10]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => M_READY_I,
D => \USE_RTL_FIFO.data_srl_reg[31][10]_srl32_n_0\,
Q => cmd_step(2),
R => SR(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[11]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => M_READY_I,
D => \USE_RTL_FIFO.data_srl_reg[31][11]_srl32_n_0\,
Q => rd_cmd_mask(0),
R => SR(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[12]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => M_READY_I,
D => \USE_RTL_FIFO.data_srl_reg[31][12]_srl32_n_0\,
Q => rd_cmd_mask(1),
R => SR(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[13]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => M_READY_I,
D => \USE_RTL_FIFO.data_srl_reg[31][13]_srl32_n_0\,
Q => rd_cmd_mask(2),
R => SR(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[16]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => M_READY_I,
D => \USE_RTL_FIFO.data_srl_reg[31][16]_srl32_n_0\,
Q => rd_cmd_offset(2),
R => SR(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[17]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => M_READY_I,
D => \USE_RTL_FIFO.data_srl_reg[31][17]_srl32_n_0\,
Q => cmd_last_word(0),
R => SR(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[18]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => M_READY_I,
D => \USE_RTL_FIFO.data_srl_reg[31][18]_srl32_n_0\,
Q => cmd_last_word(1),
R => SR(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[19]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => M_READY_I,
D => \USE_RTL_FIFO.data_srl_reg[31][19]_srl32_n_0\,
Q => cmd_last_word(2),
R => SR(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[1]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => M_READY_I,
D => \USE_RTL_FIFO.data_srl_reg[31][1]_srl32_n_0\,
Q => \^q\(1),
R => SR(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[20]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => M_READY_I,
D => \USE_RTL_FIFO.data_srl_reg[31][20]_srl32_n_0\,
Q => rd_cmd_next_word(0),
R => SR(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[21]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => M_READY_I,
D => \USE_RTL_FIFO.data_srl_reg[31][21]_srl32_n_0\,
Q => \^q\(8),
R => SR(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[22]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => M_READY_I,
D => \USE_RTL_FIFO.data_srl_reg[31][22]_srl32_n_0\,
Q => rd_cmd_next_word(2),
R => SR(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[23]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => M_READY_I,
D => \USE_RTL_FIFO.data_srl_reg[31][23]_srl32_n_0\,
Q => rd_cmd_first_word(0),
R => SR(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[24]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => M_READY_I,
D => \USE_RTL_FIFO.data_srl_reg[31][24]_srl32_n_0\,
Q => rd_cmd_first_word(1),
R => SR(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => M_READY_I,
D => \USE_RTL_FIFO.data_srl_reg[31][25]_srl32_n_0\,
Q => rd_cmd_first_word(2),
R => SR(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[26]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => M_READY_I,
D => \USE_RTL_FIFO.data_srl_reg[31][26]_srl32_n_0\,
Q => \^q\(9),
R => SR(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[27]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => M_READY_I,
D => \USE_RTL_FIFO.data_srl_reg[31][27]_srl32_n_0\,
Q => rd_cmd_complete_wrap,
R => SR(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => M_READY_I,
D => \USE_RTL_FIFO.data_srl_reg[31][28]_srl32_n_0\,
Q => rd_cmd_modified,
R => SR(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => M_READY_I,
D => \USE_RTL_FIFO.data_srl_reg[31][29]_srl32_n_0\,
Q => \^q\(10),
R => SR(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[2]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => M_READY_I,
D => \USE_RTL_FIFO.data_srl_reg[31][2]_srl32_n_0\,
Q => \^q\(2),
R => SR(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[3]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => M_READY_I,
D => \USE_RTL_FIFO.data_srl_reg[31][3]_srl32_n_0\,
Q => \^q\(3),
R => SR(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[4]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => M_READY_I,
D => \USE_RTL_FIFO.data_srl_reg[31][4]_srl32_n_0\,
Q => \^q\(4),
R => SR(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[5]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => M_READY_I,
D => \USE_RTL_FIFO.data_srl_reg[31][5]_srl32_n_0\,
Q => \^q\(5),
R => SR(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[6]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => M_READY_I,
D => \USE_RTL_FIFO.data_srl_reg[31][6]_srl32_n_0\,
Q => \^q\(6),
R => SR(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[7]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => M_READY_I,
D => \USE_RTL_FIFO.data_srl_reg[31][7]_srl32_n_0\,
Q => \^q\(7),
R => SR(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[8]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => M_READY_I,
D => \USE_RTL_FIFO.data_srl_reg[31][8]_srl32_n_0\,
Q => cmd_step(0),
R => SR(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[9]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => M_READY_I,
D => \USE_RTL_FIFO.data_srl_reg[31][9]_srl32_n_0\,
Q => cmd_step(1),
R => SR(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => M_READY_I,
D => data_Exists_I,
Q => \^rd_cmd_valid\,
R => SR(0)
);
\USE_RTL_ADDR.addr_q[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \USE_RTL_ADDR.addr_q_reg__0\(0),
O => \USE_RTL_ADDR.addr_q[0]_i_1_n_0\
);
\USE_RTL_ADDR.addr_q[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"9999999999999699"
)
port map (
I0 => \USE_RTL_ADDR.addr_q_reg__0\(0),
I1 => \USE_RTL_ADDR.addr_q_reg__0\(1),
I2 => cmd_push_block,
I3 => sr_arvalid,
I4 => buffer_Full_q,
I5 => M_READY_I,
O => \USE_RTL_ADDR.addr_q[1]_i_1_n_0\
);
\USE_RTL_ADDR.addr_q[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"DFBA2045"
)
port map (
I0 => \USE_RTL_ADDR.addr_q_reg__0\(0),
I1 => M_READY_I,
I2 => valid_Write,
I3 => \USE_RTL_ADDR.addr_q_reg__0\(1),
I4 => \USE_RTL_ADDR.addr_q_reg__0\(2),
O => \USE_RTL_ADDR.addr_q[2]_i_1_n_0\
);
\USE_RTL_ADDR.addr_q[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F7FF0800EFEE1011"
)
port map (
I0 => \USE_RTL_ADDR.addr_q_reg__0\(1),
I1 => \USE_RTL_ADDR.addr_q_reg__0\(0),
I2 => M_READY_I,
I3 => valid_Write,
I4 => \USE_RTL_ADDR.addr_q_reg__0\(3),
I5 => \USE_RTL_ADDR.addr_q_reg__0\(2),
O => \USE_RTL_ADDR.addr_q[3]_i_1_n_0\
);
\USE_RTL_ADDR.addr_q[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"8080808080508080"
)
port map (
I0 => M_READY_I,
I1 => data_Exists_I_i_2_n_0,
I2 => data_Exists_I,
I3 => cmd_push_block,
I4 => sr_arvalid,
I5 => buffer_Full_q,
O => addr_q
);
\USE_RTL_ADDR.addr_q[4]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFE80000001"
)
port map (
I0 => \USE_RTL_ADDR.addr_q_reg__0\(3),
I1 => \USE_RTL_ADDR.addr_q_reg__0\(2),
I2 => \USE_RTL_ADDR.addr_q_reg__0\(1),
I3 => \USE_RTL_ADDR.addr_q_reg__0\(0),
I4 => \USE_RTL_ADDR.addr_q[4]_i_3_n_0\,
I5 => \USE_RTL_ADDR.addr_q_reg__0\(4),
O => \USE_RTL_ADDR.addr_q[4]_i_2_n_0\
);
\USE_RTL_ADDR.addr_q[4]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"8888080888880888"
)
port map (
I0 => valid_Write,
I1 => \^rd_cmd_valid\,
I2 => use_wrap_buffer_reg,
I3 => use_wrap_buffer,
I4 => \^use_ff_out.use_rtl_output_pipeline.m_valid_q_reg_0\,
I5 => wrap_buffer_available_reg,
O => \USE_RTL_ADDR.addr_q[4]_i_3_n_0\
);
\USE_RTL_ADDR.addr_q_reg[0]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => addr_q,
D => \USE_RTL_ADDR.addr_q[0]_i_1_n_0\,
Q => \USE_RTL_ADDR.addr_q_reg__0\(0),
R => SR(0)
);
\USE_RTL_ADDR.addr_q_reg[1]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => addr_q,
D => \USE_RTL_ADDR.addr_q[1]_i_1_n_0\,
Q => \USE_RTL_ADDR.addr_q_reg__0\(1),
R => SR(0)
);
\USE_RTL_ADDR.addr_q_reg[2]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => addr_q,
D => \USE_RTL_ADDR.addr_q[2]_i_1_n_0\,
Q => \USE_RTL_ADDR.addr_q_reg__0\(2),
R => SR(0)
);
\USE_RTL_ADDR.addr_q_reg[3]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => addr_q,
D => \USE_RTL_ADDR.addr_q[3]_i_1_n_0\,
Q => \USE_RTL_ADDR.addr_q_reg__0\(3),
R => SR(0)
);
\USE_RTL_ADDR.addr_q_reg[4]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => addr_q,
D => \USE_RTL_ADDR.addr_q[4]_i_2_n_0\,
Q => \USE_RTL_ADDR.addr_q_reg__0\(4),
R => SR(0)
);
\USE_RTL_FIFO.data_srl_reg[31][0]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => \out\,
D => \in\(0),
Q => \USE_RTL_FIFO.data_srl_reg[31][0]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][0]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][0]_srl32_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => buffer_Full_q,
I1 => sr_arvalid,
I2 => cmd_push_block,
O => valid_Write
);
\USE_RTL_FIFO.data_srl_reg[31][10]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => \out\,
D => \in\(10),
Q => \USE_RTL_FIFO.data_srl_reg[31][10]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][10]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][11]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => \out\,
D => \in\(11),
Q => \USE_RTL_FIFO.data_srl_reg[31][11]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][11]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][12]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => \out\,
D => \in\(12),
Q => \USE_RTL_FIFO.data_srl_reg[31][12]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][12]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][13]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => \out\,
D => \in\(13),
Q => \USE_RTL_FIFO.data_srl_reg[31][13]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][13]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][16]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => \out\,
D => \in\(14),
Q => \USE_RTL_FIFO.data_srl_reg[31][16]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][16]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][17]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => \out\,
D => \in\(15),
Q => \USE_RTL_FIFO.data_srl_reg[31][17]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][17]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][18]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => \out\,
D => \in\(16),
Q => \USE_RTL_FIFO.data_srl_reg[31][18]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][18]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][19]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => \out\,
D => \in\(17),
Q => \USE_RTL_FIFO.data_srl_reg[31][19]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][19]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][1]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => \out\,
D => \in\(1),
Q => \USE_RTL_FIFO.data_srl_reg[31][1]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][1]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][20]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => \out\,
D => \in\(18),
Q => \USE_RTL_FIFO.data_srl_reg[31][20]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][20]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][21]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => \out\,
D => \in\(19),
Q => \USE_RTL_FIFO.data_srl_reg[31][21]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][21]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][22]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => \out\,
D => \in\(20),
Q => \USE_RTL_FIFO.data_srl_reg[31][22]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][22]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][23]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => \out\,
D => \in\(21),
Q => \USE_RTL_FIFO.data_srl_reg[31][23]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][23]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][24]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => \out\,
D => \in\(22),
Q => \USE_RTL_FIFO.data_srl_reg[31][24]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][24]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][25]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => \out\,
D => \in\(23),
Q => \USE_RTL_FIFO.data_srl_reg[31][25]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][25]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][26]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => \out\,
D => \in\(24),
Q => \USE_RTL_FIFO.data_srl_reg[31][26]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][26]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][27]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => \out\,
D => \in\(25),
Q => \USE_RTL_FIFO.data_srl_reg[31][27]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][27]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][28]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => \out\,
D => \in\(26),
Q => \USE_RTL_FIFO.data_srl_reg[31][28]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][28]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][29]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => \out\,
D => \in\(27),
Q => \USE_RTL_FIFO.data_srl_reg[31][29]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][29]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][2]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => \out\,
D => \in\(2),
Q => \USE_RTL_FIFO.data_srl_reg[31][2]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][2]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][3]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => \out\,
D => \in\(3),
Q => \USE_RTL_FIFO.data_srl_reg[31][3]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][3]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][4]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => \out\,
D => \in\(4),
Q => \USE_RTL_FIFO.data_srl_reg[31][4]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][4]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][5]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => \out\,
D => \in\(5),
Q => \USE_RTL_FIFO.data_srl_reg[31][5]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][5]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][6]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => \out\,
D => \in\(6),
Q => \USE_RTL_FIFO.data_srl_reg[31][6]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][6]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][7]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => \out\,
D => \in\(7),
Q => \USE_RTL_FIFO.data_srl_reg[31][7]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][7]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][8]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => \out\,
D => \in\(8),
Q => \USE_RTL_FIFO.data_srl_reg[31][8]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][8]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][9]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => \out\,
D => \in\(9),
Q => \USE_RTL_FIFO.data_srl_reg[31][9]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][9]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_VALID_WRITE.buffer_Full_q_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00FFFFFF00200000"
)
port map (
I0 => \USE_RTL_VALID_WRITE.buffer_Full_q_i_2_n_0\,
I1 => cmd_push_block,
I2 => sr_arvalid,
I3 => M_READY_I,
I4 => data_Exists_I,
I5 => buffer_Full_q,
O => \USE_RTL_VALID_WRITE.buffer_Full_q_i_1_n_0\
);
\USE_RTL_VALID_WRITE.buffer_Full_q_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"40000000"
)
port map (
I0 => \USE_RTL_ADDR.addr_q_reg__0\(0),
I1 => \USE_RTL_ADDR.addr_q_reg__0\(1),
I2 => \USE_RTL_ADDR.addr_q_reg__0\(4),
I3 => \USE_RTL_ADDR.addr_q_reg__0\(2),
I4 => \USE_RTL_ADDR.addr_q_reg__0\(3),
O => \USE_RTL_VALID_WRITE.buffer_Full_q_i_2_n_0\
);
\USE_RTL_VALID_WRITE.buffer_Full_q_reg\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \USE_RTL_VALID_WRITE.buffer_Full_q_i_1_n_0\,
Q => buffer_Full_q,
R => SR(0)
);
cmd_push_block_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"00D0"
)
port map (
I0 => buffer_Full_q,
I1 => cmd_push_block,
I2 => sr_arvalid,
I3 => m_axi_arready,
O => cmd_push_block0
);
\current_word_1[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAA80008"
)
port map (
I0 => rd_cmd_mask(0),
I1 => \pre_next_word_1_reg[2]\(0),
I2 => first_word,
I3 => \^q\(10),
I4 => rd_cmd_next_word(0),
O => \^current_word_1_reg[2]\(0)
);
\current_word_1[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"888A8880"
)
port map (
I0 => rd_cmd_mask(1),
I1 => \^q\(8),
I2 => first_word,
I3 => \^q\(10),
I4 => \pre_next_word_1_reg[2]\(1),
O => \^current_word_1_reg[2]\(1)
);
\current_word_1[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAA80008"
)
port map (
I0 => rd_cmd_mask(2),
I1 => \pre_next_word_1_reg[2]\(2),
I2 => first_word,
I3 => \^q\(10),
I4 => rd_cmd_next_word(2),
O => \^current_word_1_reg[2]\(2)
);
data_Exists_I_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FF000404FF00FF04"
)
port map (
I0 => buffer_Full_q,
I1 => sr_arvalid,
I2 => cmd_push_block,
I3 => data_Exists_I,
I4 => data_Exists_I_i_2_n_0,
I5 => M_READY_I,
O => next_Data_Exists
);
data_Exists_I_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => \USE_RTL_ADDR.addr_q_reg__0\(0),
I1 => \USE_RTL_ADDR.addr_q_reg__0\(4),
I2 => \USE_RTL_ADDR.addr_q_reg__0\(3),
I3 => \USE_RTL_ADDR.addr_q_reg__0\(2),
I4 => \USE_RTL_ADDR.addr_q_reg__0\(1),
O => data_Exists_I_i_2_n_0
);
data_Exists_I_reg: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => next_Data_Exists,
Q => data_Exists_I,
R => SR(0)
);
m_axi_arvalid_INST_0: unisim.vcomponents.LUT3
generic map(
INIT => X"8A"
)
port map (
I0 => sr_arvalid,
I1 => cmd_push_block,
I2 => buffer_Full_q,
O => m_axi_arvalid
);
\m_payload_i[66]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \^m_payload_i_reg[0]\,
I1 => mr_rvalid,
O => E(0)
);
\pre_next_word_1[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"54570000ABA80000"
)
port map (
I0 => rd_cmd_next_word(0),
I1 => \^q\(10),
I2 => first_word,
I3 => \pre_next_word_1_reg[2]\(0),
I4 => rd_cmd_mask(0),
I5 => cmd_step(0),
O => D(0)
);
\pre_next_word_1[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"8488844448444888"
)
port map (
I0 => \pre_next_word_1[1]_i_2_n_0\,
I1 => rd_cmd_mask(1),
I2 => \pre_next_word_1_reg[2]\(1),
I3 => s_axi_rlast_INST_0_i_10_n_0,
I4 => \^q\(8),
I5 => cmd_step(1),
O => D(1)
);
\pre_next_word_1[1]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAA80008"
)
port map (
I0 => cmd_step(0),
I1 => \pre_next_word_1_reg[2]\(0),
I2 => first_word,
I3 => \^q\(10),
I4 => rd_cmd_next_word(0),
O => \pre_next_word_1[1]_i_2_n_0\
);
\pre_next_word_1[2]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"8884448444488848"
)
port map (
I0 => \pre_next_word_1[2]_i_3_n_0\,
I1 => rd_cmd_mask(2),
I2 => rd_cmd_next_word(2),
I3 => s_axi_rlast_INST_0_i_10_n_0,
I4 => \pre_next_word_1_reg[2]\(2),
I5 => cmd_step(2),
O => D(2)
);
\pre_next_word_1[2]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"EEEFEEEA888A8880"
)
port map (
I0 => cmd_step(1),
I1 => \^q\(8),
I2 => first_word,
I3 => \^q\(10),
I4 => \pre_next_word_1_reg[2]\(1),
I5 => \pre_next_word_1[1]_i_2_n_0\,
O => \pre_next_word_1[2]_i_3_n_0\
);
\s_axi_rdata[31]_INST_0_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"000001FD"
)
port map (
I0 => \current_word_1_reg[2]_0\(2),
I1 => first_word,
I2 => \^q\(10),
I3 => rd_cmd_first_word(2),
I4 => rd_cmd_offset(2),
O => \s_axi_rdata[31]\
);
s_axi_rlast_INST_0_i_10: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \^q\(10),
I1 => first_word,
O => s_axi_rlast_INST_0_i_10_n_0
);
s_axi_rlast_INST_0_i_11: unisim.vcomponents.LUT5
generic map(
INIT => X"5556AAA6"
)
port map (
I0 => cmd_last_word(2),
I1 => \current_word_1_reg[2]_0\(2),
I2 => first_word,
I3 => \^q\(10),
I4 => rd_cmd_first_word(2),
O => s_axi_rlast_INST_0_i_11_n_0
);
s_axi_rlast_INST_0_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFBBBEEEBE"
)
port map (
I0 => s_axi_rlast_INST_0_i_9_n_0,
I1 => cmd_last_word(1),
I2 => rd_cmd_first_word(1),
I3 => s_axi_rlast_INST_0_i_10_n_0,
I4 => \current_word_1_reg[2]_0\(1),
I5 => s_axi_rlast_INST_0_i_11_n_0,
O => \^use_ff_out.use_rtl_output_pipeline.m_valid_q_reg_0\
);
s_axi_rlast_INST_0_i_9: unisim.vcomponents.LUT5
generic map(
INIT => X"6665666A"
)
port map (
I0 => cmd_last_word(0),
I1 => rd_cmd_first_word(0),
I2 => first_word,
I3 => \^q\(10),
I4 => \current_word_1_reg[2]_0\(0),
O => s_axi_rlast_INST_0_i_9_n_0
);
s_ready_i_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"A8A8A8A8A8AAA8A8"
)
port map (
I0 => \^m_payload_i_reg[0]_0\,
I1 => s_ready_i_i_4_n_0,
I2 => s_ready_i_i_5_n_0,
I3 => use_wrap_buffer,
I4 => wrap_buffer_available_reg,
I5 => \^use_ff_out.use_rtl_output_pipeline.m_valid_q_reg_0\,
O => \^m_payload_i_reg[0]\
);
\s_ready_i_i_2__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"8088"
)
port map (
I0 => m_axi_arready,
I1 => s_axi_aresetn,
I2 => cmd_push_block,
I3 => buffer_Full_q,
O => s_ready_i_reg
);
s_ready_i_i_3: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => s_axi_rready,
I1 => \^rd_cmd_valid\,
O => \^m_payload_i_reg[0]_0\
);
s_ready_i_i_4: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \^q\(10),
I1 => rd_cmd_modified,
O => s_ready_i_i_4_n_0
);
s_ready_i_i_5: unisim.vcomponents.LUT6
generic map(
INIT => X"0111011100000111"
)
port map (
I0 => rd_cmd_complete_wrap,
I1 => \^current_word_1_reg[2]\(2),
I2 => rd_cmd_mask(1),
I3 => \pre_next_word_1_reg[1]\,
I4 => rd_cmd_mask(0),
I5 => s_ready_i_i_8_n_0,
O => s_ready_i_i_5_n_0
);
s_ready_i_i_8: unisim.vcomponents.LUT4
generic map(
INIT => X"5457"
)
port map (
I0 => rd_cmd_next_word(0),
I1 => \^q\(10),
I2 => first_word,
I3 => \pre_next_word_1_reg[2]\(0),
O => s_ready_i_i_8_n_0
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_us_1_axi_dwidth_converter_v2_1_11_a_upsizer is
port (
rd_cmd_valid : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[0]\ : out STD_LOGIC;
\m_payload_i_reg[0]_0\ : out STD_LOGIC;
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 10 downto 0 );
D : out STD_LOGIC_VECTOR ( 2 downto 0 );
\current_word_1_reg[2]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\s_axi_rdata[31]\ : out STD_LOGIC;
s_ready_i_reg : out STD_LOGIC;
m_axi_arvalid : out STD_LOGIC;
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : in STD_LOGIC;
M_READY_I : in STD_LOGIC;
mr_rvalid : in STD_LOGIC;
use_wrap_buffer : in STD_LOGIC;
wrap_buffer_available_reg : in STD_LOGIC;
\pre_next_word_1_reg[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\pre_next_word_1_reg[1]\ : in STD_LOGIC;
first_word : in STD_LOGIC;
sr_arvalid : in STD_LOGIC;
use_wrap_buffer_reg : in STD_LOGIC;
\current_word_1_reg[2]_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_rready : in STD_LOGIC;
m_axi_arready : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
\in\ : in STD_LOGIC_VECTOR ( 27 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_us_1_axi_dwidth_converter_v2_1_11_a_upsizer : entity is "axi_dwidth_converter_v2_1_11_a_upsizer";
end system_auto_us_1_axi_dwidth_converter_v2_1_11_a_upsizer;
architecture STRUCTURE of system_auto_us_1_axi_dwidth_converter_v2_1_11_a_upsizer is
signal cmd_push_block : STD_LOGIC;
signal cmd_push_block0 : STD_LOGIC;
begin
\GEN_CMD_QUEUE.cmd_queue\: entity work.system_auto_us_1_generic_baseblocks_v2_1_0_command_fifo
port map (
D(2 downto 0) => D(2 downto 0),
E(0) => E(0),
M_READY_I => M_READY_I,
Q(10 downto 0) => Q(10 downto 0),
SR(0) => SR(0),
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_0\ => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg\,
cmd_push_block => cmd_push_block,
cmd_push_block0 => cmd_push_block0,
\current_word_1_reg[2]\(2 downto 0) => \current_word_1_reg[2]\(2 downto 0),
\current_word_1_reg[2]_0\(2 downto 0) => \current_word_1_reg[2]_0\(2 downto 0),
first_word => first_word,
\in\(27 downto 0) => \in\(27 downto 0),
m_axi_arready => m_axi_arready,
m_axi_arvalid => m_axi_arvalid,
\m_payload_i_reg[0]\ => \m_payload_i_reg[0]\,
\m_payload_i_reg[0]_0\ => \m_payload_i_reg[0]_0\,
mr_rvalid => mr_rvalid,
\out\ => \out\,
\pre_next_word_1_reg[1]\ => \pre_next_word_1_reg[1]\,
\pre_next_word_1_reg[2]\(2 downto 0) => \pre_next_word_1_reg[2]\(2 downto 0),
rd_cmd_valid => rd_cmd_valid,
s_axi_aresetn => s_axi_aresetn,
\s_axi_rdata[31]\ => \s_axi_rdata[31]\,
s_axi_rready => s_axi_rready,
s_ready_i_reg => s_ready_i_reg,
sr_arvalid => sr_arvalid,
use_wrap_buffer => use_wrap_buffer,
use_wrap_buffer_reg => use_wrap_buffer_reg,
wrap_buffer_available_reg => wrap_buffer_available_reg
);
cmd_push_block_reg: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => cmd_push_block0,
Q => cmd_push_block,
R => SR(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_us_1_axi_register_slice_v2_1_11_axi_register_slice is
port (
m_axi_rready : out STD_LOGIC;
mr_rvalid : out STD_LOGIC;
use_wrap_buffer_reg : out STD_LOGIC;
\USE_RTL_LENGTH.first_mi_word_q_reg\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 65 downto 0 );
\out\ : in STD_LOGIC;
rd_cmd_valid : in STD_LOGIC;
use_wrap_buffer : in STD_LOGIC;
m_axi_rlast : in STD_LOGIC;
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
use_wrap_buffer_reg_0 : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC;
\aresetn_d_reg[1]\ : in STD_LOGIC;
\aresetn_d_reg[0]\ : in STD_LOGIC;
first_mi_word_q : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_us_1_axi_register_slice_v2_1_11_axi_register_slice : entity is "axi_register_slice_v2_1_11_axi_register_slice";
end system_auto_us_1_axi_register_slice_v2_1_11_axi_register_slice;
architecture STRUCTURE of system_auto_us_1_axi_register_slice_v2_1_11_axi_register_slice is
begin
r_pipe: entity work.\system_auto_us_1_axi_register_slice_v2_1_11_axic_register_slice__parameterized2\
port map (
E(0) => E(0),
Q(65 downto 0) => Q(65 downto 0),
\USE_RTL_LENGTH.first_mi_word_q_reg\ => mr_rvalid,
\USE_RTL_LENGTH.first_mi_word_q_reg_0\ => \USE_RTL_LENGTH.first_mi_word_q_reg\,
\aresetn_d_reg[0]\ => \aresetn_d_reg[0]\,
\aresetn_d_reg[1]\ => \aresetn_d_reg[1]\,
first_mi_word_q => first_mi_word_q,
m_axi_rdata(63 downto 0) => m_axi_rdata(63 downto 0),
m_axi_rlast => m_axi_rlast,
m_axi_rready => m_axi_rready,
m_axi_rresp(1 downto 0) => m_axi_rresp(1 downto 0),
m_axi_rvalid => m_axi_rvalid,
\out\ => \out\,
rd_cmd_valid => rd_cmd_valid,
use_wrap_buffer => use_wrap_buffer,
use_wrap_buffer_reg => use_wrap_buffer_reg,
use_wrap_buffer_reg_0 => use_wrap_buffer_reg_0
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_auto_us_1_axi_register_slice_v2_1_11_axi_register_slice__parameterized0\ is
port (
\aresetn_d_reg[1]\ : out STD_LOGIC;
s_ready_i_reg : out STD_LOGIC;
sr_arvalid : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 44 downto 0 );
s_axi_arready : out STD_LOGIC;
\in\ : out STD_LOGIC_VECTOR ( 27 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 2 downto 0 );
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : in STD_LOGIC;
cmd_push_block_reg : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 60 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_auto_us_1_axi_register_slice_v2_1_11_axi_register_slice__parameterized0\ : entity is "axi_register_slice_v2_1_11_axi_register_slice";
end \system_auto_us_1_axi_register_slice_v2_1_11_axi_register_slice__parameterized0\;
architecture STRUCTURE of \system_auto_us_1_axi_register_slice_v2_1_11_axi_register_slice__parameterized0\ is
begin
ar_pipe: entity work.system_auto_us_1_axi_register_slice_v2_1_11_axic_register_slice
port map (
D(60 downto 0) => D(60 downto 0),
Q(44 downto 0) => Q(44 downto 0),
SR(0) => SR(0),
\aresetn_d_reg[1]_0\ => \aresetn_d_reg[1]\,
cmd_push_block_reg => cmd_push_block_reg,
\in\(27 downto 0) => \in\(27 downto 0),
m_axi_araddr(2 downto 0) => m_axi_araddr(2 downto 0),
m_axi_arburst(1 downto 0) => m_axi_arburst(1 downto 0),
m_axi_arsize(2 downto 0) => m_axi_arsize(2 downto 0),
\out\ => \out\,
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid,
s_ready_i_reg_0 => s_ready_i_reg,
sr_arvalid => sr_arvalid
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_us_1_axi_dwidth_converter_v2_1_11_axi_upsizer is
port (
Q : out STD_LOGIC_VECTOR ( 44 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_rready : out STD_LOGIC;
s_axi_rlast : out STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rvalid : out STD_LOGIC;
m_axi_arvalid : out STD_LOGIC;
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 2 downto 0 );
\out\ : in STD_LOGIC;
m_axi_rlast : in STD_LOGIC;
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
D : in STD_LOGIC_VECTOR ( 60 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_arready : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_us_1_axi_dwidth_converter_v2_1_11_axi_upsizer : entity is "axi_dwidth_converter_v2_1_11_axi_upsizer";
end system_auto_us_1_axi_dwidth_converter_v2_1_11_axi_upsizer;
architecture STRUCTURE of system_auto_us_1_axi_dwidth_converter_v2_1_11_axi_upsizer is
signal \GEN_CMD_QUEUE.cmd_queue/M_READY_I\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_10\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_11\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_12\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_13\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_14\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_15\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_16\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_17\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_18\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_19\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_2\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_20\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_21\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_22\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_23\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_24\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_25\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_26\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_27\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_28\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_29\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_3\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_30\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_31\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_32\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_33\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_34\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_35\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_36\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_37\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_38\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_39\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_40\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_41\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_42\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_43\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_44\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_45\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_46\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_47\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_48\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_49\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_50\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_51\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_52\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_53\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_54\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_55\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_56\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_57\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_58\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_59\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_6\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_60\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_61\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_62\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_63\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_64\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_65\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_66\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_67\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_68\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_69\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_7\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_8\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_9\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_1\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_10\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_43\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_5\ : STD_LOGIC;
signal \USE_READ.read_addr_inst_n_10\ : STD_LOGIC;
signal \USE_READ.read_addr_inst_n_11\ : STD_LOGIC;
signal \USE_READ.read_addr_inst_n_12\ : STD_LOGIC;
signal \USE_READ.read_addr_inst_n_13\ : STD_LOGIC;
signal \USE_READ.read_addr_inst_n_14\ : STD_LOGIC;
signal \USE_READ.read_addr_inst_n_15\ : STD_LOGIC;
signal \USE_READ.read_addr_inst_n_2\ : STD_LOGIC;
signal \USE_READ.read_addr_inst_n_22\ : STD_LOGIC;
signal \USE_READ.read_addr_inst_n_23\ : STD_LOGIC;
signal \USE_READ.read_addr_inst_n_3\ : STD_LOGIC;
signal \USE_READ.read_addr_inst_n_4\ : STD_LOGIC;
signal \USE_READ.read_addr_inst_n_8\ : STD_LOGIC;
signal \USE_READ.read_addr_inst_n_9\ : STD_LOGIC;
signal cmd_complete_wrap_i : STD_LOGIC;
signal cmd_first_word_i : STD_LOGIC_VECTOR ( 2 downto 0 );
signal cmd_fix_i : STD_LOGIC;
signal cmd_modified_i : STD_LOGIC;
signal cmd_packed_wrap_i : STD_LOGIC;
signal current_word_1 : STD_LOGIC_VECTOR ( 2 downto 0 );
signal first_mi_word_q : STD_LOGIC;
signal first_word : STD_LOGIC;
signal \^m_axi_arlen\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal mr_rresp : STD_LOGIC_VECTOR ( 1 downto 0 );
signal mr_rvalid : STD_LOGIC;
signal next_word : STD_LOGIC_VECTOR ( 2 downto 0 );
signal p_1_out : STD_LOGIC_VECTOR ( 22 downto 16 );
signal pre_next_word : STD_LOGIC_VECTOR ( 2 downto 0 );
signal pre_next_word_1 : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \r_pipe/p_1_in\ : STD_LOGIC;
signal rd_cmd_fix : STD_LOGIC;
signal rd_cmd_next_word : STD_LOGIC_VECTOR ( 1 to 1 );
signal rd_cmd_packed_wrap : STD_LOGIC;
signal rd_cmd_valid : STD_LOGIC;
signal si_register_slice_inst_n_0 : STD_LOGIC;
signal si_register_slice_inst_n_1 : STD_LOGIC;
signal si_register_slice_inst_n_63 : STD_LOGIC;
signal si_register_slice_inst_n_64 : STD_LOGIC;
signal si_register_slice_inst_n_65 : STD_LOGIC;
signal si_register_slice_inst_n_66 : STD_LOGIC;
signal si_register_slice_inst_n_67 : STD_LOGIC;
signal si_register_slice_inst_n_68 : STD_LOGIC;
signal sr_arvalid : STD_LOGIC;
signal use_wrap_buffer : STD_LOGIC;
begin
m_axi_arlen(7 downto 0) <= \^m_axi_arlen\(7 downto 0);
\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst\: entity work.system_auto_us_1_axi_register_slice_v2_1_11_axi_register_slice
port map (
E(0) => \r_pipe/p_1_in\,
Q(65 downto 64) => mr_rresp(1 downto 0),
Q(63) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_6\,
Q(62) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_7\,
Q(61) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_8\,
Q(60) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_9\,
Q(59) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_10\,
Q(58) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_11\,
Q(57) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_12\,
Q(56) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_13\,
Q(55) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_14\,
Q(54) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_15\,
Q(53) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_16\,
Q(52) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_17\,
Q(51) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_18\,
Q(50) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_19\,
Q(49) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_20\,
Q(48) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_21\,
Q(47) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_22\,
Q(46) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_23\,
Q(45) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_24\,
Q(44) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_25\,
Q(43) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_26\,
Q(42) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_27\,
Q(41) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_28\,
Q(40) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_29\,
Q(39) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_30\,
Q(38) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_31\,
Q(37) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_32\,
Q(36) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_33\,
Q(35) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_34\,
Q(34) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_35\,
Q(33) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_36\,
Q(32) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_37\,
Q(31) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_38\,
Q(30) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_39\,
Q(29) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_40\,
Q(28) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_41\,
Q(27) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_42\,
Q(26) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_43\,
Q(25) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_44\,
Q(24) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_45\,
Q(23) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_46\,
Q(22) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_47\,
Q(21) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_48\,
Q(20) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_49\,
Q(19) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_50\,
Q(18) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_51\,
Q(17) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_52\,
Q(16) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_53\,
Q(15) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_54\,
Q(14) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_55\,
Q(13) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_56\,
Q(12) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_57\,
Q(11) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_58\,
Q(10) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_59\,
Q(9) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_60\,
Q(8) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_61\,
Q(7) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_62\,
Q(6) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_63\,
Q(5) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_64\,
Q(4) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_65\,
Q(3) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_66\,
Q(2) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_67\,
Q(1) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_68\,
Q(0) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_69\,
\USE_RTL_LENGTH.first_mi_word_q_reg\ => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_3\,
\aresetn_d_reg[0]\ => si_register_slice_inst_n_0,
\aresetn_d_reg[1]\ => si_register_slice_inst_n_1,
first_mi_word_q => first_mi_word_q,
m_axi_rdata(63 downto 0) => m_axi_rdata(63 downto 0),
m_axi_rlast => m_axi_rlast,
m_axi_rready => m_axi_rready,
m_axi_rresp(1 downto 0) => m_axi_rresp(1 downto 0),
m_axi_rvalid => m_axi_rvalid,
mr_rvalid => mr_rvalid,
\out\ => \out\,
rd_cmd_valid => rd_cmd_valid,
use_wrap_buffer => use_wrap_buffer,
use_wrap_buffer_reg => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_2\,
use_wrap_buffer_reg_0 => \USE_READ.read_addr_inst_n_2\
);
\USE_READ.gen_non_fifo_r_upsizer.read_data_inst\: entity work.system_auto_us_1_axi_dwidth_converter_v2_1_11_r_upsizer
port map (
D(2 downto 0) => pre_next_word(2 downto 0),
M_READY_I => \GEN_CMD_QUEUE.cmd_queue/M_READY_I\,
Q(10) => rd_cmd_fix,
Q(9) => rd_cmd_packed_wrap,
Q(8) => rd_cmd_next_word(1),
Q(7) => \USE_READ.read_addr_inst_n_8\,
Q(6) => \USE_READ.read_addr_inst_n_9\,
Q(5) => \USE_READ.read_addr_inst_n_10\,
Q(4) => \USE_READ.read_addr_inst_n_11\,
Q(3) => \USE_READ.read_addr_inst_n_12\,
Q(2) => \USE_READ.read_addr_inst_n_13\,
Q(1) => \USE_READ.read_addr_inst_n_14\,
Q(0) => \USE_READ.read_addr_inst_n_15\,
SR(0) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_1\,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[13]\(2 downto 0) => next_word(2 downto 0),
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[18]\ => \USE_READ.read_addr_inst_n_4\,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg\ => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_10\,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_0\(2 downto 0) => current_word_1(2 downto 0),
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_1\ => \USE_READ.read_addr_inst_n_3\,
\USE_RTL_ADDR.addr_q_reg[4]\ => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_43\,
\current_word_1_reg[2]_0\(2 downto 0) => pre_next_word_1(2 downto 0),
\current_word_1_reg[2]_1\ => \USE_READ.read_addr_inst_n_22\,
first_mi_word_q => first_mi_word_q,
first_word => first_word,
\m_payload_i_reg[0]\ => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_5\,
\m_payload_i_reg[65]\(65 downto 64) => mr_rresp(1 downto 0),
\m_payload_i_reg[65]\(63) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_6\,
\m_payload_i_reg[65]\(62) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_7\,
\m_payload_i_reg[65]\(61) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_8\,
\m_payload_i_reg[65]\(60) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_9\,
\m_payload_i_reg[65]\(59) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_10\,
\m_payload_i_reg[65]\(58) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_11\,
\m_payload_i_reg[65]\(57) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_12\,
\m_payload_i_reg[65]\(56) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_13\,
\m_payload_i_reg[65]\(55) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_14\,
\m_payload_i_reg[65]\(54) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_15\,
\m_payload_i_reg[65]\(53) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_16\,
\m_payload_i_reg[65]\(52) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_17\,
\m_payload_i_reg[65]\(51) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_18\,
\m_payload_i_reg[65]\(50) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_19\,
\m_payload_i_reg[65]\(49) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_20\,
\m_payload_i_reg[65]\(48) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_21\,
\m_payload_i_reg[65]\(47) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_22\,
\m_payload_i_reg[65]\(46) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_23\,
\m_payload_i_reg[65]\(45) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_24\,
\m_payload_i_reg[65]\(44) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_25\,
\m_payload_i_reg[65]\(43) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_26\,
\m_payload_i_reg[65]\(42) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_27\,
\m_payload_i_reg[65]\(41) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_28\,
\m_payload_i_reg[65]\(40) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_29\,
\m_payload_i_reg[65]\(39) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_30\,
\m_payload_i_reg[65]\(38) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_31\,
\m_payload_i_reg[65]\(37) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_32\,
\m_payload_i_reg[65]\(36) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_33\,
\m_payload_i_reg[65]\(35) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_34\,
\m_payload_i_reg[65]\(34) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_35\,
\m_payload_i_reg[65]\(33) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_36\,
\m_payload_i_reg[65]\(32) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_37\,
\m_payload_i_reg[65]\(31) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_38\,
\m_payload_i_reg[65]\(30) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_39\,
\m_payload_i_reg[65]\(29) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_40\,
\m_payload_i_reg[65]\(28) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_41\,
\m_payload_i_reg[65]\(27) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_42\,
\m_payload_i_reg[65]\(26) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_43\,
\m_payload_i_reg[65]\(25) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_44\,
\m_payload_i_reg[65]\(24) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_45\,
\m_payload_i_reg[65]\(23) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_46\,
\m_payload_i_reg[65]\(22) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_47\,
\m_payload_i_reg[65]\(21) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_48\,
\m_payload_i_reg[65]\(20) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_49\,
\m_payload_i_reg[65]\(19) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_50\,
\m_payload_i_reg[65]\(18) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_51\,
\m_payload_i_reg[65]\(17) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_52\,
\m_payload_i_reg[65]\(16) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_53\,
\m_payload_i_reg[65]\(15) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_54\,
\m_payload_i_reg[65]\(14) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_55\,
\m_payload_i_reg[65]\(13) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_56\,
\m_payload_i_reg[65]\(12) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_57\,
\m_payload_i_reg[65]\(11) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_58\,
\m_payload_i_reg[65]\(10) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_59\,
\m_payload_i_reg[65]\(9) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_60\,
\m_payload_i_reg[65]\(8) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_61\,
\m_payload_i_reg[65]\(7) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_62\,
\m_payload_i_reg[65]\(6) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_63\,
\m_payload_i_reg[65]\(5) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_64\,
\m_payload_i_reg[65]\(4) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_65\,
\m_payload_i_reg[65]\(3) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_66\,
\m_payload_i_reg[65]\(2) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_67\,
\m_payload_i_reg[65]\(1) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_68\,
\m_payload_i_reg[65]\(0) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_69\,
\m_payload_i_reg[66]\ => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_3\,
m_valid_i_reg => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_2\,
mr_rvalid => mr_rvalid,
\out\ => \out\,
rd_cmd_valid => rd_cmd_valid,
s_axi_aresetn => s_axi_aresetn,
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rlast => s_axi_rlast,
s_axi_rready => s_axi_rready,
s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0),
s_axi_rvalid => s_axi_rvalid,
use_wrap_buffer => use_wrap_buffer,
use_wrap_buffer_reg_0 => \USE_READ.read_addr_inst_n_2\
);
\USE_READ.read_addr_inst\: entity work.system_auto_us_1_axi_dwidth_converter_v2_1_11_a_upsizer
port map (
D(2 downto 0) => pre_next_word(2 downto 0),
E(0) => \r_pipe/p_1_in\,
M_READY_I => \GEN_CMD_QUEUE.cmd_queue/M_READY_I\,
Q(10) => rd_cmd_fix,
Q(9) => rd_cmd_packed_wrap,
Q(8) => rd_cmd_next_word(1),
Q(7) => \USE_READ.read_addr_inst_n_8\,
Q(6) => \USE_READ.read_addr_inst_n_9\,
Q(5) => \USE_READ.read_addr_inst_n_10\,
Q(4) => \USE_READ.read_addr_inst_n_11\,
Q(3) => \USE_READ.read_addr_inst_n_12\,
Q(2) => \USE_READ.read_addr_inst_n_13\,
Q(1) => \USE_READ.read_addr_inst_n_14\,
Q(0) => \USE_READ.read_addr_inst_n_15\,
SR(0) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_1\,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg\ => \USE_READ.read_addr_inst_n_4\,
\current_word_1_reg[2]\(2 downto 0) => next_word(2 downto 0),
\current_word_1_reg[2]_0\(2 downto 0) => current_word_1(2 downto 0),
first_word => first_word,
\in\(27) => cmd_fix_i,
\in\(26) => cmd_modified_i,
\in\(25) => cmd_complete_wrap_i,
\in\(24) => cmd_packed_wrap_i,
\in\(23 downto 21) => cmd_first_word_i(2 downto 0),
\in\(20 downto 14) => p_1_out(22 downto 16),
\in\(13) => si_register_slice_inst_n_63,
\in\(12) => si_register_slice_inst_n_64,
\in\(11) => si_register_slice_inst_n_65,
\in\(10) => si_register_slice_inst_n_66,
\in\(9) => si_register_slice_inst_n_67,
\in\(8) => si_register_slice_inst_n_68,
\in\(7 downto 0) => \^m_axi_arlen\(7 downto 0),
m_axi_arready => m_axi_arready,
m_axi_arvalid => m_axi_arvalid,
\m_payload_i_reg[0]\ => \USE_READ.read_addr_inst_n_2\,
\m_payload_i_reg[0]_0\ => \USE_READ.read_addr_inst_n_3\,
mr_rvalid => mr_rvalid,
\out\ => \out\,
\pre_next_word_1_reg[1]\ => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_5\,
\pre_next_word_1_reg[2]\(2 downto 0) => pre_next_word_1(2 downto 0),
rd_cmd_valid => rd_cmd_valid,
s_axi_aresetn => s_axi_aresetn,
\s_axi_rdata[31]\ => \USE_READ.read_addr_inst_n_22\,
s_axi_rready => s_axi_rready,
s_ready_i_reg => \USE_READ.read_addr_inst_n_23\,
sr_arvalid => sr_arvalid,
use_wrap_buffer => use_wrap_buffer,
use_wrap_buffer_reg => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_10\,
wrap_buffer_available_reg => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_43\
);
si_register_slice_inst: entity work.\system_auto_us_1_axi_register_slice_v2_1_11_axi_register_slice__parameterized0\
port map (
D(60 downto 0) => D(60 downto 0),
Q(44 downto 0) => Q(44 downto 0),
SR(0) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_1\,
\aresetn_d_reg[1]\ => si_register_slice_inst_n_0,
cmd_push_block_reg => \USE_READ.read_addr_inst_n_23\,
\in\(27) => cmd_fix_i,
\in\(26) => cmd_modified_i,
\in\(25) => cmd_complete_wrap_i,
\in\(24) => cmd_packed_wrap_i,
\in\(23 downto 21) => cmd_first_word_i(2 downto 0),
\in\(20 downto 14) => p_1_out(22 downto 16),
\in\(13) => si_register_slice_inst_n_63,
\in\(12) => si_register_slice_inst_n_64,
\in\(11) => si_register_slice_inst_n_65,
\in\(10) => si_register_slice_inst_n_66,
\in\(9) => si_register_slice_inst_n_67,
\in\(8) => si_register_slice_inst_n_68,
\in\(7 downto 0) => \^m_axi_arlen\(7 downto 0),
m_axi_araddr(2 downto 0) => m_axi_araddr(2 downto 0),
m_axi_arburst(1 downto 0) => m_axi_arburst(1 downto 0),
m_axi_arsize(2 downto 0) => m_axi_arsize(2 downto 0),
\out\ => \out\,
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid,
s_ready_i_reg => si_register_slice_inst_n_1,
sr_arvalid => sr_arvalid
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_us_1_axi_dwidth_converter_v2_1_11_top is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_aclk : in STD_LOGIC;
m_axi_aresetn : in STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_wlast : out STD_LOGIC;
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of system_auto_us_1_axi_dwidth_converter_v2_1_11_top : entity is 32;
attribute C_AXI_IS_ACLK_ASYNC : integer;
attribute C_AXI_IS_ACLK_ASYNC of system_auto_us_1_axi_dwidth_converter_v2_1_11_top : entity is 0;
attribute C_AXI_PROTOCOL : integer;
attribute C_AXI_PROTOCOL of system_auto_us_1_axi_dwidth_converter_v2_1_11_top : entity is 0;
attribute C_AXI_SUPPORTS_READ : integer;
attribute C_AXI_SUPPORTS_READ of system_auto_us_1_axi_dwidth_converter_v2_1_11_top : entity is 1;
attribute C_AXI_SUPPORTS_WRITE : integer;
attribute C_AXI_SUPPORTS_WRITE of system_auto_us_1_axi_dwidth_converter_v2_1_11_top : entity is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of system_auto_us_1_axi_dwidth_converter_v2_1_11_top : entity is "zynq";
attribute C_FIFO_MODE : integer;
attribute C_FIFO_MODE of system_auto_us_1_axi_dwidth_converter_v2_1_11_top : entity is 0;
attribute C_MAX_SPLIT_BEATS : integer;
attribute C_MAX_SPLIT_BEATS of system_auto_us_1_axi_dwidth_converter_v2_1_11_top : entity is 16;
attribute C_M_AXI_ACLK_RATIO : integer;
attribute C_M_AXI_ACLK_RATIO of system_auto_us_1_axi_dwidth_converter_v2_1_11_top : entity is 2;
attribute C_M_AXI_BYTES_LOG : integer;
attribute C_M_AXI_BYTES_LOG of system_auto_us_1_axi_dwidth_converter_v2_1_11_top : entity is 3;
attribute C_M_AXI_DATA_WIDTH : integer;
attribute C_M_AXI_DATA_WIDTH of system_auto_us_1_axi_dwidth_converter_v2_1_11_top : entity is 64;
attribute C_PACKING_LEVEL : integer;
attribute C_PACKING_LEVEL of system_auto_us_1_axi_dwidth_converter_v2_1_11_top : entity is 1;
attribute C_RATIO : integer;
attribute C_RATIO of system_auto_us_1_axi_dwidth_converter_v2_1_11_top : entity is 0;
attribute C_RATIO_LOG : integer;
attribute C_RATIO_LOG of system_auto_us_1_axi_dwidth_converter_v2_1_11_top : entity is 0;
attribute C_SUPPORTS_ID : integer;
attribute C_SUPPORTS_ID of system_auto_us_1_axi_dwidth_converter_v2_1_11_top : entity is 0;
attribute C_SYNCHRONIZER_STAGE : integer;
attribute C_SYNCHRONIZER_STAGE of system_auto_us_1_axi_dwidth_converter_v2_1_11_top : entity is 3;
attribute C_S_AXI_ACLK_RATIO : integer;
attribute C_S_AXI_ACLK_RATIO of system_auto_us_1_axi_dwidth_converter_v2_1_11_top : entity is 1;
attribute C_S_AXI_BYTES_LOG : integer;
attribute C_S_AXI_BYTES_LOG of system_auto_us_1_axi_dwidth_converter_v2_1_11_top : entity is 2;
attribute C_S_AXI_DATA_WIDTH : integer;
attribute C_S_AXI_DATA_WIDTH of system_auto_us_1_axi_dwidth_converter_v2_1_11_top : entity is 32;
attribute C_S_AXI_ID_WIDTH : integer;
attribute C_S_AXI_ID_WIDTH of system_auto_us_1_axi_dwidth_converter_v2_1_11_top : entity is 1;
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of system_auto_us_1_axi_dwidth_converter_v2_1_11_top : entity is "yes";
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_us_1_axi_dwidth_converter_v2_1_11_top : entity is "axi_dwidth_converter_v2_1_11_top";
attribute P_AXI3 : integer;
attribute P_AXI3 of system_auto_us_1_axi_dwidth_converter_v2_1_11_top : entity is 1;
attribute P_AXI4 : integer;
attribute P_AXI4 of system_auto_us_1_axi_dwidth_converter_v2_1_11_top : entity is 0;
attribute P_AXILITE : integer;
attribute P_AXILITE of system_auto_us_1_axi_dwidth_converter_v2_1_11_top : entity is 2;
attribute P_CONVERSION : integer;
attribute P_CONVERSION of system_auto_us_1_axi_dwidth_converter_v2_1_11_top : entity is 2;
attribute P_MAX_SPLIT_BEATS : integer;
attribute P_MAX_SPLIT_BEATS of system_auto_us_1_axi_dwidth_converter_v2_1_11_top : entity is 16;
end system_auto_us_1_axi_dwidth_converter_v2_1_11_top;
architecture STRUCTURE of system_auto_us_1_axi_dwidth_converter_v2_1_11_top is
signal \<const0>\ : STD_LOGIC;
begin
m_axi_awaddr(31) <= \<const0>\;
m_axi_awaddr(30) <= \<const0>\;
m_axi_awaddr(29) <= \<const0>\;
m_axi_awaddr(28) <= \<const0>\;
m_axi_awaddr(27) <= \<const0>\;
m_axi_awaddr(26) <= \<const0>\;
m_axi_awaddr(25) <= \<const0>\;
m_axi_awaddr(24) <= \<const0>\;
m_axi_awaddr(23) <= \<const0>\;
m_axi_awaddr(22) <= \<const0>\;
m_axi_awaddr(21) <= \<const0>\;
m_axi_awaddr(20) <= \<const0>\;
m_axi_awaddr(19) <= \<const0>\;
m_axi_awaddr(18) <= \<const0>\;
m_axi_awaddr(17) <= \<const0>\;
m_axi_awaddr(16) <= \<const0>\;
m_axi_awaddr(15) <= \<const0>\;
m_axi_awaddr(14) <= \<const0>\;
m_axi_awaddr(13) <= \<const0>\;
m_axi_awaddr(12) <= \<const0>\;
m_axi_awaddr(11) <= \<const0>\;
m_axi_awaddr(10) <= \<const0>\;
m_axi_awaddr(9) <= \<const0>\;
m_axi_awaddr(8) <= \<const0>\;
m_axi_awaddr(7) <= \<const0>\;
m_axi_awaddr(6) <= \<const0>\;
m_axi_awaddr(5) <= \<const0>\;
m_axi_awaddr(4) <= \<const0>\;
m_axi_awaddr(3) <= \<const0>\;
m_axi_awaddr(2) <= \<const0>\;
m_axi_awaddr(1) <= \<const0>\;
m_axi_awaddr(0) <= \<const0>\;
m_axi_awburst(1) <= \<const0>\;
m_axi_awburst(0) <= \<const0>\;
m_axi_awcache(3) <= \<const0>\;
m_axi_awcache(2) <= \<const0>\;
m_axi_awcache(1) <= \<const0>\;
m_axi_awcache(0) <= \<const0>\;
m_axi_awlen(7) <= \<const0>\;
m_axi_awlen(6) <= \<const0>\;
m_axi_awlen(5) <= \<const0>\;
m_axi_awlen(4) <= \<const0>\;
m_axi_awlen(3) <= \<const0>\;
m_axi_awlen(2) <= \<const0>\;
m_axi_awlen(1) <= \<const0>\;
m_axi_awlen(0) <= \<const0>\;
m_axi_awlock(0) <= \<const0>\;
m_axi_awprot(2) <= \<const0>\;
m_axi_awprot(1) <= \<const0>\;
m_axi_awprot(0) <= \<const0>\;
m_axi_awqos(3) <= \<const0>\;
m_axi_awqos(2) <= \<const0>\;
m_axi_awqos(1) <= \<const0>\;
m_axi_awqos(0) <= \<const0>\;
m_axi_awregion(3) <= \<const0>\;
m_axi_awregion(2) <= \<const0>\;
m_axi_awregion(1) <= \<const0>\;
m_axi_awregion(0) <= \<const0>\;
m_axi_awsize(2) <= \<const0>\;
m_axi_awsize(1) <= \<const0>\;
m_axi_awsize(0) <= \<const0>\;
m_axi_awvalid <= \<const0>\;
m_axi_bready <= \<const0>\;
m_axi_wdata(63) <= \<const0>\;
m_axi_wdata(62) <= \<const0>\;
m_axi_wdata(61) <= \<const0>\;
m_axi_wdata(60) <= \<const0>\;
m_axi_wdata(59) <= \<const0>\;
m_axi_wdata(58) <= \<const0>\;
m_axi_wdata(57) <= \<const0>\;
m_axi_wdata(56) <= \<const0>\;
m_axi_wdata(55) <= \<const0>\;
m_axi_wdata(54) <= \<const0>\;
m_axi_wdata(53) <= \<const0>\;
m_axi_wdata(52) <= \<const0>\;
m_axi_wdata(51) <= \<const0>\;
m_axi_wdata(50) <= \<const0>\;
m_axi_wdata(49) <= \<const0>\;
m_axi_wdata(48) <= \<const0>\;
m_axi_wdata(47) <= \<const0>\;
m_axi_wdata(46) <= \<const0>\;
m_axi_wdata(45) <= \<const0>\;
m_axi_wdata(44) <= \<const0>\;
m_axi_wdata(43) <= \<const0>\;
m_axi_wdata(42) <= \<const0>\;
m_axi_wdata(41) <= \<const0>\;
m_axi_wdata(40) <= \<const0>\;
m_axi_wdata(39) <= \<const0>\;
m_axi_wdata(38) <= \<const0>\;
m_axi_wdata(37) <= \<const0>\;
m_axi_wdata(36) <= \<const0>\;
m_axi_wdata(35) <= \<const0>\;
m_axi_wdata(34) <= \<const0>\;
m_axi_wdata(33) <= \<const0>\;
m_axi_wdata(32) <= \<const0>\;
m_axi_wdata(31) <= \<const0>\;
m_axi_wdata(30) <= \<const0>\;
m_axi_wdata(29) <= \<const0>\;
m_axi_wdata(28) <= \<const0>\;
m_axi_wdata(27) <= \<const0>\;
m_axi_wdata(26) <= \<const0>\;
m_axi_wdata(25) <= \<const0>\;
m_axi_wdata(24) <= \<const0>\;
m_axi_wdata(23) <= \<const0>\;
m_axi_wdata(22) <= \<const0>\;
m_axi_wdata(21) <= \<const0>\;
m_axi_wdata(20) <= \<const0>\;
m_axi_wdata(19) <= \<const0>\;
m_axi_wdata(18) <= \<const0>\;
m_axi_wdata(17) <= \<const0>\;
m_axi_wdata(16) <= \<const0>\;
m_axi_wdata(15) <= \<const0>\;
m_axi_wdata(14) <= \<const0>\;
m_axi_wdata(13) <= \<const0>\;
m_axi_wdata(12) <= \<const0>\;
m_axi_wdata(11) <= \<const0>\;
m_axi_wdata(10) <= \<const0>\;
m_axi_wdata(9) <= \<const0>\;
m_axi_wdata(8) <= \<const0>\;
m_axi_wdata(7) <= \<const0>\;
m_axi_wdata(6) <= \<const0>\;
m_axi_wdata(5) <= \<const0>\;
m_axi_wdata(4) <= \<const0>\;
m_axi_wdata(3) <= \<const0>\;
m_axi_wdata(2) <= \<const0>\;
m_axi_wdata(1) <= \<const0>\;
m_axi_wdata(0) <= \<const0>\;
m_axi_wlast <= \<const0>\;
m_axi_wstrb(7) <= \<const0>\;
m_axi_wstrb(6) <= \<const0>\;
m_axi_wstrb(5) <= \<const0>\;
m_axi_wstrb(4) <= \<const0>\;
m_axi_wstrb(3) <= \<const0>\;
m_axi_wstrb(2) <= \<const0>\;
m_axi_wstrb(1) <= \<const0>\;
m_axi_wstrb(0) <= \<const0>\;
m_axi_wvalid <= \<const0>\;
s_axi_awready <= \<const0>\;
s_axi_bid(0) <= \<const0>\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_bvalid <= \<const0>\;
s_axi_rid(0) <= \<const0>\;
s_axi_wready <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
\gen_upsizer.gen_full_upsizer.axi_upsizer_inst\: entity work.system_auto_us_1_axi_dwidth_converter_v2_1_11_axi_upsizer
port map (
D(60 downto 57) => s_axi_arregion(3 downto 0),
D(56 downto 53) => s_axi_arqos(3 downto 0),
D(52) => s_axi_arlock(0),
D(51 downto 44) => s_axi_arlen(7 downto 0),
D(43 downto 40) => s_axi_arcache(3 downto 0),
D(39 downto 38) => s_axi_arburst(1 downto 0),
D(37 downto 35) => s_axi_arsize(2 downto 0),
D(34 downto 32) => s_axi_arprot(2 downto 0),
D(31 downto 0) => s_axi_araddr(31 downto 0),
Q(44 downto 41) => m_axi_arregion(3 downto 0),
Q(40 downto 37) => m_axi_arqos(3 downto 0),
Q(36) => m_axi_arlock(0),
Q(35 downto 32) => m_axi_arcache(3 downto 0),
Q(31 downto 29) => m_axi_arprot(2 downto 0),
Q(28 downto 0) => m_axi_araddr(31 downto 3),
m_axi_araddr(2 downto 0) => m_axi_araddr(2 downto 0),
m_axi_arburst(1 downto 0) => m_axi_arburst(1 downto 0),
m_axi_arlen(7 downto 0) => m_axi_arlen(7 downto 0),
m_axi_arready => m_axi_arready,
m_axi_arsize(2 downto 0) => m_axi_arsize(2 downto 0),
m_axi_arvalid => m_axi_arvalid,
m_axi_rdata(63 downto 0) => m_axi_rdata(63 downto 0),
m_axi_rlast => m_axi_rlast,
m_axi_rready => m_axi_rready,
m_axi_rresp(1 downto 0) => m_axi_rresp(1 downto 0),
m_axi_rvalid => m_axi_rvalid,
\out\ => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid,
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rlast => s_axi_rlast,
s_axi_rready => s_axi_rready,
s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0),
s_axi_rvalid => s_axi_rvalid
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_us_1 is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_auto_us_1 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_auto_us_1 : entity is "system_auto_us_1,axi_dwidth_converter_v2_1_11_top,{}";
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of system_auto_us_1 : entity is "yes";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of system_auto_us_1 : entity is "axi_dwidth_converter_v2_1_11_top,Vivado 2016.4";
end system_auto_us_1;
architecture STRUCTURE of system_auto_us_1 is
signal NLW_inst_m_axi_awvalid_UNCONNECTED : STD_LOGIC;
signal NLW_inst_m_axi_bready_UNCONNECTED : STD_LOGIC;
signal NLW_inst_m_axi_wlast_UNCONNECTED : STD_LOGIC;
signal NLW_inst_m_axi_wvalid_UNCONNECTED : STD_LOGIC;
signal NLW_inst_s_axi_awready_UNCONNECTED : STD_LOGIC;
signal NLW_inst_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
signal NLW_inst_s_axi_wready_UNCONNECTED : STD_LOGIC;
signal NLW_inst_m_axi_awaddr_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_m_axi_awburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_m_axi_awcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_m_axi_awlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_m_axi_awlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_m_axi_awprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_m_axi_awqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_m_axi_awregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_m_axi_awsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_m_axi_wdata_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_m_axi_wstrb_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of inst : label is 32;
attribute C_AXI_IS_ACLK_ASYNC : integer;
attribute C_AXI_IS_ACLK_ASYNC of inst : label is 0;
attribute C_AXI_PROTOCOL : integer;
attribute C_AXI_PROTOCOL of inst : label is 0;
attribute C_AXI_SUPPORTS_READ : integer;
attribute C_AXI_SUPPORTS_READ of inst : label is 1;
attribute C_AXI_SUPPORTS_WRITE : integer;
attribute C_AXI_SUPPORTS_WRITE of inst : label is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of inst : label is "zynq";
attribute C_FIFO_MODE : integer;
attribute C_FIFO_MODE of inst : label is 0;
attribute C_MAX_SPLIT_BEATS : integer;
attribute C_MAX_SPLIT_BEATS of inst : label is 16;
attribute C_M_AXI_ACLK_RATIO : integer;
attribute C_M_AXI_ACLK_RATIO of inst : label is 2;
attribute C_M_AXI_BYTES_LOG : integer;
attribute C_M_AXI_BYTES_LOG of inst : label is 3;
attribute C_M_AXI_DATA_WIDTH : integer;
attribute C_M_AXI_DATA_WIDTH of inst : label is 64;
attribute C_PACKING_LEVEL : integer;
attribute C_PACKING_LEVEL of inst : label is 1;
attribute C_RATIO : integer;
attribute C_RATIO of inst : label is 0;
attribute C_RATIO_LOG : integer;
attribute C_RATIO_LOG of inst : label is 0;
attribute C_SUPPORTS_ID : integer;
attribute C_SUPPORTS_ID of inst : label is 0;
attribute C_SYNCHRONIZER_STAGE : integer;
attribute C_SYNCHRONIZER_STAGE of inst : label is 3;
attribute C_S_AXI_ACLK_RATIO : integer;
attribute C_S_AXI_ACLK_RATIO of inst : label is 1;
attribute C_S_AXI_BYTES_LOG : integer;
attribute C_S_AXI_BYTES_LOG of inst : label is 2;
attribute C_S_AXI_DATA_WIDTH : integer;
attribute C_S_AXI_DATA_WIDTH of inst : label is 32;
attribute C_S_AXI_ID_WIDTH : integer;
attribute C_S_AXI_ID_WIDTH of inst : label is 1;
attribute DowngradeIPIdentifiedWarnings of inst : label is "yes";
attribute P_AXI3 : integer;
attribute P_AXI3 of inst : label is 1;
attribute P_AXI4 : integer;
attribute P_AXI4 of inst : label is 0;
attribute P_AXILITE : integer;
attribute P_AXILITE of inst : label is 2;
attribute P_CONVERSION : integer;
attribute P_CONVERSION of inst : label is 2;
attribute P_MAX_SPLIT_BEATS : integer;
attribute P_MAX_SPLIT_BEATS of inst : label is 16;
begin
inst: entity work.system_auto_us_1_axi_dwidth_converter_v2_1_11_top
port map (
m_axi_aclk => '0',
m_axi_araddr(31 downto 0) => m_axi_araddr(31 downto 0),
m_axi_arburst(1 downto 0) => m_axi_arburst(1 downto 0),
m_axi_arcache(3 downto 0) => m_axi_arcache(3 downto 0),
m_axi_aresetn => '0',
m_axi_arlen(7 downto 0) => m_axi_arlen(7 downto 0),
m_axi_arlock(0) => m_axi_arlock(0),
m_axi_arprot(2 downto 0) => m_axi_arprot(2 downto 0),
m_axi_arqos(3 downto 0) => m_axi_arqos(3 downto 0),
m_axi_arready => m_axi_arready,
m_axi_arregion(3 downto 0) => m_axi_arregion(3 downto 0),
m_axi_arsize(2 downto 0) => m_axi_arsize(2 downto 0),
m_axi_arvalid => m_axi_arvalid,
m_axi_awaddr(31 downto 0) => NLW_inst_m_axi_awaddr_UNCONNECTED(31 downto 0),
m_axi_awburst(1 downto 0) => NLW_inst_m_axi_awburst_UNCONNECTED(1 downto 0),
m_axi_awcache(3 downto 0) => NLW_inst_m_axi_awcache_UNCONNECTED(3 downto 0),
m_axi_awlen(7 downto 0) => NLW_inst_m_axi_awlen_UNCONNECTED(7 downto 0),
m_axi_awlock(0) => NLW_inst_m_axi_awlock_UNCONNECTED(0),
m_axi_awprot(2 downto 0) => NLW_inst_m_axi_awprot_UNCONNECTED(2 downto 0),
m_axi_awqos(3 downto 0) => NLW_inst_m_axi_awqos_UNCONNECTED(3 downto 0),
m_axi_awready => '0',
m_axi_awregion(3 downto 0) => NLW_inst_m_axi_awregion_UNCONNECTED(3 downto 0),
m_axi_awsize(2 downto 0) => NLW_inst_m_axi_awsize_UNCONNECTED(2 downto 0),
m_axi_awvalid => NLW_inst_m_axi_awvalid_UNCONNECTED,
m_axi_bready => NLW_inst_m_axi_bready_UNCONNECTED,
m_axi_bresp(1 downto 0) => B"00",
m_axi_bvalid => '0',
m_axi_rdata(63 downto 0) => m_axi_rdata(63 downto 0),
m_axi_rlast => m_axi_rlast,
m_axi_rready => m_axi_rready,
m_axi_rresp(1 downto 0) => m_axi_rresp(1 downto 0),
m_axi_rvalid => m_axi_rvalid,
m_axi_wdata(63 downto 0) => NLW_inst_m_axi_wdata_UNCONNECTED(63 downto 0),
m_axi_wlast => NLW_inst_m_axi_wlast_UNCONNECTED,
m_axi_wready => '0',
m_axi_wstrb(7 downto 0) => NLW_inst_m_axi_wstrb_UNCONNECTED(7 downto 0),
m_axi_wvalid => NLW_inst_m_axi_wvalid_UNCONNECTED,
s_axi_aclk => s_axi_aclk,
s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0),
s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
s_axi_arcache(3 downto 0) => s_axi_arcache(3 downto 0),
s_axi_aresetn => s_axi_aresetn,
s_axi_arid(0) => '0',
s_axi_arlen(7 downto 0) => s_axi_arlen(7 downto 0),
s_axi_arlock(0) => s_axi_arlock(0),
s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0),
s_axi_arqos(3 downto 0) => s_axi_arqos(3 downto 0),
s_axi_arready => s_axi_arready,
s_axi_arregion(3 downto 0) => s_axi_arregion(3 downto 0),
s_axi_arsize(2 downto 0) => s_axi_arsize(2 downto 0),
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_awburst(1 downto 0) => B"01",
s_axi_awcache(3 downto 0) => B"0000",
s_axi_awid(0) => '0',
s_axi_awlen(7 downto 0) => B"00000000",
s_axi_awlock(0) => '0',
s_axi_awprot(2 downto 0) => B"000",
s_axi_awqos(3 downto 0) => B"0000",
s_axi_awready => NLW_inst_s_axi_awready_UNCONNECTED,
s_axi_awregion(3 downto 0) => B"0000",
s_axi_awsize(2 downto 0) => B"000",
s_axi_awvalid => '0',
s_axi_bid(0) => NLW_inst_s_axi_bid_UNCONNECTED(0),
s_axi_bready => '0',
s_axi_bresp(1 downto 0) => NLW_inst_s_axi_bresp_UNCONNECTED(1 downto 0),
s_axi_bvalid => NLW_inst_s_axi_bvalid_UNCONNECTED,
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rid(0) => NLW_inst_s_axi_rid_UNCONNECTED(0),
s_axi_rlast => s_axi_rlast,
s_axi_rready => s_axi_rready,
s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0),
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(31 downto 0) => B"00000000000000000000000000000000",
s_axi_wlast => '1',
s_axi_wready => NLW_inst_s_axi_wready_UNCONNECTED,
s_axi_wstrb(3 downto 0) => B"1111",
s_axi_wvalid => '0'
);
end STRUCTURE;
| mit |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/ov7670_hessian_split/ov7670_hessian_split.srcs/sources_1/bd/system/ip/system_zed_vga_0_0_1/sim/system_zed_vga_0_0.vhd | 2 | 3256 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:zed_vga:1.0
-- IP Revision: 2
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_zed_vga_0_0 IS
PORT (
rgb565 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
vga_r : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
vga_g : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
vga_b : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
);
END system_zed_vga_0_0;
ARCHITECTURE system_zed_vga_0_0_arch OF system_zed_vga_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_zed_vga_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT zed_vga IS
PORT (
rgb565 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
vga_r : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
vga_g : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
vga_b : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
);
END COMPONENT zed_vga;
BEGIN
U0 : zed_vga
PORT MAP (
rgb565 => rgb565,
vga_r => vga_r,
vga_g => vga_g,
vga_b => vga_b
);
END system_zed_vga_0_0_arch;
| mit |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_dual_fusion/zed_dual_fusion.srcs/sources_1/bd/system/ipshared/737d/debounce.vhd | 5 | 746 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity debounce is
port (
clk : in std_logic;
signal_in : in std_logic;
signal_out : out std_logic
);
end debounce;
architecture Behavioral of debounce is
signal c : unsigned(23 downto 0);
begin
process(clk)
begin
if rising_edge(clk) then
if signal_in = '1' then
if c = x"FFFFFF" then
signal_out <= '1';
else
signal_out <= '0';
end if;
c <= c + 1;
else
c <= (others => '0');
signal_out <= '0';
end if;
end if;
end process;
end Behavioral;
| mit |
ashikpoojari/Hardware-Security | DES CryptoCore/src/roundfunc.vhd | 2 | 2695 | ----------------------------------------------------------------------------------
-- Company: Hardware Security
-- Designer: Vinayaka Jyothi
--
-- Create Date: 18:42:44 11/28/2016
-- Design Name: DES Round Function
-- Module Name: des_roundfunc - Structural
-- Project Name: DES Crypto Core
-- Target Devices: ANY FPGAs
-- Tool versions: ISE, Vivado
-- Description: Implements round function of DES - Complete Structural Modelling
-- The final outputs are swap left and right 32 bits using registers
-- User may want to just without using registers
--
-- Dependencies: Modules :-> XP- Expansion; DESXOR1,DESXOR2 - XOR; S1..S8 - S-Boxes;
-- PP - Permutation; REG32 - 32 bit register
-- Files :-> xp.vhd,desxor1.vhd,desxor2.vhd, s1.vhd...s8.vhd,pp.vhd
-- reg32.vhd
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity roundfunc is port
(
clk : in std_logic;
reset : in std_logic;
li,ri : in std_logic_vector(1 to 32); --- Left and right 32 bits in
k : in std_logic_vector(1 to 48); -- Round key
lo,ro : out std_logic_vector(1 to 32) --Left and right 32 bits out (After swapping)
);
end roundfunc;
architecture behaviour of roundfunc is
signal xp_to_xor : std_logic_vector(1 to 48);
signal b1x,b2x,b3x,b4x,b5x,b6x,b7x,b8x: std_logic_vector(1 to 6);
signal so1x,so2x,so3x,so4x,so5x,so6x,so7x,so8x: std_logic_vector(1 to 4);
signal ppo,r_toreg32,l_toreg32 : std_logic_vector(1 to 32);
begin
xpension: entity work.xp port map ( ri=>ri,e=>xp_to_xor );
des_xor1: entity work.desxor1 port map ( e=>xp_to_xor,k=>k,b1x=>b1x, b2x=>b2x, b3x=>b3x, b4x=>b4x, b5x=>b5x, b6x=>b6x,b7x=>b7x, b8x=>b8x);
s1a: entity work.s1 port map ( clk=>clk, b=>b1x, so=>so1x);
s2a: entity work.s2 port map ( clk=>clk, b=>b2x, so=>so2x);
s3a: entity work.s3 port map ( clk=>clk, b=>b3x, so=>so3x);
s4a: entity work.s4 port map ( clk=>clk, b=>b4x, so=>so4x);
s5a: entity work.s5 port map ( clk=>clk, b=>b5x, so=>so5x);
s6a: entity work.s6 port map ( clk=>clk, b=>b6x, so=>so6x);
s7a: entity work.s7 port map ( clk=>clk, b=>b7x, so=>so7x);
s8a: entity work.s8 port map ( clk=>clk, b=>b8x, so=>so8x);
pperm: entity work.pp port map ( so1x=>so1x, so2x=>so2x, so3x=>so3x, so4x=>so4x, so5x=>so5x, so6x=>so6x, so7x=>so7x, so8x=>so8x,
ppo=>ppo );
des_xor2: entity work.desxor2 port map ( d=>ppo,l=>li, q=>r_toreg32 );
l_toreg32<=ri;
register32_left: entity work.reg32 port map ( a=>l_toreg32, q=>lo,reset=>reset, clk=>clk );
register32_right: entity work.reg32 port map ( a=>r_toreg32, q=>ro,reset=>reset, clk=>clk );
end;
| mit |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_dual_fusion/zed_dual_fusion.srcs/sources_1/bd/system/ip/system_util_vector_logic_0_0/synth/system_util_vector_logic_0_0.vhd | 3 | 4126 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:util_vector_logic:2.0
-- IP Revision: 2
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY util_vector_logic_v2_0;
USE util_vector_logic_v2_0.util_vector_logic;
ENTITY system_util_vector_logic_0_0 IS
PORT (
Op1 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
Op2 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
Res : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END system_util_vector_logic_0_0;
ARCHITECTURE system_util_vector_logic_0_0_arch OF system_util_vector_logic_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_util_vector_logic_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT util_vector_logic IS
GENERIC (
C_OPERATION : STRING;
C_SIZE : INTEGER
);
PORT (
Op1 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
Op2 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
Res : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT util_vector_logic;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF system_util_vector_logic_0_0_arch: ARCHITECTURE IS "util_vector_logic,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF system_util_vector_logic_0_0_arch : ARCHITECTURE IS "system_util_vector_logic_0_0,util_vector_logic,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF system_util_vector_logic_0_0_arch: ARCHITECTURE IS "system_util_vector_logic_0_0,util_vector_logic,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=util_vector_logic,x_ipVersion=2.0,x_ipCoreRevision=2,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_OPERATION=and,C_SIZE=1}";
BEGIN
U0 : util_vector_logic
GENERIC MAP (
C_OPERATION => "and",
C_SIZE => 1
)
PORT MAP (
Op1 => Op1,
Op2 => Op2,
Res => Res
);
END system_util_vector_logic_0_0_arch;
| mit |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_camera_hessian/zed_camera_hessian.srcs/sources_1/bd/system/ip/system_vga_sync_ref_0_0/system_vga_sync_ref_0_0_sim_netlist.vhdl | 3 | 70090 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Thu May 25 15:18:23 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- C:/ZyboIP/examples/zed_camera_test/zed_camera_test.srcs/sources_1/bd/system/ip/system_vga_sync_ref_0_0/system_vga_sync_ref_0_0_sim_netlist.vhdl
-- Design : system_vga_sync_ref_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_vga_sync_ref_0_0_vga_sync_ref is
port (
xaddr : out STD_LOGIC_VECTOR ( 9 downto 0 );
yaddr : out STD_LOGIC_VECTOR ( 9 downto 0 );
start : out STD_LOGIC;
active : out STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
vsync : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_vga_sync_ref_0_0_vga_sync_ref : entity is "vga_sync_ref";
end system_vga_sync_ref_0_0_vga_sync_ref;
architecture STRUCTURE of system_vga_sync_ref_0_0_vga_sync_ref is
signal \^active\ : STD_LOGIC;
signal active_i_1_n_0 : STD_LOGIC;
signal active_i_2_n_0 : STD_LOGIC;
signal counter : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \counter[12]_i_3_n_0\ : STD_LOGIC;
signal \counter[12]_i_4_n_0\ : STD_LOGIC;
signal \counter[12]_i_5_n_0\ : STD_LOGIC;
signal \counter[12]_i_6_n_0\ : STD_LOGIC;
signal \counter[16]_i_3_n_0\ : STD_LOGIC;
signal \counter[16]_i_4_n_0\ : STD_LOGIC;
signal \counter[16]_i_5_n_0\ : STD_LOGIC;
signal \counter[16]_i_6_n_0\ : STD_LOGIC;
signal \counter[20]_i_3_n_0\ : STD_LOGIC;
signal \counter[20]_i_4_n_0\ : STD_LOGIC;
signal \counter[20]_i_5_n_0\ : STD_LOGIC;
signal \counter[20]_i_6_n_0\ : STD_LOGIC;
signal \counter[24]_i_3_n_0\ : STD_LOGIC;
signal \counter[24]_i_4_n_0\ : STD_LOGIC;
signal \counter[24]_i_5_n_0\ : STD_LOGIC;
signal \counter[24]_i_6_n_0\ : STD_LOGIC;
signal \counter[28]_i_3_n_0\ : STD_LOGIC;
signal \counter[28]_i_4_n_0\ : STD_LOGIC;
signal \counter[28]_i_5_n_0\ : STD_LOGIC;
signal \counter[28]_i_6_n_0\ : STD_LOGIC;
signal \counter[31]_i_10_n_0\ : STD_LOGIC;
signal \counter[31]_i_11_n_0\ : STD_LOGIC;
signal \counter[31]_i_12_n_0\ : STD_LOGIC;
signal \counter[31]_i_13_n_0\ : STD_LOGIC;
signal \counter[31]_i_14_n_0\ : STD_LOGIC;
signal \counter[31]_i_15_n_0\ : STD_LOGIC;
signal \counter[31]_i_16_n_0\ : STD_LOGIC;
signal \counter[31]_i_17_n_0\ : STD_LOGIC;
signal \counter[31]_i_18_n_0\ : STD_LOGIC;
signal \counter[31]_i_19_n_0\ : STD_LOGIC;
signal \counter[31]_i_1_n_0\ : STD_LOGIC;
signal \counter[31]_i_2_n_0\ : STD_LOGIC;
signal \counter[31]_i_4_n_0\ : STD_LOGIC;
signal \counter[31]_i_6_n_0\ : STD_LOGIC;
signal \counter[31]_i_7_n_0\ : STD_LOGIC;
signal \counter[31]_i_8_n_0\ : STD_LOGIC;
signal \counter[31]_i_9_n_0\ : STD_LOGIC;
signal \counter[4]_i_3_n_0\ : STD_LOGIC;
signal \counter[4]_i_4_n_0\ : STD_LOGIC;
signal \counter[4]_i_5_n_0\ : STD_LOGIC;
signal \counter[4]_i_6_n_0\ : STD_LOGIC;
signal \counter[8]_i_3_n_0\ : STD_LOGIC;
signal \counter[8]_i_4_n_0\ : STD_LOGIC;
signal \counter[8]_i_5_n_0\ : STD_LOGIC;
signal \counter[8]_i_6_n_0\ : STD_LOGIC;
signal \counter_reg[12]_i_2_n_0\ : STD_LOGIC;
signal \counter_reg[12]_i_2_n_1\ : STD_LOGIC;
signal \counter_reg[12]_i_2_n_2\ : STD_LOGIC;
signal \counter_reg[12]_i_2_n_3\ : STD_LOGIC;
signal \counter_reg[12]_i_2_n_4\ : STD_LOGIC;
signal \counter_reg[12]_i_2_n_5\ : STD_LOGIC;
signal \counter_reg[12]_i_2_n_6\ : STD_LOGIC;
signal \counter_reg[12]_i_2_n_7\ : STD_LOGIC;
signal \counter_reg[16]_i_2_n_0\ : STD_LOGIC;
signal \counter_reg[16]_i_2_n_1\ : STD_LOGIC;
signal \counter_reg[16]_i_2_n_2\ : STD_LOGIC;
signal \counter_reg[16]_i_2_n_3\ : STD_LOGIC;
signal \counter_reg[16]_i_2_n_4\ : STD_LOGIC;
signal \counter_reg[16]_i_2_n_5\ : STD_LOGIC;
signal \counter_reg[16]_i_2_n_6\ : STD_LOGIC;
signal \counter_reg[16]_i_2_n_7\ : STD_LOGIC;
signal \counter_reg[20]_i_2_n_0\ : STD_LOGIC;
signal \counter_reg[20]_i_2_n_1\ : STD_LOGIC;
signal \counter_reg[20]_i_2_n_2\ : STD_LOGIC;
signal \counter_reg[20]_i_2_n_3\ : STD_LOGIC;
signal \counter_reg[20]_i_2_n_4\ : STD_LOGIC;
signal \counter_reg[20]_i_2_n_5\ : STD_LOGIC;
signal \counter_reg[20]_i_2_n_6\ : STD_LOGIC;
signal \counter_reg[20]_i_2_n_7\ : STD_LOGIC;
signal \counter_reg[24]_i_2_n_0\ : STD_LOGIC;
signal \counter_reg[24]_i_2_n_1\ : STD_LOGIC;
signal \counter_reg[24]_i_2_n_2\ : STD_LOGIC;
signal \counter_reg[24]_i_2_n_3\ : STD_LOGIC;
signal \counter_reg[24]_i_2_n_4\ : STD_LOGIC;
signal \counter_reg[24]_i_2_n_5\ : STD_LOGIC;
signal \counter_reg[24]_i_2_n_6\ : STD_LOGIC;
signal \counter_reg[24]_i_2_n_7\ : STD_LOGIC;
signal \counter_reg[28]_i_2_n_0\ : STD_LOGIC;
signal \counter_reg[28]_i_2_n_1\ : STD_LOGIC;
signal \counter_reg[28]_i_2_n_2\ : STD_LOGIC;
signal \counter_reg[28]_i_2_n_3\ : STD_LOGIC;
signal \counter_reg[28]_i_2_n_4\ : STD_LOGIC;
signal \counter_reg[28]_i_2_n_5\ : STD_LOGIC;
signal \counter_reg[28]_i_2_n_6\ : STD_LOGIC;
signal \counter_reg[28]_i_2_n_7\ : STD_LOGIC;
signal \counter_reg[31]_i_5_n_2\ : STD_LOGIC;
signal \counter_reg[31]_i_5_n_3\ : STD_LOGIC;
signal \counter_reg[31]_i_5_n_5\ : STD_LOGIC;
signal \counter_reg[31]_i_5_n_6\ : STD_LOGIC;
signal \counter_reg[31]_i_5_n_7\ : STD_LOGIC;
signal \counter_reg[4]_i_2_n_0\ : STD_LOGIC;
signal \counter_reg[4]_i_2_n_1\ : STD_LOGIC;
signal \counter_reg[4]_i_2_n_2\ : STD_LOGIC;
signal \counter_reg[4]_i_2_n_3\ : STD_LOGIC;
signal \counter_reg[4]_i_2_n_4\ : STD_LOGIC;
signal \counter_reg[4]_i_2_n_5\ : STD_LOGIC;
signal \counter_reg[4]_i_2_n_6\ : STD_LOGIC;
signal \counter_reg[4]_i_2_n_7\ : STD_LOGIC;
signal \counter_reg[8]_i_2_n_0\ : STD_LOGIC;
signal \counter_reg[8]_i_2_n_1\ : STD_LOGIC;
signal \counter_reg[8]_i_2_n_2\ : STD_LOGIC;
signal \counter_reg[8]_i_2_n_3\ : STD_LOGIC;
signal \counter_reg[8]_i_2_n_4\ : STD_LOGIC;
signal \counter_reg[8]_i_2_n_5\ : STD_LOGIC;
signal \counter_reg[8]_i_2_n_6\ : STD_LOGIC;
signal \counter_reg[8]_i_2_n_7\ : STD_LOGIC;
signal \h_count_reg[9]_i_1_n_0\ : STD_LOGIC;
signal \h_count_reg[9]_i_2_n_0\ : STD_LOGIC;
signal \h_count_reg[9]_i_4_n_0\ : STD_LOGIC;
signal \h_count_reg[9]_i_5_n_0\ : STD_LOGIC;
signal \h_count_reg[9]_i_6_n_0\ : STD_LOGIC;
signal \h_count_reg[9]_i_7_n_0\ : STD_LOGIC;
signal \h_count_reg[9]_i_8_n_0\ : STD_LOGIC;
signal \h_count_reg_reg__0\ : STD_LOGIC_VECTOR ( 9 downto 0 );
signal p_2_in : STD_LOGIC_VECTOR ( 31 downto 0 );
signal plusOp : STD_LOGIC_VECTOR ( 9 downto 0 );
signal \plusOp__0\ : STD_LOGIC_VECTOR ( 9 downto 0 );
signal \^start\ : STD_LOGIC;
signal start_i_1_n_0 : STD_LOGIC;
signal start_i_2_n_0 : STD_LOGIC;
signal start_i_3_n_0 : STD_LOGIC;
signal start_i_4_n_0 : STD_LOGIC;
signal start_i_5_n_0 : STD_LOGIC;
signal start_i_6_n_0 : STD_LOGIC;
signal \state[0]_i_1_n_0\ : STD_LOGIC;
signal \state[1]_i_10_n_0\ : STD_LOGIC;
signal \state[1]_i_11_n_0\ : STD_LOGIC;
signal \state[1]_i_1_n_0\ : STD_LOGIC;
signal \state[1]_i_2_n_0\ : STD_LOGIC;
signal \state[1]_i_3_n_0\ : STD_LOGIC;
signal \state[1]_i_4_n_0\ : STD_LOGIC;
signal \state[1]_i_5_n_0\ : STD_LOGIC;
signal \state[1]_i_6_n_0\ : STD_LOGIC;
signal \state[1]_i_7_n_0\ : STD_LOGIC;
signal \state[1]_i_8_n_0\ : STD_LOGIC;
signal \state[1]_i_9_n_0\ : STD_LOGIC;
signal \state_reg_n_0_[0]\ : STD_LOGIC;
signal \state_reg_n_0_[1]\ : STD_LOGIC;
signal \v_count_reg[9]_i_10_n_0\ : STD_LOGIC;
signal \v_count_reg[9]_i_1_n_0\ : STD_LOGIC;
signal \v_count_reg[9]_i_3_n_0\ : STD_LOGIC;
signal \v_count_reg[9]_i_4_n_0\ : STD_LOGIC;
signal \v_count_reg[9]_i_5_n_0\ : STD_LOGIC;
signal \v_count_reg[9]_i_6_n_0\ : STD_LOGIC;
signal \v_count_reg[9]_i_7_n_0\ : STD_LOGIC;
signal \v_count_reg[9]_i_8_n_0\ : STD_LOGIC;
signal \v_count_reg[9]_i_9_n_0\ : STD_LOGIC;
signal \v_count_reg_reg__0\ : STD_LOGIC_VECTOR ( 9 downto 0 );
signal \NLW_counter_reg[31]_i_5_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_counter_reg[31]_i_5_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \counter[0]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \counter[31]_i_15\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \counter[31]_i_18\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \h_count_reg[0]_i_1\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \h_count_reg[1]_i_1\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \h_count_reg[2]_i_1\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \h_count_reg[3]_i_1\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \h_count_reg[4]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \h_count_reg[7]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \h_count_reg[8]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \h_count_reg[9]_i_7\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \h_count_reg[9]_i_8\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of start_i_3 : label is "soft_lutpair10";
attribute SOFT_HLUTNM of start_i_4 : label is "soft_lutpair2";
attribute SOFT_HLUTNM of start_i_6 : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \state[1]_i_10\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \v_count_reg[0]_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \v_count_reg[1]_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \v_count_reg[2]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \v_count_reg[3]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \v_count_reg[4]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \v_count_reg[7]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \v_count_reg[8]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \v_count_reg[9]_i_5\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \v_count_reg[9]_i_6\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \v_count_reg[9]_i_7\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \v_count_reg[9]_i_8\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \v_count_reg[9]_i_9\ : label is "soft_lutpair8";
begin
active <= \^active\;
start <= \^start\;
active_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"000000000002FFFE"
)
port map (
I0 => \^active\,
I1 => active_i_2_n_0,
I2 => \v_count_reg[9]_i_1_n_0\,
I3 => start_i_2_n_0,
I4 => \state_reg_n_0_[0]\,
I5 => \counter[31]_i_1_n_0\,
O => active_i_1_n_0
);
active_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => \v_count_reg[9]_i_6_n_0\,
I1 => counter(25),
I2 => counter(26),
I3 => counter(24),
I4 => \v_count_reg[9]_i_5_n_0\,
I5 => \counter[31]_i_7_n_0\,
O => active_i_2_n_0
);
active_reg: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => active_i_1_n_0,
Q => \^active\,
R => '0'
);
\counter[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => counter(0),
O => p_2_in(0)
);
\counter[10]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[12]_i_2_n_6\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(10)
);
\counter[11]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[12]_i_2_n_5\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(11)
);
\counter[12]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[12]_i_2_n_4\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(12)
);
\counter[12]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(12),
O => \counter[12]_i_3_n_0\
);
\counter[12]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(11),
O => \counter[12]_i_4_n_0\
);
\counter[12]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(10),
O => \counter[12]_i_5_n_0\
);
\counter[12]_i_6\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(9),
O => \counter[12]_i_6_n_0\
);
\counter[13]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[16]_i_2_n_7\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(13)
);
\counter[14]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[16]_i_2_n_6\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(14)
);
\counter[15]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[16]_i_2_n_5\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(15)
);
\counter[16]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[16]_i_2_n_4\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(16)
);
\counter[16]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(16),
O => \counter[16]_i_3_n_0\
);
\counter[16]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(15),
O => \counter[16]_i_4_n_0\
);
\counter[16]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(14),
O => \counter[16]_i_5_n_0\
);
\counter[16]_i_6\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(13),
O => \counter[16]_i_6_n_0\
);
\counter[17]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[20]_i_2_n_7\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(17)
);
\counter[18]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[20]_i_2_n_6\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(18)
);
\counter[19]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[20]_i_2_n_5\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(19)
);
\counter[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[4]_i_2_n_7\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(1)
);
\counter[20]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[20]_i_2_n_4\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(20)
);
\counter[20]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(20),
O => \counter[20]_i_3_n_0\
);
\counter[20]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(19),
O => \counter[20]_i_4_n_0\
);
\counter[20]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(18),
O => \counter[20]_i_5_n_0\
);
\counter[20]_i_6\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(17),
O => \counter[20]_i_6_n_0\
);
\counter[21]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[24]_i_2_n_7\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(21)
);
\counter[22]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[24]_i_2_n_6\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(22)
);
\counter[23]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[24]_i_2_n_5\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(23)
);
\counter[24]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[24]_i_2_n_4\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(24)
);
\counter[24]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(24),
O => \counter[24]_i_3_n_0\
);
\counter[24]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(23),
O => \counter[24]_i_4_n_0\
);
\counter[24]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(22),
O => \counter[24]_i_5_n_0\
);
\counter[24]_i_6\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(21),
O => \counter[24]_i_6_n_0\
);
\counter[25]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[28]_i_2_n_7\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(25)
);
\counter[26]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[28]_i_2_n_6\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(26)
);
\counter[27]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[28]_i_2_n_5\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(27)
);
\counter[28]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[28]_i_2_n_4\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(28)
);
\counter[28]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(28),
O => \counter[28]_i_3_n_0\
);
\counter[28]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(27),
O => \counter[28]_i_4_n_0\
);
\counter[28]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(26),
O => \counter[28]_i_5_n_0\
);
\counter[28]_i_6\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(25),
O => \counter[28]_i_6_n_0\
);
\counter[29]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[31]_i_5_n_7\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(29)
);
\counter[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[4]_i_2_n_6\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(2)
);
\counter[30]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[31]_i_5_n_6\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(30)
);
\counter[31]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => vsync,
I1 => rst,
O => \counter[31]_i_1_n_0\
);
\counter[31]_i_10\: unisim.vcomponents.LUT3
generic map(
INIT => X"FE"
)
port map (
I0 => counter(24),
I1 => counter(26),
I2 => counter(25),
O => \counter[31]_i_10_n_0\
);
\counter[31]_i_11\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(31),
O => \counter[31]_i_11_n_0\
);
\counter[31]_i_12\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(30),
O => \counter[31]_i_12_n_0\
);
\counter[31]_i_13\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(29),
O => \counter[31]_i_13_n_0\
);
\counter[31]_i_14\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => counter(17),
I1 => counter(16),
I2 => counter(19),
I3 => counter(18),
I4 => \v_count_reg[9]_i_10_n_0\,
I5 => \counter[31]_i_10_n_0\,
O => \counter[31]_i_14_n_0\
);
\counter[31]_i_15\: unisim.vcomponents.LUT3
generic map(
INIT => X"FE"
)
port map (
I0 => counter(31),
I1 => counter(30),
I2 => counter(29),
O => \counter[31]_i_15_n_0\
);
\counter[31]_i_16\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF7FFFFFFFFFFF"
)
port map (
I0 => counter(2),
I1 => counter(1),
I2 => counter(0),
I3 => counter(3),
I4 => \state_reg_n_0_[1]\,
I5 => \state_reg_n_0_[0]\,
O => \counter[31]_i_16_n_0\
);
\counter[31]_i_17\: unisim.vcomponents.LUT4
generic map(
INIT => X"DFFF"
)
port map (
I0 => counter(4),
I1 => counter(8),
I2 => counter(6),
I3 => counter(5),
O => \counter[31]_i_17_n_0\
);
\counter[31]_i_18\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => counter(10),
I1 => counter(11),
O => \counter[31]_i_18_n_0\
);
\counter[31]_i_19\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => counter(15),
I1 => counter(14),
I2 => counter(13),
I3 => counter(12),
O => \counter[31]_i_19_n_0\
);
\counter[31]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => \state_reg_n_0_[0]\,
I1 => \state_reg_n_0_[1]\,
O => \counter[31]_i_2_n_0\
);
\counter[31]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"4440404044404440"
)
port map (
I0 => \counter[31]_i_4_n_0\,
I1 => \counter_reg[31]_i_5_n_5\,
I2 => \counter[31]_i_6_n_0\,
I3 => \counter[31]_i_7_n_0\,
I4 => \counter[31]_i_8_n_0\,
I5 => \counter[31]_i_9_n_0\,
O => p_2_in(31)
);
\counter[31]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => \v_count_reg[9]_i_6_n_0\,
I1 => start_i_5_n_0,
I2 => start_i_4_n_0,
I3 => \v_count_reg[9]_i_5_n_0\,
I4 => start_i_3_n_0,
I5 => \counter[31]_i_10_n_0\,
O => \counter[31]_i_4_n_0\
);
\counter[31]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFEFEFEFF"
)
port map (
I0 => \counter[31]_i_14_n_0\,
I1 => counter(28),
I2 => counter(27),
I3 => \state_reg_n_0_[1]\,
I4 => \state_reg_n_0_[0]\,
I5 => \counter[31]_i_15_n_0\,
O => \counter[31]_i_6_n_0\
);
\counter[31]_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFEFF"
)
port map (
I0 => \counter[31]_i_16_n_0\,
I1 => \counter[31]_i_17_n_0\,
I2 => counter(7),
I3 => counter(9),
I4 => \counter[31]_i_18_n_0\,
I5 => \counter[31]_i_19_n_0\,
O => \counter[31]_i_7_n_0\
);
\counter[31]_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFBFFF"
)
port map (
I0 => \h_count_reg[9]_i_5_n_0\,
I1 => counter(3),
I2 => counter(0),
I3 => counter(7),
I4 => counter(6),
I5 => \h_count_reg[9]_i_2_n_0\,
O => \counter[31]_i_8_n_0\
);
\counter[31]_i_9\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000001"
)
port map (
I0 => \counter[31]_i_19_n_0\,
I1 => counter(10),
I2 => counter(11),
I3 => counter(8),
I4 => counter(9),
O => \counter[31]_i_9_n_0\
);
\counter[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[4]_i_2_n_5\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(3)
);
\counter[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[4]_i_2_n_4\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(4)
);
\counter[4]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(4),
O => \counter[4]_i_3_n_0\
);
\counter[4]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(3),
O => \counter[4]_i_4_n_0\
);
\counter[4]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(2),
O => \counter[4]_i_5_n_0\
);
\counter[4]_i_6\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(1),
O => \counter[4]_i_6_n_0\
);
\counter[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[8]_i_2_n_7\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(5)
);
\counter[6]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[8]_i_2_n_6\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(6)
);
\counter[7]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[8]_i_2_n_5\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(7)
);
\counter[8]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[8]_i_2_n_4\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(8)
);
\counter[8]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(8),
O => \counter[8]_i_3_n_0\
);
\counter[8]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(7),
O => \counter[8]_i_4_n_0\
);
\counter[8]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(6),
O => \counter[8]_i_5_n_0\
);
\counter[8]_i_6\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(5),
O => \counter[8]_i_6_n_0\
);
\counter[9]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[12]_i_2_n_7\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(9)
);
\counter_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(0),
Q => counter(0),
R => \counter[31]_i_1_n_0\
);
\counter_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(10),
Q => counter(10),
R => \counter[31]_i_1_n_0\
);
\counter_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(11),
Q => counter(11),
R => \counter[31]_i_1_n_0\
);
\counter_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(12),
Q => counter(12),
R => \counter[31]_i_1_n_0\
);
\counter_reg[12]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => \counter_reg[8]_i_2_n_0\,
CO(3) => \counter_reg[12]_i_2_n_0\,
CO(2) => \counter_reg[12]_i_2_n_1\,
CO(1) => \counter_reg[12]_i_2_n_2\,
CO(0) => \counter_reg[12]_i_2_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \counter_reg[12]_i_2_n_4\,
O(2) => \counter_reg[12]_i_2_n_5\,
O(1) => \counter_reg[12]_i_2_n_6\,
O(0) => \counter_reg[12]_i_2_n_7\,
S(3) => \counter[12]_i_3_n_0\,
S(2) => \counter[12]_i_4_n_0\,
S(1) => \counter[12]_i_5_n_0\,
S(0) => \counter[12]_i_6_n_0\
);
\counter_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(13),
Q => counter(13),
R => \counter[31]_i_1_n_0\
);
\counter_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(14),
Q => counter(14),
R => \counter[31]_i_1_n_0\
);
\counter_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(15),
Q => counter(15),
R => \counter[31]_i_1_n_0\
);
\counter_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(16),
Q => counter(16),
R => \counter[31]_i_1_n_0\
);
\counter_reg[16]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => \counter_reg[12]_i_2_n_0\,
CO(3) => \counter_reg[16]_i_2_n_0\,
CO(2) => \counter_reg[16]_i_2_n_1\,
CO(1) => \counter_reg[16]_i_2_n_2\,
CO(0) => \counter_reg[16]_i_2_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \counter_reg[16]_i_2_n_4\,
O(2) => \counter_reg[16]_i_2_n_5\,
O(1) => \counter_reg[16]_i_2_n_6\,
O(0) => \counter_reg[16]_i_2_n_7\,
S(3) => \counter[16]_i_3_n_0\,
S(2) => \counter[16]_i_4_n_0\,
S(1) => \counter[16]_i_5_n_0\,
S(0) => \counter[16]_i_6_n_0\
);
\counter_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(17),
Q => counter(17),
R => \counter[31]_i_1_n_0\
);
\counter_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(18),
Q => counter(18),
R => \counter[31]_i_1_n_0\
);
\counter_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(19),
Q => counter(19),
R => \counter[31]_i_1_n_0\
);
\counter_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(1),
Q => counter(1),
R => \counter[31]_i_1_n_0\
);
\counter_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(20),
Q => counter(20),
R => \counter[31]_i_1_n_0\
);
\counter_reg[20]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => \counter_reg[16]_i_2_n_0\,
CO(3) => \counter_reg[20]_i_2_n_0\,
CO(2) => \counter_reg[20]_i_2_n_1\,
CO(1) => \counter_reg[20]_i_2_n_2\,
CO(0) => \counter_reg[20]_i_2_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \counter_reg[20]_i_2_n_4\,
O(2) => \counter_reg[20]_i_2_n_5\,
O(1) => \counter_reg[20]_i_2_n_6\,
O(0) => \counter_reg[20]_i_2_n_7\,
S(3) => \counter[20]_i_3_n_0\,
S(2) => \counter[20]_i_4_n_0\,
S(1) => \counter[20]_i_5_n_0\,
S(0) => \counter[20]_i_6_n_0\
);
\counter_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(21),
Q => counter(21),
R => \counter[31]_i_1_n_0\
);
\counter_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(22),
Q => counter(22),
R => \counter[31]_i_1_n_0\
);
\counter_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(23),
Q => counter(23),
R => \counter[31]_i_1_n_0\
);
\counter_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(24),
Q => counter(24),
R => \counter[31]_i_1_n_0\
);
\counter_reg[24]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => \counter_reg[20]_i_2_n_0\,
CO(3) => \counter_reg[24]_i_2_n_0\,
CO(2) => \counter_reg[24]_i_2_n_1\,
CO(1) => \counter_reg[24]_i_2_n_2\,
CO(0) => \counter_reg[24]_i_2_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \counter_reg[24]_i_2_n_4\,
O(2) => \counter_reg[24]_i_2_n_5\,
O(1) => \counter_reg[24]_i_2_n_6\,
O(0) => \counter_reg[24]_i_2_n_7\,
S(3) => \counter[24]_i_3_n_0\,
S(2) => \counter[24]_i_4_n_0\,
S(1) => \counter[24]_i_5_n_0\,
S(0) => \counter[24]_i_6_n_0\
);
\counter_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(25),
Q => counter(25),
R => \counter[31]_i_1_n_0\
);
\counter_reg[26]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(26),
Q => counter(26),
R => \counter[31]_i_1_n_0\
);
\counter_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(27),
Q => counter(27),
R => \counter[31]_i_1_n_0\
);
\counter_reg[28]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(28),
Q => counter(28),
R => \counter[31]_i_1_n_0\
);
\counter_reg[28]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => \counter_reg[24]_i_2_n_0\,
CO(3) => \counter_reg[28]_i_2_n_0\,
CO(2) => \counter_reg[28]_i_2_n_1\,
CO(1) => \counter_reg[28]_i_2_n_2\,
CO(0) => \counter_reg[28]_i_2_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \counter_reg[28]_i_2_n_4\,
O(2) => \counter_reg[28]_i_2_n_5\,
O(1) => \counter_reg[28]_i_2_n_6\,
O(0) => \counter_reg[28]_i_2_n_7\,
S(3) => \counter[28]_i_3_n_0\,
S(2) => \counter[28]_i_4_n_0\,
S(1) => \counter[28]_i_5_n_0\,
S(0) => \counter[28]_i_6_n_0\
);
\counter_reg[29]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(29),
Q => counter(29),
R => \counter[31]_i_1_n_0\
);
\counter_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(2),
Q => counter(2),
R => \counter[31]_i_1_n_0\
);
\counter_reg[30]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(30),
Q => counter(30),
R => \counter[31]_i_1_n_0\
);
\counter_reg[31]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(31),
Q => counter(31),
R => \counter[31]_i_1_n_0\
);
\counter_reg[31]_i_5\: unisim.vcomponents.CARRY4
port map (
CI => \counter_reg[28]_i_2_n_0\,
CO(3 downto 2) => \NLW_counter_reg[31]_i_5_CO_UNCONNECTED\(3 downto 2),
CO(1) => \counter_reg[31]_i_5_n_2\,
CO(0) => \counter_reg[31]_i_5_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \NLW_counter_reg[31]_i_5_O_UNCONNECTED\(3),
O(2) => \counter_reg[31]_i_5_n_5\,
O(1) => \counter_reg[31]_i_5_n_6\,
O(0) => \counter_reg[31]_i_5_n_7\,
S(3) => '0',
S(2) => \counter[31]_i_11_n_0\,
S(1) => \counter[31]_i_12_n_0\,
S(0) => \counter[31]_i_13_n_0\
);
\counter_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(3),
Q => counter(3),
R => \counter[31]_i_1_n_0\
);
\counter_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(4),
Q => counter(4),
R => \counter[31]_i_1_n_0\
);
\counter_reg[4]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \counter_reg[4]_i_2_n_0\,
CO(2) => \counter_reg[4]_i_2_n_1\,
CO(1) => \counter_reg[4]_i_2_n_2\,
CO(0) => \counter_reg[4]_i_2_n_3\,
CYINIT => counter(0),
DI(3 downto 0) => B"0000",
O(3) => \counter_reg[4]_i_2_n_4\,
O(2) => \counter_reg[4]_i_2_n_5\,
O(1) => \counter_reg[4]_i_2_n_6\,
O(0) => \counter_reg[4]_i_2_n_7\,
S(3) => \counter[4]_i_3_n_0\,
S(2) => \counter[4]_i_4_n_0\,
S(1) => \counter[4]_i_5_n_0\,
S(0) => \counter[4]_i_6_n_0\
);
\counter_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(5),
Q => counter(5),
R => \counter[31]_i_1_n_0\
);
\counter_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(6),
Q => counter(6),
R => \counter[31]_i_1_n_0\
);
\counter_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(7),
Q => counter(7),
R => \counter[31]_i_1_n_0\
);
\counter_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(8),
Q => counter(8),
R => \counter[31]_i_1_n_0\
);
\counter_reg[8]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => \counter_reg[4]_i_2_n_0\,
CO(3) => \counter_reg[8]_i_2_n_0\,
CO(2) => \counter_reg[8]_i_2_n_1\,
CO(1) => \counter_reg[8]_i_2_n_2\,
CO(0) => \counter_reg[8]_i_2_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \counter_reg[8]_i_2_n_4\,
O(2) => \counter_reg[8]_i_2_n_5\,
O(1) => \counter_reg[8]_i_2_n_6\,
O(0) => \counter_reg[8]_i_2_n_7\,
S(3) => \counter[8]_i_3_n_0\,
S(2) => \counter[8]_i_4_n_0\,
S(1) => \counter[8]_i_5_n_0\,
S(0) => \counter[8]_i_6_n_0\
);
\counter_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(9),
Q => counter(9),
R => \counter[31]_i_1_n_0\
);
\h_count_reg[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \h_count_reg_reg__0\(0),
O => \plusOp__0\(0)
);
\h_count_reg[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \h_count_reg_reg__0\(0),
I1 => \h_count_reg_reg__0\(1),
O => \plusOp__0\(1)
);
\h_count_reg[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => \h_count_reg_reg__0\(2),
I1 => \h_count_reg_reg__0\(0),
I2 => \h_count_reg_reg__0\(1),
O => \plusOp__0\(2)
);
\h_count_reg[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => \h_count_reg_reg__0\(3),
I1 => \h_count_reg_reg__0\(1),
I2 => \h_count_reg_reg__0\(0),
I3 => \h_count_reg_reg__0\(2),
O => \plusOp__0\(3)
);
\h_count_reg[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \h_count_reg_reg__0\(2),
I1 => \h_count_reg_reg__0\(0),
I2 => \h_count_reg_reg__0\(1),
I3 => \h_count_reg_reg__0\(3),
I4 => \h_count_reg_reg__0\(4),
O => \plusOp__0\(4)
);
\h_count_reg[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6AAAAAAAAAAAAAAA"
)
port map (
I0 => \h_count_reg_reg__0\(5),
I1 => \h_count_reg_reg__0\(2),
I2 => \h_count_reg_reg__0\(0),
I3 => \h_count_reg_reg__0\(1),
I4 => \h_count_reg_reg__0\(3),
I5 => \h_count_reg_reg__0\(4),
O => \plusOp__0\(5)
);
\h_count_reg[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => \h_count_reg_reg__0\(6),
I1 => \h_count_reg[9]_i_7_n_0\,
I2 => \h_count_reg_reg__0\(5),
O => \plusOp__0\(6)
);
\h_count_reg[7]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => \h_count_reg_reg__0\(7),
I1 => \h_count_reg_reg__0\(5),
I2 => \h_count_reg[9]_i_7_n_0\,
I3 => \h_count_reg_reg__0\(6),
O => \plusOp__0\(7)
);
\h_count_reg[8]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"6AAAAAAA"
)
port map (
I0 => \h_count_reg_reg__0\(8),
I1 => \h_count_reg_reg__0\(6),
I2 => \h_count_reg[9]_i_7_n_0\,
I3 => \h_count_reg_reg__0\(5),
I4 => \h_count_reg_reg__0\(7),
O => \plusOp__0\(8)
);
\h_count_reg[9]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"DDDDDDFDDDDDDDDD"
)
port map (
I0 => rst,
I1 => vsync,
I2 => \counter[31]_i_9_n_0\,
I3 => \h_count_reg[9]_i_4_n_0\,
I4 => \h_count_reg[9]_i_5_n_0\,
I5 => \h_count_reg[9]_i_6_n_0\,
O => \h_count_reg[9]_i_1_n_0\
);
\h_count_reg[9]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \state_reg_n_0_[0]\,
I1 => \state_reg_n_0_[1]\,
O => \h_count_reg[9]_i_2_n_0\
);
\h_count_reg[9]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"6AAAAAAAAAAAAAAA"
)
port map (
I0 => \h_count_reg_reg__0\(9),
I1 => \h_count_reg_reg__0\(7),
I2 => \h_count_reg_reg__0\(5),
I3 => \h_count_reg[9]_i_7_n_0\,
I4 => \h_count_reg_reg__0\(6),
I5 => \h_count_reg_reg__0\(8),
O => \plusOp__0\(9)
);
\h_count_reg[9]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"FDFFFFFFFFFFFFFF"
)
port map (
I0 => \state_reg_n_0_[1]\,
I1 => \state_reg_n_0_[0]\,
I2 => counter(6),
I3 => counter(7),
I4 => counter(0),
I5 => counter(3),
O => \h_count_reg[9]_i_4_n_0\
);
\h_count_reg[9]_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFF7"
)
port map (
I0 => counter(1),
I1 => counter(2),
I2 => counter(4),
I3 => counter(5),
O => \h_count_reg[9]_i_5_n_0\
);
\h_count_reg[9]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => \v_count_reg[9]_i_5_n_0\,
I1 => counter(24),
I2 => counter(26),
I3 => counter(25),
I4 => \v_count_reg[9]_i_10_n_0\,
I5 => \h_count_reg[9]_i_8_n_0\,
O => \h_count_reg[9]_i_6_n_0\
);
\h_count_reg[9]_i_7\: unisim.vcomponents.LUT5
generic map(
INIT => X"80000000"
)
port map (
I0 => \h_count_reg_reg__0\(4),
I1 => \h_count_reg_reg__0\(3),
I2 => \h_count_reg_reg__0\(1),
I3 => \h_count_reg_reg__0\(0),
I4 => \h_count_reg_reg__0\(2),
O => \h_count_reg[9]_i_7_n_0\
);
\h_count_reg[9]_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => counter(17),
I1 => counter(16),
I2 => counter(19),
I3 => counter(18),
O => \h_count_reg[9]_i_8_n_0\
);
\h_count_reg_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \h_count_reg[9]_i_2_n_0\,
D => \plusOp__0\(0),
Q => \h_count_reg_reg__0\(0),
R => \h_count_reg[9]_i_1_n_0\
);
\h_count_reg_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \h_count_reg[9]_i_2_n_0\,
D => \plusOp__0\(1),
Q => \h_count_reg_reg__0\(1),
R => \h_count_reg[9]_i_1_n_0\
);
\h_count_reg_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \h_count_reg[9]_i_2_n_0\,
D => \plusOp__0\(2),
Q => \h_count_reg_reg__0\(2),
R => \h_count_reg[9]_i_1_n_0\
);
\h_count_reg_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \h_count_reg[9]_i_2_n_0\,
D => \plusOp__0\(3),
Q => \h_count_reg_reg__0\(3),
R => \h_count_reg[9]_i_1_n_0\
);
\h_count_reg_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \h_count_reg[9]_i_2_n_0\,
D => \plusOp__0\(4),
Q => \h_count_reg_reg__0\(4),
R => \h_count_reg[9]_i_1_n_0\
);
\h_count_reg_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \h_count_reg[9]_i_2_n_0\,
D => \plusOp__0\(5),
Q => \h_count_reg_reg__0\(5),
R => \h_count_reg[9]_i_1_n_0\
);
\h_count_reg_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \h_count_reg[9]_i_2_n_0\,
D => \plusOp__0\(6),
Q => \h_count_reg_reg__0\(6),
R => \h_count_reg[9]_i_1_n_0\
);
\h_count_reg_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \h_count_reg[9]_i_2_n_0\,
D => \plusOp__0\(7),
Q => \h_count_reg_reg__0\(7),
R => \h_count_reg[9]_i_1_n_0\
);
\h_count_reg_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \h_count_reg[9]_i_2_n_0\,
D => \plusOp__0\(8),
Q => \h_count_reg_reg__0\(8),
R => \h_count_reg[9]_i_1_n_0\
);
\h_count_reg_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \h_count_reg[9]_i_2_n_0\,
D => \plusOp__0\(9),
Q => \h_count_reg_reg__0\(9),
R => \h_count_reg[9]_i_1_n_0\
);
start_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000220E0000"
)
port map (
I0 => \^start\,
I1 => start_i_2_n_0,
I2 => \state_reg_n_0_[0]\,
I3 => \state_reg_n_0_[1]\,
I4 => rst,
I5 => vsync,
O => start_i_1_n_0
);
start_i_2: unisim.vcomponents.LUT4
generic map(
INIT => X"0002"
)
port map (
I0 => \h_count_reg[9]_i_6_n_0\,
I1 => start_i_3_n_0,
I2 => start_i_4_n_0,
I3 => start_i_5_n_0,
O => start_i_2_n_0
);
start_i_3: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => counter(15),
I1 => counter(14),
I2 => counter(4),
I3 => counter(6),
O => start_i_3_n_0
);
start_i_4: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => counter(3),
I1 => counter(1),
I2 => counter(2),
I3 => counter(11),
I4 => start_i_6_n_0,
O => start_i_4_n_0
);
start_i_5: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFF7"
)
port map (
I0 => counter(5),
I1 => counter(13),
I2 => counter(8),
I3 => counter(9),
I4 => \state_reg_n_0_[1]\,
I5 => \state_reg_n_0_[0]\,
O => start_i_5_n_0
);
start_i_6: unisim.vcomponents.LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => counter(7),
I1 => counter(0),
I2 => counter(10),
I3 => counter(12),
O => start_i_6_n_0
);
start_reg: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => start_i_1_n_0,
Q => \^start\,
R => '0'
);
\state[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000FE560000"
)
port map (
I0 => \state_reg_n_0_[0]\,
I1 => \state[1]_i_2_n_0\,
I2 => start_i_2_n_0,
I3 => \state_reg_n_0_[1]\,
I4 => rst,
I5 => vsync,
O => \state[0]_i_1_n_0\
);
\state[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"0000E6E2"
)
port map (
I0 => \state_reg_n_0_[1]\,
I1 => \state[1]_i_2_n_0\,
I2 => \state[1]_i_3_n_0\,
I3 => \state_reg_n_0_[0]\,
I4 => \state[1]_i_4_n_0\,
O => \state[1]_i_1_n_0\
);
\state[1]_i_10\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => counter(2),
I1 => counter(1),
O => \state[1]_i_10_n_0\
);
\state[1]_i_11\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => counter(27),
I1 => counter(28),
O => \state[1]_i_11_n_0\
);
\state[1]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"4444444F44444444"
)
port map (
I0 => \counter[31]_i_7_n_0\,
I1 => \h_count_reg[9]_i_6_n_0\,
I2 => \state[1]_i_5_n_0\,
I3 => \state[1]_i_6_n_0\,
I4 => \v_count_reg[9]_i_4_n_0\,
I5 => \state[1]_i_7_n_0\,
O => \state[1]_i_2_n_0\
);
\state[1]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0010000000000000"
)
port map (
I0 => \v_count_reg[9]_i_7_n_0\,
I1 => \v_count_reg_reg__0\(9),
I2 => \v_count_reg_reg__0\(6),
I3 => \v_count_reg_reg__0\(5),
I4 => \v_count_reg_reg__0\(7),
I5 => \v_count_reg_reg__0\(8),
O => \state[1]_i_3_n_0\
);
\state[1]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAABAAAAAAAA"
)
port map (
I0 => \counter[31]_i_1_n_0\,
I1 => \state[1]_i_8_n_0\,
I2 => \state[1]_i_9_n_0\,
I3 => \state[1]_i_6_n_0\,
I4 => start_i_4_n_0,
I5 => \state[1]_i_7_n_0\,
O => \state[1]_i_4_n_0\
);
\state[1]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFB"
)
port map (
I0 => \state[1]_i_10_n_0\,
I1 => counter(7),
I2 => counter(5),
I3 => \h_count_reg[9]_i_2_n_0\,
I4 => \state[1]_i_9_n_0\,
I5 => \v_count_reg[9]_i_9_n_0\,
O => \state[1]_i_5_n_0\
);
\state[1]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => counter(25),
I1 => counter(26),
I2 => \state[1]_i_11_n_0\,
I3 => counter(16),
I4 => counter(31),
I5 => \v_count_reg[9]_i_8_n_0\,
O => \state[1]_i_6_n_0\
);
\state[1]_i_7\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000001"
)
port map (
I0 => counter(18),
I1 => counter(17),
I2 => counter(19),
I3 => \v_count_reg[9]_i_10_n_0\,
I4 => counter(24),
O => \state[1]_i_7_n_0\
);
\state[1]_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFF7"
)
port map (
I0 => counter(13),
I1 => counter(5),
I2 => \state_reg_n_0_[0]\,
I3 => \state_reg_n_0_[1]\,
I4 => counter(9),
I5 => counter(14),
O => \state[1]_i_8_n_0\
);
\state[1]_i_9\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => counter(30),
I1 => counter(29),
I2 => counter(4),
I3 => counter(8),
O => \state[1]_i_9_n_0\
);
\state_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => \state[0]_i_1_n_0\,
Q => \state_reg_n_0_[0]\,
R => '0'
);
\state_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => \state[1]_i_1_n_0\,
Q => \state_reg_n_0_[1]\,
R => '0'
);
\v_count_reg[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \v_count_reg_reg__0\(0),
O => plusOp(0)
);
\v_count_reg[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \v_count_reg_reg__0\(0),
I1 => \v_count_reg_reg__0\(1),
O => plusOp(1)
);
\v_count_reg[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => \v_count_reg_reg__0\(2),
I1 => \v_count_reg_reg__0\(0),
I2 => \v_count_reg_reg__0\(1),
O => plusOp(2)
);
\v_count_reg[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => \v_count_reg_reg__0\(3),
I1 => \v_count_reg_reg__0\(1),
I2 => \v_count_reg_reg__0\(0),
I3 => \v_count_reg_reg__0\(2),
O => plusOp(3)
);
\v_count_reg[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"6AAAAAAA"
)
port map (
I0 => \v_count_reg_reg__0\(4),
I1 => \v_count_reg_reg__0\(2),
I2 => \v_count_reg_reg__0\(0),
I3 => \v_count_reg_reg__0\(1),
I4 => \v_count_reg_reg__0\(3),
O => plusOp(4)
);
\v_count_reg[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6AAAAAAAAAAAAAAA"
)
port map (
I0 => \v_count_reg_reg__0\(5),
I1 => \v_count_reg_reg__0\(3),
I2 => \v_count_reg_reg__0\(1),
I3 => \v_count_reg_reg__0\(0),
I4 => \v_count_reg_reg__0\(2),
I5 => \v_count_reg_reg__0\(4),
O => plusOp(5)
);
\v_count_reg[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => \v_count_reg_reg__0\(6),
I1 => \v_count_reg[9]_i_7_n_0\,
I2 => \v_count_reg_reg__0\(5),
O => plusOp(6)
);
\v_count_reg[7]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"A6AA"
)
port map (
I0 => \v_count_reg_reg__0\(7),
I1 => \v_count_reg_reg__0\(5),
I2 => \v_count_reg[9]_i_7_n_0\,
I3 => \v_count_reg_reg__0\(6),
O => plusOp(7)
);
\v_count_reg[8]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"A6AAAAAA"
)
port map (
I0 => \v_count_reg_reg__0\(8),
I1 => \v_count_reg_reg__0\(6),
I2 => \v_count_reg[9]_i_7_n_0\,
I3 => \v_count_reg_reg__0\(5),
I4 => \v_count_reg_reg__0\(7),
O => plusOp(8)
);
\v_count_reg[9]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000001"
)
port map (
I0 => \v_count_reg[9]_i_3_n_0\,
I1 => \v_count_reg[9]_i_4_n_0\,
I2 => \v_count_reg[9]_i_5_n_0\,
I3 => \v_count_reg[9]_i_6_n_0\,
I4 => \state[1]_i_3_n_0\,
O => \v_count_reg[9]_i_1_n_0\
);
\v_count_reg[9]_i_10\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => counter(21),
I1 => counter(20),
I2 => counter(23),
I3 => counter(22),
O => \v_count_reg[9]_i_10_n_0\
);
\v_count_reg[9]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAA6AAAAAAAAAAA"
)
port map (
I0 => \v_count_reg_reg__0\(9),
I1 => \v_count_reg_reg__0\(7),
I2 => \v_count_reg_reg__0\(8),
I3 => \v_count_reg_reg__0\(6),
I4 => \v_count_reg[9]_i_7_n_0\,
I5 => \v_count_reg_reg__0\(5),
O => plusOp(9)
);
\v_count_reg[9]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFB"
)
port map (
I0 => \v_count_reg[9]_i_8_n_0\,
I1 => counter(7),
I2 => counter(8),
I3 => \h_count_reg[9]_i_5_n_0\,
I4 => \v_count_reg[9]_i_9_n_0\,
I5 => \counter[31]_i_10_n_0\,
O => \v_count_reg[9]_i_3_n_0\
);
\v_count_reg[9]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => counter(11),
I1 => counter(10),
I2 => counter(9),
I3 => counter(14),
I4 => counter(12),
I5 => counter(13),
O => \v_count_reg[9]_i_4_n_0\
);
\v_count_reg[9]_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => counter(28),
I1 => counter(27),
I2 => counter(29),
I3 => counter(30),
I4 => counter(31),
O => \v_count_reg[9]_i_5_n_0\
);
\v_count_reg[9]_i_6\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => \v_count_reg[9]_i_10_n_0\,
I1 => counter(18),
I2 => counter(19),
I3 => counter(16),
I4 => counter(17),
O => \v_count_reg[9]_i_6_n_0\
);
\v_count_reg[9]_i_7\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFFFFFF"
)
port map (
I0 => \v_count_reg_reg__0\(3),
I1 => \v_count_reg_reg__0\(1),
I2 => \v_count_reg_reg__0\(0),
I3 => \v_count_reg_reg__0\(2),
I4 => \v_count_reg_reg__0\(4),
O => \v_count_reg[9]_i_7_n_0\
);
\v_count_reg[9]_i_8\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => counter(6),
I1 => counter(15),
O => \v_count_reg[9]_i_8_n_0\
);
\v_count_reg[9]_i_9\: unisim.vcomponents.LUT4
generic map(
INIT => X"FF7F"
)
port map (
I0 => counter(3),
I1 => counter(0),
I2 => \state_reg_n_0_[1]\,
I3 => \state_reg_n_0_[0]\,
O => \v_count_reg[9]_i_9_n_0\
);
\v_count_reg_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \v_count_reg[9]_i_1_n_0\,
D => plusOp(0),
Q => \v_count_reg_reg__0\(0),
R => \counter[31]_i_1_n_0\
);
\v_count_reg_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \v_count_reg[9]_i_1_n_0\,
D => plusOp(1),
Q => \v_count_reg_reg__0\(1),
R => \counter[31]_i_1_n_0\
);
\v_count_reg_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \v_count_reg[9]_i_1_n_0\,
D => plusOp(2),
Q => \v_count_reg_reg__0\(2),
R => \counter[31]_i_1_n_0\
);
\v_count_reg_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \v_count_reg[9]_i_1_n_0\,
D => plusOp(3),
Q => \v_count_reg_reg__0\(3),
R => \counter[31]_i_1_n_0\
);
\v_count_reg_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \v_count_reg[9]_i_1_n_0\,
D => plusOp(4),
Q => \v_count_reg_reg__0\(4),
R => \counter[31]_i_1_n_0\
);
\v_count_reg_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \v_count_reg[9]_i_1_n_0\,
D => plusOp(5),
Q => \v_count_reg_reg__0\(5),
R => \counter[31]_i_1_n_0\
);
\v_count_reg_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \v_count_reg[9]_i_1_n_0\,
D => plusOp(6),
Q => \v_count_reg_reg__0\(6),
R => \counter[31]_i_1_n_0\
);
\v_count_reg_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \v_count_reg[9]_i_1_n_0\,
D => plusOp(7),
Q => \v_count_reg_reg__0\(7),
R => \counter[31]_i_1_n_0\
);
\v_count_reg_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \v_count_reg[9]_i_1_n_0\,
D => plusOp(8),
Q => \v_count_reg_reg__0\(8),
R => \counter[31]_i_1_n_0\
);
\v_count_reg_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \v_count_reg[9]_i_1_n_0\,
D => plusOp(9),
Q => \v_count_reg_reg__0\(9),
R => \counter[31]_i_1_n_0\
);
\xaddr_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \h_count_reg_reg__0\(0),
Q => xaddr(0),
R => '0'
);
\xaddr_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \h_count_reg_reg__0\(1),
Q => xaddr(1),
R => '0'
);
\xaddr_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \h_count_reg_reg__0\(2),
Q => xaddr(2),
R => '0'
);
\xaddr_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \h_count_reg_reg__0\(3),
Q => xaddr(3),
R => '0'
);
\xaddr_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \h_count_reg_reg__0\(4),
Q => xaddr(4),
R => '0'
);
\xaddr_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \h_count_reg_reg__0\(5),
Q => xaddr(5),
R => '0'
);
\xaddr_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \h_count_reg_reg__0\(6),
Q => xaddr(6),
R => '0'
);
\xaddr_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \h_count_reg_reg__0\(7),
Q => xaddr(7),
R => '0'
);
\xaddr_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \h_count_reg_reg__0\(8),
Q => xaddr(8),
R => '0'
);
\xaddr_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \h_count_reg_reg__0\(9),
Q => xaddr(9),
R => '0'
);
\yaddr_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \v_count_reg_reg__0\(0),
Q => yaddr(0),
R => '0'
);
\yaddr_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \v_count_reg_reg__0\(1),
Q => yaddr(1),
R => '0'
);
\yaddr_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \v_count_reg_reg__0\(2),
Q => yaddr(2),
R => '0'
);
\yaddr_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \v_count_reg_reg__0\(3),
Q => yaddr(3),
R => '0'
);
\yaddr_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \v_count_reg_reg__0\(4),
Q => yaddr(4),
R => '0'
);
\yaddr_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \v_count_reg_reg__0\(5),
Q => yaddr(5),
R => '0'
);
\yaddr_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \v_count_reg_reg__0\(6),
Q => yaddr(6),
R => '0'
);
\yaddr_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \v_count_reg_reg__0\(7),
Q => yaddr(7),
R => '0'
);
\yaddr_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \v_count_reg_reg__0\(8),
Q => yaddr(8),
R => '0'
);
\yaddr_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \v_count_reg_reg__0\(9),
Q => yaddr(9),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_vga_sync_ref_0_0 is
port (
clk : in STD_LOGIC;
rst : in STD_LOGIC;
hsync : in STD_LOGIC;
vsync : in STD_LOGIC;
start : out STD_LOGIC;
active : out STD_LOGIC;
xaddr : out STD_LOGIC_VECTOR ( 9 downto 0 );
yaddr : out STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_vga_sync_ref_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_vga_sync_ref_0_0 : entity is "system_vga_sync_ref_0_0,vga_sync_ref,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_vga_sync_ref_0_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_vga_sync_ref_0_0 : entity is "vga_sync_ref,Vivado 2016.4";
end system_vga_sync_ref_0_0;
architecture STRUCTURE of system_vga_sync_ref_0_0 is
begin
U0: entity work.system_vga_sync_ref_0_0_vga_sync_ref
port map (
active => active,
clk => clk,
rst => rst,
start => start,
vsync => vsync,
xaddr(9 downto 0) => xaddr(9 downto 0),
yaddr(9 downto 0) => yaddr(9 downto 0)
);
end STRUCTURE;
| mit |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/test_cdma/test_cdma.srcs/sources_1/bd/system/ip/system_axi_datamover_0_0/synth/system_axi_datamover_0_0.vhd | 1 | 25966 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_datamover:5.1
-- IP Revision: 13
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_datamover_v5_1_13;
USE axi_datamover_v5_1_13.axi_datamover;
ENTITY system_axi_datamover_0_0 IS
PORT (
m_axi_mm2s_aclk : IN STD_LOGIC;
m_axi_mm2s_aresetn : IN STD_LOGIC;
mm2s_err : OUT STD_LOGIC;
m_axis_mm2s_cmdsts_aclk : IN STD_LOGIC;
m_axis_mm2s_cmdsts_aresetn : IN STD_LOGIC;
s_axis_mm2s_cmd_tvalid : IN STD_LOGIC;
s_axis_mm2s_cmd_tready : OUT STD_LOGIC;
s_axis_mm2s_cmd_tdata : IN STD_LOGIC_VECTOR(71 DOWNTO 0);
m_axis_mm2s_sts_tvalid : OUT STD_LOGIC;
m_axis_mm2s_sts_tready : IN STD_LOGIC;
m_axis_mm2s_sts_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_mm2s_sts_tkeep : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_mm2s_sts_tlast : OUT STD_LOGIC;
m_axi_mm2s_arid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_mm2s_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_mm2s_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_mm2s_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_mm2s_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mm2s_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_mm2s_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_mm2s_aruser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_mm2s_arvalid : OUT STD_LOGIC;
m_axi_mm2s_arready : IN STD_LOGIC;
m_axi_mm2s_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_mm2s_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mm2s_rlast : IN STD_LOGIC;
m_axi_mm2s_rvalid : IN STD_LOGIC;
m_axi_mm2s_rready : OUT STD_LOGIC;
m_axis_mm2s_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_mm2s_tkeep : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_mm2s_tlast : OUT STD_LOGIC;
m_axis_mm2s_tvalid : OUT STD_LOGIC;
m_axis_mm2s_tready : IN STD_LOGIC;
m_axi_s2mm_aclk : IN STD_LOGIC;
m_axi_s2mm_aresetn : IN STD_LOGIC;
s2mm_err : OUT STD_LOGIC;
m_axis_s2mm_cmdsts_awclk : IN STD_LOGIC;
m_axis_s2mm_cmdsts_aresetn : IN STD_LOGIC;
s_axis_s2mm_cmd_tvalid : IN STD_LOGIC;
s_axis_s2mm_cmd_tready : OUT STD_LOGIC;
s_axis_s2mm_cmd_tdata : IN STD_LOGIC_VECTOR(71 DOWNTO 0);
m_axis_s2mm_sts_tvalid : OUT STD_LOGIC;
m_axis_s2mm_sts_tready : IN STD_LOGIC;
m_axis_s2mm_sts_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_s2mm_sts_tkeep : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_s2mm_sts_tlast : OUT STD_LOGIC;
m_axi_s2mm_awid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_s2mm_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_s2mm_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_s2mm_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_s2mm_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_s2mm_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_s2mm_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_s2mm_awuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_s2mm_awvalid : OUT STD_LOGIC;
m_axi_s2mm_awready : IN STD_LOGIC;
m_axi_s2mm_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_s2mm_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_s2mm_wlast : OUT STD_LOGIC;
m_axi_s2mm_wvalid : OUT STD_LOGIC;
m_axi_s2mm_wready : IN STD_LOGIC;
m_axi_s2mm_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_s2mm_bvalid : IN STD_LOGIC;
m_axi_s2mm_bready : OUT STD_LOGIC;
s_axis_s2mm_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_s2mm_tkeep : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_s2mm_tlast : IN STD_LOGIC;
s_axis_s2mm_tvalid : IN STD_LOGIC;
s_axis_s2mm_tready : OUT STD_LOGIC
);
END system_axi_datamover_0_0;
ARCHITECTURE system_axi_datamover_0_0_arch OF system_axi_datamover_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_axi_datamover_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_datamover IS
GENERIC (
C_INCLUDE_MM2S : INTEGER;
C_M_AXI_MM2S_ARID : INTEGER;
C_M_AXI_MM2S_ID_WIDTH : INTEGER;
C_M_AXI_MM2S_ADDR_WIDTH : INTEGER;
C_M_AXI_MM2S_DATA_WIDTH : INTEGER;
C_M_AXIS_MM2S_TDATA_WIDTH : INTEGER;
C_INCLUDE_MM2S_STSFIFO : INTEGER;
C_MM2S_STSCMD_FIFO_DEPTH : INTEGER;
C_MM2S_STSCMD_IS_ASYNC : INTEGER;
C_INCLUDE_MM2S_DRE : INTEGER;
C_MM2S_BURST_SIZE : INTEGER;
C_MM2S_BTT_USED : INTEGER;
C_MM2S_ADDR_PIPE_DEPTH : INTEGER;
C_INCLUDE_S2MM : INTEGER;
C_M_AXI_S2MM_AWID : INTEGER;
C_M_AXI_S2MM_ID_WIDTH : INTEGER;
C_M_AXI_S2MM_ADDR_WIDTH : INTEGER;
C_M_AXI_S2MM_DATA_WIDTH : INTEGER;
C_S_AXIS_S2MM_TDATA_WIDTH : INTEGER;
C_INCLUDE_S2MM_STSFIFO : INTEGER;
C_S2MM_STSCMD_FIFO_DEPTH : INTEGER;
C_S2MM_STSCMD_IS_ASYNC : INTEGER;
C_INCLUDE_S2MM_DRE : INTEGER;
C_S2MM_BURST_SIZE : INTEGER;
C_S2MM_BTT_USED : INTEGER;
C_S2MM_SUPPORT_INDET_BTT : INTEGER;
C_S2MM_ADDR_PIPE_DEPTH : INTEGER;
C_FAMILY : STRING;
C_MM2S_INCLUDE_SF : INTEGER;
C_S2MM_INCLUDE_SF : INTEGER;
C_ENABLE_CACHE_USER : INTEGER;
C_ENABLE_MM2S_TKEEP : INTEGER;
C_ENABLE_S2MM_TKEEP : INTEGER;
C_ENABLE_SKID_BUF : STRING;
C_ENABLE_S2MM_ADV_SIG : INTEGER;
C_ENABLE_MM2S_ADV_SIG : INTEGER;
C_CMD_WIDTH : INTEGER
);
PORT (
m_axi_mm2s_aclk : IN STD_LOGIC;
m_axi_mm2s_aresetn : IN STD_LOGIC;
mm2s_halt : IN STD_LOGIC;
mm2s_halt_cmplt : OUT STD_LOGIC;
mm2s_err : OUT STD_LOGIC;
m_axis_mm2s_cmdsts_aclk : IN STD_LOGIC;
m_axis_mm2s_cmdsts_aresetn : IN STD_LOGIC;
s_axis_mm2s_cmd_tvalid : IN STD_LOGIC;
s_axis_mm2s_cmd_tready : OUT STD_LOGIC;
s_axis_mm2s_cmd_tdata : IN STD_LOGIC_VECTOR(71 DOWNTO 0);
m_axis_mm2s_sts_tvalid : OUT STD_LOGIC;
m_axis_mm2s_sts_tready : IN STD_LOGIC;
m_axis_mm2s_sts_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_mm2s_sts_tkeep : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_mm2s_sts_tlast : OUT STD_LOGIC;
mm2s_allow_addr_req : IN STD_LOGIC;
mm2s_addr_req_posted : OUT STD_LOGIC;
mm2s_rd_xfer_cmplt : OUT STD_LOGIC;
m_axi_mm2s_arid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_mm2s_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_mm2s_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_mm2s_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_mm2s_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mm2s_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_mm2s_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_mm2s_aruser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_mm2s_arvalid : OUT STD_LOGIC;
m_axi_mm2s_arready : IN STD_LOGIC;
m_axi_mm2s_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_mm2s_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mm2s_rlast : IN STD_LOGIC;
m_axi_mm2s_rvalid : IN STD_LOGIC;
m_axi_mm2s_rready : OUT STD_LOGIC;
m_axis_mm2s_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_mm2s_tkeep : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_mm2s_tlast : OUT STD_LOGIC;
m_axis_mm2s_tvalid : OUT STD_LOGIC;
m_axis_mm2s_tready : IN STD_LOGIC;
mm2s_dbg_sel : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
mm2s_dbg_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_s2mm_aclk : IN STD_LOGIC;
m_axi_s2mm_aresetn : IN STD_LOGIC;
s2mm_halt : IN STD_LOGIC;
s2mm_halt_cmplt : OUT STD_LOGIC;
s2mm_err : OUT STD_LOGIC;
m_axis_s2mm_cmdsts_awclk : IN STD_LOGIC;
m_axis_s2mm_cmdsts_aresetn : IN STD_LOGIC;
s_axis_s2mm_cmd_tvalid : IN STD_LOGIC;
s_axis_s2mm_cmd_tready : OUT STD_LOGIC;
s_axis_s2mm_cmd_tdata : IN STD_LOGIC_VECTOR(71 DOWNTO 0);
m_axis_s2mm_sts_tvalid : OUT STD_LOGIC;
m_axis_s2mm_sts_tready : IN STD_LOGIC;
m_axis_s2mm_sts_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_s2mm_sts_tkeep : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_s2mm_sts_tlast : OUT STD_LOGIC;
s2mm_allow_addr_req : IN STD_LOGIC;
s2mm_addr_req_posted : OUT STD_LOGIC;
s2mm_wr_xfer_cmplt : OUT STD_LOGIC;
s2mm_ld_nxt_len : OUT STD_LOGIC;
s2mm_wr_len : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_s2mm_awid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_s2mm_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_s2mm_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_s2mm_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_s2mm_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_s2mm_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_s2mm_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_s2mm_awuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_s2mm_awvalid : OUT STD_LOGIC;
m_axi_s2mm_awready : IN STD_LOGIC;
m_axi_s2mm_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_s2mm_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_s2mm_wlast : OUT STD_LOGIC;
m_axi_s2mm_wvalid : OUT STD_LOGIC;
m_axi_s2mm_wready : IN STD_LOGIC;
m_axi_s2mm_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_s2mm_bvalid : IN STD_LOGIC;
m_axi_s2mm_bready : OUT STD_LOGIC;
s_axis_s2mm_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_s2mm_tkeep : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_s2mm_tlast : IN STD_LOGIC;
s_axis_s2mm_tvalid : IN STD_LOGIC;
s_axis_s2mm_tready : OUT STD_LOGIC;
s2mm_dbg_sel : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s2mm_dbg_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT axi_datamover;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF system_axi_datamover_0_0_arch: ARCHITECTURE IS "axi_datamover,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF system_axi_datamover_0_0_arch : ARCHITECTURE IS "system_axi_datamover_0_0,axi_datamover,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF system_axi_datamover_0_0_arch: ARCHITECTURE IS "system_axi_datamover_0_0,axi_datamover,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_datamover,x_ipVersion=5.1,x_ipCoreRevision=13,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_INCLUDE_MM2S=1,C_M_AXI_MM2S_ARID=0,C_M_AXI_MM2S_ID_WIDTH=4,C_M_AXI_MM2S_ADDR_WIDTH=32,C_M_AXI_MM2S_DATA_WIDTH=32,C_M_AXIS_MM2S_TDATA_WIDTH=32,C_INCLUDE_MM2S_STSFIFO=1,C_MM2S_STSCMD_FIFO_DEPTH=4,C_MM2S_STSCMD_IS_ASYNC=1,C_INCLUDE_MM2S_DRE=0,C_MM2S_BURST_SIZE=16,C_MM2S_BTT_USED=16,C_MM2S_ADDR_PIPE" &
"_DEPTH=3,C_INCLUDE_S2MM=1,C_M_AXI_S2MM_AWID=0,C_M_AXI_S2MM_ID_WIDTH=4,C_M_AXI_S2MM_ADDR_WIDTH=32,C_M_AXI_S2MM_DATA_WIDTH=32,C_S_AXIS_S2MM_TDATA_WIDTH=32,C_INCLUDE_S2MM_STSFIFO=1,C_S2MM_STSCMD_FIFO_DEPTH=4,C_S2MM_STSCMD_IS_ASYNC=1,C_INCLUDE_S2MM_DRE=0,C_S2MM_BURST_SIZE=16,C_S2MM_BTT_USED=16,C_S2MM_SUPPORT_INDET_BTT=0,C_S2MM_ADDR_PIPE_DEPTH=4,C_FAMILY=zynq,C_MM2S_INCLUDE_SF=1,C_S2MM_INCLUDE_SF=1,C_ENABLE_CACHE_USER=0,C_ENABLE_MM2S_TKEEP=1,C_ENABLE_S2MM_TKEEP=1,C_ENABLE_SKID_BUF=11111,C_ENABLE_S2MM" &
"_ADV_SIG=0,C_ENABLE_MM2S_ADV_SIG=0,C_CMD_WIDTH=72}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 M_AXI_MM2S_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 M_AXI_MM2S_ARESETN RST";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_cmdsts_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 M_AXIS_MM2S_CMDSTS_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_cmdsts_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 M_AXIS_MM2S_CMDSTS_ARESETN RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_mm2s_cmd_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_MM2S_CMD TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_mm2s_cmd_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_MM2S_CMD TREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_mm2s_cmd_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_MM2S_CMD TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_sts_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S_STS TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_sts_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S_STS TREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_sts_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S_STS TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_sts_tkeep: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S_STS TKEEP";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_sts_tlast: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S_STS TLAST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARLEN";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARSIZE";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARBURST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARPROT";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARCACHE";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_aruser: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARUSER";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RRESP";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RLAST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tkeep: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TKEEP";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tlast: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TLAST";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 M_AXI_S2MM_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 M_AXI_S2MM_ARESETN RST";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_s2mm_cmdsts_awclk: SIGNAL IS "xilinx.com:signal:clock:1.0 M_AXIS_S2MM_CMDSTS_AWCLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_s2mm_cmdsts_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 M_AXIS_S2MM_CMDSTS_ARESETN RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_cmd_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM_CMD TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_cmd_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM_CMD TREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_cmd_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM_CMD TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_s2mm_sts_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_S2MM_STS TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_s2mm_sts_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_S2MM_STS TREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_s2mm_sts_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_S2MM_STS TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_s2mm_sts_tkeep: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_S2MM_STS TKEEP";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_s2mm_sts_tlast: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_S2MM_STS TLAST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWLEN";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWSIZE";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWBURST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWPROT";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWCACHE";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awuser: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWUSER";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WLAST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM BRESP";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM BVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tkeep: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TKEEP";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tlast: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TLAST";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TREADY";
BEGIN
U0 : axi_datamover
GENERIC MAP (
C_INCLUDE_MM2S => 1,
C_M_AXI_MM2S_ARID => 0,
C_M_AXI_MM2S_ID_WIDTH => 4,
C_M_AXI_MM2S_ADDR_WIDTH => 32,
C_M_AXI_MM2S_DATA_WIDTH => 32,
C_M_AXIS_MM2S_TDATA_WIDTH => 32,
C_INCLUDE_MM2S_STSFIFO => 1,
C_MM2S_STSCMD_FIFO_DEPTH => 4,
C_MM2S_STSCMD_IS_ASYNC => 1,
C_INCLUDE_MM2S_DRE => 0,
C_MM2S_BURST_SIZE => 16,
C_MM2S_BTT_USED => 16,
C_MM2S_ADDR_PIPE_DEPTH => 3,
C_INCLUDE_S2MM => 1,
C_M_AXI_S2MM_AWID => 0,
C_M_AXI_S2MM_ID_WIDTH => 4,
C_M_AXI_S2MM_ADDR_WIDTH => 32,
C_M_AXI_S2MM_DATA_WIDTH => 32,
C_S_AXIS_S2MM_TDATA_WIDTH => 32,
C_INCLUDE_S2MM_STSFIFO => 1,
C_S2MM_STSCMD_FIFO_DEPTH => 4,
C_S2MM_STSCMD_IS_ASYNC => 1,
C_INCLUDE_S2MM_DRE => 0,
C_S2MM_BURST_SIZE => 16,
C_S2MM_BTT_USED => 16,
C_S2MM_SUPPORT_INDET_BTT => 0,
C_S2MM_ADDR_PIPE_DEPTH => 4,
C_FAMILY => "zynq",
C_MM2S_INCLUDE_SF => 1,
C_S2MM_INCLUDE_SF => 1,
C_ENABLE_CACHE_USER => 0,
C_ENABLE_MM2S_TKEEP => 1,
C_ENABLE_S2MM_TKEEP => 1,
C_ENABLE_SKID_BUF => "11111",
C_ENABLE_S2MM_ADV_SIG => 0,
C_ENABLE_MM2S_ADV_SIG => 0,
C_CMD_WIDTH => 72
)
PORT MAP (
m_axi_mm2s_aclk => m_axi_mm2s_aclk,
m_axi_mm2s_aresetn => m_axi_mm2s_aresetn,
mm2s_halt => '0',
mm2s_err => mm2s_err,
m_axis_mm2s_cmdsts_aclk => m_axis_mm2s_cmdsts_aclk,
m_axis_mm2s_cmdsts_aresetn => m_axis_mm2s_cmdsts_aresetn,
s_axis_mm2s_cmd_tvalid => s_axis_mm2s_cmd_tvalid,
s_axis_mm2s_cmd_tready => s_axis_mm2s_cmd_tready,
s_axis_mm2s_cmd_tdata => s_axis_mm2s_cmd_tdata,
m_axis_mm2s_sts_tvalid => m_axis_mm2s_sts_tvalid,
m_axis_mm2s_sts_tready => m_axis_mm2s_sts_tready,
m_axis_mm2s_sts_tdata => m_axis_mm2s_sts_tdata,
m_axis_mm2s_sts_tkeep => m_axis_mm2s_sts_tkeep,
m_axis_mm2s_sts_tlast => m_axis_mm2s_sts_tlast,
mm2s_allow_addr_req => '1',
m_axi_mm2s_arid => m_axi_mm2s_arid,
m_axi_mm2s_araddr => m_axi_mm2s_araddr,
m_axi_mm2s_arlen => m_axi_mm2s_arlen,
m_axi_mm2s_arsize => m_axi_mm2s_arsize,
m_axi_mm2s_arburst => m_axi_mm2s_arburst,
m_axi_mm2s_arprot => m_axi_mm2s_arprot,
m_axi_mm2s_arcache => m_axi_mm2s_arcache,
m_axi_mm2s_aruser => m_axi_mm2s_aruser,
m_axi_mm2s_arvalid => m_axi_mm2s_arvalid,
m_axi_mm2s_arready => m_axi_mm2s_arready,
m_axi_mm2s_rdata => m_axi_mm2s_rdata,
m_axi_mm2s_rresp => m_axi_mm2s_rresp,
m_axi_mm2s_rlast => m_axi_mm2s_rlast,
m_axi_mm2s_rvalid => m_axi_mm2s_rvalid,
m_axi_mm2s_rready => m_axi_mm2s_rready,
m_axis_mm2s_tdata => m_axis_mm2s_tdata,
m_axis_mm2s_tkeep => m_axis_mm2s_tkeep,
m_axis_mm2s_tlast => m_axis_mm2s_tlast,
m_axis_mm2s_tvalid => m_axis_mm2s_tvalid,
m_axis_mm2s_tready => m_axis_mm2s_tready,
mm2s_dbg_sel => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
m_axi_s2mm_aclk => m_axi_s2mm_aclk,
m_axi_s2mm_aresetn => m_axi_s2mm_aresetn,
s2mm_halt => '0',
s2mm_err => s2mm_err,
m_axis_s2mm_cmdsts_awclk => m_axis_s2mm_cmdsts_awclk,
m_axis_s2mm_cmdsts_aresetn => m_axis_s2mm_cmdsts_aresetn,
s_axis_s2mm_cmd_tvalid => s_axis_s2mm_cmd_tvalid,
s_axis_s2mm_cmd_tready => s_axis_s2mm_cmd_tready,
s_axis_s2mm_cmd_tdata => s_axis_s2mm_cmd_tdata,
m_axis_s2mm_sts_tvalid => m_axis_s2mm_sts_tvalid,
m_axis_s2mm_sts_tready => m_axis_s2mm_sts_tready,
m_axis_s2mm_sts_tdata => m_axis_s2mm_sts_tdata,
m_axis_s2mm_sts_tkeep => m_axis_s2mm_sts_tkeep,
m_axis_s2mm_sts_tlast => m_axis_s2mm_sts_tlast,
s2mm_allow_addr_req => '1',
m_axi_s2mm_awid => m_axi_s2mm_awid,
m_axi_s2mm_awaddr => m_axi_s2mm_awaddr,
m_axi_s2mm_awlen => m_axi_s2mm_awlen,
m_axi_s2mm_awsize => m_axi_s2mm_awsize,
m_axi_s2mm_awburst => m_axi_s2mm_awburst,
m_axi_s2mm_awprot => m_axi_s2mm_awprot,
m_axi_s2mm_awcache => m_axi_s2mm_awcache,
m_axi_s2mm_awuser => m_axi_s2mm_awuser,
m_axi_s2mm_awvalid => m_axi_s2mm_awvalid,
m_axi_s2mm_awready => m_axi_s2mm_awready,
m_axi_s2mm_wdata => m_axi_s2mm_wdata,
m_axi_s2mm_wstrb => m_axi_s2mm_wstrb,
m_axi_s2mm_wlast => m_axi_s2mm_wlast,
m_axi_s2mm_wvalid => m_axi_s2mm_wvalid,
m_axi_s2mm_wready => m_axi_s2mm_wready,
m_axi_s2mm_bresp => m_axi_s2mm_bresp,
m_axi_s2mm_bvalid => m_axi_s2mm_bvalid,
m_axi_s2mm_bready => m_axi_s2mm_bready,
s_axis_s2mm_tdata => s_axis_s2mm_tdata,
s_axis_s2mm_tkeep => s_axis_s2mm_tkeep,
s_axis_s2mm_tlast => s_axis_s2mm_tlast,
s_axis_s2mm_tvalid => s_axis_s2mm_tvalid,
s_axis_s2mm_tready => s_axis_s2mm_tready,
s2mm_dbg_sel => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4))
);
END system_axi_datamover_0_0_arch;
| mit |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_hdmi_test/zed_hdmi_test.srcs/sources_1/bd/system/ip/system_vga_pll_0_0/system_vga_pll_0_0_sim_netlist.vhdl | 1 | 4327 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Sun May 21 18:47:25 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- c:/ZyboIP/examples/zed_hdmi_test/zed_hdmi_test.srcs/sources_1/bd/system/ip/system_vga_pll_0_0/system_vga_pll_0_0_sim_netlist.vhdl
-- Design : system_vga_pll_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_vga_pll_0_0_vga_pll is
port (
clk_50 : out STD_LOGIC;
clk_25 : out STD_LOGIC;
clk_12_5 : out STD_LOGIC;
clk_6_25 : out STD_LOGIC;
clk_100 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_vga_pll_0_0_vga_pll : entity is "vga_pll";
end system_vga_pll_0_0_vga_pll;
architecture STRUCTURE of system_vga_pll_0_0_vga_pll is
signal \^clk_12_5\ : STD_LOGIC;
signal clk_12_5_s_i_1_n_0 : STD_LOGIC;
signal \^clk_25\ : STD_LOGIC;
signal clk_25_s_i_1_n_0 : STD_LOGIC;
signal \^clk_50\ : STD_LOGIC;
signal \^clk_6_25\ : STD_LOGIC;
signal clk_6_25_s_i_1_n_0 : STD_LOGIC;
signal p_0_in : STD_LOGIC;
begin
clk_12_5 <= \^clk_12_5\;
clk_25 <= \^clk_25\;
clk_50 <= \^clk_50\;
clk_6_25 <= \^clk_6_25\;
clk_12_5_s_i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^clk_12_5\,
O => clk_12_5_s_i_1_n_0
);
clk_12_5_s_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^clk_25\,
CE => '1',
D => clk_12_5_s_i_1_n_0,
Q => \^clk_12_5\,
R => '0'
);
clk_25_s_i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^clk_25\,
O => clk_25_s_i_1_n_0
);
clk_25_s_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^clk_50\,
CE => '1',
D => clk_25_s_i_1_n_0,
Q => \^clk_25\,
R => '0'
);
clk_50_s_i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^clk_50\,
O => p_0_in
);
clk_50_s_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_100,
CE => '1',
D => p_0_in,
Q => \^clk_50\,
R => '0'
);
clk_6_25_s_i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^clk_6_25\,
O => clk_6_25_s_i_1_n_0
);
clk_6_25_s_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^clk_6_25\,
CE => '1',
D => clk_6_25_s_i_1_n_0,
Q => \^clk_6_25\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_vga_pll_0_0 is
port (
clk_100 : in STD_LOGIC;
clk_50 : out STD_LOGIC;
clk_25 : out STD_LOGIC;
clk_12_5 : out STD_LOGIC;
clk_6_25 : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_vga_pll_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_vga_pll_0_0 : entity is "system_vga_pll_0_0,vga_pll,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_vga_pll_0_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_vga_pll_0_0 : entity is "vga_pll,Vivado 2016.4";
end system_vga_pll_0_0;
architecture STRUCTURE of system_vga_pll_0_0 is
begin
U0: entity work.system_vga_pll_0_0_vga_pll
port map (
clk_100 => clk_100,
clk_12_5 => clk_12_5,
clk_25 => clk_25,
clk_50 => clk_50,
clk_6_25 => clk_6_25
);
end STRUCTURE;
| mit |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_camera_hessian/zed_camera_hessian.srcs/sources_1/bd/system/ip/system_vga_nmsuppression_0_0/sim/system_vga_nmsuppression_0_0.vhd | 2 | 4143 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:vga_nmsuppression:1.0
-- IP Revision: 2
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_vga_nmsuppression_0_0 IS
PORT (
clk : IN STD_LOGIC;
enable : IN STD_LOGIC;
active : IN STD_LOGIC;
x_addr_in : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
y_addr_in : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
hessian_in : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
x_addr_out : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
y_addr_out : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
hessian_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END system_vga_nmsuppression_0_0;
ARCHITECTURE system_vga_nmsuppression_0_0_arch OF system_vga_nmsuppression_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_vga_nmsuppression_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT vga_nmsuppression IS
GENERIC (
ROW_WIDTH : INTEGER
);
PORT (
clk : IN STD_LOGIC;
enable : IN STD_LOGIC;
active : IN STD_LOGIC;
x_addr_in : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
y_addr_in : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
hessian_in : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
x_addr_out : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
y_addr_out : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
hessian_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT vga_nmsuppression;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clk CLK";
BEGIN
U0 : vga_nmsuppression
GENERIC MAP (
ROW_WIDTH => 5
)
PORT MAP (
clk => clk,
enable => enable,
active => active,
x_addr_in => x_addr_in,
y_addr_in => y_addr_in,
hessian_in => hessian_in,
x_addr_out => x_addr_out,
y_addr_out => y_addr_out,
hessian_out => hessian_out
);
END system_vga_nmsuppression_0_0_arch;
| mit |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_camera_hessian/zed_camera_hessian.srcs/sources_1/bd/system/ip/system_rgb565_to_rgb888_0_0/system_rgb565_to_rgb888_0_0_stub.vhdl | 3 | 1432 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Thu May 25 15:17:13 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub
-- C:/ZyboIP/examples/zed_camera_test/zed_camera_test.srcs/sources_1/bd/system/ip/system_rgb565_to_rgb888_0_0/system_rgb565_to_rgb888_0_0_stub.vhdl
-- Design : system_rgb565_to_rgb888_0_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity system_rgb565_to_rgb888_0_0 is
Port (
clk : in STD_LOGIC;
rgb_565 : in STD_LOGIC_VECTOR ( 15 downto 0 );
rgb_888 : out STD_LOGIC_VECTOR ( 23 downto 0 )
);
end system_rgb565_to_rgb888_0_0;
architecture stub of system_rgb565_to_rgb888_0_0 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clk,rgb_565[15:0],rgb_888[23:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "rgb565_to_rgb888,Vivado 2016.4";
begin
end;
| mit |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/ov7670_passthrough/ov7670_passthrough.srcs/sources_1/bd/system/ip/system_ov7670_controller_0_0/system_ov7670_controller_0_0_stub.vhdl | 1 | 1560 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Mon Feb 27 15:47:55 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub
-- c:/ZyboIP/examples/ov7670_passthrough/ov7670_passthrough.srcs/sources_1/bd/system/ip/system_ov7670_controller_0_0/system_ov7670_controller_0_0_stub.vhdl
-- Design : system_ov7670_controller_0_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z010clg400-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity system_ov7670_controller_0_0 is
Port (
clk : in STD_LOGIC;
resend : in STD_LOGIC;
config_finished : out STD_LOGIC;
sioc : out STD_LOGIC;
siod : inout STD_LOGIC;
reset : out STD_LOGIC;
pwdn : out STD_LOGIC;
xclk : out STD_LOGIC
);
end system_ov7670_controller_0_0;
architecture stub of system_ov7670_controller_0_0 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clk,resend,config_finished,sioc,siod,reset,pwdn,xclk";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "ov7670_controller,Vivado 2016.4";
begin
end;
| mit |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/affine_transform_demo/affine_transform_demo.srcs/sources_1/bd/system/ip/system_affine_transform_0_1/ip/affine_block_ieee754_fp_multiplier_1_0/sim/affine_block_ieee754_fp_multiplier_1_0.vhd | 2 | 3266 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:ieee754_fp_multiplier:1.0
-- IP Revision: 5
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY affine_block_ieee754_fp_multiplier_1_0 IS
PORT (
x : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
y : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
z : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END affine_block_ieee754_fp_multiplier_1_0;
ARCHITECTURE affine_block_ieee754_fp_multiplier_1_0_arch OF affine_block_ieee754_fp_multiplier_1_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF affine_block_ieee754_fp_multiplier_1_0_arch: ARCHITECTURE IS "yes";
COMPONENT ieee754_fp_multiplier IS
PORT (
x : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
y : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
z : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT ieee754_fp_multiplier;
BEGIN
U0 : ieee754_fp_multiplier
PORT MAP (
x => x,
y => y,
z => z
);
END affine_block_ieee754_fp_multiplier_1_0_arch;
| mit |
SoCdesign/audiomixer | ZedBoard_Linux_Design/hw/xps_proj/pcores/axi_i2s_adi_v1_00_a/hdl/vhdl/user_logic.vhd | 3 | 19765 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
entity user_logic is
generic
(
C_NUM_REG : integer := 12;
C_SLV_DWIDTH : integer := 24;
C_MSB_POS : integer := 0; -- MSB Position in the LRCLK frame (0 - MSB first, 1 - LSB first)
C_FRM_SYNC : integer := 0; -- Frame sync type (0 - 50% Duty Cycle, 1 - Pulse mode)
C_LRCLK_POL : integer := 0; -- LRCLK Polarity (0 - Falling edge, 1 - Rising edge)
C_BCLK_POL : integer := 0 -- BCLK Polarity (0 - Falling edge, 1 - Rising edge)
);
port
(
-- I2S
BCLK_O : out std_logic;
LRCLK_O : out std_logic;
SDATA_I : in std_logic;
SDATA_O : out std_logic;
-- added mem_rd for debugging
MEM_RD_O : out std_logic;
-- AXI4-Lite
Bus2IP_Clk : in std_logic;
Bus2IP_Resetn : in std_logic;
Bus2IP_Data : in std_logic_vector(31 downto 0);
Bus2IP_BE : in std_logic_vector(3 downto 0);
Bus2IP_RdCE : in std_logic_vector(C_NUM_REG-1 downto 0);
Bus2IP_WrCE : in std_logic_vector(C_NUM_REG-1 downto 0);
IP2Bus_Data : out std_logic_vector(31 downto 0);
IP2Bus_RdAck : out std_logic;
IP2Bus_WrAck : out std_logic;
IP2Bus_Error : out std_logic;
-- AXI Streaming interface
S_AXIS_ACLK : in std_logic;
S_AXIS_TREADY : out std_logic;
S_AXIS_TDATA : in std_logic_vector(31 downto 0);
S_AXIS_TLAST : in std_logic;
S_AXIS_TVALID : in std_logic;
M_AXIS_ACLK : in std_logic;
M_AXIS_TREADY : in std_logic;
M_AXIS_TDATA : out std_logic_vector(31 downto 0);
M_AXIS_TLAST : out std_logic;
M_AXIS_TVALID : out std_logic;
M_AXIS_TKEEP : out std_logic_vector(3 downto 0)
);
attribute MAX_FANOUT : string;
attribute SIGIS : string;
attribute SIGIS of S_AXIS_ACLK : signal is "CLK";
attribute SIGIS of Bus2IP_Clk : signal is "CLK";
attribute SIGIS of Bus2IP_Resetn : signal is "RST";
end entity user_logic;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture Behavioral of user_logic is
component i2s_rx_tx is
generic(
C_SLOT_WIDTH : integer := 24;
C_MSB_POS : integer := 0;
C_FRM_SYNC : integer := 0;
C_LRCLK_POL : integer := 0;
C_BCLK_POL : integer := 0
);
port(
CLK_I : in std_logic;
RST_I : in std_logic;
START_TX_I : in std_logic;
START_RX_I : in std_logic;
STOP_RX_I : in std_logic;
DIV_RATE_I : in std_logic_vector(7 downto 0);
LRCLK_RATE_I : in std_logic_vector(7 downto 0);
TX_DATA_I : in std_logic_vector(C_SLOT_WIDTH-1 downto 0);
OE_S_O : out std_logic;
RX_DATA_O : out std_logic_vector(C_SLOT_WIDTH-1 downto 0);
WE_S_O : out std_logic;
BCLK_O : out std_logic;
LRCLK_O : out std_logic;
SDATA_I : in std_logic;
SDATA_O : out std_logic
);
end component;
------------------------------------------
-- Signals for user logic slave model s/w accessible register example
------------------------------------------
signal I2S_RST_I : std_logic;
signal I2S_RST_TX_FIFO : std_logic;
signal I2S_RST_RX_FIFO : std_logic;
signal START_TX_I_int : std_logic;
signal START_RX_I_int : std_logic;
signal OE_S_O_int : std_logic;
signal WE_S_O_int : std_logic;
signal RX_DATA_O_int : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal TX_DATA_I_int : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal mem_rd : std_logic;
signal mem_rd_d1 : std_logic;
signal sample_wr : std_logic;
signal sample_wr_d1 : std_logic;
signal period_cnt : integer range 0 to 65535;
signal period_cnt2 : integer range 0 to 65535;
signal I2S_RESET_REG : std_logic_vector(31 downto 0);
signal I2S_CONTROL_REG : std_logic_vector(31 downto 0);
signal I2S_CLK_CONTROL_REG : std_logic_vector(31 downto 0);
signal I2S_STATUS_REG : std_logic_vector(31 downto 0);
signal DIV_RATE_REG : std_logic_vector(7 downto 0);
signal LRCLK_RATE_REG : std_logic_vector(7 downto 0);
signal I2S_NR_CHAN_REG : std_logic_vector(31 downto 0);
signal PERIOD_CNT_REG : std_logic_vector(31 downto 0);
signal slv_reg7 : std_logic_vector(31 downto 0);
signal slv_reg4 : std_logic_vector(31 downto 0);
signal slv_reg8 : std_logic_vector(31 downto 0);
signal slv_reg9 : std_logic_vector(31 downto 0);
signal I2S_REG10 : std_logic_vector(31 downto 0);
signal I2S_REG11 : std_logic_vector(31 downto 0);
signal slv_reg_write_sel : std_logic_vector(11 downto 0);
signal slv_reg_read_sel : std_logic_vector(11 downto 0);
signal slv_ip2bus_data : std_logic_vector(31 downto 0);
signal slv_read_ack : std_logic;
signal slv_write_ack : std_logic;
-- Audio samples FIFO
constant RAM_ADDR_WIDTH : integer := 7;
type RAM_TYPE is array (0 to (2**RAM_ADDR_WIDTH - 1)) of std_logic_vector(31 downto 0);
-- TX FIFO signals
signal audio_fifo_tx : RAM_TYPE;
signal audio_fifo_tx_wr_addr : integer range 0 to 2**RAM_ADDR_WIDTH-1;
signal audio_fifo_tx_rd_addr : integer range 0 to 2**RAM_ADDR_WIDTH-1;
signal audio_fifo_tx_full : std_logic;
signal audio_fifo_tx_empty : std_logic;
-- RX FIFO signals
signal audio_fifo_rx : RAM_TYPE;
signal audio_fifo_rx_wr_addr : integer range 0 to 2**RAM_ADDR_WIDTH-1;
signal audio_fifo_rx_rd_addr : integer range 0 to 2**RAM_ADDR_WIDTH-1;
signal tvalid : std_logic := '0';
signal rx_tlast : std_logic;
signal drain_tx_dma : std_logic;
begin
drain_process: process (Bus2IP_Clk) is
variable START_TX_I_int_d1 : std_logic;
begin
if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
if Bus2IP_Resetn = '0' then
drain_tx_dma <= '0';
else
if S_AXIS_TLAST = '1' then
drain_tx_dma <= '0';
elsif START_TX_I_int_d1 = '1' and START_TX_I_int = '0' then
drain_tx_dma <= '1';
end if;
START_TX_I_int_d1 := START_TX_I_int;
end if;
end if;
end process;
-- Audio FIFO samples management
-- TX FIFO
S_AXIS_TREADY <= '1' when (audio_fifo_tx_full = '0' or drain_tx_dma = '1') else '0';
mem_rd <= OE_S_O_int;
-- MEM_RD_O for debugging
MEM_RD_O <= mem_rd;
--
AUDIO_FIFO_TX_PROCESS : process(S_AXIS_ACLK) is
variable audio_fifo_free_cnt : integer range 0 to 2**RAM_ADDR_WIDTH;
begin
if(S_AXIS_ACLK'event and S_AXIS_ACLK = '1') then
if(Bus2IP_Resetn = '0') then
audio_fifo_tx_wr_addr <= 0;
audio_fifo_tx_rd_addr <= 0;
audio_fifo_free_cnt := 2**RAM_ADDR_WIDTH;
audio_fifo_tx_full <= '0';
audio_fifo_tx_empty <= '1';
mem_rd_d1 <= '0';
elsif(I2S_RST_TX_FIFO = '1') then
-- Fill TX FIFO with zeros
for i in 0 to (2**RAM_ADDR_WIDTH - 1) loop
audio_fifo_tx(conv_integer(i)) <= (others => '0');
end loop;
-- Reset FIFO counters
audio_fifo_tx_wr_addr <= 0;
audio_fifo_tx_rd_addr <= 0;
audio_fifo_free_cnt := 2**RAM_ADDR_WIDTH;
audio_fifo_tx_full <= '0';
audio_fifo_tx_empty <= '1';
mem_rd_d1 <= '0';
else
mem_rd_d1 <= mem_rd;
if((S_AXIS_TVALID = '1')and(audio_fifo_free_cnt > 0)) then
audio_fifo_tx(audio_fifo_tx_wr_addr) <= S_AXIS_TDATA;
audio_fifo_tx_wr_addr <= audio_fifo_tx_wr_addr + 1;
audio_fifo_free_cnt := audio_fifo_free_cnt - 1;
end if;
if(((mem_rd_d1 = '1')and(mem_rd = '0'))and(audio_fifo_free_cnt < (2**RAM_ADDR_WIDTH))) then
audio_fifo_tx_rd_addr <= audio_fifo_tx_rd_addr + 1;
audio_fifo_free_cnt := audio_fifo_free_cnt + 1;
end if;
if(audio_fifo_free_cnt = 0) then
audio_fifo_tx_full <= '1';
else
audio_fifo_tx_full <= '0';
end if;
if(audio_fifo_free_cnt = 2**RAM_ADDR_WIDTH) then
audio_fifo_tx_empty <= '1';
else
audio_fifo_tx_empty <= '0';
end if;
--TX_DATA_I_int(C_SLV_DWIDTH-1 downto 0) <= audio_fifo_tx(audio_fifo_tx_rd_addr)(C_SLV_DWIDTH-1 downto 0);
TX_DATA_I_int(C_SLV_DWIDTH-1 downto 0) <= audio_fifo_tx(audio_fifo_tx_rd_addr)(31 downto 32-C_SLV_DWIDTH);
end if;
end if;
end process AUDIO_FIFO_TX_PROCESS;
-- RX FIFO
sample_wr <= WE_S_O_int;
AUDIO_FIFO_RX_PROCESS: process(M_AXIS_ACLK) is
variable data_cnt : integer range 0 to 2**RAM_ADDR_WIDTH-1;
begin
if(M_AXIS_ACLK'event and M_AXIS_ACLK = '1') then
if(Bus2IP_Resetn = '0') then
audio_fifo_rx_wr_addr <= 0;
audio_fifo_rx_rd_addr <= 0;
data_cnt := 0;
elsif(I2S_RST_RX_FIFO = '1') then
-- Fill TX FIFO with zeros
for i in 0 to (2**RAM_ADDR_WIDTH - 1) loop
audio_fifo_rx(conv_integer(i)) <= (others => '0');
end loop;
-- Reset FIFO counters
audio_fifo_rx_wr_addr <= 0;
audio_fifo_rx_rd_addr <= 0;
data_cnt := 0;
else
sample_wr_d1 <= sample_wr;
if((sample_wr_d1 = '0')and(sample_wr = '1')) then
audio_fifo_rx(audio_fifo_rx_wr_addr) <= RX_DATA_O_int & "00000000";
--audio_fifo_rx(audio_fifo_rx_wr_addr) <= "0" & RX_DATA_O_int & "0000000";
audio_fifo_rx_wr_addr <= audio_fifo_rx_wr_addr + 1;
if(data_cnt < (2**RAM_ADDR_WIDTH - 1)) then
data_cnt := data_cnt + 1;
end if;
end if;
if((tvalid = '1')and(M_AXIS_TREADY = '1')) then
audio_fifo_rx_rd_addr <= audio_fifo_rx_rd_addr + 1;
data_cnt := data_cnt - 1;
-- Added counter
if(period_cnt2 = 0) then
period_cnt2 <= period_cnt;
rx_tlast <= '1';
else
period_cnt2 <= period_cnt2 - 1;
rx_tlast <= '0';
end if;
end if;
if(data_cnt > 0) then
tvalid <= '1';
else
tvalid <= '0';
end if;
end if;
end if;
end process AUDIO_FIFO_RX_PROCESS;
M_AXIS_TDATA <= audio_fifo_rx(audio_fifo_rx_rd_addr);
M_AXIS_TVALID <= tvalid;
M_AXIS_TLAST <= rx_tlast;
M_AXIS_TKEEP <= "1111";
Inst_I2sCtl: i2s_rx_tx
generic map(
C_SLOT_WIDTH => C_SLV_DWIDTH,
C_MSB_POS => C_MSB_POS,
C_FRM_SYNC => C_FRM_SYNC,
C_LRCLK_POL => C_LRCLK_POL,
C_BCLK_POL => C_BCLK_POL
)
port map(
CLK_I => Bus2IP_Clk,
RST_I => I2S_RST_I,
START_TX_I => START_TX_I_int,
START_RX_I => START_RX_I_int,
STOP_RX_I => rx_tlast,
DIV_RATE_I => DIV_RATE_REG,
LRCLK_RATE_I => LRCLK_RATE_REG,
TX_DATA_I => TX_DATA_I_int,
OE_S_O => OE_S_O_int,
WE_S_O => WE_S_O_int,
RX_DATA_O => RX_DATA_O_int,
BCLK_O => BCLK_O,
LRCLK_O => LRCLK_O,
SDATA_I => SDATA_I,
SDATA_O => SDATA_O
);
------------------------------------------
slv_reg_write_sel <= Bus2IP_WrCE(11 downto 0);
slv_reg_read_sel <= Bus2IP_RdCE(11 downto 0);
slv_write_ack <= Bus2IP_WrCE(0) or Bus2IP_WrCE(1) or Bus2IP_WrCE(2) or Bus2IP_WrCE(3) or Bus2IP_WrCE(4) or Bus2IP_WrCE(5) or Bus2IP_WrCE(6) or Bus2IP_WrCE(7) or Bus2IP_WrCE(8) or Bus2IP_WrCE(9) or Bus2IP_WrCE(10) or Bus2IP_WrCE(11);
slv_read_ack <= Bus2IP_RdCE(0) or Bus2IP_RdCE(1) or Bus2IP_RdCE(2) or Bus2IP_RdCE(3) or Bus2IP_RdCE(4) or Bus2IP_RdCE(5) or Bus2IP_RdCE(6) or Bus2IP_RdCE(7) or Bus2IP_RdCE(8) or Bus2IP_RdCE(9) or Bus2IP_RdCE(10) or Bus2IP_RdCE(11);
I2S_RST_I <= I2S_RESET_REG(0);
I2S_RST_TX_FIFO <= I2S_RESET_REG(1);
I2S_RST_RX_FIFO <= I2S_RESET_REG(2);
START_TX_I_int <= I2S_CONTROL_REG(0);
START_RX_I_int <= I2S_CONTROL_REG(1);
DIV_RATE_REG <= I2S_CLK_CONTROL_REG(7 downto 0);
LRCLK_RATE_REG <= I2S_CLK_CONTROL_REG(23 downto 16);
period_cnt <= conv_integer(PERIOD_CNT_REG);
-- implement slave model software accessible register(s)
SLAVE_REG_WRITE_PROC : process( Bus2IP_Clk ) is
begin
if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
if Bus2IP_Resetn = '0' then
I2S_RESET_REG <= (others => '0');
I2S_CONTROL_REG <= (others => '0');
I2S_CLK_CONTROL_REG <= (others => '0');
I2S_STATUS_REG <= (others => '0');
I2S_NR_CHAN_REG <= (others => '0');
PERIOD_CNT_REG <= (others => '0');
slv_reg7 <= (others => '0');
slv_reg8 <= (others => '0');
slv_reg9 <= (others => '0');
I2S_REG10 <= (others => '0');
I2S_REG11 <= (others => '0');
else
-- Auto-clear the Reset Register bits
I2S_RESET_REG(0) <= '0';
I2S_RESET_REG(1) <= '0';
I2S_RESET_REG(2) <= '0';
case slv_reg_write_sel is
when "100000000000" => -- 0x00 RESET
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
I2S_RESET_REG(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "010000000000" => -- 0x04 CONTROL
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
I2S_CONTROL_REG(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "001000000000" => -- 0x08 CLOCK CONTROL
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
I2S_CLK_CONTROL_REG(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "000100000000" => -- 0x0C RESERVED
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg4(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "000010000000" => -- 0x10 STATUS
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
I2S_STATUS_REG(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "000001000000" => -- 0x14 NR CHANNELS REG
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
I2S_NR_CHAN_REG(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "000000100000" => -- 0x18 PERIOD_CNT_REG
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
PERIOD_CNT_REG(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "000000010000" => -- 0x1C
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg7(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "000000001000" => -- 0x20
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg8(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "000000000100" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg9(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "000000000010" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
I2S_REG10(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "000000000001" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
I2S_REG11(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when others =>
--LRCLK_RATE_REG(31 downto 0) <= RX_DATA_O_int & "00000000";
I2S_STATUS_REG(0) <= OE_S_O_int;
I2S_STATUS_REG(1) <= WE_S_O_int;
I2S_STATUS_REG(2) <= audio_fifo_tx_full;
I2S_STATUS_REG(3) <= audio_fifo_tx_empty;
end case;
end if;
end if;
end process SLAVE_REG_WRITE_PROC;
-- implement slave model software accessible register(s) read mux
SLAVE_REG_READ_PROC : process( slv_reg_read_sel, I2S_RESET_REG, I2S_CONTROL_REG, I2S_STATUS_REG, DIV_RATE_REG, LRCLK_RATE_REG, I2S_NR_CHAN_REG, PERIOD_CNT_REG, slv_reg7, slv_reg8, slv_reg9, I2S_REG10, I2S_REG11 ) is
begin
case slv_reg_read_sel is
when "100000000000" => slv_ip2bus_data <= I2S_RESET_REG;
when "010000000000" => slv_ip2bus_data <= I2S_CONTROL_REG;
when "001000000000" => slv_ip2bus_data <= I2S_CLK_CONTROL_REG;
when "000100000000" => slv_ip2bus_data <= slv_reg4;
when "000010000000" => slv_ip2bus_data <= I2S_STATUS_REG;
when "000001000000" => slv_ip2bus_data <= I2S_NR_CHAN_REG;
when "000000100000" => slv_ip2bus_data <= PERIOD_CNT_REG;
when "000000010000" => slv_ip2bus_data <= slv_reg7;
when "000000001000" => slv_ip2bus_data <= slv_reg8;
when "000000000100" => slv_ip2bus_data <= slv_reg9;
when "000000000010" => slv_ip2bus_data <= I2S_REG10;
when "000000000001" => slv_ip2bus_data <= I2S_REG11;
when others => slv_ip2bus_data <= (others => '0');
end case;
end process SLAVE_REG_READ_PROC;
------------------------------------------
-- Example code to drive IP to Bus signals
------------------------------------------
IP2Bus_Data <= slv_ip2bus_data when slv_read_ack = '1' else
(others => '0');
IP2Bus_WrAck <= slv_write_ack;
IP2Bus_RdAck <= slv_read_ack;
IP2Bus_Error <= '0';
end Behavioral;
| mit |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_camera_test/zed_camera_test.srcs/sources_1/bd/system/ip/system_zed_hdmi_0_0/synth/system_zed_hdmi_0_0.vhd | 6 | 4878 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:zed_hdmi:1.0
-- IP Revision: 11
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_zed_hdmi_0_0 IS
PORT (
clk : IN STD_LOGIC;
clk_x2 : IN STD_LOGIC;
clk_100 : IN STD_LOGIC;
active : IN STD_LOGIC;
hsync : IN STD_LOGIC;
vsync : IN STD_LOGIC;
rgb888 : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
hdmi_clk : OUT STD_LOGIC;
hdmi_hsync : OUT STD_LOGIC;
hdmi_vsync : OUT STD_LOGIC;
hdmi_d : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
hdmi_de : OUT STD_LOGIC;
hdmi_scl : OUT STD_LOGIC;
hdmi_sda : INOUT STD_LOGIC
);
END system_zed_hdmi_0_0;
ARCHITECTURE system_zed_hdmi_0_0_arch OF system_zed_hdmi_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_zed_hdmi_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT zed_hdmi IS
PORT (
clk : IN STD_LOGIC;
clk_x2 : IN STD_LOGIC;
clk_100 : IN STD_LOGIC;
active : IN STD_LOGIC;
hsync : IN STD_LOGIC;
vsync : IN STD_LOGIC;
rgb888 : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
hdmi_clk : OUT STD_LOGIC;
hdmi_hsync : OUT STD_LOGIC;
hdmi_vsync : OUT STD_LOGIC;
hdmi_d : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
hdmi_de : OUT STD_LOGIC;
hdmi_scl : OUT STD_LOGIC;
hdmi_sda : INOUT STD_LOGIC
);
END COMPONENT zed_hdmi;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF system_zed_hdmi_0_0_arch: ARCHITECTURE IS "zed_hdmi,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF system_zed_hdmi_0_0_arch : ARCHITECTURE IS "system_zed_hdmi_0_0,zed_hdmi,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF system_zed_hdmi_0_0_arch: ARCHITECTURE IS "system_zed_hdmi_0_0,zed_hdmi,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=user,x_ipName=zed_hdmi,x_ipVersion=1.0,x_ipCoreRevision=11,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clk CLK";
ATTRIBUTE X_INTERFACE_INFO OF hdmi_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 hdmi_clk CLK";
BEGIN
U0 : zed_hdmi
PORT MAP (
clk => clk,
clk_x2 => clk_x2,
clk_100 => clk_100,
active => active,
hsync => hsync,
vsync => vsync,
rgb888 => rgb888,
hdmi_clk => hdmi_clk,
hdmi_hsync => hdmi_hsync,
hdmi_vsync => hdmi_vsync,
hdmi_d => hdmi_d,
hdmi_de => hdmi_de,
hdmi_scl => hdmi_scl,
hdmi_sda => hdmi_sda
);
END system_zed_hdmi_0_0_arch;
| mit |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_transform_test/zed_transform_test.srcs/sources_1/bd/system/ip/system_vga_feature_transform_0_0/system_vga_feature_transform_0_0_stub.vhdl | 1 | 2304 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Tue Jun 06 01:40:38 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub
-- C:/ZyboIP/examples/zed_transform_test/zed_transform_test.srcs/sources_1/bd/system/ip/system_vga_feature_transform_0_0/system_vga_feature_transform_0_0_stub.vhdl
-- Design : system_vga_feature_transform_0_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity system_vga_feature_transform_0_0 is
Port (
clk : in STD_LOGIC;
clk_x2 : in STD_LOGIC;
rst : in STD_LOGIC;
active : in STD_LOGIC;
vsync : in STD_LOGIC;
x_addr_0 : in STD_LOGIC_VECTOR ( 9 downto 0 );
y_addr_0 : in STD_LOGIC_VECTOR ( 9 downto 0 );
hessian_0 : in STD_LOGIC_VECTOR ( 31 downto 0 );
x_addr_1 : in STD_LOGIC_VECTOR ( 9 downto 0 );
y_addr_1 : in STD_LOGIC_VECTOR ( 9 downto 0 );
hessian_1 : in STD_LOGIC_VECTOR ( 31 downto 0 );
rot_m00 : out STD_LOGIC_VECTOR ( 15 downto 0 );
rot_m01 : out STD_LOGIC_VECTOR ( 15 downto 0 );
rot_m10 : out STD_LOGIC_VECTOR ( 15 downto 0 );
rot_m11 : out STD_LOGIC_VECTOR ( 15 downto 0 );
t_x : out STD_LOGIC_VECTOR ( 9 downto 0 );
t_y : out STD_LOGIC_VECTOR ( 9 downto 0 );
state : out STD_LOGIC_VECTOR ( 1 downto 0 )
);
end system_vga_feature_transform_0_0;
architecture stub of system_vga_feature_transform_0_0 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clk,clk_x2,rst,active,vsync,x_addr_0[9:0],y_addr_0[9:0],hessian_0[31:0],x_addr_1[9:0],y_addr_1[9:0],hessian_1[31:0],rot_m00[15:0],rot_m01[15:0],rot_m10[15:0],rot_m11[15:0],t_x[9:0],t_y[9:0],state[1:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "vga_feature_transform,Vivado 2016.4";
begin
end;
| mit |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | video_ip/zybo_hdmi/zybo_hdmi.srcs/sources_1/new/dvid.vhd | 6 | 3920 | ----------------------------------------------------------------------------------
-- Company: DBRSS
-- Engineer: Daniel Barcklow
-- Module: TOP level DVI-D
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-- Adapted by: Rob Taglang
----------------------------------------------------------------------------------
library IEEE;
library UNISIM;
use IEEE.STD_LOGIC_1164.ALL;
use UNISIM.VCOMPONENTS.ALL;
entity dvid is
port(
clk : in std_logic;
clk_n : in std_logic;
clk_pixel : in std_logic;
red_p : in std_logic_vector(7 downto 0);
green_p : in std_logic_vector(7 downto 0);
blue_p : in std_logic_vector(7 downto 0);
video_on : in std_logic;
hsync : in std_logic;
vsync : in std_logic;
red_serial : out std_logic;
green_serial : out std_logic;
blue_serial : out std_logic;
clock_serial : out std_logic
);
end dvid;
architecture Behavioral of dvid is
signal encoded_red, encoded_green, encoded_blue : std_logic_vector(9 downto 0);
signal shift_red, shift_green, shift_blue : std_logic_vector(9 downto 0) := (others => '0');
signal shift_clock : std_logic_vector(9 downto 0) := "0000011111";
constant c_red : std_logic_vector(1 downto 0) := (others => '0'); -- "00"
constant c_green : std_logic_vector(1 downto 0) := (others => '0'); -- "00"
signal c_blue : std_logic_vector(1 downto 0); -- variable based on vsync and hsync
begin
c_blue <= vsync & hsync;
-- implement TDMS Algorithms for all d_in channels (red, green, blue)
TMDS_encoder_RED : entity work.TMDS_encoder(Behavioral) PORT MAP(clk => clk_pixel, d_in => red_p, c => c_red, video_on => video_on, encoded => encoded_red);
TMDS_encoder_GREEN : entity work.TMDS_encoder(Behavioral) PORT MAP(clk => clk_pixel, d_in => green_p, c => c_green, video_on => video_on, encoded => encoded_green);
TMDS_encoder_BLUE : entity work.TMDS_encoder(Behavioral) PORT MAP(clk => clk_pixel, d_in => blue_p, c => c_blue, video_on => video_on, encoded => encoded_blue);
-- Output at DOUBLE RATE (updated by clock at 125MHz, typically)
ODDR2_RED : ODDR2 generic map( DDR_ALIGNMENT => "C0", INIT => '0', SRTYPE => "ASYNC")
port map (D0 => shift_red(0), D1 => shift_red(1), C0 => clk, C1 => clk_n, CE => '1', R => '0', S => '0', Q => red_serial);
ODDR2_GREEN : ODDR2 generic map( DDR_ALIGNMENT => "C0", INIT => '0', SRTYPE => "ASYNC")
port map (D0 => shift_green(0), D1 => shift_green(1), C0 => clk, C1 => clk_n, CE => '1', R => '0', S => '0', Q => green_serial);
ODDR2_BLUE : ODDR2 generic map( DDR_ALIGNMENT => "C0", INIT => '0', SRTYPE => "ASYNC")
port map (D0 => shift_blue(0), D1 => shift_blue(1), C0 => clk, C1 => clk_n, CE => '1', R => '0', S => '0', Q => blue_serial);
ODDR2_CLK : ODDR2 generic map( DDR_ALIGNMENT => "C0", INIT => '0', SRTYPE => "ASYNC")
port map (D0 => shift_clock(0), D1 => shift_clock(1), C0 => clk, C1 => clk_n, CE => '1', R => '0', S => '0', Q => clock_serial);
feed_data: process(clk)
begin
if rising_edge(clk) then
if shift_clock = "0000011111" then -- occurs at rate of 25MHz
shift_red <= encoded_red;
shift_green <= encoded_green;
shift_blue <= encoded_blue;
else
-- shift last two bits outs
shift_red <= "00" & shift_red (9 downto 2);
shift_green <= "00" & shift_green(9 downto 2);
shift_blue <= "00" & shift_blue (9 downto 2);
end if;
shift_clock <= shift_clock(1 downto 0) & shift_clock(9 downto 2); -- clk (div by 5) ROTATE RIGHT
end if;
end process feed_data;
end Behavioral; | mit |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/video_gaussian_blur/video_gaussian_blur.srcs/sources_1/bd/system/ipshared/xilinx.com/zybo_hdmi_v1_0/dvid.vhd | 6 | 3920 | ----------------------------------------------------------------------------------
-- Company: DBRSS
-- Engineer: Daniel Barcklow
-- Module: TOP level DVI-D
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-- Adapted by: Rob Taglang
----------------------------------------------------------------------------------
library IEEE;
library UNISIM;
use IEEE.STD_LOGIC_1164.ALL;
use UNISIM.VCOMPONENTS.ALL;
entity dvid is
port(
clk : in std_logic;
clk_n : in std_logic;
clk_pixel : in std_logic;
red_p : in std_logic_vector(7 downto 0);
green_p : in std_logic_vector(7 downto 0);
blue_p : in std_logic_vector(7 downto 0);
video_on : in std_logic;
hsync : in std_logic;
vsync : in std_logic;
red_serial : out std_logic;
green_serial : out std_logic;
blue_serial : out std_logic;
clock_serial : out std_logic
);
end dvid;
architecture Behavioral of dvid is
signal encoded_red, encoded_green, encoded_blue : std_logic_vector(9 downto 0);
signal shift_red, shift_green, shift_blue : std_logic_vector(9 downto 0) := (others => '0');
signal shift_clock : std_logic_vector(9 downto 0) := "0000011111";
constant c_red : std_logic_vector(1 downto 0) := (others => '0'); -- "00"
constant c_green : std_logic_vector(1 downto 0) := (others => '0'); -- "00"
signal c_blue : std_logic_vector(1 downto 0); -- variable based on vsync and hsync
begin
c_blue <= vsync & hsync;
-- implement TDMS Algorithms for all d_in channels (red, green, blue)
TMDS_encoder_RED : entity work.TMDS_encoder(Behavioral) PORT MAP(clk => clk_pixel, d_in => red_p, c => c_red, video_on => video_on, encoded => encoded_red);
TMDS_encoder_GREEN : entity work.TMDS_encoder(Behavioral) PORT MAP(clk => clk_pixel, d_in => green_p, c => c_green, video_on => video_on, encoded => encoded_green);
TMDS_encoder_BLUE : entity work.TMDS_encoder(Behavioral) PORT MAP(clk => clk_pixel, d_in => blue_p, c => c_blue, video_on => video_on, encoded => encoded_blue);
-- Output at DOUBLE RATE (updated by clock at 125MHz, typically)
ODDR2_RED : ODDR2 generic map( DDR_ALIGNMENT => "C0", INIT => '0', SRTYPE => "ASYNC")
port map (D0 => shift_red(0), D1 => shift_red(1), C0 => clk, C1 => clk_n, CE => '1', R => '0', S => '0', Q => red_serial);
ODDR2_GREEN : ODDR2 generic map( DDR_ALIGNMENT => "C0", INIT => '0', SRTYPE => "ASYNC")
port map (D0 => shift_green(0), D1 => shift_green(1), C0 => clk, C1 => clk_n, CE => '1', R => '0', S => '0', Q => green_serial);
ODDR2_BLUE : ODDR2 generic map( DDR_ALIGNMENT => "C0", INIT => '0', SRTYPE => "ASYNC")
port map (D0 => shift_blue(0), D1 => shift_blue(1), C0 => clk, C1 => clk_n, CE => '1', R => '0', S => '0', Q => blue_serial);
ODDR2_CLK : ODDR2 generic map( DDR_ALIGNMENT => "C0", INIT => '0', SRTYPE => "ASYNC")
port map (D0 => shift_clock(0), D1 => shift_clock(1), C0 => clk, C1 => clk_n, CE => '1', R => '0', S => '0', Q => clock_serial);
feed_data: process(clk)
begin
if rising_edge(clk) then
if shift_clock = "0000011111" then -- occurs at rate of 25MHz
shift_red <= encoded_red;
shift_green <= encoded_green;
shift_blue <= encoded_blue;
else
-- shift last two bits outs
shift_red <= "00" & shift_red (9 downto 2);
shift_green <= "00" & shift_green(9 downto 2);
shift_blue <= "00" & shift_blue (9 downto 2);
end if;
shift_clock <= shift_clock(1 downto 0) & shift_clock(9 downto 2); -- clk (div by 5) ROTATE RIGHT
end if;
end process feed_data;
end Behavioral; | mit |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_camera_hessian/zed_camera_hessian.srcs/sources_1/bd/system/ip/system_vga_nmsuppression_0_0/system_vga_nmsuppression_0_0_stub.vhdl | 1 | 1766 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Tue May 30 20:23:12 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub -rename_top system_vga_nmsuppression_0_0 -prefix
-- system_vga_nmsuppression_0_0_ system_vga_nmsuppression_0_0_stub.vhdl
-- Design : system_vga_nmsuppression_0_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity system_vga_nmsuppression_0_0 is
Port (
clk : in STD_LOGIC;
enable : in STD_LOGIC;
active : in STD_LOGIC;
x_addr_in : in STD_LOGIC_VECTOR ( 9 downto 0 );
y_addr_in : in STD_LOGIC_VECTOR ( 9 downto 0 );
hessian_in : in STD_LOGIC_VECTOR ( 31 downto 0 );
x_addr_out : out STD_LOGIC_VECTOR ( 9 downto 0 );
y_addr_out : out STD_LOGIC_VECTOR ( 9 downto 0 );
hessian_out : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
end system_vga_nmsuppression_0_0;
architecture stub of system_vga_nmsuppression_0_0 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clk,enable,active,x_addr_in[9:0],y_addr_in[9:0],hessian_in[31:0],x_addr_out[9:0],y_addr_out[9:0],hessian_out[31:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "vga_nmsuppression,Vivado 2016.4";
begin
end;
| mit |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_dual_camera_test/zed_dual_camera_test.srcs/sources_1/bd/system/ip/system_util_vector_logic_0_0/system_util_vector_logic_0_0_stub.vhdl | 1 | 1405 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Thu May 25 15:29:57 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub -rename_top system_util_vector_logic_0_0 -prefix
-- system_util_vector_logic_0_0_ system_util_vector_logic_0_0_stub.vhdl
-- Design : system_util_vector_logic_0_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity system_util_vector_logic_0_0 is
Port (
Op1 : in STD_LOGIC_VECTOR ( 0 to 0 );
Op2 : in STD_LOGIC_VECTOR ( 0 to 0 );
Res : out STD_LOGIC_VECTOR ( 0 to 0 )
);
end system_util_vector_logic_0_0;
architecture stub of system_util_vector_logic_0_0 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "Op1[0:0],Op2[0:0],Res[0:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "util_vector_logic,Vivado 2016.4";
begin
end;
| mit |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/ov7670_fusion/ov7670_fusion.srcs/sources_1/bd/system/ip/system_zybo_hdmi_0_0/system_zybo_hdmi_0_0_sim_netlist.vhdl | 1 | 129288 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Wed Mar 01 09:54:28 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- C:/ZyboIP/examples/ov7670_fusion/ov7670_fusion.srcs/sources_1/bd/system/ip/system_zybo_hdmi_0_0/system_zybo_hdmi_0_0_sim_netlist.vhdl
-- Design : system_zybo_hdmi_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z010clg400-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_zybo_hdmi_0_0_TMDS_encoder is
port (
SR : out STD_LOGIC_VECTOR ( 0 to 0 );
D : out STD_LOGIC_VECTOR ( 7 downto 0 );
Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
rgb : in STD_LOGIC_VECTOR ( 7 downto 0 );
active : in STD_LOGIC;
hsync : in STD_LOGIC;
vsync : in STD_LOGIC;
shift_blue : in STD_LOGIC_VECTOR ( 7 downto 0 );
\shift_clock_reg[5]\ : in STD_LOGIC;
clk_25 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_zybo_hdmi_0_0_TMDS_encoder : entity is "TMDS_encoder";
end system_zybo_hdmi_0_0_TMDS_encoder;
architecture STRUCTURE of system_zybo_hdmi_0_0_TMDS_encoder is
signal \^sr\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \dc_bias[0]_i_1__1_n_0\ : STD_LOGIC;
signal \dc_bias[0]_i_2__1_n_0\ : STD_LOGIC;
signal \dc_bias[0]_i_3__1_n_0\ : STD_LOGIC;
signal \dc_bias[0]_i_4__1_n_0\ : STD_LOGIC;
signal \dc_bias[0]_i_5__0_n_0\ : STD_LOGIC;
signal \dc_bias[1]_i_1__0_n_0\ : STD_LOGIC;
signal \dc_bias[1]_i_2__1_n_0\ : STD_LOGIC;
signal \dc_bias[1]_i_3__1_n_0\ : STD_LOGIC;
signal \dc_bias[1]_i_4__1_n_0\ : STD_LOGIC;
signal \dc_bias[1]_i_5__1_n_0\ : STD_LOGIC;
signal \dc_bias[1]_i_6__0_n_0\ : STD_LOGIC;
signal \dc_bias[1]_i_7__1_n_0\ : STD_LOGIC;
signal \dc_bias[1]_i_8_n_0\ : STD_LOGIC;
signal \dc_bias[1]_i_9__0_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_10_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_11__1_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_12__0_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_13__0_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_14__0_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_15__0_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_1__1_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_2__0_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_3__1_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_4__1_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_5__1_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_6__1_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_7__0_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_8__1_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_9__0_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_10__1_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_11__1_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_12__1_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_13__0_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_14__0_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_15__1_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_16__0_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_17__0_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_18__0_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_19__1_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_1__1_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_20__0_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_21_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_22__1_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_23__0_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_24__1_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_25__1_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_26__1_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_27__1_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_28__0_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_29__0_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_2__1_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_30__0_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_31__0_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_32__0_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_33__0_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_3__1_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_4__1_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_5_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_6__1_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_7__1_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_8__1_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_9__1_n_0\ : STD_LOGIC;
signal \dc_bias_reg_n_0_[0]\ : STD_LOGIC;
signal \dc_bias_reg_n_0_[1]\ : STD_LOGIC;
signal \dc_bias_reg_n_0_[2]\ : STD_LOGIC;
signal \encoded[0]_i_1__1_n_0\ : STD_LOGIC;
signal \encoded[1]_i_1__1_n_0\ : STD_LOGIC;
signal \encoded[1]_i_2_n_0\ : STD_LOGIC;
signal \encoded[2]_i_1__1_n_0\ : STD_LOGIC;
signal \encoded[2]_i_2_n_0\ : STD_LOGIC;
signal \encoded[3]_i_1__1_n_0\ : STD_LOGIC;
signal \encoded[3]_i_2_n_0\ : STD_LOGIC;
signal \encoded[4]_i_1__1_n_0\ : STD_LOGIC;
signal \encoded[4]_i_2_n_0\ : STD_LOGIC;
signal \encoded[5]_i_1__1_n_0\ : STD_LOGIC;
signal \encoded[5]_i_2_n_0\ : STD_LOGIC;
signal \encoded[6]_i_1__1_n_0\ : STD_LOGIC;
signal \encoded[6]_i_2__1_n_0\ : STD_LOGIC;
signal \encoded[7]_i_1__1_n_0\ : STD_LOGIC;
signal \encoded[7]_i_2__1_n_0\ : STD_LOGIC;
signal \encoded[8]_i_1__1_n_0\ : STD_LOGIC;
signal \encoded[9]_i_1__1_n_0\ : STD_LOGIC;
signal \encoded_reg_n_0_[0]\ : STD_LOGIC;
signal \encoded_reg_n_0_[1]\ : STD_LOGIC;
signal \encoded_reg_n_0_[2]\ : STD_LOGIC;
signal \encoded_reg_n_0_[3]\ : STD_LOGIC;
signal \encoded_reg_n_0_[4]\ : STD_LOGIC;
signal \encoded_reg_n_0_[5]\ : STD_LOGIC;
signal \encoded_reg_n_0_[6]\ : STD_LOGIC;
signal \encoded_reg_n_0_[7]\ : STD_LOGIC;
signal p_1_in : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \dc_bias[0]_i_3__1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \dc_bias[0]_i_4__1\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \dc_bias[1]_i_3__1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \dc_bias[1]_i_4__1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \dc_bias[1]_i_6__0\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \dc_bias[1]_i_7__1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \dc_bias[1]_i_9__0\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \dc_bias[2]_i_11__1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \dc_bias[2]_i_14__0\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \dc_bias[2]_i_15__0\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \dc_bias[2]_i_7__0\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \dc_bias[2]_i_9__0\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \dc_bias[3]_i_11__1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \dc_bias[3]_i_16__0\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \dc_bias[3]_i_19__1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \dc_bias[3]_i_26__1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \dc_bias[3]_i_29__0\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \encoded[1]_i_2\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \encoded[2]_i_2\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \encoded[3]_i_2\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \encoded[4]_i_2\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \encoded[6]_i_2__1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \encoded[7]_i_2__1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \encoded[8]_i_1__1\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \shift_blue[0]_i_1\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \shift_blue[1]_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \shift_blue[2]_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \shift_blue[3]_i_1\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \shift_blue[4]_i_1\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \shift_blue[5]_i_1\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \shift_blue[6]_i_1\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \shift_blue[7]_i_1\ : label is "soft_lutpair11";
begin
SR(0) <= \^sr\(0);
\dc_bias[0]_i_1__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"9F90909F909F9F90"
)
port map (
I0 => \dc_bias_reg_n_0_[0]\,
I1 => \dc_bias[0]_i_2__1_n_0\,
I2 => \dc_bias[3]_i_5_n_0\,
I3 => \dc_bias[2]_i_2__0_n_0\,
I4 => \dc_bias[0]_i_3__1_n_0\,
I5 => \dc_bias[0]_i_4__1_n_0\,
O => \dc_bias[0]_i_1__1_n_0\
);
\dc_bias[0]_i_2__1\: unisim.vcomponents.LUT5
generic map(
INIT => X"69969669"
)
port map (
I0 => \dc_bias[3]_i_3__1_n_0\,
I1 => \encoded[7]_i_2__1_n_0\,
I2 => \dc_bias[0]_i_5__0_n_0\,
I3 => rgb(1),
I4 => rgb(3),
O => \dc_bias[0]_i_2__1_n_0\
);
\dc_bias[0]_i_3__1\: unisim.vcomponents.LUT5
generic map(
INIT => X"69969669"
)
port map (
I0 => \encoded[3]_i_2_n_0\,
I1 => rgb(5),
I2 => rgb(0),
I3 => \dc_bias_reg_n_0_[0]\,
I4 => rgb(7),
O => \dc_bias[0]_i_3__1_n_0\
);
\dc_bias[0]_i_4__1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb(2),
I1 => \dc_bias[3]_i_3__1_n_0\,
O => \dc_bias[0]_i_4__1_n_0\
);
\dc_bias[0]_i_5__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"6696969999696966"
)
port map (
I0 => rgb(6),
I1 => rgb(4),
I2 => \dc_bias[2]_i_13__0_n_0\,
I3 => \dc_bias[3]_i_13__0_n_0\,
I4 => \dc_bias[2]_i_12__0_n_0\,
I5 => \encoded[3]_i_2_n_0\,
O => \dc_bias[0]_i_5__0_n_0\
);
\dc_bias[1]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"C5C0CFCACFCAC5C0"
)
port map (
I0 => \dc_bias[2]_i_2__0_n_0\,
I1 => \dc_bias[1]_i_2__1_n_0\,
I2 => \dc_bias[3]_i_5_n_0\,
I3 => \dc_bias[1]_i_3__1_n_0\,
I4 => \dc_bias[1]_i_4__1_n_0\,
I5 => \dc_bias[1]_i_5__1_n_0\,
O => \dc_bias[1]_i_1__0_n_0\
);
\dc_bias[1]_i_2__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6F60606F606F6F60"
)
port map (
I0 => \dc_bias[1]_i_6__0_n_0\,
I1 => \dc_bias[1]_i_7__1_n_0\,
I2 => \dc_bias[3]_i_3__1_n_0\,
I3 => \dc_bias[1]_i_8_n_0\,
I4 => \dc_bias[1]_i_9__0_n_0\,
I5 => \dc_bias[3]_i_17__0_n_0\,
O => \dc_bias[1]_i_2__1_n_0\
);
\dc_bias[1]_i_3__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"5695"
)
port map (
I0 => \dc_bias[1]_i_7__1_n_0\,
I1 => \dc_bias[0]_i_2__1_n_0\,
I2 => \dc_bias_reg_n_0_[0]\,
I3 => \dc_bias[3]_i_3__1_n_0\,
O => \dc_bias[1]_i_3__1_n_0\
);
\dc_bias[1]_i_4__1\: unisim.vcomponents.LUT5
generic map(
INIT => X"D7BE2841"
)
port map (
I0 => rgb(2),
I1 => rgb(1),
I2 => rgb(0),
I3 => \dc_bias[3]_i_3__1_n_0\,
I4 => \dc_bias[2]_i_10_n_0\,
O => \dc_bias[1]_i_4__1_n_0\
);
\dc_bias[1]_i_5__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"EB7D7DEB7D14147D"
)
port map (
I0 => rgb(7),
I1 => \dc_bias_reg_n_0_[0]\,
I2 => rgb(0),
I3 => rgb(5),
I4 => \encoded[3]_i_2_n_0\,
I5 => \dc_bias[0]_i_4__1_n_0\,
O => \dc_bias[1]_i_5__1_n_0\
);
\dc_bias[1]_i_6__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \dc_bias_reg_n_0_[0]\,
I1 => \dc_bias[0]_i_2__1_n_0\,
O => \dc_bias[1]_i_6__0_n_0\
);
\dc_bias[1]_i_7__1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \dc_bias_reg_n_0_[1]\,
I1 => \dc_bias[3]_i_25__1_n_0\,
O => \dc_bias[1]_i_7__1_n_0\
);
\dc_bias[1]_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"14D782BE82BE14D7"
)
port map (
I0 => rgb(0),
I1 => \dc_bias_reg_n_0_[0]\,
I2 => \dc_bias[3]_i_31__0_n_0\,
I3 => \dc_bias[0]_i_5__0_n_0\,
I4 => rgb(3),
I5 => rgb(1),
O => \dc_bias[1]_i_8_n_0\
);
\dc_bias[1]_i_9__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"6A56566A"
)
port map (
I0 => \dc_bias_reg_n_0_[1]\,
I1 => rgb(0),
I2 => \dc_bias_reg_n_0_[0]\,
I3 => \dc_bias[3]_i_3__1_n_0\,
I4 => \encoded[7]_i_2__1_n_0\,
O => \dc_bias[1]_i_9__0_n_0\
);
\dc_bias[2]_i_10\: unisim.vcomponents.LUT6
generic map(
INIT => X"9A5965A665A69A59"
)
port map (
I0 => \dc_bias[2]_i_8__1_n_0\,
I1 => \dc_bias[3]_i_3__1_n_0\,
I2 => rgb(7),
I3 => \encoded[6]_i_2__1_n_0\,
I4 => \dc_bias_reg_n_0_[1]\,
I5 => \dc_bias[2]_i_14__0_n_0\,
O => \dc_bias[2]_i_10_n_0\
);
\dc_bias[2]_i_11__1\: unisim.vcomponents.LUT5
generic map(
INIT => X"82EBEB82"
)
port map (
I0 => rgb(7),
I1 => \dc_bias_reg_n_0_[0]\,
I2 => rgb(0),
I3 => rgb(5),
I4 => \encoded[3]_i_2_n_0\,
O => \dc_bias[2]_i_11__1_n_0\
);
\dc_bias[2]_i_12__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"022BBFFF"
)
port map (
I0 => \dc_bias[2]_i_15__0_n_0\,
I1 => rgb(0),
I2 => rgb(7),
I3 => \dc_bias[3]_i_29__0_n_0\,
I4 => \dc_bias[3]_i_12__1_n_0\,
O => \dc_bias[2]_i_12__0_n_0\
);
\dc_bias[2]_i_13__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"79E9EF7FFFFFFFFF"
)
port map (
I0 => rgb(7),
I1 => \dc_bias[3]_i_29__0_n_0\,
I2 => \encoded[3]_i_2_n_0\,
I3 => \dc_bias[2]_i_15__0_n_0\,
I4 => \dc_bias[3]_i_12__1_n_0\,
I5 => rgb(0),
O => \dc_bias[2]_i_13__0_n_0\
);
\dc_bias[2]_i_14__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => rgb(0),
I1 => \dc_bias_reg_n_0_[0]\,
O => \dc_bias[2]_i_14__0_n_0\
);
\dc_bias[2]_i_15__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => rgb(3),
I1 => rgb(2),
I2 => rgb(1),
O => \dc_bias[2]_i_15__0_n_0\
);
\dc_bias[2]_i_1__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"C5C0CFCACFCAC5C0"
)
port map (
I0 => \dc_bias[2]_i_2__0_n_0\,
I1 => \dc_bias[2]_i_3__1_n_0\,
I2 => \dc_bias[3]_i_5_n_0\,
I3 => \dc_bias[2]_i_4__1_n_0\,
I4 => \dc_bias[2]_i_5__1_n_0\,
I5 => \dc_bias[2]_i_6__1_n_0\,
O => \dc_bias[2]_i_1__1_n_0\
);
\dc_bias[2]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"999999A999A9AAAA"
)
port map (
I0 => p_1_in,
I1 => \dc_bias[3]_i_21_n_0\,
I2 => \dc_bias[3]_i_20__0_n_0\,
I3 => \dc_bias[3]_i_19__1_n_0\,
I4 => \dc_bias[3]_i_18__0_n_0\,
I5 => \dc_bias[3]_i_17__0_n_0\,
O => \dc_bias[2]_i_2__0_n_0\
);
\dc_bias[2]_i_3__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6699A5A566995A5A"
)
port map (
I0 => \dc_bias_reg_n_0_[2]\,
I1 => \dc_bias[3]_i_14__0_n_0\,
I2 => \dc_bias[3]_i_9__1_n_0\,
I3 => \dc_bias[3]_i_15__1_n_0\,
I4 => \dc_bias[3]_i_3__1_n_0\,
I5 => \dc_bias[3]_i_8__1_n_0\,
O => \dc_bias[2]_i_3__1_n_0\
);
\dc_bias[2]_i_4__1\: unisim.vcomponents.LUT5
generic map(
INIT => X"4BB4B44B"
)
port map (
I0 => \dc_bias[3]_i_25__1_n_0\,
I1 => \dc_bias_reg_n_0_[1]\,
I2 => \dc_bias_reg_n_0_[2]\,
I3 => \dc_bias[3]_i_14__0_n_0\,
I4 => \dc_bias[3]_i_26__1_n_0\,
O => \dc_bias[2]_i_4__1_n_0\
);
\dc_bias[2]_i_5__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"75F710518A08EFAE"
)
port map (
I0 => \dc_bias[2]_i_7__0_n_0\,
I1 => \dc_bias[3]_i_3__1_n_0\,
I2 => rgb(7),
I3 => \encoded[6]_i_2__1_n_0\,
I4 => \dc_bias[2]_i_8__1_n_0\,
I5 => \dc_bias[2]_i_9__0_n_0\,
O => \dc_bias[2]_i_5__1_n_0\
);
\dc_bias[2]_i_6__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"177E777777777E17"
)
port map (
I0 => \dc_bias[2]_i_10_n_0\,
I1 => \dc_bias[2]_i_11__1_n_0\,
I2 => \dc_bias[0]_i_3__1_n_0\,
I3 => \encoded[1]_i_2_n_0\,
I4 => \dc_bias[3]_i_3__1_n_0\,
I5 => rgb(2),
O => \dc_bias[2]_i_6__1_n_0\
);
\dc_bias[2]_i_7__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => \dc_bias_reg_n_0_[1]\,
I1 => \dc_bias_reg_n_0_[0]\,
I2 => rgb(0),
O => \dc_bias[2]_i_7__0_n_0\
);
\dc_bias[2]_i_8__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"2DB4B4B42D2D2DB4"
)
port map (
I0 => rgb(4),
I1 => rgb(5),
I2 => \encoded[3]_i_2_n_0\,
I3 => \dc_bias[2]_i_12__0_n_0\,
I4 => \dc_bias[3]_i_13__0_n_0\,
I5 => \dc_bias[2]_i_13__0_n_0\,
O => \dc_bias[2]_i_8__1_n_0\
);
\dc_bias[2]_i_9__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"AA95"
)
port map (
I0 => \dc_bias_reg_n_0_[2]\,
I1 => rgb(0),
I2 => \dc_bias_reg_n_0_[0]\,
I3 => \dc_bias_reg_n_0_[1]\,
O => \dc_bias[2]_i_9__0_n_0\
);
\dc_bias[3]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => active,
O => \^sr\(0)
);
\dc_bias[3]_i_10__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"69FFFF69FF6969FF"
)
port map (
I0 => rgb(1),
I1 => rgb(2),
I2 => rgb(3),
I3 => rgb(0),
I4 => rgb(7),
I5 => \dc_bias[3]_i_29__0_n_0\,
O => \dc_bias[3]_i_10__1_n_0\
);
\dc_bias[3]_i_11__1\: unisim.vcomponents.LUT5
generic map(
INIT => X"17717117"
)
port map (
I0 => rgb(0),
I1 => rgb(7),
I2 => rgb(6),
I3 => rgb(5),
I4 => rgb(4),
O => \dc_bias[3]_i_11__1_n_0\
);
\dc_bias[3]_i_12__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"171717E817E8E8E8"
)
port map (
I0 => rgb(3),
I1 => rgb(2),
I2 => rgb(1),
I3 => rgb(5),
I4 => rgb(4),
I5 => rgb(6),
O => \dc_bias[3]_i_12__1_n_0\
);
\dc_bias[3]_i_13__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"171717FF17FFFFFF"
)
port map (
I0 => rgb(3),
I1 => rgb(2),
I2 => rgb(1),
I3 => rgb(5),
I4 => rgb(4),
I5 => rgb(6),
O => \dc_bias[3]_i_13__0_n_0\
);
\dc_bias[3]_i_14__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"4DDD444D444D2444"
)
port map (
I0 => \dc_bias[3]_i_28__0_n_0\,
I1 => \dc_bias[3]_i_30__0_n_0\,
I2 => \dc_bias[0]_i_5__0_n_0\,
I3 => rgb(0),
I4 => \dc_bias[3]_i_31__0_n_0\,
I5 => \dc_bias[3]_i_19__1_n_0\,
O => \dc_bias[3]_i_14__0_n_0\
);
\dc_bias[3]_i_15__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"ECFE8FC88FC8ECFE"
)
port map (
I0 => \dc_bias_reg_n_0_[0]\,
I1 => \dc_bias_reg_n_0_[1]\,
I2 => \dc_bias[3]_i_19__1_n_0\,
I3 => \dc_bias[3]_i_20__0_n_0\,
I4 => \dc_bias[3]_i_18__0_n_0\,
I5 => \dc_bias[3]_i_17__0_n_0\,
O => \dc_bias[3]_i_15__1_n_0\
);
\dc_bias[3]_i_16__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => \dc_bias_reg_n_0_[1]\,
I1 => \dc_bias_reg_n_0_[2]\,
I2 => \dc_bias_reg_n_0_[0]\,
I3 => p_1_in,
O => \dc_bias[3]_i_16__0_n_0\
);
\dc_bias[3]_i_17__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"D22D4BB42DD2B44B"
)
port map (
I0 => rgb(3),
I1 => rgb(2),
I2 => rgb(1),
I3 => rgb(0),
I4 => \dc_bias[3]_i_3__1_n_0\,
I5 => \dc_bias[3]_i_28__0_n_0\,
O => \dc_bias[3]_i_17__0_n_0\
);
\dc_bias[3]_i_18__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"1D8B8B1D8B1D1D8B"
)
port map (
I0 => \dc_bias[3]_i_3__1_n_0\,
I1 => \encoded[7]_i_2__1_n_0\,
I2 => rgb(0),
I3 => rgb(6),
I4 => rgb(4),
I5 => \encoded[3]_i_2_n_0\,
O => \dc_bias[3]_i_18__0_n_0\
);
\dc_bias[3]_i_19__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => rgb(3),
I1 => rgb(1),
I2 => rgb(0),
O => \dc_bias[3]_i_19__1_n_0\
);
\dc_bias[3]_i_1__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"1DFF1D001DFF1DFF"
)
port map (
I0 => \dc_bias[3]_i_2__1_n_0\,
I1 => \dc_bias[3]_i_3__1_n_0\,
I2 => \dc_bias[3]_i_4__1_n_0\,
I3 => \dc_bias[3]_i_5_n_0\,
I4 => \dc_bias[3]_i_6__1_n_0\,
I5 => \dc_bias[3]_i_7__1_n_0\,
O => \dc_bias[3]_i_1__1_n_0\
);
\dc_bias[3]_i_20__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"69969669"
)
port map (
I0 => \encoded[3]_i_2_n_0\,
I1 => rgb(4),
I2 => rgb(6),
I3 => \encoded[7]_i_2__1_n_0\,
I4 => rgb(0),
O => \dc_bias[3]_i_20__0_n_0\
);
\dc_bias[3]_i_21\: unisim.vcomponents.LUT6
generic map(
INIT => X"A20808A2208A8A20"
)
port map (
I0 => \dc_bias[3]_i_28__0_n_0\,
I1 => rgb(3),
I2 => rgb(2),
I3 => rgb(1),
I4 => rgb(0),
I5 => \dc_bias[3]_i_3__1_n_0\,
O => \dc_bias[3]_i_21_n_0\
);
\dc_bias[3]_i_22__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"BBBABA22BA22BA22"
)
port map (
I0 => \dc_bias_reg_n_0_[2]\,
I1 => \dc_bias[3]_i_32__0_n_0\,
I2 => \dc_bias[3]_i_33__0_n_0\,
I3 => \dc_bias_reg_n_0_[1]\,
I4 => \dc_bias_reg_n_0_[0]\,
I5 => rgb(0),
O => \dc_bias[3]_i_22__1_n_0\
);
\dc_bias[3]_i_23__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFEFFFFEF"
)
port map (
I0 => \dc_bias[2]_i_10_n_0\,
I1 => \dc_bias[0]_i_3__1_n_0\,
I2 => \encoded[1]_i_2_n_0\,
I3 => \dc_bias[3]_i_3__1_n_0\,
I4 => rgb(2),
I5 => \dc_bias[2]_i_11__1_n_0\,
O => \dc_bias[3]_i_23__0_n_0\
);
\dc_bias[3]_i_24__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFE7810081000000"
)
port map (
I0 => rgb(2),
I1 => \dc_bias[3]_i_3__1_n_0\,
I2 => \encoded[1]_i_2_n_0\,
I3 => \dc_bias[0]_i_3__1_n_0\,
I4 => \dc_bias[2]_i_11__1_n_0\,
I5 => \dc_bias[2]_i_10_n_0\,
O => \dc_bias[3]_i_24__1_n_0\
);
\dc_bias[3]_i_25__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"188EE771E771188E"
)
port map (
I0 => \dc_bias[3]_i_19__1_n_0\,
I1 => \dc_bias[3]_i_31__0_n_0\,
I2 => rgb(0),
I3 => \dc_bias[0]_i_5__0_n_0\,
I4 => \dc_bias[3]_i_30__0_n_0\,
I5 => \dc_bias[3]_i_28__0_n_0\,
O => \dc_bias[3]_i_25__1_n_0\
);
\dc_bias[3]_i_26__1\: unisim.vcomponents.LUT5
generic map(
INIT => X"9990F999"
)
port map (
I0 => \dc_bias_reg_n_0_[1]\,
I1 => \dc_bias[3]_i_25__1_n_0\,
I2 => \dc_bias_reg_n_0_[0]\,
I3 => \dc_bias[0]_i_2__1_n_0\,
I4 => \dc_bias[3]_i_3__1_n_0\,
O => \dc_bias[3]_i_26__1_n_0\
);
\dc_bias[3]_i_27__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AA696955559696AA"
)
port map (
I0 => \dc_bias[3]_i_28__0_n_0\,
I1 => \encoded[7]_i_2__1_n_0\,
I2 => \dc_bias[3]_i_3__1_n_0\,
I3 => \dc_bias_reg_n_0_[0]\,
I4 => rgb(0),
I5 => \dc_bias_reg_n_0_[1]\,
O => \dc_bias[3]_i_27__1_n_0\
);
\dc_bias[3]_i_28__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"28882228BEEEBBBE"
)
port map (
I0 => \encoded[4]_i_2_n_0\,
I1 => \encoded[5]_i_2_n_0\,
I2 => \dc_bias[2]_i_12__0_n_0\,
I3 => \dc_bias[3]_i_13__0_n_0\,
I4 => \dc_bias[2]_i_13__0_n_0\,
I5 => \encoded[6]_i_2__1_n_0\,
O => \dc_bias[3]_i_28__0_n_0\
);
\dc_bias[3]_i_29__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => rgb(6),
I1 => rgb(5),
I2 => rgb(4),
O => \dc_bias[3]_i_29__0_n_0\
);
\dc_bias[3]_i_2__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"24DB"
)
port map (
I0 => \dc_bias[3]_i_8__1_n_0\,
I1 => \dc_bias[3]_i_9__1_n_0\,
I2 => \dc_bias_reg_n_0_[2]\,
I3 => p_1_in,
O => \dc_bias[3]_i_2__1_n_0\
);
\dc_bias[3]_i_30__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"2BD400FFFF002BD4"
)
port map (
I0 => \dc_bias[2]_i_13__0_n_0\,
I1 => \dc_bias[3]_i_13__0_n_0\,
I2 => \dc_bias[2]_i_12__0_n_0\,
I3 => \encoded[1]_i_2_n_0\,
I4 => rgb(2),
I5 => rgb(3),
O => \dc_bias[3]_i_30__0_n_0\
);
\dc_bias[3]_i_31__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"55F5F5FFAE8A8A08"
)
port map (
I0 => \dc_bias[3]_i_13__0_n_0\,
I1 => rgb(0),
I2 => \dc_bias[3]_i_12__1_n_0\,
I3 => \dc_bias[3]_i_11__1_n_0\,
I4 => \dc_bias[3]_i_10__1_n_0\,
I5 => \encoded[7]_i_2__1_n_0\,
O => \dc_bias[3]_i_31__0_n_0\
);
\dc_bias[3]_i_32__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"01B00071B20001B0"
)
port map (
I0 => rgb(6),
I1 => rgb(7),
I2 => \dc_bias[3]_i_3__1_n_0\,
I3 => \encoded[3]_i_2_n_0\,
I4 => rgb(5),
I5 => rgb(4),
O => \dc_bias[3]_i_32__0_n_0\
);
\dc_bias[3]_i_33__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9208000059591049"
)
port map (
I0 => \encoded[3]_i_2_n_0\,
I1 => rgb(4),
I2 => rgb(5),
I3 => rgb(6),
I4 => rgb(7),
I5 => \dc_bias[3]_i_3__1_n_0\,
O => \dc_bias[3]_i_33__0_n_0\
);
\dc_bias[3]_i_3__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"2B023F03FFBFFFFF"
)
port map (
I0 => \encoded[7]_i_2__1_n_0\,
I1 => \dc_bias[3]_i_10__1_n_0\,
I2 => \dc_bias[3]_i_11__1_n_0\,
I3 => \dc_bias[3]_i_12__1_n_0\,
I4 => rgb(0),
I5 => \dc_bias[3]_i_13__0_n_0\,
O => \dc_bias[3]_i_3__1_n_0\
);
\dc_bias[3]_i_4__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"65A6"
)
port map (
I0 => \dc_bias[2]_i_2__0_n_0\,
I1 => \dc_bias_reg_n_0_[2]\,
I2 => \dc_bias[3]_i_14__0_n_0\,
I3 => \dc_bias[3]_i_15__1_n_0\,
O => \dc_bias[3]_i_4__1_n_0\
);
\dc_bias[3]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAEAAAAABEABAA"
)
port map (
I0 => \dc_bias[3]_i_16__0_n_0\,
I1 => \dc_bias[3]_i_17__0_n_0\,
I2 => \dc_bias[3]_i_18__0_n_0\,
I3 => \dc_bias[3]_i_19__1_n_0\,
I4 => \dc_bias[3]_i_20__0_n_0\,
I5 => \dc_bias[3]_i_21_n_0\,
O => \dc_bias[3]_i_5_n_0\
);
\dc_bias[3]_i_6__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"8228822828288228"
)
port map (
I0 => \dc_bias[2]_i_2__0_n_0\,
I1 => p_1_in,
I2 => \dc_bias[3]_i_22__1_n_0\,
I3 => \dc_bias[3]_i_23__0_n_0\,
I4 => \dc_bias[2]_i_5__1_n_0\,
I5 => \dc_bias[3]_i_24__1_n_0\,
O => \dc_bias[3]_i_6__1_n_0\
);
\dc_bias[3]_i_7__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFF4F4F0FBFFFFF4"
)
port map (
I0 => \dc_bias[3]_i_25__1_n_0\,
I1 => \dc_bias_reg_n_0_[1]\,
I2 => \dc_bias[2]_i_2__0_n_0\,
I3 => \dc_bias[3]_i_26__1_n_0\,
I4 => \dc_bias_reg_n_0_[2]\,
I5 => \dc_bias[3]_i_14__0_n_0\,
O => \dc_bias[3]_i_7__1_n_0\
);
\dc_bias[3]_i_8__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"08A28A20AEFBEFBA"
)
port map (
I0 => \dc_bias[3]_i_27__1_n_0\,
I1 => rgb(3),
I2 => rgb(2),
I3 => \encoded[1]_i_2_n_0\,
I4 => \dc_bias[3]_i_3__1_n_0\,
I5 => \dc_bias[1]_i_8_n_0\,
O => \dc_bias[3]_i_8__1_n_0\
);
\dc_bias[3]_i_9__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000099F099FFFFF"
)
port map (
I0 => \encoded[7]_i_2__1_n_0\,
I1 => \dc_bias[3]_i_3__1_n_0\,
I2 => rgb(0),
I3 => \dc_bias_reg_n_0_[0]\,
I4 => \dc_bias_reg_n_0_[1]\,
I5 => \dc_bias[3]_i_28__0_n_0\,
O => \dc_bias[3]_i_9__1_n_0\
);
\dc_bias_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25,
CE => '1',
D => \dc_bias[0]_i_1__1_n_0\,
Q => \dc_bias_reg_n_0_[0]\,
R => \^sr\(0)
);
\dc_bias_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25,
CE => '1',
D => \dc_bias[1]_i_1__0_n_0\,
Q => \dc_bias_reg_n_0_[1]\,
R => \^sr\(0)
);
\dc_bias_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25,
CE => '1',
D => \dc_bias[2]_i_1__1_n_0\,
Q => \dc_bias_reg_n_0_[2]\,
R => \^sr\(0)
);
\dc_bias_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25,
CE => '1',
D => \dc_bias[3]_i_1__1_n_0\,
Q => p_1_in,
R => \^sr\(0)
);
\encoded[0]_i_1__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6F6FAF5F6060A050"
)
port map (
I0 => rgb(0),
I1 => \dc_bias[3]_i_3__1_n_0\,
I2 => active,
I3 => \dc_bias[2]_i_2__0_n_0\,
I4 => \dc_bias[3]_i_5_n_0\,
I5 => hsync,
O => \encoded[0]_i_1__1_n_0\
);
\encoded[1]_i_1__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF7B33B7CC480084"
)
port map (
I0 => \dc_bias[3]_i_3__1_n_0\,
I1 => active,
I2 => \dc_bias[2]_i_2__0_n_0\,
I3 => \dc_bias[3]_i_5_n_0\,
I4 => \encoded[1]_i_2_n_0\,
I5 => hsync,
O => \encoded[1]_i_1__1_n_0\
);
\encoded[1]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb(0),
I1 => rgb(1),
O => \encoded[1]_i_2_n_0\
);
\encoded[2]_i_1__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"880C44C0BB3F77F3"
)
port map (
I0 => \dc_bias[3]_i_3__1_n_0\,
I1 => active,
I2 => \dc_bias[2]_i_2__0_n_0\,
I3 => \dc_bias[3]_i_5_n_0\,
I4 => \encoded[2]_i_2_n_0\,
I5 => hsync,
O => \encoded[2]_i_1__1_n_0\
);
\encoded[2]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => rgb(2),
I1 => rgb(1),
I2 => rgb(0),
O => \encoded[2]_i_2_n_0\
);
\encoded[3]_i_1__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"33B7FF7B0084CC48"
)
port map (
I0 => \dc_bias[3]_i_3__1_n_0\,
I1 => active,
I2 => \dc_bias[2]_i_2__0_n_0\,
I3 => \dc_bias[3]_i_5_n_0\,
I4 => \encoded[3]_i_2_n_0\,
I5 => hsync,
O => \encoded[3]_i_1__1_n_0\
);
\encoded[3]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9669"
)
port map (
I0 => rgb(3),
I1 => rgb(0),
I2 => rgb(1),
I3 => rgb(2),
O => \encoded[3]_i_2_n_0\
);
\encoded[4]_i_1__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"44C0880C77F3BB3F"
)
port map (
I0 => \dc_bias[3]_i_3__1_n_0\,
I1 => active,
I2 => \dc_bias[2]_i_2__0_n_0\,
I3 => \dc_bias[3]_i_5_n_0\,
I4 => \encoded[4]_i_2_n_0\,
I5 => hsync,
O => \encoded[4]_i_1__1_n_0\
);
\encoded[4]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"96696996"
)
port map (
I0 => rgb(4),
I1 => rgb(2),
I2 => rgb(1),
I3 => rgb(0),
I4 => rgb(3),
O => \encoded[4]_i_2_n_0\
);
\encoded[5]_i_1__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"33B7FF7B0084CC48"
)
port map (
I0 => \dc_bias[3]_i_3__1_n_0\,
I1 => active,
I2 => \dc_bias[2]_i_2__0_n_0\,
I3 => \dc_bias[3]_i_5_n_0\,
I4 => \encoded[5]_i_2_n_0\,
I5 => hsync,
O => \encoded[5]_i_1__1_n_0\
);
\encoded[5]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"9669699669969669"
)
port map (
I0 => rgb(2),
I1 => rgb(1),
I2 => rgb(0),
I3 => rgb(3),
I4 => rgb(5),
I5 => rgb(4),
O => \encoded[5]_i_2_n_0\
);
\encoded[6]_i_1__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"880C44C0BB3F77F3"
)
port map (
I0 => \dc_bias[3]_i_3__1_n_0\,
I1 => active,
I2 => \dc_bias[2]_i_2__0_n_0\,
I3 => \dc_bias[3]_i_5_n_0\,
I4 => \encoded[6]_i_2__1_n_0\,
I5 => hsync,
O => \encoded[6]_i_1__1_n_0\
);
\encoded[6]_i_2__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \encoded[3]_i_2_n_0\,
I1 => rgb(4),
I2 => rgb(5),
I3 => rgb(6),
O => \encoded[6]_i_2__1_n_0\
);
\encoded[7]_i_1__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF337BB7CC004884"
)
port map (
I0 => \dc_bias[3]_i_3__1_n_0\,
I1 => active,
I2 => \dc_bias[2]_i_2__0_n_0\,
I3 => \encoded[7]_i_2__1_n_0\,
I4 => \dc_bias[3]_i_5_n_0\,
I5 => hsync,
O => \encoded[7]_i_1__1_n_0\
);
\encoded[7]_i_2__1\: unisim.vcomponents.LUT5
generic map(
INIT => X"69969669"
)
port map (
I0 => rgb(7),
I1 => rgb(6),
I2 => rgb(5),
I3 => rgb(4),
I4 => \encoded[3]_i_2_n_0\,
O => \encoded[7]_i_2__1_n_0\
);
\encoded[8]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \dc_bias[3]_i_3__1_n_0\,
I1 => active,
I2 => hsync,
O => \encoded[8]_i_1__1_n_0\
);
\encoded[9]_i_1__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"C5FFC500C500C5FF"
)
port map (
I0 => \dc_bias[2]_i_2__0_n_0\,
I1 => \dc_bias[3]_i_3__1_n_0\,
I2 => \dc_bias[3]_i_5_n_0\,
I3 => active,
I4 => hsync,
I5 => vsync,
O => \encoded[9]_i_1__1_n_0\
);
\encoded_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \encoded[0]_i_1__1_n_0\,
Q => \encoded_reg_n_0_[0]\,
R => '0'
);
\encoded_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \encoded[1]_i_1__1_n_0\,
Q => \encoded_reg_n_0_[1]\,
R => '0'
);
\encoded_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \encoded[2]_i_1__1_n_0\,
Q => \encoded_reg_n_0_[2]\,
R => '0'
);
\encoded_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \encoded[3]_i_1__1_n_0\,
Q => \encoded_reg_n_0_[3]\,
R => '0'
);
\encoded_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \encoded[4]_i_1__1_n_0\,
Q => \encoded_reg_n_0_[4]\,
R => '0'
);
\encoded_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \encoded[5]_i_1__1_n_0\,
Q => \encoded_reg_n_0_[5]\,
R => '0'
);
\encoded_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \encoded[6]_i_1__1_n_0\,
Q => \encoded_reg_n_0_[6]\,
R => '0'
);
\encoded_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \encoded[7]_i_1__1_n_0\,
Q => \encoded_reg_n_0_[7]\,
R => '0'
);
\encoded_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \encoded[8]_i_1__1_n_0\,
Q => Q(0),
R => '0'
);
\encoded_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \encoded[9]_i_1__1_n_0\,
Q => Q(1),
R => '0'
);
\shift_blue[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => shift_blue(0),
I1 => \shift_clock_reg[5]\,
I2 => \encoded_reg_n_0_[0]\,
O => D(0)
);
\shift_blue[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => shift_blue(1),
I1 => \shift_clock_reg[5]\,
I2 => \encoded_reg_n_0_[1]\,
O => D(1)
);
\shift_blue[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => shift_blue(2),
I1 => \shift_clock_reg[5]\,
I2 => \encoded_reg_n_0_[2]\,
O => D(2)
);
\shift_blue[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => shift_blue(3),
I1 => \shift_clock_reg[5]\,
I2 => \encoded_reg_n_0_[3]\,
O => D(3)
);
\shift_blue[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => shift_blue(4),
I1 => \shift_clock_reg[5]\,
I2 => \encoded_reg_n_0_[4]\,
O => D(4)
);
\shift_blue[5]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => shift_blue(5),
I1 => \shift_clock_reg[5]\,
I2 => \encoded_reg_n_0_[5]\,
O => D(5)
);
\shift_blue[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => shift_blue(6),
I1 => \shift_clock_reg[5]\,
I2 => \encoded_reg_n_0_[6]\,
O => D(6)
);
\shift_blue[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => shift_blue(7),
I1 => \shift_clock_reg[5]\,
I2 => \encoded_reg_n_0_[7]\,
O => D(7)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_zybo_hdmi_0_0_TMDS_encoder_0 is
port (
D : out STD_LOGIC_VECTOR ( 7 downto 0 );
Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
rgb : in STD_LOGIC_VECTOR ( 7 downto 0 );
active : in STD_LOGIC;
shift_green : in STD_LOGIC_VECTOR ( 7 downto 0 );
\shift_clock_reg[5]\ : in STD_LOGIC;
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
clk_25 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_zybo_hdmi_0_0_TMDS_encoder_0 : entity is "TMDS_encoder";
end system_zybo_hdmi_0_0_TMDS_encoder_0;
architecture STRUCTURE of system_zybo_hdmi_0_0_TMDS_encoder_0 is
signal \dc_bias[0]_i_1__0_n_0\ : STD_LOGIC;
signal \dc_bias[0]_i_2__0_n_0\ : STD_LOGIC;
signal \dc_bias[0]_i_3__0_n_0\ : STD_LOGIC;
signal \dc_bias[0]_i_4__0_n_0\ : STD_LOGIC;
signal \dc_bias[0]_i_5__1_n_0\ : STD_LOGIC;
signal \dc_bias[0]_i_6_n_0\ : STD_LOGIC;
signal \dc_bias[0]_i_7_n_0\ : STD_LOGIC;
signal \dc_bias[1]_i_1_n_0\ : STD_LOGIC;
signal \dc_bias[1]_i_2__0_n_0\ : STD_LOGIC;
signal \dc_bias[1]_i_3__0_n_0\ : STD_LOGIC;
signal \dc_bias[1]_i_4__0_n_0\ : STD_LOGIC;
signal \dc_bias[1]_i_5_n_0\ : STD_LOGIC;
signal \dc_bias[1]_i_6__1_n_0\ : STD_LOGIC;
signal \dc_bias[1]_i_7__0_n_0\ : STD_LOGIC;
signal \dc_bias[1]_i_8__0_n_0\ : STD_LOGIC;
signal \dc_bias[1]_i_9_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_10__1_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_11__0_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_1__0_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_2__1_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_3__0_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_4_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_5__0_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_6__0_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_7_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_8__0_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_9_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_10__0_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_11__0_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_12__0_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_13__1_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_14__1_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_15__0_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_16_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_17_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_18__1_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_19__0_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_1__0_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_20_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_21__1_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_22__0_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_23__1_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_24__0_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_25__0_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_26__0_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_27__0_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_28_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_29_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_2__0_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_30_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_31_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_32_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_33_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_34_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_3__0_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_4__0_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_5__1_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_6__0_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_7__0_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_8__0_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_9__0_n_0\ : STD_LOGIC;
signal \dc_bias_reg_n_0_[0]\ : STD_LOGIC;
signal \dc_bias_reg_n_0_[1]\ : STD_LOGIC;
signal \dc_bias_reg_n_0_[2]\ : STD_LOGIC;
signal \encoded[0]_i_1__0_n_0\ : STD_LOGIC;
signal \encoded[1]_i_1__0_n_0\ : STD_LOGIC;
signal \encoded[2]_i_1__0_n_0\ : STD_LOGIC;
signal \encoded[3]_i_1__0_n_0\ : STD_LOGIC;
signal \encoded[4]_i_1__0_n_0\ : STD_LOGIC;
signal \encoded[5]_i_1__0_n_0\ : STD_LOGIC;
signal \encoded[6]_i_1__0_n_0\ : STD_LOGIC;
signal \encoded[6]_i_2__0_n_0\ : STD_LOGIC;
signal \encoded[7]_i_1__0_n_0\ : STD_LOGIC;
signal \encoded[7]_i_2_n_0\ : STD_LOGIC;
signal \encoded[7]_i_3__0_n_0\ : STD_LOGIC;
signal \encoded[8]_i_1__0_n_0\ : STD_LOGIC;
signal \encoded[8]_i_2_n_0\ : STD_LOGIC;
signal \encoded[8]_i_3_n_0\ : STD_LOGIC;
signal \encoded[8]_i_4_n_0\ : STD_LOGIC;
signal \encoded[8]_i_5_n_0\ : STD_LOGIC;
signal \encoded[8]_i_6_n_0\ : STD_LOGIC;
signal \encoded[8]_i_7_n_0\ : STD_LOGIC;
signal \encoded[9]_i_1_n_0\ : STD_LOGIC;
signal \encoded[9]_i_2__0_n_0\ : STD_LOGIC;
signal \encoded_reg_n_0_[0]\ : STD_LOGIC;
signal \encoded_reg_n_0_[1]\ : STD_LOGIC;
signal \encoded_reg_n_0_[2]\ : STD_LOGIC;
signal \encoded_reg_n_0_[3]\ : STD_LOGIC;
signal \encoded_reg_n_0_[4]\ : STD_LOGIC;
signal \encoded_reg_n_0_[5]\ : STD_LOGIC;
signal \encoded_reg_n_0_[6]\ : STD_LOGIC;
signal \encoded_reg_n_0_[7]\ : STD_LOGIC;
signal p_1_in : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \dc_bias[0]_i_2__0\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \dc_bias[0]_i_3__0\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \dc_bias[0]_i_4__0\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \dc_bias[0]_i_5__1\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \dc_bias[0]_i_6\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \dc_bias[0]_i_7\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \dc_bias[1]_i_3__0\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \dc_bias[1]_i_8__0\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \dc_bias[2]_i_10__1\ : label is "soft_lutpair38";
attribute SOFT_HLUTNM of \dc_bias[2]_i_11__0\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \dc_bias[2]_i_8__0\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \dc_bias[2]_i_9\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \dc_bias[3]_i_11__0\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \dc_bias[3]_i_12__0\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \dc_bias[3]_i_13__1\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \dc_bias[3]_i_14__1\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \dc_bias[3]_i_15__0\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \dc_bias[3]_i_16\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \dc_bias[3]_i_18__1\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \dc_bias[3]_i_22__0\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \dc_bias[3]_i_23__1\ : label is "soft_lutpair38";
attribute SOFT_HLUTNM of \dc_bias[3]_i_24__0\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \dc_bias[3]_i_2__0\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \dc_bias[3]_i_33\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \dc_bias[3]_i_7__0\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \dc_bias[3]_i_8__0\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \encoded[0]_i_1__0\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \encoded[1]_i_1__0\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \encoded[2]_i_1__0\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \encoded[4]_i_1__0\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \encoded[5]_i_1__0\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \encoded[6]_i_2__0\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \encoded[7]_i_1__0\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of \encoded[7]_i_2\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \encoded[7]_i_3__0\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \encoded[8]_i_1__0\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of \encoded[8]_i_4\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \encoded[8]_i_7\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \shift_green[0]_i_1\ : label is "soft_lutpair34";
attribute SOFT_HLUTNM of \shift_green[1]_i_1\ : label is "soft_lutpair35";
attribute SOFT_HLUTNM of \shift_green[2]_i_1\ : label is "soft_lutpair36";
attribute SOFT_HLUTNM of \shift_green[3]_i_1\ : label is "soft_lutpair36";
attribute SOFT_HLUTNM of \shift_green[4]_i_1\ : label is "soft_lutpair35";
attribute SOFT_HLUTNM of \shift_green[5]_i_1\ : label is "soft_lutpair37";
attribute SOFT_HLUTNM of \shift_green[6]_i_1\ : label is "soft_lutpair37";
attribute SOFT_HLUTNM of \shift_green[7]_i_1\ : label is "soft_lutpair34";
begin
\dc_bias[0]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"6F60606F606F6F60"
)
port map (
I0 => \dc_bias_reg_n_0_[0]\,
I1 => \dc_bias[0]_i_2__0_n_0\,
I2 => \dc_bias[3]_i_2__0_n_0\,
I3 => \dc_bias[3]_i_5__1_n_0\,
I4 => \dc_bias[0]_i_3__0_n_0\,
I5 => \dc_bias[0]_i_4__0_n_0\,
O => \dc_bias[0]_i_1__0_n_0\
);
\dc_bias[0]_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"69969669"
)
port map (
I0 => \dc_bias[0]_i_5__1_n_0\,
I1 => rgb(0),
I2 => \dc_bias[0]_i_6_n_0\,
I3 => \dc_bias[0]_i_7_n_0\,
I4 => rgb(6),
O => \dc_bias[0]_i_2__0_n_0\
);
\dc_bias[0]_i_3__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"69969669"
)
port map (
I0 => \encoded[6]_i_2__0_n_0\,
I1 => rgb(5),
I2 => rgb(0),
I3 => \dc_bias_reg_n_0_[0]\,
I4 => rgb(7),
O => \dc_bias[0]_i_3__0_n_0\
);
\dc_bias[0]_i_4__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb(2),
I1 => \encoded[8]_i_2_n_0\,
O => \dc_bias[0]_i_4__0_n_0\
);
\dc_bias[0]_i_5__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => rgb(3),
I1 => rgb(1),
I2 => rgb(0),
O => \dc_bias[0]_i_5__1_n_0\
);
\dc_bias[0]_i_6\: unisim.vcomponents.LUT5
generic map(
INIT => X"69969669"
)
port map (
I0 => rgb(7),
I1 => \encoded[6]_i_2__0_n_0\,
I2 => rgb(6),
I3 => rgb(5),
I4 => rgb(4),
O => \dc_bias[0]_i_6_n_0\
);
\dc_bias[0]_i_7\: unisim.vcomponents.LUT5
generic map(
INIT => X"96696996"
)
port map (
I0 => rgb(4),
I1 => rgb(2),
I2 => rgb(1),
I3 => rgb(0),
I4 => rgb(3),
O => \dc_bias[0]_i_7_n_0\
);
\dc_bias[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \dc_bias[1]_i_2__0_n_0\,
I1 => \dc_bias[3]_i_2__0_n_0\,
I2 => \dc_bias[1]_i_3__0_n_0\,
I3 => \dc_bias[3]_i_5__1_n_0\,
I4 => \dc_bias[1]_i_4__0_n_0\,
O => \dc_bias[1]_i_1_n_0\
);
\dc_bias[1]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"960096FF96FF9600"
)
port map (
I0 => \dc_bias[1]_i_5_n_0\,
I1 => \dc_bias[1]_i_6__1_n_0\,
I2 => \dc_bias[1]_i_7__0_n_0\,
I3 => \encoded[8]_i_2_n_0\,
I4 => \dc_bias[1]_i_8__0_n_0\,
I5 => \dc_bias[2]_i_10__1_n_0\,
O => \dc_bias[1]_i_2__0_n_0\
);
\dc_bias[1]_i_3__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"5965"
)
port map (
I0 => \dc_bias[2]_i_10__1_n_0\,
I1 => \encoded[8]_i_2_n_0\,
I2 => \dc_bias[0]_i_2__0_n_0\,
I3 => \dc_bias_reg_n_0_[0]\,
O => \dc_bias[1]_i_3__0_n_0\
);
\dc_bias[1]_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"56955965A96AA69A"
)
port map (
I0 => \dc_bias[3]_i_11__0_n_0\,
I1 => \dc_bias[0]_i_3__0_n_0\,
I2 => rgb(2),
I3 => \encoded[8]_i_2_n_0\,
I4 => \dc_bias[2]_i_11__0_n_0\,
I5 => \dc_bias[3]_i_12__0_n_0\,
O => \dc_bias[1]_i_4__0_n_0\
);
\dc_bias[1]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"066090096FF6F99F"
)
port map (
I0 => rgb(6),
I1 => \dc_bias[0]_i_7_n_0\,
I2 => \dc_bias[1]_i_9_n_0\,
I3 => \dc_bias[0]_i_6_n_0\,
I4 => \encoded[8]_i_2_n_0\,
I5 => \dc_bias[0]_i_5__1_n_0\,
O => \dc_bias[1]_i_5_n_0\
);
\dc_bias[1]_i_6__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"556969AAAA969655"
)
port map (
I0 => \dc_bias[3]_i_27__0_n_0\,
I1 => \dc_bias[0]_i_6_n_0\,
I2 => \encoded[8]_i_2_n_0\,
I3 => \dc_bias_reg_n_0_[0]\,
I4 => rgb(0),
I5 => \dc_bias_reg_n_0_[1]\,
O => \dc_bias[1]_i_6__1_n_0\
);
\dc_bias[1]_i_7__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9C3939399C9C9C39"
)
port map (
I0 => rgb(2),
I1 => \dc_bias[2]_i_11__0_n_0\,
I2 => rgb(3),
I3 => \dc_bias[3]_i_30_n_0\,
I4 => \encoded[8]_i_6_n_0\,
I5 => \dc_bias[3]_i_31_n_0\,
O => \dc_bias[1]_i_7__0_n_0\
);
\dc_bias[1]_i_8__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \dc_bias_reg_n_0_[0]\,
I1 => \dc_bias[0]_i_2__0_n_0\,
O => \dc_bias[1]_i_8__0_n_0\
);
\dc_bias[1]_i_9\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb(0),
I1 => \dc_bias_reg_n_0_[0]\,
O => \dc_bias[1]_i_9_n_0\
);
\dc_bias[2]_i_10__1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \dc_bias_reg_n_0_[1]\,
I1 => \dc_bias[3]_i_10__0_n_0\,
O => \dc_bias[2]_i_10__1_n_0\
);
\dc_bias[2]_i_11__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb(0),
I1 => rgb(1),
O => \dc_bias[2]_i_11__0_n_0\
);
\dc_bias[2]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"B888B8BBB8BBB888"
)
port map (
I0 => \dc_bias[2]_i_2__1_n_0\,
I1 => \dc_bias[3]_i_2__0_n_0\,
I2 => \dc_bias[2]_i_3__0_n_0\,
I3 => \dc_bias[3]_i_5__1_n_0\,
I4 => \dc_bias[2]_i_4_n_0\,
I5 => \dc_bias[2]_i_5__0_n_0\,
O => \dc_bias[2]_i_1__0_n_0\
);
\dc_bias[2]_i_2__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"96FF9600960096FF"
)
port map (
I0 => \dc_bias_reg_n_0_[2]\,
I1 => \dc_bias[2]_i_6__0_n_0\,
I2 => \dc_bias[2]_i_7_n_0\,
I3 => \encoded[8]_i_2_n_0\,
I4 => \dc_bias[2]_i_8__0_n_0\,
I5 => \dc_bias[2]_i_9_n_0\,
O => \dc_bias[2]_i_2__1_n_0\
);
\dc_bias[2]_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"04DFFB20FB2004DF"
)
port map (
I0 => \dc_bias_reg_n_0_[0]\,
I1 => \dc_bias[0]_i_2__0_n_0\,
I2 => \encoded[8]_i_2_n_0\,
I3 => \dc_bias[2]_i_10__1_n_0\,
I4 => \dc_bias[3]_i_23__1_n_0\,
I5 => \dc_bias[2]_i_8__0_n_0\,
O => \dc_bias[2]_i_3__0_n_0\
);
\dc_bias[2]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"711818188EE7E7E7"
)
port map (
I0 => \dc_bias[3]_i_16_n_0\,
I1 => \dc_bias[3]_i_17_n_0\,
I2 => \dc_bias_reg_n_0_[1]\,
I3 => \dc_bias_reg_n_0_[0]\,
I4 => rgb(0),
I5 => \dc_bias_reg_n_0_[2]\,
O => \dc_bias[2]_i_4_n_0\
);
\dc_bias[2]_i_5__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"BB2BB2BBBBBDDBBB"
)
port map (
I0 => \dc_bias[3]_i_11__0_n_0\,
I1 => \dc_bias[3]_i_12__0_n_0\,
I2 => \dc_bias[2]_i_11__0_n_0\,
I3 => \encoded[8]_i_2_n_0\,
I4 => rgb(2),
I5 => \dc_bias[0]_i_3__0_n_0\,
O => \dc_bias[2]_i_5__0_n_0\
);
\dc_bias[2]_i_6__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"01151501577F7F57"
)
port map (
I0 => \dc_bias_reg_n_0_[1]\,
I1 => rgb(0),
I2 => \dc_bias_reg_n_0_[0]\,
I3 => \dc_bias[0]_i_6_n_0\,
I4 => \encoded[8]_i_2_n_0\,
I5 => \dc_bias[3]_i_27__0_n_0\,
O => \dc_bias[2]_i_6__0_n_0\
);
\dc_bias[2]_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"802AA802EABFFEAB"
)
port map (
I0 => \dc_bias[1]_i_5_n_0\,
I1 => \encoded[8]_i_2_n_0\,
I2 => rgb(3),
I3 => \dc_bias[2]_i_11__0_n_0\,
I4 => rgb(2),
I5 => \dc_bias[1]_i_6__1_n_0\,
O => \dc_bias[2]_i_7_n_0\
);
\dc_bias[2]_i_8__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \dc_bias_reg_n_0_[2]\,
I1 => \dc_bias[3]_i_9__0_n_0\,
O => \dc_bias[2]_i_8__0_n_0\
);
\dc_bias[2]_i_9\: unisim.vcomponents.LUT4
generic map(
INIT => X"2B22"
)
port map (
I0 => \dc_bias[3]_i_10__0_n_0\,
I1 => \dc_bias_reg_n_0_[1]\,
I2 => \dc_bias_reg_n_0_[0]\,
I3 => \dc_bias[0]_i_2__0_n_0\,
O => \dc_bias[2]_i_9_n_0\
);
\dc_bias[3]_i_10__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"188EE771E771188E"
)
port map (
I0 => \dc_bias[0]_i_5__1_n_0\,
I1 => \dc_bias[3]_i_29_n_0\,
I2 => rgb(0),
I3 => \dc_bias[3]_i_28_n_0\,
I4 => \dc_bias[3]_i_27__0_n_0\,
I5 => \dc_bias[1]_i_7__0_n_0\,
O => \dc_bias[3]_i_10__0_n_0\
);
\dc_bias[3]_i_11__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"96696969"
)
port map (
I0 => \dc_bias[3]_i_16_n_0\,
I1 => \dc_bias[3]_i_17_n_0\,
I2 => \dc_bias_reg_n_0_[1]\,
I3 => \dc_bias_reg_n_0_[0]\,
I4 => rgb(0),
O => \dc_bias[3]_i_11__0_n_0\
);
\dc_bias[3]_i_12__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"82EBEB82"
)
port map (
I0 => rgb(7),
I1 => \dc_bias_reg_n_0_[0]\,
I2 => rgb(0),
I3 => rgb(5),
I4 => \encoded[6]_i_2__0_n_0\,
O => \dc_bias[3]_i_12__0_n_0\
);
\dc_bias[3]_i_13__1\: unisim.vcomponents.LUT5
generic map(
INIT => X"96669996"
)
port map (
I0 => rgb(1),
I1 => rgb(0),
I2 => \dc_bias[3]_i_30_n_0\,
I3 => \encoded[8]_i_6_n_0\,
I4 => \dc_bias[3]_i_31_n_0\,
O => \dc_bias[3]_i_13__1_n_0\
);
\dc_bias[3]_i_14__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => rgb(2),
I1 => rgb(1),
I2 => rgb(0),
O => \dc_bias[3]_i_14__1_n_0\
);
\dc_bias[3]_i_15__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => rgb(0),
I1 => \dc_bias_reg_n_0_[0]\,
O => \dc_bias[3]_i_15__0_n_0\
);
\dc_bias[3]_i_16\: unisim.vcomponents.LUT4
generic map(
INIT => X"B42D"
)
port map (
I0 => \encoded[8]_i_2_n_0\,
I1 => rgb(4),
I2 => \encoded[6]_i_2__0_n_0\,
I3 => rgb(5),
O => \dc_bias[3]_i_16_n_0\
);
\dc_bias[3]_i_17\: unisim.vcomponents.LUT6
generic map(
INIT => X"1771711771171771"
)
port map (
I0 => \encoded[8]_i_2_n_0\,
I1 => rgb(7),
I2 => \encoded[6]_i_2__0_n_0\,
I3 => rgb(6),
I4 => rgb(5),
I5 => rgb(4),
O => \dc_bias[3]_i_17_n_0\
);
\dc_bias[3]_i_18__1\: unisim.vcomponents.LUT5
generic map(
INIT => X"14414114"
)
port map (
I0 => \dc_bias[0]_i_5__1_n_0\,
I1 => rgb(0),
I2 => \dc_bias[0]_i_6_n_0\,
I3 => \dc_bias[0]_i_7_n_0\,
I4 => rgb(6),
O => \dc_bias[3]_i_18__1_n_0\
);
\dc_bias[3]_i_19__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"82BE14D714D782BE"
)
port map (
I0 => \encoded[8]_i_2_n_0\,
I1 => rgb(7),
I2 => \encoded[7]_i_2_n_0\,
I3 => rgb(0),
I4 => \dc_bias[0]_i_7_n_0\,
I5 => rgb(6),
O => \dc_bias[3]_i_19__0_n_0\
);
\dc_bias[3]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000FFFFAAEB"
)
port map (
I0 => \dc_bias[3]_i_2__0_n_0\,
I1 => \dc_bias[3]_i_3__0_n_0\,
I2 => \dc_bias[3]_i_4__0_n_0\,
I3 => \dc_bias[3]_i_5__1_n_0\,
I4 => \dc_bias[3]_i_6__0_n_0\,
I5 => \dc_bias[3]_i_7__0_n_0\,
O => \dc_bias[3]_i_1__0_n_0\
);
\dc_bias[3]_i_20\: unisim.vcomponents.LUT6
generic map(
INIT => X"42BDBD42BD4242BD"
)
port map (
I0 => rgb(6),
I1 => \encoded[8]_i_2_n_0\,
I2 => rgb(5),
I3 => rgb(4),
I4 => \encoded[6]_i_2__0_n_0\,
I5 => \dc_bias[1]_i_7__0_n_0\,
O => \dc_bias[3]_i_20_n_0\
);
\dc_bias[3]_i_21__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"BAAEEFFBEFFBBAAE"
)
port map (
I0 => \dc_bias[1]_i_7__0_n_0\,
I1 => rgb(6),
I2 => \encoded[8]_i_2_n_0\,
I3 => rgb(5),
I4 => rgb(4),
I5 => \encoded[6]_i_2__0_n_0\,
O => \dc_bias[3]_i_21__1_n_0\
);
\dc_bias[3]_i_22__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"99F99099"
)
port map (
I0 => \dc_bias_reg_n_0_[1]\,
I1 => \dc_bias[3]_i_10__0_n_0\,
I2 => \encoded[8]_i_2_n_0\,
I3 => \dc_bias[0]_i_2__0_n_0\,
I4 => \dc_bias_reg_n_0_[0]\,
O => \dc_bias[3]_i_22__0_n_0\
);
\dc_bias[3]_i_23__1\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \dc_bias[3]_i_10__0_n_0\,
I1 => \dc_bias_reg_n_0_[1]\,
O => \dc_bias[3]_i_23__1_n_0\
);
\dc_bias[3]_i_24__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"DF"
)
port map (
I0 => \dc_bias_reg_n_0_[0]\,
I1 => \dc_bias[0]_i_2__0_n_0\,
I2 => \encoded[8]_i_2_n_0\,
O => \dc_bias[3]_i_24__0_n_0\
);
\dc_bias[3]_i_25__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"002BD400FFD42BFF"
)
port map (
I0 => \dc_bias[1]_i_5_n_0\,
I1 => \dc_bias[1]_i_7__0_n_0\,
I2 => \dc_bias[1]_i_6__1_n_0\,
I3 => \dc_bias[2]_i_6__0_n_0\,
I4 => \dc_bias_reg_n_0_[2]\,
I5 => p_1_in,
O => \dc_bias[3]_i_25__0_n_0\
);
\dc_bias[3]_i_26__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFD4DDD4DD0000"
)
port map (
I0 => \dc_bias[3]_i_10__0_n_0\,
I1 => \dc_bias_reg_n_0_[1]\,
I2 => \dc_bias_reg_n_0_[0]\,
I3 => \dc_bias[0]_i_2__0_n_0\,
I4 => \dc_bias_reg_n_0_[2]\,
I5 => \dc_bias[3]_i_9__0_n_0\,
O => \dc_bias[3]_i_26__0_n_0\
);
\dc_bias[3]_i_27__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EBBBEEEB82228882"
)
port map (
I0 => \dc_bias[0]_i_7_n_0\,
I1 => \dc_bias[3]_i_32_n_0\,
I2 => \dc_bias[3]_i_30_n_0\,
I3 => \encoded[8]_i_6_n_0\,
I4 => \dc_bias[3]_i_31_n_0\,
I5 => \encoded[7]_i_2_n_0\,
O => \dc_bias[3]_i_27__0_n_0\
);
\dc_bias[3]_i_28\: unisim.vcomponents.LUT6
generic map(
INIT => X"8E71718E718E8E71"
)
port map (
I0 => \dc_bias[3]_i_30_n_0\,
I1 => \encoded[8]_i_6_n_0\,
I2 => \dc_bias[3]_i_31_n_0\,
I3 => rgb(4),
I4 => \encoded[6]_i_2__0_n_0\,
I5 => rgb(6),
O => \dc_bias[3]_i_28_n_0\
);
\dc_bias[3]_i_29\: unisim.vcomponents.LUT6
generic map(
INIT => X"BAFB5D45BAFB4504"
)
port map (
I0 => \encoded[8]_i_6_n_0\,
I1 => \encoded[8]_i_5_n_0\,
I2 => \encoded[8]_i_4_n_0\,
I3 => \encoded[8]_i_3_n_0\,
I4 => \dc_bias[0]_i_6_n_0\,
I5 => rgb(0),
O => \dc_bias[3]_i_29_n_0\
);
\dc_bias[3]_i_2__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"AAAE"
)
port map (
I0 => \dc_bias[3]_i_8__0_n_0\,
I1 => \dc_bias[3]_i_9__0_n_0\,
I2 => \dc_bias[3]_i_10__0_n_0\,
I3 => \dc_bias[0]_i_2__0_n_0\,
O => \dc_bias[3]_i_2__0_n_0\
);
\dc_bias[3]_i_30\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000F6606000FFF6"
)
port map (
I0 => \dc_bias[3]_i_33_n_0\,
I1 => rgb(6),
I2 => rgb(7),
I3 => rgb(0),
I4 => \encoded[8]_i_5_n_0\,
I5 => \dc_bias[3]_i_34_n_0\,
O => \dc_bias[3]_i_30_n_0\
);
\dc_bias[3]_i_31\: unisim.vcomponents.LUT6
generic map(
INIT => X"4008000029610000"
)
port map (
I0 => rgb(7),
I1 => \encoded[6]_i_2__0_n_0\,
I2 => \encoded[8]_i_7_n_0\,
I3 => \dc_bias[3]_i_34_n_0\,
I4 => rgb(0),
I5 => \encoded[8]_i_5_n_0\,
O => \dc_bias[3]_i_31_n_0\
);
\dc_bias[3]_i_32\: unisim.vcomponents.LUT6
generic map(
INIT => X"9669699669969669"
)
port map (
I0 => rgb(5),
I1 => rgb(4),
I2 => rgb(2),
I3 => rgb(1),
I4 => rgb(0),
I5 => rgb(3),
O => \dc_bias[3]_i_32_n_0\
);
\dc_bias[3]_i_33\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb(4),
I1 => rgb(5),
O => \dc_bias[3]_i_33_n_0\
);
\dc_bias[3]_i_34\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => rgb(3),
I1 => rgb(2),
I2 => rgb(1),
O => \dc_bias[3]_i_34_n_0\
);
\dc_bias[3]_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"8A088A8A8A8AAE8A"
)
port map (
I0 => \dc_bias[2]_i_4_n_0\,
I1 => \dc_bias[3]_i_11__0_n_0\,
I2 => \dc_bias[3]_i_12__0_n_0\,
I3 => \dc_bias[3]_i_13__1_n_0\,
I4 => \dc_bias[3]_i_14__1_n_0\,
I5 => \dc_bias[0]_i_3__0_n_0\,
O => \dc_bias[3]_i_3__0_n_0\
);
\dc_bias[3]_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"56555555AA6A6A56"
)
port map (
I0 => p_1_in,
I1 => \dc_bias[3]_i_15__0_n_0\,
I2 => \dc_bias_reg_n_0_[1]\,
I3 => \dc_bias[3]_i_16_n_0\,
I4 => \dc_bias[3]_i_17_n_0\,
I5 => \dc_bias_reg_n_0_[2]\,
O => \dc_bias[3]_i_4__0_n_0\
);
\dc_bias[3]_i_5__1\: unisim.vcomponents.LUT5
generic map(
INIT => X"A6655555"
)
port map (
I0 => p_1_in,
I1 => \dc_bias[3]_i_18__1_n_0\,
I2 => \dc_bias[3]_i_19__0_n_0\,
I3 => \dc_bias[3]_i_20_n_0\,
I4 => \dc_bias[3]_i_21__1_n_0\,
O => \dc_bias[3]_i_5__1_n_0\
);
\dc_bias[3]_i_6__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"000C40404040CCC0"
)
port map (
I0 => \dc_bias[3]_i_22__0_n_0\,
I1 => \dc_bias[3]_i_5__1_n_0\,
I2 => \dc_bias[3]_i_23__1_n_0\,
I3 => \dc_bias[3]_i_24__0_n_0\,
I4 => \dc_bias[3]_i_9__0_n_0\,
I5 => \dc_bias_reg_n_0_[2]\,
O => \dc_bias[3]_i_6__0_n_0\
);
\dc_bias[3]_i_7__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B08080B0"
)
port map (
I0 => \dc_bias[3]_i_25__0_n_0\,
I1 => \encoded[8]_i_2_n_0\,
I2 => \dc_bias[3]_i_2__0_n_0\,
I3 => \dc_bias[3]_i_26__0_n_0\,
I4 => \dc_bias[3]_i_5__1_n_0\,
O => \dc_bias[3]_i_7__0_n_0\
);
\dc_bias[3]_i_8__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => \dc_bias_reg_n_0_[0]\,
I1 => \dc_bias_reg_n_0_[2]\,
I2 => p_1_in,
I3 => \dc_bias_reg_n_0_[1]\,
O => \dc_bias[3]_i_8__0_n_0\
);
\dc_bias[3]_i_9__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"D444DDD4DDD4BDDD"
)
port map (
I0 => \dc_bias[1]_i_7__0_n_0\,
I1 => \dc_bias[3]_i_27__0_n_0\,
I2 => \dc_bias[3]_i_28_n_0\,
I3 => rgb(0),
I4 => \dc_bias[3]_i_29_n_0\,
I5 => \dc_bias[0]_i_5__1_n_0\,
O => \dc_bias[3]_i_9__0_n_0\
);
\dc_bias_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25,
CE => '1',
D => \dc_bias[0]_i_1__0_n_0\,
Q => \dc_bias_reg_n_0_[0]\,
R => SR(0)
);
\dc_bias_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25,
CE => '1',
D => \dc_bias[1]_i_1_n_0\,
Q => \dc_bias_reg_n_0_[1]\,
R => SR(0)
);
\dc_bias_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25,
CE => '1',
D => \dc_bias[2]_i_1__0_n_0\,
Q => \dc_bias_reg_n_0_[2]\,
R => SR(0)
);
\dc_bias_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25,
CE => '1',
D => \dc_bias[3]_i_1__0_n_0\,
Q => p_1_in,
R => SR(0)
);
\encoded[0]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"82"
)
port map (
I0 => active,
I1 => rgb(0),
I2 => \encoded[9]_i_2__0_n_0\,
O => \encoded[0]_i_1__0_n_0\
);
\encoded[1]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"2882"
)
port map (
I0 => active,
I1 => rgb(1),
I2 => rgb(0),
I3 => \encoded[7]_i_3__0_n_0\,
O => \encoded[1]_i_1__0_n_0\
);
\encoded[2]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"D77D7DD7"
)
port map (
I0 => active,
I1 => rgb(0),
I2 => rgb(1),
I3 => rgb(2),
I4 => \encoded[9]_i_2__0_n_0\,
O => \encoded[2]_i_1__0_n_0\
);
\encoded[3]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"2882822882282882"
)
port map (
I0 => active,
I1 => rgb(2),
I2 => rgb(1),
I3 => rgb(0),
I4 => rgb(3),
I5 => \encoded[7]_i_3__0_n_0\,
O => \encoded[3]_i_1__0_n_0\
);
\encoded[4]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"D77D"
)
port map (
I0 => active,
I1 => \encoded[6]_i_2__0_n_0\,
I2 => rgb(4),
I3 => \encoded[9]_i_2__0_n_0\,
O => \encoded[4]_i_1__0_n_0\
);
\encoded[5]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"28828228"
)
port map (
I0 => active,
I1 => \encoded[6]_i_2__0_n_0\,
I2 => rgb(4),
I3 => rgb(5),
I4 => \encoded[7]_i_3__0_n_0\,
O => \encoded[5]_i_1__0_n_0\
);
\encoded[6]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"D77D7DD77DD7D77D"
)
port map (
I0 => active,
I1 => \encoded[6]_i_2__0_n_0\,
I2 => rgb(6),
I3 => rgb(5),
I4 => rgb(4),
I5 => \encoded[9]_i_2__0_n_0\,
O => \encoded[6]_i_1__0_n_0\
);
\encoded[6]_i_2__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9669"
)
port map (
I0 => rgb(3),
I1 => rgb(0),
I2 => rgb(1),
I3 => rgb(2),
O => \encoded[6]_i_2__0_n_0\
);
\encoded[7]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"2882"
)
port map (
I0 => active,
I1 => \encoded[7]_i_2_n_0\,
I2 => rgb(7),
I3 => \encoded[7]_i_3__0_n_0\,
O => \encoded[7]_i_1__0_n_0\
);
\encoded[7]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9669"
)
port map (
I0 => rgb(4),
I1 => rgb(5),
I2 => rgb(6),
I3 => \encoded[6]_i_2__0_n_0\,
O => \encoded[7]_i_2_n_0\
);
\encoded[7]_i_3__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"BE"
)
port map (
I0 => \dc_bias[3]_i_2__0_n_0\,
I1 => \dc_bias[3]_i_5__1_n_0\,
I2 => \encoded[8]_i_2_n_0\,
O => \encoded[7]_i_3__0_n_0\
);
\encoded[8]_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \encoded[8]_i_2_n_0\,
I1 => active,
O => \encoded[8]_i_1__0_n_0\
);
\encoded[8]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"00200000F2FF20F2"
)
port map (
I0 => rgb(0),
I1 => \dc_bias[0]_i_6_n_0\,
I2 => \encoded[8]_i_3_n_0\,
I3 => \encoded[8]_i_4_n_0\,
I4 => \encoded[8]_i_5_n_0\,
I5 => \encoded[8]_i_6_n_0\,
O => \encoded[8]_i_2_n_0\
);
\encoded[8]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF6969FF69FFFF69"
)
port map (
I0 => rgb(1),
I1 => rgb(2),
I2 => rgb(3),
I3 => rgb(0),
I4 => rgb(7),
I5 => \encoded[8]_i_7_n_0\,
O => \encoded[8]_i_3_n_0\
);
\encoded[8]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"E88E8EE8"
)
port map (
I0 => rgb(0),
I1 => rgb(7),
I2 => rgb(6),
I3 => rgb(5),
I4 => rgb(4),
O => \encoded[8]_i_4_n_0\
);
\encoded[8]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"E8E8E817E8171717"
)
port map (
I0 => rgb(2),
I1 => rgb(3),
I2 => rgb(1),
I3 => rgb(6),
I4 => rgb(5),
I5 => rgb(4),
O => \encoded[8]_i_5_n_0\
);
\encoded[8]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"E8E8E800E8000000"
)
port map (
I0 => rgb(6),
I1 => rgb(5),
I2 => rgb(4),
I3 => rgb(2),
I4 => rgb(3),
I5 => rgb(1),
O => \encoded[8]_i_6_n_0\
);
\encoded[8]_i_7\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => rgb(6),
I1 => rgb(5),
I2 => rgb(4),
O => \encoded[8]_i_7_n_0\
);
\encoded[9]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => active,
I1 => \encoded[9]_i_2__0_n_0\,
O => \encoded[9]_i_1_n_0\
);
\encoded[9]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"8B"
)
port map (
I0 => \encoded[8]_i_2_n_0\,
I1 => \dc_bias[3]_i_2__0_n_0\,
I2 => \dc_bias[3]_i_5__1_n_0\,
O => \encoded[9]_i_2__0_n_0\
);
\encoded_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \encoded[0]_i_1__0_n_0\,
Q => \encoded_reg_n_0_[0]\,
R => '0'
);
\encoded_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \encoded[1]_i_1__0_n_0\,
Q => \encoded_reg_n_0_[1]\,
R => '0'
);
\encoded_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \encoded[2]_i_1__0_n_0\,
Q => \encoded_reg_n_0_[2]\,
R => '0'
);
\encoded_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \encoded[3]_i_1__0_n_0\,
Q => \encoded_reg_n_0_[3]\,
R => '0'
);
\encoded_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \encoded[4]_i_1__0_n_0\,
Q => \encoded_reg_n_0_[4]\,
R => '0'
);
\encoded_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \encoded[5]_i_1__0_n_0\,
Q => \encoded_reg_n_0_[5]\,
R => '0'
);
\encoded_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \encoded[6]_i_1__0_n_0\,
Q => \encoded_reg_n_0_[6]\,
R => '0'
);
\encoded_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \encoded[7]_i_1__0_n_0\,
Q => \encoded_reg_n_0_[7]\,
R => '0'
);
\encoded_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \encoded[8]_i_1__0_n_0\,
Q => Q(0),
R => '0'
);
\encoded_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \encoded[9]_i_1_n_0\,
Q => Q(1),
R => '0'
);
\shift_green[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => shift_green(0),
I1 => \shift_clock_reg[5]\,
I2 => \encoded_reg_n_0_[0]\,
O => D(0)
);
\shift_green[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => shift_green(1),
I1 => \shift_clock_reg[5]\,
I2 => \encoded_reg_n_0_[1]\,
O => D(1)
);
\shift_green[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => shift_green(2),
I1 => \shift_clock_reg[5]\,
I2 => \encoded_reg_n_0_[2]\,
O => D(2)
);
\shift_green[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => shift_green(3),
I1 => \shift_clock_reg[5]\,
I2 => \encoded_reg_n_0_[3]\,
O => D(3)
);
\shift_green[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => shift_green(4),
I1 => \shift_clock_reg[5]\,
I2 => \encoded_reg_n_0_[4]\,
O => D(4)
);
\shift_green[5]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => shift_green(5),
I1 => \shift_clock_reg[5]\,
I2 => \encoded_reg_n_0_[5]\,
O => D(5)
);
\shift_green[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => shift_green(6),
I1 => \shift_clock_reg[5]\,
I2 => \encoded_reg_n_0_[6]\,
O => D(6)
);
\shift_green[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => shift_green(7),
I1 => \shift_clock_reg[5]\,
I2 => \encoded_reg_n_0_[7]\,
O => D(7)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_zybo_hdmi_0_0_TMDS_encoder_1 is
port (
D : out STD_LOGIC_VECTOR ( 7 downto 0 );
Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
rgb : in STD_LOGIC_VECTOR ( 7 downto 0 );
active : in STD_LOGIC;
data1 : in STD_LOGIC_VECTOR ( 7 downto 0 );
\shift_clock_reg[5]\ : in STD_LOGIC;
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
clk_25 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_zybo_hdmi_0_0_TMDS_encoder_1 : entity is "TMDS_encoder";
end system_zybo_hdmi_0_0_TMDS_encoder_1;
architecture STRUCTURE of system_zybo_hdmi_0_0_TMDS_encoder_1 is
signal \dc_bias[0]_i_1_n_0\ : STD_LOGIC;
signal \dc_bias[0]_i_2_n_0\ : STD_LOGIC;
signal \dc_bias[0]_i_3_n_0\ : STD_LOGIC;
signal \dc_bias[0]_i_4_n_0\ : STD_LOGIC;
signal \dc_bias[0]_i_5_n_0\ : STD_LOGIC;
signal \dc_bias[0]_i_6__0_n_0\ : STD_LOGIC;
signal \dc_bias[1]_i_2_n_0\ : STD_LOGIC;
signal \dc_bias[1]_i_3_n_0\ : STD_LOGIC;
signal \dc_bias[1]_i_4_n_0\ : STD_LOGIC;
signal \dc_bias[1]_i_5__0_n_0\ : STD_LOGIC;
signal \dc_bias[1]_i_6_n_0\ : STD_LOGIC;
signal \dc_bias[1]_i_7_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_10__0_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_11_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_12_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_13_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_14_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_15_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_16_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_17_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_18_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_19_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_1_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_20_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_21_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_22_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_2_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_3_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_4__0_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_5_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_6_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_7__1_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_8_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_9__1_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_10_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_11_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_12_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_13_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_14_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_15_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_16__1_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_17__1_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_18_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_19_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_20__1_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_21__0_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_22_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_23_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_24_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_25_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_26_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_27_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_2_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_3_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_4_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_5__0_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_6_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_7_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_8_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_9_n_0\ : STD_LOGIC;
signal \dc_bias_reg[1]_i_1_n_0\ : STD_LOGIC;
signal \dc_bias_reg_n_0_[0]\ : STD_LOGIC;
signal \dc_bias_reg_n_0_[1]\ : STD_LOGIC;
signal \dc_bias_reg_n_0_[2]\ : STD_LOGIC;
signal encoded : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \encoded[6]_i_2_n_0\ : STD_LOGIC;
signal \encoded[7]_i_2__0_n_0\ : STD_LOGIC;
signal \encoded[7]_i_3_n_0\ : STD_LOGIC;
signal \encoded[8]_i_1_n_0\ : STD_LOGIC;
signal \encoded[9]_i_1__0_n_0\ : STD_LOGIC;
signal \encoded[9]_i_2_n_0\ : STD_LOGIC;
signal \encoded_reg_n_0_[0]\ : STD_LOGIC;
signal \encoded_reg_n_0_[1]\ : STD_LOGIC;
signal \encoded_reg_n_0_[2]\ : STD_LOGIC;
signal \encoded_reg_n_0_[3]\ : STD_LOGIC;
signal \encoded_reg_n_0_[4]\ : STD_LOGIC;
signal \encoded_reg_n_0_[5]\ : STD_LOGIC;
signal \encoded_reg_n_0_[6]\ : STD_LOGIC;
signal \encoded_reg_n_0_[7]\ : STD_LOGIC;
signal p_1_in : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \dc_bias[0]_i_2\ : label is "soft_lutpair45";
attribute SOFT_HLUTNM of \dc_bias[0]_i_4\ : label is "soft_lutpair54";
attribute SOFT_HLUTNM of \dc_bias[0]_i_6__0\ : label is "soft_lutpair50";
attribute SOFT_HLUTNM of \dc_bias[1]_i_7\ : label is "soft_lutpair41";
attribute SOFT_HLUTNM of \dc_bias[2]_i_10__0\ : label is "soft_lutpair46";
attribute SOFT_HLUTNM of \dc_bias[2]_i_12\ : label is "soft_lutpair40";
attribute SOFT_HLUTNM of \dc_bias[2]_i_13\ : label is "soft_lutpair47";
attribute SOFT_HLUTNM of \dc_bias[2]_i_15\ : label is "soft_lutpair47";
attribute SOFT_HLUTNM of \dc_bias[2]_i_16\ : label is "soft_lutpair42";
attribute SOFT_HLUTNM of \dc_bias[2]_i_17\ : label is "soft_lutpair49";
attribute SOFT_HLUTNM of \dc_bias[2]_i_18\ : label is "soft_lutpair39";
attribute SOFT_HLUTNM of \dc_bias[2]_i_19\ : label is "soft_lutpair42";
attribute SOFT_HLUTNM of \dc_bias[2]_i_20\ : label is "soft_lutpair39";
attribute SOFT_HLUTNM of \dc_bias[2]_i_22\ : label is "soft_lutpair44";
attribute SOFT_HLUTNM of \dc_bias[2]_i_8\ : label is "soft_lutpair51";
attribute SOFT_HLUTNM of \dc_bias[3]_i_10\ : label is "soft_lutpair41";
attribute SOFT_HLUTNM of \dc_bias[3]_i_14\ : label is "soft_lutpair44";
attribute SOFT_HLUTNM of \dc_bias[3]_i_16__1\ : label is "soft_lutpair45";
attribute SOFT_HLUTNM of \dc_bias[3]_i_20__1\ : label is "soft_lutpair54";
attribute SOFT_HLUTNM of \dc_bias[3]_i_25\ : label is "soft_lutpair46";
attribute SOFT_HLUTNM of \dc_bias[3]_i_3\ : label is "soft_lutpair51";
attribute SOFT_HLUTNM of \encoded[0]_i_1\ : label is "soft_lutpair43";
attribute SOFT_HLUTNM of \encoded[1]_i_1\ : label is "soft_lutpair49";
attribute SOFT_HLUTNM of \encoded[2]_i_1\ : label is "soft_lutpair43";
attribute SOFT_HLUTNM of \encoded[4]_i_1\ : label is "soft_lutpair52";
attribute SOFT_HLUTNM of \encoded[6]_i_2\ : label is "soft_lutpair40";
attribute SOFT_HLUTNM of \encoded[7]_i_1\ : label is "soft_lutpair48";
attribute SOFT_HLUTNM of \encoded[7]_i_2__0\ : label is "soft_lutpair50";
attribute SOFT_HLUTNM of \encoded[7]_i_3\ : label is "soft_lutpair53";
attribute SOFT_HLUTNM of \encoded[8]_i_1\ : label is "soft_lutpair52";
attribute SOFT_HLUTNM of \encoded[9]_i_1__0\ : label is "soft_lutpair48";
attribute SOFT_HLUTNM of \encoded[9]_i_2\ : label is "soft_lutpair53";
attribute SOFT_HLUTNM of \shift_red[0]_i_1\ : label is "soft_lutpair55";
attribute SOFT_HLUTNM of \shift_red[1]_i_1\ : label is "soft_lutpair56";
attribute SOFT_HLUTNM of \shift_red[2]_i_1\ : label is "soft_lutpair56";
attribute SOFT_HLUTNM of \shift_red[3]_i_1\ : label is "soft_lutpair57";
attribute SOFT_HLUTNM of \shift_red[4]_i_1\ : label is "soft_lutpair58";
attribute SOFT_HLUTNM of \shift_red[5]_i_1\ : label is "soft_lutpair57";
attribute SOFT_HLUTNM of \shift_red[6]_i_1\ : label is "soft_lutpair58";
attribute SOFT_HLUTNM of \shift_red[7]_i_1\ : label is "soft_lutpair55";
begin
\dc_bias[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6F60606F606F6F60"
)
port map (
I0 => \dc_bias_reg_n_0_[0]\,
I1 => \dc_bias[0]_i_2_n_0\,
I2 => \dc_bias[3]_i_6_n_0\,
I3 => \dc_bias[2]_i_4__0_n_0\,
I4 => \dc_bias[0]_i_3_n_0\,
I5 => \dc_bias[0]_i_4_n_0\,
O => \dc_bias[0]_i_1_n_0\
);
\dc_bias[0]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => rgb(1),
I1 => rgb(3),
I2 => \dc_bias[0]_i_5_n_0\,
I3 => \dc_bias[0]_i_6__0_n_0\,
O => \dc_bias[0]_i_2_n_0\
);
\dc_bias[0]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"69969669"
)
port map (
I0 => \encoded[6]_i_2_n_0\,
I1 => rgb(5),
I2 => rgb(0),
I3 => \dc_bias_reg_n_0_[0]\,
I4 => rgb(7),
O => \dc_bias[0]_i_3_n_0\
);
\dc_bias[0]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb(2),
I1 => \dc_bias[3]_i_4_n_0\,
O => \dc_bias[0]_i_4_n_0\
);
\dc_bias[0]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"9669699669969669"
)
port map (
I0 => \encoded[6]_i_2_n_0\,
I1 => rgb(4),
I2 => rgb(5),
I3 => rgb(6),
I4 => rgb(7),
I5 => \dc_bias[3]_i_4_n_0\,
O => \dc_bias[0]_i_5_n_0\
);
\dc_bias[0]_i_6__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9669"
)
port map (
I0 => \dc_bias[3]_i_4_n_0\,
I1 => rgb(4),
I2 => \encoded[6]_i_2_n_0\,
I3 => rgb(6),
O => \dc_bias[0]_i_6__0_n_0\
);
\dc_bias[1]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"CC3CC3CC55555555"
)
port map (
I0 => \dc_bias[1]_i_4_n_0\,
I1 => \dc_bias[1]_i_5__0_n_0\,
I2 => \dc_bias[3]_i_4_n_0\,
I3 => \dc_bias[0]_i_2_n_0\,
I4 => \dc_bias_reg_n_0_[0]\,
I5 => \dc_bias[2]_i_4__0_n_0\,
O => \dc_bias[1]_i_2_n_0\
);
\dc_bias[1]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"F00F0FF099999999"
)
port map (
I0 => \dc_bias[3]_i_16__1_n_0\,
I1 => \dc_bias[1]_i_5__0_n_0\,
I2 => \dc_bias[1]_i_6_n_0\,
I3 => \dc_bias[1]_i_7_n_0\,
I4 => \dc_bias[2]_i_12_n_0\,
I5 => \dc_bias[3]_i_4_n_0\,
O => \dc_bias[1]_i_3_n_0\
);
\dc_bias[1]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"95A9A96A569595A9"
)
port map (
I0 => \dc_bias[2]_i_18_n_0\,
I1 => \dc_bias[2]_i_16_n_0\,
I2 => \dc_bias[2]_i_17_n_0\,
I3 => \dc_bias[2]_i_19_n_0\,
I4 => \dc_bias[2]_i_20_n_0\,
I5 => rgb(7),
O => \dc_bias[1]_i_4_n_0\
);
\dc_bias[1]_i_5__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9996699969996669"
)
port map (
I0 => \dc_bias_reg_n_0_[1]\,
I1 => \dc_bias[3]_i_26_n_0\,
I2 => \dc_bias[0]_i_6__0_n_0\,
I3 => \dc_bias[0]_i_5_n_0\,
I4 => rgb(0),
I5 => \dc_bias[3]_i_25_n_0\,
O => \dc_bias[1]_i_5__0_n_0\
);
\dc_bias[1]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"5CC5355335535CC5"
)
port map (
I0 => \dc_bias[0]_i_6__0_n_0\,
I1 => rgb(0),
I2 => \dc_bias_reg_n_0_[0]\,
I3 => \dc_bias[0]_i_5_n_0\,
I4 => rgb(3),
I5 => rgb(1),
O => \dc_bias[1]_i_6_n_0\
);
\dc_bias[1]_i_7\: unisim.vcomponents.LUT5
generic map(
INIT => X"A665599A"
)
port map (
I0 => \dc_bias[2]_i_13_n_0\,
I1 => \dc_bias[0]_i_5_n_0\,
I2 => \dc_bias_reg_n_0_[0]\,
I3 => rgb(0),
I4 => \dc_bias_reg_n_0_[1]\,
O => \dc_bias[1]_i_7_n_0\
);
\dc_bias[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"B888B8BBB8BBB888"
)
port map (
I0 => \dc_bias[2]_i_2_n_0\,
I1 => \dc_bias[3]_i_6_n_0\,
I2 => \dc_bias[2]_i_3_n_0\,
I3 => \dc_bias[2]_i_4__0_n_0\,
I4 => \dc_bias[2]_i_5_n_0\,
I5 => \dc_bias[2]_i_6_n_0\,
O => \dc_bias[2]_i_1_n_0\
);
\dc_bias[2]_i_10__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"90060690"
)
port map (
I0 => \dc_bias[0]_i_5_n_0\,
I1 => \dc_bias[0]_i_6__0_n_0\,
I2 => rgb(0),
I3 => rgb(1),
I4 => rgb(3),
O => \dc_bias[2]_i_10__0_n_0\
);
\dc_bias[2]_i_11\: unisim.vcomponents.LUT6
generic map(
INIT => X"3AA3ACCAACCA3AA3"
)
port map (
I0 => rgb(0),
I1 => \dc_bias[3]_i_4_n_0\,
I2 => rgb(7),
I3 => \encoded[7]_i_2__0_n_0\,
I4 => \dc_bias[2]_i_22_n_0\,
I5 => rgb(6),
O => \dc_bias[2]_i_11_n_0\
);
\dc_bias[2]_i_12\: unisim.vcomponents.LUT5
generic map(
INIT => X"2DD2B44B"
)
port map (
I0 => rgb(2),
I1 => \dc_bias[3]_i_4_n_0\,
I2 => rgb(0),
I3 => rgb(1),
I4 => rgb(3),
O => \dc_bias[2]_i_12_n_0\
);
\dc_bias[2]_i_13\: unisim.vcomponents.LUT5
generic map(
INIT => X"A59669A5"
)
port map (
I0 => rgb(4),
I1 => rgb(5),
I2 => \encoded[6]_i_2_n_0\,
I3 => \dc_bias[3]_i_4_n_0\,
I4 => rgb(6),
O => \dc_bias[2]_i_13_n_0\
);
\dc_bias[2]_i_14\: unisim.vcomponents.LUT6
generic map(
INIT => X"1771711771171771"
)
port map (
I0 => \dc_bias[3]_i_4_n_0\,
I1 => rgb(7),
I2 => rgb(6),
I3 => rgb(5),
I4 => rgb(4),
I5 => \encoded[6]_i_2_n_0\,
O => \dc_bias[2]_i_14_n_0\
);
\dc_bias[2]_i_15\: unisim.vcomponents.LUT4
generic map(
INIT => X"4BD2"
)
port map (
I0 => \dc_bias[3]_i_4_n_0\,
I1 => rgb(4),
I2 => \encoded[6]_i_2_n_0\,
I3 => rgb(5),
O => \dc_bias[2]_i_15_n_0\
);
\dc_bias[2]_i_16\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => rgb(2),
I1 => rgb(1),
I2 => rgb(0),
O => \dc_bias[2]_i_16_n_0\
);
\dc_bias[2]_i_17\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => rgb(1),
I1 => rgb(0),
I2 => \dc_bias[3]_i_4_n_0\,
O => \dc_bias[2]_i_17_n_0\
);
\dc_bias[2]_i_18\: unisim.vcomponents.LUT5
generic map(
INIT => X"69969696"
)
port map (
I0 => \dc_bias[2]_i_15_n_0\,
I1 => \dc_bias[2]_i_14_n_0\,
I2 => \dc_bias_reg_n_0_[1]\,
I3 => \dc_bias_reg_n_0_[0]\,
I4 => rgb(0),
O => \dc_bias[2]_i_18_n_0\
);
\dc_bias[2]_i_19\: unisim.vcomponents.LUT5
generic map(
INIT => X"96696996"
)
port map (
I0 => rgb(5),
I1 => rgb(2),
I2 => rgb(1),
I3 => rgb(0),
I4 => rgb(3),
O => \dc_bias[2]_i_19_n_0\
);
\dc_bias[2]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"6F60606F"
)
port map (
I0 => \dc_bias[2]_i_7__1_n_0\,
I1 => \dc_bias[3]_i_9_n_0\,
I2 => \dc_bias[3]_i_4_n_0\,
I3 => \dc_bias[2]_i_8_n_0\,
I4 => \dc_bias[2]_i_9__1_n_0\,
O => \dc_bias[2]_i_2_n_0\
);
\dc_bias[2]_i_20\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb(0),
I1 => \dc_bias_reg_n_0_[0]\,
O => \dc_bias[2]_i_20_n_0\
);
\dc_bias[2]_i_21\: unisim.vcomponents.LUT5
generic map(
INIT => X"96696996"
)
port map (
I0 => rgb(6),
I1 => \dc_bias[2]_i_22_n_0\,
I2 => \encoded[7]_i_2__0_n_0\,
I3 => rgb(7),
I4 => rgb(0),
O => \dc_bias[2]_i_21_n_0\
);
\dc_bias[2]_i_22\: unisim.vcomponents.LUT5
generic map(
INIT => X"96696996"
)
port map (
I0 => rgb(4),
I1 => rgb(2),
I2 => rgb(1),
I3 => rgb(0),
I4 => rgb(3),
O => \dc_bias[2]_i_22_n_0\
);
\dc_bias[2]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"56569556566A5656"
)
port map (
I0 => \dc_bias[2]_i_8_n_0\,
I1 => \dc_bias_reg_n_0_[1]\,
I2 => \dc_bias[3]_i_17__1_n_0\,
I3 => \dc_bias[3]_i_4_n_0\,
I4 => \dc_bias[0]_i_2_n_0\,
I5 => \dc_bias_reg_n_0_[0]\,
O => \dc_bias[2]_i_3_n_0\
);
\dc_bias[2]_i_4__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"5556566A"
)
port map (
I0 => p_1_in,
I1 => \dc_bias[2]_i_10__0_n_0\,
I2 => \dc_bias[2]_i_11_n_0\,
I3 => \dc_bias[2]_i_12_n_0\,
I4 => \dc_bias[2]_i_13_n_0\,
O => \dc_bias[2]_i_4__0_n_0\
);
\dc_bias[2]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"D44242422BBDBDBD"
)
port map (
I0 => \dc_bias[2]_i_14_n_0\,
I1 => \dc_bias[2]_i_15_n_0\,
I2 => \dc_bias_reg_n_0_[1]\,
I3 => \dc_bias_reg_n_0_[0]\,
I4 => rgb(0),
I5 => \dc_bias_reg_n_0_[2]\,
O => \dc_bias[2]_i_5_n_0\
);
\dc_bias[2]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"F7F1F170EFF7F7F1"
)
port map (
I0 => \dc_bias[2]_i_16_n_0\,
I1 => \dc_bias[2]_i_17_n_0\,
I2 => \dc_bias[2]_i_18_n_0\,
I3 => \dc_bias[2]_i_19_n_0\,
I4 => \dc_bias[2]_i_20_n_0\,
I5 => rgb(7),
O => \dc_bias[2]_i_6_n_0\
);
\dc_bias[2]_i_7__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"5565656666A6A6AA"
)
port map (
I0 => \dc_bias_reg_n_0_[2]\,
I1 => \dc_bias[2]_i_13_n_0\,
I2 => \dc_bias[0]_i_5_n_0\,
I3 => \dc_bias_reg_n_0_[0]\,
I4 => rgb(0),
I5 => \dc_bias_reg_n_0_[1]\,
O => \dc_bias[2]_i_7__1_n_0\
);
\dc_bias[2]_i_8\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \dc_bias_reg_n_0_[2]\,
I1 => \dc_bias[3]_i_15_n_0\,
O => \dc_bias[2]_i_8_n_0\
);
\dc_bias[2]_i_9__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"41141414417D7D14"
)
port map (
I0 => \dc_bias_reg_n_0_[1]\,
I1 => \dc_bias[3]_i_26_n_0\,
I2 => \dc_bias[2]_i_11_n_0\,
I3 => \dc_bias[2]_i_21_n_0\,
I4 => \dc_bias[3]_i_25_n_0\,
I5 => \dc_bias_reg_n_0_[0]\,
O => \dc_bias[2]_i_9__1_n_0\
);
\dc_bias[3]_i_10\: unisim.vcomponents.LUT5
generic map(
INIT => X"15017F57"
)
port map (
I0 => \dc_bias_reg_n_0_[1]\,
I1 => rgb(0),
I2 => \dc_bias_reg_n_0_[0]\,
I3 => \dc_bias[0]_i_5_n_0\,
I4 => \dc_bias[2]_i_13_n_0\,
O => \dc_bias[3]_i_10_n_0\
);
\dc_bias[3]_i_11\: unisim.vcomponents.LUT6
generic map(
INIT => X"171717FF17FFFFFF"
)
port map (
I0 => rgb(1),
I1 => rgb(3),
I2 => rgb(2),
I3 => rgb(6),
I4 => rgb(5),
I5 => rgb(4),
O => \dc_bias[3]_i_11_n_0\
);
\dc_bias[3]_i_12\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => rgb(6),
I1 => rgb(5),
I2 => rgb(4),
O => \dc_bias[3]_i_12_n_0\
);
\dc_bias[3]_i_13\: unisim.vcomponents.LUT6
generic map(
INIT => X"171717E817E8E8E8"
)
port map (
I0 => rgb(1),
I1 => rgb(3),
I2 => rgb(2),
I3 => rgb(6),
I4 => rgb(5),
I5 => rgb(4),
O => \dc_bias[3]_i_13_n_0\
);
\dc_bias[3]_i_14\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => rgb(3),
I1 => rgb(2),
I2 => rgb(1),
O => \dc_bias[3]_i_14_n_0\
);
\dc_bias[3]_i_15\: unisim.vcomponents.LUT6
generic map(
INIT => X"EEE78EEE8EEE888E"
)
port map (
I0 => \dc_bias[2]_i_13_n_0\,
I1 => \dc_bias[2]_i_12_n_0\,
I2 => \dc_bias[0]_i_6__0_n_0\,
I3 => \dc_bias[0]_i_5_n_0\,
I4 => rgb(0),
I5 => \dc_bias[3]_i_25_n_0\,
O => \dc_bias[3]_i_15_n_0\
);
\dc_bias[3]_i_16__1\: unisim.vcomponents.LUT5
generic map(
INIT => X"EBBEBEEB"
)
port map (
I0 => \dc_bias_reg_n_0_[0]\,
I1 => \dc_bias[0]_i_6__0_n_0\,
I2 => \dc_bias[0]_i_5_n_0\,
I3 => rgb(3),
I4 => rgb(1),
O => \dc_bias[3]_i_16__1_n_0\
);
\dc_bias[3]_i_17__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"90F6F66F6F090990"
)
port map (
I0 => rgb(3),
I1 => rgb(1),
I2 => rgb(0),
I3 => \dc_bias[0]_i_5_n_0\,
I4 => \dc_bias[0]_i_6__0_n_0\,
I5 => \dc_bias[3]_i_26_n_0\,
O => \dc_bias[3]_i_17__1_n_0\
);
\dc_bias[3]_i_18\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFFF799E799EFFF7"
)
port map (
I0 => \dc_bias[3]_i_25_n_0\,
I1 => rgb(0),
I2 => \dc_bias[0]_i_5_n_0\,
I3 => \dc_bias[0]_i_6__0_n_0\,
I4 => \dc_bias[2]_i_12_n_0\,
I5 => \dc_bias[2]_i_13_n_0\,
O => \dc_bias[3]_i_18_n_0\
);
\dc_bias[3]_i_19\: unisim.vcomponents.LUT6
generic map(
INIT => X"E00E0EE00EE0E00E"
)
port map (
I0 => \dc_bias[3]_i_16__1_n_0\,
I1 => \dc_bias[3]_i_4_n_0\,
I2 => \dc_bias[2]_i_10__0_n_0\,
I3 => \dc_bias[2]_i_11_n_0\,
I4 => \dc_bias[3]_i_26_n_0\,
I5 => \dc_bias_reg_n_0_[1]\,
O => \dc_bias[3]_i_19_n_0\
);
\dc_bias[3]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"B8FFB8FFB8FFB800"
)
port map (
I0 => \dc_bias[3]_i_3_n_0\,
I1 => \dc_bias[3]_i_4_n_0\,
I2 => \dc_bias[3]_i_5__0_n_0\,
I3 => \dc_bias[3]_i_6_n_0\,
I4 => \dc_bias[3]_i_7_n_0\,
I5 => \dc_bias[3]_i_8_n_0\,
O => \dc_bias[3]_i_2_n_0\
);
\dc_bias[3]_i_20__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"DF"
)
port map (
I0 => \dc_bias_reg_n_0_[0]\,
I1 => \dc_bias[0]_i_2_n_0\,
I2 => \dc_bias[3]_i_4_n_0\,
O => \dc_bias[3]_i_20__1_n_0\
);
\dc_bias[3]_i_21__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"A96A6A5600000000"
)
port map (
I0 => \dc_bias[3]_i_26_n_0\,
I1 => \dc_bias[0]_i_6__0_n_0\,
I2 => \dc_bias[0]_i_5_n_0\,
I3 => rgb(0),
I4 => \dc_bias[3]_i_25_n_0\,
I5 => \dc_bias_reg_n_0_[1]\,
O => \dc_bias[3]_i_21__0_n_0\
);
\dc_bias[3]_i_22\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFAEAE8AAE8AAE8A"
)
port map (
I0 => \dc_bias_reg_n_0_[2]\,
I1 => \dc_bias[2]_i_15_n_0\,
I2 => \dc_bias[2]_i_14_n_0\,
I3 => \dc_bias_reg_n_0_[1]\,
I4 => \dc_bias_reg_n_0_[0]\,
I5 => rgb(0),
O => \dc_bias[3]_i_22_n_0\
);
\dc_bias[3]_i_23\: unisim.vcomponents.LUT6
generic map(
INIT => X"02BF002B002B0002"
)
port map (
I0 => rgb(7),
I1 => \dc_bias[2]_i_20_n_0\,
I2 => \dc_bias[2]_i_19_n_0\,
I3 => \dc_bias[2]_i_18_n_0\,
I4 => \dc_bias[2]_i_17_n_0\,
I5 => \dc_bias[2]_i_16_n_0\,
O => \dc_bias[3]_i_23_n_0\
);
\dc_bias[3]_i_24\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF5775D55D"
)
port map (
I0 => \dc_bias[2]_i_18_n_0\,
I1 => \dc_bias[3]_i_4_n_0\,
I2 => rgb(0),
I3 => rgb(1),
I4 => rgb(2),
I5 => \dc_bias[3]_i_27_n_0\,
O => \dc_bias[3]_i_24_n_0\
);
\dc_bias[3]_i_25\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => rgb(3),
I1 => rgb(1),
I2 => rgb(0),
O => \dc_bias[3]_i_25_n_0\
);
\dc_bias[3]_i_26\: unisim.vcomponents.LUT6
generic map(
INIT => X"963CC39669C33C69"
)
port map (
I0 => rgb(3),
I1 => rgb(1),
I2 => rgb(0),
I3 => \dc_bias[3]_i_4_n_0\,
I4 => rgb(2),
I5 => \dc_bias[2]_i_13_n_0\,
O => \dc_bias[3]_i_26_n_0\
);
\dc_bias[3]_i_27\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFBEBEFF"
)
port map (
I0 => \dc_bias[0]_i_4_n_0\,
I1 => \encoded[6]_i_2_n_0\,
I2 => rgb(5),
I3 => rgb(0),
I4 => \dc_bias_reg_n_0_[0]\,
I5 => rgb(7),
O => \dc_bias[3]_i_27_n_0\
);
\dc_bias[3]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"E718"
)
port map (
I0 => \dc_bias[3]_i_9_n_0\,
I1 => \dc_bias[3]_i_10_n_0\,
I2 => \dc_bias_reg_n_0_[2]\,
I3 => p_1_in,
O => \dc_bias[3]_i_3_n_0\
);
\dc_bias[3]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"0022AAAA32EAAAAA"
)
port map (
I0 => \dc_bias[3]_i_11_n_0\,
I1 => \dc_bias[3]_i_12_n_0\,
I2 => rgb(0),
I3 => rgb(7),
I4 => \dc_bias[3]_i_13_n_0\,
I5 => \dc_bias[3]_i_14_n_0\,
O => \dc_bias[3]_i_4_n_0\
);
\dc_bias[3]_i_5__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"5656566A566A6A6A"
)
port map (
I0 => \dc_bias[2]_i_4__0_n_0\,
I1 => \dc_bias[3]_i_15_n_0\,
I2 => \dc_bias_reg_n_0_[2]\,
I3 => \dc_bias[3]_i_16__1_n_0\,
I4 => \dc_bias[3]_i_17__1_n_0\,
I5 => \dc_bias_reg_n_0_[1]\,
O => \dc_bias[3]_i_5__0_n_0\
);
\dc_bias[3]_i_6\: unisim.vcomponents.LUT5
generic map(
INIT => X"0001FFFF"
)
port map (
I0 => \dc_bias_reg_n_0_[1]\,
I1 => p_1_in,
I2 => \dc_bias_reg_n_0_[2]\,
I3 => \dc_bias_reg_n_0_[0]\,
I4 => \dc_bias[3]_i_18_n_0\,
O => \dc_bias[3]_i_6_n_0\
);
\dc_bias[3]_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"0C0000400040C0CC"
)
port map (
I0 => \dc_bias[3]_i_19_n_0\,
I1 => \dc_bias[2]_i_4__0_n_0\,
I2 => \dc_bias[3]_i_20__1_n_0\,
I3 => \dc_bias[3]_i_21__0_n_0\,
I4 => \dc_bias_reg_n_0_[2]\,
I5 => \dc_bias[3]_i_15_n_0\,
O => \dc_bias[3]_i_7_n_0\
);
\dc_bias[3]_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000096969996"
)
port map (
I0 => p_1_in,
I1 => \dc_bias[3]_i_22_n_0\,
I2 => \dc_bias[3]_i_23_n_0\,
I3 => \dc_bias[3]_i_24_n_0\,
I4 => \dc_bias[2]_i_5_n_0\,
I5 => \dc_bias[2]_i_4__0_n_0\,
O => \dc_bias[3]_i_8_n_0\
);
\dc_bias[3]_i_9\: unisim.vcomponents.LUT3
generic map(
INIT => X"17"
)
port map (
I0 => \dc_bias[1]_i_6_n_0\,
I1 => \dc_bias[2]_i_12_n_0\,
I2 => \dc_bias[1]_i_7_n_0\,
O => \dc_bias[3]_i_9_n_0\
);
\dc_bias_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25,
CE => '1',
D => \dc_bias[0]_i_1_n_0\,
Q => \dc_bias_reg_n_0_[0]\,
R => SR(0)
);
\dc_bias_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25,
CE => '1',
D => \dc_bias_reg[1]_i_1_n_0\,
Q => \dc_bias_reg_n_0_[1]\,
R => SR(0)
);
\dc_bias_reg[1]_i_1\: unisim.vcomponents.MUXF7
port map (
I0 => \dc_bias[1]_i_2_n_0\,
I1 => \dc_bias[1]_i_3_n_0\,
O => \dc_bias_reg[1]_i_1_n_0\,
S => \dc_bias[3]_i_6_n_0\
);
\dc_bias_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25,
CE => '1',
D => \dc_bias[2]_i_1_n_0\,
Q => \dc_bias_reg_n_0_[2]\,
R => SR(0)
);
\dc_bias_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25,
CE => '1',
D => \dc_bias[3]_i_2_n_0\,
Q => p_1_in,
R => SR(0)
);
\encoded[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"28"
)
port map (
I0 => active,
I1 => rgb(0),
I2 => \encoded[9]_i_2_n_0\,
O => encoded(0)
);
\encoded[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"8228"
)
port map (
I0 => active,
I1 => \encoded[7]_i_3_n_0\,
I2 => rgb(1),
I3 => rgb(0),
O => encoded(1)
);
\encoded[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7DD7D77D"
)
port map (
I0 => active,
I1 => rgb(0),
I2 => rgb(1),
I3 => rgb(2),
I4 => \encoded[9]_i_2_n_0\,
O => encoded(2)
);
\encoded[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"8228288228828228"
)
port map (
I0 => active,
I1 => rgb(2),
I2 => rgb(1),
I3 => rgb(0),
I4 => rgb(3),
I5 => \encoded[7]_i_3_n_0\,
O => encoded(3)
);
\encoded[4]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7DD7"
)
port map (
I0 => active,
I1 => \encoded[6]_i_2_n_0\,
I2 => rgb(4),
I3 => \encoded[9]_i_2_n_0\,
O => encoded(4)
);
\encoded[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"82282882"
)
port map (
I0 => active,
I1 => rgb(4),
I2 => rgb(5),
I3 => \encoded[6]_i_2_n_0\,
I4 => \encoded[7]_i_3_n_0\,
O => encoded(5)
);
\encoded[6]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"7DD7D77DD77D7DD7"
)
port map (
I0 => active,
I1 => rgb(6),
I2 => rgb(5),
I3 => rgb(4),
I4 => \encoded[6]_i_2_n_0\,
I5 => \encoded[9]_i_2_n_0\,
O => encoded(6)
);
\encoded[6]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9669"
)
port map (
I0 => rgb(3),
I1 => rgb(0),
I2 => rgb(1),
I3 => rgb(2),
O => \encoded[6]_i_2_n_0\
);
\encoded[7]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"8228"
)
port map (
I0 => active,
I1 => \encoded[7]_i_2__0_n_0\,
I2 => rgb(7),
I3 => \encoded[7]_i_3_n_0\,
O => encoded(7)
);
\encoded[7]_i_2__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9669"
)
port map (
I0 => \encoded[6]_i_2_n_0\,
I1 => rgb(4),
I2 => rgb(5),
I3 => rgb(6),
O => \encoded[7]_i_2__0_n_0\
);
\encoded[7]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"41"
)
port map (
I0 => \dc_bias[3]_i_6_n_0\,
I1 => \dc_bias[2]_i_4__0_n_0\,
I2 => \dc_bias[3]_i_4_n_0\,
O => \encoded[7]_i_3_n_0\
);
\encoded[8]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \dc_bias[3]_i_4_n_0\,
I1 => active,
O => \encoded[8]_i_1_n_0\
);
\encoded[9]_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \encoded[9]_i_2_n_0\,
I1 => active,
O => \encoded[9]_i_1__0_n_0\
);
\encoded[9]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"74"
)
port map (
I0 => \dc_bias[3]_i_4_n_0\,
I1 => \dc_bias[3]_i_6_n_0\,
I2 => \dc_bias[2]_i_4__0_n_0\,
O => \encoded[9]_i_2_n_0\
);
\encoded_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => encoded(0),
Q => \encoded_reg_n_0_[0]\,
R => '0'
);
\encoded_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => encoded(1),
Q => \encoded_reg_n_0_[1]\,
R => '0'
);
\encoded_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => encoded(2),
Q => \encoded_reg_n_0_[2]\,
R => '0'
);
\encoded_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => encoded(3),
Q => \encoded_reg_n_0_[3]\,
R => '0'
);
\encoded_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => encoded(4),
Q => \encoded_reg_n_0_[4]\,
R => '0'
);
\encoded_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => encoded(5),
Q => \encoded_reg_n_0_[5]\,
R => '0'
);
\encoded_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => encoded(6),
Q => \encoded_reg_n_0_[6]\,
R => '0'
);
\encoded_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => encoded(7),
Q => \encoded_reg_n_0_[7]\,
R => '0'
);
\encoded_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \encoded[8]_i_1_n_0\,
Q => Q(0),
R => '0'
);
\encoded_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \encoded[9]_i_1__0_n_0\,
Q => Q(1),
R => '0'
);
\shift_red[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => data1(0),
I1 => \shift_clock_reg[5]\,
I2 => \encoded_reg_n_0_[0]\,
O => D(0)
);
\shift_red[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => data1(1),
I1 => \shift_clock_reg[5]\,
I2 => \encoded_reg_n_0_[1]\,
O => D(1)
);
\shift_red[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => data1(2),
I1 => \shift_clock_reg[5]\,
I2 => \encoded_reg_n_0_[2]\,
O => D(2)
);
\shift_red[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => data1(3),
I1 => \shift_clock_reg[5]\,
I2 => \encoded_reg_n_0_[3]\,
O => D(3)
);
\shift_red[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => data1(4),
I1 => \shift_clock_reg[5]\,
I2 => \encoded_reg_n_0_[4]\,
O => D(4)
);
\shift_red[5]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => data1(5),
I1 => \shift_clock_reg[5]\,
I2 => \encoded_reg_n_0_[5]\,
O => D(5)
);
\shift_red[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => data1(6),
I1 => \shift_clock_reg[5]\,
I2 => \encoded_reg_n_0_[6]\,
O => D(6)
);
\shift_red[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => data1(7),
I1 => \shift_clock_reg[5]\,
I2 => \encoded_reg_n_0_[7]\,
O => D(7)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_zybo_hdmi_0_0_dvid is
port (
red_s : out STD_LOGIC;
green_s : out STD_LOGIC;
blue_s : out STD_LOGIC;
clock_s : out STD_LOGIC;
clk_125 : in STD_LOGIC;
rgb : in STD_LOGIC_VECTOR ( 23 downto 0 );
active : in STD_LOGIC;
hsync : in STD_LOGIC;
vsync : in STD_LOGIC;
clk_25 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_zybo_hdmi_0_0_dvid : entity is "dvid";
end system_zybo_hdmi_0_0_dvid;
architecture STRUCTURE of system_zybo_hdmi_0_0_dvid is
signal D0 : STD_LOGIC;
signal D1 : STD_LOGIC;
signal TMDS_encoder_BLUE_n_0 : STD_LOGIC;
signal TMDS_encoder_BLUE_n_10 : STD_LOGIC;
signal TMDS_encoder_BLUE_n_9 : STD_LOGIC;
signal TMDS_encoder_GREEN_n_8 : STD_LOGIC;
signal TMDS_encoder_GREEN_n_9 : STD_LOGIC;
signal TMDS_encoder_RED_n_8 : STD_LOGIC;
signal TMDS_encoder_RED_n_9 : STD_LOGIC;
signal clk_dvin : STD_LOGIC;
signal data1 : STD_LOGIC_VECTOR ( 7 downto 0 );
signal shift_blue : STD_LOGIC_VECTOR ( 9 downto 2 );
signal shift_blue_0 : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \shift_blue_reg_n_0_[0]\ : STD_LOGIC;
signal \shift_blue_reg_n_0_[1]\ : STD_LOGIC;
signal shift_clock : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \shift_clock_reg_n_0_[2]\ : STD_LOGIC;
signal \shift_clock_reg_n_0_[3]\ : STD_LOGIC;
signal \shift_clock_reg_n_0_[4]\ : STD_LOGIC;
signal \shift_clock_reg_n_0_[5]\ : STD_LOGIC;
signal \shift_clock_reg_n_0_[6]\ : STD_LOGIC;
signal \shift_clock_reg_n_0_[7]\ : STD_LOGIC;
signal \shift_clock_reg_n_0_[8]\ : STD_LOGIC;
signal \shift_clock_reg_n_0_[9]\ : STD_LOGIC;
signal shift_green : STD_LOGIC_VECTOR ( 9 downto 2 );
signal shift_green_1 : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \shift_green_reg_n_0_[0]\ : STD_LOGIC;
signal \shift_green_reg_n_0_[1]\ : STD_LOGIC;
signal shift_red : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \shift_red[9]_i_1_n_0\ : STD_LOGIC;
signal \shift_red[9]_i_2_n_0\ : STD_LOGIC;
signal NLW_ODDR2_BLUE_R_UNCONNECTED : STD_LOGIC;
signal NLW_ODDR2_BLUE_S_UNCONNECTED : STD_LOGIC;
signal NLW_ODDR2_CLK_R_UNCONNECTED : STD_LOGIC;
signal NLW_ODDR2_CLK_S_UNCONNECTED : STD_LOGIC;
signal NLW_ODDR2_GREEN_R_UNCONNECTED : STD_LOGIC;
signal NLW_ODDR2_GREEN_S_UNCONNECTED : STD_LOGIC;
signal NLW_ODDR2_RED_R_UNCONNECTED : STD_LOGIC;
signal NLW_ODDR2_RED_S_UNCONNECTED : STD_LOGIC;
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of ODDR2_BLUE : label is "ODDR2";
attribute XILINX_TRANSFORM_PINMAP : string;
attribute XILINX_TRANSFORM_PINMAP of ODDR2_BLUE : label is "D0:D1 D1:D2 C0:C";
attribute \__SRVAL\ : string;
attribute \__SRVAL\ of ODDR2_BLUE : label is "TRUE";
attribute box_type : string;
attribute box_type of ODDR2_BLUE : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of ODDR2_CLK : label is "ODDR2";
attribute XILINX_TRANSFORM_PINMAP of ODDR2_CLK : label is "D0:D1 D1:D2 C0:C";
attribute \__SRVAL\ of ODDR2_CLK : label is "TRUE";
attribute box_type of ODDR2_CLK : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of ODDR2_GREEN : label is "ODDR2";
attribute XILINX_TRANSFORM_PINMAP of ODDR2_GREEN : label is "D0:D1 D1:D2 C0:C";
attribute \__SRVAL\ of ODDR2_GREEN : label is "TRUE";
attribute box_type of ODDR2_GREEN : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of ODDR2_RED : label is "ODDR2";
attribute XILINX_TRANSFORM_PINMAP of ODDR2_RED : label is "D0:D1 D1:D2 C0:C";
attribute \__SRVAL\ of ODDR2_RED : label is "TRUE";
attribute box_type of ODDR2_RED : label is "PRIMITIVE";
begin
ODDR2_BLUE: unisim.vcomponents.ODDR
generic map(
DDR_CLK_EDGE => "SAME_EDGE",
INIT => '0',
SRTYPE => "ASYNC"
)
port map (
C => clk_125,
CE => '1',
D1 => \shift_blue_reg_n_0_[0]\,
D2 => \shift_blue_reg_n_0_[1]\,
Q => blue_s,
R => NLW_ODDR2_BLUE_R_UNCONNECTED,
S => NLW_ODDR2_BLUE_S_UNCONNECTED
);
ODDR2_CLK: unisim.vcomponents.ODDR
generic map(
DDR_CLK_EDGE => "SAME_EDGE",
INIT => '0',
SRTYPE => "ASYNC"
)
port map (
C => clk_125,
CE => '1',
D1 => shift_clock(0),
D2 => shift_clock(1),
Q => clock_s,
R => NLW_ODDR2_CLK_R_UNCONNECTED,
S => NLW_ODDR2_CLK_S_UNCONNECTED
);
ODDR2_GREEN: unisim.vcomponents.ODDR
generic map(
DDR_CLK_EDGE => "SAME_EDGE",
INIT => '0',
SRTYPE => "ASYNC"
)
port map (
C => clk_125,
CE => '1',
D1 => \shift_green_reg_n_0_[0]\,
D2 => \shift_green_reg_n_0_[1]\,
Q => green_s,
R => NLW_ODDR2_GREEN_R_UNCONNECTED,
S => NLW_ODDR2_GREEN_S_UNCONNECTED
);
ODDR2_RED: unisim.vcomponents.ODDR
generic map(
DDR_CLK_EDGE => "SAME_EDGE",
INIT => '0',
SRTYPE => "ASYNC"
)
port map (
C => clk_125,
CE => '1',
D1 => D0,
D2 => D1,
Q => red_s,
R => NLW_ODDR2_RED_R_UNCONNECTED,
S => NLW_ODDR2_RED_S_UNCONNECTED
);
ODDR2_RED_i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => clk_125,
O => clk_dvin
);
TMDS_encoder_BLUE: entity work.system_zybo_hdmi_0_0_TMDS_encoder
port map (
D(7 downto 0) => shift_blue_0(7 downto 0),
Q(1) => TMDS_encoder_BLUE_n_9,
Q(0) => TMDS_encoder_BLUE_n_10,
SR(0) => TMDS_encoder_BLUE_n_0,
active => active,
clk_25 => clk_25,
hsync => hsync,
rgb(7 downto 0) => rgb(7 downto 0),
shift_blue(7 downto 0) => shift_blue(9 downto 2),
\shift_clock_reg[5]\ => \shift_red[9]_i_1_n_0\,
vsync => vsync
);
TMDS_encoder_GREEN: entity work.system_zybo_hdmi_0_0_TMDS_encoder_0
port map (
D(7 downto 0) => shift_green_1(7 downto 0),
Q(1) => TMDS_encoder_GREEN_n_8,
Q(0) => TMDS_encoder_GREEN_n_9,
SR(0) => TMDS_encoder_BLUE_n_0,
active => active,
clk_25 => clk_25,
rgb(7 downto 0) => rgb(15 downto 8),
\shift_clock_reg[5]\ => \shift_red[9]_i_1_n_0\,
shift_green(7 downto 0) => shift_green(9 downto 2)
);
TMDS_encoder_RED: entity work.system_zybo_hdmi_0_0_TMDS_encoder_1
port map (
D(7 downto 0) => shift_red(7 downto 0),
Q(1) => TMDS_encoder_RED_n_8,
Q(0) => TMDS_encoder_RED_n_9,
SR(0) => TMDS_encoder_BLUE_n_0,
active => active,
clk_25 => clk_25,
data1(7 downto 0) => data1(7 downto 0),
rgb(7 downto 0) => rgb(23 downto 16),
\shift_clock_reg[5]\ => \shift_red[9]_i_1_n_0\
);
\shift_blue_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_125,
CE => '1',
D => shift_blue_0(0),
Q => \shift_blue_reg_n_0_[0]\,
R => '0'
);
\shift_blue_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_125,
CE => '1',
D => shift_blue_0(1),
Q => \shift_blue_reg_n_0_[1]\,
R => '0'
);
\shift_blue_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_125,
CE => '1',
D => shift_blue_0(2),
Q => shift_blue(2),
R => '0'
);
\shift_blue_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_125,
CE => '1',
D => shift_blue_0(3),
Q => shift_blue(3),
R => '0'
);
\shift_blue_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_125,
CE => '1',
D => shift_blue_0(4),
Q => shift_blue(4),
R => '0'
);
\shift_blue_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_125,
CE => '1',
D => shift_blue_0(5),
Q => shift_blue(5),
R => '0'
);
\shift_blue_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_125,
CE => '1',
D => shift_blue_0(6),
Q => shift_blue(6),
R => '0'
);
\shift_blue_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_125,
CE => '1',
D => shift_blue_0(7),
Q => shift_blue(7),
R => '0'
);
\shift_blue_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_125,
CE => '1',
D => TMDS_encoder_BLUE_n_10,
Q => shift_blue(8),
R => \shift_red[9]_i_1_n_0\
);
\shift_blue_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_125,
CE => '1',
D => TMDS_encoder_BLUE_n_9,
Q => shift_blue(9),
R => \shift_red[9]_i_1_n_0\
);
\shift_clock_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_125,
CE => '1',
D => \shift_clock_reg_n_0_[2]\,
Q => shift_clock(0),
R => '0'
);
\shift_clock_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_125,
CE => '1',
D => \shift_clock_reg_n_0_[3]\,
Q => shift_clock(1),
R => '0'
);
\shift_clock_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_125,
CE => '1',
D => \shift_clock_reg_n_0_[4]\,
Q => \shift_clock_reg_n_0_[2]\,
R => '0'
);
\shift_clock_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_125,
CE => '1',
D => \shift_clock_reg_n_0_[5]\,
Q => \shift_clock_reg_n_0_[3]\,
R => '0'
);
\shift_clock_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_125,
CE => '1',
D => \shift_clock_reg_n_0_[6]\,
Q => \shift_clock_reg_n_0_[4]\,
R => '0'
);
\shift_clock_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_125,
CE => '1',
D => \shift_clock_reg_n_0_[7]\,
Q => \shift_clock_reg_n_0_[5]\,
R => '0'
);
\shift_clock_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_125,
CE => '1',
D => \shift_clock_reg_n_0_[8]\,
Q => \shift_clock_reg_n_0_[6]\,
R => '0'
);
\shift_clock_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_125,
CE => '1',
D => \shift_clock_reg_n_0_[9]\,
Q => \shift_clock_reg_n_0_[7]\,
R => '0'
);
\shift_clock_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_125,
CE => '1',
D => shift_clock(0),
Q => \shift_clock_reg_n_0_[8]\,
R => '0'
);
\shift_clock_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_125,
CE => '1',
D => shift_clock(1),
Q => \shift_clock_reg_n_0_[9]\,
R => '0'
);
\shift_green_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_125,
CE => '1',
D => shift_green_1(0),
Q => \shift_green_reg_n_0_[0]\,
R => '0'
);
\shift_green_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_125,
CE => '1',
D => shift_green_1(1),
Q => \shift_green_reg_n_0_[1]\,
R => '0'
);
\shift_green_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_125,
CE => '1',
D => shift_green_1(2),
Q => shift_green(2),
R => '0'
);
\shift_green_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_125,
CE => '1',
D => shift_green_1(3),
Q => shift_green(3),
R => '0'
);
\shift_green_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_125,
CE => '1',
D => shift_green_1(4),
Q => shift_green(4),
R => '0'
);
\shift_green_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_125,
CE => '1',
D => shift_green_1(5),
Q => shift_green(5),
R => '0'
);
\shift_green_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_125,
CE => '1',
D => shift_green_1(6),
Q => shift_green(6),
R => '0'
);
\shift_green_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_125,
CE => '1',
D => shift_green_1(7),
Q => shift_green(7),
R => '0'
);
\shift_green_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_125,
CE => '1',
D => TMDS_encoder_GREEN_n_9,
Q => shift_green(8),
R => \shift_red[9]_i_1_n_0\
);
\shift_green_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_125,
CE => '1',
D => TMDS_encoder_GREEN_n_8,
Q => shift_green(9),
R => \shift_red[9]_i_1_n_0\
);
\shift_red[9]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"EFFFFFFF"
)
port map (
I0 => \shift_red[9]_i_2_n_0\,
I1 => \shift_clock_reg_n_0_[5]\,
I2 => \shift_clock_reg_n_0_[4]\,
I3 => \shift_clock_reg_n_0_[2]\,
I4 => \shift_clock_reg_n_0_[3]\,
O => \shift_red[9]_i_1_n_0\
);
\shift_red[9]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFEFFFFFFFFFFFF"
)
port map (
I0 => \shift_clock_reg_n_0_[8]\,
I1 => \shift_clock_reg_n_0_[9]\,
I2 => \shift_clock_reg_n_0_[6]\,
I3 => \shift_clock_reg_n_0_[7]\,
I4 => shift_clock(1),
I5 => shift_clock(0),
O => \shift_red[9]_i_2_n_0\
);
\shift_red_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_125,
CE => '1',
D => shift_red(0),
Q => D0,
R => '0'
);
\shift_red_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_125,
CE => '1',
D => shift_red(1),
Q => D1,
R => '0'
);
\shift_red_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_125,
CE => '1',
D => shift_red(2),
Q => data1(0),
R => '0'
);
\shift_red_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_125,
CE => '1',
D => shift_red(3),
Q => data1(1),
R => '0'
);
\shift_red_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_125,
CE => '1',
D => shift_red(4),
Q => data1(2),
R => '0'
);
\shift_red_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_125,
CE => '1',
D => shift_red(5),
Q => data1(3),
R => '0'
);
\shift_red_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_125,
CE => '1',
D => shift_red(6),
Q => data1(4),
R => '0'
);
\shift_red_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_125,
CE => '1',
D => shift_red(7),
Q => data1(5),
R => '0'
);
\shift_red_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_125,
CE => '1',
D => TMDS_encoder_RED_n_9,
Q => data1(6),
R => \shift_red[9]_i_1_n_0\
);
\shift_red_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_125,
CE => '1',
D => TMDS_encoder_RED_n_8,
Q => data1(7),
R => \shift_red[9]_i_1_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_zybo_hdmi_0_0_zybo_hdmi is
port (
tmds : out STD_LOGIC_VECTOR ( 3 downto 0 );
tmdsb : out STD_LOGIC_VECTOR ( 3 downto 0 );
rgb : in STD_LOGIC_VECTOR ( 23 downto 0 );
active : in STD_LOGIC;
hsync : in STD_LOGIC;
vsync : in STD_LOGIC;
clk_125 : in STD_LOGIC;
clk_25 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_zybo_hdmi_0_0_zybo_hdmi : entity is "zybo_hdmi";
end system_zybo_hdmi_0_0_zybo_hdmi;
architecture STRUCTURE of system_zybo_hdmi_0_0_zybo_hdmi is
signal blue_s : STD_LOGIC;
signal clock_s : STD_LOGIC;
signal green_s : STD_LOGIC;
signal red_s : STD_LOGIC;
attribute CAPACITANCE : string;
attribute CAPACITANCE of OBUFDS_blue : label is "DONT_CARE";
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of OBUFDS_blue : label is "OBUFDS";
attribute box_type : string;
attribute box_type of OBUFDS_blue : label is "PRIMITIVE";
attribute CAPACITANCE of OBUFDS_clock : label is "DONT_CARE";
attribute XILINX_LEGACY_PRIM of OBUFDS_clock : label is "OBUFDS";
attribute box_type of OBUFDS_clock : label is "PRIMITIVE";
attribute CAPACITANCE of OBUFDS_green : label is "DONT_CARE";
attribute XILINX_LEGACY_PRIM of OBUFDS_green : label is "OBUFDS";
attribute box_type of OBUFDS_green : label is "PRIMITIVE";
attribute CAPACITANCE of OBUFDS_red : label is "DONT_CARE";
attribute XILINX_LEGACY_PRIM of OBUFDS_red : label is "OBUFDS";
attribute box_type of OBUFDS_red : label is "PRIMITIVE";
begin
DVID: entity work.system_zybo_hdmi_0_0_dvid
port map (
active => active,
blue_s => blue_s,
clk_125 => clk_125,
clk_25 => clk_25,
clock_s => clock_s,
green_s => green_s,
hsync => hsync,
red_s => red_s,
rgb(23 downto 0) => rgb(23 downto 0),
vsync => vsync
);
OBUFDS_blue: unisim.vcomponents.OBUFDS
generic map(
IOSTANDARD => "DEFAULT"
)
port map (
I => blue_s,
O => tmds(0),
OB => tmdsb(0)
);
OBUFDS_clock: unisim.vcomponents.OBUFDS
generic map(
IOSTANDARD => "DEFAULT"
)
port map (
I => clock_s,
O => tmds(3),
OB => tmdsb(3)
);
OBUFDS_green: unisim.vcomponents.OBUFDS
generic map(
IOSTANDARD => "DEFAULT"
)
port map (
I => red_s,
O => tmds(2),
OB => tmdsb(2)
);
OBUFDS_red: unisim.vcomponents.OBUFDS
generic map(
IOSTANDARD => "DEFAULT"
)
port map (
I => green_s,
O => tmds(1),
OB => tmdsb(1)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_zybo_hdmi_0_0 is
port (
clk_125 : in STD_LOGIC;
clk_25 : in STD_LOGIC;
hsync : in STD_LOGIC;
vsync : in STD_LOGIC;
active : in STD_LOGIC;
rgb : in STD_LOGIC_VECTOR ( 23 downto 0 );
tmds : out STD_LOGIC_VECTOR ( 3 downto 0 );
tmdsb : out STD_LOGIC_VECTOR ( 3 downto 0 );
hdmi_cec : in STD_LOGIC;
hdmi_hpd : in STD_LOGIC;
hdmi_out_en : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_zybo_hdmi_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_zybo_hdmi_0_0 : entity is "system_zybo_hdmi_0_0,zybo_hdmi,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_zybo_hdmi_0_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_zybo_hdmi_0_0 : entity is "zybo_hdmi,Vivado 2016.4";
end system_zybo_hdmi_0_0;
architecture STRUCTURE of system_zybo_hdmi_0_0 is
signal \<const1>\ : STD_LOGIC;
begin
hdmi_out_en <= \<const1>\;
U0: entity work.system_zybo_hdmi_0_0_zybo_hdmi
port map (
active => active,
clk_125 => clk_125,
clk_25 => clk_25,
hsync => hsync,
rgb(23 downto 0) => rgb(23 downto 0),
tmds(3 downto 0) => tmds(3 downto 0),
tmdsb(3 downto 0) => tmdsb(3 downto 0),
vsync => vsync
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
end STRUCTURE;
| mit |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_camera_hessian/zed_camera_hessian.srcs/sources_1/bd/system/ipshared/ac51/new/vga_hessian.vhd | 4 | 27351 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity vga_hessian is
generic (
ROW_WIDTH: integer := 10
);
port (
clk_x16: in std_logic;
active: in std_logic;
rst: in std_logic;
x_addr: in std_logic_vector(9 downto 0);
y_addr: in std_logic_vector(9 downto 0);
g_in: in std_logic_vector(7 downto 0);
hessian_out: out std_logic_vector(31 downto 0)
);
end vga_hessian;
architecture Structural of vga_hessian is
component blk_mem_gen_0 IS
PORT (
clka : IN STD_LOGIC;
ena : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
clkb : IN STD_LOGIC;
enb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END component;
signal addr_0, addr_1 : std_logic_vector(13 downto 0);
signal x, x0, x1, y_actual : unsigned(9 downto 0);
signal y, y1, y2, y3, y4, y5, y6, y7, y8, y9 : unsigned(3 downto 0);
signal compute_addr_0, compute_addr_1, compute_addr_2, compute_addr_3 : std_logic_vector(13 downto 0);
signal din : std_logic_vector(15 downto 0) := x"0000";
signal dout_0, dout_1 : std_logic_vector(15 downto 0);
signal cycle : std_logic_vector(3 downto 0) := "0000";
signal top_left_0, top_left_1, top_right_0, top_right_1, bottom_left_0, bottom_left_1, bottom_right_0, bottom_right_1, top, left, corner, value, last_value, Lyy_2_top_left, Lyy_2_top_right, Lyy_2_bottom_left, Lyy_2_bottom_right, Lxx_0, Lxx_1, Lxx_2, Lyy_0, Lyy_1, Lyy_2, Lxy_0, Lxy_1, Lxy_2, Lxy_3 : unsigned(15 downto 0) := (others => '0');
signal Lxx, Lyy, Lxy : signed(15 downto 0) := (others => '0');
signal det_0, det_1, det_abs, det : signed(31 downto 0) := (others => '0');
signal wen : std_logic := '0';
type CACHE_TYPE is array(ROW_WIDTH downto 0) of std_logic_vector(15 downto 0);
signal cache : CACHE_TYPE := (others => x"0000");
begin
bram_0 : blk_mem_gen_0 port map(
clka => clk_x16,
ena => '1',
wea(0) => wen,
addra => addr_0,
dina => din,
douta => dout_0,
clkb => clk_x16,
enb => '1',
web => "0",
addrb => addr_1,
dinb => x"0000",
doutb => dout_1
);
process(clk_x16)
begin
if rising_edge(clk_x16) then
if rst = '0' then
-- clear cache
cache <= (others => x"0000");
cycle <= "0000";
else
if active = '0' then
cycle <= "0000";
else
if cycle = "0000" then
-- store x and y for next iteration
x <= unsigned(x_addr);
y <= unsigned(y_addr(3 downto 0));
y_actual <= unsigned(y_addr);
-- get value
last_value <= value;
value(7 downto 0) <= unsigned(g_in);
-- get integral top and corner from cache
if y_actual = 0 then
top <= (others => '0');
else
top <= unsigned(cache(ROW_WIDTH - 1));
end if;
if x = 0 then
left <= (others => '0');
else
left <= unsigned(cache(0));
end if;
if x = 0 or y_actual = 0 then
corner <= (others => '0');
else
corner <= unsigned(cache(ROW_WIDTH));
end if;
-- compute addresses for top left and top right for Lyy_2/Lyy_1
compute_addr_0(13 downto 10) <= std_logic_vector(y3);
compute_addr_0(9 downto 0) <= std_logic_vector(x0);
compute_addr_1(13 downto 10) <= std_logic_vector(y3);
compute_addr_1(9 downto 0) <= std_logic_vector(x1);
-- write addresses to read top left and top right for Lyy_1/Lyy_0
addr_0 <= compute_addr_2;
addr_1 <= compute_addr_3;
-- data ready, bottom right corner and top right corner for Lxx_2/Lxx_1
bottom_right_1 <= bottom_left_0;
top_right_1 <= top_left_0;
bottom_left_1 <= unsigned(dout_0);
top_left_1 <= unsigned(dout_1);
-- compute Lxx_0
Lxx_0 <= bottom_right_0 - top_right_0 - bottom_left_0 + top_left_0;
cycle <= "0001";
elsif cycle = "0001" then
-- compute (x, y) bottom right corner and top left corner for Lxy_0
x0 <= x-3;
y5 <= y-5;
x1 <= x-6;
y8 <= y-8;
-- write addresses to read top left corner and top right corner for Lyy_2/Lyy_1
addr_0 <= compute_addr_0;
addr_1 <= compute_addr_1;
-- data ready, bottom left corner and top left corner for Lxx_2
top_right_0 <= top_left_1;
bottom_right_0 <= bottom_left_1;
bottom_left_0 <= unsigned(dout_0);
top_left_0 <= unsigned(dout_1);
-- compute Lxx_1, Lxx_2
Lxx_1 <= (bottom_right_1 - top_right_1 - bottom_left_1 + top_left_1) sll 1;
-- compute integral
Lyy_2_bottom_right <= last_value + left + top - corner;
Lyy_2_bottom_left <= unsigned(cache(4));
cycle <= "0010";
elsif cycle = "0010" then
-- compute (x, y) bottom left corner and top right corner for Lxy_0
x0 <= x1;
x1 <= x0;
-- compute addresses for bottom right corner and top left corner for Lxy_0
compute_addr_0(13 downto 10) <= std_logic_vector(y5);
compute_addr_0(9 downto 0) <= std_logic_vector(x0);
compute_addr_1(13 downto 10) <= std_logic_vector(y8);
compute_addr_1(9 downto 0) <= std_logic_vector(x1);
-- data ready, top left corner and top right corner for Lyy_0
top_left_0 <= unsigned(dout_0);
top_right_0 <= unsigned(dout_1);
-- compute Lxx_2
Lxx_2 <= bottom_right_0 - top_right_0 - bottom_left_0 + top_left_0;
cycle <= "0011";
elsif cycle = "0011" then
-- compute (x, y) bottom right corner and top left corner for Lxy_1
x0 <= x+1;
x1 <= x-2;
-- compute addresses for bottom left corner and top right corner for Lxy_0
compute_addr_2(13 downto 10) <= std_logic_vector(y5);
compute_addr_2(9 downto 0) <= std_logic_vector(x0);
compute_addr_3(13 downto 10) <= std_logic_vector(y8);
compute_addr_3(9 downto 0) <= std_logic_vector(x1);
-- write addresses to read bottom right corner and top left corner for Lxy_0
addr_0 <= compute_addr_0;
addr_1 <= compute_addr_1;
-- data ready, top left corner and top right corner for Lyy_1/Lyy_0
bottom_left_0 <= unsigned(dout_0);
bottom_right_0 <= unsigned(dout_1);
-- compute Lxx
Lxx <= signed(Lxx_0 - Lxx_1 + Lxx_2);
cycle <= "0100";
elsif cycle = "0100" then
-- compute (x, y) bottom left corner and top right corner for Lxy_1
x0 <= x1;
x1 <= x0;
-- compute addresses for bottom right corner and top left corner for Lxy_1
compute_addr_0(13 downto 10) <= std_logic_vector(y5);
compute_addr_0(9 downto 0) <= std_logic_vector(x0);
compute_addr_1(13 downto 10) <= std_logic_vector(y8);
compute_addr_1(9 downto 0) <= std_logic_vector(x1);
-- write addresses to read bottom left corner and top right corner for Lxy_0
addr_0 <= compute_addr_2;
addr_1 <= compute_addr_3;
-- data ready, top left corner and top right corner for Lyy_2/Lyy_1
top_left_1 <= bottom_left_0;
top_right_1 <= bottom_right_0;
bottom_left_1 <= unsigned(dout_0);
bottom_right_1 <= unsigned(dout_1);
-- compute Lyy_0
Lyy_0 <= bottom_right_0 - top_right_0 - bottom_left_0 + top_left_0;
cycle <= "0101";
elsif cycle = "0101" then
-- compute (x, y) bottom right corner and top left corner for Lxy_2
x0 <= x1;
y1 <= y-1;
x1 <= x0;
y4 <= y-4;
-- compute addresses for bottom left corner and top right corner for Lxy_1
compute_addr_2(13 downto 10) <= std_logic_vector(y5);
compute_addr_2(9 downto 0) <= std_logic_vector(x0);
compute_addr_3(13 downto 10) <= std_logic_vector(y8);
compute_addr_3(9 downto 0) <= std_logic_vector(x1);
-- write addresses to read bottom right corner and top left corner for Lxy_1
addr_0 <= compute_addr_0;
addr_1 <= compute_addr_1;
Lyy_2_top_left <= bottom_left_1;
Lyy_2_top_right <= bottom_right_1;
-- compute Lyy_1
Lyy_1 <= (bottom_right_1 - top_right_1 - bottom_left_1 + top_left_1) sll 1;
cycle <= "0110";
elsif cycle = "0110" then
-- compute (x, y) bottom left corner and top right corner for Lxy_2
x0 <= x1;
x1 <= x0;
-- compute address to write above point to cache
compute_addr_0(13 downto 10) <= std_logic_vector(y1);
compute_addr_0(9 downto 0) <= std_logic_vector(x);
-- compute address for top left corner for Lxy_2
compute_addr_1(13 downto 10) <= std_logic_vector(y4);
compute_addr_1(9 downto 0) <= std_logic_vector(x1);
-- write addresses to read bottom left corner and top right corner for Lxy_1
addr_0 <= compute_addr_2;
addr_1 <= compute_addr_3;
-- data ready, bottom right corner and top left corner for Lxy_0
bottom_right_0 <= unsigned(dout_0);
top_left_0 <= unsigned(dout_1);
-- compute Lyy_2
Lyy_2 <= Lyy_2_bottom_right - Lyy_2_bottom_left - Lyy_2_top_right + Lyy_2_top_left;
cycle <= "0111";
elsif cycle = "0111" then
-- compute (x, y) bottom right corner and top left corner for Lxy_3
x0 <= x-3;
x1 <= x-6;
-- compute addresses for bottom left corner and top right corner for Lxy_2
compute_addr_2(13 downto 10) <= std_logic_vector(y1);
compute_addr_2(9 downto 0) <= std_logic_vector(x0);
compute_addr_3(13 downto 10) <= std_logic_vector(y4);
compute_addr_3(9 downto 0) <= std_logic_vector(x1);
-- write address to write above point to cache
addr_0 <= compute_addr_0;
din <= cache(ROW_WIDTH-2);
wen <= '1';
-- write address to read top left corner for Lxy_2
addr_1 <= compute_addr_1;
-- data ready, bottom left corner and top right corner for Lxy_0
bottom_left_0 <= unsigned(dout_0);
top_right_0 <= unsigned(dout_1);
-- shift cache
for i in 1 to ROW_WIDTH loop
cache(i) <= cache(i-1);
end loop;
cache(0) <= std_logic_vector(Lyy_2_bottom_right);
-- compute Lyy
Lyy <= signed(Lyy_0 - Lyy_1 + Lyy_2);
cycle <= "1000";
elsif cycle = "1000" then
-- compute (x, y) bottom left corner and top right corner for Lxy_3
x0 <= x1;
x1 <= x0;
-- compute addresses for bottom right corner and top left corner for Lxy_3
compute_addr_0(13 downto 10) <= std_logic_vector(y1);
compute_addr_0(9 downto 0) <= std_logic_vector(x0);
compute_addr_1(13 downto 10) <= std_logic_vector(y4);
compute_addr_1(9 downto 0) <= std_logic_vector(x1);
-- write addresses to read bottom left corner and top right corner for Lxy_2
addr_0 <= compute_addr_2;
addr_1 <= compute_addr_3;
-- turn off write
wen <= '0';
-- data ready, bottom right corner and top left corner for Lxy_1
bottom_right_1 <= unsigned(dout_0);
top_left_1 <= unsigned(dout_1);
-- compute Lxy_0
Lxy_0 <= bottom_right_0 - top_right_0 - bottom_left_0 + top_left_0;
cycle <= "1001";
elsif cycle = "1001" then
-- compute (x, y) bottom right corner and top right corner for Lxx_0
x0 <= x+2;
y2 <= y-2;
y7 <= y-7;
-- compute addresses for bottom left corner and top right corner for Lxy_3
compute_addr_2(13 downto 10) <= std_logic_vector(y1);
compute_addr_2(9 downto 0) <= std_logic_vector(x0);
compute_addr_3(13 downto 10) <= std_logic_vector(y4);
compute_addr_3(9 downto 0) <= std_logic_vector(x1);
-- write addresses to read bottom right corner and top left corner for Lxy_3
addr_0 <= compute_addr_0;
addr_1 <= compute_addr_1;
-- data ready, bottom left corner and top right corner for Lxy_1
bottom_left_1 <= unsigned(dout_0);
top_right_1 <= unsigned(dout_1);
-- compute determinant secondary diagonal
det_1 <= Lxy * Lxy;
cycle <= "1010";
elsif cycle = "1010" then
-- compute (x, y) bottom right corner and top right corner for Lxx_1/Lxx_0
x0 <= x-1;
-- compute addresses for bottom right corner and top right corner for Lxx_0
compute_addr_0(13 downto 10) <= std_logic_vector(y2);
compute_addr_0(9 downto 0) <= std_logic_vector(x0);
compute_addr_1(13 downto 10) <= std_logic_vector(y7);
compute_addr_1(9 downto 0) <= std_logic_vector(x0);
-- write addresses to read bottom left corner and top right corner for Lxy_3
addr_0 <= compute_addr_2;
addr_1 <= compute_addr_3;
-- data ready, bottom right corner and top left corner for Lxy_2
bottom_right_0 <= unsigned(cache(ROW_WIDTH-2));
top_left_0 <= unsigned(dout_1);
-- compute Lxy_1
Lxy_1 <= bottom_right_1 - top_right_1 - bottom_left_1 + top_left_1;
cycle <= "1011";
elsif cycle = "1011" then
-- compute (x, y) bottom right corner and top right corner for Lxx_2/Lxx_1
x0 <= x-4;
-- compute addresses for bottom right corner and top right corner for Lxx_1/Lxx_0
compute_addr_2(13 downto 10) <= std_logic_vector(y2);
compute_addr_2(9 downto 0) <= std_logic_vector(x0);
compute_addr_3(13 downto 10) <= std_logic_vector(y7);
compute_addr_3(9 downto 0) <= std_logic_vector(x0);
-- write addresses to read bottom right corner and top right corner for Lxx_0
addr_0 <= compute_addr_0;
addr_1 <= compute_addr_1;
-- data ready, bottom left corner and top right corner for Lxy_2
bottom_left_0 <= unsigned(dout_0);
top_right_0 <= unsigned(dout_1);
cycle <= "1100";
elsif cycle = "1100" then
-- compute (x, y) bottom left and top left corner for Lxx_2
x0 <= x-7;
-- compute addresses for bottom right corner and top right corner for Lxx_2/Lxx_1
compute_addr_0(13 downto 10) <= std_logic_vector(y2);
compute_addr_0(9 downto 0) <= std_logic_vector(x0);
compute_addr_1(13 downto 10) <= std_logic_vector(y7);
compute_addr_1(9 downto 0) <= std_logic_vector(x0);
-- write addresses to read bottom right corner and top right corner for Lxx_1/Lxx_0
addr_0 <= compute_addr_2;
addr_1 <= compute_addr_3;
-- data ready, bottom right corner and top left corner for Lxy_3
bottom_right_1 <= unsigned(dout_0);
top_left_1 <= unsigned(dout_1);
-- compute determinant primary diagonal
det_0 <= Lxx * Lyy;
-- compute Lxy_2
Lxy_2 <= bottom_right_0 - top_right_0 - bottom_left_0 + top_left_0;
cycle <= "1101";
elsif cycle = "1101" then
-- compute (x, y) top left and top right for Lyy_0
x0 <= x-5;
x1 <= x;
y9 <= y-9;
-- compute addresses for bottom left and top left corner for Lxx_2
compute_addr_2(13 downto 10) <= std_logic_vector(y2);
compute_addr_2(9 downto 0) <= std_logic_vector(x0);
compute_addr_3(13 downto 10) <= std_logic_vector(y7);
compute_addr_3(9 downto 0) <= std_logic_vector(x0);
-- write addresses to read bottom right corner and top right corner for Lxx_2/Lxx_1
addr_0 <= compute_addr_0;
addr_1 <= compute_addr_1;
-- data ready, bottom left corner and top right corner for Lxy_3
bottom_left_1 <= unsigned(dout_0);
top_right_1 <= unsigned(dout_1);
-- compute determinant
det <= det_0 - det_1;
cycle <= "1110";
elsif cycle <= "1110" then
-- compute (x, y) top left and top right for Lyy_1/Lyy_0
y6 <= y-6;
-- compute addresses for top left and top right for Lyy_0
compute_addr_0(13 downto 10) <= std_logic_vector(y9);
compute_addr_0(9 downto 0) <= std_logic_vector(x0);
compute_addr_1(13 downto 10) <= std_logic_vector(y9);
compute_addr_1(9 downto 0) <= std_logic_vector(x1);
-- write addresses to read bottom left corner and top left corner for Lxx_2
addr_0 <= compute_addr_2;
addr_1 <= compute_addr_3;
-- data ready, bottom right corner and top right corner for Lxx_0
bottom_right_0 <= unsigned(dout_0);
top_right_0 <= unsigned(dout_1);
-- compute Lxy_3
Lxy_3 <= bottom_right_1 - top_right_1 - bottom_left_1 + top_left_1;
-- absolute value determinant
if det < 0 then
det_abs <= -det;
else
det_abs <= det;
end if;
cycle <= "1111";
elsif cycle <= "1111" then
-- compute (x, y) top left and top right for Lyy_2/Lyy_1
y3 <= y-3;
-- compute addresses for top left and top right for Lyy_1/Lyy_0
compute_addr_2(13 downto 10) <= std_logic_vector(y6);
compute_addr_2(9 downto 0) <= std_logic_vector(x0);
compute_addr_3(13 downto 10) <= std_logic_vector(y6);
compute_addr_3(9 downto 0) <= std_logic_vector(x1);
-- write addresses to read top left corner and top right corner for Lyy_0
addr_0 <= compute_addr_0;
addr_1 <= compute_addr_1;
-- data ready, bottom right corner and top right corner for Lxx_1/Lxx_0
bottom_left_0 <= unsigned(dout_0);
top_left_0 <= unsigned(dout_1);
-- compute Lxy
Lxy <= signed(Lxy_0 - Lxy_1 + Lxy_2 - Lxy_3);
-- output hessian
hessian_out <= std_logic_vector(det_abs);
cycle <= "0000";
end if;
end if;
end if;
end if;
end process;
end Structural;
| mit |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_dual_camera_test/zed_dual_camera_test.srcs/sources_1/bd/system/ip/system_vga_sync_reset_0_0/system_vga_sync_reset_0_0_sim_netlist.vhdl | 1 | 19047 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Thu May 25 15:29:02 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- C:/ZyboIP/examples/zed_dual_camera_test/zed_dual_camera_test.srcs/sources_1/bd/system/ip/system_vga_sync_reset_0_0/system_vga_sync_reset_0_0_sim_netlist.vhdl
-- Design : system_vga_sync_reset_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_vga_sync_reset_0_0_vga_sync_reset is
port (
xaddr : out STD_LOGIC_VECTOR ( 9 downto 0 );
yaddr : out STD_LOGIC_VECTOR ( 9 downto 0 );
active : out STD_LOGIC;
hsync : out STD_LOGIC;
vsync : out STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_vga_sync_reset_0_0_vga_sync_reset : entity is "vga_sync_reset";
end system_vga_sync_reset_0_0_vga_sync_reset;
architecture STRUCTURE of system_vga_sync_reset_0_0_vga_sync_reset is
signal active_i_1_n_0 : STD_LOGIC;
signal active_i_2_n_0 : STD_LOGIC;
signal \h_count_reg[0]_i_1_n_0\ : STD_LOGIC;
signal \h_count_reg[9]_i_1_n_0\ : STD_LOGIC;
signal \h_count_reg[9]_i_3_n_0\ : STD_LOGIC;
signal \h_count_reg[9]_i_4_n_0\ : STD_LOGIC;
signal hsync_i_1_n_0 : STD_LOGIC;
signal hsync_i_2_n_0 : STD_LOGIC;
signal hsync_i_3_n_0 : STD_LOGIC;
signal plusOp : STD_LOGIC_VECTOR ( 9 downto 1 );
signal \plusOp__0\ : STD_LOGIC_VECTOR ( 9 downto 0 );
signal \v_count_reg[9]_i_1_n_0\ : STD_LOGIC;
signal \v_count_reg[9]_i_2_n_0\ : STD_LOGIC;
signal \v_count_reg[9]_i_4_n_0\ : STD_LOGIC;
signal \v_count_reg[9]_i_5_n_0\ : STD_LOGIC;
signal \v_count_reg[9]_i_6_n_0\ : STD_LOGIC;
signal vsync_i_1_n_0 : STD_LOGIC;
signal vsync_i_2_n_0 : STD_LOGIC;
signal \^xaddr\ : STD_LOGIC_VECTOR ( 9 downto 0 );
signal \^yaddr\ : STD_LOGIC_VECTOR ( 9 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of active_i_2 : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \h_count_reg[1]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \h_count_reg[2]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \h_count_reg[3]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \h_count_reg[4]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \h_count_reg[7]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \h_count_reg[8]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \h_count_reg[9]_i_3\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \h_count_reg[9]_i_4\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of hsync_i_1 : label is "soft_lutpair5";
attribute SOFT_HLUTNM of hsync_i_3 : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \v_count_reg[0]_i_1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \v_count_reg[1]_i_1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \v_count_reg[2]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \v_count_reg[3]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \v_count_reg[4]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \v_count_reg[7]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \v_count_reg[8]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \v_count_reg[9]_i_6\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of vsync_i_2 : label is "soft_lutpair3";
begin
xaddr(9 downto 0) <= \^xaddr\(9 downto 0);
yaddr(9 downto 0) <= \^yaddr\(9 downto 0);
active_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"0000222A00000000"
)
port map (
I0 => active_i_2_n_0,
I1 => \^xaddr\(9),
I2 => \^xaddr\(7),
I3 => \^xaddr\(8),
I4 => \^yaddr\(9),
I5 => rst,
O => active_i_1_n_0
);
active_i_2: unisim.vcomponents.LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => \^yaddr\(7),
I1 => \^yaddr\(5),
I2 => \^yaddr\(6),
I3 => \^yaddr\(8),
O => active_i_2_n_0
);
active_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => active_i_1_n_0,
Q => active,
R => '0'
);
\h_count_reg[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^xaddr\(0),
O => \h_count_reg[0]_i_1_n_0\
);
\h_count_reg[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^xaddr\(0),
I1 => \^xaddr\(1),
O => plusOp(1)
);
\h_count_reg[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \^xaddr\(1),
I1 => \^xaddr\(0),
I2 => \^xaddr\(2),
O => plusOp(2)
);
\h_count_reg[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^xaddr\(2),
I1 => \^xaddr\(0),
I2 => \^xaddr\(1),
I3 => \^xaddr\(3),
O => plusOp(3)
);
\h_count_reg[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \^xaddr\(3),
I1 => \^xaddr\(1),
I2 => \^xaddr\(0),
I3 => \^xaddr\(2),
I4 => \^xaddr\(4),
O => plusOp(4)
);
\h_count_reg[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFF80000000"
)
port map (
I0 => \^xaddr\(4),
I1 => \^xaddr\(2),
I2 => \^xaddr\(0),
I3 => \^xaddr\(1),
I4 => \^xaddr\(3),
I5 => \^xaddr\(5),
O => plusOp(5)
);
\h_count_reg[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"D2"
)
port map (
I0 => \^xaddr\(5),
I1 => \h_count_reg[9]_i_3_n_0\,
I2 => \^xaddr\(6),
O => plusOp(6)
);
\h_count_reg[7]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"BF40"
)
port map (
I0 => \h_count_reg[9]_i_3_n_0\,
I1 => \^xaddr\(5),
I2 => \^xaddr\(6),
I3 => \^xaddr\(7),
O => plusOp(7)
);
\h_count_reg[8]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF7F0080"
)
port map (
I0 => \^xaddr\(7),
I1 => \^xaddr\(6),
I2 => \^xaddr\(5),
I3 => \h_count_reg[9]_i_3_n_0\,
I4 => \^xaddr\(8),
O => plusOp(8)
);
\h_count_reg[9]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"10000000FFFFFFFF"
)
port map (
I0 => \h_count_reg[9]_i_3_n_0\,
I1 => \^xaddr\(7),
I2 => \^xaddr\(8),
I3 => \^xaddr\(9),
I4 => \h_count_reg[9]_i_4_n_0\,
I5 => rst,
O => \h_count_reg[9]_i_1_n_0\
);
\h_count_reg[9]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"DFFFFFFF20000000"
)
port map (
I0 => \^xaddr\(8),
I1 => \h_count_reg[9]_i_3_n_0\,
I2 => \^xaddr\(5),
I3 => \^xaddr\(6),
I4 => \^xaddr\(7),
I5 => \^xaddr\(9),
O => plusOp(9)
);
\h_count_reg[9]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFFFFFF"
)
port map (
I0 => \^xaddr\(3),
I1 => \^xaddr\(1),
I2 => \^xaddr\(0),
I3 => \^xaddr\(2),
I4 => \^xaddr\(4),
O => \h_count_reg[9]_i_3_n_0\
);
\h_count_reg[9]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \^xaddr\(5),
I1 => \^xaddr\(6),
O => \h_count_reg[9]_i_4_n_0\
);
\h_count_reg_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \h_count_reg[0]_i_1_n_0\,
Q => \^xaddr\(0),
R => \h_count_reg[9]_i_1_n_0\
);
\h_count_reg_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => plusOp(1),
Q => \^xaddr\(1),
R => \h_count_reg[9]_i_1_n_0\
);
\h_count_reg_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => plusOp(2),
Q => \^xaddr\(2),
R => \h_count_reg[9]_i_1_n_0\
);
\h_count_reg_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => plusOp(3),
Q => \^xaddr\(3),
R => \h_count_reg[9]_i_1_n_0\
);
\h_count_reg_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => plusOp(4),
Q => \^xaddr\(4),
R => \h_count_reg[9]_i_1_n_0\
);
\h_count_reg_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => plusOp(5),
Q => \^xaddr\(5),
R => \h_count_reg[9]_i_1_n_0\
);
\h_count_reg_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => plusOp(6),
Q => \^xaddr\(6),
R => \h_count_reg[9]_i_1_n_0\
);
\h_count_reg_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => plusOp(7),
Q => \^xaddr\(7),
R => \h_count_reg[9]_i_1_n_0\
);
\h_count_reg_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => plusOp(8),
Q => \^xaddr\(8),
R => \h_count_reg[9]_i_1_n_0\
);
\h_count_reg_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => plusOp(9),
Q => \^xaddr\(9),
R => \h_count_reg[9]_i_1_n_0\
);
hsync_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"ABEAFFFF"
)
port map (
I0 => hsync_i_2_n_0,
I1 => \^xaddr\(5),
I2 => \^xaddr\(6),
I3 => hsync_i_3_n_0,
I4 => rst,
O => hsync_i_1_n_0
);
hsync_i_2: unisim.vcomponents.LUT3
generic map(
INIT => X"DF"
)
port map (
I0 => \^xaddr\(9),
I1 => \^xaddr\(8),
I2 => \^xaddr\(7),
O => hsync_i_2_n_0
);
hsync_i_3: unisim.vcomponents.LUT5
generic map(
INIT => X"0001FFFF"
)
port map (
I0 => \^xaddr\(2),
I1 => \^xaddr\(3),
I2 => \^xaddr\(0),
I3 => \^xaddr\(1),
I4 => \^xaddr\(4),
O => hsync_i_3_n_0
);
hsync_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => hsync_i_1_n_0,
Q => hsync,
R => '0'
);
\v_count_reg[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^yaddr\(0),
O => \plusOp__0\(0)
);
\v_count_reg[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^yaddr\(0),
I1 => \^yaddr\(1),
O => \plusOp__0\(1)
);
\v_count_reg[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \^yaddr\(1),
I1 => \^yaddr\(0),
I2 => \^yaddr\(2),
O => \plusOp__0\(2)
);
\v_count_reg[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^yaddr\(2),
I1 => \^yaddr\(0),
I2 => \^yaddr\(1),
I3 => \^yaddr\(3),
O => \plusOp__0\(3)
);
\v_count_reg[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \^yaddr\(3),
I1 => \^yaddr\(1),
I2 => \^yaddr\(0),
I3 => \^yaddr\(2),
I4 => \^yaddr\(4),
O => \plusOp__0\(4)
);
\v_count_reg[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFF80000000"
)
port map (
I0 => \^yaddr\(4),
I1 => \^yaddr\(2),
I2 => \^yaddr\(0),
I3 => \^yaddr\(1),
I4 => \^yaddr\(3),
I5 => \^yaddr\(5),
O => \plusOp__0\(5)
);
\v_count_reg[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"D2"
)
port map (
I0 => \^yaddr\(5),
I1 => \v_count_reg[9]_i_6_n_0\,
I2 => \^yaddr\(6),
O => \plusOp__0\(6)
);
\v_count_reg[7]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"F708"
)
port map (
I0 => \^yaddr\(5),
I1 => \^yaddr\(6),
I2 => \v_count_reg[9]_i_6_n_0\,
I3 => \^yaddr\(7),
O => \plusOp__0\(7)
);
\v_count_reg[8]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"BFFF4000"
)
port map (
I0 => \v_count_reg[9]_i_6_n_0\,
I1 => \^yaddr\(6),
I2 => \^yaddr\(5),
I3 => \^yaddr\(7),
I4 => \^yaddr\(8),
O => \plusOp__0\(8)
);
\v_count_reg[9]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00400000FFFFFFFF"
)
port map (
I0 => \h_count_reg[9]_i_3_n_0\,
I1 => \v_count_reg[9]_i_4_n_0\,
I2 => \h_count_reg[9]_i_4_n_0\,
I3 => \^yaddr\(0),
I4 => \v_count_reg[9]_i_5_n_0\,
I5 => rst,
O => \v_count_reg[9]_i_1_n_0\
);
\v_count_reg[9]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000001000"
)
port map (
I0 => \^xaddr\(5),
I1 => \^xaddr\(6),
I2 => \^xaddr\(9),
I3 => \^xaddr\(8),
I4 => \^xaddr\(7),
I5 => \h_count_reg[9]_i_3_n_0\,
O => \v_count_reg[9]_i_2_n_0\
);
\v_count_reg[9]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"BFFFFFFF40000000"
)
port map (
I0 => \v_count_reg[9]_i_6_n_0\,
I1 => \^yaddr\(7),
I2 => \^yaddr\(5),
I3 => \^yaddr\(6),
I4 => \^yaddr\(8),
I5 => \^yaddr\(9),
O => \plusOp__0\(9)
);
\v_count_reg[9]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"0002000000000000"
)
port map (
I0 => \^yaddr\(9),
I1 => \^xaddr\(7),
I2 => \^yaddr\(7),
I3 => \^yaddr\(8),
I4 => \^xaddr\(9),
I5 => \^xaddr\(8),
O => \v_count_reg[9]_i_4_n_0\
);
\v_count_reg[9]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000020"
)
port map (
I0 => \^yaddr\(3),
I1 => \^yaddr\(4),
I2 => \^yaddr\(2),
I3 => \^yaddr\(1),
I4 => \^yaddr\(6),
I5 => \^yaddr\(5),
O => \v_count_reg[9]_i_5_n_0\
);
\v_count_reg[9]_i_6\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFFFFFF"
)
port map (
I0 => \^yaddr\(3),
I1 => \^yaddr\(1),
I2 => \^yaddr\(0),
I3 => \^yaddr\(2),
I4 => \^yaddr\(4),
O => \v_count_reg[9]_i_6_n_0\
);
\v_count_reg_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \v_count_reg[9]_i_2_n_0\,
D => \plusOp__0\(0),
Q => \^yaddr\(0),
R => \v_count_reg[9]_i_1_n_0\
);
\v_count_reg_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \v_count_reg[9]_i_2_n_0\,
D => \plusOp__0\(1),
Q => \^yaddr\(1),
R => \v_count_reg[9]_i_1_n_0\
);
\v_count_reg_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \v_count_reg[9]_i_2_n_0\,
D => \plusOp__0\(2),
Q => \^yaddr\(2),
R => \v_count_reg[9]_i_1_n_0\
);
\v_count_reg_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \v_count_reg[9]_i_2_n_0\,
D => \plusOp__0\(3),
Q => \^yaddr\(3),
R => \v_count_reg[9]_i_1_n_0\
);
\v_count_reg_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \v_count_reg[9]_i_2_n_0\,
D => \plusOp__0\(4),
Q => \^yaddr\(4),
R => \v_count_reg[9]_i_1_n_0\
);
\v_count_reg_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \v_count_reg[9]_i_2_n_0\,
D => \plusOp__0\(5),
Q => \^yaddr\(5),
R => \v_count_reg[9]_i_1_n_0\
);
\v_count_reg_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \v_count_reg[9]_i_2_n_0\,
D => \plusOp__0\(6),
Q => \^yaddr\(6),
R => \v_count_reg[9]_i_1_n_0\
);
\v_count_reg_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \v_count_reg[9]_i_2_n_0\,
D => \plusOp__0\(7),
Q => \^yaddr\(7),
R => \v_count_reg[9]_i_1_n_0\
);
\v_count_reg_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \v_count_reg[9]_i_2_n_0\,
D => \plusOp__0\(8),
Q => \^yaddr\(8),
R => \v_count_reg[9]_i_1_n_0\
);
\v_count_reg_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \v_count_reg[9]_i_2_n_0\,
D => \plusOp__0\(9),
Q => \^yaddr\(9),
R => \v_count_reg[9]_i_1_n_0\
);
vsync_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFBFFFFFFFF"
)
port map (
I0 => vsync_i_2_n_0,
I1 => \^yaddr\(1),
I2 => \^yaddr\(2),
I3 => \^yaddr\(9),
I4 => \^yaddr\(4),
I5 => rst,
O => vsync_i_1_n_0
);
vsync_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFFFFFF"
)
port map (
I0 => \^yaddr\(8),
I1 => \^yaddr\(6),
I2 => \^yaddr\(5),
I3 => \^yaddr\(7),
I4 => \^yaddr\(3),
O => vsync_i_2_n_0
);
vsync_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => vsync_i_1_n_0,
Q => vsync,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_vga_sync_reset_0_0 is
port (
clk : in STD_LOGIC;
rst : in STD_LOGIC;
active : out STD_LOGIC;
hsync : out STD_LOGIC;
vsync : out STD_LOGIC;
xaddr : out STD_LOGIC_VECTOR ( 9 downto 0 );
yaddr : out STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_vga_sync_reset_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_vga_sync_reset_0_0 : entity is "system_vga_sync_reset_0_0,vga_sync_reset,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_vga_sync_reset_0_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_vga_sync_reset_0_0 : entity is "vga_sync_reset,Vivado 2016.4";
end system_vga_sync_reset_0_0;
architecture STRUCTURE of system_vga_sync_reset_0_0 is
begin
U0: entity work.system_vga_sync_reset_0_0_vga_sync_reset
port map (
active => active,
clk => clk,
hsync => hsync,
rst => rst,
vsync => vsync,
xaddr(9 downto 0) => xaddr(9 downto 0),
yaddr(9 downto 0) => yaddr(9 downto 0)
);
end STRUCTURE;
| mit |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_camera_hessian/zed_camera_hessian.srcs/sources_1/bd/system/ip/system_comparator_0_0/system_comparator_0_0_sim_netlist.vhdl | 1 | 14590 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Sat May 27 21:33:31 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- c:/ZyboIP/examples/zed_camera_hessian/zed_camera_hessian.srcs/sources_1/bd/system/ip/system_comparator_0_0/system_comparator_0_0_sim_netlist.vhdl
-- Design : system_comparator_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_comparator_0_0_comparator is
port (
z : out STD_LOGIC;
y : in STD_LOGIC_VECTOR ( 31 downto 0 );
x : in STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_comparator_0_0_comparator : entity is "comparator";
end system_comparator_0_0_comparator;
architecture STRUCTURE of system_comparator_0_0_comparator is
signal z1 : STD_LOGIC;
signal \z1_carry__0_i_1_n_0\ : STD_LOGIC;
signal \z1_carry__0_i_2_n_0\ : STD_LOGIC;
signal \z1_carry__0_i_3_n_0\ : STD_LOGIC;
signal \z1_carry__0_i_4_n_0\ : STD_LOGIC;
signal \z1_carry__0_i_5_n_0\ : STD_LOGIC;
signal \z1_carry__0_i_6_n_0\ : STD_LOGIC;
signal \z1_carry__0_i_7_n_0\ : STD_LOGIC;
signal \z1_carry__0_i_8_n_0\ : STD_LOGIC;
signal \z1_carry__0_n_0\ : STD_LOGIC;
signal \z1_carry__0_n_1\ : STD_LOGIC;
signal \z1_carry__0_n_2\ : STD_LOGIC;
signal \z1_carry__0_n_3\ : STD_LOGIC;
signal \z1_carry__1_i_1_n_0\ : STD_LOGIC;
signal \z1_carry__1_i_2_n_0\ : STD_LOGIC;
signal \z1_carry__1_i_3_n_0\ : STD_LOGIC;
signal \z1_carry__1_i_4_n_0\ : STD_LOGIC;
signal \z1_carry__1_i_5_n_0\ : STD_LOGIC;
signal \z1_carry__1_i_6_n_0\ : STD_LOGIC;
signal \z1_carry__1_i_7_n_0\ : STD_LOGIC;
signal \z1_carry__1_i_8_n_0\ : STD_LOGIC;
signal \z1_carry__1_n_0\ : STD_LOGIC;
signal \z1_carry__1_n_1\ : STD_LOGIC;
signal \z1_carry__1_n_2\ : STD_LOGIC;
signal \z1_carry__1_n_3\ : STD_LOGIC;
signal \z1_carry__2_i_1_n_0\ : STD_LOGIC;
signal \z1_carry__2_i_2_n_0\ : STD_LOGIC;
signal \z1_carry__2_i_3_n_0\ : STD_LOGIC;
signal \z1_carry__2_i_4_n_0\ : STD_LOGIC;
signal \z1_carry__2_i_5_n_0\ : STD_LOGIC;
signal \z1_carry__2_i_6_n_0\ : STD_LOGIC;
signal \z1_carry__2_i_7_n_0\ : STD_LOGIC;
signal \z1_carry__2_i_8_n_0\ : STD_LOGIC;
signal \z1_carry__2_n_1\ : STD_LOGIC;
signal \z1_carry__2_n_2\ : STD_LOGIC;
signal \z1_carry__2_n_3\ : STD_LOGIC;
signal z1_carry_i_1_n_0 : STD_LOGIC;
signal z1_carry_i_2_n_0 : STD_LOGIC;
signal z1_carry_i_3_n_0 : STD_LOGIC;
signal z1_carry_i_4_n_0 : STD_LOGIC;
signal z1_carry_i_5_n_0 : STD_LOGIC;
signal z1_carry_i_6_n_0 : STD_LOGIC;
signal z1_carry_i_7_n_0 : STD_LOGIC;
signal z1_carry_i_8_n_0 : STD_LOGIC;
signal z1_carry_n_0 : STD_LOGIC;
signal z1_carry_n_1 : STD_LOGIC;
signal z1_carry_n_2 : STD_LOGIC;
signal z1_carry_n_3 : STD_LOGIC;
signal NLW_z1_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_z1_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_z1_carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_z1_carry__2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_z1_carry__3_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_z1_carry__3_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
begin
z1_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => z1_carry_n_0,
CO(2) => z1_carry_n_1,
CO(1) => z1_carry_n_2,
CO(0) => z1_carry_n_3,
CYINIT => '0',
DI(3) => z1_carry_i_1_n_0,
DI(2) => z1_carry_i_2_n_0,
DI(1) => z1_carry_i_3_n_0,
DI(0) => z1_carry_i_4_n_0,
O(3 downto 0) => NLW_z1_carry_O_UNCONNECTED(3 downto 0),
S(3) => z1_carry_i_5_n_0,
S(2) => z1_carry_i_6_n_0,
S(1) => z1_carry_i_7_n_0,
S(0) => z1_carry_i_8_n_0
);
\z1_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => z1_carry_n_0,
CO(3) => \z1_carry__0_n_0\,
CO(2) => \z1_carry__0_n_1\,
CO(1) => \z1_carry__0_n_2\,
CO(0) => \z1_carry__0_n_3\,
CYINIT => '0',
DI(3) => \z1_carry__0_i_1_n_0\,
DI(2) => \z1_carry__0_i_2_n_0\,
DI(1) => \z1_carry__0_i_3_n_0\,
DI(0) => \z1_carry__0_i_4_n_0\,
O(3 downto 0) => \NLW_z1_carry__0_O_UNCONNECTED\(3 downto 0),
S(3) => \z1_carry__0_i_5_n_0\,
S(2) => \z1_carry__0_i_6_n_0\,
S(1) => \z1_carry__0_i_7_n_0\,
S(0) => \z1_carry__0_i_8_n_0\
);
\z1_carry__0_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"2F02"
)
port map (
I0 => y(14),
I1 => x(14),
I2 => x(15),
I3 => y(15),
O => \z1_carry__0_i_1_n_0\
);
\z1_carry__0_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"2F02"
)
port map (
I0 => y(12),
I1 => x(12),
I2 => x(13),
I3 => y(13),
O => \z1_carry__0_i_2_n_0\
);
\z1_carry__0_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"2F02"
)
port map (
I0 => y(10),
I1 => x(10),
I2 => x(11),
I3 => y(11),
O => \z1_carry__0_i_3_n_0\
);
\z1_carry__0_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"2F02"
)
port map (
I0 => y(8),
I1 => x(8),
I2 => x(9),
I3 => y(9),
O => \z1_carry__0_i_4_n_0\
);
\z1_carry__0_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => y(14),
I1 => x(14),
I2 => y(15),
I3 => x(15),
O => \z1_carry__0_i_5_n_0\
);
\z1_carry__0_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => y(12),
I1 => x(12),
I2 => y(13),
I3 => x(13),
O => \z1_carry__0_i_6_n_0\
);
\z1_carry__0_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => y(10),
I1 => x(10),
I2 => y(11),
I3 => x(11),
O => \z1_carry__0_i_7_n_0\
);
\z1_carry__0_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => y(8),
I1 => x(8),
I2 => y(9),
I3 => x(9),
O => \z1_carry__0_i_8_n_0\
);
\z1_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \z1_carry__0_n_0\,
CO(3) => \z1_carry__1_n_0\,
CO(2) => \z1_carry__1_n_1\,
CO(1) => \z1_carry__1_n_2\,
CO(0) => \z1_carry__1_n_3\,
CYINIT => '0',
DI(3) => \z1_carry__1_i_1_n_0\,
DI(2) => \z1_carry__1_i_2_n_0\,
DI(1) => \z1_carry__1_i_3_n_0\,
DI(0) => \z1_carry__1_i_4_n_0\,
O(3 downto 0) => \NLW_z1_carry__1_O_UNCONNECTED\(3 downto 0),
S(3) => \z1_carry__1_i_5_n_0\,
S(2) => \z1_carry__1_i_6_n_0\,
S(1) => \z1_carry__1_i_7_n_0\,
S(0) => \z1_carry__1_i_8_n_0\
);
\z1_carry__1_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"2F02"
)
port map (
I0 => y(22),
I1 => x(22),
I2 => x(23),
I3 => y(23),
O => \z1_carry__1_i_1_n_0\
);
\z1_carry__1_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"2F02"
)
port map (
I0 => y(20),
I1 => x(20),
I2 => x(21),
I3 => y(21),
O => \z1_carry__1_i_2_n_0\
);
\z1_carry__1_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"2F02"
)
port map (
I0 => y(18),
I1 => x(18),
I2 => x(19),
I3 => y(19),
O => \z1_carry__1_i_3_n_0\
);
\z1_carry__1_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"2F02"
)
port map (
I0 => y(16),
I1 => x(16),
I2 => x(17),
I3 => y(17),
O => \z1_carry__1_i_4_n_0\
);
\z1_carry__1_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => y(22),
I1 => x(22),
I2 => y(23),
I3 => x(23),
O => \z1_carry__1_i_5_n_0\
);
\z1_carry__1_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => y(20),
I1 => x(20),
I2 => y(21),
I3 => x(21),
O => \z1_carry__1_i_6_n_0\
);
\z1_carry__1_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => y(18),
I1 => x(18),
I2 => y(19),
I3 => x(19),
O => \z1_carry__1_i_7_n_0\
);
\z1_carry__1_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => y(16),
I1 => x(16),
I2 => y(17),
I3 => x(17),
O => \z1_carry__1_i_8_n_0\
);
\z1_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \z1_carry__1_n_0\,
CO(3) => z1,
CO(2) => \z1_carry__2_n_1\,
CO(1) => \z1_carry__2_n_2\,
CO(0) => \z1_carry__2_n_3\,
CYINIT => '0',
DI(3) => \z1_carry__2_i_1_n_0\,
DI(2) => \z1_carry__2_i_2_n_0\,
DI(1) => \z1_carry__2_i_3_n_0\,
DI(0) => \z1_carry__2_i_4_n_0\,
O(3 downto 0) => \NLW_z1_carry__2_O_UNCONNECTED\(3 downto 0),
S(3) => \z1_carry__2_i_5_n_0\,
S(2) => \z1_carry__2_i_6_n_0\,
S(1) => \z1_carry__2_i_7_n_0\,
S(0) => \z1_carry__2_i_8_n_0\
);
\z1_carry__2_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"2F02"
)
port map (
I0 => y(30),
I1 => x(30),
I2 => x(31),
I3 => y(31),
O => \z1_carry__2_i_1_n_0\
);
\z1_carry__2_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"2F02"
)
port map (
I0 => y(28),
I1 => x(28),
I2 => x(29),
I3 => y(29),
O => \z1_carry__2_i_2_n_0\
);
\z1_carry__2_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"2F02"
)
port map (
I0 => y(26),
I1 => x(26),
I2 => x(27),
I3 => y(27),
O => \z1_carry__2_i_3_n_0\
);
\z1_carry__2_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"2F02"
)
port map (
I0 => y(24),
I1 => x(24),
I2 => x(25),
I3 => y(25),
O => \z1_carry__2_i_4_n_0\
);
\z1_carry__2_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => y(30),
I1 => x(30),
I2 => y(31),
I3 => x(31),
O => \z1_carry__2_i_5_n_0\
);
\z1_carry__2_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => y(28),
I1 => x(28),
I2 => y(29),
I3 => x(29),
O => \z1_carry__2_i_6_n_0\
);
\z1_carry__2_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => y(26),
I1 => x(26),
I2 => y(27),
I3 => x(27),
O => \z1_carry__2_i_7_n_0\
);
\z1_carry__2_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => y(24),
I1 => x(24),
I2 => y(25),
I3 => x(25),
O => \z1_carry__2_i_8_n_0\
);
\z1_carry__3\: unisim.vcomponents.CARRY4
port map (
CI => z1,
CO(3 downto 0) => \NLW_z1_carry__3_CO_UNCONNECTED\(3 downto 0),
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 1) => \NLW_z1_carry__3_O_UNCONNECTED\(3 downto 1),
O(0) => z,
S(3 downto 0) => B"0001"
);
z1_carry_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"2F02"
)
port map (
I0 => y(6),
I1 => x(6),
I2 => x(7),
I3 => y(7),
O => z1_carry_i_1_n_0
);
z1_carry_i_2: unisim.vcomponents.LUT4
generic map(
INIT => X"2F02"
)
port map (
I0 => y(4),
I1 => x(4),
I2 => x(5),
I3 => y(5),
O => z1_carry_i_2_n_0
);
z1_carry_i_3: unisim.vcomponents.LUT4
generic map(
INIT => X"2F02"
)
port map (
I0 => y(2),
I1 => x(2),
I2 => x(3),
I3 => y(3),
O => z1_carry_i_3_n_0
);
z1_carry_i_4: unisim.vcomponents.LUT4
generic map(
INIT => X"2F02"
)
port map (
I0 => y(0),
I1 => x(0),
I2 => x(1),
I3 => y(1),
O => z1_carry_i_4_n_0
);
z1_carry_i_5: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => y(6),
I1 => x(6),
I2 => y(7),
I3 => x(7),
O => z1_carry_i_5_n_0
);
z1_carry_i_6: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => y(4),
I1 => x(4),
I2 => y(5),
I3 => x(5),
O => z1_carry_i_6_n_0
);
z1_carry_i_7: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => y(2),
I1 => x(2),
I2 => y(3),
I3 => x(3),
O => z1_carry_i_7_n_0
);
z1_carry_i_8: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => y(0),
I1 => x(0),
I2 => y(1),
I3 => x(1),
O => z1_carry_i_8_n_0
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_comparator_0_0 is
port (
x : in STD_LOGIC_VECTOR ( 31 downto 0 );
y : in STD_LOGIC_VECTOR ( 31 downto 0 );
z : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_comparator_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_comparator_0_0 : entity is "system_comparator_0_0,comparator,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_comparator_0_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_comparator_0_0 : entity is "comparator,Vivado 2016.4";
end system_comparator_0_0;
architecture STRUCTURE of system_comparator_0_0 is
begin
U0: entity work.system_comparator_0_0_comparator
port map (
x(31 downto 0) => x(31 downto 0),
y(31 downto 0) => y(31 downto 0),
z => z
);
end STRUCTURE;
| mit |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_hdmi_test/zed_hdmi_test.srcs/sources_1/bd/system/ip/system_vga_color_test_0_0/system_vga_color_test_0_0_sim_netlist.vhdl | 1 | 24976 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Thu May 18 23:19:00 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- c:/ZyboIP/examples/zed_hdmi_test/zed_hdmi_test.srcs/sources_1/bd/system/ip/system_vga_color_test_0_0/system_vga_color_test_0_0_sim_netlist.vhdl
-- Design : system_vga_color_test_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_vga_color_test_0_0_vga_color_test is
port (
rgb : out STD_LOGIC_VECTOR ( 9 downto 0 );
yaddr : in STD_LOGIC_VECTOR ( 6 downto 0 );
xaddr : in STD_LOGIC_VECTOR ( 9 downto 0 );
clk_25 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_vga_color_test_0_0_vga_color_test : entity is "vga_color_test";
end system_vga_color_test_0_0_vga_color_test;
architecture STRUCTURE of system_vga_color_test_0_0_vga_color_test is
signal \rgb[13]_i_1_n_0\ : STD_LOGIC;
signal \rgb[14]_i_1_n_0\ : STD_LOGIC;
signal \rgb[14]_i_2_n_0\ : STD_LOGIC;
signal \rgb[14]_i_3_n_0\ : STD_LOGIC;
signal \rgb[14]_i_4_n_0\ : STD_LOGIC;
signal \rgb[14]_i_5_n_0\ : STD_LOGIC;
signal \rgb[14]_i_6_n_0\ : STD_LOGIC;
signal \rgb[15]_i_1_n_0\ : STD_LOGIC;
signal \rgb[15]_i_2_n_0\ : STD_LOGIC;
signal \rgb[15]_i_3_n_0\ : STD_LOGIC;
signal \rgb[15]_i_4_n_0\ : STD_LOGIC;
signal \rgb[15]_i_5_n_0\ : STD_LOGIC;
signal \rgb[15]_i_6_n_0\ : STD_LOGIC;
signal \rgb[15]_i_7_n_0\ : STD_LOGIC;
signal \rgb[21]_i_1_n_0\ : STD_LOGIC;
signal \rgb[22]_i_10_n_0\ : STD_LOGIC;
signal \rgb[22]_i_11_n_0\ : STD_LOGIC;
signal \rgb[22]_i_1_n_0\ : STD_LOGIC;
signal \rgb[22]_i_2_n_0\ : STD_LOGIC;
signal \rgb[22]_i_3_n_0\ : STD_LOGIC;
signal \rgb[22]_i_4_n_0\ : STD_LOGIC;
signal \rgb[22]_i_5_n_0\ : STD_LOGIC;
signal \rgb[22]_i_6_n_0\ : STD_LOGIC;
signal \rgb[22]_i_7_n_0\ : STD_LOGIC;
signal \rgb[22]_i_8_n_0\ : STD_LOGIC;
signal \rgb[22]_i_9_n_0\ : STD_LOGIC;
signal \rgb[23]_i_10_n_0\ : STD_LOGIC;
signal \rgb[23]_i_11_n_0\ : STD_LOGIC;
signal \rgb[23]_i_12_n_0\ : STD_LOGIC;
signal \rgb[23]_i_13_n_0\ : STD_LOGIC;
signal \rgb[23]_i_14_n_0\ : STD_LOGIC;
signal \rgb[23]_i_15_n_0\ : STD_LOGIC;
signal \rgb[23]_i_16_n_0\ : STD_LOGIC;
signal \rgb[23]_i_17_n_0\ : STD_LOGIC;
signal \rgb[23]_i_18_n_0\ : STD_LOGIC;
signal \rgb[23]_i_1_n_0\ : STD_LOGIC;
signal \rgb[23]_i_2_n_0\ : STD_LOGIC;
signal \rgb[23]_i_3_n_0\ : STD_LOGIC;
signal \rgb[23]_i_4_n_0\ : STD_LOGIC;
signal \rgb[23]_i_5_n_0\ : STD_LOGIC;
signal \rgb[23]_i_6_n_0\ : STD_LOGIC;
signal \rgb[23]_i_7_n_0\ : STD_LOGIC;
signal \rgb[23]_i_8_n_0\ : STD_LOGIC;
signal \rgb[23]_i_9_n_0\ : STD_LOGIC;
signal \rgb[4]_i_1_n_0\ : STD_LOGIC;
signal \rgb[4]_i_2_n_0\ : STD_LOGIC;
signal \rgb[5]_i_1_n_0\ : STD_LOGIC;
signal \rgb[5]_i_2_n_0\ : STD_LOGIC;
signal \rgb[6]_i_1_n_0\ : STD_LOGIC;
signal \rgb[6]_i_2_n_0\ : STD_LOGIC;
signal \rgb[6]_i_3_n_0\ : STD_LOGIC;
signal \rgb[6]_i_4_n_0\ : STD_LOGIC;
signal \rgb[6]_i_5_n_0\ : STD_LOGIC;
signal \rgb[7]_i_1_n_0\ : STD_LOGIC;
signal \rgb[7]_i_2_n_0\ : STD_LOGIC;
signal \rgb[7]_i_3_n_0\ : STD_LOGIC;
signal \rgb[7]_i_4_n_0\ : STD_LOGIC;
signal \rgb[7]_i_5_n_0\ : STD_LOGIC;
signal \rgb[7]_i_6_n_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \rgb[14]_i_3\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \rgb[14]_i_5\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \rgb[15]_i_2\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \rgb[15]_i_3\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \rgb[15]_i_5\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \rgb[15]_i_6\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \rgb[15]_i_7\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \rgb[22]_i_10\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \rgb[22]_i_11\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \rgb[23]_i_10\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \rgb[23]_i_11\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \rgb[23]_i_14\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \rgb[23]_i_15\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \rgb[23]_i_17\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \rgb[23]_i_18\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \rgb[23]_i_6\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \rgb[5]_i_2\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \rgb[6]_i_2\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \rgb[6]_i_4\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \rgb[6]_i_5\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \rgb[7]_i_3\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \rgb[7]_i_4\ : label is "soft_lutpair5";
begin
\rgb[13]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"5555FF02"
)
port map (
I0 => \rgb[15]_i_4_n_0\,
I1 => \rgb[14]_i_2_n_0\,
I2 => \rgb[14]_i_3_n_0\,
I3 => \rgb[22]_i_2_n_0\,
I4 => \rgb[23]_i_6_n_0\,
O => \rgb[13]_i_1_n_0\
);
\rgb[14]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"55555555FFFFFF02"
)
port map (
I0 => \rgb[15]_i_4_n_0\,
I1 => \rgb[14]_i_2_n_0\,
I2 => \rgb[14]_i_3_n_0\,
I3 => \rgb[22]_i_3_n_0\,
I4 => \rgb[22]_i_2_n_0\,
I5 => \rgb[23]_i_6_n_0\,
O => \rgb[14]_i_1_n_0\
);
\rgb[14]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"02F20202"
)
port map (
I0 => \rgb[14]_i_4_n_0\,
I1 => \rgb[23]_i_11_n_0\,
I2 => xaddr(9),
I3 => \rgb[14]_i_5_n_0\,
I4 => \rgb[23]_i_10_n_0\,
O => \rgb[14]_i_2_n_0\
);
\rgb[14]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \rgb[14]_i_6_n_0\,
I1 => yaddr(6),
O => \rgb[14]_i_3_n_0\
);
\rgb[14]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"FEFEFEFEFEFEFEEE"
)
port map (
I0 => xaddr(4),
I1 => xaddr(5),
I2 => xaddr(3),
I3 => xaddr(0),
I4 => xaddr(1),
I5 => xaddr(2),
O => \rgb[14]_i_4_n_0\
);
\rgb[14]_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFF8"
)
port map (
I0 => xaddr(2),
I1 => xaddr(5),
I2 => xaddr(7),
I3 => xaddr(6),
I4 => xaddr(8),
O => \rgb[14]_i_5_n_0\
);
\rgb[14]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"A888A888A8888888"
)
port map (
I0 => yaddr(5),
I1 => yaddr(4),
I2 => yaddr(2),
I3 => yaddr(3),
I4 => yaddr(1),
I5 => yaddr(0),
O => \rgb[14]_i_6_n_0\
);
\rgb[15]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FFFF55455545"
)
port map (
I0 => \rgb[23]_i_4_n_0\,
I1 => \rgb[22]_i_2_n_0\,
I2 => \rgb[15]_i_2_n_0\,
I3 => \rgb[15]_i_3_n_0\,
I4 => \rgb[15]_i_4_n_0\,
I5 => \rgb[23]_i_6_n_0\,
O => \rgb[15]_i_1_n_0\
);
\rgb[15]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => \rgb[22]_i_8_n_0\,
I1 => \rgb[23]_i_12_n_0\,
O => \rgb[15]_i_2_n_0\
);
\rgb[15]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAA88888"
)
port map (
I0 => \rgb[14]_i_3_n_0\,
I1 => xaddr(9),
I2 => xaddr(6),
I3 => xaddr(7),
I4 => xaddr(8),
O => \rgb[15]_i_3_n_0\
);
\rgb[15]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"ECEEEEEEECECECEC"
)
port map (
I0 => xaddr(8),
I1 => xaddr(9),
I2 => xaddr(7),
I3 => \rgb[15]_i_5_n_0\,
I4 => \rgb[15]_i_6_n_0\,
I5 => \rgb[15]_i_7_n_0\,
O => \rgb[15]_i_4_n_0\
);
\rgb[15]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"1F"
)
port map (
I0 => xaddr(0),
I1 => xaddr(1),
I2 => xaddr(2),
O => \rgb[15]_i_5_n_0\
);
\rgb[15]_i_6\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => xaddr(5),
I1 => xaddr(4),
O => \rgb[15]_i_6_n_0\
);
\rgb[15]_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"8880"
)
port map (
I0 => xaddr(6),
I1 => xaddr(5),
I2 => xaddr(4),
I3 => xaddr(3),
O => \rgb[15]_i_7_n_0\
);
\rgb[21]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFBF0FB"
)
port map (
I0 => \rgb[22]_i_2_n_0\,
I1 => \rgb[22]_i_4_n_0\,
I2 => \rgb[23]_i_2_n_0\,
I3 => \rgb[23]_i_6_n_0\,
I4 => \rgb[23]_i_7_n_0\,
O => \rgb[21]_i_1_n_0\
);
\rgb[22]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFEFFF00FFEF"
)
port map (
I0 => \rgb[22]_i_2_n_0\,
I1 => \rgb[22]_i_3_n_0\,
I2 => \rgb[22]_i_4_n_0\,
I3 => \rgb[23]_i_2_n_0\,
I4 => \rgb[23]_i_6_n_0\,
I5 => \rgb[23]_i_7_n_0\,
O => \rgb[22]_i_1_n_0\
);
\rgb[22]_i_10\: unisim.vcomponents.LUT3
generic map(
INIT => X"01"
)
port map (
I0 => xaddr(9),
I1 => xaddr(6),
I2 => xaddr(7),
O => \rgb[22]_i_10_n_0\
);
\rgb[22]_i_11\: unisim.vcomponents.LUT4
generic map(
INIT => X"0070"
)
port map (
I0 => xaddr(3),
I1 => xaddr(4),
I2 => xaddr(8),
I3 => xaddr(5),
O => \rgb[22]_i_11_n_0\
);
\rgb[22]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000AAABABAB"
)
port map (
I0 => \rgb[22]_i_5_n_0\,
I1 => xaddr(8),
I2 => xaddr(9),
I3 => xaddr(6),
I4 => xaddr(7),
I5 => \rgb[22]_i_6_n_0\,
O => \rgb[22]_i_2_n_0\
);
\rgb[22]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000FD0000"
)
port map (
I0 => \rgb[23]_i_15_n_0\,
I1 => xaddr(4),
I2 => xaddr(5),
I3 => \rgb[22]_i_7_n_0\,
I4 => xaddr(9),
I5 => \rgb[22]_i_6_n_0\,
O => \rgb[22]_i_3_n_0\
);
\rgb[22]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFAE"
)
port map (
I0 => \rgb[23]_i_7_n_0\,
I1 => \rgb[22]_i_8_n_0\,
I2 => \rgb[23]_i_8_n_0\,
I3 => \rgb[14]_i_3_n_0\,
O => \rgb[22]_i_4_n_0\
);
\rgb[22]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000200030003"
)
port map (
I0 => \rgb[15]_i_5_n_0\,
I1 => xaddr(9),
I2 => xaddr(8),
I3 => xaddr(5),
I4 => xaddr(3),
I5 => xaddr(4),
O => \rgb[22]_i_5_n_0\
);
\rgb[22]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"111111111111111F"
)
port map (
I0 => \rgb[14]_i_6_n_0\,
I1 => yaddr(6),
I2 => \rgb[22]_i_9_n_0\,
I3 => xaddr(7),
I4 => xaddr(8),
I5 => xaddr(9),
O => \rgb[22]_i_6_n_0\
);
\rgb[22]_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFEFEFEFFFFFFFF"
)
port map (
I0 => xaddr(8),
I1 => xaddr(6),
I2 => xaddr(7),
I3 => xaddr(5),
I4 => xaddr(2),
I5 => \rgb[23]_i_10_n_0\,
O => \rgb[22]_i_7_n_0\
);
\rgb[22]_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"5515551555151515"
)
port map (
I0 => \rgb[23]_i_14_n_0\,
I1 => \rgb[22]_i_10_n_0\,
I2 => \rgb[22]_i_11_n_0\,
I3 => xaddr(4),
I4 => xaddr(1),
I5 => xaddr(2),
O => \rgb[22]_i_8_n_0\
);
\rgb[22]_i_9\: unisim.vcomponents.LUT6
generic map(
INIT => X"CCCC000088800000"
)
port map (
I0 => xaddr(3),
I1 => xaddr(6),
I2 => xaddr(2),
I3 => xaddr(1),
I4 => xaddr(5),
I5 => xaddr(4),
O => \rgb[22]_i_9_n_0\
);
\rgb[23]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFAAAEAAAEAAAE"
)
port map (
I0 => \rgb[23]_i_2_n_0\,
I1 => \rgb[23]_i_3_n_0\,
I2 => \rgb[23]_i_4_n_0\,
I3 => \rgb[23]_i_5_n_0\,
I4 => \rgb[23]_i_6_n_0\,
I5 => \rgb[23]_i_7_n_0\,
O => \rgb[23]_i_1_n_0\
);
\rgb[23]_i_10\: unisim.vcomponents.LUT3
generic map(
INIT => X"1F"
)
port map (
I0 => xaddr(3),
I1 => xaddr(4),
I2 => xaddr(5),
O => \rgb[23]_i_10_n_0\
);
\rgb[23]_i_11\: unisim.vcomponents.LUT3
generic map(
INIT => X"7F"
)
port map (
I0 => xaddr(8),
I1 => xaddr(6),
I2 => xaddr(7),
O => \rgb[23]_i_11_n_0\
);
\rgb[23]_i_12\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => yaddr(6),
I1 => \rgb[14]_i_6_n_0\,
O => \rgb[23]_i_12_n_0\
);
\rgb[23]_i_13\: unisim.vcomponents.LUT6
generic map(
INIT => X"0515555515155555"
)
port map (
I0 => \rgb[23]_i_18_n_0\,
I1 => xaddr(4),
I2 => xaddr(5),
I3 => \rgb[23]_i_17_n_0\,
I4 => xaddr(6),
I5 => xaddr(3),
O => \rgb[23]_i_13_n_0\
);
\rgb[23]_i_14\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => xaddr(9),
I1 => xaddr(8),
O => \rgb[23]_i_14_n_0\
);
\rgb[23]_i_15\: unisim.vcomponents.LUT3
generic map(
INIT => X"15"
)
port map (
I0 => xaddr(3),
I1 => xaddr(1),
I2 => xaddr(2),
O => \rgb[23]_i_15_n_0\
);
\rgb[23]_i_16\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => xaddr(7),
I1 => xaddr(6),
O => \rgb[23]_i_16_n_0\
);
\rgb[23]_i_17\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => xaddr(2),
I1 => xaddr(1),
O => \rgb[23]_i_17_n_0\
);
\rgb[23]_i_18\: unisim.vcomponents.LUT3
generic map(
INIT => X"FE"
)
port map (
I0 => xaddr(7),
I1 => xaddr(8),
I2 => xaddr(9),
O => \rgb[23]_i_18_n_0\
);
\rgb[23]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000022222"
)
port map (
I0 => \rgb[15]_i_4_n_0\,
I1 => yaddr(6),
I2 => yaddr(4),
I3 => yaddr(3),
I4 => yaddr(5),
I5 => \rgb[23]_i_8_n_0\,
O => \rgb[23]_i_2_n_0\
);
\rgb[23]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAFFFB"
)
port map (
I0 => \rgb[14]_i_3_n_0\,
I1 => \rgb[15]_i_4_n_0\,
I2 => \rgb[23]_i_9_n_0\,
I3 => xaddr(9),
I4 => \rgb[23]_i_7_n_0\,
O => \rgb[23]_i_3_n_0\
);
\rgb[23]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"00004440"
)
port map (
I0 => xaddr(9),
I1 => \rgb[23]_i_9_n_0\,
I2 => \rgb[23]_i_10_n_0\,
I3 => \rgb[23]_i_11_n_0\,
I4 => \rgb[23]_i_12_n_0\,
O => \rgb[23]_i_4_n_0\
);
\rgb[23]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"0057FFFF00570057"
)
port map (
I0 => yaddr(5),
I1 => yaddr(3),
I2 => yaddr(4),
I3 => yaddr(6),
I4 => \rgb[23]_i_12_n_0\,
I5 => \rgb[23]_i_13_n_0\,
O => \rgb[23]_i_5_n_0\
);
\rgb[23]_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"0155"
)
port map (
I0 => yaddr(6),
I1 => yaddr(4),
I2 => yaddr(3),
I3 => yaddr(5),
O => \rgb[23]_i_6_n_0\
);
\rgb[23]_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"40CC44CC44CC44CC"
)
port map (
I0 => xaddr(6),
I1 => \rgb[23]_i_14_n_0\,
I2 => \rgb[23]_i_15_n_0\,
I3 => xaddr(7),
I4 => xaddr(4),
I5 => xaddr(5),
O => \rgb[23]_i_7_n_0\
);
\rgb[23]_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFD500000000"
)
port map (
I0 => \rgb[23]_i_10_n_0\,
I1 => xaddr(2),
I2 => xaddr(5),
I3 => \rgb[23]_i_16_n_0\,
I4 => xaddr(8),
I5 => xaddr(9),
O => \rgb[23]_i_8_n_0\
);
\rgb[23]_i_9\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000FFFFFFE0"
)
port map (
I0 => \rgb[23]_i_17_n_0\,
I1 => xaddr(0),
I2 => xaddr(3),
I3 => xaddr(5),
I4 => xaddr(4),
I5 => \rgb[23]_i_11_n_0\,
O => \rgb[23]_i_9_n_0\
);
\rgb[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"04770404"
)
port map (
I0 => \rgb[6]_i_2_n_0\,
I1 => \rgb[23]_i_6_n_0\,
I2 => \rgb[23]_i_7_n_0\,
I3 => \rgb[4]_i_2_n_0\,
I4 => \rgb[5]_i_2_n_0\,
O => \rgb[4]_i_1_n_0\
);
\rgb[4]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF2F2FFFFF202F"
)
port map (
I0 => \rgb[22]_i_8_n_0\,
I1 => \rgb[15]_i_4_n_0\,
I2 => \rgb[23]_i_12_n_0\,
I3 => \rgb[6]_i_5_n_0\,
I4 => \rgb[23]_i_6_n_0\,
I5 => \rgb[23]_i_13_n_0\,
O => \rgb[4]_i_2_n_0\
);
\rgb[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAFEAAAAAAAA"
)
port map (
I0 => \rgb[7]_i_4_n_0\,
I1 => \rgb[15]_i_2_n_0\,
I2 => \rgb[15]_i_4_n_0\,
I3 => \rgb[15]_i_3_n_0\,
I4 => \rgb[23]_i_6_n_0\,
I5 => \rgb[5]_i_2_n_0\,
O => \rgb[5]_i_1_n_0\
);
\rgb[5]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"7F7F0F7F"
)
port map (
I0 => \rgb[14]_i_2_n_0\,
I1 => \rgb[22]_i_8_n_0\,
I2 => \rgb[23]_i_12_n_0\,
I3 => \rgb[23]_i_7_n_0\,
I4 => \rgb[7]_i_3_n_0\,
O => \rgb[5]_i_2_n_0\
);
\rgb[6]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"000F000FFFFF0045"
)
port map (
I0 => \rgb[14]_i_3_n_0\,
I1 => \rgb[7]_i_3_n_0\,
I2 => \rgb[23]_i_7_n_0\,
I3 => \rgb[6]_i_2_n_0\,
I4 => \rgb[6]_i_3_n_0\,
I5 => \rgb[23]_i_6_n_0\,
O => \rgb[6]_i_1_n_0\
);
\rgb[6]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"EA"
)
port map (
I0 => \rgb[14]_i_2_n_0\,
I1 => \rgb[22]_i_8_n_0\,
I2 => \rgb[7]_i_6_n_0\,
O => \rgb[6]_i_2_n_0\
);
\rgb[6]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"00FF0002"
)
port map (
I0 => xaddr(9),
I1 => \rgb[22]_i_7_n_0\,
I2 => \rgb[6]_i_4_n_0\,
I3 => \rgb[22]_i_6_n_0\,
I4 => \rgb[6]_i_5_n_0\,
O => \rgb[6]_i_3_n_0\
);
\rgb[6]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000007"
)
port map (
I0 => xaddr(2),
I1 => xaddr(1),
I2 => xaddr(3),
I3 => xaddr(4),
I4 => xaddr(5),
O => \rgb[6]_i_4_n_0\
);
\rgb[6]_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"0057"
)
port map (
I0 => xaddr(8),
I1 => xaddr(7),
I2 => xaddr(6),
I3 => xaddr(9),
O => \rgb[6]_i_5_n_0\
);
\rgb[7]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"0000222A"
)
port map (
I0 => \rgb[7]_i_3_n_0\,
I1 => yaddr(5),
I2 => yaddr(3),
I3 => yaddr(4),
I4 => yaddr(6),
O => \rgb[7]_i_1_n_0\
);
\rgb[7]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF000000FB"
)
port map (
I0 => \rgb[7]_i_3_n_0\,
I1 => \rgb[23]_i_7_n_0\,
I2 => \rgb[14]_i_3_n_0\,
I3 => \rgb[23]_i_4_n_0\,
I4 => \rgb[23]_i_6_n_0\,
I5 => \rgb[7]_i_4_n_0\,
O => \rgb[7]_i_2_n_0\
);
\rgb[7]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"0000000D"
)
port map (
I0 => xaddr(6),
I1 => \rgb[7]_i_5_n_0\,
I2 => xaddr(9),
I3 => xaddr(8),
I4 => xaddr(7),
O => \rgb[7]_i_3_n_0\
);
\rgb[7]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000444"
)
port map (
I0 => \rgb[23]_i_7_n_0\,
I1 => \rgb[23]_i_6_n_0\,
I2 => \rgb[7]_i_6_n_0\,
I3 => \rgb[22]_i_8_n_0\,
I4 => \rgb[14]_i_2_n_0\,
O => \rgb[7]_i_4_n_0\
);
\rgb[7]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"1515155515155555"
)
port map (
I0 => xaddr(5),
I1 => xaddr(3),
I2 => xaddr(4),
I3 => xaddr(0),
I4 => xaddr(2),
I5 => xaddr(1),
O => \rgb[7]_i_5_n_0\
);
\rgb[7]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000007F55"
)
port map (
I0 => \rgb[15]_i_7_n_0\,
I1 => xaddr(4),
I2 => xaddr(5),
I3 => \rgb[15]_i_5_n_0\,
I4 => xaddr(7),
I5 => xaddr(9),
O => \rgb[7]_i_6_n_0\
);
\rgb_reg[13]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \rgb[13]_i_1_n_0\,
Q => rgb(4),
R => '0'
);
\rgb_reg[14]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \rgb[14]_i_1_n_0\,
Q => rgb(5),
R => '0'
);
\rgb_reg[15]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \rgb[15]_i_1_n_0\,
Q => rgb(6),
R => '0'
);
\rgb_reg[21]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \rgb[21]_i_1_n_0\,
Q => rgb(7),
R => '0'
);
\rgb_reg[22]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \rgb[22]_i_1_n_0\,
Q => rgb(8),
R => '0'
);
\rgb_reg[23]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \rgb[23]_i_1_n_0\,
Q => rgb(9),
R => '0'
);
\rgb_reg[4]\: unisim.vcomponents.FDSE
port map (
C => clk_25,
CE => '1',
D => \rgb[4]_i_1_n_0\,
Q => rgb(0),
S => \rgb[7]_i_1_n_0\
);
\rgb_reg[5]\: unisim.vcomponents.FDSE
port map (
C => clk_25,
CE => '1',
D => \rgb[5]_i_1_n_0\,
Q => rgb(1),
S => \rgb[7]_i_1_n_0\
);
\rgb_reg[6]\: unisim.vcomponents.FDSE
port map (
C => clk_25,
CE => '1',
D => \rgb[6]_i_1_n_0\,
Q => rgb(2),
S => \rgb[7]_i_1_n_0\
);
\rgb_reg[7]\: unisim.vcomponents.FDSE
port map (
C => clk_25,
CE => '1',
D => \rgb[7]_i_2_n_0\,
Q => rgb(3),
S => \rgb[7]_i_1_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_vga_color_test_0_0 is
port (
clk_25 : in STD_LOGIC;
xaddr : in STD_LOGIC_VECTOR ( 9 downto 0 );
yaddr : in STD_LOGIC_VECTOR ( 9 downto 0 );
rgb : out STD_LOGIC_VECTOR ( 23 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_vga_color_test_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_vga_color_test_0_0 : entity is "system_vga_color_test_0_0,vga_color_test,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_vga_color_test_0_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_vga_color_test_0_0 : entity is "vga_color_test,Vivado 2016.4";
end system_vga_color_test_0_0;
architecture STRUCTURE of system_vga_color_test_0_0 is
signal \^rgb\ : STD_LOGIC_VECTOR ( 23 downto 3 );
begin
rgb(23 downto 22) <= \^rgb\(23 downto 22);
rgb(21) <= \^rgb\(20);
rgb(20) <= \^rgb\(20);
rgb(19) <= \^rgb\(20);
rgb(18) <= \^rgb\(20);
rgb(17) <= \^rgb\(20);
rgb(16) <= \^rgb\(20);
rgb(15 downto 14) <= \^rgb\(15 downto 14);
rgb(13) <= \^rgb\(12);
rgb(12) <= \^rgb\(12);
rgb(11) <= \^rgb\(12);
rgb(10) <= \^rgb\(12);
rgb(9) <= \^rgb\(12);
rgb(8) <= \^rgb\(12);
rgb(7 downto 5) <= \^rgb\(7 downto 5);
rgb(4) <= \^rgb\(3);
rgb(3) <= \^rgb\(3);
rgb(2) <= \^rgb\(3);
rgb(1) <= \^rgb\(3);
rgb(0) <= \^rgb\(3);
U0: entity work.system_vga_color_test_0_0_vga_color_test
port map (
clk_25 => clk_25,
rgb(9 downto 8) => \^rgb\(23 downto 22),
rgb(7) => \^rgb\(20),
rgb(6 downto 5) => \^rgb\(15 downto 14),
rgb(4) => \^rgb\(12),
rgb(3 downto 1) => \^rgb\(7 downto 5),
rgb(0) => \^rgb\(3),
xaddr(9 downto 0) => xaddr(9 downto 0),
yaddr(6 downto 0) => yaddr(9 downto 3)
);
end STRUCTURE;
| mit |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | video_ip/axi_vga_framebuffer_1.0/hdl/axi_vga_framebuffer_v1_0.vhd | 1 | 4600 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity axi_vga_framebuffer_v1_0 is
generic (
-- Users to add parameters here
-- User parameters ends
-- Do not modify the parameters beyond this line
-- Parameters of Axi Slave Bus Interface S_AXI
C_S_AXI_DATA_WIDTH : integer := 32;
C_S_AXI_ADDR_WIDTH : integer := 11
);
port (
-- Users to add ports here
clk : in std_logic;
active : in std_logic;
x_addr_w : in std_logic_vector(9 downto 0);
y_addr_w : in std_logic_vector(9 downto 0);
x_addr_r : in std_logic_vector(9 downto 0);
y_addr_r : in std_logic_vector(9 downto 0);
data_w : in std_logic_vector(23 downto 0);
data_r : out std_logic_vector(23 downto 0);
-- User ports ends
-- Do not modify the ports beyond this line
-- Ports of Axi Slave Bus Interface S_AXI
s_axi_aclk : in std_logic;
s_axi_aresetn : in std_logic;
s_axi_awaddr : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
s_axi_awprot : in std_logic_vector(2 downto 0);
s_axi_awvalid : in std_logic;
s_axi_awready : out std_logic;
s_axi_wdata : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
s_axi_wstrb : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
s_axi_wvalid : in std_logic;
s_axi_wready : out std_logic;
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic;
s_axi_araddr : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
s_axi_arprot : in std_logic_vector(2 downto 0);
s_axi_arvalid : in std_logic;
s_axi_arready : out std_logic;
s_axi_rdata : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
s_axi_rresp : out std_logic_vector(1 downto 0);
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic
);
end axi_vga_framebuffer_v1_0;
architecture arch_imp of axi_vga_framebuffer_v1_0 is
-- component declaration
component axi_vga_framebuffer_v1_0_S_AXI is
generic (
C_S_AXI_DATA_WIDTH : integer := 32;
C_S_AXI_ADDR_WIDTH : integer := 11
);
port (
-- user ports
clk : in std_logic;
active : in std_logic;
x_addr_w : in std_logic_vector(9 downto 0);
y_addr_w : in std_logic_vector(9 downto 0);
x_addr_r : in std_logic_vector(9 downto 0);
y_addr_r : in std_logic_vector(9 downto 0);
data_w : in std_logic_vector(23 downto 0);
data_r : out std_logic_vector(23 downto 0);
--
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWPROT : in std_logic_vector(2 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARPROT : in std_logic_vector(2 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic
);
end component axi_vga_framebuffer_v1_0_S_AXI;
begin
-- Instantiation of Axi Bus Interface S_AXI
axi_vga_framebuffer_v1_0_S_AXI_inst : axi_vga_framebuffer_v1_0_S_AXI
generic map (
C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH,
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH
)
port map (
clk => clk,
active => active,
x_addr_w => x_addr_w,
y_addr_w => y_addr_w,
x_addr_r => x_addr_r,
y_addr_r => y_addr_r,
data_w => data_w,
data_r => data_r,
S_AXI_ACLK => s_axi_aclk,
S_AXI_ARESETN => s_axi_aresetn,
S_AXI_AWADDR => s_axi_awaddr,
S_AXI_AWPROT => s_axi_awprot,
S_AXI_AWVALID => s_axi_awvalid,
S_AXI_AWREADY => s_axi_awready,
S_AXI_WDATA => s_axi_wdata,
S_AXI_WSTRB => s_axi_wstrb,
S_AXI_WVALID => s_axi_wvalid,
S_AXI_WREADY => s_axi_wready,
S_AXI_BRESP => s_axi_bresp,
S_AXI_BVALID => s_axi_bvalid,
S_AXI_BREADY => s_axi_bready,
S_AXI_ARADDR => s_axi_araddr,
S_AXI_ARPROT => s_axi_arprot,
S_AXI_ARVALID => s_axi_arvalid,
S_AXI_ARREADY => s_axi_arready,
S_AXI_RDATA => s_axi_rdata,
S_AXI_RRESP => s_axi_rresp,
S_AXI_RVALID => s_axi_rvalid,
S_AXI_RREADY => s_axi_rready
);
-- Add user logic here
-- User logic ends
end arch_imp;
| mit |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_vga_test/zed_vga_test.srcs/sources_1/bd/system/ip/system_vga_sync_0_0/synth/system_vga_sync_0_0.vhd | 2 | 4819 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:vga_sync:1.0
-- IP Revision: 8
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_vga_sync_0_0 IS
PORT (
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
active : OUT STD_LOGIC;
hsync : OUT STD_LOGIC;
vsync : OUT STD_LOGIC;
xaddr : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
yaddr : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END system_vga_sync_0_0;
ARCHITECTURE system_vga_sync_0_0_arch OF system_vga_sync_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_vga_sync_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT vga_sync IS
GENERIC (
H_SIZE : INTEGER;
H_FRONT_DELAY : INTEGER;
H_BACK_DELAY : INTEGER;
H_RETRACE_DELAY : INTEGER;
V_SIZE : INTEGER;
V_FRONT_DELAY : INTEGER;
V_BACK_DELAY : INTEGER;
V_RETRACE_DELAY : INTEGER
);
PORT (
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
active : OUT STD_LOGIC;
hsync : OUT STD_LOGIC;
vsync : OUT STD_LOGIC;
xaddr : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
yaddr : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END COMPONENT vga_sync;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF system_vga_sync_0_0_arch: ARCHITECTURE IS "vga_sync,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF system_vga_sync_0_0_arch : ARCHITECTURE IS "system_vga_sync_0_0,vga_sync,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF system_vga_sync_0_0_arch: ARCHITECTURE IS "system_vga_sync_0_0,vga_sync,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=user,x_ipName=vga_sync,x_ipVersion=1.0,x_ipCoreRevision=8,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,H_SIZE=640,H_FRONT_DELAY=16,H_BACK_DELAY=48,H_RETRACE_DELAY=96,V_SIZE=480,V_FRONT_DELAY=10,V_BACK_DELAY=33,V_RETRACE_DELAY=2}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clk CLK";
ATTRIBUTE X_INTERFACE_INFO OF rst: SIGNAL IS "xilinx.com:signal:reset:1.0 rst RST";
BEGIN
U0 : vga_sync
GENERIC MAP (
H_SIZE => 640,
H_FRONT_DELAY => 16,
H_BACK_DELAY => 48,
H_RETRACE_DELAY => 96,
V_SIZE => 480,
V_FRONT_DELAY => 10,
V_BACK_DELAY => 33,
V_RETRACE_DELAY => 2
)
PORT MAP (
clk => clk,
rst => rst,
active => active,
hsync => hsync,
vsync => vsync,
xaddr => xaddr,
yaddr => yaddr
);
END system_vga_sync_0_0_arch;
| mit |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | general_ip/affine_transform/affine_transform.srcs/sources_1/bd/affine_block/ip/affine_block_ieee754_fp_multiplier_1_2/affine_block_ieee754_fp_multiplier_1_2_sim_netlist.vhdl | 1 | 200504 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Mon Feb 20 13:53:00 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim -rename_top affine_block_ieee754_fp_multiplier_1_2 -prefix
-- affine_block_ieee754_fp_multiplier_1_2_ affine_block_ieee754_fp_multiplier_0_0_sim_netlist.vhdl
-- Design : affine_block_ieee754_fp_multiplier_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z010clg400-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity affine_block_ieee754_fp_multiplier_1_2_ieee754_fp_multiplier is
port (
z : out STD_LOGIC_VECTOR ( 7 downto 0 );
z_mantissa : out STD_LOGIC_VECTOR ( 22 downto 0 );
x : in STD_LOGIC_VECTOR ( 30 downto 0 );
y : in STD_LOGIC_VECTOR ( 30 downto 0 );
\y_11__s_port_\ : in STD_LOGIC
);
end affine_block_ieee754_fp_multiplier_1_2_ieee754_fp_multiplier;
architecture STRUCTURE of affine_block_ieee754_fp_multiplier_1_2_ieee754_fp_multiplier is
signal L1 : STD_LOGIC;
signal \L1_carry__0_i_1_n_0\ : STD_LOGIC;
signal \L1_carry__0_i_2_n_0\ : STD_LOGIC;
signal \L1_carry__0_i_3_n_0\ : STD_LOGIC;
signal \L1_carry__0_i_4_n_0\ : STD_LOGIC;
signal \L1_carry__0_i_5_n_0\ : STD_LOGIC;
signal \L1_carry__0_i_6_n_0\ : STD_LOGIC;
signal \L1_carry__0_i_7_n_0\ : STD_LOGIC;
signal \L1_carry__0_i_8_n_0\ : STD_LOGIC;
signal \L1_carry__0_n_0\ : STD_LOGIC;
signal \L1_carry__0_n_1\ : STD_LOGIC;
signal \L1_carry__0_n_2\ : STD_LOGIC;
signal \L1_carry__0_n_3\ : STD_LOGIC;
signal \L1_carry__1_i_1_n_0\ : STD_LOGIC;
signal \L1_carry__1_i_2_n_0\ : STD_LOGIC;
signal \L1_carry__1_i_3_n_0\ : STD_LOGIC;
signal \L1_carry__1_i_4_n_0\ : STD_LOGIC;
signal \L1_carry__1_i_5_n_0\ : STD_LOGIC;
signal \L1_carry__1_i_6_n_0\ : STD_LOGIC;
signal \L1_carry__1_i_7_n_0\ : STD_LOGIC;
signal \L1_carry__1_i_8_n_0\ : STD_LOGIC;
signal \L1_carry__1_n_0\ : STD_LOGIC;
signal \L1_carry__1_n_1\ : STD_LOGIC;
signal \L1_carry__1_n_2\ : STD_LOGIC;
signal \L1_carry__1_n_3\ : STD_LOGIC;
signal \L1_carry__2_i_1_n_0\ : STD_LOGIC;
signal \L1_carry__2_i_2_n_0\ : STD_LOGIC;
signal \L1_carry__2_i_3_n_0\ : STD_LOGIC;
signal \L1_carry__2_i_4_n_0\ : STD_LOGIC;
signal \L1_carry__2_i_5_n_0\ : STD_LOGIC;
signal \L1_carry__2_i_6_n_0\ : STD_LOGIC;
signal \L1_carry__2_i_7_n_0\ : STD_LOGIC;
signal \L1_carry__2_n_1\ : STD_LOGIC;
signal \L1_carry__2_n_2\ : STD_LOGIC;
signal \L1_carry__2_n_3\ : STD_LOGIC;
signal L1_carry_i_10_n_0 : STD_LOGIC;
signal L1_carry_i_11_n_0 : STD_LOGIC;
signal L1_carry_i_12_n_0 : STD_LOGIC;
signal L1_carry_i_13_n_0 : STD_LOGIC;
signal L1_carry_i_14_n_0 : STD_LOGIC;
signal L1_carry_i_15_n_0 : STD_LOGIC;
signal L1_carry_i_16_n_0 : STD_LOGIC;
signal L1_carry_i_17_n_0 : STD_LOGIC;
signal L1_carry_i_18_n_0 : STD_LOGIC;
signal L1_carry_i_19_n_0 : STD_LOGIC;
signal L1_carry_i_1_n_0 : STD_LOGIC;
signal L1_carry_i_20_n_0 : STD_LOGIC;
signal L1_carry_i_21_n_0 : STD_LOGIC;
signal L1_carry_i_22_n_0 : STD_LOGIC;
signal L1_carry_i_23_n_0 : STD_LOGIC;
signal L1_carry_i_24_n_0 : STD_LOGIC;
signal L1_carry_i_25_n_0 : STD_LOGIC;
signal L1_carry_i_26_n_0 : STD_LOGIC;
signal L1_carry_i_27_n_0 : STD_LOGIC;
signal L1_carry_i_28_n_0 : STD_LOGIC;
signal L1_carry_i_29_n_0 : STD_LOGIC;
signal L1_carry_i_2_n_0 : STD_LOGIC;
signal L1_carry_i_30_n_0 : STD_LOGIC;
signal L1_carry_i_31_n_0 : STD_LOGIC;
signal L1_carry_i_32_n_0 : STD_LOGIC;
signal L1_carry_i_33_n_0 : STD_LOGIC;
signal L1_carry_i_34_n_0 : STD_LOGIC;
signal L1_carry_i_35_n_0 : STD_LOGIC;
signal L1_carry_i_36_n_0 : STD_LOGIC;
signal L1_carry_i_37_n_0 : STD_LOGIC;
signal L1_carry_i_38_n_0 : STD_LOGIC;
signal L1_carry_i_39_n_0 : STD_LOGIC;
signal L1_carry_i_3_n_0 : STD_LOGIC;
signal L1_carry_i_40_n_0 : STD_LOGIC;
signal L1_carry_i_41_n_0 : STD_LOGIC;
signal L1_carry_i_42_n_0 : STD_LOGIC;
signal L1_carry_i_43_n_0 : STD_LOGIC;
signal L1_carry_i_44_n_0 : STD_LOGIC;
signal L1_carry_i_45_n_0 : STD_LOGIC;
signal L1_carry_i_46_n_0 : STD_LOGIC;
signal L1_carry_i_47_n_0 : STD_LOGIC;
signal L1_carry_i_48_n_0 : STD_LOGIC;
signal L1_carry_i_49_n_0 : STD_LOGIC;
signal L1_carry_i_4_n_0 : STD_LOGIC;
signal L1_carry_i_50_n_0 : STD_LOGIC;
signal L1_carry_i_51_n_0 : STD_LOGIC;
signal L1_carry_i_52_n_0 : STD_LOGIC;
signal L1_carry_i_53_n_0 : STD_LOGIC;
signal L1_carry_i_54_n_0 : STD_LOGIC;
signal L1_carry_i_5_n_0 : STD_LOGIC;
signal L1_carry_i_6_n_0 : STD_LOGIC;
signal L1_carry_i_7_n_0 : STD_LOGIC;
signal L1_carry_i_8_n_0 : STD_LOGIC;
signal L1_carry_i_9_n_0 : STD_LOGIC;
signal L1_carry_n_0 : STD_LOGIC;
signal L1_carry_n_1 : STD_LOGIC;
signal L1_carry_n_2 : STD_LOGIC;
signal L1_carry_n_3 : STD_LOGIC;
signal \_carry__0_i_1_n_0\ : STD_LOGIC;
signal \_carry__0_i_2_n_0\ : STD_LOGIC;
signal \_carry__0_i_3_n_0\ : STD_LOGIC;
signal \_carry__0_i_4_n_0\ : STD_LOGIC;
signal \_carry__0_n_0\ : STD_LOGIC;
signal \_carry__0_n_1\ : STD_LOGIC;
signal \_carry__0_n_2\ : STD_LOGIC;
signal \_carry__0_n_3\ : STD_LOGIC;
signal \_carry__0_n_4\ : STD_LOGIC;
signal \_carry__0_n_5\ : STD_LOGIC;
signal \_carry__0_n_6\ : STD_LOGIC;
signal \_carry__0_n_7\ : STD_LOGIC;
signal \_carry__1_i_1_n_0\ : STD_LOGIC;
signal \_carry__1_i_2_n_0\ : STD_LOGIC;
signal \_carry__1_i_3_n_0\ : STD_LOGIC;
signal \_carry__1_i_4_n_0\ : STD_LOGIC;
signal \_carry__1_n_0\ : STD_LOGIC;
signal \_carry__1_n_1\ : STD_LOGIC;
signal \_carry__1_n_2\ : STD_LOGIC;
signal \_carry__1_n_3\ : STD_LOGIC;
signal \_carry__1_n_4\ : STD_LOGIC;
signal \_carry__1_n_5\ : STD_LOGIC;
signal \_carry__1_n_6\ : STD_LOGIC;
signal \_carry__1_n_7\ : STD_LOGIC;
signal \_carry__2_i_1_n_0\ : STD_LOGIC;
signal \_carry__2_i_2_n_0\ : STD_LOGIC;
signal \_carry__2_i_3_n_0\ : STD_LOGIC;
signal \_carry__2_i_4_n_0\ : STD_LOGIC;
signal \_carry__2_n_0\ : STD_LOGIC;
signal \_carry__2_n_1\ : STD_LOGIC;
signal \_carry__2_n_2\ : STD_LOGIC;
signal \_carry__2_n_3\ : STD_LOGIC;
signal \_carry__2_n_4\ : STD_LOGIC;
signal \_carry__2_n_5\ : STD_LOGIC;
signal \_carry__2_n_6\ : STD_LOGIC;
signal \_carry__2_n_7\ : STD_LOGIC;
signal \_carry__3_i_1_n_0\ : STD_LOGIC;
signal \_carry__3_i_2_n_0\ : STD_LOGIC;
signal \_carry__3_i_3_n_0\ : STD_LOGIC;
signal \_carry__3_i_4_n_0\ : STD_LOGIC;
signal \_carry__3_n_0\ : STD_LOGIC;
signal \_carry__3_n_1\ : STD_LOGIC;
signal \_carry__3_n_2\ : STD_LOGIC;
signal \_carry__3_n_3\ : STD_LOGIC;
signal \_carry__3_n_4\ : STD_LOGIC;
signal \_carry__3_n_5\ : STD_LOGIC;
signal \_carry__3_n_6\ : STD_LOGIC;
signal \_carry__3_n_7\ : STD_LOGIC;
signal \_carry__4_i_1_n_0\ : STD_LOGIC;
signal \_carry__4_i_2_n_0\ : STD_LOGIC;
signal \_carry__4_i_3_n_0\ : STD_LOGIC;
signal \_carry__4_i_4_n_0\ : STD_LOGIC;
signal \_carry__4_n_0\ : STD_LOGIC;
signal \_carry__4_n_1\ : STD_LOGIC;
signal \_carry__4_n_2\ : STD_LOGIC;
signal \_carry__4_n_3\ : STD_LOGIC;
signal \_carry__4_n_4\ : STD_LOGIC;
signal \_carry__4_n_5\ : STD_LOGIC;
signal \_carry__4_n_6\ : STD_LOGIC;
signal \_carry__4_n_7\ : STD_LOGIC;
signal \_carry__5_i_1_n_0\ : STD_LOGIC;
signal \_carry__5_i_2_n_0\ : STD_LOGIC;
signal \_carry__5_i_3_n_0\ : STD_LOGIC;
signal \_carry__5_i_4_n_0\ : STD_LOGIC;
signal \_carry__5_n_0\ : STD_LOGIC;
signal \_carry__5_n_1\ : STD_LOGIC;
signal \_carry__5_n_2\ : STD_LOGIC;
signal \_carry__5_n_3\ : STD_LOGIC;
signal \_carry__5_n_4\ : STD_LOGIC;
signal \_carry__5_n_5\ : STD_LOGIC;
signal \_carry__5_n_6\ : STD_LOGIC;
signal \_carry__5_n_7\ : STD_LOGIC;
signal \_carry__6_i_1_n_0\ : STD_LOGIC;
signal \_carry__6_i_2_n_0\ : STD_LOGIC;
signal \_carry__6_n_3\ : STD_LOGIC;
signal \_carry__6_n_6\ : STD_LOGIC;
signal \_carry__6_n_7\ : STD_LOGIC;
signal \_carry_i_10_n_0\ : STD_LOGIC;
signal \_carry_i_11_n_0\ : STD_LOGIC;
signal \_carry_i_12_n_0\ : STD_LOGIC;
signal \_carry_i_13_n_0\ : STD_LOGIC;
signal \_carry_i_14_n_0\ : STD_LOGIC;
signal \_carry_i_15_n_0\ : STD_LOGIC;
signal \_carry_i_16_n_0\ : STD_LOGIC;
signal \_carry_i_17_n_0\ : STD_LOGIC;
signal \_carry_i_18_n_0\ : STD_LOGIC;
signal \_carry_i_19_n_0\ : STD_LOGIC;
signal \_carry_i_1_n_0\ : STD_LOGIC;
signal \_carry_i_20_n_0\ : STD_LOGIC;
signal \_carry_i_21_n_0\ : STD_LOGIC;
signal \_carry_i_22_n_0\ : STD_LOGIC;
signal \_carry_i_23_n_0\ : STD_LOGIC;
signal \_carry_i_24_n_0\ : STD_LOGIC;
signal \_carry_i_2_n_0\ : STD_LOGIC;
signal \_carry_i_3_n_0\ : STD_LOGIC;
signal \_carry_i_4_n_0\ : STD_LOGIC;
signal \_carry_i_6_n_0\ : STD_LOGIC;
signal \_carry_i_7_n_0\ : STD_LOGIC;
signal \_carry_i_8_n_0\ : STD_LOGIC;
signal \_carry_i_9_n_0\ : STD_LOGIC;
signal \_carry_n_0\ : STD_LOGIC;
signal \_carry_n_1\ : STD_LOGIC;
signal \_carry_n_2\ : STD_LOGIC;
signal \_carry_n_3\ : STD_LOGIC;
signal \_carry_n_4\ : STD_LOGIC;
signal \_carry_n_5\ : STD_LOGIC;
signal \_carry_n_6\ : STD_LOGIC;
signal \_carry_n_7\ : STD_LOGIC;
signal data0 : STD_LOGIC_VECTOR ( 7 downto 0 );
signal data1 : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \msb1__1\ : STD_LOGIC_VECTOR ( 47 downto 0 );
signal msb1_n_106 : STD_LOGIC;
signal msb1_n_107 : STD_LOGIC;
signal msb1_n_108 : STD_LOGIC;
signal msb1_n_109 : STD_LOGIC;
signal msb1_n_110 : STD_LOGIC;
signal msb1_n_111 : STD_LOGIC;
signal msb1_n_112 : STD_LOGIC;
signal msb1_n_113 : STD_LOGIC;
signal msb1_n_114 : STD_LOGIC;
signal msb1_n_115 : STD_LOGIC;
signal msb1_n_116 : STD_LOGIC;
signal msb1_n_117 : STD_LOGIC;
signal msb1_n_118 : STD_LOGIC;
signal msb1_n_119 : STD_LOGIC;
signal msb1_n_120 : STD_LOGIC;
signal msb1_n_121 : STD_LOGIC;
signal msb1_n_122 : STD_LOGIC;
signal msb1_n_123 : STD_LOGIC;
signal msb1_n_124 : STD_LOGIC;
signal msb1_n_125 : STD_LOGIC;
signal msb1_n_126 : STD_LOGIC;
signal msb1_n_127 : STD_LOGIC;
signal msb1_n_128 : STD_LOGIC;
signal msb1_n_129 : STD_LOGIC;
signal msb1_n_130 : STD_LOGIC;
signal msb1_n_131 : STD_LOGIC;
signal msb1_n_132 : STD_LOGIC;
signal msb1_n_133 : STD_LOGIC;
signal msb1_n_134 : STD_LOGIC;
signal msb1_n_135 : STD_LOGIC;
signal msb1_n_136 : STD_LOGIC;
signal msb1_n_137 : STD_LOGIC;
signal msb1_n_138 : STD_LOGIC;
signal msb1_n_139 : STD_LOGIC;
signal msb1_n_140 : STD_LOGIC;
signal msb1_n_141 : STD_LOGIC;
signal msb1_n_142 : STD_LOGIC;
signal msb1_n_143 : STD_LOGIC;
signal msb1_n_144 : STD_LOGIC;
signal msb1_n_145 : STD_LOGIC;
signal msb1_n_146 : STD_LOGIC;
signal msb1_n_147 : STD_LOGIC;
signal msb1_n_148 : STD_LOGIC;
signal msb1_n_149 : STD_LOGIC;
signal msb1_n_150 : STD_LOGIC;
signal msb1_n_151 : STD_LOGIC;
signal msb1_n_152 : STD_LOGIC;
signal msb1_n_153 : STD_LOGIC;
signal msb1_n_58 : STD_LOGIC;
signal msb1_n_59 : STD_LOGIC;
signal msb1_n_60 : STD_LOGIC;
signal msb1_n_61 : STD_LOGIC;
signal msb1_n_62 : STD_LOGIC;
signal msb1_n_63 : STD_LOGIC;
signal msb1_n_64 : STD_LOGIC;
signal msb1_n_65 : STD_LOGIC;
signal msb1_n_66 : STD_LOGIC;
signal msb1_n_67 : STD_LOGIC;
signal msb1_n_68 : STD_LOGIC;
signal msb1_n_69 : STD_LOGIC;
signal msb1_n_70 : STD_LOGIC;
signal msb1_n_71 : STD_LOGIC;
signal msb1_n_72 : STD_LOGIC;
signal msb1_n_73 : STD_LOGIC;
signal msb1_n_74 : STD_LOGIC;
signal msb1_n_75 : STD_LOGIC;
signal msb1_n_76 : STD_LOGIC;
signal msb1_n_77 : STD_LOGIC;
signal msb1_n_78 : STD_LOGIC;
signal msb1_n_79 : STD_LOGIC;
signal msb1_n_80 : STD_LOGIC;
signal msb1_n_81 : STD_LOGIC;
signal msb1_n_82 : STD_LOGIC;
signal msb1_n_83 : STD_LOGIC;
signal msb1_n_84 : STD_LOGIC;
signal msb1_n_85 : STD_LOGIC;
signal msb1_n_86 : STD_LOGIC;
signal msb1_n_87 : STD_LOGIC;
signal msb1_n_88 : STD_LOGIC;
signal p_0_in : STD_LOGIC_VECTOR ( 1 to 1 );
signal sel0 : STD_LOGIC_VECTOR ( 22 downto 0 );
signal \y_11__s_net_1\ : STD_LOGIC;
signal \z[11]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \z[11]_INST_0_i_1_n_1\ : STD_LOGIC;
signal \z[11]_INST_0_i_1_n_2\ : STD_LOGIC;
signal \z[11]_INST_0_i_1_n_3\ : STD_LOGIC;
signal \z[11]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \z[11]_INST_0_i_6_n_0\ : STD_LOGIC;
signal \z[11]_INST_0_i_7_n_0\ : STD_LOGIC;
signal \z[11]_INST_0_i_8_n_0\ : STD_LOGIC;
signal \z[11]_INST_0_i_9_n_0\ : STD_LOGIC;
signal \z[15]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \z[15]_INST_0_i_1_n_1\ : STD_LOGIC;
signal \z[15]_INST_0_i_1_n_2\ : STD_LOGIC;
signal \z[15]_INST_0_i_1_n_3\ : STD_LOGIC;
signal \z[15]_INST_0_i_6_n_0\ : STD_LOGIC;
signal \z[15]_INST_0_i_7_n_0\ : STD_LOGIC;
signal \z[15]_INST_0_i_8_n_0\ : STD_LOGIC;
signal \z[19]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \z[19]_INST_0_i_1_n_1\ : STD_LOGIC;
signal \z[19]_INST_0_i_1_n_2\ : STD_LOGIC;
signal \z[19]_INST_0_i_1_n_3\ : STD_LOGIC;
signal \z[22]_INST_0_i_1_n_2\ : STD_LOGIC;
signal \z[22]_INST_0_i_1_n_3\ : STD_LOGIC;
signal \z[22]_INST_0_i_5_n_0\ : STD_LOGIC;
signal \z[22]_INST_0_i_6_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_100_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_101_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_102_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_103_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_104_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_105_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_106_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_107_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_108_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_109_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_110_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_111_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_112_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_113_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_114_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_115_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_116_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_117_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_118_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_119_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_11_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_120_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_121_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_122_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_123_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_124_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_125_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_126_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_127_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_128_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_129_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_130_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_131_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_132_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_133_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_134_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_135_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_136_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_137_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_138_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_139_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_13_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_140_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_141_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_142_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_143_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_144_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_145_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_146_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_147_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_148_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_149_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_14_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_150_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_151_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_152_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_153_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_154_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_155_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_156_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_157_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_158_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_159_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_15_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_160_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_161_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_162_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_163_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_164_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_165_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_166_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_167_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_168_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_169_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_16_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_170_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_171_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_172_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_173_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_174_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_175_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_176_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_177_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_178_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_179_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_17_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_180_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_181_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_182_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_183_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_184_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_185_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_186_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_187_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_188_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_189_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_18_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_190_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_191_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_192_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_193_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_194_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_195_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_196_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_197_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_198_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_199_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_19_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_200_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_201_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_202_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_203_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_204_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_205_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_206_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_207_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_208_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_209_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_20_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_210_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_211_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_212_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_213_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_214_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_215_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_216_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_217_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_218_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_219_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_21_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_220_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_221_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_222_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_223_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_224_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_225_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_226_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_227_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_228_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_229_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_22_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_230_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_231_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_232_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_233_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_234_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_235_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_236_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_237_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_238_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_239_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_240_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_241_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_242_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_243_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_244_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_245_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_246_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_29_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_30_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_31_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_32_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_33_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_34_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_35_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_36_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_37_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_38_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_39_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_40_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_41_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_42_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_43_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_44_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_45_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_46_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_47_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_48_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_49_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_50_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_51_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_52_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_53_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_54_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_55_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_56_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_57_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_58_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_59_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_5_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_60_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_61_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_62_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_63_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_64_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_65_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_66_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_67_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_68_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_69_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_6_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_70_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_71_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_72_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_73_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_74_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_75_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_76_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_77_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_78_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_79_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_80_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_81_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_82_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_83_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_94_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_95_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_96_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_97_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_98_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_99_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_9_n_0\ : STD_LOGIC;
signal \z[3]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \z[3]_INST_0_i_1_n_1\ : STD_LOGIC;
signal \z[3]_INST_0_i_1_n_2\ : STD_LOGIC;
signal \z[3]_INST_0_i_1_n_3\ : STD_LOGIC;
signal \z[3]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \z[3]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \z[3]_INST_0_i_5_n_0\ : STD_LOGIC;
signal \z[3]_INST_0_i_6_n_0\ : STD_LOGIC;
signal \z[3]_INST_0_i_7_n_0\ : STD_LOGIC;
signal \z[3]_INST_0_i_8_n_0\ : STD_LOGIC;
signal \z[3]_INST_0_i_9_n_0\ : STD_LOGIC;
signal \z[7]_INST_0_i_10_n_0\ : STD_LOGIC;
signal \z[7]_INST_0_i_11_n_0\ : STD_LOGIC;
signal \z[7]_INST_0_i_12_n_0\ : STD_LOGIC;
signal \z[7]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \z[7]_INST_0_i_1_n_1\ : STD_LOGIC;
signal \z[7]_INST_0_i_1_n_2\ : STD_LOGIC;
signal \z[7]_INST_0_i_1_n_3\ : STD_LOGIC;
signal \z[7]_INST_0_i_6_n_0\ : STD_LOGIC;
signal \z[7]_INST_0_i_7_n_0\ : STD_LOGIC;
signal \z[7]_INST_0_i_8_n_0\ : STD_LOGIC;
signal \z[7]_INST_0_i_9_n_0\ : STD_LOGIC;
signal \z_exponent0__0_carry__0_i_1_n_0\ : STD_LOGIC;
signal \z_exponent0__0_carry__0_i_2_n_0\ : STD_LOGIC;
signal \z_exponent0__0_carry__0_i_3_n_0\ : STD_LOGIC;
signal \z_exponent0__0_carry__0_i_4_n_0\ : STD_LOGIC;
signal \z_exponent0__0_carry__0_i_5_n_0\ : STD_LOGIC;
signal \z_exponent0__0_carry__0_i_6_n_0\ : STD_LOGIC;
signal \z_exponent0__0_carry__0_i_7_n_0\ : STD_LOGIC;
signal \z_exponent0__0_carry__0_i_8_n_0\ : STD_LOGIC;
signal \z_exponent0__0_carry__0_n_1\ : STD_LOGIC;
signal \z_exponent0__0_carry__0_n_2\ : STD_LOGIC;
signal \z_exponent0__0_carry__0_n_3\ : STD_LOGIC;
signal \z_exponent0__0_carry_i_1_n_0\ : STD_LOGIC;
signal \z_exponent0__0_carry_i_2_n_0\ : STD_LOGIC;
signal \z_exponent0__0_carry_i_3_n_0\ : STD_LOGIC;
signal \z_exponent0__0_carry_i_4_n_0\ : STD_LOGIC;
signal \z_exponent0__0_carry_i_5_n_0\ : STD_LOGIC;
signal \z_exponent0__0_carry_i_6_n_0\ : STD_LOGIC;
signal \z_exponent0__0_carry_i_7_n_0\ : STD_LOGIC;
signal \z_exponent0__0_carry_n_0\ : STD_LOGIC;
signal \z_exponent0__0_carry_n_1\ : STD_LOGIC;
signal \z_exponent0__0_carry_n_2\ : STD_LOGIC;
signal \z_exponent0__0_carry_n_3\ : STD_LOGIC;
signal \z_exponent1_carry__0_n_1\ : STD_LOGIC;
signal \z_exponent1_carry__0_n_2\ : STD_LOGIC;
signal \z_exponent1_carry__0_n_3\ : STD_LOGIC;
signal \z_exponent1_carry_i_1__0_n_0\ : STD_LOGIC;
signal z_exponent1_carry_i_1_n_0 : STD_LOGIC;
signal \z_exponent1_carry_i_2__0_n_0\ : STD_LOGIC;
signal z_exponent1_carry_i_2_n_0 : STD_LOGIC;
signal \z_exponent1_carry_i_3__0_n_0\ : STD_LOGIC;
signal z_exponent1_carry_i_3_n_0 : STD_LOGIC;
signal \z_exponent1_carry_i_4__0_n_0\ : STD_LOGIC;
signal z_exponent1_carry_i_4_n_0 : STD_LOGIC;
signal z_exponent1_carry_i_5_n_0 : STD_LOGIC;
signal z_exponent1_carry_n_0 : STD_LOGIC;
signal z_exponent1_carry_n_1 : STD_LOGIC;
signal z_exponent1_carry_n_2 : STD_LOGIC;
signal z_exponent1_carry_n_3 : STD_LOGIC;
signal NLW_L1_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_L1_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_L1_carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_L1_carry__2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW__carry__6_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW__carry__6_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal NLW_msb1_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
signal NLW_msb1_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
signal NLW_msb1_OVERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_msb1_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_msb1_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_msb1_UNDERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_msb1_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
signal NLW_msb1_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_msb1_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_msb1__0_CARRYCASCOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_msb1__0_MULTSIGNOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_msb1__0_OVERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_msb1__0_PATTERNBDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_msb1__0_PATTERNDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_msb1__0_UNDERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_msb1__0_ACOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 29 downto 0 );
signal \NLW_msb1__0_BCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
signal \NLW_msb1__0_CARRYOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_msb1__0_P_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 31 );
signal \NLW_msb1__0_PCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 0 );
signal \NLW_z[22]_INST_0_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_z[22]_INST_0_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_z_exponent0__0_carry__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_z_exponent1_carry__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of L1_carry_i_18 : label is "soft_lutpair9";
attribute SOFT_HLUTNM of L1_carry_i_19 : label is "soft_lutpair13";
attribute SOFT_HLUTNM of L1_carry_i_22 : label is "soft_lutpair3";
attribute SOFT_HLUTNM of L1_carry_i_23 : label is "soft_lutpair5";
attribute SOFT_HLUTNM of L1_carry_i_27 : label is "soft_lutpair44";
attribute SOFT_HLUTNM of L1_carry_i_30 : label is "soft_lutpair9";
attribute SOFT_HLUTNM of L1_carry_i_31 : label is "soft_lutpair5";
attribute SOFT_HLUTNM of L1_carry_i_33 : label is "soft_lutpair30";
attribute SOFT_HLUTNM of L1_carry_i_34 : label is "soft_lutpair27";
attribute SOFT_HLUTNM of L1_carry_i_36 : label is "soft_lutpair31";
attribute SOFT_HLUTNM of L1_carry_i_39 : label is "soft_lutpair29";
attribute SOFT_HLUTNM of L1_carry_i_46 : label is "soft_lutpair13";
attribute SOFT_HLUTNM of L1_carry_i_47 : label is "soft_lutpair3";
attribute SOFT_HLUTNM of L1_carry_i_49 : label is "soft_lutpair24";
attribute SOFT_HLUTNM of L1_carry_i_52 : label is "soft_lutpair29";
attribute SOFT_HLUTNM of L1_carry_i_53 : label is "soft_lutpair31";
attribute SOFT_HLUTNM of L1_carry_i_54 : label is "soft_lutpair30";
attribute SOFT_HLUTNM of \_carry_i_11\ : label is "soft_lutpair44";
attribute SOFT_HLUTNM of \_carry_i_18\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \_carry_i_19\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \_carry_i_20\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \_carry_i_22\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \_carry_i_24\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \_carry_i_6\ : label is "soft_lutpair27";
attribute METHODOLOGY_DRC_VIOS : string;
attribute METHODOLOGY_DRC_VIOS of msb1 : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \msb1__0\ : label is "{SYNTH-13 {cell *THIS*}}";
attribute SOFT_HLUTNM of \z[11]_INST_0_i_8\ : label is "soft_lutpair34";
attribute SOFT_HLUTNM of \z[11]_INST_0_i_9\ : label is "soft_lutpair37";
attribute SOFT_HLUTNM of \z[15]_INST_0_i_8\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_102\ : label is "soft_lutpair35";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_111\ : label is "soft_lutpair39";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_112\ : label is "soft_lutpair40";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_113\ : label is "soft_lutpair39";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_114\ : label is "soft_lutpair40";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_173\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_174\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_175\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_176\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_177\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_178\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_179\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_180\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_181\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_182\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_183\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_184\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_185\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_186\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_187\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_188\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_191\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_192\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_197\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_198\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_202\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_203\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_204\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_205\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_212\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_213\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_214\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_215\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_216\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_217\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_220\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_231\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_246\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_31\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_37\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_38\ : label is "soft_lutpair36";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_39\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_43\ : label is "soft_lutpair43";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_44\ : label is "soft_lutpair36";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_47\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_48\ : label is "soft_lutpair38";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_49\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_50\ : label is "soft_lutpair37";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_51\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_52\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_57\ : label is "soft_lutpair43";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_59\ : label is "soft_lutpair41";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_62\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_63\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_65\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_68\ : label is "soft_lutpair42";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_70\ : label is "soft_lutpair41";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_72\ : label is "soft_lutpair42";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_77\ : label is "soft_lutpair45";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_79\ : label is "soft_lutpair45";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_95\ : label is "soft_lutpair38";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_97\ : label is "soft_lutpair35";
attribute SOFT_HLUTNM of \z[7]_INST_0_i_10\ : label is "soft_lutpair34";
attribute SOFT_HLUTNM of \z[7]_INST_0_i_12\ : label is "soft_lutpair32";
attribute HLUTNM : string;
attribute HLUTNM of \z_exponent0__0_carry__0_i_2\ : label is "lutpair3";
attribute SOFT_HLUTNM of \z_exponent0__0_carry__0_i_8\ : label is "soft_lutpair2";
attribute HLUTNM of \z_exponent0__0_carry_i_1\ : label is "lutpair2";
attribute HLUTNM of \z_exponent0__0_carry_i_2\ : label is "lutpair1";
attribute HLUTNM of \z_exponent0__0_carry_i_3\ : label is "lutpair0";
attribute HLUTNM of \z_exponent0__0_carry_i_7\ : label is "lutpair0";
attribute HLUTNM of \z_exponent1_carry_i_1__0\ : label is "lutpair4";
attribute HLUTNM of \z_exponent1_carry_i_3__0\ : label is "lutpair2";
attribute HLUTNM of z_exponent1_carry_i_4 : label is "lutpair1";
attribute HLUTNM of \z_exponent1_carry_i_4__0\ : label is "lutpair3";
attribute HLUTNM of z_exponent1_carry_i_5 : label is "lutpair4";
begin
\y_11__s_net_1\ <= \y_11__s_port_\;
L1_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => L1_carry_n_0,
CO(2) => L1_carry_n_1,
CO(1) => L1_carry_n_2,
CO(0) => L1_carry_n_3,
CYINIT => '1',
DI(3) => L1_carry_i_1_n_0,
DI(2) => L1_carry_i_2_n_0,
DI(1) => L1_carry_i_3_n_0,
DI(0) => L1_carry_i_4_n_0,
O(3 downto 0) => NLW_L1_carry_O_UNCONNECTED(3 downto 0),
S(3) => L1_carry_i_5_n_0,
S(2) => L1_carry_i_6_n_0,
S(1) => L1_carry_i_7_n_0,
S(0) => L1_carry_i_8_n_0
);
\L1_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => L1_carry_n_0,
CO(3) => \L1_carry__0_n_0\,
CO(2) => \L1_carry__0_n_1\,
CO(1) => \L1_carry__0_n_2\,
CO(0) => \L1_carry__0_n_3\,
CYINIT => '0',
DI(3) => \L1_carry__0_i_1_n_0\,
DI(2) => \L1_carry__0_i_2_n_0\,
DI(1) => \L1_carry__0_i_3_n_0\,
DI(0) => \L1_carry__0_i_4_n_0\,
O(3 downto 0) => \NLW_L1_carry__0_O_UNCONNECTED\(3 downto 0),
S(3) => \L1_carry__0_i_5_n_0\,
S(2) => \L1_carry__0_i_6_n_0\,
S(1) => \L1_carry__0_i_7_n_0\,
S(0) => \L1_carry__0_i_8_n_0\
);
\L1_carry__0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAA2FFFF00000000"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \L1_carry__0_i_1_n_0\
);
\L1_carry__0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAA2FFFF00000000"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \L1_carry__0_i_2_n_0\
);
\L1_carry__0_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAA2FFFF00000000"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \L1_carry__0_i_3_n_0\
);
\L1_carry__0_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAA2FFFF00000000"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \L1_carry__0_i_4_n_0\
);
\L1_carry__0_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \L1_carry__0_i_5_n_0\
);
\L1_carry__0_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \L1_carry__0_i_6_n_0\
);
\L1_carry__0_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \L1_carry__0_i_7_n_0\
);
\L1_carry__0_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \L1_carry__0_i_8_n_0\
);
\L1_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \L1_carry__0_n_0\,
CO(3) => \L1_carry__1_n_0\,
CO(2) => \L1_carry__1_n_1\,
CO(1) => \L1_carry__1_n_2\,
CO(0) => \L1_carry__1_n_3\,
CYINIT => '0',
DI(3) => \L1_carry__1_i_1_n_0\,
DI(2) => \L1_carry__1_i_2_n_0\,
DI(1) => \L1_carry__1_i_3_n_0\,
DI(0) => \L1_carry__1_i_4_n_0\,
O(3 downto 0) => \NLW_L1_carry__1_O_UNCONNECTED\(3 downto 0),
S(3) => \L1_carry__1_i_5_n_0\,
S(2) => \L1_carry__1_i_6_n_0\,
S(1) => \L1_carry__1_i_7_n_0\,
S(0) => \L1_carry__1_i_8_n_0\
);
\L1_carry__1_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAA2FFFF00000000"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \L1_carry__1_i_1_n_0\
);
\L1_carry__1_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAA2FFFF00000000"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \L1_carry__1_i_2_n_0\
);
\L1_carry__1_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAA2FFFF00000000"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \L1_carry__1_i_3_n_0\
);
\L1_carry__1_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAA2FFFF00000000"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \L1_carry__1_i_4_n_0\
);
\L1_carry__1_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \L1_carry__1_i_5_n_0\
);
\L1_carry__1_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \L1_carry__1_i_6_n_0\
);
\L1_carry__1_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \L1_carry__1_i_7_n_0\
);
\L1_carry__1_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \L1_carry__1_i_8_n_0\
);
\L1_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \L1_carry__1_n_0\,
CO(3) => L1,
CO(2) => \L1_carry__2_n_1\,
CO(1) => \L1_carry__2_n_2\,
CO(0) => \L1_carry__2_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \L1_carry__2_i_1_n_0\,
DI(1) => \L1_carry__2_i_2_n_0\,
DI(0) => \L1_carry__2_i_3_n_0\,
O(3 downto 0) => \NLW_L1_carry__2_O_UNCONNECTED\(3 downto 0),
S(3) => \L1_carry__2_i_4_n_0\,
S(2) => \L1_carry__2_i_5_n_0\,
S(1) => \L1_carry__2_i_6_n_0\,
S(0) => \L1_carry__2_i_7_n_0\
);
\L1_carry__2_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAA2FFFF00000000"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \L1_carry__2_i_1_n_0\
);
\L1_carry__2_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAA2FFFF00000000"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \L1_carry__2_i_2_n_0\
);
\L1_carry__2_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAA2FFFF00000000"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \L1_carry__2_i_3_n_0\
);
\L1_carry__2_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \L1_carry__2_i_4_n_0\
);
\L1_carry__2_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \L1_carry__2_i_5_n_0\
);
\L1_carry__2_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \L1_carry__2_i_6_n_0\
);
\L1_carry__2_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \L1_carry__2_i_7_n_0\
);
L1_carry_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"AAA2FFFF00000000"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => L1_carry_i_1_n_0
);
L1_carry_i_10: unisim.vcomponents.LUT6
generic map(
INIT => X"4555FFFF45554555"
)
port map (
I0 => L1_carry_i_24_n_0,
I1 => L1_carry_i_25_n_0,
I2 => L1_carry_i_26_n_0,
I3 => L1_carry_i_27_n_0,
I4 => L1_carry_i_28_n_0,
I5 => L1_carry_i_29_n_0,
O => L1_carry_i_10_n_0
);
L1_carry_i_11: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFF7550000"
)
port map (
I0 => L1_carry_i_30_n_0,
I1 => L1_carry_i_31_n_0,
I2 => L1_carry_i_32_n_0,
I3 => L1_carry_i_33_n_0,
I4 => L1_carry_i_34_n_0,
I5 => L1_carry_i_35_n_0,
O => L1_carry_i_11_n_0
);
L1_carry_i_12: unisim.vcomponents.LUT3
generic map(
INIT => X"2A"
)
port map (
I0 => L1_carry_i_13_n_0,
I1 => L1_carry_i_22_n_0,
I2 => L1_carry_i_19_n_0,
O => L1_carry_i_12_n_0
);
L1_carry_i_13: unisim.vcomponents.LUT6
generic map(
INIT => X"0001000000000000"
)
port map (
I0 => \msb1__1\(40),
I1 => \msb1__1\(41),
I2 => \msb1__1\(43),
I3 => \msb1__1\(42),
I4 => L1_carry_i_34_n_0,
I5 => L1_carry_i_23_n_0,
O => L1_carry_i_13_n_0
);
L1_carry_i_14: unisim.vcomponents.LUT5
generic map(
INIT => X"A9AA5555"
)
port map (
I0 => L1_carry_i_12_n_0,
I1 => L1_carry_i_11_n_0,
I2 => L1_carry_i_10_n_0,
I3 => \_carry_i_1_n_0\,
I4 => L1_carry_i_9_n_0,
O => L1_carry_i_14_n_0
);
L1_carry_i_15: unisim.vcomponents.LUT6
generic map(
INIT => X"0200AAAAFDFF5555"
)
port map (
I0 => L1_carry_i_12_n_0,
I1 => L1_carry_i_11_n_0,
I2 => L1_carry_i_10_n_0,
I3 => \_carry_i_1_n_0\,
I4 => L1_carry_i_9_n_0,
I5 => L1_carry_i_13_n_0,
O => L1_carry_i_15_n_0
);
L1_carry_i_16: unisim.vcomponents.LUT3
generic map(
INIT => X"65"
)
port map (
I0 => L1_carry_i_11_n_0,
I1 => L1_carry_i_10_n_0,
I2 => \_carry_i_1_n_0\,
O => L1_carry_i_16_n_0
);
L1_carry_i_17: unisim.vcomponents.LUT4
generic map(
INIT => X"10EF"
)
port map (
I0 => L1_carry_i_11_n_0,
I1 => L1_carry_i_10_n_0,
I2 => \_carry_i_1_n_0\,
I3 => L1_carry_i_9_n_0,
O => L1_carry_i_17_n_0
);
L1_carry_i_18: unisim.vcomponents.LUT5
generic map(
INIT => X"00000002"
)
port map (
I0 => L1_carry_i_34_n_0,
I1 => \msb1__1\(42),
I2 => \msb1__1\(43),
I3 => \msb1__1\(41),
I4 => \msb1__1\(40),
O => L1_carry_i_18_n_0
);
L1_carry_i_19: unisim.vcomponents.LUT5
generic map(
INIT => X"00000002"
)
port map (
I0 => L1_carry_i_36_n_0,
I1 => \msb1__1\(26),
I2 => \msb1__1\(27),
I3 => \msb1__1\(25),
I4 => \msb1__1\(24),
O => L1_carry_i_19_n_0
);
L1_carry_i_2: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => L1_carry_i_14_n_0,
I1 => L1_carry_i_15_n_0,
O => L1_carry_i_2_n_0
);
L1_carry_i_20: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => \msb1__1\(10),
I1 => \msb1__1\(11),
I2 => \msb1__1\(9),
I3 => \msb1__1\(8),
O => L1_carry_i_20_n_0
);
L1_carry_i_21: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \msb1__1\(14),
I1 => \msb1__1\(15),
I2 => \msb1__1\(13),
I3 => \msb1__1\(12),
O => L1_carry_i_21_n_0
);
L1_carry_i_22: unisim.vcomponents.LUT5
generic map(
INIT => X"00000002"
)
port map (
I0 => L1_carry_i_37_n_0,
I1 => \msb1__1\(16),
I2 => \msb1__1\(17),
I3 => \msb1__1\(19),
I4 => \msb1__1\(18),
O => L1_carry_i_22_n_0
);
L1_carry_i_23: unisim.vcomponents.LUT5
generic map(
INIT => X"00000002"
)
port map (
I0 => L1_carry_i_33_n_0,
I1 => \msb1__1\(32),
I2 => \msb1__1\(33),
I3 => \msb1__1\(35),
I4 => \msb1__1\(34),
O => L1_carry_i_23_n_0
);
L1_carry_i_24: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF000EFFFF"
)
port map (
I0 => \msb1__1\(39),
I1 => \msb1__1\(38),
I2 => \msb1__1\(41),
I3 => \msb1__1\(40),
I4 => L1_carry_i_29_n_0,
I5 => L1_carry_i_38_n_0,
O => L1_carry_i_24_n_0
);
L1_carry_i_25: unisim.vcomponents.LUT6
generic map(
INIT => X"000000000000F100"
)
port map (
I0 => L1_carry_i_39_n_0,
I1 => L1_carry_i_40_n_0,
I2 => L1_carry_i_41_n_0,
I3 => L1_carry_i_42_n_0,
I4 => \msb1__1\(35),
I5 => \msb1__1\(34),
O => L1_carry_i_25_n_0
);
L1_carry_i_26: unisim.vcomponents.LUT6
generic map(
INIT => X"1111110011111101"
)
port map (
I0 => \msb1__1\(37),
I1 => \msb1__1\(36),
I2 => \msb1__1\(33),
I3 => \msb1__1\(34),
I4 => \msb1__1\(35),
I5 => \msb1__1\(32),
O => L1_carry_i_26_n_0
);
L1_carry_i_27: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \msb1__1\(41),
I1 => \msb1__1\(40),
O => L1_carry_i_27_n_0
);
L1_carry_i_28: unisim.vcomponents.LUT6
generic map(
INIT => X"1111111011111111"
)
port map (
I0 => \msb1__1\(45),
I1 => \msb1__1\(44),
I2 => L1_carry_i_43_n_0,
I3 => L1_carry_i_44_n_0,
I4 => L1_carry_i_39_n_0,
I5 => L1_carry_i_45_n_0,
O => L1_carry_i_28_n_0
);
L1_carry_i_29: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \msb1__1\(46),
I1 => \msb1__1\(47),
O => L1_carry_i_29_n_0
);
L1_carry_i_3: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => L1_carry_i_16_n_0,
I1 => L1_carry_i_17_n_0,
O => L1_carry_i_3_n_0
);
L1_carry_i_30: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => \msb1__1\(40),
I1 => \msb1__1\(41),
I2 => \msb1__1\(43),
I3 => \msb1__1\(42),
O => L1_carry_i_30_n_0
);
L1_carry_i_31: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => \msb1__1\(34),
I1 => \msb1__1\(35),
I2 => \msb1__1\(33),
I3 => \msb1__1\(32),
O => L1_carry_i_31_n_0
);
L1_carry_i_32: unisim.vcomponents.LUT6
generic map(
INIT => X"8A888A888A88AA88"
)
port map (
I0 => L1_carry_i_36_n_0,
I1 => L1_carry_i_46_n_0,
I2 => L1_carry_i_47_n_0,
I3 => L1_carry_i_37_n_0,
I4 => L1_carry_i_20_n_0,
I5 => L1_carry_i_21_n_0,
O => L1_carry_i_32_n_0
);
L1_carry_i_33: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => \msb1__1\(37),
I1 => \msb1__1\(36),
I2 => \msb1__1\(38),
I3 => \msb1__1\(39),
O => L1_carry_i_33_n_0
);
L1_carry_i_34: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => \msb1__1\(47),
I1 => \msb1__1\(46),
I2 => \msb1__1\(45),
I3 => \msb1__1\(44),
O => L1_carry_i_34_n_0
);
L1_carry_i_35: unisim.vcomponents.LUT6
generic map(
INIT => X"0000400000000000"
)
port map (
I0 => L1_carry_i_48_n_0,
I1 => L1_carry_i_49_n_0,
I2 => L1_carry_i_34_n_0,
I3 => L1_carry_i_36_n_0,
I4 => L1_carry_i_21_n_0,
I5 => L1_carry_i_37_n_0,
O => L1_carry_i_35_n_0
);
L1_carry_i_36: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => \msb1__1\(28),
I1 => \msb1__1\(29),
I2 => \msb1__1\(30),
I3 => \msb1__1\(31),
O => L1_carry_i_36_n_0
);
L1_carry_i_37: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => \msb1__1\(23),
I1 => \msb1__1\(22),
I2 => \msb1__1\(20),
I3 => \msb1__1\(21),
O => L1_carry_i_37_n_0
);
L1_carry_i_38: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \msb1__1\(42),
I1 => \msb1__1\(43),
O => L1_carry_i_38_n_0
);
L1_carry_i_39: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \msb1__1\(23),
I1 => \msb1__1\(22),
I2 => \msb1__1\(18),
I3 => \msb1__1\(19),
O => L1_carry_i_39_n_0
);
L1_carry_i_4: unisim.vcomponents.LUT2
generic map(
INIT => X"D"
)
port map (
I0 => \_carry_i_1_n_0\,
I1 => L1_carry_i_10_n_0,
O => L1_carry_i_4_n_0
);
L1_carry_i_40: unisim.vcomponents.LUT6
generic map(
INIT => X"000000000000FFF2"
)
port map (
I0 => L1_carry_i_50_n_0,
I1 => L1_carry_i_51_n_0,
I2 => \msb1__1\(15),
I3 => \msb1__1\(14),
I4 => \msb1__1\(17),
I5 => \msb1__1\(16),
O => L1_carry_i_40_n_0
);
L1_carry_i_41: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFE0FF"
)
port map (
I0 => \msb1__1\(21),
I1 => \msb1__1\(20),
I2 => L1_carry_i_52_n_0,
I3 => L1_carry_i_53_n_0,
I4 => \msb1__1\(25),
I5 => \msb1__1\(24),
O => L1_carry_i_41_n_0
);
L1_carry_i_42: unisim.vcomponents.LUT6
generic map(
INIT => X"1111111111110001"
)
port map (
I0 => \msb1__1\(30),
I1 => \msb1__1\(31),
I2 => \msb1__1\(26),
I3 => \msb1__1\(27),
I4 => \msb1__1\(29),
I5 => \msb1__1\(28),
O => L1_carry_i_42_n_0
);
L1_carry_i_43: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFEFFFF"
)
port map (
I0 => \msb1__1\(2),
I1 => \msb1__1\(3),
I2 => \msb1__1\(26),
I3 => \msb1__1\(27),
I4 => L1_carry_i_54_n_0,
I5 => L1_carry_i_38_n_0,
O => L1_carry_i_43_n_0
);
L1_carry_i_44: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \msb1__1\(7),
I1 => \msb1__1\(6),
I2 => \msb1__1\(10),
I3 => \msb1__1\(11),
O => L1_carry_i_44_n_0
);
L1_carry_i_45: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => \msb1__1\(34),
I1 => \msb1__1\(35),
I2 => \msb1__1\(15),
I3 => \msb1__1\(14),
I4 => \msb1__1\(31),
I5 => \msb1__1\(30),
O => L1_carry_i_45_n_0
);
L1_carry_i_46: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \msb1__1\(24),
I1 => \msb1__1\(25),
I2 => \msb1__1\(27),
I3 => \msb1__1\(26),
O => L1_carry_i_46_n_0
);
L1_carry_i_47: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => \msb1__1\(18),
I1 => \msb1__1\(19),
I2 => \msb1__1\(17),
I3 => \msb1__1\(16),
O => L1_carry_i_47_n_0
);
L1_carry_i_48: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => \msb1__1\(7),
I1 => \msb1__1\(6),
I2 => \msb1__1\(39),
I3 => \msb1__1\(38),
I4 => \msb1__1\(36),
I5 => \msb1__1\(37),
O => L1_carry_i_48_n_0
);
L1_carry_i_49: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \msb1__1\(5),
I1 => \msb1__1\(4),
O => L1_carry_i_49_n_0
);
L1_carry_i_5: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => L1_carry_i_5_n_0
);
L1_carry_i_50: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFF1"
)
port map (
I0 => \msb1__1\(4),
I1 => \msb1__1\(5),
I2 => \msb1__1\(11),
I3 => \msb1__1\(10),
I4 => \msb1__1\(6),
I5 => \msb1__1\(7),
O => L1_carry_i_50_n_0
);
L1_carry_i_51: unisim.vcomponents.LUT6
generic map(
INIT => X"EEEEEEEEEEEEFFFE"
)
port map (
I0 => \msb1__1\(13),
I1 => \msb1__1\(12),
I2 => \msb1__1\(8),
I3 => \msb1__1\(9),
I4 => \msb1__1\(11),
I5 => \msb1__1\(10),
O => L1_carry_i_51_n_0
);
L1_carry_i_52: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \msb1__1\(22),
I1 => \msb1__1\(23),
O => L1_carry_i_52_n_0
);
L1_carry_i_53: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \msb1__1\(29),
I1 => \msb1__1\(28),
O => L1_carry_i_53_n_0
);
L1_carry_i_54: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \msb1__1\(39),
I1 => \msb1__1\(38),
O => L1_carry_i_54_n_0
);
L1_carry_i_6: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => L1_carry_i_15_n_0,
I1 => L1_carry_i_14_n_0,
O => L1_carry_i_6_n_0
);
L1_carry_i_7: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => L1_carry_i_17_n_0,
I1 => L1_carry_i_16_n_0,
O => L1_carry_i_7_n_0
);
L1_carry_i_8: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \_carry_i_1_n_0\,
I1 => L1_carry_i_10_n_0,
O => L1_carry_i_8_n_0
);
L1_carry_i_9: unisim.vcomponents.LUT6
generic map(
INIT => X"00808888AAAAAAAA"
)
port map (
I0 => L1_carry_i_18_n_0,
I1 => L1_carry_i_19_n_0,
I2 => L1_carry_i_20_n_0,
I3 => L1_carry_i_21_n_0,
I4 => L1_carry_i_22_n_0,
I5 => L1_carry_i_23_n_0,
O => L1_carry_i_9_n_0
);
\_carry\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \_carry_n_0\,
CO(2) => \_carry_n_1\,
CO(1) => \_carry_n_2\,
CO(0) => \_carry_n_3\,
CYINIT => \_carry_i_1_n_0\,
DI(3 downto 0) => B"0000",
O(3) => \_carry_n_4\,
O(2) => \_carry_n_5\,
O(1) => \_carry_n_6\,
O(0) => \_carry_n_7\,
S(3) => \_carry_i_2_n_0\,
S(2) => \_carry_i_3_n_0\,
S(1) => \_carry_i_4_n_0\,
S(0) => p_0_in(1)
);
\_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => \_carry_n_0\,
CO(3) => \_carry__0_n_0\,
CO(2) => \_carry__0_n_1\,
CO(1) => \_carry__0_n_2\,
CO(0) => \_carry__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \_carry__0_n_4\,
O(2) => \_carry__0_n_5\,
O(1) => \_carry__0_n_6\,
O(0) => \_carry__0_n_7\,
S(3) => \_carry__0_i_1_n_0\,
S(2) => \_carry__0_i_2_n_0\,
S(1) => \_carry__0_i_3_n_0\,
S(0) => \_carry__0_i_4_n_0\
);
\_carry__0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \_carry__0_i_1_n_0\
);
\_carry__0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \_carry__0_i_2_n_0\
);
\_carry__0_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \_carry__0_i_3_n_0\
);
\_carry__0_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"0200AAAAFDFF5555"
)
port map (
I0 => L1_carry_i_12_n_0,
I1 => L1_carry_i_11_n_0,
I2 => L1_carry_i_10_n_0,
I3 => \_carry_i_1_n_0\,
I4 => L1_carry_i_9_n_0,
I5 => L1_carry_i_13_n_0,
O => \_carry__0_i_4_n_0\
);
\_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \_carry__0_n_0\,
CO(3) => \_carry__1_n_0\,
CO(2) => \_carry__1_n_1\,
CO(1) => \_carry__1_n_2\,
CO(0) => \_carry__1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \_carry__1_n_4\,
O(2) => \_carry__1_n_5\,
O(1) => \_carry__1_n_6\,
O(0) => \_carry__1_n_7\,
S(3) => \_carry__1_i_1_n_0\,
S(2) => \_carry__1_i_2_n_0\,
S(1) => \_carry__1_i_3_n_0\,
S(0) => \_carry__1_i_4_n_0\
);
\_carry__1_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \_carry__1_i_1_n_0\
);
\_carry__1_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \_carry__1_i_2_n_0\
);
\_carry__1_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \_carry__1_i_3_n_0\
);
\_carry__1_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \_carry__1_i_4_n_0\
);
\_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \_carry__1_n_0\,
CO(3) => \_carry__2_n_0\,
CO(2) => \_carry__2_n_1\,
CO(1) => \_carry__2_n_2\,
CO(0) => \_carry__2_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \_carry__2_n_4\,
O(2) => \_carry__2_n_5\,
O(1) => \_carry__2_n_6\,
O(0) => \_carry__2_n_7\,
S(3) => \_carry__2_i_1_n_0\,
S(2) => \_carry__2_i_2_n_0\,
S(1) => \_carry__2_i_3_n_0\,
S(0) => \_carry__2_i_4_n_0\
);
\_carry__2_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \_carry__2_i_1_n_0\
);
\_carry__2_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \_carry__2_i_2_n_0\
);
\_carry__2_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \_carry__2_i_3_n_0\
);
\_carry__2_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \_carry__2_i_4_n_0\
);
\_carry__3\: unisim.vcomponents.CARRY4
port map (
CI => \_carry__2_n_0\,
CO(3) => \_carry__3_n_0\,
CO(2) => \_carry__3_n_1\,
CO(1) => \_carry__3_n_2\,
CO(0) => \_carry__3_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \_carry__3_n_4\,
O(2) => \_carry__3_n_5\,
O(1) => \_carry__3_n_6\,
O(0) => \_carry__3_n_7\,
S(3) => \_carry__3_i_1_n_0\,
S(2) => \_carry__3_i_2_n_0\,
S(1) => \_carry__3_i_3_n_0\,
S(0) => \_carry__3_i_4_n_0\
);
\_carry__3_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \_carry__3_i_1_n_0\
);
\_carry__3_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \_carry__3_i_2_n_0\
);
\_carry__3_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \_carry__3_i_3_n_0\
);
\_carry__3_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \_carry__3_i_4_n_0\
);
\_carry__4\: unisim.vcomponents.CARRY4
port map (
CI => \_carry__3_n_0\,
CO(3) => \_carry__4_n_0\,
CO(2) => \_carry__4_n_1\,
CO(1) => \_carry__4_n_2\,
CO(0) => \_carry__4_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \_carry__4_n_4\,
O(2) => \_carry__4_n_5\,
O(1) => \_carry__4_n_6\,
O(0) => \_carry__4_n_7\,
S(3) => \_carry__4_i_1_n_0\,
S(2) => \_carry__4_i_2_n_0\,
S(1) => \_carry__4_i_3_n_0\,
S(0) => \_carry__4_i_4_n_0\
);
\_carry__4_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \_carry__4_i_1_n_0\
);
\_carry__4_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \_carry__4_i_2_n_0\
);
\_carry__4_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \_carry__4_i_3_n_0\
);
\_carry__4_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \_carry__4_i_4_n_0\
);
\_carry__5\: unisim.vcomponents.CARRY4
port map (
CI => \_carry__4_n_0\,
CO(3) => \_carry__5_n_0\,
CO(2) => \_carry__5_n_1\,
CO(1) => \_carry__5_n_2\,
CO(0) => \_carry__5_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \_carry__5_n_4\,
O(2) => \_carry__5_n_5\,
O(1) => \_carry__5_n_6\,
O(0) => \_carry__5_n_7\,
S(3) => \_carry__5_i_1_n_0\,
S(2) => \_carry__5_i_2_n_0\,
S(1) => \_carry__5_i_3_n_0\,
S(0) => \_carry__5_i_4_n_0\
);
\_carry__5_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \_carry__5_i_1_n_0\
);
\_carry__5_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \_carry__5_i_2_n_0\
);
\_carry__5_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \_carry__5_i_3_n_0\
);
\_carry__5_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \_carry__5_i_4_n_0\
);
\_carry__6\: unisim.vcomponents.CARRY4
port map (
CI => \_carry__5_n_0\,
CO(3 downto 1) => \NLW__carry__6_CO_UNCONNECTED\(3 downto 1),
CO(0) => \_carry__6_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 2) => \NLW__carry__6_O_UNCONNECTED\(3 downto 2),
O(1) => \_carry__6_n_6\,
O(0) => \_carry__6_n_7\,
S(3 downto 2) => B"00",
S(1) => \_carry__6_i_1_n_0\,
S(0) => \_carry__6_i_2_n_0\
);
\_carry__6_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \_carry__6_i_1_n_0\
);
\_carry__6_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \_carry__6_i_2_n_0\
);
\_carry_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"BBBBABAA"
)
port map (
I0 => \msb1__1\(47),
I1 => \_carry_i_6_n_0\,
I2 => \_carry_i_7_n_0\,
I3 => \_carry_i_8_n_0\,
I4 => \_carry_i_9_n_0\,
O => \_carry_i_1_n_0\
);
\_carry_i_10\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \_carry_i_1_n_0\,
I1 => L1_carry_i_10_n_0,
O => \_carry_i_10_n_0\
);
\_carry_i_11\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \msb1__1\(42),
I1 => \msb1__1\(40),
O => \_carry_i_11_n_0\
);
\_carry_i_12\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFF0FFF0FFFFFFF4"
)
port map (
I0 => \msb1__1\(25),
I1 => \msb1__1\(24),
I2 => \msb1__1\(28),
I3 => \_carry_i_18_n_0\,
I4 => \msb1__1\(26),
I5 => \msb1__1\(27),
O => \_carry_i_12_n_0\
);
\_carry_i_13\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFF0FFF0FFFFFFF4"
)
port map (
I0 => \msb1__1\(15),
I1 => \msb1__1\(14),
I2 => \msb1__1\(18),
I3 => \_carry_i_19_n_0\,
I4 => \msb1__1\(16),
I5 => \msb1__1\(17),
O => \_carry_i_13_n_0\
);
\_carry_i_14\: unisim.vcomponents.LUT5
generic map(
INIT => X"0000EFEE"
)
port map (
I0 => \_carry_i_20_n_0\,
I1 => \msb1__1\(7),
I2 => \msb1__1\(6),
I3 => \msb1__1\(5),
I4 => \_carry_i_21_n_0\,
O => \_carry_i_14_n_0\
);
\_carry_i_15\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFF00BA"
)
port map (
I0 => \msb1__1\(11),
I1 => \msb1__1\(10),
I2 => \msb1__1\(9),
I3 => \msb1__1\(12),
I4 => \_carry_i_22_n_0\,
I5 => \msb1__1\(13),
O => \_carry_i_15_n_0\
);
\_carry_i_16\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFF0FFF0FFFFFFF4"
)
port map (
I0 => \msb1__1\(20),
I1 => \msb1__1\(19),
I2 => \msb1__1\(23),
I3 => \_carry_i_23_n_0\,
I4 => \msb1__1\(21),
I5 => \msb1__1\(22),
O => \_carry_i_16_n_0\
);
\_carry_i_17\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFF0FFF0FFFFFFF4"
)
port map (
I0 => \msb1__1\(30),
I1 => \msb1__1\(29),
I2 => \msb1__1\(33),
I3 => \_carry_i_24_n_0\,
I4 => \msb1__1\(31),
I5 => \msb1__1\(32),
O => \_carry_i_17_n_0\
);
\_carry_i_18\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \msb1__1\(32),
I1 => \msb1__1\(30),
O => \_carry_i_18_n_0\
);
\_carry_i_19\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \msb1__1\(22),
I1 => \msb1__1\(20),
O => \_carry_i_19_n_0\
);
\_carry_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"555DAAA2"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
O => \_carry_i_2_n_0\
);
\_carry_i_20\: unisim.vcomponents.LUT4
generic map(
INIT => X"5504"
)
port map (
I0 => \msb1__1\(4),
I1 => \msb1__1\(1),
I2 => \msb1__1\(2),
I3 => \msb1__1\(3),
O => \_carry_i_20_n_0\
);
\_carry_i_21\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFF4"
)
port map (
I0 => \msb1__1\(7),
I1 => \msb1__1\(6),
I2 => \msb1__1\(12),
I3 => \msb1__1\(10),
I4 => \msb1__1\(8),
O => \_carry_i_21_n_0\
);
\_carry_i_22\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \msb1__1\(17),
I1 => \msb1__1\(15),
O => \_carry_i_22_n_0\
);
\_carry_i_23\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \msb1__1\(27),
I1 => \msb1__1\(25),
O => \_carry_i_23_n_0\
);
\_carry_i_24\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \msb1__1\(37),
I1 => \msb1__1\(35),
O => \_carry_i_24_n_0\
);
\_carry_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"10EF"
)
port map (
I0 => L1_carry_i_11_n_0,
I1 => L1_carry_i_10_n_0,
I2 => \_carry_i_1_n_0\,
I3 => L1_carry_i_9_n_0,
O => \_carry_i_3_n_0\
);
\_carry_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => L1_carry_i_16_n_0,
O => \_carry_i_4_n_0\
);
\_carry_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \_carry_i_10_n_0\,
O => p_0_in(1)
);
\_carry_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"BA"
)
port map (
I0 => \msb1__1\(46),
I1 => \msb1__1\(45),
I2 => \msb1__1\(44),
O => \_carry_i_6_n_0\
);
\_carry_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFF0FFF0FFFFFFF4"
)
port map (
I0 => \msb1__1\(35),
I1 => \msb1__1\(34),
I2 => \msb1__1\(38),
I3 => \_carry_i_11_n_0\,
I4 => \msb1__1\(36),
I5 => \msb1__1\(37),
O => \_carry_i_7_n_0\
);
\_carry_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF55551110"
)
port map (
I0 => \_carry_i_12_n_0\,
I1 => \_carry_i_13_n_0\,
I2 => \_carry_i_14_n_0\,
I3 => \_carry_i_15_n_0\,
I4 => \_carry_i_16_n_0\,
I5 => \_carry_i_17_n_0\,
O => \_carry_i_8_n_0\
);
\_carry_i_9\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFF00F4"
)
port map (
I0 => \msb1__1\(40),
I1 => \msb1__1\(39),
I2 => \msb1__1\(41),
I3 => \msb1__1\(42),
I4 => \msb1__1\(45),
I5 => \msb1__1\(43),
O => \_carry_i_9_n_0\
);
msb1: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29 downto 23) => B"0000001",
A(22 downto 0) => y(22 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => NLW_msb1_ACOUT_UNCONNECTED(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => '0',
B(16 downto 0) => x(16 downto 0),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => NLW_msb1_BCOUT_UNCONNECTED(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => NLW_msb1_CARRYCASCOUT_UNCONNECTED,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => NLW_msb1_CARRYOUT_UNCONNECTED(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => NLW_msb1_MULTSIGNOUT_UNCONNECTED,
OPMODE(6 downto 0) => B"0000101",
OVERFLOW => NLW_msb1_OVERFLOW_UNCONNECTED,
P(47) => msb1_n_58,
P(46) => msb1_n_59,
P(45) => msb1_n_60,
P(44) => msb1_n_61,
P(43) => msb1_n_62,
P(42) => msb1_n_63,
P(41) => msb1_n_64,
P(40) => msb1_n_65,
P(39) => msb1_n_66,
P(38) => msb1_n_67,
P(37) => msb1_n_68,
P(36) => msb1_n_69,
P(35) => msb1_n_70,
P(34) => msb1_n_71,
P(33) => msb1_n_72,
P(32) => msb1_n_73,
P(31) => msb1_n_74,
P(30) => msb1_n_75,
P(29) => msb1_n_76,
P(28) => msb1_n_77,
P(27) => msb1_n_78,
P(26) => msb1_n_79,
P(25) => msb1_n_80,
P(24) => msb1_n_81,
P(23) => msb1_n_82,
P(22) => msb1_n_83,
P(21) => msb1_n_84,
P(20) => msb1_n_85,
P(19) => msb1_n_86,
P(18) => msb1_n_87,
P(17) => msb1_n_88,
P(16 downto 0) => \msb1__1\(16 downto 0),
PATTERNBDETECT => NLW_msb1_PATTERNBDETECT_UNCONNECTED,
PATTERNDETECT => NLW_msb1_PATTERNDETECT_UNCONNECTED,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47) => msb1_n_106,
PCOUT(46) => msb1_n_107,
PCOUT(45) => msb1_n_108,
PCOUT(44) => msb1_n_109,
PCOUT(43) => msb1_n_110,
PCOUT(42) => msb1_n_111,
PCOUT(41) => msb1_n_112,
PCOUT(40) => msb1_n_113,
PCOUT(39) => msb1_n_114,
PCOUT(38) => msb1_n_115,
PCOUT(37) => msb1_n_116,
PCOUT(36) => msb1_n_117,
PCOUT(35) => msb1_n_118,
PCOUT(34) => msb1_n_119,
PCOUT(33) => msb1_n_120,
PCOUT(32) => msb1_n_121,
PCOUT(31) => msb1_n_122,
PCOUT(30) => msb1_n_123,
PCOUT(29) => msb1_n_124,
PCOUT(28) => msb1_n_125,
PCOUT(27) => msb1_n_126,
PCOUT(26) => msb1_n_127,
PCOUT(25) => msb1_n_128,
PCOUT(24) => msb1_n_129,
PCOUT(23) => msb1_n_130,
PCOUT(22) => msb1_n_131,
PCOUT(21) => msb1_n_132,
PCOUT(20) => msb1_n_133,
PCOUT(19) => msb1_n_134,
PCOUT(18) => msb1_n_135,
PCOUT(17) => msb1_n_136,
PCOUT(16) => msb1_n_137,
PCOUT(15) => msb1_n_138,
PCOUT(14) => msb1_n_139,
PCOUT(13) => msb1_n_140,
PCOUT(12) => msb1_n_141,
PCOUT(11) => msb1_n_142,
PCOUT(10) => msb1_n_143,
PCOUT(9) => msb1_n_144,
PCOUT(8) => msb1_n_145,
PCOUT(7) => msb1_n_146,
PCOUT(6) => msb1_n_147,
PCOUT(5) => msb1_n_148,
PCOUT(4) => msb1_n_149,
PCOUT(3) => msb1_n_150,
PCOUT(2) => msb1_n_151,
PCOUT(1) => msb1_n_152,
PCOUT(0) => msb1_n_153,
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => NLW_msb1_UNDERFLOW_UNCONNECTED
);
\msb1__0\: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29 downto 23) => B"0000001",
A(22 downto 0) => y(22 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => \NLW_msb1__0_ACOUT_UNCONNECTED\(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17 downto 6) => B"000000000001",
B(5 downto 0) => x(22 downto 17),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => \NLW_msb1__0_BCOUT_UNCONNECTED\(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => \NLW_msb1__0_CARRYCASCOUT_UNCONNECTED\,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => \NLW_msb1__0_CARRYOUT_UNCONNECTED\(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => \NLW_msb1__0_MULTSIGNOUT_UNCONNECTED\,
OPMODE(6 downto 0) => B"1010101",
OVERFLOW => \NLW_msb1__0_OVERFLOW_UNCONNECTED\,
P(47 downto 31) => \NLW_msb1__0_P_UNCONNECTED\(47 downto 31),
P(30 downto 0) => \msb1__1\(47 downto 17),
PATTERNBDETECT => \NLW_msb1__0_PATTERNBDETECT_UNCONNECTED\,
PATTERNDETECT => \NLW_msb1__0_PATTERNDETECT_UNCONNECTED\,
PCIN(47) => msb1_n_106,
PCIN(46) => msb1_n_107,
PCIN(45) => msb1_n_108,
PCIN(44) => msb1_n_109,
PCIN(43) => msb1_n_110,
PCIN(42) => msb1_n_111,
PCIN(41) => msb1_n_112,
PCIN(40) => msb1_n_113,
PCIN(39) => msb1_n_114,
PCIN(38) => msb1_n_115,
PCIN(37) => msb1_n_116,
PCIN(36) => msb1_n_117,
PCIN(35) => msb1_n_118,
PCIN(34) => msb1_n_119,
PCIN(33) => msb1_n_120,
PCIN(32) => msb1_n_121,
PCIN(31) => msb1_n_122,
PCIN(30) => msb1_n_123,
PCIN(29) => msb1_n_124,
PCIN(28) => msb1_n_125,
PCIN(27) => msb1_n_126,
PCIN(26) => msb1_n_127,
PCIN(25) => msb1_n_128,
PCIN(24) => msb1_n_129,
PCIN(23) => msb1_n_130,
PCIN(22) => msb1_n_131,
PCIN(21) => msb1_n_132,
PCIN(20) => msb1_n_133,
PCIN(19) => msb1_n_134,
PCIN(18) => msb1_n_135,
PCIN(17) => msb1_n_136,
PCIN(16) => msb1_n_137,
PCIN(15) => msb1_n_138,
PCIN(14) => msb1_n_139,
PCIN(13) => msb1_n_140,
PCIN(12) => msb1_n_141,
PCIN(11) => msb1_n_142,
PCIN(10) => msb1_n_143,
PCIN(9) => msb1_n_144,
PCIN(8) => msb1_n_145,
PCIN(7) => msb1_n_146,
PCIN(6) => msb1_n_147,
PCIN(5) => msb1_n_148,
PCIN(4) => msb1_n_149,
PCIN(3) => msb1_n_150,
PCIN(2) => msb1_n_151,
PCIN(1) => msb1_n_152,
PCIN(0) => msb1_n_153,
PCOUT(47 downto 0) => \NLW_msb1__0_PCOUT_UNCONNECTED\(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => \NLW_msb1__0_UNDERFLOW_UNCONNECTED\
);
\z[11]_INST_0_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \z[7]_INST_0_i_1_n_0\,
CO(3) => \z[11]_INST_0_i_1_n_0\,
CO(2) => \z[11]_INST_0_i_1_n_1\,
CO(1) => \z[11]_INST_0_i_1_n_2\,
CO(0) => \z[11]_INST_0_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => z_mantissa(11 downto 8),
S(3) => sel0(11),
S(2) => \z[11]_INST_0_i_3_n_0\,
S(1 downto 0) => sel0(9 downto 8)
);
\z[11]_INST_0_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \z[30]_INST_0_i_11_n_0\,
O => sel0(11)
);
\z[11]_INST_0_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFF8A80"
)
port map (
I0 => L1,
I1 => \z[30]_INST_0_i_50_n_0\,
I2 => \_carry_i_1_n_0\,
I3 => \z[30]_INST_0_i_47_n_0\,
I4 => \z[30]_INST_0_i_51_n_0\,
O => \z[11]_INST_0_i_3_n_0\
);
\z[11]_INST_0_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \z[11]_INST_0_i_6_n_0\,
O => sel0(9)
);
\z[11]_INST_0_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \z[11]_INST_0_i_7_n_0\,
O => sel0(8)
);
\z[11]_INST_0_i_6\: unisim.vcomponents.LUT5
generic map(
INIT => X"000047FF"
)
port map (
I0 => \z[11]_INST_0_i_8_n_0\,
I1 => \_carry_i_1_n_0\,
I2 => \z[30]_INST_0_i_50_n_0\,
I3 => L1,
I4 => \z[30]_INST_0_i_52_n_0\,
O => \z[11]_INST_0_i_6_n_0\
);
\z[11]_INST_0_i_7\: unisim.vcomponents.LUT5
generic map(
INIT => X"000047FF"
)
port map (
I0 => \z[11]_INST_0_i_9_n_0\,
I1 => \_carry_i_1_n_0\,
I2 => \z[11]_INST_0_i_8_n_0\,
I3 => L1,
I4 => \z[30]_INST_0_i_54_n_0\,
O => \z[11]_INST_0_i_7_n_0\
);
\z[11]_INST_0_i_8\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \z[30]_INST_0_i_121_n_0\,
I1 => \_carry_i_10_n_0\,
I2 => \z[30]_INST_0_i_98_n_0\,
O => \z[11]_INST_0_i_8_n_0\
);
\z[11]_INST_0_i_9\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \z[30]_INST_0_i_100_n_0\,
I1 => \_carry_i_10_n_0\,
I2 => \z[30]_INST_0_i_101_n_0\,
O => \z[11]_INST_0_i_9_n_0\
);
\z[15]_INST_0_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \z[11]_INST_0_i_1_n_0\,
CO(3) => \z[15]_INST_0_i_1_n_0\,
CO(2) => \z[15]_INST_0_i_1_n_1\,
CO(1) => \z[15]_INST_0_i_1_n_2\,
CO(0) => \z[15]_INST_0_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => z_mantissa(15 downto 12),
S(3 downto 0) => sel0(15 downto 12)
);
\z[15]_INST_0_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \z[30]_INST_0_i_14_n_0\,
O => sel0(15)
);
\z[15]_INST_0_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \z[30]_INST_0_i_15_n_0\,
O => sel0(14)
);
\z[15]_INST_0_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \z[15]_INST_0_i_6_n_0\,
O => sel0(13)
);
\z[15]_INST_0_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \z[15]_INST_0_i_7_n_0\,
O => sel0(12)
);
\z[15]_INST_0_i_6\: unisim.vcomponents.LUT5
generic map(
INIT => X"000047FF"
)
port map (
I0 => \z[15]_INST_0_i_8_n_0\,
I1 => \_carry_i_1_n_0\,
I2 => \z[30]_INST_0_i_60_n_0\,
I3 => L1,
I4 => \z[30]_INST_0_i_63_n_0\,
O => \z[15]_INST_0_i_6_n_0\
);
\z[15]_INST_0_i_7\: unisim.vcomponents.LUT5
generic map(
INIT => X"000047FF"
)
port map (
I0 => \z[30]_INST_0_i_48_n_0\,
I1 => \_carry_i_1_n_0\,
I2 => \z[15]_INST_0_i_8_n_0\,
I3 => L1,
I4 => \z[30]_INST_0_i_65_n_0\,
O => \z[15]_INST_0_i_7_n_0\
);
\z[15]_INST_0_i_8\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \z[30]_INST_0_i_142_n_0\,
I1 => \_carry_i_10_n_0\,
I2 => \z[30]_INST_0_i_120_n_0\,
O => \z[15]_INST_0_i_8_n_0\
);
\z[19]_INST_0_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \z[15]_INST_0_i_1_n_0\,
CO(3) => \z[19]_INST_0_i_1_n_0\,
CO(2) => \z[19]_INST_0_i_1_n_1\,
CO(1) => \z[19]_INST_0_i_1_n_2\,
CO(0) => \z[19]_INST_0_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => z_mantissa(19 downto 16),
S(3 downto 0) => sel0(19 downto 16)
);
\z[19]_INST_0_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \z[30]_INST_0_i_17_n_0\,
O => sel0(19)
);
\z[19]_INST_0_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \z[30]_INST_0_i_18_n_0\,
O => sel0(18)
);
\z[19]_INST_0_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \z[30]_INST_0_i_19_n_0\,
O => sel0(17)
);
\z[19]_INST_0_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \z[30]_INST_0_i_20_n_0\,
O => sel0(16)
);
\z[22]_INST_0_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \z[19]_INST_0_i_1_n_0\,
CO(3 downto 2) => \NLW_z[22]_INST_0_i_1_CO_UNCONNECTED\(3 downto 2),
CO(1) => \z[22]_INST_0_i_1_n_2\,
CO(0) => \z[22]_INST_0_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \NLW_z[22]_INST_0_i_1_O_UNCONNECTED\(3),
O(2 downto 0) => z_mantissa(22 downto 20),
S(3) => '0',
S(2 downto 0) => sel0(22 downto 20)
);
\z[22]_INST_0_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"F2F2FFF2"
)
port map (
I0 => \z[30]_INST_0_i_57_n_0\,
I1 => \z[30]_INST_0_i_81_n_0\,
I2 => \z[30]_INST_0_i_76_n_0\,
I3 => L1,
I4 => \z[22]_INST_0_i_5_n_0\,
O => sel0(22)
);
\z[22]_INST_0_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \z[30]_INST_0_i_22_n_0\,
O => sel0(21)
);
\z[22]_INST_0_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"22F222F2FFFF22F2"
)
port map (
I0 => \z[30]_INST_0_i_43_n_0\,
I1 => \z[30]_INST_0_i_82_n_0\,
I2 => \z[30]_INST_0_i_57_n_0\,
I3 => \z[30]_INST_0_i_67_n_0\,
I4 => L1,
I5 => \z[22]_INST_0_i_6_n_0\,
O => sel0(20)
);
\z[22]_INST_0_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[30]_INST_0_i_168_n_0\,
I1 => \z[30]_INST_0_i_154_n_0\,
I2 => \_carry_i_1_n_0\,
I3 => \z[30]_INST_0_i_159_n_0\,
I4 => \_carry_i_10_n_0\,
I5 => \z[30]_INST_0_i_158_n_0\,
O => \z[22]_INST_0_i_5_n_0\
);
\z[22]_INST_0_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[30]_INST_0_i_154_n_0\,
I1 => \z[30]_INST_0_i_155_n_0\,
I2 => \_carry_i_1_n_0\,
I3 => \z[30]_INST_0_i_158_n_0\,
I4 => \_carry_i_10_n_0\,
I5 => \z[30]_INST_0_i_152_n_0\,
O => \z[22]_INST_0_i_6_n_0\
);
\z[23]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000FFFE0002"
)
port map (
I0 => data0(0),
I1 => \z[30]_INST_0_i_1_n_0\,
I2 => \z[30]_INST_0_i_2_n_0\,
I3 => \z[30]_INST_0_i_3_n_0\,
I4 => data1(0),
I5 => \y_11__s_net_1\,
O => z(0)
);
\z[24]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000FFFE0002"
)
port map (
I0 => data0(1),
I1 => \z[30]_INST_0_i_1_n_0\,
I2 => \z[30]_INST_0_i_2_n_0\,
I3 => \z[30]_INST_0_i_3_n_0\,
I4 => data1(1),
I5 => \y_11__s_net_1\,
O => z(1)
);
\z[25]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000FFFE0002"
)
port map (
I0 => data0(2),
I1 => \z[30]_INST_0_i_1_n_0\,
I2 => \z[30]_INST_0_i_2_n_0\,
I3 => \z[30]_INST_0_i_3_n_0\,
I4 => data1(2),
I5 => \y_11__s_net_1\,
O => z(2)
);
\z[26]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000FFFE0002"
)
port map (
I0 => data0(3),
I1 => \z[30]_INST_0_i_1_n_0\,
I2 => \z[30]_INST_0_i_2_n_0\,
I3 => \z[30]_INST_0_i_3_n_0\,
I4 => data1(3),
I5 => \y_11__s_net_1\,
O => z(3)
);
\z[27]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000FFFE0002"
)
port map (
I0 => data0(4),
I1 => \z[30]_INST_0_i_1_n_0\,
I2 => \z[30]_INST_0_i_2_n_0\,
I3 => \z[30]_INST_0_i_3_n_0\,
I4 => data1(4),
I5 => \y_11__s_net_1\,
O => z(4)
);
\z[28]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000FFFE0002"
)
port map (
I0 => data0(5),
I1 => \z[30]_INST_0_i_1_n_0\,
I2 => \z[30]_INST_0_i_2_n_0\,
I3 => \z[30]_INST_0_i_3_n_0\,
I4 => data1(5),
I5 => \y_11__s_net_1\,
O => z(5)
);
\z[29]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000FFFE0002"
)
port map (
I0 => data0(6),
I1 => \z[30]_INST_0_i_1_n_0\,
I2 => \z[30]_INST_0_i_2_n_0\,
I3 => \z[30]_INST_0_i_3_n_0\,
I4 => data1(6),
I5 => \y_11__s_net_1\,
O => z(6)
);
\z[30]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000FFFE0002"
)
port map (
I0 => data0(7),
I1 => \z[30]_INST_0_i_1_n_0\,
I2 => \z[30]_INST_0_i_2_n_0\,
I3 => \z[30]_INST_0_i_3_n_0\,
I4 => data1(7),
I5 => \y_11__s_net_1\,
O => z(7)
);
\z[30]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFEFFFFFFFFFFF"
)
port map (
I0 => \z[30]_INST_0_i_5_n_0\,
I1 => \z[30]_INST_0_i_6_n_0\,
I2 => sel0(3),
I3 => sel0(0),
I4 => \z[30]_INST_0_i_9_n_0\,
I5 => sel0(2),
O => \z[30]_INST_0_i_1_n_0\
);
\z[30]_INST_0_i_10\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFF8A80"
)
port map (
I0 => L1,
I1 => \z[30]_INST_0_i_44_n_0\,
I2 => \_carry_i_1_n_0\,
I3 => \z[30]_INST_0_i_37_n_0\,
I4 => \z[30]_INST_0_i_46_n_0\,
O => sel0(2)
);
\z[30]_INST_0_i_100\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[30]_INST_0_i_181_n_0\,
I1 => \z[30]_INST_0_i_182_n_0\,
I2 => L1_carry_i_16_n_0,
I3 => \z[30]_INST_0_i_183_n_0\,
I4 => L1_carry_i_17_n_0,
I5 => \z[30]_INST_0_i_184_n_0\,
O => \z[30]_INST_0_i_100_n_0\
);
\z[30]_INST_0_i_101\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[30]_INST_0_i_185_n_0\,
I1 => \z[30]_INST_0_i_186_n_0\,
I2 => L1_carry_i_16_n_0,
I3 => \z[30]_INST_0_i_187_n_0\,
I4 => L1_carry_i_17_n_0,
I5 => \z[30]_INST_0_i_188_n_0\,
O => \z[30]_INST_0_i_101_n_0\
);
\z[30]_INST_0_i_102\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \z[30]_INST_0_i_189_n_0\,
I1 => \z[30]_INST_0_i_95_n_0\,
I2 => \z[30]_INST_0_i_171_n_0\,
O => \z[30]_INST_0_i_102_n_0\
);
\z[30]_INST_0_i_103\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFF4FFF7"
)
port map (
I0 => \msb1__1\(1),
I1 => \z[30]_INST_0_i_95_n_0\,
I2 => \z[30]_INST_0_i_118_n_0\,
I3 => \z[30]_INST_0_i_170_n_0\,
I4 => \msb1__1\(3),
I5 => \z[30]_INST_0_i_169_n_0\,
O => \z[30]_INST_0_i_103_n_0\
);
\z[30]_INST_0_i_104\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[30]_INST_0_i_183_n_0\,
I1 => \z[30]_INST_0_i_184_n_0\,
I2 => L1_carry_i_16_n_0,
I3 => \z[30]_INST_0_i_190_n_0\,
I4 => L1_carry_i_17_n_0,
I5 => \z[30]_INST_0_i_181_n_0\,
O => \z[30]_INST_0_i_104_n_0\
);
\z[30]_INST_0_i_105\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[30]_INST_0_i_187_n_0\,
I1 => \z[30]_INST_0_i_188_n_0\,
I2 => L1_carry_i_16_n_0,
I3 => \z[30]_INST_0_i_191_n_0\,
I4 => L1_carry_i_17_n_0,
I5 => \z[30]_INST_0_i_185_n_0\,
O => \z[30]_INST_0_i_105_n_0\
);
\z[30]_INST_0_i_106\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[30]_INST_0_i_175_n_0\,
I1 => \z[30]_INST_0_i_176_n_0\,
I2 => L1_carry_i_16_n_0,
I3 => \z[30]_INST_0_i_192_n_0\,
I4 => L1_carry_i_17_n_0,
I5 => \z[30]_INST_0_i_173_n_0\,
O => \z[30]_INST_0_i_106_n_0\
);
\z[30]_INST_0_i_107\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFEAEFFFF"
)
port map (
I0 => \z[30]_INST_0_i_118_n_0\,
I1 => \_carry_n_4\,
I2 => L1,
I3 => L1_carry_i_14_n_0,
I4 => \msb1__1\(3),
I5 => \z[30]_INST_0_i_169_n_0\,
O => \z[30]_INST_0_i_107_n_0\
);
\z[30]_INST_0_i_108\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[30]_INST_0_i_179_n_0\,
I1 => \z[30]_INST_0_i_180_n_0\,
I2 => L1_carry_i_16_n_0,
I3 => \z[30]_INST_0_i_193_n_0\,
I4 => L1_carry_i_17_n_0,
I5 => \z[30]_INST_0_i_177_n_0\,
O => \z[30]_INST_0_i_108_n_0\
);
\z[30]_INST_0_i_109\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFF4F7FFFF"
)
port map (
I0 => \msb1__1\(0),
I1 => \z[30]_INST_0_i_95_n_0\,
I2 => \z[30]_INST_0_i_118_n_0\,
I3 => \msb1__1\(2),
I4 => \z[30]_INST_0_i_194_n_0\,
I5 => \z[30]_INST_0_i_169_n_0\,
O => \z[30]_INST_0_i_109_n_0\
);
\z[30]_INST_0_i_11\: unisim.vcomponents.LUT5
generic map(
INIT => X"000047FF"
)
port map (
I0 => \z[30]_INST_0_i_47_n_0\,
I1 => \_carry_i_1_n_0\,
I2 => \z[30]_INST_0_i_48_n_0\,
I3 => L1,
I4 => \z[30]_INST_0_i_49_n_0\,
O => \z[30]_INST_0_i_11_n_0\
);
\z[30]_INST_0_i_110\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[30]_INST_0_i_190_n_0\,
I1 => \z[30]_INST_0_i_181_n_0\,
I2 => L1_carry_i_16_n_0,
I3 => \z[30]_INST_0_i_195_n_0\,
I4 => L1_carry_i_17_n_0,
I5 => \z[30]_INST_0_i_183_n_0\,
O => \z[30]_INST_0_i_110_n_0\
);
\z[30]_INST_0_i_111\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \z[30]_INST_0_i_191_n_0\,
I1 => L1_carry_i_17_n_0,
I2 => \z[30]_INST_0_i_185_n_0\,
O => \z[30]_INST_0_i_111_n_0\
);
\z[30]_INST_0_i_112\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \z[30]_INST_0_i_196_n_0\,
I1 => L1_carry_i_17_n_0,
I2 => \z[30]_INST_0_i_187_n_0\,
O => \z[30]_INST_0_i_112_n_0\
);
\z[30]_INST_0_i_113\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \z[30]_INST_0_i_192_n_0\,
I1 => L1_carry_i_17_n_0,
I2 => \z[30]_INST_0_i_173_n_0\,
O => \z[30]_INST_0_i_113_n_0\
);
\z[30]_INST_0_i_114\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \z[30]_INST_0_i_197_n_0\,
I1 => L1_carry_i_17_n_0,
I2 => \z[30]_INST_0_i_175_n_0\,
O => \z[30]_INST_0_i_114_n_0\
);
\z[30]_INST_0_i_115\: unisim.vcomponents.LUT6
generic map(
INIT => X"3FFF3FAAFFFFFFFF"
)
port map (
I0 => \_carry_n_5\,
I1 => L1_carry_i_17_n_0,
I2 => \z[30]_INST_0_i_198_n_0\,
I3 => L1,
I4 => \_carry_n_4\,
I5 => \msb1__1\(0),
O => \z[30]_INST_0_i_115_n_0\
);
\z[30]_INST_0_i_116\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => \z[30]_INST_0_i_199_n_0\,
I1 => \_carry__0_n_6\,
I2 => \_carry__5_n_6\,
I3 => \_carry__0_n_5\,
I4 => \z[30]_INST_0_i_200_n_0\,
I5 => \z[30]_INST_0_i_201_n_0\,
O => \z[30]_INST_0_i_116_n_0\
);
\z[30]_INST_0_i_117\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF3FFFFFFF3FAFAF"
)
port map (
I0 => \_carry_n_5\,
I1 => L1_carry_i_17_n_0,
I2 => \msb1__1\(1),
I3 => L1_carry_i_14_n_0,
I4 => L1,
I5 => \_carry_n_4\,
O => \z[30]_INST_0_i_117_n_0\
);
\z[30]_INST_0_i_118\: unisim.vcomponents.LUT5
generic map(
INIT => X"3C33AAAA"
)
port map (
I0 => \_carry_n_6\,
I1 => L1_carry_i_11_n_0,
I2 => L1_carry_i_10_n_0,
I3 => \_carry_i_1_n_0\,
I4 => L1,
O => \z[30]_INST_0_i_118_n_0\
);
\z[30]_INST_0_i_119\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFEAEFFFF"
)
port map (
I0 => \z[30]_INST_0_i_118_n_0\,
I1 => \_carry_n_4\,
I2 => L1,
I3 => L1_carry_i_14_n_0,
I4 => \msb1__1\(1),
I5 => \z[30]_INST_0_i_169_n_0\,
O => \z[30]_INST_0_i_119_n_0\
);
\z[30]_INST_0_i_12\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFF8A80"
)
port map (
I0 => L1,
I1 => \z[30]_INST_0_i_50_n_0\,
I2 => \_carry_i_1_n_0\,
I3 => \z[30]_INST_0_i_47_n_0\,
I4 => \z[30]_INST_0_i_51_n_0\,
O => sel0(10)
);
\z[30]_INST_0_i_120\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[30]_INST_0_i_176_n_0\,
I1 => \z[30]_INST_0_i_202_n_0\,
I2 => L1_carry_i_16_n_0,
I3 => \z[30]_INST_0_i_173_n_0\,
I4 => L1_carry_i_17_n_0,
I5 => \z[30]_INST_0_i_174_n_0\,
O => \z[30]_INST_0_i_120_n_0\
);
\z[30]_INST_0_i_121\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[30]_INST_0_i_180_n_0\,
I1 => \z[30]_INST_0_i_203_n_0\,
I2 => L1_carry_i_16_n_0,
I3 => \z[30]_INST_0_i_177_n_0\,
I4 => L1_carry_i_17_n_0,
I5 => \z[30]_INST_0_i_178_n_0\,
O => \z[30]_INST_0_i_121_n_0\
);
\z[30]_INST_0_i_122\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[30]_INST_0_i_184_n_0\,
I1 => \z[30]_INST_0_i_204_n_0\,
I2 => L1_carry_i_16_n_0,
I3 => \z[30]_INST_0_i_181_n_0\,
I4 => L1_carry_i_17_n_0,
I5 => \z[30]_INST_0_i_182_n_0\,
O => \z[30]_INST_0_i_122_n_0\
);
\z[30]_INST_0_i_123\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[30]_INST_0_i_188_n_0\,
I1 => \z[30]_INST_0_i_205_n_0\,
I2 => L1_carry_i_16_n_0,
I3 => \z[30]_INST_0_i_185_n_0\,
I4 => L1_carry_i_17_n_0,
I5 => \z[30]_INST_0_i_186_n_0\,
O => \z[30]_INST_0_i_123_n_0\
);
\z[30]_INST_0_i_124\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \z[30]_INST_0_i_206_n_0\,
I1 => \z[30]_INST_0_i_118_n_0\,
I2 => \z[30]_INST_0_i_207_n_0\,
I3 => \z[30]_INST_0_i_95_n_0\,
I4 => \z[30]_INST_0_i_208_n_0\,
O => \z[30]_INST_0_i_124_n_0\
);
\z[30]_INST_0_i_125\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \z[30]_INST_0_i_209_n_0\,
I1 => \z[30]_INST_0_i_118_n_0\,
I2 => \z[30]_INST_0_i_132_n_0\,
I3 => \z[30]_INST_0_i_95_n_0\,
I4 => \z[30]_INST_0_i_210_n_0\,
O => \z[30]_INST_0_i_125_n_0\
);
\z[30]_INST_0_i_126\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \z[30]_INST_0_i_96_n_0\,
I1 => \z[30]_INST_0_i_95_n_0\,
I2 => \z[30]_INST_0_i_206_n_0\,
I3 => \z[30]_INST_0_i_118_n_0\,
I4 => \z[30]_INST_0_i_207_n_0\,
O => \z[30]_INST_0_i_126_n_0\
);
\z[30]_INST_0_i_127\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \z[30]_INST_0_i_172_n_0\,
I1 => \z[30]_INST_0_i_95_n_0\,
I2 => \z[30]_INST_0_i_209_n_0\,
I3 => \z[30]_INST_0_i_118_n_0\,
I4 => \z[30]_INST_0_i_132_n_0\,
O => \z[30]_INST_0_i_127_n_0\
);
\z[30]_INST_0_i_128\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA03030AFA03F3F"
)
port map (
I0 => \z[30]_INST_0_i_211_n_0\,
I1 => \z[30]_INST_0_i_212_n_0\,
I2 => L1_carry_i_16_n_0,
I3 => \z[30]_INST_0_i_213_n_0\,
I4 => L1_carry_i_17_n_0,
I5 => \z[30]_INST_0_i_202_n_0\,
O => \z[30]_INST_0_i_128_n_0\
);
\z[30]_INST_0_i_129\: unisim.vcomponents.LUT6
generic map(
INIT => X"505F3030505F3F3F"
)
port map (
I0 => \z[30]_INST_0_i_178_n_0\,
I1 => \z[30]_INST_0_i_214_n_0\,
I2 => L1_carry_i_16_n_0,
I3 => \z[30]_INST_0_i_180_n_0\,
I4 => L1_carry_i_17_n_0,
I5 => \z[30]_INST_0_i_203_n_0\,
O => \z[30]_INST_0_i_129_n_0\
);
\z[30]_INST_0_i_13\: unisim.vcomponents.LUT5
generic map(
INIT => X"115F1F5F"
)
port map (
I0 => \z[30]_INST_0_i_52_n_0\,
I1 => \z[30]_INST_0_i_53_n_0\,
I2 => \z[30]_INST_0_i_54_n_0\,
I3 => L1,
I4 => \z[30]_INST_0_i_55_n_0\,
O => \z[30]_INST_0_i_13_n_0\
);
\z[30]_INST_0_i_130\: unisim.vcomponents.LUT6
generic map(
INIT => X"505FC0C0505FCFCF"
)
port map (
I0 => \z[30]_INST_0_i_182_n_0\,
I1 => \z[30]_INST_0_i_215_n_0\,
I2 => L1_carry_i_16_n_0,
I3 => \z[30]_INST_0_i_184_n_0\,
I4 => L1_carry_i_17_n_0,
I5 => \z[30]_INST_0_i_204_n_0\,
O => \z[30]_INST_0_i_130_n_0\
);
\z[30]_INST_0_i_131\: unisim.vcomponents.LUT6
generic map(
INIT => X"A0AF3030A0AF3F3F"
)
port map (
I0 => \z[30]_INST_0_i_216_n_0\,
I1 => \z[30]_INST_0_i_217_n_0\,
I2 => L1_carry_i_16_n_0,
I3 => \z[30]_INST_0_i_188_n_0\,
I4 => L1_carry_i_17_n_0,
I5 => \z[30]_INST_0_i_205_n_0\,
O => \z[30]_INST_0_i_131_n_0\
);
\z[30]_INST_0_i_132\: unisim.vcomponents.LUT6
generic map(
INIT => X"1510D5DFFFFFFFFF"
)
port map (
I0 => \msb1__1\(0),
I1 => L1_carry_i_17_n_0,
I2 => L1,
I3 => \_carry_n_5\,
I4 => \msb1__1\(8),
I5 => \z[30]_INST_0_i_194_n_0\,
O => \z[30]_INST_0_i_132_n_0\
);
\z[30]_INST_0_i_133\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFF444F4FFF777F7"
)
port map (
I0 => \msb1__1\(4),
I1 => \z[30]_INST_0_i_169_n_0\,
I2 => \_carry_n_4\,
I3 => L1,
I4 => L1_carry_i_14_n_0,
I5 => \msb1__1\(12),
O => \z[30]_INST_0_i_133_n_0\
);
\z[30]_INST_0_i_134\: unisim.vcomponents.LUT6
generic map(
INIT => X"1510D5DFFFFFFFFF"
)
port map (
I0 => \msb1__1\(2),
I1 => L1_carry_i_17_n_0,
I2 => L1,
I3 => \_carry_n_5\,
I4 => \msb1__1\(10),
I5 => \z[30]_INST_0_i_194_n_0\,
O => \z[30]_INST_0_i_134_n_0\
);
\z[30]_INST_0_i_135\: unisim.vcomponents.LUT6
generic map(
INIT => X"1510D5DFFFFFFFFF"
)
port map (
I0 => \msb1__1\(6),
I1 => L1_carry_i_17_n_0,
I2 => L1,
I3 => \_carry_n_5\,
I4 => \msb1__1\(14),
I5 => \z[30]_INST_0_i_194_n_0\,
O => \z[30]_INST_0_i_135_n_0\
);
\z[30]_INST_0_i_136\: unisim.vcomponents.LUT5
generic map(
INIT => X"AFBBA088"
)
port map (
I0 => \z[30]_INST_0_i_207_n_0\,
I1 => \_carry_n_6\,
I2 => L1_carry_i_16_n_0,
I3 => L1,
I4 => \z[30]_INST_0_i_146_n_0\,
O => \z[30]_INST_0_i_136_n_0\
);
\z[30]_INST_0_i_137\: unisim.vcomponents.LUT5
generic map(
INIT => X"AFBBA088"
)
port map (
I0 => \z[30]_INST_0_i_218_n_0\,
I1 => \_carry_n_6\,
I2 => L1_carry_i_16_n_0,
I3 => L1,
I4 => \z[30]_INST_0_i_148_n_0\,
O => \z[30]_INST_0_i_137_n_0\
);
\z[30]_INST_0_i_138\: unisim.vcomponents.LUT6
generic map(
INIT => X"B080FFFFB0800000"
)
port map (
I0 => \msb1__1\(36),
I1 => L1_carry_i_14_n_0,
I2 => L1_carry_i_15_n_0,
I3 => \msb1__1\(20),
I4 => L1_carry_i_17_n_0,
I5 => \z[30]_INST_0_i_217_n_0\,
O => \z[30]_INST_0_i_138_n_0\
);
\z[30]_INST_0_i_139\: unisim.vcomponents.LUT6
generic map(
INIT => X"B8BB8888B8B88888"
)
port map (
I0 => \z[30]_INST_0_i_188_n_0\,
I1 => L1_carry_i_17_n_0,
I2 => \msb1__1\(40),
I3 => L1_carry_i_14_n_0,
I4 => L1_carry_i_15_n_0,
I5 => \msb1__1\(24),
O => \z[30]_INST_0_i_139_n_0\
);
\z[30]_INST_0_i_14\: unisim.vcomponents.LUT6
generic map(
INIT => X"DD0DDD0D0000DD0D"
)
port map (
I0 => L1,
I1 => \z[30]_INST_0_i_56_n_0\,
I2 => \z[30]_INST_0_i_57_n_0\,
I3 => \z[30]_INST_0_i_58_n_0\,
I4 => \z[30]_INST_0_i_43_n_0\,
I5 => \z[30]_INST_0_i_59_n_0\,
O => \z[30]_INST_0_i_14_n_0\
);
\z[30]_INST_0_i_140\: unisim.vcomponents.LUT6
generic map(
INIT => X"B080FFFFB0800000"
)
port map (
I0 => \msb1__1\(37),
I1 => L1_carry_i_14_n_0,
I2 => L1_carry_i_15_n_0,
I3 => \msb1__1\(21),
I4 => L1_carry_i_17_n_0,
I5 => \z[30]_INST_0_i_212_n_0\,
O => \z[30]_INST_0_i_140_n_0\
);
\z[30]_INST_0_i_141\: unisim.vcomponents.LUT6
generic map(
INIT => X"B080FFFFB0800000"
)
port map (
I0 => \msb1__1\(33),
I1 => L1_carry_i_14_n_0,
I2 => L1_carry_i_15_n_0,
I3 => \msb1__1\(17),
I4 => L1_carry_i_17_n_0,
I5 => \z[30]_INST_0_i_202_n_0\,
O => \z[30]_INST_0_i_141_n_0\
);
\z[30]_INST_0_i_142\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[30]_INST_0_i_178_n_0\,
I1 => \z[30]_INST_0_i_214_n_0\,
I2 => L1_carry_i_16_n_0,
I3 => \z[30]_INST_0_i_180_n_0\,
I4 => L1_carry_i_17_n_0,
I5 => \z[30]_INST_0_i_203_n_0\,
O => \z[30]_INST_0_i_142_n_0\
);
\z[30]_INST_0_i_143\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \z[30]_INST_0_i_208_n_0\,
I1 => \z[30]_INST_0_i_95_n_0\,
I2 => \z[30]_INST_0_i_207_n_0\,
I3 => \z[30]_INST_0_i_118_n_0\,
I4 => \z[30]_INST_0_i_146_n_0\,
O => \z[30]_INST_0_i_143_n_0\
);
\z[30]_INST_0_i_144\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \z[30]_INST_0_i_210_n_0\,
I1 => \z[30]_INST_0_i_95_n_0\,
I2 => \z[30]_INST_0_i_132_n_0\,
I3 => \z[30]_INST_0_i_118_n_0\,
I4 => \z[30]_INST_0_i_133_n_0\,
O => \z[30]_INST_0_i_144_n_0\
);
\z[30]_INST_0_i_145\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[30]_INST_0_i_186_n_0\,
I1 => \z[30]_INST_0_i_217_n_0\,
I2 => L1_carry_i_16_n_0,
I3 => \z[30]_INST_0_i_188_n_0\,
I4 => L1_carry_i_17_n_0,
I5 => \z[30]_INST_0_i_205_n_0\,
O => \z[30]_INST_0_i_145_n_0\
);
\z[30]_INST_0_i_146\: unisim.vcomponents.LUT6
generic map(
INIT => X"4747FF47FFFFFF47"
)
port map (
I0 => \msb1__1\(5),
I1 => \z[30]_INST_0_i_169_n_0\,
I2 => \msb1__1\(13),
I3 => \_carry_n_4\,
I4 => L1,
I5 => \z[30]_INST_0_i_198_n_0\,
O => \z[30]_INST_0_i_146_n_0\
);
\z[30]_INST_0_i_147\: unisim.vcomponents.LUT6
generic map(
INIT => X"77CF44CC77CF77CF"
)
port map (
I0 => \msb1__1\(9),
I1 => \z[30]_INST_0_i_169_n_0\,
I2 => \msb1__1\(1),
I3 => \z[30]_INST_0_i_194_n_0\,
I4 => \z[30]_INST_0_i_170_n_0\,
I5 => \msb1__1\(17),
O => \z[30]_INST_0_i_147_n_0\
);
\z[30]_INST_0_i_148\: unisim.vcomponents.LUT6
generic map(
INIT => X"7757555777F7FFF7"
)
port map (
I0 => \z[30]_INST_0_i_194_n_0\,
I1 => \msb1__1\(15),
I2 => \_carry_n_5\,
I3 => L1,
I4 => L1_carry_i_17_n_0,
I5 => \msb1__1\(7),
O => \z[30]_INST_0_i_148_n_0\
);
\z[30]_INST_0_i_149\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF00FFFF47474747"
)
port map (
I0 => \msb1__1\(19),
I1 => \z[30]_INST_0_i_194_n_0\,
I2 => \msb1__1\(3),
I3 => \z[30]_INST_0_i_170_n_0\,
I4 => \msb1__1\(11),
I5 => \z[30]_INST_0_i_169_n_0\,
O => \z[30]_INST_0_i_149_n_0\
);
\z[30]_INST_0_i_15\: unisim.vcomponents.LUT5
generic map(
INIT => X"000047FF"
)
port map (
I0 => \z[30]_INST_0_i_60_n_0\,
I1 => \_carry_i_1_n_0\,
I2 => \z[30]_INST_0_i_61_n_0\,
I3 => L1,
I4 => \z[30]_INST_0_i_62_n_0\,
O => \z[30]_INST_0_i_15_n_0\
);
\z[30]_INST_0_i_150\: unisim.vcomponents.LUT5
generic map(
INIT => X"AFBBA088"
)
port map (
I0 => \z[30]_INST_0_i_133_n_0\,
I1 => \_carry_n_6\,
I2 => L1_carry_i_16_n_0,
I3 => L1,
I4 => \z[30]_INST_0_i_166_n_0\,
O => \z[30]_INST_0_i_150_n_0\
);
\z[30]_INST_0_i_151\: unisim.vcomponents.LUT5
generic map(
INIT => X"F5DD0511"
)
port map (
I0 => \z[30]_INST_0_i_163_n_0\,
I1 => \_carry_n_6\,
I2 => L1_carry_i_16_n_0,
I3 => L1,
I4 => \z[30]_INST_0_i_135_n_0\,
O => \z[30]_INST_0_i_151_n_0\
);
\z[30]_INST_0_i_152\: unisim.vcomponents.LUT5
generic map(
INIT => X"B888B8BB"
)
port map (
I0 => \z[30]_INST_0_i_219_n_0\,
I1 => L1_carry_i_16_n_0,
I2 => \z[30]_INST_0_i_211_n_0\,
I3 => L1_carry_i_17_n_0,
I4 => \z[30]_INST_0_i_212_n_0\,
O => \z[30]_INST_0_i_152_n_0\
);
\z[30]_INST_0_i_153\: unisim.vcomponents.LUT6
generic map(
INIT => X"505FC0C0505FCFCF"
)
port map (
I0 => \z[30]_INST_0_i_203_n_0\,
I1 => \z[30]_INST_0_i_220_n_0\,
I2 => L1_carry_i_16_n_0,
I3 => \z[30]_INST_0_i_178_n_0\,
I4 => L1_carry_i_17_n_0,
I5 => \z[30]_INST_0_i_214_n_0\,
O => \z[30]_INST_0_i_153_n_0\
);
\z[30]_INST_0_i_154\: unisim.vcomponents.LUT5
generic map(
INIT => X"8BBB8B88"
)
port map (
I0 => \z[30]_INST_0_i_221_n_0\,
I1 => L1_carry_i_16_n_0,
I2 => \z[30]_INST_0_i_182_n_0\,
I3 => L1_carry_i_17_n_0,
I4 => \z[30]_INST_0_i_215_n_0\,
O => \z[30]_INST_0_i_154_n_0\
);
\z[30]_INST_0_i_155\: unisim.vcomponents.LUT5
generic map(
INIT => X"B888B8BB"
)
port map (
I0 => \z[30]_INST_0_i_222_n_0\,
I1 => L1_carry_i_16_n_0,
I2 => \z[30]_INST_0_i_216_n_0\,
I3 => L1_carry_i_17_n_0,
I4 => \z[30]_INST_0_i_217_n_0\,
O => \z[30]_INST_0_i_155_n_0\
);
\z[30]_INST_0_i_156\: unisim.vcomponents.LUT5
generic map(
INIT => X"AFBBA088"
)
port map (
I0 => \z[30]_INST_0_i_146_n_0\,
I1 => \_carry_n_6\,
I2 => L1_carry_i_16_n_0,
I3 => L1,
I4 => \z[30]_INST_0_i_147_n_0\,
O => \z[30]_INST_0_i_156_n_0\
);
\z[30]_INST_0_i_157\: unisim.vcomponents.LUT5
generic map(
INIT => X"AFBBA088"
)
port map (
I0 => \z[30]_INST_0_i_134_n_0\,
I1 => \_carry_n_6\,
I2 => L1_carry_i_16_n_0,
I3 => L1,
I4 => \z[30]_INST_0_i_135_n_0\,
O => \z[30]_INST_0_i_157_n_0\
);
\z[30]_INST_0_i_158\: unisim.vcomponents.LUT5
generic map(
INIT => X"8BBB8B88"
)
port map (
I0 => \z[30]_INST_0_i_223_n_0\,
I1 => L1_carry_i_16_n_0,
I2 => \z[30]_INST_0_i_203_n_0\,
I3 => L1_carry_i_17_n_0,
I4 => \z[30]_INST_0_i_220_n_0\,
O => \z[30]_INST_0_i_158_n_0\
);
\z[30]_INST_0_i_159\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \z[30]_INST_0_i_224_n_0\,
I1 => L1_carry_i_16_n_0,
I2 => \z[30]_INST_0_i_219_n_0\,
O => \z[30]_INST_0_i_159_n_0\
);
\z[30]_INST_0_i_16\: unisim.vcomponents.LUT5
generic map(
INIT => X"115F1F5F"
)
port map (
I0 => \z[30]_INST_0_i_63_n_0\,
I1 => \z[30]_INST_0_i_64_n_0\,
I2 => \z[30]_INST_0_i_65_n_0\,
I3 => L1,
I4 => \z[30]_INST_0_i_66_n_0\,
O => \z[30]_INST_0_i_16_n_0\
);
\z[30]_INST_0_i_160\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[30]_INST_0_i_225_n_0\,
I1 => \z[30]_INST_0_i_222_n_0\,
I2 => \_carry_i_10_n_0\,
I3 => \z[30]_INST_0_i_221_n_0\,
I4 => L1_carry_i_16_n_0,
I5 => \z[30]_INST_0_i_226_n_0\,
O => \z[30]_INST_0_i_160_n_0\
);
\z[30]_INST_0_i_161\: unisim.vcomponents.LUT5
generic map(
INIT => X"B888B8BB"
)
port map (
I0 => \z[30]_INST_0_i_166_n_0\,
I1 => \z[30]_INST_0_i_118_n_0\,
I2 => \z[30]_INST_0_i_227_n_0\,
I3 => \z[30]_INST_0_i_169_n_0\,
I4 => \z[30]_INST_0_i_228_n_0\,
O => \z[30]_INST_0_i_161_n_0\
);
\z[30]_INST_0_i_162\: unisim.vcomponents.LUT5
generic map(
INIT => X"30BB3088"
)
port map (
I0 => \msb1__1\(14),
I1 => \z[30]_INST_0_i_169_n_0\,
I2 => \msb1__1\(6),
I3 => \z[30]_INST_0_i_170_n_0\,
I4 => \msb1__1\(22),
O => \z[30]_INST_0_i_162_n_0\
);
\z[30]_INST_0_i_163\: unisim.vcomponents.LUT5
generic map(
INIT => X"30BB3088"
)
port map (
I0 => \msb1__1\(10),
I1 => \z[30]_INST_0_i_169_n_0\,
I2 => \msb1__1\(2),
I3 => \z[30]_INST_0_i_170_n_0\,
I4 => \msb1__1\(18),
O => \z[30]_INST_0_i_163_n_0\
);
\z[30]_INST_0_i_164\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[30]_INST_0_i_223_n_0\,
I1 => \z[30]_INST_0_i_229_n_0\,
I2 => \_carry_i_10_n_0\,
I3 => \z[30]_INST_0_i_219_n_0\,
I4 => L1_carry_i_16_n_0,
I5 => \z[30]_INST_0_i_230_n_0\,
O => \z[30]_INST_0_i_164_n_0\
);
\z[30]_INST_0_i_165\: unisim.vcomponents.LUT5
generic map(
INIT => X"47CC47FF"
)
port map (
I0 => \msb1__1\(13),
I1 => \z[30]_INST_0_i_169_n_0\,
I2 => \msb1__1\(21),
I3 => \z[30]_INST_0_i_194_n_0\,
I4 => \msb1__1\(5),
O => \z[30]_INST_0_i_165_n_0\
);
\z[30]_INST_0_i_166\: unisim.vcomponents.LUT6
generic map(
INIT => X"4447CCCF4447FFFF"
)
port map (
I0 => \msb1__1\(8),
I1 => \z[30]_INST_0_i_169_n_0\,
I2 => \z[30]_INST_0_i_170_n_0\,
I3 => \msb1__1\(16),
I4 => \z[30]_INST_0_i_194_n_0\,
I5 => \msb1__1\(0),
O => \z[30]_INST_0_i_166_n_0\
);
\z[30]_INST_0_i_167\: unisim.vcomponents.LUT6
generic map(
INIT => X"B0BFB0B0B0BFBFBF"
)
port map (
I0 => \z[30]_INST_0_i_170_n_0\,
I1 => \msb1__1\(12),
I2 => \z[30]_INST_0_i_169_n_0\,
I3 => \msb1__1\(20),
I4 => \z[30]_INST_0_i_194_n_0\,
I5 => \msb1__1\(4),
O => \z[30]_INST_0_i_167_n_0\
);
\z[30]_INST_0_i_168\: unisim.vcomponents.LUT6
generic map(
INIT => X"7477FFFF74770000"
)
port map (
I0 => \z[30]_INST_0_i_217_n_0\,
I1 => L1_carry_i_17_n_0,
I2 => L1_carry_i_14_n_0,
I3 => \z[30]_INST_0_i_231_n_0\,
I4 => L1_carry_i_16_n_0,
I5 => \z[30]_INST_0_i_222_n_0\,
O => \z[30]_INST_0_i_168_n_0\
);
\z[30]_INST_0_i_169\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAA6FFFFAAA60000"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1,
I5 => \_carry_n_5\,
O => \z[30]_INST_0_i_169_n_0\
);
\z[30]_INST_0_i_17\: unisim.vcomponents.LUT6
generic map(
INIT => X"DD0DDD0D0000DD0D"
)
port map (
I0 => \z[30]_INST_0_i_43_n_0\,
I1 => \z[30]_INST_0_i_67_n_0\,
I2 => \z[30]_INST_0_i_57_n_0\,
I3 => \z[30]_INST_0_i_68_n_0\,
I4 => L1,
I5 => \z[30]_INST_0_i_69_n_0\,
O => \z[30]_INST_0_i_17_n_0\
);
\z[30]_INST_0_i_170\: unisim.vcomponents.LUT6
generic map(
INIT => X"9A55FFFF9A550000"
)
port map (
I0 => L1_carry_i_12_n_0,
I1 => \z[30]_INST_0_i_232_n_0\,
I2 => \_carry_i_1_n_0\,
I3 => L1_carry_i_9_n_0,
I4 => L1,
I5 => \_carry_n_4\,
O => \z[30]_INST_0_i_170_n_0\
);
\z[30]_INST_0_i_171\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF7FFF7FFF70FF7F"
)
port map (
I0 => \z[30]_INST_0_i_194_n_0\,
I1 => \msb1__1\(0),
I2 => \z[30]_INST_0_i_118_n_0\,
I3 => \z[30]_INST_0_i_169_n_0\,
I4 => \msb1__1\(4),
I5 => \z[30]_INST_0_i_170_n_0\,
O => \z[30]_INST_0_i_171_n_0\
);
\z[30]_INST_0_i_172\: unisim.vcomponents.LUT5
generic map(
INIT => X"F4FFF7FF"
)
port map (
I0 => \msb1__1\(2),
I1 => \z[30]_INST_0_i_118_n_0\,
I2 => \z[30]_INST_0_i_169_n_0\,
I3 => \z[30]_INST_0_i_194_n_0\,
I4 => \msb1__1\(6),
O => \z[30]_INST_0_i_172_n_0\
);
\z[30]_INST_0_i_173\: unisim.vcomponents.LUT5
generic map(
INIT => X"B833B800"
)
port map (
I0 => \msb1__1\(29),
I1 => L1_carry_i_14_n_0,
I2 => \msb1__1\(13),
I3 => L1_carry_i_15_n_0,
I4 => \msb1__1\(45),
O => \z[30]_INST_0_i_173_n_0\
);
\z[30]_INST_0_i_174\: unisim.vcomponents.LUT4
generic map(
INIT => X"B080"
)
port map (
I0 => \msb1__1\(37),
I1 => L1_carry_i_14_n_0,
I2 => L1_carry_i_15_n_0,
I3 => \msb1__1\(21),
O => \z[30]_INST_0_i_174_n_0\
);
\z[30]_INST_0_i_175\: unisim.vcomponents.LUT5
generic map(
INIT => X"B833B800"
)
port map (
I0 => \msb1__1\(25),
I1 => L1_carry_i_14_n_0,
I2 => \msb1__1\(9),
I3 => L1_carry_i_15_n_0,
I4 => \msb1__1\(41),
O => \z[30]_INST_0_i_175_n_0\
);
\z[30]_INST_0_i_176\: unisim.vcomponents.LUT4
generic map(
INIT => X"B080"
)
port map (
I0 => \msb1__1\(33),
I1 => L1_carry_i_14_n_0,
I2 => L1_carry_i_15_n_0,
I3 => \msb1__1\(17),
O => \z[30]_INST_0_i_176_n_0\
);
\z[30]_INST_0_i_177\: unisim.vcomponents.LUT5
generic map(
INIT => X"B833B800"
)
port map (
I0 => \msb1__1\(27),
I1 => L1_carry_i_14_n_0,
I2 => \msb1__1\(11),
I3 => L1_carry_i_15_n_0,
I4 => \msb1__1\(43),
O => \z[30]_INST_0_i_177_n_0\
);
\z[30]_INST_0_i_178\: unisim.vcomponents.LUT4
generic map(
INIT => X"88C0"
)
port map (
I0 => \msb1__1\(19),
I1 => L1_carry_i_15_n_0,
I2 => \msb1__1\(35),
I3 => \z[30]_INST_0_i_198_n_0\,
O => \z[30]_INST_0_i_178_n_0\
);
\z[30]_INST_0_i_179\: unisim.vcomponents.LUT5
generic map(
INIT => X"B833B800"
)
port map (
I0 => \msb1__1\(23),
I1 => L1_carry_i_14_n_0,
I2 => \msb1__1\(7),
I3 => L1_carry_i_15_n_0,
I4 => \msb1__1\(39),
O => \z[30]_INST_0_i_179_n_0\
);
\z[30]_INST_0_i_18\: unisim.vcomponents.LUT6
generic map(
INIT => X"DD0DDD0D0000DD0D"
)
port map (
I0 => \z[30]_INST_0_i_43_n_0\,
I1 => \z[30]_INST_0_i_68_n_0\,
I2 => \z[30]_INST_0_i_57_n_0\,
I3 => \z[30]_INST_0_i_70_n_0\,
I4 => L1,
I5 => \z[30]_INST_0_i_71_n_0\,
O => \z[30]_INST_0_i_18_n_0\
);
\z[30]_INST_0_i_180\: unisim.vcomponents.LUT5
generic map(
INIT => X"ACACF000"
)
port map (
I0 => \msb1__1\(15),
I1 => \msb1__1\(47),
I2 => L1_carry_i_15_n_0,
I3 => \msb1__1\(31),
I4 => \z[30]_INST_0_i_198_n_0\,
O => \z[30]_INST_0_i_180_n_0\
);
\z[30]_INST_0_i_181\: unisim.vcomponents.LUT5
generic map(
INIT => X"B833B800"
)
port map (
I0 => \msb1__1\(30),
I1 => L1_carry_i_14_n_0,
I2 => \msb1__1\(14),
I3 => L1_carry_i_15_n_0,
I4 => \msb1__1\(46),
O => \z[30]_INST_0_i_181_n_0\
);
\z[30]_INST_0_i_182\: unisim.vcomponents.LUT4
generic map(
INIT => X"88C0"
)
port map (
I0 => \msb1__1\(22),
I1 => L1_carry_i_15_n_0,
I2 => \msb1__1\(38),
I3 => \z[30]_INST_0_i_198_n_0\,
O => \z[30]_INST_0_i_182_n_0\
);
\z[30]_INST_0_i_183\: unisim.vcomponents.LUT5
generic map(
INIT => X"B833B800"
)
port map (
I0 => \msb1__1\(26),
I1 => L1_carry_i_14_n_0,
I2 => \msb1__1\(10),
I3 => L1_carry_i_15_n_0,
I4 => \msb1__1\(42),
O => \z[30]_INST_0_i_183_n_0\
);
\z[30]_INST_0_i_184\: unisim.vcomponents.LUT4
generic map(
INIT => X"88C0"
)
port map (
I0 => \msb1__1\(18),
I1 => L1_carry_i_15_n_0,
I2 => \msb1__1\(34),
I3 => \z[30]_INST_0_i_198_n_0\,
O => \z[30]_INST_0_i_184_n_0\
);
\z[30]_INST_0_i_185\: unisim.vcomponents.LUT5
generic map(
INIT => X"B833B800"
)
port map (
I0 => \msb1__1\(28),
I1 => L1_carry_i_14_n_0,
I2 => \msb1__1\(12),
I3 => L1_carry_i_15_n_0,
I4 => \msb1__1\(44),
O => \z[30]_INST_0_i_185_n_0\
);
\z[30]_INST_0_i_186\: unisim.vcomponents.LUT4
generic map(
INIT => X"B080"
)
port map (
I0 => \msb1__1\(36),
I1 => L1_carry_i_14_n_0,
I2 => L1_carry_i_15_n_0,
I3 => \msb1__1\(20),
O => \z[30]_INST_0_i_186_n_0\
);
\z[30]_INST_0_i_187\: unisim.vcomponents.LUT5
generic map(
INIT => X"B833B800"
)
port map (
I0 => \msb1__1\(24),
I1 => L1_carry_i_14_n_0,
I2 => \msb1__1\(8),
I3 => L1_carry_i_15_n_0,
I4 => \msb1__1\(40),
O => \z[30]_INST_0_i_187_n_0\
);
\z[30]_INST_0_i_188\: unisim.vcomponents.LUT4
generic map(
INIT => X"88C0"
)
port map (
I0 => \msb1__1\(16),
I1 => L1_carry_i_15_n_0,
I2 => \msb1__1\(32),
I3 => \z[30]_INST_0_i_198_n_0\,
O => \z[30]_INST_0_i_188_n_0\
);
\z[30]_INST_0_i_189\: unisim.vcomponents.LUT6
generic map(
INIT => X"BFFFFFFFBFFFBFBF"
)
port map (
I0 => \z[30]_INST_0_i_118_n_0\,
I1 => \msb1__1\(2),
I2 => \z[30]_INST_0_i_194_n_0\,
I3 => L1_carry_i_17_n_0,
I4 => L1,
I5 => \_carry_n_5\,
O => \z[30]_INST_0_i_189_n_0\
);
\z[30]_INST_0_i_19\: unisim.vcomponents.LUT6
generic map(
INIT => X"DD0DDD0D0000DD0D"
)
port map (
I0 => \z[30]_INST_0_i_57_n_0\,
I1 => \z[30]_INST_0_i_72_n_0\,
I2 => \z[30]_INST_0_i_43_n_0\,
I3 => \z[30]_INST_0_i_70_n_0\,
I4 => L1,
I5 => \z[30]_INST_0_i_73_n_0\,
O => \z[30]_INST_0_i_19_n_0\
);
\z[30]_INST_0_i_190\: unisim.vcomponents.LUT5
generic map(
INIT => X"B833B800"
)
port map (
I0 => \msb1__1\(22),
I1 => L1_carry_i_14_n_0,
I2 => \msb1__1\(6),
I3 => L1_carry_i_15_n_0,
I4 => \msb1__1\(38),
O => \z[30]_INST_0_i_190_n_0\
);
\z[30]_INST_0_i_191\: unisim.vcomponents.LUT5
generic map(
INIT => X"B833B800"
)
port map (
I0 => \msb1__1\(20),
I1 => L1_carry_i_14_n_0,
I2 => \msb1__1\(4),
I3 => L1_carry_i_15_n_0,
I4 => \msb1__1\(36),
O => \z[30]_INST_0_i_191_n_0\
);
\z[30]_INST_0_i_192\: unisim.vcomponents.LUT5
generic map(
INIT => X"B833B800"
)
port map (
I0 => \msb1__1\(21),
I1 => L1_carry_i_14_n_0,
I2 => \msb1__1\(5),
I3 => L1_carry_i_15_n_0,
I4 => \msb1__1\(37),
O => \z[30]_INST_0_i_192_n_0\
);
\z[30]_INST_0_i_193\: unisim.vcomponents.LUT5
generic map(
INIT => X"B833B800"
)
port map (
I0 => \msb1__1\(19),
I1 => L1_carry_i_14_n_0,
I2 => \msb1__1\(3),
I3 => L1_carry_i_15_n_0,
I4 => \msb1__1\(35),
O => \z[30]_INST_0_i_193_n_0\
);
\z[30]_INST_0_i_194\: unisim.vcomponents.LUT6
generic map(
INIT => X"5DA200005DA2FFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => \z[30]_INST_0_i_232_n_0\,
I3 => L1_carry_i_12_n_0,
I4 => L1,
I5 => \_carry_n_4\,
O => \z[30]_INST_0_i_194_n_0\
);
\z[30]_INST_0_i_195\: unisim.vcomponents.LUT5
generic map(
INIT => X"B833B800"
)
port map (
I0 => \msb1__1\(18),
I1 => L1_carry_i_14_n_0,
I2 => \msb1__1\(2),
I3 => L1_carry_i_15_n_0,
I4 => \msb1__1\(34),
O => \z[30]_INST_0_i_195_n_0\
);
\z[30]_INST_0_i_196\: unisim.vcomponents.LUT5
generic map(
INIT => X"B833B800"
)
port map (
I0 => \msb1__1\(16),
I1 => L1_carry_i_14_n_0,
I2 => \msb1__1\(0),
I3 => L1_carry_i_15_n_0,
I4 => \msb1__1\(32),
O => \z[30]_INST_0_i_196_n_0\
);
\z[30]_INST_0_i_197\: unisim.vcomponents.LUT5
generic map(
INIT => X"B833B800"
)
port map (
I0 => \msb1__1\(17),
I1 => L1_carry_i_14_n_0,
I2 => \msb1__1\(1),
I3 => L1_carry_i_15_n_0,
I4 => \msb1__1\(33),
O => \z[30]_INST_0_i_197_n_0\
);
\z[30]_INST_0_i_198\: unisim.vcomponents.LUT5
generic map(
INIT => X"555DAAA2"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
O => \z[30]_INST_0_i_198_n_0\
);
\z[30]_INST_0_i_199\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => \_carry__2_n_4\,
I1 => \_carry__3_n_4\,
I2 => \_carry__4_n_4\,
I3 => \_carry__5_n_5\,
I4 => \z[30]_INST_0_i_233_n_0\,
O => \z[30]_INST_0_i_199_n_0\
);
\z[30]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFB"
)
port map (
I0 => \z[30]_INST_0_i_11_n_0\,
I1 => sel0(10),
I2 => \z[30]_INST_0_i_13_n_0\,
I3 => \z[30]_INST_0_i_14_n_0\,
I4 => \z[30]_INST_0_i_15_n_0\,
I5 => \z[30]_INST_0_i_16_n_0\,
O => \z[30]_INST_0_i_2_n_0\
);
\z[30]_INST_0_i_20\: unisim.vcomponents.LUT6
generic map(
INIT => X"DD0DDD0D0000DD0D"
)
port map (
I0 => \z[30]_INST_0_i_43_n_0\,
I1 => \z[30]_INST_0_i_72_n_0\,
I2 => \z[30]_INST_0_i_57_n_0\,
I3 => \z[30]_INST_0_i_59_n_0\,
I4 => L1,
I5 => \z[30]_INST_0_i_74_n_0\,
O => \z[30]_INST_0_i_20_n_0\
);
\z[30]_INST_0_i_200\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => \_carry__1_n_4\,
I1 => \_carry__6_n_6\,
I2 => \_carry__0_n_7\,
I3 => \_carry__4_n_5\,
I4 => \z[30]_INST_0_i_234_n_0\,
O => \z[30]_INST_0_i_200_n_0\
);
\z[30]_INST_0_i_201\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => \_carry__2_n_5\,
I1 => \_carry__6_n_7\,
I2 => \_carry__0_n_4\,
I3 => \_carry__5_n_7\,
I4 => \z[30]_INST_0_i_235_n_0\,
O => \z[30]_INST_0_i_201_n_0\
);
\z[30]_INST_0_i_202\: unisim.vcomponents.LUT4
generic map(
INIT => X"B0A0"
)
port map (
I0 => \msb1__1\(41),
I1 => L1_carry_i_14_n_0,
I2 => L1_carry_i_15_n_0,
I3 => \msb1__1\(25),
O => \z[30]_INST_0_i_202_n_0\
);
\z[30]_INST_0_i_203\: unisim.vcomponents.LUT4
generic map(
INIT => X"B0A0"
)
port map (
I0 => \msb1__1\(39),
I1 => L1_carry_i_14_n_0,
I2 => L1_carry_i_15_n_0,
I3 => \msb1__1\(23),
O => \z[30]_INST_0_i_203_n_0\
);
\z[30]_INST_0_i_204\: unisim.vcomponents.LUT4
generic map(
INIT => X"B0A0"
)
port map (
I0 => \msb1__1\(42),
I1 => L1_carry_i_14_n_0,
I2 => L1_carry_i_15_n_0,
I3 => \msb1__1\(26),
O => \z[30]_INST_0_i_204_n_0\
);
\z[30]_INST_0_i_205\: unisim.vcomponents.LUT4
generic map(
INIT => X"B0A0"
)
port map (
I0 => \msb1__1\(40),
I1 => L1_carry_i_14_n_0,
I2 => L1_carry_i_15_n_0,
I3 => \msb1__1\(24),
O => \z[30]_INST_0_i_205_n_0\
);
\z[30]_INST_0_i_206\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF3FFFFFFF3FAFAF"
)
port map (
I0 => \_carry_n_5\,
I1 => L1_carry_i_17_n_0,
I2 => \msb1__1\(5),
I3 => L1_carry_i_14_n_0,
I4 => L1,
I5 => \_carry_n_4\,
O => \z[30]_INST_0_i_206_n_0\
);
\z[30]_INST_0_i_207\: unisim.vcomponents.LUT6
generic map(
INIT => X"4747FF47FFFFFF47"
)
port map (
I0 => \msb1__1\(1),
I1 => \z[30]_INST_0_i_169_n_0\,
I2 => \msb1__1\(9),
I3 => \_carry_n_4\,
I4 => L1,
I5 => \z[30]_INST_0_i_198_n_0\,
O => \z[30]_INST_0_i_207_n_0\
);
\z[30]_INST_0_i_208\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFCF44FFFFCF77"
)
port map (
I0 => \msb1__1\(7),
I1 => \z[30]_INST_0_i_118_n_0\,
I2 => \msb1__1\(3),
I3 => \z[30]_INST_0_i_169_n_0\,
I4 => \z[30]_INST_0_i_170_n_0\,
I5 => \msb1__1\(11),
O => \z[30]_INST_0_i_208_n_0\
);
\z[30]_INST_0_i_209\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF3FFFFFFF3FAFAF"
)
port map (
I0 => \_carry_n_5\,
I1 => L1_carry_i_17_n_0,
I2 => \msb1__1\(4),
I3 => L1_carry_i_14_n_0,
I4 => L1,
I5 => \_carry_n_4\,
O => \z[30]_INST_0_i_209_n_0\
);
\z[30]_INST_0_i_21\: unisim.vcomponents.LUT6
generic map(
INIT => X"101010FF10101010"
)
port map (
I0 => \z[30]_INST_0_i_75_n_0\,
I1 => \z[30]_INST_0_i_76_n_0\,
I2 => \z[30]_INST_0_i_77_n_0\,
I3 => \z[30]_INST_0_i_78_n_0\,
I4 => \z[30]_INST_0_i_79_n_0\,
I5 => \z[30]_INST_0_i_80_n_0\,
O => \z[30]_INST_0_i_21_n_0\
);
\z[30]_INST_0_i_210\: unisim.vcomponents.LUT6
generic map(
INIT => X"CF44CF77FFFFFFFF"
)
port map (
I0 => \msb1__1\(6),
I1 => \z[30]_INST_0_i_118_n_0\,
I2 => \msb1__1\(2),
I3 => \z[30]_INST_0_i_169_n_0\,
I4 => \msb1__1\(10),
I5 => \z[30]_INST_0_i_194_n_0\,
O => \z[30]_INST_0_i_210_n_0\
);
\z[30]_INST_0_i_211\: unisim.vcomponents.LUT4
generic map(
INIT => X"773F"
)
port map (
I0 => \msb1__1\(21),
I1 => L1_carry_i_15_n_0,
I2 => \msb1__1\(37),
I3 => \z[30]_INST_0_i_198_n_0\,
O => \z[30]_INST_0_i_211_n_0\
);
\z[30]_INST_0_i_212\: unisim.vcomponents.LUT4
generic map(
INIT => X"B0A0"
)
port map (
I0 => \msb1__1\(45),
I1 => L1_carry_i_14_n_0,
I2 => L1_carry_i_15_n_0,
I3 => \msb1__1\(29),
O => \z[30]_INST_0_i_212_n_0\
);
\z[30]_INST_0_i_213\: unisim.vcomponents.LUT4
generic map(
INIT => X"773F"
)
port map (
I0 => \msb1__1\(17),
I1 => L1_carry_i_15_n_0,
I2 => \msb1__1\(33),
I3 => \z[30]_INST_0_i_198_n_0\,
O => \z[30]_INST_0_i_213_n_0\
);
\z[30]_INST_0_i_214\: unisim.vcomponents.LUT4
generic map(
INIT => X"B0A0"
)
port map (
I0 => \msb1__1\(43),
I1 => L1_carry_i_14_n_0,
I2 => L1_carry_i_15_n_0,
I3 => \msb1__1\(27),
O => \z[30]_INST_0_i_214_n_0\
);
\z[30]_INST_0_i_215\: unisim.vcomponents.LUT4
generic map(
INIT => X"4F5F"
)
port map (
I0 => \msb1__1\(46),
I1 => L1_carry_i_14_n_0,
I2 => L1_carry_i_15_n_0,
I3 => \msb1__1\(30),
O => \z[30]_INST_0_i_215_n_0\
);
\z[30]_INST_0_i_216\: unisim.vcomponents.LUT4
generic map(
INIT => X"773F"
)
port map (
I0 => \msb1__1\(20),
I1 => L1_carry_i_15_n_0,
I2 => \msb1__1\(36),
I3 => \z[30]_INST_0_i_198_n_0\,
O => \z[30]_INST_0_i_216_n_0\
);
\z[30]_INST_0_i_217\: unisim.vcomponents.LUT4
generic map(
INIT => X"B0A0"
)
port map (
I0 => \msb1__1\(44),
I1 => L1_carry_i_14_n_0,
I2 => L1_carry_i_15_n_0,
I3 => \msb1__1\(28),
O => \z[30]_INST_0_i_217_n_0\
);
\z[30]_INST_0_i_218\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFF444F4FFF777F7"
)
port map (
I0 => \msb1__1\(3),
I1 => \z[30]_INST_0_i_169_n_0\,
I2 => \_carry_n_4\,
I3 => L1,
I4 => L1_carry_i_14_n_0,
I5 => \msb1__1\(11),
O => \z[30]_INST_0_i_218_n_0\
);
\z[30]_INST_0_i_219\: unisim.vcomponents.LUT6
generic map(
INIT => X"3F103F1FFFFFFFFF"
)
port map (
I0 => \msb1__1\(25),
I1 => \msb1__1\(41),
I2 => L1_carry_i_17_n_0,
I3 => L1_carry_i_14_n_0,
I4 => \msb1__1\(33),
I5 => L1_carry_i_15_n_0,
O => \z[30]_INST_0_i_219_n_0\
);
\z[30]_INST_0_i_22\: unisim.vcomponents.LUT6
generic map(
INIT => X"DD0DDD0D0000DD0D"
)
port map (
I0 => \z[30]_INST_0_i_43_n_0\,
I1 => \z[30]_INST_0_i_81_n_0\,
I2 => \z[30]_INST_0_i_57_n_0\,
I3 => \z[30]_INST_0_i_82_n_0\,
I4 => L1,
I5 => \z[30]_INST_0_i_83_n_0\,
O => \z[30]_INST_0_i_22_n_0\
);
\z[30]_INST_0_i_220\: unisim.vcomponents.LUT4
generic map(
INIT => X"3777"
)
port map (
I0 => \msb1__1\(47),
I1 => L1_carry_i_15_n_0,
I2 => \msb1__1\(31),
I3 => \z[30]_INST_0_i_198_n_0\,
O => \z[30]_INST_0_i_220_n_0\
);
\z[30]_INST_0_i_221\: unisim.vcomponents.LUT6
generic map(
INIT => X"103F1F3FFFFFFFFF"
)
port map (
I0 => \msb1__1\(26),
I1 => \msb1__1\(42),
I2 => L1_carry_i_17_n_0,
I3 => \z[30]_INST_0_i_198_n_0\,
I4 => \msb1__1\(34),
I5 => L1_carry_i_15_n_0,
O => \z[30]_INST_0_i_221_n_0\
);
\z[30]_INST_0_i_222\: unisim.vcomponents.LUT6
generic map(
INIT => X"103F1F3FFFFFFFFF"
)
port map (
I0 => \msb1__1\(24),
I1 => \msb1__1\(40),
I2 => L1_carry_i_17_n_0,
I3 => \z[30]_INST_0_i_198_n_0\,
I4 => \msb1__1\(32),
I5 => L1_carry_i_15_n_0,
O => \z[30]_INST_0_i_222_n_0\
);
\z[30]_INST_0_i_223\: unisim.vcomponents.LUT6
generic map(
INIT => X"103F1F3FFFFFFFFF"
)
port map (
I0 => \msb1__1\(27),
I1 => \msb1__1\(43),
I2 => L1_carry_i_17_n_0,
I3 => \z[30]_INST_0_i_198_n_0\,
I4 => \msb1__1\(35),
I5 => L1_carry_i_15_n_0,
O => \z[30]_INST_0_i_223_n_0\
);
\z[30]_INST_0_i_224\: unisim.vcomponents.LUT6
generic map(
INIT => X"3F103F1FFFFFFFFF"
)
port map (
I0 => \msb1__1\(29),
I1 => \msb1__1\(45),
I2 => L1_carry_i_17_n_0,
I3 => L1_carry_i_14_n_0,
I4 => \msb1__1\(37),
I5 => L1_carry_i_15_n_0,
O => \z[30]_INST_0_i_224_n_0\
);
\z[30]_INST_0_i_225\: unisim.vcomponents.LUT6
generic map(
INIT => X"3F103F1FFFFFFFFF"
)
port map (
I0 => \msb1__1\(28),
I1 => \msb1__1\(44),
I2 => L1_carry_i_17_n_0,
I3 => L1_carry_i_14_n_0,
I4 => \msb1__1\(36),
I5 => L1_carry_i_15_n_0,
O => \z[30]_INST_0_i_225_n_0\
);
\z[30]_INST_0_i_226\: unisim.vcomponents.LUT6
generic map(
INIT => X"E0E0E0E0E0EFEFEF"
)
port map (
I0 => \z[30]_INST_0_i_236_n_0\,
I1 => \z[30]_INST_0_i_237_n_0\,
I2 => L1_carry_i_17_n_0,
I3 => \msb1__1\(46),
I4 => L1_carry_i_15_n_0,
I5 => \z[30]_INST_0_i_238_n_0\,
O => \z[30]_INST_0_i_226_n_0\
);
\z[30]_INST_0_i_227\: unisim.vcomponents.LUT4
generic map(
INIT => X"E2FF"
)
port map (
I0 => \_carry_n_4\,
I1 => L1,
I2 => L1_carry_i_14_n_0,
I3 => \msb1__1\(12),
O => \z[30]_INST_0_i_227_n_0\
);
\z[30]_INST_0_i_228\: unisim.vcomponents.LUT5
generic map(
INIT => X"BFBA808A"
)
port map (
I0 => \msb1__1\(20),
I1 => \z[30]_INST_0_i_198_n_0\,
I2 => L1,
I3 => \_carry_n_4\,
I4 => \msb1__1\(4),
O => \z[30]_INST_0_i_228_n_0\
);
\z[30]_INST_0_i_229\: unisim.vcomponents.LUT6
generic map(
INIT => X"10105050101F5F5F"
)
port map (
I0 => \z[30]_INST_0_i_239_n_0\,
I1 => \msb1__1\(39),
I2 => L1_carry_i_17_n_0,
I3 => \msb1__1\(47),
I4 => L1_carry_i_15_n_0,
I5 => \z[30]_INST_0_i_240_n_0\,
O => \z[30]_INST_0_i_229_n_0\
);
\z[30]_INST_0_i_230\: unisim.vcomponents.LUT6
generic map(
INIT => X"50503030505F3F3F"
)
port map (
I0 => \z[30]_INST_0_i_241_n_0\,
I1 => \z[30]_INST_0_i_242_n_0\,
I2 => L1_carry_i_17_n_0,
I3 => \z[30]_INST_0_i_243_n_0\,
I4 => \z[30]_INST_0_i_198_n_0\,
I5 => \z[30]_INST_0_i_244_n_0\,
O => \z[30]_INST_0_i_230_n_0\
);
\z[30]_INST_0_i_231\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => L1_carry_i_15_n_0,
I1 => \msb1__1\(36),
O => \z[30]_INST_0_i_231_n_0\
);
\z[30]_INST_0_i_232\: unisim.vcomponents.LUT6
generic map(
INIT => X"AEAEAEAEFFFFFFAE"
)
port map (
I0 => L1_carry_i_11_n_0,
I1 => L1_carry_i_29_n_0,
I2 => L1_carry_i_28_n_0,
I3 => \z[30]_INST_0_i_245_n_0\,
I4 => L1_carry_i_25_n_0,
I5 => L1_carry_i_24_n_0,
O => \z[30]_INST_0_i_232_n_0\
);
\z[30]_INST_0_i_233\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \_carry__2_n_6\,
I1 => \_carry__1_n_6\,
I2 => \_carry__3_n_6\,
I3 => \_carry__1_n_7\,
O => \z[30]_INST_0_i_233_n_0\
);
\z[30]_INST_0_i_234\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \_carry__2_n_7\,
I1 => L1,
I2 => \_carry__3_n_5\,
I3 => \_carry__1_n_5\,
O => \z[30]_INST_0_i_234_n_0\
);
\z[30]_INST_0_i_235\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \_carry__5_n_4\,
I1 => \_carry__3_n_7\,
I2 => \_carry__4_n_6\,
I3 => \_carry__4_n_7\,
O => \z[30]_INST_0_i_235_n_0\
);
\z[30]_INST_0_i_236\: unisim.vcomponents.LUT6
generic map(
INIT => X"C3CC333341441111"
)
port map (
I0 => \msb1__1\(38),
I1 => L1_carry_i_12_n_0,
I2 => \z[30]_INST_0_i_232_n_0\,
I3 => \_carry_i_1_n_0\,
I4 => L1_carry_i_9_n_0,
I5 => L1_carry_i_13_n_0,
O => \z[30]_INST_0_i_236_n_0\
);
\z[30]_INST_0_i_237\: unisim.vcomponents.LUT6
generic map(
INIT => X"343344441C11CCCC"
)
port map (
I0 => \msb1__1\(22),
I1 => L1_carry_i_12_n_0,
I2 => \z[30]_INST_0_i_232_n_0\,
I3 => \_carry_i_1_n_0\,
I4 => L1_carry_i_9_n_0,
I5 => L1_carry_i_13_n_0,
O => \z[30]_INST_0_i_237_n_0\
);
\z[30]_INST_0_i_238\: unisim.vcomponents.LUT6
generic map(
INIT => X"0808880820200020"
)
port map (
I0 => \msb1__1\(30),
I1 => L1_carry_i_13_n_0,
I2 => L1_carry_i_9_n_0,
I3 => \_carry_i_1_n_0\,
I4 => \z[30]_INST_0_i_232_n_0\,
I5 => L1_carry_i_12_n_0,
O => \z[30]_INST_0_i_238_n_0\
);
\z[30]_INST_0_i_239\: unisim.vcomponents.LUT6
generic map(
INIT => X"0808880820200020"
)
port map (
I0 => \msb1__1\(23),
I1 => L1_carry_i_13_n_0,
I2 => L1_carry_i_9_n_0,
I3 => \_carry_i_1_n_0\,
I4 => \z[30]_INST_0_i_232_n_0\,
I5 => L1_carry_i_12_n_0,
O => \z[30]_INST_0_i_239_n_0\
);
\z[30]_INST_0_i_240\: unisim.vcomponents.LUT6
generic map(
INIT => X"0800888820220000"
)
port map (
I0 => \msb1__1\(31),
I1 => L1_carry_i_12_n_0,
I2 => \z[30]_INST_0_i_232_n_0\,
I3 => \_carry_i_1_n_0\,
I4 => L1_carry_i_9_n_0,
I5 => L1_carry_i_13_n_0,
O => \z[30]_INST_0_i_240_n_0\
);
\z[30]_INST_0_i_241\: unisim.vcomponents.LUT6
generic map(
INIT => X"66A6555500000000"
)
port map (
I0 => L1_carry_i_13_n_0,
I1 => L1_carry_i_9_n_0,
I2 => \_carry_i_1_n_0\,
I3 => \z[30]_INST_0_i_232_n_0\,
I4 => L1_carry_i_12_n_0,
I5 => \msb1__1\(21),
O => \z[30]_INST_0_i_241_n_0\
);
\z[30]_INST_0_i_242\: unisim.vcomponents.LUT6
generic map(
INIT => X"66A6555500000000"
)
port map (
I0 => L1_carry_i_13_n_0,
I1 => L1_carry_i_9_n_0,
I2 => \_carry_i_1_n_0\,
I3 => \z[30]_INST_0_i_232_n_0\,
I4 => L1_carry_i_12_n_0,
I5 => \msb1__1\(37),
O => \z[30]_INST_0_i_242_n_0\
);
\z[30]_INST_0_i_243\: unisim.vcomponents.LUT6
generic map(
INIT => X"66A6555500000000"
)
port map (
I0 => L1_carry_i_13_n_0,
I1 => L1_carry_i_9_n_0,
I2 => \_carry_i_1_n_0\,
I3 => \z[30]_INST_0_i_232_n_0\,
I4 => L1_carry_i_12_n_0,
I5 => \msb1__1\(29),
O => \z[30]_INST_0_i_243_n_0\
);
\z[30]_INST_0_i_244\: unisim.vcomponents.LUT6
generic map(
INIT => X"66A6555500000000"
)
port map (
I0 => L1_carry_i_13_n_0,
I1 => L1_carry_i_9_n_0,
I2 => \_carry_i_1_n_0\,
I3 => \z[30]_INST_0_i_232_n_0\,
I4 => L1_carry_i_12_n_0,
I5 => \msb1__1\(45),
O => \z[30]_INST_0_i_244_n_0\
);
\z[30]_INST_0_i_245\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFF5D5"
)
port map (
I0 => L1_carry_i_27_n_0,
I1 => \msb1__1\(32),
I2 => \z[30]_INST_0_i_246_n_0\,
I3 => \msb1__1\(33),
I4 => \msb1__1\(36),
I5 => \msb1__1\(37),
O => \z[30]_INST_0_i_245_n_0\
);
\z[30]_INST_0_i_246\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \msb1__1\(35),
I1 => \msb1__1\(34),
O => \z[30]_INST_0_i_246_n_0\
);
\z[30]_INST_0_i_29\: unisim.vcomponents.LUT6
generic map(
INIT => X"4700FFFF47004700"
)
port map (
I0 => \z[30]_INST_0_i_94_n_0\,
I1 => \z[30]_INST_0_i_95_n_0\,
I2 => \z[30]_INST_0_i_96_n_0\,
I3 => \z[30]_INST_0_i_43_n_0\,
I4 => \z[30]_INST_0_i_97_n_0\,
I5 => \z[30]_INST_0_i_57_n_0\,
O => \z[30]_INST_0_i_29_n_0\
);
\z[30]_INST_0_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => \z[30]_INST_0_i_17_n_0\,
I1 => \z[30]_INST_0_i_18_n_0\,
I2 => \z[30]_INST_0_i_19_n_0\,
I3 => \z[30]_INST_0_i_20_n_0\,
I4 => \z[30]_INST_0_i_21_n_0\,
I5 => \z[30]_INST_0_i_22_n_0\,
O => \z[30]_INST_0_i_3_n_0\
);
\z[30]_INST_0_i_30\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[30]_INST_0_i_98_n_0\,
I1 => \z[30]_INST_0_i_99_n_0\,
I2 => \_carry_i_1_n_0\,
I3 => \z[30]_INST_0_i_100_n_0\,
I4 => \_carry_i_10_n_0\,
I5 => \z[30]_INST_0_i_101_n_0\,
O => \z[30]_INST_0_i_30_n_0\
);
\z[30]_INST_0_i_31\: unisim.vcomponents.LUT4
generic map(
INIT => X"4F44"
)
port map (
I0 => \z[30]_INST_0_i_102_n_0\,
I1 => \z[30]_INST_0_i_43_n_0\,
I2 => \z[30]_INST_0_i_103_n_0\,
I3 => \z[30]_INST_0_i_57_n_0\,
O => \z[30]_INST_0_i_31_n_0\
);
\z[30]_INST_0_i_32\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[30]_INST_0_i_104_n_0\,
I1 => \z[30]_INST_0_i_105_n_0\,
I2 => \_carry_i_1_n_0\,
I3 => \z[30]_INST_0_i_99_n_0\,
I4 => \_carry_i_10_n_0\,
I5 => \z[30]_INST_0_i_106_n_0\,
O => \z[30]_INST_0_i_32_n_0\
);
\z[30]_INST_0_i_33\: unisim.vcomponents.LUT6
generic map(
INIT => X"47FF474700FF0000"
)
port map (
I0 => \z[30]_INST_0_i_107_n_0\,
I1 => \z[30]_INST_0_i_95_n_0\,
I2 => \z[30]_INST_0_i_94_n_0\,
I3 => \z[30]_INST_0_i_97_n_0\,
I4 => \z[30]_INST_0_i_43_n_0\,
I5 => \z[30]_INST_0_i_57_n_0\,
O => \z[30]_INST_0_i_33_n_0\
);
\z[30]_INST_0_i_34\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[30]_INST_0_i_101_n_0\,
I1 => \z[30]_INST_0_i_104_n_0\,
I2 => \_carry_i_1_n_0\,
I3 => \z[30]_INST_0_i_98_n_0\,
I4 => \_carry_i_10_n_0\,
I5 => \z[30]_INST_0_i_99_n_0\,
O => \z[30]_INST_0_i_34_n_0\
);
\z[30]_INST_0_i_35\: unisim.vcomponents.LUT6
generic map(
INIT => X"4700FFFF47004700"
)
port map (
I0 => \z[30]_INST_0_i_107_n_0\,
I1 => \z[30]_INST_0_i_95_n_0\,
I2 => \z[30]_INST_0_i_94_n_0\,
I3 => \z[30]_INST_0_i_43_n_0\,
I4 => \z[30]_INST_0_i_102_n_0\,
I5 => \z[30]_INST_0_i_57_n_0\,
O => \z[30]_INST_0_i_35_n_0\
);
\z[30]_INST_0_i_36\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[30]_INST_0_i_99_n_0\,
I1 => \z[30]_INST_0_i_106_n_0\,
I2 => \_carry_i_1_n_0\,
I3 => \z[30]_INST_0_i_101_n_0\,
I4 => \_carry_i_10_n_0\,
I5 => \z[30]_INST_0_i_104_n_0\,
O => \z[30]_INST_0_i_36_n_0\
);
\z[30]_INST_0_i_37\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \z[30]_INST_0_i_106_n_0\,
I1 => \_carry_i_10_n_0\,
I2 => \z[30]_INST_0_i_108_n_0\,
O => \z[30]_INST_0_i_37_n_0\
);
\z[30]_INST_0_i_38\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \z[30]_INST_0_i_104_n_0\,
I1 => \_carry_i_10_n_0\,
I2 => \z[30]_INST_0_i_105_n_0\,
O => \z[30]_INST_0_i_38_n_0\
);
\z[30]_INST_0_i_39\: unisim.vcomponents.LUT4
generic map(
INIT => X"4F44"
)
port map (
I0 => \z[30]_INST_0_i_103_n_0\,
I1 => \z[30]_INST_0_i_43_n_0\,
I2 => \z[30]_INST_0_i_109_n_0\,
I3 => \z[30]_INST_0_i_57_n_0\,
O => \z[30]_INST_0_i_39_n_0\
);
\z[30]_INST_0_i_40\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \z[30]_INST_0_i_110_n_0\,
I1 => \_carry_i_10_n_0\,
I2 => \z[30]_INST_0_i_111_n_0\,
I3 => L1_carry_i_16_n_0,
I4 => \z[30]_INST_0_i_112_n_0\,
O => \z[30]_INST_0_i_40_n_0\
);
\z[30]_INST_0_i_41\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \z[30]_INST_0_i_108_n_0\,
I1 => \_carry_i_10_n_0\,
I2 => \z[30]_INST_0_i_113_n_0\,
I3 => L1_carry_i_16_n_0,
I4 => \z[30]_INST_0_i_114_n_0\,
O => \z[30]_INST_0_i_41_n_0\
);
\z[30]_INST_0_i_42\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFD8"
)
port map (
I0 => L1,
I1 => L1_carry_i_16_n_0,
I2 => \_carry_n_6\,
I3 => \z[30]_INST_0_i_115_n_0\,
I4 => \z[30]_INST_0_i_95_n_0\,
O => \z[30]_INST_0_i_42_n_0\
);
\z[30]_INST_0_i_43\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \_carry_i_1_n_0\,
I1 => \z[30]_INST_0_i_116_n_0\,
O => \z[30]_INST_0_i_43_n_0\
);
\z[30]_INST_0_i_44\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \z[30]_INST_0_i_105_n_0\,
I1 => \_carry_i_10_n_0\,
I2 => \z[30]_INST_0_i_110_n_0\,
O => \z[30]_INST_0_i_44_n_0\
);
\z[30]_INST_0_i_45\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000040F00000404"
)
port map (
I0 => \z[30]_INST_0_i_117_n_0\,
I1 => \z[30]_INST_0_i_43_n_0\,
I2 => \z[30]_INST_0_i_95_n_0\,
I3 => \z[30]_INST_0_i_115_n_0\,
I4 => \z[30]_INST_0_i_118_n_0\,
I5 => \z[30]_INST_0_i_57_n_0\,
O => \z[30]_INST_0_i_45_n_0\
);
\z[30]_INST_0_i_46\: unisim.vcomponents.LUT5
generic map(
INIT => X"10FF1010"
)
port map (
I0 => \z[30]_INST_0_i_95_n_0\,
I1 => \z[30]_INST_0_i_119_n_0\,
I2 => \z[30]_INST_0_i_57_n_0\,
I3 => \z[30]_INST_0_i_109_n_0\,
I4 => \z[30]_INST_0_i_43_n_0\,
O => \z[30]_INST_0_i_46_n_0\
);
\z[30]_INST_0_i_47\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \z[30]_INST_0_i_120_n_0\,
I1 => \_carry_i_10_n_0\,
I2 => \z[30]_INST_0_i_121_n_0\,
O => \z[30]_INST_0_i_47_n_0\
);
\z[30]_INST_0_i_48\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \z[30]_INST_0_i_122_n_0\,
I1 => \_carry_i_10_n_0\,
I2 => \z[30]_INST_0_i_123_n_0\,
O => \z[30]_INST_0_i_48_n_0\
);
\z[30]_INST_0_i_49\: unisim.vcomponents.LUT4
generic map(
INIT => X"4F44"
)
port map (
I0 => \z[30]_INST_0_i_124_n_0\,
I1 => \z[30]_INST_0_i_43_n_0\,
I2 => \z[30]_INST_0_i_125_n_0\,
I3 => \z[30]_INST_0_i_57_n_0\,
O => \z[30]_INST_0_i_49_n_0\
);
\z[30]_INST_0_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"115F1F5F"
)
port map (
I0 => \z[30]_INST_0_i_29_n_0\,
I1 => \z[30]_INST_0_i_30_n_0\,
I2 => \z[30]_INST_0_i_31_n_0\,
I3 => L1,
I4 => \z[30]_INST_0_i_32_n_0\,
O => \z[30]_INST_0_i_5_n_0\
);
\z[30]_INST_0_i_50\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \z[30]_INST_0_i_123_n_0\,
I1 => \_carry_i_10_n_0\,
I2 => \z[30]_INST_0_i_100_n_0\,
O => \z[30]_INST_0_i_50_n_0\
);
\z[30]_INST_0_i_51\: unisim.vcomponents.LUT4
generic map(
INIT => X"4F44"
)
port map (
I0 => \z[30]_INST_0_i_125_n_0\,
I1 => \z[30]_INST_0_i_43_n_0\,
I2 => \z[30]_INST_0_i_126_n_0\,
I3 => \z[30]_INST_0_i_57_n_0\,
O => \z[30]_INST_0_i_51_n_0\
);
\z[30]_INST_0_i_52\: unisim.vcomponents.LUT4
generic map(
INIT => X"4F44"
)
port map (
I0 => \z[30]_INST_0_i_126_n_0\,
I1 => \z[30]_INST_0_i_43_n_0\,
I2 => \z[30]_INST_0_i_127_n_0\,
I3 => \z[30]_INST_0_i_57_n_0\,
O => \z[30]_INST_0_i_52_n_0\
);
\z[30]_INST_0_i_53\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[30]_INST_0_i_121_n_0\,
I1 => \z[30]_INST_0_i_98_n_0\,
I2 => \_carry_i_1_n_0\,
I3 => \z[30]_INST_0_i_123_n_0\,
I4 => \_carry_i_10_n_0\,
I5 => \z[30]_INST_0_i_100_n_0\,
O => \z[30]_INST_0_i_53_n_0\
);
\z[30]_INST_0_i_54\: unisim.vcomponents.LUT6
generic map(
INIT => X"47FF474700FF0000"
)
port map (
I0 => \z[30]_INST_0_i_94_n_0\,
I1 => \z[30]_INST_0_i_95_n_0\,
I2 => \z[30]_INST_0_i_96_n_0\,
I3 => \z[30]_INST_0_i_127_n_0\,
I4 => \z[30]_INST_0_i_43_n_0\,
I5 => \z[30]_INST_0_i_57_n_0\,
O => \z[30]_INST_0_i_54_n_0\
);
\z[30]_INST_0_i_55\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[30]_INST_0_i_100_n_0\,
I1 => \z[30]_INST_0_i_101_n_0\,
I2 => \_carry_i_1_n_0\,
I3 => \z[30]_INST_0_i_121_n_0\,
I4 => \_carry_i_10_n_0\,
I5 => \z[30]_INST_0_i_98_n_0\,
O => \z[30]_INST_0_i_55_n_0\
);
\z[30]_INST_0_i_56\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[30]_INST_0_i_128_n_0\,
I1 => \z[30]_INST_0_i_129_n_0\,
I2 => \_carry_i_1_n_0\,
I3 => \z[30]_INST_0_i_130_n_0\,
I4 => \_carry_i_10_n_0\,
I5 => \z[30]_INST_0_i_131_n_0\,
O => \z[30]_INST_0_i_56_n_0\
);
\z[30]_INST_0_i_57\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \_carry_i_1_n_0\,
I1 => \z[30]_INST_0_i_116_n_0\,
O => \z[30]_INST_0_i_57_n_0\
);
\z[30]_INST_0_i_58\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[30]_INST_0_i_132_n_0\,
I1 => \z[30]_INST_0_i_133_n_0\,
I2 => \z[30]_INST_0_i_95_n_0\,
I3 => \z[30]_INST_0_i_134_n_0\,
I4 => \z[30]_INST_0_i_118_n_0\,
I5 => \z[30]_INST_0_i_135_n_0\,
O => \z[30]_INST_0_i_58_n_0\
);
\z[30]_INST_0_i_59\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \z[30]_INST_0_i_136_n_0\,
I1 => \z[30]_INST_0_i_95_n_0\,
I2 => \z[30]_INST_0_i_137_n_0\,
O => \z[30]_INST_0_i_59_n_0\
);
\z[30]_INST_0_i_6\: unisim.vcomponents.LUT5
generic map(
INIT => X"115F1F5F"
)
port map (
I0 => \z[30]_INST_0_i_33_n_0\,
I1 => \z[30]_INST_0_i_34_n_0\,
I2 => \z[30]_INST_0_i_35_n_0\,
I3 => L1,
I4 => \z[30]_INST_0_i_36_n_0\,
O => \z[30]_INST_0_i_6_n_0\
);
\z[30]_INST_0_i_60\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \z[30]_INST_0_i_138_n_0\,
I1 => L1_carry_i_16_n_0,
I2 => \z[30]_INST_0_i_139_n_0\,
I3 => \_carry_i_10_n_0\,
I4 => \z[30]_INST_0_i_122_n_0\,
O => \z[30]_INST_0_i_60_n_0\
);
\z[30]_INST_0_i_61\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \z[30]_INST_0_i_140_n_0\,
I1 => L1_carry_i_16_n_0,
I2 => \z[30]_INST_0_i_141_n_0\,
I3 => \_carry_i_10_n_0\,
I4 => \z[30]_INST_0_i_142_n_0\,
O => \z[30]_INST_0_i_61_n_0\
);
\z[30]_INST_0_i_62\: unisim.vcomponents.LUT4
generic map(
INIT => X"4F44"
)
port map (
I0 => \z[30]_INST_0_i_58_n_0\,
I1 => \z[30]_INST_0_i_43_n_0\,
I2 => \z[30]_INST_0_i_143_n_0\,
I3 => \z[30]_INST_0_i_57_n_0\,
O => \z[30]_INST_0_i_62_n_0\
);
\z[30]_INST_0_i_63\: unisim.vcomponents.LUT4
generic map(
INIT => X"4F44"
)
port map (
I0 => \z[30]_INST_0_i_143_n_0\,
I1 => \z[30]_INST_0_i_43_n_0\,
I2 => \z[30]_INST_0_i_144_n_0\,
I3 => \z[30]_INST_0_i_57_n_0\,
O => \z[30]_INST_0_i_63_n_0\
);
\z[30]_INST_0_i_64\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[30]_INST_0_i_142_n_0\,
I1 => \z[30]_INST_0_i_120_n_0\,
I2 => \_carry_i_1_n_0\,
I3 => \z[30]_INST_0_i_145_n_0\,
I4 => \_carry_i_10_n_0\,
I5 => \z[30]_INST_0_i_122_n_0\,
O => \z[30]_INST_0_i_64_n_0\
);
\z[30]_INST_0_i_65\: unisim.vcomponents.LUT4
generic map(
INIT => X"4F44"
)
port map (
I0 => \z[30]_INST_0_i_144_n_0\,
I1 => \z[30]_INST_0_i_43_n_0\,
I2 => \z[30]_INST_0_i_124_n_0\,
I3 => \z[30]_INST_0_i_57_n_0\,
O => \z[30]_INST_0_i_65_n_0\
);
\z[30]_INST_0_i_66\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[30]_INST_0_i_122_n_0\,
I1 => \z[30]_INST_0_i_123_n_0\,
I2 => \_carry_i_1_n_0\,
I3 => \z[30]_INST_0_i_142_n_0\,
I4 => \_carry_i_10_n_0\,
I5 => \z[30]_INST_0_i_120_n_0\,
O => \z[30]_INST_0_i_66_n_0\
);
\z[30]_INST_0_i_67\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[30]_INST_0_i_146_n_0\,
I1 => \z[30]_INST_0_i_147_n_0\,
I2 => \z[30]_INST_0_i_95_n_0\,
I3 => \z[30]_INST_0_i_148_n_0\,
I4 => \z[30]_INST_0_i_118_n_0\,
I5 => \z[30]_INST_0_i_149_n_0\,
O => \z[30]_INST_0_i_67_n_0\
);
\z[30]_INST_0_i_68\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \z[30]_INST_0_i_150_n_0\,
I1 => \z[30]_INST_0_i_95_n_0\,
I2 => \z[30]_INST_0_i_151_n_0\,
O => \z[30]_INST_0_i_68_n_0\
);
\z[30]_INST_0_i_69\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[30]_INST_0_i_152_n_0\,
I1 => \z[30]_INST_0_i_153_n_0\,
I2 => \_carry_i_1_n_0\,
I3 => \z[30]_INST_0_i_154_n_0\,
I4 => \_carry_i_10_n_0\,
I5 => \z[30]_INST_0_i_155_n_0\,
O => \z[30]_INST_0_i_69_n_0\
);
\z[30]_INST_0_i_7\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFF8A80"
)
port map (
I0 => L1,
I1 => \z[30]_INST_0_i_37_n_0\,
I2 => \_carry_i_1_n_0\,
I3 => \z[30]_INST_0_i_38_n_0\,
I4 => \z[30]_INST_0_i_39_n_0\,
O => sel0(3)
);
\z[30]_INST_0_i_70\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \z[30]_INST_0_i_137_n_0\,
I1 => \z[30]_INST_0_i_95_n_0\,
I2 => \z[30]_INST_0_i_156_n_0\,
O => \z[30]_INST_0_i_70_n_0\
);
\z[30]_INST_0_i_71\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[30]_INST_0_i_155_n_0\,
I1 => \z[30]_INST_0_i_130_n_0\,
I2 => \_carry_i_1_n_0\,
I3 => \z[30]_INST_0_i_152_n_0\,
I4 => \_carry_i_10_n_0\,
I5 => \z[30]_INST_0_i_153_n_0\,
O => \z[30]_INST_0_i_71_n_0\
);
\z[30]_INST_0_i_72\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \z[30]_INST_0_i_157_n_0\,
I1 => \z[30]_INST_0_i_95_n_0\,
I2 => \z[30]_INST_0_i_150_n_0\,
O => \z[30]_INST_0_i_72_n_0\
);
\z[30]_INST_0_i_73\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[30]_INST_0_i_153_n_0\,
I1 => \z[30]_INST_0_i_128_n_0\,
I2 => \_carry_i_1_n_0\,
I3 => \z[30]_INST_0_i_155_n_0\,
I4 => \_carry_i_10_n_0\,
I5 => \z[30]_INST_0_i_130_n_0\,
O => \z[30]_INST_0_i_73_n_0\
);
\z[30]_INST_0_i_74\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[30]_INST_0_i_130_n_0\,
I1 => \z[30]_INST_0_i_131_n_0\,
I2 => \_carry_i_1_n_0\,
I3 => \z[30]_INST_0_i_153_n_0\,
I4 => \_carry_i_10_n_0\,
I5 => \z[30]_INST_0_i_128_n_0\,
O => \z[30]_INST_0_i_74_n_0\
);
\z[30]_INST_0_i_75\: unisim.vcomponents.LUT6
generic map(
INIT => X"000002A2AAAA02A2"
)
port map (
I0 => L1,
I1 => \z[30]_INST_0_i_158_n_0\,
I2 => \_carry_i_10_n_0\,
I3 => \z[30]_INST_0_i_159_n_0\,
I4 => \_carry_i_1_n_0\,
I5 => \z[30]_INST_0_i_160_n_0\,
O => \z[30]_INST_0_i_75_n_0\
);
\z[30]_INST_0_i_76\: unisim.vcomponents.LUT6
generic map(
INIT => X"4C4C4C4040404C40"
)
port map (
I0 => \z[30]_INST_0_i_161_n_0\,
I1 => \z[30]_INST_0_i_43_n_0\,
I2 => \z[30]_INST_0_i_95_n_0\,
I3 => \z[30]_INST_0_i_162_n_0\,
I4 => \z[30]_INST_0_i_118_n_0\,
I5 => \z[30]_INST_0_i_163_n_0\,
O => \z[30]_INST_0_i_76_n_0\
);
\z[30]_INST_0_i_77\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \z[30]_INST_0_i_81_n_0\,
I1 => \z[30]_INST_0_i_57_n_0\,
O => \z[30]_INST_0_i_77_n_0\
);
\z[30]_INST_0_i_78\: unisim.vcomponents.LUT6
generic map(
INIT => X"020202A2A2A202A2"
)
port map (
I0 => L1,
I1 => \z[30]_INST_0_i_164_n_0\,
I2 => \_carry_i_1_n_0\,
I3 => \z[30]_INST_0_i_155_n_0\,
I4 => \_carry_i_10_n_0\,
I5 => \z[30]_INST_0_i_154_n_0\,
O => \z[30]_INST_0_i_78_n_0\
);
\z[30]_INST_0_i_79\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \z[30]_INST_0_i_57_n_0\,
I1 => \z[30]_INST_0_i_67_n_0\,
O => \z[30]_INST_0_i_79_n_0\
);
\z[30]_INST_0_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"8A80FFFF8A808A80"
)
port map (
I0 => L1,
I1 => \z[30]_INST_0_i_40_n_0\,
I2 => \_carry_i_1_n_0\,
I3 => \z[30]_INST_0_i_41_n_0\,
I4 => \z[30]_INST_0_i_42_n_0\,
I5 => \z[30]_INST_0_i_43_n_0\,
O => sel0(0)
);
\z[30]_INST_0_i_80\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \z[30]_INST_0_i_82_n_0\,
I1 => \z[30]_INST_0_i_43_n_0\,
O => \z[30]_INST_0_i_80_n_0\
);
\z[30]_INST_0_i_81\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[30]_INST_0_i_148_n_0\,
I1 => \z[30]_INST_0_i_149_n_0\,
I2 => \z[30]_INST_0_i_95_n_0\,
I3 => \z[30]_INST_0_i_147_n_0\,
I4 => \z[30]_INST_0_i_118_n_0\,
I5 => \z[30]_INST_0_i_165_n_0\,
O => \z[30]_INST_0_i_81_n_0\
);
\z[30]_INST_0_i_82\: unisim.vcomponents.LUT6
generic map(
INIT => X"CFC05F5FCFC05050"
)
port map (
I0 => \z[30]_INST_0_i_163_n_0\,
I1 => \z[30]_INST_0_i_135_n_0\,
I2 => \z[30]_INST_0_i_95_n_0\,
I3 => \z[30]_INST_0_i_166_n_0\,
I4 => \z[30]_INST_0_i_118_n_0\,
I5 => \z[30]_INST_0_i_167_n_0\,
O => \z[30]_INST_0_i_82_n_0\
);
\z[30]_INST_0_i_83\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[30]_INST_0_i_158_n_0\,
I1 => \z[30]_INST_0_i_152_n_0\,
I2 => \_carry_i_1_n_0\,
I3 => \z[30]_INST_0_i_168_n_0\,
I4 => \_carry_i_10_n_0\,
I5 => \z[30]_INST_0_i_154_n_0\,
O => \z[30]_INST_0_i_83_n_0\
);
\z[30]_INST_0_i_9\: unisim.vcomponents.LUT5
generic map(
INIT => X"000047FF"
)
port map (
I0 => \z[30]_INST_0_i_41_n_0\,
I1 => \_carry_i_1_n_0\,
I2 => \z[30]_INST_0_i_44_n_0\,
I3 => L1,
I4 => \z[30]_INST_0_i_45_n_0\,
O => \z[30]_INST_0_i_9_n_0\
);
\z[30]_INST_0_i_94\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFF4F7"
)
port map (
I0 => \msb1__1\(1),
I1 => \z[30]_INST_0_i_118_n_0\,
I2 => \z[30]_INST_0_i_169_n_0\,
I3 => \msb1__1\(5),
I4 => \z[30]_INST_0_i_170_n_0\,
O => \z[30]_INST_0_i_94_n_0\
);
\z[30]_INST_0_i_95\: unisim.vcomponents.LUT3
generic map(
INIT => X"CA"
)
port map (
I0 => \_carry_n_7\,
I1 => \_carry_i_10_n_0\,
I2 => L1,
O => \z[30]_INST_0_i_95_n_0\
);
\z[30]_INST_0_i_96\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFF4F7"
)
port map (
I0 => \msb1__1\(3),
I1 => \z[30]_INST_0_i_118_n_0\,
I2 => \z[30]_INST_0_i_170_n_0\,
I3 => \msb1__1\(7),
I4 => \z[30]_INST_0_i_169_n_0\,
O => \z[30]_INST_0_i_96_n_0\
);
\z[30]_INST_0_i_97\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \z[30]_INST_0_i_171_n_0\,
I1 => \z[30]_INST_0_i_95_n_0\,
I2 => \z[30]_INST_0_i_172_n_0\,
O => \z[30]_INST_0_i_97_n_0\
);
\z[30]_INST_0_i_98\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[30]_INST_0_i_173_n_0\,
I1 => \z[30]_INST_0_i_174_n_0\,
I2 => L1_carry_i_16_n_0,
I3 => \z[30]_INST_0_i_175_n_0\,
I4 => L1_carry_i_17_n_0,
I5 => \z[30]_INST_0_i_176_n_0\,
O => \z[30]_INST_0_i_98_n_0\
);
\z[30]_INST_0_i_99\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[30]_INST_0_i_177_n_0\,
I1 => \z[30]_INST_0_i_178_n_0\,
I2 => L1_carry_i_16_n_0,
I3 => \z[30]_INST_0_i_179_n_0\,
I4 => L1_carry_i_17_n_0,
I5 => \z[30]_INST_0_i_180_n_0\,
O => \z[30]_INST_0_i_99_n_0\
);
\z[3]_INST_0_i_1\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \z[3]_INST_0_i_1_n_0\,
CO(2) => \z[3]_INST_0_i_1_n_1\,
CO(1) => \z[3]_INST_0_i_1_n_2\,
CO(0) => \z[3]_INST_0_i_1_n_3\,
CYINIT => '0',
DI(3 downto 1) => B"000",
DI(0) => sel0(0),
O(3 downto 0) => z_mantissa(3 downto 0),
S(3) => \z[3]_INST_0_i_2_n_0\,
S(2) => \z[3]_INST_0_i_3_n_0\,
S(1) => sel0(1),
S(0) => \z[3]_INST_0_i_5_n_0\
);
\z[3]_INST_0_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFF8A80"
)
port map (
I0 => L1,
I1 => \z[30]_INST_0_i_37_n_0\,
I2 => \_carry_i_1_n_0\,
I3 => \z[30]_INST_0_i_38_n_0\,
I4 => \z[30]_INST_0_i_39_n_0\,
O => \z[3]_INST_0_i_2_n_0\
);
\z[3]_INST_0_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFF8A80"
)
port map (
I0 => L1,
I1 => \z[30]_INST_0_i_44_n_0\,
I2 => \_carry_i_1_n_0\,
I3 => \z[30]_INST_0_i_37_n_0\,
I4 => \z[30]_INST_0_i_46_n_0\,
O => \z[3]_INST_0_i_3_n_0\
);
\z[3]_INST_0_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \z[30]_INST_0_i_9_n_0\,
O => sel0(1)
);
\z[3]_INST_0_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAAAAAAA9AA"
)
port map (
I0 => sel0(0),
I1 => \z[30]_INST_0_i_3_n_0\,
I2 => \z[3]_INST_0_i_6_n_0\,
I3 => \z[3]_INST_0_i_7_n_0\,
I4 => \z[3]_INST_0_i_8_n_0\,
I5 => \z[3]_INST_0_i_9_n_0\,
O => \z[3]_INST_0_i_5_n_0\
);
\z[3]_INST_0_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFF7"
)
port map (
I0 => sel0(0),
I1 => sel0(2),
I2 => \z[7]_INST_0_i_8_n_0\,
I3 => \z[7]_INST_0_i_6_n_0\,
O => \z[3]_INST_0_i_6_n_0\
);
\z[3]_INST_0_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"0004"
)
port map (
I0 => \z[7]_INST_0_i_9_n_0\,
I1 => sel0(10),
I2 => \z[30]_INST_0_i_11_n_0\,
I3 => \z[30]_INST_0_i_15_n_0\,
O => \z[3]_INST_0_i_7_n_0\
);
\z[3]_INST_0_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFEF"
)
port map (
I0 => \z[15]_INST_0_i_7_n_0\,
I1 => \z[15]_INST_0_i_6_n_0\,
I2 => sel0(3),
I3 => \z[7]_INST_0_i_7_n_0\,
O => \z[3]_INST_0_i_8_n_0\
);
\z[3]_INST_0_i_9\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \z[30]_INST_0_i_9_n_0\,
I1 => \z[11]_INST_0_i_6_n_0\,
I2 => \z[11]_INST_0_i_7_n_0\,
I3 => \z[30]_INST_0_i_14_n_0\,
O => \z[3]_INST_0_i_9_n_0\
);
\z[7]_INST_0_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \z[3]_INST_0_i_1_n_0\,
CO(3) => \z[7]_INST_0_i_1_n_0\,
CO(2) => \z[7]_INST_0_i_1_n_1\,
CO(1) => \z[7]_INST_0_i_1_n_2\,
CO(0) => \z[7]_INST_0_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => z_mantissa(7 downto 4),
S(3 downto 0) => sel0(7 downto 4)
);
\z[7]_INST_0_i_10\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \z[30]_INST_0_i_98_n_0\,
I1 => \_carry_i_10_n_0\,
I2 => \z[30]_INST_0_i_99_n_0\,
O => \z[7]_INST_0_i_10_n_0\
);
\z[7]_INST_0_i_11\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \z[30]_INST_0_i_101_n_0\,
I1 => \_carry_i_10_n_0\,
I2 => \z[30]_INST_0_i_104_n_0\,
O => \z[7]_INST_0_i_11_n_0\
);
\z[7]_INST_0_i_12\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \z[30]_INST_0_i_99_n_0\,
I1 => \_carry_i_10_n_0\,
I2 => \z[30]_INST_0_i_106_n_0\,
O => \z[7]_INST_0_i_12_n_0\
);
\z[7]_INST_0_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \z[7]_INST_0_i_6_n_0\,
O => sel0(7)
);
\z[7]_INST_0_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \z[7]_INST_0_i_7_n_0\,
O => sel0(6)
);
\z[7]_INST_0_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \z[7]_INST_0_i_8_n_0\,
O => sel0(5)
);
\z[7]_INST_0_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \z[7]_INST_0_i_9_n_0\,
O => sel0(4)
);
\z[7]_INST_0_i_6\: unisim.vcomponents.LUT5
generic map(
INIT => X"000047FF"
)
port map (
I0 => \z[7]_INST_0_i_10_n_0\,
I1 => \_carry_i_1_n_0\,
I2 => \z[11]_INST_0_i_9_n_0\,
I3 => L1,
I4 => \z[30]_INST_0_i_29_n_0\,
O => \z[7]_INST_0_i_6_n_0\
);
\z[7]_INST_0_i_7\: unisim.vcomponents.LUT5
generic map(
INIT => X"000047FF"
)
port map (
I0 => \z[7]_INST_0_i_11_n_0\,
I1 => \_carry_i_1_n_0\,
I2 => \z[7]_INST_0_i_10_n_0\,
I3 => L1,
I4 => \z[30]_INST_0_i_33_n_0\,
O => \z[7]_INST_0_i_7_n_0\
);
\z[7]_INST_0_i_8\: unisim.vcomponents.LUT5
generic map(
INIT => X"000047FF"
)
port map (
I0 => \z[7]_INST_0_i_12_n_0\,
I1 => \_carry_i_1_n_0\,
I2 => \z[7]_INST_0_i_11_n_0\,
I3 => L1,
I4 => \z[30]_INST_0_i_35_n_0\,
O => \z[7]_INST_0_i_8_n_0\
);
\z[7]_INST_0_i_9\: unisim.vcomponents.LUT5
generic map(
INIT => X"000047FF"
)
port map (
I0 => \z[30]_INST_0_i_38_n_0\,
I1 => \_carry_i_1_n_0\,
I2 => \z[7]_INST_0_i_12_n_0\,
I3 => L1,
I4 => \z[30]_INST_0_i_31_n_0\,
O => \z[7]_INST_0_i_9_n_0\
);
\z_exponent0__0_carry\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \z_exponent0__0_carry_n_0\,
CO(2) => \z_exponent0__0_carry_n_1\,
CO(1) => \z_exponent0__0_carry_n_2\,
CO(0) => \z_exponent0__0_carry_n_3\,
CYINIT => '1',
DI(3) => \z_exponent0__0_carry_i_1_n_0\,
DI(2) => \z_exponent0__0_carry_i_2_n_0\,
DI(1) => \z_exponent0__0_carry_i_3_n_0\,
DI(0) => '1',
O(3 downto 0) => data0(3 downto 0),
S(3) => \z_exponent0__0_carry_i_4_n_0\,
S(2) => \z_exponent0__0_carry_i_5_n_0\,
S(1) => \z_exponent0__0_carry_i_6_n_0\,
S(0) => \z_exponent0__0_carry_i_7_n_0\
);
\z_exponent0__0_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => \z_exponent0__0_carry_n_0\,
CO(3) => \NLW_z_exponent0__0_carry__0_CO_UNCONNECTED\(3),
CO(2) => \z_exponent0__0_carry__0_n_1\,
CO(1) => \z_exponent0__0_carry__0_n_2\,
CO(0) => \z_exponent0__0_carry__0_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \z_exponent0__0_carry__0_i_1_n_0\,
DI(1) => \z_exponent0__0_carry__0_i_2_n_0\,
DI(0) => \z_exponent0__0_carry__0_i_3_n_0\,
O(3 downto 0) => data0(7 downto 4),
S(3) => \z_exponent0__0_carry__0_i_4_n_0\,
S(2) => \z_exponent0__0_carry__0_i_5_n_0\,
S(1) => \z_exponent0__0_carry__0_i_6_n_0\,
S(0) => \z_exponent0__0_carry__0_i_7_n_0\
);
\z_exponent0__0_carry__0_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFA9A900"
)
port map (
I0 => L1_carry_i_13_n_0,
I1 => \z_exponent0__0_carry__0_i_8_n_0\,
I2 => L1_carry_i_12_n_0,
I3 => y(28),
I4 => x(28),
O => \z_exponent0__0_carry__0_i_1_n_0\
);
\z_exponent0__0_carry__0_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"F990"
)
port map (
I0 => L1_carry_i_12_n_0,
I1 => \z_exponent0__0_carry__0_i_8_n_0\,
I2 => y(27),
I3 => x(27),
O => \z_exponent0__0_carry__0_i_2_n_0\
);
\z_exponent0__0_carry__0_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF1E1E00"
)
port map (
I0 => L1_carry_i_10_n_0,
I1 => L1_carry_i_11_n_0,
I2 => L1_carry_i_9_n_0,
I3 => y(26),
I4 => x(26),
O => \z_exponent0__0_carry__0_i_3_n_0\
);
\z_exponent0__0_carry__0_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"6999699969999996"
)
port map (
I0 => x(30),
I1 => y(30),
I2 => x(29),
I3 => y(29),
I4 => \msb1__1\(47),
I5 => \msb1__1\(46),
O => \z_exponent0__0_carry__0_i_4_n_0\
);
\z_exponent0__0_carry__0_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"96969669"
)
port map (
I0 => \z_exponent0__0_carry__0_i_1_n_0\,
I1 => y(29),
I2 => x(29),
I3 => \msb1__1\(46),
I4 => \msb1__1\(47),
O => \z_exponent0__0_carry__0_i_5_n_0\
);
\z_exponent0__0_carry__0_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"56A9A956A95656A9"
)
port map (
I0 => L1_carry_i_13_n_0,
I1 => \z_exponent0__0_carry__0_i_8_n_0\,
I2 => L1_carry_i_12_n_0,
I3 => \z_exponent0__0_carry__0_i_2_n_0\,
I4 => y(28),
I5 => x(28),
O => \z_exponent0__0_carry__0_i_6_n_0\
);
\z_exponent0__0_carry__0_i_7\: unisim.vcomponents.LUT5
generic map(
INIT => X"69969669"
)
port map (
I0 => L1_carry_i_12_n_0,
I1 => \z_exponent0__0_carry__0_i_8_n_0\,
I2 => \z_exponent0__0_carry__0_i_3_n_0\,
I3 => x(27),
I4 => y(27),
O => \z_exponent0__0_carry__0_i_7_n_0\
);
\z_exponent0__0_carry__0_i_8\: unisim.vcomponents.LUT3
generic map(
INIT => X"01"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => L1_carry_i_10_n_0,
I2 => L1_carry_i_11_n_0,
O => \z_exponent0__0_carry__0_i_8_n_0\
);
\z_exponent0__0_carry_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"F660"
)
port map (
I0 => L1_carry_i_11_n_0,
I1 => L1_carry_i_10_n_0,
I2 => y(25),
I3 => x(25),
O => \z_exponent0__0_carry_i_1_n_0\
);
\z_exponent0__0_carry_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => y(24),
I1 => x(24),
I2 => L1_carry_i_10_n_0,
O => \z_exponent0__0_carry_i_2_n_0\
);
\z_exponent0__0_carry_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => x(23),
I1 => y(23),
I2 => \_carry_i_1_n_0\,
O => \z_exponent0__0_carry_i_3_n_0\
);
\z_exponent0__0_carry_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"E11E1EE11EE1E11E"
)
port map (
I0 => L1_carry_i_10_n_0,
I1 => L1_carry_i_11_n_0,
I2 => L1_carry_i_9_n_0,
I3 => \z_exponent0__0_carry_i_1_n_0\,
I4 => y(26),
I5 => x(26),
O => \z_exponent0__0_carry_i_4_n_0\
);
\z_exponent0__0_carry_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"96696996"
)
port map (
I0 => L1_carry_i_11_n_0,
I1 => L1_carry_i_10_n_0,
I2 => \z_exponent0__0_carry_i_2_n_0\,
I3 => y(25),
I4 => x(25),
O => \z_exponent0__0_carry_i_5_n_0\
);
\z_exponent0__0_carry_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => y(24),
I1 => L1_carry_i_10_n_0,
I2 => x(24),
I3 => \z_exponent0__0_carry_i_3_n_0\,
O => \z_exponent0__0_carry_i_6_n_0\
);
\z_exponent0__0_carry_i_7\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => x(23),
I1 => y(23),
I2 => \_carry_i_1_n_0\,
O => \z_exponent0__0_carry_i_7_n_0\
);
z_exponent1_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => z_exponent1_carry_n_0,
CO(2) => z_exponent1_carry_n_1,
CO(1) => z_exponent1_carry_n_2,
CO(0) => z_exponent1_carry_n_3,
CYINIT => '0',
DI(3) => \z_exponent0__0_carry_i_1_n_0\,
DI(2) => \z_exponent0__0_carry_i_2_n_0\,
DI(1) => \z_exponent1_carry_i_1__0_n_0\,
DI(0) => x(23),
O(3 downto 0) => data1(3 downto 0),
S(3) => \z_exponent1_carry_i_2__0_n_0\,
S(2) => \z_exponent1_carry_i_3__0_n_0\,
S(1) => z_exponent1_carry_i_4_n_0,
S(0) => z_exponent1_carry_i_5_n_0
);
\z_exponent1_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => z_exponent1_carry_n_0,
CO(3) => \NLW_z_exponent1_carry__0_CO_UNCONNECTED\(3),
CO(2) => \z_exponent1_carry__0_n_1\,
CO(1) => \z_exponent1_carry__0_n_2\,
CO(0) => \z_exponent1_carry__0_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \z_exponent0__0_carry__0_i_1_n_0\,
DI(1) => \z_exponent0__0_carry__0_i_2_n_0\,
DI(0) => \z_exponent0__0_carry__0_i_3_n_0\,
O(3 downto 0) => data1(7 downto 4),
S(3) => z_exponent1_carry_i_1_n_0,
S(2) => z_exponent1_carry_i_2_n_0,
S(1) => z_exponent1_carry_i_3_n_0,
S(0) => \z_exponent1_carry_i_4__0_n_0\
);
z_exponent1_carry_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"6999699969999996"
)
port map (
I0 => x(30),
I1 => y(30),
I2 => x(29),
I3 => y(29),
I4 => \msb1__1\(47),
I5 => \msb1__1\(46),
O => z_exponent1_carry_i_1_n_0
);
\z_exponent1_carry_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => y(23),
I1 => \_carry_i_1_n_0\,
O => \z_exponent1_carry_i_1__0_n_0\
);
z_exponent1_carry_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"96969669"
)
port map (
I0 => \z_exponent0__0_carry__0_i_1_n_0\,
I1 => y(29),
I2 => x(29),
I3 => \msb1__1\(46),
I4 => \msb1__1\(47),
O => z_exponent1_carry_i_2_n_0
);
\z_exponent1_carry_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"E11E1EE11EE1E11E"
)
port map (
I0 => L1_carry_i_10_n_0,
I1 => L1_carry_i_11_n_0,
I2 => L1_carry_i_9_n_0,
I3 => \z_exponent0__0_carry_i_1_n_0\,
I4 => y(26),
I5 => x(26),
O => \z_exponent1_carry_i_2__0_n_0\
);
z_exponent1_carry_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"56A9A956A95656A9"
)
port map (
I0 => L1_carry_i_13_n_0,
I1 => \z_exponent0__0_carry__0_i_8_n_0\,
I2 => L1_carry_i_12_n_0,
I3 => \z_exponent0__0_carry__0_i_2_n_0\,
I4 => y(28),
I5 => x(28),
O => z_exponent1_carry_i_3_n_0
);
\z_exponent1_carry_i_3__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"96696996"
)
port map (
I0 => L1_carry_i_11_n_0,
I1 => L1_carry_i_10_n_0,
I2 => y(25),
I3 => x(25),
I4 => \z_exponent0__0_carry_i_2_n_0\,
O => \z_exponent1_carry_i_3__0_n_0\
);
z_exponent1_carry_i_4: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => y(24),
I1 => x(24),
I2 => L1_carry_i_10_n_0,
I3 => \z_exponent1_carry_i_1__0_n_0\,
O => z_exponent1_carry_i_4_n_0
);
\z_exponent1_carry_i_4__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"69969669"
)
port map (
I0 => L1_carry_i_12_n_0,
I1 => \z_exponent0__0_carry__0_i_8_n_0\,
I2 => y(27),
I3 => x(27),
I4 => \z_exponent0__0_carry__0_i_3_n_0\,
O => \z_exponent1_carry_i_4__0_n_0\
);
z_exponent1_carry_i_5: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => y(23),
I1 => \_carry_i_1_n_0\,
I2 => x(23),
O => z_exponent1_carry_i_5_n_0
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity affine_block_ieee754_fp_multiplier_1_2 is
port (
x : in STD_LOGIC_VECTOR ( 31 downto 0 );
y : in STD_LOGIC_VECTOR ( 31 downto 0 );
z : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of affine_block_ieee754_fp_multiplier_1_2 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of affine_block_ieee754_fp_multiplier_1_2 : entity is "affine_block_ieee754_fp_multiplier_0_0,ieee754_fp_multiplier,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of affine_block_ieee754_fp_multiplier_1_2 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of affine_block_ieee754_fp_multiplier_1_2 : entity is "ieee754_fp_multiplier,Vivado 2016.4";
end affine_block_ieee754_fp_multiplier_1_2;
architecture STRUCTURE of affine_block_ieee754_fp_multiplier_1_2 is
signal \z[30]_INST_0_i_23_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_24_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_25_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_26_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_27_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_28_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_84_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_85_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_86_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_87_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_88_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_89_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_90_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_91_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_92_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_93_n_0\ : STD_LOGIC;
signal z_mantissa : STD_LOGIC_VECTOR ( 22 downto 0 );
begin
U0: entity work.affine_block_ieee754_fp_multiplier_1_2_ieee754_fp_multiplier
port map (
x(30 downto 0) => x(30 downto 0),
y(30 downto 0) => y(30 downto 0),
\y_11__s_port_\ => \z[30]_INST_0_i_4_n_0\,
z(7 downto 0) => z(30 downto 23),
z_mantissa(22 downto 0) => z_mantissa(22 downto 0)
);
\z[0]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => z_mantissa(0),
I1 => \z[30]_INST_0_i_4_n_0\,
O => z(0)
);
\z[10]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => z_mantissa(10),
I1 => \z[30]_INST_0_i_4_n_0\,
O => z(10)
);
\z[11]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => z_mantissa(11),
I1 => \z[30]_INST_0_i_4_n_0\,
O => z(11)
);
\z[12]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => z_mantissa(12),
I1 => \z[30]_INST_0_i_4_n_0\,
O => z(12)
);
\z[13]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => z_mantissa(13),
I1 => \z[30]_INST_0_i_4_n_0\,
O => z(13)
);
\z[14]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => z_mantissa(14),
I1 => \z[30]_INST_0_i_4_n_0\,
O => z(14)
);
\z[15]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => z_mantissa(15),
I1 => \z[30]_INST_0_i_4_n_0\,
O => z(15)
);
\z[16]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => z_mantissa(16),
I1 => \z[30]_INST_0_i_4_n_0\,
O => z(16)
);
\z[17]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => z_mantissa(17),
I1 => \z[30]_INST_0_i_4_n_0\,
O => z(17)
);
\z[18]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => z_mantissa(18),
I1 => \z[30]_INST_0_i_4_n_0\,
O => z(18)
);
\z[19]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => z_mantissa(19),
I1 => \z[30]_INST_0_i_4_n_0\,
O => z(19)
);
\z[1]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => z_mantissa(1),
I1 => \z[30]_INST_0_i_4_n_0\,
O => z(1)
);
\z[20]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => z_mantissa(20),
I1 => \z[30]_INST_0_i_4_n_0\,
O => z(20)
);
\z[21]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => z_mantissa(21),
I1 => \z[30]_INST_0_i_4_n_0\,
O => z(21)
);
\z[22]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => z_mantissa(22),
I1 => \z[30]_INST_0_i_4_n_0\,
O => z(22)
);
\z[2]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => z_mantissa(2),
I1 => \z[30]_INST_0_i_4_n_0\,
O => z(2)
);
\z[30]_INST_0_i_23\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => x(29),
I1 => x(4),
I2 => x(11),
I3 => x(13),
I4 => \z[30]_INST_0_i_84_n_0\,
O => \z[30]_INST_0_i_23_n_0\
);
\z[30]_INST_0_i_24\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => x(25),
I1 => x(20),
I2 => x(15),
I3 => x(22),
I4 => \z[30]_INST_0_i_85_n_0\,
O => \z[30]_INST_0_i_24_n_0\
);
\z[30]_INST_0_i_25\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000004"
)
port map (
I0 => \z[30]_INST_0_i_86_n_0\,
I1 => \z[30]_INST_0_i_87_n_0\,
I2 => \z[30]_INST_0_i_88_n_0\,
I3 => x(24),
I4 => x(10),
I5 => x(2),
O => \z[30]_INST_0_i_25_n_0\
);
\z[30]_INST_0_i_26\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => y(30),
I1 => y(5),
I2 => y(0),
I3 => y(1),
I4 => \z[30]_INST_0_i_89_n_0\,
O => \z[30]_INST_0_i_26_n_0\
);
\z[30]_INST_0_i_27\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => y(29),
I1 => y(18),
I2 => y(2),
I3 => y(10),
I4 => \z[30]_INST_0_i_90_n_0\,
O => \z[30]_INST_0_i_27_n_0\
);
\z[30]_INST_0_i_28\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000004"
)
port map (
I0 => \z[30]_INST_0_i_91_n_0\,
I1 => \z[30]_INST_0_i_92_n_0\,
I2 => \z[30]_INST_0_i_93_n_0\,
I3 => y(12),
I4 => y(20),
I5 => y(4),
O => \z[30]_INST_0_i_28_n_0\
);
\z[30]_INST_0_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"101010FF10101010"
)
port map (
I0 => \z[30]_INST_0_i_23_n_0\,
I1 => \z[30]_INST_0_i_24_n_0\,
I2 => \z[30]_INST_0_i_25_n_0\,
I3 => \z[30]_INST_0_i_26_n_0\,
I4 => \z[30]_INST_0_i_27_n_0\,
I5 => \z[30]_INST_0_i_28_n_0\,
O => \z[30]_INST_0_i_4_n_0\
);
\z[30]_INST_0_i_84\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => x(9),
I1 => x(3),
I2 => x(17),
I3 => x(7),
O => \z[30]_INST_0_i_84_n_0\
);
\z[30]_INST_0_i_85\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => x(18),
I1 => x(30),
I2 => x(21),
I3 => x(6),
O => \z[30]_INST_0_i_85_n_0\
);
\z[30]_INST_0_i_86\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => x(14),
I1 => x(12),
I2 => x(8),
I3 => x(27),
O => \z[30]_INST_0_i_86_n_0\
);
\z[30]_INST_0_i_87\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => x(28),
I1 => x(23),
I2 => x(19),
I3 => x(1),
O => \z[30]_INST_0_i_87_n_0\
);
\z[30]_INST_0_i_88\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => x(0),
I1 => x(26),
I2 => x(16),
I3 => x(5),
O => \z[30]_INST_0_i_88_n_0\
);
\z[30]_INST_0_i_89\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => y(14),
I1 => y(8),
I2 => y(24),
I3 => y(27),
O => \z[30]_INST_0_i_89_n_0\
);
\z[30]_INST_0_i_90\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => y(7),
I1 => y(26),
I2 => y(17),
I3 => y(6),
O => \z[30]_INST_0_i_90_n_0\
);
\z[30]_INST_0_i_91\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => y(21),
I1 => y(15),
I2 => y(22),
I3 => y(23),
O => \z[30]_INST_0_i_91_n_0\
);
\z[30]_INST_0_i_92\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => y(19),
I1 => y(28),
I2 => y(9),
I3 => y(3),
O => \z[30]_INST_0_i_92_n_0\
);
\z[30]_INST_0_i_93\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => y(16),
I1 => y(25),
I2 => y(13),
I3 => y(11),
O => \z[30]_INST_0_i_93_n_0\
);
\z[31]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => y(31),
I1 => x(31),
O => z(31)
);
\z[3]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => z_mantissa(3),
I1 => \z[30]_INST_0_i_4_n_0\,
O => z(3)
);
\z[4]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => z_mantissa(4),
I1 => \z[30]_INST_0_i_4_n_0\,
O => z(4)
);
\z[5]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => z_mantissa(5),
I1 => \z[30]_INST_0_i_4_n_0\,
O => z(5)
);
\z[6]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => z_mantissa(6),
I1 => \z[30]_INST_0_i_4_n_0\,
O => z(6)
);
\z[7]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => z_mantissa(7),
I1 => \z[30]_INST_0_i_4_n_0\,
O => z(7)
);
\z[8]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => z_mantissa(8),
I1 => \z[30]_INST_0_i_4_n_0\,
O => z(8)
);
\z[9]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => z_mantissa(9),
I1 => \z[30]_INST_0_i_4_n_0\,
O => z(9)
);
end STRUCTURE;
| mit |
SoCdesign/audiomixer | ZedBoard_Linux_Design/hw/xps_proj/pcores/globalmixer_v1_00_a/hdl/vhdl/globalmixer.vhd | 1 | 17936 | ------------------------------------------------------------------------------
-- globalmixer.vhd - entity/architecture pair
------------------------------------------------------------------------------
-- IMPORTANT:
-- DO NOT MODIFY THIS FILE EXCEPT IN THE DESIGNATED SECTIONS.
--
-- SEARCH FOR --USER TO DETERMINE WHERE CHANGES ARE ALLOWED.
--
-- TYPICALLY, THE ONLY ACCEPTABLE CHANGES INVOLVE ADDING NEW
-- PORTS AND GENERICS THAT GET PASSED THROUGH TO THE INSTANTIATION
-- OF THE USER_LOGIC ENTITY.
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: globalmixer.vhd
-- Version: 1.00.a
-- Description: Top level design, instantiates library components and user logic.
-- Date: Fri May 29 17:58:19 2015 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
use proc_common_v3_00_a.ipif_pkg.all;
library axi_lite_ipif_v1_01_a;
use axi_lite_ipif_v1_01_a.axi_lite_ipif;
library globalmixer_v1_00_a;
use globalmixer_v1_00_a.user_logic;
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_S_AXI_DATA_WIDTH -- AXI4LITE slave: Data width
-- C_S_AXI_ADDR_WIDTH -- AXI4LITE slave: Address Width
-- C_S_AXI_MIN_SIZE -- AXI4LITE slave: Min Size
-- C_USE_WSTRB -- AXI4LITE slave: Write Strobe
-- C_DPHASE_TIMEOUT -- AXI4LITE slave: Data Phase Timeout
-- C_BASEADDR -- AXI4LITE slave: base address
-- C_HIGHADDR -- AXI4LITE slave: high address
-- C_FAMILY -- FPGA Family
-- C_NUM_REG -- Number of software accessible registers
-- C_NUM_MEM -- Number of address-ranges
-- C_SLV_AWIDTH -- Slave interface address bus width
-- C_SLV_DWIDTH -- Slave interface data bus width
--
-- Definition of Ports:
-- S_AXI_ACLK -- AXI4LITE slave: Clock
-- S_AXI_ARESETN -- AXI4LITE slave: Reset
-- S_AXI_AWADDR -- AXI4LITE slave: Write address
-- S_AXI_AWVALID -- AXI4LITE slave: Write address valid
-- S_AXI_WDATA -- AXI4LITE slave: Write data
-- S_AXI_WSTRB -- AXI4LITE slave: Write strobe
-- S_AXI_WVALID -- AXI4LITE slave: Write data valid
-- S_AXI_BREADY -- AXI4LITE slave: Response ready
-- S_AXI_ARADDR -- AXI4LITE slave: Read address
-- S_AXI_ARVALID -- AXI4LITE slave: Read address valid
-- S_AXI_RREADY -- AXI4LITE slave: Read data ready
-- S_AXI_ARREADY -- AXI4LITE slave: read addres ready
-- S_AXI_RDATA -- AXI4LITE slave: Read data
-- S_AXI_RRESP -- AXI4LITE slave: Read data response
-- S_AXI_RVALID -- AXI4LITE slave: Read data valid
-- S_AXI_WREADY -- AXI4LITE slave: Write data ready
-- S_AXI_BRESP -- AXI4LITE slave: Response
-- S_AXI_BVALID -- AXI4LITE slave: Resonse valid
-- S_AXI_AWREADY -- AXI4LITE slave: Wrte address ready
------------------------------------------------------------------------------
entity globalmixer is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_S_AXI_DATA_WIDTH : integer := 32;
C_S_AXI_ADDR_WIDTH : integer := 32;
C_S_AXI_MIN_SIZE : std_logic_vector := X"000001FF";
C_USE_WSTRB : integer := 0;
C_DPHASE_TIMEOUT : integer := 8;
C_BASEADDR : std_logic_vector := X"FFFFFFFF";
C_HIGHADDR : std_logic_vector := X"00000000";
C_FAMILY : string := "virtex6";
C_NUM_REG : integer := 1;
C_NUM_MEM : integer := 1;
C_SLV_AWIDTH : integer := 32;
C_SLV_DWIDTH : integer := 32
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
CLK_48_in : in std_logic;
CLK_100M_in : in std_logic; -- get rid of this
GM_Left_in_0 : in std_logic_vector(23 downto 0);
GM_Right_in_0 : in std_logic_vector(23 downto 0);
GM_Left_in_1 : in std_logic_vector(23 downto 0);
GM_Right_in_1 : in std_logic_vector(23 downto 0);
GM_Left_in_2 : in std_logic_vector(23 downto 0);
GM_Right_in_2 : in std_logic_vector(23 downto 0);
GM_Left_in_3 : in std_logic_vector(23 downto 0);
GM_Right_in_3 : in std_logic_vector(23 downto 0);
GM_Left_out : out std_logic_vector(23 downto 0);
GM_Right_out : out std_logic_vector(23 downto 0);
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_RREADY : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_AWREADY : out std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute MAX_FANOUT : string;
attribute SIGIS : string;
attribute MAX_FANOUT of S_AXI_ACLK : signal is "10000";
attribute MAX_FANOUT of S_AXI_ARESETN : signal is "10000";
attribute SIGIS of S_AXI_ACLK : signal is "Clk";
attribute SIGIS of S_AXI_ARESETN : signal is "Rst";
end entity globalmixer;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of globalmixer is
constant USER_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH;
constant IPIF_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH;
constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0');
constant USER_SLV_BASEADDR : std_logic_vector := C_BASEADDR;
constant USER_SLV_HIGHADDR : std_logic_vector := C_HIGHADDR;
constant IPIF_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(
ZERO_ADDR_PAD & USER_SLV_BASEADDR, -- user logic slave space base address
ZERO_ADDR_PAD & USER_SLV_HIGHADDR -- user logic slave space high address
);
constant USER_SLV_NUM_REG : integer := 32;
constant USER_NUM_REG : integer := USER_SLV_NUM_REG;
constant TOTAL_IPIF_CE : integer := USER_NUM_REG;
constant IPIF_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => (USER_SLV_NUM_REG) -- number of ce for user logic slave space
);
------------------------------------------
-- Index for CS/CE
------------------------------------------
constant USER_SLV_CS_INDEX : integer := 0;
constant USER_SLV_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, USER_SLV_CS_INDEX);
constant USER_CE_INDEX : integer := USER_SLV_CE_INDEX;
------------------------------------------
-- IP Interconnect (IPIC) signal declarations
------------------------------------------
signal ipif_Bus2IP_Clk : std_logic;
signal ipif_Bus2IP_Resetn : std_logic;
signal ipif_Bus2IP_Addr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal ipif_Bus2IP_RNW : std_logic;
signal ipif_Bus2IP_BE : std_logic_vector(IPIF_SLV_DWIDTH/8-1 downto 0);
signal ipif_Bus2IP_CS : std_logic_vector((IPIF_ARD_ADDR_RANGE_ARRAY'LENGTH)/2-1 downto 0);
signal ipif_Bus2IP_RdCE : std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0);
signal ipif_Bus2IP_WrCE : std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0);
signal ipif_Bus2IP_Data : std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0);
signal ipif_IP2Bus_WrAck : std_logic;
signal ipif_IP2Bus_RdAck : std_logic;
signal ipif_IP2Bus_Error : std_logic;
signal ipif_IP2Bus_Data : std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0);
signal user_Bus2IP_RdCE : std_logic_vector(USER_NUM_REG-1 downto 0);
signal user_Bus2IP_WrCE : std_logic_vector(USER_NUM_REG-1 downto 0);
signal user_IP2Bus_Data : std_logic_vector(USER_SLV_DWIDTH-1 downto 0);
signal user_IP2Bus_RdAck : std_logic;
signal user_IP2Bus_WrAck : std_logic;
signal user_IP2Bus_Error : std_logic;
begin
------------------------------------------
-- instantiate axi_lite_ipif
------------------------------------------
AXI_LITE_IPIF_I : entity axi_lite_ipif_v1_01_a.axi_lite_ipif
generic map
(
C_S_AXI_DATA_WIDTH => IPIF_SLV_DWIDTH,
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH,
C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE,
C_USE_WSTRB => C_USE_WSTRB,
C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT,
C_ARD_ADDR_RANGE_ARRAY => IPIF_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => IPIF_ARD_NUM_CE_ARRAY,
C_FAMILY => C_FAMILY
)
port map
(
S_AXI_ACLK => S_AXI_ACLK,
S_AXI_ARESETN => S_AXI_ARESETN,
S_AXI_AWADDR => S_AXI_AWADDR,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_WDATA => S_AXI_WDATA,
S_AXI_WSTRB => S_AXI_WSTRB,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_ARADDR => S_AXI_ARADDR,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_RREADY => S_AXI_RREADY,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RDATA => S_AXI_RDATA,
S_AXI_RRESP => S_AXI_RRESP,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BRESP => S_AXI_BRESP,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_AWREADY => S_AXI_AWREADY,
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Resetn => ipif_Bus2IP_Resetn,
Bus2IP_Addr => ipif_Bus2IP_Addr,
Bus2IP_RNW => ipif_Bus2IP_RNW,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_CS => ipif_Bus2IP_CS,
Bus2IP_RdCE => ipif_Bus2IP_RdCE,
Bus2IP_WrCE => ipif_Bus2IP_WrCE,
Bus2IP_Data => ipif_Bus2IP_Data,
IP2Bus_WrAck => ipif_IP2Bus_WrAck,
IP2Bus_RdAck => ipif_IP2Bus_RdAck,
IP2Bus_Error => ipif_IP2Bus_Error,
IP2Bus_Data => ipif_IP2Bus_Data
);
------------------------------------------
-- instantiate User Logic
------------------------------------------
USER_LOGIC_I : entity globalmixer_v1_00_a.user_logic
generic map
(
-- MAP USER GENERICS BELOW THIS LINE ---------------
--USER generics mapped here
-- MAP USER GENERICS ABOVE THIS LINE ---------------
C_NUM_REG => USER_NUM_REG,
C_SLV_DWIDTH => USER_SLV_DWIDTH
)
port map
(
-- MAP USER PORTS BELOW THIS LINE ------------------
CLK_48_in => CLK_48_in,
CLK_100M_in => CLK_100M_in,
GM_Left_in_0 => GM_Left_in_0,
GM_Right_in_0 => GM_Right_in_0,
GM_Left_in_1 => GM_Left_in_1,
GM_Right_in_1 => GM_Right_in_1,
GM_Left_in_2 => GM_Left_in_2,
GM_Right_in_2 => GM_Right_in_2,
GM_Left_in_3 => GM_Left_in_3,
GM_Right_in_3 => GM_Right_in_3,
GM_Left_out => GM_Left_out,
GM_Right_out => GM_Right_out,
-- MAP USER PORTS ABOVE THIS LINE ------------------
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Resetn => ipif_Bus2IP_Resetn,
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_RdCE => user_Bus2IP_RdCE,
Bus2IP_WrCE => user_Bus2IP_WrCE,
IP2Bus_Data => user_IP2Bus_Data,
IP2Bus_RdAck => user_IP2Bus_RdAck,
IP2Bus_WrAck => user_IP2Bus_WrAck,
IP2Bus_Error => user_IP2Bus_Error
);
------------------------------------------
-- connect internal signals
------------------------------------------
ipif_IP2Bus_Data <= user_IP2Bus_Data;
ipif_IP2Bus_WrAck <= user_IP2Bus_WrAck;
ipif_IP2Bus_RdAck <= user_IP2Bus_RdAck;
ipif_IP2Bus_Error <= user_IP2Bus_Error;
user_Bus2IP_RdCE <= ipif_Bus2IP_RdCE(USER_NUM_REG-1 downto 0);
user_Bus2IP_WrCE <= ipif_Bus2IP_WrCE(USER_NUM_REG-1 downto 0);
end IMP;
| mit |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | general_ip/ieee754_fp_adder_subtractor/ieee754_fp_adder_subtractor.srcs/sources_1/new/ieee754_fp_adder_subtractor.vhd | 3 | 3203 | ----------------------------------------------------------------------------------
-- Company: Drexel University
-- Engineer: Rob Taglang
--
-- Module Name: ieee754_fp_adder_subtractor - Structural
-- Description: Adds/subtracts two IEEE-754 floating point numbers
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity ieee754_fp_adder_subtractor is
port(
x : in std_logic_vector(31 downto 0);
y : in std_logic_vector(31 downto 0);
z : out std_logic_vector(31 downto 0)
);
end ieee754_fp_adder_subtractor;
architecture Structural of ieee754_fp_adder_subtractor is
signal x_sign, y_sign, z_sign : std_logic;
signal x_exponent, y_exponent, z_exponent : std_logic_vector(7 downto 0);
signal x_mantissa, y_mantissa : std_logic_vector(24 downto 0);
signal z_mantissa : std_logic_vector(22 downto 0);
begin
x_sign <= x(31);
y_sign <= y(31);
z(31) <= z_sign;
x_exponent <= x(30 downto 23);
y_exponent <= y(30 downto 23);
z(30 downto 23) <= z_exponent;
x_mantissa(24) <= '0';
x_mantissa(23) <= '1';
x_mantissa(22 downto 0) <= x(22 downto 0);
y_mantissa(24) <= '0';
y_mantissa(23) <= '1';
y_mantissa(22 downto 0) <= y(22 downto 0);
z(22 downto 0) <= z_mantissa;
process(x_sign, y_sign, x_exponent, y_exponent, x_mantissa, y_mantissa)
variable sign : std_logic := '0';
variable large_exp, small_exp, msb : integer;
variable sum, shifted_sum : unsigned(24 downto 0);
variable large_mant, small_mant: unsigned(24 downto 0);
begin
-- determine which is of greater magnitude: x or y
if unsigned(x_exponent) > unsigned(y_exponent) then
large_exp := to_integer(unsigned(x_exponent));
small_exp := to_integer(unsigned(y_exponent));
large_mant := unsigned(x_mantissa);
small_mant := unsigned(y_mantissa);
sign := x_sign;
else
large_exp := to_integer(unsigned(y_exponent));
small_exp := to_integer(unsigned(x_exponent));
large_mant := unsigned(y_mantissa);
small_mant := unsigned(x_mantissa);
sign := y_sign;
end if;
-- shift the smaller to match the larger, add if the signs match, subtract if not
if (x_sign xor y_sign) = '0' then
sum := large_mant + (small_mant srl (large_exp - small_exp));
else
sum := large_mant - (small_mant srl (large_exp - small_exp));
end if;
msb := 0;
-- shift back the result
for i in 0 to 24 loop
if sum(i) = '1' then
msb := i;
end if;
end loop;
shifted_sum := sum sll 23 - msb;
z_mantissa <= std_logic_vector(shifted_sum(22 downto 0));
z_exponent <= std_logic_vector(to_signed(large_exp, 8) - to_signed(23 - msb, 8));
-- if the result was zero, make the sign positive
if sum = "000000000000000000000000" then
sign := '0';
end if;
z_sign <= sign;
end process;
end Structural;
| mit |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_dual_camera_test/zed_dual_camera_test.srcs/sources_1/bd/system/ipshared/347e/vga_sync.vhd | 3 | 2998 | ----------------------------------------------------------------------------------
-- Company: Drexel University
-- Engineer: Rob Taglang
--
-- Module Name: vga_sync - Behavioral
-- Description: Create a sync signal for display pixel data
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity vga_sync_reset is
generic(
-- The default values are for 640x480
H_SIZE : integer := 640;
H_FRONT_DELAY : integer := 16;
H_BACK_DELAY : integer := 48;
H_RETRACE_DELAY : integer := 96;
V_SIZE : integer := 480;
V_FRONT_DELAY : integer := 10;
V_BACK_DELAY : integer := 33;
V_RETRACE_DELAY : integer := 2
);
port(
clk : in std_logic;
rst : in std_logic;
active : out std_logic := '0';
hsync : out std_logic := '0';
vsync : out std_logic := '0';
xaddr : out std_logic_vector(9 downto 0);
yaddr : out std_logic_vector(9 downto 0)
);
end vga_sync_reset;
architecture Structural of vga_sync_reset is
-- sync counters
signal v_count_reg : std_logic_vector(9 downto 0);
signal h_count_reg : std_logic_vector(9 downto 0);
begin
-- registers
process (clk)
begin
if rising_edge(clk) then
if rst = '0' then
v_count_reg <= (others=>'0');
h_count_reg <= (others=>'0');
vsync <= '1';
hsync <= '1';
active <= '0';
else
-- Count the lines and rows
if h_count_reg = H_SIZE + H_FRONT_DELAY + H_BACK_DELAY + H_RETRACE_DELAY - 1 then
h_count_reg <= (others => '0');
if v_count_reg = V_SIZE + V_FRONT_DELAY + V_BACK_DELAY + V_RETRACE_DELAY - 1 then
v_count_reg <= (others => '0');
else
v_count_reg <= v_count_reg + 1;
end if;
else
h_count_reg <= h_count_reg + 1;
end if;
if v_count_reg < V_SIZE and h_count_reg < H_SIZE then
active <= '1';
else
active <= '0';
end if;
if h_count_reg > H_SIZE + H_FRONT_DELAY and h_count_reg <= H_SIZE + H_FRONT_DELAY + H_RETRACE_DELAY then
hsync <= '0';
else
hsync <= '1';
end if;
if v_count_reg >= V_SIZE + V_FRONT_DELAY and v_count_reg < V_SIZE + V_FRONT_DELAY + V_RETRACE_DELAY then
vsync <= '0';
else
vsync <= '1';
end if;
end if;
end if;
end process;
xaddr <= h_count_reg;
yaddr <= v_count_reg;
end Structural;
| mit |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/ov7670_fusion/ov7670_fusion.srcs/sources_1/bd/system/ip/system_ov7670_controller_0_0/system_ov7670_controller_0_0_sim_netlist.vhdl | 1 | 70932 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Wed Mar 01 09:52:04 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- C:/ZyboIP/examples/ov7670_fusion/ov7670_fusion.srcs/sources_1/bd/system/ip/system_ov7670_controller_0_0/system_ov7670_controller_0_0_sim_netlist.vhdl
-- Design : system_ov7670_controller_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z010clg400-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_ov7670_controller_0_0_i2c_sender is
port (
E : out STD_LOGIC_VECTOR ( 0 to 0 );
sioc : out STD_LOGIC;
p_0_in : out STD_LOGIC;
\busy_sr_reg[1]_0\ : out STD_LOGIC;
siod : out STD_LOGIC;
\busy_sr_reg[31]_0\ : in STD_LOGIC;
clk : in STD_LOGIC;
p_1_in : in STD_LOGIC_VECTOR ( 0 to 0 );
DOADO : in STD_LOGIC_VECTOR ( 15 downto 0 );
\busy_sr_reg[31]_1\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_ov7670_controller_0_0_i2c_sender : entity is "i2c_sender";
end system_ov7670_controller_0_0_i2c_sender;
architecture STRUCTURE of system_ov7670_controller_0_0_i2c_sender is
signal busy_sr0 : STD_LOGIC;
signal \busy_sr[0]_i_3_n_0\ : STD_LOGIC;
signal \busy_sr[0]_i_5_n_0\ : STD_LOGIC;
signal \busy_sr[10]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[11]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[12]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[13]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[14]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[15]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[16]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[17]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[18]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[19]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[1]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[20]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[21]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[22]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[23]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[24]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[25]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[26]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[27]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[28]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[29]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[2]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[30]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[31]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[31]_i_2_n_0\ : STD_LOGIC;
signal \busy_sr[3]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[4]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[5]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[6]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[7]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[8]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[9]_i_1_n_0\ : STD_LOGIC;
signal \^busy_sr_reg[1]_0\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[0]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[10]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[11]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[12]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[13]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[14]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[15]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[16]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[17]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[18]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[1]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[21]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[22]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[23]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[24]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[25]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[26]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[27]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[28]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[29]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[2]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[30]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[3]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[4]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[5]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[6]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[7]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[8]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[9]\ : STD_LOGIC;
signal \data_sr[10]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[12]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[13]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[14]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[15]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[16]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[17]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[18]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[19]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[22]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[27]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[30]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[31]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[31]_i_2_n_0\ : STD_LOGIC;
signal \data_sr[3]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[4]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[5]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[6]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[7]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[8]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[9]_i_1_n_0\ : STD_LOGIC;
signal \data_sr_reg_n_0_[10]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[11]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[12]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[13]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[14]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[15]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[16]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[17]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[18]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[19]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[1]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[20]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[21]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[22]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[23]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[24]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[25]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[26]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[27]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[28]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[29]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[2]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[30]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[31]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[3]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[4]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[5]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[6]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[7]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[8]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[9]\ : STD_LOGIC;
signal \divider_reg__0\ : STD_LOGIC_VECTOR ( 7 downto 6 );
signal \divider_reg__1\ : STD_LOGIC_VECTOR ( 5 downto 0 );
signal \^p_0_in\ : STD_LOGIC;
signal \p_0_in__0\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal p_1_in_0 : STD_LOGIC_VECTOR ( 1 downto 0 );
signal sioc_i_1_n_0 : STD_LOGIC;
signal sioc_i_2_n_0 : STD_LOGIC;
signal sioc_i_3_n_0 : STD_LOGIC;
signal sioc_i_4_n_0 : STD_LOGIC;
signal sioc_i_5_n_0 : STD_LOGIC;
signal siod_INST_0_i_1_n_0 : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \busy_sr[0]_i_4\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \busy_sr[0]_i_5\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \busy_sr[10]_i_1\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \busy_sr[11]_i_1\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \busy_sr[12]_i_1\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \busy_sr[13]_i_1\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \busy_sr[14]_i_1\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \busy_sr[15]_i_1\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \busy_sr[16]_i_1\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \busy_sr[17]_i_1\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \busy_sr[18]_i_1\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \busy_sr[19]_i_1\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \busy_sr[1]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \busy_sr[20]_i_1\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \busy_sr[21]_i_1\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \busy_sr[22]_i_1\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \busy_sr[23]_i_1\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \busy_sr[24]_i_1\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \busy_sr[25]_i_1\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \busy_sr[26]_i_1\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \busy_sr[27]_i_1\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \busy_sr[28]_i_1\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \busy_sr[29]_i_1\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \busy_sr[2]_i_1\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \busy_sr[30]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \busy_sr[31]_i_2\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \busy_sr[3]_i_1\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \busy_sr[4]_i_1\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \busy_sr[5]_i_1\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \busy_sr[6]_i_1\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \busy_sr[7]_i_1\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \busy_sr[8]_i_1\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \busy_sr[9]_i_1\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \data_sr[10]_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \data_sr[12]_i_1\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \data_sr[13]_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \data_sr[14]_i_1\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \data_sr[15]_i_1\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \data_sr[16]_i_1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \data_sr[17]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \data_sr[18]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \data_sr[19]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \data_sr[31]_i_2\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \data_sr[3]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \data_sr[4]_i_1\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \data_sr[5]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \data_sr[6]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \data_sr[7]_i_1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \data_sr[8]_i_1\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \data_sr[9]_i_1\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \divider[0]_i_1\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \divider[1]_i_1\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \divider[2]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \divider[3]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \divider[4]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \divider[6]_i_1\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \divider[7]_i_2\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of sioc_i_3 : label is "soft_lutpair4";
attribute SOFT_HLUTNM of sioc_i_4 : label is "soft_lutpair5";
attribute SOFT_HLUTNM of sioc_i_5 : label is "soft_lutpair3";
begin
\busy_sr_reg[1]_0\ <= \^busy_sr_reg[1]_0\;
p_0_in <= \^p_0_in\;
\busy_sr[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"4000FFFF40004000"
)
port map (
I0 => \busy_sr[0]_i_3_n_0\,
I1 => \divider_reg__0\(6),
I2 => \divider_reg__0\(7),
I3 => \^p_0_in\,
I4 => \^busy_sr_reg[1]_0\,
I5 => p_1_in(0),
O => busy_sr0
);
\busy_sr[0]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFFFFFFFFFF"
)
port map (
I0 => \divider_reg__1\(4),
I1 => \divider_reg__1\(2),
I2 => \divider_reg__1\(0),
I3 => \divider_reg__1\(1),
I4 => \divider_reg__1\(3),
I5 => \divider_reg__1\(5),
O => \busy_sr[0]_i_3_n_0\
);
\busy_sr[0]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => \divider_reg__1\(2),
I1 => \divider_reg__1\(3),
I2 => \divider_reg__1\(0),
I3 => \divider_reg__1\(1),
I4 => \busy_sr[0]_i_5_n_0\,
O => \^busy_sr_reg[1]_0\
);
\busy_sr[0]_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \divider_reg__1\(5),
I1 => \divider_reg__1\(4),
I2 => \divider_reg__0\(7),
I3 => \divider_reg__0\(6),
O => \busy_sr[0]_i_5_n_0\
);
\busy_sr[10]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[9]\,
I1 => \^p_0_in\,
O => \busy_sr[10]_i_1_n_0\
);
\busy_sr[11]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[10]\,
I1 => \^p_0_in\,
O => \busy_sr[11]_i_1_n_0\
);
\busy_sr[12]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[11]\,
I1 => \^p_0_in\,
O => \busy_sr[12]_i_1_n_0\
);
\busy_sr[13]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[12]\,
I1 => \^p_0_in\,
O => \busy_sr[13]_i_1_n_0\
);
\busy_sr[14]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[13]\,
I1 => \^p_0_in\,
O => \busy_sr[14]_i_1_n_0\
);
\busy_sr[15]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[14]\,
I1 => \^p_0_in\,
O => \busy_sr[15]_i_1_n_0\
);
\busy_sr[16]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[15]\,
I1 => \^p_0_in\,
O => \busy_sr[16]_i_1_n_0\
);
\busy_sr[17]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[16]\,
I1 => \^p_0_in\,
O => \busy_sr[17]_i_1_n_0\
);
\busy_sr[18]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[17]\,
I1 => \^p_0_in\,
O => \busy_sr[18]_i_1_n_0\
);
\busy_sr[19]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[18]\,
I1 => \^p_0_in\,
O => \busy_sr[19]_i_1_n_0\
);
\busy_sr[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[0]\,
I1 => \^p_0_in\,
O => \busy_sr[1]_i_1_n_0\
);
\busy_sr[20]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => p_1_in_0(0),
I1 => \^p_0_in\,
O => \busy_sr[20]_i_1_n_0\
);
\busy_sr[21]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => p_1_in_0(1),
I1 => \^p_0_in\,
O => \busy_sr[21]_i_1_n_0\
);
\busy_sr[22]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[21]\,
I1 => \^p_0_in\,
O => \busy_sr[22]_i_1_n_0\
);
\busy_sr[23]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[22]\,
I1 => \^p_0_in\,
O => \busy_sr[23]_i_1_n_0\
);
\busy_sr[24]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[23]\,
I1 => \^p_0_in\,
O => \busy_sr[24]_i_1_n_0\
);
\busy_sr[25]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[24]\,
I1 => \^p_0_in\,
O => \busy_sr[25]_i_1_n_0\
);
\busy_sr[26]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[25]\,
I1 => \^p_0_in\,
O => \busy_sr[26]_i_1_n_0\
);
\busy_sr[27]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[26]\,
I1 => \^p_0_in\,
O => \busy_sr[27]_i_1_n_0\
);
\busy_sr[28]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[27]\,
I1 => \^p_0_in\,
O => \busy_sr[28]_i_1_n_0\
);
\busy_sr[29]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[28]\,
I1 => \^p_0_in\,
O => \busy_sr[29]_i_1_n_0\
);
\busy_sr[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[1]\,
I1 => \^p_0_in\,
O => \busy_sr[2]_i_1_n_0\
);
\busy_sr[30]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[29]\,
I1 => \^p_0_in\,
O => \busy_sr[30]_i_1_n_0\
);
\busy_sr[31]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"22222222A2222222"
)
port map (
I0 => p_1_in(0),
I1 => \^busy_sr_reg[1]_0\,
I2 => \^p_0_in\,
I3 => \divider_reg__0\(7),
I4 => \divider_reg__0\(6),
I5 => \busy_sr[0]_i_3_n_0\,
O => \busy_sr[31]_i_1_n_0\
);
\busy_sr[31]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^p_0_in\,
I1 => \busy_sr_reg_n_0_[30]\,
O => \busy_sr[31]_i_2_n_0\
);
\busy_sr[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[2]\,
I1 => \^p_0_in\,
O => \busy_sr[3]_i_1_n_0\
);
\busy_sr[4]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[3]\,
I1 => \^p_0_in\,
O => \busy_sr[4]_i_1_n_0\
);
\busy_sr[5]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[4]\,
I1 => \^p_0_in\,
O => \busy_sr[5]_i_1_n_0\
);
\busy_sr[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[5]\,
I1 => \^p_0_in\,
O => \busy_sr[6]_i_1_n_0\
);
\busy_sr[7]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[6]\,
I1 => \^p_0_in\,
O => \busy_sr[7]_i_1_n_0\
);
\busy_sr[8]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[7]\,
I1 => \^p_0_in\,
O => \busy_sr[8]_i_1_n_0\
);
\busy_sr[9]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[8]\,
I1 => \^p_0_in\,
O => \busy_sr[9]_i_1_n_0\
);
\busy_sr_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => p_1_in(0),
Q => \busy_sr_reg_n_0_[0]\,
R => '0'
);
\busy_sr_reg[10]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[10]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[10]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[11]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[11]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[11]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[12]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[12]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[12]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[13]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[13]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[13]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[14]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[14]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[14]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[15]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[15]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[15]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[16]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[16]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[16]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[17]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[17]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[17]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[18]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[18]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[18]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[19]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[19]_i_1_n_0\,
Q => p_1_in_0(0),
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[1]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[1]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[1]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[20]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[20]_i_1_n_0\,
Q => p_1_in_0(1),
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[21]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[21]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[21]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[22]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[22]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[22]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[23]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[23]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[23]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[24]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[24]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[24]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[25]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[25]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[25]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[26]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[26]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[26]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[27]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[27]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[27]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[28]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[28]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[28]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[29]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[29]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[29]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[2]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[2]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[2]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[30]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[30]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[30]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[31]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[31]_i_2_n_0\,
Q => \^p_0_in\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[3]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[3]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[3]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[4]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[4]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[4]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[5]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[5]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[5]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[6]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[6]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[6]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[7]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[7]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[7]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[8]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[8]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[8]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[9]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[9]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[9]\,
S => \busy_sr[31]_i_1_n_0\
);
\data_sr[10]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[9]\,
I1 => \^p_0_in\,
I2 => DOADO(7),
O => \data_sr[10]_i_1_n_0\
);
\data_sr[12]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[11]\,
I1 => \^p_0_in\,
I2 => DOADO(8),
O => \data_sr[12]_i_1_n_0\
);
\data_sr[13]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[12]\,
I1 => \^p_0_in\,
I2 => DOADO(9),
O => \data_sr[13]_i_1_n_0\
);
\data_sr[14]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[13]\,
I1 => \^p_0_in\,
I2 => DOADO(10),
O => \data_sr[14]_i_1_n_0\
);
\data_sr[15]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[14]\,
I1 => \^p_0_in\,
I2 => DOADO(11),
O => \data_sr[15]_i_1_n_0\
);
\data_sr[16]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[15]\,
I1 => \^p_0_in\,
I2 => DOADO(12),
O => \data_sr[16]_i_1_n_0\
);
\data_sr[17]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[16]\,
I1 => \^p_0_in\,
I2 => DOADO(13),
O => \data_sr[17]_i_1_n_0\
);
\data_sr[18]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[17]\,
I1 => \^p_0_in\,
I2 => DOADO(14),
O => \data_sr[18]_i_1_n_0\
);
\data_sr[19]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[18]\,
I1 => \^p_0_in\,
I2 => DOADO(15),
O => \data_sr[19]_i_1_n_0\
);
\data_sr[22]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"CFCFCFCFAACAAAAA"
)
port map (
I0 => \data_sr_reg_n_0_[22]\,
I1 => \data_sr_reg_n_0_[21]\,
I2 => \^p_0_in\,
I3 => \data_sr[31]_i_2_n_0\,
I4 => \divider_reg__0\(7),
I5 => \busy_sr_reg[31]_0\,
O => \data_sr[22]_i_1_n_0\
);
\data_sr[27]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"CFCFCFCFAACAAAAA"
)
port map (
I0 => \data_sr_reg_n_0_[27]\,
I1 => \data_sr_reg_n_0_[26]\,
I2 => \^p_0_in\,
I3 => \data_sr[31]_i_2_n_0\,
I4 => \divider_reg__0\(7),
I5 => \busy_sr_reg[31]_0\,
O => \data_sr[27]_i_1_n_0\
);
\data_sr[30]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => p_1_in(0),
I1 => \^busy_sr_reg[1]_0\,
I2 => \^p_0_in\,
O => \data_sr[30]_i_1_n_0\
);
\data_sr[31]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"CFCFCFCFAACAAAAA"
)
port map (
I0 => \data_sr_reg_n_0_[31]\,
I1 => \data_sr_reg_n_0_[30]\,
I2 => \^p_0_in\,
I3 => \data_sr[31]_i_2_n_0\,
I4 => \divider_reg__0\(7),
I5 => \busy_sr_reg[31]_0\,
O => \data_sr[31]_i_1_n_0\
);
\data_sr[31]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \busy_sr[0]_i_3_n_0\,
I1 => \divider_reg__0\(6),
O => \data_sr[31]_i_2_n_0\
);
\data_sr[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[2]\,
I1 => \^p_0_in\,
I2 => DOADO(0),
O => \data_sr[3]_i_1_n_0\
);
\data_sr[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[3]\,
I1 => \^p_0_in\,
I2 => DOADO(1),
O => \data_sr[4]_i_1_n_0\
);
\data_sr[5]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[4]\,
I1 => \^p_0_in\,
I2 => DOADO(2),
O => \data_sr[5]_i_1_n_0\
);
\data_sr[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[5]\,
I1 => \^p_0_in\,
I2 => DOADO(3),
O => \data_sr[6]_i_1_n_0\
);
\data_sr[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[6]\,
I1 => \^p_0_in\,
I2 => DOADO(4),
O => \data_sr[7]_i_1_n_0\
);
\data_sr[8]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[7]\,
I1 => \^p_0_in\,
I2 => DOADO(5),
O => \data_sr[8]_i_1_n_0\
);
\data_sr[9]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[8]\,
I1 => \^p_0_in\,
I2 => DOADO(6),
O => \data_sr[9]_i_1_n_0\
);
\data_sr_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[10]_i_1_n_0\,
Q => \data_sr_reg_n_0_[10]\,
R => '0'
);
\data_sr_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[10]\,
Q => \data_sr_reg_n_0_[11]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[12]_i_1_n_0\,
Q => \data_sr_reg_n_0_[12]\,
R => '0'
);
\data_sr_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[13]_i_1_n_0\,
Q => \data_sr_reg_n_0_[13]\,
R => '0'
);
\data_sr_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[14]_i_1_n_0\,
Q => \data_sr_reg_n_0_[14]\,
R => '0'
);
\data_sr_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[15]_i_1_n_0\,
Q => \data_sr_reg_n_0_[15]\,
R => '0'
);
\data_sr_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[16]_i_1_n_0\,
Q => \data_sr_reg_n_0_[16]\,
R => '0'
);
\data_sr_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[17]_i_1_n_0\,
Q => \data_sr_reg_n_0_[17]\,
R => '0'
);
\data_sr_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[18]_i_1_n_0\,
Q => \data_sr_reg_n_0_[18]\,
R => '0'
);
\data_sr_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[19]_i_1_n_0\,
Q => \data_sr_reg_n_0_[19]\,
R => '0'
);
\data_sr_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \^p_0_in\,
Q => \data_sr_reg_n_0_[1]\,
R => '0'
);
\data_sr_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[19]\,
Q => \data_sr_reg_n_0_[20]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[20]\,
Q => \data_sr_reg_n_0_[21]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => \data_sr[22]_i_1_n_0\,
Q => \data_sr_reg_n_0_[22]\,
R => '0'
);
\data_sr_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[22]\,
Q => \data_sr_reg_n_0_[23]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[23]\,
Q => \data_sr_reg_n_0_[24]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[24]\,
Q => \data_sr_reg_n_0_[25]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[26]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[25]\,
Q => \data_sr_reg_n_0_[26]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => \data_sr[27]_i_1_n_0\,
Q => \data_sr_reg_n_0_[27]\,
R => '0'
);
\data_sr_reg[28]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[27]\,
Q => \data_sr_reg_n_0_[28]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[29]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[28]\,
Q => \data_sr_reg_n_0_[29]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[1]\,
Q => \data_sr_reg_n_0_[2]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[30]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[29]\,
Q => \data_sr_reg_n_0_[30]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[31]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => \data_sr[31]_i_1_n_0\,
Q => \data_sr_reg_n_0_[31]\,
R => '0'
);
\data_sr_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[3]_i_1_n_0\,
Q => \data_sr_reg_n_0_[3]\,
R => '0'
);
\data_sr_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[4]_i_1_n_0\,
Q => \data_sr_reg_n_0_[4]\,
R => '0'
);
\data_sr_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[5]_i_1_n_0\,
Q => \data_sr_reg_n_0_[5]\,
R => '0'
);
\data_sr_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[6]_i_1_n_0\,
Q => \data_sr_reg_n_0_[6]\,
R => '0'
);
\data_sr_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[7]_i_1_n_0\,
Q => \data_sr_reg_n_0_[7]\,
R => '0'
);
\data_sr_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[8]_i_1_n_0\,
Q => \data_sr_reg_n_0_[8]\,
R => '0'
);
\data_sr_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[9]_i_1_n_0\,
Q => \data_sr_reg_n_0_[9]\,
R => '0'
);
\divider[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \divider_reg__1\(0),
O => \p_0_in__0\(0)
);
\divider[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \divider_reg__1\(0),
I1 => \divider_reg__1\(1),
O => \p_0_in__0\(1)
);
\divider[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \divider_reg__1\(1),
I1 => \divider_reg__1\(0),
I2 => \divider_reg__1\(2),
O => \p_0_in__0\(2)
);
\divider[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \divider_reg__1\(2),
I1 => \divider_reg__1\(0),
I2 => \divider_reg__1\(1),
I3 => \divider_reg__1\(3),
O => \p_0_in__0\(3)
);
\divider[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \divider_reg__1\(3),
I1 => \divider_reg__1\(1),
I2 => \divider_reg__1\(0),
I3 => \divider_reg__1\(2),
I4 => \divider_reg__1\(4),
O => \p_0_in__0\(4)
);
\divider[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFF80000000"
)
port map (
I0 => \divider_reg__1\(4),
I1 => \divider_reg__1\(2),
I2 => \divider_reg__1\(0),
I3 => \divider_reg__1\(1),
I4 => \divider_reg__1\(3),
I5 => \divider_reg__1\(5),
O => \p_0_in__0\(5)
);
\divider[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \busy_sr[0]_i_3_n_0\,
I1 => \divider_reg__0\(6),
O => \p_0_in__0\(6)
);
\divider[7]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"D2"
)
port map (
I0 => \divider_reg__0\(6),
I1 => \busy_sr[0]_i_3_n_0\,
I2 => \divider_reg__0\(7),
O => \p_0_in__0\(7)
);
\divider_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => \busy_sr_reg[31]_1\(0),
D => \p_0_in__0\(0),
Q => \divider_reg__1\(0),
R => '0'
);
\divider_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \busy_sr_reg[31]_1\(0),
D => \p_0_in__0\(1),
Q => \divider_reg__1\(1),
R => '0'
);
\divider_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \busy_sr_reg[31]_1\(0),
D => \p_0_in__0\(2),
Q => \divider_reg__1\(2),
R => '0'
);
\divider_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \busy_sr_reg[31]_1\(0),
D => \p_0_in__0\(3),
Q => \divider_reg__1\(3),
R => '0'
);
\divider_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \busy_sr_reg[31]_1\(0),
D => \p_0_in__0\(4),
Q => \divider_reg__1\(4),
R => '0'
);
\divider_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \busy_sr_reg[31]_1\(0),
D => \p_0_in__0\(5),
Q => \divider_reg__1\(5),
R => '0'
);
\divider_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \busy_sr_reg[31]_1\(0),
D => \p_0_in__0\(6),
Q => \divider_reg__0\(6),
R => '0'
);
\divider_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \busy_sr_reg[31]_1\(0),
D => \p_0_in__0\(7),
Q => \divider_reg__0\(7),
R => '0'
);
sioc_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FCFCFFF8FFFFFFFF"
)
port map (
I0 => \busy_sr_reg_n_0_[0]\,
I1 => sioc_i_2_n_0,
I2 => sioc_i_3_n_0,
I3 => \busy_sr_reg_n_0_[1]\,
I4 => sioc_i_4_n_0,
I5 => \^p_0_in\,
O => sioc_i_1_n_0
);
sioc_i_2: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \divider_reg__0\(6),
I1 => \divider_reg__0\(7),
O => sioc_i_2_n_0
);
sioc_i_3: unisim.vcomponents.LUT4
generic map(
INIT => X"A222"
)
port map (
I0 => sioc_i_5_n_0,
I1 => \busy_sr_reg_n_0_[30]\,
I2 => \divider_reg__0\(6),
I3 => \^p_0_in\,
O => sioc_i_3_n_0
);
sioc_i_4: unisim.vcomponents.LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => \busy_sr_reg_n_0_[29]\,
I1 => \busy_sr_reg_n_0_[2]\,
I2 => \^p_0_in\,
I3 => \busy_sr_reg_n_0_[30]\,
O => sioc_i_4_n_0
);
sioc_i_5: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => \busy_sr_reg_n_0_[0]\,
I1 => \busy_sr_reg_n_0_[1]\,
I2 => \busy_sr_reg_n_0_[29]\,
I3 => \busy_sr_reg_n_0_[2]\,
O => sioc_i_5_n_0
);
sioc_reg: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => sioc_i_1_n_0,
Q => sioc,
R => '0'
);
siod_INST_0: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \data_sr_reg_n_0_[31]\,
I1 => siod_INST_0_i_1_n_0,
O => siod
);
siod_INST_0_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"B0BBB0BB0000B0BB"
)
port map (
I0 => \busy_sr_reg_n_0_[28]\,
I1 => \busy_sr_reg_n_0_[29]\,
I2 => p_1_in_0(0),
I3 => p_1_in_0(1),
I4 => \busy_sr_reg_n_0_[11]\,
I5 => \busy_sr_reg_n_0_[10]\,
O => siod_INST_0_i_1_n_0
);
taken_reg: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \busy_sr_reg[31]_0\,
Q => E(0),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_ov7670_controller_0_0_ov7670_registers is
port (
DOADO : out STD_LOGIC_VECTOR ( 15 downto 0 );
\divider_reg[7]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
config_finished : out STD_LOGIC;
taken_reg : out STD_LOGIC;
p_1_in : out STD_LOGIC_VECTOR ( 0 to 0 );
clk : in STD_LOGIC;
\divider_reg[2]\ : in STD_LOGIC;
p_0_in : in STD_LOGIC;
resend : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_ov7670_controller_0_0_ov7670_registers : entity is "ov7670_registers";
end system_ov7670_controller_0_0_ov7670_registers;
architecture STRUCTURE of system_ov7670_controller_0_0_ov7670_registers is
signal \^doado\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal address : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \address_reg__0\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \address_rep[0]_i_1_n_0\ : STD_LOGIC;
signal \address_rep[1]_i_1_n_0\ : STD_LOGIC;
signal \address_rep[2]_i_1_n_0\ : STD_LOGIC;
signal \address_rep[3]_i_1_n_0\ : STD_LOGIC;
signal \address_rep[4]_i_1_n_0\ : STD_LOGIC;
signal \address_rep[5]_i_1_n_0\ : STD_LOGIC;
signal \address_rep[6]_i_1_n_0\ : STD_LOGIC;
signal \address_rep[7]_i_1_n_0\ : STD_LOGIC;
signal \address_rep[7]_i_2_n_0\ : STD_LOGIC;
signal config_finished_INST_0_i_1_n_0 : STD_LOGIC;
signal config_finished_INST_0_i_2_n_0 : STD_LOGIC;
signal config_finished_INST_0_i_3_n_0 : STD_LOGIC;
signal config_finished_INST_0_i_4_n_0 : STD_LOGIC;
signal NLW_sreg_reg_DOBDO_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
signal NLW_sreg_reg_DOPADOP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_sreg_reg_DOPBDOP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of \address_reg[0]\ : label is "no";
attribute equivalent_register_removal of \address_reg[1]\ : label is "no";
attribute equivalent_register_removal of \address_reg[2]\ : label is "no";
attribute equivalent_register_removal of \address_reg[3]\ : label is "no";
attribute equivalent_register_removal of \address_reg[4]\ : label is "no";
attribute equivalent_register_removal of \address_reg[5]\ : label is "no";
attribute equivalent_register_removal of \address_reg[6]\ : label is "no";
attribute equivalent_register_removal of \address_reg[7]\ : label is "no";
attribute equivalent_register_removal of \address_reg_rep[0]\ : label is "no";
attribute equivalent_register_removal of \address_reg_rep[1]\ : label is "no";
attribute equivalent_register_removal of \address_reg_rep[2]\ : label is "no";
attribute equivalent_register_removal of \address_reg_rep[3]\ : label is "no";
attribute equivalent_register_removal of \address_reg_rep[4]\ : label is "no";
attribute equivalent_register_removal of \address_reg_rep[5]\ : label is "no";
attribute equivalent_register_removal of \address_reg_rep[6]\ : label is "no";
attribute equivalent_register_removal of \address_reg_rep[7]\ : label is "no";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \address_rep[1]_i_1\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \address_rep[2]_i_1\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \address_rep[3]_i_1\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \address_rep[4]_i_1\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \address_rep[6]_i_1\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \address_rep[7]_i_1\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \busy_sr[0]_i_2\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of config_finished_INST_0 : label is "soft_lutpair30";
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of sreg_reg : label is "INDEPENDENT";
attribute \MEM.PORTA.DATA_BIT_LAYOUT\ : string;
attribute \MEM.PORTA.DATA_BIT_LAYOUT\ of sreg_reg : label is "p0_d16";
attribute METHODOLOGY_DRC_VIOS : string;
attribute METHODOLOGY_DRC_VIOS of sreg_reg : label is "{SYNTH-6 {cell *THIS*}}";
attribute RTL_RAM_BITS : integer;
attribute RTL_RAM_BITS of sreg_reg : label is 4096;
attribute RTL_RAM_NAME : string;
attribute RTL_RAM_NAME of sreg_reg : label is "U0/Inst_ov7670_registers/sreg";
attribute bram_addr_begin : integer;
attribute bram_addr_begin of sreg_reg : label is 0;
attribute bram_addr_end : integer;
attribute bram_addr_end of sreg_reg : label is 1023;
attribute bram_slice_begin : integer;
attribute bram_slice_begin of sreg_reg : label is 0;
attribute bram_slice_end : integer;
attribute bram_slice_end of sreg_reg : label is 15;
begin
DOADO(15 downto 0) <= \^doado\(15 downto 0);
\address_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[0]_i_1_n_0\,
Q => \address_reg__0\(0),
R => resend
);
\address_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[1]_i_1_n_0\,
Q => \address_reg__0\(1),
R => resend
);
\address_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[2]_i_1_n_0\,
Q => \address_reg__0\(2),
R => resend
);
\address_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[3]_i_1_n_0\,
Q => \address_reg__0\(3),
R => resend
);
\address_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[4]_i_1_n_0\,
Q => \address_reg__0\(4),
R => resend
);
\address_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[5]_i_1_n_0\,
Q => \address_reg__0\(5),
R => resend
);
\address_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[6]_i_1_n_0\,
Q => \address_reg__0\(6),
R => resend
);
\address_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[7]_i_1_n_0\,
Q => \address_reg__0\(7),
R => resend
);
\address_reg_rep[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[0]_i_1_n_0\,
Q => address(0),
R => resend
);
\address_reg_rep[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[1]_i_1_n_0\,
Q => address(1),
R => resend
);
\address_reg_rep[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[2]_i_1_n_0\,
Q => address(2),
R => resend
);
\address_reg_rep[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[3]_i_1_n_0\,
Q => address(3),
R => resend
);
\address_reg_rep[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[4]_i_1_n_0\,
Q => address(4),
R => resend
);
\address_reg_rep[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[5]_i_1_n_0\,
Q => address(5),
R => resend
);
\address_reg_rep[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[6]_i_1_n_0\,
Q => address(6),
R => resend
);
\address_reg_rep[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[7]_i_1_n_0\,
Q => address(7),
R => resend
);
\address_rep[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \address_reg__0\(0),
O => \address_rep[0]_i_1_n_0\
);
\address_rep[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \address_reg__0\(0),
I1 => \address_reg__0\(1),
O => \address_rep[1]_i_1_n_0\
);
\address_rep[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \address_reg__0\(1),
I1 => \address_reg__0\(0),
I2 => \address_reg__0\(2),
O => \address_rep[2]_i_1_n_0\
);
\address_rep[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \address_reg__0\(2),
I1 => \address_reg__0\(0),
I2 => \address_reg__0\(1),
I3 => \address_reg__0\(3),
O => \address_rep[3]_i_1_n_0\
);
\address_rep[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \address_reg__0\(3),
I1 => \address_reg__0\(1),
I2 => \address_reg__0\(0),
I3 => \address_reg__0\(2),
I4 => \address_reg__0\(4),
O => \address_rep[4]_i_1_n_0\
);
\address_rep[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFF80000000"
)
port map (
I0 => \address_reg__0\(4),
I1 => \address_reg__0\(2),
I2 => \address_reg__0\(0),
I3 => \address_reg__0\(1),
I4 => \address_reg__0\(3),
I5 => \address_reg__0\(5),
O => \address_rep[5]_i_1_n_0\
);
\address_rep[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \address_rep[7]_i_2_n_0\,
I1 => \address_reg__0\(6),
O => \address_rep[6]_i_1_n_0\
);
\address_rep[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"D2"
)
port map (
I0 => \address_reg__0\(6),
I1 => \address_rep[7]_i_2_n_0\,
I2 => \address_reg__0\(7),
O => \address_rep[7]_i_1_n_0\
);
\address_rep[7]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFFFFFFFFFF"
)
port map (
I0 => \address_reg__0\(4),
I1 => \address_reg__0\(2),
I2 => \address_reg__0\(0),
I3 => \address_reg__0\(1),
I4 => \address_reg__0\(3),
I5 => \address_reg__0\(5),
O => \address_rep[7]_i_2_n_0\
);
\busy_sr[0]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"0000FFFE"
)
port map (
I0 => config_finished_INST_0_i_4_n_0,
I1 => config_finished_INST_0_i_3_n_0,
I2 => config_finished_INST_0_i_2_n_0,
I3 => config_finished_INST_0_i_1_n_0,
I4 => p_0_in,
O => p_1_in(0)
);
config_finished_INST_0: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => config_finished_INST_0_i_1_n_0,
I1 => config_finished_INST_0_i_2_n_0,
I2 => config_finished_INST_0_i_3_n_0,
I3 => config_finished_INST_0_i_4_n_0,
O => config_finished
);
config_finished_INST_0_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => \^doado\(5),
I1 => \^doado\(4),
I2 => \^doado\(7),
I3 => \^doado\(6),
O => config_finished_INST_0_i_1_n_0
);
config_finished_INST_0_i_2: unisim.vcomponents.LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => \^doado\(1),
I1 => \^doado\(0),
I2 => \^doado\(3),
I3 => \^doado\(2),
O => config_finished_INST_0_i_2_n_0
);
config_finished_INST_0_i_3: unisim.vcomponents.LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => \^doado\(13),
I1 => \^doado\(12),
I2 => \^doado\(15),
I3 => \^doado\(14),
O => config_finished_INST_0_i_3_n_0
);
config_finished_INST_0_i_4: unisim.vcomponents.LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => \^doado\(9),
I1 => \^doado\(8),
I2 => \^doado\(11),
I3 => \^doado\(10),
O => config_finished_INST_0_i_4_n_0
);
\divider[7]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFE0000"
)
port map (
I0 => config_finished_INST_0_i_1_n_0,
I1 => config_finished_INST_0_i_2_n_0,
I2 => config_finished_INST_0_i_3_n_0,
I3 => config_finished_INST_0_i_4_n_0,
I4 => \divider_reg[2]\,
I5 => p_0_in,
O => \divider_reg[7]\(0)
);
sreg_reg: unisim.vcomponents.RAMB18E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"53295217510C50344F4014383A04401004008C003E000C001100120412801280",
INIT_01 => X"229121021E3716020F4B0E61030A1A7B190332A41861171111003DC0581E5440",
INIT_02 => X"90008F008E008D4F74106B4A69004E204D403C78392A3871371D350B330B2907",
INIT_03 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFB80AB382B20EB10CB0849A0096009100",
INIT_04 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_05 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_06 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_07 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_08 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_09 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0A => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0B => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0C => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0D => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0E => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0F => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"00000",
INIT_B => X"00000",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 18,
READ_WIDTH_B => 0,
RSTREG_PRIORITY_A => "RSTREG",
RSTREG_PRIORITY_B => "RSTREG",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"00000",
SRVAL_B => X"00000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 18,
WRITE_WIDTH_B => 0
)
port map (
ADDRARDADDR(13 downto 12) => B"00",
ADDRARDADDR(11 downto 4) => address(7 downto 0),
ADDRARDADDR(3 downto 0) => B"0000",
ADDRBWRADDR(13 downto 0) => B"11111111111111",
CLKARDCLK => clk,
CLKBWRCLK => '0',
DIADI(15 downto 0) => B"1111111111111111",
DIBDI(15 downto 0) => B"1111111111111111",
DIPADIP(1 downto 0) => B"00",
DIPBDIP(1 downto 0) => B"11",
DOADO(15 downto 0) => \^doado\(15 downto 0),
DOBDO(15 downto 0) => NLW_sreg_reg_DOBDO_UNCONNECTED(15 downto 0),
DOPADOP(1 downto 0) => NLW_sreg_reg_DOPADOP_UNCONNECTED(1 downto 0),
DOPBDOP(1 downto 0) => NLW_sreg_reg_DOPBDOP_UNCONNECTED(1 downto 0),
ENARDEN => '1',
ENBWREN => '0',
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
WEA(1 downto 0) => B"00",
WEBWE(3 downto 0) => B"0000"
);
taken_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000055555554"
)
port map (
I0 => p_0_in,
I1 => config_finished_INST_0_i_1_n_0,
I2 => config_finished_INST_0_i_2_n_0,
I3 => config_finished_INST_0_i_3_n_0,
I4 => config_finished_INST_0_i_4_n_0,
I5 => \divider_reg[2]\,
O => taken_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_ov7670_controller_0_0_ov7670_controller is
port (
config_finished : out STD_LOGIC;
siod : out STD_LOGIC;
xclk : out STD_LOGIC;
sioc : out STD_LOGIC;
resend : in STD_LOGIC;
clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_ov7670_controller_0_0_ov7670_controller : entity is "ov7670_controller";
end system_ov7670_controller_0_0_ov7670_controller;
architecture STRUCTURE of system_ov7670_controller_0_0_ov7670_controller is
signal Inst_i2c_sender_n_3 : STD_LOGIC;
signal Inst_ov7670_registers_n_16 : STD_LOGIC;
signal Inst_ov7670_registers_n_18 : STD_LOGIC;
signal p_0_in : STD_LOGIC;
signal p_1_in : STD_LOGIC_VECTOR ( 0 to 0 );
signal sreg_reg : STD_LOGIC_VECTOR ( 15 downto 0 );
signal sys_clk_i_1_n_0 : STD_LOGIC;
signal taken : STD_LOGIC;
signal \^xclk\ : STD_LOGIC;
begin
xclk <= \^xclk\;
Inst_i2c_sender: entity work.system_ov7670_controller_0_0_i2c_sender
port map (
DOADO(15 downto 0) => sreg_reg(15 downto 0),
E(0) => taken,
\busy_sr_reg[1]_0\ => Inst_i2c_sender_n_3,
\busy_sr_reg[31]_0\ => Inst_ov7670_registers_n_18,
\busy_sr_reg[31]_1\(0) => Inst_ov7670_registers_n_16,
clk => clk,
p_0_in => p_0_in,
p_1_in(0) => p_1_in(0),
sioc => sioc,
siod => siod
);
Inst_ov7670_registers: entity work.system_ov7670_controller_0_0_ov7670_registers
port map (
DOADO(15 downto 0) => sreg_reg(15 downto 0),
E(0) => taken,
clk => clk,
config_finished => config_finished,
\divider_reg[2]\ => Inst_i2c_sender_n_3,
\divider_reg[7]\(0) => Inst_ov7670_registers_n_16,
p_0_in => p_0_in,
p_1_in(0) => p_1_in(0),
resend => resend,
taken_reg => Inst_ov7670_registers_n_18
);
sys_clk_i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^xclk\,
O => sys_clk_i_1_n_0
);
sys_clk_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => sys_clk_i_1_n_0,
Q => \^xclk\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_ov7670_controller_0_0 is
port (
clk : in STD_LOGIC;
resend : in STD_LOGIC;
config_finished : out STD_LOGIC;
sioc : out STD_LOGIC;
siod : inout STD_LOGIC;
reset : out STD_LOGIC;
pwdn : out STD_LOGIC;
xclk : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_ov7670_controller_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_ov7670_controller_0_0 : entity is "system_ov7670_controller_0_0,ov7670_controller,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_ov7670_controller_0_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_ov7670_controller_0_0 : entity is "ov7670_controller,Vivado 2016.4";
end system_ov7670_controller_0_0;
architecture STRUCTURE of system_ov7670_controller_0_0 is
signal \<const0>\ : STD_LOGIC;
signal \<const1>\ : STD_LOGIC;
begin
pwdn <= \<const0>\;
reset <= \<const1>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
U0: entity work.system_ov7670_controller_0_0_ov7670_controller
port map (
clk => clk,
config_finished => config_finished,
resend => resend,
sioc => sioc,
siod => siod,
xclk => xclk
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
end STRUCTURE;
| mit |
SoCdesign/audiomixer | ZedBoard_Linux_Design/hw/xps_proj/pcores/channel_v1_00_a/hdl/vhdl/Filter_Top_Level.vhd | 2 | 8376 | ---------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11:51:05 05/05/2015
-- Design Name:
-- Module Name: Filter_Top_Level - RTL
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Filter_Top_Level is
Port(slv_reg0 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg1 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg2 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg3 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg4 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg5 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg6 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg7 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg8 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg9 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg10 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg11 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg12 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg13 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg14 : in STD_LOGIC_VECTOR(31 downto 0);
CLK_48 : in std_logic;
RST : in std_logic;
SAMPLE_TRIG : in std_logic;
sample_trigger_en : in std_logic;
HP_SW : in std_logic;
BP_SW : in std_logic;
LP_SW : in std_logic;
AUDIO_IN_L : in std_logic_vector(23 downto 0);
AUDIO_IN_R : in std_logic_vector(23 downto 0);
AUDIO_OUT_L : out std_logic_vector(23 downto 0);
AUDIO_OUT_R : out std_logic_vector(23 downto 0);
FILTER_DONE : out std_logic
-- clk : in STD_LOGIC;
-- rst : in STD_LOGIC;
-- sample_trig : in STD_LOGIC;
-- Audio_in : in STD_LOGIC_VECTOR (23 downto 0);
-- filter_done : in STD_LOGIC;
-- Audio_out : in STD_LOGIC_VECTOR (23 downto 0)
);
end Filter_Top_Level;
architecture RTL of Filter_Top_Level is
Component IIR_Biquad_II_v3 is
Port(
Coef_b0 : std_logic_vector(31 downto 0);
Coef_b1 : std_logic_vector(31 downto 0);
Coef_b2 : std_logic_vector(31 downto 0);
Coef_a1 : std_logic_vector(31 downto 0);
Coef_a2 : std_logic_vector(31 downto 0);
clk : in STD_LOGIC;
rst : in STD_LOGIC;
sample_trig : in STD_LOGIC;
X_in : in STD_LOGIC_VECTOR(23 downto 0);
filter_done : out STD_LOGIC;
Y_out : out STD_LOGIC_VECTOR(23 downto 0)
);
end Component;
signal IIR_LP_Done_R, IIR_LP_Done_L, IIR_BP_Done_R, IIR_BP_Done_L, IIR_HP_Done_R, IIR_HP_Done_L : std_logic;
signal AUDIO_OUT_TRUNC_L, AUDIO_OUT_TRUNC_R, IIR_LP_Y_Out_R, IIR_LP_Y_Out_L, IIR_BP_Y_Out_R, IIR_BP_Y_Out_L, IIR_HP_Y_Out_R, IIR_HP_Y_Out_L : std_logic_vector(23 downto 0);
signal sample_trigger_safe : STD_LOGIC := '0';
signal val : std_logic_vector(2 downto 0);
begin
sample_trigger_safe <= SAMPLE_TRIG or (not sample_trigger_en);
val <= HP_SW & BP_SW & LP_SW;
--USER logic implementation added here
---- connect all the "filter done" with an AND gate to the user_logic top level entity.
FILTER_DONE <= IIR_LP_Done_R and IIR_LP_Done_L and IIR_BP_Done_R and IIR_BP_Done_L and IIR_HP_Done_R and IIR_HP_Done_L;
AUDIO_OUT_L <= AUDIO_OUT_TRUNC_L; -- & X"00";
AUDIO_OUT_R <= AUDIO_OUT_TRUNC_R; -- & X"00";
---this process controls each individual filter and the final output of the filter.
process (IIR_BP_Y_Out_L, IIR_BP_Y_Out_R, IIR_HP_Y_Out_L, IIR_HP_Y_Out_R, IIR_LP_Y_Out_L, IIR_LP_Y_Out_R, val)
begin
case VAL is
when "000" =>
AUDIO_OUT_TRUNC_L <= (others => '0'); --IIR_LP_Y_Out_L + IIR_BP_Y_Out_L + IIR_HP_Y_Out_L;
AUDIO_OUT_TRUNC_R <= (others => '0'); --IIR_LP_Y_Out_R + IIR_BP_Y_Out_R + IIR_HP_Y_Out_R;
when "001" =>
AUDIO_OUT_TRUNC_L <= IIR_LP_Y_Out_L;
AUDIO_OUT_TRUNC_R <= IIR_LP_Y_Out_R;
when "010" =>
AUDIO_OUT_TRUNC_L <= IIR_BP_Y_Out_L;
AUDIO_OUT_TRUNC_R <= IIR_BP_Y_Out_R;
when "011" =>
AUDIO_OUT_TRUNC_L <= IIR_LP_Y_Out_L + IIR_BP_Y_Out_L;
AUDIO_OUT_TRUNC_R <= IIR_LP_Y_Out_R + IIR_BP_Y_Out_R;
when "100" =>
AUDIO_OUT_TRUNC_L <= IIR_HP_Y_Out_L;
AUDIO_OUT_TRUNC_R <= IIR_HP_Y_Out_R;
when "101" =>
AUDIO_OUT_TRUNC_L <= IIR_LP_Y_Out_L + IIR_HP_Y_Out_L;
AUDIO_OUT_TRUNC_R <= IIR_LP_Y_Out_R + IIR_HP_Y_Out_R;
when "110" =>
AUDIO_OUT_TRUNC_L <= IIR_HP_Y_Out_L + IIR_BP_Y_Out_L;
AUDIO_OUT_TRUNC_R <= IIR_HP_Y_Out_R + IIR_BP_Y_Out_R;
when "111" =>
AUDIO_OUT_TRUNC_L <= IIR_LP_Y_Out_L + IIR_BP_Y_Out_L + IIR_HP_Y_Out_L;
AUDIO_OUT_TRUNC_R <= IIR_LP_Y_Out_R + IIR_BP_Y_Out_R + IIR_HP_Y_Out_R;
when others =>
AUDIO_OUT_TRUNC_L <= (others => '0'); --IIR_LP_Y_Out_L + IIR_BP_Y_Out_L + IIR_HP_Y_Out_L;
AUDIO_OUT_TRUNC_R <= (others => '0'); --IIR_LP_Y_Out_R + IIR_BP_Y_Out_R + IIR_HP_Y_Out_R;
end case;
end process;
IIR_LP_R : IIR_Biquad_II_v3
Port map(
Coef_b0 => slv_reg0,
Coef_b1 => slv_reg1,
Coef_b2 => slv_reg2,
Coef_a1 => slv_reg3,
Coef_a2 => slv_reg4,
clk => CLK_48,
rst => rst,
sample_trig => sample_trigger_safe, --Sample_IIR,
X_in => AUDIO_IN_R(23 downto 0),
filter_done => IIR_LP_Done_R,
Y_out => IIR_LP_Y_Out_R
);
IIR_LP_L : IIR_Biquad_II_v3
Port map(
Coef_b0 => slv_reg0,
Coef_b1 => slv_reg1,
Coef_b2 => slv_reg2,
Coef_a1 => slv_reg3,
Coef_a2 => slv_reg4,
clk => CLK_48,
rst => rst,
sample_trig => sample_trigger_safe, --Sample_IIR,
X_in => AUDIO_IN_L(23 downto 0), --X_in_truncated_L,
filter_done => IIR_LP_Done_L,
Y_out => IIR_LP_Y_Out_L
);
IIR_BP_R : IIR_Biquad_II_v3 --(20 - 20000)
Port map(
Coef_b0 => slv_reg5,
Coef_b1 => slv_reg6,
Coef_b2 => slv_reg7,
Coef_a1 => slv_reg8,
Coef_a2 => slv_reg9,
clk => CLK_48,
rst => rst,
sample_trig => sample_trigger_safe, --Sample_IIR,
X_in => AUDIO_IN_R(23 downto 0), --X_in_truncated_R,
filter_done => IIR_BP_Done_R,
Y_out => IIR_BP_Y_Out_R
);
IIR_BP_L : IIR_Biquad_II_v3 --(20 - 20000)
Port map(
Coef_b0 => slv_reg5,
Coef_b1 => slv_reg6,
Coef_b2 => slv_reg7,
Coef_a1 => slv_reg8,
Coef_a2 => slv_reg9,
clk => CLK_48,
rst => rst,
sample_trig => sample_trigger_safe, --Sample_IIR,
X_in => AUDIO_IN_L(23 downto 0), --X_in_truncated_L,
filter_done => IIR_BP_Done_L,
Y_out => IIR_BP_Y_Out_L
);
IIR_HP_R : IIR_Biquad_II_v3
Port map(
Coef_b0 => slv_reg10,
Coef_b1 => slv_reg11,
Coef_b2 => slv_reg12,
Coef_a1 => slv_reg13,
Coef_a2 => slv_reg14,
clk => CLK_48,
rst => rst,
sample_trig => sample_trigger_safe, --Sample_IIR,
X_in => AUDIO_IN_R(23 downto 0), --X_in_truncated_R,
filter_done => IIR_HP_Done_R,
Y_out => IIR_HP_Y_Out_R
);
IIR_HP_L : IIR_Biquad_II_v3
Port map(
Coef_b0 => slv_reg10,
Coef_b1 => slv_reg11,
Coef_b2 => slv_reg12,
Coef_a1 => slv_reg13,
Coef_a2 => slv_reg14,
clk => CLK_48,
rst => rst,
sample_trig => sample_trigger_safe, --Sample_IIR,
X_in => AUDIO_IN_L(23 downto 0), --X_in_truncated_L,
filter_done => IIR_HP_Done_L,
Y_out => IIR_HP_Y_Out_L
);
end RTL;
| mit |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_dual_camera_test/zed_dual_camera_test.srcs/sources_1/bd/system/ip/system_ov7670_controller_0_0/system_ov7670_controller_0_0_sim_netlist.vhdl | 2 | 70017 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Sun May 21 18:13:28 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim -rename_top system_ov7670_controller_0_0 -prefix
-- system_ov7670_controller_0_0_ system_ov7670_controller_0_0_sim_netlist.vhdl
-- Design : system_ov7670_controller_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_ov7670_controller_0_0_i2c_sender is
port (
E : out STD_LOGIC_VECTOR ( 0 to 0 );
sioc : out STD_LOGIC;
p_0_in : out STD_LOGIC;
\busy_sr_reg[1]_0\ : out STD_LOGIC;
siod : out STD_LOGIC;
\busy_sr_reg[31]_0\ : in STD_LOGIC;
clk : in STD_LOGIC;
p_1_in : in STD_LOGIC_VECTOR ( 0 to 0 );
DOADO : in STD_LOGIC_VECTOR ( 15 downto 0 );
\busy_sr_reg[31]_1\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end system_ov7670_controller_0_0_i2c_sender;
architecture STRUCTURE of system_ov7670_controller_0_0_i2c_sender is
signal busy_sr0 : STD_LOGIC;
signal \busy_sr[0]_i_3_n_0\ : STD_LOGIC;
signal \busy_sr[0]_i_5_n_0\ : STD_LOGIC;
signal \busy_sr[10]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[11]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[12]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[13]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[14]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[15]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[16]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[17]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[18]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[19]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[1]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[20]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[21]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[22]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[23]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[24]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[25]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[26]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[27]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[28]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[29]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[2]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[30]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[31]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[31]_i_2_n_0\ : STD_LOGIC;
signal \busy_sr[3]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[4]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[5]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[6]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[7]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[8]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[9]_i_1_n_0\ : STD_LOGIC;
signal \^busy_sr_reg[1]_0\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[0]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[10]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[11]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[12]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[13]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[14]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[15]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[16]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[17]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[18]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[1]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[21]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[22]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[23]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[24]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[25]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[26]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[27]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[28]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[29]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[2]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[30]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[3]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[4]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[5]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[6]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[7]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[8]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[9]\ : STD_LOGIC;
signal \data_sr[10]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[12]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[13]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[14]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[15]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[16]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[17]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[18]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[19]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[22]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[27]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[30]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[31]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[31]_i_2_n_0\ : STD_LOGIC;
signal \data_sr[3]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[4]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[5]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[6]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[7]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[8]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[9]_i_1_n_0\ : STD_LOGIC;
signal \data_sr_reg_n_0_[10]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[11]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[12]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[13]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[14]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[15]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[16]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[17]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[18]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[19]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[1]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[20]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[21]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[22]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[23]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[24]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[25]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[26]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[27]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[28]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[29]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[2]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[30]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[31]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[3]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[4]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[5]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[6]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[7]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[8]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[9]\ : STD_LOGIC;
signal \divider_reg__0\ : STD_LOGIC_VECTOR ( 7 downto 6 );
signal \divider_reg__1\ : STD_LOGIC_VECTOR ( 5 downto 0 );
signal \^p_0_in\ : STD_LOGIC;
signal \p_0_in__0\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal p_1_in_0 : STD_LOGIC_VECTOR ( 1 downto 0 );
signal sioc_i_1_n_0 : STD_LOGIC;
signal sioc_i_2_n_0 : STD_LOGIC;
signal sioc_i_3_n_0 : STD_LOGIC;
signal sioc_i_4_n_0 : STD_LOGIC;
signal sioc_i_5_n_0 : STD_LOGIC;
signal siod_INST_0_i_1_n_0 : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \busy_sr[0]_i_4\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \busy_sr[0]_i_5\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \busy_sr[10]_i_1\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \busy_sr[11]_i_1\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \busy_sr[12]_i_1\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \busy_sr[13]_i_1\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \busy_sr[14]_i_1\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \busy_sr[15]_i_1\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \busy_sr[16]_i_1\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \busy_sr[17]_i_1\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \busy_sr[18]_i_1\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \busy_sr[19]_i_1\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \busy_sr[1]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \busy_sr[20]_i_1\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \busy_sr[21]_i_1\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \busy_sr[22]_i_1\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \busy_sr[23]_i_1\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \busy_sr[24]_i_1\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \busy_sr[25]_i_1\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \busy_sr[26]_i_1\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \busy_sr[27]_i_1\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \busy_sr[28]_i_1\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \busy_sr[29]_i_1\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \busy_sr[2]_i_1\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \busy_sr[30]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \busy_sr[31]_i_2\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \busy_sr[3]_i_1\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \busy_sr[4]_i_1\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \busy_sr[5]_i_1\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \busy_sr[6]_i_1\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \busy_sr[7]_i_1\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \busy_sr[8]_i_1\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \busy_sr[9]_i_1\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \data_sr[10]_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \data_sr[12]_i_1\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \data_sr[13]_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \data_sr[14]_i_1\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \data_sr[15]_i_1\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \data_sr[16]_i_1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \data_sr[17]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \data_sr[18]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \data_sr[19]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \data_sr[31]_i_2\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \data_sr[3]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \data_sr[4]_i_1\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \data_sr[5]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \data_sr[6]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \data_sr[7]_i_1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \data_sr[8]_i_1\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \data_sr[9]_i_1\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \divider[0]_i_1\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \divider[1]_i_1\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \divider[2]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \divider[3]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \divider[4]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \divider[6]_i_1\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \divider[7]_i_2\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of sioc_i_3 : label is "soft_lutpair4";
attribute SOFT_HLUTNM of sioc_i_4 : label is "soft_lutpair5";
attribute SOFT_HLUTNM of sioc_i_5 : label is "soft_lutpair3";
begin
\busy_sr_reg[1]_0\ <= \^busy_sr_reg[1]_0\;
p_0_in <= \^p_0_in\;
\busy_sr[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"4000FFFF40004000"
)
port map (
I0 => \busy_sr[0]_i_3_n_0\,
I1 => \divider_reg__0\(6),
I2 => \divider_reg__0\(7),
I3 => \^p_0_in\,
I4 => \^busy_sr_reg[1]_0\,
I5 => p_1_in(0),
O => busy_sr0
);
\busy_sr[0]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFFFFFFFFFF"
)
port map (
I0 => \divider_reg__1\(4),
I1 => \divider_reg__1\(2),
I2 => \divider_reg__1\(0),
I3 => \divider_reg__1\(1),
I4 => \divider_reg__1\(3),
I5 => \divider_reg__1\(5),
O => \busy_sr[0]_i_3_n_0\
);
\busy_sr[0]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => \divider_reg__1\(2),
I1 => \divider_reg__1\(3),
I2 => \divider_reg__1\(0),
I3 => \divider_reg__1\(1),
I4 => \busy_sr[0]_i_5_n_0\,
O => \^busy_sr_reg[1]_0\
);
\busy_sr[0]_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \divider_reg__1\(5),
I1 => \divider_reg__1\(4),
I2 => \divider_reg__0\(7),
I3 => \divider_reg__0\(6),
O => \busy_sr[0]_i_5_n_0\
);
\busy_sr[10]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[9]\,
I1 => \^p_0_in\,
O => \busy_sr[10]_i_1_n_0\
);
\busy_sr[11]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[10]\,
I1 => \^p_0_in\,
O => \busy_sr[11]_i_1_n_0\
);
\busy_sr[12]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[11]\,
I1 => \^p_0_in\,
O => \busy_sr[12]_i_1_n_0\
);
\busy_sr[13]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[12]\,
I1 => \^p_0_in\,
O => \busy_sr[13]_i_1_n_0\
);
\busy_sr[14]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[13]\,
I1 => \^p_0_in\,
O => \busy_sr[14]_i_1_n_0\
);
\busy_sr[15]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[14]\,
I1 => \^p_0_in\,
O => \busy_sr[15]_i_1_n_0\
);
\busy_sr[16]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[15]\,
I1 => \^p_0_in\,
O => \busy_sr[16]_i_1_n_0\
);
\busy_sr[17]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[16]\,
I1 => \^p_0_in\,
O => \busy_sr[17]_i_1_n_0\
);
\busy_sr[18]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[17]\,
I1 => \^p_0_in\,
O => \busy_sr[18]_i_1_n_0\
);
\busy_sr[19]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[18]\,
I1 => \^p_0_in\,
O => \busy_sr[19]_i_1_n_0\
);
\busy_sr[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[0]\,
I1 => \^p_0_in\,
O => \busy_sr[1]_i_1_n_0\
);
\busy_sr[20]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => p_1_in_0(0),
I1 => \^p_0_in\,
O => \busy_sr[20]_i_1_n_0\
);
\busy_sr[21]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => p_1_in_0(1),
I1 => \^p_0_in\,
O => \busy_sr[21]_i_1_n_0\
);
\busy_sr[22]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[21]\,
I1 => \^p_0_in\,
O => \busy_sr[22]_i_1_n_0\
);
\busy_sr[23]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[22]\,
I1 => \^p_0_in\,
O => \busy_sr[23]_i_1_n_0\
);
\busy_sr[24]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[23]\,
I1 => \^p_0_in\,
O => \busy_sr[24]_i_1_n_0\
);
\busy_sr[25]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[24]\,
I1 => \^p_0_in\,
O => \busy_sr[25]_i_1_n_0\
);
\busy_sr[26]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[25]\,
I1 => \^p_0_in\,
O => \busy_sr[26]_i_1_n_0\
);
\busy_sr[27]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[26]\,
I1 => \^p_0_in\,
O => \busy_sr[27]_i_1_n_0\
);
\busy_sr[28]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[27]\,
I1 => \^p_0_in\,
O => \busy_sr[28]_i_1_n_0\
);
\busy_sr[29]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[28]\,
I1 => \^p_0_in\,
O => \busy_sr[29]_i_1_n_0\
);
\busy_sr[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[1]\,
I1 => \^p_0_in\,
O => \busy_sr[2]_i_1_n_0\
);
\busy_sr[30]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[29]\,
I1 => \^p_0_in\,
O => \busy_sr[30]_i_1_n_0\
);
\busy_sr[31]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"22222222A2222222"
)
port map (
I0 => p_1_in(0),
I1 => \^busy_sr_reg[1]_0\,
I2 => \^p_0_in\,
I3 => \divider_reg__0\(7),
I4 => \divider_reg__0\(6),
I5 => \busy_sr[0]_i_3_n_0\,
O => \busy_sr[31]_i_1_n_0\
);
\busy_sr[31]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^p_0_in\,
I1 => \busy_sr_reg_n_0_[30]\,
O => \busy_sr[31]_i_2_n_0\
);
\busy_sr[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[2]\,
I1 => \^p_0_in\,
O => \busy_sr[3]_i_1_n_0\
);
\busy_sr[4]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[3]\,
I1 => \^p_0_in\,
O => \busy_sr[4]_i_1_n_0\
);
\busy_sr[5]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[4]\,
I1 => \^p_0_in\,
O => \busy_sr[5]_i_1_n_0\
);
\busy_sr[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[5]\,
I1 => \^p_0_in\,
O => \busy_sr[6]_i_1_n_0\
);
\busy_sr[7]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[6]\,
I1 => \^p_0_in\,
O => \busy_sr[7]_i_1_n_0\
);
\busy_sr[8]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[7]\,
I1 => \^p_0_in\,
O => \busy_sr[8]_i_1_n_0\
);
\busy_sr[9]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[8]\,
I1 => \^p_0_in\,
O => \busy_sr[9]_i_1_n_0\
);
\busy_sr_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => p_1_in(0),
Q => \busy_sr_reg_n_0_[0]\,
R => '0'
);
\busy_sr_reg[10]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[10]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[10]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[11]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[11]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[11]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[12]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[12]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[12]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[13]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[13]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[13]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[14]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[14]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[14]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[15]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[15]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[15]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[16]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[16]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[16]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[17]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[17]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[17]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[18]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[18]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[18]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[19]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[19]_i_1_n_0\,
Q => p_1_in_0(0),
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[1]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[1]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[1]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[20]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[20]_i_1_n_0\,
Q => p_1_in_0(1),
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[21]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[21]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[21]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[22]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[22]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[22]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[23]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[23]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[23]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[24]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[24]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[24]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[25]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[25]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[25]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[26]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[26]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[26]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[27]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[27]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[27]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[28]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[28]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[28]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[29]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[29]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[29]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[2]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[2]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[2]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[30]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[30]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[30]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[31]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[31]_i_2_n_0\,
Q => \^p_0_in\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[3]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[3]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[3]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[4]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[4]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[4]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[5]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[5]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[5]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[6]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[6]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[6]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[7]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[7]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[7]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[8]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[8]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[8]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[9]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[9]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[9]\,
S => \busy_sr[31]_i_1_n_0\
);
\data_sr[10]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[9]\,
I1 => \^p_0_in\,
I2 => DOADO(7),
O => \data_sr[10]_i_1_n_0\
);
\data_sr[12]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[11]\,
I1 => \^p_0_in\,
I2 => DOADO(8),
O => \data_sr[12]_i_1_n_0\
);
\data_sr[13]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[12]\,
I1 => \^p_0_in\,
I2 => DOADO(9),
O => \data_sr[13]_i_1_n_0\
);
\data_sr[14]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[13]\,
I1 => \^p_0_in\,
I2 => DOADO(10),
O => \data_sr[14]_i_1_n_0\
);
\data_sr[15]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[14]\,
I1 => \^p_0_in\,
I2 => DOADO(11),
O => \data_sr[15]_i_1_n_0\
);
\data_sr[16]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[15]\,
I1 => \^p_0_in\,
I2 => DOADO(12),
O => \data_sr[16]_i_1_n_0\
);
\data_sr[17]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[16]\,
I1 => \^p_0_in\,
I2 => DOADO(13),
O => \data_sr[17]_i_1_n_0\
);
\data_sr[18]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[17]\,
I1 => \^p_0_in\,
I2 => DOADO(14),
O => \data_sr[18]_i_1_n_0\
);
\data_sr[19]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[18]\,
I1 => \^p_0_in\,
I2 => DOADO(15),
O => \data_sr[19]_i_1_n_0\
);
\data_sr[22]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"CFCFCFCFAACAAAAA"
)
port map (
I0 => \data_sr_reg_n_0_[22]\,
I1 => \data_sr_reg_n_0_[21]\,
I2 => \^p_0_in\,
I3 => \data_sr[31]_i_2_n_0\,
I4 => \divider_reg__0\(7),
I5 => \busy_sr_reg[31]_0\,
O => \data_sr[22]_i_1_n_0\
);
\data_sr[27]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"CFCFCFCFAACAAAAA"
)
port map (
I0 => \data_sr_reg_n_0_[27]\,
I1 => \data_sr_reg_n_0_[26]\,
I2 => \^p_0_in\,
I3 => \data_sr[31]_i_2_n_0\,
I4 => \divider_reg__0\(7),
I5 => \busy_sr_reg[31]_0\,
O => \data_sr[27]_i_1_n_0\
);
\data_sr[30]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => p_1_in(0),
I1 => \^busy_sr_reg[1]_0\,
I2 => \^p_0_in\,
O => \data_sr[30]_i_1_n_0\
);
\data_sr[31]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"CFCFCFCFAACAAAAA"
)
port map (
I0 => \data_sr_reg_n_0_[31]\,
I1 => \data_sr_reg_n_0_[30]\,
I2 => \^p_0_in\,
I3 => \data_sr[31]_i_2_n_0\,
I4 => \divider_reg__0\(7),
I5 => \busy_sr_reg[31]_0\,
O => \data_sr[31]_i_1_n_0\
);
\data_sr[31]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \busy_sr[0]_i_3_n_0\,
I1 => \divider_reg__0\(6),
O => \data_sr[31]_i_2_n_0\
);
\data_sr[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[2]\,
I1 => \^p_0_in\,
I2 => DOADO(0),
O => \data_sr[3]_i_1_n_0\
);
\data_sr[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[3]\,
I1 => \^p_0_in\,
I2 => DOADO(1),
O => \data_sr[4]_i_1_n_0\
);
\data_sr[5]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[4]\,
I1 => \^p_0_in\,
I2 => DOADO(2),
O => \data_sr[5]_i_1_n_0\
);
\data_sr[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[5]\,
I1 => \^p_0_in\,
I2 => DOADO(3),
O => \data_sr[6]_i_1_n_0\
);
\data_sr[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[6]\,
I1 => \^p_0_in\,
I2 => DOADO(4),
O => \data_sr[7]_i_1_n_0\
);
\data_sr[8]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[7]\,
I1 => \^p_0_in\,
I2 => DOADO(5),
O => \data_sr[8]_i_1_n_0\
);
\data_sr[9]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[8]\,
I1 => \^p_0_in\,
I2 => DOADO(6),
O => \data_sr[9]_i_1_n_0\
);
\data_sr_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[10]_i_1_n_0\,
Q => \data_sr_reg_n_0_[10]\,
R => '0'
);
\data_sr_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[10]\,
Q => \data_sr_reg_n_0_[11]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[12]_i_1_n_0\,
Q => \data_sr_reg_n_0_[12]\,
R => '0'
);
\data_sr_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[13]_i_1_n_0\,
Q => \data_sr_reg_n_0_[13]\,
R => '0'
);
\data_sr_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[14]_i_1_n_0\,
Q => \data_sr_reg_n_0_[14]\,
R => '0'
);
\data_sr_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[15]_i_1_n_0\,
Q => \data_sr_reg_n_0_[15]\,
R => '0'
);
\data_sr_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[16]_i_1_n_0\,
Q => \data_sr_reg_n_0_[16]\,
R => '0'
);
\data_sr_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[17]_i_1_n_0\,
Q => \data_sr_reg_n_0_[17]\,
R => '0'
);
\data_sr_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[18]_i_1_n_0\,
Q => \data_sr_reg_n_0_[18]\,
R => '0'
);
\data_sr_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[19]_i_1_n_0\,
Q => \data_sr_reg_n_0_[19]\,
R => '0'
);
\data_sr_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \^p_0_in\,
Q => \data_sr_reg_n_0_[1]\,
R => '0'
);
\data_sr_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[19]\,
Q => \data_sr_reg_n_0_[20]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[20]\,
Q => \data_sr_reg_n_0_[21]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => \data_sr[22]_i_1_n_0\,
Q => \data_sr_reg_n_0_[22]\,
R => '0'
);
\data_sr_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[22]\,
Q => \data_sr_reg_n_0_[23]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[23]\,
Q => \data_sr_reg_n_0_[24]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[24]\,
Q => \data_sr_reg_n_0_[25]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[26]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[25]\,
Q => \data_sr_reg_n_0_[26]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => \data_sr[27]_i_1_n_0\,
Q => \data_sr_reg_n_0_[27]\,
R => '0'
);
\data_sr_reg[28]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[27]\,
Q => \data_sr_reg_n_0_[28]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[29]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[28]\,
Q => \data_sr_reg_n_0_[29]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[1]\,
Q => \data_sr_reg_n_0_[2]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[30]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[29]\,
Q => \data_sr_reg_n_0_[30]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[31]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => \data_sr[31]_i_1_n_0\,
Q => \data_sr_reg_n_0_[31]\,
R => '0'
);
\data_sr_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[3]_i_1_n_0\,
Q => \data_sr_reg_n_0_[3]\,
R => '0'
);
\data_sr_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[4]_i_1_n_0\,
Q => \data_sr_reg_n_0_[4]\,
R => '0'
);
\data_sr_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[5]_i_1_n_0\,
Q => \data_sr_reg_n_0_[5]\,
R => '0'
);
\data_sr_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[6]_i_1_n_0\,
Q => \data_sr_reg_n_0_[6]\,
R => '0'
);
\data_sr_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[7]_i_1_n_0\,
Q => \data_sr_reg_n_0_[7]\,
R => '0'
);
\data_sr_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[8]_i_1_n_0\,
Q => \data_sr_reg_n_0_[8]\,
R => '0'
);
\data_sr_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[9]_i_1_n_0\,
Q => \data_sr_reg_n_0_[9]\,
R => '0'
);
\divider[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \divider_reg__1\(0),
O => \p_0_in__0\(0)
);
\divider[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \divider_reg__1\(0),
I1 => \divider_reg__1\(1),
O => \p_0_in__0\(1)
);
\divider[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \divider_reg__1\(1),
I1 => \divider_reg__1\(0),
I2 => \divider_reg__1\(2),
O => \p_0_in__0\(2)
);
\divider[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \divider_reg__1\(2),
I1 => \divider_reg__1\(0),
I2 => \divider_reg__1\(1),
I3 => \divider_reg__1\(3),
O => \p_0_in__0\(3)
);
\divider[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \divider_reg__1\(3),
I1 => \divider_reg__1\(1),
I2 => \divider_reg__1\(0),
I3 => \divider_reg__1\(2),
I4 => \divider_reg__1\(4),
O => \p_0_in__0\(4)
);
\divider[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFF80000000"
)
port map (
I0 => \divider_reg__1\(4),
I1 => \divider_reg__1\(2),
I2 => \divider_reg__1\(0),
I3 => \divider_reg__1\(1),
I4 => \divider_reg__1\(3),
I5 => \divider_reg__1\(5),
O => \p_0_in__0\(5)
);
\divider[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \busy_sr[0]_i_3_n_0\,
I1 => \divider_reg__0\(6),
O => \p_0_in__0\(6)
);
\divider[7]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"D2"
)
port map (
I0 => \divider_reg__0\(6),
I1 => \busy_sr[0]_i_3_n_0\,
I2 => \divider_reg__0\(7),
O => \p_0_in__0\(7)
);
\divider_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => \busy_sr_reg[31]_1\(0),
D => \p_0_in__0\(0),
Q => \divider_reg__1\(0),
R => '0'
);
\divider_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \busy_sr_reg[31]_1\(0),
D => \p_0_in__0\(1),
Q => \divider_reg__1\(1),
R => '0'
);
\divider_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \busy_sr_reg[31]_1\(0),
D => \p_0_in__0\(2),
Q => \divider_reg__1\(2),
R => '0'
);
\divider_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \busy_sr_reg[31]_1\(0),
D => \p_0_in__0\(3),
Q => \divider_reg__1\(3),
R => '0'
);
\divider_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \busy_sr_reg[31]_1\(0),
D => \p_0_in__0\(4),
Q => \divider_reg__1\(4),
R => '0'
);
\divider_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \busy_sr_reg[31]_1\(0),
D => \p_0_in__0\(5),
Q => \divider_reg__1\(5),
R => '0'
);
\divider_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \busy_sr_reg[31]_1\(0),
D => \p_0_in__0\(6),
Q => \divider_reg__0\(6),
R => '0'
);
\divider_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \busy_sr_reg[31]_1\(0),
D => \p_0_in__0\(7),
Q => \divider_reg__0\(7),
R => '0'
);
sioc_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FCFCFFF8FFFFFFFF"
)
port map (
I0 => \busy_sr_reg_n_0_[0]\,
I1 => sioc_i_2_n_0,
I2 => sioc_i_3_n_0,
I3 => \busy_sr_reg_n_0_[1]\,
I4 => sioc_i_4_n_0,
I5 => \^p_0_in\,
O => sioc_i_1_n_0
);
sioc_i_2: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \divider_reg__0\(6),
I1 => \divider_reg__0\(7),
O => sioc_i_2_n_0
);
sioc_i_3: unisim.vcomponents.LUT4
generic map(
INIT => X"A222"
)
port map (
I0 => sioc_i_5_n_0,
I1 => \busy_sr_reg_n_0_[30]\,
I2 => \divider_reg__0\(6),
I3 => \^p_0_in\,
O => sioc_i_3_n_0
);
sioc_i_4: unisim.vcomponents.LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => \busy_sr_reg_n_0_[29]\,
I1 => \busy_sr_reg_n_0_[2]\,
I2 => \^p_0_in\,
I3 => \busy_sr_reg_n_0_[30]\,
O => sioc_i_4_n_0
);
sioc_i_5: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => \busy_sr_reg_n_0_[0]\,
I1 => \busy_sr_reg_n_0_[1]\,
I2 => \busy_sr_reg_n_0_[29]\,
I3 => \busy_sr_reg_n_0_[2]\,
O => sioc_i_5_n_0
);
sioc_reg: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => sioc_i_1_n_0,
Q => sioc,
R => '0'
);
siod_INST_0: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \data_sr_reg_n_0_[31]\,
I1 => siod_INST_0_i_1_n_0,
O => siod
);
siod_INST_0_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"B0BBB0BB0000B0BB"
)
port map (
I0 => \busy_sr_reg_n_0_[28]\,
I1 => \busy_sr_reg_n_0_[29]\,
I2 => p_1_in_0(0),
I3 => p_1_in_0(1),
I4 => \busy_sr_reg_n_0_[11]\,
I5 => \busy_sr_reg_n_0_[10]\,
O => siod_INST_0_i_1_n_0
);
taken_reg: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \busy_sr_reg[31]_0\,
Q => E(0),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_ov7670_controller_0_0_ov7670_registers is
port (
DOADO : out STD_LOGIC_VECTOR ( 15 downto 0 );
\divider_reg[7]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
config_finished : out STD_LOGIC;
taken_reg : out STD_LOGIC;
p_1_in : out STD_LOGIC_VECTOR ( 0 to 0 );
clk : in STD_LOGIC;
\divider_reg[2]\ : in STD_LOGIC;
p_0_in : in STD_LOGIC;
resend : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end system_ov7670_controller_0_0_ov7670_registers;
architecture STRUCTURE of system_ov7670_controller_0_0_ov7670_registers is
signal \^doado\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal address : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \address_reg__0\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \address_rep[0]_i_1_n_0\ : STD_LOGIC;
signal \address_rep[1]_i_1_n_0\ : STD_LOGIC;
signal \address_rep[2]_i_1_n_0\ : STD_LOGIC;
signal \address_rep[3]_i_1_n_0\ : STD_LOGIC;
signal \address_rep[4]_i_1_n_0\ : STD_LOGIC;
signal \address_rep[5]_i_1_n_0\ : STD_LOGIC;
signal \address_rep[6]_i_1_n_0\ : STD_LOGIC;
signal \address_rep[7]_i_1_n_0\ : STD_LOGIC;
signal \address_rep[7]_i_2_n_0\ : STD_LOGIC;
signal config_finished_INST_0_i_1_n_0 : STD_LOGIC;
signal config_finished_INST_0_i_2_n_0 : STD_LOGIC;
signal config_finished_INST_0_i_3_n_0 : STD_LOGIC;
signal config_finished_INST_0_i_4_n_0 : STD_LOGIC;
signal NLW_sreg_reg_DOBDO_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
signal NLW_sreg_reg_DOPADOP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_sreg_reg_DOPBDOP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of \address_reg[0]\ : label is "no";
attribute equivalent_register_removal of \address_reg[1]\ : label is "no";
attribute equivalent_register_removal of \address_reg[2]\ : label is "no";
attribute equivalent_register_removal of \address_reg[3]\ : label is "no";
attribute equivalent_register_removal of \address_reg[4]\ : label is "no";
attribute equivalent_register_removal of \address_reg[5]\ : label is "no";
attribute equivalent_register_removal of \address_reg[6]\ : label is "no";
attribute equivalent_register_removal of \address_reg[7]\ : label is "no";
attribute equivalent_register_removal of \address_reg_rep[0]\ : label is "no";
attribute equivalent_register_removal of \address_reg_rep[1]\ : label is "no";
attribute equivalent_register_removal of \address_reg_rep[2]\ : label is "no";
attribute equivalent_register_removal of \address_reg_rep[3]\ : label is "no";
attribute equivalent_register_removal of \address_reg_rep[4]\ : label is "no";
attribute equivalent_register_removal of \address_reg_rep[5]\ : label is "no";
attribute equivalent_register_removal of \address_reg_rep[6]\ : label is "no";
attribute equivalent_register_removal of \address_reg_rep[7]\ : label is "no";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \address_rep[1]_i_1\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \address_rep[2]_i_1\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \address_rep[3]_i_1\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \address_rep[4]_i_1\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \address_rep[6]_i_1\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \address_rep[7]_i_1\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \busy_sr[0]_i_2\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of config_finished_INST_0 : label is "soft_lutpair30";
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of sreg_reg : label is "INDEPENDENT";
attribute \MEM.PORTA.DATA_BIT_LAYOUT\ : string;
attribute \MEM.PORTA.DATA_BIT_LAYOUT\ of sreg_reg : label is "p0_d16";
attribute METHODOLOGY_DRC_VIOS : string;
attribute METHODOLOGY_DRC_VIOS of sreg_reg : label is "{SYNTH-6 {cell *THIS*}}";
attribute RTL_RAM_BITS : integer;
attribute RTL_RAM_BITS of sreg_reg : label is 4096;
attribute RTL_RAM_NAME : string;
attribute RTL_RAM_NAME of sreg_reg : label is "U0/Inst_ov7670_registers/sreg";
attribute bram_addr_begin : integer;
attribute bram_addr_begin of sreg_reg : label is 0;
attribute bram_addr_end : integer;
attribute bram_addr_end of sreg_reg : label is 1023;
attribute bram_slice_begin : integer;
attribute bram_slice_begin of sreg_reg : label is 0;
attribute bram_slice_end : integer;
attribute bram_slice_end of sreg_reg : label is 15;
begin
DOADO(15 downto 0) <= \^doado\(15 downto 0);
\address_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[0]_i_1_n_0\,
Q => \address_reg__0\(0),
R => resend
);
\address_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[1]_i_1_n_0\,
Q => \address_reg__0\(1),
R => resend
);
\address_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[2]_i_1_n_0\,
Q => \address_reg__0\(2),
R => resend
);
\address_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[3]_i_1_n_0\,
Q => \address_reg__0\(3),
R => resend
);
\address_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[4]_i_1_n_0\,
Q => \address_reg__0\(4),
R => resend
);
\address_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[5]_i_1_n_0\,
Q => \address_reg__0\(5),
R => resend
);
\address_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[6]_i_1_n_0\,
Q => \address_reg__0\(6),
R => resend
);
\address_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[7]_i_1_n_0\,
Q => \address_reg__0\(7),
R => resend
);
\address_reg_rep[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[0]_i_1_n_0\,
Q => address(0),
R => resend
);
\address_reg_rep[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[1]_i_1_n_0\,
Q => address(1),
R => resend
);
\address_reg_rep[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[2]_i_1_n_0\,
Q => address(2),
R => resend
);
\address_reg_rep[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[3]_i_1_n_0\,
Q => address(3),
R => resend
);
\address_reg_rep[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[4]_i_1_n_0\,
Q => address(4),
R => resend
);
\address_reg_rep[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[5]_i_1_n_0\,
Q => address(5),
R => resend
);
\address_reg_rep[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[6]_i_1_n_0\,
Q => address(6),
R => resend
);
\address_reg_rep[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[7]_i_1_n_0\,
Q => address(7),
R => resend
);
\address_rep[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \address_reg__0\(0),
O => \address_rep[0]_i_1_n_0\
);
\address_rep[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \address_reg__0\(0),
I1 => \address_reg__0\(1),
O => \address_rep[1]_i_1_n_0\
);
\address_rep[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \address_reg__0\(1),
I1 => \address_reg__0\(0),
I2 => \address_reg__0\(2),
O => \address_rep[2]_i_1_n_0\
);
\address_rep[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \address_reg__0\(2),
I1 => \address_reg__0\(0),
I2 => \address_reg__0\(1),
I3 => \address_reg__0\(3),
O => \address_rep[3]_i_1_n_0\
);
\address_rep[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \address_reg__0\(3),
I1 => \address_reg__0\(1),
I2 => \address_reg__0\(0),
I3 => \address_reg__0\(2),
I4 => \address_reg__0\(4),
O => \address_rep[4]_i_1_n_0\
);
\address_rep[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFF80000000"
)
port map (
I0 => \address_reg__0\(4),
I1 => \address_reg__0\(2),
I2 => \address_reg__0\(0),
I3 => \address_reg__0\(1),
I4 => \address_reg__0\(3),
I5 => \address_reg__0\(5),
O => \address_rep[5]_i_1_n_0\
);
\address_rep[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \address_rep[7]_i_2_n_0\,
I1 => \address_reg__0\(6),
O => \address_rep[6]_i_1_n_0\
);
\address_rep[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"D2"
)
port map (
I0 => \address_reg__0\(6),
I1 => \address_rep[7]_i_2_n_0\,
I2 => \address_reg__0\(7),
O => \address_rep[7]_i_1_n_0\
);
\address_rep[7]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFFFFFFFFFF"
)
port map (
I0 => \address_reg__0\(4),
I1 => \address_reg__0\(2),
I2 => \address_reg__0\(0),
I3 => \address_reg__0\(1),
I4 => \address_reg__0\(3),
I5 => \address_reg__0\(5),
O => \address_rep[7]_i_2_n_0\
);
\busy_sr[0]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"0000FFFE"
)
port map (
I0 => config_finished_INST_0_i_4_n_0,
I1 => config_finished_INST_0_i_3_n_0,
I2 => config_finished_INST_0_i_2_n_0,
I3 => config_finished_INST_0_i_1_n_0,
I4 => p_0_in,
O => p_1_in(0)
);
config_finished_INST_0: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => config_finished_INST_0_i_1_n_0,
I1 => config_finished_INST_0_i_2_n_0,
I2 => config_finished_INST_0_i_3_n_0,
I3 => config_finished_INST_0_i_4_n_0,
O => config_finished
);
config_finished_INST_0_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => \^doado\(5),
I1 => \^doado\(4),
I2 => \^doado\(7),
I3 => \^doado\(6),
O => config_finished_INST_0_i_1_n_0
);
config_finished_INST_0_i_2: unisim.vcomponents.LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => \^doado\(1),
I1 => \^doado\(0),
I2 => \^doado\(3),
I3 => \^doado\(2),
O => config_finished_INST_0_i_2_n_0
);
config_finished_INST_0_i_3: unisim.vcomponents.LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => \^doado\(13),
I1 => \^doado\(12),
I2 => \^doado\(15),
I3 => \^doado\(14),
O => config_finished_INST_0_i_3_n_0
);
config_finished_INST_0_i_4: unisim.vcomponents.LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => \^doado\(9),
I1 => \^doado\(8),
I2 => \^doado\(11),
I3 => \^doado\(10),
O => config_finished_INST_0_i_4_n_0
);
\divider[7]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFE0000"
)
port map (
I0 => config_finished_INST_0_i_1_n_0,
I1 => config_finished_INST_0_i_2_n_0,
I2 => config_finished_INST_0_i_3_n_0,
I3 => config_finished_INST_0_i_4_n_0,
I4 => \divider_reg[2]\,
I5 => p_0_in,
O => \divider_reg[7]\(0)
);
sreg_reg: unisim.vcomponents.RAMB18E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"53295217510C50344F4014383A04401004008C003E000C001100120412801280",
INIT_01 => X"229121021E3716020F4B0E61030A1A7B190332A41861171111003DC0581E5440",
INIT_02 => X"90008F008E008D4F74106B4A69004E204D403C78392A3871371D350B330B2907",
INIT_03 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFB80AB382B20EB10CB0849A0096009100",
INIT_04 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_05 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_06 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_07 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_08 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_09 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0A => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0B => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0C => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0D => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0E => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0F => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"00000",
INIT_B => X"00000",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 18,
READ_WIDTH_B => 0,
RSTREG_PRIORITY_A => "RSTREG",
RSTREG_PRIORITY_B => "RSTREG",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"00000",
SRVAL_B => X"00000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 18,
WRITE_WIDTH_B => 0
)
port map (
ADDRARDADDR(13 downto 12) => B"00",
ADDRARDADDR(11 downto 4) => address(7 downto 0),
ADDRARDADDR(3 downto 0) => B"0000",
ADDRBWRADDR(13 downto 0) => B"11111111111111",
CLKARDCLK => clk,
CLKBWRCLK => '0',
DIADI(15 downto 0) => B"1111111111111111",
DIBDI(15 downto 0) => B"1111111111111111",
DIPADIP(1 downto 0) => B"00",
DIPBDIP(1 downto 0) => B"11",
DOADO(15 downto 0) => \^doado\(15 downto 0),
DOBDO(15 downto 0) => NLW_sreg_reg_DOBDO_UNCONNECTED(15 downto 0),
DOPADOP(1 downto 0) => NLW_sreg_reg_DOPADOP_UNCONNECTED(1 downto 0),
DOPBDOP(1 downto 0) => NLW_sreg_reg_DOPBDOP_UNCONNECTED(1 downto 0),
ENARDEN => '1',
ENBWREN => '0',
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
WEA(1 downto 0) => B"00",
WEBWE(3 downto 0) => B"0000"
);
taken_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000055555554"
)
port map (
I0 => p_0_in,
I1 => config_finished_INST_0_i_1_n_0,
I2 => config_finished_INST_0_i_2_n_0,
I3 => config_finished_INST_0_i_3_n_0,
I4 => config_finished_INST_0_i_4_n_0,
I5 => \divider_reg[2]\,
O => taken_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_ov7670_controller_0_0_ov7670_controller is
port (
config_finished : out STD_LOGIC;
siod : out STD_LOGIC;
sioc : out STD_LOGIC;
resend : in STD_LOGIC;
clk : in STD_LOGIC
);
end system_ov7670_controller_0_0_ov7670_controller;
architecture STRUCTURE of system_ov7670_controller_0_0_ov7670_controller is
signal Inst_i2c_sender_n_3 : STD_LOGIC;
signal Inst_ov7670_registers_n_16 : STD_LOGIC;
signal Inst_ov7670_registers_n_18 : STD_LOGIC;
signal p_0_in : STD_LOGIC;
signal p_1_in : STD_LOGIC_VECTOR ( 0 to 0 );
signal sreg_reg : STD_LOGIC_VECTOR ( 15 downto 0 );
signal taken : STD_LOGIC;
begin
Inst_i2c_sender: entity work.system_ov7670_controller_0_0_i2c_sender
port map (
DOADO(15 downto 0) => sreg_reg(15 downto 0),
E(0) => taken,
\busy_sr_reg[1]_0\ => Inst_i2c_sender_n_3,
\busy_sr_reg[31]_0\ => Inst_ov7670_registers_n_18,
\busy_sr_reg[31]_1\(0) => Inst_ov7670_registers_n_16,
clk => clk,
p_0_in => p_0_in,
p_1_in(0) => p_1_in(0),
sioc => sioc,
siod => siod
);
Inst_ov7670_registers: entity work.system_ov7670_controller_0_0_ov7670_registers
port map (
DOADO(15 downto 0) => sreg_reg(15 downto 0),
E(0) => taken,
clk => clk,
config_finished => config_finished,
\divider_reg[2]\ => Inst_i2c_sender_n_3,
\divider_reg[7]\(0) => Inst_ov7670_registers_n_16,
p_0_in => p_0_in,
p_1_in(0) => p_1_in(0),
resend => resend,
taken_reg => Inst_ov7670_registers_n_18
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_ov7670_controller_0_0 is
port (
clk : in STD_LOGIC;
resend : in STD_LOGIC;
config_finished : out STD_LOGIC;
sioc : out STD_LOGIC;
siod : inout STD_LOGIC;
reset : out STD_LOGIC;
pwdn : out STD_LOGIC;
xclk : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_ov7670_controller_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_ov7670_controller_0_0 : entity is "system_ov7670_controller_0_0,ov7670_controller,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_ov7670_controller_0_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_ov7670_controller_0_0 : entity is "ov7670_controller,Vivado 2016.4";
end system_ov7670_controller_0_0;
architecture STRUCTURE of system_ov7670_controller_0_0 is
signal \<const0>\ : STD_LOGIC;
signal \<const1>\ : STD_LOGIC;
begin
pwdn <= \<const0>\;
reset <= \<const1>\;
xclk <= 'Z';
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
U0: entity work.system_ov7670_controller_0_0_ov7670_controller
port map (
clk => clk,
config_finished => config_finished,
resend => resend,
sioc => sioc,
siod => siod
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
end STRUCTURE;
| mit |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/ov7670_hessian_split/ov7670_hessian_split.srcs/sources_1/bd/system/ip/system_vga_sync_0_0_1/system_vga_sync_0_0_stub.vhdl | 1 | 1462 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Sun Apr 09 09:37:58 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub -rename_top system_vga_sync_0_0 -prefix
-- system_vga_sync_0_0_ system_vga_sync_0_0_stub.vhdl
-- Design : system_vga_sync_0_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity system_vga_sync_0_0 is
Port (
clk_25 : in STD_LOGIC;
rst : in STD_LOGIC;
active : out STD_LOGIC;
hsync : out STD_LOGIC;
vsync : out STD_LOGIC;
xaddr : out STD_LOGIC_VECTOR ( 9 downto 0 );
yaddr : out STD_LOGIC_VECTOR ( 9 downto 0 )
);
end system_vga_sync_0_0;
architecture stub of system_vga_sync_0_0 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clk_25,rst,active,hsync,vsync,xaddr[9:0],yaddr[9:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "vga_sync,Vivado 2016.4";
begin
end;
| mit |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_transform_test/zed_transform_test.srcs/sources_1/bd/system/ip/system_util_ds_buf_1_0/synth/system_util_ds_buf_1_0.vhd | 1 | 6451 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:util_ds_buf:2.1
-- IP Revision: 6
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY util_ds_buf_v2_01_a;
USE util_ds_buf_v2_01_a.util_ds_buf;
ENTITY system_util_ds_buf_1_0 IS
PORT (
BUFG_I : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
BUFG_O : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END system_util_ds_buf_1_0;
ARCHITECTURE system_util_ds_buf_1_0_arch OF system_util_ds_buf_1_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_util_ds_buf_1_0_arch: ARCHITECTURE IS "yes";
COMPONENT util_ds_buf IS
GENERIC (
C_BUF_TYPE : STRING;
C_SIZE : INTEGER
);
PORT (
IBUF_DS_P : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
IBUF_DS_N : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
IBUF_OUT : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
IBUF_DS_ODIV2 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
OBUF_IN : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
OBUF_DS_P : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
OBUF_DS_N : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
IOBUF_DS_P : INOUT STD_LOGIC_VECTOR(0 DOWNTO 0);
IOBUF_DS_N : INOUT STD_LOGIC_VECTOR(0 DOWNTO 0);
IOBUF_IO_T : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
IOBUF_IO_I : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
IOBUF_IO_O : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
BUFG_I : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
BUFG_O : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
BUFGCE_I : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
BUFGCE_CE : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
BUFGCE_O : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
BUFH_I : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
BUFH_O : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
BUFHCE_I : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
BUFHCE_CE : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
BUFHCE_O : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
BUFG_GT_I : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
BUFG_GT_CE : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
BUFG_GT_CEMASK : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
BUFG_GT_CLR : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
BUFG_GT_CLRMASK : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
BUFG_GT_DIV : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
BUFG_GT_O : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT util_ds_buf;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF system_util_ds_buf_1_0_arch: ARCHITECTURE IS "util_ds_buf,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF system_util_ds_buf_1_0_arch : ARCHITECTURE IS "system_util_ds_buf_1_0,util_ds_buf,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF system_util_ds_buf_1_0_arch: ARCHITECTURE IS "system_util_ds_buf_1_0,util_ds_buf,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=util_ds_buf,x_ipVersion=2.1,x_ipCoreRevision=6,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_BUF_TYPE=BUFG,C_SIZE=1}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF BUFG_I: SIGNAL IS "xilinx.com:signal:clock:1.0 BUFG_I CLK";
ATTRIBUTE X_INTERFACE_INFO OF BUFG_O: SIGNAL IS "xilinx.com:signal:clock:1.0 BUFG_O CLK";
BEGIN
U0 : util_ds_buf
GENERIC MAP (
C_BUF_TYPE => "BUFG",
C_SIZE => 1
)
PORT MAP (
IBUF_DS_P => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
IBUF_DS_N => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
OBUF_IN => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
IOBUF_IO_T => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
IOBUF_IO_I => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
BUFG_I => BUFG_I,
BUFG_O => BUFG_O,
BUFGCE_I => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
BUFGCE_CE => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
BUFH_I => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
BUFHCE_I => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
BUFHCE_CE => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
BUFG_GT_I => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
BUFG_GT_CE => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
BUFG_GT_CEMASK => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
BUFG_GT_CLR => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
BUFG_GT_CLRMASK => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
BUFG_GT_DIV => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3))
);
END system_util_ds_buf_1_0_arch;
| mit |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/ov7670_fusion/ov7670_fusion.srcs/sources_1/bd/system/ipshared/6554/vga_gaussian_blur.vhd | 2 | 5725 | ----------------------------------------------------------------------------------
-- Company: Drexel University
-- Engineer: Rob Taglang
--
-- Module Name: vga_gaussian_blur - Structural
-- Description: Blur an input image stream and sync with output
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
entity vga_gaussian_blur is
generic(
H_SIZE : integer := 640;
H_DELAY : integer := 160;
KERNEL : integer := 3
);
port(
clk_25 : in std_logic;
hsync_in : in std_logic;
vsync_in : in std_logic;
rgb_in : in std_logic_vector(23 downto 0);
hsync_out : out std_logic;
vsync_out : out std_logic;
rgb_blur : out std_logic_vector(23 downto 0);
rgb_pass : out std_logic_vector(23 downto 0)
);
end vga_gaussian_blur;
architecture Structural of vga_gaussian_blur is
type PIXEL_BUFFER is array ((H_SIZE)*(KERNEL-1) + KERNEL - 1 downto 0) of std_logic_vector(23 downto 0);
type SIGNAL_BUFFER is array ((H_SIZE + H_DELAY)*(KERNEL/2) + KERNEL/2 downto 0) of std_logic_vector(1 downto 0);
type INT_ARRAY is array (integer range<>) of integer;
signal active : std_logic;
begin
active <= not (hsync_in or vsync_in);
process(clk_25)
variable rgb_buffer : PIXEL_BUFFER;
variable sync_buffer : SIGNAL_BUFFER;
variable temp_r : INT_ARRAY(KERNEL*KERNEL - 1 downto 0);
variable temp_g : INT_ARRAY(KERNEL*KERNEL - 1 downto 0);
variable temp_b : INT_ARRAY(KERNEL*KERNEL - 1 downto 0);
variable compute_r, compute_g, compute_b : integer;
begin
if rising_edge(clk_25) then
if active = '1' then
temp_r(0) := to_integer(unsigned(rgb_buffer(0)(23 downto 16)));
temp_r(1) := to_integer(unsigned(rgb_buffer(1)(23 downto 16)));
temp_r(2) := to_integer(unsigned(rgb_buffer(2)(23 downto 16)));
temp_r(3) := to_integer(unsigned(rgb_buffer(H_SIZE)(23 downto 16)));
temp_r(4) := to_integer(unsigned(rgb_buffer(H_SIZE+1)(23 downto 16)));
temp_r(5) := to_integer(unsigned(rgb_buffer(H_SIZE+2)(23 downto 16)));
temp_r(6) := to_integer(unsigned(rgb_buffer(2*(H_SIZE))(23 downto 16)));
temp_r(7) := to_integer(unsigned(rgb_buffer(2*(H_SIZE)+1)(23 downto 16)));
temp_r(8) := to_integer(unsigned(rgb_buffer(2*(H_SIZE)+2)(23 downto 16)));
compute_r := (temp_r(0) + 2*temp_r(1) + temp_r(2) + 2*temp_r(3) + 4*temp_r(4) + 2*temp_r(5) + temp_r(6) + 2*temp_r(7) + temp_r(8))/16;
temp_g(0) := to_integer(unsigned(rgb_buffer(0)(15 downto 8)));
temp_g(1) := to_integer(unsigned(rgb_buffer(1)(15 downto 8)));
temp_g(2) := to_integer(unsigned(rgb_buffer(2)(15 downto 8)));
temp_g(3) := to_integer(unsigned(rgb_buffer(H_SIZE)(15 downto 8)));
temp_g(4) := to_integer(unsigned(rgb_buffer(H_SIZE+1)(15 downto 8)));
temp_g(5) := to_integer(unsigned(rgb_buffer(H_SIZE+2)(15 downto 8)));
temp_g(6) := to_integer(unsigned(rgb_buffer(2*(H_SIZE))(15 downto 8)));
temp_g(7) := to_integer(unsigned(rgb_buffer(2*(H_SIZE)+1)(15 downto 8)));
temp_g(8) := to_integer(unsigned(rgb_buffer(2*(H_SIZE)+2)(15 downto 8)));
compute_g := (temp_g(0) + 2*temp_g(1) + temp_g(2) + 2*temp_g(3) + 4*temp_g(4) + 2*temp_g(5) + temp_g(6) + 2*temp_g(7) + temp_g(8))/16;
temp_b(0) := to_integer(unsigned(rgb_buffer(0)(7 downto 0)));
temp_b(1) := to_integer(unsigned(rgb_buffer(1)(7 downto 0)));
temp_b(2) := to_integer(unsigned(rgb_buffer(2)(7 downto 0)));
temp_b(3) := to_integer(unsigned(rgb_buffer(H_SIZE)(7 downto 0)));
temp_b(4) := to_integer(unsigned(rgb_buffer(H_SIZE+1)(7 downto 0)));
temp_b(5) := to_integer(unsigned(rgb_buffer(H_SIZE+2)(7 downto 0)));
temp_b(6) := to_integer(unsigned(rgb_buffer(2*(H_SIZE))(7 downto 0)));
temp_b(7) := to_integer(unsigned(rgb_buffer(2*(H_SIZE)+1)(7 downto 0)));
temp_b(8) := to_integer(unsigned(rgb_buffer(2*(H_SIZE)+2)(7 downto 0)));
compute_b := (temp_b(0) + 2*temp_b(1) + temp_b(2) + 2*temp_b(3) + 4*temp_b(4) + 2*temp_b(5) + temp_b(6) + 2*temp_b(7) + temp_b(8))/16;
rgb_blur(23 downto 16) <= std_logic_vector(to_unsigned(compute_r, 8));
rgb_blur(15 downto 8) <= std_logic_vector(to_unsigned(compute_g, 8));
rgb_blur(7 downto 0) <= std_logic_vector(to_unsigned(compute_b, 8));
rgb_pass <= rgb_buffer(H_SIZE+1);
for i in (H_SIZE)*(KERNEL-1) + KERNEL - 1 downto 1 loop
rgb_buffer(i) := rgb_buffer(i-1);
end loop;
rgb_buffer(0) := rgb_in;
else
rgb_blur <= (others => '0');
rgb_pass <= (others => '0');
end if;
hsync_out <= sync_buffer(H_SIZE+H_DELAY+1)(1);
vsync_out <= sync_buffer(H_SIZE+H_DELAY+1)(0);
for i in (H_SIZE + H_DELAY)*(KERNEL/2) + KERNEL/2 - 1 downto 1 loop
sync_buffer(i) := sync_buffer(i-1);
end loop;
sync_buffer(0) := (1 => hsync_in, 0 => vsync_in);
end if;
end process;
end Structural;
| mit |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_camera_hessian/zed_camera_hessian.srcs/sources_1/bd/system/ip/system_debounce_0_0/synth/system_debounce_0_0.vhd | 4 | 3776 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:debounce:1.0
-- IP Revision: 6
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_debounce_0_0 IS
PORT (
clk : IN STD_LOGIC;
signal_in : IN STD_LOGIC;
signal_out : OUT STD_LOGIC
);
END system_debounce_0_0;
ARCHITECTURE system_debounce_0_0_arch OF system_debounce_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_debounce_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT debounce IS
PORT (
clk : IN STD_LOGIC;
signal_in : IN STD_LOGIC;
signal_out : OUT STD_LOGIC
);
END COMPONENT debounce;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF system_debounce_0_0_arch: ARCHITECTURE IS "debounce,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF system_debounce_0_0_arch : ARCHITECTURE IS "system_debounce_0_0,debounce,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF system_debounce_0_0_arch: ARCHITECTURE IS "system_debounce_0_0,debounce,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=user,x_ipName=debounce,x_ipVersion=1.0,x_ipCoreRevision=6,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clk CLK";
BEGIN
U0 : debounce
PORT MAP (
clk => clk,
signal_in => signal_in,
signal_out => signal_out
);
END system_debounce_0_0_arch;
| mit |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_dual_fusion/zed_dual_fusion.srcs/sources_1/bd/system/ip/system_vga_hessian_0_0/sim/system_vga_hessian_0_0.vhd | 1 | 3768 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:vga_hessian:1.0
-- IP Revision: 41
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_vga_hessian_0_0 IS
PORT (
clk_x16 : IN STD_LOGIC;
active : IN STD_LOGIC;
rst : IN STD_LOGIC;
x_addr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
y_addr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
g_in : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
hessian_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END system_vga_hessian_0_0;
ARCHITECTURE system_vga_hessian_0_0_arch OF system_vga_hessian_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_vga_hessian_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT vga_hessian IS
GENERIC (
ROW_WIDTH : INTEGER
);
PORT (
clk_x16 : IN STD_LOGIC;
active : IN STD_LOGIC;
rst : IN STD_LOGIC;
x_addr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
y_addr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
g_in : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
hessian_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT vga_hessian;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF rst: SIGNAL IS "xilinx.com:signal:reset:1.0 rst RST";
BEGIN
U0 : vga_hessian
GENERIC MAP (
ROW_WIDTH => 640
)
PORT MAP (
clk_x16 => clk_x16,
active => active,
rst => rst,
x_addr => x_addr,
y_addr => y_addr,
g_in => g_in,
hessian_out => hessian_out
);
END system_vga_hessian_0_0_arch;
| mit |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/ov7670_hessian_split/ov7670_hessian_split.srcs/sources_1/bd/system/ip/system_ov7670_controller_1_0_1/sim/system_ov7670_controller_1_0.vhd | 2 | 3747 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:ov7670_controller:1.0
-- IP Revision: 3
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_ov7670_controller_1_0 IS
PORT (
clk : IN STD_LOGIC;
resend : IN STD_LOGIC;
config_finished : OUT STD_LOGIC;
sioc : OUT STD_LOGIC;
siod : INOUT STD_LOGIC;
reset : OUT STD_LOGIC;
pwdn : OUT STD_LOGIC;
xclk : OUT STD_LOGIC
);
END system_ov7670_controller_1_0;
ARCHITECTURE system_ov7670_controller_1_0_arch OF system_ov7670_controller_1_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_ov7670_controller_1_0_arch: ARCHITECTURE IS "yes";
COMPONENT ov7670_controller IS
PORT (
clk : IN STD_LOGIC;
resend : IN STD_LOGIC;
config_finished : OUT STD_LOGIC;
sioc : OUT STD_LOGIC;
siod : INOUT STD_LOGIC;
reset : OUT STD_LOGIC;
pwdn : OUT STD_LOGIC;
xclk : OUT STD_LOGIC
);
END COMPONENT ov7670_controller;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clk CLK";
ATTRIBUTE X_INTERFACE_INFO OF reset: SIGNAL IS "xilinx.com:signal:reset:1.0 reset RST";
BEGIN
U0 : ov7670_controller
PORT MAP (
clk => clk,
resend => resend,
config_finished => config_finished,
sioc => sioc,
siod => siod,
reset => reset,
pwdn => pwdn,
xclk => xclk
);
END system_ov7670_controller_1_0_arch;
| mit |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_transform_test/zed_transform_test.srcs/sources_1/bd/system/ip/system_c_addsub_0_0/sim/system_c_addsub_0_0.vhd | 1 | 5365 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:c_addsub:12.0
-- IP Revision: 10
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY c_addsub_v12_0_10;
USE c_addsub_v12_0_10.c_addsub_v12_0_10;
ENTITY system_c_addsub_0_0 IS
PORT (
A : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
B : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
S : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END system_c_addsub_0_0;
ARCHITECTURE system_c_addsub_0_0_arch OF system_c_addsub_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_c_addsub_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT c_addsub_v12_0_10 IS
GENERIC (
C_VERBOSITY : INTEGER;
C_XDEVICEFAMILY : STRING;
C_IMPLEMENTATION : INTEGER;
C_A_WIDTH : INTEGER;
C_B_WIDTH : INTEGER;
C_OUT_WIDTH : INTEGER;
C_CE_OVERRIDES_SCLR : INTEGER;
C_A_TYPE : INTEGER;
C_B_TYPE : INTEGER;
C_LATENCY : INTEGER;
C_ADD_MODE : INTEGER;
C_B_CONSTANT : INTEGER;
C_B_VALUE : STRING;
C_AINIT_VAL : STRING;
C_SINIT_VAL : STRING;
C_CE_OVERRIDES_BYPASS : INTEGER;
C_BYPASS_LOW : INTEGER;
C_SCLR_OVERRIDES_SSET : INTEGER;
C_HAS_C_IN : INTEGER;
C_HAS_C_OUT : INTEGER;
C_BORROW_LOW : INTEGER;
C_HAS_CE : INTEGER;
C_HAS_BYPASS : INTEGER;
C_HAS_SCLR : INTEGER;
C_HAS_SSET : INTEGER;
C_HAS_SINIT : INTEGER
);
PORT (
A : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
B : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
CLK : IN STD_LOGIC;
ADD : IN STD_LOGIC;
C_IN : IN STD_LOGIC;
CE : IN STD_LOGIC;
BYPASS : IN STD_LOGIC;
SCLR : IN STD_LOGIC;
SSET : IN STD_LOGIC;
SINIT : IN STD_LOGIC;
C_OUT : OUT STD_LOGIC;
S : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END COMPONENT c_addsub_v12_0_10;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF A: SIGNAL IS "xilinx.com:signal:data:1.0 a_intf DATA";
ATTRIBUTE X_INTERFACE_INFO OF B: SIGNAL IS "xilinx.com:signal:data:1.0 b_intf DATA";
ATTRIBUTE X_INTERFACE_INFO OF S: SIGNAL IS "xilinx.com:signal:data:1.0 s_intf DATA";
BEGIN
U0 : c_addsub_v12_0_10
GENERIC MAP (
C_VERBOSITY => 0,
C_XDEVICEFAMILY => "zynq",
C_IMPLEMENTATION => 0,
C_A_WIDTH => 10,
C_B_WIDTH => 10,
C_OUT_WIDTH => 10,
C_CE_OVERRIDES_SCLR => 0,
C_A_TYPE => 0,
C_B_TYPE => 0,
C_LATENCY => 0,
C_ADD_MODE => 0,
C_B_CONSTANT => 0,
C_B_VALUE => "0000000000",
C_AINIT_VAL => "0",
C_SINIT_VAL => "0",
C_CE_OVERRIDES_BYPASS => 1,
C_BYPASS_LOW => 0,
C_SCLR_OVERRIDES_SSET => 1,
C_HAS_C_IN => 0,
C_HAS_C_OUT => 0,
C_BORROW_LOW => 1,
C_HAS_CE => 0,
C_HAS_BYPASS => 0,
C_HAS_SCLR => 0,
C_HAS_SSET => 0,
C_HAS_SINIT => 0
)
PORT MAP (
A => A,
B => B,
CLK => '0',
ADD => '1',
C_IN => '0',
CE => '1',
BYPASS => '0',
SCLR => '0',
SSET => '0',
SINIT => '0',
S => S
);
END system_c_addsub_0_0_arch;
| mit |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/ov7670_hessian_split/ov7670_hessian_split.srcs/sources_1/bd/system/ip/system_rgb888_to_rgb565_0_0/synth/system_rgb888_to_rgb565_0_0.vhd | 4 | 3795 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:rgb888_to_rgb565:1.0
-- IP Revision: 2
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_rgb888_to_rgb565_0_0 IS
PORT (
rgb_888 : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
rgb_565 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END system_rgb888_to_rgb565_0_0;
ARCHITECTURE system_rgb888_to_rgb565_0_0_arch OF system_rgb888_to_rgb565_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_rgb888_to_rgb565_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT rgb888_to_rgb565 IS
PORT (
rgb_888 : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
rgb_565 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END COMPONENT rgb888_to_rgb565;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF system_rgb888_to_rgb565_0_0_arch: ARCHITECTURE IS "rgb888_to_rgb565,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF system_rgb888_to_rgb565_0_0_arch : ARCHITECTURE IS "system_rgb888_to_rgb565_0_0,rgb888_to_rgb565,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF system_rgb888_to_rgb565_0_0_arch: ARCHITECTURE IS "system_rgb888_to_rgb565_0_0,rgb888_to_rgb565,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=user,x_ipName=rgb888_to_rgb565,x_ipVersion=1.0,x_ipCoreRevision=2,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED}";
BEGIN
U0 : rgb888_to_rgb565
PORT MAP (
rgb_888 => rgb_888,
rgb_565 => rgb_565
);
END system_rgb888_to_rgb565_0_0_arch;
| mit |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/ov7670_hessian_split/ov7670_hessian_split.srcs/sources_1/bd/system/ip/system_rgb888_to_rgb565_0_0_1/synth/system_rgb888_to_rgb565_0_0.vhd | 4 | 3795 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:rgb888_to_rgb565:1.0
-- IP Revision: 2
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_rgb888_to_rgb565_0_0 IS
PORT (
rgb_888 : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
rgb_565 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END system_rgb888_to_rgb565_0_0;
ARCHITECTURE system_rgb888_to_rgb565_0_0_arch OF system_rgb888_to_rgb565_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_rgb888_to_rgb565_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT rgb888_to_rgb565 IS
PORT (
rgb_888 : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
rgb_565 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END COMPONENT rgb888_to_rgb565;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF system_rgb888_to_rgb565_0_0_arch: ARCHITECTURE IS "rgb888_to_rgb565,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF system_rgb888_to_rgb565_0_0_arch : ARCHITECTURE IS "system_rgb888_to_rgb565_0_0,rgb888_to_rgb565,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF system_rgb888_to_rgb565_0_0_arch: ARCHITECTURE IS "system_rgb888_to_rgb565_0_0,rgb888_to_rgb565,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=user,x_ipName=rgb888_to_rgb565,x_ipVersion=1.0,x_ipCoreRevision=2,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED}";
BEGIN
U0 : rgb888_to_rgb565
PORT MAP (
rgb_888 => rgb_888,
rgb_565 => rgb_565
);
END system_rgb888_to_rgb565_0_0_arch;
| mit |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_transform_test/zed_transform_test.srcs/sources_1/bd/system/ipshared/0b31/zed_hdmi.vhd | 7 | 6019 | ----------------------------------------------------------------------------------
-- Authors: Mike Field <[email protected]>
-- Rob Taglang <[email protected]>
--
-- Create Date: 06:01:06 01/23/2013
-- Modified: 5/20/2017
--
-- Description:
-- Drive the ADV7511 HDMI encoder directly from the PL fabric.
-- Modified to fit modularly with other designs
--
-- Notes:
-- Technically, the ADV7511 supports rgb input formats, and it would
-- be really nice to be able to just drive that straight through.
-- Unfortunately, the pin mapping for hdmi_d maps to the [23-8] input
-- pins on the IC, and there is not rgb format that lies only in that
-- range of pins.
--
-- http://www.analog.com/media/en/technical-documentation/user-guides/ADV7511_Programming_Guide.pdf
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
Library UNISIM;
use UNISIM.vcomponents.all;
entity zed_hdmi is
port(
clk : in std_logic;
clk_x2 : in std_logic;
clk_100 : in std_logic;
active : in std_logic;
hsync : in std_logic;
vsync : in std_logic;
rgb888 : in std_logic_vector(23 downto 0);
hdmi_clk : out std_logic;
hdmi_hsync : out std_logic;
hdmi_vsync : out std_logic;
hdmi_d : out std_logic_vector(15 downto 0);
hdmi_de : out std_logic;
hdmi_scl : out std_logic;
hdmi_sda : inout std_logic
);
end zed_hdmi;
architecture Behavioral of zed_hdmi is
component i2c_sender
port(
clk : IN std_logic;
resend : IN std_logic;
siod : INOUT std_logic;
sioc : OUT std_logic
);
end component;
signal hdmi_clk_bits : STD_LOGIC_VECTOR (1 downto 0);
signal edge : std_logic := '0';
signal edge_rb : std_logic := '0';
signal r, g, b : std_logic_vector(7 downto 0);
signal y, cr, cb : std_logic_vector(7 downto 0);
begin
-- there is a 16 bit interface into the HDMI transmitter, although I only use 8 bits
r <= rgb888(23 downto 16);
g <= rgb888(15 downto 8);
b <= rgb888(7 downto 0);
hdmi_d(7 downto 0) <= x"00";
process(clk_x2)
variable y_hold, cr_hold, cb_hold : std_logic_vector(7 downto 0);
begin
---------------------------------------------------------------------------
-- signal generation for the HDMI encoder
--
-- Transfer on rising edge of clock Y
-- on falling edge of clock Either Cr or Cb
----------------------------------------------------------------------------
if rising_edge(clk_x2) then
if edge = '0' then
edge <= '1';
hdmi_clk_bits <= "11";
if edge_rb = '0' then
-- lock in value from conversion
y_hold := y;
cr_hold := cr;
cb_hold := cb;
end if;
if active = '0' then
hdmi_d(15 downto 8) <= (others => '0');
hdmi_de <= '0';
edge_rb <= '0';
else
hdmi_d(15 downto 8) <= y_hold;
hdmi_de <= '1';
end if;
else
edge <= '0';
hdmi_clk_bits <= "00";
if active = '0' then
hdmi_d(15 downto 8) <= (others => '0');
hdmi_de <= '0';
edge_rb <= '0';
else
if edge_rb = '0' then
hdmi_d(15 downto 8) <= cr_hold;
edge_rb <= '1';
else
hdmi_d(15 downto 8) <= cb_hold;
edge_rb <= '0';
end if;
hdmi_de <= '1';
end if;
end if;
hdmi_hsync <= not hsync;
hdmi_vsync <= not vsync;
end if;
end process;
process (clk)
variable r_int, g_int, b_int, y_int, cr_int, cb_int : integer;
begin
if rising_edge(clk) then
-- color space conversion and clamping
r_int := to_integer(unsigned(r));
g_int := to_integer(unsigned(g));
b_int := to_integer(unsigned(b));
y_int := ((r_int * 77) / 256) + ((g_int * 150) / 256) + ((b_int * 29) / 256);
cr_int := ((r_int * 131) / 256) - ((g_int * 110) / 256) - ((b_int * 21) / 256) + 128;
cb_int := -((r_int * 44) / 256) - ((g_int * 87) / 256) + ((b_int * 131) / 256) + 128;
end if;
if falling_edge(clk) then
if y_int > 255 then
y <= (others => '1');
elsif y_int < 0 then
y <= (others => '0');
else
y <= std_logic_vector(to_unsigned(y_int, 8));
end if;
if cr_int > 255 then
cr <= (others => '1');
elsif cr_int < 0 then
cr <= (others => '0');
else
cr <= std_logic_vector(to_unsigned(cr_int, 8));
end if;
if cb_int > 255 then
cb <= (others => '1');
elsif cb_int < 0 then
cb <= (others => '0');
else
cb <= std_logic_vector(to_unsigned(cb_int, 8));
end if;
end if;
end process;
ODDR_inst : ODDR
generic map(
DDR_CLK_EDGE => "OPPOSITE_EDGE", INIT => '0',SRTYPE => "SYNC")
port map (
Q => hdmi_clk,
C => clk_x2,
D1 => hdmi_clk_bits(0),
D2 => hdmi_clk_bits(1),
CE => '1', R => '0', S => '0'
);
Inst_i2c_sender: i2c_sender PORT MAP(
clk => clk_100,
resend => '0',
sioc => hdmi_scl,
siod => hdmi_sda
);
end Behavioral; | mit |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_camera_test/zed_camera_test.srcs/sources_1/bd/system/ipshared/0b31/zed_hdmi.vhd | 7 | 6019 | ----------------------------------------------------------------------------------
-- Authors: Mike Field <[email protected]>
-- Rob Taglang <[email protected]>
--
-- Create Date: 06:01:06 01/23/2013
-- Modified: 5/20/2017
--
-- Description:
-- Drive the ADV7511 HDMI encoder directly from the PL fabric.
-- Modified to fit modularly with other designs
--
-- Notes:
-- Technically, the ADV7511 supports rgb input formats, and it would
-- be really nice to be able to just drive that straight through.
-- Unfortunately, the pin mapping for hdmi_d maps to the [23-8] input
-- pins on the IC, and there is not rgb format that lies only in that
-- range of pins.
--
-- http://www.analog.com/media/en/technical-documentation/user-guides/ADV7511_Programming_Guide.pdf
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
Library UNISIM;
use UNISIM.vcomponents.all;
entity zed_hdmi is
port(
clk : in std_logic;
clk_x2 : in std_logic;
clk_100 : in std_logic;
active : in std_logic;
hsync : in std_logic;
vsync : in std_logic;
rgb888 : in std_logic_vector(23 downto 0);
hdmi_clk : out std_logic;
hdmi_hsync : out std_logic;
hdmi_vsync : out std_logic;
hdmi_d : out std_logic_vector(15 downto 0);
hdmi_de : out std_logic;
hdmi_scl : out std_logic;
hdmi_sda : inout std_logic
);
end zed_hdmi;
architecture Behavioral of zed_hdmi is
component i2c_sender
port(
clk : IN std_logic;
resend : IN std_logic;
siod : INOUT std_logic;
sioc : OUT std_logic
);
end component;
signal hdmi_clk_bits : STD_LOGIC_VECTOR (1 downto 0);
signal edge : std_logic := '0';
signal edge_rb : std_logic := '0';
signal r, g, b : std_logic_vector(7 downto 0);
signal y, cr, cb : std_logic_vector(7 downto 0);
begin
-- there is a 16 bit interface into the HDMI transmitter, although I only use 8 bits
r <= rgb888(23 downto 16);
g <= rgb888(15 downto 8);
b <= rgb888(7 downto 0);
hdmi_d(7 downto 0) <= x"00";
process(clk_x2)
variable y_hold, cr_hold, cb_hold : std_logic_vector(7 downto 0);
begin
---------------------------------------------------------------------------
-- signal generation for the HDMI encoder
--
-- Transfer on rising edge of clock Y
-- on falling edge of clock Either Cr or Cb
----------------------------------------------------------------------------
if rising_edge(clk_x2) then
if edge = '0' then
edge <= '1';
hdmi_clk_bits <= "11";
if edge_rb = '0' then
-- lock in value from conversion
y_hold := y;
cr_hold := cr;
cb_hold := cb;
end if;
if active = '0' then
hdmi_d(15 downto 8) <= (others => '0');
hdmi_de <= '0';
edge_rb <= '0';
else
hdmi_d(15 downto 8) <= y_hold;
hdmi_de <= '1';
end if;
else
edge <= '0';
hdmi_clk_bits <= "00";
if active = '0' then
hdmi_d(15 downto 8) <= (others => '0');
hdmi_de <= '0';
edge_rb <= '0';
else
if edge_rb = '0' then
hdmi_d(15 downto 8) <= cr_hold;
edge_rb <= '1';
else
hdmi_d(15 downto 8) <= cb_hold;
edge_rb <= '0';
end if;
hdmi_de <= '1';
end if;
end if;
hdmi_hsync <= not hsync;
hdmi_vsync <= not vsync;
end if;
end process;
process (clk)
variable r_int, g_int, b_int, y_int, cr_int, cb_int : integer;
begin
if rising_edge(clk) then
-- color space conversion and clamping
r_int := to_integer(unsigned(r));
g_int := to_integer(unsigned(g));
b_int := to_integer(unsigned(b));
y_int := ((r_int * 77) / 256) + ((g_int * 150) / 256) + ((b_int * 29) / 256);
cr_int := ((r_int * 131) / 256) - ((g_int * 110) / 256) - ((b_int * 21) / 256) + 128;
cb_int := -((r_int * 44) / 256) - ((g_int * 87) / 256) + ((b_int * 131) / 256) + 128;
end if;
if falling_edge(clk) then
if y_int > 255 then
y <= (others => '1');
elsif y_int < 0 then
y <= (others => '0');
else
y <= std_logic_vector(to_unsigned(y_int, 8));
end if;
if cr_int > 255 then
cr <= (others => '1');
elsif cr_int < 0 then
cr <= (others => '0');
else
cr <= std_logic_vector(to_unsigned(cr_int, 8));
end if;
if cb_int > 255 then
cb <= (others => '1');
elsif cb_int < 0 then
cb <= (others => '0');
else
cb <= std_logic_vector(to_unsigned(cb_int, 8));
end if;
end if;
end process;
ODDR_inst : ODDR
generic map(
DDR_CLK_EDGE => "OPPOSITE_EDGE", INIT => '0',SRTYPE => "SYNC")
port map (
Q => hdmi_clk,
C => clk_x2,
D1 => hdmi_clk_bits(0),
D2 => hdmi_clk_bits(1),
CE => '1', R => '0', S => '0'
);
Inst_i2c_sender: i2c_sender PORT MAP(
clk => clk_100,
resend => '0',
sioc => hdmi_scl,
siod => hdmi_sda
);
end Behavioral; | mit |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_dual_fusion/zed_dual_fusion.srcs/sources_1/bd/system/ipshared/1d19/hdl/util_vector_logic.vhd | 7 | 6359 | -------------------------------------------------------------------------------
-- $Id: util_vector_logic.vhd,v 2.0 2014/10/03 04:52:57 abq_ip Exp $
-------------------------------------------------------------------------------
-- util_vector_logic.vhd - Entity and architecture
--
-- ***************************************************************************
-- ** Copyright(C) 2003 by Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This text contains proprietary, confidential **
-- ** information of Xilinx, Inc. , is distributed by **
-- ** under license from Xilinx, Inc., and may be used, **
-- ** copied and/or disclosed only pursuant to the terms **
-- ** of a valid license agreement with Xilinx, Inc. **
-- ** **
-- ** Unmodified source code is guaranteed to place and route, **
-- ** function and run at speed according to the datasheet **
-- ** specification. Source code is provided "as-is", with no **
-- ** obligation on the part of Xilinx to provide support. **
-- ** **
-- ** Xilinx Hotline support of source code IP shall only include **
-- ** standard level Xilinx Hotline support, and will only address **
-- ** issues and questions related to the standard released Netlist **
-- ** version of the core (and thus indirectly, the original core source). **
-- ** **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Support Hotline will only be able **
-- ** to confirm the problem in the Netlist version of the core. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: util_vector_logic.vhd
--
-- Description:
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- util_vector_logic.vhd
--
-------------------------------------------------------------------------------
-- Author: goran
-- Revision: $Revision: 1.1 $
-- Date: $Date: 2003/10/03 04:52:57 $
--
-- History:
-- goran 2003-06-06 First Version
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity util_vector_logic is
generic (
C_OPERATION : string := "and";
C_SIZE : integer := 8
);
port (
Op1 : in std_logic_vector(C_SIZE-1 downto 0);
Op2 : in std_logic_vector(C_SIZE-1 downto 0);
Res : out std_logic_vector(C_SIZE-1 downto 0)
);
end util_vector_logic;
architecture IMP of util_vector_logic is
function LowerCase_Char(char : character) return character is
begin
-- If char is not an upper case letter then return char
if char < 'A' or char > 'Z' then
return char;
end if;
-- Otherwise map char to its corresponding lower case character and
-- return that
case char is
when 'A' => return 'a'; when 'B' => return 'b'; when 'C' => return 'c'; when 'D' => return 'd';
when 'E' => return 'e'; when 'F' => return 'f'; when 'G' => return 'g'; when 'H' => return 'h';
when 'I' => return 'i'; when 'J' => return 'j'; when 'K' => return 'k'; when 'L' => return 'l';
when 'M' => return 'm'; when 'N' => return 'n'; when 'O' => return 'o'; when 'P' => return 'p';
when 'Q' => return 'q'; when 'R' => return 'r'; when 'S' => return 's'; when 'T' => return 't';
when 'U' => return 'u'; when 'V' => return 'v'; when 'W' => return 'w'; when 'X' => return 'x';
when 'Y' => return 'y'; when 'Z' => return 'z';
when others => return char;
end case;
end LowerCase_Char;
function LowerCase_String (s : string) return string is
variable res : string(s'range);
begin -- function LoweerCase_String
for I in s'range loop
res(I) := LowerCase_Char(s(I));
end loop; -- I
return res;
end function LowerCase_String;
constant C_Oper : string := LowerCase_String(C_OPERATION);
begin
Use_AND: if (C_Oper = "and") generate
res <= Op1 and Op2;
end generate Use_AND;
Use_OR: if (C_Oper = "or") generate
res <= Op1 or Op2;
end generate Use_OR;
Use_XOR: if (C_Oper = "xor") generate
res <= Op1 xor Op2;
end generate Use_XOR;
Use_NOT: if (C_Oper = "not") generate
res <= NOT Op1;
end generate Use_NOT;
end IMP;
| mit |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_dual_camera_test/zed_dual_camera_test.srcs/sources_1/bd/system/ipshared/1d19/hdl/util_vector_logic.vhd | 7 | 6359 | -------------------------------------------------------------------------------
-- $Id: util_vector_logic.vhd,v 2.0 2014/10/03 04:52:57 abq_ip Exp $
-------------------------------------------------------------------------------
-- util_vector_logic.vhd - Entity and architecture
--
-- ***************************************************************************
-- ** Copyright(C) 2003 by Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This text contains proprietary, confidential **
-- ** information of Xilinx, Inc. , is distributed by **
-- ** under license from Xilinx, Inc., and may be used, **
-- ** copied and/or disclosed only pursuant to the terms **
-- ** of a valid license agreement with Xilinx, Inc. **
-- ** **
-- ** Unmodified source code is guaranteed to place and route, **
-- ** function and run at speed according to the datasheet **
-- ** specification. Source code is provided "as-is", with no **
-- ** obligation on the part of Xilinx to provide support. **
-- ** **
-- ** Xilinx Hotline support of source code IP shall only include **
-- ** standard level Xilinx Hotline support, and will only address **
-- ** issues and questions related to the standard released Netlist **
-- ** version of the core (and thus indirectly, the original core source). **
-- ** **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Support Hotline will only be able **
-- ** to confirm the problem in the Netlist version of the core. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: util_vector_logic.vhd
--
-- Description:
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- util_vector_logic.vhd
--
-------------------------------------------------------------------------------
-- Author: goran
-- Revision: $Revision: 1.1 $
-- Date: $Date: 2003/10/03 04:52:57 $
--
-- History:
-- goran 2003-06-06 First Version
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity util_vector_logic is
generic (
C_OPERATION : string := "and";
C_SIZE : integer := 8
);
port (
Op1 : in std_logic_vector(C_SIZE-1 downto 0);
Op2 : in std_logic_vector(C_SIZE-1 downto 0);
Res : out std_logic_vector(C_SIZE-1 downto 0)
);
end util_vector_logic;
architecture IMP of util_vector_logic is
function LowerCase_Char(char : character) return character is
begin
-- If char is not an upper case letter then return char
if char < 'A' or char > 'Z' then
return char;
end if;
-- Otherwise map char to its corresponding lower case character and
-- return that
case char is
when 'A' => return 'a'; when 'B' => return 'b'; when 'C' => return 'c'; when 'D' => return 'd';
when 'E' => return 'e'; when 'F' => return 'f'; when 'G' => return 'g'; when 'H' => return 'h';
when 'I' => return 'i'; when 'J' => return 'j'; when 'K' => return 'k'; when 'L' => return 'l';
when 'M' => return 'm'; when 'N' => return 'n'; when 'O' => return 'o'; when 'P' => return 'p';
when 'Q' => return 'q'; when 'R' => return 'r'; when 'S' => return 's'; when 'T' => return 't';
when 'U' => return 'u'; when 'V' => return 'v'; when 'W' => return 'w'; when 'X' => return 'x';
when 'Y' => return 'y'; when 'Z' => return 'z';
when others => return char;
end case;
end LowerCase_Char;
function LowerCase_String (s : string) return string is
variable res : string(s'range);
begin -- function LoweerCase_String
for I in s'range loop
res(I) := LowerCase_Char(s(I));
end loop; -- I
return res;
end function LowerCase_String;
constant C_Oper : string := LowerCase_String(C_OPERATION);
begin
Use_AND: if (C_Oper = "and") generate
res <= Op1 and Op2;
end generate Use_AND;
Use_OR: if (C_Oper = "or") generate
res <= Op1 or Op2;
end generate Use_OR;
Use_XOR: if (C_Oper = "xor") generate
res <= Op1 xor Op2;
end generate Use_XOR;
Use_NOT: if (C_Oper = "not") generate
res <= NOT Op1;
end generate Use_NOT;
end IMP;
| mit |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_dual_fusion/zed_dual_fusion.srcs/sources_1/bd/system/ip/system_ov7670_controller_1_0/synth/system_ov7670_controller_1_0.vhd | 2 | 4423 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:ov7670_controller:1.0
-- IP Revision: 9
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_ov7670_controller_1_0 IS
PORT (
clk : IN STD_LOGIC;
resend : IN STD_LOGIC;
config_finished : OUT STD_LOGIC;
sioc : OUT STD_LOGIC;
siod : INOUT STD_LOGIC;
reset : OUT STD_LOGIC;
pwdn : OUT STD_LOGIC;
xclk : OUT STD_LOGIC
);
END system_ov7670_controller_1_0;
ARCHITECTURE system_ov7670_controller_1_0_arch OF system_ov7670_controller_1_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_ov7670_controller_1_0_arch: ARCHITECTURE IS "yes";
COMPONENT ov7670_controller IS
PORT (
clk : IN STD_LOGIC;
resend : IN STD_LOGIC;
config_finished : OUT STD_LOGIC;
sioc : OUT STD_LOGIC;
siod : INOUT STD_LOGIC;
reset : OUT STD_LOGIC;
pwdn : OUT STD_LOGIC;
xclk : OUT STD_LOGIC
);
END COMPONENT ov7670_controller;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF system_ov7670_controller_1_0_arch: ARCHITECTURE IS "ov7670_controller,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF system_ov7670_controller_1_0_arch : ARCHITECTURE IS "system_ov7670_controller_1_0,ov7670_controller,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF system_ov7670_controller_1_0_arch: ARCHITECTURE IS "system_ov7670_controller_1_0,ov7670_controller,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=user,x_ipName=ov7670_controller,x_ipVersion=1.0,x_ipCoreRevision=9,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clk CLK";
ATTRIBUTE X_INTERFACE_INFO OF reset: SIGNAL IS "xilinx.com:signal:reset:1.0 reset RST";
BEGIN
U0 : ov7670_controller
PORT MAP (
clk => clk,
resend => resend,
config_finished => config_finished,
sioc => sioc,
siod => siod,
reset => reset,
pwdn => pwdn,
xclk => xclk
);
END system_ov7670_controller_1_0_arch;
| mit |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/affine_transform_demo/affine_transform_demo.srcs/sources_1/bd/system/ip/system_vga_sync_0_0/sim/system_vga_sync_0_0.vhd | 3 | 4025 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:vga_sync:1.0
-- IP Revision: 5
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_vga_sync_0_0 IS
PORT (
clk_25 : IN STD_LOGIC;
rst : IN STD_LOGIC;
active : OUT STD_LOGIC;
hsync : OUT STD_LOGIC;
vsync : OUT STD_LOGIC;
xaddr : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
yaddr : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END system_vga_sync_0_0;
ARCHITECTURE system_vga_sync_0_0_arch OF system_vga_sync_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_vga_sync_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT vga_sync IS
GENERIC (
H_SIZE : INTEGER;
H_FRONT_DELAY : INTEGER;
H_BACK_DELAY : INTEGER;
H_RETRACE_DELAY : INTEGER;
V_SIZE : INTEGER;
V_FRONT_DELAY : INTEGER;
V_BACK_DELAY : INTEGER;
V_RETRACE_DELAY : INTEGER
);
PORT (
clk_25 : IN STD_LOGIC;
rst : IN STD_LOGIC;
active : OUT STD_LOGIC;
hsync : OUT STD_LOGIC;
vsync : OUT STD_LOGIC;
xaddr : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
yaddr : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END COMPONENT vga_sync;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF rst: SIGNAL IS "xilinx.com:signal:reset:1.0 rst RST";
BEGIN
U0 : vga_sync
GENERIC MAP (
H_SIZE => 640,
H_FRONT_DELAY => 16,
H_BACK_DELAY => 48,
H_RETRACE_DELAY => 96,
V_SIZE => 480,
V_FRONT_DELAY => 10,
V_BACK_DELAY => 33,
V_RETRACE_DELAY => 2
)
PORT MAP (
clk_25 => clk_25,
rst => rst,
active => active,
hsync => hsync,
vsync => vsync,
xaddr => xaddr,
yaddr => yaddr
);
END system_vga_sync_0_0_arch;
| mit |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_dual_camera_test/zed_dual_camera_test.srcs/sources_1/bd/system/ip/system_rgb565_to_rgb888_1_0/system_rgb565_to_rgb888_1_0_stub.vhdl | 1 | 1402 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Thu May 25 15:27:56 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub -rename_top system_rgb565_to_rgb888_1_0 -prefix
-- system_rgb565_to_rgb888_1_0_ system_rgb565_to_rgb888_0_0_stub.vhdl
-- Design : system_rgb565_to_rgb888_0_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity system_rgb565_to_rgb888_1_0 is
Port (
clk : in STD_LOGIC;
rgb_565 : in STD_LOGIC_VECTOR ( 15 downto 0 );
rgb_888 : out STD_LOGIC_VECTOR ( 23 downto 0 )
);
end system_rgb565_to_rgb888_1_0;
architecture stub of system_rgb565_to_rgb888_1_0 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clk,rgb_565[15:0],rgb_888[23:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "rgb565_to_rgb888,Vivado 2016.4";
begin
end;
| mit |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_transform_test/zed_transform_test.srcs/sources_1/bd/system/ip/system_vga_sync_ref_0_0/synth/system_vga_sync_ref_0_0.vhd | 5 | 4637 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:vga_sync_ref:1.0
-- IP Revision: 65
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_vga_sync_ref_0_0 IS
PORT (
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
hsync : IN STD_LOGIC;
vsync : IN STD_LOGIC;
start : OUT STD_LOGIC;
active : OUT STD_LOGIC;
xaddr : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
yaddr : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END system_vga_sync_ref_0_0;
ARCHITECTURE system_vga_sync_ref_0_0_arch OF system_vga_sync_ref_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_vga_sync_ref_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT vga_sync_ref IS
GENERIC (
H_SIZE : INTEGER;
H_SYNC_SIZE : INTEGER;
V_SIZE : INTEGER;
DELAY : INTEGER
);
PORT (
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
hsync : IN STD_LOGIC;
vsync : IN STD_LOGIC;
start : OUT STD_LOGIC;
active : OUT STD_LOGIC;
xaddr : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
yaddr : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END COMPONENT vga_sync_ref;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF system_vga_sync_ref_0_0_arch: ARCHITECTURE IS "vga_sync_ref,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF system_vga_sync_ref_0_0_arch : ARCHITECTURE IS "system_vga_sync_ref_0_0,vga_sync_ref,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF system_vga_sync_ref_0_0_arch: ARCHITECTURE IS "system_vga_sync_ref_0_0,vga_sync_ref,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=user,x_ipName=vga_sync_ref,x_ipVersion=1.0,x_ipCoreRevision=65,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,H_SIZE=640,H_SYNC_SIZE=144,V_SIZE=480,DELAY=2}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clk CLK";
ATTRIBUTE X_INTERFACE_INFO OF rst: SIGNAL IS "xilinx.com:signal:reset:1.0 rst RST";
BEGIN
U0 : vga_sync_ref
GENERIC MAP (
H_SIZE => 640,
H_SYNC_SIZE => 144,
V_SIZE => 480,
DELAY => 2
)
PORT MAP (
clk => clk,
rst => rst,
hsync => hsync,
vsync => vsync,
start => start,
active => active,
xaddr => xaddr,
yaddr => yaddr
);
END system_vga_sync_ref_0_0_arch;
| mit |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | general_ip/svd_2x2/svd_2x2.srcs/sources_1/ip/sqrt/synth/sqrt.vhd | 1 | 8353 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:cordic:6.0
-- IP Revision: 11
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY cordic_v6_0_11;
USE cordic_v6_0_11.cordic_v6_0_11;
ENTITY sqrt IS
PORT (
aclk : IN STD_LOGIC;
s_axis_cartesian_tvalid : IN STD_LOGIC;
s_axis_cartesian_tdata : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
m_axis_dout_tvalid : OUT STD_LOGIC;
m_axis_dout_tdata : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END sqrt;
ARCHITECTURE sqrt_arch OF sqrt IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF sqrt_arch: ARCHITECTURE IS "yes";
COMPONENT cordic_v6_0_11 IS
GENERIC (
C_ARCHITECTURE : INTEGER;
C_CORDIC_FUNCTION : INTEGER;
C_COARSE_ROTATE : INTEGER;
C_DATA_FORMAT : INTEGER;
C_XDEVICEFAMILY : STRING;
C_HAS_ACLKEN : INTEGER;
C_HAS_ACLK : INTEGER;
C_HAS_S_AXIS_CARTESIAN : INTEGER;
C_HAS_S_AXIS_PHASE : INTEGER;
C_HAS_ARESETN : INTEGER;
C_INPUT_WIDTH : INTEGER;
C_ITERATIONS : INTEGER;
C_OUTPUT_WIDTH : INTEGER;
C_PHASE_FORMAT : INTEGER;
C_PIPELINE_MODE : INTEGER;
C_PRECISION : INTEGER;
C_ROUND_MODE : INTEGER;
C_SCALE_COMP : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_HAS_S_AXIS_PHASE_TUSER : INTEGER;
C_HAS_S_AXIS_PHASE_TLAST : INTEGER;
C_S_AXIS_PHASE_TDATA_WIDTH : INTEGER;
C_S_AXIS_PHASE_TUSER_WIDTH : INTEGER;
C_HAS_S_AXIS_CARTESIAN_TUSER : INTEGER;
C_HAS_S_AXIS_CARTESIAN_TLAST : INTEGER;
C_S_AXIS_CARTESIAN_TDATA_WIDTH : INTEGER;
C_S_AXIS_CARTESIAN_TUSER_WIDTH : INTEGER;
C_M_AXIS_DOUT_TDATA_WIDTH : INTEGER;
C_M_AXIS_DOUT_TUSER_WIDTH : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_phase_tvalid : IN STD_LOGIC;
s_axis_phase_tready : OUT STD_LOGIC;
s_axis_phase_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_phase_tlast : IN STD_LOGIC;
s_axis_phase_tdata : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
s_axis_cartesian_tvalid : IN STD_LOGIC;
s_axis_cartesian_tready : OUT STD_LOGIC;
s_axis_cartesian_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_cartesian_tlast : IN STD_LOGIC;
s_axis_cartesian_tdata : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
m_axis_dout_tvalid : OUT STD_LOGIC;
m_axis_dout_tready : IN STD_LOGIC;
m_axis_dout_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_dout_tlast : OUT STD_LOGIC;
m_axis_dout_tdata : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END COMPONENT cordic_v6_0_11;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF sqrt_arch: ARCHITECTURE IS "cordic_v6_0_11,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF sqrt_arch : ARCHITECTURE IS "sqrt,cordic_v6_0_11,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF sqrt_arch: ARCHITECTURE IS "sqrt,cordic_v6_0_11,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=cordic,x_ipVersion=6.0,x_ipCoreRevision=11,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_ARCHITECTURE=2,C_CORDIC_FUNCTION=6,C_COARSE_ROTATE=0,C_DATA_FORMAT=1,C_XDEVICEFAMILY=zynq,C_HAS_ACLKEN=0,C_HAS_ACLK=1,C_HAS_S_AXIS_CARTESIAN=1,C_HAS_S_AXIS_PHASE=0,C_HAS_ARESETN=0,C_INPUT_WIDTH=16,C_ITERATIONS=0,C_OUTPUT_WIDTH=16,C_PHASE_FORMAT=0,C_PIPELINE_MODE=-2,C_PRECISION=0,C_ROUND_MODE=0,C_SCALE_COMP=0,C_THROTTLE_S" &
"CHEME=3,C_TLAST_RESOLUTION=0,C_HAS_S_AXIS_PHASE_TUSER=0,C_HAS_S_AXIS_PHASE_TLAST=0,C_S_AXIS_PHASE_TDATA_WIDTH=16,C_S_AXIS_PHASE_TUSER_WIDTH=1,C_HAS_S_AXIS_CARTESIAN_TUSER=0,C_HAS_S_AXIS_CARTESIAN_TLAST=0,C_S_AXIS_CARTESIAN_TDATA_WIDTH=16,C_S_AXIS_CARTESIAN_TUSER_WIDTH=1,C_M_AXIS_DOUT_TDATA_WIDTH=16,C_M_AXIS_DOUT_TUSER_WIDTH=1}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_cartesian_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_CARTESIAN TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_cartesian_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_CARTESIAN TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_dout_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DOUT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_dout_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DOUT TDATA";
BEGIN
U0 : cordic_v6_0_11
GENERIC MAP (
C_ARCHITECTURE => 2,
C_CORDIC_FUNCTION => 6,
C_COARSE_ROTATE => 0,
C_DATA_FORMAT => 1,
C_XDEVICEFAMILY => "zynq",
C_HAS_ACLKEN => 0,
C_HAS_ACLK => 1,
C_HAS_S_AXIS_CARTESIAN => 1,
C_HAS_S_AXIS_PHASE => 0,
C_HAS_ARESETN => 0,
C_INPUT_WIDTH => 16,
C_ITERATIONS => 0,
C_OUTPUT_WIDTH => 16,
C_PHASE_FORMAT => 0,
C_PIPELINE_MODE => -2,
C_PRECISION => 0,
C_ROUND_MODE => 0,
C_SCALE_COMP => 0,
C_THROTTLE_SCHEME => 3,
C_TLAST_RESOLUTION => 0,
C_HAS_S_AXIS_PHASE_TUSER => 0,
C_HAS_S_AXIS_PHASE_TLAST => 0,
C_S_AXIS_PHASE_TDATA_WIDTH => 16,
C_S_AXIS_PHASE_TUSER_WIDTH => 1,
C_HAS_S_AXIS_CARTESIAN_TUSER => 0,
C_HAS_S_AXIS_CARTESIAN_TLAST => 0,
C_S_AXIS_CARTESIAN_TDATA_WIDTH => 16,
C_S_AXIS_CARTESIAN_TUSER_WIDTH => 1,
C_M_AXIS_DOUT_TDATA_WIDTH => 16,
C_M_AXIS_DOUT_TUSER_WIDTH => 1
)
PORT MAP (
aclk => aclk,
aclken => '1',
aresetn => '1',
s_axis_phase_tvalid => '0',
s_axis_phase_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_phase_tlast => '0',
s_axis_phase_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 16)),
s_axis_cartesian_tvalid => s_axis_cartesian_tvalid,
s_axis_cartesian_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_cartesian_tlast => '0',
s_axis_cartesian_tdata => s_axis_cartesian_tdata,
m_axis_dout_tvalid => m_axis_dout_tvalid,
m_axis_dout_tready => '0',
m_axis_dout_tdata => m_axis_dout_tdata
);
END sqrt_arch;
| mit |
SoCdesign/audiomixer | ZedBoard_Linux_Design/hw/xps_proj/pcores/filter_v1_00_a/hdl/vhdl/IIR_Biquad_1.vhd | 3 | 27481 | --////////////////////// IIR_Biquad_I //////////////////////////////////--
-- ***********************************************************************
-- FileName: IIR_Biquad_1.vhd
-- FPGA: Xilinx Spartan 6
-- IDE: Xilinx ISE 13.1
--
-- HDL IS PROVIDED "AS IS." DIGI-KEY EXPRESSLY DISCLAIMS ANY
-- WARRANTY OF ANY KIND, WHETHER EXPRESS OR IMPLIED, INCLUDING BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
-- PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL DIGI-KEY
-- BE LIABLE FOR ANY INCIDENTAL, SPECIAL, INDIRECT OR CONSEQUENTIAL
-- DAMAGES, LOST PROFITS OR LOST DATA, HARM TO YOUR EQUIPMENT, COST OF
-- PROCUREMENT OF SUBSTITUTE GOODS, TECHNOLOGY OR SERVICES, ANY CLAIMS
-- BY THIRD PARTIES (INCLUDING BUT NOT LIMITED TO ANY DEFENSE THEREOF),
-- ANY CLAIMS FOR INDEMNITY OR CONTRIBUTION, OR OTHER SIMILAR COSTS.
-- DIGI-KEY ALSO DISCLAIMS ANY LIABILITY FOR PATENT OR COPYRIGHT
-- INFRINGEMENT.
--
-- Version History
-- Version 1.0 7/31/2012 Tony Storey
-- Initial Public Releaselibrary ieee;
-- This biquad is set up for 18 bit input words with 32 bit coefficients
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity IIR_Biquad is
Port (
clk : in STD_LOGIC;
n_reset : in STD_LOGIC;
sample_trig : in STD_LOGIC;
X_in : in STD_LOGIC_VECTOR (23 downto 0);
filter_done : out STD_LOGIC;
Y_out : out STD_LOGIC_VECTOR (23 downto 0)
);
end IIR_Biquad;
architecture arch of IIR_Biquad is
-- -- Used Bilinear Z Transform
-- band stop butterworth 2nd order fo = 59.79, fl = 55Hz, fu = 65Hz, Fs = 48000Hz, PBR = .08 dB, SBR = .03 dB
--------------------------------------------------------------------------
--
-- b0 + b1*Z^-1 + b2*Z^-2
-- H[z] = -------------------------
-- 1 + a1*Z^-1 + a2*Z^-2
--
--------------------------------------------------------------------------
-- define biquad coefficients WORKED WITH HIGH SOUND
constant Coef_b0 : std_logic_vector(31 downto 0) := B"00_00_1110_0011_1110_0101_0110_0111_1100"; -- b0 ~ +0.2225548
constant Coef_b1 : std_logic_vector(31 downto 0) := B"00_01_1100_0111_1100_1010_1100_1000_1110"; -- b1 ~ +0.4451095
constant Coef_b2 : std_logic_vector(31 downto 0) := B"00_00_1110_0011_1110_0101_0110_0111_1100"; -- b2 ~ +0.2225548
constant Coef_a1 : std_logic_vector(31 downto 0) := B"11_10_1010_0110_1001_1101_0101_0001_1011"; -- a1 ~ -0.3372905
constant Coef_a2 : std_logic_vector(31 downto 0) := B"00_01_0011_1000_0011_1100_1110_1100_0001"; -- a2 ~ +0.3049199
-- Pre Generated Example IIR filters
-------------------------------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------------------------------------
-- -- band pass 2nd order butterworth f0 = 2000Hz, fl = 1500Hz, fu = 2500 Fs = 48000Hz, PBR = .08 dB, SBR = .03 dB
-- --------------------------------------------------------------------------
----
---- b0 + b1*Z^-1 + b2*Z^-2
---- H[z] = -------------------------
---- 1 + a1*Z^-1 + a2*Z^-2
----
-- --------------------------------------------------------------------------
--
-- define biquad coefficients -- DID NOT WORK NO SOUND
-- constant Coef_b0 : std_logic_vector(31 downto 0) := B"00_00_0011_1110_1111_1100_1111_0000_1111"; -- b0 ~ +0.061511769
-- constant Coef_b1 : std_logic_vector(31 downto 0) := B"00_00_0000_0000_0000_0000_0000_0000_0000"; -- b1 ~ 0.0
-- constant Coef_b2 : std_logic_vector(31 downto 0) := B"11_11_1100_0001_0000_0011_0000_1111_0001"; -- b0 ~ -0.061511769
--
-- constant Coef_a1 : std_logic_vector(31 downto 0) := B"10_00_1011_1011_0111_1011_1110_0101_0111"; -- a1 ~ -1.816910185
-- constant Coef_a2 : std_logic_vector(31 downto 0) := B"00_11_1000_0010_0000_0110_0001_1110_0010"; -- a2 ~ +0.876976463
-- -- low pass 2nd order butt fl = 500Hz, Fs = 48000Hz, PBR = .08 dB, SBR = .03 dB
-- --------------------------------------------------------------------------
----
---- b0 + b1*Z^-1 + b2*Z^-2
---- H[z] = -------------------------
---- 1 + a1*Z^-1 + a2*Z^-2
----
-- --------------------------------------------------------------------------
--
-- -- define biquad coefficients WORKED BUT VERY LOW SOUND
-- constant Coef_b0 : std_logic_vector(31 downto 0) := B"00_00_0000_0001_0000_1100_0011_1001_1100"; -- b0 ~ +0.0010232
-- constant Coef_b1 : std_logic_vector(31 downto 0) := B"00_00_0000_0010_0001_1000_0111_0011_1001"; -- b1 ~ +0.0020464
-- constant Coef_b2 : std_logic_vector(31 downto 0) := B"00_00_0000_0001_0000_1100_0011_1001_1100"; -- b2 ~ +0.0010232
--
-- constant Coef_a1 : std_logic_vector(31 downto 0) := B"10_00_0101_1110_1011_0111_1110_0110_1000"; -- a1 ~ -1.9075016
-- constant Coef_a2 : std_logic_vector(31 downto 0) := B"00_11_1010_0101_0111_1001_0000_0111_0101"; -- a2 ~ +0.9115945
---- -- stop band 2nd order cheb f0 = 2828.47, Hz, fl = 2000Hz, fu = 4000Hz, Fs = 48000Hz, PBR = .08 dB, SBR = .03 dB
---- --------------------------------------------------------------------------
----
---- b0 + b1*Z^-1 + b2*Z^-2
---- H[z] = -------------------------
---- 1 + a1*Z^-1 + a2*Z^-2
----
---- --------------------------------------------------------------------------
----
---- define biquad coefficients -- WORKED WITH AVERAGE SOUND
-- constant Coef_b0 : std_logic_vector(31 downto 0) := B"00_11_1000_1000_1101_1111_0001_1100_0110"; -- b0 ~ +0.8836636
-- constant Coef_b1 : std_logic_vector(31 downto 0) := B"10_01_0110_1001_1001_0110_1000_0001_1011"; -- b1 ~ -1.6468868
-- constant Coef_b2 : std_logic_vector(31 downto 0) := B"00_11_1000_1000_1101_1111_0001_1100_0110"; -- b2 ~ +0.8836636
--
-- constant Coef_a1 : std_logic_vector(31 downto 0) := B"10_01_0110_1001_1001_0110_1000_0001_1011"; -- a1 ~ -1.6468868
-- constant Coef_a2 : std_logic_vector(31 downto 0) := B"00_11_0001_0001_1011_1110_0011_1000_1011"; -- a2 ~ +0.7673272
-- -- band pass 2nd order elliptical fl= 2000Hz, fu = 2500Hz, Fs = 48000Hz, PBR = .08 dB, SBR = .03 dB
-- --------------------------------------------------------------------------
----
---- b0 + b1*Z^-1 + b2*Z^-2
---- H[z] = -------------------------
---- 1 + a1*Z^-1 + a2*Z^-2
----
-- --------------------------------------------------------------------------
--
---- define biquad coefficients --DID NOT WORK NO SOUND
-- constant Coef_b0 : std_logic_vector(31 downto 0) := B"00_00_0100_1001_0001_0011_0101_0100_0111"; -- b0 ~ +0.0713628
-- constant Coef_b1 : std_logic_vector(31 downto 0) := B"00_00_0000_0000_0000_0000_0000_0000_0000"; -- b1 ~ +0.0
-- constant Coef_b2 : std_logic_vector(31 downto 0) := B"11_11_1011_0110_1110_1100_1010_1011_1000"; -- b2 ~ -0.0713628
--
-- constant Coef_a1 : std_logic_vector(31 downto 0) := B"10_00_1110_0011_0001_0001_1010_1011_1111"; -- a1 ~ -1.7782529**
-- constant Coef_a2 : std_logic_vector(31 downto 0) := B"00_11_0110_1101_1101_1001_0101_0111_0001"; -- a2 ~ +0.8572744
-- -- Used Bilinear Z Transform
-- -- low pass 2nd order butterworth fc = 12000Hz, Fs = 48000Hz, PBR = .08 dB, SBR = .03 dB
-- --------------------------------------------------------------------------
----
---- b0 + b1*Z^-1 + b2*Z^-2
---- H[z] = -------------------------
---- 1 + a1*Z^-1 + a2*Z^-2
----
-- --------------------------------------------------------------------------
--
---- define biquad coefficients WORKED WITH HIGH SOUND
-- constant Coef_b0 : std_logic_vector(31 downto 0) := B"00_01_0010_1011_1110_1100_0011_0011_0011"; -- b0 ~ +0.292893219
-- constant Coef_b1 : std_logic_vector(31 downto 0) := B"00_10_0101_0111_1101_1000_0110_0110_0110"; -- b1 ~ +0.585786438
-- constant Coef_b2 : std_logic_vector(31 downto 0) := B"00_01_0010_1011_1110_1100_0011_0011_0011"; -- b2 ~ +0.292893219
--
-- constant Coef_a1 : std_logic_vector(31 downto 0) := B"00_00_0000_0000_0000_0000_0000_0000_0000"; -- a1 ~ 0.0
-- constant Coef_a2 : std_logic_vector(31 downto 0) := B"00_00_0000_0000_0000_0101_0111_1101_1000"; -- a2 ~ +0.171572875***
-- -- band stop butterworth 2nd order fo = 59.79, fl = 55Hz, fu = 65Hz, Fs = 48000Hz, PBR = .08 dB, SBR = .03 dB
-- --------------------------------------------------------------------------
----
---- b0 + b1*Z^-1 + b2*Z^-2
---- H[z] = -------------------------
---- 1 + a1*Z^-1 + a2*Z^-2
----
-- --------------------------------------------------------------------------
--
-- -- define biquad coefficients DID NOT WORK NO SOUND
-- constant Coef_b0 : std_logic_vector(31 downto 0) := B"00_11_1111_1111_0101_0100_1000_1000_0001"; -- b0 ~ +0.9993459
-- constant Coef_b1 : std_logic_vector(31 downto 0) := B"10_00_0000_0001_0110_0110_1111_1010_1110"; -- b1 ~ -1.9986306
-- constant Coef_b2 : std_logic_vector(31 downto 0) := B"00_11_1111_1111_0101_0100_1000_1000_0001"; -- b2 ~ +0.9993459
--
-- constant Coef_a1 : std_logic_vector(31 downto 0) := B"10_00_0000_0001_0110_0110_1111_1010_1110"; -- a1 ~
-- constant Coef_a2 : std_logic_vector(31 downto 0) := B"00_11_1111_1110_1010_1001_0001_0110_1110"; -- a2 ~ +0.9986919
--
-- -- stop band 2nd order ellip fl = 500Hz, fu = 2000Hz, Fs = 48000Hz, PBR = .08 dB, SBR = .03 dB
-- --------------------------------------------------------------------------
----
---- b0 + b1*Z^-1 + b2*Z^-2
---- H[z] = -------------------------
---- 1 + a1*Z^-1 + a2*Z^-2
----
-- --------------------------------------------------------------------------
--
-- -- define biquad coefficients WORKED BUT WITH LOW SOUND
-- constant Coef_b0 : std_logic_vector(31 downto 0) := B"00_11_1101_0110_1100_0100_0001_0000_0110"; -- b0 ~ +0.9597323
-- constant Coef_b1 : std_logic_vector(31 downto 0) := B"10_00_0110_0011_0101_0110_0111_0101_0101"; -- b1 ~ -1.9029905
-- constant Coef_b2 : std_logic_vector(31 downto 0) := B"00_11_1101_0110_1100_0100_0001_0000_0110"; -- b2 ~ +0.9597323
--
-- constant Coef_a1 : std_logic_vector(31 downto 0) := B"10_00_0110_0011_0101_0110_0111_0101_0101"; -- a1 ~ -1.9029905
-- constant Coef_a2 : std_logic_vector(31 downto 0) := B"00_11_1010_1101_1000_1000_0010_0111_1000"; -- a2 ~ +0.9194647
-- -- low pass 2nd order cheb fc = 10000Hz, Fs = 48000Hz, PBR = .08 dB, SBR = .03 dB
-- --------------------------------------------------------------------------
----
---- b0 + b1*Z^-1 + b2*Z^-2
---- H[z] = -------------------------
---- 1 + a1*Z^-1 + a2*Z^-2
----
-- --------------------------------------------------------------------------
--
---- define biquad coefficients WORKED WITH HIGH SOUND
-- constant Coef_b0 : std_logic_vector(31 downto 0) := B"00_00_1110_0001_0111_1010_1011_1000_0011"; -- b0 ~ +0.2201947
-- constant Coef_b1 : std_logic_vector(31 downto 0) := B"00_01_1100_0010_1111_0101_0111_0000_0101"; -- b1 ~ 0.4403894
-- constant Coef_b2 : std_logic_vector(31 downto 0) := B"00_00_1110_0001_0111_1010_1011_1000_0011"; -- b0 ~ +0.2201947
--
-- constant Coef_a1 : std_logic_vector(31 downto 0) := B"11_10_1100_0101_0000_1101_0101_0000_0100"; -- a1 ~ -0.3075664
-- constant Coef_a2 : std_logic_vector(31 downto 0) := B"00_00_1100_0000_1101_1101_1001_0000_0110"; -- a2 ~ +0.1883452
-- -- band pass 2nd order cheb f0 = 2000Hz, fl = 1500Hz, fu = 2500 Fs = 48000Hz, PBR = .08 dB, SBR = .03 dB
-- --------------------------------------------------------------------------
----
---- b0 + b1*Z^-1 + b2*Z^-2
---- H[z] = -------------------------
---- 1 + a1*Z^-1 + a2*Z^-2
----
-- --------------------------------------------------------------------------
--
---- define biquad coefficients --DID NOT WORK NO SOUND
-- constant Coef_b0 : std_logic_vector(31 downto 0) := B"00_00_0011_1110_1111_1100_1111_0011_0000"; -- b0 ~ +0.0615118
-- constant Coef_b1 : std_logic_vector(31 downto 0) := B"00_00_0000_0000_0000_0000_0000_0000_0000"; -- b1 ~ 0.0
-- constant Coef_b2 : std_logic_vector(31 downto 0) := B"11_11_1100_0001_0000_0011_0000_1100_1111"; -- b0 ~ -0.0615118**
--
-- constant Coef_a1 : std_logic_vector(31 downto 0) := B"10_00_1011_1011_0111_1011_1110_0100_1000"; -- a1 ~ -1.8169102
-- constant Coef_a2 : std_logic_vector(31 downto 0) := B"00_11_1000_0010_0000_0110_0010_0000_1011"; -- a2 ~ +0.8769765
-- define each pre gain sample flip flop
signal ZFF_X0, ZFF_X1, ZFF_X2, ZFF_Y1, ZFF_Y2 : std_logic_vector(23 downto 0) := (others => '0');
-- define each post gain 64 bit sample
signal pgZFF_X0_quad, pgZFF_X1_quad, pgZFF_X2_quad, pgZFF_Y1_quad, pgZFF_Y2_quad : std_logic_vector( 55 downto 0) := (others => '0');
-- define each post gain 32 but truncated sample
signal pgZFF_X0, pgZFF_X1, pgZFF_X2, pgZFF_Y1, pgZFF_Y2 : std_logic_vector(23 downto 0) := (others => '0');
-- define output double reg
signal Y_out_double : std_logic_vector( 23 downto 0) := (others => '0');
-- state machine signals
type state_type is (idle, run);
signal state_reg, state_next : state_type;
-- counter signals
signal q_reg, q_next : unsigned(2 downto 0);
signal q_reset, q_add : std_logic;
-- data path flags
signal mul_coefs, trunc_prods, sum_stg_a, trunc_out : std_logic;
begin
-- process to shift samples
process(clk, n_reset, Y_out_double, sample_trig)
begin
if(n_reset = '1') then
ZFF_X0 <= (others => '0');
ZFF_X1 <= (others => '0');
ZFF_X2 <= (others => '0');
ZFF_Y1 <= (others => '0');
ZFF_Y2 <= (others => '0');
elsif(rising_edge(clk)) then
if(sample_trig = '1' and state_reg = idle)
then
ZFF_X0 <= X_in(23) & X_in(23 downto 1);
ZFF_X1 <= ZFF_X0;
ZFF_X2 <= ZFF_X1;
ZFF_Y1 <= Y_out_double;
ZFF_Y2 <= ZFF_Y1;
end if;
end if;
end process;
-- STATE UPDATE AND TIMING
process(clk, n_reset)
begin
if(n_reset = '1') then
state_reg <= idle;
q_reg <= (others => '0'); -- reset counter
elsif (rising_edge(clk)) then
state_reg <= state_next; -- update the state
q_reg <= q_next;
end if;
end process;
-- COUNTER FOR TIMING
q_next <= (others => '0') when q_reset = '1' else -- resets the counter
q_reg + 1 when q_add = '1' else -- increment count if commanded
q_reg;
-- process for control of data path flags
process( q_reg, state_reg, sample_trig)
begin
-- defaults
q_reset <= '0';
q_add <= '0';
mul_coefs <= '0';
trunc_prods <= '0';
sum_stg_a <= '0';
trunc_out <= '0';
filter_done <= '0';
case state_reg is
when idle =>
if(sample_trig = '1') then
state_next <= run;
else
state_next <= idle;
end if;
when run =>
if( q_reg < "001") then
q_add <= '1';
state_next <= run;
elsif( q_reg < "011") then
mul_coefs <= '1';
q_add <= '1';
state_next <= run;
elsif( q_reg < "100") then
trunc_prods <= '1';
q_add <= '1';
state_next <= run;
elsif( q_reg < "101") then
sum_stg_a <= '1';
q_add <= '1';
state_next <= run;
elsif( q_reg < "110") then
trunc_out <= '1';
q_add <= '1';
state_next <= run;
else
q_reset <= '1';
filter_done <= '1';
state_next <= idle;
end if;
end case;
end process;
-- add gain factors to numerator of biquad (feed forward path)
pgZFF_X0_quad <= std_logic_vector( signed(Coef_b0) * signed(ZFF_X0)) when mul_coefs = '1';
pgZFF_X1_quad <= std_logic_vector( signed(Coef_b1) * signed(ZFF_X1)) when mul_coefs = '1';
pgZFF_X2_quad <= std_logic_vector( signed(Coef_b2) * signed(ZFF_X2)) when mul_coefs = '1';
-- add gain factors to denominator of biquad (feed back path)
pgZFF_Y1_quad <= std_logic_vector( signed(Coef_a1) * signed(ZFF_Y1)) when mul_coefs = '1';
pgZFF_Y2_quad <= std_logic_vector( signed(Coef_a2) * signed(ZFF_Y2)) when mul_coefs = '1';
-- truncate the output to summation block
process(clk, trunc_prods, pgZFF_X0_quad, pgZFF_X1_quad, pgZFF_X2_quad, pgZFF_Y1_quad, pgZFF_Y2_quad)
begin
if rising_edge(clk) then
if (trunc_prods = '1') then
pgZFF_X0 <= pgZFF_X0_quad(55 downto 32);
pgZFF_X2 <= pgZFF_X2_quad(55 downto 32);
pgZFF_X1 <= pgZFF_X1_quad(55 downto 32);
pgZFF_Y1 <= pgZFF_Y1_quad(55 downto 32);
pgZFF_Y2 <= pgZFF_Y2_quad(55 downto 32);
end if;
end if;
end process;
-- sum all post gain feedback and feedfoward paths
-- Y[z] = X[z]*bo + X[z]*b1*Z^-1 + X[z]*b2*Z^-2 - Y[z]*a1*z^-1 + Y[z]*a2*z^-2
process(clk, sum_stg_a)
begin
if(rising_edge(clk)) then
if(sum_stg_a = '1') then
Y_out_double <= std_logic_vector(signed(pgZFF_X0) + signed(pgZFF_X1) + signed(pgZFF_X2) - signed(pgZFF_Y1) - signed(pgZFF_Y2)); --std_logic_vector((pgZFF_X0));--
end if;
end if;
end process;
-- output truncation block
process(clk, trunc_out)
begin
if rising_edge(clk) then
if (trunc_out = '1') then
Y_out <= Y_out_double( 23 downto 0);
end if;
end if;
end process;
end arch;
-- Pre Generated Example IIR filters
-------------------------------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------------------------------------
-- -- band pass 2nd order butterworth f0 = 2000Hz, fl = 1500Hz, fu = 2500 Fs = 48000Hz, PBR = .08 dB, SBR = .03 dB
-- --------------------------------------------------------------------------
----
---- b0 + b1*Z^-1 + b2*Z^-2
---- H[z] = -------------------------
---- 1 + a1*Z^-1 + a2*Z^-2
----
-- --------------------------------------------------------------------------
--
---- define biquad coefficients
-- constant Coef_b0 : std_logic_vector(31 downto 0) := B"00_00_0011_1110_1111_1100_1111_0000_1111"; -- b0 ~ +0.061511769
-- constant Coef_b1 : std_logic_vector(31 downto 0) := B"00_00_0000_0000_0000_0000_0000_0000_0000"; -- b1 ~ 0.0
-- constant Coef_b2 : std_logic_vector(31 downto 0) := B"11_11_1100_0001_0000_0011_0000_1111_0001"; -- b0 ~ -0.061511769
-- constant Coef_a1 : std_logic_vector(31 downto 0) := B"10_00_1011_1011_0111_1011_1110_0101_0111"; -- a1 ~ -1.816910185
-- constant Coef_a2 : std_logic_vector(31 downto 0) := B"00_11_1000_0010_0000_0110_0001_1110_0010"; -- a2 ~ +0.876976463
-- -- low pass 2nd order butt fl = 500Hz, Fs = 48000Hz, PBR = .08 dB, SBR = .03 dB
-- --------------------------------------------------------------------------
----
---- b0 + b1*Z^-1 + b2*Z^-2
---- H[z] = -------------------------
---- 1 + a1*Z^-1 + a2*Z^-2
----
-- --------------------------------------------------------------------------
--
-- -- define biquad coefficients
-- constant Coef_b0 : std_logic_vector(31 downto 0) := B"00_00_0000_0001_0000_1100_0011_1001_1100"; -- b0 ~ +0.0010232
-- constant Coef_b1 : std_logic_vector(31 downto 0) := B"00_00_0000_0010_0001_1000_0111_0011_1001"; -- b1 ~ +0.0020464
-- constant Coef_b2 : std_logic_vector(31 downto 0) := B"00_00_0000_0001_0000_1100_0011_1001_1100"; -- b2 ~ +0.0010232
-- constant Coef_a1 : std_logic_vector(31 downto 0) := B"10_00_0101_1110_1011_0111_1110_0110_1000"; -- a1 ~ -1.9075016
-- constant Coef_a2 : std_logic_vector(31 downto 0) := B"00_11_1010_0101_0111_1001_0000_0111_0101"; -- a2 ~ +0.9115945
---- -- stop band 2nd order cheb f0 = 2828.47, Hz, fl = 2000Hz, fu = 4000Hz, Fs = 48000Hz, PBR = .08 dB, SBR = .03 dB
---- --------------------------------------------------------------------------
----
---- b0 + b1*Z^-1 + b2*Z^-2
---- H[z] = -------------------------
---- 1 + a1*Z^-1 + a2*Z^-2
----
---- --------------------------------------------------------------------------
----
---- define biquad coefficients
-- constant Coef_b0 : std_logic_vector(31 downto 0) := B"00_11_1000_1000_1101_1111_0001_1100_0110"; -- b0 ~ +0.8836636
-- constant Coef_b1 : std_logic_vector(31 downto 0) := B"10_01_0110_1001_1001_0110_1000_0001_1011"; -- b1 ~ -1.6468868
-- constant Coef_b2 : std_logic_vector(31 downto 0) := B"00_11_1000_1000_1101_1111_0001_1100_0110"; -- b2 ~ +0.8836636
--
-- constant Coef_a1 : std_logic_vector(31 downto 0) := B"10_01_0110_1001_1001_0110_1000_0001_1011"; -- a1 ~ -1.6468868
-- constant Coef_a2 : std_logic_vector(31 downto 0) := B"00_11_0001_0001_1011_1110_0011_1000_1011"; -- a2 ~ +0.7673272
-- -- band pass 2nd order elliptical fl= 2000Hz, fu = 2500Hz, Fs = 48000Hz, PBR = .08 dB, SBR = .03 dB
-- --------------------------------------------------------------------------
----
---- b0 + b1*Z^-1 + b2*Z^-2
---- H[z] = -------------------------
---- 1 + a1*Z^-1 + a2*Z^-2
----
-- --------------------------------------------------------------------------
--
---- define biquad coefficients
-- constant Coef_b0 : std_logic_vector(31 downto 0) := B"00_00_0100_1001_0001_0011_0101_0100_0111"; -- b0 ~ +0.0713628
-- constant Coef_b1 : std_logic_vector(31 downto 0) := B"00_00_0000_0000_0000_0000_0000_0000_0000"; -- b1 ~ +0.0
-- constant Coef_b2 : std_logic_vector(31 downto 0) := B"11_11_1011_0110_1110_1100_1010_1011_1000"; -- b2 ~ -0.0713628
--
-- constant Coef_a1 : std_logic_vector(31 downto 0) := B"10_00_1110_0011_0001_0001_1010_1011_1111"; -- a1 ~ -1.7782529
-- constant Coef_a2 : std_logic_vector(31 downto 0) := B"00_11_0110_1101_1101_1001_0101_0111_0001"; -- a2 ~ +0.8572744
-- -- Used Bilinear Z Transform
-- -- low pass 2nd order butterworth fc = 12000Hz, Fs = 48000Hz, PBR = .08 dB, SBR = .03 dB
-- --------------------------------------------------------------------------
----
---- b0 + b1*Z^-1 + b2*Z^-2
---- H[z] = -------------------------
---- 1 + a1*Z^-1 + a2*Z^-2
----
-- --------------------------------------------------------------------------
--
---- define biquad coefficients
-- constant Coef_b0 : std_logic_vector(31 downto 0) := B"00_01_0010_1011_1110_1100_0011_0011_0011"; -- b0 ~ +0.292893219
-- constant Coef_b1 : std_logic_vector(31 downto 0) := B"00_10_0101_0111_1101_1000_0110_0110_0110"; -- b1 ~ +0.585786438
-- constant Coef_b2 : std_logic_vector(31 downto 0) := B"00_01_0010_1011_1110_1100_0011_0011_0011"; -- b2 ~ +0.292893219
--
-- constant Coef_a1 : std_logic_vector(31 downto 0) := B"00_00_0000_0000_0000_0000_0000_0000_0000"; -- a1 ~ 0.0
-- constant Coef_a2 : std_logic_vector(31 downto 0) := B"00_00_0000_0000_0000_0101_0111_1101_1000"; -- a2 ~ +0.171572875
-- -- band stop butterworth 2nd order fo = 59.79, fl = 55Hz, fu = 65Hz, Fs = 48000Hz, PBR = .08 dB, SBR = .03 dB
-- --------------------------------------------------------------------------
----
---- b0 + b1*Z^-1 + b2*Z^-2
---- H[z] = -------------------------
---- 1 + a1*Z^-1 + a2*Z^-2
----
-- --------------------------------------------------------------------------
--
-- -- define biquad coefficients
-- constant Coef_b0 : std_logic_vector(31 downto 0) := B"00_11_1111_1111_0101_0100_1000_1000_0001"; -- b0 ~ +0.9993459
-- constant Coef_b1 : std_logic_vector(31 downto 0) := B"10_00_0000_0001_0110_0110_1111_1010_1110"; -- b1 ~ -1.9986306
-- constant Coef_b2 : std_logic_vector(31 downto 0) := B"00_11_1111_1111_0101_0100_1000_1000_0001"; -- b2 ~ +0.9993459
--
-- constant Coef_a1 : std_logic_vector(31 downto 0) := B"10_00_0000_0001_0110_0110_1111_1010_1110"; -- a1 ~ -1.9986306
-- constant Coef_a2 : std_logic_vector(31 downto 0) := B"00_11_1111_1110_1010_1001_0001_0110_1110"; -- a2 ~ +0.9986919
--
-- -- stop band 2nd order ellip fl = 500Hz, fu = 2000Hz, Fs = 48000Hz, PBR = .08 dB, SBR = .03 dB
-- --------------------------------------------------------------------------
----
---- b0 + b1*Z^-1 + b2*Z^-2
---- H[z] = -------------------------
---- 1 + a1*Z^-1 + a2*Z^-2
----
-- --------------------------------------------------------------------------
--
-- -- define biquad coefficients
-- constant Coef_b0 : std_logic_vector(31 downto 0) := B"00_11_1101_0110_1100_0100_0001_0000_0110"; -- b0 ~ +0.9597323
-- constant Coef_b1 : std_logic_vector(31 downto 0) := B"10_00_0110_0011_0101_0110_0111_0101_0101"; -- b1 ~ -1.9029905
-- constant Coef_b2 : std_logic_vector(31 downto 0) := B"00_11_1101_0110_1100_0100_0001_0000_0110"; -- b2 ~ +0.9597323
-- constant Coef_a1 : std_logic_vector(31 downto 0) := B"10_00_0110_0011_0101_0110_0111_0101_0101"; -- a1 ~ -1.9029905
-- constant Coef_a2 : std_logic_vector(31 downto 0) := B"00_11_1010_1101_1000_1000_0010_0111_1000"; -- a2 ~ +0.9194647
--
-- -- low pass 2nd order cheb fc = 10000Hz, Fs = 48000Hz, PBR = .08 dB, SBR = .03 dB
-- --------------------------------------------------------------------------
----
---- b0 + b1*Z^-1 + b2*Z^-2
---- H[z] = -------------------------
---- 1 + a1*Z^-1 + a2*Z^-2
----
-- --------------------------------------------------------------------------
--
---- define biquad coefficients
-- constant Coef_b0 : std_logic_vector(31 downto 0) := B"00_00_1110_0001_0111_1010_1011_1000_0011"; -- b0 ~ +0.2201947
-- constant Coef_b1 : std_logic_vector(31 downto 0) := B"00_01_1100_0010_1111_0101_0111_0000_0101"; -- b1 ~ 0.4403894
-- constant Coef_b2 : std_logic_vector(31 downto 0) := B"00_00_1110_0001_0111_1010_1011_1000_0011"; -- b0 ~ +0.2201947
-- constant Coef_a1 : std_logic_vector(31 downto 0) := B"11_10_1100_0101_0000_1101_0101_0000_0100"; -- a1 ~ -0.3075664
-- constant Coef_a2 : std_logic_vector(31 downto 0) := B"00_00_1100_0000_1101_1101_1001_0000_0110"; -- a2 ~ +0.1883452
-- -- band pass 2nd order cheb f0 = 2000Hz, fl = 1500Hz, fu = 2500 Fs = 48000Hz, PBR = .08 dB, SBR = .03 dB
-- --------------------------------------------------------------------------
----
---- b0 + b1*Z^-1 + b2*Z^-2
---- H[z] = -------------------------
---- 1 + a1*Z^-1 + a2*Z^-2
----
-- --------------------------------------------------------------------------
--
---- define biquad coefficients
-- constant Coef_b0 : std_logic_vector(31 downto 0) := B"00_00_0011_1110_1111_1100_1111_0011_0000"; -- b0 ~ +0.0615118
-- constant Coef_b1 : std_logic_vector(31 downto 0) := B"00_00_0000_0000_0000_0000_0000_0000_0000"; -- b1 ~ 0.0
-- constant Coef_b2 : std_logic_vector(31 downto 0) := B"11_11_1100_0001_0000_0011_0000_1100_1111"; -- b0 ~ -0.0615118
-- constant Coef_a1 : std_logic_vector(31 downto 0) := B"10_00_1011_1011_0111_1011_1110_0100_1000"; -- a1 ~ -1.8169102
-- constant Coef_a2 : std_logic_vector(31 downto 0) := B"00_11_1000_0010_0000_0110_0010_0000_1011"; -- a2 ~ +0.8769765
| mit |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/dma_example/dma_example.srcs/sources_1/bd/system/ip/system_rst_ps7_0_100M_0/system_rst_ps7_0_100M_0_stub.vhdl | 1 | 1844 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Wed May 31 20:13:47 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub
-- c:/ZyboIP/examples/dma_example/dma_example.srcs/sources_1/bd/system/ip/system_rst_ps7_0_100M_0/system_rst_ps7_0_100M_0_stub.vhdl
-- Design : system_rst_ps7_0_100M_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity system_rst_ps7_0_100M_0 is
Port (
slowest_sync_clk : in STD_LOGIC;
ext_reset_in : in STD_LOGIC;
aux_reset_in : in STD_LOGIC;
mb_debug_sys_rst : in STD_LOGIC;
dcm_locked : in STD_LOGIC;
mb_reset : out STD_LOGIC;
bus_struct_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
interconnect_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 )
);
end system_rst_ps7_0_100M_0;
architecture stub of system_rst_ps7_0_100M_0 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "slowest_sync_clk,ext_reset_in,aux_reset_in,mb_debug_sys_rst,dcm_locked,mb_reset,bus_struct_reset[0:0],peripheral_reset[0:0],interconnect_aresetn[0:0],peripheral_aresetn[0:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "proc_sys_reset,Vivado 2016.4";
begin
end;
| mit |
Kolchuzhin/piezoresistance_of_SWCNT_in_VHDL-AMS_part_I | pr_swcnt.vhd | 1 | 6147 | -------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Model: piezoresistance of single walled carbon nanotube in hAMSter
--
-- Authors: Vladimir Kolchuzhin, LMGT, TU Chemnitz
-- <[email protected]>
--
-- Date: 07.06.2011 16:03
-- Library: kvl in hAMSter
-------------------------------------------------------------------------------
-- ID: pr_swcnt.vhd
-------------------------------------------------------------------------------
-- Modification History:
--
-- Revision 1.0 25.04.2012 official release for ForGr1713: www.zfm.tu-chemnitz.de/for1713
-- Revision 1.1 02.03.2015 verification for (13.0), (14,0), (15,0)
-- 05.03.2015 GitHub
--
-- Dependencies:
-- mod_ad == modulus after division
-- sign == signum function (Returns 0.0 if X < 0.0) :( e.g. (14,0)
-- floor
--
-- Status: Compile OK, model was compiled with hAMSter simulator
-------------------------------------------------------------------------------
-- Reference:
-- Theory taken from M. A. Cullinan and M.L. Culpepper
-- Carbon nanotubes as piezoresistive microelectromechanical sensors: Theory and experiment
-- Phys Rev. B, American Physical Society, 82, 115428, 2010
-- *********************************************************
-- three types of SWNTs classified by:
-- p =0 => (semi)metallic
-- abs(p)=1 => semiconducting
-- n=m => metallic
-- *********************************************************
-- theta=0; % zigzag m=0 (n,0)
-- theta=30; % armchair n=m (n,n)
-- *********************************************************
-- data for verification (SWCNT_bandgap.m):
-- (13,0) semiconducting p=+1 kind=1 Eg0=0.7423 R_002 = 1.5689e+19
-- (14,0) semiconducting p=-1 kind=1 Eg0=0.6892 R_002 = 7.4154e+11
-- (15,0) semimetallic p= 0 kind=0 Eg0=0.0292 R_002 = 3.3838e+05
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.math_real.all;
use work.electromagnetic_system.all;
use work.all;
-------------------------------------------------------------------------------
entity pr_swcnt is
-- input parameters:
-- n -- chiral parameter for CNT
-- m -- chiral parameter for CNT
-- c1 -- stiffness, N/m
-- L0 -- initial length of tube, m
-- Rc -- contact resistance, Ohm
-- environment parameters
-- T -- temperature, K
-- s0 -- pretension strain
-- s -- strain = (L-L0)/L0 = f/c1/L0; (L-L0=u; f=c1*u)
-- g -- torsional strain
generic(Rc,T,n,m,s0,g,c1,L0:real); -- given as a generic parameter
port (terminal m1,m2:translational; -- structural ports
terminal e1,e2:electrical); -- electrical ports
end entity pr_swcnt;
--===========================================================================--
--===========================================================================--
architecture analytic of pr_swcnt is
quantity u across f through m1 to m2;
quantity v across i through e1 to e2;
--
quantity strain:real;
quantity p1:real;
quantity p:real;
quantity Eg0:real;
quantity Egs:real;
quantity kind:real;
quantity Rcnt:real;
-- physical constants
constant h:real:=6.6260695729e-34; -- Plancks constant, Js
constant e_charge:real:=1.60217646e-19; -- charge on an electron, As = C
constant kB:real:=1.380648813e-23; -- Boltzmanns constant, J/K
-- parameters of CNT
constant tp:real:=1.0; -- transmission probability t^2 of an electron
constant a:real:=1.421*sqrt(3.0); -- length of lattice vector, Å
constant t0:real:=2.66; -- the tight-binding overlap integral, eV
constant b:real:=3.5; -- change in transfer integral by changed bond lengths, eV/Å
constant nu:real:=0.2; -- Poisson's ratio = E/(2*G)-1
-- calculated parameters of CNT from m,n
constant r0:real:=(a*sqrt(n*n+m*m+m*n)/(2.0*MATH_PI)); -- radius
constant theta:real:=arctan(sqrt(3.0)*m/(2.0*n+m)); -- chiral angle
--===========================================================================--
FUNCTION mod_ad(x:real;y:real) RETURN real is
variable result:real:= 0.0;
-- Modulus after division
-- the inputs must be real scalars
-- MOD(x,0) is x.
-- MOD(x,x) is 0.
-- MOD(x,y) for x~=y and y~=0, has the same sign as y.
-- MOD(x,y) is x - n.*y where n = floor(x./y) if y ~= 0.
begin
if x = y then
result:=0.0; -- x = y
elsif y = 0.0 then -- y = 0
result:=x;
else -- x ~= y
result:=x - y*floor(x/y);
end if;
RETURN result;
END FUNCTION mod_ad;
--===========================================================================--
begin
f == c1*u; -- linear spring
strain == u/L0;
---------------
p1 == abs(mod_ad(n-m,3.0));
if p1 <= 1.0 use
p == p1;
else
p == p1 - 3.0; -- p = p - 3*(p>1)
end use;
if n = m use
kind == 2.0; -- metallic
else
kind == abs(p); -- semimetallic / semiconducting classified by p
end use;
---------------
if kind = 0.0 use -- kind = 0 (semimetallic)
Eg0==t0*a**2/(16.0*r0**2.0)*cos(3.0*theta); -- zero strain band gap
Egs==abs(Eg0-(sqrt(3.0)/2.0)*a*b*cos(3.0*theta)*strain);
elsif kind = 1.0 use -- kind = 1 (semiconducting)
Eg0==t0*a/(sqrt(3.0)*r0); -- zero strain band gap
--Egs==abs(Eg0+sign(2.0*p+1.0)*3.0*t0*((1.0+nu)*cos(3.0*theta)*strain+sin(3.0*theta)*g));
if p < 1.0 use
Egs==abs(Eg0+(-1.0)*3.0*t0*((1.0+nu)*cos(3.0*theta)*strain+sin(3.0*theta)*g));
else
Egs==abs(Eg0+(+1.0)*3.0*t0*((1.0+nu)*cos(3.0*theta)*strain+sin(3.0*theta)*g));
end use;
else -- kind = 2 (metallic)
Eg0==0.0;
Egs==0.0;
end use;
---------------
Rcnt == h/(8.0*(tp*e_charge)**2)*(1.0+exp(Egs/(kB*T/e_charge))); -- resistance of a strained SWCNT, Ohm
---------------
v == i*(Rc + Rcnt);
end architecture analytic;
--===========================================================================--
--===========================================================================--
| mit |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_dual_fusion/zed_dual_fusion.srcs/sources_1/bd/system/ip/system_vga_sync_reset_0_0/system_vga_sync_reset_0_0_sim_netlist.vhdl | 1 | 19037 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Tue Jun 06 02:48:32 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- C:/ZyboIP/examples/zed_dual_fusion/zed_dual_fusion.srcs/sources_1/bd/system/ip/system_vga_sync_reset_0_0/system_vga_sync_reset_0_0_sim_netlist.vhdl
-- Design : system_vga_sync_reset_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_vga_sync_reset_0_0_vga_sync_reset is
port (
xaddr : out STD_LOGIC_VECTOR ( 9 downto 0 );
yaddr : out STD_LOGIC_VECTOR ( 9 downto 0 );
active : out STD_LOGIC;
hsync : out STD_LOGIC;
vsync : out STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_vga_sync_reset_0_0_vga_sync_reset : entity is "vga_sync_reset";
end system_vga_sync_reset_0_0_vga_sync_reset;
architecture STRUCTURE of system_vga_sync_reset_0_0_vga_sync_reset is
signal active_i_1_n_0 : STD_LOGIC;
signal active_i_2_n_0 : STD_LOGIC;
signal \h_count_reg[0]_i_1_n_0\ : STD_LOGIC;
signal \h_count_reg[9]_i_1_n_0\ : STD_LOGIC;
signal \h_count_reg[9]_i_3_n_0\ : STD_LOGIC;
signal \h_count_reg[9]_i_4_n_0\ : STD_LOGIC;
signal hsync_i_1_n_0 : STD_LOGIC;
signal hsync_i_2_n_0 : STD_LOGIC;
signal hsync_i_3_n_0 : STD_LOGIC;
signal plusOp : STD_LOGIC_VECTOR ( 9 downto 1 );
signal \plusOp__0\ : STD_LOGIC_VECTOR ( 9 downto 0 );
signal \v_count_reg[9]_i_1_n_0\ : STD_LOGIC;
signal \v_count_reg[9]_i_2_n_0\ : STD_LOGIC;
signal \v_count_reg[9]_i_4_n_0\ : STD_LOGIC;
signal \v_count_reg[9]_i_5_n_0\ : STD_LOGIC;
signal \v_count_reg[9]_i_6_n_0\ : STD_LOGIC;
signal vsync_i_1_n_0 : STD_LOGIC;
signal vsync_i_2_n_0 : STD_LOGIC;
signal \^xaddr\ : STD_LOGIC_VECTOR ( 9 downto 0 );
signal \^yaddr\ : STD_LOGIC_VECTOR ( 9 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of active_i_2 : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \h_count_reg[1]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \h_count_reg[2]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \h_count_reg[3]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \h_count_reg[4]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \h_count_reg[7]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \h_count_reg[8]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \h_count_reg[9]_i_3\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \h_count_reg[9]_i_4\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of hsync_i_1 : label is "soft_lutpair5";
attribute SOFT_HLUTNM of hsync_i_3 : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \v_count_reg[0]_i_1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \v_count_reg[1]_i_1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \v_count_reg[2]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \v_count_reg[3]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \v_count_reg[4]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \v_count_reg[7]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \v_count_reg[8]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \v_count_reg[9]_i_6\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of vsync_i_2 : label is "soft_lutpair3";
begin
xaddr(9 downto 0) <= \^xaddr\(9 downto 0);
yaddr(9 downto 0) <= \^yaddr\(9 downto 0);
active_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"0000222A00000000"
)
port map (
I0 => active_i_2_n_0,
I1 => \^xaddr\(9),
I2 => \^xaddr\(7),
I3 => \^xaddr\(8),
I4 => \^yaddr\(9),
I5 => rst,
O => active_i_1_n_0
);
active_i_2: unisim.vcomponents.LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => \^yaddr\(7),
I1 => \^yaddr\(5),
I2 => \^yaddr\(6),
I3 => \^yaddr\(8),
O => active_i_2_n_0
);
active_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => active_i_1_n_0,
Q => active,
R => '0'
);
\h_count_reg[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^xaddr\(0),
O => \h_count_reg[0]_i_1_n_0\
);
\h_count_reg[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^xaddr\(0),
I1 => \^xaddr\(1),
O => plusOp(1)
);
\h_count_reg[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \^xaddr\(1),
I1 => \^xaddr\(0),
I2 => \^xaddr\(2),
O => plusOp(2)
);
\h_count_reg[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^xaddr\(2),
I1 => \^xaddr\(0),
I2 => \^xaddr\(1),
I3 => \^xaddr\(3),
O => plusOp(3)
);
\h_count_reg[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \^xaddr\(3),
I1 => \^xaddr\(1),
I2 => \^xaddr\(0),
I3 => \^xaddr\(2),
I4 => \^xaddr\(4),
O => plusOp(4)
);
\h_count_reg[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFF80000000"
)
port map (
I0 => \^xaddr\(4),
I1 => \^xaddr\(2),
I2 => \^xaddr\(0),
I3 => \^xaddr\(1),
I4 => \^xaddr\(3),
I5 => \^xaddr\(5),
O => plusOp(5)
);
\h_count_reg[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"D2"
)
port map (
I0 => \^xaddr\(5),
I1 => \h_count_reg[9]_i_3_n_0\,
I2 => \^xaddr\(6),
O => plusOp(6)
);
\h_count_reg[7]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"BF40"
)
port map (
I0 => \h_count_reg[9]_i_3_n_0\,
I1 => \^xaddr\(5),
I2 => \^xaddr\(6),
I3 => \^xaddr\(7),
O => plusOp(7)
);
\h_count_reg[8]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF7F0080"
)
port map (
I0 => \^xaddr\(7),
I1 => \^xaddr\(6),
I2 => \^xaddr\(5),
I3 => \h_count_reg[9]_i_3_n_0\,
I4 => \^xaddr\(8),
O => plusOp(8)
);
\h_count_reg[9]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"10000000FFFFFFFF"
)
port map (
I0 => \h_count_reg[9]_i_3_n_0\,
I1 => \^xaddr\(7),
I2 => \^xaddr\(8),
I3 => \^xaddr\(9),
I4 => \h_count_reg[9]_i_4_n_0\,
I5 => rst,
O => \h_count_reg[9]_i_1_n_0\
);
\h_count_reg[9]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"DFFFFFFF20000000"
)
port map (
I0 => \^xaddr\(8),
I1 => \h_count_reg[9]_i_3_n_0\,
I2 => \^xaddr\(5),
I3 => \^xaddr\(6),
I4 => \^xaddr\(7),
I5 => \^xaddr\(9),
O => plusOp(9)
);
\h_count_reg[9]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFFFFFF"
)
port map (
I0 => \^xaddr\(3),
I1 => \^xaddr\(1),
I2 => \^xaddr\(0),
I3 => \^xaddr\(2),
I4 => \^xaddr\(4),
O => \h_count_reg[9]_i_3_n_0\
);
\h_count_reg[9]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \^xaddr\(5),
I1 => \^xaddr\(6),
O => \h_count_reg[9]_i_4_n_0\
);
\h_count_reg_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \h_count_reg[0]_i_1_n_0\,
Q => \^xaddr\(0),
R => \h_count_reg[9]_i_1_n_0\
);
\h_count_reg_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => plusOp(1),
Q => \^xaddr\(1),
R => \h_count_reg[9]_i_1_n_0\
);
\h_count_reg_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => plusOp(2),
Q => \^xaddr\(2),
R => \h_count_reg[9]_i_1_n_0\
);
\h_count_reg_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => plusOp(3),
Q => \^xaddr\(3),
R => \h_count_reg[9]_i_1_n_0\
);
\h_count_reg_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => plusOp(4),
Q => \^xaddr\(4),
R => \h_count_reg[9]_i_1_n_0\
);
\h_count_reg_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => plusOp(5),
Q => \^xaddr\(5),
R => \h_count_reg[9]_i_1_n_0\
);
\h_count_reg_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => plusOp(6),
Q => \^xaddr\(6),
R => \h_count_reg[9]_i_1_n_0\
);
\h_count_reg_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => plusOp(7),
Q => \^xaddr\(7),
R => \h_count_reg[9]_i_1_n_0\
);
\h_count_reg_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => plusOp(8),
Q => \^xaddr\(8),
R => \h_count_reg[9]_i_1_n_0\
);
\h_count_reg_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => plusOp(9),
Q => \^xaddr\(9),
R => \h_count_reg[9]_i_1_n_0\
);
hsync_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"ABEAFFFF"
)
port map (
I0 => hsync_i_2_n_0,
I1 => \^xaddr\(5),
I2 => \^xaddr\(6),
I3 => hsync_i_3_n_0,
I4 => rst,
O => hsync_i_1_n_0
);
hsync_i_2: unisim.vcomponents.LUT3
generic map(
INIT => X"DF"
)
port map (
I0 => \^xaddr\(9),
I1 => \^xaddr\(8),
I2 => \^xaddr\(7),
O => hsync_i_2_n_0
);
hsync_i_3: unisim.vcomponents.LUT5
generic map(
INIT => X"0001FFFF"
)
port map (
I0 => \^xaddr\(2),
I1 => \^xaddr\(3),
I2 => \^xaddr\(0),
I3 => \^xaddr\(1),
I4 => \^xaddr\(4),
O => hsync_i_3_n_0
);
hsync_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => hsync_i_1_n_0,
Q => hsync,
R => '0'
);
\v_count_reg[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^yaddr\(0),
O => \plusOp__0\(0)
);
\v_count_reg[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^yaddr\(0),
I1 => \^yaddr\(1),
O => \plusOp__0\(1)
);
\v_count_reg[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \^yaddr\(1),
I1 => \^yaddr\(0),
I2 => \^yaddr\(2),
O => \plusOp__0\(2)
);
\v_count_reg[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^yaddr\(2),
I1 => \^yaddr\(0),
I2 => \^yaddr\(1),
I3 => \^yaddr\(3),
O => \plusOp__0\(3)
);
\v_count_reg[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \^yaddr\(3),
I1 => \^yaddr\(1),
I2 => \^yaddr\(0),
I3 => \^yaddr\(2),
I4 => \^yaddr\(4),
O => \plusOp__0\(4)
);
\v_count_reg[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFF80000000"
)
port map (
I0 => \^yaddr\(4),
I1 => \^yaddr\(2),
I2 => \^yaddr\(0),
I3 => \^yaddr\(1),
I4 => \^yaddr\(3),
I5 => \^yaddr\(5),
O => \plusOp__0\(5)
);
\v_count_reg[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"D2"
)
port map (
I0 => \^yaddr\(5),
I1 => \v_count_reg[9]_i_6_n_0\,
I2 => \^yaddr\(6),
O => \plusOp__0\(6)
);
\v_count_reg[7]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"F708"
)
port map (
I0 => \^yaddr\(5),
I1 => \^yaddr\(6),
I2 => \v_count_reg[9]_i_6_n_0\,
I3 => \^yaddr\(7),
O => \plusOp__0\(7)
);
\v_count_reg[8]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"BFFF4000"
)
port map (
I0 => \v_count_reg[9]_i_6_n_0\,
I1 => \^yaddr\(6),
I2 => \^yaddr\(5),
I3 => \^yaddr\(7),
I4 => \^yaddr\(8),
O => \plusOp__0\(8)
);
\v_count_reg[9]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00400000FFFFFFFF"
)
port map (
I0 => \h_count_reg[9]_i_3_n_0\,
I1 => \v_count_reg[9]_i_4_n_0\,
I2 => \h_count_reg[9]_i_4_n_0\,
I3 => \^yaddr\(0),
I4 => \v_count_reg[9]_i_5_n_0\,
I5 => rst,
O => \v_count_reg[9]_i_1_n_0\
);
\v_count_reg[9]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000001000"
)
port map (
I0 => \^xaddr\(5),
I1 => \^xaddr\(6),
I2 => \^xaddr\(9),
I3 => \^xaddr\(8),
I4 => \^xaddr\(7),
I5 => \h_count_reg[9]_i_3_n_0\,
O => \v_count_reg[9]_i_2_n_0\
);
\v_count_reg[9]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"BFFFFFFF40000000"
)
port map (
I0 => \v_count_reg[9]_i_6_n_0\,
I1 => \^yaddr\(7),
I2 => \^yaddr\(5),
I3 => \^yaddr\(6),
I4 => \^yaddr\(8),
I5 => \^yaddr\(9),
O => \plusOp__0\(9)
);
\v_count_reg[9]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"0002000000000000"
)
port map (
I0 => \^yaddr\(9),
I1 => \^xaddr\(7),
I2 => \^yaddr\(7),
I3 => \^yaddr\(8),
I4 => \^xaddr\(9),
I5 => \^xaddr\(8),
O => \v_count_reg[9]_i_4_n_0\
);
\v_count_reg[9]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000020"
)
port map (
I0 => \^yaddr\(3),
I1 => \^yaddr\(4),
I2 => \^yaddr\(2),
I3 => \^yaddr\(1),
I4 => \^yaddr\(6),
I5 => \^yaddr\(5),
O => \v_count_reg[9]_i_5_n_0\
);
\v_count_reg[9]_i_6\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFFFFFF"
)
port map (
I0 => \^yaddr\(3),
I1 => \^yaddr\(1),
I2 => \^yaddr\(0),
I3 => \^yaddr\(2),
I4 => \^yaddr\(4),
O => \v_count_reg[9]_i_6_n_0\
);
\v_count_reg_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \v_count_reg[9]_i_2_n_0\,
D => \plusOp__0\(0),
Q => \^yaddr\(0),
R => \v_count_reg[9]_i_1_n_0\
);
\v_count_reg_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \v_count_reg[9]_i_2_n_0\,
D => \plusOp__0\(1),
Q => \^yaddr\(1),
R => \v_count_reg[9]_i_1_n_0\
);
\v_count_reg_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \v_count_reg[9]_i_2_n_0\,
D => \plusOp__0\(2),
Q => \^yaddr\(2),
R => \v_count_reg[9]_i_1_n_0\
);
\v_count_reg_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \v_count_reg[9]_i_2_n_0\,
D => \plusOp__0\(3),
Q => \^yaddr\(3),
R => \v_count_reg[9]_i_1_n_0\
);
\v_count_reg_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \v_count_reg[9]_i_2_n_0\,
D => \plusOp__0\(4),
Q => \^yaddr\(4),
R => \v_count_reg[9]_i_1_n_0\
);
\v_count_reg_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \v_count_reg[9]_i_2_n_0\,
D => \plusOp__0\(5),
Q => \^yaddr\(5),
R => \v_count_reg[9]_i_1_n_0\
);
\v_count_reg_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \v_count_reg[9]_i_2_n_0\,
D => \plusOp__0\(6),
Q => \^yaddr\(6),
R => \v_count_reg[9]_i_1_n_0\
);
\v_count_reg_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \v_count_reg[9]_i_2_n_0\,
D => \plusOp__0\(7),
Q => \^yaddr\(7),
R => \v_count_reg[9]_i_1_n_0\
);
\v_count_reg_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \v_count_reg[9]_i_2_n_0\,
D => \plusOp__0\(8),
Q => \^yaddr\(8),
R => \v_count_reg[9]_i_1_n_0\
);
\v_count_reg_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \v_count_reg[9]_i_2_n_0\,
D => \plusOp__0\(9),
Q => \^yaddr\(9),
R => \v_count_reg[9]_i_1_n_0\
);
vsync_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFBFFFFFFFF"
)
port map (
I0 => vsync_i_2_n_0,
I1 => \^yaddr\(1),
I2 => \^yaddr\(2),
I3 => \^yaddr\(9),
I4 => \^yaddr\(4),
I5 => rst,
O => vsync_i_1_n_0
);
vsync_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFFFFFF"
)
port map (
I0 => \^yaddr\(8),
I1 => \^yaddr\(6),
I2 => \^yaddr\(5),
I3 => \^yaddr\(7),
I4 => \^yaddr\(3),
O => vsync_i_2_n_0
);
vsync_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => vsync_i_1_n_0,
Q => vsync,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_vga_sync_reset_0_0 is
port (
clk : in STD_LOGIC;
rst : in STD_LOGIC;
active : out STD_LOGIC;
hsync : out STD_LOGIC;
vsync : out STD_LOGIC;
xaddr : out STD_LOGIC_VECTOR ( 9 downto 0 );
yaddr : out STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_vga_sync_reset_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_vga_sync_reset_0_0 : entity is "system_vga_sync_reset_0_0,vga_sync_reset,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_vga_sync_reset_0_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_vga_sync_reset_0_0 : entity is "vga_sync_reset,Vivado 2016.4";
end system_vga_sync_reset_0_0;
architecture STRUCTURE of system_vga_sync_reset_0_0 is
begin
U0: entity work.system_vga_sync_reset_0_0_vga_sync_reset
port map (
active => active,
clk => clk,
hsync => hsync,
rst => rst,
vsync => vsync,
xaddr(9 downto 0) => xaddr(9 downto 0),
yaddr(9 downto 0) => yaddr(9 downto 0)
);
end STRUCTURE;
| mit |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | general_ip/affine_transform/affine_transform.srcs/sources_1/bd/affine_block/ip/affine_block_uint_to_ieee754_fp_0_1/affine_block_uint_to_ieee754_fp_0_1_sim_netlist.vhdl | 1 | 30710 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Mon Feb 20 13:53:58 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- c:/ZyboIP/general_ip/affine_transform/affine_transform.srcs/sources_1/bd/affine_block/ip/affine_block_uint_to_ieee754_fp_0_1/affine_block_uint_to_ieee754_fp_0_1_sim_netlist.vhdl
-- Design : affine_block_uint_to_ieee754_fp_0_1
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z010clg400-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity affine_block_uint_to_ieee754_fp_0_1_uint_to_ieee754_fp is
port (
\y[13]\ : out STD_LOGIC;
\y[23]\ : out STD_LOGIC;
y : out STD_LOGIC_VECTOR ( 9 downto 0 );
\y[22]\ : out STD_LOGIC;
\y[20]\ : out STD_LOGIC;
\y[18]\ : out STD_LOGIC;
\y[22]_0\ : out STD_LOGIC;
\y[22]_1\ : out STD_LOGIC;
\y[21]\ : out STD_LOGIC;
\y[20]_0\ : out STD_LOGIC;
\x_9__s_port_]\ : in STD_LOGIC;
\x[9]_0\ : in STD_LOGIC;
\x[9]_1\ : in STD_LOGIC;
\x[9]_2\ : in STD_LOGIC;
\x[9]_3\ : in STD_LOGIC;
x : in STD_LOGIC_VECTOR ( 9 downto 0 );
\x[9]_4\ : in STD_LOGIC;
O : in STD_LOGIC_VECTOR ( 2 downto 0 );
CO : in STD_LOGIC_VECTOR ( 0 to 0 );
p_1_out : in STD_LOGIC_VECTOR ( 0 to 0 );
\x[9]_5\ : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of affine_block_uint_to_ieee754_fp_0_1_uint_to_ieee754_fp : entity is "uint_to_ieee754_fp";
end affine_block_uint_to_ieee754_fp_0_1_uint_to_ieee754_fp;
architecture STRUCTURE of affine_block_uint_to_ieee754_fp_0_1_uint_to_ieee754_fp is
signal mantissa2_carry_i_1_n_0 : STD_LOGIC;
signal mantissa2_carry_i_2_n_0 : STD_LOGIC;
signal mantissa2_carry_i_3_n_0 : STD_LOGIC;
signal mantissa2_carry_i_4_n_0 : STD_LOGIC;
signal mantissa2_carry_n_2 : STD_LOGIC;
signal mantissa2_carry_n_3 : STD_LOGIC;
signal \x_9__s_net_1\ : STD_LOGIC;
signal \^y[13]\ : STD_LOGIC;
signal \y[13]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \y[13]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \y[14]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \y[14]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \y[14]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \y[14]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \y[14]_INST_0_i_5_n_0\ : STD_LOGIC;
signal \y[15]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \y[15]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \y[15]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \y[16]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \y[16]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \y[16]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \y[16]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \y[17]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \y[17]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \y[17]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \^y[18]\ : STD_LOGIC;
signal \y[18]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \y[18]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \y[18]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \y[19]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \y[19]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \^y[20]\ : STD_LOGIC;
signal \^y[20]_0\ : STD_LOGIC;
signal \y[20]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \y[20]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \y[20]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \y[20]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \^y[21]\ : STD_LOGIC;
signal \y[21]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \y[21]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \y[21]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \y[21]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \y[21]_INST_0_i_6_n_0\ : STD_LOGIC;
signal \^y[22]\ : STD_LOGIC;
signal \^y[22]_0\ : STD_LOGIC;
signal \^y[22]_1\ : STD_LOGIC;
signal \^y[23]\ : STD_LOGIC;
signal \y[23]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \y[23]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \y[27]_INST_0_i_4_n_0\ : STD_LOGIC;
signal NLW_mantissa2_carry_CO_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 2 );
signal NLW_mantissa2_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \y[14]_INST_0_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \y[14]_INST_0_i_3\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \y[15]_INST_0_i_2\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \y[16]_INST_0_i_4\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \y[20]_INST_0_i_3\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \y[20]_INST_0_i_4\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \y[21]_INST_0_i_3\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \y[21]_INST_0_i_6\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \y[22]_INST_0_i_3\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \y[22]_INST_0_i_6\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \y[23]_INST_0_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \y[27]_INST_0_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \y[27]_INST_0_i_2\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \y[30]_INST_0_i_2\ : label is "soft_lutpair1";
begin
\x_9__s_net_1\ <= \x_9__s_port_]\;
\y[13]\ <= \^y[13]\;
\y[18]\ <= \^y[18]\;
\y[20]\ <= \^y[20]\;
\y[20]_0\ <= \^y[20]_0\;
\y[21]\ <= \^y[21]\;
\y[22]\ <= \^y[22]\;
\y[22]_0\ <= \^y[22]_0\;
\y[22]_1\ <= \^y[22]_1\;
\y[23]\ <= \^y[23]\;
mantissa2_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3 downto 2) => NLW_mantissa2_carry_CO_UNCONNECTED(3 downto 2),
CO(1) => mantissa2_carry_n_2,
CO(0) => mantissa2_carry_n_3,
CYINIT => '1',
DI(3 downto 2) => B"00",
DI(1) => mantissa2_carry_i_1_n_0,
DI(0) => mantissa2_carry_i_2_n_0,
O(3 downto 0) => NLW_mantissa2_carry_O_UNCONNECTED(3 downto 0),
S(3 downto 2) => B"00",
S(1) => mantissa2_carry_i_3_n_0,
S(0) => mantissa2_carry_i_4_n_0
);
mantissa2_carry_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \^y[22]\,
I1 => \^y[20]\,
O => mantissa2_carry_i_1_n_0
);
mantissa2_carry_i_2: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => \^y[13]\,
I1 => \^y[23]\,
O => mantissa2_carry_i_2_n_0
);
mantissa2_carry_i_3: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^y[20]\,
I1 => \^y[22]\,
O => mantissa2_carry_i_3_n_0
);
mantissa2_carry_i_4: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^y[23]\,
I1 => \^y[13]\,
O => mantissa2_carry_i_4_n_0
);
\y[13]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"8888888C888888BF"
)
port map (
I0 => \y[14]_INST_0_i_3_n_0\,
I1 => \^y[23]\,
I2 => \y[13]_INST_0_i_1_n_0\,
I3 => \y[14]_INST_0_i_1_n_0\,
I4 => \x[9]_4\,
I5 => \y[14]_INST_0_i_2_n_0\,
O => y(0)
);
\y[13]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"BBBB8B88BBBB8BBB"
)
port map (
I0 => \y[13]_INST_0_i_2_n_0\,
I1 => \y[14]_INST_0_i_5_n_0\,
I2 => x(6),
I3 => \y[20]_INST_0_i_4_n_0\,
I4 => \y[21]_INST_0_i_4_n_0\,
I5 => x(2),
O => \y[13]_INST_0_i_1_n_0\
);
\y[13]_INST_0_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"CF44CF77"
)
port map (
I0 => x(4),
I1 => \y[20]_INST_0_i_4_n_0\,
I2 => x(8),
I3 => \y[21]_INST_0_i_4_n_0\,
I4 => x(0),
O => \y[13]_INST_0_i_2_n_0\
);
\y[14]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"ABFFAB00ABFFABFF"
)
port map (
I0 => \y[15]_INST_0_i_2_n_0\,
I1 => \y[14]_INST_0_i_1_n_0\,
I2 => \y[14]_INST_0_i_2_n_0\,
I3 => \^y[23]\,
I4 => \y[14]_INST_0_i_3_n_0\,
I5 => \y[15]_INST_0_i_1_n_0\,
O => y(1)
);
\y[14]_INST_0_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => mantissa2_carry_n_2,
I1 => CO(0),
O => \y[14]_INST_0_i_1_n_0\
);
\y[14]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"BBBB8B88BBBB8BBB"
)
port map (
I0 => \y[14]_INST_0_i_4_n_0\,
I1 => \y[14]_INST_0_i_5_n_0\,
I2 => x(7),
I3 => \y[20]_INST_0_i_4_n_0\,
I4 => \y[21]_INST_0_i_4_n_0\,
I5 => x(3),
O => \y[14]_INST_0_i_2_n_0\
);
\y[14]_INST_0_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"0080"
)
port map (
I0 => \y[16]_INST_0_i_4_n_0\,
I1 => \^y[20]\,
I2 => x(0),
I3 => \^y[22]\,
O => \y[14]_INST_0_i_3_n_0\
);
\y[14]_INST_0_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"CF44CF77"
)
port map (
I0 => x(5),
I1 => \y[20]_INST_0_i_4_n_0\,
I2 => x(9),
I3 => \y[21]_INST_0_i_4_n_0\,
I4 => x(1),
O => \y[14]_INST_0_i_4_n_0\
);
\y[14]_INST_0_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"AB"
)
port map (
I0 => \y[16]_INST_0_i_4_n_0\,
I1 => O(0),
I2 => mantissa2_carry_n_2,
O => \y[14]_INST_0_i_5_n_0\
);
\y[15]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"1BBB1BBB0AAA1BBB"
)
port map (
I0 => \^y[23]\,
I1 => \x[9]_4\,
I2 => \y[16]_INST_0_i_2_n_0\,
I3 => \y[15]_INST_0_i_1_n_0\,
I4 => \y[16]_INST_0_i_1_n_0\,
I5 => \y[15]_INST_0_i_2_n_0\,
O => y(2)
);
\y[15]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFAACAFFFF"
)
port map (
I0 => \y[15]_INST_0_i_3_n_0\,
I1 => \y[17]_INST_0_i_3_n_0\,
I2 => O(0),
I3 => \y[16]_INST_0_i_4_n_0\,
I4 => CO(0),
I5 => mantissa2_carry_n_2,
O => \y[15]_INST_0_i_1_n_0\
);
\y[15]_INST_0_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"0080"
)
port map (
I0 => \y[16]_INST_0_i_4_n_0\,
I1 => \^y[20]\,
I2 => x(1),
I3 => \^y[22]\,
O => \y[15]_INST_0_i_2_n_0\
);
\y[15]_INST_0_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF4540FFFF757F"
)
port map (
I0 => x(6),
I1 => \^y[22]\,
I2 => mantissa2_carry_n_2,
I3 => O(1),
I4 => \y[21]_INST_0_i_4_n_0\,
I5 => x(2),
O => \y[15]_INST_0_i_3_n_0\
);
\y[16]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0AAA1BBB1BBB1BBB"
)
port map (
I0 => \^y[23]\,
I1 => \x[9]_4\,
I2 => \y[17]_INST_0_i_2_n_0\,
I3 => \y[16]_INST_0_i_1_n_0\,
I4 => \y[17]_INST_0_i_1_n_0\,
I5 => \y[16]_INST_0_i_2_n_0\,
O => y(3)
);
\y[16]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFAACAFFFF"
)
port map (
I0 => \y[16]_INST_0_i_3_n_0\,
I1 => \y[18]_INST_0_i_3_n_0\,
I2 => O(0),
I3 => \y[16]_INST_0_i_4_n_0\,
I4 => CO(0),
I5 => mantissa2_carry_n_2,
O => \y[16]_INST_0_i_1_n_0\
);
\y[16]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"CFFFDDFFFFFFFFFF"
)
port map (
I0 => x(0),
I1 => \^y[22]\,
I2 => x(2),
I3 => \^y[20]\,
I4 => \^y[13]\,
I5 => mantissa2_carry_n_2,
O => \y[16]_INST_0_i_2_n_0\
);
\y[16]_INST_0_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF4540FFFF757F"
)
port map (
I0 => x(7),
I1 => \^y[22]\,
I2 => mantissa2_carry_n_2,
I3 => O(1),
I4 => \y[21]_INST_0_i_4_n_0\,
I5 => x(3),
O => \y[16]_INST_0_i_3_n_0\
);
\y[16]_INST_0_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"60"
)
port map (
I0 => \^y[18]\,
I1 => \^y[23]\,
I2 => mantissa2_carry_n_2,
O => \y[16]_INST_0_i_4_n_0\
);
\y[17]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0AAA1BBB1BBB1BBB"
)
port map (
I0 => \^y[23]\,
I1 => \x[9]_4\,
I2 => \y[18]_INST_0_i_2_n_0\,
I3 => \y[17]_INST_0_i_1_n_0\,
I4 => \y[18]_INST_0_i_1_n_0\,
I5 => \y[17]_INST_0_i_2_n_0\,
O => y(4)
);
\y[17]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFB0000FFFBFFFB"
)
port map (
I0 => \y[20]_INST_0_i_4_n_0\,
I1 => x(6),
I2 => \y[21]_INST_0_i_4_n_0\,
I3 => \y[20]_INST_0_i_3_n_0\,
I4 => \y[17]_INST_0_i_3_n_0\,
I5 => \y[21]_INST_0_i_6_n_0\,
O => \y[17]_INST_0_i_1_n_0\
);
\y[17]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"CFFFDDFFFFFFFFFF"
)
port map (
I0 => x(1),
I1 => \^y[22]\,
I2 => x(3),
I3 => \^y[20]\,
I4 => \^y[13]\,
I5 => mantissa2_carry_n_2,
O => \y[17]_INST_0_i_2_n_0\
);
\y[17]_INST_0_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF4540FFFF757F"
)
port map (
I0 => x(8),
I1 => \^y[22]\,
I2 => mantissa2_carry_n_2,
I3 => O(1),
I4 => \y[21]_INST_0_i_4_n_0\,
I5 => x(4),
O => \y[17]_INST_0_i_3_n_0\
);
\y[18]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B0BFBFBF"
)
port map (
I0 => \y[19]_INST_0_i_2_n_0\,
I1 => \y[18]_INST_0_i_1_n_0\,
I2 => \^y[23]\,
I3 => \y[18]_INST_0_i_2_n_0\,
I4 => \y[19]_INST_0_i_1_n_0\,
O => y(5)
);
\y[18]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFEF0000FFEFFFEF"
)
port map (
I0 => \y[20]_INST_0_i_3_n_0\,
I1 => \y[20]_INST_0_i_4_n_0\,
I2 => x(7),
I3 => \y[21]_INST_0_i_4_n_0\,
I4 => \y[18]_INST_0_i_3_n_0\,
I5 => \y[21]_INST_0_i_6_n_0\,
O => \y[18]_INST_0_i_1_n_0\
);
\y[18]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF00BFBFFFFFFFFF"
)
port map (
I0 => \^y[22]\,
I1 => x(2),
I2 => \^y[20]\,
I3 => \x[9]_2\,
I4 => \^y[13]\,
I5 => mantissa2_carry_n_2,
O => \y[18]_INST_0_i_2_n_0\
);
\y[18]_INST_0_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF4540FFFF757F"
)
port map (
I0 => x(9),
I1 => \^y[22]\,
I2 => mantissa2_carry_n_2,
I3 => O(1),
I4 => \y[21]_INST_0_i_4_n_0\,
I5 => x(5),
O => \y[18]_INST_0_i_3_n_0\
);
\y[19]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"1BBB1BBB0AAA1BBB"
)
port map (
I0 => \^y[23]\,
I1 => \x[9]_4\,
I2 => \y[20]_INST_0_i_2_n_0\,
I3 => \y[19]_INST_0_i_1_n_0\,
I4 => \y[20]_INST_0_i_1_n_0\,
I5 => \y[19]_INST_0_i_2_n_0\,
O => y(6)
);
\y[19]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFF70FF77"
)
port map (
I0 => \y[21]_INST_0_i_6_n_0\,
I1 => x(6),
I2 => \y[20]_INST_0_i_3_n_0\,
I3 => \y[20]_INST_0_i_4_n_0\,
I4 => x(8),
I5 => \y[21]_INST_0_i_4_n_0\,
O => \y[19]_INST_0_i_1_n_0\
);
\y[19]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"00FF404000000000"
)
port map (
I0 => \^y[22]\,
I1 => x(3),
I2 => \^y[20]\,
I3 => \x[9]_0\,
I4 => \^y[13]\,
I5 => mantissa2_carry_n_2,
O => \y[19]_INST_0_i_2_n_0\
);
\y[20]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"1BBB1BBB0AAA1BBB"
)
port map (
I0 => \^y[23]\,
I1 => \x[9]_4\,
I2 => \y[21]_INST_0_i_3_n_0\,
I3 => \y[20]_INST_0_i_1_n_0\,
I4 => \y[20]_INST_0_i_2_n_0\,
I5 => \y[21]_INST_0_i_1_n_0\,
O => y(7)
);
\y[20]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFF70FF77"
)
port map (
I0 => \y[21]_INST_0_i_6_n_0\,
I1 => x(7),
I2 => \y[20]_INST_0_i_3_n_0\,
I3 => \y[20]_INST_0_i_4_n_0\,
I4 => x(9),
I5 => \y[21]_INST_0_i_4_n_0\,
O => \y[20]_INST_0_i_1_n_0\
);
\y[20]_INST_0_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"2FEF"
)
port map (
I0 => \x[9]_2\,
I1 => \^y[13]\,
I2 => mantissa2_carry_n_2,
I3 => \x[9]_3\,
O => \y[20]_INST_0_i_2_n_0\
);
\y[20]_INST_0_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFDF"
)
port map (
I0 => O(0),
I1 => \y[16]_INST_0_i_4_n_0\,
I2 => CO(0),
I3 => mantissa2_carry_n_2,
O => \y[20]_INST_0_i_3_n_0\
);
\y[20]_INST_0_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"E1FFE100"
)
port map (
I0 => \^y[23]\,
I1 => \^y[18]\,
I2 => \^y[22]_0\,
I3 => mantissa2_carry_n_2,
I4 => O(1),
O => \y[20]_INST_0_i_4_n_0\
);
\y[21]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EAFFEA00EAFFEAFF"
)
port map (
I0 => \y[21]_INST_0_i_1_n_0\,
I1 => \x_9__s_net_1\,
I2 => mantissa2_carry_n_2,
I3 => \^y[23]\,
I4 => \y[21]_INST_0_i_2_n_0\,
I5 => \y[21]_INST_0_i_3_n_0\,
O => y(8)
);
\y[21]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0400044400000000"
)
port map (
I0 => \y[21]_INST_0_i_4_n_0\,
I1 => x(8),
I2 => \^y[22]\,
I3 => mantissa2_carry_n_2,
I4 => O(1),
I5 => \y[21]_INST_0_i_6_n_0\,
O => \y[21]_INST_0_i_1_n_0\
);
\y[21]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0020000000202020"
)
port map (
I0 => \y[21]_INST_0_i_6_n_0\,
I1 => \y[21]_INST_0_i_4_n_0\,
I2 => x(9),
I3 => \^y[22]\,
I4 => mantissa2_carry_n_2,
I5 => O(1),
O => \y[21]_INST_0_i_2_n_0\
);
\y[21]_INST_0_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"2FEF"
)
port map (
I0 => \x[9]_0\,
I1 => \^y[13]\,
I2 => mantissa2_carry_n_2,
I3 => \x[9]_1\,
O => \y[21]_INST_0_i_3_n_0\
);
\y[21]_INST_0_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"55A9FFFF55A90000"
)
port map (
I0 => p_1_out(0),
I1 => \^y[23]\,
I2 => \^y[18]\,
I3 => \^y[22]_0\,
I4 => mantissa2_carry_n_2,
I5 => O(2),
O => \y[21]_INST_0_i_4_n_0\
);
\y[21]_INST_0_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"00D0"
)
port map (
I0 => O(0),
I1 => \y[16]_INST_0_i_4_n_0\,
I2 => CO(0),
I3 => mantissa2_carry_n_2,
O => \y[21]_INST_0_i_6_n_0\
);
\y[22]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EEE222E200000000"
)
port map (
I0 => \x_9__s_net_1\,
I1 => \^y[23]\,
I2 => \x[9]_1\,
I3 => \^y[13]\,
I4 => \x[9]_5\,
I5 => mantissa2_carry_n_2,
O => y(9)
);
\y[22]_INST_0_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^y[23]\,
I1 => \^y[18]\,
O => \^y[13]\
);
\y[22]_INST_0_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"E1"
)
port map (
I0 => \^y[23]\,
I1 => \^y[18]\,
I2 => \^y[22]_0\,
O => \^y[22]\
);
\y[22]_INST_0_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"EEEEEEEEEEEEFF10"
)
port map (
I0 => \^y[18]\,
I1 => \^y[23]\,
I2 => \^y[20]_0\,
I3 => \^y[21]\,
I4 => x(8),
I5 => x(9),
O => \^y[20]\
);
\y[23]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF00005504"
)
port map (
I0 => x(3),
I1 => x(0),
I2 => x(1),
I3 => x(2),
I4 => \y[23]_INST_0_i_1_n_0\,
I5 => \y[23]_INST_0_i_2_n_0\,
O => \^y[23]\
);
\y[23]_INST_0_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"FE"
)
port map (
I0 => x(5),
I1 => x(9),
I2 => x(7),
O => \y[23]_INST_0_i_1_n_0\
);
\y[23]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000F0FFF0F4"
)
port map (
I0 => x(5),
I1 => x(4),
I2 => x(8),
I3 => x(7),
I4 => x(6),
I5 => x(9),
O => \y[23]_INST_0_i_2_n_0\
);
\y[25]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"888888888888888A"
)
port map (
I0 => \^y[22]_1\,
I1 => \^y[21]\,
I2 => x(1),
I3 => x(0),
I4 => x(2),
I5 => x(3),
O => \^y[22]_0\
);
\y[27]_INST_0_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFF01"
)
port map (
I0 => \y[27]_INST_0_i_4_n_0\,
I1 => x(7),
I2 => x(6),
I3 => x(9),
I4 => x(8),
O => \^y[18]\
);
\y[27]_INST_0_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => x(4),
I1 => x(5),
I2 => x(6),
I3 => x(7),
O => \^y[21]\
);
\y[27]_INST_0_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => x(1),
I1 => x(0),
I2 => x(2),
I3 => x(3),
O => \^y[20]_0\
);
\y[27]_INST_0_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"1110111011101111"
)
port map (
I0 => x(4),
I1 => x(5),
I2 => x(3),
I3 => x(2),
I4 => x(0),
I5 => x(1),
O => \y[27]_INST_0_i_4_n_0\
);
\y[30]_INST_0_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => x(8),
I1 => x(9),
O => \^y[22]_1\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity affine_block_uint_to_ieee754_fp_0_1 is
port (
x : in STD_LOGIC_VECTOR ( 9 downto 0 );
y : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of affine_block_uint_to_ieee754_fp_0_1 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of affine_block_uint_to_ieee754_fp_0_1 : entity is "affine_block_uint_to_ieee754_fp_0_1,uint_to_ieee754_fp,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of affine_block_uint_to_ieee754_fp_0_1 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of affine_block_uint_to_ieee754_fp_0_1 : entity is "uint_to_ieee754_fp,Vivado 2016.4";
end affine_block_uint_to_ieee754_fp_0_1;
architecture STRUCTURE of affine_block_uint_to_ieee754_fp_0_1 is
signal \<const0>\ : STD_LOGIC;
signal U0_n_0 : STD_LOGIC;
signal U0_n_12 : STD_LOGIC;
signal U0_n_13 : STD_LOGIC;
signal U0_n_14 : STD_LOGIC;
signal U0_n_15 : STD_LOGIC;
signal U0_n_16 : STD_LOGIC;
signal U0_n_17 : STD_LOGIC;
signal U0_n_18 : STD_LOGIC;
signal p_1_out : STD_LOGIC_VECTOR ( 3 to 3 );
signal \^y\ : STD_LOGIC_VECTOR ( 30 downto 13 );
signal \y[20]_INST_0_i_5_n_0\ : STD_LOGIC;
signal \y[20]_INST_0_i_6_n_0\ : STD_LOGIC;
signal \y[21]_INST_0_i_10_n_0\ : STD_LOGIC;
signal \y[21]_INST_0_i_11_n_0\ : STD_LOGIC;
signal \y[21]_INST_0_i_5_n_0\ : STD_LOGIC;
signal \y[21]_INST_0_i_5_n_2\ : STD_LOGIC;
signal \y[21]_INST_0_i_5_n_3\ : STD_LOGIC;
signal \y[21]_INST_0_i_5_n_5\ : STD_LOGIC;
signal \y[21]_INST_0_i_5_n_6\ : STD_LOGIC;
signal \y[21]_INST_0_i_5_n_7\ : STD_LOGIC;
signal \y[21]_INST_0_i_7_n_0\ : STD_LOGIC;
signal \y[21]_INST_0_i_9_n_0\ : STD_LOGIC;
signal \y[22]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \y[22]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \y[22]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \y[22]_INST_0_i_5_n_0\ : STD_LOGIC;
signal \y[30]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \NLW_y[21]_INST_0_i_5_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 to 2 );
signal \NLW_y[21]_INST_0_i_5_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \y[20]_INST_0_i_5\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \y[21]_INST_0_i_7\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \y[22]_INST_0_i_4\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \y[22]_INST_0_i_5\ : label is "soft_lutpair8";
begin
y(31) <= \<const0>\;
y(30) <= \^y\(30);
y(29) <= \^y\(27);
y(28) <= \^y\(27);
y(27 downto 13) <= \^y\(27 downto 13);
y(12) <= \<const0>\;
y(11) <= \<const0>\;
y(10) <= \<const0>\;
y(9) <= \<const0>\;
y(8) <= \<const0>\;
y(7) <= \<const0>\;
y(6) <= \<const0>\;
y(5) <= \<const0>\;
y(4) <= \<const0>\;
y(3) <= \<const0>\;
y(2) <= \<const0>\;
y(1) <= \<const0>\;
y(0) <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
U0: entity work.affine_block_uint_to_ieee754_fp_0_1_uint_to_ieee754_fp
port map (
CO(0) => \y[21]_INST_0_i_5_n_0\,
O(2) => \y[21]_INST_0_i_5_n_5\,
O(1) => \y[21]_INST_0_i_5_n_6\,
O(0) => \y[21]_INST_0_i_5_n_7\,
p_1_out(0) => p_1_out(3),
x(9 downto 0) => x(9 downto 0),
\x[9]_0\ => \y[21]_INST_0_i_7_n_0\,
\x[9]_1\ => \y[22]_INST_0_i_2_n_0\,
\x[9]_2\ => \y[20]_INST_0_i_5_n_0\,
\x[9]_3\ => \y[20]_INST_0_i_6_n_0\,
\x[9]_4\ => \y[30]_INST_0_i_1_n_0\,
\x[9]_5\ => \y[22]_INST_0_i_4_n_0\,
\x_9__s_port_]\ => \y[22]_INST_0_i_1_n_0\,
y(9 downto 0) => \^y\(22 downto 13),
\y[13]\ => U0_n_0,
\y[18]\ => U0_n_14,
\y[20]\ => U0_n_13,
\y[20]_0\ => U0_n_18,
\y[21]\ => U0_n_17,
\y[22]\ => U0_n_12,
\y[22]_0\ => U0_n_15,
\y[22]_1\ => U0_n_16,
\y[23]\ => \^y\(23)
);
\y[20]_INST_0_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"4F7F"
)
port map (
I0 => x(0),
I1 => U0_n_12,
I2 => U0_n_13,
I3 => x(4),
O => \y[20]_INST_0_i_5_n_0\
);
\y[20]_INST_0_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"B080"
)
port map (
I0 => x(2),
I1 => U0_n_12,
I2 => U0_n_13,
I3 => x(6),
O => \y[20]_INST_0_i_6_n_0\
);
\y[21]_INST_0_i_10\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => U0_n_12,
O => \y[21]_INST_0_i_10_n_0\
);
\y[21]_INST_0_i_11\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^y\(23),
I1 => U0_n_14,
O => \y[21]_INST_0_i_11_n_0\
);
\y[21]_INST_0_i_5\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \y[21]_INST_0_i_5_n_0\,
CO(2) => \NLW_y[21]_INST_0_i_5_CO_UNCONNECTED\(2),
CO(1) => \y[21]_INST_0_i_5_n_2\,
CO(0) => \y[21]_INST_0_i_5_n_3\,
CYINIT => \^y\(23),
DI(3 downto 0) => B"0000",
O(3) => \NLW_y[21]_INST_0_i_5_O_UNCONNECTED\(3),
O(2) => \y[21]_INST_0_i_5_n_5\,
O(1) => \y[21]_INST_0_i_5_n_6\,
O(0) => \y[21]_INST_0_i_5_n_7\,
S(3) => '1',
S(2) => \y[21]_INST_0_i_9_n_0\,
S(1) => \y[21]_INST_0_i_10_n_0\,
S(0) => \y[21]_INST_0_i_11_n_0\
);
\y[21]_INST_0_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"4F7F"
)
port map (
I0 => x(1),
I1 => U0_n_12,
I2 => U0_n_13,
I3 => x(5),
O => \y[21]_INST_0_i_7_n_0\
);
\y[21]_INST_0_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAAAAAAAAA8"
)
port map (
I0 => U0_n_16,
I1 => U0_n_17,
I2 => x(1),
I3 => x(0),
I4 => x(2),
I5 => x(3),
O => p_1_out(3)
);
\y[21]_INST_0_i_9\: unisim.vcomponents.LUT6
generic map(
INIT => X"EEEEEEEEEEEEFF10"
)
port map (
I0 => U0_n_14,
I1 => \^y\(23),
I2 => U0_n_18,
I3 => U0_n_17,
I4 => x(8),
I5 => x(9),
O => \y[21]_INST_0_i_9_n_0\
);
\y[22]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"B8BB8888B8888888"
)
port map (
I0 => \y[22]_INST_0_i_5_n_0\,
I1 => U0_n_0,
I2 => x(2),
I3 => U0_n_12,
I4 => U0_n_13,
I5 => x(6),
O => \y[22]_INST_0_i_1_n_0\
);
\y[22]_INST_0_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"C888"
)
port map (
I0 => x(7),
I1 => U0_n_13,
I2 => x(3),
I3 => U0_n_12,
O => \y[22]_INST_0_i_2_n_0\
);
\y[22]_INST_0_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"B833B800"
)
port map (
I0 => x(5),
I1 => U0_n_12,
I2 => x(9),
I3 => U0_n_13,
I4 => x(1),
O => \y[22]_INST_0_i_4_n_0\
);
\y[22]_INST_0_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"B833B800"
)
port map (
I0 => x(4),
I1 => U0_n_12,
I2 => x(8),
I3 => U0_n_13,
I4 => x(0),
O => \y[22]_INST_0_i_5_n_0\
);
\y[24]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"41"
)
port map (
I0 => \y[30]_INST_0_i_1_n_0\,
I1 => \^y\(23),
I2 => U0_n_14,
O => \^y\(24)
);
\y[25]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0078"
)
port map (
I0 => U0_n_14,
I1 => \^y\(23),
I2 => U0_n_15,
I3 => \y[30]_INST_0_i_1_n_0\,
O => \^y\(25)
);
\y[26]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => x(9),
I1 => \^y\(27),
O => \^y\(26)
);
\y[27]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000800000000"
)
port map (
I0 => U0_n_14,
I1 => \^y\(23),
I2 => x(9),
I3 => x(8),
I4 => U0_n_17,
I5 => U0_n_18,
O => \^y\(27)
);
\y[30]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \y[30]_INST_0_i_1_n_0\,
I1 => \^y\(27),
O => \^y\(30)
);
\y[30]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000100000000"
)
port map (
I0 => U0_n_17,
I1 => x(1),
I2 => x(0),
I3 => x(2),
I4 => x(3),
I5 => U0_n_16,
O => \y[30]_INST_0_i_1_n_0\
);
end STRUCTURE;
| mit |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_transform_test/zed_transform_test.srcs/sources_1/bd/system/ipshared/1d6f/inverter.vhd | 11 | 538 | ----------------------------------------------------------------------------------
-- Company: Drexel University
-- Engineer: Robert Taglang
--
-- Module Name: inverter - Structural
-- Description: Invert an input signal
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity inverter is
port(
x : in std_logic;
x_not : out std_logic
);
end inverter;
architecture Structural of inverter is
begin
x_not <= not x;
end Structural;
| mit |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/affine_transform_demo/affine_transform_demo.srcs/sources_1/bd/system/ipshared/1d6f/inverter.vhd | 11 | 538 | ----------------------------------------------------------------------------------
-- Company: Drexel University
-- Engineer: Robert Taglang
--
-- Module Name: inverter - Structural
-- Description: Invert an input signal
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity inverter is
port(
x : in std_logic;
x_not : out std_logic
);
end inverter;
architecture Structural of inverter is
begin
x_not <= not x;
end Structural;
| mit |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/ov7670_hessian_split/ov7670_hessian_split.srcs/sources_1/bd/system/ipshared/1d6f/inverter.vhd | 11 | 538 | ----------------------------------------------------------------------------------
-- Company: Drexel University
-- Engineer: Robert Taglang
--
-- Module Name: inverter - Structural
-- Description: Invert an input signal
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity inverter is
port(
x : in std_logic;
x_not : out std_logic
);
end inverter;
architecture Structural of inverter is
begin
x_not <= not x;
end Structural;
| mit |
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