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CprE488/Final | system/implementation/system_axi_interconnect_1_wrapper_fifo_generator_v9_1_1/simulation/system_axi_interconnect_1_wrapper_fifo_generator_v9_1_1_pctrl.vhd | 1 | 15657 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_interconnect_1_wrapper_fifo_generator_v9_1_1_pctrl.vhd
--
-- Description:
-- Used for protocol control on write and read interface stimulus and status generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.system_axi_interconnect_1_wrapper_fifo_generator_v9_1_1_pkg.ALL;
ENTITY system_axi_interconnect_1_wrapper_fifo_generator_v9_1_1_pctrl IS
GENERIC(
AXI_CHANNEL : STRING :="NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_pc_arch OF system_axi_interconnect_1_wrapper_fifo_generator_v9_1_1_pctrl IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
CONSTANT D_WIDTH_DIFF : INTEGER := log2roundup(C_DOUT_WIDTH/C_DIN_WIDTH);
SIGNAL data_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL full_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL empty_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL status_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL status_d1_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL rd_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_cntr : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL full_as_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL full_ds_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL rd_cntr : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_as_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_ds_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL state : STD_LOGIC := '0';
SIGNAL wr_control : STD_LOGIC := '0';
SIGNAL rd_control : STD_LOGIC := '0';
SIGNAL stop_on_err : STD_LOGIC := '0';
SIGNAL sim_stop_cntr : STD_LOGIC_VECTOR(7 DOWNTO 0):= conv_std_logic_vector(if_then_else(C_CH_TYPE=2,64,TB_STOP_CNT),8);
SIGNAL sim_done_i : STD_LOGIC := '0';
SIGNAL rdw_gt_wrw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL wrw_gt_rdw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL rd_activ_cont : STD_LOGIC_VECTOR(25 downto 0):= (OTHERS => '0');
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL reset_en_i : STD_LOGIC := '0';
SIGNAL state_d1 : STD_LOGIC := '0';
SIGNAL post_rst_dly_wr : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
SIGNAL post_rst_dly_rd : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
BEGIN
status_i <= data_chk_i & full_chk_i & empty_chk_i & '0' & '0';
STATUS <= status_d1_i & '0' & '0' & rd_activ_cont(rd_activ_cont'high);
prc_we_i <= wr_en_i WHEN sim_done_i = '0' ELSE '0';
prc_re_i <= rd_en_i WHEN sim_done_i = '0' ELSE '0';
SIM_DONE <= sim_done_i;
rdw_gt_wrw <= (OTHERS => '1');
wrw_gt_rdw <= (OTHERS => '1');
PROCESS(RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(prc_re_i = '1') THEN
rd_activ_cont <= rd_activ_cont + "1";
END IF;
END IF;
END PROCESS;
PROCESS(sim_done_i)
BEGIN
assert sim_done_i = '0'
report "Simulation Complete for:" & AXI_CHANNEL
severity note;
END PROCESS;
-----------------------------------------------------
-- SIM_DONE SIGNAL GENERATION
-----------------------------------------------------
PROCESS (RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
--sim_done_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF((OR_REDUCE(sim_stop_cntr) = '0' AND TB_STOP_CNT /= 0) OR stop_on_err = '1') THEN
sim_done_i <= '1';
END IF;
END IF;
END PROCESS;
-- TB Timeout/Stop
fifo_tb_stop_run:IF(TB_STOP_CNT /= 0) GENERATE
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0' AND state_d1 = '1') THEN
sim_stop_cntr <= sim_stop_cntr - "1";
END IF;
END IF;
END PROCESS;
END GENERATE fifo_tb_stop_run;
-- Stop when error found
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(sim_done_i = '0') THEN
status_d1_i <= status_i OR status_d1_i;
END IF;
IF(FREEZEON_ERROR = 1 AND status_i /= "0") THEN
stop_on_err <= '1';
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-----------------------------------------------------
-- CHECKS FOR FIFO
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
post_rst_dly_rd <= (OTHERS => '1');
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
post_rst_dly_rd <= post_rst_dly_rd-post_rst_dly_rd(4);
END IF;
END PROCESS;
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
post_rst_dly_wr <= (OTHERS => '1');
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
post_rst_dly_wr <= post_rst_dly_wr-post_rst_dly_wr(4);
END IF;
END PROCESS;
-- FULL de-assert Counter
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_ds_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(rd_en_i = '1' AND wr_en_i = '0' AND FULL = '1' AND AND_REDUCE(wrw_gt_rdw) = '1') THEN
full_ds_timeout <= full_ds_timeout + '1';
END IF;
ELSE
full_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- EMPTY deassert counter
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_ds_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(wr_en_i = '1' AND rd_en_i = '0' AND EMPTY = '1' AND AND_REDUCE(rdw_gt_wrw) = '1') THEN
empty_ds_timeout <= empty_ds_timeout + '1';
END IF;
ELSE
empty_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- Full check signal generation
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_chk_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
full_chk_i <= '0';
ELSE
full_chk_i <= AND_REDUCE(full_as_timeout) OR
AND_REDUCE(full_ds_timeout);
END IF;
END IF;
END PROCESS;
-- Empty checks
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_chk_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
empty_chk_i <= '0';
ELSE
empty_chk_i <= AND_REDUCE(empty_as_timeout) OR
AND_REDUCE(empty_ds_timeout);
END IF;
END IF;
END PROCESS;
fifo_d_chk:IF(C_CH_TYPE /= 2) GENERATE
PRC_WR_EN <= prc_we_i AFTER 50 ns;
PRC_RD_EN <= prc_re_i AFTER 50 ns;
data_chk_i <= dout_chk;
END GENERATE fifo_d_chk;
-----------------------------------------------------
RESET_EN <= reset_en_i;
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
state_d1 <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
state_d1 <= state;
END IF;
END PROCESS;
data_fifo_en:IF(C_CH_TYPE /= 2) GENERATE
-----------------------------------------------------
-- WR_EN GENERATION
-----------------------------------------------------
gen_rand_wr_en:system_axi_interconnect_1_wrapper_fifo_generator_v9_1_1_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+1
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET_WR,
RANDOM_NUM => wr_en_gen,
ENABLE => '1'
);
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
wr_en_i <= wr_en_gen(0) AND wr_en_gen(7) AND wr_en_gen(2) AND wr_control;
ELSE
wr_en_i <= (wr_en_gen(3) OR wr_en_gen(4) OR wr_en_gen(2)) AND (NOT post_rst_dly_wr(4));
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- WR_EN CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_cntr <= (OTHERS => '0');
wr_control <= '1';
full_as_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(wr_en_i = '1') THEN
wr_cntr <= wr_cntr + "1";
END IF;
full_as_timeout <= (OTHERS => '0');
ELSE
wr_cntr <= (OTHERS => '0');
IF(rd_en_i = '0') THEN
IF(wr_en_i = '1') THEN
full_as_timeout <= full_as_timeout + "1";
END IF;
ELSE
full_as_timeout <= (OTHERS => '0');
END IF;
END IF;
wr_control <= NOT wr_cntr(wr_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN GENERATION
-----------------------------------------------------
gen_rand_rd_en:system_axi_interconnect_1_wrapper_fifo_generator_v9_1_1_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED
)
PORT MAP(
CLK => RD_CLK,
RESET => RESET_RD,
RANDOM_NUM => rd_en_gen,
ENABLE => '1'
);
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_en_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
rd_en_i <= rd_en_gen(1) AND rd_en_gen(5) AND rd_en_gen(3) AND rd_control AND (NOT post_rst_dly_rd(4));
ELSE
rd_en_i <= rd_en_gen(0) OR rd_en_gen(6);
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN CONTROL
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_cntr <= (OTHERS => '0');
rd_control <= '1';
empty_as_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(rd_en_i = '1') THEN
rd_cntr <= rd_cntr + "1";
END IF;
empty_as_timeout <= (OTHERS => '0');
ELSE
rd_cntr <= (OTHERS => '0');
IF(wr_en_i = '0') THEN
IF(rd_en_i = '1') THEN
empty_as_timeout <= empty_as_timeout + "1";
END IF;
ELSE
empty_as_timeout <= (OTHERS => '0');
END IF;
END IF;
rd_control <= NOT rd_cntr(rd_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- STIMULUS CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
state <= '0';
reset_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
CASE state IS
WHEN '0' =>
IF(FULL = '1' AND EMPTY = '0') THEN
state <= '1';
reset_en_i <= '0';
END IF;
WHEN '1' =>
IF(EMPTY = '1' AND FULL = '0') THEN
state <= '0';
reset_en_i <= '1';
END IF;
WHEN OTHERS => state <= state;
END CASE;
END IF;
END PROCESS;
END GENERATE data_fifo_en;
END ARCHITECTURE;
| gpl-3.0 |
EliasLuiz/TCC | Leon3/designs/leon3-xilinx-ml50x/testbench.vhd | 1 | 13438 | -----------------------------------------------------------------------------
-- LEON Demonstration design test bench
-- Copyright (C) 2004 - 2015 Cobham Gaisler AB
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.config.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
library techmap;
use techmap.gencomp.all;
library micron;
use micron.components.all;
library cypress;
use cypress.components.all;
use work.debug.all;
use work.config.all; -- configuration
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
transtech : integer := CFG_TRANSTECH;
clktech : integer := CFG_CLKTECH;
ncpu : integer := CFG_NCPU;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
clkperiod : integer := 10; -- system clock period
romwidth : integer := 32; -- rom data width (8/32)
romdepth : integer := 16; -- rom address depth
sramwidth : integer := 32; -- ram data width (8/16/32)
sramdepth : integer := 18; -- ram address depth
srambanks : integer := 2 -- number of ram banks
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec"; -- rom contents
constant sramfile : string := "ram.srec"; -- ram contents
constant sdramfile : string := "ram.srec"; -- sdram contents
signal sys_clk : std_logic := '0';
signal sys_rst_in : std_logic := '0'; -- Reset
constant ct : integer := clkperiod/2;
constant slips : integer := 11;
signal bus_error : std_logic_vector (1 downto 0);
signal sram_flash_addr : std_logic_vector(23 downto 0);
signal address : std_logic_vector(24 downto 0);
signal sram_flash_data, data : std_logic_vector(31 downto 0);
signal sram_cen : std_logic;
signal sram_bw : std_logic_vector (3 downto 0);
signal sram_oen : std_ulogic;
signal flash_oen : std_ulogic;
signal sram_flash_we_n : std_ulogic;
signal flash_cen : std_logic;
signal flash_adv_n : std_logic;
signal sram_clk : std_ulogic;
signal sram_clk_fb : std_ulogic;
signal sram_mode : std_ulogic;
signal sram_adv_ld_n : std_ulogic;
signal iosn : std_ulogic;
signal ddr_clk : std_logic_vector(1 downto 0);
signal ddr_clkb : std_logic_vector(1 downto 0);
signal ddr_cke : std_logic_vector(1 downto 0);
signal ddr_csb : std_logic_vector(1 downto 0);
signal ddr_odt : std_logic_vector(1 downto 0);
signal ddr_web : std_ulogic; -- ddr write enable
signal ddr_rasb : std_ulogic; -- ddr ras
signal ddr_casb : std_ulogic; -- ddr cas
signal ddr_dm : std_logic_vector (7 downto 0); -- ddr dm
signal ddr_dqsp : std_logic_vector (7 downto 0); -- ddr dqs
signal ddr_dqsn : std_logic_vector (7 downto 0); -- ddr dqs
signal ddr_rdqs : std_logic_vector (7 downto 0); -- ddr dqs
signal ddr_ad : std_logic_vector (13 downto 0); -- ddr address
signal ddr_ba : std_logic_vector (1+CFG_DDR2SP downto 0); -- ddr bank address
signal ddr_dq : std_logic_vector (63 downto 0); -- ddr data
signal ddr_dq2 : std_logic_vector (63 downto 0); -- ddr data
signal txd1 : std_ulogic; -- UART1 tx data
signal rxd1 : std_ulogic; -- UART1 rx data
signal txd2 : std_ulogic; -- UART2 tx data
signal rxd2 : std_ulogic; -- UART2 rx data
signal gpio : std_logic_vector(12 downto 0); -- I/O port
signal led : std_logic_vector(12 downto 0); -- I/O port
signal phy_mii_data: std_logic; -- ethernet PHY interface
signal phy_tx_clk : std_ulogic;
signal phy_rx_clk : std_ulogic;
signal phy_rx_data : std_logic_vector(7 downto 0);
signal phy_dv : std_ulogic;
signal phy_rx_er : std_ulogic;
signal phy_col : std_ulogic;
signal phy_crs : std_ulogic;
signal phy_tx_data : std_logic_vector(7 downto 0);
signal phy_tx_en : std_ulogic;
signal phy_tx_er : std_ulogic;
signal phy_mii_clk : std_ulogic;
signal phy_rst_n : std_ulogic;
signal phy_int : std_ulogic := '0';
signal phy_gtx_clk : std_ulogic;
signal sgmii_rx_n : std_ulogic;
signal sgmii_rx_p : std_ulogic;
signal sgmii_rx_n_d : std_ulogic;
signal sgmii_rx_p_d : std_ulogic;
signal sgmii_tx_n : std_ulogic;
signal sgmii_tx_p : std_ulogic;
signal ps2_keyb_clk: std_logic;
signal ps2_keyb_data: std_logic;
signal ps2_mouse_clk: std_logic;
signal ps2_mouse_data: std_logic;
signal usb_csn, usb_rstn : std_logic;
signal iic_scl_main, iic_sda_main : std_logic;
signal iic_scl_video, iic_sda_video : std_logic;
signal tft_lcd_data : std_logic_vector(11 downto 0);
signal tft_lcd_clk_p : std_logic;
signal tft_lcd_clk_n : std_logic;
signal tft_lcd_hsync : std_logic;
signal tft_lcd_vsync : std_logic;
signal tft_lcd_de : std_logic;
signal tft_lcd_reset_b : std_logic;
signal sysace_mpa : std_logic_vector(6 downto 0);
signal sysace_mpce : std_ulogic;
signal sysace_mpirq : std_ulogic;
signal sysace_mpoe : std_ulogic;
signal sysace_mpwe : std_ulogic;
signal sysace_d : std_logic_vector(15 downto 0);
--pcie--
signal cor_sys_reset_n : std_logic := '1';
signal ep_sys_clk_p : std_logic;
signal ep_sys_clk_n : std_logic;
signal rp_sys_clk : std_logic;
signal cor_pci_exp_txn : std_logic_vector(CFG_NO_OF_LANES-1 downto 0) := (others => '0');
signal cor_pci_exp_txp : std_logic_vector(CFG_NO_OF_LANES-1 downto 0) := (others => '0');
signal cor_pci_exp_rxn : std_logic_vector(CFG_NO_OF_LANES-1 downto 0) := (others => '0');
signal cor_pci_exp_rxp : std_logic_vector(CFG_NO_OF_LANES-1 downto 0) := (others => '0');
--pcie end--
signal GND : std_ulogic := '0';
signal VCC : std_ulogic := '1';
signal NC : std_ulogic := 'Z';
signal clk_200_p : std_ulogic := '0';
signal clk_200_n : std_ulogic := '1';
signal clk_33 : std_ulogic := '0';
signal clk_125_p : std_ulogic := '0';
signal clk_125_n : std_ulogic := '1';
signal rst_125 : std_ulogic;
constant lresp : boolean := false;
begin
-- clock and reset
sys_clk <= not sys_clk after ct * 1 ns;
sys_rst_in <= '0', '1' after 200 ns;
clk_200_p <= not clk_200_p after 2.5 ns;
clk_200_n <= not clk_200_n after 2.5 ns;
clk_125_p <= not clk_125_p after 4 ns;
clk_125_n <= not clk_125_n after 4 ns;
clk_33 <= not clk_33 after 15 ns;
rxd1 <= 'H'; gpio(11) <= 'L';
sram_clk_fb <= sram_clk;
ps2_keyb_data <= 'H'; ps2_keyb_clk <= 'H';
ps2_mouse_clk <= 'H'; ps2_mouse_data <= 'H';
iic_scl_main <= 'H'; iic_sda_main <= 'H';
iic_scl_video <= 'H'; iic_sda_video <= 'H';
sysace_d <= (others => 'H'); sysace_mpirq <= 'L';
cpu : entity work.leon3mp
generic map ( fabtech, memtech, padtech, transtech, ncpu, disas, dbguart, pclow )
port map ( sys_rst_in, sys_clk, clk_200_p, clk_200_n, clk_33, sram_flash_addr,
sram_flash_data, sram_cen, sram_bw, sram_oen, sram_flash_we_n,
flash_cen, flash_oen, flash_adv_n,sram_clk, sram_clk_fb, sram_mode,
sram_adv_ld_n, iosn,
ddr_clk, ddr_clkb, ddr_cke, ddr_csb, ddr_odt, ddr_web,
ddr_rasb, ddr_casb, ddr_dm, ddr_dqsp, ddr_dqsn, ddr_ad, ddr_ba, ddr_dq,
txd1, rxd1, txd2, rxd2, gpio, led, bus_error,
phy_gtx_clk, phy_mii_data, phy_tx_clk, phy_rx_clk,
phy_rx_data, phy_dv, phy_rx_er, phy_col, phy_crs,
phy_tx_data, phy_tx_en, phy_tx_er, phy_mii_clk, phy_rst_n, phy_int,
sgmii_rx_n, sgmii_rx_p, sgmii_tx_n, sgmii_tx_p, clk_125_n, clk_125_p,
ps2_keyb_clk, ps2_keyb_data, ps2_mouse_clk, ps2_mouse_data,
usb_csn, usb_rstn,
iic_scl_main, iic_sda_main,
iic_scl_video, iic_sda_video,
tft_lcd_data, tft_lcd_clk_p, tft_lcd_clk_n, tft_lcd_hsync,
tft_lcd_vsync, tft_lcd_de, tft_lcd_reset_b,
sysace_mpa, sysace_mpce, sysace_mpirq, sysace_mpoe,
sysace_mpwe, sysace_d, cor_pci_exp_txp, cor_pci_exp_txn, cor_pci_exp_rxp,
cor_pci_exp_rxn, ep_sys_clk_p, ep_sys_clk_n, cor_sys_reset_n
);
ddr0 : ddr2ram
generic map(width => 64, abits => 13, babits =>2, colbits => 10, rowbits => 13,
implbanks => 1, fname => sdramfile, speedbin=>1, density => 2,
lddelay => 100 us * CFG_MIG_DDR2)
port map (ck => ddr_clk(0), ckn => ddr_clkb(0), cke => ddr_cke(0), csn => ddr_csb(0),
odt => ddr_odt(0), rasn => ddr_rasb, casn => ddr_casb, wen => ddr_web,
dm => ddr_dm, ba => ddr_ba(1 downto 0), a => ddr_ad(12 downto 0), dq => ddr_dq2,
dqs => ddr_dqsp, dqsn =>ddr_dqsn);
nodqdel : if (CFG_MIG_DDR2 = 1) generate
ddr2delay : delay_wire
generic map(data_width => ddr_dq'length, delay_atob => 0.0, delay_btoa => 0.0)
port map(a => ddr_dq, b => ddr_dq2);
end generate;
dqdel : if (CFG_MIG_DDR2 = 0) generate
ddr2delay : delay_wire
generic map(data_width => ddr_dq'length, delay_atob => 0.0, delay_btoa => 5.5)
port map(a => ddr_dq, b => ddr_dq2);
end generate;
sram01 : for i in 0 to 1 generate
sr0 : sram generic map (index => i, abits => sramdepth, fname => sramfile)
port map (sram_flash_addr(sramdepth downto 1), sram_flash_data(15-i*8 downto 8-i*8),
sram_cen, sram_bw(i+2), sram_oen);
end generate;
sram23 : for i in 2 to 3 generate
sr0 : sram generic map (index => i, abits => sramdepth, fname => sramfile)
port map (sram_flash_addr(sramdepth downto 1), sram_flash_data(47-i*8 downto 40-i*8),
sram_cen, sram_bw(i-2), sram_oen);
end generate;
prom0 : sram16 generic map (index => 4, abits => romdepth, fname => promfile)
port map (sram_flash_addr(romdepth-1 downto 0), sram_flash_data(15 downto 0),
gnd, gnd, flash_cen, sram_flash_we_n, flash_oen);
gmii_phy: if CFG_GRETH_SGMII = 0 generate
phy_mii_data <= 'H';
p0: phy
generic map (address => 7)
port map(phy_rst_n, phy_mii_data, phy_tx_clk, phy_rx_clk, phy_rx_data,
phy_dv, phy_rx_er, phy_col, phy_crs, phy_tx_data, phy_tx_en,
phy_tx_er, phy_mii_clk, phy_gtx_clk);
end generate;
sgmii_phy: if CFG_GRETH_SGMII /= 0 generate
-- delaying rx line
sgmii_rx_p <= transport sgmii_rx_p_d after 0.8 ns * slips;
sgmii_rx_n <= transport sgmii_rx_n_d after 0.8 ns * slips;
rst_125 <= not phy_rst_n;
sp0: ser_phy
generic map(
address => 7,
extended_regs => 1,
aneg => 1,
fd_10 => 1,
hd_10 => 1,
base100_t4 => 1,
base100_x_fd => 1,
base100_x_hd => 1,
base100_t2_fd => 1,
base100_t2_hd => 1,
base1000_x_fd => 1,
base1000_x_hd => 1,
base1000_t_fd => 1,
base1000_t_hd => 1,
fabtech => virtex5,
memtech => virtex5
)
port map(
rstn => phy_rst_n,
clk_125 => clk_125_p,
rst_125 => rst_125,
eth_rx_p => sgmii_rx_p_d,
eth_rx_n => sgmii_rx_n_d,
eth_tx_p => sgmii_tx_p,
eth_tx_n => sgmii_tx_n,
mdio => phy_mii_data,
mdc => phy_mii_clk
);
end generate;
i0: i2c_slave_model
port map (iic_scl_main, iic_sda_main);
iuerr : process
begin
wait for 5000 ns;
if to_x01(bus_error(0)) = '0' then wait on bus_error; end if;
assert (to_x01(bus_error(0)) = '0')
report "*** IU in error mode, simulation halted ***"
severity failure ;
end process;
data <= sram_flash_data(15 downto 0) & sram_flash_data(31 downto 16);
address <= sram_flash_addr & '0';
test0 : grtestmod
port map ( sys_rst_in, sys_clk, bus_error(0), sram_flash_addr(20 downto 1), data,
iosn, flash_oen, sram_bw(0), open);
sram_flash_data <= buskeep(sram_flash_data), (others => 'H') after 250 ns;
-- ddr_dq <= buskeep(ddr_dq), (others => 'H') after 250 ns;
data <= buskeep(data), (others => 'H') after 250 ns;
end ;
| gpl-3.0 |
EliasLuiz/TCC | Leon3/lib/gaisler/misc/grgpio.in.vhd | 6 | 208 | -- GPIO port
constant CFG_GRGPIO_ENABLE : integer := CONFIG_GRGPIO_ENABLE;
constant CFG_GRGPIO_IMASK : integer := 16#CONFIG_GRGPIO_IMASK#;
constant CFG_GRGPIO_WIDTH : integer := CONFIG_GRGPIO_WIDTH;
| gpl-3.0 |
EliasLuiz/TCC | Leon3/lib/techmap/maps/iodpad.vhd | 1 | 5278 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: iodpad
-- File: iodpad.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Open-drain I/O pad with technology wrapper
------------------------------------------------------------------------------
library ieee;
library techmap;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
use techmap.allpads.all;
entity iodpad is
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12;
oepol : integer := 0);
port (pad : inout std_ulogic; i : in std_ulogic; o : out std_ulogic);
end;
architecture rtl of iodpad is
signal gnd, oen : std_ulogic;
begin
oen <= not i when oepol /= padoen_polarity(tech) else i;
gnd <= '0';
gen0 : if has_pads(tech) = 0 generate
pad <= '0'
-- pragma translate_off
after 2 ns
-- pragma translate_on
when oen = '0'
-- pragma translate_off
else 'X' after 2 ns when is_x(i)
-- pragma translate_on
else 'Z'
-- pragma translate_off
after 2 ns
-- pragma translate_on
;
o <= to_X01(pad)
-- pragma translate_off
after 1 ns
-- pragma translate_on
;
end generate;
xcv : if (is_unisim(tech) = 1) generate
x0 : unisim_iopad generic map (level, slew, voltage, strength)
port map (pad, gnd, oen, o);
end generate;
axc : if (tech = axcel) or (tech = axdsp) generate
x0 : axcel_iopad generic map (level, slew, voltage, strength)
port map (pad, gnd, oen, o);
end generate;
pa : if (tech = proasic) or (tech = apa3) generate
x0 : apa3_iopad generic map (level, slew, voltage, strength)
port map (pad, gnd, oen, o);
end generate;
pa3e : if (tech = apa3e) generate
x0 : apa3e_iopad generic map (level, slew, voltage, strength)
port map (pad, gnd, oen, o);
end generate;
igl2 : if (tech = igloo2) or (tech = rtg4) generate
x0 : igloo2_iopad port map (pad, gnd, oen, o);
end generate;
pa3l : if (tech = apa3l) generate
x0 : apa3l_iopad generic map (level, slew, voltage, strength)
port map (pad, gnd, oen, o);
end generate;
fus : if (tech = actfus) generate
x0 : fusion_iopad generic map (level, slew, voltage, strength)
port map (pad, gnd, oen, o);
end generate;
atc : if (tech = atc18s) generate
x0 : atc18_iopad generic map (level, slew, voltage, strength)
port map (pad, gnd, oen, o);
end generate;
atcrh : if (tech = atc18rha) generate
x0 : atc18rha_iopad generic map (level, slew, voltage, strength)
port map (pad, gnd, oen, o);
end generate;
um : if (tech = umc) generate
x0 : umc_iopad generic map (level, slew, voltage, strength)
port map (pad, gnd, oen, o);
end generate;
rhu : if (tech = rhumc) generate
x0 : rhumc_iopad generic map (level, slew, voltage, strength)
port map (pad, gnd, oen, o);
end generate;
ihp : if (tech = ihp25) generate
x0 : ihp25_iopad generic map (level, slew, voltage, strength)
port map (pad, gnd, oen, o);
end generate;
rh18t : if (tech = rhlib18t) generate
x0 : rh_lib18t_iopad generic map (strength)
port map (pad, gnd, oen, o);
end generate;
ut025 : if (tech = ut25) generate
x0 : ut025crh_iopad generic map (strength)
port map (pad, gnd, oen, o);
end generate;
ut13 : if (tech = ut130) generate
x0 : ut130hbd_iopad generic map (strength) port map (pad, gnd, oen, o);
end generate;
pere : if (tech = peregrine) generate
x0 : peregrine_iopad generic map (level, slew, voltage, strength)
port map(pad, gnd, oen, o);
end generate;
end;
library ieee;
library techmap;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
entity iodpadv is
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0; width : integer := 1;
oepol : integer := 0);
port (
pad : inout std_logic_vector(width-1 downto 0);
i : in std_logic_vector(width-1 downto 0);
o : out std_logic_vector(width-1 downto 0));
end;
architecture rtl of iodpadv is
begin
v : for j in width-1 downto 0 generate
x0 : iodpad generic map (tech, level, slew, voltage, strength, oepol)
port map (pad(j), i(j), o(j));
end generate;
end;
| gpl-3.0 |
EliasLuiz/TCC | Leon3/lib/gaisler/uart/uart2.in.vhd | 6 | 128 | -- UART 2
constant CFG_UART2_ENABLE : integer := CONFIG_UART2_ENABLE;
constant CFG_UART2_FIFO : integer := CFG_UA2_FIFO;
| gpl-3.0 |
EliasLuiz/TCC | Leon3/lib/esa/pci/pci_arb.vhd | 4 | 18127 |
----------------------------------------------------------------------------
-- This file is a part of the LEON VHDL model
-- Copyright (C) 1999 European Space Agency (ESA)
--
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2 of the License, or (at your option) any later version.
--
-- See the file COPYING.LGPL for the full details of the license.
--============================================================================--
-- Design unit : pci_arb
--
-- File name : pci_arb.vhd
--
-- Purpose : Arbiter for the PCI bus
-- - configurable size: 4, 8, 16, 32 agents
-- - nested round-robbing in two different priority levels
-- - priority assignment hard-coded or APB-programmable
--
-- Reference : PCI Local Bus Specification, Revision 2.1,
-- PCI Special Interest Group, 1st June 1995
-- (for information: http:
-- Reference : AMBA(TM) Specification (Rev 2.0), ARM IHI 0011A,
-- 13th May 1999, issue A, first release, ARM Limited
-- The document can be retrieved from http:
--
-- Note : Numbering for req_n, gnt_n, or priority levels is in
-- increasing order <0 = left> to <NUMBER-1 = right>.
-- APB data/address arrays are in the conventional order:
-- The least significant bit is located to the
-- right, carrying the lower index number (usually 0).
-- The arbiter considers strong signal levels ('1' and '0')
-- only. Weak levels ('H', 'L') are not considered. The
-- appropriate translation function (to_X01) must be applied
-- to the inputs. This is usually done by the pads,
-- and therefore not contained in this model.
--
-- Configuration: The arbiter can be configured to NB_AGENTS = 4, 8, 16 or 32.
-- A priority level (0 = high, 1 = low) is assigned to each device.
-- Exception is agent NB_AGENTS-1, which has always lowest priority.
--
-- a) The priority levels are hard-coded, when APB_PRIOS = false.
-- In this case, the APB ports (pbi/pbo) are unconnected.
-- The constant ARB_LVL_C must then be set to appropriate values.
--
-- b) When APB_PRIOS = true, the levels are programmable via the
-- APB-address 0x80 (allows to be ored with the PCI interface):
-- Bit 31 (leftmost) = master 31 . . bit 0 (rightmost) = master 0.
-- Bit NB_AGENTS-1 is dont care at write and reads 1.
-- Bits NB_AGENTS to 31, if existing, are dont care and read 0.
-- The constant ARB_LVL_C is then the reset value.
--
-- Algorithm : The algorithm is described in the implementation note of
-- section 3.4 of the PCI standard:
-- The bus is granted by two nested round-robbing loops.
-- An agent number and a priority level is assigned to each agent.
-- The agent number determines, the pair of req_n/gnt_n lines.
-- Agents are counted from 0 to NB_AGENTS-1.
-- All agents in one level have equal access to the bus
-- (round-robbing); all agents of level 1 as a group have access
-- equal to each agent of level 0.
-- Re-arbitration occurs, when frame_n is asserted, as soon
-- as any other master has requested the bus, but only
-- once per transaction.
--
-- b) With programmable priorities. The priority level of all
-- agents (except NB_AGENTS-1) is programmable via APB.
-- In a 256 byte APB address range, the priority level of
-- agent N is accessed via the address 0x80 + 4*N. The APB
-- slave returns 0 on all non-implemented addresses, the
-- address bits (1:0) are not decoded. Since only addresses
-- >= 0x80 are occupied, it can be used in parallel (ored
-- read data) with our PCI interface (uses <= 0x78).
-- The constant ARB_LVL_C in pci_arb_pkg is the reset value.
--
-- Timeout: The "broken master" timeout is another reason for
-- re-arbitration (section 3.4.1 of the standard). Grant is
-- removed from an agent, which has not started a cycle
-- within 16 cycles after request (and grant). Reporting of
-- such a 'broken' master is not implemented.
--
-- Turnover: A turnover cycle is required by the standard, when re-
-- arbitration occurs during idle state of the bus.
-- Notwithstanding to the standard, "idle state" is assumed,
-- when frame_n is high for more than 1 cycle.
--
-- Bus parking : The bus is parked to agent 0 after reset, it remains granted
-- to the last owner, if no other agent requests the bus.
-- When another request is asserted, re-arbitration occurs
-- after one turnover cycle.
--
-- Lock : Lock is defined as a resource lock by the PCI standard.
-- The optional bus lock mentioned in the standard is not
-- considered here and there are no special conditions to
-- handle when lock_n is active.
-- in arbitration.
--
-- Latency : Latency control in PCI is via the latency counters of each
-- agent. The arbiter does not perform any latency check and
-- a once granted agent continues its transaction until its
-- grant is removed AND its own latency counter has expired.
-- Even though, a bus re-arbitration occurs during a
-- transaction, the hand-over only becomes effective,
-- when the current owner deasserts frame_n.
--
-- Limitations : [add here known bugs and limitations]
--
-- Library : work
--
-- Dependencies : LEON config package
-- package amba, can be retrieved from:
-- http:
--
-- Author : Roland Weigand <[email protected]>
-- European Space Agency (ESA)
-- Microelectronics Section (TOS-ESM)
-- P.O. Box 299
-- NL-2200 AG Noordwijk ZH
-- The Netherlands
--
-- Contact : mailto:[email protected]
-- http:
-- Copyright (C): European Space Agency (ESA) 2002.
-- This source code is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2 of the License, or (at your option) any
-- later version. For full details of the license see file
-- http:
--
-- It is recommended that any use of this VHDL source code is
-- reported to the European Space Agency. It is also recommended
-- that any use of the VHDL source code properly acknowledges the
-- European Space Agency as originator.
-- Disclaimer : All information is provided "as is", there is no warranty that
-- the information is correct or suitable for any purpose,
-- neither implicit nor explicit. This information does not
-- necessarily reflect the policy of the European Space Agency.
--
-- Simulator : Modelsim 5.5e on Linux RedHat 7.2
--
-- Synthesis : Synopsys Version 1999.10 on Sparc + Solaris 5.5.1
--
--------------------------------------------------------------------------------
-- Version Author Date Changes
--
-- 0.0 R. W. 2000/11/02 File created
-- 0.1 J.Gaisler 2001/04/10 Integrated in LEON
-- 0.2 R. Weigand 2001/04/25 Connect arb_lvl reg to AMBA clock/reset
-- 0.3 R. Weigand 2002/03/19 Default assignment to owneri in find_next
-- 1.0 RW. 2002/04/08 Implementation of TMR registers
-- Removed recursive function call
-- Fixed ARB_LEVELS = 2
-- 3.0 R. Weigand 2002/04/16 Released for leon2
-- 4.0 M. Isomaki 2004/10/19 Minor changes for GRLIB integration
-- 4.1 J.Gaisler 2004/11/17 Minor changes for GRLIB integration
--$Log$
-- Revision 3.1 2002/07/31 13:22:09 weigand
-- Bugfix for cases where no valid request in level 0 (level 1 was not rearbitrated)
--
-- Revision 3.0 2002/07/24 12:19:38 weigand
-- Installed RCS with version 3.0
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library esa;
use esa.pci_arb_pkg.all;
entity pci_arb is
generic(NB_AGENTS : integer := 4;
ARB_SIZE : integer := 2;
APB_EN : integer := 1
);
port (clk : in clk_type; -- clock
rst_n : in std_logic; -- async reset active low
req_n : in std_logic_vector(0 to NB_AGENTS-1); -- bus request
frame_n : in std_logic;
gnt_n : out std_logic_vector(0 to NB_AGENTS-1); -- bus grant
pclk : in clk_type; -- APB clock
prst_n : in std_logic; -- APB reset
pbi : in EAPB_Slv_In_Type; -- APB inputs
pbo : out EAPB_Slv_Out_Type -- APB outputs
);
end pci_arb;
architecture rtl of pci_arb is
subtype agent_t is std_logic_vector(ARB_SIZE-1 downto 0);
subtype arb_lvl_t is std_logic_vector(NB_AGENTS-1 downto 0);
subtype agentno_t is integer range 0 to NB_AGENTS-1;
-- Note: the agent with the highest index (3, 7, 15, 31) is always in level 1
-- Example: x010 = prio 0 for agent 2 and 0, prio 1 for agent 3 and 1.
-- Default: start with all devices equal priority at level 1.
constant ARB_LVL_C : arb_lvl_t := (others => '1');
constant all_ones : std_logic_vector(0 to NB_AGENTS-1) := (others => '1');
--Necessary definitions from amba.vhd and iface.vhd
--added to pci_arb package with modified names to avoid
--name clashes in GRLIB
constant APB_PRIOS : boolean := APB_EN = 1;
signal owner0, owneri0 : agent_t; -- current owner in level 0
signal owner1, owneri1 : agent_t; -- current owner in level 1
signal cown, cowni : agent_t; -- current level
signal rearb, rearbi : std_logic; -- re-arbitration flag
signal tout, touti : std_logic_vector(3 downto 0); -- timeout counter
signal turn, turni : std_logic; -- turnaround cycle
signal arb_lvl, arb_lvli : arb_lvl_t; -- := ARB_LVL_C; -- level registers
type nmstarr is array (0 to 3) of agentno_t;
type nvalarr is array (0 to 3) of boolean;
begin -- rtl
----------------------------------------------------------------------------
-- PCI ARBITER
----------------------------------------------------------------------------
-- purpose: Grants the bus depending on the request signals. All agents have
-- equal priority, if another request occurs during a transaction, the bus is
-- granted to the new agent. However, PCI protocol specifies that the master
-- can finish the current transaction within the limit of its latency timer.
arbiter : process(cown, owner0, owner1, req_n, rearb, tout, turn, frame_n,
arb_lvl, rst_n)
variable owner0v, owner1v : agentno_t; -- integer variables for current owner
variable new_request : agentno_t; -- detected request
variable nmst : nmstarr;
variable nvalid : nvalarr;
begin -- process arbiter
-- default assignments
rearbi <= rearb;
owneri0 <= owner0;
owneri1 <= owner1;
cowni <= cown;
touti <= tout;
turni <= '0'; -- no turnaround
-- re-arbitrate once during the transaction,
-- or when timeout counter expired (bus idle).
if (frame_n = '0' and rearb = '0') or turn = '1' then
owner0v := conv_integer(owner0);
owner1v := conv_integer(owner1);
new_request := conv_integer(cown);
nvalid(0 to 3) := (others => false);
nmst(0 to 3) := (others => 0);
-- Determine next request in both priority levels
rob : for i in NB_AGENTS-1 downto 0 loop
-- consider all masters with valid request
if req_n(i) = '0' then
-- next in prio level 0
if arb_lvl(i) = '0' then
if i > owner0v then
nmst(0) := i; nvalid(0) := true;
elsif i < owner0v then
nmst(1) := i; nvalid(1) := true;
end if;
-- next in prio level 1
elsif arb_lvl(i) = '1' then
if i > owner1v then
nmst(2) := i; nvalid(2) := true;
elsif i < owner1v then
nmst(3) := i; nvalid(3) := true;
end if;
end if; -- arb_lvl
end if; -- req_n
end loop rob;
-- select new master
if nvalid(0) then -- consider level 0 before wrap
new_request := nmst(0);
owner0v := nmst(0);
-- consider level 1 only once, except when no request in level 0
elsif owner0v /= NB_AGENTS-1 or not nvalid(1) then
if nvalid(2) then -- level 1 before wrap
new_request := nmst(2);
owner0v := NB_AGENTS-1;
owner1v := nmst(2);
elsif nvalid(3) then -- level 1 after wrap
new_request := nmst(3);
owner0v := NB_AGENTS-1;
owner1v := nmst(3);
end if;
elsif nvalid(1) then -- level 0 after wrap
new_request := nmst(1);
owner0v := nmst(1);
end if;
owneri0 <= conv_std_logic_vector(owner0v, ARB_SIZE);
owneri1 <= conv_std_logic_vector(owner1v, ARB_SIZE);
-- rearbitration if any request asserted & different from current owner
if conv_integer(cown) /= new_request then
-- if idle state: turnaround cycle required by PCI standard
cowni <= conv_std_logic_vector(new_request, ARB_SIZE);
touti <= "0000"; -- reset timeout counter
if turn = '0' then
rearbi <= '1'; -- only one re-arbitration
end if;
end if;
elsif frame_n = '1' then
rearbi <= '0';
end if;
-- if frame deasserted, but request asserted: count timeout
if req_n = all_ones then -- no request: prepare timeout counter
touti <= "1111";
elsif frame_n = '1' then -- request, but no transaction
if tout = "1111" then -- timeout expired, re-arbitrate
turni <= '1'; -- remove grant, turnaround cycle
touti <= "0000"; -- next cycle re-arbitrate
else
touti <= tout + 1;
end if;
end if;
grant : for i in 0 to NB_AGENTS-1 loop
if i = conv_integer(cown) and turn = '0' then
gnt_n(i) <= '0';
else
gnt_n(i) <= '1';
end if;
end loop grant;
-- synchronous reset
if rst_n = '0' then
touti <= "0000";
cowni <= (others => '0');
owneri0 <= (others => '0');
owneri1 <= (others => '0');
rearbi <= '0';
turni <= '0';
new_request := 0;
end if;
end process arbiter;
arb_lvl(NB_AGENTS-1) <= '1'; -- always prio 1.
fixed_prios : if not APB_PRIOS generate -- assign constant value
arb_lvl(NB_AGENTS-2 downto 0) <= ARB_LVL_C(NB_AGENTS-2 downto 0);
end generate fixed_prios;
-- Generate APB regs and APB slave
apbgen : if APB_PRIOS generate
-- purpose: APB read and write of arb_lvl configuration registers
-- type: memoryless
-- inputs: pbi, arb_lvl, prst_n
-- outputs: pbo, arb_lvli
config : process (pbi, arb_lvl, prst_n)
begin -- process config
arb_lvli <= arb_lvl;
pbo.PRDATA <= (others => '0'); -- default for unimplemented addresses
-- register select at (byte-) addresses 0x80
if pbi.PADDR(7 downto 0) = "10000000" and pbi.PSEL = '1' then -- address select
if (pbi.PWRITE and pbi.PENABLE) = '1' then -- APB write
arb_lvli <= pbi.PWDATA(NB_AGENTS-1 downto 0);
end if;
pbo.PRDATA(NB_AGENTS-1 downto 0) <= arb_lvl;
end if;
-- synchronous reset
if prst_n = '0' then
arb_lvli <= ARB_LVL_C; -- assign default value
end if;
end process config;
-- APB registers
apb_regs : process (pclk)
begin -- process regs
-- activities triggered by asynchronous reset (active low)
if pclk'event and pclk = '1' then -- '
arb_lvl(NB_AGENTS-2 downto 0) <= arb_lvli(NB_AGENTS-2 downto 0);
end if;
end process apb_regs;
end generate apbgen;
-- PCI registers
regs0 : process (clk)
begin -- process regs
if clk'event and clk = '1' then -- '
tout <= touti;
owner0 <= owneri0;
owner1 <= owneri1;
cown <= cowni;
rearb <= rearbi;
turn <= turni;
end if;
end process regs0;
end rtl;
| gpl-3.0 |
EliasLuiz/TCC | Leon3/lib/gaisler/misc/ahbstat.in.vhd | 6 | 144 | -- AHB status register
constant CFG_AHBSTAT : integer := CONFIG_AHBSTAT_ENABLE;
constant CFG_AHBSTATN : integer := CONFIG_AHBSTAT_NFTSLV;
| gpl-3.0 |
EliasLuiz/TCC | Leon3/lib/gaisler/i2c/i2c2ahb_apb.vhd | 1 | 7393 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Entity: i2c2ahb_apb
-- File: i2c2ahb_apb.vhd
-- Author: Jan Andersson - Aeroflex Gaisler AB
-- Contact: [email protected]
-- Description: Simple I2C-slave providing a bridge to AMBA AHB
-- This entity provides an APB interface for setting defining the
-- AHB address window that can be accessed from I2C.
-- See i2c2ahbx.vhd and GRIP for documentation
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.i2c.all;
library grlib;
use grlib.amba.all;
use grlib.devices.all;
use grlib.stdlib.conv_std_logic;
use grlib.stdlib.conv_std_logic_vector;
entity i2c2ahb_apb is
generic (
-- AHB Configuration
hindex : integer := 0;
--
ahbaddrh : integer := 0;
ahbaddrl : integer := 0;
ahbmaskh : integer := 0;
ahbmaskl : integer := 0;
resen : integer := 0;
-- APB configuration
pindex : integer := 0; -- slave bus index
paddr : integer := 0;
pmask : integer := 16#fff#;
pirq : integer := 0;
-- I2C configuration
i2cslvaddr : integer range 0 to 127 := 0;
i2ccfgaddr : integer range 0 to 127 := 0;
oepol : integer range 0 to 1 := 0;
--
filter : integer range 2 to 512 := 2
);
port (
rstn : in std_ulogic;
clk : in std_ulogic;
-- AHB master interface
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
--
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
-- I2C signals
i2ci : in i2c_in_type;
i2co : out i2c_out_type
);
end entity i2c2ahb_apb;
architecture rtl of i2c2ahb_apb is
-- Register offsets
constant CTRL_OFF : std_logic_vector(4 downto 2) := "000";
constant STS_OFF : std_logic_vector(4 downto 2) := "001";
constant ADDR_OFF : std_logic_vector(4 downto 2) := "010";
constant MASK_OFF : std_logic_vector(4 downto 2) := "011";
constant SLVA_OFF : std_logic_vector(4 downto 2) := "100";
constant SLVC_OFF : std_logic_vector(4 downto 2) := "101";
-- AMBA PnP
constant PCONFIG : apb_config_type := (
0 => ahb_device_reg(VENDOR_GAISLER, GAISLER_I2C2AHB, 0, 0, pirq),
1 => apb_iobar(paddr, pmask));
type apb_reg_type is record
i2c2ahbi : i2c2ahb_in_type;
irq : std_ulogic;
irqen : std_ulogic;
prot : std_ulogic;
protx : std_ulogic;
wr : std_ulogic;
dma : std_ulogic;
dmax : std_ulogic;
end record;
signal r, rin : apb_reg_type;
signal i2c2ahbo : i2c2ahb_out_type;
begin
bridge : i2c2ahbx
generic map (hindex => hindex, oepol => oepol, filter => filter)
port map (rstn => rstn, clk => clk, ahbi => ahbi, ahbo => ahbo,
i2ci => i2ci, i2co => i2co, i2c2ahbi => r.i2c2ahbi,
i2c2ahbo => i2c2ahbo);
comb: process (r, rstn, apbi, i2c2ahbo)
variable v : apb_reg_type;
variable apbaddr : std_logic_vector(4 downto 2);
variable apbout : std_logic_vector(31 downto 0);
variable irqout : std_logic_vector(NAHBIRQ-1 downto 0);
begin
v := r; apbaddr := apbi.paddr(apbaddr'range); apbout := (others => '0');
v.irq := '0'; irqout := (others => '0'); irqout(pirq) := r.irq;
v.protx := i2c2ahbo.prot; v.dmax := i2c2ahbo.dma;
---------------------------------------------------------------------------
-- APB register interface
---------------------------------------------------------------------------
-- read registers
if (apbi.psel(pindex) and apbi.penable and (not apbi.pwrite)) = '1' then
case apbaddr is
when CTRL_OFF => apbout(1 downto 0) := r.irqen & r.i2c2ahbi.en;
when STS_OFF => apbout(2 downto 0) := r.prot & r.wr & r.dma;
when ADDR_OFF => apbout := r.i2c2ahbi.haddr;
when MASK_OFF => apbout := r.i2c2ahbi.hmask;
when SLVA_OFF => apbout(6 downto 0) := r.i2c2ahbi.slvaddr;
when SLVC_OFF => apbout(6 downto 0) := r.i2c2ahbi.cfgaddr;
when others => null;
end case;
end if;
-- write registers
if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
case apbaddr is
when CTRL_OFF => v.irqen := apbi.pwdata(1); v.i2c2ahbi.en := apbi.pwdata(0);
when STS_OFF => v.dma := r.dma and not apbi.pwdata(0);
v.prot := r.prot and not apbi.pwdata(2);
when ADDR_OFF => v.i2c2ahbi.haddr := apbi.pwdata;
when MASK_OFF => v.i2c2ahbi.hmask := apbi.pwdata;
when SLVA_OFF => v.i2c2ahbi.slvaddr := apbi.pwdata(6 downto 0);
when SLVC_OFF => v.i2c2ahbi.cfgaddr := apbi.pwdata(6 downto 0);
when others => null;
end case;
end if;
-- interrupt and status register handling
if ((i2c2ahbo.dma and not r.dmax) or
(i2c2ahbo.prot and not r.protx)) = '1' then
v.dma := '1'; v.prot := r.prot or i2c2ahbo.prot; v.wr := i2c2ahbo.wr;
if (r.irqen and not r.dma) = '1' then v.irq := '1'; end if;
end if;
---------------------------------------------------------------------------
-- reset
---------------------------------------------------------------------------
if rstn = '0' then
v.i2c2ahbi.en := conv_std_logic(resen = 1);
v.i2c2ahbi.haddr := conv_std_logic_vector(ahbaddrh, 16) &
conv_std_logic_vector(ahbaddrl, 16);
v.i2c2ahbi.hmask := conv_std_logic_vector(ahbmaskh, 16) &
conv_std_logic_vector(ahbmaskl, 16);
v.i2c2ahbi.slvaddr := conv_std_logic_vector(i2cslvaddr, 7);
v.i2c2ahbi.cfgaddr := conv_std_logic_vector(i2ccfgaddr, 7);
v.irqen := '0'; v.prot := '0'; v.wr := '0'; v.dma := '0';
end if;
---------------------------------------------------------------------------
-- signal assignments
---------------------------------------------------------------------------
-- update registers
rin <= v;
-- update outputs
apbo.prdata <= apbout;
apbo.pirq <= irqout;
apbo.pconfig <= PCONFIG;
apbo.pindex <= pindex;
end process comb;
reg: process(clk)
begin
if rising_edge(clk) then r <= rin; end if;
end process reg;
-- Boot message provided in i2c2ahbx...
end architecture rtl;
| gpl-3.0 |
EliasLuiz/TCC | Leon3/lib/gaisler/uart/uart1.in.vhd | 6 | 128 | -- UART 1
constant CFG_UART1_ENABLE : integer := CONFIG_UART1_ENABLE;
constant CFG_UART1_FIFO : integer := CFG_UA1_FIFO;
| gpl-3.0 |
hoglet67/CoPro6502 | src/DCM/dcm_49_24.vhd | 1 | 2075 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.Vcomponents.all;
entity dcm_49_24 is
port (CLKIN_IN : in std_logic;
CLK0_OUT : out std_logic;
CLK0_OUT1 : out std_logic;
CLK2X_OUT : out std_logic);
end dcm_49_24;
architecture BEHAVIORAL of dcm_49_24 is
signal CLKFX_BUF : std_logic;
signal CLKIN_IBUFG : std_logic;
signal GND_BIT : std_logic;
begin
GND_BIT <= '0';
CLKFX_BUFG_INST : BUFG
port map (I => CLKFX_BUF, O => CLK0_OUT);
DCM_INST : DCM
generic map(CLK_FEEDBACK => "NONE",
CLKDV_DIVIDE => 4.0, -- 24.576 = 49.152 * 10/20
CLKFX_DIVIDE => 20,
CLKFX_MULTIPLY => 10,
CLKIN_DIVIDE_BY_2 => false,
CLKIN_PERIOD => 20.3450520833,
CLKOUT_PHASE_SHIFT => "NONE",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
DFS_FREQUENCY_MODE => "LOW",
DLL_FREQUENCY_MODE => "LOW",
DUTY_CYCLE_CORRECTION => true,
FACTORY_JF => x"C080",
PHASE_SHIFT => 0,
STARTUP_WAIT => false)
port map (CLKFB => GND_BIT,
CLKIN => CLKIN_IN,
DSSEN => GND_BIT,
PSCLK => GND_BIT,
PSEN => GND_BIT,
PSINCDEC => GND_BIT,
RST => GND_BIT,
CLKDV => open,
CLKFX => CLKFX_BUF,
CLKFX180 => open,
CLK0 => open,
CLK2X => open,
CLK2X180 => open,
CLK90 => open,
CLK180 => open,
CLK270 => open,
LOCKED => open,
PSDONE => open,
STATUS => open);
end BEHAVIORAL;
| gpl-3.0 |
EliasLuiz/TCC | Leon3/lib/gaisler/net/edcl.in.vhd | 4 | 401 | -- Ethernet DSU
constant CFG_DSU_ETH : integer := CONFIG_DSU_ETH + CONFIG_DSU_ETH_PROG + CONFIG_DSU_ETH_DIS;
constant CFG_ETH_BUF : integer := CFG_DSU_ETHB;
constant CFG_ETH_IPM : integer := 16#CONFIG_DSU_IPMSB#;
constant CFG_ETH_IPL : integer := 16#CONFIG_DSU_IPLSB#;
constant CFG_ETH_ENM : integer := 16#CONFIG_DSU_ETHMSB#;
constant CFG_ETH_ENL : integer := 16#CONFIG_DSU_ETHLSB#;
| gpl-3.0 |
EliasLuiz/TCC | Leon3/designs/leon3-gr-cpci-xc4v/dprc_fir_demo/fir_v1.vhd | 4 | 4901 | ------------------------------------------------------------------------------
-- Copyright (c) 2014, Pascal Trotta - Testgroup (Politecnico di Torino)
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright notice, this
-- list of conditions and the following disclaimer in the documentation and/or other
-- materials provided with the distribution.
--
-- THIS SOURCE CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-- MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-- EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
-- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
-- OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
-----------------------------------------------------------------------------
-- Entity: fir
-- File: fir_v1.vhd
-- Author: Pascal Trotta (TestGroup research group - Politecnico di Torino)
-- Contacts: [email protected] www.testgroup.polito.it
-- Description: FIR filter core (version 1) -- for dprc demo
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity fir is
port (
clk : in std_ulogic;
rst : in std_ulogic;
start : in std_ulogic;
in_data : in std_logic_vector(31 downto 0);
in_data_read : out std_ulogic;
out_data : out std_logic_vector (31 downto 0);
out_data_write : out std_ulogic);
end fir;
architecture fir_rtl of fir is
type fsm_state is (idle, running);
signal pstate, nstate : fsm_state;
type sh_reg_type is array (0 to 8) of unsigned(7 downto 0);
signal sh_reg, rsh_reg : sh_reg_type;
type mul_type is array (0 to 9) of unsigned(15 downto 0);
signal mul, rmul : mul_type;
signal rout_data : std_logic_vector(21 downto 0);
signal dcount, rdcount : std_logic_vector(8 downto 0);
type coeffT is array (0 to 9) of unsigned(7 downto 0);
constant coeff : coeffT := (to_unsigned(21,8),to_unsigned(23,8),to_unsigned(21,8),to_unsigned(19,8),to_unsigned(13,8),to_unsigned(9,8),to_unsigned(13,8),to_unsigned(15,8),to_unsigned(21,8),to_unsigned(17,8));
begin
comb: process(rsh_reg, rmul, start, pstate, rdcount, in_data)
variable vsh_reg : sh_reg_type;
variable vout_data : unsigned(21 downto 0);
variable start_flag : std_ulogic;
variable vdcount : std_logic_vector(8 downto 0);
begin
vdcount := rdcount;
vout_data := to_unsigned(0,22);
for i in 8 downto 1 loop
vsh_reg(i) := rsh_reg(i-1);
end loop;
vsh_reg(0) := unsigned(in_data(7 downto 0));
for i in 0 to 9 loop
vout_data := vout_data + rmul(i);
end loop;
in_data_read <= '0';
out_data_write <= '0';
case pstate is
when idle =>
if start='1' then
nstate <= running;
else
nstate <= idle;
vdcount := (others=>'0');
end if;
when running =>
if vdcount=std_logic_vector(to_unsigned(102,9)) then
nstate<=idle;
in_data_read <= '0';
else
nstate<=running;
in_data_read <= '1';
end if;
if vdcount>=std_logic_vector(to_unsigned(12,9)) then --9+2latency
out_data_write <= '1';
end if;
end case;
if pstate/= idle then
vdcount := vdcount+1;
end if;
sh_reg <= vsh_reg;
rout_data(21 downto 0) <= std_logic_vector(vout_data);
dcount <= vdcount;
end process;
reg: process(clk,rst)
begin
if (rst='1') then
for i in 0 to 8 loop
rsh_reg(i) <= (others=>'0');
end loop;
for i in 0 to 9 loop
rmul(i) <= (others=>'0');
end loop;
out_data <= (others=>'0');
rdcount <= (others=>'0');
pstate <= idle;
elsif rising_edge(clk) then
rsh_reg <= sh_reg;
rmul <= mul;
out_data <= "0000000000"&rout_data;
rdcount <= dcount;
pstate <= nstate;
end if;
end process;
mul_gen: for i in 1 to 9 generate
mul(i) <= rsh_reg(i-1) * coeff(i);
end generate;
mul(0) <= unsigned(in_data(7 downto 0))*coeff(0);
end fir_rtl;
| gpl-3.0 |
EliasLuiz/TCC | Leon3/lib/techmap/maps/toutpad_ds.vhd | 1 | 4694 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: toutpad_ds
-- File: toutpad_ds.vhd
-- Author: Jonas Ekergarn - Aeroflex Gaisler
-- Description: tri-state differential output pad with technology wrapper
------------------------------------------------------------------------------
library techmap;
library ieee;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
use techmap.allpads.all;
entity toutpad_ds is
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12;
oepol : integer := 0);
port (padp, padn : out std_ulogic; i, en : in std_ulogic);
end;
architecture rtl of toutpad_ds is
signal oen : std_ulogic;
signal padx, gnd : std_ulogic;
begin
gnd <= '0';
oen <= not en when oepol /= padoen_polarity(tech) else en;
gen0 : if has_ds_pads(tech) = 0 or (is_unisim(tech) = 1) or
tech = axcel or tech = axdsp or tech = rhlib18t or
tech = ut25 or tech = ut130
generate
padp <= i
-- pragma translate_off
after 2 ns
-- pragma translate_on
when oen = '0'
-- pragma translate_off
else 'X' after 2 ns when is_x(en)
-- pragma translate_on
else 'Z'
-- pragma translate_off
after 2 ns
-- pragma translate_on
;
padn <= not i
-- pragma translate_off
after 2 ns
-- pragma translate_on
when oen = '0'
-- pragma translate_off
else 'X' after 2 ns when is_x(en)
-- pragma translate_on
else 'Z'
-- pragma translate_off
after 2 ns
-- pragma translate_on
;
end generate;
pa3 : if (tech = apa3) generate
u0 : apa3_toutpad_ds generic map (level)
port map (padp, padn, i, oen);
end generate;
pa3e : if (tech = apa3e) generate
u0 : apa3e_toutpad_ds generic map (level)
port map (padp, padn, i, oen);
end generate;
igl2 : if (tech = igloo2) or (tech = rtg4) generate
u0 : igloo2_toutpad_ds port map (padp, padn, i, oen);
end generate;
pa3l : if (tech = apa3l) generate
u0 : apa3l_toutpad_ds generic map (level)
port map (padp, padn, i, oen);
end generate;
fus : if (tech = actfus) generate
u0 : fusion_toutpad_ds generic map (level)
port map (padp, padn, i, oen);
end generate;
end;
library techmap;
library ieee;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
entity toutpad_dsv is
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12; width : integer := 1;
oepol : integer := 0);
port (
padp : out std_logic_vector(width-1 downto 0);
padn : out std_logic_vector(width-1 downto 0);
i : in std_logic_vector(width-1 downto 0);
en : in std_ulogic);
end;
architecture rtl of toutpad_dsv is
begin
v : for j in width-1 downto 0 generate
u0 : toutpad_ds generic map (tech, level, slew, voltage, strength, oepol)
port map (padp(j), padn(j), i(j), en);
end generate;
end;
library techmap;
library ieee;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
entity toutpad_dsvv is
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12; width : integer := 1;
oepol : integer := 0);
port (
padp : out std_logic_vector(width-1 downto 0);
padn : out std_logic_vector(width-1 downto 0);
i : in std_logic_vector(width-1 downto 0);
en : in std_logic_vector(width-1 downto 0));
end;
architecture rtl of toutpad_dsvv is
begin
v : for j in width-1 downto 0 generate
u0 : toutpad_ds generic map (tech, level, slew, voltage, strength, oepol)
port map (padp(j), padn(j), i(j), en(j));
end generate;
end;
| gpl-3.0 |
EliasLuiz/TCC | Leon3/lib/gaisler/can/can_mod.vhd | 1 | 7813 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: can_mod
-- File: can_mod.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: OpenCores CAN MAC with FIFO RAM
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
library opencores;
use opencores.cancomp.all;
library grlib;
use grlib.stdlib.all;
entity can_mod is
generic (memtech : integer := DEFMEMTECH; syncrst : integer := 0;
ft : integer := 0);
port (
reset : in std_logic;
clk : in std_logic;
cs : in std_logic;
we : in std_logic;
addr : in std_logic_vector(7 downto 0);
data_in : in std_logic_vector(7 downto 0);
data_out: out std_logic_vector(7 downto 0);
irq : out std_logic;
rxi : in std_logic;
txo : out std_logic;
testen : in std_logic
);
attribute sync_set_reset of reset : signal is "true";
end;
architecture rtl of can_mod is
type reg_type is record
waddr : std_logic_vector(5 downto 0);
ready : std_ulogic;
end record;
-- // port connections for Ram
--//64x8
signal q_dp_64x8 : std_logic_vector(7 downto 0);
signal data_64x8 : std_logic_vector(7 downto 0);
signal ldata_64x8 : std_logic_vector(7 downto 0);
signal wren_64x8 : std_logic;
signal lwren_64x8 : std_logic;
signal rden_64x8 : std_logic;
signal wraddress_64x8 : std_logic_vector(5 downto 0);
signal lwraddress_64x8 : std_logic_vector(5 downto 0);
signal rdaddress_64x8 : std_logic_vector(5 downto 0);
--//64x4
signal q_dp_64x4 : std_logic_vector(3 downto 0);
signal lq_dp_64x4 : std_logic_vector(4 downto 0);
signal data_64x4 : std_logic_vector(3 downto 0);
signal ldata_64x4 : std_logic_vector(4 downto 0);
signal wren_64x4x1 : std_logic;
signal lwren_64x4x1 : std_logic;
signal wraddress_64x4x1 : std_logic_vector(5 downto 0);
signal lwraddress_64x4x1 : std_logic_vector(5 downto 0);
signal rdaddress_64x4x1 : std_logic_vector(5 downto 0);
--//64x1
signal q_dp_64x1 : std_logic_vector(0 downto 0);
signal data_64x1 : std_logic_vector(0 downto 0);
signal ldata_64x1 : std_logic_vector(0 downto 0);
signal vcc, gnd : std_ulogic;
signal testin : std_logic_vector(3 downto 0);
signal r, rin : reg_type;
begin
ramclear : if syncrst = 2 generate
comb : process(r, reset, wren_64x8, data_64x8, wraddress_64x8,
data_64x4, wren_64x4x1, wraddress_64x4x1, data_64x1)
variable v : reg_type;
begin
v := r;
if r.ready = '0' then
v.waddr := r.waddr + 1;
if (r.waddr(5) and not v.waddr(5)) = '1' then v.ready := '1'; end if;
lwren_64x8 <= '1'; ldata_64x8 <= (others => '0');
lwraddress_64x8 <= r.waddr;
ldata_64x4 <= (others => '0'); lwren_64x4x1 <= '1';
lwraddress_64x4x1 <= r.waddr;
ldata_64x1 <= "0";
else
lwren_64x8 <= wren_64x8; ldata_64x8 <= data_64x8;
lwraddress_64x8 <= wraddress_64x8;
ldata_64x4 <= data_64x1 & data_64x4; lwren_64x4x1 <= wren_64x4x1;
lwraddress_64x4x1 <= wraddress_64x4x1;
ldata_64x1 <= data_64x1;
end if;
if reset = '1' then
v.ready := '0'; v.waddr := (others => '0');
end if;
rin <= v;
end process;
regs : process(clk)
begin if rising_edge(clk) then r <= rin; end if; end process;
end generate;
noramclear : if syncrst /= 2 generate
lwren_64x8 <= wren_64x8; ldata_64x8 <= data_64x8;
lwraddress_64x8 <= wraddress_64x8;
ldata_64x4 <= data_64x1 & data_64x4; lwren_64x4x1 <= wren_64x4x1;
lwraddress_64x4x1 <= wraddress_64x4x1;
ldata_64x1 <= data_64x1;
end generate;
gnd <= '0'; vcc <= '1';
testin <= testen & "000";
async : if syncrst = 0 generate
can : can_top port map ( rst => reset, addr => addr, data_in => data_in,
data_out => data_out, cs => cs, we => we, clk_i => clk,
tx_o => txo, rx_i => rxi, bus_off_on => open, irq_on => irq,
clkout_o => open,
q_dp_64x8 => q_dp_64x8, data_64x8 => data_64x8, wren_64x8 => wren_64x8,
rden_64x8 => rden_64x8, wraddress_64x8 => wraddress_64x8,
rdaddress_64x8 => rdaddress_64x8, q_dp_64x4 => q_dp_64x4,
data_64x4 => data_64x4, wren_64x4x1 => wren_64x4x1,
wraddress_64x4x1 => wraddress_64x4x1,
rdaddress_64x4x1 => rdaddress_64x4x1,
q_dp_64x1 => q_dp_64x1(0), data_64x1 => data_64x1(0));
end generate;
sync : if syncrst /= 0 generate
can : can_top_sync port map ( rst => reset, addr => addr, data_in => data_in,
data_out => data_out, cs => cs, we => we, clk_i => clk,
tx_o => txo, rx_i => rxi, bus_off_on => open, irq_on => irq,
clkout_o => open,
q_dp_64x8 => q_dp_64x8, data_64x8 => data_64x8, wren_64x8 => wren_64x8,
rden_64x8 => rden_64x8, wraddress_64x8 => wraddress_64x8,
rdaddress_64x8 => rdaddress_64x8, q_dp_64x4 => q_dp_64x4,
data_64x4 => data_64x4, wren_64x4x1 => wren_64x4x1,
wraddress_64x4x1 => wraddress_64x4x1,
rdaddress_64x4x1 => rdaddress_64x4x1,
q_dp_64x1 => q_dp_64x1(0), data_64x1 => data_64x1(0));
end generate;
noft : if (ft = 0) or (memtech = 0) generate
fifo : syncram_2p generic map(memtech,6,8,0)
port map(rclk => clk, renable => rden_64x8, wclk => clk,
raddress => rdaddress_64x8, waddress => lwraddress_64x8,
datain => ldata_64x8, write => lwren_64x8, dataout => q_dp_64x8,
testin => testin);
info_fifo : syncram_2p generic map(memtech,6,5,0)
port map(rclk => clk, wclk => clk, raddress => rdaddress_64x4x1,
waddress => lwraddress_64x4x1, datain => ldata_64x4,
write => lwren_64x4x1, dataout => lq_dp_64x4, renable =>vcc,
testin => testin);
end generate;
ften : if not((ft = 0) or (memtech = 0)) generate
fifo : syncram_2pft generic map(memtech,6,8,0,0,2)
port map(rclk => clk, renable => rden_64x8, wclk => clk,
raddress => rdaddress_64x8, waddress => lwraddress_64x8,
datain => ldata_64x8, write => lwren_64x8, dataout => q_dp_64x8,
testin => testin);
info_fifo : syncram_2pft generic map(memtech,6,5,0,0,2)
port map(rclk => clk, wclk => clk, raddress => rdaddress_64x4x1,
waddress => lwraddress_64x4x1, datain => ldata_64x4,
write => lwren_64x4x1, dataout => lq_dp_64x4, renable =>vcc,
testin => testin);
end generate;
q_dp_64x4 <= lq_dp_64x4(3 downto 0);
q_dp_64x1 <= lq_dp_64x4(4 downto 4);
-- overrun_fifo : syncram_2p generic map(0,6,1,0)
-- port map(rclk => clk, wclk => clk, raddress => rdaddress_64x4x1,
-- waddress => lwraddress_64x4x1, datain => ldata_64x1,
-- write => lwren_64x4x1, dataout => q_dp_64x1, renable => vcc,
-- testin => testin);
end;
| gpl-3.0 |
EliasLuiz/TCC | Leon3/designs/leon3-altera-ep3sl150/testbench.vhd | 1 | 13033 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
-- Altera Stratix-III LEON3 Demonstration design test bench
-- Copyright (C) 2007 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
library techmap;
use techmap.gencomp.all;
library micron;
use micron.components.all;
library cypress;
use cypress.components.all;
use work.debug.all;
use work.config.all; -- configuration
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
ncpu : integer := CFG_NCPU;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
clkperiod : integer := 20; -- system clock period
romwidth : integer := 32; -- rom data width (8/32)
romdepth : integer := 23; -- rom address depth
sramwidth : integer := 32; -- ram data width (8/16/32)
sramdepth : integer := 20; -- ram address depth
srambanks : integer := 1; -- number of ram banks
dbits : integer := CFG_DDR2SP_DATAWIDTH
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec"; -- rom contents
constant sramfile : string := "ram.srec"; -- ram contents
constant sdramfile : string := "ram.srec"; -- sdram contents
constant ct : integer := clkperiod/2;
constant lresp : boolean := false;
signal GND : std_ulogic := '0';
signal VCC : std_ulogic := '1';
signal NC : std_ulogic := 'Z';
signal Rst : std_logic := '0'; -- Reset
signal clk : std_logic := '0';
signal clk125 : std_logic := '0';
signal address : std_logic_vector(25 downto 0);
signal data : std_logic_vector(31 downto 0);
signal romsn : std_ulogic;
signal iosn : std_ulogic;
signal oen : std_ulogic;
signal writen : std_ulogic;
signal dsuen, dsutx, dsurx, dsubren, dsuact : std_ulogic;
signal dsurst : std_ulogic;
signal error : std_logic;
signal gpio : std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0);
signal txd1, rxd1 : std_ulogic;
-- PSRAM and FLASH control
signal sram_advn : std_logic;
signal sram_csn : std_logic;
signal sram_wen : std_logic;
signal sram_ben : std_logic_vector (0 to 3);
signal sram_oen : std_ulogic;
signal sram_clk : std_ulogic;
signal sram_adscn : std_ulogic;
signal sram_psn : std_ulogic;
signal sram_adv_n : std_ulogic;
signal sram_wait : std_logic_vector(1 downto 0);
signal flash_clk, flash_cen, max_csn : std_logic;
signal flash_advn, flash_oen, flash_resetn, flash_wen : std_logic;
-- DDR2 memory
signal ddr_clk : std_logic_vector(2 downto 0);
signal ddr_clkb : std_logic_vector(2 downto 0);
signal ddr_cke : std_logic_vector(1 downto 0);
signal ddr_csb : std_logic_vector(1 downto 0);
signal ddr_odt : std_logic_vector(1 downto 0);
signal ddr_web : std_ulogic; -- ddr write enable
signal ddr_rasb : std_ulogic; -- ddr ras
signal ddr_casb : std_ulogic; -- ddr cas
signal ddr_dm : std_logic_vector (8 downto 0); -- ddr dm
signal ddr_dqsp : std_logic_vector (8 downto 0); -- ddr dqs
signal ddr_dqsn : std_logic_vector (8 downto 0); -- ddr dqs
signal ddr_rdqs : std_logic_vector (8 downto 0); -- ddr dqs
signal ddr_ad : std_logic_vector (15 downto 0); -- ddr address
signal ddr_ba : std_logic_vector (2 downto 0); -- ddr bank address
signal ddr_dq : std_logic_vector (71 downto 0); -- ddr data
signal ddr_dq2 : std_logic_vector (71 downto 0); -- ddr data
--signal ddra_cke : std_logic;
--signal ddra_csb : std_logic;
--signal ddra_web : std_ulogic; -- ddr write enable
--signal ddra_rasb : std_ulogic; -- ddr ras
--signal ddra_casb : std_ulogic; -- ddr cas
--signal ddra_ad : std_logic_vector (15 downto 0); -- ddr address
--signal ddra_ba : std_logic_vector (2 downto 0); -- ddr bank address
--signal ddrb_cke : std_logic;
--signal ddrb_csb : std_logic;
--signal ddrb_web : std_ulogic; -- ddr write enable
--signal ddrb_rasb : std_ulogic; -- ddr ras
--signal ddrb_casb : std_ulogic; -- ddr cas
--signal ddrb_ad : std_logic_vector (15 downto 0); -- ddr address
--signal ddrb_ba : std_logic_vector (2 downto 0); -- ddr bank address
--signal ddrab_clk : std_logic_vector(1 downto 0);
--signal ddrab_clkb : std_logic_vector(1 downto 0);
--signal ddrab_odt : std_logic_vector(1 downto 0);
--signal ddrab_dqsp : std_logic_vector(1 downto 0); -- ddr dqs
--signal ddrab_dqsn : std_logic_vector(1 downto 0); -- ddr dqs
--signal ddrab_dm : std_logic_vector(1 downto 0); -- ddr dm
--signal ddrab_dq : std_logic_vector (15 downto 0);-- ddr data
-- Ethernet
signal phy_mii_data: std_logic; -- ethernet PHY interface
signal phy_tx_clk : std_ulogic;
signal phy_rx_clk : std_ulogic;
signal phy_rx_data : std_logic_vector(7 downto 0);
signal phy_dv : std_ulogic;
signal phy_rx_er : std_ulogic;
signal phy_col : std_ulogic;
signal phy_crs : std_ulogic;
signal phy_tx_data : std_logic_vector(7 downto 0);
signal phy_tx_en : std_ulogic;
signal phy_tx_er : std_ulogic;
signal phy_mii_clk : std_ulogic;
signal phy_rst_n : std_ulogic;
signal phy_gtx_clk : std_ulogic;
begin
-- clock and reset
clk <= not clk after ct * 1 ns;
clk125 <= not clk125 after 4 * 1 ns;
rst <= dsurst;
dsubren <= '1'; rxd1 <= '1';
address(0) <= '0';
ddr_dq(71 downto dbits) <= (others => 'H');
ddr_dq2(71 downto dbits) <= (others => 'H');
ddr_dqsp(8 downto dbits/8) <= (others => 'H');
ddr_dqsn(8 downto dbits/8) <= (others => 'H');
ddr_rdqs(8 downto dbits/8) <= (others => 'H');
ddr_dm(8 downto dbits/8) <= (others => 'H');
d3 : entity work.leon3mp
generic map (fabtech, memtech, padtech, clktech,
ncpu, disas, dbguart, pclow, 50000, dbits)
port map (rst, clk, clk125, error, dsubren, dsuact,
-- rxd1, txd1,
gpio, address(25 downto 1), data, open,
sram_advn, sram_csn, sram_wen, sram_ben, sram_oen, sram_clk, sram_psn, sram_wait,
flash_clk, flash_advn, flash_cen, flash_oen, flash_resetn, flash_wen,
max_csn, iosn,
ddr_clk, ddr_clkb, ddr_cke, ddr_csb, ddr_odt, ddr_web,
ddr_rasb, ddr_casb, ddr_dm, ddr_dqsp, ddr_dqsn, ddr_ad, ddr_ba, ddr_dq,
open, open,
-- ddra_cke, ddra_csb, ddra_web, ddra_rasb, ddra_casb, ddra_ad(14 downto 0), ddra_ba, ddrb_cke,
-- ddrb_csb, ddrb_web, ddrb_rasb, ddrb_casb, ddrb_ad(14 downto 0), ddrb_ba, ddrab_clk, ddrab_clkb,
-- ddrab_odt, ddrab_dqsp, ddrab_dqsn, ddrab_dm, ddrab_dq,
phy_gtx_clk, phy_mii_data, phy_tx_clk, phy_rx_clk,
phy_rx_data, phy_dv, phy_rx_er, phy_col, phy_crs,
phy_tx_data, phy_tx_en, phy_tx_er, phy_mii_clk, phy_rst_n
);
ddr2delay : delay_wire
generic map(data_width => dbits, delay_atob => 0.0, delay_btoa => 5.5)
port map(a => ddr_dq(dbits-1 downto 0), b => ddr_dq2(dbits-1 downto 0));
ddr0 : ddr2ram
generic map(width => dbits, abits => 13, babits =>2, colbits => 10, rowbits => 13,
implbanks => 1, fname => sdramfile, speedbin=>1, density => 2)
port map (ck => ddr_clk(0), ckn => ddr_clkb(0), cke => ddr_cke(0), csn => ddr_csb(0),
odt => ddr_odt(0), rasn => ddr_rasb, casn => ddr_casb, wen => ddr_web,
dm => ddr_dm(dbits/8-1 downto 0), ba => ddr_ba(1 downto 0),
a => ddr_ad(12 downto 0), dq => ddr_dq2(dbits-1 downto 0),
dqs => ddr_dqsp(dbits/8-1 downto 0), dqsn =>ddr_dqsn(dbits/8-1 downto 0));
-- 16 bit prom
prom0 : sram16 generic map (index => 4, abits => romdepth, fname => promfile)
port map (address(romdepth downto 1), data(31 downto 16),
gnd, gnd, flash_cen, flash_wen, flash_oen);
-- -- 32 bit prom
-- prom0 : for i in 0 to 3 generate
-- sr0 : sram generic map (index => i, abits => romdepth, fname => promfile)
-- port map (address(romdepth+1 downto 2), data(31-i*8 downto 24-i*8), flash_cen,
-- flash_wen, flash_oen);
-- end generate;
sram0 : for i in 0 to (sramwidth/8)-1 generate
sr0 : sram generic map (index => i, abits => sramdepth, fname => sramfile)
port map (address(sramdepth+1 downto 2), data(31-i*8 downto 24-i*8), sram_csn,
sram_wen, sram_oen);
end generate;
error <= 'H'; -- ERROR pull-up
iuerr : process
begin
wait for 2500 ns;
if to_x01(error) = '1' then wait on error; end if;
assert (to_x01(error) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure ;
end process;
data <= buskeep(data), (others => 'H') after 250 ns;
test0 : grtestmod
port map ( rst, clk, error, address(21 downto 2), data,
iosn, sram_oen, sram_wen, open);
dsucom : process
procedure dsucfg(signal dsurx : in std_ulogic; signal dsutx : out std_ulogic) is
variable w32 : std_logic_vector(31 downto 0);
variable c8 : std_logic_vector(7 downto 0);
constant txp : time := 160 * 1 ns;
begin
dsutx <= '1';
dsurst <= '0';
wait for 500 ns;
dsurst <= '1';
wait;
wait for 5000 ns;
txc(dsutx, 16#55#, txp); -- sync uart
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#02#, 16#ae#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#ae#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#24#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#03#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#fc#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#2f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#6f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#11#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#00#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#04#, txp);
txa(dsutx, 16#00#, 16#02#, 16#20#, 16#01#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#02#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#43#, 16#10#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#40#, 16#00#, 16#24#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#24#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#70#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#03#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#ff#, 16#ff#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#48#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#12#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#60#, txp);
txa(dsutx, 16#00#, 16#00#, 16#12#, 16#10#, txp);
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
txc(dsutx, 16#a0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
end;
begin
dsucfg(dsutx, dsurx);
wait;
end process;
end ;
| gpl-3.0 |
EliasLuiz/TCC | Leon3/lib/techmap/cycloneiii/alt/actrlout.vhd | 1 | 2085 | library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library cycloneiii;
use cycloneiii.all;
entity actrlout is
generic(
power_up : string := "high"
);
port(
clk : in std_logic;
i : in std_logic;
o : out std_logic
);
end;
architecture rtl of actrlout is
component cycloneiii_ddio_out
generic(
power_up : string := "low";
async_mode : string := "none";
sync_mode : string := "none";
lpm_type : string := "cycloneiii_ddio_out"
);
port (
datainlo : in std_logic := '0';
datainhi : in std_logic := '0';
clk : in std_logic := '0';
ena : in std_logic := '1';
areset : in std_logic := '0';
sreset : in std_logic := '0';
dataout : out std_logic;
dfflo : out std_logic;
dffhi : out std_logic-- ;
--devclrn : in std_logic := '1';
--devpor : in std_logic := '1'
);
end component;
signal vcc : std_logic;
signal gnd : std_logic_vector(13 downto 0);
signal clk_reg : std_logic;
signal clk_buf, clk_bufn : std_logic;
begin
vcc <= '1'; gnd <= (others => '0');
out_reg0 : cycloneiii_ddio_out
generic map(
power_up => power_up,--"high",
async_mode => "none",
sync_mode => "none",
lpm_type => "cycloneiii_ddio_out"
)
port map(
datainlo => i,
datainhi => i,
clk => clk,
ena => vcc,
areset => gnd(0),
sreset => gnd(0),
dataout => o,
dfflo => open,
dffhi => open--,
--devclrn => vcc,
--devpor => vcc
);
end;
| gpl-3.0 |
EliasLuiz/TCC | Leon3/lib/work/debug/grtestmod.vhd | 1 | 6920 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: grtestmod
-- File: grtestmod.vhd
-- Author: Jiri Gaisler, Gaisler Research
-- Modified: Jan Andersson, Aeroflex Gaisler
-- Contact: [email protected]
-- Description: Test report module
--
-- See also the gaiser.sim.ahbrep module for a module connected via AHB for
-- for use internally on SoC.
--
-- This module supports a 16- or 32-bit interface as selected via the 'width'
-- generic.
--
-- In 32-bit mode the module has the following memory map:
--
-- 0x00 : sets and prints vendor id from data[31:24] and
-- device id from data[23:12]
-- 0x04 : asserts error number data[15:0]
-- 0x08 : calls subtest data[7:0]
-- 0x10 : prints *** GRLIB system test starting ***
-- 0x14 : prints Test passed / errors detected
-- 0x18 : prints Checkpoint data[15:0] with time stamp
--
-- In 16-bit mode the module has the following memory map:
--
-- 0x00 : sets vendor id from data[15:8] and MSbs of device id from data[7:0]
-- 0x04 : asserts error number data[15:0]
-- 0x08 : calls subtest data[7:0]
-- 0x0C : sets LSbs of device id from data[15:12], prints vendor and device id
-- 0x10 : prints *** GRLIB system test starting ***
-- 0x14 : prints Test passed / errors detected
-- 0x18 : prints Checkpoint data[15:0] with time stamp
--
-- The width is defined for the systest software via GRLIB_REPORTDEV_WIDTH
------------------------------------------------------------------------------
-- pragma translate_off
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.sim.all;
library grlib;
use grlib.stdlib.all;
use grlib.stdio.all;
use grlib.devices.all;
use std.textio.all;
entity grtestmod is
generic (
halt : integer := 0;
width : integer := 32);
port (
resetn : in std_ulogic;
clk : in std_ulogic;
errorn : in std_ulogic;
address : in std_logic_vector(21 downto 2);
data : inout std_logic_vector(width-1 downto 0);
iosn : in std_ulogic;
oen : in std_ulogic;
writen : in std_ulogic;
brdyn : out std_ulogic := '1';
bexcn : out std_ulogic := '1';
state : out std_logic_vector(1 downto 0);
testdev : out std_logic_vector(19 downto 0);
subtest : out std_logic_vector(7 downto 0)
);
end;
architecture sim of grtestmod is
subtype msgtype is string(1 to 40);
constant ntests : integer := 2;
type msgarr is array (0 to ntests) of msgtype;
constant msg : msgarr := (
"*** Starting GRLIB system test *** ", -- 0
"Test completed OK, halting simulation ", -- 1
"Test FAILED " -- 2
);
signal ior, iow : std_ulogic;
signal addr : std_logic_vector(21 downto 2);
signal ldata : std_logic_vector(width-1 downto 0);
begin
ior <= iosn or oen;
iow <= iosn or writen;
data <= (others => 'Z');
addr <= to_X01(address) after 1 ns;
ldata <= to_X01(data) after 1 ns;
log : process(ior, iow) --, clk)
variable errno, errcnt, lsubtest, vendorid, deviceid : integer;
variable lstate: std_logic_vector(1 downto 0) := "00";
--variable addr : std_logic_vector(21 downto 2);
--variable ldata : std_logic_vector(width-1 downto 0);
begin
--if rising_edge(clk) then
-- addr := to_X01(address);
-- ldata := to_X01(data);
--end if;
if falling_edge (ior) then
brdyn <= '1', '0' after 100 ns;
if addr(15) = '1' then bexcn <= '1', '0' after 100 ns; end if;
elsif rising_edge (ior) then
brdyn <= '1'; bexcn <= '1';
elsif falling_edge(iow) then
brdyn <= '1', '0' after 100 ns;
if addr(15) = '1' then bexcn <= '1', '0' after 100 ns; end if;
elsif rising_edge(iow) then
brdyn <= '1'; bexcn <= '1';
-- addr := to_X01(address);
case addr(7 downto 2) is
when "000000" =>
if width = 32 then
vendorid := conv_integer(ldata(31*(width/32) downto 24*(width/32)));
deviceid := conv_integer(ldata(23*(width/32) downto 12*(width/32)));
print(iptable(vendorid).device_table(deviceid));
testdev <= conv_std_logic_vector(vendorid*256+deviceid,20);
else
vendorid := conv_integer(ldata(15 downto 8));
deviceid := 2**4*conv_integer(ldata(7 downto 0));
end if;
when "000001" =>
errno := conv_integer(ldata(15 downto 0));
if (halt = 0) then
assert false
report "test failed, error (" & tost(errno) & ")"
severity failure;
else
assert false
report "test failed, error (" & tost(errno) & ")"
severity warning;
end if;
lstate := "11";
when "000010" =>
lsubtest := conv_integer(ldata(7 downto 0));
call_subtest(vendorid, deviceid, lsubtest);
subtest <= conv_std_logic_vector(lsubtest,8);
when "000011" =>
if width = 16 then
deviceid := deviceid + conv_integer(ldata(15 downto 12));
print(iptable(vendorid).device_table(deviceid));
testdev <= conv_std_logic_vector(vendorid*256+deviceid,20);
end if;
when "000100" =>
print ("");
print ("**** GRLIB system test starting ****");
errcnt := 0;
if lstate="00" then lstate := "01"; end if;
when "000101" =>
if errcnt = 0 then
print ("Test passed, halting with IU error mode");
if lstate="01" then lstate := "10"; end if;
elsif errcnt = 1 then
print ("1 error detected, halting with IU error mode");
else
print (tost(errcnt) & " errors detected, halting with IU error mode");
end if;
print ("");
when "000110" =>
grlib.testlib.print("Checkpoint " & tost(conv_integer(ldata(15 downto 0))));
when "000111" =>
vendorid := 0; deviceid := 0;
print ("Basic memory test");
when others =>
end case;
end if;
state <= lstate;
end process;
end;
-- pragma translate_on
| gpl-3.0 |
EliasLuiz/TCC | Leon3/designs/leon3-xilinx-zc702/testbench.vhd | 2 | 7478 | -----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2012 Fredrik Ringhage, Gaisler Research
-- Modified by Jiri Gaisler, 2014-04-05
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.config.all;
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
end;
architecture behav of testbench is
signal button : std_logic_vector(3 downto 0) := (others => '0');
signal switch : std_logic_vector(7 downto 0); -- I/O port
signal led : std_logic_vector(7 downto 0); -- I/O port
signal processing_system7_0_MIO : std_logic_vector(53 downto 0);
signal processing_system7_0_PS_SRSTB : std_logic;
signal processing_system7_0_PS_CLK : std_logic;
signal processing_system7_0_PS_PORB : std_logic;
signal processing_system7_0_DDR_Clk : std_logic;
signal processing_system7_0_DDR_Clk_n : std_logic;
signal processing_system7_0_DDR_CKE : std_logic;
signal processing_system7_0_DDR_CS_n : std_logic;
signal processing_system7_0_DDR_RAS_n : std_logic;
signal processing_system7_0_DDR_CAS_n : std_logic;
signal processing_system7_0_DDR_WEB_pin : std_logic;
signal processing_system7_0_DDR_BankAddr : std_logic_vector(2 downto 0);
signal processing_system7_0_DDR_Addr : std_logic_vector(14 downto 0);
signal processing_system7_0_DDR_ODT : std_logic;
signal processing_system7_0_DDR_DRSTB : std_logic;
signal processing_system7_0_DDR_DQ : std_logic_vector(31 downto 0);
signal processing_system7_0_DDR_DM : std_logic_vector(3 downto 0);
signal processing_system7_0_DDR_DQS : std_logic_vector(3 downto 0);
signal processing_system7_0_DDR_DQS_n : std_logic_vector(3 downto 0);
signal processing_system7_0_DDR_VRN : std_logic;
signal processing_system7_0_DDR_VRP : std_logic;
component leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
port (
processing_system7_0_MIO : inout std_logic_vector(53 downto 0);
processing_system7_0_PS_SRSTB : inout std_logic;
processing_system7_0_PS_CLK : inout std_logic;
processing_system7_0_PS_PORB : inout std_logic;
processing_system7_0_DDR_Clk : inout std_logic;
processing_system7_0_DDR_Clk_n : inout std_logic;
processing_system7_0_DDR_CKE : inout std_logic;
processing_system7_0_DDR_CS_n : inout std_logic;
processing_system7_0_DDR_RAS_n : inout std_logic;
processing_system7_0_DDR_CAS_n : inout std_logic;
processing_system7_0_DDR_WEB_pin : inout std_logic;
processing_system7_0_DDR_BankAddr : inout std_logic_vector(2 downto 0);
processing_system7_0_DDR_Addr : inout std_logic_vector(14 downto 0);
processing_system7_0_DDR_ODT : inout std_logic;
processing_system7_0_DDR_DRSTB : inout std_logic;
processing_system7_0_DDR_DQ : inout std_logic_vector(31 downto 0);
processing_system7_0_DDR_DM : inout std_logic_vector(3 downto 0);
processing_system7_0_DDR_DQS : inout std_logic_vector(3 downto 0);
processing_system7_0_DDR_DQS_n : inout std_logic_vector(3 downto 0);
processing_system7_0_DDR_VRN : inout std_logic;
processing_system7_0_DDR_VRP : inout std_logic;
button : in std_logic_vector(3 downto 0);
switch : inout std_logic_vector(7 downto 0);
led : out std_logic_vector(7 downto 0)
);
end component;
begin
-- clock, reset and misc
button <= (others => '0');
switch <= (others => '0');
cpu : leon3mp
generic map (
fabtech => fabtech,
memtech => memtech,
padtech => padtech,
clktech => clktech,
disas => disas,
dbguart => dbguart,
pclow => pclow
)
port map (
processing_system7_0_MIO => processing_system7_0_MIO,
processing_system7_0_PS_SRSTB => processing_system7_0_PS_SRSTB,
processing_system7_0_PS_CLK => processing_system7_0_PS_CLK,
processing_system7_0_PS_PORB => processing_system7_0_PS_PORB,
processing_system7_0_DDR_Clk => processing_system7_0_DDR_Clk,
processing_system7_0_DDR_Clk_n => processing_system7_0_DDR_Clk_n,
processing_system7_0_DDR_CKE => processing_system7_0_DDR_CKE,
processing_system7_0_DDR_CS_n => processing_system7_0_DDR_CS_n,
processing_system7_0_DDR_RAS_n => processing_system7_0_DDR_RAS_n,
processing_system7_0_DDR_CAS_n => processing_system7_0_DDR_CAS_n,
processing_system7_0_DDR_WEB_pin => processing_system7_0_DDR_WEB_pin,
processing_system7_0_DDR_BankAddr => processing_system7_0_DDR_BankAddr,
processing_system7_0_DDR_Addr => processing_system7_0_DDR_Addr,
processing_system7_0_DDR_ODT => processing_system7_0_DDR_ODT,
processing_system7_0_DDR_DRSTB => processing_system7_0_DDR_DRSTB,
processing_system7_0_DDR_DQ => processing_system7_0_DDR_DQ,
processing_system7_0_DDR_DM => processing_system7_0_DDR_DM,
processing_system7_0_DDR_DQS => processing_system7_0_DDR_DQS,
processing_system7_0_DDR_DQS_n => processing_system7_0_DDR_DQS_n,
processing_system7_0_DDR_VRN => processing_system7_0_DDR_VRN,
processing_system7_0_DDR_VRP => processing_system7_0_DDR_VRP,
button => button,
switch => switch,
led => led
);
iuerr : process
begin
wait for 5000 ns;
wait on led(1);
assert (led(1) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure ;
end process;
end ;
| gpl-3.0 |
EliasLuiz/TCC | Leon3/designs/leon3-digilent-xc7z020/testbench.vhd | 2 | 7478 | -----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2012 Fredrik Ringhage, Gaisler Research
-- Modified by Jiri Gaisler, 2014-04-05
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.config.all;
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
end;
architecture behav of testbench is
signal button : std_logic_vector(3 downto 0) := (others => '0');
signal switch : std_logic_vector(7 downto 0); -- I/O port
signal led : std_logic_vector(7 downto 0); -- I/O port
signal processing_system7_0_MIO : std_logic_vector(53 downto 0);
signal processing_system7_0_PS_SRSTB : std_logic;
signal processing_system7_0_PS_CLK : std_logic;
signal processing_system7_0_PS_PORB : std_logic;
signal processing_system7_0_DDR_Clk : std_logic;
signal processing_system7_0_DDR_Clk_n : std_logic;
signal processing_system7_0_DDR_CKE : std_logic;
signal processing_system7_0_DDR_CS_n : std_logic;
signal processing_system7_0_DDR_RAS_n : std_logic;
signal processing_system7_0_DDR_CAS_n : std_logic;
signal processing_system7_0_DDR_WEB_pin : std_logic;
signal processing_system7_0_DDR_BankAddr : std_logic_vector(2 downto 0);
signal processing_system7_0_DDR_Addr : std_logic_vector(14 downto 0);
signal processing_system7_0_DDR_ODT : std_logic;
signal processing_system7_0_DDR_DRSTB : std_logic;
signal processing_system7_0_DDR_DQ : std_logic_vector(31 downto 0);
signal processing_system7_0_DDR_DM : std_logic_vector(3 downto 0);
signal processing_system7_0_DDR_DQS : std_logic_vector(3 downto 0);
signal processing_system7_0_DDR_DQS_n : std_logic_vector(3 downto 0);
signal processing_system7_0_DDR_VRN : std_logic;
signal processing_system7_0_DDR_VRP : std_logic;
component leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
port (
processing_system7_0_MIO : inout std_logic_vector(53 downto 0);
processing_system7_0_PS_SRSTB : inout std_logic;
processing_system7_0_PS_CLK : inout std_logic;
processing_system7_0_PS_PORB : inout std_logic;
processing_system7_0_DDR_Clk : inout std_logic;
processing_system7_0_DDR_Clk_n : inout std_logic;
processing_system7_0_DDR_CKE : inout std_logic;
processing_system7_0_DDR_CS_n : inout std_logic;
processing_system7_0_DDR_RAS_n : inout std_logic;
processing_system7_0_DDR_CAS_n : inout std_logic;
processing_system7_0_DDR_WEB_pin : inout std_logic;
processing_system7_0_DDR_BankAddr : inout std_logic_vector(2 downto 0);
processing_system7_0_DDR_Addr : inout std_logic_vector(14 downto 0);
processing_system7_0_DDR_ODT : inout std_logic;
processing_system7_0_DDR_DRSTB : inout std_logic;
processing_system7_0_DDR_DQ : inout std_logic_vector(31 downto 0);
processing_system7_0_DDR_DM : inout std_logic_vector(3 downto 0);
processing_system7_0_DDR_DQS : inout std_logic_vector(3 downto 0);
processing_system7_0_DDR_DQS_n : inout std_logic_vector(3 downto 0);
processing_system7_0_DDR_VRN : inout std_logic;
processing_system7_0_DDR_VRP : inout std_logic;
button : in std_logic_vector(3 downto 0);
switch : inout std_logic_vector(7 downto 0);
led : out std_logic_vector(7 downto 0)
);
end component;
begin
-- clock, reset and misc
button <= (others => '0');
switch <= (others => '0');
cpu : leon3mp
generic map (
fabtech => fabtech,
memtech => memtech,
padtech => padtech,
clktech => clktech,
disas => disas,
dbguart => dbguart,
pclow => pclow
)
port map (
processing_system7_0_MIO => processing_system7_0_MIO,
processing_system7_0_PS_SRSTB => processing_system7_0_PS_SRSTB,
processing_system7_0_PS_CLK => processing_system7_0_PS_CLK,
processing_system7_0_PS_PORB => processing_system7_0_PS_PORB,
processing_system7_0_DDR_Clk => processing_system7_0_DDR_Clk,
processing_system7_0_DDR_Clk_n => processing_system7_0_DDR_Clk_n,
processing_system7_0_DDR_CKE => processing_system7_0_DDR_CKE,
processing_system7_0_DDR_CS_n => processing_system7_0_DDR_CS_n,
processing_system7_0_DDR_RAS_n => processing_system7_0_DDR_RAS_n,
processing_system7_0_DDR_CAS_n => processing_system7_0_DDR_CAS_n,
processing_system7_0_DDR_WEB_pin => processing_system7_0_DDR_WEB_pin,
processing_system7_0_DDR_BankAddr => processing_system7_0_DDR_BankAddr,
processing_system7_0_DDR_Addr => processing_system7_0_DDR_Addr,
processing_system7_0_DDR_ODT => processing_system7_0_DDR_ODT,
processing_system7_0_DDR_DRSTB => processing_system7_0_DDR_DRSTB,
processing_system7_0_DDR_DQ => processing_system7_0_DDR_DQ,
processing_system7_0_DDR_DM => processing_system7_0_DDR_DM,
processing_system7_0_DDR_DQS => processing_system7_0_DDR_DQS,
processing_system7_0_DDR_DQS_n => processing_system7_0_DDR_DQS_n,
processing_system7_0_DDR_VRN => processing_system7_0_DDR_VRN,
processing_system7_0_DDR_VRP => processing_system7_0_DDR_VRP,
button => button,
switch => switch,
led => led
);
iuerr : process
begin
wait for 5000 ns;
wait on led(1);
assert (led(1) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure ;
end process;
end ;
| gpl-3.0 |
EliasLuiz/TCC | Leon3/lib/techmap/maps/allmul.vhd | 1 | 3200 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: allmul
-- File: allmul.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Multiplier components
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package allmul is
component mul_dw is
generic (
a_width : positive := 2; -- multiplier word width
b_width : positive := 2; -- multiplicand word width
num_stages : positive := 2; -- number of pipeline stages
stall_mode : natural range 0 to 1 := 1 -- '0': non-stallable; '1': stallable
);
port(a : in std_logic_vector(a_width-1 downto 0);
b : in std_logic_vector(b_width-1 downto 0);
clk : in std_logic;
en : in std_logic;
sign : in std_logic;
product : out std_logic_vector(a_width+b_width-1 downto 0));
end component;
component gen_mult_pipe
generic (
a_width : positive; -- multiplier word width
b_width : positive; -- multiplicand word width
num_stages : positive := 2; -- number of pipeline stages
stall_mode : natural range 0 to 1 := 1); -- '0': non-stallable; '1': stallable
port (
clk : in std_logic; -- register clock
en : in std_logic; -- register enable
tc : in std_logic; -- '0' : unsigned, '1' : signed
a : in std_logic_vector(a_width-1 downto 0); -- multiplier
b : in std_logic_vector(b_width-1 downto 0); -- multiplicand
product : out std_logic_vector(a_width+b_width-1 downto 0)); -- product
end component;
component axcel_mul_33x33_signed
generic (
pipe: Integer := 0);
port (
a: in Std_Logic_Vector(32 downto 0);
b: in Std_Logic_Vector(32 downto 0);
en: in Std_Logic;
clk: in Std_Logic;
p: out Std_Logic_Vector(65 downto 0));
end component;
end;
| gpl-3.0 |
EliasLuiz/TCC | Leon3/lib/gaisler/misc/ahbtrace_mmb.vhd | 1 | 24388 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ahbtrace_mmb
-- File: ahbtrace_mmb.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Modified: Jan Andersson - Aeroflex Gaisler
-- Description: AHB trace unit that can have registers on a separate bus and
-- select between several trace buses.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
entity ahbtrace_mmb is
generic (
hindex : integer := 0;
ioaddr : integer := 16#000#;
iomask : integer := 16#E00#;
tech : integer := DEFMEMTECH;
irq : integer := 0;
kbytes : integer := 1;
bwidth : integer := 32;
ahbfilt : integer := 0;
ntrace : integer range 1 to 8 := 1;
scantest : integer range 0 to 1 := 0;
exttimer : integer range 0 to 1 := 0;
exten : integer range 0 to 1 := 0);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type; -- Register interface
ahbso : out ahb_slv_out_type;
tahbmiv : in ahb_mst_in_vector_type(0 to ntrace-1); -- Trace
tahbsiv : in ahb_slv_in_vector_type(0 to ntrace-1);
timer : in std_logic_vector(30 downto 0);
astat : out amba_stat_type;
resen : in std_ulogic := '0'
);
end;
architecture rtl of ahbtrace_mmb is
constant TBUFABITS : integer := log2(kbytes) + 6;
constant TIMEBITS : integer := 32 - exttimer;
constant FILTEN : boolean := ahbfilt /= 0;
constant PERFEN : boolean := (ahbfilt > 1);
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_AHBTRACE, 0, 0, irq),
4 => ahb_iobar (ioaddr, iomask),
others => zero32);
type tracebuf_in_type is record
addr : std_logic_vector(TBUFABITS-1 downto 0);
data : std_logic_vector(255 downto 0);
enable : std_logic;
write : std_logic_vector(7 downto 0);
end record;
type tracebuf_out_type is record
data : std_logic_vector(255 downto 0);
end record;
type trace_break_reg is record
addr : std_logic_vector(31 downto 2);
mask : std_logic_vector(31 downto 2);
read : std_logic;
write : std_logic;
end record;
type regtype is record
thaddr : std_logic_vector(31 downto 0);
thwrite : std_logic;
thtrans : std_logic_vector(1 downto 0);
thsize : std_logic_vector(2 downto 0);
thburst : std_logic_vector(2 downto 0);
thmaster : std_logic_vector(3 downto 0);
thmastlock : std_logic;
ahbactive : std_logic;
timer : std_logic_vector((TIMEBITS-1)*(1-exttimer) downto 0);
aindex : std_logic_vector(TBUFABITS - 1 downto 0); -- buffer index
hready : std_logic;
hready2 : std_logic;
hready3 : std_logic;
hsel : std_logic;
hwrite : std_logic;
haddr : std_logic_vector(TBUFABITS+4 downto 2);
hrdata : std_logic_vector(31 downto 0);
regacc : std_logic;
enable : std_logic; -- trace enable
bahb : std_logic; -- break on AHB watchpoint hit
bhit : std_logic; -- breakpoint hit
dcnten : std_logic; -- delay counter enable
delaycnt : std_logic_vector(TBUFABITS - 1 downto 0); -- delay counter
tbreg1 : trace_break_reg;
tbreg2 : trace_break_reg;
end record;
type pregtype is record
stat : amba_stat_type;
split : std_ulogic;
splmst : std_logic_vector(3 downto 0);
hready : std_ulogic;
hresp : std_logic_vector(1 downto 0);
end record;
type fregtype is record
shsel : std_logic_vector(0 to NAHBSLV-1);
pf : std_ulogic; -- Filter perf outputs
af : std_ulogic; -- Address filtering
fr : std_ulogic; -- Filter reads
fw : std_ulogic; -- Filter writes
smask : std_logic_vector(15 downto 0);
mmask : std_logic_vector(15 downto 0);
rf : std_ulogic; -- Retry filtering
end record;
type bregtype is record
bsel : std_logic_vector(log2(ntrace) downto 0);
end record;
function ahb_filt_hit (
r : regtype;
rf : fregtype;
hresp : std_logic_vector(1 downto 0)) return boolean is
variable hit : boolean;
begin
-- filter hit -> inhibit
hit := false;
-- Filter on read/write
if ((rf.fw and r.thwrite) or (rf.fr and not r.thwrite)) = '1' then
hit := true;
end if;
-- Filter on address range
if (((r.tbreg2.addr xor r.thaddr(31 downto 2)) and r.tbreg2.mask) /= zero32(29 downto 0)) then
if rf.af = '1' then hit := true; end if;
end if;
-- Filter on master mask
for i in rf.mmask'range loop
if i > NAHBMST-1 then exit; end if;
if i = conv_integer(r.thmaster) and rf.mmask(i) = '1' then
hit := true;
end if;
end loop;
-- Filter on slave mask
for i in rf.smask'range loop
if i > NAHBSLV-1 then exit; end if;
if (rf.shsel(i) and rf.smask(i)) /= '0' then
hit := true;
end if;
end loop;
-- Filter on retry response
if (rf.rf = '1' and hresp = HRESP_RETRY) then
hit := true;
end if;
return hit;
end function ahb_filt_hit;
function getnrams return integer is
variable v: integer;
begin
v := 2;
if bwidth > 32 then v:=v+1; end if;
if bwidth > 64 then v:=v+1; end if;
return v;
end getnrams;
constant nrams: integer := getnrams;
subtype mtest64_vector is std_logic_vector(2*memtest_vlen-1 downto 0);
type mtest64_type is array(0 to 2) of mtest64_vector;
signal mtesti64, mtesto64: mtest64_type;
signal tbi : tracebuf_in_type;
signal tbo : tracebuf_out_type;
signal enable : std_logic_vector(1 downto 0);
signal r, rin : regtype;
signal rf, rfin : fregtype;
signal rb, rbin : bregtype;
signal pr, prin : pregtype;
begin
ctrl : process(rst, ahbsi, tahbmiv, tahbsiv, r, rf, rb, tbo, pr, timer, resen)
variable v : regtype;
variable vabufi : tracebuf_in_type;
variable regsd : std_logic_vector(31 downto 0); -- data from registers
variable aindex : std_logic_vector(TBUFABITS - 1 downto 0); -- buffer index
variable bphit : std_logic;
variable wdata, rdata : std_logic_vector(255 downto 0);
variable hwdata : std_logic_vector(31 downto 0);
variable hirq : std_logic_vector(NAHBIRQ-1 downto 0);
variable tahbmi : ahb_mst_in_type;
variable tahbsi : ahb_slv_in_type;
variable vf : fregtype;
variable vb : bregtype;
variable regaddr : std_logic_vector(4 downto 2);
variable tbaddr : std_logic_vector(3 downto 2);
variable timeval : std_logic_vector(31 downto 0);
variable pv : pregtype;
begin
v := r; regsd := (others => '0'); vabufi.enable := '0';
vabufi.data := (others => '0'); vabufi.addr := (others => '0');
vabufi.write := (others => '0'); bphit := '0';
v.hready := r.hready2; v.hready2 := r.hready3; v.hready3 := '0';
hwdata := ahbreadword(ahbsi.hwdata, r.haddr(4 downto 2));
hirq := (others => '0'); hirq(irq) := r.bhit;
vf := rf; vb := rb; pv := pr;
if ntrace = 1 then
tahbmi := tahbmiv(0); tahbsi := tahbsiv(0);
else
tahbmi := tahbmiv(conv_integer(rb.bsel));
tahbsi := tahbsiv(conv_integer(rb.bsel));
end if;
regaddr := r.haddr(4 downto 2); --tbaddr := r.haddr(3 downto 2);
timeval := (others => '0');
timeval((TIMEBITS-1)*(1-exttimer) downto 0) := r.timer;
if exttimer /= 0 then
timeval(TIMEBITS-1 downto 0) := timer(TIMEBITS-1 downto 0);
end if;
wdata := (others => '0'); rdata := (others => '0');
-- trace buffer index and delay counters
if exttimer = 0 and r.enable = '1' then v.timer := r.timer + 1; end if;
aindex := r.aindex + 1;
-- check for AHB watchpoints
if (tahbsi.hready and r.ahbactive ) = '1' then
if ((((r.tbreg1.addr xor r.thaddr(31 downto 2)) and r.tbreg1.mask) = zero32(29 downto 0)) and
(((r.tbreg1.read and not r.thwrite) or (r.tbreg1.write and r.thwrite)) = '1'))
or ((((r.tbreg2.addr xor r.thaddr(31 downto 2)) and r.tbreg2.mask) = zero32(29 downto 0)) and
(((r.tbreg2.read and not r.thwrite) or (r.tbreg2.write and r.thwrite)) = '1'))
then
if (r.enable = '1') and (r.dcnten = '0') and
(r.delaycnt /= zero32(TBUFABITS-1 downto 0))
then v.dcnten := '1'; bphit := '1';
--else bphit := '1'; v.enable := '0'; end if;
elsif (r.enable = '1') and (r.dcnten = '0') then bphit := '1'; v.enable := '0'; end if;
end if;
end if;
-- generate buffer inputs
vabufi.write := "00000000";
wdata(AHBDW-1 downto 0) := tahbsi.hwdata;
rdata(AHBDW-1 downto 0) := tahbmi.hrdata;
if r.enable = '1' then
vabufi.addr(TBUFABITS-1 downto 0) := r.aindex;
vabufi.data(127 downto 96) := timeval;
vabufi.data(95) := bphit;
vabufi.data(94 downto 80) := (others => '0'); --tahbmi.hirq(15 downto 1);
vabufi.data(79) := r.thwrite;
vabufi.data(78 downto 77) := r.thtrans;
vabufi.data(76 downto 74) := r.thsize;
vabufi.data(73 downto 71) := r.thburst;
vabufi.data(70 downto 67) := r.thmaster;
vabufi.data(66) := r.thmastlock;
vabufi.data(65 downto 64) := tahbmi.hresp;
if r.thwrite = '1' then
vabufi.data(63 downto 32) := wdata(31 downto 0);
vabufi.data(223 downto 128) := wdata(127 downto 32);
else
vabufi.data(63 downto 32) := rdata(31 downto 0);
vabufi.data(223 downto 128) := rdata(127 downto 32);
end if;
vabufi.data(31 downto 0) := r.thaddr;
else
if bwidth = 32 then
vabufi.addr(TBUFABITS-1 downto 0) := r.haddr(TBUFABITS+3 downto 4);
else
vabufi.addr(TBUFABITS-1 downto 0) := r.haddr(TBUFABITS+4 downto 5);
end if;
-- Note: HWDATA from register i/f
vabufi.data := hwdata & hwdata & hwdata & hwdata & hwdata & hwdata & hwdata & hwdata;
end if;
-- write trace buffer
if r.enable = '1' then
if (r.ahbactive and tahbsi.hready) = '1' then
if not (FILTEN and ahb_filt_hit(r, rf, tahbmi.hresp)) then
v.aindex := aindex;
vabufi.enable := '1'; vabufi.write := "11111111";
end if;
end if;
end if;
-- trace buffer delay counter handling
if (r.dcnten = '1') and (r.ahbactive and tahbsi.hready) = '1' then
if (r.delaycnt = zero32(TBUFABITS-1 downto 0)) then
v.enable := '0'; v.dcnten := '0';
end if;
v.delaycnt := r.delaycnt - 1;
end if;
-- AHB statistics
if PERFEN then
pv.hready := tahbsi.hready;
pv.hresp := tahbmi.hresp;
pv.stat := amba_stat_none;
if pr.hready = '1' then
case r.thtrans is
when HTRANS_IDLE => pv.stat.idle := '1';
when HTRANS_BUSY => pv.stat.busy := '1';
when HTRANS_NONSEQ => pv.stat.nseq := '1';
when others => pv.stat.seq := '1';
end case;
if r.ahbactive = '1' then
pv.stat.read := not r.thwrite;
pv.stat.write := r.thwrite;
case r.thsize is
when HSIZE_BYTE => pv.stat.hsize(0) := '1';
when HSIZE_HWORD => pv.stat.hsize(1) := '1';
when HSIZE_WORD => pv.stat.hsize(2) := '1';
when HSIZE_DWORD => pv.stat.hsize(3) := '1';
when HSIZE_4WORD => pv.stat.hsize(4) := '1';
when others => pv.stat.hsize(5) := '1';
end case;
end if;
pv.stat.hmaster := r.thmaster;
end if;
if pr.hresp = HRESP_OKAY then
pv.stat.ws := not pr.hready;
end if;
-- It may also be interesting to count the maximum grant latency. That
-- is; the delay between asserting hbusreq and receiving hgrant. This
-- would require that all bus request signals were present in this
-- entity. This has been left as a possible future extension.
if pr.hready = '1' then
if pr.hresp = HRESP_SPLIT then
pv.stat.split := '1';
pv.split := '1';
if pr.split = '0' then
pv.splmst := r.thmaster;
end if;
end if;
if pr.hresp = HRESP_RETRY then
pv.stat.retry := '1';
end if;
end if;
pv.stat.locked := r.thmastlock;
if rf.pf = '1' and ahb_filt_hit(r, rf, tahbmi.hresp) then
pv.stat := amba_stat_none;
pv.split := pr.split; pv.splmst := pr.splmst;
end if;
-- Count cycles where master is in SPLIT
if pr.split = '1' then
for i in tahbmi.hgrant'range loop
if i = conv_integer(pr.splmst) and tahbmi.hgrant(i) = '1' then
pv.split := '0';
end if;
end loop;
pv.stat.spdel := pv.split;
end if;
end if;
-- save AHB transfer parameters
if (tahbsi.hready = '1' ) then
v.thaddr := tahbsi.haddr; v.thwrite := tahbsi.hwrite; v.thtrans := tahbsi.htrans;
v.thsize := tahbsi.hsize; v.thburst := tahbsi.hburst;
v.thmaster := tahbsi.hmaster; v.thmastlock := tahbsi.hmastlock;
v.ahbactive := tahbsi.htrans(1);
if FILTEN then vf.shsel := tahbsi.hsel; end if;
end if;
-- AHB transfer parameters for register accesses
if (ahbsi.hready = '1' ) then
v.haddr := ahbsi.haddr(TBUFABITS+4 downto 2); v.hwrite := ahbsi.hwrite;
v.regacc := ahbsi.haddr(16);
v.hsel := ahbsi.htrans(1) and ahbsi.hsel(hindex);
end if;
-- AHB slave access to DSU registers and trace buffers
if (r.hsel and not r.hready) = '1' then
if r.regacc = '0' then -- registers
v.hready := '1';
case regaddr is
when "000" =>
regsd((TBUFABITS + 15) downto 16) := r.delaycnt;
if ntrace /= 1 then
regsd(15) := '1';
regsd(log2(ntrace)+12 downto 12) := vb.bsel;
end if;
regsd(7 downto 6) := conv_std_logic_vector(log2(bwidth/32), 2);
if FILTEN then
regsd(8) := rf.pf;
regsd(5) := rf.rf;
regsd(4) := rf.af;
regsd(3) := rf.fr;
regsd(2) := rf.fw;
end if;
regsd(1 downto 0) := r.dcnten & r.enable;
if r.hwrite = '1' then
v.delaycnt := ahbsi.hwdata((TBUFABITS+ 15) downto 16);
if ntrace /= 1 then
vb.bsel := ahbsi.hwdata(log2(ntrace)+12 downto 12);
end if;
if FILTEN then
vf.pf := ahbsi.hwdata(8);
vf.rf := ahbsi.hwdata(5);
vf.af := ahbsi.hwdata(4);
vf.fr := ahbsi.hwdata(3);
vf.fw := ahbsi.hwdata(2);
end if;
v.dcnten := ahbsi.hwdata(1);
v.enable := ahbsi.hwdata(0);
end if;
when "001" =>
regsd((TBUFABITS - 1 + 4) downto 4) := r.aindex;
if r.hwrite = '1' then
v.aindex := ahbsi.hwdata((TBUFABITS- 1) downto 0);
end if;
when "010" =>
regsd := timeval;
if exttimer = 0 and r.hwrite = '1' then
v.timer := ahbsi.hwdata((TIMEBITS- 1)*(1-exttimer) downto 0);
end if;
when "011" =>
if FILTEN then
regsd(31 downto 0) := rf.smask & rf.mmask;
if r.hwrite = '1' then
vf.smask := ahbsi.hwdata(31 downto 16);
vf.mmask := ahbsi.hwdata(15 downto 0);
end if;
end if;
when "100" =>
regsd(31 downto 2) := r.tbreg1.addr;
if r.hwrite = '1' then
v.tbreg1.addr := ahbsi.hwdata(31 downto 2);
end if;
when "101" =>
regsd := r.tbreg1.mask & r.tbreg1.read & r.tbreg1.write;
if r.hwrite = '1' then
v.tbreg1.mask := ahbsi.hwdata(31 downto 2);
v.tbreg1.read := ahbsi.hwdata(1);
v.tbreg1.write := ahbsi.hwdata(0);
end if;
when "110" =>
regsd(31 downto 2) := r.tbreg2.addr;
if r.hwrite = '1' then
v.tbreg2.addr := ahbsi.hwdata(31 downto 2);
end if;
when others =>
regsd := r.tbreg2.mask & r.tbreg2.read & r.tbreg2.write;
if r.hwrite = '1' then
v.tbreg2.mask := ahbsi.hwdata(31 downto 2);
v.tbreg2.read := ahbsi.hwdata(1);
v.tbreg2.write := ahbsi.hwdata(0);
end if;
end case;
v.hrdata := regsd;
else -- read/write access to trace buffer
if r.hwrite = '1' then v.hready := '1'; else v.hready2 := not (r.hready2 or r.hready); end if;
vabufi.enable := not r.enable;
case regaddr is
when "000" =>
v.hrdata := tbo.data(127 downto 96);
if r.hwrite = '1' then
vabufi.write(3) := vabufi.enable;
end if;
when "001" =>
v.hrdata := tbo.data(95 downto 64);
if r.hwrite = '1' then
vabufi.write(2) := vabufi.enable;
end if;
when "010" =>
v.hrdata := tbo.data(63 downto 32);
if r.hwrite = '1' then
vabufi.write(1) := vabufi.enable;
end if;
when "011" =>
v.hrdata := tbo.data(31 downto 0);
if r.hwrite = '1' then
vabufi.write(0) := vabufi.enable;
end if;
when "100" =>
if bwidth > 32 then
v.hrdata := tbo.data(159 downto 128);
if r.hwrite = '1' then
vabufi.write(7) := vabufi.enable;
end if;
else
v.hrdata := tbo.data(127 downto 96);
if r.hwrite = '1' then
vabufi.write(3) := vabufi.enable;
end if;
end if;
when "101" =>
if bwidth > 32 then
if bwidth > 64 then
v.hrdata := tbo.data(223 downto 192);
if r.hwrite = '1' then
vabufi.write(6) := vabufi.enable;
end if;
else v.hrdata := zero32; end if;
else
v.hrdata := tbo.data(95 downto 64);
if r.hwrite = '1' then
vabufi.write(2) := vabufi.enable;
end if;
end if;
when "110" =>
if bwidth > 32 then
if bwidth > 64 then
v.hrdata := tbo.data(191 downto 160);
if r.hwrite = '1' then
vabufi.write(5) := vabufi.enable;
end if;
else v.hrdata := zero32; end if;
else
v.hrdata := tbo.data(63 downto 32);
if r.hwrite = '1' then
vabufi.write(1) := vabufi.enable;
end if;
end if;
when others =>
if bwidth > 32 then
v.hrdata := zero32;
else
v.hrdata := tbo.data(31 downto 0);
if r.hwrite = '1' then
vabufi.write(0) := vabufi.enable;
end if;
end if;
end case;
end if;
end if;
if ((ahbsi.hsel(hindex) and ahbsi.hready) = '1') and
((ahbsi.htrans = HTRANS_BUSY) or (ahbsi.htrans = HTRANS_IDLE))
then v.hready := '1'; end if;
if rst = '0' then
v.ahbactive := '0';
if exten /= 0 then v.enable := resen;
else v.enable := '0'; end if;
v.timer := (others => '0');
v.hsel := '0'; v.dcnten := '0'; v.bhit := '0';
v.regacc := '0'; v.hready := '1';
v.tbreg1.read := '0'; v.tbreg1.write := '0';
v.tbreg2.read := '0'; v.tbreg2.write := '0';
if FILTEN then
vf.smask := (others => '0'); vf.mmask := (others => '0');
end if;
if PERFEN then
pv.split := '0'; pv.splmst := (others => '0');
end if;
if ntrace /= 1 then vb.bsel := (others => '0'); end if;
end if;
if PERFEN then astat <= pr.stat; else astat <= amba_stat_none; end if;
tbi <= vabufi;
rin <= v; rfin <= vf; rbin <= vb; prin <= pv;
ahbso.hconfig <= hconfig;
ahbso.hirq <= hirq;
ahbso.hsplit <= (others => '0');
ahbso.hrdata <= ahbdrivedata(r.hrdata);
ahbso.hready <= r.hready;
ahbso.hindex <= hindex;
end process;
ahbso.hresp <= HRESP_OKAY;
regs : process(clk)
begin if rising_edge(clk) then r <= rin; end if; end process;
fregs : if FILTEN generate
regs : process(clk)
begin if rising_edge(clk) then rf <= rfin; end if; end process;
end generate;
nofregs : if not FILTEN generate
rf.shsel <= (others => '0');
rf.pf <= '0';
rf.af <= '0';
rf.fr <= '0';
rf.fw <= '0';
rf.smask <= (others => '0');
rf.mmask <= (others => '0');
rf.rf <= '0';
end generate;
perf : if PERFEN generate
preg : process(clk)
begin
if rising_edge(clk) then
pr <= prin;
end if;
end process;
end generate;
noperf : if not PERFEN generate
pr.stat <= amba_stat_none;
pr.split <= '0';
pr.splmst <= (others => '0');
pr.hready <= '0';
pr.hresp <= (others => '0');
end generate;
bregs : if ntrace /= 1 generate
regs : process(clk)
begin if rising_edge(clk) then rb <= rbin; end if; end process;
end generate;
nobregs : if ntrace = 1 generate
rb.bsel <= (others => '0');
end generate;
enable <= tbi.enable & tbi.enable;
mem32 : for i in 0 to 1 generate
ram0 : syncram64 generic map (tech => tech, abits => TBUFABITS, testen => scantest, custombits => memtest_vlen)
port map (clk, tbi.addr(TBUFABITS-1 downto 0), tbi.data(((i*64)+63) downto (i*64)),
tbo.data(((i*64)+63) downto (i*64)), enable, tbi.write(i*2+1 downto i*2),
ahbsi.testin
);
end generate;
mem64 : if bwidth > 32 generate -- extra data buffer for 64-bit bus
ram0 : syncram generic map (tech => tech, abits => TBUFABITS, dbits => 32, testen => scantest, custombits => memtest_vlen)
port map ( clk, tbi.addr(TBUFABITS-1 downto 0), tbi.data((128+31) downto 128),
tbo.data((128+31) downto 128), tbi.enable, tbi.write(7),
ahbsi.testin
);
end generate;
mem128 : if bwidth > 64 generate -- extra data buffer for 128-bit bus
ram0 : syncram64 generic map (tech => tech, abits => TBUFABITS, testen => scantest, custombits => memtest_vlen)
port map ( clk, tbi.addr(TBUFABITS-1 downto 0), tbi.data((128+95) downto (128+32)),
tbo.data((128+95) downto (128+32)), enable, tbi.write(6 downto 5),
ahbsi.testin
);
end generate;
nomem64 : if bwidth < 64 generate -- no extra data buffer for 64-bit bus
tbo.data((128+31) downto 128) <= (others => '0');
end generate;
nomem128 : if bwidth < 128 generate -- no extra data buffer for 128-bit bus
tbo.data((128+95) downto (128+32)) <= (others => '0');
end generate;
tbo.data(255 downto 224) <= (others => '0');
-- pragma translate_off
bootmsg : report_version
generic map ("ahbtrace" & tost(hindex) &
": AHB Trace Buffer, " & tost(kbytes) & " kbytes");
-- pragma translate_on
end;
| gpl-3.0 |
EliasLuiz/TCC | Leon3/lib/gaisler/jtag/jtag2.in.vhd | 4 | 92 | -- Second JTAG based DSU interface
constant CFG_AHB_JTAG2 : integer := CONFIG_DSU_JTAG2;
| gpl-3.0 |
kdgwill/VHDL_Framer_Example | VHDL_Framer_Example/Example1/blockDiagram/ramController.vhd | 1 | 3067 | ---------------------------------------------------------------------------------
--RamController---------------------------------------------------------------------
--By Kyle Williams, 04/07/2011--------------------------------------------------
--CLASS DESCRIPTION------------------------------------------------------------
-----3-After frame detect take every 8 bits and store them in a ram----------------
-----4-After 8 bytes have been written in the ram start reading the data from the ram
----------------Define Libraries to be used--------------------------------------
LIBRARY IEEE ;
USE IEEE.std_logic_1164.all ;
USE IEEE.std_logic_unsigned.all;
USE ieee.numeric_std.all;
-----------------ENTITY FOR RAM CONTROLLER------------------------------------------
ENTITY ramController is
GENERIC ( bits : INTEGER := 8;
words : INTEGER := 32); -- # of bits per word
PORT ( reset : IN STD_Logic;
clock : IN STD_LOGIC;
enable : IN STD_LOGIC;
ctrl_in : IN STD_LOGIC_VECTOR (bits - 1 DOWNTO 0);
addr : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
wr_ena : OUT STD_LOGIC; -- write enable
ctrl_out : OUT STD_LOGIC_VECTOR (bits -1 DOWNTO 0)
);
END ramController;
-----------------BEHAVIOR OF RAM CONTROLLER-----------------------------------------
ARCHITECTURE ramController of ramController IS
Signal temp_addr : INTEGER:=0;
--///CHECK FOR CHANGE IN IMPUT AND ADJUST ACCORDINGLY
--/SHOULD ALSO BE DOING WORK OF RETRIEVING
-------------------PROCEDUREE------------------------------
BEGIN
Process(clock,reset)
Variable S_wr_ena : STD_LOGIC:='0';
BEGIN
IF(reset='0') THEN
S_wr_ena:='0';
temp_addr <= 0;
ELSIF(rising_edge(clock) AND enable = '1') THEN
--you can't increment std_logic directly,
--you need to convert it to unsigned and the result
--back to std_logic_vector using the numeric_std package.
--temp_addr <= to_integer(unsigned(S_addr));
IF(S_wr_ena='1')THEN
--READ FROM RAM-------------------------------
--position pointer to end of list if location is 0 to locate the previous address
S_wr_ena:='0';
ELSE
--WRITE TO RAM--------------------------------
--RESET pointer if pointing to location greater than memory else increase address
IF(temp_addr <= words-2)THEN--for some reason compare with 32 instead of 31 look into this
temp_addr <= temp_addr+1;
ELSE
temp_addr <= 0;
END IF;
S_wr_ena:='1';
END IF;
END IF;
wr_ena<=S_wr_ena;
END PROCESS;
ADDR_CHECK:PROCESS(clock, reset)
Variable S_addr : STD_LOGIC_VECTOR(5 DOWNTO 0):="000000";--local variable
BEGIN
IF (reset = '0')THEN
addr <= (others => '0');
s_addr := (others => '0');
ELSIF rising_edge (clock)THEN
s_addr:=std_logic_vector(to_unsigned(temp_addr,6) );
END IF;
addr<=s_addr;
ctrl_out<=ctrl_in;
END PROCESS;
END ramController; | gpl-3.0 |
EliasLuiz/TCC | Leon3/lib/gaisler/pci/grpci2/grpci2_phy.vhd | 1 | 25495 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: grpci2_phy
-- File: grpci2_phy.vhd
-- Author: Nils-Johan Wessman - Aeroflex Gaisler
-- Description: Logic controlled by the PCI control signals in the GRPCI2 core
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
use grlib.config.all;
use grlib.config_types.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.pci.all;
use work.pcilib2.all;
entity grpci2_phy is
generic(
tech : integer := DEFMEMTECH;
oepol : integer := 0;
bypass : integer range 0 to 1 := 1;
netlist : integer := 0;
scantest: integer := 0;
iotest : integer := 0
);
port(
pciclk : in std_logic;
pcii : in pci_in_type;
phyi : in grpci2_phy_in_type;
pcio : out pci_out_type;
phyo : out grpci2_phy_out_type;
iotmact : in std_ulogic;
iotmoe : in std_ulogic;
iotdout : in std_logic_vector(44 downto 0);
iotdin : out std_logic_vector(45 downto 0)
);
end;
architecture rtl of grpci2_phy is
constant oeon : std_logic := conv_std_logic_vector(oepol,1)(0);
constant oeoff : std_logic := not conv_std_logic_vector(oepol,1)(0);
constant ones32 : std_logic_vector(31 downto 0) := (others => '1');
type phy_m_reg_type is record
state : pci_master_state_type;
cfi : integer range 0 to 2;
pi_irdy_or_trdy : std_logic;
last : std_logic_vector(1 downto 0);
hold : std_logic_vector(1 downto 0);
term : std_logic_vector(1 downto 0);
end record;
type phy_t_reg_type is record
cfi : integer range 0 to 2;
pi_irdy_or_trdy : std_logic;
hold : std_logic_vector(0 downto 0);
stop : std_logic;
abort : std_logic;
diswithout : std_logic;
addr_perr : std_logic;
end record;
type phy_reg_type is record
po : pci_reg_out_type;
m : phy_m_reg_type;
t : phy_t_reg_type;
end record;
signal pr, prin : phy_reg_type;
signal pi, piin, piin_buf : pci_in_type; -- Registered PCI signals.
signal po, poin, po_keep : pci_reg_out_type; -- PCI output signals (to drive pads)
signal poin_keep : std_logic_vector(90 downto 0);
signal raden, rinaden, rinaden_tmp : std_logic_vector(31 downto 0);
signal pcirst : std_logic_vector(2 downto 0); -- PCI reset
signal xarst : std_ulogic;
signal pcisynrst : std_ulogic;
attribute sync_set_reset of pcisynrst : signal is "true";
attribute syn_keep : boolean;
attribute syn_keep of poin_keep : signal is true;
begin
phycomb : process(pcii, pr, pi, po, phyi, pcisynrst, rinaden)
variable pv : phy_reg_type;
variable pci : pci_in_type;
begin
-- defaults ---------------------------------------------------------------------
pv := pr;
pv.po.frame := '1'; pv.po.irdy := '1'; pv.po.req := '1';
pv.po.trdy := '1'; pv.po.stop := '1';
pv.po.perr := '1'; pv.po.lock := '1'; pv.po.devsel := '1';
pv.po.serr := '1';
pv.po.devselen := oeoff; pv.po.trdyen := oeoff; pv.po.stopen := oeoff;
pv.po.aden := (others => oeoff); pv.po.cbeen := (others => oeoff);
pv.po.frameen := oeoff; pv.po.irdyen := oeoff;
pv.po.perren := oeoff; pv.po.serren := oeoff;
pv.po.reqen := oeon; -- Always on (point-to-point signal, tri-state during reset)
-- PCI input mux ----------------------------------------------------------------
pci := pcii;
if bypass /= 0 then
if pr.po.aden(0) = oeon then pci.ad := pr.po.ad; end if;
if pr.po.cbeen(0) = oeon then pci.cbe := pr.po.cbe; end if;
if pr.po.frameen = oeon then pci.frame := pr.po.frame; end if;
if pr.po.irdyen = oeon then pci.irdy := pr.po.irdy; end if;
if pr.po.trdyen = oeon then pci.trdy := pr.po.trdy; end if;
if pr.po.stopen = oeon then pci.stop := pr.po.stop; end if;
if pr.po.paren = oeon then pci.par := pr.po.par; end if;
if pr.po.devselen = oeon then pci.devsel := pr.po.devsel; end if;
if pr.po.perren = oeon then pci.perr := pr.po.perr; end if;
if pr.po.serren = oeon then pci.serr := pr.po.serren; end if;
end if;
-- Master -----------------------------------------------------------------------
pv.m.pi_irdy_or_trdy := pi.irdy or pi.trdy;
if ((not (pr.po.irdy or pci.trdy)) and pr.m.pi_irdy_or_trdy) = '1' then
if pr.m.state = pm_m_data or pr.m.state = pm_turn_ar then
--pv.m.cfi := pr.m.cfi + 1;
case pr.m.cfi is
when 0 => pv.m.cfi := 1;
when 1 => pv.m.cfi := 2;
when others => pv.m.cfi := 0;
end case;
end if;
elsif ((pr.po.irdy or pci.trdy) and (not pr.m.pi_irdy_or_trdy)) = '1' then
if pr.m.state = pm_m_data or pr.m.state = pm_turn_ar then
--pv.m.cfi := pr.m.cfi - 1;
case pr.m.cfi is
when 2 => pv.m.cfi := 1;
when 1 => pv.m.cfi := 0;
when others => pv.m.cfi := 0;
end case;
end if;
end if;
-- PCI state machine
case pr.m.state is
when pm_idle =>
if pci.gnt = '0' and (pci.frame and pci.irdy) = '1' then
if phyi.m_request = '1' then pv.m.state := pm_addr;
else pv.m.state := pm_dr_bus; end if;
end if;
pv.m.cfi := 0;
when pm_addr =>
pv.m.state := pm_m_data;
when pm_m_data =>
if pr.po.frame = '0' or (pr.po.frame and pci.trdy and pci.stop and not phyi.m_mabort) = '1' then
pv.m.state := pm_m_data;
elsif (pr.po.frame and (phyi.m_mabort or not pci.stop)) = '1' then
pv.m.state := pm_s_tar;
else
pv.m.state := pm_turn_ar;
end if;
when pm_turn_ar =>
if pci.gnt = '0' then
if phyi.m_request = '1' then pv.m.state := pm_addr; -- remove if no back-to-back
else pv.m.state := pm_dr_bus; end if;
else
pv.m.state := pm_idle;
end if;
when pm_s_tar =>
if pci.gnt = '0' then pv.m.state := pm_dr_bus;
else pv.m.state := pm_idle; end if;
when pm_dr_bus =>
if pci.gnt = '1' then pv.m.state := pm_idle;
elsif phyi.m_request = '1' then pv.m.state := pm_addr; end if;
pv.m.cfi := 0;
when others =>
end case;
if phyi.pr_m_fstate = pmf_fifo then
if (phyi.pv_m_cfifo(0).valid = '1' and phyi.pv_m_cfifo(1).valid = '1' and phyi.pv_m_cfifo(2).valid = '1')
or (phyi.pv_m_cfifo(0).valid = '1' and phyi.pr_m_done_fifo = '1' and not (phyi.pv_m_cfifo(1).valid = '0' and phyi.pv_m_cfifo(2).valid = '1')) then
pv.m.hold(0) := '0';
end if;
if ((pi.trdy or pi.irdy) = '0' and (pr.m.state = pm_m_data or pr.m.state = pm_turn_ar or pr.m.state = pm_s_tar))
or (phyi.pr_m_abort(0)) = '1' then
if phyi.pr_m_cfifo(pv.m.cfi).last = '1' and pr.m.last(0) = '0' then pv.m.last(0) := '1'; end if; -- This is the last data phase
pv.m.last(1) := pr.m.last(0);
if phyi.pr_m_done_fifo = '1' and phyi.pr_m_cfifo(pv.m.cfi).valid = '0' then pv.m.last(1) := '1'; end if; -- This is the last data phase
pv.m.hold(1) := pr.m.hold(0);
end if;
if (pr.m.state = pm_m_data or pr.m.state = pm_addr) and phyi.pr_m_cfifo(pv.m.cfi).hold = '1' then pv.m.hold(0) := '1'; end if; -- Transfer not done but no avalible fifo => deassert IRDY#
if (pr.m.state = pm_s_tar or pr.m.state = pm_turn_ar) then
pv.m.last := (others => '0');
pv.m.hold(0) := '0';
end if;
if phyi.pr_m_cfifo(0).last = '1' and phyi.pr_m_first(0) = '1' and pr.m.state = pm_addr and (phyi.pr_m_cbe_cmd = MEM_WRITE or phyi.pr_m_cbe_cmd = CONF_WRITE or phyi.pr_m_cbe_cmd = IO_WRITE) then pv.m.last := "11"; end if; -- Single data phase
if phyi.pr_m_first(1) = '1' and pr.m.state = pm_m_data and phyi.pr_m_cfifo(pv.m.cfi).last = '1' then pv.m.last(0) := '1'; end if; -- This is the last data phase
end if;
if phyi.pr_m_fstate = pmf_idle then
pv.m.last := (others => '0');
pv.m.hold := (others => '0');
end if;
-- PCI master latency timer timeout
pv.m.term := phyi.pv_m_term;
if pci.gnt = '1' then
if phyi.pr_m_ltimer = x"00" and pr.m.state = pm_m_data and phyi.pr_m_burst = '1' and phyi.pr_m_fstate /= pmf_idle then
pv.m.term(0) := '1';
end if;
end if;
-- FRAME#
if (pci.frame and pci.irdy and not pci.gnt and phyi.m_request) = '1' -- Address phase
or (pr.po.frame = '0' and phyi.m_mabort = '0' -- Not Master abort
and (pr.po.irdy or pci.stop) = '1' -- Not Disconnect
and ((phyi.pr_m_first(0) or not (pr.po.irdy or pci.trdy)) and (phyi.pr_m_cfifo(pv.m.cfi).last or pv.m.term(0))) = '0') then -- Not last data phase
pv.po.frame := '0';
end if;
-- IRDY#
if (pr.po.frame = '0' and phyi.m_mabort = '0' and (pr.m.hold(0) = '0' or (not pr.po.irdy and (pci.trdy and pci.stop)) = '1')) -- Access ongoing, not Master abort, not hold (no data available)
or (pr.po.frame and not phyi.m_mabort and not pr.po.irdy and (pci.trdy and pci.stop)) = '1' then -- Last data phase, not Master abort (if first access, can get master abort)
pv.po.irdy := '0';
end if;
-- Output enable ctrl signals
if (pci.frame and pci.irdy and not pci.gnt) = '1' -- Address phase
or pr.po.frame = '0' -- Access ongoing
or (not pr.po.irdy and (pci.stop and pci.trdy)) = '1' then -- Last data phase
pv.po.frameen := oeon;
pv.po.cbeen := (others => oeon);
end if;
pv.po.irdyen := pr.po.frameen;
-- REQ#
if (phyi.m_request) = '1' and (phyi.m_mabort or phyi.pr_m_abort(0)) = '0' then
pv.po.req := '0';
end if;
-- Output enable req
--pv.po.reqen := oeon; -- always on if not in reset
-- CBE#
if pr.po.irdy = '0' or pr.po.req = '0' or phyi.m_request = '1' then
if pr.m.state /= pm_idle and (pr.m.state /= pm_dr_bus) then pv.po.cbe := phyi.pr_m_cbe_data;
else pv.po.cbe := phyi.pr_m_cbe_cmd; end if;
else
pv.po.cbe := (others => '0');
end if;
-- Target -----------------------------------------------------------------------
pv.t.pi_irdy_or_trdy := pi.irdy or pi.trdy;
if (pr.t.pi_irdy_or_trdy and (not (pci.irdy or pr.po.trdy))) = '1' then
if phyi.pr_t_state = pt_s_data or phyi.pr_t_state = pt_turn_ar or phyi.pr_t_state = pt_backoff then
--pv.t.cfi := pr.t.cfi + 1;
case pr.t.cfi is
when 0 => pv.t.cfi := 1;
when 1 => pv.t.cfi := 2;
when others => pv.t.cfi := 0;
end case;
end if;
elsif ((not pr.t.pi_irdy_or_trdy) and (pci.irdy or pr.po.trdy)) = '1' then
if phyi.pr_t_state = pt_s_data or phyi.pr_t_state = pt_turn_ar or phyi.pr_t_state = pt_backoff then
--pv.t.cfi := pr.t.cfi - 1;
case pr.t.cfi is
when 2 => pv.t.cfi := 1;
when 1 => pv.t.cfi := 0;
when others => pv.t.cfi := 0;
end case;
end if;
end if;
pv.t.hold(0) := (phyi.pr_t_cfifo(pv.t.cfi).hold or pr.t.hold(0) or phyi.pv_t_hold_write) and phyi.pv_t_hold_reset;
pv.t.stop := (phyi.pr_t_cfifo(pv.t.cfi).stlast or pr.t.stop) and phyi.pv_t_hold_reset;
if phyi.pr_t_state = pt_s_data and phyi.pr_t_cfifo(pv.t.cfi).err = '1' and (phyi.pr_t_stoped = '0' or pr.t.abort = '1') and phyi.t_retry = '0' then pv.t.abort := '1';
else pv.t.abort := '0'; end if;
pv.t.diswithout := phyi.pv_t_diswithout;
-- Disconnect without data if CBE change in burst
if pci.cbe /= pi.cbe and (phyi.pr_t_state = pt_s_data and phyi.pr_t_fstate = ptf_write) then pv.t.diswithout := '1'; end if;
-- Parity error detected on address phase
if (phyi.pr_t_state = pt_idle or phyi.pr_t_state = pt_turn_ar) and pi.frame = '0' then
pv.t.addr_perr := (pci.par xor xorv(pi.ad & pi.cbe));
else
pv.t.addr_perr := '0';
end if;
-- TRDY#
if (phyi.pr_t_state = pt_s_data and ((phyi.t_ready and not phyi.t_retry) = '1' and pv.t.diswithout = '0' and
pv.t.abort = '0') and (pr.po.stop and not phyi.pr_t_stoped) = '1' and (phyi.pr_t_first_word or not pci.frame) = '1') -- Target accessed, data/fifo available, not stoped
or (not pr.po.trdy and pci.irdy) = '1' then -- During master waitstates
pv.po.trdy := '0';
end if;
-- STOP#
if
(pr.po.stop = '1' and phyi.pr_t_stoped = '0' and phyi.pr_t_lcount = "111" and pr.po.trdy = '1') -- latency timerout
or ((
((phyi.t_abort = '1' or pv.t.diswithout = '1') and (pci.irdy or pr.po.trdy) = '0' and pci.frame = '0') -- transfer done or disconnect without data (when cbe has changed during write to target)
or (pv.t.abort = '1' and (((pci.irdy or pr.po.trdy) = '0' and pci.frame = '0') or phyi.pr_t_first_word = '1')) -- To signal target abort
or ((phyi.pr_t_cfifo(0).valid and phyi.pr_t_cfifo(0).hold and phyi.pr_t_cfifo(0).stlast and phyi.pr_t_first_word) = '1') -- When first word in this access is the last word in the transfer
) and pr.po.stop = '1' and phyi.pr_t_stoped = '0') -- Only stop when master is ready (and target ready)
or (pr.po.stop = '0' and pci.frame = '0') -- When stop and frame are asserted
or (phyi.t_retry = '1' and pr.po.stop = '1' and phyi.pr_t_stoped = '0') then -- To signal retry
pv.po.stop := '0';
end if;
-- DEVSEL#
if (phyi.pr_t_state /= pt_s_data and phyi.pv_t_state = pt_s_data)
or (pr.po.devsel = '0' and (pci.frame and not pci.irdy and not (pr.po.trdy and pr.po.stop)) = '0'
and pv.t.abort = '0' -- To signal target abort
) then
pv.po.devsel := '0';
end if;
-- Output enable ctrl signals
if phyi.pv_t_state = pt_s_data or phyi.pv_t_state = pt_backoff then
pv.po.devselen := oeon; pv.po.trdyen := oeon; pv.po.stopen := oeon;
end if;
-- Master & Target --------------------------------------------------------------
-- AD
if (pr.m.state /= pm_idle and pr.m.state /= pm_dr_bus and phyi.pr_m_fstate = pmf_fifo) then
pv.po.ad := phyi.pr_m_cfifo(pv.m.cfi).data; -- PCI master data
elsif (phyi.pr_t_state = pt_s_data and phyi.pv_t_state /= pt_turn_ar) then
pv.po.ad := phyi.pr_t_cfifo(pv.t.cfi).data; -- PCI target data
else
pv.po.ad := phyi.pr_m_addr; -- Address
end if;
-- Output enable AD [target]
if phyi.pr_t_state = pt_s_data and phyi.pv_t_state /= pt_turn_ar and phyi.pr_t_cur_acc_0_read = '1'
and (pci.frame and (not pr.po.stop or not pr.po.trdy)) = '0' then
pv.po.aden := (others => oeon);
end if;
-- Output enable AD [master]
if (pcii.frame and pcii.irdy and not pcii.gnt) = '1'
or ((pr.m.state = pm_addr or pr.m.state = pm_m_data) and phyi.pr_m_fstate /= pmf_read and (pr.po.frame and (not pci.stop or not pci.trdy)) = '0') then
pv.po.aden := (others => oeon);
end if;
-- PAR
pv.po.par := xorv(pr.po.ad & pci.cbe);
-- Output enable PAR
pv.po.paren := pr.po.aden(15); -- AD[15] should be closest to PAR
-- PERR
pv.po.perr := pi.irdy or pi.trdy or not (pci.par xor xorv(pi.ad & pi.cbe)); -- Signal perr two cycles after data phase is completed
-- Output enable PERR
if phyi.pr_conf_comm_perren = '1' and -- Parity error response enable bit[6] = 1
(phyi.pr_m_perren(0) = '1' -- During master read
or (phyi.pr_t_state = pt_s_data and phyi.pr_t_cur_acc_0_read = '0') -- Write to target
or (pr.po.perr = '0' and pr.po.perren = oeon)) then -- Parity error on last phase
pv.po.perren := oeon;
end if;
-- SERR & Output enable for SERR
if phyi.pr_conf_comm_perren = '1' and phyi.pr_conf_comm_serren = '1' and pv.t.addr_perr = '1' then
pv.po.serren := oeon;
end if;
-- PCI reset --------------------------------------------------------------------
-- soft reset
if (pcisynrst and not phyi.pcisoftrst(2) and not phyi.pcisoftrst(1)) = '0' then -- Master reset
-- Master
pv.m.state := pm_idle;
pv.m.cfi := 0;
pv.m.hold := (others => '0');
pv.m.term := (others => '0');
end if;
if (pcisynrst and not phyi.pcisoftrst(2) and not phyi.pcisoftrst(0)) = '0' then -- Target reset
-- Target
pv.t.cfi := 0;
pv.t.hold := (others => '0');
pv.t.stop := '0';
pv.t.addr_perr := '0';
end if;
if (pcisynrst and not phyi.pcisoftrst(2)) = '0' then -- Hard reset
-- PCI signals
pv.po.frame := '1'; pv.po.irdy := '1'; pv.po.req := '1';
pv.po.trdy := '1'; pv.po.stop := '1';
pv.po.perr := '1'; pv.po.devsel := '1';
end if;
---------------------------------------------------------------------------------
piin <= pci;
prin <= pv;
poin <= pv.po;
phyo.pciv <= pci;
phyo.pr_m_state <= pr.m.state;
phyo.pr_m_last <= pr.m.last;
phyo.pr_m_hold <= pr.m.hold;
phyo.pr_m_term <= pr.m.term;
phyo.pr_t_hold <= pr.t.hold;
phyo.pr_t_stop <= pr.t.stop;
phyo.pr_t_abort <= pr.t.abort;
phyo.pr_t_diswithout <= pr.t.diswithout;
phyo.pr_t_addr_perr <= pr.t.addr_perr;
phyo.pcirsto(0) <= pcisynrst;
phyo.pr_po <= pr.po;
phyo.pio <= pi;
phyo.poo <= po;
-- PCI output signals
pcio.ad <= po.ad; pcio.vaden <= po.aden;
pcio.cbe <= po.cbe; pcio.cbeen <= po.cbeen;
pcio.frame <= po.frame; pcio.frameen <= po.frameen;
pcio.irdy <= po.irdy; pcio.irdyen <= po.irdyen;
pcio.trdy <= po.trdy; pcio.trdyen <= po.trdyen;
pcio.stop <= po.stop; pcio.stopen <= po.stopen;
pcio.devsel <= po.devsel; pcio.devselen <= po.devselen;
pcio.par <= po.par; pcio.paren <= po.paren;
pcio.perr <= po.perr; pcio.perren <= po.perren;
pcio.req <= po.req; pcio.reqen <= po.reqen;
pcio.int <= '0'; pcio.inten <= phyi.pciinten(0);
pcio.vinten <= phyi.pciinten;
pcio.rst <= phyi.pcirstout;
pcio.serr <= po.serr; pcio.serren <= po.serren;
if SCANTEST/=0 and GRLIB_CONFIG_ARRAY(GRLIB_EXTERNAL_TESTOEN)=0 then
if phyi.testen='1' then
pcio.vaden <= (others => phyi.testoen);
pcio.cbeen <= (others => phyi.testoen);
pcio.frameen <= phyi.testoen;
pcio.irdyen <= phyi.testoen;
pcio.trdyen <= phyi.testoen;
pcio.stopen <= phyi.testoen;
pcio.devselen <= phyi.testoen;
pcio.paren <= phyi.testoen;
pcio.perren <= phyi.testoen;
pcio.reqen <= phyi.testoen;
pcio.inten <= phyi.testoen;
pcio.vinten <= (others => phyi.testoen);
pcio.rst <= phyi.testoen xor oeon;
pcio.serren <= phyi.testoen;
end if;
end if;
-- Unused signals
pcio.lock <= oeoff; pcio.locken <= oeoff;
pcio.aden <= oeoff; pcio.ctrlen <= oeoff;
pcio.pme_enable <= oeoff; pcio.pme_clear <= oeoff;
pcio.power_state <= (others => oeoff);
end process;
-- po_keep <= poin_keep;
poin_keep(31 downto 0) <= poin.ad; po_keep.ad <= poin_keep(31 downto 0);
poin_keep(63 downto 32) <= poin.aden; po_keep.aden <= poin_keep(63 downto 32);
poin_keep(67 downto 64) <= poin.cbe; po_keep.cbe <= poin_keep(67 downto 64);
poin_keep(71 downto 68) <= poin.cbeen; po_keep.cbeen <= poin_keep(71 downto 68);
poin_keep( 72) <= poin.frame; po_keep.frame <= poin_keep( 72);
poin_keep( 73) <= poin.frameen; po_keep.frameen <= poin_keep( 73);
poin_keep( 74) <= poin.irdy; po_keep.irdy <= poin_keep( 74);
poin_keep( 75) <= poin.irdyen; po_keep.irdyen <= poin_keep( 75);
poin_keep( 76) <= poin.trdy; po_keep.trdy <= poin_keep( 76);
poin_keep( 77) <= poin.trdyen; po_keep.trdyen <= poin_keep( 77);
poin_keep( 78) <= poin.stop; po_keep.stop <= poin_keep( 78);
poin_keep( 79) <= poin.stopen; po_keep.stopen <= poin_keep( 79);
poin_keep( 80) <= poin.devsel; po_keep.devsel <= poin_keep( 80);
poin_keep( 81) <= poin.devselen; po_keep.devselen <= poin_keep( 81);
poin_keep( 82) <= poin.par; po_keep.par <= poin_keep( 82);
poin_keep( 83) <= poin.paren; po_keep.paren <= poin_keep( 83);
poin_keep( 84) <= poin.perr; po_keep.perr <= poin_keep( 84);
poin_keep( 85) <= poin.perren; po_keep.perren <= poin_keep( 85);
poin_keep( 86) <= poin.lock; po_keep.lock <= poin_keep( 86);
poin_keep( 87) <= poin.locken; po_keep.locken <= poin_keep( 87);
poin_keep( 88) <= poin.req; po_keep.req <= poin_keep( 88);
poin_keep( 89) <= poin.reqen; po_keep.reqen <= poin_keep( 89);
poin_keep( 90) <= poin.serren; po_keep.serren <= poin_keep( 90);
po_keep.inten <= phyi.pciinten(0);
po_keep.vinten <= phyi.pciinten;
xarst <= phyi.testrst when scantest/=0 and phyi.testen='1' else pcirst(0);
phyreg : process(pciclk, phyi.pciasyncrst, pcirst, xarst)
begin
if rising_edge(pciclk) then
pr <= prin;
pi <= piin;
po <= po_keep;
if iotmact /= '0' then
po.ad <= iotdout(31 downto 0);
po.cbe <= iotdout(35 downto 32);
po.frame <= iotdout(36);
po.irdy <= iotdout(37);
po.trdy <= iotdout(38);
po.par <= iotdout(39);
po.perr <= iotdout(40);
po.serr <= iotdout(41);
po.devsel <= iotdout(42);
po.stop <= iotdout(43);
po.req <= iotdout(44);
po.reqen <= oeon;
if iotmoe /= '0' then
po.aden <= (others => oeon); po.cbeen <= (others => oeon); po.frameen <= oeon;
po.devselen <= oeon; po.trdyen <= oeon; po.irdyen <= oeon; po.stopen <= oeon;
po.paren <= oeon; po.perren <= oeon; po.locken <= oeon;
po.inten <= oeon; po.vinten <= (others => oeon); po.serren <= oeon;
else
po.aden <= (others => oeoff); po.cbeen <= (others => oeoff); po.frameen <= oeoff;
po.devselen <= oeoff; po.trdyen <= oeoff; po.irdyen <= oeoff; po.stopen <= oeoff;
po.paren <= oeoff; po.perren <= oeoff; po.locken <= oeoff;
po.inten <= oeoff; po.vinten <= (others => oeoff); po.serren <= oeoff;
end if;
end if;
pcisynrst <= pcirst(1) and pcirst(2);
pcirst(0) <= pcirst(1) and pcirst(2);
pcirst(1) <= pcirst(2); pcirst(2) <= '1';
end if;
if phyi.pciasyncrst = '0' then pcirst <= (others => '0'); end if;
if xarst = '0' then -- asynch reset required
po.ad <= (others => '1'); pi.ad <= (others => '1'); -- for virtex-4 all registers in IOB need to have same reset
po.trdy <= '1'; pi.trdy <= '1'; po.stop <= '1'; pi.stop <= '1';
po.irdy <= '1'; pi.irdy <= '1'; po.frame <= '1'; pi.frame <= '1';
po.cbe <= (others => '1'); pi.cbe <= (others => '1');
po.par <= '1'; pi.par <= '1';
po.perr <= '1'; pi.perr <= '1';
po.devsel <= '1'; pi.devsel <= '1';
pi.serr <= '1';
po.aden <= (others => oeoff); po.cbeen <= (others => oeoff); po.frameen <= oeoff;
po.devselen <= oeoff; po.trdyen <= oeoff; po.irdyen <= oeoff; po.stopen <= oeoff;
po.paren <= oeoff; po.perren <= oeoff; po.locken <= oeoff; po.reqen <= oeoff;
po.inten <= oeoff; po.vinten <= (others => oeoff); po.serren <= oeoff;
end if;
end process;
iotdin(45) <= pi.idsel;
iotdin(44) <= pi.gnt;
iotdin(43) <= pi.stop;
iotdin(42) <= pi.devsel;
iotdin(41) <= pi.serr;
iotdin(40) <= pi.perr;
iotdin(39) <= pi.par;
iotdin(38) <= pi.trdy;
iotdin(37) <= pi.irdy;
iotdin(36) <= pi.frame;
iotdin(35 downto 32) <= pi.cbe;
iotdin(31 downto 0) <= pi.ad;
end;
| gpl-3.0 |
hoglet67/CoPro6502 | src/ROM/tuberom_pdp11.vhd | 1 | 45768 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity tuberom_pdp11 is
port (
CLK : in std_logic;
ADDR : in std_logic_vector(9 downto 0);
DATA : out std_logic_vector(15 downto 0)
);
end;
architecture RTL of tuberom_pdp11 is
signal rom_addr : std_logic_vector(11 downto 0);
begin
p_addr : process(ADDR)
begin
rom_addr <= (others => '0');
rom_addr(9 downto 0) <= ADDR;
end process;
p_rom : process
begin
wait until rising_edge(CLK);
DATA <= (others => '0');
case rom_addr is
when x"000" => DATA <= x"0077";
when x"001" => DATA <= x"0018";
when x"002" => DATA <= x"500D";
when x"003" => DATA <= x"5044";
when x"004" => DATA <= x"3131";
when x"005" => DATA <= x"5420";
when x"006" => DATA <= x"4255";
when x"007" => DATA <= x"2045";
when x"008" => DATA <= x"3436";
when x"009" => DATA <= x"204B";
when x"00a" => DATA <= x"2E30";
when x"00b" => DATA <= x"3732";
when x"00c" => DATA <= x"0D61";
when x"00d" => DATA <= x"000D";
when x"00e" => DATA <= x"15C6";
when x"00f" => DATA <= x"F5D8";
when x"010" => DATA <= x"17E6";
when x"011" => DATA <= x"F5FC";
when x"012" => DATA <= x"09F7";
when x"013" => DATA <= x"0572";
when x"014" => DATA <= x"159F";
when x"015" => DATA <= x"F5F8";
when x"016" => DATA <= x"15C1";
when x"017" => DATA <= x"F804";
when x"018" => DATA <= x"09F7";
when x"019" => DATA <= x"0084";
when x"01a" => DATA <= x"09F7";
when x"01b" => DATA <= x"048E";
when x"01c" => DATA <= x"00A1";
when x"01d" => DATA <= x"09F7";
when x"01e" => DATA <= x"0124";
when x"01f" => DATA <= x"17C6";
when x"020" => DATA <= x"F5F6";
when x"021" => DATA <= x"15DF";
when x"022" => DATA <= x"F83E";
when x"023" => DATA <= x"F5FC";
when x"024" => DATA <= x"15C1";
when x"025" => DATA <= x"F860";
when x"026" => DATA <= x"09F7";
when x"027" => DATA <= x"0068";
when x"028" => DATA <= x"09F7";
when x"029" => DATA <= x"0280";
when x"02a" => DATA <= x"870C";
when x"02b" => DATA <= x"17C0";
when x"02c" => DATA <= x"F868";
when x"02d" => DATA <= x"09F7";
when x"02e" => DATA <= x"0076";
when x"02f" => DATA <= x"01F4";
when x"030" => DATA <= x"4450";
when x"031" => DATA <= x"3150";
when x"032" => DATA <= x"3E31";
when x"033" => DATA <= x"002A";
when x"034" => DATA <= x"F500";
when x"035" => DATA <= x"20B8";
when x"036" => DATA <= x"00FF";
when x"037" => DATA <= x"15C0";
when x"038" => DATA <= x"007E";
when x"039" => DATA <= x"09F7";
when x"03a" => DATA <= x"01E0";
when x"03b" => DATA <= x"880F";
when x"03c" => DATA <= x"4511";
when x"03d" => DATA <= x"6373";
when x"03e" => DATA <= x"7061";
when x"03f" => DATA <= x"0065";
when x"040" => DATA <= x"17C6";
when x"041" => DATA <= x"F5F6";
when x"042" => DATA <= x"1001";
when x"043" => DATA <= x"0A81";
when x"044" => DATA <= x"09F7";
when x"045" => DATA <= x"042E";
when x"046" => DATA <= x"09F7";
when x"047" => DATA <= x"0028";
when x"048" => DATA <= x"09F7";
when x"049" => DATA <= x"0426";
when x"04a" => DATA <= x"01D4";
when x"04b" => DATA <= x"6000";
when x"04c" => DATA <= x"903F";
when x"04d" => DATA <= x"FD42";
when x"04e" => DATA <= x"0087";
when x"04f" => DATA <= x"E5C1";
when x"050" => DATA <= x"0002";
when x"051" => DATA <= x"9440";
when x"052" => DATA <= x"45C0";
when x"053" => DATA <= x"FF00";
when x"054" => DATA <= x"9241";
when x"055" => DATA <= x"45C1";
when x"056" => DATA <= x"FF00";
when x"057" => DATA <= x"00C1";
when x"058" => DATA <= x"5001";
when x"059" => DATA <= x"0087";
when x"05a" => DATA <= x"09F7";
when x"05b" => DATA <= x"03FC";
when x"05c" => DATA <= x"9440";
when x"05d" => DATA <= x"02FC";
when x"05e" => DATA <= x"0087";
when x"05f" => DATA <= x"A417";
when x"060" => DATA <= x"0021";
when x"061" => DATA <= x"86FD";
when x"062" => DATA <= x"0AC0";
when x"063" => DATA <= x"A417";
when x"064" => DATA <= x"0020";
when x"065" => DATA <= x"03FD";
when x"066" => DATA <= x"0AC0";
when x"067" => DATA <= x"0087";
when x"068" => DATA <= x"7572";
when x"069" => DATA <= x"006E";
when x"06a" => DATA <= x"1066";
when x"06b" => DATA <= x"10A6";
when x"06c" => DATA <= x"10E6";
when x"06d" => DATA <= x"1126";
when x"06e" => DATA <= x"1166";
when x"06f" => DATA <= x"1185";
when x"070" => DATA <= x"2157";
when x"071" => DATA <= x"F500";
when x"072" => DATA <= x"8602";
when x"073" => DATA <= x"15C6";
when x"074" => DATA <= x"F5D8";
when x"075" => DATA <= x"1166";
when x"076" => DATA <= x"17E6";
when x"077" => DATA <= x"F5F6";
when x"078" => DATA <= x"17E6";
when x"079" => DATA <= x"F5FC";
when x"07a" => DATA <= x"09F7";
when x"07b" => DATA <= x"0018";
when x"07c" => DATA <= x"159F";
when x"07d" => DATA <= x"F5FC";
when x"07e" => DATA <= x"159F";
when x"07f" => DATA <= x"F5F6";
when x"080" => DATA <= x"1386";
when x"081" => DATA <= x"1585";
when x"082" => DATA <= x"1584";
when x"083" => DATA <= x"1583";
when x"084" => DATA <= x"1582";
when x"085" => DATA <= x"1581";
when x"086" => DATA <= x"0A00";
when x"087" => DATA <= x"0087";
when x"088" => DATA <= x"09F7";
when x"089" => DATA <= x"FFB2";
when x"08a" => DATA <= x"A417";
when x"08b" => DATA <= x"002A";
when x"08c" => DATA <= x"03FB";
when x"08d" => DATA <= x"0AC0";
when x"08e" => DATA <= x"1001";
when x"08f" => DATA <= x"1004";
when x"090" => DATA <= x"A417";
when x"091" => DATA <= x"002F";
when x"092" => DATA <= x"030F";
when x"093" => DATA <= x"0AC0";
when x"094" => DATA <= x"15C2";
when x"095" => DATA <= x"F8D0";
when x"096" => DATA <= x"9403";
when x"097" => DATA <= x"55C3";
when x"098" => DATA <= x"0020";
when x"099" => DATA <= x"A483";
when x"09a" => DATA <= x"03FB";
when x"09b" => DATA <= x"0AC0";
when x"09c" => DATA <= x"0AC2";
when x"09d" => DATA <= x"A217";
when x"09e" => DATA <= x"0021";
when x"09f" => DATA <= x"8605";
when x"0a0" => DATA <= x"8BCA";
when x"0a1" => DATA <= x"0203";
when x"0a2" => DATA <= x"09F7";
when x"0a3" => DATA <= x"FF7E";
when x"0a4" => DATA <= x"1004";
when x"0a5" => DATA <= x"1100";
when x"0a6" => DATA <= x"09F7";
when x"0a7" => DATA <= x"FF6E";
when x"0a8" => DATA <= x"1037";
when x"0a9" => DATA <= x"FC9C";
when x"0aa" => DATA <= x"15C0";
when x"0ab" => DATA <= x"0002";
when x"0ac" => DATA <= x"09F7";
when x"0ad" => DATA <= x"0518";
when x"0ae" => DATA <= x"09F7";
when x"0af" => DATA <= x"04E4";
when x"0b0" => DATA <= x"00B1";
when x"0b1" => DATA <= x"09F7";
when x"0b2" => DATA <= x"032A";
when x"0b3" => DATA <= x"80D3";
when x"0b4" => DATA <= x"17C1";
when x"0b5" => DATA <= x"F5F8";
when x"0b6" => DATA <= x"15C5";
when x"0b7" => DATA <= x"0000";
when x"0b8" => DATA <= x"0C45";
when x"0b9" => DATA <= x"1066";
when x"0ba" => DATA <= x"9C42";
when x"0bb" => DATA <= x"0007";
when x"0bc" => DATA <= x"45C2";
when x"0bd" => DATA <= x"FF00";
when x"0be" => DATA <= x"6081";
when x"0bf" => DATA <= x"8BD1";
when x"0c0" => DATA <= x"0226";
when x"0c1" => DATA <= x"A457";
when x"0c2" => DATA <= x"0028";
when x"0c3" => DATA <= x"0223";
when x"0c4" => DATA <= x"A457";
when x"0c5" => DATA <= x"0043";
when x"0c6" => DATA <= x"0220";
when x"0c7" => DATA <= x"A457";
when x"0c8" => DATA <= x"0029";
when x"0c9" => DATA <= x"021D";
when x"0ca" => DATA <= x"1381";
when x"0cb" => DATA <= x"9C42";
when x"0cc" => DATA <= x"0006";
when x"0cd" => DATA <= x"45C2";
when x"0ce" => DATA <= x"FFB0";
when x"0cf" => DATA <= x"2097";
when x"0d0" => DATA <= x"0047";
when x"0d1" => DATA <= x"0246";
when x"0d2" => DATA <= x"9C42";
when x"0d3" => DATA <= x"0006";
when x"0d4" => DATA <= x"35C2";
when x"0d5" => DATA <= x"0020";
when x"0d6" => DATA <= x"030E";
when x"0d7" => DATA <= x"9C42";
when x"0d8" => DATA <= x"0007";
when x"0d9" => DATA <= x"45C2";
when x"0da" => DATA <= x"FF00";
when x"0db" => DATA <= x"6081";
when x"0dc" => DATA <= x"0A81";
when x"0dd" => DATA <= x"8BD1";
when x"0de" => DATA <= x"02FE";
when x"0df" => DATA <= x"65C1";
when x"0e0" => DATA <= x"0004";
when x"0e1" => DATA <= x"09F7";
when x"0e2" => DATA <= x"FEDC";
when x"0e3" => DATA <= x"6581";
when x"0e4" => DATA <= x"1066";
when x"0e5" => DATA <= x"55C5";
when x"0e6" => DATA <= x"0002";
when x"0e7" => DATA <= x"1581";
when x"0e8" => DATA <= x"45C1";
when x"0e9" => DATA <= x"0001";
when x"0ea" => DATA <= x"1242";
when x"0eb" => DATA <= x"2097";
when x"0ec" => DATA <= x"0105";
when x"0ed" => DATA <= x"871A";
when x"0ee" => DATA <= x"2097";
when x"0ef" => DATA <= x"0109";
when x"0f0" => DATA <= x"8617";
when x"0f1" => DATA <= x"0BD1";
when x"0f2" => DATA <= x"1443";
when x"0f3" => DATA <= x"1444";
when x"0f4" => DATA <= x"6103";
when x"0f5" => DATA <= x"1444";
when x"0f6" => DATA <= x"17C2";
when x"0f7" => DATA <= x"F5F4";
when x"0f8" => DATA <= x"65C1";
when x"0f9" => DATA <= x"0008";
when x"0fa" => DATA <= x"0C83";
when x"0fb" => DATA <= x"1452";
when x"0fc" => DATA <= x"0AC3";
when x"0fd" => DATA <= x"02FD";
when x"0fe" => DATA <= x"0C84";
when x"0ff" => DATA <= x"0303";
when x"100" => DATA <= x"0A12";
when x"101" => DATA <= x"0AC4";
when x"102" => DATA <= x"02FD";
when x"103" => DATA <= x"17C1";
when x"104" => DATA <= x"F5F4";
when x"105" => DATA <= x"0A26";
when x"106" => DATA <= x"0A26";
when x"107" => DATA <= x"0A26";
when x"108" => DATA <= x"1066";
when x"109" => DATA <= x"1140";
when x"10a" => DATA <= x"15C5";
when x"10b" => DATA <= x"0BBC";
when x"10c" => DATA <= x"0A04";
when x"10d" => DATA <= x"0A03";
when x"10e" => DATA <= x"0A02";
when x"10f" => DATA <= x"17C1";
when x"110" => DATA <= x"F5F0";
when x"111" => DATA <= x"139F";
when x"112" => DATA <= x"F5FA";
when x"113" => DATA <= x"8002";
when x"114" => DATA <= x"139F";
when x"115" => DATA <= x"F5F6";
when x"116" => DATA <= x"0C80";
when x"117" => DATA <= x"0087";
when x"118" => DATA <= x"0C85";
when x"119" => DATA <= x"860B";
when x"11a" => DATA <= x"09F7";
when x"11b" => DATA <= x"0396";
when x"11c" => DATA <= x"880F";
when x"11d" => DATA <= x"4EF9";
when x"11e" => DATA <= x"746F";
when x"11f" => DATA <= x"5020";
when x"120" => DATA <= x"5044";
when x"121" => DATA <= x"3131";
when x"122" => DATA <= x"6320";
when x"123" => DATA <= x"646F";
when x"124" => DATA <= x"0065";
when x"125" => DATA <= x"0077";
when x"126" => DATA <= x"FDF0";
when x"127" => DATA <= x"15F7";
when x"128" => DATA <= x"F804";
when x"129" => DATA <= x"FB9C";
when x"12a" => DATA <= x"0185";
when x"12b" => DATA <= x"1026";
when x"12c" => DATA <= x"8BC0";
when x"12d" => DATA <= x"810B";
when x"12e" => DATA <= x"15C0";
when x"12f" => DATA <= x"0004";
when x"130" => DATA <= x"09F7";
when x"131" => DATA <= x"040A";
when x"132" => DATA <= x"1380";
when x"133" => DATA <= x"09F7";
when x"134" => DATA <= x"040A";
when x"135" => DATA <= x"09F7";
when x"136" => DATA <= x"0222";
when x"137" => DATA <= x"1001";
when x"138" => DATA <= x"012F";
when x"139" => DATA <= x"2017";
when x"13a" => DATA <= x"0082";
when x"13b" => DATA <= x"8703";
when x"13c" => DATA <= x"2017";
when x"13d" => DATA <= x"0085";
when x"13e" => DATA <= x"8722";
when x"13f" => DATA <= x"15C0";
when x"140" => DATA <= x"0006";
when x"141" => DATA <= x"09F7";
when x"142" => DATA <= x"03E8";
when x"143" => DATA <= x"1080";
when x"144" => DATA <= x"09F7";
when x"145" => DATA <= x"03E8";
when x"146" => DATA <= x"1580";
when x"147" => DATA <= x"09F7";
when x"148" => DATA <= x"03E2";
when x"149" => DATA <= x"2017";
when x"14a" => DATA <= x"009D";
when x"14b" => DATA <= x"031D";
when x"14c" => DATA <= x"2017";
when x"14d" => DATA <= x"008E";
when x"14e" => DATA <= x"03D8";
when x"14f" => DATA <= x"1026";
when x"150" => DATA <= x"09F7";
when x"151" => DATA <= x"01EC";
when x"152" => DATA <= x"65C0";
when x"153" => DATA <= x"FF80";
when x"154" => DATA <= x"09F7";
when x"155" => DATA <= x"01E4";
when x"156" => DATA <= x"45C0";
when x"157" => DATA <= x"FF00";
when x"158" => DATA <= x"1002";
when x"159" => DATA <= x"00C0";
when x"15a" => DATA <= x"1001";
when x"15b" => DATA <= x"09F7";
when x"15c" => DATA <= x"01D6";
when x"15d" => DATA <= x"45C0";
when x"15e" => DATA <= x"FF00";
when x"15f" => DATA <= x"5001";
when x"160" => DATA <= x"0107";
when x"161" => DATA <= x"0CC0";
when x"162" => DATA <= x"1C01";
when x"163" => DATA <= x"F4EE";
when x"164" => DATA <= x"1042";
when x"165" => DATA <= x"00C2";
when x"166" => DATA <= x"45C2";
when x"167" => DATA <= x"FF00";
when x"168" => DATA <= x"1580";
when x"169" => DATA <= x"0087";
when x"16a" => DATA <= x"0BC0";
when x"16b" => DATA <= x"034D";
when x"16c" => DATA <= x"10E6";
when x"16d" => DATA <= x"10A6";
when x"16e" => DATA <= x"1026";
when x"16f" => DATA <= x"15C0";
when x"170" => DATA <= x"0008";
when x"171" => DATA <= x"09F7";
when x"172" => DATA <= x"038E";
when x"173" => DATA <= x"1380";
when x"174" => DATA <= x"09F7";
when x"175" => DATA <= x"0388";
when x"176" => DATA <= x"8BC0";
when x"177" => DATA <= x"8003";
when x"178" => DATA <= x"9442";
when x"179" => DATA <= x"9243";
when x"17a" => DATA <= x"010C";
when x"17b" => DATA <= x"15C2";
when x"17c" => DATA <= x"0010";
when x"17d" => DATA <= x"15C3";
when x"17e" => DATA <= x"0010";
when x"17f" => DATA <= x"2017";
when x"180" => DATA <= x"0015";
when x"181" => DATA <= x"8605";
when x"182" => DATA <= x"6000";
when x"183" => DATA <= x"65C0";
when x"184" => DATA <= x"FB48";
when x"185" => DATA <= x"9402";
when x"186" => DATA <= x"9203";
when x"187" => DATA <= x"1080";
when x"188" => DATA <= x"09F7";
when x"189" => DATA <= x"0360";
when x"18a" => DATA <= x"6081";
when x"18b" => DATA <= x"0AC2";
when x"18c" => DATA <= x"2097";
when x"18d" => DATA <= x"0080";
when x"18e" => DATA <= x"8605";
when x"18f" => DATA <= x"9840";
when x"190" => DATA <= x"09F7";
when x"191" => DATA <= x"0350";
when x"192" => DATA <= x"0AC2";
when x"193" => DATA <= x"80FB";
when x"194" => DATA <= x"10C0";
when x"195" => DATA <= x"09F7";
when x"196" => DATA <= x"0346";
when x"197" => DATA <= x"60C1";
when x"198" => DATA <= x"0AC3";
when x"199" => DATA <= x"20D7";
when x"19a" => DATA <= x"0080";
when x"19b" => DATA <= x"8605";
when x"19c" => DATA <= x"09F7";
when x"19d" => DATA <= x"0154";
when x"19e" => DATA <= x"9021";
when x"19f" => DATA <= x"0AC3";
when x"1a0" => DATA <= x"80FB";
when x"1a1" => DATA <= x"1580";
when x"1a2" => DATA <= x"1582";
when x"1a3" => DATA <= x"1583";
when x"1a4" => DATA <= x"0087";
when x"1a5" => DATA <= x"0500";
when x"1a6" => DATA <= x"0005";
when x"1a7" => DATA <= x"0500";
when x"1a8" => DATA <= x"0005";
when x"1a9" => DATA <= x"0504";
when x"1aa" => DATA <= x"0005";
when x"1ab" => DATA <= x"0008";
when x"1ac" => DATA <= x"000E";
when x"1ad" => DATA <= x"0504";
when x"1ae" => DATA <= x"0901";
when x"1af" => DATA <= x"0501";
when x"1b0" => DATA <= x"0005";
when x"1b1" => DATA <= x"0800";
when x"1b2" => DATA <= x"1910";
when x"1b3" => DATA <= x"0020";
when x"1b4" => DATA <= x"0110";
when x"1b5" => DATA <= x"0D0D";
when x"1b6" => DATA <= x"8000";
when x"1b7" => DATA <= x"0808";
when x"1b8" => DATA <= x"8080";
when x"1b9" => DATA <= x"15C0";
when x"1ba" => DATA <= x"000A";
when x"1bb" => DATA <= x"09F7";
when x"1bc" => DATA <= x"02FA";
when x"1bd" => DATA <= x"65C1";
when x"1be" => DATA <= x"0002";
when x"1bf" => DATA <= x"15C2";
when x"1c0" => DATA <= x"0003";
when x"1c1" => DATA <= x"09F7";
when x"1c2" => DATA <= x"02CC";
when x"1c3" => DATA <= x"15C0";
when x"1c4" => DATA <= x"0007";
when x"1c5" => DATA <= x"09F7";
when x"1c6" => DATA <= x"02E6";
when x"1c7" => DATA <= x"0A00";
when x"1c8" => DATA <= x"09F7";
when x"1c9" => DATA <= x"02E0";
when x"1ca" => DATA <= x"09F7";
when x"1cb" => DATA <= x"00F8";
when x"1cc" => DATA <= x"65C0";
when x"1cd" => DATA <= x"FF80";
when x"1ce" => DATA <= x"870B";
when x"1cf" => DATA <= x"09F7";
when x"1d0" => DATA <= x"FCFC";
when x"1d1" => DATA <= x"0A02";
when x"1d2" => DATA <= x"09F7";
when x"1d3" => DATA <= x"00E8";
when x"1d4" => DATA <= x"9011";
when x"1d5" => DATA <= x"0A82";
when x"1d6" => DATA <= x"2017";
when x"1d7" => DATA <= x"000D";
when x"1d8" => DATA <= x"02F9";
when x"1d9" => DATA <= x"0AC2";
when x"1da" => DATA <= x"0087";
when x"1db" => DATA <= x"10A6";
when x"1dc" => DATA <= x"1066";
when x"1dd" => DATA <= x"1026";
when x"1de" => DATA <= x"15C0";
when x"1df" => DATA <= x"000C";
when x"1e0" => DATA <= x"09F7";
when x"1e1" => DATA <= x"02AA";
when x"1e2" => DATA <= x"1081";
when x"1e3" => DATA <= x"15C2";
when x"1e4" => DATA <= x"0004";
when x"1e5" => DATA <= x"09F7";
when x"1e6" => DATA <= x"0284";
when x"1e7" => DATA <= x"1580";
when x"1e8" => DATA <= x"09F7";
when x"1e9" => DATA <= x"02A0";
when x"1ea" => DATA <= x"09F7";
when x"1eb" => DATA <= x"00B8";
when x"1ec" => DATA <= x"1026";
when x"1ed" => DATA <= x"15C2";
when x"1ee" => DATA <= x"0004";
when x"1ef" => DATA <= x"0133";
when x"1f0" => DATA <= x"1026";
when x"1f1" => DATA <= x"15C0";
when x"1f2" => DATA <= x"0012";
when x"1f3" => DATA <= x"09F7";
when x"1f4" => DATA <= x"028A";
when x"1f5" => DATA <= x"1580";
when x"1f6" => DATA <= x"09F7";
when x"1f7" => DATA <= x"0284";
when x"1f8" => DATA <= x"0BC0";
when x"1f9" => DATA <= x"0206";
when x"1fa" => DATA <= x"09F7";
when x"1fb" => DATA <= x"027A";
when x"1fc" => DATA <= x"09F7";
when x"1fd" => DATA <= x"0094";
when x"1fe" => DATA <= x"0A00";
when x"1ff" => DATA <= x"0087";
when x"200" => DATA <= x"1066";
when x"201" => DATA <= x"09F7";
when x"202" => DATA <= x"023E";
when x"203" => DATA <= x"09F7";
when x"204" => DATA <= x"0086";
when x"205" => DATA <= x"1581";
when x"206" => DATA <= x"0087";
when x"207" => DATA <= x"10A6";
when x"208" => DATA <= x"1066";
when x"209" => DATA <= x"1026";
when x"20a" => DATA <= x"15C0";
when x"20b" => DATA <= x"0014";
when x"20c" => DATA <= x"09F7";
when x"20d" => DATA <= x"0258";
when x"20e" => DATA <= x"65C1";
when x"20f" => DATA <= x"0002";
when x"210" => DATA <= x"15C2";
when x"211" => DATA <= x"0010";
when x"212" => DATA <= x"09F7";
when x"213" => DATA <= x"022A";
when x"214" => DATA <= x"09F7";
when x"215" => DATA <= x"FC72";
when x"216" => DATA <= x"09F7";
when x"217" => DATA <= x"0214";
when x"218" => DATA <= x"1580";
when x"219" => DATA <= x"09F7";
when x"21a" => DATA <= x"023E";
when x"21b" => DATA <= x"09F7";
when x"21c" => DATA <= x"0056";
when x"21d" => DATA <= x"1381";
when x"21e" => DATA <= x"1026";
when x"21f" => DATA <= x"65C1";
when x"220" => DATA <= x"0002";
when x"221" => DATA <= x"15C2";
when x"222" => DATA <= x"0010";
when x"223" => DATA <= x"09F7";
when x"224" => DATA <= x"0216";
when x"225" => DATA <= x"1580";
when x"226" => DATA <= x"1581";
when x"227" => DATA <= x"1582";
when x"228" => DATA <= x"0087";
when x"229" => DATA <= x"10A6";
when x"22a" => DATA <= x"1026";
when x"22b" => DATA <= x"15C0";
when x"22c" => DATA <= x"0016";
when x"22d" => DATA <= x"09F7";
when x"22e" => DATA <= x"0216";
when x"22f" => DATA <= x"15C2";
when x"230" => DATA <= x"000D";
when x"231" => DATA <= x"09F7";
when x"232" => DATA <= x"01EC";
when x"233" => DATA <= x"1580";
when x"234" => DATA <= x"09F7";
when x"235" => DATA <= x"0208";
when x"236" => DATA <= x"15C2";
when x"237" => DATA <= x"000D";
when x"238" => DATA <= x"09F7";
when x"239" => DATA <= x"01EC";
when x"23a" => DATA <= x"1582";
when x"23b" => DATA <= x"0108";
when x"23c" => DATA <= x"15C0";
when x"23d" => DATA <= x"000E";
when x"23e" => DATA <= x"09F7";
when x"23f" => DATA <= x"01EE";
when x"240" => DATA <= x"0103";
when x"241" => DATA <= x"0A00";
when x"242" => DATA <= x"09F7";
when x"243" => DATA <= x"01EC";
when x"244" => DATA <= x"09F7";
when x"245" => DATA <= x"0004";
when x"246" => DATA <= x"65C0";
when x"247" => DATA <= x"FF80";
when x"248" => DATA <= x"97C0";
when x"249" => DATA <= x"FFF4";
when x"24a" => DATA <= x"80FD";
when x"24b" => DATA <= x"97C0";
when x"24c" => DATA <= x"FFF6";
when x"24d" => DATA <= x"0087";
when x"24e" => DATA <= x"1026";
when x"24f" => DATA <= x"15C0";
when x"250" => DATA <= x"0010";
when x"251" => DATA <= x"09F7";
when x"252" => DATA <= x"01C8";
when x"253" => DATA <= x"1380";
when x"254" => DATA <= x"09F7";
when x"255" => DATA <= x"01C8";
when x"256" => DATA <= x"09F7";
when x"257" => DATA <= x"FFE0";
when x"258" => DATA <= x"1580";
when x"259" => DATA <= x"0087";
when x"25a" => DATA <= x"25C0";
when x"25b" => DATA <= x"000D";
when x"25c" => DATA <= x"0206";
when x"25d" => DATA <= x"15C0";
when x"25e" => DATA <= x"000A";
when x"25f" => DATA <= x"09F7";
when x"260" => DATA <= x"0004";
when x"261" => DATA <= x"15C0";
when x"262" => DATA <= x"000D";
when x"263" => DATA <= x"35DF";
when x"264" => DATA <= x"0040";
when x"265" => DATA <= x"FFF0";
when x"266" => DATA <= x"03FC";
when x"267" => DATA <= x"901F";
when x"268" => DATA <= x"FFF2";
when x"269" => DATA <= x"0087";
when x"26a" => DATA <= x"880F";
when x"26b" => DATA <= x"42FF";
when x"26c" => DATA <= x"6461";
when x"26d" => DATA <= x"0000";
when x"26e" => DATA <= x"45F6";
when x"26f" => DATA <= x"FFF0";
when x"270" => DATA <= x"0002";
when x"271" => DATA <= x"17E6";
when x"272" => DATA <= x"F5E0";
when x"273" => DATA <= x"17E6";
when x"274" => DATA <= x"F5EC";
when x"275" => DATA <= x"119F";
when x"276" => DATA <= x"F5EC";
when x"277" => DATA <= x"15DF";
when x"278" => DATA <= x"FD12";
when x"279" => DATA <= x"F5E0";
when x"27a" => DATA <= x"0BE6";
when x"27b" => DATA <= x"1026";
when x"27c" => DATA <= x"1D80";
when x"27d" => DATA <= x"0008";
when x"27e" => DATA <= x"1800";
when x"27f" => DATA <= x"45C0";
when x"280" => DATA <= x"FF00";
when x"281" => DATA <= x"6000";
when x"282" => DATA <= x"67C0";
when x"283" => DATA <= x"F5EE";
when x"284" => DATA <= x"1236";
when x"285" => DATA <= x"0002";
when x"286" => DATA <= x"1580";
when x"287" => DATA <= x"09DE";
when x"288" => DATA <= x"8405";
when x"289" => DATA <= x"17C6";
when x"28a" => DATA <= x"F5EC";
when x"28b" => DATA <= x"55F6";
when x"28c" => DATA <= x"0002";
when x"28d" => DATA <= x"0006";
when x"28e" => DATA <= x"8603";
when x"28f" => DATA <= x"55F6";
when x"290" => DATA <= x"0001";
when x"291" => DATA <= x"0006";
when x"292" => DATA <= x"159F";
when x"293" => DATA <= x"F5EC";
when x"294" => DATA <= x"159F";
when x"295" => DATA <= x"F5E0";
when x"296" => DATA <= x"0002";
when x"297" => DATA <= x"1D80";
when x"298" => DATA <= x"0006";
when x"299" => DATA <= x"1DB6";
when x"29a" => DATA <= x"0004";
when x"29b" => DATA <= x"0006";
when x"29c" => DATA <= x"0087";
when x"29d" => DATA <= x"0BD6";
when x"29e" => DATA <= x"159F";
when x"29f" => DATA <= x"F5EC";
when x"2a0" => DATA <= x"159F";
when x"2a1" => DATA <= x"F5E0";
when x"2a2" => DATA <= x"1026";
when x"2a3" => DATA <= x"810B";
when x"2a4" => DATA <= x"2017";
when x"2a5" => DATA <= x"0100";
when x"2a6" => DATA <= x"861B";
when x"2a7" => DATA <= x"6000";
when x"2a8" => DATA <= x"67C0";
when x"2a9" => DATA <= x"F5EE";
when x"2aa" => DATA <= x"1226";
when x"2ab" => DATA <= x"0BC1";
when x"2ac" => DATA <= x"0314";
when x"2ad" => DATA <= x"1048";
when x"2ae" => DATA <= x"0112";
when x"2af" => DATA <= x"0A40";
when x"2b0" => DATA <= x"2017";
when x"2b1" => DATA <= x"000A";
when x"2b2" => DATA <= x"860F";
when x"2b3" => DATA <= x"6000";
when x"2b4" => DATA <= x"6000";
when x"2b5" => DATA <= x"65C0";
when x"2b6" => DATA <= x"F5D8";
when x"2b7" => DATA <= x"1226";
when x"2b8" => DATA <= x"0BC1";
when x"2b9" => DATA <= x"0301";
when x"2ba" => DATA <= x"1048";
when x"2bb" => DATA <= x"0BD0";
when x"2bc" => DATA <= x"1226";
when x"2bd" => DATA <= x"0BC2";
when x"2be" => DATA <= x"0301";
when x"2bf" => DATA <= x"1088";
when x"2c0" => DATA <= x"1582";
when x"2c1" => DATA <= x"1581";
when x"2c2" => DATA <= x"1580";
when x"2c3" => DATA <= x"0002";
when x"2c4" => DATA <= x"0BC0";
when x"2c5" => DATA <= x"0304";
when x"2c6" => DATA <= x"2017";
when x"2c7" => DATA <= x"0003";
when x"2c8" => DATA <= x"871D";
when x"2c9" => DATA <= x"0303";
when x"2ca" => DATA <= x"0087";
when x"2cb" => DATA <= x"007F";
when x"2cc" => DATA <= x"F83E";
when x"2cd" => DATA <= x"0A00";
when x"2ce" => DATA <= x"15D0";
when x"2cf" => DATA <= x"FFC0";
when x"2d0" => DATA <= x"0A10";
when x"2d1" => DATA <= x"2017";
when x"2d2" => DATA <= x"0100";
when x"2d3" => DATA <= x"02FA";
when x"2d4" => DATA <= x"15DF";
when x"2d5" => DATA <= x"FCD4";
when x"2d6" => DATA <= x"001C";
when x"2d7" => DATA <= x"15DF";
when x"2d8" => DATA <= x"FCDC";
when x"2d9" => DATA <= x"0018";
when x"2da" => DATA <= x"15DF";
when x"2db" => DATA <= x"FFBC";
when x"2dc" => DATA <= x"0080";
when x"2dd" => DATA <= x"15DF";
when x"2de" => DATA <= x"00E0";
when x"2df" => DATA <= x"0082";
when x"2e0" => DATA <= x"15DF";
when x"2e1" => DATA <= x"FE9A";
when x"2e2" => DATA <= x"0084";
when x"2e3" => DATA <= x"15DF";
when x"2e4" => DATA <= x"00C0";
when x"2e5" => DATA <= x"0086";
when x"2e6" => DATA <= x"0C00";
when x"2e7" => DATA <= x"17DF";
when x"2e8" => DATA <= x"F5FA";
when x"2e9" => DATA <= x"F5FC";
when x"2ea" => DATA <= x"15C0";
when x"2eb" => DATA <= x"000C";
when x"2ec" => DATA <= x"15C1";
when x"2ed" => DATA <= x"FDFA";
when x"2ee" => DATA <= x"15C2";
when x"2ef" => DATA <= x"F5D8";
when x"2f0" => DATA <= x"8702";
when x"2f1" => DATA <= x"65C0";
when x"2f2" => DATA <= x"0018";
when x"2f3" => DATA <= x"1452";
when x"2f4" => DATA <= x"0AC0";
when x"2f5" => DATA <= x"02FD";
when x"2f6" => DATA <= x"8705";
when x"2f7" => DATA <= x"15C0";
when x"2f8" => DATA <= x"00F0";
when x"2f9" => DATA <= x"1252";
when x"2fa" => DATA <= x"0AC0";
when x"2fb" => DATA <= x"02FD";
when x"2fc" => DATA <= x"0087";
when x"2fd" => DATA <= x"F83E";
when x"2fe" => DATA <= x"0027";
when x"2ff" => DATA <= x"F896";
when x"300" => DATA <= x"F5FF";
when x"301" => DATA <= x"F880";
when x"302" => DATA <= x"F500";
when x"303" => DATA <= x"FD94";
when x"304" => DATA <= x"0000";
when x"305" => DATA <= x"FFC0";
when x"306" => DATA <= x"0000";
when x"307" => DATA <= x"0000";
when x"308" => DATA <= x"F600";
when x"309" => DATA <= x"F804";
when x"30a" => DATA <= x"0000";
when x"30b" => DATA <= x"0100";
when x"30c" => DATA <= x"F500";
when x"30d" => DATA <= x"F83E";
when x"30e" => DATA <= x"F83E";
when x"30f" => DATA <= x"F83E";
when x"310" => DATA <= x"0000";
when x"311" => DATA <= x"FD96";
when x"312" => DATA <= x"F8D4";
when x"313" => DATA <= x"FA56";
when x"314" => DATA <= x"FAD4";
when x"315" => DATA <= x"FCC6";
when x"316" => DATA <= x"FCBA";
when x"317" => DATA <= x"FC82";
when x"318" => DATA <= x"FC0E";
when x"319" => DATA <= x"FBB6";
when x"31a" => DATA <= x"FC78";
when x"31b" => DATA <= x"FC9C";
when x"31c" => DATA <= x"FC52";
when x"31d" => DATA <= x"FBE0";
when x"31e" => DATA <= x"FD88";
when x"31f" => DATA <= x"FD3A";
when x"320" => DATA <= x"FD2E";
when x"321" => DATA <= x"FD94";
when x"322" => DATA <= x"9440";
when x"323" => DATA <= x"09F7";
when x"324" => DATA <= x"002A";
when x"325" => DATA <= x"2017";
when x"326" => DATA <= x"000D";
when x"327" => DATA <= x"02FA";
when x"328" => DATA <= x"0087";
when x"329" => DATA <= x"6081";
when x"32a" => DATA <= x"9840";
when x"32b" => DATA <= x"09F7";
when x"32c" => DATA <= x"001A";
when x"32d" => DATA <= x"0AC2";
when x"32e" => DATA <= x"02FB";
when x"32f" => DATA <= x"0087";
when x"330" => DATA <= x"6081";
when x"331" => DATA <= x"09F7";
when x"332" => DATA <= x"FE2A";
when x"333" => DATA <= x"9021";
when x"334" => DATA <= x"0AC2";
when x"335" => DATA <= x"02FB";
when x"336" => DATA <= x"0087";
when x"337" => DATA <= x"09F7";
when x"338" => DATA <= x"0002";
when x"339" => DATA <= x"1040";
when x"33a" => DATA <= x"35DF";
when x"33b" => DATA <= x"0040";
when x"33c" => DATA <= x"FFF4";
when x"33d" => DATA <= x"03FC";
when x"33e" => DATA <= x"901F";
when x"33f" => DATA <= x"FFF6";
when x"340" => DATA <= x"0087";
when x"341" => DATA <= x"97C0";
when x"342" => DATA <= x"FFF0";
when x"343" => DATA <= x"80FD";
when x"344" => DATA <= x"97C0";
when x"345" => DATA <= x"FFF2";
when x"346" => DATA <= x"0087";
when x"347" => DATA <= x"97C0";
when x"348" => DATA <= x"FFFC";
when x"349" => DATA <= x"80FD";
when x"34a" => DATA <= x"97C0";
when x"34b" => DATA <= x"FFFE";
when x"34c" => DATA <= x"0087";
when x"34d" => DATA <= x"1026";
when x"34e" => DATA <= x"97C0";
when x"34f" => DATA <= x"FFFC";
when x"350" => DATA <= x"811C";
when x"351" => DATA <= x"97C0";
when x"352" => DATA <= x"FFF0";
when x"353" => DATA <= x"8103";
when x"354" => DATA <= x"1580";
when x"355" => DATA <= x"007F";
when x"356" => DATA <= x"F73A";
when x"357" => DATA <= x"97C0";
when x"358" => DATA <= x"FFF2";
when x"359" => DATA <= x"8110";
when x"35a" => DATA <= x"1066";
when x"35b" => DATA <= x"10A6";
when x"35c" => DATA <= x"09F7";
when x"35d" => DATA <= x"FFC6";
when x"35e" => DATA <= x"1002";
when x"35f" => DATA <= x"09F7";
when x"360" => DATA <= x"FFC0";
when x"361" => DATA <= x"1001";
when x"362" => DATA <= x"09F7";
when x"363" => DATA <= x"FFBA";
when x"364" => DATA <= x"09FF";
when x"365" => DATA <= x"F718";
when x"366" => DATA <= x"1582";
when x"367" => DATA <= x"1581";
when x"368" => DATA <= x"1580";
when x"369" => DATA <= x"0002";
when x"36a" => DATA <= x"09FF";
when x"36b" => DATA <= x"F704";
when x"36c" => DATA <= x"01FB";
when x"36d" => DATA <= x"1066";
when x"36e" => DATA <= x"97C0";
when x"36f" => DATA <= x"FFFE";
when x"370" => DATA <= x"8012";
when x"371" => DATA <= x"09F7";
when x"372" => DATA <= x"FDAA";
when x"373" => DATA <= x"17C1";
when x"374" => DATA <= x"F5E2";
when x"375" => DATA <= x"09F7";
when x"376" => DATA <= x"FDA2";
when x"377" => DATA <= x"9011";
when x"378" => DATA <= x"09F7";
when x"379" => DATA <= x"FD9C";
when x"37a" => DATA <= x"9011";
when x"37b" => DATA <= x"02FC";
when x"37c" => DATA <= x"1581";
when x"37d" => DATA <= x"1580";
when x"37e" => DATA <= x"17C0";
when x"37f" => DATA <= x"F5E2";
when x"380" => DATA <= x"17CE";
when x"381" => DATA <= x"F5E0";
when x"382" => DATA <= x"0002";
when x"383" => DATA <= x"1001";
when x"384" => DATA <= x"09F7";
when x"385" => DATA <= x"FF82";
when x"386" => DATA <= x"2057";
when x"387" => DATA <= x"0005";
when x"388" => DATA <= x"03DE";
when x"389" => DATA <= x"09F7";
when x"38a" => DATA <= x"FF78";
when x"38b" => DATA <= x"09F7";
when x"38c" => DATA <= x"FF74";
when x"38d" => DATA <= x"09F7";
when x"38e" => DATA <= x"FF70";
when x"38f" => DATA <= x"901F";
when x"390" => DATA <= x"F5EB";
when x"391" => DATA <= x"09F7";
when x"392" => DATA <= x"FF68";
when x"393" => DATA <= x"901F";
when x"394" => DATA <= x"F5EA";
when x"395" => DATA <= x"6041";
when x"396" => DATA <= x"1C5F";
when x"397" => DATA <= x"FFC2";
when x"398" => DATA <= x"0080";
when x"399" => DATA <= x"09F7";
when x"39a" => DATA <= x"FF58";
when x"39b" => DATA <= x"17C0";
when x"39c" => DATA <= x"F5EA";
when x"39d" => DATA <= x"2057";
when x"39e" => DATA <= x"0008";
when x"39f" => DATA <= x"031D";
when x"3a0" => DATA <= x"2057";
when x"3a1" => DATA <= x"000C";
when x"3a2" => DATA <= x"87C4";
when x"3a3" => DATA <= x"030A";
when x"3a4" => DATA <= x"15C1";
when x"3a5" => DATA <= x"0100";
when x"3a6" => DATA <= x"8BDF";
when x"3a7" => DATA <= x"FFF8";
when x"3a8" => DATA <= x"80FD";
when x"3a9" => DATA <= x"97D0";
when x"3aa" => DATA <= x"FFFA";
when x"3ab" => DATA <= x"0AC1";
when x"3ac" => DATA <= x"02F9";
when x"3ad" => DATA <= x"01B9";
when x"3ae" => DATA <= x"15C1";
when x"3af" => DATA <= x"0100";
when x"3b0" => DATA <= x"8BDF";
when x"3b1" => DATA <= x"FFF8";
when x"3b2" => DATA <= x"80FD";
when x"3b3" => DATA <= x"941F";
when x"3b4" => DATA <= x"FFFA";
when x"3b5" => DATA <= x"0AC1";
when x"3b6" => DATA <= x"02F9";
when x"3b7" => DATA <= x"8BDF";
when x"3b8" => DATA <= x"FFF8";
when x"3b9" => DATA <= x"80FD";
when x"3ba" => DATA <= x"8A1F";
when x"3bb" => DATA <= x"FFFA";
when x"3bc" => DATA <= x"01AA";
when x"3bd" => DATA <= x"101F";
when x"3be" => DATA <= x"F5F8";
when x"3bf" => DATA <= x"01A7";
when x"3c0" => DATA <= x"1026";
when x"3c1" => DATA <= x"17C0";
when x"3c2" => DATA <= x"F5EA";
when x"3c3" => DATA <= x"97D0";
when x"3c4" => DATA <= x"FFFA";
when x"3c5" => DATA <= x"97D0";
when x"3c6" => DATA <= x"FFFA";
when x"3c7" => DATA <= x"0113";
when x"3c8" => DATA <= x"1026";
when x"3c9" => DATA <= x"17C0";
when x"3ca" => DATA <= x"F5EA";
when x"3cb" => DATA <= x"941F";
when x"3cc" => DATA <= x"FFFA";
when x"3cd" => DATA <= x"941F";
when x"3ce" => DATA <= x"FFFA";
when x"3cf" => DATA <= x"010B";
when x"3d0" => DATA <= x"1026";
when x"3d1" => DATA <= x"17C0";
when x"3d2" => DATA <= x"F5EA";
when x"3d3" => DATA <= x"97D0";
when x"3d4" => DATA <= x"FFFA";
when x"3d5" => DATA <= x"0105";
when x"3d6" => DATA <= x"1026";
when x"3d7" => DATA <= x"17C0";
when x"3d8" => DATA <= x"F5EA";
when x"3d9" => DATA <= x"941F";
when x"3da" => DATA <= x"FFFA";
when x"3db" => DATA <= x"101F";
when x"3dc" => DATA <= x"F5EA";
when x"3dd" => DATA <= x"018A";
when x"3de" => DATA <= x"8A1F";
when x"3df" => DATA <= x"FFFA";
when x"3e0" => DATA <= x"0002";
when x"3e1" => DATA <= x"FFAC";
when x"3e2" => DATA <= x"FFA0";
when x"3e3" => DATA <= x"FF90";
when x"3e4" => DATA <= x"FF80";
when x"3e5" => DATA <= x"FFBC";
when x"3e6" => DATA <= x"FFBC";
when x"3e7" => DATA <= x"FFBC";
when x"3e8" => DATA <= x"FFBC";
when x"3e9" => DATA <= x"0000";
when x"3ea" => DATA <= x"0000";
when x"3eb" => DATA <= x"0000";
when x"3ec" => DATA <= x"0000";
when x"3ed" => DATA <= x"0000";
when x"3ee" => DATA <= x"0000";
when x"3ef" => DATA <= x"0000";
when x"3f0" => DATA <= x"0000";
when x"3f1" => DATA <= x"0000";
when x"3f2" => DATA <= x"0000";
when x"3f3" => DATA <= x"0000";
when x"3f4" => DATA <= x"0000";
when x"3f5" => DATA <= x"0000";
when x"3f6" => DATA <= x"0000";
when x"3f7" => DATA <= x"0000";
when x"3f8" => DATA <= x"0000";
when x"3f9" => DATA <= x"0000";
when x"3fa" => DATA <= x"0000";
when x"3fb" => DATA <= x"0000";
when x"3fc" => DATA <= x"0000";
when x"3fd" => DATA <= x"0000";
when x"3fe" => DATA <= x"0000";
when x"3ff" => DATA <= x"0000";
when others => DATA <= (others => '0');
end case;
end process;
end RTL;
| gpl-3.0 |
EliasLuiz/TCC | Leon3/lib/techmap/maps/inpad_ds.vhd | 1 | 3890 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: inpad_ds
-- File: inpad_ds.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: input pad with technology wrapper
------------------------------------------------------------------------------
library techmap;
library ieee;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
use techmap.allpads.all;
entity inpad_ds is
generic (tech : integer := 0; level : integer := lvds; voltage : integer := x33v; term : integer := 0);
port (padp, padn : in std_ulogic; o : out std_ulogic);
end;
architecture rtl of inpad_ds is
signal gnd : std_ulogic;
begin
gnd <= '0';
gen0 : if has_ds_pads(tech) = 0 generate
o <= to_X01(padp)
-- pragma translate_off
after 1 ns
-- pragma translate_on
;
end generate;
xcv : if (tech = virtex2) or (tech = spartan3) generate
u0 : unisim_inpad_ds generic map (level, voltage, term) port map (padp, padn, o);
end generate;
xc4v : if (tech = virtex4) or (tech = spartan3e) or (tech = virtex5) or (tech = spartan6)
or (tech = virtex6) or (tech = virtex7) or (tech = kintex7) or (tech =artix7) or (tech =zynq7000) generate
u0 : virtex4_inpad_ds generic map (level, voltage) port map (padp, padn, o);
end generate;
axc : if (tech = axcel) or (tech = axdsp) generate
u0 : axcel_inpad_ds generic map (level, voltage) port map (padp, padn, o);
end generate;
pa3 : if (tech = apa3) generate
u0 : apa3_inpad_ds generic map (level) port map (padp, padn, o);
end generate;
igl2 : if (tech = igloo2) or (tech = rtg4) generate
u0 : igloo2_inpad_ds port map (padp, padn, o);
end generate;
pa3e : if (tech = apa3e) generate
u0 : apa3e_inpad_ds generic map (level) port map (padp, padn, o);
end generate;
pa3l : if (tech = apa3l) generate
u0 : apa3l_inpad_ds generic map (level) port map (padp, padn, o);
end generate;
fus : if (tech = actfus) generate
u0 : fusion_inpad_ds generic map (level) port map (padp, padn, o);
end generate;
rht : if (tech = rhlib18t) generate
u0 : rh_lib18t_inpad_ds port map (padp, padn, o, gnd);
end generate;
n2x : if (tech = easic45) generate
u0 : n2x_inpad_ds generic map (level, voltage) port map (padp, padn, o);
end generate;
end;
library techmap;
library ieee;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
entity inpad_dsv is
generic (tech : integer := 0; level : integer := lvds;
voltage : integer := x33v; width : integer := 1; term : integer := 0);
port (
padp : in std_logic_vector(width-1 downto 0);
padn : in std_logic_vector(width-1 downto 0);
o : out std_logic_vector(width-1 downto 0));
end;
architecture rtl of inpad_dsv is
begin
v : for i in width-1 downto 0 generate
u0 : inpad_ds generic map (tech, level, voltage, term) port map (padp(i), padn(i), o(i));
end generate;
end;
| gpl-3.0 |
hoglet67/CoPro6502 | src/PDP2011/cpu.vhd | 1 | 236365 |
--
-- Copyright (c) 2008-2015 Sytse van Slooten
--
-- Permission is hereby granted to any person obtaining a copy of these VHDL source files and
-- other language source files and associated documentation files ("the materials") to use
-- these materials solely for personal, non-commercial purposes.
-- You are also granted permission to make changes to the materials, on the condition that this
-- copyright notice is retained unchanged.
--
-- The materials are distributed in the hope that they will be useful, but WITHOUT ANY WARRANTY;
-- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
--
-- $Revision: 1.424 $
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity pdp2011_cpu is
port(
addr_v : out std_logic_vector(15 downto 0); -- the virtual address that the cpu drives out to the bus for the current read or write
datain : in std_logic_vector(15 downto 0); -- when doing a read, the data input to the cpu
dataout : out std_logic_vector(15 downto 0); -- when doing a write, the data output from the cpu
wr : out std_logic; -- if '1', the cpu is doing a write to the bus and drives addr_v and dataout
rd : out std_logic; -- if '1', the cpu is doing a read from the bus, drives addr_v and reads datain
dw8 : out std_logic; -- if '1', the read or write initiated by the cpu is 8 bits wide
cp : out std_logic; -- if '1', the read or write should use the previous cpu mode
ifetch : out std_logic; -- if '1', this read is for an instruction fetch
id : out std_logic; -- if '1', the read or write should use data space
init : out std_logic; -- if '1', the devices on the bus should reset
iwait : out std_logic; -- if '1', the cpu is waiting for an interrupt
br7 : in std_logic; -- interrupt request, 7
bg7 : out std_logic; -- interrupt grant, 7
int_vector7 : in std_logic_vector(8 downto 0); -- interrupt vector, 7
br6 : in std_logic;
bg6 : out std_logic;
int_vector6 : in std_logic_vector(8 downto 0);
br5 : in std_logic;
bg5 : out std_logic;
int_vector5 : in std_logic_vector(8 downto 0);
bg4 : out std_logic; -- interrupt request, 4
br4 : in std_logic; -- interrupt grant, 4
int_vector4 : in std_logic_vector(8 downto 0); -- interrupt vector, 4
mmutrap : in std_logic; -- if '1', the mmu requests a trap to be serviced after the current instruction completes
ack_mmutrap : out std_logic; -- if '1', the mmu trap request is being acknowledged
mmuabort : in std_logic; -- if '1', the mmu requests that the current instruction is aborted because of a mmu fault
ack_mmuabort : out std_logic; -- if '1', the mmu abort request is being acknowledged
npr : in std_logic; -- non-processor request
npg : out std_logic; -- non-processor grant
nxmabort : in std_logic; -- nxm abort - a memory access cycle by the cpu refers to an address that does not exist
oddabort : in std_logic; -- odd abort - a memory access cycle by the cpu is for a full word, but uses an odd address
illhalt : out std_logic; -- a halt instruction was not executed because it was illegal in the current mode; for use in the cer cpu error register
ysv : out std_logic; -- a yellow stack trap is in progress - for use in the cer cpu error register
rsv : out std_logic; -- a red stack trap is in progress - for use in the cer cpu error register
cpu_stack_limit : in std_logic_vector(15 downto 0); -- the cpu stack limit control register value
cpu_kmillhalt : in std_logic; -- the control register setting for kernel mode illegal halt
sr0_ic : out std_logic; -- sr0/mmr0 instruction complete flag
sr1 : out std_logic_vector(15 downto 0); -- sr1/mmr1, address of the current instruction
sr2 : out std_logic_vector(15 downto 0); -- sr2, register autoincrement/autodecrement information for instruction restart
dstfreference : out std_logic; -- if '1', the destination reference is the final reference for this addressing mode
sr3csmenable : in std_logic; -- if '1', the enable csm instruction flag in sr3/mmr3 is set
psw_in : in std_logic_vector(15 downto 0); -- psw input from the control register address @ 177776
psw_in_we_even : in std_logic; -- psw input from the control register address @ 177776, write enable for the even address part
psw_in_we_odd : in std_logic; -- psw input from the control register address @ 177776, write enable for the odd address part
psw_out : out std_logic_vector(15 downto 0); -- psw output, current psw that the cpu uses
pir_in : in std_logic_vector(15 downto 0); -- pirq value input from the control register
modelcode : in integer range 0 to 255; -- cpu model code
have_fp : in integer range 0 to 2 := 2; -- floating point; 0=force disable; 1=force enable; 2=follow default for cpu model
have_fpa : in integer range 0 to 1 := 0; -- floating point accelerator present with J11 cpu
init_r7 : in std_logic_vector(15 downto 0) := x"f600"; -- start address after reset = o'173000' = m9312 hi rom
init_psw : in std_logic_vector(15 downto 0) := x"00e0"; -- initial psw for kernel mode, primary register set, priority 7
run : in std_logic := '0'; -- if '1', continue when the cpu is in halt state
clk : in std_logic; -- input clock
reset : in std_logic -- reset cpu, also causes init signal to devices on the bus to be asserted
);
end pdp2011_cpu;
architecture implementation of pdp2011_cpu is
component cpuregs is
port(
raddr : in std_logic_vector(5 downto 0);
waddr : in std_logic_vector(5 downto 0);
d : in std_logic_vector(15 downto 0);
o : out std_logic_vector(15 downto 0);
we : in std_logic;
clk : in std_logic
);
end component;
component fpuregs is
port(
raddr : in std_logic_vector(2 downto 0);
waddr : in std_logic_vector(2 downto 0);
d : in std_logic_vector(63 downto 0);
o : out std_logic_vector(63 downto 0);
fpmode : in std_logic;
we : in std_logic;
clk : in std_logic
);
end component;
type state_type is (
state_init, state_ifetch, state_idecode,
state_src0,
state_src1,
state_src2, state_src2w,
state_src3, state_src3a,
state_src4, state_src4w,
state_src5, state_src5a,
state_src6, state_src6a,
state_src7, state_src7a, state_src7b,
state_dst0,
state_dst1,
state_dst2,
state_dst3, state_dst3a,
state_dst4,
state_dst5, state_dst5a,
state_dst6, state_dst6a,
state_dst7, state_dst7a, state_dst7b,
state_sob,
state_jmp,
state_jsr, state_jsra, state_jsrb, state_jsrc,
state_rts, state_rtsa,
state_mark, state_marka, state_markb,
state_csm, state_csma, state_csmb, state_csmc, state_csmd, state_csme, state_csmf, state_csmg, state_csmh, state_csmi,
state_mfp, state_mfpa,
state_mtp, state_mtpa,
state_mtps,
state_dopr, state_dopra, state_doprb,
state_mul, state_mula, state_mulb,
state_div, state_diva, state_divb,
state_ash, state_ashb,
state_ashc, state_ashd, state_ashe,
state_xor,
state_ldfps,
state_stststore,
state_fptrap,
state_fpao,
state_fpso2,
state_fpwr, state_fpwr1, state_fpwr2,
state_fpd0,
state_fpir1, state_fpir2,
state_fpiwr, state_fpiww, state_fpiw1, state_fpiw2,
state_fpr1, state_fpr2, state_fpr3, state_fpr4,
state_fpww, state_fpw1, state_fpw2, state_fpw3, state_fpw4,
state_fprun,
state_fprunao,
state_tstset, state_wrtlck, state_wrtlcka,
state_rsv,
state_trap, state_trapa, state_trapb, state_trapc, state_trapw, state_trapd, state_trape, state_trapf,
state_rti, state_rtia, state_rtib,
state_illegalop,
state_mmuabort, state_mmutrap,
state_br7, state_br6, state_br5, state_br4,
state_store_alu_p, state_store_alu_w, state_store_alu_r,
state_npg
);
signal state : state_type := state_init;
signal pdststate : state_type := state_store_alu_r; -- initialize to a valid value, to enable optimizing
signal psrcstate : state_type := state_store_alu_r; -- initialize to a valid value, to enable optimizing
signal ir : std_logic_vector(15 downto 0);
signal ir_addr : std_logic_vector(15 downto 0);
signal ir_dop : std_logic;
signal ir_sop : std_logic;
signal ir_jmp : std_logic;
signal ir_jsr : std_logic;
signal ir_csm : std_logic;
signal ir_mfpi : std_logic;
signal ir_mfpd : std_logic;
signal ir_mf : std_logic;
signal ir_mtpi : std_logic;
signal ir_mtpd : std_logic;
signal ir_mt : std_logic;
signal ir_mtps : std_logic;
signal ir_mfps : std_logic;
signal ir_dopr : std_logic;
signal ir_fpsop1 : std_logic;
signal ir_fpsop2 : std_logic;
signal ir_fpao : std_logic;
signal ir_facdst : std_logic;
signal ir_facsrc : std_logic;
signal ir_facfdst : std_logic;
signal ir_facfsrc : std_logic;
signal ir_fpma48 : std_logic;
signal ir_fpmai : std_logic;
signal ir_fpmaf : std_logic;
signal ir_mpr : std_logic;
signal ir_rtt : std_logic;
signal ir_wait : std_logic;
signal ir_halt : std_logic;
signal ir_byte : std_logic;
signal ir_store : std_logic;
signal ir_srcr7 : std_logic;
signal ir_dstr7 : std_logic;
signal ir_dstm2r7 : std_logic;
signal temp_psw : std_logic_vector(15 downto 0);
signal trap_vector : std_logic_vector(8 downto 0);
signal trap_vectorp2 : std_logic_vector(8 downto 0);
-- addr
signal addr : std_logic_vector(15 downto 0);
-- psw
signal psw : std_logic_vector(15 downto 0) := init_psw;
signal pswmf : std_logic_vector(15 downto 8);
signal psw_delayedupdate : std_logic_vector(15 downto 0);
signal psw_delayedupdate_even : std_logic;
signal psw_delayedupdate_odd : std_logic;
-- pc
signal r7 : std_logic_vector(15 downto 0) := init_r7;
signal r7p2 : std_logic_vector(15 downto 0);
-- alu signals
signal alu_input : std_logic_vector(15 downto 0);
signal alus_input : std_logic_vector(15 downto 0);
signal alut_input : std_logic_vector(15 downto 0);
signal alu_output : std_logic_vector(15 downto 0);
signal alu_output_signext : std_logic_vector(15 downto 0);
signal alu_psw : std_logic_vector(3 downto 0);
-- register bus
signal rbus_raddr : std_logic_vector(5 downto 0);
signal rbus_waddr : std_logic_vector(5 downto 0);
signal rbus_d : std_logic_vector(15 downto 0);
signal rbus_o : std_logic_vector(15 downto 0);
signal rbus_we : std_logic;
signal rbus_ix : std_logic_vector(2 downto 0);
signal rbus_cpu_mode : std_logic_vector(1 downto 0);
signal rbus_data : std_logic_vector(15 downto 0);
signal rbus_data_m8 : std_logic_vector(15 downto 0);
signal rbus_data_m4 : std_logic_vector(15 downto 0);
signal rbus_data_m2 : std_logic_vector(15 downto 0);
signal rbus_data_m1 : std_logic_vector(15 downto 0);
signal rbus_data_p8 : std_logic_vector(15 downto 0);
signal rbus_data_p4 : std_logic_vector(15 downto 0);
signal rbus_data_p2 : std_logic_vector(15 downto 0);
signal rbus_data_p1 : std_logic_vector(15 downto 0);
signal rbus_data_mv : std_logic_vector(15 downto 0);
signal rbus_data_pv : std_logic_vector(15 downto 0);
-- sr1/mmr1
signal sr1_dst : std_logic_vector(7 downto 0);
signal sr1_src : std_logic_vector(7 downto 0);
signal sr1_dstd : std_logic_vector(4 downto 0);
signal sr1_srcd : std_logic_vector(4 downto 0);
signal sr1_p2 : std_logic_vector(4 downto 0);
signal sr1_pv : std_logic_vector(4 downto 0);
signal sr1_m2 : std_logic_vector(4 downto 0);
signal sr1_mv : std_logic_vector(4 downto 0);
-- current/previous mode flags
signal cp_req : std_logic;
signal cp_mf : std_logic;
signal cp_mt : std_logic;
-- id selector output based on state
signal id_select : std_logic;
-- rd output based on state
signal rd_select : std_logic;
signal rs_mt : std_logic;
signal rs_jj : std_logic;
-- address buffers
signal dest_addr : std_logic_vector(15 downto 0);
signal addr_indirect : std_logic_vector(15 downto 0);
signal finalreference : std_logic;
-- signals for eis operations (div, mul, ash, ashc)
signal eis_output : std_logic_vector(15 downto 0);
signal eis_output32 : std_logic_vector(15 downto 0);
signal eis_temp : std_logic_vector(15 downto 0);
signal eis_temp1 : std_logic_vector(31 downto 0);
signal eis_temp2 : std_logic_vector(31 downto 0);
signal eis_sequencer : std_logic_vector(4 downto 0);
signal eis_psw : std_logic_vector(3 downto 0);
signal eis_flag1 : std_logic;
signal eis_flag2 : std_logic;
-- counter for number of cycles to remain in init state
signal initcycles : integer range 0 to 7;
-- signals for yellow stack trap recognition
signal yellow_stack_trap : std_logic;
signal yellow_stack_trap_trigger : std_logic;
signal yellow_stack_trap_relevant_state : std_logic;
signal yellow_stack_trap_inhibit : std_logic;
-- signals for red stack trap recognition
signal red_stack_trap : std_logic;
signal red_stack_trap_trigger : std_logic;
signal red_stack_trap_relevant_state : std_logic;
-- floating point stuff
signal fps : std_logic_vector(15 downto 0);
signal fec : std_logic_vector(3 downto 0);
signal fea : std_logic_vector(15 downto 0);
-- floating point alu
signal falu_input : std_logic_vector(63 downto 0);
signal falus_input : std_logic_vector(63 downto 0);
signal falu_output : std_logic_vector(63 downto 0);
signal falu_output2 : std_logic_vector(63 downto 0);
signal falu_fps : std_logic_vector(3 downto 0);
signal falu_load : std_logic;
signal falu_done : std_logic;
signal falu_flag1 : std_logic;
type falu_fsm_type is (
falu_idle,
falu_align,
falu_mult,
falu_div,
falu_addsub,
falu_shift, falu_shift2, falu_shifte,
falu_norm,
falu_rt, falu_rtc,
falu_sep, falu_sep2, falu_sep3,
falu_zres,
falu_res
);
signal falu_fsm : falu_fsm_type := falu_idle;
signal falu_ccw : std_logic_vector(9 downto 0);
signal falu_state : integer range 0 to 163;
signal falu_work1 : std_logic_vector(58 downto 0);
signal falu_work2 : std_logic_vector(58 downto 0);
signal falu_pending_clear : std_logic;
signal falu_pending_fic : std_logic;
signal falu_pending_fiu : std_logic;
signal falu_pending_fiv : std_logic;
signal falu_pending_divz : std_logic;
-- floating point registers
signal fbus_raddr : std_logic_vector(2 downto 0);
signal fbus_waddr : std_logic_vector(2 downto 0);
signal fbus_d : std_logic_vector(63 downto 0);
signal fbus_o : std_logic_vector(63 downto 0);
signal fbus_we : std_logic;
signal fbus_fd : std_logic;
-- sob slowdown
signal sob_slowdown: integer range 0 to 255;
-- configuration stuff
signal have_sob_zkdjbug : integer range 0 to 1;
signal have_sob : integer range 0 to 1;
signal have_sxt : integer range 0 to 1;
signal have_rtt : integer range 0 to 1;
signal have_mark : integer range 0 to 1;
signal have_xor : integer range 0 to 1;
signal have_eis : integer range 0 to 1;
signal have_fpu_default : integer range 0 to 1;
signal have_fpu : integer range 0 to 1;
signal have_mtps : integer range 0 to 1;
signal have_mfp : integer range 0 to 1;
signal have_mpr : integer range 0 to 1;
signal have_spl : integer range 0 to 1;
signal have_csm : integer range 0 to 1;
signal have_red : integer range 0 to 1;
signal have_pswimmediateupdate : integer range 0 to 1;
signal have_mmuimmediateabort : integer range 0 to 1;
signal have_oddimmediateabort : integer range 0 to 1;
signal have_psw1512 : integer range 0 to 1;
signal have_psw11 : integer range 0 to 1;
signal have_psw8 : integer range 0 to 1;
begin
cpuregs0: cpuregs port map(
raddr => rbus_raddr,
waddr => rbus_waddr,
d => rbus_d,
o => rbus_o,
we => rbus_we,
clk => clk
);
fpuregs0: fpuregs port map(
raddr => fbus_raddr,
waddr => fbus_waddr,
d => fbus_d,
o => fbus_o,
fpmode => fbus_fd,
we => fbus_we,
clk => clk
);
r7p2 <= r7 + 2;
trap_vectorp2 <= trap_vector + 2;
alu_output_signext <= alu_output(7) & alu_output(7) & alu_output(7) & alu_output(7) & alu_output(7) & alu_output(7) & alu_output(7) & alu_output(7) & alu_output(7 downto 0);
-- generate bus stuff
iwait <= ir_wait;
-- finalreference : this bit signals states that access the final operand
-- this is needed for a) byte accesses; b) m[f|t]p[i|d]; so several other access types can be omitted here
with state select finalreference <=
'1' when state_dst1,
'1' when state_dst2,
'1' when state_dst3a,
'1' when state_dst4,
'1' when state_dst5a,
'1' when state_dst6a,
'1' when state_dst7b,
'1' when state_src1,
'1' when state_src2,
'1' when state_src3a,
'1' when state_src4,
'1' when state_src5a,
'1' when state_src6a,
'1' when state_src7b,
'1' when state_store_alu_w,
'0' when others;
-- dstfreference : this bit signals states that access the final operand in dest mode only
-- this is needed for maintenance mode in the mmu, and then most likely only to be able
-- to pass diagnostics without error messages
with state select dstfreference <=
'1' when state_dst1,
'1' when state_dst2,
'1' when state_dst3a,
'1' when state_dst4,
'1' when state_dst5a,
'1' when state_dst6a,
'1' when state_dst7b,
'1' when state_store_alu_w,
'0' when others;
-- generate signals for yellow stack trap
with state select yellow_stack_trap_relevant_state <=
'1' when state_dst4,
'1' when state_dst5a,
'1' when state_src4,
'1' when state_src5a,
'1' when state_trapc,
'1' when state_trapd,
'1' when state_csmc,
'1' when state_csme,
'1' when state_csmg,
'0' when others;
yellow_stack_trap_trigger <= '1'
when yellow_stack_trap_relevant_state = '1'
and rbus_ix = "110"
and psw(15 downto 14) = "00"
and yellow_stack_trap_inhibit = '0'
and red_stack_trap = '0'
and unsigned(cpu_stack_limit) > unsigned(rbus_data_m2)
else '0';
ysv <= yellow_stack_trap_trigger;
-- generate signals for red stack trap
with state select red_stack_trap_relevant_state <=
'1' when state_trapc,
'1' when state_trapd,
'0' when others;
red_stack_trap_trigger <= '1'
when red_stack_trap_relevant_state = '1'
-- and (mmuabort = '1' or oddabort = '1' or nxmabort = '1')
and (oddabort = '1' or nxmabort = '1')
else '0';
rsv <= red_stack_trap_trigger;
-- dw8 : data width 8, signals that a byte is accessed
dw8 <= '1' when (finalreference = '1' and ir_byte = '1') else '0';
-- cp : this address refers to current or previous mode
cp_mf <= '1' when finalreference = '1' and state /= state_store_alu_w and (ir_mfpi = '1' or ir_mfpd = '1') else '0';
cp_mt <= '1' when state = state_store_alu_w and (ir_mtpi = '1' or ir_mtpd = '1') else '0';
cp_req <= '1' when cp_mf = '1' or cp_mt = '1' else '0';
cp <= cp_req;
-- rd : cpu needs read transaction
with state select rd_select <=
'1' when state_idecode,
'1' when state_dst1,
'1' when state_dst2,
'1' when state_dst3 | state_dst3a,
'1' when state_dst4,
'1' when state_dst5 | state_dst5a,
'1' when state_dst6 | state_dst6a,
'1' when state_dst7 | state_dst7a | state_dst7b,
'1' when state_src1,
'1' when state_src2,
'1' when state_src3 | state_src3a,
'1' when state_src4,
'1' when state_src5 | state_src5a,
'1' when state_src6 | state_src6a,
'1' when state_src7 | state_src7a | state_src7b,
'1' when state_mfpa,
'1' when state_mtpa,
'1' when state_fpir1 | state_fpir2,
'1' when state_fpr1 | state_fpr2 | state_fpr3 | state_fpr4,
'1' when state_trapa | state_trapf,
'1' when state_csmi,
'1' when state_rtsa,
'1' when state_markb,
'1' when state_rtia | state_rtib,
'0' when others;
-- rs signals - read suppression for specific cases, because raising the read line would cause a wrong memory access - potentially a trap
rs_mt <= '1' when (ir_mtpi = '1' or ir_mtpd = '1') and finalreference = '1' and state /= state_store_alu_w else '0';
rs_jj <= '1' when (ir_jmp = '1' or ir_jsr = '1') and finalreference = '1' else '0';
rd <= '0' when rs_mt = '1' or rs_jj = '1' or ir_wait = '1' else rd_select;
-- wr : cpu needs write transaction
with state select wr <=
ir_store when state_store_alu_w,
'1' when state_stststore,
'1' when state_fpiw1 | state_fpiw2,
'1' when state_fpw1 | state_fpw2 | state_fpw3 | state_fpw4,
'1' when state_jsrb,
'1' when state_trapc | state_trapd,
'1' when state_csmc | state_csme | state_csmg,
'0' when others;
-- select data to write
with state select dataout <=
alu_output when state_store_alu_w,
fea when state_stststore,
falu_output(63 downto 48) when state_fpw1,
falu_output(47 downto 32) when state_fpw2,
falu_output(31 downto 16) when state_fpw3,
falu_output(15 downto 0) when state_fpw4,
falu_output(63 downto 48) when state_fpiw1,
falu_output(47 downto 32) when state_fpiw2,
rbus_data when state_jsrb,
temp_psw when state_trapc,
r7 when state_trapd,
temp_psw when state_csmc,
r7 when state_csme,
alu_output when state_csmg,
"0000000000000000" when others;
-- addr : select address to drive
with state select addr <=
r7 when state_ifetch, -- r7 is driven out during wait or halt states - only used for debugging, not to drive actual logic
r7 when state_idecode,
rbus_data when state_dst1,
rbus_data when state_dst2,
rbus_data when state_dst3,
addr_indirect when state_dst3a,
rbus_data_mv when state_dst4,
rbus_data_m2 when state_dst5,
addr_indirect when state_dst5a,
r7 when state_dst6,
addr_indirect when state_dst6a,
r7 when state_dst7,
addr_indirect when state_dst7a,
addr_indirect when state_dst7b,
rbus_data when state_src1,
rbus_data when state_src2,
rbus_data when state_src3,
addr_indirect when state_src3a,
rbus_data_mv when state_src4,
rbus_data_m2 when state_src5,
addr_indirect when state_src5a,
r7 when state_src6,
addr_indirect when state_src6a,
r7 when state_src7,
addr_indirect when state_src7a,
addr_indirect when state_src7b,
rbus_data_m2 when state_mfpa,
rbus_data when state_mtpa,
addr_indirect when state_fpir1,
addr_indirect when state_fpir2,
addr_indirect when state_fpr1,
addr_indirect when state_fpr2,
addr_indirect when state_fpr3,
addr_indirect when state_fpr4,
addr_indirect when state_fpiw1,
addr_indirect when state_fpiw2,
addr_indirect when state_fpw1,
addr_indirect when state_fpw2,
addr_indirect when state_fpw3,
addr_indirect when state_fpw4,
"0000000" & trap_vectorp2 when state_trapa,
"0000000" & trap_vector when state_trapb,
rbus_data_m2 when state_trapc,
rbus_data_m2 when state_trapd,
"0000000" & trap_vector when state_trapf,
addr_indirect when state_jsrb,
addr_indirect when state_rtsa,
rbus_data when state_markb,
rbus_data when state_rtia,
rbus_data when state_rtib,
rbus_data_m2 when state_csmc,
rbus_data_m2 when state_csme,
rbus_data_m2 when state_csmg,
"0000000" & trap_vector when state_csmi,
dest_addr when state_store_alu_w,
dest_addr when state_stststore,
"0000000000000000" when others;
addr_v <= addr;
-- id : map states onto instruction or data access
ir_dstm2r7 <= '0' when ir(5 downto 0) = "010111" else '1';
ir_srcr7 <= '0' when ir(8 downto 6) = "111" else '1';
ir_dstr7 <= '0' when ir(2 downto 0) = "111" else '1';
with state select id_select <=
'0' when state_idecode,
ir_dstr7 when state_dst1,
ir_dstr7 when state_dst2,
ir_dstr7 when state_dst3,
'1' when state_dst3a,
ir_dstr7 when state_dst4,
ir_dstr7 when state_dst5,
'1' when state_dst5a,
'0' when state_dst6,
'1' when state_dst6a,
'0' when state_dst7,
'1' when state_dst7a,
'1' when state_dst7b,
ir_srcr7 when state_src1,
ir_srcr7 when state_src2,
ir_srcr7 when state_src3,
'1' when state_src3a,
ir_srcr7 when state_src4,
ir_srcr7 when state_src5,
'1' when state_src5a,
'0' when state_src6,
'1' when state_src6a,
'0' when state_src7,
'1' when state_src7a,
'1' when state_src7b,
ir_dstm2r7 when state_fpir1,
'1' when state_fpir2,
ir_dstm2r7 when state_fpiw1,
'1' when state_fpiw2,
ir_dstm2r7 when state_fpr1,
'1' when state_fpr2 | state_fpr3 | state_fpr4,
ir_dstm2r7 when state_fpw1,
'1' when state_fpw2 | state_fpw3 | state_fpw4,
'1' when state_stststore, -- always in d-space, this is the second store - first is handled by store_alu_w
'1' when state_mfpa, -- move from previous, stack push is to current d-space
'1' when state_mtpa, -- move to previous, stack pop is from current d-space
'1' when state_trapa, -- d-mapping for loading the trap psw from kernel d-space
'1' when state_trapb, -- to enable debugging output via addr - d-mapping should be 1 to 1, i-mapping likely is not
'1' when state_trapc, -- stack is in d-space
'1' when state_trapd, -- stack is in d-space
'1' when state_trapf, -- d-mapping for loading the trap vector from kernel d-space
'1' when state_jsrb,
'1' when state_rtsa,
'0' when state_mark,
'0' when state_marka,
'1' when state_rtia, -- stack is in d-space
'1' when state_rtib, -- stack is in d-space
'1' when state_csmc | state_csme | state_csmg,
'0' when state_csmi, -- apparently; this at least is suggested by 0174_CKKTBD0_1144mmgmt.pdf
ir_dstm2r7 when state_store_alu_w,
'0' when others;
id <=
'1' when ir_mfpi = '1' and psw(15 downto 12) = "1111" and cp_req = '1'
else '0' when ir_mfpi = '1' and cp_req = '1'
else '1' when ir_mfpd = '1' and cp_req = '1'
else '0' when ir_mtpi = '1' and cp_req = '1'
else '1' when ir_mtpd = '1' and cp_req = '1'
else id_select;
-- psw that is output to the mmu
psw_out <= rbus_cpu_mode & pswmf(13 downto 8) & psw(7 downto 0);
-- psw filtered by cpu modelcode
pswmf(15 downto 12) <= psw(15 downto 12) when have_psw1512 = 1 else "0000";
pswmf(11) <= psw(11) when have_psw11 = 1 else '0';
pswmf(10 downto 9) <= "00";
pswmf(8) <= psw(8) when have_psw8 = 1 else '0';
-- pswmf(7 downto 0) <= psw(7 downto 0);
-- registers
rbus_raddr <= rbus_cpu_mode & pswmf(11) & rbus_ix;
with rbus_ix select rbus_data <=
r7 when "111",
rbus_o when others;
-- calculate amount of autoincrement or autodecrement
ir_fpma48 <= '1' when (fps(7) = '1' and ir(11 downto 8) /= "1111") or (fps(7) = '0' and ir(11 downto 8) = "1111") else '0';
rbus_data_m8 <= rbus_data - 8;
rbus_data_m4 <= rbus_data - 4;
rbus_data_m2 <= rbus_data - 2;
rbus_data_m1 <= rbus_data - 1;
rbus_data_p8 <= rbus_data + 8;
rbus_data_p4 <= rbus_data + 4;
rbus_data_p2 <= rbus_data + 2;
rbus_data_p1 <= rbus_data + 1;
rbus_data_mv <= rbus_data_m8 when (ir_fpmaf = '1' and ir_fpma48 = '1' and rbus_ix /= "111")
else rbus_data_m4 when (ir_fpmaf = '1' and ir_fpma48 = '0' and rbus_ix /= "111")
else rbus_data_m4 when (ir_fpmai = '1' and fps(6) = '1' and rbus_ix /= "111")
else rbus_data_m1 when (ir_byte = '1' and rbus_ix(2 downto 1) /= "11")
else rbus_data_m2;
rbus_data_pv <= rbus_data_p8 when (ir_fpmaf = '1' and ir_fpma48 = '1' and rbus_ix /= "111")
else rbus_data_p4 when (ir_fpmaf = '1' and ir_fpma48 = '0' and rbus_ix /= "111")
else rbus_data_p4 when (ir_fpmai = '1' and fps(6) = '1' and rbus_ix /= "111")
else rbus_data_p1 when (ir_byte = '1' and rbus_ix(2 downto 1) /= "11")
else rbus_data_p2;
-- sr1 cq. mmr1 construction
ir_mf <= '1' when ir_mfpi = '1' or ir_mfpd = '1' else '0';
ir_mt <= '1' when ir_mtpi = '1' or ir_mtpd = '1' else '0';
sr1_dst <= sr1_dstd & ir(2 downto 0) when sr1_dstd /= "00000" and ir(2 downto 0) /= "111"
else "00000000";
sr1_src <= sr1_srcd & "110" when (ir_mt = '1' or ir_mf = '1' or ir_jsr = '1') and sr1_srcd /= "00000"
else sr1_srcd & ir(8 downto 6) when sr1_srcd /= "00000" and ir(8 downto 6) /= "111" and ir_dop = '1'
else "00000000";
sr1 <= sr1_dst & sr1_src when (ir_dop = '1' or ir_jsr = '1') and sr1_srcd /= "00000"
else sr1_dst & sr1_src when sr1_dstd = "00000"
else sr1_src & sr1_dst;
-- sr1 <= sr1_src & sr1_dst when sr1_dstd /= "00000" and sr1_src(2 downto 0) /= sr1_dst(2 downto 0)
-- else "00000000" & (sr1_src(7 downto 3) + sr1_dst(7 downto 3)) & sr1_dst(2 downto 0) when sr1_src(2 downto 0) = sr1_dst(2 downto 0)
-- else "00000000" & sr1_src;
sr1_p2 <= "00010";
sr1_pv <= "01000" when (ir_fpmaf = '1' and ir_fpma48 = '1' and rbus_ix /= "111")
else "00100" when (ir_fpmaf = '1' and ir_fpma48 = '0' and rbus_ix /= "111")
else "00100" when (ir_fpmai = '1' and fps(6) = '1' and rbus_ix /= "111")
else "00001" when (ir_byte = '1' and rbus_ix(2 downto 1) /= "11")
else "00010";
sr1_m2 <= "11110";
sr1_mv <= "11000" when (ir_fpmaf = '1' and ir_fpma48 = '1' and rbus_ix /= "111")
else "11100" when (ir_fpmaf = '1' and ir_fpma48 = '0' and rbus_ix /= "111")
else "11100" when (ir_fpmai = '1' and fps(6) = '1' and rbus_ix /= "111")
else "11111" when (ir_byte = '1' and rbus_ix(2 downto 1) /= "11")
else "11110";
-- cpu model configuration
have_sob_zkdjbug <= 0; -- set flag to enable bugfix for zkdj maindec
with modelcode select have_sob <=
1 when 3,
1 when 23 | 24, -- kdf11
1 when 34,
1 when 35 | 40,
1 when 44,
1 when 45 | 50 | 55,
1 when 60,
1 when 70,
1 when 73 | 83 | 84 | 93 | 94, -- kdj11
0 when others;
with modelcode select have_sxt <=
1 when 3,
1 when 23 | 24, -- kdf11
1 when 34,
1 when 35 | 40,
1 when 44,
1 when 45 | 50 | 55,
1 when 60,
1 when 70,
1 when 73 | 83 | 84 | 93 | 94, -- kdj11
0 when others;
with modelcode select have_rtt <=
1 when 3,
1 when 23 | 24, -- kdf11
1 when 34,
1 when 35 | 40,
1 when 44,
1 when 45 | 50 | 55,
1 when 60,
1 when 70,
1 when 73 | 83 | 84 | 93 | 94, -- kdj11
0 when others;
with modelcode select have_mark <=
1 when 3,
1 when 23 | 24, -- kdf11
1 when 34,
1 when 35 | 40,
1 when 44,
1 when 45 | 50 | 55,
1 when 60,
1 when 70,
1 when 73 | 83 | 84 | 93 | 94, -- kdj11
0 when others;
with modelcode select have_xor <=
1 when 3,
1 when 23 | 24, -- kdf11
1 when 34,
1 when 35 | 40,
1 when 44,
1 when 45 | 50 | 55,
1 when 60,
1 when 70,
1 when 73 | 83 | 84 | 93 | 94, -- kdj11
0 when others;
with modelcode select have_eis <=
1 when 23 | 24, -- kdf11
1 when 34,
1 when 35 | 40,
1 when 44,
1 when 45 | 50 | 55,
1 when 60,
1 when 70,
1 when 73 | 83 | 84 | 93 | 94, -- kdj11
0 when others;
with modelcode select have_fpu_default <=
1 when 23 | 24, -- kdf11
1 when 34,
1 when 44,
1 when 45 | 50 | 55,
1 when 60,
1 when 70,
1 when 73 | 83 | 84 | 93 | 94, -- kdj11
0 when others;
have_fpu <= have_fpu_default when have_fp = 2 else have_fp;
with modelcode select have_mtps <=
1 when 3,
1 when 4,
1 when 23 | 24, -- kdf11
1 when 34 | 35 | 40, -- kt11d!
1 when 73 | 83 | 84 | 93 | 94, -- kdj11
0 when others;
with modelcode select have_mfp <=
1 when 23 | 24, -- kdf11
1 when 34 | 35 | 40, -- kt11d!
1 when 44,
1 when 45 | 50 | 55,
1 when 60,
1 when 70,
1 when 73 | 83 | 84 | 93 | 94, -- kdj11
0 when others;
with modelcode select have_mpr <=
1 when 73 | 83 | 84 | 93 | 94, -- kdj11
0 when others;
with modelcode select have_spl <=
1 when 44,
1 when 45 | 50 | 55,
1 when 70,
1 when 73 | 83 | 84 | 93 | 94, -- kdj11
0 when others;
with modelcode select have_csm <=
1 when 44,
1 when 73 | 83 | 84 | 93 | 94, -- kdj11
0 when others;
with modelcode select have_red <=
1 when 35 | 40,
1 when 45 | 50 | 55,
1 when 60,
1 when 70,
1 when 73 | 83 | 84 | 93 | 94, -- kdj11
0 when others;
with modelcode select have_pswimmediateupdate <=
0 when 44, -- observed behaviour, at least from kkab
0 when 4,
-- 0 when 5 | 10, FIXME FIXME FIXME
-- 0 when 15 | 20,
1 when others;
with modelcode select have_mmuimmediateabort <=
-- 1 when 73 | 83 | 84 | 93 | 94, -- kdj11 -- as understood from 2.11BSD, trap.c
0 when others;
with modelcode select have_oddimmediateabort <=
1 when others; -- found no evidence that this is not actually what all pdps do
with modelcode select have_psw1512 <= -- curr/prev mode bits
1 when 23 | 24, -- kdf11
1 when 34 | 35 | 40, -- kt11d!
1 when 44,
1 when 45 | 50 | 55,
1 when 60,
1 when 70,
1 when 73 | 83 | 84 | 93 | 94, -- kdj11
0 when others;
with modelcode select have_psw11 <= -- general purpose reg set bit
1 when 45 | 50 | 55,
1 when 70,
1 when 73 | 83 | 84 | 93 | 94, -- kdj11
0 when others;
with modelcode select have_psw8 <= -- FIXME, what is this? 11/44 handbook has this as CIS insn suspension
1 when 23 | 24, -- kdf11
1 when 44,
1 when 73 | 83 | 84 | 93 | 94, -- kdj11
0 when others;
-- state sequencer
process(clk)
variable v_sop : std_logic;
variable v_dop : std_logic;
variable v_jmp : std_logic;
variable v_jsr : std_logic;
variable v_csm : std_logic;
variable v_mfpi : std_logic;
variable v_mfpd : std_logic;
variable v_mtpi : std_logic;
variable v_mtpd : std_logic;
variable v_mtps : std_logic;
variable v_mfps : std_logic;
variable v_dopr : std_logic;
variable v_mpr : std_logic;
variable v_fpsop1 : std_logic;
variable v_fpsop2 : std_logic;
variable v_fpao : std_logic;
begin
if clk='1' and clk'event then
--
-- synchronous reset; setup some signals that must have a known value after a reset signal to the cpu
--
if reset='1' then
r7 <= init_r7; -- start address
psw <= init_psw; -- initial psw
rbus_cpu_mode <= "00"; -- initial rbus access for kernel mode sp
ir_rtt <= '0'; -- no rtt
ir_wait <= '0'; -- not in wait state
ir_halt <= '0'; -- not halted
bg7 <= '0'; -- no bg7 active
bg6 <= '0'; -- no bg6 active
bg5 <= '0'; -- no bg5 active
bg4 <= '0'; -- no bg4 active
npg <= '0'; -- not granting bus
if have_red = 1 then
red_stack_trap <= '0'; -- not doing a red stack trap
end if;
yellow_stack_trap <= '0'; -- not doing a yellow stack trap
fps <= x"0000"; -- initial fp11 status register
fea <= x"0000"; -- initial fp11 error address register
fec <= "0000"; -- initial fp11 error code register
falu_load <= '0'; -- not doing a load of the fp11 fpao alu
psw_delayedupdate_even <= '0'; -- not updating psw after the fact - even address byte part
psw_delayedupdate_odd <= '0'; -- not updating psw after the fact - odd address byte
state <= state_init; -- first state in the major state machine after reset
initcycles <= 7; -- setup to stay this many cycles in state_init
init <= '1'; -- send reset signal to outside
rbus_waddr <= "000000"; -- select r0 in set 0
rbus_d <= conv_std_logic_vector(modelcode, 16); -- set modelcode on rbus
rbus_we <= '1'; -- pulse write
else
--
-- main state machine; setup some default values for signals that are applicable in each state
--
rbus_we <= '0'; -- default is not writing to the register file
fbus_we <= '0'; -- default is not writing to the fp11 register file
ifetch <= '0'; -- default is not an instruction fetch
ack_mmuabort <= '0'; -- default not acknowledging an mmu abort
ack_mmutrap <= '0'; -- default not acknowledging an mmu trap
illhalt <= '0'; -- no illegal halt
falu_pending_clear <= '0'; -- not clearing any pending fp11 interrupt flags
if yellow_stack_trap_trigger = '1' then -- do we have a pending yellow stack trap?
yellow_stack_trap <= '1'; -- signal to deal with it on the next pass through state_ifetch
end if;
--
-- aborts; these conditions abort the execution of instructions, no matter in which state the state machine is
--
-- the ir_csm check in here is really a dirty hack - it's to prevent state_csmi from changing r7 when an abort occurs in
-- the final memory reference. It's needed to pass zkdk - but, probably a more generic case exists for anything that changes
-- r7. The problem lies in what happens if r7 is changed, and subsequently an abort occurs - then r7 will be pushed, but
-- with the changed value, which most likely is incorrect - because the memory access was aborted.
-- It may make more sense to generically enable have_mmuimmediateabort, but, then 2.11BSD will not run - it needs the
-- decrement of a stack push to be reflected in the r6, because otherwise it will not grow a stack. Re. the ls -als problem.
if have_red = 1 and red_stack_trap_trigger = '1' then -- if the conditions for a red stack trap have tripped
red_stack_trap <= '1'; -- set flag
state <= state_rsv; -- start red trap sequence
elsif mmuabort = '1' and (have_mmuimmediateabort = 1 or ir_csm = '1') then -- signal from mmu that an access caused an abort. dealing with the abort here suppresses any actions taken by the state itself, re. code at end of state machine
state <= state_mmuabort; -- precursor state for mmu abort
ack_mmuabort <= '1'; -- set acknowledge flag to mmu core
elsif oddabort = '1' and (have_oddimmediateabort = 1 or ir_csm = '1') then -- odd abort signal, and need to deal with it and suppress the state machine actions?
trap_vector <= o"004"; -- set vector
state <= state_trap; -- do trap
else
--
-- state_init; this is the first state after a reset, both the hardware signal as well as the insn. This state will
-- set the init signal towards the 'bus', and stretch it a bit, to give slower things on the bus a bit of extra time
-- to reset in their turn. Since there are not really 'slower' things on the bus, this may not be necessary, but at
-- some point it did help in debugging.
--
case state is
when state_init =>
if initcycles = 0 then
state <= state_ifetch;
init <= '0';
else
init <= '1';
initcycles <= initcycles - 1;
end if;
--
-- state_ifetch; all things that need to happen before starting to decode a new instruction. Actually, this state
-- just sets up the memory to produce a new instruction; besides however there is a lot of logic that deduces
-- whether other things, such as handling interrupts need to be serviced before a new instruction can start.
--
-- the if-elsif statement is a priority encoder that determines the relative priority of interrupts.
--
when state_ifetch =>
rbus_cpu_mode <= pswmf(15 downto 14); -- set rbus to the current cpu mode
ir_wait <= '0';
if have_red = 1 then
red_stack_trap <= '0';
end if;
yellow_stack_trap_inhibit <= '0';
if ir_halt = '1' then
if run = '1' then -- mostly just to allow passing a halt in a test program
state <= state_ifetch;
ir_halt <= '0';
end if;
elsif npr = '1' then -- bus master request
state <= state_npg;
npg <= '1';
elsif mmutrap = '1' then -- mmu trap vector = 250
state <= state_mmutrap;
ack_mmutrap <= '1';
elsif yellow_stack_trap = '1' then
yellow_stack_trap <= '0';
yellow_stack_trap_inhibit <= '1';
trap_vector <= o"004"; -- yellow stack trap, vector = 004
state <= state_trap;
elsif falu_pending_fic = '1' then -- pending fic trap from fp11
state <= state_fptrap;
elsif falu_pending_fiu = '1' then -- pending fiu trap from fp11
state <= state_fptrap;
elsif falu_pending_fiv = '1' then -- pending fiv trap from fp11
state <= state_fptrap;
elsif falu_pending_divz = '1' then -- pending div by zero trap from fp11
state <= state_fptrap;
elsif pir_in(15) = '1' and unsigned(psw(7 downto 5)) < unsigned'("111") then
trap_vector <= o"240"; -- pirq, vector = 240
state <= state_trap;
elsif br7 = '1' and unsigned(psw(7 downto 5)) < unsigned'("111") then
state <= state_br7; -- external, level 7, vector determined by device
bg7 <= '1';
elsif pir_in(14) = '1' and unsigned(psw(7 downto 5)) < unsigned'("110") then
trap_vector <= o"240"; -- pirq, vector = 240
state <= state_trap;
elsif br6 = '1' and unsigned(psw(7 downto 5)) < unsigned'("110") then
state <= state_br6; -- external, level 6, vector determined by device
bg6 <= '1';
elsif pir_in(13) = '1' and unsigned(psw(7 downto 5)) < unsigned'("101") then
trap_vector <= o"240"; -- pirq, vector = 240
state <= state_trap;
elsif br5 = '1' and unsigned(psw(7 downto 5)) < unsigned'("101") then
state <= state_br5; -- external, level 5, vector determined by device
bg5 <= '1';
elsif pir_in(12) = '1' and unsigned(psw(7 downto 5)) < unsigned'("100") then
trap_vector <= o"240"; -- pirq, vector = 240
state <= state_trap;
elsif br4 = '1' and unsigned(psw(7 downto 5)) < unsigned'("100") then
state <= state_br4; -- external, level 4, vector determined by device
bg4 <= '1';
elsif pir_in(11) = '1' and unsigned(psw(7 downto 5)) < unsigned'("011") then
trap_vector <= o"240"; -- pirq, vector = 240
state <= state_trap;
elsif pir_in(10) = '1' and unsigned(psw(7 downto 5)) < unsigned'("010") then
trap_vector <= o"240"; -- pirq, vector = 240
state <= state_trap;
elsif pir_in(9) = '1' and unsigned(psw(7 downto 5)) < unsigned'("001") then
trap_vector <= o"240"; -- pirq, vector = 240
state <= state_trap;
elsif psw(4) = '1' and ir_rtt = '0' then
trap_vector <= o"014"; -- trace bit, vector = 014
state <= state_trap;
else
if ir_wait = '0' then -- if not in wait mode
state <= state_idecode; -- go process an instruction
ifetch <= '1'; -- set ifetch flag to signal instruction fetch to the outside world
else
ir_wait <= '1'; -- go into wait mode
end if;
sr1_srcd <= "00000"; -- setup mmu sr1 source part
sr1_dstd <= "00000"; -- setup mmu sr1 destination part
sr0_ic <= '1'; -- set mmu sr0 instruction complete flag
if modelcode = 44 -- fairly sure about this list, see kktb. Seems likely that at least 70 and J11 would also do this variant. However, not sure about F11 or other models
or modelcode = 45 or modelcode = 50 or modelcode = 55 -- and least sure of all about 45... but gamble is on this variant, seems 70 is most likely similar
or modelcode = 70
or modelcode = 73
or modelcode = 83
or modelcode = 84
or modelcode = 93
or modelcode = 94
then
sr2 <= r7; -- store address of instruction for mmu, sr2/mmr2
end if;
end if;
if have_pswimmediateupdate = 0 then -- some cpu models only effectuate the result of updates to the psw after the insn fetch following the update
if psw_delayedupdate_even = '1' then
psw(7 downto 5) <= psw_delayedupdate(7 downto 5); -- T bit can only be set with RTI/RTT instruction
if modelcode = 04 -- except for 11/04 etc
or modelcode = 05 or modelcode = 10
or modelcode = 15 or modelcode = 20
then
psw(4) <= psw_delayedupdate(4);
end if;
psw(3 downto 0) <= psw_delayedupdate(3 downto 0);
end if;
if psw_delayedupdate_odd = '1' then
psw(15 downto 8) <= psw_delayedupdate(15 downto 8);
rbus_cpu_mode <= psw_delayedupdate(15 downto 14); -- set rbus to the current cpu mode
end if;
psw_delayedupdate_even <= '0';
psw_delayedupdate_odd <= '0';
end if;
--
-- state_idecode; decode the instruction word and determine which path through the states will have to be initiated
--
--
-- first, set defaults for several status flags
--
when state_idecode =>
r7 <= r7p2; -- increment pc after instruction fetch
ir <= datain; -- store instruction word
ir_addr <= r7; -- store address of instruction
sr0_ic <= '0'; -- set instruction not complete in our part of sr0/mmr0
if modelcode = 34
or modelcode = 23 or modelcode = 24 -- fixme, verify this, but how?
then
sr2 <= r7; -- store address of instruction for mmu, sr2/mmr2
end if;
ir_fpmaf <= '0'; -- not a fp 4- or 8-byte memory access
ir_fpmai <= '0'; -- not a fp integer mode memory access
ir_sop <= '0'; -- current instruction is not single operand
ir_dop <= '0'; -- current instruction is not dual operand
ir_jmp <= '0'; -- current instruction is not jmp
ir_jsr <= '0'; -- current instruction is not jsr
ir_csm <= '0'; -- current instruction is not csm
ir_mfpi <= '0'; -- current instruction is not mfpi
ir_mfpd <= '0'; -- current instruction is not mfpd
ir_mtpi <= '0'; -- current instruction is not mtpi
ir_mtpd <= '0'; -- current instruction is not mtpd
ir_mtps <= '0'; -- current instruction is not mtps
ir_mfps <= '0'; -- current instruction is not mfps
ir_dopr <= '0'; -- current instruction is not dual operand register
ir_fpsop1 <= '0'; -- current instruction is not an fp single operand group 1 insn
ir_fpsop2 <= '0'; -- current instruction is not an fp single operand group 2 insn
ir_fpao <= '0'; -- current instruction is not an fp accumulator and operand insn
ir_facdst <= '0'; -- current instruction is not an fp accumulator and operand insn in cpu dst format
ir_facsrc <= '0'; -- current instruction is not an fp accumulator and operand insn in cpu src format
ir_facfdst <= '0'; -- current instruction is not an fp accumulator and operand insn in fp11 dst format
ir_facfsrc <= '0'; -- current instruction is not an fp accumulator and operand insn in fp11 src format
ir_mpr <= '0'; -- current instruction is not a multiprocessor instruction
ir_rtt <= '0'; -- current instruction is not rtt and no trace trap is being suppressed
fbus_fd <= fps(7); -- start on the assumption that access to the fp register set follows the fps fd flag
falu_pending_clear <= '1'; -- clear any leftover pending interrupt flags
state <= state_illegalop; -- set catch value in case we don't decode an insn
--
-- setup variables to classify which of several instruction groups the current instruction is, to make the decode logic easier to follow
--
-- sop - single operand insn
if datain(14 downto 9) = "0000101" -- single operand, word or byte (x05xxx)
or datain(14 downto 8) = "00001100" -- single operand, word or byte (x06xxx), first half of range
or datain(15 downto 6) = "0000000011" -- swab
or (datain(15 downto 6) = "0000110111" and have_sxt = 1) -- sxt
then
v_sop := '1';
else
v_sop := '0';
end if;
-- dop - double operand insn
if datain(14 downto 12) /= "000" and datain(14 downto 12) /= "111" then -- dop
v_dop := '1';
else
v_dop := '0';
end if;
-- jmp
if datain(15 downto 6) = "0000000001" then -- jmp
v_jmp := '1';
else
v_jmp := '0';
end if;
-- jsr
if datain(15 downto 9) = "0000100" then -- jsr
v_jsr := '1';
else
v_jsr := '0';
end if;
-- csm
if have_csm = 1 and datain(15 downto 6) = "0000111000" then -- csm
v_csm := '1';
else
v_csm := '0';
end if;
-- mfpi/mfpd/mtpi/mtpd
if have_mfp = 1 and datain(15 downto 6) = "0000110101" then -- mfpi
v_mfpi := '1';
else
v_mfpi := '0';
end if;
if have_mfp = 1 and datain(15 downto 6) = "1000110101" then -- mfpd
v_mfpd := '1';
else
v_mfpd := '0';
end if;
if have_mfp = 1 and datain(15 downto 6) = "0000110110" then -- mtpi
v_mtpi := '1';
else
v_mtpi := '0';
end if;
if have_mfp = 1 and datain(15 downto 6) = "1000110110" then -- mtpd
v_mtpd := '1';
else
v_mtpd := '0';
end if;
-- mtps/mfps
if have_mtps = 1 and datain(15 downto 6) = "1000110100" then -- mtps
v_mtps := '1';
else
v_mtps := '0';
end if;
if have_mtps = 1 and datain(15 downto 6) = "1000110111" then -- mfps
v_mfps := '1';
else
v_mfps := '0';
end if;
-- double operand, register - eis/xor
if (have_eis = 1 and datain(15 downto 11) = "01110") -- mul, div, ash, ashc
or (have_xor = 1 and datain(15 downto 9) = "0111100") then -- xor
v_dopr := '1';
else
v_dopr := '0';
end if;
-- multiprocessor insns - mpr
if have_mpr = 1 and datain(15 downto 7) = "000011101" then -- tstset/wrtlck
v_mpr := '1';
else
v_mpr := '0';
end if;
-- floating point insns - fpu, single op group 1 - those that dont have an ac as operand
if datain(15 downto 8) = "11110000"
and datain(7 downto 6) /= "00"
and have_fpu = 1
then -- fp11 single operand group 1: ldfps, stfps, stst
v_fpsop1 := '1';
else
v_fpsop1 := '0';
end if;
-- floating point insns - fpu, single op group 2 - those that have an ac as operand
if datain(15 downto 8) = "11110001"
and have_fpu = 1
then -- fp11 single operand group 2: clr(f/d), tst(f/d), abs(f/d), neg(f/d)
v_fpsop2 := '1';
else
v_fpsop2 := '0';
end if;
-- floating point insns - fpu, ac and operand group
if datain(15 downto 12) = "1111"
and datain(11 downto 9) /= "000"
and have_fpu = 1
then -- fp11 ac and operand group
v_fpao := '1';
else
v_fpao := '0';
end if;
--
-- setup signal copies of the variables just set, to be used in other states following idecode
--
if v_sop = '1' then
ir_sop <= '1';
end if;
if v_dop = '1' then
ir_dop <= '1';
end if;
if v_jmp = '1' then
ir_jmp <= '1';
end if;
if v_jsr = '1' then
ir_jsr <= '1';
end if;
if v_csm = '1' then
ir_csm <= '1';
end if;
if v_mfpi = '1' then
ir_mfpi <= '1';
end if;
if v_mfpd = '1' then
ir_mfpd <= '1';
end if;
if v_mtpi = '1' then
ir_mtpi <= '1';
end if;
if v_mtpd = '1' then
ir_mtpd <= '1';
end if;
if v_mtps = '1' then
ir_mtps <= '1';
end if;
if v_mfps = '1' then
ir_mfps <= '1';
end if;
if v_dopr = '1' then
ir_dopr <= '1';
end if;
if v_mpr = '1' then
ir_mpr <= '1';
end if;
-- with the floating point insns, here we also set flags that determine whether 2 or 4 (integer), or 4 or 8 (float/double) byte memory access is needed
if v_fpsop1 = '1' then
ir_fpsop1 <= '1';
end if;
if v_fpsop2 = '1' then
ir_fpsop2 <= '1';
ir_fpmaf <= '1';
end if;
if v_fpao = '1' then
ir_fpao <= '1';
ir_facdst <= '0';
ir_facsrc <= '0';
ir_facfdst <= '0';
ir_facfsrc <= '0';
if datain(11 downto 9) = "101" then -- stexp, stc(f|d)(i|l)
ir_facdst <= '1';
if datain(8) = '1' then -- stc(f|d)(i|l)
ir_fpmai <= '1'; -- needs 2 or 4 byte memory access
end if;
elsif datain(11 downto 8) = "1101" then -- ldexp
ir_facsrc <= '1';
elsif datain(11 downto 8) = "1110" then -- ldc(i|l)(f|d)
ir_facsrc <= '1';
ir_fpmai <= '1'; -- needs 2 or 4 byte memory access
elsif datain(11 downto 8) = "1000" then -- st(f|d)
ir_facfdst <= '1';
ir_fpmaf <= '1'; -- needs 4 or 8 byte memory access
elsif datain(11 downto 8) = "1100" then -- stc(f|d)
ir_facfdst <= '1';
ir_fpmaf <= '1'; -- needs 4 or 8 byte memory access
else -- if not any of the other special cases,
ir_facfsrc <= '1'; -- then it should be an fsrc format insn
ir_fpmaf <= '1'; -- needs 4 or 8 byte memory access
end if;
end if;
-- instruction decoder proper
if
v_sop = '1'
or v_dop = '1'
or v_jmp = '1'
or v_jsr = '1'
or v_csm = '1'
or v_mfpi = '1'
or v_mfpd = '1'
or v_mtpi = '1'
or v_mtpd = '1'
or v_mtps = '1'
or v_mfps = '1'
or v_dopr = '1'
or v_mpr = '1'
or v_fpsop1 = '1'
or v_fpsop2 = '1'
or v_fpao = '1'
then
case datain(5 downto 3) is
when "000" =>
psrcstate <= state_dst0;
when "001" =>
psrcstate <= state_dst1;
when "010" =>
psrcstate <= state_dst2;
when "011" =>
psrcstate <= state_dst3;
when "100" =>
psrcstate <= state_dst4;
when "101" =>
psrcstate <= state_dst5;
when "110" =>
psrcstate <= state_dst6;
when "111" =>
psrcstate <= state_dst7;
when others =>
null;
end case;
if datain(5 downto 3) = "000" then
pdststate <= state_store_alu_r;
else
pdststate <= state_store_alu_p;
end if;
if v_dop = '1' then
case datain(11 downto 9) is
when "000" =>
rbus_ix <= datain(8 downto 6);
state <= state_src0;
when "001" =>
rbus_ix <= datain(8 downto 6);
state <= state_src1;
when "010" =>
rbus_ix <= datain(8 downto 6);
state <= state_src2;
when "011" =>
rbus_ix <= datain(8 downto 6);
state <= state_src3;
when "100" =>
rbus_ix <= datain(8 downto 6);
state <= state_src4;
when "101" =>
rbus_ix <= datain(8 downto 6);
state <= state_src5;
when "110" =>
rbus_ix <= datain(8 downto 6);
state <= state_src6;
when "111" =>
rbus_ix <= datain(8 downto 6);
state <= state_src7;
when others =>
null;
end case;
else
case datain(5 downto 3) is
when "000" =>
if v_jmp = '1' then
state <= state_illegalop; -- jmp with mode 0 is illegal
elsif v_jsr = '1' then
state <= state_illegalop; -- jsr with mode 0 is illegal
elsif have_mfp = 1 and (v_mfpi = '1' or v_mfpd = '1') then
if datain(2 downto 0) = "110" then
rbus_cpu_mode <= psw(13 downto 12);
end if;
rbus_ix <= datain(2 downto 0);
state <= state_dst0;
elsif have_mfp = 1 and (v_mtpi = '1' or v_mtpd = '1') then -- if mode is 0, it's not very interesting to try and read the register
rbus_ix <= "110";
state <= state_mtp;
elsif have_mpr = 1 and v_mpr = '1' then
state <= state_illegalop; -- tstset/wrtlck mode 0 are illegal
elsif have_fpu = 1 and v_fpao = '1' then
if datain(11 downto 9) /= "101" -- stexp, stc(f/d)(i/l)
and datain(11 downto 8) /= "1101" -- ldexp
and datain(11 downto 8) /= "1110" -- ldc(i/l)(f/d)
then
if datain(2 downto 1) = "11" then -- ac6 and ac7 do not exist
fec <= "0010";
state <= state_fptrap;
else
if datain(11) & datain(9 downto 8) = "100" then
fbus_raddr <= '0' & datain(7 downto 6); -- fdst insn, need ac
else
fbus_raddr <= datain(2 downto 0); -- fsrc insn, need mode 0 fsrc ac
end if;
state <= state_fpao;
end if;
else
fbus_raddr <= '0' & datain(7 downto 6); -- ldexp, ldc(i/l)(f/d), stexp, stc(f/d)(i/l) get ac
rbus_ix <= datain(2 downto 0);
state <= state_dst0;
end if;
elsif have_fpu = 1 and v_fpsop2 = '1' then
if datain(2 downto 1) = "11" then -- ac6 and ac7 do not exist
fec <= "0010";
state <= state_fptrap;
else
fbus_raddr <= datain(2 downto 0); -- fsrc insn, need mode 0 fsrc ac
state <= state_fpso2;
end if;
else
rbus_ix <= datain(2 downto 0);
state <= state_dst0;
end if;
when "001" =>
state <= state_dst1;
rbus_ix <= datain(2 downto 0);
when "010" =>
state <= state_dst2;
rbus_ix <= datain(2 downto 0);
when "011" =>
state <= state_dst3;
rbus_ix <= datain(2 downto 0);
when "100" =>
state <= state_dst4;
rbus_ix <= datain(2 downto 0);
when "101" =>
state <= state_dst5;
rbus_ix <= datain(2 downto 0);
when "110" =>
state <= state_dst6;
rbus_ix <= datain(2 downto 0);
when "111" =>
state <= state_dst7;
rbus_ix <= datain(2 downto 0);
when others =>
null;
end case;
if v_sop = '1' then
if datain(5 downto 3) = "000" then
pdststate <= state_store_alu_r;
else
pdststate <= state_store_alu_p;
end if;
elsif v_jmp = '1' then
pdststate <= state_jmp;
elsif v_jsr = '1' then
pdststate <= state_jsr;
elsif v_csm = '1' then
pdststate <= state_csm;
elsif v_mfpi = '1' or v_mfpd = '1' then
pdststate <= state_mfp;
elsif v_mtpi = '1' or v_mtpd = '1' then
rbus_ix <= "110";
state <= state_mtp;
elsif have_mtps = 1 and v_mtps = '1' then
pdststate <= state_mtps;
elsif have_mtps = 1 and v_mfps = '1' then
if datain(5 downto 3) = "000" then
pdststate <= state_store_alu_r;
else
pdststate <= state_store_alu_p;
end if;
elsif v_dopr = '1' then
pdststate <= state_dopr;
elsif v_mpr = '1' then
if datain(6) = '0' then
pdststate <= state_tstset;
else
pdststate <= state_wrtlck;
end if;
elsif have_fpu = 1 and v_fpsop1 = '1' then
case datain(7 downto 6) is
when "01" => -- ldfps
pdststate <= state_ldfps;
when "10" => -- stfps
if datain(5 downto 3) = "000" then
pdststate <= state_store_alu_r;
else
pdststate <= state_store_alu_p;
end if;
when "11" => -- stst
if datain(5 downto 3) = "000" then
pdststate <= state_store_alu_r;
else
pdststate <= state_store_alu_p;
end if;
when others =>
null;
end case;
elsif have_fpu = 1 and v_fpsop2 = '1' then
pdststate <= state_fpso2; -- clr(f|d),tst(f|d),abs(f|d),neg(f|d)
elsif have_fpu = 1 and v_fpao = '1' then
pdststate <= state_fpao;
if datain(11 downto 8) = "1101" -- ldexp
or datain(11 downto 8) = "1010" -- stexp
or datain(11) & datain(9 downto 8) = "100" -- st(f|d), stc(f|d)(d|f)
or datain(11 downto 8) = "1011" -- stc(f|d)(i|l)
then
fbus_raddr <= '0' & datain(7 downto 6); -- needed for st(f|d), stc(f|d)(d|f), ldexp, stexp
end if;
else
pdststate <= state_illegalop;
end if;
end if;
end if;
if datain(14 downto 11) = "0000" then -- pc and ps change, excl. jsr, emt, trap
if datain(15) = '0' and datain(10 downto 8) = "000" then -- halt group, jmp
-- halt is a complicated case - it is handled differently by most models - it traps either to 4, 10, or to the console, or plainly halts
-- don't have a console yet - so the last two are simple. Still, the mode bit for the J11 came as a surprise - thought I had seen all variants.
if datain(7 downto 0) = "00000000" then -- halt
if pswmf(15 downto 14) /= "00"
and (modelcode = 73 or modelcode = 44 or modelcode = 45 or modelcode = 50 or modelcode = 55 or modelcode = 70 or modelcode = 84 or modelcode = 83 or modelcode = 93 or modelcode = 94)
then
illhalt <= '1';
trap_vector <= o"004";
state <= state_trap;
elsif pswmf(15 downto 14) /= "00"
and (modelcode = 23 or modelcode = 24 or modelcode = 34 or modelcode = 35 or modelcode = 40 or modelcode = 60)
then
illhalt <= '1';
trap_vector <= o"010";
state <= state_trap;
elsif modelcode = 3 or modelcode = 21 or modelcode = 4 or modelcode = 5 or modelcode = 10 or modelcode = 15 or modelcode = 20
then
ir_halt <= '1';
state <= state_ifetch;
elsif pswmf(15 downto 14) = "00" and cpu_kmillhalt = '1'
then
illhalt <= '1';
trap_vector <= o"004";
state <= state_trap;
elsif pswmf(15 downto 14) = "00"
then
ir_halt <= '1';
state <= state_ifetch;
else -- the default, if we do not know the model of the cpu, is to follow the rule of J11
illhalt <= '1';
trap_vector <= o"004";
state <= state_trap;
end if;
end if;
if datain(7 downto 0) = "00000001" then -- wait
if pswmf(15 downto 14) = "00" then -- if not in kernel mode, this insn is a noop
ir_wait <= '1'; -- setting this flag will cause ifetch not to switch into idecode until an interrupt has occurred
end if;
state <= state_ifetch; -- next state is ifetch
end if;
if datain(7 downto 0) = "00000010" then -- rti
state <= state_rti;
rbus_ix <= "110";
if modelcode = 4 -- these models do not have rtt, but allow rti to set the t bit
or modelcode = 5 or modelcode = 10
or modelcode = 15 or modelcode = 20
then
if psw(4) = '0' then
ir_rtt <= '1';
end if;
end if;
end if;
if datain(7 downto 0) = "00000011" then -- bpt
trap_vector <= o"014"; -- bpt, vector = 014
state <= state_trap;
end if;
if datain(7 downto 0) = "00000100" then -- iot
trap_vector <= o"020"; -- iot, vector = 020
state <= state_trap;
end if;
if datain(7 downto 0) = "00000101" then -- reset
if pswmf(15 downto 14) = "00" then
initcycles <= 7; -- not as long as the original specs say, but just a bit more than a single cycle
state <= state_init;
else
state <= state_ifetch; -- reset is a no-op when not in kernel mode
end if;
end if;
if have_rtt = 1 and datain(7 downto 0) = "00000110" then -- rtt
state <= state_rti;
rbus_ix <= "110";
ir_rtt <= '1';
end if;
--
-- mfpt : the opcode 000007 is used by some diagnostics, including at least fkaa, 11/34 basic inst tst, to trigger an illegal instruction trap
-- also, obviously it should work differently for the appropriate models
--
if datain(7 downto 0) = "00000111" then -- mfpt
if modelcode = 21 then
state <= state_ifetch;
rbus_waddr <= pswmf(15 downto 14) & pswmf(11) & "000";
rbus_d <= '0' & o"00004"; -- 4 = T-11
rbus_we <= '1';
end if;
if modelcode = 23 or modelcode = 24 then
state <= state_ifetch;
rbus_waddr <= pswmf(15 downto 14) & pswmf(11) & "000";
rbus_d <= '0' & o"00003"; -- 3 = F-11
rbus_we <= '1';
end if;
if modelcode = 44 then
state <= state_ifetch;
rbus_waddr <= pswmf(15 downto 14) & pswmf(11) & "000";
rbus_d <= '0' & o"00001"; -- 1 = 11/44
rbus_we <= '1';
end if;
if modelcode = 73
or modelcode = 53
or modelcode = 83
or modelcode = 84
or modelcode = 93
or modelcode = 94
then
state <= state_ifetch;
rbus_waddr <= pswmf(15 downto 14) & pswmf(11) & "000";
rbus_d <= '0' & o"00005"; -- 5 = J11
rbus_we <= '1';
end if;
end if;
if datain(7 downto 3) = "10000" then -- rts
state <= state_rts;
rbus_ix <= "110";
end if;
if have_spl = 1 and datain(7 downto 3) = "10011" then -- spl
if pswmf(15 downto 14) = "00" then
psw(7 downto 5) <= datain(2 downto 0);
end if;
state <= state_ifetch;
end if;
if datain(7 downto 4) = "1010" then -- clear cc
psw(3 downto 0) <= psw(3 downto 0) and (not datain(3 downto 0));
state <= state_ifetch;
end if;
if datain(7 downto 4) = "1011" then -- set cc
psw(3 downto 0) <= psw(3 downto 0) or datain(3 downto 0);
state <= state_ifetch;
end if;
else -- branch group
-- the branch insns used to have a separate state to actually do the branch, including calculating the effective address
-- this variant, however notationally inelegant, uses less logic, and less cycles as well.
state <= state_ifetch;
case datain(15) & datain(10 downto 8) is
when "0001" => -- br
r7 <= r7p2 + (datain(7) & datain(7) & datain(7) & datain(7) & datain(7) & datain(7) & datain(7) & datain(7 downto 0) & '0');
when "0010" => -- bne
if psw(2) = '0' then
r7 <= r7p2 + (datain(7) & datain(7) & datain(7) & datain(7) & datain(7) & datain(7) & datain(7) & datain(7 downto 0) & '0');
end if;
when "0011" => -- beq
if psw(2) = '1' then
r7 <= r7p2 + (datain(7) & datain(7) & datain(7) & datain(7) & datain(7) & datain(7) & datain(7) & datain(7 downto 0) & '0');
end if;
when "0100" => -- bge
if psw(3) = psw(1) then
r7 <= r7p2 + (datain(7) & datain(7) & datain(7) & datain(7) & datain(7) & datain(7) & datain(7) & datain(7 downto 0) & '0');
end if;
when "0101" => -- blt
if psw(3) /= psw(1) then
r7 <= r7p2 + (datain(7) & datain(7) & datain(7) & datain(7) & datain(7) & datain(7) & datain(7) & datain(7 downto 0) & '0');
end if;
when "0110" => -- bgt
if psw(2) = '0' and psw(3) = psw(1) then
r7 <= r7p2 + (datain(7) & datain(7) & datain(7) & datain(7) & datain(7) & datain(7) & datain(7) & datain(7 downto 0) & '0');
end if;
when "0111" => -- ble
if psw(2) = '1' or psw(3) /= psw(1) then
r7 <= r7p2 + (datain(7) & datain(7) & datain(7) & datain(7) & datain(7) & datain(7) & datain(7) & datain(7 downto 0) & '0');
end if;
when "1000" => -- bpl
if psw(3) = '0' then
r7 <= r7p2 + (datain(7) & datain(7) & datain(7) & datain(7) & datain(7) & datain(7) & datain(7) & datain(7 downto 0) & '0');
end if;
when "1001" => -- bmi
if psw(3) = '1' then
r7 <= r7p2 + (datain(7) & datain(7) & datain(7) & datain(7) & datain(7) & datain(7) & datain(7) & datain(7 downto 0) & '0');
end if;
when "1010" => -- bhi
if psw(2) = '0' and psw(0) = '0' then
r7 <= r7p2 + (datain(7) & datain(7) & datain(7) & datain(7) & datain(7) & datain(7) & datain(7) & datain(7 downto 0) & '0');
end if;
when "1011" => -- blos
if psw(2) = '1' or psw(0) = '1' then
r7 <= r7p2 + (datain(7) & datain(7) & datain(7) & datain(7) & datain(7) & datain(7) & datain(7) & datain(7 downto 0) & '0');
end if;
when "1100" => -- bvc
if psw(1) = '0' then
r7 <= r7p2 + (datain(7) & datain(7) & datain(7) & datain(7) & datain(7) & datain(7) & datain(7) & datain(7 downto 0) & '0');
end if;
when "1101" => -- bvs
if psw(1) = '1' then
r7 <= r7p2 + (datain(7) & datain(7) & datain(7) & datain(7) & datain(7) & datain(7) & datain(7) & datain(7 downto 0) & '0');
end if;
when "1110" => -- bhis
if psw(0) = '0' then
r7 <= r7p2 + (datain(7) & datain(7) & datain(7) & datain(7) & datain(7) & datain(7) & datain(7) & datain(7 downto 0) & '0');
end if;
when "1111" => -- blo
if psw(0) = '1' then
r7 <= r7p2 + (datain(7) & datain(7) & datain(7) & datain(7) & datain(7) & datain(7) & datain(7) & datain(7 downto 0) & '0');
end if;
when others =>
null;
end case;
end if;
end if;
if datain(15 downto 9) = "1000100" then -- trap, emt etc
if datain(8) = '0' then
trap_vector <= o"030"; -- emt, vector = 030
else
trap_vector <= o"034"; -- trap, vector = 034
end if;
state <= state_trap;
end if;
if have_sob = 1 and datain(15 downto 9) = "0111111" then -- sob
rbus_ix <= datain(8 downto 6);
state <= state_sob;
if have_sob_zkdjbug = 1 and (modelcode = 73 or modelcode = 83 or modelcode = 84 or modelcode = 93 or modelcode = 94) then
sob_slowdown <= 255;
end if;
end if;
if have_mark = 1 and datain(15 downto 6) = "0000110100" then -- mark
rbus_waddr <= pswmf(15 downto 14) & "0110";
rbus_d <= unsigned(r7p2) + unsigned(datain(5 downto 0) & '0');
rbus_we <= '1';
rbus_ix <= "101";
state <= state_mark;
end if;
if have_fpu = 1 and datain(15 downto 6) = "1111000000" then -- fp11 operate group
case datain(5 downto 0) is
when "000000" => -- cfcc
psw(3 downto 0) <= fps(3 downto 0);
state <= state_ifetch;
when "000001" => -- setf
fps(7) <= '0';
state <= state_ifetch;
when "000010" => -- seti
fps(6) <= '0';
state <= state_ifetch;
when "001001" => -- setd
fps(7) <= '1';
state <= state_ifetch;
when "001010" => -- setl
fps(6) <= '1';
state <= state_ifetch;
when others =>
if modelcode = 45 or modelcode = 50 or modelcode = 55 or modelcode = 70 then
if datain(5 downto 3) = "000" then
state <= state_ifetch; -- allow 45/55/70 specific insns ldub, ldsc, stao, mrs, stq0 not to cause a trap
else
fec <= "0010"; -- unknown insn, start trap seq
state <= state_fptrap;
end if;
else
fec <= "0010"; -- unknown insn, start trap seq
state <= state_fptrap;
end if;
end case;
end if;
--
-- illegal op : used for both catching unknown opcodes and for illegal operands to jmp and jsr, also tstset/wrtlck
--
when state_illegalop =>
--
-- vector for illegal operand, register mode jmp or jsr
-- manuals seem to incorrectly list what vector should be used; systems use either 004 or 010.
-- for instance, EK-DCJ11-UG-PRE_J11ug_Oct83.pdf pg. C-7 item 5
-- however, diagnostics reveal the following:
-- 11/34 - 004, source AC-8045D-MC_CFKABD0-1134-Traps-Tst_Apr77.pdf
-- 11/44 - 010, confirmed by running kkab
-- 11/45 - 010, source PDP1145_Handbook_1973.pdf, pg. 230
-- J11 - 010, source 0095_CZKDJB0_KDJ11.pdf, seq 166/K13
--
if have_fpu = 1 and ir(15 downto 12) = "1111" then
fec <= "0010";
state <= state_fptrap;
elsif ir_jmp = '1' or ir_jsr = '1' then
if modelcode = 34
or modelcode = 4 -- verified 04 behaviour by running gkab
then
trap_vector <= o"004";
else
trap_vector <= o"010";
end if;
state <= state_trap;
else
trap_vector <= o"010"; -- illegal op, vector = 010
state <= state_trap;
end if;
--
-- jmp : move dest addr as computed into r7
--
when state_jmp =>
r7 <= dest_addr;
state <= state_ifetch;
--
-- npg : non-processor grant, ie. allow the bus to another bus master while the npr signal is active
--
when state_npg =>
if npr = '0' then
state <= state_ifetch;
npg <= '0';
else
npg <= '1';
end if;
--
-- mmuabort : the mmu requests an abort of the current instruction, potentially halfway trough an instruction
--
when state_mmuabort =>
if have_psw1512 = 1 and mmuabort = '0' then
ack_mmuabort <= '0';
trap_vector <= o"250"; -- mmu, vector = 250
state <= state_trap;
end if;
--
-- mmutrap : the mmu has requested a trap after the current instruction has finished; this trap will now be initiated
--
when state_mmutrap =>
if have_psw1512 = 1 and mmutrap = '0' then
ack_mmutrap <= '0';
trap_vector <= o"250"; -- mmu, vector = 250
state <= state_trap;
end if;
-- bus request aka interrupt, prio level 7; handle br7/bg7 signals and initiate trap
when state_br7 =>
if br7 = '0' then
bg7 <= '0';
trap_vector <= int_vector7;
state <= state_trap;
if modelcode = 45 or modelcode = 50 or modelcode = 55
or modelcode = 70 then
sr2 <= "0000000" & int_vector7; -- set trap vector in sr2
sr0_ic <= '0'; -- make sure to flag instruction not complete
end if;
end if;
-- bus request, prio level 6; handle br6/bg6 signals and initiate trap
when state_br6 =>
if br6 = '0' then
bg6 <= '0';
trap_vector <= int_vector6;
state <= state_trap;
if modelcode = 45 or modelcode = 50 or modelcode = 55
or modelcode = 70 then
sr2 <= "0000000" & int_vector6; -- set trap vector in sr2
sr0_ic <= '0'; -- make sure to flag instruction not complete
end if;
end if;
-- bus request, prio level 5; handle br5/bg5 signals and initiate trap
when state_br5 =>
if br5 = '0' then
bg5 <= '0';
trap_vector <= int_vector5;
state <= state_trap;
if modelcode = 45 or modelcode = 50 or modelcode = 55
or modelcode = 70 then
sr2 <= "0000000" & int_vector5; -- set trap vector in sr2
sr0_ic <= '0'; -- make sure to flag instruction not complete
end if;
end if;
-- bus request, prio level 4; handle br4/bg4 signals and initiate trap
when state_br4 =>
if br4 = '0' then
bg4 <= '0';
trap_vector <= int_vector4;
state <= state_trap;
if modelcode = 45 or modelcode = 50 or modelcode = 55
or modelcode = 70 then
sr2 <= "0000000" & int_vector4; -- set trap vector in sr2
sr0_ic <= '0'; -- make sure to flag instruction not complete
end if;
end if;
-- floating point error trap : precursor state handles fid bit in fps and contents of fea, and pending conditions signalled by the floating point alu
when state_fptrap =>
if falu_pending_fic = '1' then -- note the order... if more than one bit is set, the order of precedence is v, u, c
fec <= "0110";
end if;
if falu_pending_fiu = '1' then
fec <= "1010";
end if;
if falu_pending_fiv = '1' then
fec <= "1000";
end if;
if falu_pending_divz = '1' then
fec <= "0100";
end if;
fea <= ir_addr;
fps(15) <= '1';
if fps(14) = '0' then
trap_vector <= o"244"; -- floating point trap, vector = 244
state <= state_trap;
else -- wait for pending interrupt flags to clear before continuing
if falu_pending_fic = '0' and falu_pending_fiu = '0' and falu_pending_fiv = '0' and falu_pending_divz = '0' then
state <= state_ifetch;
end if;
end if;
falu_pending_clear <= '1';
--
-- rsv: red stack trap
-- implemented by setting the kernel sp to 4, and then starting a trap
-- the trap states will then decrement the sp, and save psw and r7 in
-- the right locations.
-- this approach is not necessarily correct, but passes czkdjb0
-- and it is also as described in EK-KDJ1B-UG_KDJ11-B_Nov86.pdf
-- in chapter 1.3.2, page 1-10
-- this takes some extra attention when sequencing through the
-- trap code to select kernel sp, though. Need to ignore whatever
-- is set in loc. 6
--
-- some extra explanation is probably needed for the copying of
-- psw from temp_psw. The reason is as follows: a red trap by
-- definition is a result from an earlier trap gone wrong. In the
-- first step of a normal trap, the psw is copied into temp_psw.
-- State_rsv restores that original psw into the real psw - then
-- starts a new trap.
--
when state_rsv =>
if have_red = 1 then
psw <= temp_psw;
rbus_waddr <= "00" & "0110";
rbus_d <= x"0004";
rbus_we <= '1';
trap_vector <= o"004"; -- red stack trap, vector = 004
state <= state_trap;
end if;
-- trap: start a trap sequence, trap through trapf
when state_trap =>
temp_psw <= psw;
psw(15 downto 14) <= "00"; -- initial, we'll load the real mode to select the correct stack by in the next step
psw(13 downto 12) <= pswmf(15 downto 14);
rbus_cpu_mode <= "00"; -- force rbus cpu mode to 00 - this is output to the mmu to select the par/pdr set
state <= state_trapa;
when state_trapa =>
rbus_ix <= "110";
if have_red = 1 and red_stack_trap = '1' then
rbus_cpu_mode <= "00";
else
rbus_cpu_mode <= datain(15 downto 14);
end if;
psw(15 downto 14) <= datain(15 downto 14);
psw(11 downto 0) <= datain(11 downto 0);
state <= state_trapb;
when state_trapb =>
state <= state_trapc;
when state_trapc =>
if have_red = 1 and red_stack_trap = '1' then
rbus_waddr <= "00" & "0110";
else
rbus_waddr <= pswmf(15 downto 14) & "0110";
end if;
rbus_d <= rbus_data_m2;
rbus_we <= '1';
state <= state_trapw;
when state_trapw =>
state <= state_trapd;
when state_trapd =>
if have_red = 1 and red_stack_trap = '1' then
rbus_waddr <= "00" & "0110";
else
rbus_waddr <= pswmf(15 downto 14) & "0110";
end if;
rbus_d <= rbus_data_m2;
rbus_we <= '1';
state <= state_trape;
when state_trape =>
rbus_cpu_mode <= "00"; -- force rbus cpu mode to 00 - this is output to the mmu to select the par/pdr set
state <= state_trapf;
when state_trapf =>
r7 <= datain;
state <= state_ifetch;
-- rti: start a rti sequence, rti through rtib
when state_rti =>
state <= state_rtia;
rbus_waddr <= pswmf(15 downto 14) & "0110";
rbus_d <= rbus_data_p2;
rbus_we <= '1';
when state_rtia =>
state <= state_rtib;
r7 <= datain;
when state_rtib =>
state <= state_ifetch;
rbus_waddr <= pswmf(15 downto 14) & "0110";
rbus_d <= rbus_data_p2;
rbus_we <= '1';
if modelcode = 4 then -- FIXME, probably other models as well - 5, 10, 15, 20? 04 behaviour tested with gkab
psw_delayedupdate <= datain;
psw_delayedupdate_even <= '1';
psw_delayedupdate_odd <= '1';
else
psw(4 downto 0) <= datain(4 downto 0);
if pswmf(15 downto 14) = "00" then
psw(7 downto 5) <= datain(7 downto 5);
end if;
psw(10 downto 8) <= datain(10 downto 8);
if pswmf(15 downto 14) = "00" then
psw(15 downto 11) <= datain(15 downto 11);
else
psw(15 downto 11) <= datain(15 downto 11) or pswmf(15 downto 11);
end if;
end if;
-- csm : process csm insn
when state_csm =>
if have_csm = 1 and sr3csmenable = '1' and psw(15 downto 14) /= "00" then
temp_psw(15 downto 4) <= psw(15 downto 4);
temp_psw(3 downto 0) <= "0000";
psw(15 downto 14) <= "01";
psw(13 downto 12) <= psw(15 downto 14);
psw(4) <= '0';
rbus_ix <= "110";
rbus_cpu_mode <= psw(15 downto 14);
state <= state_csma;
else
state <= state_illegalop;
end if;
when state_csma =>
rbus_waddr <= "01" & "0110"; -- address super sp
rbus_d <= rbus_data;
rbus_we <= '1';
state <= state_csmb;
when state_csmb =>
rbus_cpu_mode <= "01";
state <= state_csmc;
when state_csmc => -- push temp_psw
rbus_waddr <= "01" & "0110";
rbus_d <= rbus_data_m2;
rbus_we <= '1';
state <= state_csmd;
when state_csmd =>
state <= state_csme;
when state_csme => -- push pc
rbus_waddr <= "01" & "0110";
rbus_d <= rbus_data_m2;
rbus_we <= '1';
state <= state_csmf;
when state_csmf =>
state <= state_csmg;
when state_csmg => -- push alu_output
rbus_waddr <= "01" & "0110";
rbus_d <= rbus_data_m2;
rbus_we <= '1';
state <= state_csmh;
when state_csmh =>
trap_vector <= o"010"; -- csm loads r7 from vector = 010, but from supervisor I-space
state <= state_csmi;
when state_csmi =>
r7 <= datain;
state <= state_ifetch;
-- sob: deal with sob instruction
when state_sob =>
if have_sob_zkdjbug = 1 and (modelcode = 73 or modelcode = 83 or modelcode = 84 or modelcode = 93 or modelcode = 94) then
if sob_slowdown = 0 then
rbus_waddr <= pswmf(15 downto 14) & pswmf(11) & ir(8 downto 6);
rbus_d <= rbus_data_m1;
rbus_we <= '1';
if rbus_data_m1 = "0000000000000000" then
state <= state_ifetch;
else
r7 <= r7 - (ir(5 downto 0) & '0');
state <= state_ifetch;
end if;
else
sob_slowdown <= sob_slowdown - 1;
end if;
else
rbus_waddr <= pswmf(15 downto 14) & pswmf(11) & ir(8 downto 6);
rbus_d <= rbus_data_m1;
rbus_we <= '1';
if rbus_data_m1 = "0000000000000000" then
state <= state_ifetch;
else
r7 <= r7 - (ir(5 downto 0) & '0');
state <= state_ifetch;
end if;
end if;
-- move from previous i/d
when state_mfp =>
rbus_ix <= "110";
state <= state_mfpa;
when state_mfpa =>
dest_addr <= addr;
state <= state_store_alu_p;
sr1_srcd <= sr1_m2; -- it is the dest, actually - but that field is already used
rbus_waddr <= psw(15 downto 14) & '0' & "110";
rbus_d <= rbus_data_m2;
rbus_we <= '1';
-- move to previous i/d
when state_mtp =>
sr1_srcd <= sr1_p2;
rbus_waddr <= psw(15 downto 14) & '0' & "110";
rbus_d <= rbus_data_p2;
rbus_we <= '1';
state <= state_mtpa;
when state_mtpa =>
alus_input <= datain;
rbus_ix <= ir(2 downto 0);
state <= psrcstate;
-- mtps insn - move to ps
when state_mtps =>
if have_mtps = 1 then
if psw(15 downto 14) = "00" then
psw(7 downto 5) <= alu_output(7 downto 5);
psw(3 downto 0) <= alu_output(3 downto 0);
else
psw(3 downto 0) <= alu_output(3 downto 0);
end if;
state <= state_ifetch;
end if;
-- double operand,register instruction states dopr through doprb
-- these are for the EIS instruction set, ie mul, div, ash, ashc, xor
-- dopr is a precursor state, used to pick up the second operand from
-- the register file
when state_dopr =>
rbus_ix <= ir(8 downto 6);
state <= state_dopra;
-- dopra: setup the eis_sequencer to handle microstates for the eis alu
-- and dispatch to the states needed for each insn; also setup to read
-- ternary operand from the register file
when state_dopra =>
alus_input <= rbus_data;
rbus_ix <= ir(8 downto 7) & '1';
if ir(11 downto 9) = "000" then
eis_sequencer <= "11111";
state <= state_mul;
elsif ir(11 downto 9) = "010" then
eis_sequencer <= "11111";
state <= state_ash;
elsif ir(11 downto 9) = "100" then
state <= state_xor;
else
state <= state_doprb;
end if;
-- doprb: read ternary operand from the rbus, setup the
-- eis_sequencer for div and ashc
when state_doprb =>
alut_input <= rbus_data;
if ir (11 downto 9) = "001" then
if ir(6) = '1' then -- illegal, R must be even acc. EK-KDJ1B-UG_KDJ11-B_Nov86.pdf, pg. 9-31, and PDP1145_Handbook_1973.pdf, pg. 71
state <= state_ifetch; -- FIXME, does it make sense to go back to ifetch from here if the ir was illegal?
psw(3 downto 0) <= "0010"; -- not sure if this makes sense, but CZKDJB0 won't pass without
else
eis_sequencer <= "10000";
state <= state_div;
end if;
elsif ir(11 downto 9) = "011" then
eis_sequencer <= "11111";
state <= state_ashc;
else
state <= state_illegalop; -- should not be possible
end if;
-- mul through mulb: handle mul insn
when state_mul =>
if eis_sequencer = "00001" then
state <= state_mula;
end if;
eis_sequencer <= eis_sequencer + 1;
when state_mula =>
if ir(8 downto 6) /= "111" then
rbus_waddr <= pswmf(15 downto 14) & pswmf(11) & ir(8 downto 6);
rbus_d <= eis_output;
rbus_we <= '1';
else
r7 <= eis_output;
end if;
state <= state_mulb;
when state_mulb =>
if ir(8 downto 7) /= "11" then
rbus_waddr <= pswmf(15 downto 14) & pswmf(11) & ir(8 downto 7) & '1';
rbus_d <= eis_output32;
rbus_we <= '1';
else
r7 <= eis_output32;
end if;
psw(3 downto 0) <= eis_psw;
state <= state_ifetch;
-- div through divb: handle div insn
when state_div =>
if eis_sequencer = "11111" then
state <= state_diva;
end if;
eis_sequencer <= eis_sequencer - 1;
when state_diva =>
if eis_psw(1 downto 0) = "00" then
if ir(8 downto 6) /= "111" then
rbus_waddr <= pswmf(15 downto 14) & pswmf(11) & ir(8 downto 6);
rbus_d <= eis_output;
rbus_we <= '1';
else
r7 <= eis_output;
end if;
end if;
state <= state_divb;
when state_divb =>
if eis_psw(1 downto 0) = "00" then
if ir(8 downto 7) /= "11" then
rbus_waddr <= pswmf(15 downto 14) & pswmf(11) & ir(8 downto 7) & '1';
rbus_d <= eis_output32;
rbus_we <= '1';
else
r7 <= eis_output32;
end if;
end if;
psw(3 downto 0) <= eis_psw;
state <= state_ifetch;
-- ash through ashb: handle ash insn
when state_ash =>
if eis_sequencer = "11111" then
eis_sequencer <= eis_sequencer + 1;
else
if eis_flag2 = '1' then
state <= state_ashb;
end if;
end if;
when state_ashb =>
if ir(8 downto 6) /= "111" then
rbus_waddr <= pswmf(15 downto 14) & pswmf(11) & ir(8 downto 6);
rbus_d <= eis_output;
rbus_we <= '1';
else
r7 <= eis_output;
end if;
psw(3 downto 0) <= eis_psw;
state <= state_ifetch;
-- ashc through ashe: handle ashc insn
when state_ashc =>
if eis_sequencer = "11111" then
eis_sequencer <= eis_sequencer + 1;
else
if eis_flag2 = '1' then
state <= state_ashd;
end if;
end if;
when state_ashd =>
if ir(8 downto 6) /= "111" then
rbus_waddr <= pswmf(15 downto 14) & pswmf(11) & ir(8 downto 6);
rbus_d <= eis_output;
rbus_we <= '1';
else
r7 <= eis_output;
end if;
state <= state_ashe;
when state_ashe =>
if ir(8 downto 7) /= "11" then
rbus_waddr <= pswmf(15 downto 14) & pswmf(11) & ir(8 downto 7) & '1';
rbus_d <= eis_output32;
rbus_we <= '1';
else
r7 <= eis_output32;
end if;
psw(3 downto 0) <= eis_psw;
state <= state_ifetch;
-- xor: dispatch to state that stores result
when state_xor =>
if ir(5 downto 3) = "000" then
state <= state_store_alu_r;
else
state <= state_store_alu_p;
end if;
-- ldfps - load fpu state
when state_ldfps =>
fps <= alu_output;
state <= state_ifetch;
-- stst - store fpu fec and fea
when state_stststore =>
state <= state_ifetch;
-- dispatch insn in the fpso2 group - unless the insn is a clr(f|d), go into the
-- states that read an fp src operand
when state_fpso2 =>
addr_indirect <= dest_addr;
if ir(5 downto 3) /= "000" then
if ir(7 downto 6) = "00" then -- clr(f|d)
state <= state_fprun; -- don't need to read for clear
else
state <= state_fpr1;
end if;
else
falu_input <= fbus_o; -- fbus read already done in ifetch for mode 0
state <= state_fprun;
end if;
-- dispatch insn groups for the fp acc and operand format, in
-- all forms - fsrc, fsdt, src, dst, as signalled by the main
-- state machine - and cycle into the appropriate state to
-- handle the core accesses that are required to load the
-- operands, either in f|d, or i|l format.
when state_fpao =>
if ir(5 downto 3) /= "000" then
addr_indirect <= dest_addr;
if ir_facfsrc = '1' then
fbus_raddr <= '0' & ir(7 downto 6);
state <= state_fpr1;
elsif ir_facfdst = '1' then
falu_input <= fbus_o;
state <= state_fprun;
elsif ir_facdst = '1' then
falu_input <= fbus_o;
state <= state_fprun;
elsif ir_facsrc = '1' then
falu_input <= fbus_o;
state <= state_fpir1;
else
-- FIXME, go into some cpu error state?
end if;
else -- mode 0, so input from register!!!
if ir_facfsrc = '1' then
falu_input <= fbus_o;
fbus_raddr <= '0' & ir(7 downto 6);
state <= state_fprun;
elsif ir_facfdst = '1' then
falu_input <= fbus_o;
state <= state_fprun;
elsif ir_facdst = '1' then
falu_input <= fbus_o;
state <= state_fprun;
elsif ir_facsrc = '1' then
if ir(8) = '1' then -- ldexp
falu_input <= fbus_o;
falus_input(55 downto 40) <= rbus_data;
else -- ldc(i|l)(f|d)
falu_input(55 downto 40) <= "0000000000000000";
falu_input(39 downto 24) <= rbus_data;
falu_input(23 downto 0) <= "000000000000000000000000";
end if;
state <= state_fprun; -- FIXME, what about long data?
end if;
end if;
when state_fpir1 =>
if ir(8) = '1' then -- state is reachable only for ldexp and ldc(i|l)(f|d); ir(8) = 1 means ldexp
state <= state_fprun; -- ldexp
falus_input(55 downto 40) <= datain; -- FIXME, it does not really make sense to put the input value here?
else
falu_input(23 downto 0) <= "000000000000000000000000";
if fps(6) = '1' and ir(5 downto 0) /= "010111" then -- ldc(i|l)(f|d) mode 2, reg 7 : then only 1 word to be read
falu_input(55 downto 40) <= datain;
addr_indirect <= addr_indirect + 2;
state <= state_fpir2;
else
falu_input(55 downto 40) <= "0000000000000000";
falu_input(39 downto 24) <= datain;
state <= state_fprun;
end if;
end if;
when state_fpir2 =>
falu_input(39 downto 24) <= datain;
state <= state_fprun;
when state_fpr1 =>
if datain(15 downto 7) = "100000000" and fps(11) = '1' and fps(14) = '0' then -- do we need to trigger the fiuv trap for -0, undefined variable?
state <= state_fptrap; -- cause trap
fps(15) <= '1'; -- set error flag
fec <= "1100"; -- fiuv code
else
if datain(15 downto 7) = "100000000" and fps(11) = '1' then -- if interrupts are disabled, we still signal the error... FIXME, is this required at all?
fps(15) <= '1'; -- set error flag
fec <= "1100"; -- fiuv code
end if;
falu_input(63 downto 48) <= datain;
addr_indirect <= addr_indirect + 2;
if ir(5 downto 0) = "010111" then -- mode 2, reg 7 : then only 1 word to be loaded
falu_input(47 downto 0) <= "000000000000000000000000000000000000000000000000";
state <= state_fprun;
else
state <= state_fpr2;
end if;
end if;
when state_fpr2 =>
falu_input(47 downto 32) <= datain;
if fps(7) = '1' -- if mode is d
or (fps(7) = '0' and ir(11 downto 8) = "1111") -- or if mode is f, and the insn is ldcfd
then -- then we need to read the next two words
state <= state_fpr3;
addr_indirect <= addr_indirect + 2;
else
falu_input(31 downto 0) <= "00000000000000000000000000000000"; -- if mode is f, insn is not ldcfd, zero out the low 32 bits of the input
state <= state_fprun;
end if;
when state_fpr3 =>
falu_input(31 downto 16) <= datain;
addr_indirect <= addr_indirect + 2;
state <= state_fpr4;
when state_fpr4 =>
falu_input(15 downto 0) <= datain;
state <= state_fprun;
when state_fpwr =>
fbus_d <= falu_output;
fps(4) <= '0'; -- this appears to be needed to pass zkdl; always setting the bit to zero makes one of the other tests complain.
fps(3 downto 0) <= falu_fps;
fbus_waddr <= '0' & ir(7 downto 6);
fbus_we <= '1';
state <= state_ifetch;
if ir(11 downto 8) = "0011" and ir(6) = '0' then -- mod with even ac, need to store ac+1
state <= state_fpwr1;
end if;
when state_fpwr1 =>
state <= state_fpwr2;
when state_fpwr2 =>
fbus_d <= falu_output2;
fbus_waddr <= '0' & ir(7) & '1';
fbus_we <= '1';
state <= state_ifetch;
when state_fpd0 =>
fps(4) <= '0'; -- this appears to be needed to pass zkdl; always setting the bit to zero makes one of the other tests complain.
fps(3 downto 0) <= falu_fps;
if ir_fpsop2 = '1' and ir(7 downto 6) = "01" then -- tst(f/d)
state <= state_ifetch;
elsif ir(2 downto 1) /= "11" then
fbus_d <= falu_output;
fbus_waddr <= ir(2 downto 0);
fbus_we <= '1';
end if;
state <= state_ifetch;
when state_fpiwr =>
if ir(2 downto 0) /= "111" then
rbus_waddr <= pswmf(15 downto 14) & pswmf(11) & ir(2 downto 0);
rbus_d <= falu_output(63 downto 48);
rbus_we <= '1';
else
r7 <= falu_output(63 downto 48); -- FIXME, check what real pdp's do?
end if;
fps(4) <= '0'; -- this appears to be needed to pass zkdl; always setting the bit to zero makes one of the other tests complain.
fps(3 downto 0) <= falu_fps;
psw(3 downto 0) <= falu_fps;
state <= state_ifetch;
when state_fpiww =>
addr_indirect <= dest_addr;
fps(4) <= '0'; -- this appears to be needed to pass zkdl; always setting the bit to zero makes one of the other tests complain.
fps(3 downto 0) <= falu_fps;
psw(3 downto 0) <= falu_fps;
state <= state_fpiw1;
when state_fpiw1 =>
if ir(5 downto 0) = "010111" -- stc(f|d)(i|l) mode 2, reg 7 : then only 1 word to be written
or fps(6) = '0' -- stc(f|d)(i|l), short integer mode
or ir(11 downto 8) = "1010" -- stexp insn
then
state <= state_ifetch;
else
addr_indirect <= addr_indirect + 2;
state <= state_fpiw2;
end if;
when state_fpiw2 =>
state <= state_ifetch;
when state_fpww =>
addr_indirect <= dest_addr;
fps(4) <= '0'; -- this appears to be needed to pass zkdl; always setting the bit to zero makes one of the other tests complain.
fps(3 downto 0) <= falu_fps;
if ir_fpsop2 = '1' and ir(7 downto 6) = "01" then -- tst(f/d)
state <= state_ifetch;
else
state <= state_fpw1;
end if;
when state_fpw1 =>
if ir(5 downto 0) = "010111" then -- mode 2, reg 7 : then only 1 word to be written
state <= state_ifetch;
else
addr_indirect <= addr_indirect + 2;
state <= state_fpw2;
end if;
when state_fpw2 =>
if (fps(7) = '1' and ir(11 downto 8) /= "1100") -- reverse sense of fps D bit when insn is stc(f|d)(d|f)
or (fps(7) = '0' and ir(11 downto 8) = "1100")
then
state <= state_fpw3;
addr_indirect <= addr_indirect + 2;
else
state <= state_ifetch;
end if;
when state_fpw3 =>
addr_indirect <= addr_indirect + 2;
state <= state_fpw4;
when state_fpw4 =>
state <= state_ifetch;
when state_fprun =>
if ir_fpao = '1' then
if ir_facfsrc = '1' then
falus_input <= fbus_o;
end if;
state <= state_fprunao;
falu_load <= '1';
falu_state <= 0;
elsif ir_fpsop2 = '1' then
if ir(5 downto 3) = "000" then
state <= state_fpd0;
else
state <= state_fpww;
end if;
else
state <= state_ifetch; -- FIXME, needed?
end if;
when state_fprunao =>
falu_state <= falu_state + 1;
falu_load <= '0';
if falu_state > 160 then -- FIXME, this may prevent hangs. Why?
state <= state_ifetch; -- FIXME, error!
end if;
if falu_done = '1' then
falu_state <= 0;
case ir(11 downto 8) is
when "1000" => -- st(f|d)
if ir(5 downto 3) = "000" then
state <= state_fpd0;
else
state <= state_fpww;
end if;
when "1010" => -- stexp
if ir(5 downto 3) = "000" then
state <= state_fpiwr;
else
state <= state_fpiww;
end if;
when "1011" => -- stc(f|d)(i|l)
if ir(5 downto 3) = "000" then
state <= state_fpiwr;
else
state <= state_fpiww;
end if;
when "1100" => -- stc(f|d)(d|f)
fbus_fd <= '1'; -- enable full access to fp register bank
if ir(5 downto 3) = "000" then
state <= state_fpd0;
else
state <= state_fpww;
end if;
when "1111" => -- ldc(d|f)(f|d)
fbus_fd <= '1'; -- enable full access to fp register bank
state <= state_fpwr;
when others =>
state <= state_fpwr;
end case;
end if;
when state_tstset =>
rbus_waddr <= pswmf(15 downto 14) & pswmf(11) & "000";
rbus_d <= alu_input;
rbus_we <= '1';
state <= state_store_alu_p;
when state_wrtlck =>
rbus_ix <= "000";
state <= state_wrtlcka;
when state_wrtlcka =>
alu_input <= rbus_data;
state <= state_store_alu_p;
when state_mark =>
r7 <= rbus_data;
rbus_ix <= "110";
state <= state_marka;
when state_marka =>
rbus_waddr <= pswmf(15 downto 14) & pswmf(11) & "110";
rbus_d <= rbus_data_p2;
rbus_we <= '1';
state <= state_markb;
when state_markb =>
rbus_waddr <= pswmf(15 downto 14) & pswmf(11) & "101";
rbus_d <= datain;
rbus_we <= '1';
state <= state_ifetch;
when state_jsr =>
rbus_ix <= "110";
state <= state_jsra;
when state_jsra =>
addr_indirect <= rbus_data_m2;
rbus_waddr <= pswmf(15 downto 14) & "0110";
rbus_d <= rbus_data_m2;
rbus_we <= '1';
sr1_srcd <= sr1_m2;
rbus_ix <= ir(8 downto 6);
state <= state_jsrb;
when state_jsrb =>
state <= state_jsrc;
when state_jsrc =>
if ir(8 downto 6) /= "111" then
rbus_waddr <= pswmf(15 downto 14) & pswmf(11) & ir(8 downto 6);
rbus_d <= r7;
rbus_we <= '1';
end if;
r7 <= dest_addr;
state <= state_ifetch;
when state_rts =>
addr_indirect <= rbus_data;
if ir(2 downto 0) /= "110" then -- the r6 special case; it is not really necessary to increment sp here, since it will be loaded in the next step. Does not harm either.
rbus_waddr <= pswmf(15 downto 14) & "0110";
rbus_d <= rbus_data_p2;
rbus_we <= '1';
-- sr1_dstd <= sr1_p2; -- simh doesn't
end if;
rbus_ix <= ir(2 downto 0);
state <= state_rtsa;
when state_rtsa =>
if ir(2 downto 0) /= "111" then
r7 <= rbus_data;
rbus_waddr <= pswmf(15 downto 14) & pswmf(11) & ir(2 downto 0);
rbus_d <= datain;
rbus_we <= '1';
else
r7 <= datain;
end if;
state <= state_ifetch;
when state_dst0 =>
alu_input <= rbus_data;
state <= pdststate;
rbus_cpu_mode <= pswmf(15 downto 14); -- may have been set temporarily to handle mode 0 r6 for mfp(i|d)
when state_src0 =>
-- handle issue 3 in programming differences list
if ir_dop = '1' and ir(8 downto 6) = "111"
and (ir(5 downto 4) = "11")
and (
modelcode = 15 or modelcode = 20 or modelcode = 35 or modelcode = 40
or modelcode = 53
or modelcode = 73 or modelcode = 83 or modelcode = 84 or modelcode = 93 or modelcode = 94
)
then
alus_input <= rbus_data_p2;
state <= psrcstate;
rbus_ix <= ir(2 downto 0);
else
alus_input <= rbus_data;
state <= psrcstate;
rbus_ix <= ir(2 downto 0);
end if;
when state_dst1 =>
dest_addr <= addr;
alu_input <= datain;
state <= pdststate;
when state_src1 =>
alus_input <= datain;
state <= psrcstate;
rbus_ix <= ir(2 downto 0);
when state_dst2 =>
dest_addr <= addr;
alu_input <= datain;
state <= pdststate;
sr1_dstd <= sr1_pv;
if ir(2 downto 0) /= "111" then
rbus_waddr <= pswmf(15 downto 14) & pswmf(11) & ir(2 downto 0);
rbus_d <= rbus_data_pv;
rbus_we <= '1';
else
r7 <= rbus_data_p2;
end if;
when state_src2 =>
alus_input <= datain;
if ir_dop = '1' and ir(8 downto 6) = ir(2 downto 0) and ir(2 downto 0) /= "111" then
state <= state_src2w;
else
state <= psrcstate;
end if;
rbus_ix <= ir(2 downto 0);
sr1_srcd <= sr1_pv;
if ir(8 downto 6) /= "111" then
rbus_waddr <= pswmf(15 downto 14) & pswmf(11) & ir(8 downto 6);
rbus_d <= rbus_data_pv;
rbus_we <= '1';
else
r7 <= rbus_data_p2;
end if;
when state_src2w =>
state <= psrcstate;
when state_dst3 =>
addr_indirect <= datain;
sr1_dstd <= sr1_p2;
if ir(2 downto 0) /= "111" then
rbus_waddr <= pswmf(15 downto 14) & pswmf(11) & ir(2 downto 0);
rbus_d <= rbus_data_p2;
rbus_we <= '1';
else
r7 <= rbus_data_p2;
end if;
state <= state_dst3a;
when state_dst3a =>
dest_addr <= addr;
alu_input <= datain;
state <= pdststate;
when state_src3 =>
addr_indirect <= datain;
rbus_ix <= ir(2 downto 0);
sr1_srcd <= sr1_p2;
if ir(8 downto 6) /= "111" then
rbus_waddr <= pswmf(15 downto 14) & pswmf(11) & ir(8 downto 6);
rbus_d <= rbus_data_p2;
rbus_we <= '1';
else
r7 <= rbus_data_p2;
end if;
state <= state_src3a;
when state_src3a =>
alus_input <= datain;
state <= psrcstate;
when state_dst4 =>
dest_addr <= addr;
alu_input <= datain;
state <= pdststate;
sr1_dstd <= sr1_mv;
if ir(2 downto 0) /= "111" then
rbus_waddr <= pswmf(15 downto 14) & pswmf(11) & ir(2 downto 0);
rbus_d <= rbus_data_mv;
rbus_we <= '1';
else
r7 <= rbus_data_m2; -- FIXME, where does this even begin to make sense - it would effectively jump to the same insn?
end if;
when state_src4 =>
alus_input <= datain;
if ir_dop = '1' and ir(8 downto 6) = ir(2 downto 0) and ir(2 downto 0) /= "111" then
state <= state_src4w;
else
state <= psrcstate;
end if;
rbus_ix <= ir(2 downto 0);
sr1_srcd <= sr1_mv;
if ir(8 downto 6) /= "111" then
rbus_waddr <= pswmf(15 downto 14) & pswmf(11) & ir(8 downto 6);
rbus_d <= rbus_data_mv;
rbus_we <= '1';
else
r7 <= rbus_data_m2;
end if;
when state_src4w =>
state <= psrcstate;
when state_dst5 =>
addr_indirect <= datain;
sr1_dstd <= sr1_m2;
if ir(2 downto 0) /= "111" then
rbus_waddr <= pswmf(15 downto 14) & pswmf(11) & ir(2 downto 0);
rbus_d <= rbus_data_m2;
rbus_we <= '1';
else
r7 <= rbus_data_m2;
end if;
state <= state_dst5a;
when state_dst5a =>
dest_addr <= addr;
alu_input <= datain;
state <= pdststate;
when state_src5 =>
addr_indirect <= datain;
rbus_ix <= ir(2 downto 0);
sr1_srcd <= sr1_m2;
if ir(8 downto 6) /= "111" then
rbus_waddr <= pswmf(15 downto 14) & pswmf(11) & ir(8 downto 6);
rbus_d <= rbus_data_m2;
rbus_we <= '1';
else
r7 <= rbus_data_m2;
end if;
state <= state_src5a;
when state_src5a =>
alus_input <= datain;
state <= psrcstate;
when state_dst6 =>
r7 <= r7p2;
if ir(2 downto 0) = "111" then
addr_indirect <= unsigned(datain) + unsigned(rbus_data_p2);
else
addr_indirect <= unsigned(datain) + unsigned(rbus_data);
end if;
state <= state_dst6a;
when state_dst6a =>
dest_addr <= addr;
alu_input <= datain;
state <= pdststate;
when state_src6 =>
r7 <= r7p2;
if ir(8 downto 6) = "111" then
addr_indirect <= unsigned(datain) + unsigned(rbus_data_p2);
else
addr_indirect <= unsigned(datain) + unsigned(rbus_data);
end if;
state <= state_src6a;
when state_src6a =>
alus_input <= datain;
state <= psrcstate;
rbus_ix <= ir(2 downto 0);
when state_dst7 =>
r7 <= r7p2;
if ir(2 downto 0) = "111" then
addr_indirect <= unsigned(datain) + unsigned(rbus_data_p2);
else
addr_indirect <= unsigned(datain) + unsigned(rbus_data);
end if;
state <= state_dst7a;
when state_dst7a =>
addr_indirect <= datain;
state <= state_dst7b;
when state_dst7b =>
dest_addr <= addr;
alu_input <= datain;
state <= pdststate;
rbus_ix <= "110";
when state_src7 =>
r7 <= r7p2;
if ir(8 downto 6) = "111" then
addr_indirect <= unsigned(datain) + unsigned(rbus_data_p2);
else
addr_indirect <= unsigned(datain) + unsigned(rbus_data);
end if;
state <= state_src7a;
when state_src7a =>
addr_indirect <= datain;
state <= state_src7b;
when state_src7b =>
alus_input <= datain;
state <= psrcstate;
rbus_ix <= ir(2 downto 0);
when state_store_alu_p =>
state <= state_store_alu_w;
when state_store_alu_w =>
psw(3 downto 0) <= alu_psw;
if psw_in_we_even = '1' then -- direct write into 777776 overrides psw setting from alu
if have_pswimmediateupdate = 1 then
psw(7 downto 5) <= psw_in(7 downto 5); -- T bit can only be set with RTI/RTT instruction
psw(3 downto 0) <= psw_in(3 downto 0);
else
psw_delayedupdate_even <= '1';
psw_delayedupdate(7 downto 0) <= psw_in(7 downto 0);
end if;
end if;
if psw_in_we_odd = '1' then
if have_pswimmediateupdate = 1 then
psw(15 downto 8) <= psw_in(15 downto 8);
else
psw_delayedupdate_odd <= '1';
psw_delayedupdate(15 downto 8) <= psw_in(15 downto 8);
end if;
end if;
state <= state_ifetch;
if ir(15 downto 6) = "1111000011" then -- stst?
if ir(5 downto 0) /= "010111" then -- not if mode 2, r7 -- immediate
state <= state_stststore;
dest_addr <= dest_addr + 2;
end if;
end if;
when state_store_alu_r =>
if ir_store = '1' then
if ir(2 downto 0) /= "111" then
if ir_mtpi = '1' or ir_mtpd = '1' then
rbus_waddr <= pswmf(13 downto 12) & pswmf(11) & ir(2 downto 0);
else
rbus_waddr <= pswmf(15 downto 14) & pswmf(11) & ir(2 downto 0);
end if;
if ir(15 downto 12) = "1001" then -- movb? movb needs to sign extend if the result is moved to a register
rbus_d <= alu_output_signext;
elsif have_mtps = 1 and ir_mfps = '1' then -- mfps needs sign extend if the result is moved to a register
rbus_d <= alu_output_signext;
elsif ir_byte = '1' then
rbus_d <= alu_input(15 downto 8) & alu_output(7 downto 0);
else
rbus_d <= alu_output;
end if;
rbus_we <= '1';
else
r7 <= alu_output;
end if;
end if;
psw(3 downto 0) <= alu_psw;
state <= state_ifetch;
when others =>
null;
end case;
end if;
if nxmabort = '1' then
if modelcode = 34 -- FIXME, if this is disabled for these models, FKAB, KKAB will fail. However, if enabled for 45, unix v7 will fail during /etc/rc processing.
or modelcode = 44
or modelcode = 04
then
if state = state_src2 or state = state_src3 then
rbus_we <= '0';
sr1_srcd <= "00000";
end if;
if state = state_dst2 or state = state_dst3 then
rbus_we <= '0';
sr1_dstd <= "00000";
end if;
end if;
trap_vector <= o"004";
state <= state_trap;
end if;
if mmuabort = '1' and have_mmuimmediateabort = 0 then -- signal from mmu that an access caused an abort.
state <= state_mmuabort; -- precursor state for mmu abort
ack_mmuabort <= '1'; -- set acknowledge flag to mmu core
elsif oddabort = '1' and have_oddimmediateabort = 0 then -- odd abort signal
trap_vector <= o"004"; -- set vector
state <= state_trap; -- do trap
end if;
end if;
end if;
end process;
-- base instruction set alu
process(alu_input, alus_input, ir, psw(3 downto 0),
ir_sop, ir_dop, ir_mfpi, ir_csm, ir_mfpd, ir_mtpi, ir_mtpd, ir_mtps, ir_mfps, ir_dopr, ir_mpr, ir_fpsop1,
have_csm, have_mfp, have_mtps, have_xor, have_mpr, fps, fec,
modelcode)
variable result : std_logic_vector(15 downto 0);
variable result8 : std_logic_vector(7 downto 0);
begin
ir_byte <= '0';
ir_store <= '1';
if ir_sop = '1' then
case ir(15 downto 6) is
when "0000000011" => -- swab
result(15 downto 8) := alu_input(7 downto 0);
result(7 downto 0) := alu_input(15 downto 8);
alu_output <= result;
alu_psw(3) <= alu_input(15);
if alu_input(15 downto 8) = "00000000" then
alu_psw(2) <= '1';
else
alu_psw(2) <= '0';
end if;
if modelcode = 15 or modelcode = 20 then
alu_psw(1) <= psw(1);
else
alu_psw(1) <= '0';
end if;
alu_psw(0) <= '0';
when "0000101000" => -- clr
result := "0000000000000000";
alu_output <= result;
alu_psw(3 downto 0) <= "0100";
when "1000101000" => -- clrb
ir_byte <= '1';
result := "0000000000000000";
alu_output <= result;
alu_psw(3 downto 0) <= "0100";
when "0000101001" => -- com
result := not alu_input;
alu_output <= result;
alu_psw(3) <= not alu_input(15);
if not alu_input = "0000000000000000" then
alu_psw(2) <= '1';
else
alu_psw(2) <= '0';
end if;
alu_psw(1 downto 0) <= "01";
when "1000101001" => -- comb
ir_byte <= '1';
result := not alu_input;
alu_output <= result;
alu_psw(3) <= not alu_input(7);
if not alu_input(7 downto 0) = "00000000" then
alu_psw(2) <= '1';
else
alu_psw(2) <= '0';
end if;
alu_psw(1 downto 0) <= "01";
when "0000101010" => -- inc
result := alu_input + 1;
alu_output <= result;
alu_psw(3) <= result(15);
if result = "0000000000000000" then
alu_psw(2) <= '1';
else
alu_psw(2) <= '0';
end if;
if alu_input = "0111111111111111" then
alu_psw(1) <= '1';
else
alu_psw(1) <= '0';
end if;
alu_psw(0) <= psw(0);
when "1000101010" => -- incb
ir_byte <= '1';
result := alu_input + 1;
alu_output <= result;
alu_psw(3) <= result(7);
if result(7 downto 0) = "00000000" then
alu_psw(2) <= '1';
else
alu_psw(2) <= '0';
end if;
if alu_input(7 downto 0) = "01111111" then
alu_psw(1) <= '1';
else
alu_psw(1) <= '0';
end if;
alu_psw(0) <= psw(0);
when "0000101011" => -- dec
result := alu_input - 1;
alu_output <= result;
alu_psw(3) <= result(15);
if result = "0000000000000000" then
alu_psw(2) <= '1';
else
alu_psw(2) <= '0';
end if;
if alu_input = "1000000000000000" then
alu_psw(1) <= '1';
else
alu_psw(1) <= '0';
end if;
alu_psw(0) <= psw(0);
when "1000101011" => -- decb
ir_byte <= '1';
result := alu_input - 1;
alu_output <= result;
alu_psw(3) <= result(7);
if result(7 downto 0) = "00000000" then
alu_psw(2) <= '1';
else
alu_psw(2) <= '0';
end if;
if alu_input(7 downto 0) = "10000000" then
alu_psw(1) <= '1';
else
alu_psw(1) <= '0';
end if;
alu_psw(0) <= psw(0);
when "0000101100" => -- neg
result := (not alu_input) + 1;
alu_output <= result;
alu_psw(3) <= result(15);
if result = "0000000000000000" then
alu_psw(2) <= '1';
alu_psw(0) <= '0';
else
alu_psw(2) <= '0';
alu_psw(0) <= '1';
end if;
if result = "1000000000000000" then
alu_psw(1) <= '1';
else
alu_psw(1) <= '0';
end if;
when "1000101100" => -- negb
ir_byte <= '1';
result := (not alu_input) + 1;
alu_output <= result;
alu_psw(3) <= result(7);
if result(7 downto 0) = "00000000" then
alu_psw(2) <= '1';
alu_psw(0) <= '0';
else
alu_psw(2) <= '0';
alu_psw(0) <= '1';
end if;
if result(7 downto 0) = "10000000" then
alu_psw(1) <= '1';
else
alu_psw(1) <= '0';
end if;
when "0000101101" => -- adc
result := alu_input + psw(0);
alu_output <= result;
alu_psw(3) <= result(15);
if result = "0000000000000000" then
alu_psw(2) <= '1';
else
alu_psw(2) <= '0';
end if;
if alu_input = "0111111111111111" and psw(0) = '1' then
alu_psw(1) <= '1';
else
alu_psw(1) <= '0';
end if;
if alu_input = "1111111111111111" and psw(0) = '1' then
alu_psw(0) <= '1';
else
alu_psw(0) <= '0';
end if;
when "1000101101" => -- adcb
ir_byte <= '1';
result := alu_input + psw(0);
alu_output <= result;
alu_psw(3) <= result(7);
if result(7 downto 0) = "00000000" then
alu_psw(2) <= '1';
else
alu_psw(2) <= '0';
end if;
if alu_input(7 downto 0) = "01111111" and psw(0) = '1' then
alu_psw(1) <= '1';
else
alu_psw(1) <= '0';
end if;
if alu_input(7 downto 0) = "11111111" and psw(0) = '1' then
alu_psw(0) <= '1';
else
alu_psw(0) <= '0';
end if;
when "0000101110" => -- sbc
result := alu_input - psw(0);
alu_output <= result;
alu_psw(3) <= result(15);
if result = "0000000000000000" then
alu_psw(2) <= '1';
else
alu_psw(2) <= '0';
end if;
if alu_input = "1000000000000000" and psw(0) = '1' then
alu_psw(1) <= '1';
else
alu_psw(1) <= '0';
end if;
if alu_input = "0000000000000000" and psw(0) = '1' then
alu_psw(0) <= '1';
else
alu_psw(0) <= '0';
end if;
when "1000101110" => -- sbcb
ir_byte <= '1';
result := alu_input - psw(0);
alu_output <= result;
alu_psw(3) <= result(7);
if result(7 downto 0) = "00000000" then
alu_psw(2) <= '1';
else
alu_psw(2) <= '0';
end if;
if alu_input(7 downto 0) = "10000000" and psw(0) = '1' then
alu_psw(1) <= '1';
else
alu_psw(1) <= '0';
end if;
if alu_input(7 downto 0) = "00000000" and psw(0) = '1' then
alu_psw(0) <= '1';
else
alu_psw(0) <= '0';
end if;
when "0000101111" => -- tst
result := alu_input;
alu_output <= result;
ir_store <= '0';
alu_psw(3) <= result(15);
if result = "0000000000000000" then
alu_psw(2) <= '1';
else
alu_psw(2) <= '0';
end if;
alu_psw(1 downto 0) <= "00";
when "1000101111" => -- tstb
ir_byte <= '1';
result := alu_input;
alu_output <= result;
ir_store <= '0';
alu_psw(3) <= result(7);
if result(7 downto 0) = "00000000" then
alu_psw(2) <= '1';
else
alu_psw(2) <= '0';
end if;
alu_psw(1 downto 0) <= "00";
when "0000110000" => -- ror
result := psw(0) & alu_input(15 downto 1);
alu_output <= result;
alu_psw(3) <= result(15);
if result = "0000000000000000" then
alu_psw(2) <= '1';
else
alu_psw(2) <= '0';
end if;
alu_psw(1) <= alu_input(0) xor result(15);
alu_psw(0) <= alu_input(0);
when "1000110000" => -- rorb
ir_byte <= '1';
result8 := psw(0) & alu_input(7 downto 1);
alu_output(7 downto 0) <= result8;
alu_output(15 downto 8) <= "XXXXXXXX";
alu_psw(3) <= result8(7);
if result8 = "00000000" then
alu_psw(2) <= '1';
else
alu_psw(2) <= '0';
end if;
alu_psw(1) <= alu_input(0) xor result8(7);
alu_psw(0) <= alu_input(0);
when "0000110001" => -- rol
result := alu_input(14 downto 0) & psw(0);
alu_output <= result;
alu_psw(3) <= result(15);
if result = "0000000000000000" then
alu_psw(2) <= '1';
else
alu_psw(2) <= '0';
end if;
alu_psw(1) <= alu_input(15) xor result(15);
alu_psw(0) <= alu_input(15);
when "1000110001" => -- rolb
ir_byte <= '1';
result8 := alu_input(6 downto 0) & psw(0);
alu_output(7 downto 0) <= result8;
alu_output(15 downto 8) <= "XXXXXXXX";
alu_psw(3) <= result8(7);
if result8 = "00000000" then
alu_psw(2) <= '1';
else
alu_psw(2) <= '0';
end if;
alu_psw(1) <= alu_input(7) xor result8(7);
alu_psw(0) <= alu_input(7);
when "0000110010" => -- asr
result := alu_input(15) & alu_input(15 downto 1);
alu_output <= result;
alu_psw(3) <= result(15);
if result = "0000000000000000" then
alu_psw(2) <= '1';
else
alu_psw(2) <= '0';
end if;
alu_psw(1) <= alu_input(0) xor result(15);
alu_psw(0) <= alu_input(0);
when "1000110010" => -- asrb
ir_byte <= '1';
result8 := alu_input(7) & alu_input(7 downto 1);
alu_output(7 downto 0) <= result8;
alu_output(15 downto 8) <= "XXXXXXXX";
alu_psw(3) <= result8(7);
if result8 = "00000000" then
alu_psw(2) <= '1';
else
alu_psw(2) <= '0';
end if;
alu_psw(1) <= alu_input(0) xor result8(7);
alu_psw(0) <= alu_input(0);
when "0000110011" => -- asl
result := alu_input(14 downto 0) & '0';
alu_output <= result;
alu_psw(3) <= result(15);
if result = "0000000000000000" then
alu_psw(2) <= '1';
else
alu_psw(2) <= '0';
end if;
alu_psw(1) <= alu_input(15) xor result(15);
alu_psw(0) <= alu_input(15);
when "1000110011" => -- aslb
ir_byte <= '1';
result8 := alu_input(6 downto 0) & '0';
alu_output(7 downto 0) <= result8;
alu_output(15 downto 8) <= "XXXXXXXX";
alu_psw(3) <= result8(7);
if result8 = "00000000" then
alu_psw(2) <= '1';
else
alu_psw(2) <= '0';
end if;
alu_psw(1) <= alu_input(7) xor result8(7);
alu_psw(0) <= alu_input(7);
when "0000110111" => -- sxt
if psw(3) = '0' then
result := "0000000000000000";
alu_psw(2) <= '1';
else
result := "1111111111111111";
alu_psw(2) <= '0';
end if;
alu_output <= result;
alu_psw(3) <= psw(3);
alu_psw(1) <= '0';
alu_psw(0) <= psw(0);
when others =>
alu_output <= "XXXXXXXXXXXXXXXX";
alu_psw <= "XXXX";
end case;
elsif ir_dop = '1' then
case ir(15 downto 12) is
when "0001" => -- mov
result := alus_input;
alu_output <= result;
alu_psw(3) <= result(15);
if result = "0000000000000000" then
alu_psw(2) <= '1';
else
alu_psw(2) <= '0';
end if;
alu_psw(1) <= '0';
alu_psw(0) <= psw(0);
when "1001" => -- movb
ir_byte <= '1';
result := alus_input;
alu_output <= result;
alu_psw(3) <= result(7);
if result(7 downto 0) = "00000000" then
alu_psw(2) <= '1';
else
alu_psw(2) <= '0';
end if;
alu_psw(1) <= '0';
alu_psw(0) <= psw(0);
when "0010" => -- cmp
result := alus_input - alu_input;
alu_output <= alu_input;
ir_store <= '0';
alu_psw(3) <= result(15);
if result = "0000000000000000" then
alu_psw(2) <= '1';
else
alu_psw(2) <= '0';
end if;
if (alu_input(15) /= alus_input(15)) and (alus_input(15) /= result(15)) then
alu_psw(1) <= '1';
else
alu_psw(1) <= '0';
end if;
alu_psw(0) <= ((not alus_input(15)) and alu_input(15)) or ((not alus_input(15)) and result(15)) or (alu_input(15) and result(15));
when "1010" => -- cmpb
ir_byte <= '1';
result8 := alus_input(7 downto 0) - alu_input(7 downto 0);
alu_output <= alu_input;
ir_store <= '0';
alu_psw(3) <= result8(7);
if result8 = "00000000" then
alu_psw(2) <= '1';
else
alu_psw(2) <= '0';
end if;
if (alu_input(7) /= alus_input(7)) and (alus_input(7) /= result8(7)) then
alu_psw(1) <= '1';
else
alu_psw(1) <= '0';
end if;
alu_psw(0) <= ((not alus_input(7)) and alu_input(7)) or ((not alus_input(7)) and result8(7)) or (alu_input(7) and result8(7));
when "0011" => -- bit
result := alus_input and alu_input;
alu_output <= alu_input;
ir_store <= '0';
alu_psw(3) <= result(15);
if result = "0000000000000000" then
alu_psw(2) <= '1';
else
alu_psw(2) <= '0';
end if;
alu_psw(1) <= '0';
alu_psw(0) <= psw(0);
when "1011" => -- bitb
ir_byte <= '1';
result := alus_input and alu_input;
alu_output <= alu_input;
ir_store <= '0';
alu_psw(3) <= result(7);
if result(7 downto 0) = "00000000" then
alu_psw(2) <= '1';
else
alu_psw(2) <= '0';
end if;
alu_psw(1) <= '0';
alu_psw(0) <= psw(0);
when "0100" => -- bic
result := (not alus_input) and alu_input;
alu_output <= result;
alu_psw(3) <= result(15);
if result = "0000000000000000" then
alu_psw(2) <= '1';
else
alu_psw(2) <= '0';
end if;
alu_psw(1) <= '0';
alu_psw(0) <= psw(0);
when "1100" => -- bicb
ir_byte <= '1';
result := (not alus_input) and alu_input;
alu_output <= result;
alu_psw(3) <= result(7);
if result(7 downto 0) = "00000000" then
alu_psw(2) <= '1';
else
alu_psw(2) <= '0';
end if;
alu_psw(1) <= '0';
alu_psw(0) <= psw(0);
when "0101" => -- bis
result := alus_input or alu_input;
alu_output <= result;
alu_psw(3) <= result(15);
if result = "0000000000000000" then
alu_psw(2) <= '1';
else
alu_psw(2) <= '0';
end if;
alu_psw(1) <= '0';
alu_psw(0) <= psw(0);
when "1101" => -- bisb
ir_byte <= '1';
result := alus_input or alu_input;
alu_output <= result;
alu_psw(3) <= result(7);
if result(7 downto 0) = "00000000" then
alu_psw(2) <= '1';
else
alu_psw(2) <= '0';
end if;
alu_psw(1) <= '0';
alu_psw(0) <= psw(0);
when "0110" => -- add
result := alu_input + alus_input;
alu_output <= result;
alu_psw(3) <= result(15);
if result = "0000000000000000" then
alu_psw(2) <= '1';
else
alu_psw(2) <= '0';
end if;
if (alu_input(15) = alus_input(15)) and (alus_input(15) /= result(15)) then
alu_psw(1) <= '1';
else
alu_psw(1) <= '0';
end if;
alu_psw(0) <= (alu_input(15) and alus_input(15)) or (alu_input(15) and not result(15)) or (alus_input(15) and not result(15));
when "1110" => -- sub
result := alu_input - alus_input;
alu_output <= result;
alu_psw(3) <= result(15);
if result = "0000000000000000" then
alu_psw(2) <= '1';
else
alu_psw(2) <= '0';
end if;
if (alu_input(15) /= alus_input(15)) and (alu_input(15) /= result(15)) then
alu_psw(1) <= '1';
else
alu_psw(1) <= '0';
end if;
alu_psw(0) <= ((not alu_input(15)) and alus_input(15)) or ((not alu_input(15)) and result(15)) or (alus_input(15) and result(15));
when others =>
alu_output <= "XXXXXXXXXXXXXXXX";
alu_psw <= "XXXX";
end case;
-- misc insns
elsif have_csm = 1 and ir_csm = '1' then -- csm
alu_output <= alu_input;
alu_psw <= psw(3 downto 0);
elsif have_mfp = 1 and (ir_mfpi = '1' or ir_mfpd = '1') then -- mfpi, mfpd, mtpi, mtpd
alu_output <= alu_input;
alu_psw(3) <= alu_input(15);
if alu_input = "0000000000000000" then
alu_psw(2) <= '1';
else
alu_psw(2) <= '0';
end if;
alu_psw(1) <= '0';
alu_psw(0) <= psw(0);
elsif have_mfp = 1 and (ir_mtpi = '1' or ir_mtpd = '1') then -- mfpi, mfpd, mtpi, mtpd
alu_output <= alus_input;
alu_psw(3) <= alus_input(15);
if alus_input = "0000000000000000" then
alu_psw(2) <= '1';
else
alu_psw(2) <= '0';
end if;
alu_psw(1) <= '0';
alu_psw(0) <= psw(0);
elsif have_mtps = 1 and ir_mtps = '1' then -- mtps
ir_byte <= '1';
alu_output <= alu_input;
alu_psw <= psw(3 downto 0);
elsif have_mtps = 1 and ir_mfps = '1' then -- mfps
ir_byte <= '1';
alu_output <= psw;
alu_psw(3) <= psw(7);
if psw(7 downto 0) = "0000000" then
alu_psw(2) <= '1';
else
alu_psw(2) <= '0';
end if;
alu_psw(1) <= '0';
alu_psw(0) <= psw(0);
elsif have_xor = 1 and ir_dopr = '1' and ir(11 downto 9) = "100" then -- xor
result := alu_input xor alus_input; -- xor is handled here, not in the eis alu
alu_output <= result;
alu_psw(3) <= result(15);
if result = "0000000000000000" then
alu_psw(2) <= '1';
else
alu_psw(2) <= '0';
end if;
alu_psw(1) <= '0';
alu_psw(0) <= psw(0);
elsif have_mpr = 1 and ir_mpr = '1' then
case ir(6) is
when '0' => -- tstset
result := alu_input(15 downto 1) & '1';
alu_output <= result;
alu_psw(3) <= alu_input(15);
if alu_input = "0000000000000000" then
alu_psw(2) <= '1';
else
alu_psw(2) <= '0';
end if;
alu_psw(1) <= '0';
alu_psw(0) <= alu_input(0);
when '1' => -- wrtlck
result := alu_input;
alu_output <= result;
alu_psw(3) <= alu_input(15);
if alu_input = "0000000000000000" then
alu_psw(2) <= '1';
else
alu_psw(2) <= '0';
end if;
alu_psw(1) <= '0';
alu_psw(0) <= psw(0);
when others =>
null;
end case;
-- fp11 insns with simple integer result
elsif ir_fpsop1 = '1' then
alu_psw(3 downto 0) <= psw(3 downto 0);
case ir(7 downto 6) is
when "01" => -- ldfps
result := alu_input;
alu_output <= result;
when "10" => -- stfps
result(15 downto 14) := fps(15 downto 14);
result(13 downto 12) := "00"; -- set these unused bits to zero to stop the tests complaining
result(11 downto 0) := fps(11 downto 0);
alu_output <= result;
when "11" => -- stst
result := "000000000000" & fec;
alu_output <= result;
when others =>
alu_output <= "XXXXXXXXXXXXXXXX";
alu_psw <= "XXXX";
end case;
else
alu_output <= "XXXXXXXXXXXXXXXX";
alu_psw <= "XXXX";
end if;
end process;
--
-- eis alu: mul, div, ash, ashc insns
--
process(clk)
begin
if clk = '1' and clk'event then
if have_eis = 1 and ir_dopr = '1' and ir(11) = '0' then
case ir(10 downto 9) is
when "00" => -- mul
if eis_sequencer = "11111" then -- load seq. code
eis_temp1 <= signed(alu_input) * signed(alus_input); -- mul is easy, just use the hw multipliers
elsif eis_sequencer = "00000" then -- done seq. code
eis_output <= eis_temp1(31 downto 16); -- high part
eis_output32 <= eis_temp1(15 downto 0); -- low part
eis_psw(3) <= eis_temp1(31); -- set n
if eis_temp1 = "00000000000000000000000000000000" then -- set z
eis_psw(2) <= '1';
else
eis_psw(2) <= '0';
end if;
eis_psw(1) <= '0'; -- set v - always 0, 15bits*15bits into 31 cannot overflow
if (eis_temp1(31) = '1' and eis_temp1(30 downto 15) /= "1111111111111111")
or (eis_temp1(31) = '0' and eis_temp1(30 downto 15) /= "0000000000000000") then
eis_psw(0) <= '1';
else
eis_psw(0) <= '0';
end if;
end if;
when "01" => -- div
if eis_sequencer = "10000" then -- load seq. code
if alu_input(15) = '1' then -- if input negative
eis_temp1 <= '0' & ((not alu_input) + 1) & (14 downto 0 => '0'); -- take two's complement
eis_flag1 <= '1';
else
eis_temp1 <= '0' & alu_input & (14 downto 0 => '0');
eis_flag1 <= '0';
end if;
if alus_input(15) = '1' then
eis_temp2 <= (not (alus_input & alut_input)) + 1;
eis_flag2 <= '1';
else
eis_temp2 <= alus_input & alut_input;
eis_flag2 <= '0';
end if;
eis_psw <= "0000";
-- main div loop
elsif eis_sequencer(4) = '0' then
if unsigned(eis_temp1) <= unsigned(eis_temp2) then
if eis_sequencer(3 downto 0) = "1111" then
if unsigned(eis_temp1) <= unsigned(eis_temp2) then
eis_psw(1) <= '1';
end if;
end if;
eis_temp(conv_integer(eis_sequencer(3 downto 0))) <= '1';
eis_temp2 <= eis_temp2 - eis_temp1;
else
eis_temp(conv_integer(eis_sequencer(3 downto 0))) <= '0';
end if;
eis_temp1(30 downto 0) <= eis_temp1(31 downto 1);
else
-- post processing
-- setting the flags after the div instruction is the tricky part. A division by zero causes
-- the result not to be stored - which is handled by the state machine, results are only
-- stored if the v and c flags are 00. Still a very tricky thing considering all the
-- border cases. I believe the current model is correct - and also, it passes all the tests
-- I can find. Specifically, fkac, and zkdj - and the results make sense as well.
if eis_flag2 = '1' then -- if 2nd op was negative
eis_output32 <= (not eis_temp2(15 downto 0)) + 1; -- sign adjust remainder
else
eis_output32 <= eis_temp2(15 downto 0); -- or just the positive
end if;
if eis_flag1 /= eis_flag2 then -- if signs were different
eis_psw(3) <= '1'; -- set N
eis_output <= (not eis_temp) + 1; -- sign adjust result
else
eis_psw(3) <= '0'; -- clear n
eis_output <= eis_temp; -- copy result
end if;
-- special cases : result is zero
if eis_temp(14 downto 0) = (14 downto 0 => '0') then
if eis_temp(15) = '0' then
eis_psw(3) <= '0';
eis_psw(2) <= '1';
eis_output(15) <= '0';
else
eis_psw(2) <= '0';
end if;
if eis_temp(15) = '1' and eis_flag1 /= eis_flag2 then
eis_psw(1) <= '0'; -- special case: quotient is negative maxint - that isn't an overflow
end if;
else
eis_psw(2) <= '0';
end if;
-- set c and v if divisor was zero
if alu_input = (15 downto 0 => '0') then
if modelcode = 73 or modelcode = 83 or modelcode = 84 or modelcode = 93 or modelcode = 94 or modelcode = 53 then
eis_psw(2) <= psw(2); -- observed behaviour and needed to pass zkdj FIXME
end if;
eis_psw(1) <= '1';
eis_psw(0) <= '1';
end if;
end if;
when "10" => -- ash
if eis_sequencer = "11111" then
eis_output <= alus_input;
eis_flag2 <= '0';
eis_psw(1) <= '0';
eis_psw(0) <= '0';
eis_temp(15 downto 6) <= "0000000000"; -- for easier debugging
eis_flag1 <= alu_input(5);
if alu_input(4 downto 0) = "11111" then -- see EK-1184E-TM-001_Dec87.pdf, page B-17
if modelcode = 73
or modelcode = 53
or modelcode = 83
or modelcode = 84
or modelcode = 93
or modelcode = 94
then
if have_fpa = 0 then -- Speculative - see ashc case
eis_flag1 <= '1';
end if;
end if;
end if;
if alu_input(5) = '1' then
eis_temp(5 downto 0) <= (not alu_input(5 downto 0)) + 1;
else
eis_temp(5 downto 0) <= alu_input(5 downto 0);
end if;
else
if eis_temp(5 downto 0) /= "000000" then
if eis_flag1 = '1' then
eis_output <= eis_output(15) & eis_output(15 downto 1);
eis_psw(0) <= eis_output(0);
else
eis_output <= eis_output(14 downto 0) & '0';
if eis_output(15 downto 14) = "10" or eis_output(15 downto 14) = "01" then
eis_psw(1) <= '1';
end if;
eis_psw(0) <= eis_output(15);
end if;
eis_temp(5 downto 0) <= eis_temp(5 downto 0) - 1;
else
eis_flag2 <= '1';
eis_psw(3) <= eis_output(15);
if eis_output = "0000000000000000" then
eis_psw(2) <= '1';
else
eis_psw(2) <= '0';
end if;
end if;
end if;
when "11" => -- ashc
if eis_sequencer = "11111" then
eis_temp1 <= alus_input & alut_input;
eis_flag2 <= '0';
eis_psw(1) <= '0';
eis_psw(0) <= '0';
eis_temp(15 downto 6) <= "0000000000"; -- for easier debugging
eis_flag1 <= alu_input(5);
if alu_input(4 downto 0) = "11111" then -- see EK-1184E-TM-001_Dec87.pdf, page B-17
if modelcode = 73
or modelcode = 53
or modelcode = 83
or modelcode = 84
or modelcode = 93
or modelcode = 94
then
if have_fpa = 0 then -- As evidenced from the test code in RSTS V10.1L
eis_flag1 <= '1';
end if;
end if;
end if;
if alu_input(5) = '1' then
eis_temp(5 downto 0) <= ('0' & (not alu_input(4 downto 0))) + 1;
else
eis_temp(4 downto 0) <= alu_input(4 downto 0);
eis_temp(5) <= '0';
end if;
else
if eis_temp(5 downto 0) /= "000000" then
if eis_flag1 = '1' then
eis_temp1 <= eis_temp1(31) & eis_temp1(31 downto 1);
eis_psw(0) <= eis_temp1(0);
else
eis_temp1 <= eis_temp1(30 downto 0) & '0';
if eis_temp1(31 downto 30) = "10" or eis_temp1(31 downto 30) = "01" then
eis_psw(1) <= '1';
end if;
eis_psw(0) <= eis_temp1(31);
end if;
eis_temp(5 downto 0) <= eis_temp(5 downto 0) - 1;
else
eis_flag2 <= '1';
eis_output <= eis_temp1(31 downto 16);
eis_output32 <= eis_temp1(15 downto 0);
eis_psw(3) <= eis_temp1(31);
if eis_temp1 = "00000000000000000000000000000000" then
eis_psw(2) <= '1';
else
eis_psw(2) <= '0';
end if;
end if;
end if;
when others =>
null;
end case;
end if;
end if;
end process;
-- floating point alu
process(clk, reset, falu_pending_clear, ir_fpao, falu_load, falu_input, falus_input, ir_wait)
variable v_caseworkaround : std_logic_vector(3 downto 0);
begin
if clk = '1' and clk'event then
if have_fpu = 1 and reset = '1' then
falu_done <= '0';
falu_fsm <= falu_idle;
falu_fps <= "0000";
falu_flag1 <= '0';
falu_pending_fiu <= '0';
falu_pending_fiv <= '0';
falu_pending_fic <= '0';
falu_pending_divz <= '0';
elsif have_fpu = 1 and ir_wait = '0' then
if falu_pending_clear = '1' then
falu_pending_fiu <= '0';
falu_pending_fiv <= '0';
falu_pending_fic <= '0';
falu_pending_divz <= '0';
end if;
if ir_fpao = '1' then
-- if the falu_load bit is one, load the work registers and the initial state for the falu state machine.
-- both of which are dependent on exactly which instruction we need to process - the sequence in the
-- state machine needs to be started at a specific point, which is not the same for all insn - and
-- definitely all insn have their own initialization requirements and special cases.
--
-- also, the main cpu state machine includes
if falu_load = '1' then
falu_done <= '0';
falu_fps <= "0000";
case ir(11 downto 8) is
when "0010" | "0011" => -- mul(f|d), mod(f|d)
if falu_input(63) = falus_input(63) then -- set sign - positive if both operands are same sign, negative otherwise
falu_fps(3) <= '0';
else
falu_fps(3) <= '1';
end if;
falu_fps(2 downto 0) <= "000"; -- set default for fps bits
falu_fsm <= falu_mult;
falu_work1 <= (others => '0');
falu_work2 <= '0' & '1' & falus_input(54 downto 0) & '0' & '0';
if falu_input(62 downto 55) = "00000000" or falus_input(62 downto 55) = "00000000" then -- if either input exponent is zero, we don't need to multiply at all
falu_output <= (others => '0');
falu_output2 <= (others => '0');
falu_fps <= "0100";
falu_fsm <= falu_idle;
falu_done <= '1';
end if;
falu_ccw <= ("00" & falu_input(62 downto 55)) + ("00" & falus_input(62 downto 55)) - "0010000001";
when "0100" | "0110" => -- add(f|d), sub(f|d)
falu_fsm <= falu_align;
falu_work1 <= '0' & '1' & falu_input(54 downto 0) & '0' & '0';
falu_work2 <= '0' & '1' & falus_input(54 downto 0) & '0' & '0';
falu_fps(3 downto 0) <= "0000"; -- set default for fps bits
if falu_input(62 downto 55) = "00000000" then -- if the primary input exponent is zero, we don't need to add (or subtract) at all
falu_output <= falus_input;
falu_fps(3) <= falus_input(63);
if falus_input(62 downto 55) = "00000000" then
falu_fps(2) <= '1';
else
falu_fps(2) <= '0';
end if;
falu_fsm <= falu_idle;
falu_done <= '1';
elsif falus_input(62 downto 55) = "00000000" then -- if the secondary input exponent is zero, we don't need to add (or subtract) at all
falu_output(62 downto 0) <= falu_input(62 downto 0);
if ir(9) = '0' then
falu_fps(3) <= falu_input(63);
falu_output(63) <= falu_input(63);
else
falu_fps(3) <= not falu_input(63);
falu_output(63) <= not falu_input(63);
end if;
falu_fsm <= falu_idle;
falu_done <= '1';
elsif unsigned(falu_input(62 downto 55)) < unsigned(falus_input(62 downto 55)) then
falu_ccw <= "00" & (unsigned(falus_input(62 downto 55)) - unsigned(falu_input(62 downto 55)));
falu_flag1 <= '1';
elsif unsigned(falu_input(62 downto 55)) = unsigned(falus_input(62 downto 55)) then
falu_ccw <= (others => '0');
if unsigned(falu_input(54 downto 0)) < unsigned(falus_input(54 downto 0)) then
falu_flag1 <= '1';
else
falu_flag1 <= '0';
end if;
else
falu_ccw <= "00" & (unsigned(falu_input(62 downto 55)) - unsigned(falus_input(62 downto 55)));
falu_flag1 <= '0';
end if;
when "0101" => -- ld(f|d)
falu_output <= falu_input;
falu_fps(3) <= falu_input(63);
if falu_input(62 downto 55) = "00000000" then
falu_fps(2) <= '1';
else
falu_fps(2) <= '0';
end if;
falu_fps(1 downto 0) <= "00"; -- set default for fps bits
falu_fsm <= falu_idle;
falu_done <= '1';
when "0111" => -- cmp(f|d)
falu_output <= falus_input;
falu_fps(3 downto 0) <= "0000"; -- set default for fps bits
if falu_input(63) = '1' and falus_input(63) = '0' then
falu_fps(3) <= '1';
elsif falu_input(63) = '0' and falus_input(63) = '0' then
if unsigned(falu_input(62 downto 55)) < unsigned(falus_input(62 downto 55)) then
falu_fps(3) <= '1';
elsif unsigned(falu_input(62 downto 55)) = unsigned(falus_input(62 downto 55)) then
if unsigned(falu_input(54 downto 0)) < unsigned(falus_input(54 downto 0)) then
falu_fps(3) <= '1';
elsif unsigned(falu_input(54 downto 0)) = unsigned(falus_input(54 downto 0)) then
falu_fps(2) <= '1';
else
-- n=0, z=0
end if;
else
-- n=0, z=0
end if;
elsif falu_input(63) = '1' and falus_input(63) = '1' then
if unsigned(falus_input(62 downto 55)) < unsigned(falu_input(62 downto 55)) then
falu_fps(3) <= '1';
elsif unsigned(falus_input(62 downto 55)) = unsigned(falu_input(62 downto 55)) then
if unsigned(falus_input(54 downto 0)) < unsigned(falu_input(54 downto 0)) then
falu_fps(3) <= '1';
elsif unsigned(falus_input(54 downto 0)) = unsigned(falu_input(54 downto 0)) then
falu_fps(2) <= '1';
else
-- n=0, z=0
end if;
else
-- n=0, z=0
end if;
end if;
if falu_input(62 downto 55) = "00000000" and falus_input(62 downto 55) = "00000000" then
falu_fps <= "0100";
falu_output <= (others => '0');
end if;
falu_fsm <= falu_idle;
falu_done <= '1';
when "1000" => -- st(f|d)
falu_output <= falu_input;
falu_fps <= fps(3 downto 0);
falu_fsm <= falu_idle;
falu_done <= '1';
when "1001" => -- div(f|d)
if falu_input(63) = falus_input(63) then -- set sign - positive if both operands are same sign, negative otherwise
falu_fps(3) <= '0';
else
falu_fps(3) <= '1';
end if;
falu_fps(2 downto 0) <= "000"; -- set default for other fps bits
falu_fsm <= falu_div;
falu_work1 <= (others => '0');
falu_work2 <= '0' & '1' & falus_input(54 downto 0) & '0' & '0';
if falus_input(62 downto 55) = "00000000" then -- check ac operand first, then if fsrc is zero, those settings will take precedence over these
falu_output <= (others => '0');
falu_fps <= "0100";
falu_fsm <= falu_idle;
falu_done <= '1';
end if;
if falu_input(62 downto 55) = "00000000" then
falu_pending_divz <= '1';
falu_output <= falus_input;
falu_fps <= fps(3 downto 0); -- the doc is unspecific... but xxdp jfpa seems to expect no updates to fps
falu_fsm <= falu_idle;
falu_done <= '1';
end if;
falu_ccw <= "0000111010";
when "1010" => -- stexp
falu_output(55 downto 48) <= falu_input(62 downto 55) - "10000000";
if unsigned(falu_input(62 downto 55)) < unsigned'("10000000") then
falu_fps(3) <= '1';
falu_output(63 downto 56) <= (others => '1');
else
falu_fps(3) <= '0';
falu_output(63 downto 56) <= (others => '0');
end if;
if falu_input(62 downto 55) = "10000000" then
falu_fps(2) <= '1';
else
falu_fps(2) <= '0';
end if;
falu_fps(1) <= '0';
falu_fps(0) <= '0';
falu_fsm <= falu_idle;
falu_done <= '1';
when "1011" => -- stc(f|d)(i|l)
falu_fsm <= falu_shift;
falu_fps(3) <= falu_input(63); -- n is set from input
falu_fps(2 downto 0) <= "000"; -- set default for other fps bits
falu_work1 <= (others => '0'); -- the idea to use work1 here is that synthesis may reuse the shifter we already have for it
if fps(6) = '0' then -- if short integer mode
falu_work1(58 downto 43) <= '1' & falu_input(54 downto 40);
falu_ccw <= unsigned'("0010010000") - unsigned("00" & falu_input(62 downto 55)); -- exponent minus the bias
else
if fps(7) = '0' then -- if in long integer mode, we need to check if we're in float mode, because then we can only copy 23 bits of fraction
falu_work1(58 downto 35) <= '1' & falu_input(54 downto 32);
else
falu_work1(58 downto 26) <= '1' & falu_input(54 downto 23);
end if;
if ir(5 downto 3) = "000" or ir(5 downto 0) = "010111" then -- reg or mode 2, reg 7
falu_ccw <= unsigned'("0010010000") - unsigned("00" & falu_input(62 downto 55)); -- exponent minus the bias
else
falu_ccw <= unsigned'("0010100000") - unsigned("00" & falu_input(62 downto 55)); -- exponent minus the bias
end if;
end if;
if unsigned(falu_input(62 downto 55)) < unsigned'("10000001") then -- it is not entirely clear in the manuals, but if the input is less than 1, the output is zero, and only the Z flag is set. It is not a conversion error!
falu_output <= (others => '0');
falu_fps(3) <= '0';
falu_fps(2) <= '1';
falu_fps(1) <= '0';
falu_fps(0) <= '0';
falu_fsm <= falu_idle;
falu_done <= '1';
end if;
when "1100" | "1111" => -- stc(f|d)(d|f), ldc(d|f)(f|d)
falu_fps(3) <= falu_input(63); -- n bit is in most cases a direct copy of the input
falu_output(63 downto 55) <= falu_input(63 downto 55); -- right in most cases
falu_fps(2 downto 0) <= "000"; -- set default for other fps bits
if falu_input(62 downto 55) = "00000000" then -- if the input exponent is zero, then the z bit in fps must be set
falu_fps(2) <= '1';
falu_fps(3) <= '0'; -- negative zero exp is ignored
falu_output <= (others => '0');
else
falu_fps(2) <= '0';
if (fps(7) = '0' and ir(11 downto 8) = "1100") or (fps(7) = '1' and ir(11 downto 8) = "1111") then -- convert to a double, or to a float?
falu_output(54 downto 32) <= falu_input(54 downto 32); -- just copy the high part if converting f to d
falu_output(31 downto 0) <= "00000000000000000000000000000000"; -- and set the low part to zeroes
else
if fps(5) = '1' then -- on d to f conversion, if round/trunc is trunc
falu_output(54 downto 32) <= falu_input(54 downto 32); -- just copy the high part
falu_output(31 downto 0) <= "00000000000000000000000000000000"; -- and set the low part to zeroes
else
if falu_input(62 downto 31) = "11111111111111111111111111111111" then -- this bit pattern causes overflow to occur
falu_output(62 downto 32) <= "0000000000000000000000000000000"; -- result after overflow is zeroes
falu_fps(2) <= '1'; -- set z bit, because of zeroes we just set!
falu_fps(1) <= '1'; -- set v bit to signal overflow
if fps(9) = '1' then -- if fiv enabled
falu_pending_fiv <= '1'; -- then signal the pending interrupt
end if;
else
falu_output(62 downto 31) <= falu_input(62 downto 31) + "1"; -- normal case, round bit added. Note that I count on normal arithmetic to handle increasing the exponent, if that is necessary to handle an overflow of the fraction part
end if;
falu_output(31 downto 0) <= "00000000000000000000000000000000"; -- in all cases, the low part is cleared
end if;
end if;
end if;
falu_fsm <= falu_idle;
falu_done <= '1';
when "1101" => -- ldexp
falu_output(63) <= falu_input(63); -- setup sign, in all cases a copy of the input
falu_output(54 downto 0) <= falu_input(54 downto 0); -- fraction is in all cases same as input
falu_fps(3) <= falu_input(63); -- setup n bit
falu_fps(2 downto 0) <= "000"; -- set default for other fps bits
if falus_input(55) = '1' then -- sign bit on, ie. is this a negative 2-complement integer
if falus_input(54 downto 47) = "11111111" -- if yes, then the next 8 bits need to be ones too, else it is an overflow
and falus_input(47 downto 40) /= "10000000" then -- would produce an overflow as well - special case
falu_output(62 downto 55) <= falus_input(47 downto 40) + "10000000"; -- not an overflow --> assign the new exponent, biased w. 200 oct
else
if fps(10) = '1' then -- if fiu enabled
falu_output(62 downto 55) <= falus_input(47 downto 40) + "10000000";
if falus_input(47 downto 40) + "10000000" = "00000000" then
falu_fps(2) <= '1';
end if;
falu_pending_fiu <= '1';
else
falu_output <= (others => '0'); -- if fiu disabled, just set the output to zeroes
falu_fps(2) <= '1'; -- and dont forget to set the z bit either
falu_fps(3) <= '0'; -- and also dont forget zero is not negative
end if;
end if;
else -- positive exponent
if falus_input(54 downto 47) = "00000000" then -- for a positive exponent, the high 8 bits must be clear, otherwise it is an overflow
falu_output(62 downto 55) <= falus_input(47 downto 40) + "10000000"; -- not overflow - assign new exponent biased w. 200 oct
else
falu_fps(1) <= '1'; -- v bit is set only when exponent > 177
if fps(9) = '1' then -- if fiv is enabled
falu_output(62 downto 55) <= falus_input(47 downto 40) + "10000000";
if falus_input(47 downto 40) + "10000000" = "00000000" then
falu_fps(2) <= '1';
end if;
falu_pending_fiv <= '1';
else -- if fiv is disabled
falu_output <= (others => '0'); -- set the output to all zeroes
falu_fps(2) <= '1'; -- set z bit as well
falu_fps(3) <= '0';
end if;
end if;
end if;
falu_fsm <= falu_idle;
falu_done <= '1';
when "1110" => -- ldc(i|l)(f|d)
falu_fsm <= falu_norm;
falu_fps(2 downto 0) <= "000"; -- set default for fps bits
if fps(6) = '0'
or ir(5 downto 3) = "000"
or ir(5 downto 0) = "010111" -- mode 2, reg 7 only
then
if fps(6) = '1' then -- if fl is set ie long mode, mode must be 0 or mode 2, reg 7, and the strange exception to use the single 16bit word as the upper applies.
falu_ccw <= "0010011111"; -- 37(8) or 31(10), max number of shifts for long mode; special case
else
falu_ccw <= "0010001111"; -- 17(8) or 15(10), max number of shifts for integer mode
end if;
falu_work1 <= (others => '0');
if falu_input(39) = '1' then
falu_fps(3) <= '1';
falu_work1(58 downto 43) <= (not falu_input(39 downto 24)) + 1;
else
falu_fps(3) <= '0';
falu_work1(58 downto 43) <= falu_input(39 downto 24);
end if;
else
falu_ccw <= "0010011111"; -- 37(8) or 31(10), max number of shifts for long mode
falu_work1 <= (others => '0');
if falu_input(55) = '1' then
falu_fps(3) <= '1';
falu_work1(58 downto 27) <= (not falu_input(55 downto 24)) + 1;
else
falu_fps(3) <= '0';
falu_work1(58 downto 27) <= falu_input(55 downto 24);
end if;
end if;
when others =>
null;
end case;
else
case falu_fsm is
-- multiply, ie. shifting and adding
-- this does not deal with the fd bit - all mult operations are full precision, regardless of the bit. The core
-- would be significantly faster for single prec if we would deal with the fd bit. FIXME!
when falu_mult =>
if falu_work2(57 downto 2) /= "00000000000000000000000000000000000000000000000000000000" then
if falu_work2(2) = '1' then -- if lowest order bit is a one
falu_work1 <= ('0' & falu_work1(58 downto 1) + ('0' & '1' & falu_input(54 downto 0) & "00")); -- then shift right and add
else
falu_work1 <= '0' & falu_work1(58 downto 1); -- if not set, then only shift right
end if;
falu_work2 <= '0' & falu_work2(58 downto 1); -- shift right for next round
else
falu_fsm <= falu_norm; -- if all bits done, then go into normalize state
end if;
-- align the operands for addition or subtraction
-- flag1 has which one of the operands needs to be shifted - and also, check the fd bit to see what the maximum value of the shift should be
-- falu_ccw has the difference - if it is 0, or shift- and decrement to 0, the addition/subtraction state is next up
when falu_align =>
if falu_ccw /= "0000000000" then
if falu_flag1 = '1' then
falu_work1 <= '0' & falu_work1(58 downto 1);
else
falu_work2 <= '0' & falu_work2(58 downto 1);
end if;
if fps(7) = '1' and unsigned(falu_ccw) > unsigned'("0000111001") then -- > 57 ??
falu_ccw <= "0000000000";
if falu_flag1 = '1' then
falu_work1 <= (others => '0');
else
falu_work2 <= (others => '0');
end if;
falu_fsm <= falu_addsub;
elsif fps(7) = '0' and unsigned(falu_ccw) > unsigned'("0000011001") then -- > 25 ??
falu_ccw <= "0000000000";
if falu_flag1 = '1' then
falu_work1 <= (others => '0');
else
falu_work2 <= (others => '0');
end if;
falu_fsm <= falu_addsub;
else
falu_ccw <= falu_ccw - 1;
end if;
else
falu_fsm <= falu_addsub;
end if;
when falu_addsub =>
-- this statement:
-- case ir(9) & falu_input(63) & falus_input(63) & falu_flag1 is
-- would be a nice and elegant way to express what I would like
-- alas, ISE cannot translate it. See:
-- AR #22098 - 8.2i XST-"ERROR:HDLParsers:818 - Cannot determine the type of the selector &"
v_caseworkaround := ir(9) & falu_input(63) & falus_input(63) & falu_flag1;
case v_caseworkaround is
when "0000" | "0001" => -- add, +|+
falu_work1 <= falu_work1 + falu_work2;
falu_fps(3) <= '0';
when "0100" => -- add, !work1<work2, -|+
falu_work1 <= falu_work1 - falu_work2;
falu_fps(3) <= '1';
when "0101" => -- add, work1<work2, -|+
falu_work1 <= falu_work2 - falu_work1;
falu_fps(3) <= '0';
when "0010" => -- add, !work1<work2, +|-
falu_work1 <= falu_work1 - falu_work2;
falu_fps(3) <= '0';
when "0011" => -- add, work1<work2, +|-
falu_work1 <= falu_work2 - falu_work1;
falu_fps(3) <= '1';
when "0110" | "0111" => -- add, -|-
falu_work1 <= falu_work1 + falu_work2;
falu_fps(3) <= '1';
when "1000" => -- sub, !work1<work2, +|+
falu_work1 <= falu_work1 - falu_work2;
falu_fps(3) <= '1';
when "1001" => -- sub, work1<work2, +|+
falu_work1 <= falu_work2 - falu_work1;
falu_fps(3) <= '0';
when "1100" | "1101" => -- sub, -|+
falu_work1 <= falu_work2 + falu_work1;
falu_fps(3) <= '0';
when "1010" | "1011" => -- sub, +|-
falu_work1 <= falu_work2 + falu_work1;
falu_fps(3) <= '1';
when "1110" => -- sub, !work1<work2, -|-
falu_work1 <= falu_work1 - falu_work2;
falu_fps(3) <= '0';
when "1111" => -- sub, work1<work2, -|-
falu_work1 <= falu_work2 - falu_work1;
falu_fps(3) <= '1';
when others =>
null;
end case;
if falu_flag1 = '1' then
falu_ccw <= "00" & falus_input(62 downto 55);
else
falu_ccw <= "00" & falu_input(62 downto 55);
end if;
falu_fsm <= falu_norm;
when falu_div =>
if unsigned(falu_work2) >= unsigned('0' & '1' & falu_input(54 downto 0) & "00") then
falu_work1 <= falu_work1(57 downto 0) & '1';
falu_work2 <= unsigned(falu_work2(57 downto 0) & '0') - unsigned('1' & falu_input(54 downto 0) & "000");
else
falu_work1 <= falu_work1(57 downto 0) & '0';
falu_work2 <= falu_work2(57 downto 0) & '0';
end if;
if falu_ccw /= "0000000000" then
falu_ccw <= falu_ccw - 1;
else
falu_fsm <= falu_norm;
falu_ccw <= unsigned("00" & falus_input(62 downto 55)) - unsigned("00" & falu_input(62 downto 55)) + unsigned'("0010000000");
end if;
when falu_shift =>
if falu_ccw /= "0000000000" then
falu_work1 <= '0' & falu_work1(58 downto 1);
falu_ccw <= falu_ccw - 1;
else
falu_output <= (others => '0');
if falu_input(63) = '1' then
falu_output(63 downto 32) <= (not falu_work1(58 downto 27)) + 1;
else
falu_output(63 downto 32) <= falu_work1(58 downto 27);
end if;
falu_fsm <= falu_shift2;
end if;
if fps(6) = '0' then
if unsigned(falu_ccw) > unsigned'("0000001111") then
falu_fsm <= falu_shifte;
end if;
else
if unsigned(falu_ccw) > unsigned'("0000011111") then
falu_fsm <= falu_shifte;
end if;
end if;
when falu_shift2 =>
if falu_output(63 downto 48) = "0000000000000000" then
if fps(6) = '0' then
falu_fps(3) <= '0';
falu_fps(2) <= '1';
else
if falu_output(47 downto 32) = "0000000000000000" then
falu_fps(3) <= '0';
falu_fps(2) <= '1';
end if;
end if;
end if;
if falu_output(63) /= falu_input(63) then
falu_fsm <= falu_shifte;
else
falu_fsm <= falu_idle;
falu_done <= '1';
end if;
when falu_shifte =>
falu_fps(3) <= '0'; -- on error, result is not negative
falu_fps(2) <= '1';
falu_fps(1) <= '0'; -- V bit is not used
falu_fps(0) <= '1';
falu_output <= (others => '0');
if fps(8) = '1' then
falu_pending_fic <= '1';
end if;
falu_fsm <= falu_idle;
falu_done <= '1';
when falu_norm =>
if falu_work1(58 downto 57) = "01" then -- hidden bit in the right place, overflow bit clear?
if ir(11 downto 8) = "0011" then
falu_fsm <= falu_sep;
else
falu_fsm <= falu_rt;
end if;
elsif falu_work1(58) = '1' then -- is the overflow bit set?
falu_work1 <= '0' & falu_work1(58 downto 1); -- shift right
falu_ccw <= falu_ccw + 1; -- increase exponent
if ir(11 downto 8) = "0011" then
falu_fsm <= falu_sep;
else
falu_fsm <= falu_rt;
end if;
else
-- 76543210987654321098765432109876543210987654321098765432
if falu_work1(57 downto 2) /= "00000000000000000000000000000000000000000000000000000000" then
falu_work1 <= falu_work1(57 downto 0) & '0'; -- shift left
falu_ccw <= falu_ccw - 1; -- decrease exponent
else -- coming here, we have lost all ones from the fraction; the output is zero
falu_fps(3) <= '0'; -- make sure that the n bit is cleared
falu_fsm <= falu_zres; -- result is zero
end if;
end if;
when falu_sep =>
if signed(falu_ccw) <= signed'("0010000000") then
falu_output2 <= (others => '0');
falu_fsm <= falu_rt;
elsif (signed(falu_ccw) > signed'("0010011000") and fps(7) = '0') or (signed(falu_ccw) > signed'("0010111000") and fps(7) = '1') then
falu_fsm <= falu_sep3;
else
falu_output2(63) <= falu_fps(3);
falu_output2(62 downto 55) <= falu_ccw(7 downto 0);
falu_output2(54 downto 0) <= falu_work1(56 downto 2);
falu_fsm <= falu_sep2;
falu_work2 <= (others => '0');
falu_work2(58 downto 57) <= "10";
end if;
when falu_sep2 =>
if signed(falu_ccw) > signed'("0010000000") then
falu_work1 <= falu_work1(57 downto 0) & '0'; -- shift left
falu_work2 <= '1' & falu_work2(58 downto 1); -- shift right
falu_ccw <= falu_ccw - 1;
elsif falu_work1(57) /= '1' and falu_ccw /= "0000000000" then
falu_work1 <= falu_work1(57 downto 0) & '0'; -- shift left
falu_ccw <= falu_ccw - 1;
if falu_work1(57 downto 2) = "00000000000000000000000000000000000000000000000000000000" then
falu_ccw <= "0000000000";
end if;
else
falu_output2(54 downto 0) <= falu_output2(54 downto 0) and falu_work2(56 downto 2);
falu_fsm <= falu_res;
if falu_ccw = "0000000000" then
falu_fsm <= falu_zres; -- zero result handled directly, because res would wrongly raise an underflow
end if;
end if;
when falu_sep3 =>
falu_output <= (others => '0'); -- set fraction output to zero
falu_fps(3) <= '0'; -- if the fraction is zero, so is its sign
falu_fps(2) <= '1'; -- set z for fraction
falu_output2(63) <= falu_fps(3);
falu_output2(62 downto 55) <= falu_ccw(7 downto 0);
falu_output2(54 downto 0) <= falu_work1(56 downto 2);
if falu_ccw(8) = '1' and falu_ccw(9) /= '1' then -- overflow?
falu_fps(1) <= '1'; -- set the flag
if fps(9) = '1' then -- are overflow traps enabled?
falu_pending_fiv <= '1'; -- yes, set flag
else
falu_output2 <= (others => '0');
end if;
end if;
falu_done <= '1';
falu_fsm <= falu_idle;
when falu_rt =>
if fps(5) = '0' then
if fps(7) = '0' then
-- 87654321098765432109876543 210987654321098765432109876543210
falu_work1 <= (unsigned(falu_work1(58 downto 33)) + unsigned'("00000000000000000000000001")) & "000000000000000000000000000000000";
else
falu_work1 <= falu_work1 + "10";
end if;
end if;
falu_fsm <= falu_rtc;
when falu_rtc =>
if falu_work1(58) = '1' then
falu_work1 <= '0' & falu_work1(58 downto 1);
falu_ccw <= falu_ccw + 1;
end if;
falu_fsm <= falu_res;
when falu_res =>
falu_output(63) <= falu_fps(3);
falu_output(62 downto 55) <= falu_ccw(7 downto 0);
falu_output(54 downto 0) <= falu_work1(56 downto 2);
falu_done <= '1';
falu_fsm <= falu_idle;
if falu_ccw(7 downto 0) = "00000000" then
falu_fps(2) <= '1';
else
falu_fps(2) <= '0';
end if;
if falu_ccw(9) = '1' or falu_ccw(9 downto 0) = "0000000000" then
if fps(10) = '1' then -- are underflow traps enabled?
falu_pending_fiu <= '1'; -- yes, set flag
else
falu_fsm <= falu_zres; -- traps are not enabled, output is zero
end if;
elsif falu_ccw(8) = '1' then
falu_fps(1) <= '1'; -- set the flag
if fps(9) = '1' then -- are overflow traps enabled?
falu_pending_fiv <= '1'; -- yes, set flag
else
falu_fsm <= falu_zres; -- traps are not enabled, output is zero
end if;
end if;
when falu_zres =>
falu_output <= (others => '0');
falu_fps(3) <= '0';
falu_fps(2) <= '1';
falu_fps(0) <= '0';
falu_done <= '1';
falu_fsm <= falu_idle;
when falu_idle =>
falu_done <= '0';
falu_ccw <= (others => '0');
falu_work1 <= (others => '0');
falu_work2 <= (others => '0');
falu_flag1 <= '0';
when others =>
null;
end case;
end if;
elsif ir_fpsop2 = '1' then
case ir(7 downto 6) is
when "00" => -- clr(f/d)
falu_output <= (others => '0');
falu_fps(3 downto 0) <= "0100";
when "01" => -- tst(f/d)
falu_output <= falu_input;
if falu_input(62 downto 55) = "00000000" then
falu_fps(2) <= '1';
falu_output <= (others => '0');
else
falu_fps(2) <= '0';
end if;
falu_fps(3) <= falu_input(63);
falu_fps(1) <= '0';
falu_fps(0) <= '0';
when "10" => -- abs(f/d)
falu_output <= '0' & falu_input(62 downto 0);
if falu_input(62 downto 55) = "00000000" then
falu_fps(2) <= '1';
falu_output <= (others => '0');
else
falu_fps(2) <= '0';
end if;
falu_fps(3) <= '0';
falu_fps(1) <= '0';
falu_fps(0) <= '0';
when "11" => -- neg(f/d)
if falu_input(63) = '0' then
falu_output <= '1' & falu_input(62 downto 0);
falu_fps(3) <= '1';
else
falu_output <= '0' & falu_input(62 downto 0);
falu_fps(3) <= '0';
end if;
if falu_input(62 downto 55) = "00000000" then
falu_output <= (others => '0');
falu_fps(2) <= '1';
falu_fps(3) <= '0';
else
falu_fps(2) <= '0';
end if;
falu_fps(1) <= '0';
falu_fps(0) <= '0';
when others =>
falu_output <= (others => 'X');
falu_fps(3 downto 0) <= "XXXX";
end case;
falu_output2 <= (others => 'X');
else
falu_output <= (others => 'X');
falu_output2 <= (others => 'X');
falu_fps(3 downto 0) <= "XXXX";
end if;
end if;
end if;
end process;
end implementation;
| gpl-3.0 |
EliasLuiz/TCC | Leon3/lib/gaisler/grdmac/grdmac_1p.vhd | 1 | 3847 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: grdmac_1p
-- File: grdmac_1p.vhd
-- Author: Andrea Gianarro - Aeroflex Gaisler AB
-- Description: AMBA DMA controller with single master interface
-- Supports scatter gather on unaligned data through internal
-- re-alignment buffer and conditional descriptors
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library techmap;
use techmap.gencomp.all;
library grlib;
use grlib.config_types.all;
use grlib.config.all;
use grlib.amba.all;
use grlib.stdlib.all;
library gaisler;
use gaisler.grdmac_pkg.all;
use grlib.devices.all;
-- pragma translate_off
use std.textio.all;
-- pragma translate_on
entity grdmac_1p is
generic (
hmindex : integer := 0; -- AHB master index
hirq : integer := 0;
pindex : integer := 0; -- APB configuration slave index
paddr : integer := 1;
pmask : integer := 16#FFF#;
ndmach : integer range 1 to 16 := 1; -- number of DMA channels --TODO: implement ndmach = 0
bufsize : integer range 4*AHBDW/8 to 64*1024:= 256; -- number of bytes in buffer (must be a multiple of 4*WORD_SIZE)
burstbound : integer range 4 to 1024 := 512;
memtech : integer := 0;
testen : integer := 0;
ft : integer range 0 to 2 := 0;
wbmask : integer := 0;
busw : integer := 64
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
irq_trig : in std_logic_vector(63 downto 0)
);
end;
architecture rtl of grdmac_1p is
begin
dma: grdmac
generic map(
hmindex => hmindex,
hirq => hirq,
pindex => pindex,
paddr => paddr,
pmask => pmask,
en_ahbm1 => 0,
hmindex1 => 0,
ndmach => ndmach,
bufsize => bufsize,
burstbound => burstbound,
memtech => memtech,
testen => testen,
ft => ft,
wbmask => wbmask,
busw => busw
)
port map (
rst => rst,
clk => clk,
ahbmi => ahbmi,
ahbmo => ahbmo,
ahbmi1 => ahbm_in_none,
ahbmo1 => open,
apbi => apbi,
apbo => apbo,
irq_trig => irq_trig
);
end architecture;
| gpl-3.0 |
EliasLuiz/TCC | Leon3/lib/spw/wrapper/grspw_gen.vhd | 1 | 11158 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: grspw_gen
-- File: grspw_gen.vhd
-- Author: Marko Isomaki - Gaisler Research
-- Description: Generic GRSPW core
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library spw;
use spw.spwcomp.all;
entity grspw_gen is
generic(
tech : integer := 0;
sysfreq : integer := 10000;
usegen : integer range 0 to 1 := 1;
nsync : integer range 1 to 2 := 1;
rmap : integer range 0 to 2 := 0;
rmapcrc : integer range 0 to 1 := 0;
fifosize1 : integer range 4 to 32 := 32;
fifosize2 : integer range 16 to 64 := 64;
rxclkbuftype : integer range 0 to 2 := 0;
rxunaligned : integer range 0 to 1 := 0;
rmapbufs : integer range 2 to 8 := 4;
ft : integer range 0 to 2 := 0;
scantest : integer range 0 to 1 := 0;
techfifo : integer range 0 to 1 := 1;
ports : integer range 1 to 2 := 1;
memtech : integer := 0;
nodeaddr : integer range 0 to 255 := 254;
destkey : integer range 0 to 255 := 0
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
txclk : in std_ulogic;
rxclk : in std_logic_vector(1 downto 0);
--ahb mst in
hgrant : in std_ulogic;
hready : in std_ulogic;
hresp : in std_logic_vector(1 downto 0);
hrdata : in std_logic_vector(31 downto 0);
--ahb mst out
hbusreq : out std_ulogic;
hlock : out std_ulogic;
htrans : out std_logic_vector(1 downto 0);
haddr : out std_logic_vector(31 downto 0);
hwrite : out std_ulogic;
hsize : out std_logic_vector(2 downto 0);
hburst : out std_logic_vector(2 downto 0);
hprot : out std_logic_vector(3 downto 0);
hwdata : out std_logic_vector(31 downto 0);
--apb slv in
psel : in std_ulogic;
penable : in std_ulogic;
paddr : in std_logic_vector(31 downto 0);
pwrite : in std_ulogic;
pwdata : in std_logic_vector(31 downto 0);
--apb slv out
prdata : out std_logic_vector(31 downto 0);
--spw in
d : in std_logic_vector(1 downto 0);
nd : in std_logic_vector(9 downto 0);
dconnect : in std_logic_vector(3 downto 0);
--spw out
do : out std_logic_vector(1 downto 0);
so : out std_logic_vector(1 downto 0);
rxrsto : out std_ulogic;
--time iface
tickin : in std_ulogic;
tickout : out std_ulogic;
--irq
irq : out std_logic;
--misc
clkdiv10 : in std_logic_vector(7 downto 0);
dcrstval : in std_logic_vector(9 downto 0);
timerrstval : in std_logic_vector(11 downto 0);
--rmapen
rmapen : in std_ulogic;
rmapnodeaddr : in std_logic_vector(7 downto 0);
linkdis : out std_ulogic;
testclk : in std_ulogic := '0';
testrst : in std_ulogic := '0';
testen : in std_ulogic := '0'
);
end entity;
architecture rtl of grspw_gen is
constant fabits1 : integer := log2(fifosize1);
constant fabits2 : integer := log2(fifosize2);
constant rfifo : integer := 5 + log2(rmapbufs);
--rx ahb fifo
signal rxrenable : std_ulogic;
signal rxraddress : std_logic_vector(4 downto 0);
signal rxwrite : std_ulogic;
signal rxwdata : std_logic_vector(31 downto 0);
signal rxwaddress : std_logic_vector(4 downto 0);
signal rxrdata : std_logic_vector(31 downto 0);
--tx ahb fifo
signal txrenable : std_ulogic;
signal txraddress : std_logic_vector(4 downto 0);
signal txwrite : std_ulogic;
signal txwdata : std_logic_vector(31 downto 0);
signal txwaddress : std_logic_vector(4 downto 0);
signal txrdata : std_logic_vector(31 downto 0);
--nchar fifo
signal ncrenable : std_ulogic;
signal ncraddress : std_logic_vector(5 downto 0);
signal ncwrite : std_ulogic;
signal ncwdata : std_logic_vector(8 downto 0);
signal ncwaddress : std_logic_vector(5 downto 0);
signal ncrdata : std_logic_vector(8 downto 0);
--rmap buf
signal rmrenable : std_ulogic;
signal rmrenablex : std_ulogic;
signal rmraddress : std_logic_vector(7 downto 0);
signal rmwrite : std_ulogic;
signal rmwdata : std_logic_vector(7 downto 0);
signal rmwaddress : std_logic_vector(7 downto 0);
signal rmrdata : std_logic_vector(7 downto 0);
attribute syn_netlist_hierarchy : boolean;
attribute syn_netlist_hierarchy of rtl : architecture is false;
begin
grspwc0 : grspwc
generic map(
sysfreq => sysfreq,
usegen => usegen,
nsync => nsync,
rmap => rmap,
rmapcrc => rmapcrc,
fifosize1 => fifosize1,
fifosize2 => fifosize2,
rxunaligned => rxunaligned,
rmapbufs => rmapbufs,
scantest => scantest,
ports => ports,
tech => tech,
nodeaddr => nodeaddr,
destkey => destkey)
port map(
rst => rst,
clk => clk,
txclk => txclk,
--ahb mst in
hgrant => hgrant,
hready => hready,
hresp => hresp,
hrdata => hrdata,
--ahb mst out
hbusreq => hbusreq,
hlock => hlock,
htrans => htrans,
haddr => haddr,
hwrite => hwrite,
hsize => hsize,
hburst => hburst,
hprot => hprot,
hwdata => hwdata,
--apb slv in
psel => psel,
penable => penable,
paddr => paddr,
pwrite => pwrite,
pwdata => pwdata,
--apb slv out
prdata => prdata,
--spw in
d => d,
nd => nd,
dconnect => dconnect,
--spw out
do => do,
so => so,
rxrsto => rxrsto,
--time iface
tickin => tickin,
tickout => tickout,
--clk bufs
rxclki => rxclk,
--irq
irq => irq,
--misc
clkdiv10 => clkdiv10,
dcrstval => dcrstval,
timerrstval => timerrstval,
--rmapen
rmapen => rmapen,
rmapnodeaddr => rmapnodeaddr,
--rx ahb fifo
rxrenable => rxrenable,
rxraddress => rxraddress,
rxwrite => rxwrite,
rxwdata => rxwdata,
rxwaddress => rxwaddress,
rxrdata => rxrdata,
--tx ahb fifo
txrenable => txrenable,
txraddress => txraddress,
txwrite => txwrite,
txwdata => txwdata,
txwaddress => txwaddress,
txrdata => txrdata,
--nchar fifo
ncrenable => ncrenable,
ncraddress => ncraddress,
ncwrite => ncwrite,
ncwdata => ncwdata,
ncwaddress => ncwaddress,
ncrdata => ncrdata,
--rmap buf
rmrenable => rmrenable,
rmraddress => rmraddress,
rmwrite => rmwrite,
rmwdata => rmwdata,
rmwaddress => rmwaddress,
rmrdata => rmrdata,
linkdis => linkdis,
testclk => clk,
testrst => testrst,
testen => testen
);
ntst: if scantest = 0 generate
rmrenablex <= rmrenable;
end generate;
tst: if scantest = 1 generate
rmrenablex <= rmrenable and not testen;
end generate;
------------------------------------------------------------------------------
-- FIFOS ---------------------------------------------------------------------
------------------------------------------------------------------------------
nft : if ft = 0 generate
--receiver AHB FIFO
rx_ram0 : syncram_2p generic map(memtech*techfifo, fabits1, 32)
port map(clk, rxrenable, rxraddress(fabits1-1 downto 0),
rxrdata, clk, rxwrite,
rxwaddress(fabits1-1 downto 0), rxwdata);
--receiver nchar FIFO
rx_ram1 : syncram_2p generic map(memtech*techfifo, fabits2, 9)
port map(clk, ncrenable, ncraddress(fabits2-1 downto 0),
ncrdata, clk, ncwrite,
ncwaddress(fabits2-1 downto 0), ncwdata);
--transmitter FIFO
tx_ram0 : syncram_2p generic map(memtech*techfifo, fabits1, 32)
port map(clk, txrenable, txraddress(fabits1-1 downto 0),
txrdata, clk, txwrite, txwaddress(fabits1-1 downto 0), txwdata);
--RMAP Buffer
rmap_ram : if (rmap /= 0) generate
ram0 : syncram_2p generic map(memtech, rfifo, 8)
port map(clk, rmrenablex, rmraddress(rfifo-1 downto 0),
rmrdata, clk, rmwrite, rmwaddress(rfifo-1 downto 0),
rmwdata);
end generate;
end generate;
ft1 : if ft /= 0 generate
--receiver AHB FIFO
rx_ram0 : syncram_2pft generic map(memtech*techfifo, fabits1, 32, 0, 0, ft*techfifo)
port map(clk, rxrenable, rxraddress(fabits1-1 downto 0),
rxrdata, clk, rxwrite,
rxwaddress(fabits1-1 downto 0), rxwdata);
--receiver nchar FIFO
rx_ram1 : syncram_2pft generic map(memtech*techfifo, fabits2, 9, 0, 0, 2*techfifo)
port map(clk, ncrenable, ncraddress(fabits2-1 downto 0),
ncrdata, clk, ncwrite,
ncwaddress(fabits2-1 downto 0), ncwdata);
--transmitter FIFO
tx_ram0 : syncram_2pft generic map(memtech*techfifo, fabits1, 32, 0, 0, ft*techfifo)
port map(clk, txrenable, txraddress(fabits1-1 downto 0),
txrdata, clk, txwrite, txwaddress(fabits1-1 downto 0), txwdata);
--RMAP Buffer
rmap_ram : if (rmap /= 0) generate
ram0 : syncram_2pft generic map(memtech, rfifo, 8, 0, 0, 2)
port map(clk, rmrenablex, rmraddress(rfifo-1 downto 0),
rmrdata, clk, rmwrite, rmwaddress(rfifo-1 downto 0),
rmwdata);
end generate;
end generate;
end architecture;
| gpl-3.0 |
EliasLuiz/TCC | Leon3/lib/esa/memoryctrl/mctrl.in.vhd | 6 | 635 | -- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := CONFIG_MCTRL_LEON2;
constant CFG_MCTRL_RAM8BIT : integer := CONFIG_MCTRL_8BIT;
constant CFG_MCTRL_RAM16BIT : integer := CONFIG_MCTRL_16BIT;
constant CFG_MCTRL_5CS : integer := CONFIG_MCTRL_5CS;
constant CFG_MCTRL_SDEN : integer := CONFIG_MCTRL_SDRAM;
constant CFG_MCTRL_SEPBUS : integer := CONFIG_MCTRL_SDRAM_SEPBUS;
constant CFG_MCTRL_INVCLK : integer := CONFIG_MCTRL_SDRAM_INVCLK;
constant CFG_MCTRL_SD64 : integer := CONFIG_MCTRL_SDRAM_BUS64;
constant CFG_MCTRL_PAGE : integer := CONFIG_MCTRL_PAGE + CONFIG_MCTRL_PROGPAGE;
| gpl-3.0 |
EliasLuiz/TCC | Leon3/designs/leon3-ahbfile/config.vhd | 1 | 4409 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := inferred;
constant CFG_MEMTECH : integer := inferred;
constant CFG_PADTECH : integer := inferred;
constant CFG_TRANSTECH : integer := GTP0;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 0 + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 0;
constant CFG_SVT : integer := 1;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 0;
constant CFG_NWP : integer := (0);
constant CFG_PWD : integer := 0*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 0;
constant CFG_ISETS : integer := 1;
constant CFG_ISETSZ : integer := 1;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 0;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 0;
constant CFG_DSETS : integer := 1;
constant CFG_DSETSZ : integer := 1;
constant CFG_DLINE : integer := 8;
constant CFG_DREPL : integer := 0;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 0 + 0*2 + 4*0;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 0;
constant CFG_ITLBNUM : integer := 2;
constant CFG_DTLBNUM : integer := 2;
constant CFG_TLB_TYPE : integer := 1 + 0*2;
constant CFG_TLB_REP : integer := 1;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 2 + 64*0;
constant CFG_ATBSZ : integer := 2;
constant CFG_AHBPF : integer := 0;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 1 + 0;
constant CFG_PCLOW : integer := 2;
constant CFG_STAT_ENABLE : integer := 0;
constant CFG_STAT_CNT : integer := 1;
constant CFG_STAT_NMAX : integer := 0;
constant CFG_STAT_DSUEN : integer := 0;
constant CFG_NP_ASI : integer := 0;
constant CFG_WRPSR : integer := 0;
constant CFG_ALTWIN : integer := 0;
constant CFG_REX : integer := 0;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 0;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 1;
constant CFG_AHBRSZ : integer := 64;
constant CFG_AHBRADDR : integer := 16#400#;
constant CFG_AHBRPIPE : integer := 0;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 1;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 0;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 0;
constant CFG_GRGPIO_IMASK : integer := 16#0000#;
constant CFG_GRGPIO_WIDTH : integer := 1;
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
| gpl-3.0 |
firecake/IRIS | FPGA/VHDL/ipcore_dir/Clk_Manager.vhd | 1 | 2812 | --------------------------------------------------------------------------------
-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : 14.7
-- \ \ Application : xaw2vhdl
-- / / Filename : Clk_Manager.vhd
-- /___/ /\ Timestamp : 05/28/2015 11:45:02
-- \ \ / \
-- \___\/\___\
--
--Command: xaw2vhdl-st C:\IRIS\ipcore_dir\.\Clk_Manager.xaw C:\IRIS\ipcore_dir\.\Clk_Manager
--Design Name: Clk_Manager
--Device: xc3s200a-4vq100
--
-- Module Clk_Manager
-- Generated by Xilinx Architecture Wizard
-- Written for synthesis tool: XST
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;
entity Clk_Manager is
port ( CLKIN_IN : in std_logic;
CLKIN_IBUFG_OUT : out std_logic;
CLK0_OUT : out std_logic;
LOCKED_OUT : out std_logic);
end Clk_Manager;
architecture BEHAVIORAL of Clk_Manager is
signal CLKFB_IN : std_logic;
signal CLKIN_IBUFG : std_logic;
signal CLK0_BUF : std_logic;
signal GND_BIT : std_logic;
begin
GND_BIT <= '0';
CLKIN_IBUFG_OUT <= CLKIN_IBUFG;
CLK0_OUT <= CLKFB_IN;
CLKIN_IBUFG_INST : IBUFG
port map (I=>CLKIN_IN,
O=>CLKIN_IBUFG);
CLK0_BUFG_INST : BUFG
port map (I=>CLK0_BUF,
O=>CLKFB_IN);
DCM_SP_INST : DCM_SP
generic map( CLK_FEEDBACK => "1X",
CLKDV_DIVIDE => 2.0,
CLKFX_DIVIDE => 1,
CLKFX_MULTIPLY => 4,
CLKIN_DIVIDE_BY_2 => FALSE,
CLKIN_PERIOD => 25.000,
CLKOUT_PHASE_SHIFT => "NONE",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
DFS_FREQUENCY_MODE => "LOW",
DLL_FREQUENCY_MODE => "LOW",
DUTY_CYCLE_CORRECTION => TRUE,
FACTORY_JF => x"C080",
PHASE_SHIFT => 0,
STARTUP_WAIT => FALSE)
port map (CLKFB=>CLKFB_IN,
CLKIN=>CLKIN_IBUFG,
DSSEN=>GND_BIT,
PSCLK=>GND_BIT,
PSEN=>GND_BIT,
PSINCDEC=>GND_BIT,
RST=>GND_BIT,
CLKDV=>open,
CLKFX=>open,
CLKFX180=>open,
CLK0=>CLK0_BUF,
CLK2X=>open,
CLK2X180=>open,
CLK90=>open,
CLK180=>open,
CLK270=>open,
LOCKED=>LOCKED_OUT,
PSDONE=>open,
STATUS=>open);
end BEHAVIORAL;
| gpl-3.0 |
EliasLuiz/TCC | Leon3/lib/gaisler/spi/spi2ahb.vhd | 1 | 2987 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Entity: spi2ahb
-- File: spi2ahb.vhd
-- Author: Jan Andersson - Aeroflex Gaisler AB
-- Contact: [email protected]
-- Description: Simple SPI slave providing a bridge to AMBA AHB
-- See spi2ahbx.vhd and GRIP for documentation
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.conv_std_logic_vector;
library gaisler;
use gaisler.spi.all;
entity spi2ahb is
generic (
-- AHB Configuration
hindex : integer := 0;
--
ahbaddrh : integer := 0;
ahbaddrl : integer := 0;
ahbmaskh : integer := 0;
ahbmaskl : integer := 0;
--
oepol : integer range 0 to 1 := 0;
--
filter : integer range 2 to 512 := 2;
--
cpol : integer range 0 to 1 := 0;
cpha : integer range 0 to 1 := 0
);
port (
rstn : in std_ulogic;
clk : in std_ulogic;
-- AHB master interface
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
-- SPI signals
spii : in spi_in_type;
spio : out spi_out_type
);
end entity spi2ahb;
architecture rtl of spi2ahb is
signal spi2ahbi : spi2ahb_in_type;
begin
bridge : spi2ahbx
generic map (
hindex => hindex,
oepol => oepol,
filter => filter,
cpol => cpol,
cpha => cpha)
port map (
rstn => rstn,
clk => clk,
ahbi => ahbi,
ahbo => ahbo,
spii => spii,
spio => spio,
spi2ahbi => spi2ahbi,
spi2ahbo => open);
spi2ahbi.en <= '1';
spi2ahbi.haddr <= conv_std_logic_vector(ahbaddrh, 16) &
conv_std_logic_vector(ahbaddrl, 16);
spi2ahbi.hmask <= conv_std_logic_vector(ahbmaskh, 16) &
conv_std_logic_vector(ahbmaskl, 16);
end architecture rtl;
| gpl-3.0 |
hoglet67/CoPro6502 | src/PDP2011/cpuregs.vhd | 1 | 4084 |
--
-- Copyright (c) 2008-2015 Sytse van Slooten
--
-- Permission is hereby granted to any person obtaining a copy of these VHDL source files and
-- other language source files and associated documentation files ("the materials") to use
-- these materials solely for personal, non-commercial purposes.
-- You are also granted permission to make changes to the materials, on the condition that this
-- copyright notice is retained unchanged.
--
-- The materials are distributed in the hope that they will be useful, but WITHOUT ANY WARRANTY;
-- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
--
-- $Revision: 1.17 $
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity cpuregs is
port(
raddr : in std_logic_vector(5 downto 0);
waddr : in std_logic_vector(5 downto 0);
d : in std_logic_vector(15 downto 0);
o : out std_logic_vector(15 downto 0);
we : in std_logic;
clk : in std_logic
);
end cpuregs;
architecture implementation of cpuregs is
subtype mem_unit is std_logic_vector(15 downto 0);
type mem_type is array(15 downto 0) of mem_unit;
signal regs : mem_type := mem_type'(
mem_unit'("0000000000000000"),
mem_unit'("0000000000000000"),
mem_unit'("0000000000000000"),
mem_unit'("0000000000000000"),
mem_unit'("0000000000000000"),
mem_unit'("0000000000000000"),
mem_unit'("0000000000000000"),
mem_unit'("0000000000000000"),
mem_unit'("0000000000000000"),
mem_unit'("0000000000000000"),
mem_unit'("0000000000000000"),
mem_unit'("0000000000000000"),
mem_unit'("0000000000000000"),
mem_unit'("0000000000000000"),
mem_unit'("0000000000000000"),
mem_unit'("0000000000000000")
);
signal r_loc : std_logic_vector(3 downto 0);
signal w_loc : std_logic_vector(3 downto 0);
signal r0k : std_logic_vector(15 downto 0);
signal r1k : std_logic_vector(15 downto 0);
signal r2k : std_logic_vector(15 downto 0);
signal r3k : std_logic_vector(15 downto 0);
signal r4k : std_logic_vector(15 downto 0);
signal r5k : std_logic_vector(15 downto 0);
signal r6k : std_logic_vector(15 downto 0);
signal r6s : std_logic_vector(15 downto 0);
signal r6u : std_logic_vector(15 downto 0);
begin
r0k <= regs(conv_integer(0));
r1k <= regs(conv_integer(1));
r2k <= regs(conv_integer(2));
r3k <= regs(conv_integer(3));
r4k <= regs(conv_integer(4));
r5k <= regs(conv_integer(5));
r6k <= regs(conv_integer(6));
r6s <= regs(conv_integer(14));
r6u <= regs(conv_integer(15));
r_loc <=
raddr(3 downto 0) when raddr(2 downto 1) /= "11" else -- kernel 0-5 loc 0-5, u 0-5 loc 8-13
"0110" when raddr(2 downto 0) = "110" and raddr(5 downto 4) = "00" else -- kernel sp loc 6
"1110" when raddr(2 downto 0) = "110" and raddr(5 downto 4) = "01" else -- super sp loc 14
"1111" when raddr(2 downto 0) = "110" and raddr(5 downto 4) = "11" else -- user sp loc 15
"0111"; -- invalid
w_loc <=
waddr(3 downto 0) when waddr(2 downto 1) /= "11" else -- kernel 0-5 loc 0-5, u 0-5 loc 8-13
"0110" when waddr(2 downto 0) = "110" and waddr(5 downto 4) = "00" else -- kernel sp loc 6
"1110" when waddr(2 downto 0) = "110" and waddr(5 downto 4) = "01" else -- super sp loc 14
"1111" when waddr(2 downto 0) = "110" and waddr(5 downto 4) = "11" else -- user sp loc 15
"0111"; -- invalid
process(clk, we, w_loc, d)
begin
if clk = '1' and clk'event then
if we = '1' and w_loc /= "0111" then
regs(conv_integer(w_loc)) <= d;
end if;
end if;
end process;
process(r_loc, regs, raddr)
begin
if r_loc /= "0111" then
o <= regs(conv_integer(r_loc));
else
o <= (others => '0');
end if;
end process;
end implementation;
| gpl-3.0 |
firecake/IRIS | FPGA/VHDL/ipcore_dir/RAM/simulation/bmg_stim_gen.vhd | 1 | 16231 | --------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Stimulus Generator For TDP
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: bmg_stim_gen.vhd
--
-- Description:
-- Stimulus Generation For TDP
-- 100 Writes and 100 Reads will be performed in a repeatitive loop till the
-- simulation ends
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY REGISTER_LOGIC_TDP IS
PORT(
Q : OUT STD_LOGIC;
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
D : IN STD_LOGIC
);
END REGISTER_LOGIC_TDP;
ARCHITECTURE REGISTER_ARCH OF REGISTER_LOGIC_TDP IS
SIGNAL Q_O : STD_LOGIC :='0';
BEGIN
Q <= Q_O;
FF_BEH: PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST ='1') THEN
Q_O <= '0';
ELSE
Q_O <= D;
END IF;
END IF;
END PROCESS;
END REGISTER_ARCH;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
--USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY BMG_STIM_GEN IS
PORT (
CLKA : IN STD_LOGIC;
CLKB : IN STD_LOGIC;
TB_RST : IN STD_LOGIC;
ADDRA : OUT STD_LOGIC_VECTOR(11 DOWNTO 0) := (OTHERS => '0');
DINA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
WEA : OUT STD_LOGIC_VECTOR (0 DOWNTO 0) := (OTHERS => '0');
WEB : OUT STD_LOGIC_VECTOR (0 DOWNTO 0) := (OTHERS => '0');
ADDRB : OUT STD_LOGIC_VECTOR(11 DOWNTO 0) := (OTHERS => '0');
DINB : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
CHECK_DATA: OUT STD_LOGIC_VECTOR(1 DOWNTO 0):=(OTHERS => '0')
);
END BMG_STIM_GEN;
ARCHITECTURE BEHAVIORAL OF BMG_STIM_GEN IS
CONSTANT ZERO : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
CONSTANT ADDR_ZERO : STD_LOGIC_VECTOR(11 DOWNTO 0) := (OTHERS => '0');
CONSTANT DATA_PART_CNT_A : INTEGER:= DIVROUNDUP(32,32);
CONSTANT DATA_PART_CNT_B : INTEGER:= DIVROUNDUP(32,32);
SIGNAL WRITE_ADDR_A : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL WRITE_ADDR_B : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL WRITE_ADDR_INT_A : STD_LOGIC_VECTOR(11 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR_INT_A : STD_LOGIC_VECTOR(11 DOWNTO 0) := (OTHERS => '0');
SIGNAL WRITE_ADDR_INT_B : STD_LOGIC_VECTOR(11 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR_INT_B : STD_LOGIC_VECTOR(11 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR_A : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR_B : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA_INT : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINB_INT : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL MAX_COUNT : STD_LOGIC_VECTOR(10 DOWNTO 0):=CONV_STD_LOGIC_VECTOR(4096,11);
SIGNAL DO_WRITE_A : STD_LOGIC := '0';
SIGNAL DO_READ_A : STD_LOGIC := '0';
SIGNAL DO_WRITE_B : STD_LOGIC := '0';
SIGNAL DO_READ_B : STD_LOGIC := '0';
SIGNAL COUNT_NO : STD_LOGIC_VECTOR (10 DOWNTO 0):=(OTHERS => '0');
SIGNAL DO_READ_RA : STD_LOGIC := '0';
SIGNAL DO_READ_RB : STD_LOGIC := '0';
SIGNAL DO_READ_REG_A: STD_LOGIC_VECTOR(4 DOWNTO 0) :=(OTHERS => '0');
SIGNAL DO_READ_REG_B: STD_LOGIC_VECTOR(4 DOWNTO 0) :=(OTHERS => '0');
SIGNAL COUNT : integer := 0;
SIGNAL COUNT_B : integer := 0;
CONSTANT WRITE_CNT_A : integer := 6;
CONSTANT READ_CNT_A : integer := 6;
CONSTANT WRITE_CNT_B : integer := 4;
CONSTANT READ_CNT_B : integer := 4;
signal porta_wr_rd : std_logic:='0';
signal portb_wr_rd : std_logic:='0';
signal porta_wr_rd_complete: std_logic:='0';
signal portb_wr_rd_complete: std_logic:='0';
signal incr_cnt : std_logic :='0';
signal incr_cnt_b : std_logic :='0';
SIGNAL PORTB_WR_RD_HAPPENED: STD_LOGIC :='0';
SIGNAL LATCH_PORTA_WR_RD_COMPLETE : STD_LOGIC :='0';
SIGNAL PORTA_WR_RD_L1 :STD_LOGIC :='0';
SIGNAL PORTA_WR_RD_L2 :STD_LOGIC :='0';
SIGNAL PORTB_WR_RD_R1 :STD_LOGIC :='0';
SIGNAL PORTB_WR_RD_R2 :STD_LOGIC :='0';
SIGNAL PORTA_WR_RD_HAPPENED: STD_LOGIC :='0';
SIGNAL LATCH_PORTB_WR_RD_COMPLETE : STD_LOGIC :='0';
SIGNAL PORTB_WR_RD_L1 :STD_LOGIC :='0';
SIGNAL PORTB_WR_RD_L2 :STD_LOGIC :='0';
SIGNAL PORTA_WR_RD_R1 :STD_LOGIC :='0';
SIGNAL PORTA_WR_RD_R2 :STD_LOGIC :='0';
BEGIN
WRITE_ADDR_INT_A(11 DOWNTO 0) <= WRITE_ADDR_A(11 DOWNTO 0);
READ_ADDR_INT_A(11 DOWNTO 0) <= READ_ADDR_A(11 DOWNTO 0);
ADDRA <= IF_THEN_ELSE(DO_WRITE_A='1',WRITE_ADDR_INT_A,READ_ADDR_INT_A) ;
WRITE_ADDR_INT_B(11 DOWNTO 0) <= WRITE_ADDR_B(11 DOWNTO 0);
--To avoid collision during idle period, negating the read_addr of port A
READ_ADDR_INT_B(11 DOWNTO 0) <= IF_THEN_ELSE( (DO_WRITE_B='0' AND DO_READ_B='0'),ADDR_ZERO,READ_ADDR_B(11 DOWNTO 0));
ADDRB <= IF_THEN_ELSE(DO_WRITE_B='1',WRITE_ADDR_INT_B,READ_ADDR_INT_B) ;
DINA <= DINA_INT ;
DINB <= DINB_INT ;
CHECK_DATA(0) <= DO_READ_A;
CHECK_DATA(1) <= DO_READ_B;
RD_ADDR_GEN_INST_A:ENTITY work.ADDR_GEN
GENERIC MAP( C_MAX_DEPTH => 4096,
RST_INC => 1 )
PORT MAP(
CLK => CLKA,
RST => TB_RST,
EN => DO_READ_A,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => READ_ADDR_A
);
WR_ADDR_GEN_INST_A:ENTITY work.ADDR_GEN
GENERIC MAP( C_MAX_DEPTH =>4096 ,
RST_INC => 1 )
PORT MAP(
CLK => CLKA,
RST => TB_RST,
EN => DO_WRITE_A,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => WRITE_ADDR_A
);
RD_ADDR_GEN_INST_B:ENTITY work.ADDR_GEN
GENERIC MAP( C_MAX_DEPTH => 4096 ,
RST_INC => 1 )
PORT MAP(
CLK => CLKB,
RST => TB_RST,
EN => DO_READ_B,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => READ_ADDR_B
);
WR_ADDR_GEN_INST_B:ENTITY work.ADDR_GEN
GENERIC MAP( C_MAX_DEPTH => 4096 ,
RST_INC => 1 )
PORT MAP(
CLK => CLKB,
RST => TB_RST,
EN => DO_WRITE_B,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => WRITE_ADDR_B
);
WR_DATA_GEN_INST_A:ENTITY work.DATA_GEN
GENERIC MAP ( DATA_GEN_WIDTH =>32,
DOUT_WIDTH => 32,
DATA_PART_CNT => 1,
SEED => 2)
PORT MAP (
CLK =>CLKA,
RST => TB_RST,
EN => DO_WRITE_A,
DATA_OUT => DINA_INT
);
WR_DATA_GEN_INST_B:ENTITY work.DATA_GEN
GENERIC MAP ( DATA_GEN_WIDTH =>32,
DOUT_WIDTH =>32 ,
DATA_PART_CNT =>1,
SEED => 2)
PORT MAP (
CLK =>CLKB,
RST => TB_RST,
EN => DO_WRITE_B,
DATA_OUT => DINB_INT
);
PROCESS(CLKB)
BEGIN
IF(RISING_EDGE(CLKB)) THEN
IF(TB_RST='1') THEN
LATCH_PORTB_WR_RD_COMPLETE<='0';
ELSIF(PORTB_WR_RD_COMPLETE='1') THEN
LATCH_PORTB_WR_RD_COMPLETE <='1';
ELSIF(PORTA_WR_RD_HAPPENED='1') THEN
LATCH_PORTB_WR_RD_COMPLETE<='0';
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(TB_RST='1') THEN
PORTB_WR_RD_L1 <='0';
PORTB_WR_RD_L2 <='0';
ELSE
PORTB_WR_RD_L1 <= LATCH_PORTB_WR_RD_COMPLETE;
PORTB_WR_RD_L2 <= PORTB_WR_RD_L1;
END IF;
END IF;
END PROCESS;
PORTA_WR_RD_EN: PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(TB_RST='1') THEN
PORTA_WR_RD <='1';
ELSE
PORTA_WR_RD <= PORTB_WR_RD_L2;
END IF;
END IF;
END PROCESS;
PROCESS(CLKB)
BEGIN
IF(RISING_EDGE(CLKB)) THEN
IF(TB_RST='1') THEN
PORTA_WR_RD_R1 <='0';
PORTA_WR_RD_R2 <='0';
ELSE
PORTA_WR_RD_R1 <=PORTA_WR_RD;
PORTA_WR_RD_R2 <=PORTA_WR_RD_R1;
END IF;
END IF;
END PROCESS;
PORTA_WR_RD_HAPPENED <= PORTA_WR_RD_R2;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(TB_RST='1') THEN
LATCH_PORTA_WR_RD_COMPLETE<='0';
ELSIF(PORTA_WR_RD_COMPLETE='1') THEN
LATCH_PORTA_WR_RD_COMPLETE <='1';
ELSIF(PORTB_WR_RD_HAPPENED='1') THEN
LATCH_PORTA_WR_RD_COMPLETE<='0';
END IF;
END IF;
END PROCESS;
PROCESS(CLKB)
BEGIN
IF(RISING_EDGE(CLKB)) THEN
IF(TB_RST='1') THEN
PORTA_WR_RD_L1 <='0';
PORTA_WR_RD_L2 <='0';
ELSE
PORTA_WR_RD_L1 <= LATCH_PORTA_WR_RD_COMPLETE;
PORTA_WR_RD_L2 <= PORTA_WR_RD_L1;
END IF;
END IF;
END PROCESS;
PORTB_EN: PROCESS(CLKB)
BEGIN
IF(RISING_EDGE(CLKB)) THEN
IF(TB_RST='1') THEN
PORTB_WR_RD <='0';
ELSE
PORTB_WR_RD <= PORTA_WR_RD_L2;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(TB_RST='1') THEN
PORTB_WR_RD_R1 <='0';
PORTB_WR_RD_R2 <='0';
ELSE
PORTB_WR_RD_R1 <=PORTB_WR_RD;
PORTB_WR_RD_R2 <=PORTB_WR_RD_R1;
END IF;
END IF;
END PROCESS;
---double registered of porta complete on portb clk
PORTB_WR_RD_HAPPENED <= PORTB_WR_RD_R2;
PORTA_WR_RD_COMPLETE <= '1' when count=(WRITE_CNT_A+READ_CNT_A) else '0';
start_counter: process(clka)
begin
if(rising_edge(clka)) then
if(TB_RST='1') then
incr_cnt <= '0';
elsif(porta_wr_rd ='1') then
incr_cnt <='1';
elsif(porta_wr_rd_complete='1') then
incr_cnt <='0';
end if;
end if;
end process;
COUNTER: process(clka)
begin
if(rising_edge(clka)) then
if(TB_RST='1') then
count <= 0;
elsif(incr_cnt='1') then
count<=count+1;
end if;
if(count=(WRITE_CNT_A+READ_CNT_A)) then
count<=0;
end if;
end if;
end process;
DO_WRITE_A<='1' when (count <WRITE_CNT_A and incr_cnt='1') else '0';
DO_READ_A <='1' when (count >WRITE_CNT_A and incr_cnt='1') else '0';
PORTB_WR_RD_COMPLETE <= '1' when count_b=(WRITE_CNT_B+READ_CNT_B) else '0';
startb_counter: process(clkb)
begin
if(rising_edge(clkb)) then
if(TB_RST='1') then
incr_cnt_b <= '0';
elsif(portb_wr_rd ='1') then
incr_cnt_b <='1';
elsif(portb_wr_rd_complete='1') then
incr_cnt_b <='0';
end if;
end if;
end process;
COUNTER_B: process(clkb)
begin
if(rising_edge(clkb)) then
if(TB_RST='1') then
count_b <= 0;
elsif(incr_cnt_b='1') then
count_b<=count_b+1;
end if;
if(count_b=WRITE_CNT_B+READ_CNT_B) then
count_b<=0;
end if;
end if;
end process;
DO_WRITE_B<='1' when (count_b <WRITE_CNT_B and incr_cnt_b='1') else '0';
DO_READ_B <='1' when (count_b >WRITE_CNT_B and incr_cnt_b='1') else '0';
BEGIN_SHIFT_REG_A: FOR I IN 0 TO 4 GENERATE
BEGIN
DFF_RIGHT: IF I=0 GENERATE
BEGIN
SHIFT_INST_0: ENTITY work.REGISTER_LOGIC_TDP
PORT MAP(
Q => DO_READ_REG_A(0),
CLK =>CLKA,
RST=>TB_RST,
D =>DO_READ_A
);
END GENERATE DFF_RIGHT;
DFF_OTHERS: IF ((I>0) AND (I<=4)) GENERATE
BEGIN
SHIFT_INST: ENTITY work.REGISTER_LOGIC_TDP
PORT MAP(
Q => DO_READ_REG_A(I),
CLK =>CLKA,
RST=>TB_RST,
D =>DO_READ_REG_A(I-1)
);
END GENERATE DFF_OTHERS;
END GENERATE BEGIN_SHIFT_REG_A;
BEGIN_SHIFT_REG_B: FOR I IN 0 TO 4 GENERATE
BEGIN
DFF_RIGHT: IF I=0 GENERATE
BEGIN
SHIFT_INST_0: ENTITY work.REGISTER_LOGIC_TDP
PORT MAP(
Q => DO_READ_REG_B(0),
CLK =>CLKB,
RST=>TB_RST,
D =>DO_READ_B
);
END GENERATE DFF_RIGHT;
DFF_OTHERS: IF ((I>0) AND (I<=4)) GENERATE
BEGIN
SHIFT_INST: ENTITY work.REGISTER_LOGIC_TDP
PORT MAP(
Q => DO_READ_REG_B(I),
CLK =>CLKB,
RST=>TB_RST,
D =>DO_READ_REG_B(I-1)
);
END GENERATE DFF_OTHERS;
END GENERATE BEGIN_SHIFT_REG_B;
REGCEA_PROCESS: PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(TB_RST='1') THEN
DO_READ_RA <= '0';
ELSE
DO_READ_RA <= DO_READ_A;
END IF;
END IF;
END PROCESS;
REGCEB_PROCESS: PROCESS(CLKB)
BEGIN
IF(RISING_EDGE(CLKB)) THEN
IF(TB_RST='1') THEN
DO_READ_RB <= '0';
ELSE
DO_READ_RB <= DO_READ_B;
END IF;
END IF;
END PROCESS;
---REGCEB SHOULD BE SET AT THE CORE OUTPUT REGISTER/EMBEEDED OUTPUT REGISTER
--- WHEN CORE OUTPUT REGISTER IS SET REGCE SHOUD BE SET TO '1' WHEN THE READ DATA IS AVAILABLE AT THE CORE OUTPUT REGISTER
--WHEN CORE OUTPUT REGISTER IS '0' AND OUTPUT_PRIMITIVE_REG ='1', REGCE SHOULD BE SET WHEN THE DATA IS AVAILABLE AT THE PRIMITIVE OUTPUT REGISTER.
-- HERE, TO GENERAILIZE REGCE IS ASSERTED
WEA(0) <= IF_THEN_ELSE(DO_WRITE_A='1','1','0') ;
WEB(0) <= IF_THEN_ELSE(DO_WRITE_B='1','1','0') ;
END ARCHITECTURE;
| gpl-3.0 |
EliasLuiz/TCC | Leon3/lib/techmap/maps/grfpw_net.vhd | 1 | 36532 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: grfpw_net
-- File: grfpw_net.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: GRFPU / GRLFPC netlist wrapper
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use work.gencomp.all;
entity grfpw_net is
generic (tech : integer := 0;
pclow : integer range 0 to 2 := 2;
dsu : integer range 0 to 2 := 1;
disas : integer range 0 to 2 := 0;
pipe : integer range 0 to 2 := 0
);
port (
rst : in std_ulogic; -- Reset
clk : in std_ulogic;
holdn : in std_ulogic; -- pipeline hold
cpi_flush : in std_ulogic; -- pipeline flush
cpi_exack : in std_ulogic; -- FP exception acknowledge
cpi_a_rs1 : in std_logic_vector(4 downto 0);
cpi_d_pc : in std_logic_vector(31 downto 0);
cpi_d_inst : in std_logic_vector(31 downto 0);
cpi_d_cnt : in std_logic_vector(1 downto 0);
cpi_d_trap : in std_ulogic;
cpi_d_annul : in std_ulogic;
cpi_d_pv : in std_ulogic;
cpi_a_pc : in std_logic_vector(31 downto 0);
cpi_a_inst : in std_logic_vector(31 downto 0);
cpi_a_cnt : in std_logic_vector(1 downto 0);
cpi_a_trap : in std_ulogic;
cpi_a_annul : in std_ulogic;
cpi_a_pv : in std_ulogic;
cpi_e_pc : in std_logic_vector(31 downto 0);
cpi_e_inst : in std_logic_vector(31 downto 0);
cpi_e_cnt : in std_logic_vector(1 downto 0);
cpi_e_trap : in std_ulogic;
cpi_e_annul : in std_ulogic;
cpi_e_pv : in std_ulogic;
cpi_m_pc : in std_logic_vector(31 downto 0);
cpi_m_inst : in std_logic_vector(31 downto 0);
cpi_m_cnt : in std_logic_vector(1 downto 0);
cpi_m_trap : in std_ulogic;
cpi_m_annul : in std_ulogic;
cpi_m_pv : in std_ulogic;
cpi_x_pc : in std_logic_vector(31 downto 0);
cpi_x_inst : in std_logic_vector(31 downto 0);
cpi_x_cnt : in std_logic_vector(1 downto 0);
cpi_x_trap : in std_ulogic;
cpi_x_annul : in std_ulogic;
cpi_x_pv : in std_ulogic;
cpi_lddata : in std_logic_vector(31 downto 0); -- load data
cpi_dbg_enable : in std_ulogic;
cpi_dbg_write : in std_ulogic;
cpi_dbg_fsr : in std_ulogic; -- FSR access
cpi_dbg_addr : in std_logic_vector(4 downto 0);
cpi_dbg_data : in std_logic_vector(31 downto 0);
cpo_data : out std_logic_vector(31 downto 0); -- store data
cpo_exc : out std_logic; -- FP exception
cpo_cc : out std_logic_vector(1 downto 0); -- FP condition codes
cpo_ccv : out std_ulogic; -- FP condition codes valid
cpo_ldlock : out std_logic; -- FP pipeline hold
cpo_holdn : out std_ulogic;
cpo_dbg_data : out std_logic_vector(31 downto 0);
rfi1_rd1addr : out std_logic_vector(3 downto 0);
rfi1_rd2addr : out std_logic_vector(3 downto 0);
rfi1_wraddr : out std_logic_vector(3 downto 0);
rfi1_wrdata : out std_logic_vector(31 downto 0);
rfi1_ren1 : out std_ulogic;
rfi1_ren2 : out std_ulogic;
rfi1_wren : out std_ulogic;
rfi2_rd1addr : out std_logic_vector(3 downto 0);
rfi2_rd2addr : out std_logic_vector(3 downto 0);
rfi2_wraddr : out std_logic_vector(3 downto 0);
rfi2_wrdata : out std_logic_vector(31 downto 0);
rfi2_ren1 : out std_ulogic;
rfi2_ren2 : out std_ulogic;
rfi2_wren : out std_ulogic;
rfo1_data1 : in std_logic_vector(31 downto 0);
rfo1_data2 : in std_logic_vector(31 downto 0);
rfo2_data1 : in std_logic_vector(31 downto 0);
rfo2_data2 : in std_logic_vector(31 downto 0)
);
end;
architecture rtl of grfpw_net is
component grfpw_0_unisim
port(
rst : in std_logic;
clk : in std_logic;
holdn : in std_logic;
cpi_flush : in std_logic;
cpi_exack : in std_logic;
cpi_a_rs1 : in std_logic_vector (4 downto 0);
cpi_d_pc : in std_logic_vector (31 downto 0);
cpi_d_inst : in std_logic_vector (31 downto 0);
cpi_d_cnt : in std_logic_vector (1 downto 0);
cpi_d_trap : in std_logic;
cpi_d_annul : in std_logic;
cpi_d_pv : in std_logic;
cpi_a_pc : in std_logic_vector (31 downto 0);
cpi_a_inst : in std_logic_vector (31 downto 0);
cpi_a_cnt : in std_logic_vector (1 downto 0);
cpi_a_trap : in std_logic;
cpi_a_annul : in std_logic;
cpi_a_pv : in std_logic;
cpi_e_pc : in std_logic_vector (31 downto 0);
cpi_e_inst : in std_logic_vector (31 downto 0);
cpi_e_cnt : in std_logic_vector (1 downto 0);
cpi_e_trap : in std_logic;
cpi_e_annul : in std_logic;
cpi_e_pv : in std_logic;
cpi_m_pc : in std_logic_vector (31 downto 0);
cpi_m_inst : in std_logic_vector (31 downto 0);
cpi_m_cnt : in std_logic_vector (1 downto 0);
cpi_m_trap : in std_logic;
cpi_m_annul : in std_logic;
cpi_m_pv : in std_logic;
cpi_x_pc : in std_logic_vector (31 downto 0);
cpi_x_inst : in std_logic_vector (31 downto 0);
cpi_x_cnt : in std_logic_vector (1 downto 0);
cpi_x_trap : in std_logic;
cpi_x_annul : in std_logic;
cpi_x_pv : in std_logic;
cpi_lddata : in std_logic_vector (31 downto 0);
cpi_dbg_enable : in std_logic;
cpi_dbg_write : in std_logic;
cpi_dbg_fsr : in std_logic;
cpi_dbg_addr : in std_logic_vector (4 downto 0);
cpi_dbg_data : in std_logic_vector (31 downto 0);
cpo_data : out std_logic_vector (31 downto 0);
cpo_exc : out std_logic;
cpo_cc : out std_logic_vector (1 downto 0);
cpo_ccv : out std_logic;
cpo_ldlock : out std_logic;
cpo_holdn : out std_logic;
cpo_dbg_data : out std_logic_vector (31 downto 0);
rfi1_rd1addr : out std_logic_vector (3 downto 0);
rfi1_rd2addr : out std_logic_vector (3 downto 0);
rfi1_wraddr : out std_logic_vector (3 downto 0);
rfi1_wrdata : out std_logic_vector (31 downto 0);
rfi1_ren1 : out std_logic;
rfi1_ren2 : out std_logic;
rfi1_wren : out std_logic;
rfi2_rd1addr : out std_logic_vector (3 downto 0);
rfi2_rd2addr : out std_logic_vector (3 downto 0);
rfi2_wraddr : out std_logic_vector (3 downto 0);
rfi2_wrdata : out std_logic_vector (31 downto 0);
rfi2_ren1 : out std_logic;
rfi2_ren2 : out std_logic;
rfi2_wren : out std_logic;
rfo1_data1 : in std_logic_vector (31 downto 0);
rfo1_data2 : in std_logic_vector (31 downto 0);
rfo2_data1 : in std_logic_vector (31 downto 0);
rfo2_data2 : in std_logic_vector (31 downto 0));
-- disasen : in std_logic);
end component;
component grfpw_0_altera
port(
rst : in std_logic;
clk : in std_logic;
holdn : in std_logic;
cpi_flush : in std_logic;
cpi_exack : in std_logic;
cpi_a_rs1 : in std_logic_vector (4 downto 0);
cpi_d_pc : in std_logic_vector (31 downto 0);
cpi_d_inst : in std_logic_vector (31 downto 0);
cpi_d_cnt : in std_logic_vector (1 downto 0);
cpi_d_trap : in std_logic;
cpi_d_annul : in std_logic;
cpi_d_pv : in std_logic;
cpi_a_pc : in std_logic_vector (31 downto 0);
cpi_a_inst : in std_logic_vector (31 downto 0);
cpi_a_cnt : in std_logic_vector (1 downto 0);
cpi_a_trap : in std_logic;
cpi_a_annul : in std_logic;
cpi_a_pv : in std_logic;
cpi_e_pc : in std_logic_vector (31 downto 0);
cpi_e_inst : in std_logic_vector (31 downto 0);
cpi_e_cnt : in std_logic_vector (1 downto 0);
cpi_e_trap : in std_logic;
cpi_e_annul : in std_logic;
cpi_e_pv : in std_logic;
cpi_m_pc : in std_logic_vector (31 downto 0);
cpi_m_inst : in std_logic_vector (31 downto 0);
cpi_m_cnt : in std_logic_vector (1 downto 0);
cpi_m_trap : in std_logic;
cpi_m_annul : in std_logic;
cpi_m_pv : in std_logic;
cpi_x_pc : in std_logic_vector (31 downto 0);
cpi_x_inst : in std_logic_vector (31 downto 0);
cpi_x_cnt : in std_logic_vector (1 downto 0);
cpi_x_trap : in std_logic;
cpi_x_annul : in std_logic;
cpi_x_pv : in std_logic;
cpi_lddata : in std_logic_vector (31 downto 0);
cpi_dbg_enable : in std_logic;
cpi_dbg_write : in std_logic;
cpi_dbg_fsr : in std_logic;
cpi_dbg_addr : in std_logic_vector (4 downto 0);
cpi_dbg_data : in std_logic_vector (31 downto 0);
cpo_data : out std_logic_vector (31 downto 0);
cpo_exc : out std_logic;
cpo_cc : out std_logic_vector (1 downto 0);
cpo_ccv : out std_logic;
cpo_ldlock : out std_logic;
cpo_holdn : out std_logic;
cpo_dbg_data : out std_logic_vector (31 downto 0);
rfi1_rd1addr : out std_logic_vector (3 downto 0);
rfi1_rd2addr : out std_logic_vector (3 downto 0);
rfi1_wraddr : out std_logic_vector (3 downto 0);
rfi1_wrdata : out std_logic_vector (31 downto 0);
rfi1_ren1 : out std_logic;
rfi1_ren2 : out std_logic;
rfi1_wren : out std_logic;
rfi2_rd1addr : out std_logic_vector (3 downto 0);
rfi2_rd2addr : out std_logic_vector (3 downto 0);
rfi2_wraddr : out std_logic_vector (3 downto 0);
rfi2_wrdata : out std_logic_vector (31 downto 0);
rfi2_ren1 : out std_logic;
rfi2_ren2 : out std_logic;
rfi2_wren : out std_logic;
rfo1_data1 : in std_logic_vector (31 downto 0);
rfo1_data2 : in std_logic_vector (31 downto 0);
rfo2_data1 : in std_logic_vector (31 downto 0);
rfo2_data2 : in std_logic_vector (31 downto 0));
end component;
component grfpw_0_stratixii
port(
rst : in std_logic;
clk : in std_logic;
holdn : in std_logic;
cpi_flush : in std_logic;
cpi_exack : in std_logic;
cpi_a_rs1 : in std_logic_vector (4 downto 0);
cpi_d_pc : in std_logic_vector (31 downto 0);
cpi_d_inst : in std_logic_vector (31 downto 0);
cpi_d_cnt : in std_logic_vector (1 downto 0);
cpi_d_trap : in std_logic;
cpi_d_annul : in std_logic;
cpi_d_pv : in std_logic;
cpi_a_pc : in std_logic_vector (31 downto 0);
cpi_a_inst : in std_logic_vector (31 downto 0);
cpi_a_cnt : in std_logic_vector (1 downto 0);
cpi_a_trap : in std_logic;
cpi_a_annul : in std_logic;
cpi_a_pv : in std_logic;
cpi_e_pc : in std_logic_vector (31 downto 0);
cpi_e_inst : in std_logic_vector (31 downto 0);
cpi_e_cnt : in std_logic_vector (1 downto 0);
cpi_e_trap : in std_logic;
cpi_e_annul : in std_logic;
cpi_e_pv : in std_logic;
cpi_m_pc : in std_logic_vector (31 downto 0);
cpi_m_inst : in std_logic_vector (31 downto 0);
cpi_m_cnt : in std_logic_vector (1 downto 0);
cpi_m_trap : in std_logic;
cpi_m_annul : in std_logic;
cpi_m_pv : in std_logic;
cpi_x_pc : in std_logic_vector (31 downto 0);
cpi_x_inst : in std_logic_vector (31 downto 0);
cpi_x_cnt : in std_logic_vector (1 downto 0);
cpi_x_trap : in std_logic;
cpi_x_annul : in std_logic;
cpi_x_pv : in std_logic;
cpi_lddata : in std_logic_vector (31 downto 0);
cpi_dbg_enable : in std_logic;
cpi_dbg_write : in std_logic;
cpi_dbg_fsr : in std_logic;
cpi_dbg_addr : in std_logic_vector (4 downto 0);
cpi_dbg_data : in std_logic_vector (31 downto 0);
cpo_data : out std_logic_vector (31 downto 0);
cpo_exc : out std_logic;
cpo_cc : out std_logic_vector (1 downto 0);
cpo_ccv : out std_logic;
cpo_ldlock : out std_logic;
cpo_holdn : out std_logic;
cpo_dbg_data : out std_logic_vector (31 downto 0);
rfi1_rd1addr : out std_logic_vector (3 downto 0);
rfi1_rd2addr : out std_logic_vector (3 downto 0);
rfi1_wraddr : out std_logic_vector (3 downto 0);
rfi1_wrdata : out std_logic_vector (31 downto 0);
rfi1_ren1 : out std_logic;
rfi1_ren2 : out std_logic;
rfi1_wren : out std_logic;
rfi2_rd1addr : out std_logic_vector (3 downto 0);
rfi2_rd2addr : out std_logic_vector (3 downto 0);
rfi2_wraddr : out std_logic_vector (3 downto 0);
rfi2_wrdata : out std_logic_vector (31 downto 0);
rfi2_ren1 : out std_logic;
rfi2_ren2 : out std_logic;
rfi2_wren : out std_logic;
rfo1_data1 : in std_logic_vector (31 downto 0);
rfo1_data2 : in std_logic_vector (31 downto 0);
rfo2_data1 : in std_logic_vector (31 downto 0);
rfo2_data2 : in std_logic_vector (31 downto 0));
end component;
component grfpw_0_cycloneiii
port(
rst : in std_logic;
clk : in std_logic;
holdn : in std_logic;
cpi_flush : in std_logic;
cpi_exack : in std_logic;
cpi_a_rs1 : in std_logic_vector (4 downto 0);
cpi_d_pc : in std_logic_vector (31 downto 0);
cpi_d_inst : in std_logic_vector (31 downto 0);
cpi_d_cnt : in std_logic_vector (1 downto 0);
cpi_d_trap : in std_logic;
cpi_d_annul : in std_logic;
cpi_d_pv : in std_logic;
cpi_a_pc : in std_logic_vector (31 downto 0);
cpi_a_inst : in std_logic_vector (31 downto 0);
cpi_a_cnt : in std_logic_vector (1 downto 0);
cpi_a_trap : in std_logic;
cpi_a_annul : in std_logic;
cpi_a_pv : in std_logic;
cpi_e_pc : in std_logic_vector (31 downto 0);
cpi_e_inst : in std_logic_vector (31 downto 0);
cpi_e_cnt : in std_logic_vector (1 downto 0);
cpi_e_trap : in std_logic;
cpi_e_annul : in std_logic;
cpi_e_pv : in std_logic;
cpi_m_pc : in std_logic_vector (31 downto 0);
cpi_m_inst : in std_logic_vector (31 downto 0);
cpi_m_cnt : in std_logic_vector (1 downto 0);
cpi_m_trap : in std_logic;
cpi_m_annul : in std_logic;
cpi_m_pv : in std_logic;
cpi_x_pc : in std_logic_vector (31 downto 0);
cpi_x_inst : in std_logic_vector (31 downto 0);
cpi_x_cnt : in std_logic_vector (1 downto 0);
cpi_x_trap : in std_logic;
cpi_x_annul : in std_logic;
cpi_x_pv : in std_logic;
cpi_lddata : in std_logic_vector (31 downto 0);
cpi_dbg_enable : in std_logic;
cpi_dbg_write : in std_logic;
cpi_dbg_fsr : in std_logic;
cpi_dbg_addr : in std_logic_vector (4 downto 0);
cpi_dbg_data : in std_logic_vector (31 downto 0);
cpo_data : out std_logic_vector (31 downto 0);
cpo_exc : out std_logic;
cpo_cc : out std_logic_vector (1 downto 0);
cpo_ccv : out std_logic;
cpo_ldlock : out std_logic;
cpo_holdn : out std_logic;
cpo_dbg_data : out std_logic_vector (31 downto 0);
rfi1_rd1addr : out std_logic_vector (3 downto 0);
rfi1_rd2addr : out std_logic_vector (3 downto 0);
rfi1_wraddr : out std_logic_vector (3 downto 0);
rfi1_wrdata : out std_logic_vector (31 downto 0);
rfi1_ren1 : out std_logic;
rfi1_ren2 : out std_logic;
rfi1_wren : out std_logic;
rfi2_rd1addr : out std_logic_vector (3 downto 0);
rfi2_rd2addr : out std_logic_vector (3 downto 0);
rfi2_wraddr : out std_logic_vector (3 downto 0);
rfi2_wrdata : out std_logic_vector (31 downto 0);
rfi2_ren1 : out std_logic;
rfi2_ren2 : out std_logic;
rfi2_wren : out std_logic;
rfo1_data1 : in std_logic_vector (31 downto 0);
rfo1_data2 : in std_logic_vector (31 downto 0);
rfo2_data1 : in std_logic_vector (31 downto 0);
rfo2_data2 : in std_logic_vector (31 downto 0));
end component;
component grfpw_0_stratixiii
port(
rst : in std_logic;
clk : in std_logic;
holdn : in std_logic;
cpi_flush : in std_logic;
cpi_exack : in std_logic;
cpi_a_rs1 : in std_logic_vector (4 downto 0);
cpi_d_pc : in std_logic_vector (31 downto 0);
cpi_d_inst : in std_logic_vector (31 downto 0);
cpi_d_cnt : in std_logic_vector (1 downto 0);
cpi_d_trap : in std_logic;
cpi_d_annul : in std_logic;
cpi_d_pv : in std_logic;
cpi_a_pc : in std_logic_vector (31 downto 0);
cpi_a_inst : in std_logic_vector (31 downto 0);
cpi_a_cnt : in std_logic_vector (1 downto 0);
cpi_a_trap : in std_logic;
cpi_a_annul : in std_logic;
cpi_a_pv : in std_logic;
cpi_e_pc : in std_logic_vector (31 downto 0);
cpi_e_inst : in std_logic_vector (31 downto 0);
cpi_e_cnt : in std_logic_vector (1 downto 0);
cpi_e_trap : in std_logic;
cpi_e_annul : in std_logic;
cpi_e_pv : in std_logic;
cpi_m_pc : in std_logic_vector (31 downto 0);
cpi_m_inst : in std_logic_vector (31 downto 0);
cpi_m_cnt : in std_logic_vector (1 downto 0);
cpi_m_trap : in std_logic;
cpi_m_annul : in std_logic;
cpi_m_pv : in std_logic;
cpi_x_pc : in std_logic_vector (31 downto 0);
cpi_x_inst : in std_logic_vector (31 downto 0);
cpi_x_cnt : in std_logic_vector (1 downto 0);
cpi_x_trap : in std_logic;
cpi_x_annul : in std_logic;
cpi_x_pv : in std_logic;
cpi_lddata : in std_logic_vector (31 downto 0);
cpi_dbg_enable : in std_logic;
cpi_dbg_write : in std_logic;
cpi_dbg_fsr : in std_logic;
cpi_dbg_addr : in std_logic_vector (4 downto 0);
cpi_dbg_data : in std_logic_vector (31 downto 0);
cpo_data : out std_logic_vector (31 downto 0);
cpo_exc : out std_logic;
cpo_cc : out std_logic_vector (1 downto 0);
cpo_ccv : out std_logic;
cpo_ldlock : out std_logic;
cpo_holdn : out std_logic;
cpo_dbg_data : out std_logic_vector (31 downto 0);
rfi1_rd1addr : out std_logic_vector (3 downto 0);
rfi1_rd2addr : out std_logic_vector (3 downto 0);
rfi1_wraddr : out std_logic_vector (3 downto 0);
rfi1_wrdata : out std_logic_vector (31 downto 0);
rfi1_ren1 : out std_logic;
rfi1_ren2 : out std_logic;
rfi1_wren : out std_logic;
rfi2_rd1addr : out std_logic_vector (3 downto 0);
rfi2_rd2addr : out std_logic_vector (3 downto 0);
rfi2_wraddr : out std_logic_vector (3 downto 0);
rfi2_wrdata : out std_logic_vector (31 downto 0);
rfi2_ren1 : out std_logic;
rfi2_ren2 : out std_logic;
rfi2_wren : out std_logic;
rfo1_data1 : in std_logic_vector (31 downto 0);
rfo1_data2 : in std_logic_vector (31 downto 0);
rfo2_data1 : in std_logic_vector (31 downto 0);
rfo2_data2 : in std_logic_vector (31 downto 0));
end component;
component grfpw_tsmc90
port (
rst : in std_ulogic; -- Reset
clk : in std_ulogic;
holdn : in std_ulogic; -- pipeline hold
cpi_flush : in std_ulogic; -- pipeline flush
cpi_exack : in std_ulogic; -- FP exception acknowledge
cpi_a_rs1 : in std_logic_vector(4 downto 0);
cpi_d_pc : in std_logic_vector(31 downto 0);
cpi_d_inst : in std_logic_vector(31 downto 0);
cpi_d_cnt : in std_logic_vector(1 downto 0);
cpi_d_trap : in std_ulogic;
cpi_d_annul : in std_ulogic;
cpi_d_pv : in std_ulogic;
cpi_a_pc : in std_logic_vector(31 downto 0);
cpi_a_inst : in std_logic_vector(31 downto 0);
cpi_a_cnt : in std_logic_vector(1 downto 0);
cpi_a_trap : in std_ulogic;
cpi_a_annul : in std_ulogic;
cpi_a_pv : in std_ulogic;
cpi_e_pc : in std_logic_vector(31 downto 0);
cpi_e_inst : in std_logic_vector(31 downto 0);
cpi_e_cnt : in std_logic_vector(1 downto 0);
cpi_e_trap : in std_ulogic;
cpi_e_annul : in std_ulogic;
cpi_e_pv : in std_ulogic;
cpi_m_pc : in std_logic_vector(31 downto 0);
cpi_m_inst : in std_logic_vector(31 downto 0);
cpi_m_cnt : in std_logic_vector(1 downto 0);
cpi_m_trap : in std_ulogic;
cpi_m_annul : in std_ulogic;
cpi_m_pv : in std_ulogic;
cpi_x_pc : in std_logic_vector(31 downto 0);
cpi_x_inst : in std_logic_vector(31 downto 0);
cpi_x_cnt : in std_logic_vector(1 downto 0);
cpi_x_trap : in std_ulogic;
cpi_x_annul : in std_ulogic;
cpi_x_pv : in std_ulogic;
cpi_lddata : in std_logic_vector(31 downto 0); -- load data
cpi_dbg_enable : in std_ulogic;
cpi_dbg_write : in std_ulogic;
cpi_dbg_fsr : in std_ulogic; -- FSR access
cpi_dbg_addr : in std_logic_vector(4 downto 0);
cpi_dbg_data : in std_logic_vector(31 downto 0);
cpo_data : out std_logic_vector(31 downto 0); -- store data
cpo_exc : out std_logic; -- FP exception
cpo_cc : out std_logic_vector(1 downto 0); -- FP condition codes
cpo_ccv : out std_ulogic; -- FP condition codes valid
cpo_ldlock : out std_logic; -- FP pipeline hold
cpo_holdn : out std_ulogic;
--cpo_restart : out std_ulogic;
cpo_dbg_data : out std_logic_vector(31 downto 0);
rfi1_rd1addr : out std_logic_vector(3 downto 0);
rfi1_rd2addr : out std_logic_vector(3 downto 0);
rfi1_wraddr : out std_logic_vector(3 downto 0);
rfi1_wrdata : out std_logic_vector(31 downto 0);
rfi1_ren1 : out std_ulogic;
rfi1_ren2 : out std_ulogic;
rfi1_wren : out std_ulogic;
rfi2_rd1addr : out std_logic_vector(3 downto 0);
rfi2_rd2addr : out std_logic_vector(3 downto 0);
rfi2_wraddr : out std_logic_vector(3 downto 0);
rfi2_wrdata : out std_logic_vector(31 downto 0);
rfi2_ren1 : out std_ulogic;
rfi2_ren2 : out std_ulogic;
rfi2_wren : out std_ulogic;
rfo1_data1 : in std_logic_vector(31 downto 0);
rfo1_data2 : in std_logic_vector(31 downto 0);
rfo2_data1 : in std_logic_vector(31 downto 0);
rfo2_data2 : in std_logic_vector(31 downto 0)
);
end component;
component grfpw_tm65gplus
port (
rst : in std_ulogic; -- Reset
clk : in std_ulogic;
holdn : in std_ulogic; -- pipeline hold
cpi_flush : in std_ulogic; -- pipeline flush
cpi_exack : in std_ulogic; -- FP exception acknowledge
cpi_a_rs1 : in std_logic_vector(4 downto 0);
cpi_d_pc : in std_logic_vector(31 downto 0);
cpi_d_inst : in std_logic_vector(31 downto 0);
cpi_d_cnt : in std_logic_vector(1 downto 0);
cpi_d_trap : in std_ulogic;
cpi_d_annul : in std_ulogic;
cpi_d_pv : in std_ulogic;
cpi_a_pc : in std_logic_vector(31 downto 0);
cpi_a_inst : in std_logic_vector(31 downto 0);
cpi_a_cnt : in std_logic_vector(1 downto 0);
cpi_a_trap : in std_ulogic;
cpi_a_annul : in std_ulogic;
cpi_a_pv : in std_ulogic;
cpi_e_pc : in std_logic_vector(31 downto 0);
cpi_e_inst : in std_logic_vector(31 downto 0);
cpi_e_cnt : in std_logic_vector(1 downto 0);
cpi_e_trap : in std_ulogic;
cpi_e_annul : in std_ulogic;
cpi_e_pv : in std_ulogic;
cpi_m_pc : in std_logic_vector(31 downto 0);
cpi_m_inst : in std_logic_vector(31 downto 0);
cpi_m_cnt : in std_logic_vector(1 downto 0);
cpi_m_trap : in std_ulogic;
cpi_m_annul : in std_ulogic;
cpi_m_pv : in std_ulogic;
cpi_x_pc : in std_logic_vector(31 downto 0);
cpi_x_inst : in std_logic_vector(31 downto 0);
cpi_x_cnt : in std_logic_vector(1 downto 0);
cpi_x_trap : in std_ulogic;
cpi_x_annul : in std_ulogic;
cpi_x_pv : in std_ulogic;
cpi_lddata : in std_logic_vector(31 downto 0); -- load data
cpi_dbg_enable : in std_ulogic;
cpi_dbg_write : in std_ulogic;
cpi_dbg_fsr : in std_ulogic; -- FSR access
cpi_dbg_addr : in std_logic_vector(4 downto 0);
cpi_dbg_data : in std_logic_vector(31 downto 0);
cpo_data : out std_logic_vector(31 downto 0); -- store data
cpo_exc : out std_logic; -- FP exception
cpo_cc : out std_logic_vector(1 downto 0); -- FP condition codes
cpo_ccv : out std_ulogic; -- FP condition codes valid
cpo_ldlock : out std_logic; -- FP pipeline hold
cpo_holdn : out std_ulogic;
--cpo_restart : out std_ulogic;
cpo_dbg_data : out std_logic_vector(31 downto 0);
rfi1_rd1addr : out std_logic_vector(3 downto 0);
rfi1_rd2addr : out std_logic_vector(3 downto 0);
rfi1_wraddr : out std_logic_vector(3 downto 0);
rfi1_wrdata : out std_logic_vector(31 downto 0);
rfi1_ren1 : out std_ulogic;
rfi1_ren2 : out std_ulogic;
rfi1_wren : out std_ulogic;
rfi2_rd1addr : out std_logic_vector(3 downto 0);
rfi2_rd2addr : out std_logic_vector(3 downto 0);
rfi2_wraddr : out std_logic_vector(3 downto 0);
rfi2_wrdata : out std_logic_vector(31 downto 0);
rfi2_ren1 : out std_ulogic;
rfi2_ren2 : out std_ulogic;
rfi2_wren : out std_ulogic;
rfo1_data1 : in std_logic_vector(31 downto 0);
rfo1_data2 : in std_logic_vector(31 downto 0);
rfo2_data1 : in std_logic_vector(31 downto 0);
rfo2_data2 : in std_logic_vector(31 downto 0)
);
end component;
component grfpw_cust1
port (
rst : in std_ulogic; -- Reset
clk : in std_ulogic;
holdn : in std_ulogic; -- pipeline hold
cpi_flush : in std_ulogic; -- pipeline flush
cpi_exack : in std_ulogic; -- FP exception acknowledge
cpi_a_rs1 : in std_logic_vector(4 downto 0);
cpi_d_pc : in std_logic_vector(31 downto 0);
cpi_d_inst : in std_logic_vector(31 downto 0);
cpi_d_cnt : in std_logic_vector(1 downto 0);
cpi_d_trap : in std_ulogic;
cpi_d_annul : in std_ulogic;
cpi_d_pv : in std_ulogic;
cpi_a_pc : in std_logic_vector(31 downto 0);
cpi_a_inst : in std_logic_vector(31 downto 0);
cpi_a_cnt : in std_logic_vector(1 downto 0);
cpi_a_trap : in std_ulogic;
cpi_a_annul : in std_ulogic;
cpi_a_pv : in std_ulogic;
cpi_e_pc : in std_logic_vector(31 downto 0);
cpi_e_inst : in std_logic_vector(31 downto 0);
cpi_e_cnt : in std_logic_vector(1 downto 0);
cpi_e_trap : in std_ulogic;
cpi_e_annul : in std_ulogic;
cpi_e_pv : in std_ulogic;
cpi_m_pc : in std_logic_vector(31 downto 0);
cpi_m_inst : in std_logic_vector(31 downto 0);
cpi_m_cnt : in std_logic_vector(1 downto 0);
cpi_m_trap : in std_ulogic;
cpi_m_annul : in std_ulogic;
cpi_m_pv : in std_ulogic;
cpi_x_pc : in std_logic_vector(31 downto 0);
cpi_x_inst : in std_logic_vector(31 downto 0);
cpi_x_cnt : in std_logic_vector(1 downto 0);
cpi_x_trap : in std_ulogic;
cpi_x_annul : in std_ulogic;
cpi_x_pv : in std_ulogic;
cpi_lddata : in std_logic_vector(31 downto 0); -- load data
cpi_dbg_enable : in std_ulogic;
cpi_dbg_write : in std_ulogic;
cpi_dbg_fsr : in std_ulogic; -- FSR access
cpi_dbg_addr : in std_logic_vector(4 downto 0);
cpi_dbg_data : in std_logic_vector(31 downto 0);
cpo_data : out std_logic_vector(31 downto 0); -- store data
cpo_exc : out std_logic; -- FP exception
cpo_cc : out std_logic_vector(1 downto 0); -- FP condition codes
cpo_ccv : out std_ulogic; -- FP condition codes valid
cpo_ldlock : out std_logic; -- FP pipeline hold
cpo_holdn : out std_ulogic;
--cpo_restart : out std_ulogic;
cpo_dbg_data : out std_logic_vector(31 downto 0);
rfi1_rd1addr : out std_logic_vector(3 downto 0);
rfi1_rd2addr : out std_logic_vector(3 downto 0);
rfi1_wraddr : out std_logic_vector(3 downto 0);
rfi1_wrdata : out std_logic_vector(31 downto 0);
rfi1_ren1 : out std_ulogic;
rfi1_ren2 : out std_ulogic;
rfi1_wren : out std_ulogic;
rfi2_rd1addr : out std_logic_vector(3 downto 0);
rfi2_rd2addr : out std_logic_vector(3 downto 0);
rfi2_wraddr : out std_logic_vector(3 downto 0);
rfi2_wrdata : out std_logic_vector(31 downto 0);
rfi2_ren1 : out std_ulogic;
rfi2_ren2 : out std_ulogic;
rfi2_wren : out std_ulogic;
rfo1_data1 : in std_logic_vector(31 downto 0);
rfo1_data2 : in std_logic_vector(31 downto 0);
rfo2_data1 : in std_logic_vector(31 downto 0);
rfo2_data2 : in std_logic_vector(31 downto 0)
);
end component;
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of u0_tsmc90 : label is TRUE;
attribute DONT_TOUCH of u0_tm65gplus : label is TRUE;
-- signal disasen : std_logic;
begin
-- disasen <= '1' when disas /= 0 else '0';
uni : if (is_unisim(tech) = 1) generate
grfpw0 : grfpw_0_unisim
port map (rst, clk, holdn, cpi_flush, cpi_exack, cpi_a_rs1, cpi_d_pc,
cpi_d_inst, cpi_d_cnt, cpi_d_trap, cpi_d_annul, cpi_d_pv, cpi_a_pc,
cpi_a_inst, cpi_a_cnt, cpi_a_trap, cpi_a_annul, cpi_a_pv, cpi_e_pc,
cpi_e_inst, cpi_e_cnt, cpi_e_trap, cpi_e_annul, cpi_e_pv, cpi_m_pc,
cpi_m_inst, cpi_m_cnt, cpi_m_trap, cpi_m_annul, cpi_m_pv, cpi_x_pc,
cpi_x_inst, cpi_x_cnt, cpi_x_trap, cpi_x_annul, cpi_x_pv, cpi_lddata,
cpi_dbg_enable, cpi_dbg_write, cpi_dbg_fsr, cpi_dbg_addr, cpi_dbg_data,
cpo_data, cpo_exc, cpo_cc, cpo_ccv, cpo_ldlock, cpo_holdn, cpo_dbg_data,
rfi1_rd1addr, rfi1_rd2addr, rfi1_wraddr, rfi1_wrdata, rfi1_ren1,
rfi1_ren2, rfi1_wren, rfi2_rd1addr, rfi2_rd2addr, rfi2_wraddr,
rfi2_wrdata, rfi2_ren1, rfi2_ren2, rfi2_wren, rfo1_data1,
rfo1_data2, rfo2_data1, rfo2_data2);--, disasen);
end generate;
alt : if (tech = altera) generate -- Cyclone, Stratix V, Cyclone V
grfpw0 : grfpw_0_altera
port map (rst, clk, holdn, cpi_flush, cpi_exack, cpi_a_rs1, cpi_d_pc,
cpi_d_inst, cpi_d_cnt, cpi_d_trap, cpi_d_annul, cpi_d_pv, cpi_a_pc,
cpi_a_inst, cpi_a_cnt, cpi_a_trap, cpi_a_annul, cpi_a_pv, cpi_e_pc,
cpi_e_inst, cpi_e_cnt, cpi_e_trap, cpi_e_annul, cpi_e_pv, cpi_m_pc,
cpi_m_inst, cpi_m_cnt, cpi_m_trap, cpi_m_annul, cpi_m_pv, cpi_x_pc,
cpi_x_inst, cpi_x_cnt, cpi_x_trap, cpi_x_annul, cpi_x_pv, cpi_lddata,
cpi_dbg_enable, cpi_dbg_write, cpi_dbg_fsr, cpi_dbg_addr, cpi_dbg_data,
cpo_data, cpo_exc, cpo_cc, cpo_ccv, cpo_ldlock, cpo_holdn, cpo_dbg_data,
rfi1_rd1addr, rfi1_rd2addr, rfi1_wraddr, rfi1_wrdata, rfi1_ren1,
rfi1_ren2, rfi1_wren, rfi2_rd1addr, rfi2_rd2addr, rfi2_wraddr,
rfi2_wrdata, rfi2_ren1, rfi2_ren2, rfi2_wren, rfo1_data1,
rfo1_data2, rfo2_data1, rfo2_data2 );
end generate;
strtx : if (tech = stratix1) or (tech = stratix2) generate
grfpw0 : grfpw_0_stratixii
port map (rst, clk, holdn, cpi_flush, cpi_exack, cpi_a_rs1, cpi_d_pc,
cpi_d_inst, cpi_d_cnt, cpi_d_trap, cpi_d_annul, cpi_d_pv, cpi_a_pc,
cpi_a_inst, cpi_a_cnt, cpi_a_trap, cpi_a_annul, cpi_a_pv, cpi_e_pc,
cpi_e_inst, cpi_e_cnt, cpi_e_trap, cpi_e_annul, cpi_e_pv, cpi_m_pc,
cpi_m_inst, cpi_m_cnt, cpi_m_trap, cpi_m_annul, cpi_m_pv, cpi_x_pc,
cpi_x_inst, cpi_x_cnt, cpi_x_trap, cpi_x_annul, cpi_x_pv, cpi_lddata,
cpi_dbg_enable, cpi_dbg_write, cpi_dbg_fsr, cpi_dbg_addr, cpi_dbg_data,
cpo_data, cpo_exc, cpo_cc, cpo_ccv, cpo_ldlock, cpo_holdn, cpo_dbg_data,
rfi1_rd1addr, rfi1_rd2addr, rfi1_wraddr, rfi1_wrdata, rfi1_ren1,
rfi1_ren2, rfi1_wren, rfi2_rd1addr, rfi2_rd2addr, rfi2_wraddr,
rfi2_wrdata, rfi2_ren1, rfi2_ren2, rfi2_wren, rfo1_data1,
rfo1_data2, rfo2_data1, rfo2_data2 );
end generate;
strtxiii : if (tech = stratix3) or (tech = stratix4) generate
grfpw0 : grfpw_0_stratixiii
port map (rst, clk, holdn, cpi_flush, cpi_exack, cpi_a_rs1, cpi_d_pc,
cpi_d_inst, cpi_d_cnt, cpi_d_trap, cpi_d_annul, cpi_d_pv, cpi_a_pc,
cpi_a_inst, cpi_a_cnt, cpi_a_trap, cpi_a_annul, cpi_a_pv, cpi_e_pc,
cpi_e_inst, cpi_e_cnt, cpi_e_trap, cpi_e_annul, cpi_e_pv, cpi_m_pc,
cpi_m_inst, cpi_m_cnt, cpi_m_trap, cpi_m_annul, cpi_m_pv, cpi_x_pc,
cpi_x_inst, cpi_x_cnt, cpi_x_trap, cpi_x_annul, cpi_x_pv, cpi_lddata,
cpi_dbg_enable, cpi_dbg_write, cpi_dbg_fsr, cpi_dbg_addr, cpi_dbg_data,
cpo_data, cpo_exc, cpo_cc, cpo_ccv, cpo_ldlock, cpo_holdn, cpo_dbg_data,
rfi1_rd1addr, rfi1_rd2addr, rfi1_wraddr, rfi1_wrdata, rfi1_ren1,
rfi1_ren2, rfi1_wren, rfi2_rd1addr, rfi2_rd2addr, rfi2_wraddr,
rfi2_wrdata, rfi2_ren1, rfi2_ren2, rfi2_wren, rfo1_data1,
rfo1_data2, rfo2_data1, rfo2_data2 );
end generate;
cyc3 : if (tech = cyclone3) generate
grfpw0 : grfpw_0_cycloneiii
port map (rst, clk, holdn, cpi_flush, cpi_exack, cpi_a_rs1, cpi_d_pc,
cpi_d_inst, cpi_d_cnt, cpi_d_trap, cpi_d_annul, cpi_d_pv, cpi_a_pc,
cpi_a_inst, cpi_a_cnt, cpi_a_trap, cpi_a_annul, cpi_a_pv, cpi_e_pc,
cpi_e_inst, cpi_e_cnt, cpi_e_trap, cpi_e_annul, cpi_e_pv, cpi_m_pc,
cpi_m_inst, cpi_m_cnt, cpi_m_trap, cpi_m_annul, cpi_m_pv, cpi_x_pc,
cpi_x_inst, cpi_x_cnt, cpi_x_trap, cpi_x_annul, cpi_x_pv, cpi_lddata,
cpi_dbg_enable, cpi_dbg_write, cpi_dbg_fsr, cpi_dbg_addr, cpi_dbg_data,
cpo_data, cpo_exc, cpo_cc, cpo_ccv, cpo_ldlock, cpo_holdn, cpo_dbg_data,
rfi1_rd1addr, rfi1_rd2addr, rfi1_wraddr, rfi1_wrdata, rfi1_ren1,
rfi1_ren2, rfi1_wren, rfi2_rd1addr, rfi2_rd2addr, rfi2_wraddr,
rfi2_wrdata, rfi2_ren1, rfi2_ren2, rfi2_wren, rfo1_data1,
rfo1_data2, rfo2_data1, rfo2_data2 );
end generate;
u0_tsmc90 : if tech = tsmc90 generate
grfpw0 : grfpw_tsmc90
port map (rst, clk, holdn, cpi_flush, cpi_exack, cpi_a_rs1, cpi_d_pc,
cpi_d_inst, cpi_d_cnt, cpi_d_trap, cpi_d_annul, cpi_d_pv, cpi_a_pc,
cpi_a_inst, cpi_a_cnt, cpi_a_trap, cpi_a_annul, cpi_a_pv, cpi_e_pc,
cpi_e_inst, cpi_e_cnt, cpi_e_trap, cpi_e_annul, cpi_e_pv, cpi_m_pc,
cpi_m_inst, cpi_m_cnt, cpi_m_trap, cpi_m_annul, cpi_m_pv, cpi_x_pc,
cpi_x_inst, cpi_x_cnt, cpi_x_trap, cpi_x_annul, cpi_x_pv, cpi_lddata,
cpi_dbg_enable, cpi_dbg_write, cpi_dbg_fsr, cpi_dbg_addr, cpi_dbg_data,
cpo_data, cpo_exc, cpo_cc, cpo_ccv, cpo_ldlock, cpo_holdn, cpo_dbg_data,
rfi1_rd1addr, rfi1_rd2addr, rfi1_wraddr, rfi1_wrdata, rfi1_ren1,
rfi1_ren2, rfi1_wren, rfi2_rd1addr, rfi2_rd2addr, rfi2_wraddr,
rfi2_wrdata, rfi2_ren1, rfi2_ren2, rfi2_wren, rfo1_data1,
rfo1_data2, rfo2_data1, rfo2_data2 );
end generate;
u0_tm65gplus : if tech = tm65gplus generate
grfpw0 : grfpw_tm65gplus
port map (rst, clk, holdn, cpi_flush, cpi_exack, cpi_a_rs1, cpi_d_pc,
cpi_d_inst, cpi_d_cnt, cpi_d_trap, cpi_d_annul, cpi_d_pv, cpi_a_pc,
cpi_a_inst, cpi_a_cnt, cpi_a_trap, cpi_a_annul, cpi_a_pv, cpi_e_pc,
cpi_e_inst, cpi_e_cnt, cpi_e_trap, cpi_e_annul, cpi_e_pv, cpi_m_pc,
cpi_m_inst, cpi_m_cnt, cpi_m_trap, cpi_m_annul, cpi_m_pv, cpi_x_pc,
cpi_x_inst, cpi_x_cnt, cpi_x_trap, cpi_x_annul, cpi_x_pv, cpi_lddata,
cpi_dbg_enable, cpi_dbg_write, cpi_dbg_fsr, cpi_dbg_addr, cpi_dbg_data,
cpo_data, cpo_exc, cpo_cc, cpo_ccv, cpo_ldlock, cpo_holdn, cpo_dbg_data,
rfi1_rd1addr, rfi1_rd2addr, rfi1_wraddr, rfi1_wrdata, rfi1_ren1,
rfi1_ren2, rfi1_wren, rfi2_rd1addr, rfi2_rd2addr, rfi2_wraddr,
rfi2_wrdata, rfi2_ren1, rfi2_ren2, rfi2_wren, rfo1_data1,
rfo1_data2, rfo2_data1, rfo2_data2 );
end generate;
u0_cust1 : if tech = custom1 generate
grfpw0 : grfpw_cust1
port map (rst, clk, holdn, cpi_flush, cpi_exack, cpi_a_rs1, cpi_d_pc,
cpi_d_inst, cpi_d_cnt, cpi_d_trap, cpi_d_annul, cpi_d_pv, cpi_a_pc,
cpi_a_inst, cpi_a_cnt, cpi_a_trap, cpi_a_annul, cpi_a_pv, cpi_e_pc,
cpi_e_inst, cpi_e_cnt, cpi_e_trap, cpi_e_annul, cpi_e_pv, cpi_m_pc,
cpi_m_inst, cpi_m_cnt, cpi_m_trap, cpi_m_annul, cpi_m_pv, cpi_x_pc,
cpi_x_inst, cpi_x_cnt, cpi_x_trap, cpi_x_annul, cpi_x_pv, cpi_lddata,
cpi_dbg_enable, cpi_dbg_write, cpi_dbg_fsr, cpi_dbg_addr, cpi_dbg_data,
cpo_data, cpo_exc, cpo_cc, cpo_ccv, cpo_ldlock, cpo_holdn, cpo_dbg_data,
rfi1_rd1addr, rfi1_rd2addr, rfi1_wraddr, rfi1_wrdata, rfi1_ren1,
rfi1_ren2, rfi1_wren, rfi2_rd1addr, rfi2_rd2addr, rfi2_wraddr,
rfi2_wrdata, rfi2_ren1, rfi2_ren2, rfi2_wren, rfo1_data1,
rfo1_data2, rfo2_data1, rfo2_data2 );
end generate;
end;
| gpl-3.0 |
EliasLuiz/TCC | Leon3/lib/gaisler/misc/ahbtrace_mb.vhd | 1 | 3199 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ahbtrace_mb
-- File: ahbtrace_mb.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Modified: Jan Andersson - Aeroflex Gaisler
-- Description: AHB trace unit that can have registers on a separate bus
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.misc.all;
entity ahbtrace_mb is
generic (
hindex : integer := 0;
ioaddr : integer := 16#000#;
iomask : integer := 16#E00#;
tech : integer := DEFMEMTECH;
irq : integer := 0;
kbytes : integer := 1;
bwidth : integer := 32;
ahbfilt : integer := 0;
scantest : integer range 0 to 1 := 0;
exttimer : integer range 0 to 1 := 0;
exten : integer range 0 to 1 := 0);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type; -- Register interface
ahbso : out ahb_slv_out_type;
tahbmi : in ahb_mst_in_type; -- Trace
tahbsi : in ahb_slv_in_type;
timer : in std_logic_vector(30 downto 0) := (others => '0');
astat : out amba_stat_type;
resen : in std_ulogic := '0'
);
end;
architecture rtl of ahbtrace_mb is
signal tahbmiv : ahb_mst_in_vector_type(0 to 0);
signal tahbsiv : ahb_slv_in_vector_type(0 to 0);
begin
tahbmiv(0) <= tahbmi;
tahbsiv(0) <= tahbsi;
ahbt0 : ahbtrace_mmb
generic map (
hindex => hindex,
ioaddr => ioaddr,
iomask => iomask,
tech => tech,
irq => irq,
kbytes => kbytes,
bwidth => bwidth,
ahbfilt => ahbfilt,
ntrace => 1,
scantest => scantest,
exttimer => exttimer,
exten => exten)
port map(
rst => rst,
clk => clk,
ahbsi => ahbsi,
ahbso => ahbso,
tahbmiv => tahbmiv,
tahbsiv => tahbsiv,
timer => timer,
astat => astat,
resen => resen);
end;
| gpl-3.0 |
hoglet67/CoPro6502 | src/T6502/T65.vhd | 1 | 21852 | -- ****
-- T65(b) core. In an effort to merge and maintain bug fixes ....
--
-- Ver 303 ost(ML) July 2014
-- (Sorry for some scratchpad comments that may make little sense)
-- Mods and some 6502 undocumented instructions.
--
-- Not correct opcodes acc. to Lorenz tests (incomplete list):
-- NOPN (nop)
-- NOPZX (nop + byte 172)
-- NOPAX (nop + word da ... da: byte 0)
-- ASOZ (byte $07 + byte 172)
--
-- Wolfgang April 2014
-- Ver 303 Bugfixes for NMI from foft
-- Ver 302 Bugfix for BRK command
-- Wolfgang January 2014
-- Ver 301 more merging
-- Ver 300 Bugfixes by ehenciak added, started tidyup *bust*
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- ****
--
-- 65xx compatible microprocessor core
--
-- Version : 0246
--
-- Copyright (c) 2002 Daniel Wallner ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t65/
--
-- Limitations :
--
-- 65C02 and 65C816 modes are incomplete
-- Undocumented instructions are not supported
-- Some interface signals behaves incorrect
--
-- File history :
--
-- 0246 : First release
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.T65_Pack.all;
-- ehenciak 2-23-2005 : Added the enable signal so that one doesn't have to use
-- the ready signal to limit the CPU.
entity T65 is
port(
Mode : in std_logic_vector(1 downto 0); -- "00" => 6502, "01" => 65C02, "10" => 65C816
Res_n : in std_logic;
Enable : in std_logic;
Clk : in std_logic;
Rdy : in std_logic;
Abort_n : in std_logic;
IRQ_n : in std_logic;
NMI_n : in std_logic;
SO_n : in std_logic;
R_W_n : out std_logic;
Sync : out std_logic;
EF : out std_logic;
MF : out std_logic;
XF : out std_logic;
ML_n : out std_logic;
VP_n : out std_logic;
VDA : out std_logic;
VPA : out std_logic;
A : out std_logic_vector(23 downto 0);
DI : in std_logic_vector(7 downto 0);--NOTE:Make sure DI equals DO when writing. This is important for DCP/DCM undoc instruction. TODO:convert to inout
DO : out std_logic_vector(7 downto 0)
);
end T65;
architecture rtl of T65 is
-- Registers
signal ABC, X, Y, D : std_logic_vector(15 downto 0);
signal P, AD, DL : std_logic_vector(7 downto 0) := x"00";
signal PwithB : std_logic_vector(7 downto 0);--ML:New way to push P with correct B state to stack
signal BAH : std_logic_vector(7 downto 0);
signal BAL : std_logic_vector(8 downto 0);
signal PBR : std_logic_vector(7 downto 0);
signal DBR : std_logic_vector(7 downto 0);
signal PC : unsigned(15 downto 0);
signal S : unsigned(15 downto 0);
signal EF_i : std_logic;
signal MF_i : std_logic;
signal XF_i : std_logic;
signal IR : std_logic_vector(7 downto 0);
signal MCycle : std_logic_vector(2 downto 0);
signal Mode_r : std_logic_vector(1 downto 0);
signal ALU_Op_r : T_ALU_Op;
signal Write_Data_r : T_Write_Data;
signal Set_Addr_To_r : T_Set_Addr_To;
signal PCAdder : unsigned(8 downto 0);
signal RstCycle : std_logic;
signal IRQCycle : std_logic;
signal NMICycle : std_logic;
signal SO_n_o : std_logic;
signal IRQ_n_o : std_logic;
signal NMI_n_o : std_logic;
signal NMIAct : std_logic;
signal Break : std_logic;
-- ALU signals
signal BusA : std_logic_vector(7 downto 0);
signal BusA_r : std_logic_vector(7 downto 0);
signal BusB : std_logic_vector(7 downto 0);
signal ALU_Q : std_logic_vector(7 downto 0);
signal P_Out : std_logic_vector(7 downto 0);
-- Micro code outputs
signal LCycle : std_logic_vector(2 downto 0);
signal ALU_Op : T_ALU_Op;
signal Set_BusA_To : T_Set_BusA_To;
signal Set_Addr_To : T_Set_Addr_To;
signal Write_Data : T_Write_Data;
signal Jump : std_logic_vector(1 downto 0);
signal BAAdd : std_logic_vector(1 downto 0);
signal BreakAtNA : std_logic;
signal ADAdd : std_logic;
signal AddY : std_logic;
signal PCAdd : std_logic;
signal Inc_S : std_logic;
signal Dec_S : std_logic;
signal LDA : std_logic;
signal LDP : std_logic;
signal LDX : std_logic;
signal LDY : std_logic;
signal LDS : std_logic;
signal LDDI : std_logic;
signal LDALU : std_logic;
signal LDAD : std_logic;
signal LDBAL : std_logic;
signal LDBAH : std_logic;
signal SaveP : std_logic;
signal Write : std_logic;
signal ALUmore : std_logic;
signal really_rdy : std_logic;
signal R_W_n_i : std_logic;
signal R_W_n_i_d : std_logic;
signal NMIActClear : std_logic; -- MWW hack
begin
-- workaround for ready-handling
-- ehenciak : Drive R_W_n_i off chip.
R_W_n <= R_W_n_i;
-- ehenciak : gate Rdy with read/write to make an "OK, it's
-- really OK to stop the processor now if Rdy is
-- deasserted" signal
really_rdy <= Rdy or not(R_W_n_i);
----
Sync <= '1' when MCycle = "000" else '0';
EF <= EF_i;
MF <= MF_i;
XF <= XF_i;
ML_n <= '0' when IR(7 downto 6) /= "10" and IR(2 downto 1) = "11" and MCycle(2 downto 1) /= "00" else '1';
VP_n <= '0' when IRQCycle = '1' and (MCycle = "101" or MCycle = "110") else '1';
VDA <= '1' when Set_Addr_To_r /= Set_Addr_To_PBR else '0'; -- Incorrect !!!!!!!!!!!!
VPA <= '1' when Jump(1) = '0' else '0'; -- Incorrect !!!!!!!!!!!!
mcode : T65_MCode
port map(
--inputs
Mode => Mode_r,
IR => IR,
MCycle => MCycle,
P => P,
--outputs
LCycle => LCycle,
ALU_Op => ALU_Op,
Set_BusA_To => Set_BusA_To,
Set_Addr_To => Set_Addr_To,
Write_Data => Write_Data,
Jump => Jump,
BAAdd => BAAdd,
BreakAtNA => BreakAtNA,
ADAdd => ADAdd,
AddY => AddY,
PCAdd => PCAdd,
Inc_S => Inc_S,
Dec_S => Dec_S,
LDA => LDA,
LDP => LDP,
LDX => LDX,
LDY => LDY,
LDS => LDS,
LDDI => LDDI,
LDALU => LDALU,
LDAD => LDAD,
LDBAL => LDBAL,
LDBAH => LDBAH,
SaveP => SaveP,
ALUmore => ALUmore,
Write => Write
);
alu : T65_ALU
port map(
Mode => Mode_r,
Op => ALU_Op_r,
BusA => BusA_r,
BusB => BusB,
P_In => P,
P_Out => P_Out,
Q => ALU_Q
);
process (Res_n, Clk)
begin
if Res_n = '0' then
PC <= (others => '0'); -- Program Counter
IR <= "00000000";
S <= (others => '0'); -- Dummy !!!!!!!!!!!!!!!!!!!!!
D <= (others => '0');
PBR <= (others => '0');
DBR <= (others => '0');
Mode_r <= (others => '0');
ALU_Op_r <= ALU_OP_BIT;
Write_Data_r <= Write_Data_DL;
Set_Addr_To_r <= Set_Addr_To_PBR;
R_W_n_i <= '1';
EF_i <= '1';
MF_i <= '1';
XF_i <= '1';
elsif Clk'event and Clk = '1' then
if (Enable = '1') then
if (really_rdy = '1') then
R_W_n_i <= not Write or RstCycle;
D <= (others => '1'); -- Dummy
PBR <= (others => '1'); -- Dummy
DBR <= (others => '1'); -- Dummy
EF_i <= '0'; -- Dummy
MF_i <= '0'; -- Dummy
XF_i <= '0'; -- Dummy
if MCycle = "000" then
Mode_r <= Mode;
if IRQCycle = '0' and NMICycle = '0' then
PC <= PC + 1;
end if;
if IRQCycle = '1' or NMICycle = '1' then
IR <= "00000000";
else
IR <= DI;
end if;
end if;
ALU_Op_r <= ALU_Op;
Write_Data_r <= Write_Data;
if Break = '1' then
Set_Addr_To_r <= Set_Addr_To_PBR;
else
Set_Addr_To_r <= Set_Addr_To;
end if;
if Inc_S = '1' then
S <= S + 1;
end if;
if Dec_S = '1' and RstCycle = '0' then
S <= S - 1;
end if;
if LDS = '1' then
S(7 downto 0) <= unsigned(ALU_Q);
end if;
if IR = "00000000" and MCycle = "001" and IRQCycle = '0' and NMICycle = '0' then
PC <= PC + 1;
end if;
--
-- jump control logic
--
case Jump is
when "01" =>
PC <= PC + 1;
when "10" =>
PC <= unsigned(DI & DL);
when "11" =>
if PCAdder(8) = '1' then
if DL(7) = '0' then
PC(15 downto 8) <= PC(15 downto 8) + 1;
else
PC(15 downto 8) <= PC(15 downto 8) - 1;
end if;
end if;
PC(7 downto 0) <= PCAdder(7 downto 0);
when others => null;
end case;
end if;
end if;
end if;
end process;
PCAdder <= resize(PC(7 downto 0),9) + resize(unsigned(DL(7) & DL),9) when PCAdd = '1'
else "0" & PC(7 downto 0);
process (Res_n, Clk)
variable tmpP:std_logic_vector(7 downto 0);--ML:Lets try to handle loading P at mcycle=0 and set/clk flags at same cycle
begin
if Res_n = '0' then
P <= x"00"; -- ensure we have nothing set on reset (e.g. B flag!)
elsif Clk'event and Clk = '1' then
tmpP:=P;
if (Enable = '1') then
if (really_rdy = '1') then
if MCycle = "000" then
if LDA = '1' then
ABC(7 downto 0) <= ALU_Q;
end if;
if LDX = '1' then
X(7 downto 0) <= ALU_Q;
end if;
if LDY = '1' then
Y(7 downto 0) <= ALU_Q;
end if;
if (LDA or LDX or LDY) = '1' then
-- P <= P_Out;-- Replaced with:
tmpP:=P_Out;
end if;
end if;
if SaveP = '1' then
-- P <= P_Out;-- Replaced with:
tmpP:=P_Out;
end if;
if LDP = '1' then
-- P <= ALU_Q;-- Replaced with: --ML:no need anymore: AND x"EF"; -- NEVER set B on RTI and PLP
tmpP:=ALU_Q;
end if;
if IR(4 downto 0) = "11000" then
case IR(7 downto 5) is
when "000" =>--0x18(clc)
-- P(Flag_C) <= '0';-- Replaced with:
tmpP(Flag_C) := '0';
when "001" =>--0x38(sec)
-- P(Flag_C) <= '1';
tmpP(Flag_C) := '1';
when "010" =>--0x58(cli)
-- P(Flag_I) <= '0';
tmpP(Flag_I) := '0';
when "011" =>--0x78(sei)
-- P(Flag_I) <= '1';
tmpP(Flag_I) := '1';
when "101" =>--0xb8(clv)
-- P(Flag_V) <= '0';
tmpP(Flag_V) := '0';
when "110" =>--0xd8(cld)
-- P(Flag_D) <= '0';
tmpP(Flag_D) := '0';
when "111" =>--0xf8(sed)
-- P(Flag_D) <= '1';
tmpP(Flag_D) := '1';
when others =>
end case;
end if;
--ML:Removed change of B flag, its constant '1' in P
--ML:The B flag appears to be locked to '1', but when pushed to stack, the SR data on the stack has the B flag cleared on interrupts, set on BRK instr.
--ML:The state of the B flag on warm reset apparently is unchanged (not confirmed, please do if you know)
--ML:The state of the B flag on cold reset is uncertain, but my guess would be set, unless it can be used to detect cold from warm reset.
--Since we cant (well, won't) simulate B=0 on cold reset, we just behave as if it was constant 1.
-- P(Flag_B) <= '1';
tmpP(Flag_B) := '1';
-- if IR = "00000000" and MCycle = "011" and RstCycle = '0' and NMICycle = '0' and IRQCycle = '0' then -- BRK
-- P(Flag_B) <= '1';
-- elsif IR = "00001000" then -- PHP
-- P(Flag_B) <= '1';
-- else
-- P(Flag_B) <= '0'; --> not the best way, but we keep B zero except for BRK and PHP opcodes
-- end if;
if IR = "00000000" and MCycle = "100" and RstCycle = '0' then --and (NMICycle = '1' or IRQCycle = '1') then
--This should happen after P has been pushed to stack
-- P(Flag_I) <= '1';
tmpP(Flag_I) := '1';
end if;
if SO_n_o = '1' and SO_n = '0' then
-- P(Flag_V) <= '1';
tmpP(Flag_V) := '1';
end if;
if RstCycle = '1' then
-- P(Flag_I) <= '0';
-- P(Flag_D) <= '0';
tmpP(Flag_I) := '0';
tmpP(Flag_D) := '0';
end if;
-- P(Flag_1) <= '1';
tmpP(Flag_1) := '1';
P<=tmpP;--new way
SO_n_o <= SO_n;
IRQ_n_o <= IRQ_n;
end if;
NMI_n_o <= NMI_n; -- MWW: detect nmi even if not rdy
end if;
end if;
end process;
---------------------------------------------------------------------------
--
-- Buses
--
---------------------------------------------------------------------------
process (Res_n, Clk)
begin
if Res_n = '0' then
BusA_r <= (others => '0');
BusB <= (others => '0');
AD <= (others => '0');
BAL <= (others => '0');
BAH <= (others => '0');
DL <= (others => '0');
elsif Clk'event and Clk = '1' then
if (Enable = '1') then
if (really_rdy = '1') then
--if (Rdy = '1') then
BusA_r <= BusA;
if ALUmore='1' then
BusB <= ALU_Q;
else
BusB <= DI;
end if;
case BAAdd is
when "01" =>
-- BA Inc
AD <= std_logic_vector(unsigned(AD) + 1);
BAL <= std_logic_vector(unsigned(BAL) + 1);
when "10" =>
-- BA Add
BAL <= std_logic_vector(resize(unsigned(BAL(7 downto 0)),9) + resize(unsigned(BusA),9));
when "11" =>
-- BA Adj
if BAL(8) = '1' then
BAH <= std_logic_vector(unsigned(BAH) + 1);
end if;
when others =>
end case;
-- ehenciak : modified to use Y register as well (bugfix)
if ADAdd = '1' then
if (AddY = '1') then
AD <= std_logic_vector(unsigned(AD) + unsigned(Y(7 downto 0)));
else
AD <= std_logic_vector(unsigned(AD) + unsigned(X(7 downto 0)));
end if;
end if;
NMIActClear <= '0';
if IR = "00000000" then
BAL <= (others => '1');
BAH <= (others => '1');
if RstCycle = '1' then
BAL(2 downto 0) <= "100";
elsif NMICycle = '1' then
BAL(2 downto 0) <= "010";
elsif NMIAct = '1' then -- MWW, force this to be changed by NMI, even if in midstream IRQ/brk
BAL(2 downto 0) <= "010";
NMIActClear <= '1';
else
BAL(2 downto 0) <= "110";
end if;
if Set_addr_To_r = Set_Addr_To_BA then
BAL(0) <= '1';
end if;
end if;
if LDDI = '1' then
DL <= DI;
end if;
if LDALU = '1' then
DL <= ALU_Q;
end if;
if LDAD = '1' then
AD <= DI;
end if;
if LDBAL = '1' then
BAL(7 downto 0) <= DI;
end if;
if LDBAH = '1' then
BAH <= DI;
end if;
end if;
end if;
end if;
end process;
Break <= (BreakAtNA and not BAL(8)) or (PCAdd and not PCAdder(8));
with Set_BusA_To select
BusA <=
DI when Set_BusA_To_DI,
ABC(7 downto 0) when Set_BusA_To_ABC,
X(7 downto 0) when Set_BusA_To_X,
Y(7 downto 0) when Set_BusA_To_Y,
std_logic_vector(S(7 downto 0)) when Set_BusA_To_S,
P when Set_BusA_To_P,
(others => '-') when Set_BusA_To_DONTCARE;--Can probably remove this
with Set_Addr_To_r select
A <=
"0000000000000001" & std_logic_vector(S(7 downto 0)) when Set_Addr_To_S,
DBR & "00000000" & AD when Set_Addr_To_AD,
"00000000" & BAH & BAL(7 downto 0) when Set_Addr_To_BA,
PBR & std_logic_vector(PC(15 downto 8)) & std_logic_vector(PCAdder(7 downto 0)) when Set_Addr_To_PBR;
--ML:This is the P that gets pushed on stack with correct B flag. I'm not sure if NMI also clears B, but I guess it does.
PwithB<=(P and x"ef") when (IRQCycle='1' or NMICycle='1') else P;
with Write_Data_r select
DO <=
DL when Write_Data_DL,
ABC(7 downto 0) when Write_Data_ABC,
X(7 downto 0) when Write_Data_X,
Y(7 downto 0) when Write_Data_Y,
std_logic_vector(S(7 downto 0)) when Write_Data_S,
PwithB when Write_Data_P,
std_logic_vector(PC(7 downto 0)) when Write_Data_PCL,
std_logic_vector(PC(15 downto 8)) when Write_Data_PCH,
(others=>'-') when Write_Data_DONTCARE;--Can probably remove this
-------------------------------------------------------------------------
--
-- Main state machine
--
-------------------------------------------------------------------------
process (Res_n, Clk)
begin
if Res_n = '0' then
MCycle <= "001";
RstCycle <= '1';
IRQCycle <= '0';
NMICycle <= '0';
NMIAct <= '0';
elsif Clk'event and Clk = '1' then
if (Enable = '1') then
if (really_rdy = '1') then
if (NMIActClear = '1') then
NMIAct <= '0';
end if;
if MCycle = LCycle or Break = '1' then
MCycle <= "000";
RstCycle <= '0';
IRQCycle <= '0';
NMICycle <= '0';
if NMIAct = '1' then
NMICycle <= '1';
elsif IRQ_n_o = '0' and P(Flag_I) = '0' then
IRQCycle <= '1';
end if;
else
MCycle <= std_logic_vector(unsigned(MCycle) + 1);
end if;
if NMICycle = '1' then
NMIAct <= '0';
end if;
end if;
if NMI_n_o = '1' and NMI_n = '0' then -- MWW: detect nmi even if not rdy
NMIAct <= '1';
end if;
end if;
end if;
end process;
end;
| gpl-3.0 |
EliasLuiz/TCC | Leon3/lib/tech/dware/simprims/DW_Foundation_comp_arith.vhd | 4 | 2072 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_misc.all;
package DW_Foundation_comp_arith is
component DW_mult_pipe
generic (
a_width : positive; -- multiplier word width
b_width : positive; -- multiplicand word width
num_stages : positive := 2; -- number of pipeline stages
stall_mode : natural range 0 to 1 := 1; -- '0': non-stallable; '1': stallable
rst_mode : natural range 0 to 2 := 1; -- '0': none; '1': async; '2': sync
op_iso_mode : natural range 0 to 4 := 0); -- '0': apply Power Compiler user setting; '1': noop; '2': and; '3': or; '4' preferred style...'and'
port (
clk : in std_logic; -- register clock
rst_n : in std_logic; -- register reset
en : in std_logic; -- register enable
tc : in std_logic; -- '0' : unsigned, '1' : signed
a : in std_logic_vector(a_width-1 downto 0); -- multiplier
b : in std_logic_vector(b_width-1 downto 0); -- multiplicand
product : out std_logic_vector(a_width+b_width-1 downto 0)); -- product
end component;
component DW02_mult
generic( A_width: NATURAL; -- multiplier wordlength
B_width: NATURAL); -- multiplicand wordlength
port(A : in std_logic_vector(A_width-1 downto 0);
B : in std_logic_vector(B_width-1 downto 0);
TC : in std_logic; -- signed -> '1', unsigned -> '0'
PRODUCT : out std_logic_vector(A_width+B_width-1 downto 0));
end component;
component DW02_mult_2_stage
generic( A_width: POSITIVE; -- multiplier wordlength
B_width: POSITIVE); -- multiplicand wordlength
port(A : in std_logic_vector(A_width-1 downto 0);
B : in std_logic_vector(B_width-1 downto 0);
TC : in std_logic; -- signed -> '1', unsigned -> '0'
CLK : in std_logic; -- clock for the stage registers.
PRODUCT : out std_logic_vector(A_width+B_width-1 downto 0));
end component;
end;
| gpl-3.0 |
EliasLuiz/TCC | Leon3/lib/esa/memoryctrl/mctrl.vhd | 4 | 36435 |
----------------------------------------------------------------------------
-- This file is a part of the LEON VHDL model
-- Copyright (C) 1999 European Space Agency (ESA)
--
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2 of the License, or (at your option) any later version.
--
-- See the file COPYING.LGPL for the full details of the license.
-----------------------------------------------------------------------------
-- Entity: mctrl
-- File: mctrl.vhd
-- Author: Jiri Gaisler - ESA/ESTEC
-- Description: External memory controller.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.devices.all;
use grlib.stdlib.all;
library gaisler;
use gaisler.memctrl.all;
library esa;
use esa.memoryctrl.all;
entity mctrl is
generic (
hindex : integer := 0;
pindex : integer := 0;
romaddr : integer := 16#000#;
rommask : integer := 16#E00#;
ioaddr : integer := 16#200#;
iomask : integer := 16#E00#;
ramaddr : integer := 16#400#;
rammask : integer := 16#C00#;
paddr : integer := 0;
pmask : integer := 16#fff#;
wprot : integer := 0;
invclk : integer := 0;
fast : integer := 0;
romasel : integer := 28;
sdrasel : integer := 29;
srbanks : integer := 4;
ram8 : integer := 0;
ram16 : integer := 0;
sden : integer := 0;
sepbus : integer := 0;
sdbits : integer := 32;
sdlsb : integer := 2; -- set to 12 for the GE-HPE board
oepol : integer := 0;
syncrst : integer := 0;
pageburst : integer := 0;
scantest : integer := 0;
mobile : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
memi : in memory_in_type;
memo : out memory_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
wpo : in wprot_out_type;
sdo : out sdram_out_type
);
end;
architecture rtl of mctrl is
constant REVISION : integer := 1;
constant prom : integer := 1;
constant memory : integer := 0;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_ESA, ESA_MCTRL, 0, REVISION, 0),
4 => ahb_membar(romaddr, '1', '1', rommask),
5 => ahb_membar(ioaddr, '0', '0', iomask),
6 => ahb_membar(ramaddr, '1', '1', rammask),
others => zero32);
constant pconfig : apb_config_type := (
0 => ahb_device_reg ( VENDOR_ESA, ESA_MCTRL, 0, REVISION, 0),
1 => apb_iobar(paddr, pmask));
constant RAMSEL5 : boolean := srbanks = 5;
constant SDRAMEN : boolean := (sden /= 0);
constant BUS16EN : boolean := (ram16 /= 0);
constant BUS8EN : boolean := (ram8 /= 0);
constant WPROTEN : boolean := (wprot /= 0);
constant WENDFB : boolean := false;
constant SDSEPBUS: boolean := (sepbus /= 0);
constant BUS64 : boolean := (sdbits = 64);
constant rom : integer := 0;
constant io : integer := 1;
constant ram : integer := 2;
type memcycletype is (idle, berr, bread, bwrite, bread8, bwrite8, bread16, bwrite16);
-- memory configuration register 1 type
type mcfg1type is record
romrws : std_logic_vector(3 downto 0);
romwws : std_logic_vector(3 downto 0);
romwidth : std_logic_vector(1 downto 0);
romwrite : std_logic;
ioen : std_logic;
iows : std_logic_vector(3 downto 0);
bexcen : std_logic;
brdyen : std_logic;
iowidth : std_logic_vector(1 downto 0);
end record;
-- memory configuration register 2 type
type mcfg2type is record
ramrws : std_logic_vector(1 downto 0);
ramwws : std_logic_vector(1 downto 0);
ramwidth : std_logic_vector(1 downto 0);
rambanksz : std_logic_vector(3 downto 0);
rmw : std_logic;
brdyen : std_logic;
srdis : std_logic;
sdren : std_logic;
end record;
-- memory status register type
-- local registers
type reg_type is record
address : std_logic_vector(31 downto 0); -- memory address
data : std_logic_vector(31 downto 0); -- latched memory data
writedata : std_logic_vector(31 downto 0);
writedata8 : std_logic_vector(15 downto 0); -- lsb write data buffer
sdwritedata : std_logic_vector(63 downto 0);
readdata : std_logic_vector(31 downto 0);
brdyn : std_logic;
ready : std_logic;
ready8 : std_logic;
bdrive : std_logic_vector(3 downto 0);
nbdrive : std_logic_vector(3 downto 0);
ws : std_logic_vector(3 downto 0);
romsn : std_logic_vector(1 downto 0);
ramsn : std_logic_vector(4 downto 0);
ramoen : std_logic_vector(4 downto 0);
size : std_logic_vector(1 downto 0);
busw : std_logic_vector(1 downto 0);
oen : std_logic;
iosn : std_logic_vector(1 downto 0);
read : std_logic;
wrn : std_logic_vector(3 downto 0);
writen : std_logic;
bstate : memcycletype;
area : std_logic_vector(0 to 2);
mcfg1 : mcfg1type;
mcfg2 : mcfg2type;
bexcn : std_logic; -- latched external bexcn
echeck : std_logic;
brmw : std_logic;
haddr : std_logic_vector(31 downto 0);
hsel : std_logic;
srhsel : std_logic;
sdhsel : std_logic;
hwrite : std_logic;
hburst : std_logic_vector(2 downto 0);
htrans : std_logic_vector(1 downto 0);
hresp : std_logic_vector(1 downto 0);
sa : std_logic_vector(14 downto 0);
sd : std_logic_vector(63 downto 0);
mben : std_logic_vector(3 downto 0);
end record;
signal r, ri : reg_type;
signal sdmo : sdram_mctrl_out_type;
signal sdi : sdram_in_type;
signal lsdo : sdram_out_type;
-- vectored output enable to data pads
signal rbdrive, ribdrive : std_logic_vector(31 downto 0);
signal rrsbdrive, rsbdrive, risbdrive : std_logic_vector(63 downto 0);
signal arst : std_ulogic;
attribute syn_preserve : boolean;
attribute syn_preserve of rbdrive : signal is true;
attribute syn_preserve of rsbdrive : signal is true;
attribute syn_preserve of rrsbdrive : signal is true;
-- **** tame: added signal to invert polarity
-- signal bprom_cs : std_ulogic;
begin
arst <= ahbsi.testrst when (scantest = 1) and (ahbsi.testen = '1') else rst;
ctrl : process(rst, ahbsi, apbi, memi, r, wpo, sdmo, rbdrive,
rsbdrive, rrsbdrive)
variable v : reg_type; -- local variables for registers
variable start : std_logic;
variable dataout : std_logic_vector(31 downto 0); -- data from memory
variable regsd : std_logic_vector(31 downto 0); -- data from registers
variable memdata : std_logic_vector(31 downto 0); -- data to memory
variable rws : std_logic_vector(3 downto 0); -- read waitstates
variable wws : std_logic_vector(3 downto 0); -- write waitstates
variable wsnew : std_logic_vector(3 downto 0); -- write waitstates
variable adec : std_logic_vector(1 downto 0);
variable rams : std_logic_vector(4 downto 0);
variable bready, leadin : std_logic;
variable csen : std_logic; -- Generate chip selects
variable aprot : std_logic_vector(14 downto 0); --
variable wrn : std_logic_vector(3 downto 0); --
variable bexc, addrerr : std_logic;
variable ready : std_logic;
variable writedata : std_logic_vector(31 downto 0);
variable bwdata : std_logic_vector(31 downto 0);
variable merrtype : std_logic_vector(2 downto 0); -- memory error type
variable noerror : std_logic;
variable area : std_logic_vector(0 to 2);
variable bdrive : std_logic_vector(3 downto 0);
variable ramsn : std_logic_vector(4 downto 0);
variable romsn, busw : std_logic_vector(1 downto 0);
variable iosn : std_logic;
variable lock : std_logic;
variable wprothitx : std_logic;
variable brmw : std_logic;
variable bidle: std_logic;
variable haddr : std_logic_vector(31 downto 0);
variable hsize : std_logic_vector(1 downto 0);
variable hwrite : std_logic;
variable hburst : std_logic_vector(2 downto 0);
variable htrans : std_logic_vector(1 downto 0);
variable sdhsel, srhsel, hready : std_logic;
variable vbdrive : std_logic_vector(31 downto 0);
variable vsbdrive : std_logic_vector(63 downto 0);
variable bdrive_sel : std_logic_vector(3 downto 0);
variable haddrsel : std_logic_vector(31 downto 13);
begin
-- Variable default settings to avoid latches
v := r; wprothitx := '0'; v.ready8 := '0'; v.iosn(0) := r.iosn(1);
ready := '0'; addrerr := '0'; regsd := (others => '0'); csen := '0';
v.ready := '0'; v.echeck := '0';
merrtype := "---"; bready := '1';
vbdrive := rbdrive; vsbdrive := rsbdrive;
v.data := memi.data; v.bexcn := memi.bexcn; v.brdyn := memi.brdyn;
if (((r.brdyn and r.mcfg1.brdyen) = '1') and (r.area(io) = '1')) or
(((r.brdyn and r.mcfg2.brdyen) = '1') and (r.area(ram) = '1') and
(r.ramsn(4) = '0') and RAMSEL5)
then
bready := '0';
else bready := '1'; end if;
v.hresp := HRESP_OKAY;
if SDRAMEN and (r.hsel = '1') and (ahbsi.hready = '0') then
haddr := r.haddr; hsize := r.size; hburst := r.hburst;
htrans := r.htrans; hwrite := r.hwrite;
area := r.area;
else
haddr := ahbsi.haddr; hsize := ahbsi.hsize(1 downto 0);
hburst := ahbsi.hburst; htrans := ahbsi.htrans; hwrite := ahbsi.hwrite;
area := ahbsi.hmbsel(0 to 2);
end if;
if SDRAMEN then
if fast = 1 then
sdhsel := ahbsi.hsel(hindex) and ahbsi.haddr(sdrasel) and
ahbsi.htrans(1) and ahbsi.hmbsel(2);
else
sdhsel := ahbsi.hsel(hindex) and ahbsi.htrans(1) and
r.mcfg2.sdren and ahbsi.hmbsel(2) and (ahbsi.haddr(sdrasel) or r.mcfg2.srdis);
end if;
srhsel := ahbsi.hsel(hindex) and not sdhsel;
else sdhsel := '0'; srhsel := ahbsi.hsel(hindex); end if;
-- decode memory area parameters
leadin := '0'; rws := "----"; wws := "----"; adec := "--";
busw := (others => '-'); brmw := '0';
if area(rom) = '1' then
busw := r.mcfg1.romwidth;
end if;
haddrsel := (others => '0');
haddrsel(sdrasel downto 13) := haddr(sdrasel downto 13);
if area(ram) = '1' then
adec := genmux(r.mcfg2.rambanksz, haddrsel(sdrasel downto 14)) &
genmux(r.mcfg2.rambanksz, haddrsel(sdrasel-1 downto 13));
if sdhsel = '1' then busw := "10";
else
busw := r.mcfg2.ramwidth;
if ((r.mcfg2.rmw and hwrite) = '1') and
((BUS16EN and (busw = "01") and (hsize = "00")) or
((busw(1) = '1') and (hsize(1) = '0'))
)
then brmw := '1'; end if; -- do a read-modify-write cycle
end if;
end if;
if area(io) = '1' then
leadin := '1';
busw := r.mcfg1.iowidth;
end if;
-- decode waitstates, illegal access and cacheability
if r.area(rom) = '1' then
rws := r.mcfg1.romrws; wws := r.mcfg1.romwws;
if (r.mcfg1.romwrite or r.read) = '0' then addrerr := '1'; end if;
end if;
if r.area(ram) = '1' then
rws := "00" & r.mcfg2.ramrws; wws := "00" & r.mcfg2.ramwws;
end if;
if r.area(io) = '1' then
rws := r.mcfg1.iows; wws := r.mcfg1.iows;
if r.mcfg1.ioen = '0' then addrerr := '1'; end if;
end if;
-- generate data buffer enables
bdrive := (others => '1');
case r.busw is
when "00" => if BUS8EN then bdrive := "0001"; end if;
when "01" => if BUS16EN then bdrive := "0011"; end if;
when others =>
end case;
-- generate chip select and output enable
rams := '0' & decode(adec);
case srbanks is
when 0 => rams := "00000";
when 1 => rams := "00001";
when 2 => rams := "000" & (rams(3 downto 2) or rams(1 downto 0));
when others =>
if RAMSEL5 and (haddr(sdrasel) = '1') then rams := "10000"; end if;
end case;
iosn := '1'; ramsn := (others => '1'); romsn := (others => '1');
if area(rom) = '1' then
romsn := (not haddr(romasel)) & haddr(romasel);
end if;
if area(ram) = '1' then ramsn := not rams; end if;
if area(io) = '1' then iosn := '0'; end if;
-- generate write strobe
wrn := "0000";
case r.busw is
when "00" =>
if BUS8EN then wrn := "1110"; end if;
when "01" =>
if BUS16EN then
if (r.size = "00") and (r.brmw = '0') then
wrn := "11" & (not r.address(0)) & r.address(0);
else wrn := "1100"; end if;
end if;
when "10" | "11" =>
case r.size is
when "00" =>
case r.address(1 downto 0) is
when "00" => wrn := "1110";
when "01" => wrn := "1101";
when "10" => wrn := "1011";
when others => wrn := "0111";
end case;
when "01" =>
wrn := not r.address(1) & not r.address(1) & r.address(1) & r.address(1);
when others => null;
end case;
when others => null;
end case;
if (r.mcfg2.rmw = '1') and (r.area(ram) = '1') then wrn := not bdrive; end if;
if (((ahbsi.hready and ahbsi.hsel(hindex) and ahbsi.htrans(1)) = '1'))
then
v.area := area;
v.address := haddr;
if (busw = "00") and (hwrite = '0') and (area(io) = '0') and BUS8EN
then v.address(1 downto 0) := "00"; end if;
if (busw = "01") and (hwrite = '0') and (area(io) = '0') and BUS16EN
then v.address(1 downto 0) := "00"; end if;
if (brmw = '1') then
v.read := '1';
else v.read := not hwrite; end if;
v.busw := busw; v.brmw := brmw;
end if;
if (((sdmo.aload and r.hsel) = '1') and SDRAMEN) then
v.address := haddr;
if (busw = "00") and (hwrite = '0') and (area(io) = '0') and BUS8EN
then v.address(1 downto 0) := "00"; end if;
if (busw = "01") and (hwrite = '0') and (area(io) = '0') and BUS16EN
then v.address(1 downto 0) := "00"; end if;
end if;
-- Select read data depending on bus width
if BUS8EN and (r.busw = "00") then
memdata := r.readdata(23 downto 0) & r.data(31 downto 24);
elsif BUS16EN and (r.busw = "01") then
memdata := r.readdata(15 downto 0) & r.data(31 downto 16);
else
memdata := r.data;
end if;
bwdata := memdata;
-- Merge data during byte write
writedata := ahbreadword(ahbsi.hwdata, r.address(4 downto 2));
if ((r.brmw and r.busw(1)) = '1')
then
case r.address(1 downto 0) is
when "00" =>
writedata(15 downto 0) := bwdata(15 downto 0);
if r.size = "00" then
writedata(23 downto 16) := bwdata(23 downto 16);
end if;
when "01" =>
writedata(31 downto 24) := bwdata(31 downto 24);
writedata(15 downto 0) := bwdata(15 downto 0);
when "10" =>
writedata(31 downto 16) := bwdata(31 downto 16);
if r.size = "00" then
writedata(7 downto 0) := bwdata(7 downto 0);
end if;
when others =>
writedata(31 downto 8) := bwdata(31 downto 8);
end case;
end if;
if (r.brmw = '1') and (r.busw = "01") and BUS16EN then
if r.address(1) = '1' then
writedata(31 downto 16) := writedata(15 downto 0);
end if;
if (r.address(0) = '0') then
writedata(23 downto 16) := r.data(23 downto 16);
else
writedata(31 downto 24) := r.data(31 downto 24);
end if;
end if;
-- save read data during 8/16 bit reads
if BUS8EN and (r.ready8 = '1') and (r.busw = "00") then
v.readdata := v.readdata(23 downto 0) & r.data(31 downto 24);
elsif BUS16EN and (r.ready8 = '1') and (r.busw = "01") then
v.readdata := v.readdata(15 downto 0) & r.data(31 downto 16);
end if;
-- Ram, rom, IO access FSM
if r.read = '1' then wsnew := rws; else wsnew := wws; end if;
case r.bstate is
when idle =>
v.ws := wsnew;
if r.bdrive(0) = '1' then
if r.busw(1) = '1' then
v.writedata(31 downto 16) := writedata(31 downto 16);
elsif r.busw = "01" then
if (r.address(1) = '0') or (r.brmw = '1') then
v.writedata(31 downto 16) := writedata(31 downto 16);
else
v.writedata(31 downto 16) := writedata(15 downto 0);
end if;
else
case r.address(1 downto 0) is
when "00" =>
v.writedata(31 downto 16) := writedata(31 downto 16);
when "01" =>
v.writedata(31 downto 24) := writedata(23 downto 16);
when "10" =>
v.writedata(31 downto 16) := writedata(15 downto 0);
when "11" =>
v.writedata(31 downto 24) := writedata(7 downto 0);
when others =>
null;
end case;
end if;
v.writedata(15 downto 0) := writedata(15 downto 0);
if r.busw(1) = '0' then
v.writedata8 := writedata(15 downto 0);
end if;
end if;
if (r.srhsel = '1') and ((sdmo.busy = '0') or not SDRAMEN)
then
if WPROTEN then wprothitx := wpo.wprothit; end if;
if (wprothitx or addrerr) = '1' then
v.hresp := HRESP_ERROR; v.bstate := berr; v.bdrive := (others => '1');
elsif r.read = '0' then
if (r.busw = "00") and (r.area(io) = '0') and BUS8EN then
v.bstate := bwrite8;
elsif (r.busw = "01") and (r.area(io) = '0') and BUS16EN then
v.bstate := bwrite16;
else v.bstate := bwrite; end if;
v.wrn := wrn; v.writen := '0'; v.bdrive := not bdrive;
else
if r.oen = '1' then v.ramoen := r.ramsn; v.oen := '0';
else
if (r.busw = "00") and (r.area(io) = '0') and BUS8EN then v.bstate := bread8;
elsif (r.busw = "01") and (r.area(io) = '0') and BUS16EN then v.bstate := bread16;
else v.bstate := bread; end if;
end if;
end if;
end if;
when berr =>
v.bstate := idle; ready := '1';
v.hresp := HRESP_ERROR;
v.ramsn := (others => '1'); v.romsn := (others => '1');
v.ramoen := (others => '1'); v.oen := '1'; v.iosn := "11"; v.bdrive := (others => '1');
when bread =>
if ((r.ws = "0000") and (r.ready = '0') and (bready = '1'))
then
if r.brmw = '0' then
ready := '1'; v.echeck := '1';
if r.area(io) = '0' then
v.address := ahbsi.haddr;
end if;
end if;
if (((ahbsi.hsel(hindex) = '0') or (ahbsi.htrans /= HTRANS_SEQ)) or
(r.hburst = HBURST_SINGLE) or (r.area(io) = '1'))
then
v.ramoen := (others => '1'); v.oen := '1'; v.iosn := "11";
v.bstate := idle; v.read := not r.hwrite;
if r.brmw = '0' then
v.ramsn := (others => '1'); v.romsn := (others => '1');
else
v.echeck := '1';
end if;
end if;
end if;
if r.ready = '1' then
v.ws := rws;
else
if r.ws /= "0000" then v.ws := r.ws - 1; end if;
end if;
when bwrite =>
if (r.ws = "0000") and (bready = '1') then
ready := '1'; v.wrn := (others => '1'); v.writen := '1'; v.echeck := '1';
v.ramsn := (others => '1'); v.romsn := (others => '1'); v.iosn := "11";
v.bdrive := (others => '1'); v.bstate := idle;
end if;
if r.ws /= "0000" then v.ws := r.ws - 1; end if;
when bread8 =>
if BUS8EN then
if (r.ws = "0000") and (r.ready8 = '0') and (bready = '1') then
v.ready8 := '1'; v.ws := rws;
v.address(1 downto 0) := r.address(1 downto 0) + 1;
if (r.address(1 downto 0) = "11") then
ready := '1'; v.address := ahbsi.haddr; v.echeck := '1';
if (((ahbsi.hsel(hindex) = '0') or (ahbsi.htrans /= HTRANS_SEQ)) or
(r.hburst = HBURST_SINGLE))
then
v.ramoen := (others => '1'); v.oen := '1'; v.iosn := "11";
v.bstate := idle;
v.ramsn := (others => '1'); v.romsn := (others => '1');
end if;
end if;
end if;
if (r.ready8 = '1') then v.ws := rws;
elsif r.ws /= "0000" then v.ws := r.ws - 1; end if;
else
v.bstate := idle;
end if;
when bwrite8 =>
if BUS8EN then
if (r.ws = "0000") and (r.ready8 = '0') and (bready = '1') then
v.ready8 := '1'; v.wrn := (others => '1'); v.writen := '1';
end if;
if (r.ws = "0000") and (bready = '1') and
((r.address(1 downto 0) = "11") or
((r.address(1 downto 0) = "01") and (r.size = "01")) or
(r.size = "00"))
then
ready := '1'; v.wrn := (others => '1'); v.writen := '1'; v.echeck := '1';
v.ramsn := (others => '1'); v.romsn := (others => '1'); v.iosn := "11";
v.bdrive := (others => '1'); v.bstate := idle;
end if;
if (r.ready8 = '1') then
v.address(1 downto 0) := r.address(1 downto 0) + 1; v.ws := rws;
v.writedata(31 downto 16) := r.writedata(23 downto 16) & r.writedata8(15 downto 8);
v.writedata8(15 downto 8) := r.writedata8(7 downto 0);
v.bstate := idle;
end if;
if r.ws /= "0000" then v.ws := r.ws - 1; end if;
else
v.bstate := idle;
end if;
when bread16 =>
if BUS16EN then
if (r.ws = "0000") and (bready = '1') and ((r.address(1) or r.brmw) = '1') and
(r.ready8 = '0')
then
if r.brmw = '0' then
ready := '1'; v.address := ahbsi.haddr; v.echeck := '1';
end if;
if (((ahbsi.hsel(hindex) = '0') or (ahbsi.htrans /= HTRANS_SEQ)) or
(r.hburst = HBURST_SINGLE))
then
if r.brmw = '0' then
v.ramsn := (others => '1'); v.romsn := (others => '1');
end if;
v.ramoen := (others => '1'); v.oen := '1'; v.iosn := "11";
v.bstate := idle; v.read := not r.hwrite;
end if;
end if;
if (r.ws = "0000") and (bready = '1') and (r.ready8 = '0') then
v.ready8 := '1'; v.ws := rws;
if r.brmw = '0' then v.address(1) := not r.address(1); end if;
end if;
if (r.ready8 = '1') then v.ws := rws;
elsif r.ws /= "0000" then v.ws := r.ws - 1; end if;
else
v.bstate := idle;
end if;
when bwrite16 =>
if BUS16EN then
if (r.ws = "0000") and (bready = '1') and
((r.address(1 downto 0) = "10") or (r.size(1) = '0'))
then
ready := '1'; v.wrn := (others => '1'); v.writen := '1'; v.echeck := '1';
v.ramsn := (others => '1'); v.romsn := (others => '1'); v.iosn := "11";
v.bdrive := (others => '1'); v.bstate := idle;
end if;
if (r.ws = "0000") and (bready = '1') and (r.ready8 = '0') then
v.ready8 := '1'; v.wrn := (others => '1'); v.writen := '1';
end if;
if (r.ready8 = '1') then
v.address(1) := not r.address(1); v.ws := rws;
v.writedata(31 downto 16) := r.writedata8(15 downto 0);
v.bstate := idle;
end if;
if r.ws /= "0000" then v.ws := r.ws - 1; end if;
else
v.bstate := idle;
end if;
when others =>
end case;
-- if BUSY or IDLE cycle seen, or if de-selected, return to idle state
if (ahbsi.hready = '1') then
if ((ahbsi.hsel(hindex) = '0') or (ahbsi.htrans = HTRANS_BUSY) or
(ahbsi.htrans = HTRANS_IDLE))
then
v.bstate := idle;
v.ramsn := (others => '1'); v.romsn := (others => '1');
v.ramoen := (others => '1'); v.oen := '1'; v.iosn := "11";
v.bdrive := (others => '1'); v.wrn := (others => '1');
v.writen := '1'; v.hsel := '0'; ready := ahbsi.hsel(hindex); v.srhsel := '0';
elsif srhsel = '1' then
v.romsn := romsn; v.ramsn(4 downto 0) := ramsn(4 downto 0); v.iosn := iosn & '1';
if v.read = '1' then v.ramoen(4 downto 0) := ramsn(4 downto 0); v.oen := leadin; end if;
end if;
end if;
-- error checking and reporting
noerror := '1';
if ((r.echeck and r.mcfg1.bexcen and not r.bexcn) = '1') then
noerror := '0'; v.bstate := berr; v.hresp := HRESP_ERROR; v.bdrive := (others => '1');
v.wrn := (others => '1'); v.writen := '1';
end if;
-- APB register access
case apbi.paddr(3 downto 2) is
when "00" =>
regsd(28 downto 0) := r.mcfg1.iowidth &
r.mcfg1.brdyen & r.mcfg1.bexcen & "0" & r.mcfg1.iows & r.mcfg1.ioen &
'0' &
"000000" & r.mcfg1.romwrite &
'0' & r.mcfg1.romwidth & r.mcfg1.romwws & r.mcfg1.romrws;
when "01" =>
if SDRAMEN then
regsd(31 downto 16) := sdmo.prdata(31 downto 16);
if BUS64 then regsd(18) := '1'; end if;
regsd(14 downto 13) := r.mcfg2.sdren & r.mcfg2.srdis;
end if;
regsd(12 downto 9) := r.mcfg2.rambanksz;
if RAMSEL5 then regsd(7) := r.mcfg2.brdyen; end if;
regsd(6 downto 0) := r.mcfg2.rmw & r.mcfg2.ramwidth &
r.mcfg2.ramwws & r.mcfg2.ramrws;
when "10" =>
if SDRAMEN then
regsd(26 downto 12) := sdmo.prdata(26 downto 12);
end if;
when "11" =>
if SDRAMEN then
regsd(31 downto 0) := sdmo.prdata(31 downto 0);
end if;
when others => regsd := (others => '0');
end case;
apbo.prdata <= regsd;
if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
case apbi.paddr(5 downto 2) is
when "0000" =>
v.mcfg1.romrws := apbi.pwdata(3 downto 0);
v.mcfg1.romwws := apbi.pwdata(7 downto 4);
v.mcfg1.romwidth := apbi.pwdata(9 downto 8);
v.mcfg1.romwrite := apbi.pwdata(11);
v.mcfg1.ioen := apbi.pwdata(19);
v.mcfg1.iows := apbi.pwdata(23 downto 20);
v.mcfg1.bexcen := apbi.pwdata(25);
v.mcfg1.brdyen := apbi.pwdata(26);
v.mcfg1.iowidth := apbi.pwdata(28 downto 27);
when "0001" =>
v.mcfg2.ramrws := apbi.pwdata(1 downto 0);
v.mcfg2.ramwws := apbi.pwdata(3 downto 2);
v.mcfg2.ramwidth := apbi.pwdata(5 downto 4);
v.mcfg2.rmw := apbi.pwdata(6);
v.mcfg2.brdyen := apbi.pwdata(7);
v.mcfg2.rambanksz := apbi.pwdata(12 downto 9);
if SDRAMEN then
v.mcfg2.srdis := apbi.pwdata(13);
v.mcfg2.sdren := apbi.pwdata(14);
end if;
when others => null;
end case;
end if;
-- select appropriate data during reads
if (r.area(rom) or r.area(ram)) = '1' then dataout := memdata;
else
if BUS8EN and (r.busw = "00") then
dataout := r.data(31 downto 24) & r.data(31 downto 24)
& r.data(31 downto 24) & r.data(31 downto 24);
elsif BUS16EN and (r.busw = "01") then
dataout := r.data(31 downto 16) & r.data(31 downto 16);
else dataout := r.data; end if;
end if;
v.ready := ready;
v.srhsel := r.srhsel and not ready;
if ahbsi.hready = '1' then v.hsel := ahbsi.hsel(hindex); end if;
if ((ahbsi.hready and ahbsi.hsel(hindex)) = '1') then
v.size := ahbsi.hsize(1 downto 0); v.hwrite := ahbsi.hwrite;
v.hburst := ahbsi.hburst; v.htrans := ahbsi.htrans;
if ahbsi.htrans(1) = '1' then v.hsel := '1'; v.srhsel := srhsel; end if;
if SDRAMEN then
v.haddr := ahbsi.haddr;
v.sdhsel := sdhsel;
end if;
end if;
-- sdram synchronisation
if SDRAMEN then
v.sa := sdmo.address; v.sd := memi.sd;
if (r.bstate /= idle) or ((r.ramsn & r.romsn & r.iosn) /= "111111111") then bidle := '0';
else
bidle := '1';
if (sdmo.busy and not sdmo.aload) = '1' then
if not SDSEPBUS then
v.address(sdlsb + 14 downto sdlsb) := sdmo.address;
end if;
v.romsn := (others => '1'); v.ramsn(4 downto 0) := (others => '1');
v.iosn := (others =>'1'); v.ramoen(4 downto 0) := (others => '1');
v.oen := '1';
v.bdrive := not (sdmo.bdrive & sdmo.bdrive & sdmo.bdrive & sdmo.bdrive);
if r.sdhsel = '1' then
v.hresp := sdmo.hresp;
end if;
end if;
end if;
if (sdmo.aload and r.srhsel) = '1' then
v.romsn := romsn; v.ramsn(4 downto 0) := ramsn(4 downto 0); v.iosn := iosn & '1';
if v.read = '1' then v.ramoen(4 downto 0) := ramsn(4 downto 0); v.oen := leadin; end if;
end if;
if sdmo.hsel = '1' then
v.writedata := writedata;
v.sdwritedata(31 downto 0) := writedata;
if BUS64 and sdmo.bsel = '1' then
v.sdwritedata(63 downto 32) := writedata;
end if;
hready := sdmo.hready and noerror and not r.brmw;
if SDSEPBUS then
if BUS64 and sdmo.bsel = '1' then dataout := r.sd(63 downto 32);
else dataout := r.sd(31 downto 0); end if;
end if;
else hready := r.ready and noerror; end if;
else
hready := r.ready and noerror;
end if;
if v.read = '1' then v.mben := "0000"; else v.mben := v.wrn; end if;
v.nbdrive := not v.bdrive;
if oepol = 0 then
bdrive_sel := r.bdrive;
vbdrive(31 downto 24) := (others => v.bdrive(0));
vbdrive(23 downto 16) := (others => v.bdrive(1));
vbdrive(15 downto 8) := (others => v.bdrive(2));
vbdrive(7 downto 0) := (others => v.bdrive(3));
vsbdrive(31 downto 24) := (others => v.bdrive(0));
vsbdrive(23 downto 16) := (others => v.bdrive(1));
vsbdrive(15 downto 8) := (others => v.bdrive(2));
vsbdrive(7 downto 0) := (others => v.bdrive(3));
vsbdrive(63 downto 56) := (others => v.bdrive(0));
vsbdrive(55 downto 48) := (others => v.bdrive(1));
vsbdrive(47 downto 40) := (others => v.bdrive(2));
vsbdrive(39 downto 32) := (others => v.bdrive(3));
else
bdrive_sel := r.nbdrive;
vbdrive(31 downto 24) := (others => v.nbdrive(0));
vbdrive(23 downto 16) := (others => v.nbdrive(1));
vbdrive(15 downto 8) := (others => v.nbdrive(2));
vbdrive(7 downto 0) := (others => v.nbdrive(3));
vsbdrive(31 downto 24) := (others => v.nbdrive(0));
vsbdrive(23 downto 16) := (others => v.nbdrive(1));
vsbdrive(15 downto 8) := (others => v.nbdrive(2));
vsbdrive(7 downto 0) := (others => v.nbdrive(3));
vsbdrive(63 downto 56) := (others => v.nbdrive(0));
vsbdrive(55 downto 48) := (others => v.nbdrive(1));
vsbdrive(47 downto 40) := (others => v.nbdrive(2));
vsbdrive(39 downto 32) := (others => v.nbdrive(3));
end if;
-- reset
if rst = '0' then
v.bstate := idle;
v.read := '1';
v.wrn := "1111";
v.writen := '1';
v.mcfg1.romwrite := '0';
v.mcfg1.ioen := '0';
v.mcfg1.brdyen := '0';
v.mcfg1.bexcen := '0';
v.hsel := '0';
v.srhsel := '0';
v.ready := '1';
v.mcfg1.iows := "0000";
v.mcfg2.ramrws := "00";
v.mcfg2.ramwws := "00";
v.mcfg1.romrws := "1111";
v.mcfg1.romwws := "1111";
v.mcfg1.romwidth := memi.bwidth;
v.mcfg2.srdis := '0';
v.mcfg2.sdren := '0';
if syncrst = 1 then
v.ramsn := (others => '1'); v.romsn := (others => '1');
v.oen := '1'; v.iosn := "11"; v.ramoen := (others => '1');
v.bdrive := (others => '1'); v.nbdrive := (others => '0');
if oepol = 0 then vbdrive := (others => '1'); vsbdrive := (others => '1');
else vbdrive := (others => '0'); vsbdrive := (others => '0'); end if;
end if;
end if;
-- optional feeb-back from write stobe to data bus drivers
if oepol = 0 then
if WENDFB then bdrive := r.bdrive and memi.wrn;
else bdrive := r.bdrive; end if;
else
if WENDFB then bdrive := r.nbdrive or not memi.wrn;
else bdrive := r.nbdrive; end if;
end if;
-- pragma translate_off
for i in dataout'range loop --'
if is_x(dataout(i)) then dataout(i) := '1'; end if;
end loop;
-- pragma translate_on
-- scan support
if (syncrst = 1) and (rst = '0') then
memo.ramsn <= (others => '1');
memo.ramoen <= (others => '1');
memo.romsn <= (others => '1');
memo.iosn <= '1';
memo.oen <= '1';
if (scantest = 1) and (ahbsi.testen = '1') then
memo.bdrive <= (others => ahbsi.testoen);
memo.vbdrive <= (others => ahbsi.testoen);
memo.svbdrive <= (others => ahbsi.testoen);
else
if oepol = 0 then
memo.bdrive <= (others => '1');
memo.vbdrive <= (others => '1');
memo.svbdrive <= (others => '1');
else
memo.bdrive <= (others => '0');
memo.vbdrive <= (others => '0');
memo.svbdrive <= (others => '0');
end if;
end if;
else
memo.ramsn <= "111" & r.ramsn;
memo.ramoen <= "111" & r.ramoen;
memo.romsn <= "111111" & r.romsn;
memo.iosn <= r.iosn(0);
memo.oen <= r.oen;
if (scantest = 1) and (ahbsi.testen = '1') then
memo.bdrive <= (others => ahbsi.testoen);
memo.vbdrive <= (others => ahbsi.testoen);
memo.svbdrive <= (others => ahbsi.testoen);
else
memo.bdrive <= bdrive;
memo.vbdrive <= rbdrive;
memo.svbdrive <= rrsbdrive;
end if;
end if;
-- drive various register inputs and external outputs
ri <= v;
ribdrive <= vbdrive;
risbdrive <= vsbdrive;
memo.address <= r.address;
memo.read <= r.read;
memo.wrn <= r.wrn;
memo.writen <= r.writen;
memo.data <= r.writedata;
memo.mben <= r.mben;
memo.svcdrive <= (others => '0');
memo.vcdrive <= (others => '0');
memo.scb <= (others => '0');
memo.cb <= (others => '0');
memo.romn <= r.romsn(0);
memo.ramn <= r.ramsn(0);
memo.sdram_en <= r.mcfg2.sdren; -- Unused
memo.rs_edac_en <= '0';
memo.ce <= '0';
sdi.idle <= bidle;
sdi.haddr <= haddr;
sdi.rhaddr <= r.haddr;
sdi.nhtrans <= htrans;
sdi.rhtrans <= r.htrans;
sdi.htrans <= ahbsi.htrans;
sdi.hready <= ahbsi.hready;
sdi.hsize <= r.size;
sdi.hwrite <= r.hwrite;
sdi.hsel <= sdhsel;
sdi.enable <= r.mcfg2.sdren;
sdi.srdis <= r.mcfg2.srdis;
sdi.edac <= '0';
sdi.brmw <= '0';
sdi.error <= '0';
ahbso.hrdata <= ahbdrivedata(dataout);
ahbso.hready <= hready;
ahbso.hresp <= r.hresp;
end process;
stdregs : process(clk, arst)
begin
if rising_edge(clk) then
r <= ri; rbdrive <= ribdrive; rsbdrive <= risbdrive;
if rst = '0' then r.ws <= (others => '0'); end if;
end if;
if (syncrst = 0) and (arst = '0') then
r.ramsn <= (others => '1'); r.romsn <= (others => '1');
r.oen <= '1'; r.iosn <= "11"; r.ramoen <= (others => '1');
r.bdrive <= (others => '1'); r.nbdrive <= (others => '0');
if oepol = 0 then rbdrive <= (others => '1'); rsbdrive <= (others => '1');
else rbdrive <= (others => '0'); rsbdrive <= (others => '0'); end if;
end if;
end process;
ahbso.hsplit <= (others => '0');
ahbso.hconfig <= hconfig;
ahbso.hirq <= (others => '0');
ahbso.hindex <= hindex;
apbo.pconfig <= pconfig;
apbo.pirq <= (others => '0');
apbo.pindex <= pindex;
-- optional sdram controller
sd0 : if SDRAMEN generate
sdctrl : sdmctrl generic map (pindex, invclk, fast, wprot, sdbits, pageburst, mobile)
port map ( rst => rst, clk => clk, sdi => sdi,
sdo => lsdo, apbi => apbi, wpo => wpo, sdmo => sdmo);
rgen : if invclk = 0 generate
memo.sa <= r.sa; sdo <= lsdo; rrsbdrive <= rsbdrive;
memo.sddata(31 downto 0) <= r.sdwritedata(31 downto 0);
memo.sddata(63 downto 32) <= r.sdwritedata(63 downto 32);
end generate;
ngen : if invclk = 1 generate
nregs : process(clk, arst) begin
if falling_edge(clk) then
memo.sa <= r.sa; sdo <= lsdo; rrsbdrive <= rsbdrive;
memo.sddata(31 downto 0) <= r.sdwritedata(31 downto 0);
memo.sddata(63 downto 32) <= r.sdwritedata(63 downto 32);
if (syncrst = 0) and (arst = '0') then
if oepol = 0 then rrsbdrive <= (others => '1');
else rrsbdrive <= (others => '0'); end if;
end if;
end if;
end process;
end generate;
end generate;
sd1 : if not SDRAMEN generate
sdo <= ("00", "11", '1', '1', '1', "11111111");
sdmo.prdata <= (others => '0');
sdmo.address <= (others => '0'); sdmo.busy <= '0';
sdmo.aload <= '0'; sdmo.bdrive <= '0'; sdmo.hready <= '1';
sdmo.hresp <= "11";
memo.sddata <= (others => '0');
memo.sa <= (others => '0');
end generate;
end;
| gpl-3.0 |
EliasLuiz/TCC | Leon3/lib/gaisler/sim/sdrtestmod.vhd | 1 | 5696 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: sdrtestmod
-- File: sdrtestmod.vhd
-- Author: Magnus Hjorth - Aeroflex Gaisler
-- Description: Test report module with SDRAM interface
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
use grlib.devices.all;
library gaisler;
use gaisler.sim.all;
entity sdrtestmod is
generic (
width: integer := 32; -- 32-bit or 64-bit supported
bank: integer range 0 to 3 := 0;
row: integer := 0;
halt: integer range 0 to 1 := 1;
swwidth: integer := 32 -- Internal reportdev size, can be 32/64
);
port (
clk: in std_ulogic;
csn: in std_ulogic;
rasn: in std_ulogic;
casn: in std_ulogic;
wen: in std_ulogic;
ba: in std_logic_vector(1 downto 0);
addr: in std_logic_vector(12 downto 0);
dq: inout std_logic_vector(width-1 downto 0);
dqm: in std_logic_vector(width/8-1 downto 0)
);
end;
architecture sim of sdrtestmod is
begin
dq <= (others => 'Z');
p: process(clk)
variable modereg: std_logic_vector(12 downto 0);
variable myrow: boolean := false;
variable wrburst: integer := 0;
variable wrcol: integer;
variable i,j,k: integer;
variable d: std_logic_vector(31 downto 0);
variable errcnt, vendorid, deviceid : integer;
procedure write_main(addr: integer; d: std_logic_vector) is
variable errno, subtest : integer;
begin
case i is
when 0 =>
vendorid := conv_integer(d(31 downto 24));
deviceid := conv_integer(d(23 downto 12));
print(iptable(vendorid).device_table(deviceid));
when 1 =>
errno := conv_integer(d(15 downto 0));
if (halt = 1) then
assert false
report "test failed, error (" & tost(errno) & ")"
severity failure;
else
assert false
report "test failed, error (" & tost(errno) & ")"
severity warning;
end if;
when 2 =>
subtest := conv_integer(d(7 downto 0));
call_subtest(vendorid, deviceid, subtest);
when 4 =>
print ("");
print ("**** GRLIB system test starting ****");
errcnt := 0;
when 5 =>
if errcnt = 0 then
print ("Test passed, halting with IU error mode");
elsif errcnt = 1 then
print ("1 error detected, halting with IU error mode");
else
print (tost(errcnt) & " errors detected, halting with IU error mode");
end if;
print ("");
when 6 =>
grlib.testlib.print("Checkpoint " & tost(conv_integer(d(15 downto 0))));
when 7 =>
vendorid := 0; deviceid := 0;
print ("Basic memory test");
when others =>
end case;
end write_main;
begin
if rising_edge(clk) then
if csn='0' then
if rasn='0' and casn='0' and wen='0' then
modereg := addr;
elsif rasn='0' and casn='1' and wen='1' then
if ba=conv_std_logic_vector(bank,2) and addr=conv_std_logic_vector(row,13) then
myrow := true;
else
myrow := false;
end if;
elsif rasn='1' and casn='0' and wen='0' then
if myrow then
if modereg(9)='0' and modereg(2 downto 0)="001" then
wrburst := 2;
elsif modereg(9)='0' and modereg(2 downto 0)="010" then
wrburst := 4;
elsif modereg(9)='0' and (modereg(2 downto 0)="011" or modereg(2)='1') then
wrburst := 8;
else
wrburst := 1;
end if;
wrcol := conv_integer(addr(7 downto 0));
end if;
elsif rasn='0' and casn='1' and wen='0' then
if ba=conv_std_logic_vector(bank,2) or addr(10)='1' then
myrow := false;
wrburst := 0;
end if;
end if;
end if;
if wrburst > 0 then
for x in 0 to (width/32)-1 loop
if width=32 and swwidth=64 and (wrcol mod 2 < 1) then next; end if;
if width=64 and swwidth=64 and x=0 then next; end if;
if dqm(width/8-1-x*4 downto width/8-4-x*4) = "0000" then
i := (wrcol*width)/swwidth + (x*32)/swwidth;
d := dq(width-1-x*32 downto width-32-x*32);
if d /= x"DEADBEEF" then
write_main(i,d);
end if;
end if;
end loop;
wrburst := wrburst-1;
wrcol := wrcol+1;
end if;
end if;
end process;
end;
| gpl-3.0 |
EliasLuiz/TCC | Leon3/designs/leon3-gr-xc3s-1500/vga_clkgen.vhd | 3 | 2028 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library unisim;
use unisim.BUFG;
-- pragma translate_on
library techmap;
use techmap.gencomp.all;
use techmap.allclkgen.all;
entity vga_clkgen is
port (
resetn : in std_logic;
sel : in std_logic_vector(1 downto 0);
clk25 : in std_logic;
clkm : in std_logic;
clk50 : in std_logic;
clkout : out std_logic
);
end;
architecture struct of vga_clkgen is
component BUFG port ( O : out std_logic; I : in std_logic); end component;
signal clk65, clksel : std_logic;
begin
-- 65 MHz clock generator
clkgen65 : clkmul_virtex2 generic map (13, 5) port map (resetn, clk25, clk65);
clk_select : process (clk25, clk50, clk65, sel)
begin
case sel is
when "00" => clksel <= clk25;
when "01" => clksel <= clkm;
when "10" => clksel <= clk50;
when "11" => clksel <= clk65;
when others => clksel <= '0';
end case;
end process;
bufg1 : BUFG port map (I => clksel, O => clkout);
end;
| gpl-3.0 |
EliasLuiz/TCC | Leon3/designs/leon3-xilinx-vc707/testbench.vhd | 1 | 18296 | -----------------------------------------------------------------------------
-- LEON Demonstration design test bench
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
use work.debug.all;
use work.config.all;
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
USE_MIG_INTERFACE_MODEL : boolean := false
);
end;
architecture behav of testbench is
-- DDR3 Simulation parameters
constant SIM_BYPASS_INIT_CAL : string := "FAST";
-- # = "OFF" - Complete memory init &
-- calibration sequence
-- # = "SKIP" - Not supported
-- # = "FAST" - Complete memory init & use
-- abbreviated calib sequence
constant SIMULATION : string := "TRUE";
-- Should be TRUE during design simulations and
-- FALSE during implementations
constant promfile : string := "prom.srec"; -- rom contents
constant ramfile : string := "ram.srec"; -- ram contents
signal clk : std_logic := '0';
signal rst : std_logic := '0';
signal address : std_logic_vector(25 downto 0);
signal data : std_logic_vector(15 downto 0);
signal button : std_logic_vector(3 downto 0) := "0000";
signal genio : std_logic_vector(59 downto 0);
signal romsn : std_logic;
signal oen : std_ulogic;
signal writen : std_ulogic;
signal adv : std_logic;
signal GND : std_ulogic := '0';
signal VCC : std_ulogic := '1';
signal NC : std_ulogic := 'Z';
signal txd1 , rxd1 , dsurx : std_logic;
signal txd2 , rxd2 , dsutx : std_logic;
signal ctsn1 , rtsn1 , dsuctsn : std_ulogic;
signal ctsn2 , rtsn2 , dsurtsn : std_ulogic;
signal phy_mii_data : std_logic;
signal phy_tx_clk : std_ulogic;
signal phy_rx_clk : std_ulogic;
signal phy_rx_data : std_logic_vector(7 downto 0);
signal phy_dv : std_ulogic;
signal phy_rx_er : std_ulogic;
signal phy_col : std_ulogic;
signal phy_crs : std_ulogic;
signal phy_tx_data : std_logic_vector(7 downto 0);
signal phy_tx_en : std_ulogic;
signal phy_tx_er : std_ulogic;
signal phy_mii_clk : std_ulogic;
signal phy_rst_n : std_ulogic;
signal phy_gtx_clk : std_ulogic;
signal phy_mii_int_n : std_ulogic;
signal clk27 : std_ulogic := '0';
signal clk200p : std_ulogic := '0';
signal clk200n : std_ulogic := '1';
signal clk33 : std_ulogic := '0';
signal clkethp : std_ulogic := '0';
signal clkethn : std_ulogic := '1';
signal txp1 : std_logic;
signal txn : std_logic;
signal rxp : std_logic := '1';
signal rxn : std_logic := '0';
signal iic_scl : std_ulogic;
signal iic_sda : std_ulogic;
signal ddc_scl : std_ulogic;
signal ddc_sda : std_ulogic;
signal dvi_iic_scl : std_logic;
signal dvi_iic_sda : std_logic;
signal tft_lcd_data : std_logic_vector(11 downto 0);
signal tft_lcd_clk_p : std_ulogic;
signal tft_lcd_clk_n : std_ulogic;
signal tft_lcd_hsync : std_ulogic;
signal tft_lcd_vsync : std_ulogic;
signal tft_lcd_de : std_ulogic;
signal tft_lcd_reset_b : std_ulogic;
-- DDR3 memory
signal ddr3_dq : std_logic_vector(63 downto 0);
signal ddr3_dqs_p : std_logic_vector(7 downto 0);
signal ddr3_dqs_n : std_logic_vector(7 downto 0);
signal ddr3_addr : std_logic_vector(13 downto 0);
signal ddr3_ba : std_logic_vector(2 downto 0);
signal ddr3_ras_n : std_logic;
signal ddr3_cas_n : std_logic;
signal ddr3_we_n : std_logic;
signal ddr3_reset_n : std_logic;
signal ddr3_ck_p : std_logic_vector(0 downto 0);
signal ddr3_ck_n : std_logic_vector(0 downto 0);
signal ddr3_cke : std_logic_vector(0 downto 0);
signal ddr3_cs_n : std_logic_vector(0 downto 0);
signal ddr3_dm : std_logic_vector(7 downto 0);
signal ddr3_odt : std_logic_vector(0 downto 0);
-- SPI flash
signal spi_sel_n : std_ulogic;
signal spi_clk : std_ulogic;
signal spi_mosi : std_ulogic;
signal dsurst : std_ulogic;
signal errorn : std_logic;
signal switch : std_logic_vector(4 downto 0); -- I/O port
signal led : std_logic_vector(6 downto 0); -- I/O port
constant lresp : boolean := false;
signal tdqs_n : std_logic;
signal gmii_tx_clk : std_logic;
signal gmii_rx_clk : std_logic;
signal gmii_txd : std_logic_vector(7 downto 0);
signal gmii_tx_en : std_logic;
signal gmii_tx_er : std_logic;
signal gmii_rxd : std_logic_vector(7 downto 0);
signal gmii_rx_dv : std_logic;
signal gmii_rx_er : std_logic;
signal configuration_finished : boolean;
signal speed_is_10_100 : std_logic;
signal speed_is_100 : std_logic;
signal usb_clkout : std_logic := '0';
signal usb_d : std_logic_vector(7 downto 0);
signal usb_resetn : std_ulogic;
signal usb_nxt : std_ulogic;
signal usb_stp : std_ulogic;
signal usb_dir : std_ulogic;
-- GRUSB_DCL test signals
signal ddelay : std_ulogic := '0';
signal dstart : std_ulogic := '0';
signal drw : std_ulogic;
signal daddr : std_logic_vector(31 downto 0);
signal dlen : std_logic_vector(14 downto 0);
signal ddi : grusb_dcl_debug_data;
signal ddone : std_ulogic;
signal ddo : grusb_dcl_debug_data;
signal phy_mdio : std_logic;
signal phy_mdc : std_ulogic;
signal txp_eth, txn_eth : std_logic;
begin
-- clock and reset
clk200p <= not clk200p after 2.5 ns;
clk200n <= not clk200n after 2.5 ns;
clkethp <= not clkethp after 4 ns;
clkethn <= not clkethp after 4 ns;
rst <= not dsurst;
rxd1 <= 'H'; ctsn1 <= '0';
rxd2 <= 'H'; ctsn2 <= '0';
button <= "0000";
switch(3 downto 0) <= "0000";
cpu : entity work.leon3mp
generic map (
fabtech => fabtech,
memtech => memtech,
padtech => padtech,
clktech => clktech,
disas => disas,
dbguart => dbguart,
pclow => pclow,
SIM_BYPASS_INIT_CAL => SIM_BYPASS_INIT_CAL,
SIMULATION => SIMULATION,
USE_MIG_INTERFACE_MODEL => USE_MIG_INTERFACE_MODEL,
autonegotiation => 0
)
port map (
reset => rst,
clk200p => clk200p,
clk200n => clk200n,
address => address,
data => data,
oen => oen,
writen => writen,
romsn => romsn,
adv => adv,
ddr3_dq => ddr3_dq,
ddr3_dqs_p => ddr3_dqs_p,
ddr3_dqs_n => ddr3_dqs_n,
ddr3_addr => ddr3_addr,
ddr3_ba => ddr3_ba,
ddr3_ras_n => ddr3_ras_n,
ddr3_cas_n => ddr3_cas_n,
ddr3_we_n => ddr3_we_n,
ddr3_reset_n => ddr3_reset_n,
ddr3_ck_p => ddr3_ck_p,
ddr3_ck_n => ddr3_ck_n,
ddr3_cke => ddr3_cke,
ddr3_cs_n => ddr3_cs_n,
ddr3_dm => ddr3_dm,
ddr3_odt => ddr3_odt,
dsurx => dsurx,
dsutx => dsutx,
dsuctsn => dsuctsn,
dsurtsn => dsurtsn,
button => button,
switch => switch,
led => led,
iic_scl => iic_scl,
iic_sda => iic_sda,
usb_refclk_opt => '0',
usb_clkout => usb_clkout,
usb_d => usb_d,
usb_nxt => usb_nxt,
usb_stp => usb_stp,
usb_dir => usb_dir,
usb_resetn => usb_resetn,
gtrefclk_p => clkethp,
gtrefclk_n => clkethn,
txp => txp_eth,
txn => txn_eth,
rxp => txp_eth,
rxn => txn_eth,
emdio => phy_mdio,
emdc => phy_mdc,
eint => '0',
erst => OPEN,
can_txd => OPEN,
can_rxd => "0",
spi_data_out => '0',
spi_data_in => OPEN,
spi_data_cs_b => OPEN,
spi_clk => OPEN
);
phy0 : if (CFG_GRETH = 1) generate
phy_mdio <= 'H';
p0: phy
generic map (
address => 7,
extended_regs => 1,
aneg => 1,
base100_t4 => 1,
base100_x_fd => 1,
base100_x_hd => 1,
fd_10 => 1,
hd_10 => 1,
base100_t2_fd => 1,
base100_t2_hd => 1,
base1000_x_fd => 1,
base1000_x_hd => 1,
base1000_t_fd => 1,
base1000_t_hd => 1,
rmii => 0,
rgmii => 1
)
port map(dsurst, phy_mdio, OPEN , OPEN , OPEN ,
OPEN , OPEN , OPEN , OPEN , "00000000",
'0', '0', phy_mdc, clkethp);
end generate;
prom0 : for i in 0 to 1 generate
sr0 : sram generic map (index => i+4, abits => 26, fname => promfile)
port map (address(25 downto 0), data(15-i*8 downto 8-i*8), romsn,
writen, oen);
end generate;
-- Memory model instantiation
gen_mem_model : if (USE_MIG_INTERFACE_MODEL /= true) generate
ddr3mem : if (CFG_MIG_7SERIES = 1) generate
u1 : ddr3ram
generic map (
width => 64,
abits => 14,
colbits => 10,
rowbits => 10,
implbanks => 1,
fname => ramfile,
lddelay => (0 ns),
ldguard => 1,
speedbin => 9, --DDR3-1600K
density => 3,
pagesize => 1,
changeendian => 8)
port map (
ck => ddr3_ck_p(0),
ckn => ddr3_ck_n(0),
cke => ddr3_cke(0),
csn => ddr3_cs_n(0),
odt => ddr3_odt(0),
rasn => ddr3_ras_n,
casn => ddr3_cas_n,
wen => ddr3_we_n,
dm => ddr3_dm,
ba => ddr3_ba,
a => ddr3_addr,
resetn => ddr3_reset_n,
dq => ddr3_dq,
dqs => ddr3_dqs_p,
dqsn => ddr3_dqs_n,
doload => led(3)
);
end generate ddr3mem;
end generate gen_mem_model;
mig_mem_model : if (USE_MIG_INTERFACE_MODEL = true) generate
ddr3_dq <= (others => 'Z');
ddr3_dqs_p <= (others => 'Z');
ddr3_dqs_n <= (others => 'Z');
end generate mig_mem_model;
errorn <= led(1);
errorn <= 'H'; -- ERROR pull-up
usbtr: if (CFG_GRUSBHC = 1) generate
u0: ulpi
port map (usb_clkout, usb_d, usb_nxt, usb_stp, usb_dir, usb_resetn);
end generate usbtr;
usbdevsim: if (CFG_GRUSBDC = 1) generate
u0: grusbdcsim
generic map (functm => 0, keepclk => 1)
port map (usb_resetn, usb_clkout, usb_d, usb_nxt, usb_stp, usb_dir);
end generate usbdevsim;
usb_dclsim: if (CFG_GRUSB_DCL = 1) generate
u0: grusb_dclsim
generic map (functm => 0, keepclk => 1)
port map (usb_resetn, usb_clkout, usb_d, usb_nxt, usb_stp, usb_dir,
ddelay, dstart, drw, daddr, dlen, ddi, ddone, ddo);
usb_dcl_proc : process
begin
wait for 10 ns;
Print("GRUSB_DCL test started");
wait until rising_edge(ddone);
-- Write 128 bytes to memory
daddr <= X"40000000";
dlen <= conv_std_logic_vector(32,15);
for i in 0 to 127 loop
ddi(i) <= conv_std_logic_vector(i+8,8);
end loop; -- i
grusb_dcl_write(usb_clkout, drw, dstart, ddone);
-- Read back written data
grusb_dcl_read(usb_clkout, drw, dstart, ddone);
-- Compare data
for i in 0 to 127 loop
if ddo(i) /= ddi(i) then
Print("ERROR: Data mismatch using GRUSB_DCL");
end if;
end loop;
Print("GRUSB_DCL test finished");
wait;
end process;
end generate usb_dclsim;
iuerr : process
begin
wait for 210 us; -- This is for proper DDR3 behaviour durign init phase not needed durin simulation
if (USE_MIG_INTERFACE_MODEL /= true) then
wait on led(3); -- DDR3 Memory Init ready
end if;
wait for 5000 ns;
if to_x01(errorn) = '1' then
wait on errorn;
end if;
assert (to_x01(errorn) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure ; -- this should be a failure
end process;
data <= buskeep(data) after 5 ns;
dsucom : process
procedure dsucfg(signal dsurx : in std_ulogic; signal dsutx : out std_ulogic) is
variable w32 : std_logic_vector(31 downto 0);
variable c8 : std_logic_vector(7 downto 0);
constant txp : time := 320 * 1 ns;
begin
dsutx <= '1';
dsurst <= '0';
switch(4) <= '0';
wait for 2500 ns;
if (USE_MIG_INTERFACE_MODEL /= true) then
wait for 210 us; -- This is for proper DDR3 behaviour durign init phase not needed durin simulation
end if;
dsurst <= '1';
switch(4) <= '1';
if (USE_MIG_INTERFACE_MODEL /= true) then
wait on led(3); -- Wait for DDR3 Memory Init ready
end if;
report "Start DSU transfer";
wait for 5000 ns;
txc(dsutx, 16#55#, txp); -- sync uart
-- Reads from memory and DSU register to mimic GRMON during simulation
l1 : loop
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#04#, txp);
rxi(dsurx, w32, txp, lresp);
--report "DSU read memory " & tost(w32);
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
rxi(dsurx, w32, txp, lresp);
--report "DSU Break and Single Step register" & tost(w32);
end loop l1;
wait;
-- ** This is only kept for reference --
-- do test read and writes to DDR3 to check status
-- Write
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#01#, 16#23#, 16#45#, 16#67#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#04#, txp);
txa(dsutx, 16#89#, 16#AB#, 16#CD#, 16#EF#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#08#, txp);
txa(dsutx, 16#08#, 16#19#, 16#2A#, 16#3B#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#0C#, txp);
txa(dsutx, 16#4C#, 16#5D#, 16#6E#, 16#7F#, txp);
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#04#, txp);
rxi(dsurx, w32, txp, lresp);
report "* Read " & tost(w32);
txc(dsutx, 16#a0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#08#, txp);
rxi(dsurx, w32, txp, lresp);
txc(dsutx, 16#a0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#0C#, txp);
rxi(dsurx, w32, txp, lresp);
wait;
-- Register 0x90000000 (DSU Control Register)
-- Data 0x0000202e (b0010 0000 0010 1110)
-- [0] - Trace Enable
-- [1] - Break On Error
-- [2] - Break on IU watchpoint
-- [3] - Break on s/w break points
--
-- [4] - (Break on trap)
-- [5] - Break on error traps
-- [6] - Debug mode (Read mode only)
-- [7] - DSUEN (read mode)
--
-- [8] - DSUBRE (read mode)
-- [9] - Processor mode error (clears error)
-- [10] - processor halt (returns 1 if processor halted)
-- [11] - power down mode (return 1 if processor in power down mode)
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#80#, 16#02#, txp);
wait;
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#20#, 16#2e#, txp);
wait for 25000 ns;
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#01#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#24#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0D#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#70#, 16#11#, 16#78#, txp);
txa(dsutx, 16#91#, 16#00#, 16#00#, 16#0D#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#44#, txp);
txa(dsutx, 16#00#, 16#00#, 16#20#, 16#00#, txp);
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#44#, txp);
wait;
end;
begin
dsuctsn <= '0';
dsucfg(dsutx, dsurx);
wait;
end process;
end ;
| gpl-3.0 |
EliasLuiz/TCC | Leon3/designs/leon3-gr-pci-xc5v/leon3mp.vhd | 1 | 57269 | -----------------------------------------------------------------------------
-- LEON Demonstration design
-- Copyright (C) 2010 - 2015 Cobham Gaisler AB
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib, techmap;
use grlib.amba.all;
use grlib.stdlib.all;
use techmap.gencomp.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.can.all;
use gaisler.pci.all;
use gaisler.net.all;
use gaisler.jtag.all;
use gaisler.spacewire.all;
use gaisler.grusb.all;
use gaisler.l2cache.all;
use gaisler.subsys.all;
use gaisler.gr1553b_pkg.all;
library esa;
use esa.memoryctrl.all;
use esa.pcicomp.all;
use work.config.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
port (
resetn : in std_logic;
clk : in std_logic;
pllref : in std_logic;
errorn : out std_logic;
wdogn : out std_logic;
address : out std_logic_vector(27 downto 0);
data : inout std_logic_vector(31 downto 0);
cb : inout std_logic_vector(7 downto 0);
sa : out std_logic_vector(14 downto 0);
sd : inout std_logic_vector(63 downto 0);
sdclk : out std_logic;
sdcke : out std_logic_vector (1 downto 0); -- sdram clock enable
sdcsn : out std_logic_vector (1 downto 0); -- sdram chip select
sdwen : out std_logic; -- sdram write enable
sdrasn : out std_logic; -- sdram ras
sdcasn : out std_logic; -- sdram cas
sddqm : out std_logic_vector (7 downto 0); -- sdram dqm
dsutx : out std_logic; -- DSU tx data
dsurx : in std_logic; -- DSU rx data
dsuen : in std_logic;
dsubre : in std_logic;
dsuact : out std_logic;
txd1 : out std_logic; -- UART1 tx data
rxd1 : in std_logic; -- UART1 rx data
txd2 : out std_logic; -- UART2 tx data
rxd2 : in std_logic; -- UART2 rx data
ramsn : out std_logic_vector (4 downto 0);
ramoen : out std_logic_vector (4 downto 0);
rwen : out std_logic_vector (3 downto 0);
oen : out std_logic;
writen : out std_logic;
read : out std_logic;
iosn : out std_logic;
romsn : out std_logic_vector (1 downto 0);
brdyn : in std_logic; -- bus ready
bexcn : in std_logic; -- bus exception
gpio : inout std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0); -- I/O port
emdio : inout std_logic; -- ethernet PHY interface
eth_macclk : in std_logic;
etx_clk : in std_logic;
erx_clk : in std_logic;
erxd : in std_logic_vector(7 downto 0);
erx_dv : in std_logic;
erx_er : in std_logic;
erx_col : in std_logic;
erx_crs : in std_logic;
emdintn : in std_logic;
etxd : out std_logic_vector(7 downto 0);
etx_en : out std_logic;
etx_er : out std_logic;
emdc : out std_logic;
pci_rst : inout std_logic; -- PCI bus
pci_clk : in std_logic;
pci_gnt : in std_logic;
pci_idsel : in std_logic;
pci_lock : inout std_logic;
pci_ad : inout std_logic_vector(31 downto 0);
pci_cbe : inout std_logic_vector(3 downto 0);
pci_frame : inout std_logic;
pci_irdy : inout std_logic;
pci_trdy : inout std_logic;
pci_devsel : inout std_logic;
pci_stop : inout std_logic;
pci_perr : inout std_logic;
pci_par : inout std_logic;
pci_req : inout std_logic;
pci_serr : inout std_logic;
pci_host : in std_logic;
pci_66 : in std_logic;
pci_arb_req : in std_logic_vector(0 to 3);
pci_arb_gnt : out std_logic_vector(0 to 3);
can_txd : out std_logic_vector(0 to CFG_CAN_NUM-1);
can_rxd : in std_logic_vector(0 to CFG_CAN_NUM-1);
-- can_stb : out std_logic_vector(0 to CFG_CAN_NUM-1)
spw_clk : in std_logic;
spw_rxdp : in std_logic_vector(0 to CFG_SPW_NUM-1);
spw_rxdn : in std_logic_vector(0 to CFG_SPW_NUM-1);
spw_rxsp : in std_logic_vector(0 to CFG_SPW_NUM-1);
spw_rxsn : in std_logic_vector(0 to CFG_SPW_NUM-1);
spw_txdp : out std_logic_vector(0 to CFG_SPW_NUM-1);
spw_txdn : out std_logic_vector(0 to CFG_SPW_NUM-1);
spw_txsp : out std_logic_vector(0 to CFG_SPW_NUM-1);
spw_txsn : out std_logic_vector(0 to CFG_SPW_NUM-1);
usb_clkout : in std_logic;
usb_d : inout std_logic_vector(7 downto 0);
usb_nxt : in std_logic;
usb_stp : out std_logic;
usb_dir : in std_logic;
usb_resetn : out std_ulogic;
busainen : out std_logic_vector(0 to 0);
busainp : in std_logic_vector(0 to 0);
busainn : in std_logic_vector(0 to 0);
busaoutin : out std_logic_vector(0 to 0);
busaoutp : out std_logic_vector(0 to 0);
busaoutn : out std_logic_vector(0 to 0);
busbinen : out std_logic_vector(0 to 0);
busbinp : in std_logic_vector(0 to 0);
busbinn : in std_logic_vector(0 to 0);
busboutin : out std_logic_vector(0 to 0);
busboutp : out std_logic_vector(0 to 0);
busboutn : out std_logic_vector(0 to 0)
);
end;
architecture rtl of leon3mp is
constant blength : integer := 12;
constant fifodepth : integer := 8;
signal vcc, gnd : std_logic_vector(4 downto 0);
signal lresetn : std_ulogic;
signal memi : memory_in_type;
signal memo : memory_out_type;
signal wpo : wprot_out_type;
signal sdi : sdctrl_in_type;
signal sdo : sdram_out_type;
signal sdo2, sdo3 : sdctrl_out_type;
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal sdram_ahbsi : ahb_slv_in_type;
signal sdram_ahbso : ahb_slv_out_vector_type(1 downto 0);
signal clkm, rstn, rstraw, pciclk, sdclkl : std_logic;
signal cgi, cgi2 : clkgen_in_type;
signal cgo, cgo2, cgo1553 : clkgen_out_type;
signal u1i, u2i, dui : uart_in_type;
signal u1o, u2o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to CFG_NCPU-1);
signal irqo : irq_out_vector(0 to CFG_NCPU-1);
signal sysi : leon_dsu_stat_base_in_type;
signal syso : leon_dsu_stat_base_out_type;
signal perf : l3stat_in_type;
signal pcii : pci_in_type;
signal pcio : pci_out_type;
signal spwi : grspw_in_type_vector(0 to CFG_SPW_NUM-1);
signal spwo : grspw_out_type_vector(0 to CFG_SPW_NUM-1);
signal spw_clkl : std_logic;
signal spw_rxclk : std_logic_vector(0 to CFG_SPW_NUM-1);
signal dtmp : std_logic_vector(0 to CFG_SPW_NUM-1);
signal stmp : std_logic_vector(0 to CFG_SPW_NUM-1);
signal spw_rxtxclk : std_ulogic;
signal spw_rxclkn : std_ulogic;
signal stati : ahbstat_in_type;
signal ethi, ethi1, ethi2 : eth_in_type;
signal etho, etho1, etho2 : eth_out_type;
signal ethclk, egtx_clk_fb : std_logic;
signal egtx_clk, legtx_clk, l2egtx_clk : std_logic;
signal gpti : gptimer_in_type;
signal gpto : gptimer_out_type;
signal wdog : std_logic;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
signal clklock, elock, ulock : std_ulogic;
signal can_lrx, can_ltx : std_logic_vector(0 to 7);
signal lclk, pci_lclk : std_logic;
signal pci_arb_req_n, pci_arb_gnt_n : std_logic_vector(0 to 3);
signal pci_dirq : std_logic_vector(3 downto 0);
signal tck, tms, tdi, tdo : std_logic;
signal usbi : grusb_in_vector(0 downto 0);
signal usbo : grusb_out_vector(0 downto 0);
signal uclk : std_ulogic := '0';
type milout_array is array (0 to 0) of gr1553b_txout_type;
type milin_array is array (0 to 0) of gr1553b_rxin_type;
signal clk1553,rst1553: std_ulogic;
signal milout: milout_array;
signal milin: milin_array;
constant BOARD_FREQ : integer := 50000; -- Board frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz
constant IOAEN : integer := CFG_CAN + CFG_GRPCI2_MASTER + CFG_GRUSBHC +
CFG_GRUSBDC+1;
constant CFG_SDEN : integer := CFG_MCTRL_SDEN + CFG_SDCTRL + CFG_MCTRLFT_SDEN;
constant CFG_INVCLK : integer := CFG_MCTRL_INVCLK + CFG_MCTRLFT_INVCLK + CFG_SDCTRL_INVCLK;
constant OEPOL : integer := padoen_polarity(padtech);
attribute syn_keep : boolean;
attribute syn_preserve : boolean;
attribute keep : boolean;
begin
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= (others => '1'); gnd <= (others => '0');
cgi.pllctrl <= "00"; cgi.pllrst <= rstraw;
pllref_pad : clkpad generic map (tech => padtech) port map (pllref, cgi.pllref);
clk_pad : clkpad generic map (tech => padtech) port map (clk, lclk);
pci_clk_pad : clkpad generic map (tech => padtech, level => pci33)
port map (pci_clk, pci_lclk);
clkgen0 : clkgen -- clock generator
generic map (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_SDEN,
CFG_INVCLK, CFG_GRPCI2_MASTER+CFG_GRPCI2_TARGET, CFG_PCIDLL, CFG_PCISYSCLK, BOARD_FREQ)
port map (lclk, pci_lclk, clkm, open, open, sdclkl, pciclk, cgi, cgo);
sdclk_pad : outpad generic map (tech => padtech, slew => 1)
port map (sdclk, sdclkl);
resetn_pad : inpad generic map (tech => padtech) port map (resetn, lresetn);
rst0 : rstgen -- reset generator
port map (lresetn, clkm, clklock, rstn, rstraw);
clklock <= cgo.clklock and elock and ulock;
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT, fpnpen => 1,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, ioen => IOAEN,
nahbm => CFG_NCPU+CFG_AHB_UART+CFG_GRPCI2_TARGET+CFG_GRPCI2_DMA+CFG_AHB_JTAG+
CFG_GRETH+CFG_SPW_EN*CFG_SPW_NUM+
CFG_GRUSBHC*(CFG_GRUSBHC_EHC+CFG_GRUSBHC_UHC)+
CFG_GRUSBDC*CFG_GRUSBDC_AIFACE+
CFG_GRUSB_DCL,
nahbs => 8+CFG_GRUSBHC*CFG_GRUSBHC_UHC+CFG_GRUSBDC,
enbusmon => CFG_AHB_MON, assertwarn => CFG_AHB_MONWAR,
asserterr => CFG_AHB_MONERR, ahbtrace => CFG_AHB_DTRACE)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON processor and DSU -----------------------------------------
----------------------------------------------------------------------
leon : leon_dsu_stat_base
generic map (
leon => CFG_LEON, ncpu => CFG_NCPU, fabtech => fabtech, memtech => memtech,
nwindows => CFG_NWIN, dsu => CFG_DSU, fpu => CFG_FPU, v8 => CFG_V8, cp => 0,
mac => CFG_MAC, pclow => pclow, notag => 0, nwp => CFG_NWP, icen => CFG_ICEN,
irepl => CFG_IREPL, isets => CFG_ISETS, ilinesize => CFG_ILINE,
isetsize => CFG_ISETSZ, isetlock => CFG_ILOCK, dcen => CFG_DCEN,
drepl => CFG_DREPL, dsets => CFG_DSETS, dlinesize => CFG_DLINE,
dsetsize => CFG_DSETSZ, dsetlock => CFG_DLOCK, dsnoop => CFG_DSNOOP,
ilram => CFG_ILRAMEN, ilramsize => CFG_ILRAMSZ, ilramstart => CFG_ILRAMADDR,
dlram => CFG_DLRAMEN, dlramsize => CFG_DLRAMSZ, dlramstart => CFG_DLRAMADDR,
mmuen => CFG_MMUEN, itlbnum => CFG_ITLBNUM, dtlbnum => CFG_DTLBNUM,
tlb_type => CFG_TLB_TYPE, tlb_rep => CFG_TLB_REP, lddel => CFG_LDDEL,
disas => disas, tbuf => CFG_ITBSZ, pwd => CFG_PWD, svt => CFG_SVT,
rstaddr => CFG_RSTADDR, smp => CFG_NCPU-1, cached => CFG_DFIXED,
wbmask => CFG_BWMASK, busw => CFG_CACHEBW, netlist => CFG_LEON_NETLIST,
ft => CFG_LEONFT_EN, npasi => CFG_NP_ASI, pwrpsr => CFG_WRPSR,
rex => CFG_REX, altwin => CFG_ALTWIN, grfpush => CFG_GRFPUSH,
dsu_hindex => 2, dsu_haddr => 16#900#, dsu_hmask => 16#F00#, atbsz => CFG_ATBSZ,
stat => CFG_STAT_ENABLE, stat_pindex => 12, stat_paddr => 16#100#,
stat_pmask => 16#ffc#, stat_ncnt => CFG_STAT_CNT, stat_nmax => CFG_STAT_NMAX)
port map (
rstn => rstn, ahbclk => clkm, cpuclk => clkm, hclken => vcc(0),
leon_ahbmi => ahbmi, leon_ahbmo => ahbmo(CFG_NCPU-1 downto 0),
leon_ahbsi => ahbsi, leon_ahbso => ahbso,
irqi => irqi, irqo => irqo,
stat_apbi => apbi, stat_apbo => apbo(12), stat_ahbsi => ahbsi,
stati => perf,
dsu_ahbsi => ahbsi, dsu_ahbso => ahbso(2),
dsu_tahbmi => ahbmi, dsu_tahbsi => ahbsi,
sysi => sysi, syso => syso);
dsuen_pad : inpad generic map (tech => padtech) port map (dsuen, sysi.dsu_enable);
dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, sysi.dsu_break);
dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, syso.dsu_active);
errorn_pad : odpad generic map (tech => padtech) port map (errorn, syso.proc_error);
dcomgen : if CFG_AHB_UART = 1 generate
dcom0: ahbuart -- Debug UART
generic map (hindex => CFG_NCPU, pindex => 7, paddr => 7)
port map (rstn, clkm, dui, duo, apbi, apbo(7), ahbmi, ahbmo(CFG_NCPU));
dsurx_pad : inpad generic map (tech => padtech) port map (dsurx, dui.rxd);
dsutx_pad : outpad generic map (tech => padtech) port map (dsutx, duo.txd);
end generate;
-- nouah : if CFG_AHB_UART = 0 generate apbo(7) <= apb_none; end generate;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => CFG_NCPU+CFG_AHB_UART)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART),
open, open, open, open, open, open, open, gnd(0));
end generate;
-----------------------------------------------------------------------
--- L2-Cache --------------------------------------------------------
-----------------------------------------------------------------------
l2cen : if CFG_L2_EN /= 0 generate
l2cblock : block
signal mem_ahbsi : ahb_slv_in_type;
signal mem_ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal mem_ahbmi : ahb_mst_in_type;
signal mem_ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal l2c_stato : std_logic_vector(10 downto 0);
begin
l2c0 : l2c generic map (
hslvidx => 0, hmstidx => 0, cen => CFG_L2_PEN,
haddr => 16#400#, hmask => 16#c00#, ioaddr => 16#FF0#,
cached => CFG_L2_MAP, repl => CFG_L2_RAN, ways => CFG_L2_WAYS,
linesize => CFG_L2_LSZ, waysize => CFG_L2_SIZE,
memtech => memtech, bbuswidth => AHBDW,
bioaddr => 16#FFE#, biomask => 16#fff#,
sbus => 0, mbus => 1, arch => CFG_L2_SHARE,
ft => CFG_L2_EDAC)
port map(rst => rstn, clk => clkm, ahbsi => ahbsi, ahbso => ahbso(0),
ahbmi => mem_ahbmi, ahbmo => mem_ahbmo(0), ahbsov => mem_ahbso,
sto => l2c_stato);
memahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => 16#FFE#,
ioen => 1, nahbm => 1, nahbs => 2)
port map (rstn, clkm, mem_ahbmi, mem_ahbmo, mem_ahbsi, mem_ahbso);
mem_ahbso(1 downto 0) <= sdram_ahbso;
sdram_ahbsi <= mem_ahbsi;
perf.event(15 downto 7) <= (others => '0');
perf.esource(15 downto 7) <= (others => (others => '0'));
perf.event(6) <= l2c_stato(10); -- Data uncorrectable error
perf.event(5) <= l2c_stato(9); -- Data correctable error
perf.event(4) <= l2c_stato(8); -- Tag uncorrectable error
perf.event(3) <= l2c_stato(7); -- Tag correctable error
perf.event(2) <= l2c_stato(2); -- Bus access
perf.event(1) <= l2c_stato(1); -- Miss
perf.event(0) <= l2c_stato(0); -- Hit
perf.esource(6 downto 3) <= (others => (others => '0'));
perf.esource(2 downto 0) <= (others => l2c_stato(6 downto 3));
perf.req <= (others => '0');
perf.sel <= (others => '0');
perf.latcnt <= '0';
--perf.timer <= dbgi(0).timer(31 downto 0);
end block l2cblock;
end generate l2cen;
nol2c : if CFG_L2_EN = 0 generate
ahbso(1 downto 0) <= sdram_ahbso;
sdram_ahbsi <= ahbsi;
perf <= l3stat_in_none;
end generate;
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
memi.edac <= gpioo.val(2); memi.bwidth <= gpioo.val(1 downto 0);
src : if CFG_SRCTRL = 1 generate -- 32-bit PROM/SRAM controller
sr0 : srctrl generic map (hindex => 0, ramws => CFG_SRCTRL_RAMWS,
romws => CFG_SRCTRL_PROMWS, ramaddr => 16#400#,
rammask => 16#E00#*(1-CFG_SDCTRL), romasel => CFG_SRCTRL_ROMASEL,
prom8en => CFG_SRCTRL_8BIT, rmw => CFG_SRCTRL_RMW)
port map (rstn, clkm, sdram_ahbsi, sdram_ahbso(0), memi, memo, sdo3);
apbo(0) <= apb_none;
addr_pad : outpadv generic map (width => 28, tech => padtech)
port map (address, memo.address(27 downto 0));
rams_pad : outpadv generic map (width => 5, tech => padtech)
port map (ramsn, memo.ramsn(4 downto 0));
roms_pad : outpadv generic map (width => 2, tech => padtech)
port map (romsn, memo.romsn(1 downto 0));
oen_pad : outpad generic map (tech => padtech)
port map (oen, memo.oen);
rwen_pad : outpadv generic map (width => 4, tech => padtech)
port map (rwen, memo.wrn);
roen_pad : outpadv generic map (width => 5, tech => padtech)
port map (ramoen, memo.ramoen(4 downto 0));
wri_pad : outpad generic map (tech => padtech)
port map (writen, memo.writen);
read_pad : outpad generic map (tech => padtech)
port map (read, memo.read);
iosn_pad : outpad generic map (tech => padtech)
port map (iosn, memo.iosn);
data_pad : iopadvv generic map (tech => padtech, width => 32, oepol => OEPOL)
port map (data, memo.data, memo.vbdrive, memi.data);
brdyn_pad : inpad generic map (tech => padtech) port map (brdyn, memi.brdyn);
bexcn_pad : inpad generic map (tech => padtech) port map (bexcn, memi.bexcn);
memi.writen <= '1'; memi.wrn <= "1111";
end generate;
sdc : if CFG_SDCTRL = 1 generate
sdc : sdctrl64 generic map (hindex => 1, haddr => 16#400#, hmask => 16#C00#,
ioaddr => 1, fast => 0, pwron => 0, invclk => CFG_SDCTRL_INVCLK)
port map (rstn, clkm, sdram_ahbsi, sdram_ahbso(1), sdi, sdo2);
sa_pad : outpadv generic map (tech => padtech, width => 15)
port map (sa, sdo2.address);
sd_pad : iopadv generic map (width => 32, tech => padtech)
port map (sd(31 downto 0), sdo2.data(31 downto 0), sdo2.bdrive, sdi.data(31 downto 0));
-- sd2 : if CFG_SDCTRL_SD64 = 1 generate
sd_pad2 : iopadv generic map (width => 32)
port map (sd(63 downto 32), sdo2.data(63 downto 32), sdo2.bdrive, sdi.data(63 downto 32));
-- end generate;
sdcke_pad : outpadv generic map (width =>2, tech => padtech)
port map (sdcke, sdo2.sdcke);
sdwen_pad : outpad generic map (tech => padtech)
port map (sdwen, sdo2.sdwen);
sdcsn_pad : outpadv generic map (width =>2, tech => padtech)
port map (sdcsn, sdo2.sdcsn);
sdras_pad : outpad generic map (tech => padtech)
port map (sdrasn, sdo2.rasn);
sdcas_pad : outpad generic map (tech => padtech)
port map (sdcasn, sdo2.casn);
sddqm_pad : outpadv generic map (width =>8, tech => padtech)
port map (sddqm, sdo2.dqm(7 downto 0));
end generate;
mctrl0 : if CFG_MCTRL_LEON2 = 1 generate -- LEON2 memory controller
sr1 : mctrl generic map (hindex => 0, pindex => 0, paddr => 0,
srbanks => 4, sden => CFG_MCTRL_SDEN, ram8 => CFG_MCTRL_RAM8BIT,
ram16 => CFG_MCTRL_RAM16BIT, invclk => CFG_MCTRL_INVCLK,
sepbus => CFG_MCTRL_SEPBUS, oepol => OEPOL,
sdbits => 32 + 32*CFG_MCTRL_SD64, pageburst => CFG_MCTRL_PAGE)
port map (rstn, clkm, memi, memo, sdram_ahbsi, sdram_ahbso(0), apbi, apbo(0), wpo, sdo);
addr_pad : outpadv generic map (width => 28, tech => padtech)
port map (address, memo.address(27 downto 0));
rams_pad : outpadv generic map (width => 5, tech => padtech)
port map (ramsn, memo.ramsn(4 downto 0));
roms_pad : outpadv generic map (width => 2, tech => padtech)
port map (romsn, memo.romsn(1 downto 0));
oen_pad : outpad generic map (tech => padtech)
port map (oen, memo.oen);
rwen_pad : outpadv generic map (width => 4, tech => padtech)
port map (rwen, memo.wrn);
roen_pad : outpadv generic map (width => 5, tech => padtech)
port map (ramoen, memo.ramoen(4 downto 0));
wri_pad : outpad generic map (tech => padtech)
port map (writen, memo.writen);
read_pad : outpad generic map (tech => padtech)
port map (read, memo.read);
iosn_pad : outpad generic map (tech => padtech)
port map (iosn, memo.iosn);
data_pad : iopadvv generic map (tech => padtech, width => 32, oepol => OEPOL)
port map (data, memo.data, memo.vbdrive, memi.data);
brdyn_pad : inpad generic map (tech => padtech) port map (brdyn, memi.brdyn);
bexcn_pad : inpad generic map (tech => padtech) port map (bexcn, memi.bexcn);
memi.writen <= '1'; memi.wrn <= "1111";
sdpads : if CFG_MCTRL_SDEN = 1 generate -- SDRAM controller
sd2 : if CFG_MCTRL_SEPBUS = 1 generate
sa_pad : outpadv generic map (tech => padtech, width => 15) port map (sa, memo.sa);
sd_pad : iopadvv generic map (tech => padtech, width => 32, oepol => OEPOL)
port map (sd(31 downto 0), memo.sddata(31 downto 0),
memo.svbdrive(31 downto 0), memi.sd(31 downto 0));
sd2 : if CFG_MCTRL_SD64 = 1 generate
sd_pad2 : iopadvv generic map (tech => padtech, width => 32)
port map (sd(63 downto 32), memo.sddata(63 downto 32),
memo.svbdrive(63 downto 32), memi.sd(63 downto 32));
end generate;
end generate;
sdwen_pad : outpad generic map (tech => padtech)
port map (sdwen, sdo.sdwen);
sdras_pad : outpad generic map (tech => padtech)
port map (sdrasn, sdo.rasn);
sdcas_pad : outpad generic map (tech => padtech)
port map (sdcasn, sdo.casn);
sddqm_pad : outpadv generic map (width => 8, tech => padtech)
port map (sddqm, sdo.dqm);
sdcke_pad : outpadv generic map (width => 2, tech => padtech)
port map (sdcke, sdo.sdcke);
sdcsn_pad : outpadv generic map (width => 2, tech => padtech)
port map (sdcsn, sdo.sdcsn);
end generate;
end generate;
mg2 : if CFG_MCTRLFT = 1 generate -- FT memory controller
sr1 : ftmctrl generic map (hindex => 0, pindex => 0,
paddr => 0, srbanks => 4, sden => CFG_MCTRLFT_SDEN, ram8 => CFG_MCTRLFT_RAM8BIT,
ram16 => CFG_MCTRLFT_RAM16BIT, invclk => CFG_MCTRLFT_INVCLK,
sepbus => CFG_MCTRLFT_SEPBUS, oepol => OEPOL,
sdbits => 32 + 32*CFG_MCTRL_SD64, pageburst => CFG_MCTRL_PAGE,
edac => CFG_MCTRLFT_EDAC)
port map (rstn, clkm, memi, memo, sdram_ahbsi, sdram_ahbso(0), apbi, apbo(0), wpo, sdo);
addr_pad : outpadv generic map (width => 28, tech => padtech)
port map (address, memo.address(27 downto 0));
rams_pad : outpadv generic map (width => 5, tech => padtech)
port map (ramsn, memo.ramsn(4 downto 0));
roms_pad : outpadv generic map (width => 2, tech => padtech)
port map (romsn, memo.romsn(1 downto 0));
oen_pad : outpad generic map (tech => padtech)
port map (oen, memo.oen);
rwen_pad : outpadv generic map (width => 4, tech => padtech)
port map (rwen, memo.wrn);
roen_pad : outpadv generic map (width => 5, tech => padtech)
port map (ramoen, memo.ramoen(4 downto 0));
wri_pad : outpad generic map (tech => padtech)
port map (writen, memo.writen);
read_pad : outpad generic map (tech => padtech)
port map (read, memo.read);
iosn_pad : outpad generic map (tech => padtech)
port map (iosn, memo.iosn);
data_pad : iopadvv generic map (tech => padtech, width => 32, oepol => OEPOL)
port map (data, memo.data, memo.vbdrive, memi.data);
cb_pad : iopadvv generic map (tech => padtech, width => 8, oepol => OEPOL)
port map (cb, memo.cb(7 downto 0), memo.vcdrive(7 downto 0), memi.cb(7 downto 0));
brdyn_pad : inpad generic map (tech => padtech) port map (brdyn, memi.brdyn);
bexcn_pad : inpad generic map (tech => padtech) port map (bexcn, memi.bexcn);
memi.writen <= '1'; memi.wrn <= "1111";
sdpads : if CFG_MCTRLFT_SDEN = 1 generate -- SDRAM controller
sd2 : if CFG_MCTRLFT_SEPBUS = 1 generate
sa_pad : outpadv generic map (tech => padtech, width => 15) port map (sa, memo.sa);
sd_pad : iopadvv generic map (tech => padtech, width => 32)
port map (sd(31 downto 0), memo.sddata(31 downto 0),
memo.svbdrive(31 downto 0), memi.sd(31 downto 0));
cbbits : if CFG_MCTRLFT_EDAC /= 0 generate
scb_pad : iopadvv generic map (tech => padtech, width => 16, oepol => OEPOL)
port map (sd(47 downto 32), memo.scb(15 downto 0), memo.svcdrive(15 downto 0), memi.scb(15 downto 0));
sd_pad : iopadvv generic map (tech => padtech, width => 16)
port map (sd(63 downto 48), memo.sddata(63 downto 48),
memo.svbdrive(63 downto 48), memi.sd(63 downto 48));
end generate;
sd64bits : if CFG_MCTRLFT_EDAC = 0 generate
sd_pad : iopadvv generic map (tech => padtech, width => 32)
port map (sd(63 downto 32), memo.sddata(63 downto 32),
memo.svbdrive(63 downto 32), memi.sd(63 downto 32));
end generate;
end generate;
sdwen_pad : outpad generic map (tech => padtech)
port map (sdwen, sdo.sdwen);
sdras_pad : outpad generic map (tech => padtech)
port map (sdrasn, sdo.rasn);
sdcas_pad : outpad generic map (tech => padtech)
port map (sdcasn, sdo.casn);
sddqm_pad : outpadv generic map (width =>8, tech => padtech)
port map (sddqm, sdo.dqm);
sdcke_pad : outpadv generic map (width =>2, tech => padtech)
port map (sdcke, sdo.sdcke);
sdcsn_pad : outpadv generic map (width =>2, tech => padtech)
port map (sdcsn, sdo.sdcsn);
end generate;
end generate;
nosd0 : if (CFG_SDEN = 0) generate -- no SDRAM controller
sdcke_pad : outpadv generic map (width =>2, tech => padtech)
port map (sdcke, vcc(1 downto 0));
sdcsn_pad : outpadv generic map (width =>2, tech => padtech)
port map (sdcsn, vcc(1 downto 0));
end generate;
-- No PROM/SRAM controller
mg0 : if (CFG_MCTRL_LEON2 + CFG_MCTRLFT + CFG_SRCTRL) = 0 generate
rams_pad : outpadv generic map (width => 5, tech => padtech)
port map (ramsn, vcc);
roms_pad : outpadv generic map (width => 2, tech => padtech)
port map (romsn, vcc(1 downto 0));
end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
apb0 : apbctrl -- AHB/APB bridge
generic map (hindex => 3, haddr => CFG_APBADDR)
port map (rstn, clkm, ahbsi, ahbso(3), apbi, apbo );
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.ctsn <= '0'; u1i.extclk <= '0';
txd1_pad : outpad generic map (tech => padtech)
port map (txd1, u1o.txd);
rxd1_pad : inpad generic map (tech => padtech)
port map (rxd1, u1i.rxd);
end generate;
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
ua2 : if CFG_UART2_ENABLE /= 0 generate
uart2 : apbuart -- UART 2
generic map (pindex => 6, paddr => 6, pirq => 3, fifosize => CFG_UART2_FIFO)
port map (rstn, clkm, apbi, apbo(6), u2i, u2o);
u2i.ctsn <= '0'; u2i.extclk <= '0';
txd1_pad : outpad generic map (tech => padtech)
port map (txd2, u2o.txd);
rxd1_pad : inpad generic map (tech => padtech)
port map (rxd2, u2i.rxd);
end generate;
noua1 : if CFG_UART2_ENABLE = 0 generate apbo(6) <= apb_none; end generate;
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp -- interrupt controller
generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to CFG_NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
-- apbo(2) <= apb_none;
end generate;
pci_dirq(3 downto 1) <= (others => '0');
pci_dirq(0) <= orv(irqi(0).irl);
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer -- timer unit
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
wdog => CFG_GPT_WDOGEN*CFG_GPT_WDOG, nbits => CFG_GPT_TW)
port map (rstn, clkm, apbi, apbo(3), gpti, gpto);
gpti <= gpti_dhalt_drive(syso.dsu_tstop);
wdog <= gpto.wdogn when OEPOL = 0 else gpto.wdog;
wdogn_pad : odpad generic map (tech => padtech, oepol => OEPOL) port map (wdogn, wdog);
end generate;
-- notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GR GPIO unit
grgpio0: grgpio
generic map( pindex => 9, paddr => 9, imask => CFG_GRGPIO_IMASK,
nbits => CFG_GRGPIO_WIDTH)
port map( rstn, clkm, apbi, apbo(9), gpioi, gpioo);
pio_pads : for i in 0 to CFG_GRGPIO_WIDTH-1 generate
pio_pad : iopad generic map (tech => padtech)
port map (gpio(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i));
end generate;
end generate;
ahbs : if CFG_AHBSTAT = 1 generate -- AHB status register
stati.cerror(0) <= memo.ce;
ahbstat0 : ahbstat generic map (pindex => 15, paddr => 15, pirq => 1,
nftslv => CFG_AHBSTATN)
port map (rstn, clkm, ahbmi, ahbsi, stati, apbi, apbo(15));
end generate;
nop2 : if CFG_AHBSTAT = 0 generate apbo(15) <= apb_none; end generate;
-----------------------------------------------------------------------
--- PCI ------------------------------------------------------------
-----------------------------------------------------------------------
pci : if (CFG_GRPCI2_MASTER+CFG_GRPCI2_TARGET) /= 0 generate
grpci2xt : if (CFG_GRPCI2_TARGET) /= 0 and (CFG_GRPCI2_MASTER+CFG_GRPCI2_DMA) = 0 generate
pci0 : grpci2
generic map (
memtech => memtech, oepol => OEPOL,
hmindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
hdmindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+1,
hsindex => 4, haddr => 16#C00#, hmask => 16#E00#, ioaddr => 16#400#,
pindex => 4, paddr => 4, irq => 4, irqmode => 0,
master => CFG_GRPCI2_MASTER, target => CFG_GRPCI2_TARGET,
dma => CFG_GRPCI2_DMA, tracebuffer => CFG_GRPCI2_TRACE,
vendorid => CFG_GRPCI2_VID, deviceid => CFG_GRPCI2_DID,
classcode => CFG_GRPCI2_CLASS, revisionid => CFG_GRPCI2_RID,
cap_pointer => CFG_GRPCI2_CAP, ext_cap_pointer => CFG_GRPCI2_NCAP,
iobase => CFG_AHBIO, extcfg => CFG_GRPCI2_EXTCFG,
bar0 => CFG_GRPCI2_BAR0, bar1 => CFG_GRPCI2_BAR1,
bar2 => CFG_GRPCI2_BAR2, bar3 => CFG_GRPCI2_BAR3,
bar4 => CFG_GRPCI2_BAR4, bar5 => CFG_GRPCI2_BAR5,
fifo_depth => CFG_GRPCI2_FDEPTH, fifo_count => CFG_GRPCI2_FCOUNT,
conv_endian => CFG_GRPCI2_ENDIAN, deviceirq => CFG_GRPCI2_DEVINT,
deviceirqmask => CFG_GRPCI2_DEVINTMSK, hostirq => CFG_GRPCI2_HOSTINT,
hostirqmask => CFG_GRPCI2_HOSTINTMSK,
nsync => 2, hostrst => 1, bypass => CFG_GRPCI2_BYPASS,
debug => 0, tbapben => 0, tbpindex => 5, tbpaddr => 16#400#,
tbpmask => 16#C00#)
port map (
rstn, clkm, pciclk, pci_dirq, pcii, pcio, apbi, apbo(4), ahbsi, open, ahbmi,
ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG), ahbmi,
open, open, open, open, open);
end generate;
grpci2xmt : if (CFG_GRPCI2_MASTER+CFG_GRPCI2_TARGET) > 1 and (CFG_GRPCI2_DMA) = 0 generate
pci0 : grpci2
generic map (
memtech => memtech, oepol => OEPOL,
hmindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
hdmindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+1,
hsindex => 4, haddr => 16#C00#, hmask => 16#E00#, ioaddr => 16#400#,
pindex => 4, paddr => 4, irq => 4, irqmode => 0,
master => CFG_GRPCI2_MASTER, target => CFG_GRPCI2_TARGET,
dma => CFG_GRPCI2_DMA, tracebuffer => CFG_GRPCI2_TRACE,
vendorid => CFG_GRPCI2_VID, deviceid => CFG_GRPCI2_DID,
classcode => CFG_GRPCI2_CLASS, revisionid => CFG_GRPCI2_RID,
cap_pointer => CFG_GRPCI2_CAP, ext_cap_pointer => CFG_GRPCI2_NCAP,
iobase => CFG_AHBIO, extcfg => CFG_GRPCI2_EXTCFG,
bar0 => CFG_GRPCI2_BAR0, bar1 => CFG_GRPCI2_BAR1,
bar2 => CFG_GRPCI2_BAR2, bar3 => CFG_GRPCI2_BAR3,
bar4 => CFG_GRPCI2_BAR4, bar5 => CFG_GRPCI2_BAR5,
fifo_depth => CFG_GRPCI2_FDEPTH, fifo_count => CFG_GRPCI2_FCOUNT,
conv_endian => CFG_GRPCI2_ENDIAN, deviceirq => CFG_GRPCI2_DEVINT,
deviceirqmask => CFG_GRPCI2_DEVINTMSK, hostirq => CFG_GRPCI2_HOSTINT,
hostirqmask => CFG_GRPCI2_HOSTINTMSK,
nsync => 2, hostrst => 1, bypass => CFG_GRPCI2_BYPASS,
debug => 0, tbapben => 0, tbpindex => 5, tbpaddr => 16#400#,
tbpmask => 16#C00#)
port map (
rstn, clkm, pciclk, pci_dirq, pcii, pcio, apbi, apbo(4), ahbsi, ahbso(4), ahbmi,
ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG), ahbmi,
open, open, open, open, open);
end generate;
grpci2xd : if (CFG_GRPCI2_MASTER+CFG_GRPCI2_TARGET) /= 0 and CFG_GRPCI2_DMA /= 0 generate
pci0 : grpci2
generic map (
memtech => memtech, oepol => OEPOL,
hmindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
hdmindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+1,
hsindex => 4, haddr => 16#C00#, hmask => 16#E00#, ioaddr => 16#400#,
pindex => 4, paddr => 4, irq => 4, irqmode => 0,
master => CFG_GRPCI2_MASTER, target => CFG_GRPCI2_TARGET,
dma => CFG_GRPCI2_DMA, tracebuffer => CFG_GRPCI2_TRACE,
vendorid => CFG_GRPCI2_VID, deviceid => CFG_GRPCI2_DID,
classcode => CFG_GRPCI2_CLASS, revisionid => CFG_GRPCI2_RID,
cap_pointer => CFG_GRPCI2_CAP, ext_cap_pointer => CFG_GRPCI2_NCAP,
iobase => CFG_AHBIO, extcfg => CFG_GRPCI2_EXTCFG,
bar0 => CFG_GRPCI2_BAR0, bar1 => CFG_GRPCI2_BAR1,
bar2 => CFG_GRPCI2_BAR2, bar3 => CFG_GRPCI2_BAR3,
bar4 => CFG_GRPCI2_BAR4, bar5 => CFG_GRPCI2_BAR5,
fifo_depth => CFG_GRPCI2_FDEPTH, fifo_count => CFG_GRPCI2_FCOUNT,
conv_endian => CFG_GRPCI2_ENDIAN, deviceirq => CFG_GRPCI2_DEVINT,
deviceirqmask => CFG_GRPCI2_DEVINTMSK, hostirq => CFG_GRPCI2_HOSTINT,
hostirqmask => CFG_GRPCI2_HOSTINTMSK,
nsync => 2, hostrst => 1, bypass => CFG_GRPCI2_BYPASS,
debug => 0, tbapben => 0, tbpindex => 5, tbpaddr => 16#400#,
tbpmask => 16#C00#)
port map (
rstn, clkm, pciclk, pci_dirq, pcii, pcio, apbi, apbo(4), ahbsi, ahbso(4), ahbmi,
ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG), ahbmi,
ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+1),
open, open, open, open);
end generate;
pcia0 : if CFG_PCI_ARB = 1 generate -- PCI arbiter
pciarb0 : pciarb generic map (pindex => 10, paddr => 10,
apb_en => CFG_PCI_ARBAPB)
port map ( clk => pciclk, rst_n => pcii.rst,
req_n => pci_arb_req_n, frame_n => pcii.frame,
gnt_n => pci_arb_gnt_n, pclk => clkm,
prst_n => rstn, apbi => apbi, apbo => apbo(10)
);
pgnt_pad : outpadv generic map (tech => padtech, width => 4)
port map (pci_arb_gnt, pci_arb_gnt_n);
preq_pad : inpadv generic map (tech => padtech, width => 4)
port map (pci_arb_req, pci_arb_req_n);
end generate;
pcipads0 : pcipads generic map (padtech => padtech, host => 0) -- PCI pads
port map ( pci_rst, pci_gnt, pci_idsel, pci_lock, pci_ad, pci_cbe,
pci_frame, pci_irdy, pci_trdy, pci_devsel, pci_stop, pci_perr,
pci_par, pci_req, pci_serr, pci_host, pci_66, pcii, pcio );
end generate;
-- noarb : if CFG_PCI_ARB = 0 generate apbo(10) <= apb_none; end generate;
-----------------------------------------------------------------------
--- ETHERNET ---------------------------------------------------------
-----------------------------------------------------------------------
eth1 : if CFG_GRETH = 1 generate -- Gaisler ethernet MAC
e1 : grethm generic map(
hindex => CFG_NCPU+CFG_AHB_UART+CFG_GRPCI2_TARGET+CFG_GRPCI2_DMA+CFG_AHB_JTAG,
pindex => 14, paddr => 14, pirq => 7, memtech => memtech,
mdcscaler => CPU_FREQ/1000, enable_mdio => 1, fifosize => CFG_ETH_FIFO,
nsync => 1, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF,
macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL, phyrstadr => 1,
ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL, giga => CFG_GRETH1G,
enable_mdint => 1)
port map(
rst => rstn, clk => clkm, ahbmi => ahbmi,
ahbmo => ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_GRPCI2_TARGET+CFG_GRPCI2_DMA+CFG_AHB_JTAG), apbi => apbi,
apbo => apbo(14), ethi => ethi, etho => etho);
greth1g: if CFG_GRETH1G = 1 generate
eth_macclk_pad : clkpad
generic map (tech => padtech, arch => 3, hf => 1)
port map (eth_macclk, egtx_clk, cgo.clklock, elock);
end generate greth1g;
emdio_pad : iopad generic map (tech => padtech)
port map (emdio, etho.mdio_o, etho.mdio_oe, ethi.mdio_i);
etxc_pad : clkpad generic map (tech => padtech, arch => 2)
port map (etx_clk, ethi.tx_clk);
erxc_pad : clkpad generic map (tech => padtech, arch => 2)
port map (erx_clk, ethi.rx_clk);
erxd_pad : inpadv generic map (tech => padtech, width => 8)
port map (erxd, ethi.rxd(7 downto 0));
erxdv_pad : inpad generic map (tech => padtech)
port map (erx_dv, ethi.rx_dv);
erxer_pad : inpad generic map (tech => padtech)
port map (erx_er, ethi.rx_er);
erxco_pad : inpad generic map (tech => padtech)
port map (erx_col, ethi.rx_col);
erxcr_pad : inpad generic map (tech => padtech)
port map (erx_crs, ethi.rx_crs);
emdintn_pad : inpad generic map (tech => padtech)
port map (emdintn, ethi.mdint);
etxd_pad : outpadv generic map (tech => padtech, width => 8)
port map (etxd, etho.txd(7 downto 0));
etxen_pad : outpad generic map (tech => padtech)
port map ( etx_en, etho.tx_en);
etxer_pad : outpad generic map (tech => padtech)
port map (etx_er, etho.tx_er);
emdc_pad : outpad generic map (tech => padtech)
port map (emdc, etho.mdc);
-- emdis_pad : outpad generic map (tech => padtech)
-- port map (emddis, vcc(0));
-- eepwrdwn_pad : outpad generic map (tech => padtech)
-- port map (epwrdwn, gnd(0));
-- esleep_pad : outpad generic map (tech => padtech)
-- port map (esleep, gnd(0));
-- epause_pad : outpad generic map (tech => padtech)
-- port map (epause, gnd(0));
-- ereset_pad : outpad generic map (tech => padtech)
-- port map (ereset, gnd(0));
ethi.gtx_clk <= egtx_clk;
end generate;
noeth: if CFG_GRETH = 0 or CFG_GRETH1G = 0 generate
elock <= '1';
end generate noeth;
-----------------------------------------------------------------------
--- CAN --------------------------------------------------------------
-----------------------------------------------------------------------
can0 : if CFG_CAN = 1 generate
can0 : can_mc generic map (slvndx => 6, ioaddr => CFG_CANIO,
iomask => 16#FF0#, irq => CFG_CANIRQ, memtech => memtech,
ncores => CFG_CAN_NUM, sepirq => CFG_CANSEPIRQ)
port map (rstn, clkm, ahbsi, ahbso(6), can_lrx, can_ltx );
can_pads : for i in 0 to CFG_CAN_NUM-1 generate
can_tx_pad : outpad generic map (tech => padtech)
port map (can_txd(i), can_ltx(i));
can_rx_pad : inpad generic map (tech => padtech)
port map (can_rxd(i), can_lrx(i));
end generate;
end generate;
-- can_stb <= '0'; -- no standby
ncan : if CFG_CAN = 0 generate ahbso(6) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
-- ocram : if CFG_AHBRAMEN = 1 generate
-- ahbram0 : ftahbram generic map (hindex => 7, haddr => CFG_AHBRADDR,
-- tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ, pindex => 6,
-- paddr => 6, edacen => CFG_AHBRAEDAC, autoscrub => CFG_AHBRASCRU,
-- errcnten => CFG_AHBRAECNT, cntbits => CFG_AHBRAEBIT)
-- port map ( rstn, clkm, ahbsi, ahbso(7), apbi, apbo(6), open);
-- end generate;
--
-- nram : if CFG_AHBRAMEN = 0 generate ahbso(7) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- SPACEWIRE -------------------------------------------------------
-----------------------------------------------------------------------
spw : if CFG_SPW_EN > 0 generate
spw_clk_pad : clkpad generic map (tech => padtech) port map (spw_clk, spw_clkl);
-- spw_clkl <= pciclk;
spw_rxtxclk <= spw_clkl;
spw_rxclkn <= not spw_rxtxclk;
swloop : for i in 0 to CFG_SPW_NUM-1 generate
-- GRSPW2 PHY
spw2_input : if CFG_SPW_GRSPW = 2 generate
spw_phy0 : grspw2_phy
generic map(
scantest => 0,
tech => fabtech,
input_type => CFG_SPW_INPUT,
rxclkbuftype => 1)
port map(
rstn => rstn,
rxclki => spw_rxtxclk,
rxclkin => spw_rxclkn,
nrxclki => spw_rxtxclk,
di => dtmp(i),
si => stmp(i),
do => spwi(i).d(1 downto 0),
dov => spwi(i).dv(1 downto 0),
dconnect => spwi(i).dconnect(1 downto 0),
rxclko => spw_rxclk(i));
spwi(i).nd <= (others => '0'); -- Only used in GRSPW
spwi(i).dv(3 downto 2) <= "00"; -- For second port
end generate spw2_input;
-- GRSPW PHY
spw1_input: if CFG_SPW_GRSPW = 1 generate
spw_phy0 : grspw_phy
generic map(
tech => fabtech,
rxclkbuftype => 1,
scantest => 0)
port map(
rxrst => spwo(i).rxrst,
di => dtmp(i),
si => stmp(i),
rxclko => spw_rxclk(i),
do => spwi(i).d(0),
ndo => spwi(i).nd(4 downto 0),
dconnect => spwi(i).dconnect(1 downto 0));
spwi(i).d(1) <= '0'; -- For second ports
spwi(i).dv <= (others => '0'); -- Only used in GRSPW2
spwi(i).nd(9 downto 5) <= "00000"; -- For second port
end generate spw1_input;
spwi(i).d(3 downto 2) <= "00"; -- For GRSPW2 second port
spwi(i).dconnect(3 downto 2) <= "00"; -- For second port
spwi(i).s(1 downto 0) <= "00"; -- Only used in PHY
sw0 : grspwm generic map(tech => memtech,
hindex => CFG_NCPU+CFG_AHB_UART+CFG_GRPCI2_TARGET+CFG_GRPCI2_DMA+CFG_AHB_JTAG+CFG_GRETH+i,
pindex => 10+i,
paddr => 10+i, pirq => 10+i,
sysfreq => CPU_FREQ, nsync => 1, rmap => CFG_SPW_RMAP,
rmapcrc => CFG_SPW_RMAPCRC, fifosize1 => CFG_SPW_AHBFIFO,
fifosize2 => CFG_SPW_RXFIFO, rxclkbuftype => 1,
rmapbufs => CFG_SPW_RMAPBUF,ft => CFG_SPW_FT, ports => 1,
dmachan => CFG_SPW_DMACHAN,
netlist => CFG_SPW_NETLIST, spwcore => CFG_SPW_GRSPW,
input_type => CFG_SPW_INPUT, output_type => CFG_SPW_OUTPUT,
rxtx_sameclk => CFG_SPW_RTSAME)
port map(rstn, clkm, spw_rxclk(i), spw_rxclk(i), spw_rxtxclk, spw_rxtxclk,
ahbmi,
ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_GRPCI2_TARGET+CFG_GRPCI2_DMA+CFG_AHB_JTAG+CFG_GRETH+i),
apbi, apbo(10+i), spwi(i), spwo(i));
spwi(i).tickin <= '0'; spwi(i).rmapen <= '0';
spwi(i).clkdiv10 <= conv_std_logic_vector(CPU_FREQ/10000-1, 8);
spwi(i).dcrstval <= (others => '0');
spwi(i).timerrstval <= (others => '0');
spw_rxd_pad : inpad_ds generic map (padtech, lvds, x25v)
port map (spw_rxdp(i), spw_rxdn(i), dtmp(i));
spw_rxs_pad : inpad_ds generic map (padtech, lvds, x25v)
port map (spw_rxsp(i), spw_rxsn(i), stmp(i));
spw_txd_pad : outpad_ds generic map (padtech, lvds, x25v)
port map (spw_txdp(i), spw_txdn(i), spwo(i).d(0), gnd(0));
spw_txs_pad : outpad_ds generic map (padtech, lvds, x25v)
port map (spw_txsp(i), spw_txsn(i), spwo(i).s(0), gnd(0));
end generate;
end generate;
nospw : if CFG_SPW_EN = 0 generate
spw_rxd_pad : inpad_ds generic map (padtech, lvds, x25v)
port map (spw_rxdp(0), spw_rxdn(0), spwi(0).d(0));
spw_rxs_pad : inpad_ds generic map (padtech, lvds, x25v)
port map (spw_rxsp(0), spw_rxsn(0), spwi(0).s(0));
spw_txd_pad : outpad_ds generic map (padtech, lvds, x25v)
port map (spw_txdp(0), spw_txdn(0), spwi(0).d(0), gnd(0));
spw_txs_pad : outpad_ds generic map (padtech, lvds, x25v)
port map (spw_txsp(0), spw_txsn(0), spwi(0).s(0), gnd(0));
end generate;
-------------------------------------------------------------------------------
-- USB ------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Note that more than one USB component can not be instantiated at the same
-- time (board has only one USB transceiver), therefore they share AHB
-- master/slave indexes
-----------------------------------------------------------------------------
-- Shared pads
-----------------------------------------------------------------------------
usbpads: if (CFG_GRUSBHC + CFG_GRUSBDC + CFG_GRUSB_DCL) /= 0 generate
-- Incoming 60 MHz clock from transceiver, arch 3 = through BUFGDLL or
-- similiar.
usb_clkout_pad : clkpad
generic map (tech => padtech, arch => 3)
port map (usb_clkout, uclk, cgo.clklock, ulock);
usb_d_pad: iopadv
generic map(tech => padtech, width => 8)
port map (usb_d, usbo(0).dataout(7 downto 0), usbo(0).oen,
usbi(0).datain(7 downto 0));
usb_nxt_pad : inpad generic map (tech => padtech)
port map (usb_nxt, usbi(0).nxt);
usb_dir_pad : inpad generic map (tech => padtech)
port map (usb_dir, usbi(0).dir);
usb_resetn_pad : outpad generic map (tech => padtech)
port map (usb_resetn, usbo(0).reset);
usb_stp_pad : outpad generic map (tech => padtech)
port map (usb_stp, usbo(0).stp);
end generate usbpads;
nousb: if (CFG_GRUSBHC + CFG_GRUSBDC + CFG_GRUSB_DCL) = 0 generate
ulock <= '1';
end generate nousb;
-----------------------------------------------------------------------------
-- USB 2.0 Host Controller
-----------------------------------------------------------------------------
usbhc0: if CFG_GRUSBHC = 1 generate
usbhc0 : grusbhc
generic map (
ehchindex => CFG_NCPU+CFG_AHB_UART+CFG_GRPCI2_TARGET+CFG_GRPCI2_DMA+CFG_AHB_JTAG+CFG_GRETH+CFG_SPW_EN*CFG_SPW_NUM,
ehcpindex => 13, ehcpaddr => 13, ehcpirq => 13, ehcpmask => 16#fff#,
uhchindex => CFG_NCPU+CFG_AHB_UART+CFG_GRPCI2_TARGET+CFG_GRPCI2_DMA+CFG_AHB_JTAG+CFG_GRETH+CFG_SPW_EN*CFG_SPW_NUM+1,
uhchsindex => 8, uhchaddr => 16#A00#, uhchmask => 16#fff#, uhchirq => 9, tech => fabtech,
memtech => memtech, ehcgen => CFG_GRUSBHC_EHC, uhcgen => CFG_GRUSBHC_UHC,
endian_conv => CFG_GRUSBHC_ENDIAN, be_regs => CFG_GRUSBHC_BEREGS,
be_desc => CFG_GRUSBHC_BEDESC, uhcblo => CFG_GRUSBHC_BLO,
bwrd => CFG_GRUSBHC_BWRD, vbusconf => CFG_GRUSBHC_VBUSCONF)
port map (
clkm,uclk,rstn,apbi,apbo(13),ahbmi,ahbsi,
ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_GRPCI2_TARGET+CFG_GRPCI2_DMA+CFG_AHB_JTAG+CFG_GRETH+CFG_SPW_EN*CFG_SPW_NUM),
ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_GRPCI2_TARGET+CFG_GRPCI2_DMA+CFG_AHB_JTAG+CFG_GRETH+CFG_SPW_EN*CFG_SPW_NUM+1
downto
CFG_NCPU+CFG_AHB_UART+CFG_GRPCI2_TARGET+CFG_GRPCI2_DMA+CFG_AHB_JTAG+CFG_GRETH+CFG_SPW_EN*CFG_SPW_NUM+1),
ahbso(8 downto 8),
usbo,usbi);
end generate usbhc0;
-----------------------------------------------------------------------------
-- USB 2.0 Device Controller
-----------------------------------------------------------------------------
usbdc0: if CFG_GRUSBDC = 1 generate
usbdc0: grusbdc
generic map(
hsindex => 8, hirq => 6, haddr => 16#004#, hmask => 16#FFC#,
hmindex => CFG_NCPU+CFG_AHB_UART+CFG_GRPCI2_TARGET+CFG_GRPCI2_DMA+CFG_AHB_JTAG+CFG_GRETH+CFG_SPW_EN*CFG_SPW_NUM,
aiface => CFG_GRUSBDC_AIFACE, uiface => 1,
nepi => CFG_GRUSBDC_NEPI, nepo => CFG_GRUSBDC_NEPO,
i0 => CFG_GRUSBDC_I0, i1 => CFG_GRUSBDC_I1,
i2 => CFG_GRUSBDC_I2, i3 => CFG_GRUSBDC_I3,
i4 => CFG_GRUSBDC_I4, i5 => CFG_GRUSBDC_I5,
i6 => CFG_GRUSBDC_I6, i7 => CFG_GRUSBDC_I7,
i8 => CFG_GRUSBDC_I8, i9 => CFG_GRUSBDC_I9,
i10 => CFG_GRUSBDC_I10, i11 => CFG_GRUSBDC_I11,
i12 => CFG_GRUSBDC_I12, i13 => CFG_GRUSBDC_I13,
i14 => CFG_GRUSBDC_I14, i15 => CFG_GRUSBDC_I15,
o0 => CFG_GRUSBDC_O0, o1 => CFG_GRUSBDC_O1,
o2 => CFG_GRUSBDC_O2, o3 => CFG_GRUSBDC_O3,
o4 => CFG_GRUSBDC_O4, o5 => CFG_GRUSBDC_O5,
o6 => CFG_GRUSBDC_O6, o7 => CFG_GRUSBDC_O7,
o8 => CFG_GRUSBDC_O8, o9 => CFG_GRUSBDC_O9,
o10 => CFG_GRUSBDC_O10, o11 => CFG_GRUSBDC_O11,
o12 => CFG_GRUSBDC_O12, o13 => CFG_GRUSBDC_O13,
o14 => CFG_GRUSBDC_O14, o15 => CFG_GRUSBDC_O15,
memtech => memtech, keepclk => 1)
port map(
uclk => uclk,
usbi => usbi(0),
usbo => usbo(0),
hclk => clkm,
hrst => rstn,
ahbmi => ahbmi,
ahbmo => ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_GRPCI2_TARGET+CFG_GRPCI2_DMA+CFG_AHB_JTAG+CFG_GRETH+CFG_SPW_EN*CFG_SPW_NUM),
ahbsi => ahbsi,
ahbso => ahbso(8)
);
end generate usbdc0;
-----------------------------------------------------------------------------
-- USB DCL
-----------------------------------------------------------------------------
usb_dcl0: if CFG_GRUSB_DCL = 1 generate
usb_dcl0: grusb_dcl
generic map (
hindex => CFG_NCPU+CFG_AHB_UART+CFG_GRPCI2_TARGET+CFG_GRPCI2_DMA+CFG_AHB_JTAG+CFG_GRETH+CFG_SPW_EN*CFG_SPW_NUM,
memtech => memtech, keepclk => 1, uiface => 1)
port map (
uclk, usbi(0), usbo(0), clkm, rstn, ahbmi,
ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_GRPCI2_TARGET+CFG_GRPCI2_DMA+CFG_AHB_JTAG+CFG_GRETH+CFG_SPW_EN*CFG_SPW_NUM));
end generate usb_dcl0;
-------------------------------------------------------------------------------
-- MIL-STD-1553B
-------------------------------------------------------------------------------
mil: if CFG_GR1553B_ENABLE /= 0 generate
milclk: entity work.lfclkgen
generic map (dv_div => 2.0, fx_mul => 4, fx_div => BOARD_FREQ/10000)
port map(resetin => rstraw, clkin => lclk, clk => clk1553, resetout => cgo1553.clklock);
milrst: rstgen
port map (resetn, clk1553, cgo1553.clklock, rst1553, open);
gr1553b0: gr1553b
generic map (
hindex => CFG_NCPU+CFG_AHB_UART+CFG_GRPCI2_TARGET+CFG_GRPCI2_DMA+CFG_AHB_JTAG+CFG_GRETH+CFG_SPW_EN*CFG_SPW_NUM+1, pindex => 12, paddr => 12, pirq => 6,
bc_enable => CFG_GR1553B_BCEN, rt_enable => CFG_GR1553B_RTEN,
bm_enable => CFG_GR1553B_BMEN,
bc_rtbusmask => 1)
port map (
clk => clkm, rst => rstn,
ahbmi => ahbmi, ahbmo => ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_GRPCI2_TARGET+CFG_GRPCI2_DMA+CFG_AHB_JTAG+CFG_GRETH+CFG_SPW_EN*CFG_SPW_NUM+1),
apbsi => apbi, apbso => apbo(12),
auxin => gr1553b_auxin_zero, auxout => open,
codec_clk => clk1553, codec_rst => rst1553,
txout => milout(0), txout_fb => milout(0), rxin => milin(0)
);
end generate;
nmil: if CFG_GR1553B_ENABLE = 0 generate
clk1553 <= '0'; rst1553 <= '0';
milout(0) <= (others => '0');
end generate;
-- milout(1) <= (others => '0');
milpads: for x in 0 to 0 generate
p: gr1553b_pads
generic map (padtech => padtech, outen_pol => 1)
port map (milout(x), milin(x),
busainen(x), busainp(x), busainn(x), busaoutin(x), busaoutp(x), busaoutn(x),
busbinen(x), busbinp(x), busbinn(x), busboutin(x), busboutp(x), busboutn(x));
end generate;
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
-- nam1 : for i in (CFG_NCPU+CFG_AHB_UART+CFG_GRPCI2_TARGET+CFG_GRPCI2_DMA+CFG_AHB_JTAG) to NAHBMST-1 generate
-- ahbmo(i) <= ahbm_none;
-- end generate;
-- nam2 : if CFG_PCI > 1 generate
-- ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+log2x(CFG_PCI)-1) <= ahbm_none;
-- end generate;
-- nap0 : for i in 11 to NAPBSLV-1 generate apbo(i) <= apb_none; end generate;
-- apbo(6) <= apb_none;
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON GR-PCI-XC5V Demonstration design",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end;
| gpl-3.0 |
EliasLuiz/TCC | Leon3/lib/gaisler/misc/gracectrl.vhd | 1 | 14070 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Entity: gracectrl
-- File: gracectrl.vhd
-- Author: Jan Andersson - Gaisler Research AB
-- Contact: [email protected]
-- Description: Provides a GRLIB AMBA AHB slave interface to Xilinx System ACE
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib, gaisler;
use grlib.amba.all;
use grlib.devices.all;
use grlib.stdlib.all;
use gaisler.misc.all;
entity gracectrl is
generic (
hindex : integer := 0; -- AHB slave index
hirq : integer := 0; -- Interrupt line
haddr : integer := 16#000#; -- Base address
hmask : integer := 16#fff#; -- Area mask
split : integer range 0 to 1 := 0; -- Enable AMBA SPLIT support
swap : integer range 0 to 1 := 0;
oepol : integer range 0 to 1 := 0; -- Output enable polarity
mode : integer range 0 to 2 := 0 -- 0: 16-bit mode only
-- 1: 8-bit mode only
-- 2: 8-bit, emulate 16-bit
);
port (
rstn : in std_ulogic;
clk : in std_ulogic; -- System (AMBA) clock
clkace : in std_ulogic; -- System ACE clock
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
acei : in gracectrl_in_type;
aceo : out gracectrl_out_type
);
end gracectrl;
architecture rtl of gracectrl is
-----------------------------------------------------------------------------
-- Constants
-----------------------------------------------------------------------------
constant REVISION : amba_version_type := 0;
constant HCONFIG : ahb_config_type := (
0 => ahb_device_reg(VENDOR_GAISLER, GAISLER_GRACECTRL, 0, REVISION, hirq),
-- 1 => conv_std_logic_vector(swap*4 + mode, 32),
4 => ahb_iobar(haddr, hmask), others => zero32);
constant OUTPUT : std_ulogic := conv_std_logic(oepol = 1);
constant INPUT : std_ulogic := not conv_std_logic(oepol = 1);
constant ACEDW : integer := 16-8*(mode mod 2);
-----------------------------------------------------------------------------
-- Functions
-----------------------------------------------------------------------------
-- purpose: swaps a hword if 'swap' is non-zero and mode is zero,
-- otherwise just propagate data
function condhswap (d : std_logic_vector)
return std_logic_vector is
variable dx : std_logic_vector(15 downto 0);
begin -- hswap
dx(ACEDW-1 downto 0) := d;
if swap /= 0 and mode = 0 then
return dx(7 downto 0) & dx(15 downto 8);
end if;
return dx;
end condhswap;
-----------------------------------------------------------------------------
-- Types
-----------------------------------------------------------------------------
type sys_sync_type is record
accdone : std_logic_vector(1 downto 0);
irq : std_logic_vector(2 downto 0);
end record;
type sys_reg_type is record
acc : std_ulogic; -- Perform access
active : std_ulogic; -- Access active
sync : sys_sync_type;
-- AHB
insplit : std_ulogic; -- SPLIT response issued
unsplit : std_ulogic; -- SPLIT complete not issued
irq : std_ulogic; -- Interrupt request
hwrite : std_ulogic;
hsel : std_ulogic;
hmbsel : std_logic_vector(0 to 1);
haddr : std_logic_vector(6 downto 0);
hready : std_ulogic;
wdata : std_logic_vector(ACEDW-1 downto 0);
hresp : std_logic_vector(1 downto 0);
splmst : std_logic_vector(log2(NAHBMST)-1 downto 0); -- SPLIT:ed master
hsplit : std_logic_vector(NAHBMST-1 downto 0); -- Other SPLIT:ed masters
ahbcancel : std_ulogic; -- Locked access cancels ongoing SPLIT
-- response
end record;
type ace_state_type is (idle, en, rd, done);
type ace_sync_type is record
acc : std_logic_vector(1 downto 0);
rstn : std_logic_vector(1 downto 0);
hwrite : std_logic_vector(1 downto 0);
dummy : std_logic_vector(1 downto 0);
end record;
type ace_reg_type is record
state : ace_state_type;
sync : ace_sync_type;
accdone : std_ulogic;
rdata : std_logic_vector(ACEDW-1 downto 0);
edone : std_ulogic;
aceo : gracectrl_out_type;
end record;
-----------------------------------------------------------------------------
-- Signals
-----------------------------------------------------------------------------
signal r, rin : sys_reg_type;
signal s, sin : ace_reg_type;
begin -- rtl
-----------------------------------------------------------------------------
-- System clock domain
-----------------------------------------------------------------------------
combsys: process (r, s, rstn, ahbsi, acei.irq)
variable v : sys_reg_type;
variable irq : std_logic_vector((NAHBIRQ-1) downto 0);
variable hsplit : std_logic_vector(NAHBMST-1 downto 0);
variable hwdata : std_logic_vector(31 downto 0);
begin -- process comb
v := r; v.irq := '0'; irq := (others => '0'); irq(hirq) := r.irq;
v.hresp := HRESP_OKAY; v.hready := '1'; hsplit := (others => '0');
hwdata := ahbreadword(ahbsi.hwdata, r.haddr(4 downto 2));
-- Sync
v.sync.accdone := r.sync.accdone(0) & s.accdone;
v.sync.irq := r.sync.irq(1 downto 0) & acei.irq;
-- AHB communication
if ahbsi.hready = '1' then
if (ahbsi.hsel(hindex) and ahbsi.htrans(1)) = '1' then
v.hmbsel := ahbsi.hmbsel(r.hmbsel'range);
if split = 0 or (not (r.active or r.acc) or ahbsi.hmastlock) = '1' then
v.hready := '0';
v.hwrite := ahbsi.hwrite;
v.haddr := ahbsi.haddr(6 downto 0);
v.hsel := '1';
if r.insplit = '0' then
v.acc := '1';
end if;
if split /= 0 then
if ahbsi.hmastlock = '0' then
v.hresp := HRESP_SPLIT;
v.splmst := ahbsi.hmaster;
v.unsplit := '1';
else
v.ahbcancel := r.insplit;
end if;
v.insplit := not ahbsi.hmastlock;
end if;
else
-- Core is busy, transfer is not locked respond with SPLIT
v.hready := '0';
if split /= 0 then
v.hresp := HRESP_SPLIT;
v.hsplit(conv_integer(ahbsi.hmaster)) := '1';
end if;
end if;
else
v.hsel := '0';
end if;
end if;
if (r.hready = '0') then
if (r.hresp = HRESP_OKAY) then v.hready := '0';
else v.hresp := r.hresp; end if;
end if;
if r.acc = '1' then
-- Propagate data
if r.active = '0' then
if mode /= 1 then
if r.haddr(1) = '0' then v.wdata := hwdata(ACEDW+15 downto 16);
else v.wdata := hwdata(ACEDW-1 downto 0); end if;
else
case r.haddr(1 downto 0) is
when "00" => v.wdata(7 downto 0) := hwdata(31 downto 24);
when "01" => v.wdata(7 downto 0) := hwdata(23 downto 16);
when "10" => v.wdata(7 downto 0) := hwdata(15 downto 8);
when others => v.wdata(7 downto 0) := hwdata(7 downto 0);
end case;
end if;
if mode = 2 then
-- Override writes to busmode register
if r.haddr(6 downto 1) = zero32(6 downto 1) then
v.wdata := (others => '0'); -- Byte
end if;
end if;
end if;
-- Remove access signal when access is done
if r.sync.accdone(1) = '1' then
v.acc := '0';
end if;
v.active := '1';
end if;
-- AMBA response when access is complete
if r.acc = '0' and r.sync.accdone(1) = '0' and r.active = '1' then
if split /= 0 and r.unsplit = '1' then
hsplit(conv_integer(r.splmst)) := '1';
v.unsplit := '0';
end if;
if ((split = 0 or v.ahbcancel = '0') and
(split = 0 or ahbsi.hmaster = r.splmst or r.insplit = '0') and
(((ahbsi.hsel(hindex) and ahbsi.hready and ahbsi.htrans(1)) = '1') or
((split = 0 or r.insplit = '0') and r.hready = '0' and r.hresp = HRESP_OKAY))) then
v.hresp := HRESP_OKAY;
if split /= 0 then
v.insplit := '0';
v.hsplit := r.hsplit;
end if;
v.hready := '1';
v.hsel := '0';
v.active := '0';
elsif split /= 0 and v.ahbcancel = '1' then
v.acc := '1';
v.ahbcancel := '0';
end if;
end if;
-- Interrupt request, not filtered, pulsed
if (not r.sync.irq(2) and r.sync.irq(1)) = '1' then
v.irq := '1';
end if;
-- Reset
if rstn = '0' then
v.acc := '0';
v.active := '0';
--
v.insplit := '0';
v.unsplit := '0';
v.hready := '1';
v.hwrite := '0';
v.hsel := '0';
v.hmbsel := (others => '0');
v.ahbcancel := '0';
end if;
if split = 0 then
v.insplit := '0';
v.unsplit := '0';
v.splmst := (others => '0');
v.hsplit := (others => '0');
v.ahbcancel := '0';
end if;
-- Update registers
rin <= v;
-- AHB slave output
ahbso.hready <= r.hready;
ahbso.hresp <= r.hresp;
ahbso.hrdata <= ahbdrivedata(s.rdata); -- Bad, but does not toggle much
ahbso.hconfig <= HCONFIG;
ahbso.hirq <= irq;
ahbso.hindex <= hindex;
ahbso.hsplit <= hsplit;
end process combsys;
regsys: process (clk)
begin -- process reg
if rising_edge(clk) then
r <= rin;
end if;
end process regsys;
-----------------------------------------------------------------------------
-- System ACE clock domain
-----------------------------------------------------------------------------
combace: process (r, s, rstn, acei)
variable v : ace_reg_type;
begin -- process comb
v := s;
-- Synchronize inputs
v.sync.acc := s.sync.acc(0) & r.acc;
v.sync.rstn := s.sync.rstn(0) & rstn;
v.sync.hwrite := s.sync.hwrite(0) & r.hwrite;
if mode = 2 then
-- Fake reads from BUSMODE register?
v.sync.dummy := s.sync.dummy(0) & not orv(r.haddr(6 downto 1));
else
v.sync.dummy := (others => '0');
end if;
case s.state is
when idle =>
v.aceo.addr := r.haddr(6 downto 0);
if mode = 2 then v.aceo.do(7 downto 0) := r.wdata(7 downto 0);
else v.aceo.do(r.wdata'range) := condhswap(r.wdata); end if;
if s.sync.acc(1) = '1' then
v.aceo.cen := '0';
v.aceo.doen := INPUT xor r.hwrite;
v.state := en;
end if;
if mode = 2 then v.edone := '0'; end if;
when en =>
v.aceo.wen := not r.hwrite;
if s.sync.hwrite(1) = '1' then
v.state := done;
else
v.state := rd;
end if;
when rd =>
v.aceo.oen := '0';
v.state := done;
when done =>
v.aceo.oen := '1';
v.aceo.wen := '1';
if mode = 2 and s.edone = '0' then
-- Keep 16-bit address map
v.aceo.addr(0) := '1';
v.aceo.do(7 downto 0) := r.wdata(ACEDW-1 downto ACEDW-8);
v.rdata(7 downto 0) := acei.di(7 downto 0);
v.edone := '1';
v.state := en;
else
v.aceo.cen := '1';
if s.accdone = '0' then
if mode = 2 then
v.rdata(ACEDW-1 downto ACEDW-8) := acei.di(7 downto 0);
if s.sync.dummy(1) = '1' then -- Fake read
v.rdata := (others => '0'); v.rdata(0) := '1';
end if;
else
v.rdata := condhswap(acei.di)(s.rdata'range);
end if;
v.accdone := '1';
else
v.aceo.doen := INPUT;
end if;
if s.sync.acc(1) = '0' then
v.state := idle;
v.accdone := '0';
end if;
end if;
end case;
-- Reset
if s.sync.rstn(1) = '0' then
v.state := idle;
v.accdone := '0';
v.aceo.cen := '1';
v.aceo.wen := '1';
v.aceo.oen := '1';
v.aceo.doen := INPUT;
end if;
if mode = 1 then v.aceo.do(15 downto 8) := (others => '0'); end if;
if mode /= 2 then v.edone := '0'; end if;
-- Update registers
sin <= v;
-- Assign outputs to System ACE
aceo <= s.aceo;
end process combace;
regace: process (clkace)
begin -- process reg
if rising_edge(clkace) then
s <= sin;
end if;
end process regace;
-- Boot message
-- pragma translate_off
bootmsg : report_version
generic map (
"gracectrl" & tost(hindex) & ": System ACE I/F Controller, rev " &
tost(REVISION) & ", irq " & tost(hirq));
-- pragma translate_on
end rtl;
| gpl-3.0 |
EliasLuiz/TCC | Leon3/designs/leon3-asic/leon3mp.vhd | 1 | 18188 | -----------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2013 Aeroflex Gaisler AB
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.config.all;
library techmap;
use techmap.gencomp.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
scantest : integer := CFG_SCAN
);
port (
resetn : in std_ulogic;
clksel : in std_logic_vector(1 downto 0);
clk : in std_ulogic;
lock : out std_ulogic;
errorn : inout std_ulogic;
wdogn : inout std_ulogic;
address : out std_logic_vector(27 downto 0);
data : inout std_logic_vector(31 downto 0);
cb : inout std_logic_vector(7 downto 0);
sdclk : out std_ulogic;
sdcsn : out std_logic_vector (1 downto 0); -- sdram chip select
sdwen : out std_ulogic; -- sdram write enable
sdrasn : out std_ulogic; -- sdram ras
sdcasn : out std_ulogic; -- sdram cas
sddqm : out std_logic_vector (3 downto 0); -- sdram dqm
dsutx : out std_ulogic; -- DSU tx data / scanout
dsurx : in std_ulogic; -- DSU rx data / scanin
dsuen : in std_ulogic;
dsubre : in std_ulogic; -- DSU break / scanen
dsuact : out std_ulogic; -- DSU active / NT
txd1 : out std_ulogic; -- UART1 tx data
rxd1 : in std_ulogic; -- UART1 rx data
txd2 : out std_ulogic; -- UART2 tx data
rxd2 : in std_ulogic; -- UART2 rx data
ramsn : out std_logic_vector (4 downto 0);
ramoen : out std_logic_vector (4 downto 0);
rwen : out std_logic_vector (3 downto 0);
oen : out std_ulogic;
writen : out std_ulogic;
read : out std_ulogic;
iosn : out std_ulogic;
romsn : out std_logic_vector (1 downto 0);
brdyn : in std_ulogic;
bexcn : in std_ulogic;
gpio : inout std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0); -- I/O port
i2c_scl : inout std_ulogic;
i2c_sda : inout std_ulogic;
spi_miso : in std_ulogic;
spi_mosi : out std_ulogic;
spi_sck : out std_ulogic;
spi_slvsel : out std_logic_vector(CFG_SPICTRL_SLVS-1 downto 0);
prom32 : in std_ulogic;
spw_clksel : in std_logic_vector(1 downto 0);
spw_clk : in std_ulogic;
spw_rxd : in std_logic_vector(0 to CFG_SPW_NUM-1);
spw_rxs : in std_logic_vector(0 to CFG_SPW_NUM-1);
spw_txd : out std_logic_vector(0 to CFG_SPW_NUM-1);
spw_txs : out std_logic_vector(0 to CFG_SPW_NUM-1);
gtx_clk : in std_ulogic;
erx_clk : in std_ulogic;
erxd : in std_logic_vector(7 downto 0);
erx_dv : in std_ulogic;
etx_clk : in std_ulogic;
etxd : out std_logic_vector(7 downto 0);
etx_en : out std_ulogic;
etx_er : out std_ulogic;
erx_er : in std_ulogic;
erx_col : in std_ulogic;
erx_crs : in std_ulogic;
emdint : in std_ulogic;
emdio : inout std_logic;
emdc : out std_ulogic;
testen : in std_ulogic;
trst : in std_ulogic;
tck : in std_ulogic;
tms : in std_ulogic;
tdi : in std_ulogic;
tdo : out std_ulogic
);
end;
architecture rtl of leon3mp is
signal lresetn : std_ulogic;
signal lclksel : std_logic_vector (1 downto 0);
signal lclk : std_ulogic;
signal llock : std_ulogic;
signal lerrorn : std_ulogic;
signal laddress : std_logic_vector(27 downto 0);
signal ldatain : std_logic_vector(31 downto 0);
signal ldataout : std_logic_vector(31 downto 0);
signal ldataen : std_logic_vector(31 downto 0);
signal lcbin : std_logic_vector(7 downto 0);
signal lcbout : std_logic_vector(7 downto 0);
signal lcben : std_logic_vector(7 downto 0);
signal lsdclk : std_ulogic;
signal lsdcsn : std_logic_vector (1 downto 0);
signal lsdwen : std_ulogic;
signal lsdrasn : std_ulogic;
signal lsdcasn : std_ulogic;
signal lsddqm : std_logic_vector (3 downto 0);
signal ldsutx : std_ulogic;
signal ldsurx : std_ulogic;
signal ldsuen : std_ulogic;
signal ldsubre : std_ulogic;
signal ldsuact : std_ulogic;
signal ltxd1 : std_ulogic;
signal lrxd1 : std_ulogic;
signal ltxd2 : std_ulogic;
signal lrxd2 : std_ulogic;
signal lramsn : std_logic_vector (4 downto 0);
signal lramoen : std_logic_vector (4 downto 0);
signal lrwen : std_logic_vector (3 downto 0);
signal loen : std_ulogic;
signal lwriten : std_ulogic;
signal lread : std_ulogic;
signal liosn : std_ulogic;
signal lromsn : std_logic_vector (1 downto 0);
signal lbrdyn : std_ulogic;
signal lbexcn : std_ulogic;
signal lwdogn : std_ulogic;
signal lgpioin : std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0);
signal lgpioout : std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0);
signal lgpioen : std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0);
signal li2c_sclout : std_ulogic;
signal li2c_sclen : std_ulogic;
signal li2c_sclin : std_ulogic;
signal li2c_sdaout : std_ulogic;
signal li2c_sdaen : std_ulogic;
signal li2c_sdain : std_ulogic;
signal lspi_miso : std_ulogic;
signal lspi_mosi : std_ulogic;
signal lspi_sck : std_ulogic;
signal lspi_slvsel : std_logic_vector(CFG_SPICTRL_SLVS-1 downto 0);
signal lprom32 : std_ulogic;
signal lspw_clksel : std_logic_vector (1 downto 0);
signal lspw_clk : std_ulogic;
signal lspw_rxd : std_logic_vector(0 to CFG_SPW_NUM-1);
signal lspw_rxs : std_logic_vector(0 to CFG_SPW_NUM-1);
signal lspw_txd : std_logic_vector(0 to CFG_SPW_NUM-1);
signal lspw_txs : std_logic_vector(0 to CFG_SPW_NUM-1);
signal lgtx_clk : std_ulogic;
signal lerx_clk : std_ulogic;
signal lerxd : std_logic_vector(7 downto 0);
signal lerx_dv : std_ulogic;
signal letx_clk : std_ulogic;
signal letxd : std_logic_vector(7 downto 0);
signal letx_en : std_ulogic;
signal letx_er : std_ulogic;
signal lerx_er : std_ulogic;
signal lerx_col : std_ulogic;
signal lerx_crs : std_ulogic;
signal lemdint : std_ulogic;
signal lemdioin : std_logic;
signal lemdioout : std_logic;
signal lemdioen : std_logic;
signal lemdc : std_ulogic;
signal ltesten : std_ulogic;
signal ltrst : std_ulogic;
signal ltck : std_ulogic;
signal ltms : std_ulogic;
signal ltdi : std_ulogic;
signal ltdo : std_ulogic;
signal ltdoen : std_ulogic;
-- Use for ASIC
--constant padvoltage : integer := x33v;
--constant padlevel : integer := ttl;
-- Use for FPGA
constant padvoltage : integer := x18v;
constant padlevel : integer := cmos;
begin
-- TODO: Move PAD options to 'xconfig'
pads0 : entity work.pads
generic map (
padtech => CFG_PADTECH,
padlevel => padlevel,
padstrength => 10,
jtag_padfilter => pullup,
testen_padfilter => pulldown,
resetn_padfilter => schmitt,
clk_padfilter => 0,
spw_padstrength => 12,
jtag_padstrength => 6,
uart_padstrength => 6,
dsu_padstrength => 6,
padvoltage => padvoltage,
spw_input_type => CFG_SPW_INPUT,
oepol => padoen_polarity(CFG_PADTECH)
)
port map (
---------------------------
--to chip boundary
---------------------------
resetn => resetn ,
clksel => clksel ,
clk => clk ,
lock => lock ,
errorn => errorn ,
address => address ,
data => data ,
cb => cb ,
sdclk => sdclk ,
sdcsn => sdcsn ,
sdwen => sdwen ,
sdrasn => sdrasn ,
sdcasn => sdcasn ,
sddqm => sddqm ,
dsutx => dsutx ,
dsurx => dsurx ,
dsuen => dsuen ,
dsubre => dsubre ,
dsuact => dsuact ,
txd1 => txd1 ,
rxd1 => rxd1 ,
txd2 => txd2 ,
rxd2 => rxd2 ,
ramsn => ramsn ,
ramoen => ramoen ,
rwen => rwen ,
oen => oen ,
writen => writen ,
read => read ,
iosn => iosn ,
romsn => romsn ,
brdyn => brdyn ,
bexcn => bexcn ,
wdogn => wdogn ,
gpio => gpio ,
i2c_scl => i2c_scl ,
i2c_sda => i2c_sda ,
spi_miso => spi_miso ,
spi_mosi => spi_mosi ,
spi_sck => spi_sck ,
spi_slvsel => spi_slvsel,
prom32 => prom32 ,
spw_clksel => spw_clksel,
spw_clk => spw_clk ,
spw_rxd => spw_rxd ,
spw_rxs => spw_rxs ,
spw_txd => spw_txd ,
spw_txs => spw_txs ,
gtx_clk => gtx_clk ,
erx_clk => erx_clk ,
erxd => erxd ,
erx_dv => erx_dv ,
etx_clk => etx_clk ,
etxd => etxd ,
etx_en => etx_en ,
etx_er => etx_er ,
erx_er => erx_er ,
erx_col => erx_col ,
erx_crs => erx_crs ,
emdint => emdint ,
emdio => emdio ,
emdc => emdc ,
testen => testen ,
trst => trst ,
tck => tck ,
tms => tms ,
tdi => tdi ,
tdo => tdo ,
------------------------- ---
--to core
----------------------------
lresetn => lresetn ,
lclksel => lclksel ,
lclk => lclk ,
llock => llock ,
lerrorn => lerrorn ,
laddress => laddress ,
ldatain => ldatain ,
ldataout => ldataout ,
ldataen => ldataen ,
lcbin => lcbin ,
lcbout => lcbout ,
lcben => lcben ,
lsdclk => lsdclk ,
lsdcsn => lsdcsn ,
lsdwen => lsdwen ,
lsdrasn => lsdrasn ,
lsdcasn => lsdcasn ,
lsddqm => lsddqm ,
ldsutx => ldsutx ,
ldsurx => ldsurx ,
ldsuen => ldsuen ,
ldsubre => ldsubre ,
ldsuact => ldsuact ,
ltxd1 => ltxd1 ,
lrxd1 => lrxd1 ,
ltxd2 => ltxd2 ,
lrxd2 => lrxd2 ,
lramsn => lramsn ,
lramoen => lramoen ,
lrwen => lrwen ,
loen => loen ,
lwriten => lwriten ,
lread => lread ,
liosn => liosn ,
lromsn => lromsn ,
lbrdyn => lbrdyn ,
lbexcn => lbexcn ,
lwdogn => lwdogn ,
lgpioin => lgpioin ,
lgpioout => lgpioout ,
lgpioen => lgpioen ,
li2c_sclout => li2c_sclout,
li2c_sclen => li2c_sclen ,
li2c_sclin => li2c_sclin ,
li2c_sdaout => li2c_sdaout,
li2c_sdaen => li2c_sdaen ,
li2c_sdain => li2c_sdain ,
lspi_miso => lspi_miso ,
lspi_mosi => lspi_mosi ,
lspi_sck => lspi_sck ,
lspi_slvsel => lspi_slvsel,
lprom32 => lprom32 ,
lspw_clksel => lspw_clksel,
lspw_clk => lspw_clk ,
lspw_rxd => lspw_rxd ,
lspw_rxs => lspw_rxs ,
lspw_txd => lspw_txd ,
lspw_txs => lspw_txs ,
lgtx_clk => lgtx_clk ,
lerx_clk => lerx_clk ,
lerxd => lerxd ,
lerx_dv => lerx_dv ,
letx_clk => letx_clk ,
letxd => letxd ,
letx_en => letx_en ,
letx_er => letx_er ,
lerx_er => lerx_er ,
lerx_col => lerx_col ,
lerx_crs => lerx_crs ,
lemdint => lemdint ,
lemdioin => lemdioin ,
lemdioout => lemdioout ,
lemdioen => lemdioen ,
lemdc => lemdc ,
ltesten => ltesten ,
ltrst => ltrst ,
ltck => ltck ,
ltms => ltms ,
ltdi => ltdi ,
ltdo => ltdo ,
ltdoen => ltdoen
);
-- ASIC Core
core0 : entity work.core
generic map (
fabtech => CFG_FABTECH,
memtech => CFG_MEMTECH,
padtech => CFG_PADTECH,
clktech => CFG_CLKTECH,
disas => CFG_DISAS,
dbguart => CFG_DUART,
pclow => CFG_PCLOW,
scantest => CFG_SCAN,
bscanen => CFG_BOUNDSCAN_EN,
oepol => padoen_polarity(CFG_PADTECH)
)
port map (
----------------------------
-- ASIC Ports/Pads
----------------------------
resetn => lresetn ,
clksel => lclksel ,
clk => lclk ,
lock => llock ,
errorn => lerrorn ,
address => laddress ,
datain => ldatain ,
dataout => ldataout ,
dataen => ldataen ,
cbin => lcbin ,
cbout => lcbout ,
cben => lcben ,
sdclk => lsdclk ,
sdcsn => lsdcsn ,
sdwen => lsdwen ,
sdrasn => lsdrasn ,
sdcasn => lsdcasn ,
sddqm => lsddqm ,
dsutx => ldsutx ,
dsurx => ldsurx ,
dsuen => ldsuen ,
dsubre => ldsubre ,
dsuact => ldsuact ,
txd1 => ltxd1 ,
rxd1 => lrxd1 ,
txd2 => ltxd2 ,
rxd2 => lrxd2 ,
ramsn => lramsn ,
ramoen => lramoen ,
rwen => lrwen ,
oen => loen ,
writen => lwriten ,
read => lread ,
iosn => liosn ,
romsn => lromsn ,
brdyn => lbrdyn ,
bexcn => lbexcn ,
wdogn => lwdogn ,
gpioin => lgpioin ,
gpioout => lgpioout ,
gpioen => lgpioen ,
i2c_sclout => li2c_sclout,
i2c_sclen => li2c_sclen ,
i2c_sclin => li2c_sclin ,
i2c_sdaout => li2c_sdaout,
i2c_sdaen => li2c_sdaen ,
i2c_sdain => li2c_sdain ,
spi_miso => lspi_miso ,
spi_mosi => lspi_mosi ,
spi_sck => lspi_sck ,
spi_slvsel => lspi_slvsel,
prom32 => lprom32 ,
spw_clksel => lspw_clksel,
spw_clk => lspw_clk ,
spw_rxd => lspw_rxd ,
spw_rxs => lspw_rxs ,
spw_txd => lspw_txd ,
spw_txs => lspw_txs ,
gtx_clk => lgtx_clk ,
erx_clk => lerx_clk ,
erxd => lerxd ,
erx_dv => lerx_dv ,
etx_clk => letx_clk ,
etxd => letxd ,
etx_en => letx_en ,
etx_er => letx_er ,
erx_er => lerx_er ,
erx_col => lerx_col ,
erx_crs => lerx_crs ,
emdint => lemdint ,
emdioin => lemdioin ,
emdioout => lemdioout ,
emdioen => lemdioen ,
emdc => lemdc ,
testen => ltesten ,
trst => ltrst ,
tck => ltck ,
tms => ltms ,
tdi => ltdi ,
tdo => ltdo ,
tdoen => ltdoen ,
----------------------------
-- BSCAN
----------------------------
chain_tck => OPEN ,
chain_tckn => OPEN ,
chain_tdi => OPEN ,
chain_tdo => '0',
bsshft => OPEN ,
bscapt => OPEN ,
bsupdi => OPEN ,
bsupdo => OPEN ,
bsdrive => OPEN ,
bshighz => OPEN
);
-- BSCAN
-- TODO: ADD BSCAN
end;
| gpl-3.0 |
EliasLuiz/TCC | Leon3/lib/eth/comp/ethcomp.vhd | 1 | 20936 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package ethcomp is
component grethc is
generic(
ifg_gap : integer := 24;
attempt_limit : integer := 16;
backoff_limit : integer := 10;
mdcscaler : integer range 0 to 255 := 25;
enable_mdio : integer range 0 to 1 := 0;
fifosize : integer range 4 to 512 := 8;
nsync : integer range 1 to 2 := 2;
edcl : integer range 0 to 3 := 0;
edclbufsz : integer range 1 to 64 := 1;
macaddrh : integer := 16#00005E#;
macaddrl : integer := 16#000000#;
ipaddrh : integer := 16#c0a8#;
ipaddrl : integer := 16#0035#;
phyrstadr : integer range 0 to 32 := 0;
rmii : integer range 0 to 1 := 0;
oepol : integer range 0 to 1 := 0;
scanen : integer range 0 to 1 := 0;
mdint_pol : integer range 0 to 1 := 0;
enable_mdint : integer range 0 to 1 := 0;
multicast : integer range 0 to 1 := 0;
edclsepahbg : integer range 0 to 1 := 0;
ramdebug : integer range 0 to 2 := 0;
mdiohold : integer := 1;
maxsize : integer;
gmiimode : integer range 0 to 1 := 0
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
--ahb mst in
hgrant : in std_ulogic;
hready : in std_ulogic;
hresp : in std_logic_vector(1 downto 0);
hrdata : in std_logic_vector(31 downto 0);
--ahb mst out
hbusreq : out std_ulogic;
hlock : out std_ulogic;
htrans : out std_logic_vector(1 downto 0);
haddr : out std_logic_vector(31 downto 0);
hwrite : out std_ulogic;
hsize : out std_logic_vector(2 downto 0);
hburst : out std_logic_vector(2 downto 0);
hprot : out std_logic_vector(3 downto 0);
hwdata : out std_logic_vector(31 downto 0);
--edcl ahb mst in
ehgrant : in std_ulogic;
ehready : in std_ulogic;
ehresp : in std_logic_vector(1 downto 0);
ehrdata : in std_logic_vector(31 downto 0);
--edcl ahb mst out
ehbusreq : out std_ulogic;
ehlock : out std_ulogic;
ehtrans : out std_logic_vector(1 downto 0);
ehaddr : out std_logic_vector(31 downto 0);
ehwrite : out std_ulogic;
ehsize : out std_logic_vector(2 downto 0);
ehburst : out std_logic_vector(2 downto 0);
ehprot : out std_logic_vector(3 downto 0);
ehwdata : out std_logic_vector(31 downto 0);
--apb slv in
psel : in std_ulogic;
penable : in std_ulogic;
paddr : in std_logic_vector(31 downto 0);
pwrite : in std_ulogic;
pwdata : in std_logic_vector(31 downto 0);
--apb slv out
prdata : out std_logic_vector(31 downto 0);
--irq
irq : out std_logic;
--rx ahb fifo
rxrenable : out std_ulogic;
rxraddress : out std_logic_vector(10 downto 0);
rxwrite : out std_ulogic;
rxwdata : out std_logic_vector(31 downto 0);
rxwaddress : out std_logic_vector(10 downto 0);
rxrdata : in std_logic_vector(31 downto 0);
--tx ahb fifo
txrenable : out std_ulogic;
txraddress : out std_logic_vector(10 downto 0);
txwrite : out std_ulogic;
txwdata : out std_logic_vector(31 downto 0);
txwaddress : out std_logic_vector(10 downto 0);
txrdata : in std_logic_vector(31 downto 0);
--edcl buf
erenable : out std_ulogic;
eraddress : out std_logic_vector(15 downto 0);
ewritem : out std_ulogic;
ewritel : out std_ulogic;
ewaddressm : out std_logic_vector(15 downto 0);
ewaddressl : out std_logic_vector(15 downto 0);
ewdata : out std_logic_vector(31 downto 0);
erdata : in std_logic_vector(31 downto 0);
--ethernet input signals
rmii_clk : in std_ulogic;
tx_clk : in std_ulogic;
rx_clk : in std_ulogic;
tx_dv : in std_ulogic;
rxd : in std_logic_vector(3 downto 0);
rx_dv : in std_ulogic;
rx_er : in std_ulogic;
rx_col : in std_ulogic;
rx_en : in std_ulogic;
rx_crs : in std_ulogic;
mdio_i : in std_ulogic;
phyrstaddr : in std_logic_vector(4 downto 0);
mdint : in std_ulogic;
--ethernet output signals
reset : out std_ulogic;
txd : out std_logic_vector(3 downto 0);
tx_en : out std_ulogic;
tx_er : out std_ulogic;
mdc : out std_ulogic;
mdio_o : out std_ulogic;
mdio_oe : out std_ulogic;
--scantest
testrst : in std_ulogic;
testen : in std_ulogic;
testoen : in std_ulogic;
edcladdr : in std_logic_vector(3 downto 0) := "0000";
edclsepahb : in std_ulogic;
edcldisable : in std_ulogic;
speed : out std_ulogic
);
end component;
component greth_gbitc is
generic(
ifg_gap : integer := 24;
attempt_limit : integer := 16;
backoff_limit : integer := 10;
slot_time : integer := 128;
mdcscaler : integer range 0 to 255 := 25;
nsync : integer range 1 to 2 := 2;
edcl : integer range 0 to 3 := 0;
edclbufsz : integer range 1 to 64 := 1;
burstlength : integer range 4 to 128 := 32;
macaddrh : integer := 16#00005E#;
macaddrl : integer := 16#000000#;
ipaddrh : integer := 16#c0a8#;
ipaddrl : integer := 16#0035#;
phyrstadr : integer range 0 to 32 := 0;
sim : integer range 0 to 1 := 0;
oepol : integer range 0 to 1 := 0;
scanen : integer range 0 to 1 := 0;
mdint_pol : integer range 0 to 1 := 0;
enable_mdint : integer range 0 to 1 := 0;
multicast : integer range 0 to 1 := 0;
edclsepahbg : integer range 0 to 1 := 0;
ramdebug : integer range 0 to 2 := 0;
mdiohold : integer := 1;
gmiimode : integer range 0 to 1 := 0;
mdiochain : integer range 0 to 1 := 0;
iotest : integer range 0 to 1 := 0
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
--ahb mst in
hgrant : in std_ulogic;
hready : in std_ulogic;
hresp : in std_logic_vector(1 downto 0);
hrdata : in std_logic_vector(31 downto 0);
--ahb mst out
hbusreq : out std_ulogic;
hlock : out std_ulogic;
htrans : out std_logic_vector(1 downto 0);
haddr : out std_logic_vector(31 downto 0);
hwrite : out std_ulogic;
hsize : out std_logic_vector(2 downto 0);
hburst : out std_logic_vector(2 downto 0);
hprot : out std_logic_vector(3 downto 0);
hwdata : out std_logic_vector(31 downto 0);
--edcl ahb mst in
ehgrant : in std_ulogic;
ehready : in std_ulogic;
ehresp : in std_logic_vector(1 downto 0);
ehrdata : in std_logic_vector(31 downto 0);
--edcl ahb mst out
ehbusreq : out std_ulogic;
ehlock : out std_ulogic;
ehtrans : out std_logic_vector(1 downto 0);
ehaddr : out std_logic_vector(31 downto 0);
ehwrite : out std_ulogic;
ehsize : out std_logic_vector(2 downto 0);
ehburst : out std_logic_vector(2 downto 0);
ehprot : out std_logic_vector(3 downto 0);
ehwdata : out std_logic_vector(31 downto 0);
--apb slv in
psel : in std_ulogic;
penable : in std_ulogic;
paddr : in std_logic_vector(31 downto 0);
pwrite : in std_ulogic;
pwdata : in std_logic_vector(31 downto 0);
--apb slv out
prdata : out std_logic_vector(31 downto 0);
--irq
irq : out std_logic;
--rx ahb fifo
rxrenable : out std_ulogic;
rxraddress : out std_logic_vector(8 downto 0);
rxwrite : out std_ulogic;
rxwdata : out std_logic_vector(31 downto 0);
rxwaddress : out std_logic_vector(8 downto 0);
rxrdata : in std_logic_vector(31 downto 0);
--tx ahb fifo
txrenable : out std_ulogic;
txraddress : out std_logic_vector(8 downto 0);
txwrite : out std_ulogic;
txwdata : out std_logic_vector(31 downto 0);
txwaddress : out std_logic_vector(8 downto 0);
txrdata : in std_logic_vector(31 downto 0);
--edcl buf
erenable : out std_ulogic;
eraddress : out std_logic_vector(15 downto 0);
ewritem : out std_ulogic;
ewritel : out std_ulogic;
ewaddressm : out std_logic_vector(15 downto 0);
ewaddressl : out std_logic_vector(15 downto 0);
ewdata : out std_logic_vector(31 downto 0);
erdata : in std_logic_vector(31 downto 0);
--ethernet input signals
gtx_clk : in std_ulogic;
tx_clk : in std_ulogic;
tx_dv : in std_ulogic;
rx_clk : in std_ulogic;
rxd : in std_logic_vector(7 downto 0);
rx_dv : in std_ulogic;
rx_er : in std_ulogic;
rx_col : in std_ulogic;
rx_crs : in std_ulogic;
rx_en : in std_ulogic;
mdio_i : in std_ulogic;
phyrstaddr : in std_logic_vector(4 downto 0);
mdint : in std_ulogic;
--ethernet output signals
reset : out std_ulogic;
txd : out std_logic_vector(7 downto 0);
tx_en : out std_ulogic;
tx_er : out std_ulogic;
mdc : out std_ulogic;
mdio_o : out std_ulogic;
mdio_oe : out std_ulogic;
--scantest
testrst : in std_ulogic;
testen : in std_ulogic;
testoen : in std_ulogic;
edcladdr : in std_logic_vector(3 downto 0) := "0000";
edclsepahb : in std_ulogic;
edcldisable : in std_ulogic;
gbit : out std_ulogic;
speed : out std_ulogic;
-- mdio sharing
mdiochain_first : in std_ulogic := '0'; -- First in chain (ignore ticki/sampi)
mdiochain_ticki : in std_ulogic := '0'; -- From above in chain
mdiochain_datai : in std_ulogic := '0';
mdiochain_locko : out std_ulogic; -- To above in chain
mdiochain_ticko : out std_ulogic; -- To below in chain
mdiochain_i : out std_ulogic; -- To below in chain
mdiochain_locki : in std_ulogic := '0'; -- From below in chain
mdiochain_o : in std_ulogic := '0';
mdiochain_oe : in std_ulogic := '0'
);
end component;
component greth_gen is
generic(
memtech : integer := 0;
ifg_gap : integer := 24;
attempt_limit : integer := 16;
backoff_limit : integer := 10;
mdcscaler : integer range 0 to 255 := 25;
enable_mdio : integer range 0 to 1 := 0;
fifosize : integer range 4 to 64 := 8;
nsync : integer range 1 to 2 := 2;
edcl : integer range 0 to 3 := 0;
edclbufsz : integer range 1 to 64 := 1;
macaddrh : integer := 16#00005E#;
macaddrl : integer := 16#000000#;
ipaddrh : integer := 16#c0a8#;
ipaddrl : integer := 16#0035#;
phyrstadr : integer range 0 to 31 := 0;
rmii : integer range 0 to 1 := 0;
oepol : integer range 0 to 1 := 0;
scanen : integer range 0 to 1 := 0;
mdint_pol : integer range 0 to 1 := 0;
enable_mdint : integer range 0 to 1 := 0;
multicast : integer range 0 to 1 := 0;
gmiimode : integer range 0 to 1 := 0
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
--ahb mst in
hgrant : in std_ulogic;
hready : in std_ulogic;
hresp : in std_logic_vector(1 downto 0);
hrdata : in std_logic_vector(31 downto 0);
--ahb mst out
hbusreq : out std_ulogic;
hlock : out std_ulogic;
htrans : out std_logic_vector(1 downto 0);
haddr : out std_logic_vector(31 downto 0);
hwrite : out std_ulogic;
hsize : out std_logic_vector(2 downto 0);
hburst : out std_logic_vector(2 downto 0);
hprot : out std_logic_vector(3 downto 0);
hwdata : out std_logic_vector(31 downto 0);
--apb slv in
psel : in std_ulogic;
penable : in std_ulogic;
paddr : in std_logic_vector(31 downto 0);
pwrite : in std_ulogic;
pwdata : in std_logic_vector(31 downto 0);
--apb slv out
prdata : out std_logic_vector(31 downto 0);
--irq
irq : out std_logic;
--ethernet input signals
rmii_clk : in std_ulogic;
tx_clk : in std_ulogic;
tx_dv : in std_ulogic;
rx_clk : in std_ulogic;
rxd : in std_logic_vector(3 downto 0);
rx_dv : in std_ulogic;
rx_er : in std_ulogic;
rx_col : in std_ulogic;
rx_crs : in std_ulogic;
rx_en : in std_ulogic;
mdio_i : in std_ulogic;
phyrstaddr : in std_logic_vector(4 downto 0);
mdint : in std_ulogic;
--ethernet output signals
reset : out std_ulogic;
txd : out std_logic_vector(3 downto 0);
tx_en : out std_ulogic;
tx_er : out std_ulogic;
mdc : out std_ulogic;
mdio_o : out std_ulogic;
mdio_oe : out std_ulogic;
--scantest
testrst : in std_ulogic;
testen : in std_ulogic;
testoen : in std_ulogic;
edcladdr : in std_logic_vector(3 downto 0);
edclsepahb : in std_ulogic;
edcldisable : in std_ulogic;
speed : out std_ulogic
);
end component;
component greth_gbit_gen is
generic(
memtech : integer := 0;
ifg_gap : integer := 24;
attempt_limit : integer := 16;
backoff_limit : integer := 10;
slot_time : integer := 128;
mdcscaler : integer range 0 to 255 := 25;
nsync : integer range 1 to 2 := 2;
edcl : integer range 0 to 3 := 1;
edclbufsz : integer range 1 to 64 := 1;
burstlength : integer range 4 to 128 := 32;
macaddrh : integer := 16#00005E#;
macaddrl : integer := 16#000000#;
ipaddrh : integer := 16#c0a8#;
ipaddrl : integer := 16#0035#;
phyrstadr : integer range 0 to 32 := 0;
sim : integer range 0 to 1 := 0;
oepol : integer range 0 to 1 := 0;
scanen : integer range 0 to 1 := 0;
ft : integer range 0 to 2 := 0;
edclft : integer range 0 to 2 := 0;
mdint_pol : integer range 0 to 1 := 0;
enable_mdint : integer range 0 to 1 := 0;
multicast : integer range 0 to 1 := 0;
edclsepahbg : integer range 0 to 1 := 0;
ramdebug : integer range 0 to 2 := 0;
gmiimode : integer range 0 to 1 := 0
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
--ahb mst in
hgrant : in std_ulogic;
hready : in std_ulogic;
hresp : in std_logic_vector(1 downto 0);
hrdata : in std_logic_vector(31 downto 0);
--ahb mst out
hbusreq : out std_ulogic;
hlock : out std_ulogic;
htrans : out std_logic_vector(1 downto 0);
haddr : out std_logic_vector(31 downto 0);
hwrite : out std_ulogic;
hsize : out std_logic_vector(2 downto 0);
hburst : out std_logic_vector(2 downto 0);
hprot : out std_logic_vector(3 downto 0);
hwdata : out std_logic_vector(31 downto 0);
--edcl ahb mst in
ehgrant : in std_ulogic;
ehready : in std_ulogic;
ehresp : in std_logic_vector(1 downto 0);
ehrdata : in std_logic_vector(31 downto 0);
--edcl ahb mst out
ehbusreq : out std_ulogic;
ehlock : out std_ulogic;
ehtrans : out std_logic_vector(1 downto 0);
ehaddr : out std_logic_vector(31 downto 0);
ehwrite : out std_ulogic;
ehsize : out std_logic_vector(2 downto 0);
ehburst : out std_logic_vector(2 downto 0);
ehprot : out std_logic_vector(3 downto 0);
ehwdata : out std_logic_vector(31 downto 0);
--apb slv in
psel : in std_ulogic;
penable : in std_ulogic;
paddr : in std_logic_vector(31 downto 0);
pwrite : in std_ulogic;
pwdata : in std_logic_vector(31 downto 0);
--apb slv out
prdata : out std_logic_vector(31 downto 0);
--irq
irq : out std_logic;
--ethernet input signals
gtx_clk : in std_ulogic;
tx_clk : in std_ulogic;
tx_dv : in std_ulogic;
rx_clk : in std_ulogic;
rxd : in std_logic_vector(7 downto 0);
rx_dv : in std_ulogic;
rx_er : in std_ulogic;
rx_col : in std_ulogic;
rx_crs : in std_ulogic;
rx_en : in std_ulogic;
mdio_i : in std_ulogic;
phyrstaddr : in std_logic_vector(4 downto 0);
mdint : in std_ulogic;
--ethernet output signals
reset : out std_ulogic;
txd : out std_logic_vector(7 downto 0);
tx_en : out std_ulogic;
tx_er : out std_ulogic;
mdc : out std_ulogic;
mdio_o : out std_ulogic;
mdio_oe : out std_ulogic;
--scantest
testrst : in std_ulogic;
testen : in std_ulogic;
testoen : in std_ulogic;
edcladdr : in std_logic_vector(3 downto 0);
edclsepahb : in std_ulogic;
edcldisable : in std_ulogic;
speed : out std_ulogic;
gbit : out std_ulogic
);
end component;
end package;
| gpl-3.0 |
EliasLuiz/TCC | Leon3/lib/gaisler/memctrl/sdctrl.in.vhd | 6 | 293 | -- SDRAM controller
constant CFG_SDCTRL : integer := CONFIG_SDCTRL;
constant CFG_SDCTRL_INVCLK : integer := CONFIG_SDCTRL_INVCLK;
constant CFG_SDCTRL_SD64 : integer := CONFIG_SDCTRL_BUS64;
constant CFG_SDCTRL_PAGE : integer := CONFIG_SDCTRL_PAGE + CONFIG_SDCTRL_PROGPAGE;
| gpl-3.0 |
EliasLuiz/TCC | Leon3/designs/leon3-minimal/config.vhd | 1 | 7705 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := artix7;
constant CFG_MEMTECH : integer := artix7;
constant CFG_PADTECH : integer := artix7;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := virtex;
constant CFG_CLKMUL : integer := (1);
constant CFG_CLKDIV : integer := (10);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 0 + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 0;
constant CFG_SVT : integer := 0;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 0;
constant CFG_NWP : integer := (0);
constant CFG_PWD : integer := 0*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 1;
constant CFG_ISETSZ : integer := 4;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 0;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 1;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 8;
constant CFG_DREPL : integer := 0;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 0 + 0 + 4*0;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 1;
constant CFG_ITLBNUM : integer := 8;
constant CFG_DTLBNUM : integer := 8;
constant CFG_TLB_TYPE : integer := 0 + 1*2;
constant CFG_TLB_REP : integer := 1;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 0;
constant CFG_ITBSZ : integer := 0;
constant CFG_ATBSZ : integer := 0;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 1;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 0;
-- Ethernet DSU
constant CFG_DSU_ETH : integer := 0 + 0 + 0;
constant CFG_ETH_BUF : integer := 1;
constant CFG_ETH_IPM : integer := 16#C0A8#;
constant CFG_ETH_IPL : integer := 16#0033#;
constant CFG_ETH_ENM : integer := 16#020000#;
constant CFG_ETH_ENL : integer := 16#000009#;
-- PROM/SRAM controller
constant CFG_SRCTRL : integer := 0;
constant CFG_SRCTRL_PROMWS : integer := 0;
constant CFG_SRCTRL_RAMWS : integer := 0;
constant CFG_SRCTRL_IOWS : integer := 0;
constant CFG_SRCTRL_RMW : integer := 0;
constant CFG_SRCTRL_8BIT : integer := 0;
constant CFG_SRCTRL_SRBANKS : integer := 1;
constant CFG_SRCTRL_BANKSZ : integer := 0;
constant CFG_SRCTRL_ROMASEL : integer := 0;
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 1;
constant CFG_MCTRL_RAM8BIT : integer := 0;
constant CFG_MCTRL_RAM16BIT : integer := 0;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 1;
constant CFG_MCTRL_SEPBUS : integer := 0;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 0;
constant CFG_MCTRL_PAGE : integer := 1 + 0;
-- SDRAM controller
constant CFG_SDCTRL : integer := 0;
constant CFG_SDCTRL_INVCLK : integer := 0;
constant CFG_SDCTRL_SD64 : integer := 0;
constant CFG_SDCTRL_PAGE : integer := 0 + 0;
-- AHB ROM
constant CFG_AHBROMEN : integer := 0;
constant CFG_AHBROPIP : integer := 0;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#000#;
constant CFG_ROMMASK : integer := 16#E00# + 16#000#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- Gaisler Ethernet core
constant CFG_GRETH : integer := 0;
constant CFG_GRETH1G : integer := 0;
constant CFG_ETH_FIFO : integer := 8;
-- CAN 2.0 interface
constant CFG_CAN : integer := 0;
constant CFG_CANIO : integer := 16#0#;
constant CFG_CANIRQ : integer := 0;
constant CFG_CANLOOP : integer := 0;
constant CFG_CAN_SYNCRST : integer := 0;
constant CFG_CANFT : integer := 0;
-- PCI interface
constant CFG_PCI : integer := 0;
constant CFG_PCIVID : integer := 16#0#;
constant CFG_PCIDID : integer := 16#0#;
constant CFG_PCIDEPTH : integer := 8;
constant CFG_PCI_MTF : integer := 1;
-- PCI arbiter
constant CFG_PCI_ARB : integer := 0;
constant CFG_PCI_ARBAPB : integer := 0;
constant CFG_PCI_ARB_NGNT : integer := 4;
-- PCI trace buffer
constant CFG_PCITBUFEN: integer := 0;
constant CFG_PCITBUF : integer := 256;
-- Spacewire interface
constant CFG_SPW_EN : integer := 0;
constant CFG_SPW_NUM : integer := 1;
constant CFG_SPW_AHBFIFO : integer := 4;
constant CFG_SPW_RXFIFO : integer := 16;
constant CFG_SPW_RMAP : integer := 0;
constant CFG_SPW_RMAPBUF : integer := 4;
constant CFG_SPW_RMAPCRC : integer := 0;
constant CFG_SPW_NETLIST : integer := 0;
constant CFG_SPW_FT : integer := 0;
constant CFG_SPW_GRSPW : integer := 2;
constant CFG_SPW_RXUNAL : integer := 0;
constant CFG_SPW_DMACHAN : integer := 1;
constant CFG_SPW_PORTS : integer := 1;
constant CFG_SPW_INPUT : integer := 2;
constant CFG_SPW_OUTPUT : integer := 0;
constant CFG_SPW_RTSAME : integer := 0;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 4;
-- UART 2
constant CFG_UART2_ENABLE : integer := 0;
constant CFG_UART2_FIFO : integer := 1;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 1;
constant CFG_GPT_WDOG : integer := 16#FFFF#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#0000#;
constant CFG_GRGPIO_WIDTH : integer := (8);
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
| gpl-3.0 |
EliasLuiz/TCC | Leon3/designs/leon3-altera-ep3c25/config.vhd | 1 | 5954 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := cyclone3;
constant CFG_MEMTECH : integer := cyclone3;
constant CFG_PADTECH : integer := cyclone3;
constant CFG_TRANSTECH : integer := GTP0;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := cyclone3;
constant CFG_CLKMUL : integer := (10);
constant CFG_CLKDIV : integer := (10);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 16#32# + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 1;
constant CFG_SVT : integer := 0;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 0;
constant CFG_NWP : integer := (2);
constant CFG_PWD : integer := 0*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 2;
constant CFG_ISETSZ : integer := 8;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 0;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 2;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 4;
constant CFG_DREPL : integer := 0;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 0 + 1*2 + 4*0;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 1;
constant CFG_ITLBNUM : integer := 8;
constant CFG_DTLBNUM : integer := 2;
constant CFG_TLB_TYPE : integer := 1 + 0*2;
constant CFG_TLB_REP : integer := 1;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 2 + 64*0;
constant CFG_ATBSZ : integer := 2;
constant CFG_AHBPF : integer := 0;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
constant CFG_STAT_ENABLE : integer := 0;
constant CFG_STAT_CNT : integer := 1;
constant CFG_STAT_NMAX : integer := 0;
constant CFG_STAT_DSUEN : integer := 0;
constant CFG_NP_ASI : integer := 0;
constant CFG_WRPSR : integer := 0;
constant CFG_ALTWIN : integer := 0;
constant CFG_REX : integer := 0;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 0;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 1;
constant CFG_MCTRL_RAM8BIT : integer := 0;
constant CFG_MCTRL_RAM16BIT : integer := 1;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 0;
constant CFG_MCTRL_SEPBUS : integer := 0;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 0;
constant CFG_MCTRL_PAGE : integer := 0 + 0;
-- SSRAM controller
constant CFG_SSCTRL : integer := 0;
constant CFG_SSCTRLP16 : integer := 0;
-- DDR controller
constant CFG_DDRSP : integer := 1;
constant CFG_DDRSP_INIT : integer := 1;
constant CFG_DDRSP_FREQ : integer := (100);
constant CFG_DDRSP_COL : integer := (9);
constant CFG_DDRSP_SIZE : integer := (32);
constant CFG_DDRSP_RSKEW : integer := (2500);
-- AHB ROM
constant CFG_AHBROMEN : integer := 0;
constant CFG_AHBROPIP : integer := 0;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#000#;
constant CFG_ROMMASK : integer := 16#E00# + 16#000#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 8;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#6#;
constant CFG_GRGPIO_WIDTH : integer := (3);
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
| gpl-3.0 |
EliasLuiz/TCC | Leon3/designs/leon3-digilent-nexys-video/leon3mp.vhd | 1 | 27309 | ------------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2016 Cobham Gaisler
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
use techmap.allclkgen.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.spi.all;
use gaisler.net.all;
use gaisler.jtag.all;
use gaisler.ddrpkg.all;
--pragma translate_off
use gaisler.sim.all;
library unisim;
use unisim.all;
--pragma translate_on
library esa;
use esa.memoryctrl.all;
use work.config.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
SIM_BYPASS_INIT_CAL : string := "OFF";
SIMULATION : string := "FALSE";
USE_MIG_INTERFACE_MODEL : boolean := false
);
port (
sysclk : in std_ulogic;
-- LEDs
led : out std_logic_vector(7 downto 0);
-- Buttons
btnc : in std_ulogic;
btnd : in std_ulogic;
btnl : in std_ulogic;
btnr : in std_ulogic;
cpu_resetn : in std_ulogic;
-- Switches
sw : in std_logic_vector(7 downto 0);
-- USB-RS232 interface
uart_tx_in : in std_logic;
uart_rx_out : out std_logic;
-- DDR3
ddr3_dq : inout std_logic_vector(15 downto 0);
ddr3_dqs_p : inout std_logic_vector(1 downto 0);
ddr3_dqs_n : inout std_logic_vector(1 downto 0);
ddr3_addr : out std_logic_vector(14 downto 0);
ddr3_ba : out std_logic_vector(2 downto 0);
ddr3_ras_n : out std_logic;
ddr3_cas_n : out std_logic;
ddr3_we_n : out std_logic;
ddr3_reset_n : out std_logic;
ddr3_ck_p : out std_logic_vector(0 downto 0);
ddr3_ck_n : out std_logic_vector(0 downto 0);
ddr3_cke : out std_logic_vector(0 downto 0);
ddr3_dm : out std_logic_vector(1 downto 0);
ddr3_odt : out std_logic_vector(0 downto 0);
-- Ethernet
--eth_int_b : in std_logic;
--eth_mdc : out std_logic;
--eth_mdio : inout std_logic;
--eth_pme_b : out std_ulogic;
--eth_rst_b : out std_logic;
--eth_rxck : in std_logic;
--eth_rxctl : in std_logic;
--eth_rxd : in std_logic_vector(3 downto 0);
--eth_txck : in std_logic;
--eth_txctl : out std_logic;
--eth_txd : out std_logic_vector(3 downto 0);
phy_txclk : out std_logic;
phy_txd : out std_logic_vector(3 downto 0);
phy_txctl_txen : out std_ulogic;
phy_rxd : in std_logic_vector(3 downto 0);
phy_rxctl_rxdv : in std_ulogic;
phy_rxclk : in std_ulogic;
phy_reset : out std_ulogic;
phy_mdio : inout std_logic;
phy_mdc : out std_ulogic;
phy_int : in std_ulogic;
-- Fan PWM
fan_pwm : out std_ulogic;
-- SPI
qspi_cs : out std_ulogic;
qspi_dq : inout std_logic_vector(3 downto 0);
scl : out std_ulogic
);
end;
architecture rtl of leon3mp is
component IDELAYCTRL
port (
RDY : out std_ulogic;
REFCLK : in std_ulogic;
RST : in std_ulogic
);
end component;
component IODELAYE1
generic (
DELAY_SRC : string := "I";
IDELAY_TYPE : string := "DEFAULT";
IDELAY_VALUE : integer := 0;
ODELAY_VALUE : integer := 0
);
port (
CNTVALUEOUT : out std_logic_vector(4 downto 0);
DATAOUT : out std_ulogic;
C : in std_ulogic;
CE : in std_ulogic;
CINVCTRL : in std_ulogic;
CLKIN : in std_ulogic;
CNTVALUEIN : in std_logic_vector(4 downto 0);
DATAIN : in std_ulogic;
IDATAIN : in std_ulogic;
INC : in std_ulogic;
ODATAIN : in std_ulogic;
RST : in std_ulogic;
T : in std_ulogic
);
end component;
component ODELAYE2
generic (
ODELAY_VALUE : integer := 0
);
port (
C : in std_ulogic;
REGRST : in std_ulogic;
LD : in std_ulogic;
CE : in std_ulogic;
INC : in std_ulogic;
CINVCTRL : in std_ulogic;
CNTVALUEIN : in std_logic_vector(4 downto 0);
CLKIN : in std_ulogic;
ODATAIN : in std_ulogic;
LDPIPEEN : in std_ulogic;
DATAOUT : out std_ulogic;
CNTVALUEOUT : out std_logic_vector(4 downto 0)
);
end component;
signal vcc : std_logic;
signal gnd : std_logic;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal cgi : clkgen_in_type;
signal cgo, cgo1 : clkgen_out_type;
signal cgi2 : clkgen_in_type;
signal cgo2 : clkgen_out_type;
signal u1i, dui : uart_in_type;
signal u1o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to CFG_NCPU-1);
signal irqo : irq_out_vector(0 to CFG_NCPU-1);
signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1);
signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal ndsuact : std_ulogic;
signal ethi : eth_in_type;
signal etho : eth_out_type;
signal gpti : gptimer_in_type;
signal spmi : spimctrl_in_type;
signal spmo : spimctrl_out_type;
signal clkm : std_ulogic
-- pragma translate_off
:= '0'
-- pragma translate_on
;
signal clkm2x, rstn : std_ulogic;
signal tck, tms, tdi, tdo : std_ulogic;
signal rstraw : std_logic;
signal lcpu_resetn : std_logic;
signal lock : std_logic;
signal clkinmig : std_logic;
signal clkref, calib_done, migrstn : std_logic;
signal gmiii : eth_in_type;
signal gmiio : eth_out_type;
signal rgmiii,rgmiii_buf : eth_in_type;
signal rgmiio : eth_out_type;
signal ethernet_phy_int : std_logic;
signal rxd1 : std_logic;
signal txd1 : std_logic;
--signal ethi : eth_in_type;
--signal etho : eth_out_type;
signal gtx_clk,gtx_clk_nobuf,gtx_clk90 : std_ulogic;
signal rstgtxn : std_logic;
signal idelay_reset_cnt : std_logic_vector(3 downto 0);
signal idelayctrl_reset : std_logic;
signal io_ref : std_logic;
signal phy_txclk_delay : std_logic;
attribute keep : boolean;
attribute syn_keep : boolean;
attribute syn_preserve : boolean;
attribute syn_keep of lock : signal is true;
attribute syn_keep of clkm : signal is true;
attribute syn_preserve of clkm : signal is true;
attribute keep of lock : signal is true;
attribute keep of clkm : signal is true;
constant BOARD_FREQ : integer := 100000; -- CLK input frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz
begin
vcc <= '1'; gnd <= '0';
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
cgi.pllctrl <= "00";
cgi.pllrst <= rstraw;
rst_pad : inpad generic map (tech => padtech, level => cmos, voltage => x15v)
port map (cpu_resetn, lcpu_resetn);
rst0 : rstgen
port map (lcpu_resetn, clkm, lock, rstn, rstraw);
lock <= calib_done when CFG_MIG_7SERIES = 1 else cgo.clklock;
rst1 : rstgen -- reset generator
port map (lcpu_resetn, clkm, vcc, migrstn, open);
-- clock generator
clkgen_gen: if (CFG_MIG_7SERIES = 0) generate
clkgen0 : clkgen
generic map (fabtech, CFG_CLKMUL, CFG_CLKDIV, 0, 0, 0, 0, 0, BOARD_FREQ, 0)
port map (sysclk, gnd, clkm, open, clkm2x, open, open, cgi, cgo, open, open, open);
end generate;
led(7) <= lcpu_resetn;
led(6) <= calib_done;
led(5) <= rstn;
led(4) <= lock; -- Used in TB
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, ioen => 1,
nahbm => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH,
nahbs => 8)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
-- LEON3 processor
leon3gen : if CFG_LEON3 = 1 generate
cpu : for i in 0 to CFG_NCPU-1 generate
u0 : leon3s
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR,
CFG_NCPU-1, CFG_DFIXED, CFG_SCAN, CFG_MMU_PAGE, CFG_BP, CFG_NP_ASI, CFG_WRPSR,
CFG_REX, CFG_ALTWIN)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso, irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
led(3) <= not dbgo(0).error;
led(2) <= not dsuo.active;
-- LEON3 Debug Support Unit
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#, ahbpf => CFG_AHBPF,
ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
--dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsui.break);
dsui.enable <= '1';
end generate;
end generate;
nodsu : if CFG_DSU = 0 generate
ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';
end generate;
-- Debug UART
dcomgen : if CFG_AHB_UART = 1 generate
dcom0 : ahbuart
generic map (hindex => CFG_NCPU, pindex => 4, paddr => 7)
port map (rstn, clkm, dui, duo, apbi, apbo(4), ahbmi, ahbmo(CFG_NCPU));
dsurx_pad : inpad generic map (tech => padtech) port map (uart_tx_in, dui.rxd);
dsutx_pad : outpad generic map (tech => padtech) port map (uart_rx_out, duo.txd);
led(0) <= not dui.rxd;
led(1) <= not duo.txd;
end generate;
nouah : if CFG_AHB_UART = 0 generate apbo(4) <= apb_none; end generate;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => CFG_NCPU+CFG_AHB_UART)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART),
open, open, open, open, open, open, open, gnd);
end generate;
----------------------------------------------------------------------
--- DDR3 Memory controller ------------------------------------------
----------------------------------------------------------------------
-- nomig : if (CFG_MIG_7SERIES = 0) generate end generate;
mig_gen : if (CFG_MIG_7SERIES = 1) generate
gen_mig : if (USE_MIG_INTERFACE_MODEL /= true) generate
ddrc : ahb2mig_7series_ddr3_dq16_ad15_ba3 generic map(
hindex => 5, haddr => 16#400#, hmask => 16#F00#, pindex => 5, paddr => 5,
SIM_BYPASS_INIT_CAL => SIM_BYPASS_INIT_CAL, SIMULATION => SIMULATION,
USE_MIG_INTERFACE_MODEL => USE_MIG_INTERFACE_MODEL)
port map(
ddr3_dq => ddr3_dq,
ddr3_dqs_p => ddr3_dqs_p,
ddr3_dqs_n => ddr3_dqs_n,
ddr3_addr => ddr3_addr,
ddr3_ba => ddr3_ba,
ddr3_ras_n => ddr3_ras_n,
ddr3_cas_n => ddr3_cas_n,
ddr3_we_n => ddr3_we_n,
ddr3_reset_n => ddr3_reset_n,
ddr3_ck_p => ddr3_ck_p,
ddr3_ck_n => ddr3_ck_n,
ddr3_cke => ddr3_cke,
ddr3_dm => ddr3_dm,
ddr3_odt => ddr3_odt,
ahbsi => ahbsi,
ahbso => ahbso(5),
apbi => apbi,
apbo => apbo(5),
calib_done => calib_done,
rst_n_syn => migrstn,
rst_n_async => cgo1.clklock,--rstraw,
clk_amba => clkm,
sys_clk_i => clkinmig,
-- clk_ref_i => clkref,
ui_clk => clkm, -- 100 MHz clk , DDR at 400 MHz
ui_clk_sync_rst => open);
clkgenmigin : clkgen
generic map (clktech, 8, 4, 0, CFG_CLK_NOFB, 0, 0, 0, 100000)
port map (sysclk, sysclk, clkinmig, open, open, open, open, cgi, cgo1, open, open, open);
end generate gen_mig;
gen_mig_model : if (USE_MIG_INTERFACE_MODEL = true) generate
-- pragma translate_off
mig_ahbram : ahbram_sim
generic map (
hindex => 5,
haddr => 16#400#,
hmask => 16#F80#,
tech => 0,
kbytes => 1000,
pipe => 0,
maccsz => AHBDW,
fname => "ram.srec"
)
port map(
rst => rstn,
clk => clkm,
ahbsi => ahbsi,
ahbso => ahbso(5)
);
ddr3_dq <= (others => 'Z');
ddr3_dqs_p <= (others => 'Z');
ddr3_dqs_n <= (others => 'Z');
ddr3_addr <= (others => '0');
ddr3_ba <= (others => '0');
ddr3_ras_n <= '0';
ddr3_cas_n <= '0';
ddr3_we_n <= '0';
ddr3_ck_p <= (others => '0');
ddr3_ck_n <= (others => '0');
ddr3_cke <= (others => '0');
ddr3_dm <= (others => '0');
ddr3_odt <= (others => '0');
--calib_done : out std_logic;
calib_done <= '1';
--ui_clk : out std_logic;
clkm <= not clkm after 10.0 ns;
--ui_clk_sync_rst : out std_logic
-- n/a
-- pragma translate_on
end generate gen_mig_model; end generate;
----------------------------------------------------------------------
--- SPI Memory controller -------------------------------------------
----------------------------------------------------------------------
spi_gen: if CFG_SPIMCTRL = 1 generate
-- OPTIONALY set the offset generic (only affect reads).
-- The first 4MB are used for loading the FPGA.
-- For dual ouptut: readcmd => 16#3B#, dualoutput => 1
spimctrl1 : spimctrl
generic map (hindex => 7, hirq => 7, faddr => 16#000#, fmask => 16#ff0#,
ioaddr => 16#700#, iomask => 16#fff#, spliten => CFG_SPLIT,
sdcard => CFG_SPIMCTRL_SDCARD, readcmd => CFG_SPIMCTRL_READCMD,
dummybyte => CFG_SPIMCTRL_DUMMYBYTE,
dualoutput => CFG_SPIMCTRL_DUALOUTPUT, scaler => CFG_SPIMCTRL_SCALER,
altscaler => CFG_SPIMCTRL_ASCALER)
port map (rstn, clkm, ahbsi, ahbso(7), spmi, spmo);
qspi_dq(3) <= '1'; qspi_dq(2) <= '1';
spi_mosi_pad : outpad generic map (tech => padtech)
port map (qspi_dq(0), spmo.mosi);
spi_miso_pad : inpad generic map (tech => padtech)
port map (qspi_dq(1), spmi.miso);
spi_slvsel0_pad : outpad generic map (tech => padtech)
port map (qspi_cs, spmo.csn);
spi_sck_pad : outpad generic map (tech => padtech)
port map (scl, spmo.sck);
end generate;
nospi: if CFG_SPIMCTRL = 0 generate
ahbso(7) <= ahbs_none;
end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
-- APB Bridge
apb0 : apbctrl
generic map (hindex => 1, haddr => CFG_APBADDR)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo);
-- Interrupt controller
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp
generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to CFG_NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
-- Timer Unit
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW,
ntimers => CFG_GPT_NTIM, nbits => CFG_GPT_TW)
port map (rstn, clkm, apbi, apbo(3), gpti, open);
gpti <= gpti_dhalt_drive(dsuo.tstop);
end generate;
notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart, fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.rxd <= rxd1;
u1i.ctsn <= '0';
u1i.extclk <= '0';
txd1 <= u1o.txd;
end generate;
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
-----------------------------------------------------------------------
--- ETHERNET ---------------------------------------------------------
-----------------------------------------------------------------------
eth0 : if CFG_GRETH = 1 generate -- Gaisler ethernet MAC
e1 : grethm
generic map(
hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
pindex => 15, paddr => 15, pirq => 12, memtech => memtech,
mdcscaler => CPU_FREQ/1000, rmii => 0, enable_mdio => 1, fifosize => CFG_ETH_FIFO,
nsync => 2, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF, phyrstadr => 1,
macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL, enable_mdint => 1,
ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL,
giga => CFG_GRETH1G, ramdebug => 0, gmiimode => 1)
port map( rst => rstn, clk => clkm, ahbmi => ahbmi,
ahbmo => ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG),
apbi => apbi, apbo => apbo(15), ethi => ethi, etho => etho);
-----------------------------------------------------------------------------
-- An IDELAYCTRL primitive needs to be instantiated for the Fixed Tap Delay
-- mode of the IDELAY.
-- All IDELAYs in Fixed Tap Delay mode and the IDELAYCTRL primitives have
-- to be LOC'ed in the UCF file.
-----------------------------------------------------------------------------
dlyctrl0 : IDELAYCTRL port map (
RDY => OPEN,
REFCLK => sysclk,
RST => idelayctrl_reset
);
delay_rgmii_rx_ctl0 : IODELAYE1 generic map(
DELAY_SRC => "I",
IDELAY_TYPE => "FIXED",
IDELAY_VALUE => 20,
ODELAY_VALUE => 20
)
port map(
IDATAIN => rgmiii_buf.rx_dv,
ODATAIN => '0',
DATAOUT => rgmiii.rx_dv,
DATAIN => '0',
C => '0',
T => '1',
CE => '0',
INC => '0',
CINVCTRL => '0',
CLKIN => '0',
CNTVALUEIN => "00000",
CNTVALUEOUT => OPEN,
RST => '0'
);
rgmii_rxd : for i in 0 to 3 generate
delay_rgmii_rxd0 : IODELAYE1 generic map(
DELAY_SRC => "I",
IDELAY_TYPE => "FIXED",
IDELAY_VALUE => 20,
ODELAY_VALUE => 20
)
port map(
IDATAIN => rgmiii_buf.rxd(i),
ODATAIN => '0',
DATAOUT => rgmiii.rxd(i),
DATAIN => '0',
C => '0',
T => '1',
CE => '0',
INC => '0',
CINVCTRL => '0',
CLKIN => '0',
CNTVALUEIN => "00000",
CNTVALUEOUT => OPEN,
RST => '0'
);
end generate;
phy_txclk_delay <= rgmiio.tx_clk;
-- Generate a synchron delayed reset for Xilinx IO delay
rst1 : rstgen
generic map (acthigh => 1)
port map (lcpu_resetn, sysclk, lock, rstgtxn, OPEN);
process (sysclk,rstgtxn)
begin
if (rstgtxn = '0') then
idelay_reset_cnt <= (others => '0');
idelayctrl_reset <= '1';
elsif rising_edge(sysclk) then
if (idelay_reset_cnt > "1110") then
idelay_reset_cnt <= (others => '1');
idelayctrl_reset <= '0';
else
idelay_reset_cnt <= idelay_reset_cnt + 1;
idelayctrl_reset <= '1';
end if;
end if;
end process;
-- RGMII Interface
rgmii0 : rgmii generic map (pindex => 11, paddr => 16#010#, pmask => 16#ff0#, tech => fabtech,
gmii => CFG_GRETH1G, debugmem => 1, abits => 8, no_clk_mux => 0,
pirq => 11, use90degtxclk => 0, mode100 => 1)
port map (rstn, ethi, etho, rgmiii, rgmiio, clkm, rstn, apbi, apbo(11));
egtxc_pad : outpad generic map (tech => padtech, level => cmos, voltage => x25v, slew => 1)
port map (phy_txclk, phy_txclk_delay);
erxc_pad : clkpad generic map (tech => padtech, level => cmos, voltage => x25v, arch => 1)
port map (phy_rxclk, rgmiii.rx_clk);
erxd_pad : inpadv generic map (tech => padtech, level => cmos, voltage => x25v, width => 4)
port map (phy_rxd, rgmiii_buf.rxd(3 downto 0));
erxdv_pad : inpad generic map (tech => padtech, level => cmos, voltage => x25v)
port map (phy_rxctl_rxdv, rgmiii_buf.rx_dv);
etxd_pad : outpadv generic map (tech => padtech, level => cmos, voltage => x25v, slew => 1, width => 4)
port map (phy_txd, rgmiio.txd(3 downto 0));
etxen_pad : outpad generic map (tech => padtech, level => cmos, voltage => x25v, slew => 1)
port map (phy_txctl_txen, rgmiio.tx_en);
emdio_pad : iopad generic map (tech => padtech, level => cmos, voltage => x25v)
port map (phy_mdio, rgmiio.mdio_o, rgmiio.mdio_oe, rgmiii.mdio_i);
emdc_pad : outpad generic map (tech => padtech, level => cmos, voltage => x25v)
port map (phy_mdc, rgmiio.mdc);
eint_pad : inpad generic map (tech => padtech, level => cmos, voltage => x25v)
port map (phy_int, rgmiii.mdint);
erst_pad : outpad generic map (tech => padtech, level => cmos, voltage => x25v)
port map (phy_reset, rgmiio.reset);
-- Use system clock for RGMII interface
rgmiii.gtx_clk <= clkm;
end generate;
noeth0 : if CFG_GRETH = 0 generate
-- TODO:
end generate;
-----------------------------------------------------------------------
--- AHB ROM ----------------------------------------------------------
-----------------------------------------------------------------------
bpromgen : if CFG_AHBROMEN /= 0 generate
brom : entity work.ahbrom
generic map (hindex => 6, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
port map ( rstn, clkm, ahbsi, ahbso(6));
end generate;
nobpromgen : if CFG_AHBROMEN = 0 generate
ahbso(6) <= ahbs_none;
end generate;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
ahbramgen : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram
generic map (hindex => 3, haddr => CFG_AHBRADDR, tech => CFG_MEMTECH,
kbytes => CFG_AHBRSZ, pipe => CFG_AHBRPIPE)
port map (rstn, clkm, ahbsi, ahbso(3));
end generate;
nram : if CFG_AHBRAMEN = 0 generate ahbso(3) <= ahbs_none; end generate;
-----------------------------------------------------------------------
-- Test report module, only used for simulation ----------------------
-----------------------------------------------------------------------
--pragma translate_off
test0 : ahbrep generic map (hindex => 4, haddr => 16#200#)
port map (rstn, clkm, ahbsi, ahbso(4));
--pragma translate_on
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
nam1 : for i in (CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH+1) to NAHBMST-1 generate
ahbmo(i) <= ahbm_none;
end generate;
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 Demonstration design for Digilent Nexys Video board",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end rtl;
| gpl-3.0 |
EliasLuiz/TCC | Leon3/designs/leon3-digilent-nexys3/testbench.vhd | 1 | 8167 | -----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
library techmap;
use techmap.gencomp.all;
use work.debug.all;
use work.config.all;
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
clkperiod : integer := 37; -- system clock period
romwidth : integer := 16; -- rom data width (8/32)
romdepth : integer := 16 -- rom address depth
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec"; -- rom contents
constant sdramfile : string := "ram.srec"; -- sdram contents
constant lresp : boolean := false;
constant ct : integer := clkperiod/2;
signal clk : std_logic := '0';
signal clk200p : std_logic := '1';
signal clk200n : std_logic := '0';
signal rst : std_logic := '0';
signal rstn1 : std_logic;
signal rstn2 : std_logic;
signal error : std_logic;
-- PROM flash
signal address : std_logic_vector(26 downto 0):=(others =>'0');
signal data : std_logic_vector(31 downto 0);
signal RamCS : std_logic;
signal oen : std_ulogic;
signal writen : std_ulogic;
signal iosn : std_ulogic;
signal FlashCS : std_ulogic;
-- Debug support unit
signal dsubre : std_ulogic;
-- AHB Uart
signal dsurx : std_ulogic;
signal dsutx : std_ulogic;
-- APB Uart
signal urxd : std_ulogic;
signal utxd : std_ulogic;
-- Ethernet signals
signal etx_clk : std_ulogic;
signal erx_clk : std_ulogic;
signal erxdt : std_logic_vector(7 downto 0);
signal erx_dv : std_ulogic;
signal erx_er : std_ulogic;
signal erx_col : std_ulogic;
signal erx_crs : std_ulogic;
signal etxdt : std_logic_vector(7 downto 0);
signal etx_en : std_ulogic;
signal etx_er : std_ulogic;
signal emdc : std_ulogic;
signal emdio : std_logic;
-- SVGA signals
signal vid_hsync : std_ulogic;
signal vid_vsync : std_ulogic;
signal vid_r : std_logic_vector(3 downto 0);
signal vid_g : std_logic_vector(3 downto 0);
signal vid_b : std_logic_vector(3 downto 0);
-- Select signal for SPI flash
signal spi_sel_n : std_logic;
signal spi_clk : std_logic;
signal spi_mosi : std_logic;
-- Output signals for LEDs
signal led : std_logic_vector(7 downto 0);
signal brdyn : std_ulogic;
signal sw : std_logic_vector(7 downto 0):= (others =>'0');
signal btn : std_logic_vector(4 downto 0):= (others =>'0');
begin
-- clock and reset
clk <= not clk after ct * 1 ns;
rst <= '1', '0' after 100 ns;
dsubre <= '0';
urxd <= 'H';
spi_sel_n <= 'H';
spi_clk <= 'L';
d3 : entity work.leon3mp
generic map (fabtech, memtech, padtech, clktech, disas, dbguart, pclow)
port map (
clk => clk,
-- PROM
address => address(25 downto 0),
data => data(31 downto 16),
MemOE => oen,
MemWR => writen,
RamCS => RamCS,
--FlashRp => FlashRP
FlashCS => FlashCS,
-- AHB Uart
RsRx => dsurx,
RsTx => dsutx,
-- PHY
PhyTxClk => etx_clk,
PhyRxClk => erx_clk,
PhyRxd => erxdt(3 downto 0),
PhyRxDv => erx_dv,
PhyRxEr => erx_er,
PhyCol => erx_col,
PhyCrs => erx_crs,
PhyTxd => etxdt(3 downto 0),
PhyTxEn => etx_en,
PhyTxEr => etx_er,
PhyMdc => emdc,
PhyMdio => emdio,
-- Output signals for LEDs
led => led,
sw => sw,
btn => btn
);
btn(0) <= rst;
prom0 : for i in 0 to (romwidth/8)-1 generate
sr0 : sram generic map (index => 4+i, abits => romdepth, fname => promfile)--index => i
port map (address(romdepth-1 downto 0), data(31-i*8 downto 24-i*8), FlashCS,
writen, oen);
end generate;
sram0 : sram
generic map (index => 4, abits => 24, fname => sdramfile)
port map (address(23 downto 0), data(31 downto 24), RamCS, writen, oen);
sram1 : sram
generic map (index => 5, abits => 24, fname => sdramfile)
port map (address(23 downto 0), data(23 downto 16), RamCS, writen, oen);
phy0 : if (CFG_GRETH = 1) generate
emdio <= 'H';
p0: phy
generic map (address => 1)
port map(rstn1, emdio, etx_clk, erx_clk, erxdt, erx_dv, erx_er,
erx_col, erx_crs, etxdt, etx_en, etx_er, emdc, '0');
end generate;
spimem0: if CFG_SPIMCTRL = 1 generate
s0 : spi_flash generic map (ftype => 4, debug => 0, fname => promfile,
readcmd => CFG_SPIMCTRL_READCMD,
dummybyte => CFG_SPIMCTRL_DUMMYBYTE,
dualoutput => 0) -- Dual output is not supported in this design
port map (spi_clk, spi_mosi, data(24), spi_sel_n);
end generate spimem0;
led(3) <= 'L'; -- ERROR pull-down
error <= not led(3);
iuerr : process
begin
wait for 5 us;
assert (to_X01(error) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure;
end process;
test0 : grtestmod
port map ( rst, clk, error, address(21 downto 2), data, iosn, oen, writen, brdyn);
data <= buskeep(data) after 5 ns;
dsucom : process
procedure dsucfg(signal dsurx : in std_ulogic; signal dsutx : out std_ulogic) is
variable w32 : std_logic_vector(31 downto 0);
variable c8 : std_logic_vector(7 downto 0);
constant txp : time := 160 * 1 ns;
begin
dsutx <= '1';
wait;
wait for 5000 ns;
txc(dsutx, 16#55#, txp); -- sync uart
txc(dsutx, 16#a0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#00#, 16#ef#, txp);
--
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#ff#, 16#ff#, txp);
--
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#40#, 16#00#, 16#48#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#00#, 16#12#, txp);
--
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#40#, 16#00#, 16#60#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#12#, 16#10#, txp);
--
-- txc(dsutx, 16#80#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
-- rxi(dsurx, w32, txp, lresp);
end;
begin
dsucfg(dsutx, dsurx);
wait;
end process;
end;
| gpl-3.0 |
EliasLuiz/TCC | Leon3/lib/gaisler/misc/ahbtrace.vhd | 1 | 2839 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ahbtrace
-- File: ahbtrace.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: AHB trace unit
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.misc.all;
entity ahbtrace is
generic (
hindex : integer := 0;
ioaddr : integer := 16#000#;
iomask : integer := 16#E00#;
tech : integer := DEFMEMTECH;
irq : integer := 0;
kbytes : integer := 1;
bwidth : integer := 32;
ahbfilt : integer := 0;
scantest : integer range 0 to 1 := 0;
exttimer : integer range 0 to 1 := 0;
exten : integer range 0 to 1 := 0);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
timer : in std_logic_vector(30 downto 0) := (others => '0');
astat : out amba_stat_type;
resen : in std_ulogic := '0'
);
end;
architecture rtl of ahbtrace is
begin
ahbt0 : ahbtrace_mb
generic map (
hindex => hindex,
ioaddr => ioaddr,
iomask => iomask,
tech => tech,
irq => irq,
kbytes => kbytes,
bwidth => bwidth,
ahbfilt => ahbfilt,
scantest => scantest,
exttimer => exttimer,
exten => exten)
port map(
rst => rst,
clk => clk,
ahbsi => ahbsi,
ahbso => ahbso,
tahbmi => ahbmi,
tahbsi => ahbsi,
timer => timer,
astat => astat,
resen => resen);
end;
| gpl-3.0 |
EliasLuiz/TCC | Leon3/lib/gaisler/sim/ddr2ram.vhd | 1 | 23543 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ddr2ram
-- File: ddr2ram.vhd
-- Author: Magnus Hjorth, Aeroflex Gaisler
-- Description: Generic simulation model of DDR2 SDRAM (JESD79-2C)
------------------------------------------------------------------------------
--pragma translate_off
use std.textio.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library grlib;
use grlib.stdio.hread;
use grlib.stdlib.all;
entity ddr2ram is
generic (
width: integer := 32;
abits: integer range 13 to 16 := 13;
babits: integer range 2 to 3 := 3;
colbits: integer range 9 to 11 := 9;
rowbits: integer range 1 to 16 := 13;
implbanks: integer range 1 to 8 := 1;
swap : integer := 0; -- byte swap during srec load
fname: string;
lddelay: time := (0 ns);
ldguard: integer range 0 to 1 := 0; -- 1: wait for doload input before
-- loading RAM
-- Speed bins: 0:DDR2-400C,1:400B,2:533C,3:533B,4:667D,5:667C,6:800E,7:800D,8:800C
-- 9:800+ (MT47H-25E)
speedbin: integer range 0 to 9 := 0;
density: integer range 1 to 5 := 3; -- 1:256M 2:512M 3:1G 4:2G 5:4G bits/chip
pagesize: integer range 1 to 2 := 1 -- 1K/2K page size (controls tRRD)
);
port (
ck: in std_ulogic;
ckn: in std_ulogic;
cke: in std_ulogic;
csn: in std_ulogic;
odt: in std_ulogic;
rasn: in std_ulogic;
casn: in std_ulogic;
wen: in std_ulogic;
dm: in std_logic_vector(width/8-1 downto 0);
ba: in std_logic_vector(babits-1 downto 0);
a: in std_logic_vector(abits-1 downto 0);
dq: inout std_logic_vector(width-1 downto 0);
dqs: inout std_logic_vector(width/8-1 downto 0);
dqsn: inout std_logic_vector(width/8-1 downto 0);
doload: in std_ulogic := '1'
);
end;
architecture sim of ddr2ram is
type moderegs is record
-- Mode register (0)
pd: std_ulogic;
wr: std_logic_vector(2 downto 0);
dllres: std_ulogic;
tm: std_ulogic;
caslat: std_logic_vector(2 downto 0);
bt: std_ulogic;
blen: std_logic_vector(2 downto 0);
-- Extended mode register 1
qoff: std_ulogic;
rdqsen: std_ulogic;
dqsndis: std_ulogic;
ocdprog: std_logic_vector(2 downto 0);
al: std_logic_vector(2 downto 0);
rtt: std_logic_vector(1 downto 0);
ds: std_ulogic;
dlldis: std_ulogic;
-- Extended mode register 2
srf: std_ulogic;
dccen: std_ulogic;
pasr: std_logic_vector(2 downto 0);
-- Extended mode register 3
emr3: std_logic_vector(abits-1 downto 0);
end record;
-- Mode registers as signal, useful for debugging
signal mr: moderegs;
-- Handshaking between command and DQ/DQS processes
signal read_en, write_en: boolean := false;
signal read_data, write_data: std_logic_vector(2*width-1 downto 0);
signal write_mask: std_logic_vector(width/4-1 downto 0);
signal initdone: boolean := false;
-- Small delta-t to adjust calculations for jitter tol.
constant deltat: time := 50 ps;
-- Timing parameters
constant tWR: time := 15 ns;
constant tMRD_ck: integer := 2;
constant tRTP: time := 7.5 ns;
type timetab is array (0 to 9) of time;
-- 400C 400B 533C 533B 667D 667C 800E 800D 800C MT-2.5E
constant tRAS : timetab := (45 ns, 40 ns, 45 ns, 45 ns, 45 ns, 45 ns, 45 ns, 45 ns, 45 ns, 40 ns);
constant tRP : timetab := (20 ns, 15 ns, 15 ns, 11.25 ns, 15 ns, 12 ns, 15 ns, 12.5 ns, 10 ns, 12.5 ns);
constant tRCD: timetab := tRP;
type timetab2 is array(1 to 5) of time;
constant tRFC: timetab2 := (75 ns, 105 ns, 127.5 ns, 195 ns, 327.5 ns);
type timetab3 is array(1 to 2) of time;
constant tRRD: timetab3 := (7.5 ns, 10 ns);
begin
-----------------------------------------------------------------------------
-- Init sequence checker
-----------------------------------------------------------------------------
initp: process
variable cyctr: integer := 0;
procedure checkcmd(crasn,ccasn,cwen: std_ulogic;
cba: std_logic_vector(1 downto 0);
ca: std_logic_vector(15 downto 0)) is
variable amatch: boolean;
begin
wait until rising_edge(ck);
cyctr := cyctr+1;
while cke='1' and (csn='1' or (rasn='1' and casn='1' and wen='1')) loop
wait until rising_edge(ck);
cyctr := cyctr+1;
end loop;
amatch := true;
for x in a'range loop
if ca(x)/='-' and ca(x)/=a(x) then amatch:=false; end if;
end loop;
assert cke='1' and csn='0' and rasn=crasn and casn=ccasn and wen=cwen and
(cba="--" or cba=ba(1 downto 0)) and amatch
report "Wrong command during init sequence" severity warning;
end checkcmd;
variable t: time;
begin
initdone <= false;
-- Allow cke to be X or U for a while during sim start
if is_x(cke) then
wait until not is_x(cke);
end if;
assert cke='0' report "CKE not deasserted on power-up" severity warning;
wait until cke/='0' for 200 us;
assert cke='0' report "CKE raised with less than 200 us init delay" severity warning;
wait until cke/='0' and rising_edge(ck);
assert cke='1' and (csn='1' or (rasn='1' and casn='1' and wen='1'));
t := now;
-- Precharge all
checkcmd('0','1','0',"--","-----1----------");
assert (now-t) > 400 ns report "Less than 400 ns wait period after CKE high!" severity warning;
-- EMRS EMR2
checkcmd('0','0','0',"10","----------------");
-- EMRS EMR3
checkcmd('0','0','0',"11","----------------");
-- EMRS enable DLL
checkcmd('0','0','0',"01","000---000-------");
-- MRS reset DLL
checkcmd('0','0','0',"00","000----1--------");
cyctr := 0;
-- Precharge all
checkcmd('0','1','0',"--","-----1----------");
-- 2 x auto refresh
checkcmd('0','0','1',"--","----------------");
checkcmd('0','0','1',"--","----------------");
-- MRS !reset DLL
checkcmd('0','0','0',"00","-------0--------");
-- EMRS EMR1 OCD default, EMRS EMR1 exit OCD cal
-- (assume OCD impedance adjust not performed)
checkcmd('0','0','0',"01","------111-------");
assert cyctr >= 200 report "Less than 200 cycles (" & tost(cyctr) & ") between DLL reset and OCD cal" severity warning;
checkcmd('0','0','0',"01","------000-------");
initdone <= true;
wait;
end process;
-----------------------------------------------------------------------------
-- Command state machine
-----------------------------------------------------------------------------
cmdp: process(ck)
subtype coldata is std_logic_vector(width-1 downto 0);
type coldata_arr is array(0 to implbanks*(2**(colbits+rowbits))-1) of coldata;
variable memdata: coldata_arr;
procedure load_srec is
file TCF : text open read_mode is fname;
variable L1: line;
variable CH : character;
variable rectype : std_logic_vector(3 downto 0);
variable recaddr : std_logic_vector(31 downto 0);
variable reclen : std_logic_vector(7 downto 0);
variable recdata : std_logic_vector(0 to 16*8-1);
variable recdatatemp : std_logic_vector(0 to 63);
variable col, coloffs, len: integer;
begin
L1:= new string'("");
while not endfile(TCF) loop
readline(TCF,L1);
if (L1'length /= 0) then
while (not (L1'length=0)) and (L1(L1'left) = ' ') loop
std.textio.read(L1,CH);
end loop;
if L1'length > 0 then
read(L1, ch);
if (ch = 'S') or (ch = 's') then
hread(L1, rectype);
hread(L1, reclen);
len := to_integer(unsigned(reclen))-1;
recaddr := (others => '0');
case rectype is
when "0001" => hread(L1, recaddr(15 downto 0)); len := len - 2;
when "0010" => hread(L1, recaddr(23 downto 0)); len := len - 3;
when "0011" => hread(L1, recaddr); len := len - 4;
when others => next;
end case;
hread(L1, recdata(0 to len*8-1));
if swap=1 then -- byte swap during srec load
for i in 0 to 7 loop
recdatatemp(0 to 7) := recdata(i*16 to i*16+7);
recdata(i*16 to i*16+7) := recdata(i*16+8 to i*16+15);
recdata(i*16+8 to i*16+15) := recdatatemp(0 to 7);
end loop;
elsif swap = 2 then
recaddr(4) := not recaddr(4);
recdatatemp := recdata(0 to 63);
recdata(0 to 63) := recdata(64 to 127);
recdata(64 to 127) := recdatatemp;
end if;
col := to_integer(unsigned(recaddr(log2(width/8)+rowbits+colbits+1 downto log2(width/8))));
coloffs := 8*to_integer(unsigned(recaddr(log2(width/8)-1 downto 0)));
while len > width/8 loop
assert coloffs=0;
memdata(col) := recdata(0 to width-1);
col := col+1;
len := len-width/8;
recdata(0 to recdata'length-width-1) := recdata(width to recdata'length-1);
end loop;
memdata(col)(width-1-coloffs downto width-coloffs-len*8) := recdata(0 to len*8-1);
end if;
end if;
end if;
end loop;
end load_srec;
variable vmr: moderegs;
type bankstate is record
openrow: integer;
opentime: time;
closetime: time;
writetime: time;
readtime: time;
autopch: integer;
pchpush: boolean;
end record;
type bankstate_arr is array(natural range <>) of bankstate;
variable banks: bankstate_arr(7 downto 0) := (others => (-1, 0 ns, 0 ns, 0 ns, 0 ns, -1, false));
type int_arr is array(natural range <>) of integer;
type dataacc is record
r,w: boolean;
col: int_arr(0 to 1);
bank: integer;
end record;
type dataacc_arr is array(natural range <>) of dataacc;
variable accpipe: dataacc_arr(0 to 9);
variable cmd: std_logic_vector(2 downto 0);
variable bank: integer;
variable colv: unsigned(a'high-1 downto 0);
variable alow: unsigned(2 downto 0);
variable col: integer;
variable prev_re, re: time;
variable blen: integer;
variable lastref: time := 0 ns;
variable i, al, cl, wrap: integer;
variable b: boolean;
variable mrscount: integer := 0;
variable loaded: boolean := false;
procedure checktime(got, exp: time; gt: boolean; req: string) is
begin
assert (got + deltat > exp and gt) or (got-deltat < exp and not gt)
report (req & " violation, got: " & tost(got/(1 ps)) & " ps, exp: " & tost(exp/(1 ps)) & "ps")
severity warning;
end checktime;
begin
if rising_edge(ck) then
-- Update pipe regs
prev_re := re;
re := now;
accpipe(1 to accpipe'high) := accpipe(0 to accpipe'high-1);
accpipe(0).r:=false; accpipe(0).w:=false;
-- Parse MR fields
cmd := rasn & casn & wen;
if is_x(vmr.caslat) then cl:=0; else cl:=to_integer(unsigned(vmr.caslat)); end if;
if cl<2 or cl>6 then cl:=0; end if;
if is_x(vmr.al) then al:=0; else al:=to_integer(unsigned(vmr.al)); end if;
if al>5 then al:=0; end if;
if is_x(vmr.wr) then wrap:=0; else wrap:=1+to_integer(unsigned(vmr.wr)); end if;
if wrap<2 or wrap>6 then wrap:=0; end if;
-- Checks for all-bank commands
if mrscount > 0 then
mrscount := mrscount-1;
assert cke='1' and (csn='1' or cmd="111") report "tMRS violation!" severity warning;
end if;
if cke='1' and csn='0' and cmd/="111" then
checktime(now-lastref, tRFC(density), true, "tRFC");
end if;
-- Main command handler
if cke='1' and csn='0' then
case cmd is
when "111" => -- NOP
when "011" => -- RAS
assert initdone report "Opening row before init sequence done!" severity warning;
bank := to_integer(unsigned(ba));
assert banks(bank).openrow < 0
report "Row already open" severity warning;
checktime(now-banks(bank).closetime, tRP(speedbin), true, "tRP");
for x in 0 to 7 loop
checktime(now-banks(x).opentime, tRRD(pagesize), true, "tRRD");
end loop;
banks(bank).openrow := to_integer(unsigned(a(rowbits-1 downto 0)));
banks(bank).opentime := now;
when "101" | "100" => -- Read/Write
bank := to_integer(unsigned(ba));
-- Get additive latency
i := to_integer(unsigned(vmr.al));
assert banks(bank).openrow >= 0
report "Row not open" severity error;
checktime(now-banks(bank).opentime+al*(re-prev_re), tRCD(speedbin), true, "tRCD");
-- Allow interrupting read in case of middle of BL8 burst only
if (accpipe(3).r and accpipe(2).r and
not (accpipe(1).r or accpipe(1).w or accpipe(0).r or accpipe(0).w)) then
accpipe(3).r := false;
accpipe(2).r := false;
end if;
for x in 0 to 3 loop
assert not accpipe(x).r and not accpipe(x).w;
end loop;
if cmd(0)='1' then accpipe(3).r:=true; else accpipe(3).w:=true; end if;
colv := unsigned(std_logic_vector'(a(a'high downto 11) & a(9 downto 0)));
case vmr.blen is
when "010" => blen := 4;
when "011" => blen := 8;
when others => assert false report "Invalid burst length setting in MR!" severity error;
end case;
alow := unsigned(a(2 downto 0));
for x in 0 to blen-1 loop
accpipe(3-x/2).bank := bank;
if cmd(0)='1' then accpipe(3-x/2).r:=true; else accpipe(3-x/2).w:=true; end if;
if vmr.bt='0' then -- Sequential
colv(log2(blen)-1 downto 0) := alow(log2(blen)-1 downto 0) + x;
else -- Interleaved
colv(log2(blen)-1 downto 0) := alow(log2(blen)-1 downto 0) xor to_unsigned(x,log2(blen));
end if;
col := to_integer(unsigned(ba))*(2**(colbits+rowbits)) +
banks(bank).openrow * (2**colbits) + to_integer(colv(colbits-1 downto 0));
accpipe(3-x/2).col(x mod 2) := col;
end loop;
-- Auto precharge
if a(10)='1' then
if cmd(0)='1' then
banks(bank).autopch := al+blen/2;
else
banks(bank).autopch := cl+al-1+blen/2+wrap;
end if;
banks(bank).pchpush := true;
end if;
when "110" => -- Reserved (Burst terminate on DDR1)
assert false report "Invalid command RAS=1 CAS=1 WE=0" severity warning;
when "010" => -- Precharge
if a(10)='0' then bank := to_integer(unsigned(ba)); else bank:=0; end if;
for x in 3 downto 0 loop -- FIXME potential window which isn't checked if AL>0
assert (not (accpipe(x).r or accpipe(x).w)) or (a(10)='0' and bank/=accpipe(x).bank)
report "Precharging bank with access in progress"
severity warning;
end loop;
for x in 0 to (2**babits)-1 loop
if a(10)='1' or ba=std_logic_vector(to_unsigned(x,babits)) then
assert banks(x).autopch<0
report "Precharging bank that is auto-precharged!" severity note;
assert a(10)='1' or banks(x).openrow >= 0
report "Precharging single bank that is in idle state!" severity note;
banks(x).autopch := 0; -- Handled below case statement
banks(x).pchpush := false;
end if;
end loop;
when "001" => -- Auto refresh
for x in 0 to 7 loop
assert banks(x).openrow < 0
report "Bank in wrong state for auto refresh!" severity warning;
checktime(now-banks(x).closetime, tRP(speedbin), true, "tRP");
end loop;
lastref := now;
when "000" => -- MRS
for x in 0 to 7 loop
checktime(now-banks(x).closetime, tRP(speedbin), true, "tRP");
end loop;
bank := to_integer(unsigned(ba));
case bank is
when 0 =>
vmr.pd := a(12);
vmr.wr := a(11 downto 9);
vmr.dllres := a(8);
vmr.tm := a(7);
vmr.caslat := a(6 downto 4);
vmr.bt := a(3);
vmr.blen := a(2 downto 0);
when 1 =>
vmr.qoff := a(12);
vmr.rdqsen := a(11);
vmr.dqsndis := a(10);
vmr.ocdprog := a(9 downto 7);
vmr.al := a(5 downto 3);
vmr.rtt := a(6) & a(2);
vmr.ds := a(1);
vmr.dlldis := a(0);
when 2 =>
vmr.srf := a(7);
vmr.dccen := a(3);
vmr.pasr := a(2 downto 0);
when 3 =>
vmr.emr3 := a;
when others =>
assert false report ("MRS to invalid bank addr: " & std_logic'image(ba(1)) & std_logic'image(ba(0))) severity warning;
end case;
mrscount := tMRD_ck-1;
when others =>
assert false report ("Invalid command: " & std_logic'image(rasn) & std_logic'image(casn) & std_logic'image(wen)) severity warning;
end case;
end if;
-- Manual or auto precharge handling
for x in 0 to 7 loop
if banks(x).autopch=0 then
if banks(x).pchpush and (now-banks(x).opentime-deltat) < tRAS(speedbin) then
-- Auto delay auto-precharge to satisfy tRAS/tRC
banks(x).autopch := banks(x).autopch+1;
elsif banks(x).pchpush and (now-banks(x).readtime-deltat) < tRTP then
-- Auto delay auto-precharge to satisfy tRTP
banks(x).autopch := banks(x).autopch+1;
else
checktime(now-banks(x).writetime, tWR, true, "tWR");
checktime(now-banks(x).opentime, tRAS(speedbin), true, "tRAS");
checktime(now-banks(x).readtime, tRTP, true, "tRTP");
banks(x).openrow := -1;
banks(x).closetime := now;
end if;
end if;
if banks(x).autopch >= 0 then
banks(x).autopch := banks(x).autopch - 1;
end if;
end loop;
-- Read/write management
if not loaded and lddelay < now and (ldguard=0 or doload='1') then
load_srec;
loaded := true;
end if;
if accpipe(2+cl+al).r then
assert cl>1 report "Incorrect CL setting!" severity warning;
read_en <= true;
-- print("Reading from col " & tost(accpipe(2+i).col(0)) & " and " & tost(accpipe(2+i).col(1)));
-- col0 <= accpipe(2+i).col(0); col1 <= accpipe(2+i).col(1);
read_data <= memdata(accpipe(2+cl+al).col(0)) & memdata(accpipe(2+cl+al).col(1));
else
read_en <= false;
end if;
-- tRTP is counted from read command + AL for BL4, read command + AL + 2
-- for BL8. This check covers both cases by writing readtime on the next-to-last
-- transfer.
if accpipe(3+al).r and accpipe(2+al).r and accpipe(3+al).bank=accpipe(2+al).bank then
banks(accpipe(2+al).bank).readtime := now;
end if;
write_en <= accpipe(1+cl+al).w or accpipe(2+cl+al).w;
if accpipe(3+cl+al).w then
assert not is_x(write_mask) report "Write error!";
for x in 0 to 1 loop
for b in width/8-1 downto 0 loop
if write_mask((1-x)*width/8+b)='0' then
memdata(accpipe(3+cl+al).col(x))(8*b+7 downto 8*b) :=
write_data( (1-x)*width+b*8+7 downto (1-x)*width+b*8);
end if;
end loop;
end loop;
banks(accpipe(3+cl+al).bank).writetime := now;
end if;
end if;
mr <= vmr;
end process;
-----------------------------------------------------------------------------
-- DQS/DQ handling and data sampling process
-----------------------------------------------------------------------------
dqproc: process
variable rdata: std_logic_vector(2*width-1 downto 0);
variable hdata: std_logic_vector(width-1 downto 0);
variable hmask: std_logic_vector(width/8-1 downto 0);
variable prevdqs: std_logic_vector(width/8-1 downto 0);
begin
dq <= (others => 'Z');
dqs <= (others => 'Z');
dqsn <= (others => 'Z');
wait until read_en or write_en;
assert not (read_en and write_en);
if read_en then
dqs <= (others => '0');
dqsn <= (others => '1');
wait until falling_edge(ck);
while read_en loop
rdata := read_data;
wait until rising_edge(ck);
dqs <= (others => '1');
dqsn <= (others => '0');
dq <= rdata(2*width-1 downto width);
wait until falling_edge(ck);
dqs <= (others => '0');
dqsn <= (others => '1');
dq <= rdata(width-1 downto 0);
end loop;
wait until rising_edge(ck);
else
wait until falling_edge(ck);
assert (to_X01(dqs)=(dqs'range => '0')) or ((to_X01(dqs)=(dqs'range => '1')) and (to_X01(dm)=(dm'range => '1') or dm=(dm'range => 'Z')));
while write_en loop
prevdqs := to_X01(dqs);
wait until to_X01(dqs) /= prevdqs or not write_en or rising_edge(ck);
if rising_edge(ck) then
write_data <= (others => 'X');
write_mask <= (others => 'X');
end if;
for x in dqs'range loop
if prevdqs(x)='0' and to_X01(dqs(x))='1' then
hdata(8*x+7 downto 8*x) := dq(8*x+7 downto 8*x);
hmask(x) := dm(x);
elsif prevdqs(x)='1' and to_X01(dqs(x))='0' then
write_data(width+8*x+7 downto width+8*x) <= hdata(8*x+7 downto 8*x);
write_data(8*x+7 downto 8*x) <= dq(8*x+7 downto 8*x);
write_mask(width/8+x) <= hmask(x);
write_mask(x) <= dm(x);
end if;
end loop;
end loop;
end if;
end process;
end;
-- pragma translate_on
| gpl-3.0 |
EliasLuiz/TCC | Leon3/lib/gaisler/misc/gptimer.vhd | 1 | 21915 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: gptimer
-- File: gptimer.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: This unit implemets a set of general-purpose timers with a
-- common prescaler. Then number of timers and the width of
-- the timers is propgrammable through generics
--
-- Revision 1 of this core merges functionality of the GRTIMET unit:
--
-- This unit also implements the use of an external clock source for the
-- timers.
--
-- This unit also implements a latching register for each timer, latching the
-- timer value on the occurence of an interrupt on the apbi.priq input. The
-- interrupt selection in possible via a mask register.
--
-- This unit also implements loading of all timers on the event of a selected
-- incoming interrupt.
--
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.config_types.all;
use grlib.config.all;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library gaisler;
use gaisler.misc.all;
--pragma translate_off
use std.textio.all;
--pragma translate_on
entity gptimer is
generic (
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
pirq : integer := 0;
sepirq : integer := 0; -- use separate interrupts for each timer
sbits : integer := 16; -- scaler bits
ntimers : integer range 1 to 7 := 1; -- number of timers
nbits : integer := 32; -- timer bits
wdog : integer := 0;
ewdogen : integer := 0;
glatch : integer := 0;
gextclk : integer := 0;
gset : integer := 0;
gelatch : integer range 0 to 2 := 0;
wdogwin : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
gpti : in gptimer_in_type;
gpto : out gptimer_out_type
);
end;
architecture rtl of gptimer is
constant REVISION : integer := 1;
constant pconfig : apb_config_type := (
0 => ahb_device_reg (VENDOR_GAISLER, GAISLER_GPTIMER, 0, REVISION, pirq),
1 => apb_iobar(paddr, pmask));
type timer_reg is record
enable : std_ulogic; -- enable counter
load : std_ulogic; -- load counter
restart : std_ulogic; -- restart counter
irqpen : std_ulogic; -- interrupt pending
irqen : std_ulogic; -- interrupt enable
irq : std_ulogic; -- interrupt pulse
chain : std_ulogic; -- chain with previous timer
value : std_logic_vector(nbits-1 downto 0);
reload : std_logic_vector(nbits-1 downto 0);
latch : std_logic_vector(glatch*(nbits-1) downto 0);
end record;
type timer_reg_vector is array (Natural range <> ) of timer_reg;
constant TBITS : integer := log2x(ntimers+1);
type registers is record
scaler : std_logic_vector(sbits-1 downto 0);
reload : std_logic_vector(sbits-1 downto 0);
tick : std_ulogic;
tsel : integer range 0 to ntimers;
timers : timer_reg_vector(1 to ntimers);
dishlt : std_ulogic;
wdogn : std_ulogic;
wdog : std_ulogic;
wdogdis : std_ulogic;
wdognmi : std_ulogic;
wdogwc : std_logic_vector(15 downto 0);
wdogwcr : std_logic_vector(15 downto 0);
end record;
type registers2 is record
setdis : std_ulogic;
latchdis : std_ulogic;
elatchen : std_ulogic;
latchsel : std_logic_vector(NAHBIRQ-1 downto 0);
latchen : std_ulogic;
latchdel : std_ulogic;
extclken : std_ulogic;
extclk : std_logic_vector(2 downto 0);
seten : std_ulogic;
setdel : std_ulogic;
end record;
constant NMI : integer := 15;
constant RESET_ALL : boolean := GRLIB_CONFIG_ARRAY(grlib_sync_reset_enable_all) = 1;
function RESVAL_FUNC return registers is
variable vres : registers;
begin
vres.scaler := (others => '1');
vres.reload := (others => '1');
vres.tick := '0';
vres.tsel := 0;
for i in 1 to ntimers loop
vres.timers(i).enable := '0';
vres.timers(i).load := '0';
vres.timers(i).restart := '0';
vres.timers(i).irqpen := '0';
vres.timers(i).irqen := '0';
vres.timers(i).irq := '0';
vres.timers(i).chain := '0';
vres.timers(i).value := (others => '0');
vres.timers(i).reload := (others => '0');
vres.timers(i).latch := (others => '0');
end loop;
if wdog /= 0 then
vres.timers(ntimers).enable := '1'; -- May be overriden by ewdogen
vres.timers(ntimers).load := '1';
vres.timers(ntimers).reload := conv_std_logic_vector(wdog, nbits);
vres.timers(ntimers).irqen := '1';
end if;
vres.dishlt := '0';
vres.wdogn := '1';
vres.wdog := '0';
vres.wdogdis := '0';
vres.wdognmi := '0';
vres.wdogwc := (others => '0');
vres.wdogwcr := (others => '0');
return vres;
end function RESVAL_FUNC;
constant RESVAL : registers := RESVAL_FUNC;
constant RESVAL2 : registers2 := (
setdis => '0',
latchdis => '0',
elatchen => '0',
latchsel => (others => '0'),
latchen => '0',
latchdel => '0',
extclken => '0',
extclk => (others => '0'),
seten => '0',
setdel => '0');
signal r, rin : registers;
signal r2, rin2 : registers2;
begin
comb : process(rst, r, r2, apbi, gpti)
variable scaler : std_logic_vector(sbits downto 0);
variable readdata, timer1 : std_logic_vector(31 downto 0);
variable res, addin : std_logic_vector(nbits-1 downto 0);
variable v : registers;
variable z : std_ulogic;
variable vtimers : timer_reg_vector(0 to ntimers);
variable xirq : std_logic_vector(NAHBIRQ-1 downto 0);
variable nirq : std_logic_vector(0 to ntimers-1);
variable tick : std_logic_vector(1 to 7);
variable latch : std_ulogic;
variable latchval : std_logic_vector(NAHBIRQ-1 downto 0);
variable latchd : std_ulogic;
variable v2 : registers2;
variable wdogwc : std_logic_vector(r.wdogwc'left+1 downto 0);
variable timeren : std_logic;
begin
v := r; v2 := r2; v.tick := '0'; tick := (others => '0'); latch := '0';
latchval := apbi.pirq; latchd := '0';
vtimers(0) := ('0', '0', '0', '0', '0', '0', '0',
zero32(nbits-1 downto 0), zero32(nbits-1 downto 0),
zero32(glatch*(nbits-1) downto 0));
vtimers(1 to ntimers) := r.timers; xirq := (others => '0');
for i in 1 to ntimers loop
v.timers(i).irq := '0'; v.timers(i).load := '0';
tick(i) := r.timers(i).irq;
end loop;
v.wdog := r.timers(ntimers).irqpen and not r.wdogdis;
v.wdogn := not v.wdog;
-- wdog timer window counter
if wdogwin /= 0 and wdog /= 0 then
wdogwc := ('0' & r.wdogwc) - 1; -- decrement scaler
if wdogwc(wdogwc'left) = '0' then
v.wdogwc := wdogwc(v.wdogwc'range);
end if;
else
wdogwc := (others => '0');
end if;
-- scaler operation
timeren := '0'; -- set if any of the timers are enabled
for i in 1 to ntimers loop timeren := timeren or r.timers(i).enable; end loop;
scaler := ('0' & r.scaler) - 1; -- decrement scaler
if gextclk = 1 then -- optional external timer clock
v2.extclk := r2.extclk(1 downto 0) & gpti.extclk;
end if;
if ((gextclk=0) or (gextclk=1 and r2.extclken='0') or
(gextclk=1 and r2.extclken='1' and r2.extclk(2 downto 1) = "01")) then
if (not gpti.dhalt or r.dishlt) = '1' -- halt timers in debug mode.
and timeren = '1' then -- scaler is halted when all timers are disabled
if (scaler(sbits) = '1') then
v.scaler := r.reload; v.tick := '1'; -- reload scaler
else v.scaler := scaler(sbits-1 downto 0); end if;
end if;
end if;
-- timer operation
if (r.tick = '1') or (r.tsel /= 0) then
if r.tsel = ntimers then v.tsel := 0;
else v.tsel := r.tsel + 1; end if;
end if;
res := vtimers(r.tsel).value - 1; -- decrement selected timer
if (res(nbits-1) = '1') and ((vtimers(r.tsel).value(nbits-1) = '0'))
then z := '1'; else z := '0'; end if; -- undeflow detect
-- update corresponding register and generate irq
for i in 1 to ntimers-1 loop nirq(i) := r.timers(i).irq; end loop;
nirq(0) := r.timers(ntimers).irq;
for i in 1 to ntimers loop
if i = r.tsel then
if (r.timers(i).enable = '1') and
(((r.timers(i).chain and nirq(i-1)) or not (r.timers(i).chain)) = '1')
then
v.timers(i).irq := z and not r.timers(i).load;
if (v.timers(i).irq and r.timers(i).irqen) = '1' then
v.timers(i).irqpen := '1';
end if;
v.timers(i).value := res;
if (z and not r.timers(i).load) = '1' then
v.timers(i).enable := r.timers(i).restart;
if r.timers(i).restart = '1' then
v.timers(i).value := r.timers(i).reload;
end if;
end if;
end if;
end if;
if r.timers(i).load = '1' then
v.timers(i).value := r.timers(i).reload;
if (i = ntimers) and wdogwin /= 0 and wdog /= 0 then
v.wdogwc := r.wdogwcr;
if wdogwc(wdogwc'left) = '0' then
v.timers(i).irq := '1';
v.timers(i).irqpen := '1';
end if;
end if;
end if;
end loop;
-- timer external set
if gset = 1 then
if gelatch /= 0 and r2.elatchen = '1' then
latchval := gpti.latchv;
end if;
if NAHBIRQ <= 32 then
for i in NAHBIRQ-1 downto 0 loop
latch := latch or (v2.latchsel(i) and latchval(i));
if gelatch = 2 then latchd := latchd or (v2.latchsel(i) and gpti.latchd(i)); end if;
end loop;
else
for i in 31 downto 0 loop
latch := latch or (v2.latchsel(i) and latchval(i));
if gelatch = 2 then latchd := latchd or (v2.latchsel(i) and gpti.latchd(i)); end if;
end loop;
end if;
if gelatch = 2 and (r2.seten = '1' and r2.elatchen = '1') then
if latchd = '1' then
v2.setdis := '1';
end if;
if r2.setdis = '1' and r.tsel = 0 then
v2.setdis := '0'; v2.seten := '0'; v2.setdel := '0';
end if;
end if;
if (latch='1' and r2.seten='1' and r.tsel = 0) or
(r2.setdel = '1' and r2.seten='1' and r.tsel = 0) then
for i in 1 to ntimers loop
v.timers(i).value := r.timers(i).reload;
end loop;
v2.setdel := '0';
if gelatch < 2 or (gelatch = 2 and (r2.elatchen = '0' or v2.setdis = '1')) then
v2.seten := '0';
if gelatch = 2 then v2.setdis := '0'; end if;
end if;
elsif latch='1' and r2.seten='1' and r.tsel /= 0 then
v2.setdel := '1';
end if;
end if;
if sepirq /= 0 then
for i in 1 to ntimers loop
xirq(i-1+pirq) := r.timers(i).irq and r.timers(i).irqen;
end loop;
else
for i in 1 to ntimers loop
xirq(pirq) := xirq(pirq) or (r.timers(i).irq and r.timers(i).irqen);
end loop;
end if;
if wdog /= 0 then
if (r.wdognmi and r.timers(ntimers).irq and r.timers(ntimers).irqen) = '1' then
xirq(NMI) := '1';
end if;
end if;
-- read registers
readdata := (others => '0');
case apbi.paddr(6 downto 2) is
when "00000" => readdata(sbits-1 downto 0) := r.scaler;
when "00001" => readdata(sbits-1 downto 0) := r.reload;
when "00010" =>
readdata(2 downto 0) := conv_std_logic_vector(ntimers, 3) ;
readdata(7 downto 3) := conv_std_logic_vector(pirq, 5) ;
if (sepirq /= 0) then readdata(8) := '1'; end if;
readdata(9) := r.dishlt;
if gextclk = 1 then readdata(10) := r2.extclken; end if;
if glatch = 1 then readdata(11) := r2.latchen; end if;
if gset = 1 then readdata(12) := r2.seten; end if;
if gelatch /= 0 then readdata(13) := r2.elatchen; end if;
when "00011" =>
if glatch = 1 then
if NAHBIRQ <= 32 then
for i in NAHBIRQ-1 downto 0 loop
readdata(i) := r2.latchsel(i);
end loop;
else
for i in 31 downto 0 loop
readdata(i) := r2.latchsel(i);
end loop;
end if;
end if;
when others =>
for i in 1 to ntimers loop
if conv_integer(apbi.paddr(6 downto 4)) = i then
case apbi.paddr(3 downto 2) is
when "00" => readdata(nbits-1 downto 0) := r.timers(i).value;
when "01" => readdata(nbits-1 downto 0) := r.timers(i).reload;
when "10" =>
if wdog /= 0 and i = ntimers then
if wdogwin /= 0 then
readdata(31 downto 16) := r.wdogwcr;
end if;
readdata(8 downto 7) := r.wdogdis & r.wdognmi;
end if;
readdata(6 downto 0) :=
gpti.dhalt & r.timers(i).chain &
r.timers(i).irqpen & r.timers(i).irqen & r.timers(i).load &
r.timers(i).restart & r.timers(i).enable;
when "11" =>
if glatch = 1 then
readdata(glatch*(nbits-1) downto 0) := r.timers(i).latch;
end if;
when others =>
end case;
end if;
end loop;
end case;
-- write registers
if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
case apbi.paddr(6 downto 2) is
when "00000" => v.scaler := apbi.pwdata(sbits-1 downto 0);
when "00001" => v.reload := apbi.pwdata(sbits-1 downto 0);
v.scaler := apbi.pwdata(sbits-1 downto 0);
when "00010" => v.dishlt := apbi.pwdata(9);
if gextclk = 1 then v2.extclken := apbi.pwdata(10); end if;
if glatch = 1 then v2.latchen := apbi.pwdata(11); end if;
if gset = 1 then v2.seten := apbi.pwdata(12); end if;
if gelatch /= 0 then v2.elatchen := apbi.pwdata(13); end if;
for i in 1 to ntimers loop
v.timers(i).enable := r.timers(i).enable or apbi.pwdata(15+i);
end loop;
when "00011" =>
if glatch=1 then
if NAHBIRQ <= 32 then
for i in NAHBIRQ-1 downto 0 loop
v2.latchsel(i) := apbi.pwdata(i);
end loop;
else
for i in 31 downto 0 loop
v2.latchsel(i) := apbi.pwdata(i);
end loop;
end if;
end if;
when others =>
for i in 1 to ntimers loop
if conv_integer(apbi.paddr(6 downto 4)) = i then
case apbi.paddr(3 downto 2) is
when "00" => v.timers(i).value := apbi.pwdata(nbits-1 downto 0);
when "01" => v.timers(i).reload := apbi.pwdata(nbits-1 downto 0);
when "10" => if wdog /= 0 and i = ntimers then
if wdogwin /= 0 then
v.wdogwcr := apbi.pwdata(31 downto 16);
end if;
v.wdogdis := apbi.pwdata(8);
v.wdognmi := apbi.pwdata(7);
end if;
v.timers(i).chain := apbi.pwdata(5);
v.timers(i).irqpen := v.timers(i).irqpen and not apbi.pwdata(4);
v.timers(i).irqen := apbi.pwdata(3);
v.timers(i).load := apbi.pwdata(2);
v.timers(i).restart := apbi.pwdata(1);
v.timers(i).enable := apbi.pwdata(0);
when others =>
end case;
end if;
end loop;
end case;
end if;
-- timer latches
if glatch=1 then
latch := '0'; latchd := '0';
if gelatch /= 0 and r2.elatchen = '1' then
latchval := gpti.latchv;
end if;
if NAHBIRQ <= 32 then
for i in NAHBIRQ-1 downto 0 loop
latch := latch or (v2.latchsel(i) and latchval(i));
if gelatch = 2 then latchd := latchd or (v2.latchsel(i) and gpti.latchd(i)); end if;
end loop;
else
for i in 31 downto 0 loop
latch := latch or (v2.latchsel(i) and latchval(i));
if gelatch = 2 then latchd := latchd or (v2.latchsel(i) and gpti.latchd(i)); end if;
end loop;
end if;
if gelatch /= 0 and (r2.latchen = '1' and r2.elatchen = '1') then
if latchd = '1' then
v2.latchdis := '1';
end if;
if r2.latchdis = '1' and r.tsel = 0 then
v2.latchdis := '0'; v2.latchen := '0'; v2.latchdel := '0';
end if;
end if;
if ((latch='1' and r2.latchen='1' and r.tsel = 0) or
(r2.latchdel = '1' and r2.latchen='1' and r.tsel = 0)) then
for i in 1 to ntimers loop
v.timers(i).latch := r.timers(i).value(glatch*(nbits-1) downto 0);
end loop;
v2.latchdel := '0';
if gelatch < 2 or (gelatch = 2 and (r2.elatchen = '0' or v2.latchdis = '1')) then
v2.latchen := '0';
if gelatch = 2 then v2.latchdis := '0'; end if;
end if;
elsif latch='1' and r2.latchen='1' and r.tsel /= 0 then
v2.latchdel := '1';
end if;
end if;
-- reset operation
if (not RESET_ALL) and (rst = '0') then
for i in 1 to ntimers loop
v.timers(i).enable := RESVAL.timers(i).enable;
v.timers(i).irqen := RESVAL.timers(i).irqen;
v.timers(i).irqpen := RESVAL.timers(i).irqpen;
v.timers(i).irq := RESVAL.timers(i).irq;
end loop;
v.scaler := RESVAL.scaler; v.reload := RESVAL.reload;
v.tsel := RESVAL.tsel; v.dishlt := RESVAL.dishlt;
v.timers(ntimers).irq := RESVAL.timers(ntimers).irq;
if (wdog /= 0) then
if ewdogen /= 0 then v.timers(ntimers).enable := gpti.wdogen;
else v.timers(ntimers).enable := RESVAL.timers(ntimers).enable; end if;
v.timers(ntimers).load := RESVAL.timers(ntimers).load;
v.timers(ntimers).reload := RESVAL.timers(ntimers).reload;
v.timers(ntimers).chain := RESVAL.timers(ntimers).chain;
v.timers(ntimers).irqen := RESVAL.timers(ntimers).irqen;
v.timers(ntimers).irqpen := RESVAL.timers(ntimers).irqpen;
v.timers(ntimers).restart := RESVAL.timers(ntimers).restart;
end if;
v.wdogdis := RESVAL.wdogdis; v.wdognmi := RESVAL.wdognmi;
v.wdogwcr := RESVAL.wdogwcr;
if glatch = 1 then
for i in 1 to ntimers loop v.timers(i).latch := RESVAL.timers(i).latch; end loop;
if gelatch /= 0 then v2.elatchen := RESVAL2.elatchen; end if;
if gelatch = 2 then v2.setdis := '0'; v2.latchdis := '0'; end if;
v2.latchen := RESVAL2.latchen; v2.latchdel := RESVAL2.latchdel;
v2.latchsel := RESVAL2.latchsel;
end if;
if gextclk = 1 then
v2.extclken := RESVAL2.extclken;
v2.extclk := RESVAL2.extclk;
end if;
if gset = 1 then v2.seten := RESVAL2.seten; v2.setdel := RESVAL2.setdel; end if;
end if;
if wdog = 0 then v.wdogdis := '0'; v.wdognmi := '0'; end if;
if wdogwin = 0 then v.wdogwc := (others => '0'); v.wdogwcr := (others => '0'); end if;
if glatch = 0 then
for i in 1 to ntimers loop v.timers(i).latch := (others => '0'); end loop;
v2.latchen := '0'; v2.latchdel := '0'; v2.latchsel := (others => '0');
end if;
if glatch = 0 or gelatch = 0 then v2.elatchen := '0'; end if;
if glatch = 0 or gelatch < 2 then v2.latchdis := '0'; v2.setdis := '0'; end if;
if gextclk = 0 then v2.extclken := '0'; v2.extclk := (others => '0'); end if;
if gset = 0 then v2.seten := '0'; v2.setdel := '0'; end if;
timer1 := (others => '0'); timer1(nbits-1 downto 0) := r.timers(1).value;
rin <= v; rin2 <= v2;
apbo.prdata <= readdata; -- drive apb read bus
apbo.pirq <= xirq;
apbo.pindex <= pindex;
gpto.tick <= r.tick & tick;
gpto.timer1 <= timer1; -- output timer1 value for debugging
gpto.wdogn <= r.wdogn;
gpto.wdog <= r.wdog;
end process;
apbo.pconfig <= pconfig;
-- registers
regs : process(clk)
begin
if rising_edge(clk) then
r <= rin; r2 <= rin2;
if RESET_ALL and rst = '0' then
r <= RESVAL; r2 <= RESVAL2;
if wdog /= 0 and ewdogen /= 0 then
r.timers(ntimers).enable <= gpti.wdogen;
end if;
end if;
end if;
end process;
-- boot message
-- pragma translate_off
bootmsg : report_version
generic map ("gptimer" & tost(pindex) &
": Timer Unit rev " & tost(REVISION) &
", " & tost(sbits) & "-bit scaler, " & tost(ntimers) &
" " & tost(nbits) & "-bit timers" & ", irq " & tost(pirq));
-- pragma translate_on
end;
| gpl-3.0 |
EliasLuiz/TCC | Leon3/lib/cypress/ssram/components.vhd | 1 | 6171 | ----------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2004 GAISLER RESEARCH
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- See the file COPYING for the full details of the license.
--
-----------------------------------------------------------------------------
-- Package: components
-- File: components.vhd
-- Author: Jiri Gaisler, Gaisler Research
-- Description: Component declaration of Cypress sync-sram
------------------------------------------------------------------------------
-- pragma translate_off
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
package components is
component cy7c1354
generic (
fname : string := "ram.srec"; -- File to read from
-- Constant parameters
addr_bits : INTEGER := 18;
data_bits : INTEGER := 36;
-- Timing parameters for -5 (225 Mhz)
tCYC : TIME := 4.4 ns;
tCH : TIME := 1.8 ns;
tCL : TIME := 1.8 ns;
tCO : TIME := 2.8 ns;
tAS : TIME := 1.4 ns;
tCENS : TIME := 1.4 ns;
tWES : TIME := 1.4 ns;
tDS : TIME := 1.4 ns;
tAH : TIME := 0.4 ns;
tCENH : TIME := 0.4 ns;
tWEH : TIME := 0.4 ns;
tDH : TIME := 0.4 ns
-- Timing parameters for -5 (200 Mhz)
--tCYC : TIME := 5.0 ns;
--tCH : TIME := 2.0 ns;
--tCL : TIME := 2.0 ns;
--tCO : TIME := 3.2 ns;
--tAS : TIME := 1.5 ns;
--tCENS : TIME := 1.5 ns;
--tWES : TIME := 1.5 ns;
--tDS : TIME := 1.5 ns;
--tAH : TIME := 0.5 ns;
--tCENH : TIME := 0.5 ns;
--tWEH : TIME := 0.5 ns;
--tDH : TIME := 0.5 ns
-- Timing parameters for -5 (166 Mhz)
--tCYC : TIME := 6.0 ns;
--tCH : TIME := 2.4 ns;
--tCL : TIME := 2.4 ns;
--tCO : TIME := 3.5 ns;
--tAS : TIME := 1.5 ns;
--tCENS : TIME := 1.5 ns;
--tWES : TIME := 1.5 ns;
--tDS : TIME := 1.5 ns;
--tAH : TIME := 0.5 ns;
--tCENH : TIME := 0.5 ns;
--tWEH : TIME := 0.5 ns;
--tDH : TIME := 0.5 ns
);
-- Port Declarations
PORT (
Dq : INOUT STD_LOGIC_VECTOR ((data_bits - 1) DOWNTO 0); -- Data I/O
Addr : IN STD_LOGIC_VECTOR ((addr_bits - 1) DOWNTO 0); -- Address
Mode : IN STD_LOGIC := '1'; -- Burst Mode
Clk : IN STD_LOGIC; -- Clk
CEN_n : IN STD_LOGIC; -- CEN#
AdvLd_n : IN STD_LOGIC; -- Adv/Ld#
Bwa_n : IN STD_LOGIC; -- Bwa#
Bwb_n : IN STD_LOGIC; -- BWb#
Bwc_n : IN STD_LOGIC; -- Bwc#
Bwd_n : IN STD_LOGIC; -- BWd#
Rw_n : IN STD_LOGIC; -- RW#
Oe_n : IN STD_LOGIC; -- OE#
Ce1_n : IN STD_LOGIC; -- CE1#
Ce2 : IN STD_LOGIC; -- CE2
Ce3_n : IN STD_LOGIC; -- CE3#
Zz : IN STD_LOGIC -- Snooze Mode
);
end component;
component CY7C1380D
GENERIC (
fname : string := "ram.srec"; -- File to read from
-- Constant Parameters
addr_bits : INTEGER := 19; -- This is external address
data_bits : INTEGER := 36;
--Clock timings for 250Mhz
Cyp_tCO : TIME := 2.6 ns; -- Data Output Valid After CLK Rise
Cyp_tCYC : TIME := 4.0 ns; -- Clock cycle time
Cyp_tCH : TIME := 1.7 ns; -- Clock HIGH time
Cyp_tCL : TIME := 1.7 ns; -- Clock LOW time
Cyp_tCHZ : TIME := 2.6 ns; -- Clock to High-Z
Cyp_tCLZ : TIME := 1.0 ns; -- Clock to Low-Z
Cyp_tOEHZ : TIME := 2.6 ns; -- OE# HIGH to Output High-Z
Cyp_tOELZ : TIME := 0.0 ns; -- OE# LOW to Output Low-Z
Cyp_tOEV : TIME := 2.6 ns; -- OE# LOW to Output Valid
Cyp_tAS : TIME := 1.2 ns; -- Address Set-up Before CLK Rise
Cyp_tADS : TIME := 1.2 ns; -- ADSC#, ADSP# Set-up Before CLK Rise
Cyp_tADVS : TIME := 1.2 ns; -- ADV# Set-up Before CLK Rise
Cyp_tWES : TIME := 1.2 ns; -- BWx#, GW#, BWE# Set-up Before CLK Rise
Cyp_tDS : TIME := 1.2 ns; -- Data Input Set-up Before CLK Rise
Cyp_tCES : TIME := 1.2 ns; -- Chip Enable Set-up
Cyp_tAH : TIME := 0.3 ns; -- Address Hold After CLK Rise
Cyp_tADH : TIME := 0.3 ns; -- ADSC#, ADSP# Hold After CLK Rise
Cyp_tADVH : TIME := 0.3 ns; -- ADV# Hold After CLK Rise
Cyp_tWEH : TIME := 0.3 ns; -- BWx#, GW#, BWE# Hold After CLK Rise
Cyp_tDH : TIME := 0.3 ns; -- Data Input Hold After CLK Rise
Cyp_tCEH : TIME := 0.3 ns -- Chip Enable Hold After CLK Rise
);
PORT (iZZ : IN STD_LOGIC;
iMode : IN STD_LOGIC;
iADDR : IN STD_LOGIC_VECTOR ((addr_bits -1) downto 0);
inGW : IN STD_LOGIC;
inBWE : IN STD_LOGIC;
inBWd : IN STD_LOGIC;
inBWc : IN STD_LOGIC;
inBWb : IN STD_LOGIC;
inBWa : IN STD_LOGIC;
inCE1 : IN STD_LOGIC;
iCE2 : IN STD_LOGIC;
inCE3 : IN STD_LOGIC;
inADSP : IN STD_LOGIC;
inADSC : IN STD_LOGIC;
inADV : IN STD_LOGIC;
inOE : IN STD_LOGIC;
ioDQ : INOUT STD_LOGIC_VECTOR ((data_bits-1) downto 0);
iCLK : IN STD_LOGIC);
end component;
end;
-- pragma translate_on
| gpl-3.0 |
EliasLuiz/TCC | Leon3/lib/techmap/stratixiii/adq_dqs/output_dqs_iobuf_inst.vhd | 1 | 7257 | -- megafunction wizard: %ALTIOBUF%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altiobuf_out
-- ============================================================
-- File Name: output_dqs_iobuf_inst.vhd
-- Megafunction Name(s):
-- altiobuf_out
--
-- Simulation Library Files(s):
-- stratixiii
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 8.0 Build 231 07/10/2008 SP 1 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2008 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
--altiobuf_out CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Stratix III" ENABLE_BUS_HOLD="FALSE" NUMBER_OF_CHANNELS=1 OPEN_DRAIN_OUTPUT="FALSE" PSEUDO_DIFFERENTIAL_MODE="TRUE" USE_DIFFERENTIAL_MODE="TRUE" USE_OE="TRUE" USE_TERMINATION_CONTROL="FALSE" datain dataout dataout_b oe
--VERSION_BEGIN 8.0SP1 cbx_altiobuf_in 2008:06:02:292401 cbx_mgl 2008:06:02:292401 cbx_stratixiii 2008:06:18:296807 VERSION_END
LIBRARY stratixiii;
USE stratixiii.all;
--synthesis_resources = stratixiii_io_obuf 2 stratixiii_pseudo_diff_out 1
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY output_dqs_iobuf_inst_iobuf_out_sdp IS
PORT
(
datain : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
dataout : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
dataout_b : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
oe : IN STD_LOGIC_VECTOR (0 DOWNTO 0) := (OTHERS => '1');
oe_b : IN STD_LOGIC_VECTOR (0 DOWNTO 0) := (OTHERS => '1')
);
END output_dqs_iobuf_inst_iobuf_out_sdp;
ARCHITECTURE RTL OF output_dqs_iobuf_inst_iobuf_out_sdp IS
-- ATTRIBUTE synthesis_clearbox : boolean;
-- ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS true;
SIGNAL wire_obuf_ba_o : STD_LOGIC;
SIGNAL wire_obufa_o : STD_LOGIC;
SIGNAL wire_pseudo_diffa_o : STD_LOGIC;
SIGNAL wire_pseudo_diffa_obar : STD_LOGIC;
--SIGNAL oe_b : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT stratixiii_io_obuf
GENERIC
(
bus_hold : STRING := "false";
open_drain_output : STRING := "false";
shift_series_termination_control : STRING := "false";
sim_dynamic_termination_control_is_connected : STRING := "false";
lpm_type : STRING := "stratixiii_io_obuf"
);
PORT
(
dynamicterminationcontrol : IN STD_LOGIC := '0';
i : IN STD_LOGIC := '0';
o : OUT STD_LOGIC;
obar : OUT STD_LOGIC;
oe : IN STD_LOGIC := '1';
parallelterminationcontrol : IN STD_LOGIC_VECTOR(13 DOWNTO 0) := (OTHERS => '0');
seriesterminationcontrol : IN STD_LOGIC_VECTOR(13 DOWNTO 0) := (OTHERS => '0')
);
END COMPONENT;
COMPONENT stratixiii_pseudo_diff_out
PORT
(
i : IN STD_LOGIC := '0';
o : OUT STD_LOGIC;
obar : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
dataout(0) <= wire_obufa_o;
dataout_b(0) <= wire_obuf_ba_o;
--oe_b <= (OTHERS => '1');
obuf_ba : stratixiii_io_obuf
GENERIC MAP (
bus_hold => "false",
open_drain_output => "false"
)
PORT MAP (
i => wire_pseudo_diffa_obar,
o => wire_obuf_ba_o,
oe => oe_b(0)
);
obufa : stratixiii_io_obuf
GENERIC MAP (
bus_hold => "false",
open_drain_output => "false"
)
PORT MAP (
i => wire_pseudo_diffa_o,
o => wire_obufa_o,
oe => oe(0)
);
pseudo_diffa : stratixiii_pseudo_diff_out
PORT MAP (
i => datain(0),
o => wire_pseudo_diffa_o,
obar => wire_pseudo_diffa_obar
);
END RTL; --output_dqs_iobuf_inst_iobuf_out_sdp
--VALID FILE
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY output_dqs_iobuf_inst IS
PORT
(
datain : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
oe : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
oe_b : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
dataout : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
dataout_b : OUT STD_LOGIC_VECTOR (0 DOWNTO 0)
);
END output_dqs_iobuf_inst;
ARCHITECTURE RTL OF output_dqs_iobuf_inst IS
-- ATTRIBUTE synthesis_clearbox: boolean;
-- ATTRIBUTE synthesis_clearbox OF RTL: ARCHITECTURE IS TRUE;
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT output_dqs_iobuf_inst_iobuf_out_sdp
PORT (
dataout : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
datain : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
dataout_b : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
oe : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
oe_b : IN STD_LOGIC_VECTOR (0 DOWNTO 0)
);
END COMPONENT;
BEGIN
dataout <= sub_wire0(0 DOWNTO 0);
dataout_b <= sub_wire1(0 DOWNTO 0);
output_dqs_iobuf_inst_iobuf_out_sdp_component : output_dqs_iobuf_inst_iobuf_out_sdp
PORT MAP (
datain => datain,
oe => oe,
oe_b => oe_b,
dataout => sub_wire0,
dataout_b => sub_wire1
);
END RTL;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix III"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix III"
-- Retrieval info: CONSTANT: enable_bus_hold STRING "FALSE"
-- Retrieval info: CONSTANT: number_of_channels NUMERIC "1"
-- Retrieval info: CONSTANT: open_drain_output STRING "FALSE"
-- Retrieval info: CONSTANT: pseudo_differential_mode STRING "TRUE"
-- Retrieval info: CONSTANT: use_differential_mode STRING "TRUE"
-- Retrieval info: CONSTANT: use_oe STRING "TRUE"
-- Retrieval info: CONSTANT: use_termination_control STRING "FALSE"
-- Retrieval info: USED_PORT: datain 0 0 1 0 INPUT NODEFVAL "datain[0..0]"
-- Retrieval info: USED_PORT: dataout 0 0 1 0 OUTPUT NODEFVAL "dataout[0..0]"
-- Retrieval info: USED_PORT: dataout_b 0 0 1 0 OUTPUT NODEFVAL "dataout_b[0..0]"
-- Retrieval info: USED_PORT: oe 0 0 1 0 INPUT NODEFVAL "oe[0..0]"
-- Retrieval info: CONNECT: @datain 0 0 1 0 datain 0 0 1 0
-- Retrieval info: CONNECT: dataout_b 0 0 1 0 @dataout_b 0 0 1 0
-- Retrieval info: CONNECT: @oe 0 0 1 0 oe 0 0 1 0
-- Retrieval info: CONNECT: dataout 0 0 1 0 @dataout 0 0 1 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL output_dqs_iobuf_inst.vhd TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL output_dqs_iobuf_inst.inc FALSE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL output_dqs_iobuf_inst.cmp FALSE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL output_dqs_iobuf_inst.bsf FALSE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL output_dqs_iobuf_inst_inst.vhd FALSE FALSE
-- Retrieval info: LIB_FILE: stratixiii
| gpl-3.0 |
EliasLuiz/TCC | Leon3/lib/gaisler/gr1553b/gr1553b_stdlogic.vhd | 1 | 6602 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: gr1553b_stdlogic
-- File: gr1553b_stdlogic.vhd
-- Author: Magnus Hjorth - Aeroflex Gaisler
-- Description: Wrapper for GR1553B with std_logic ports
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
library gaisler;
use gaisler.gr1553b_pkg.all;
entity gr1553b_stdlogic is
generic (
bc_enable: integer range 0 to 1 := 1;
rt_enable: integer range 0 to 1 := 1;
bm_enable: integer range 0 to 1 := 1;
bc_timer: integer range 0 to 2 := 1;
bc_rtbusmask: integer range 0 to 1 := 1;
extra_regkeys: integer range 0 to 1 := 0;
syncrst: integer range 0 to 2 := 1;
ahbendian: integer := 0;
bm_filters: integer range 0 to 1 := 1;
codecfreq: integer := 20;
sameclk: integer range 0 to 1 := 0;
codecver: integer range 0 to 2 := 0
);
port (
clk: in std_logic;
rst: in std_logic;
codec_clk: in std_logic;
codec_rst: in std_logic;
-- AHB interface
mi_hgrant : in std_logic; -- bus grant
mi_hready : in std_ulogic; -- transfer done
mi_hresp : in std_logic_vector(1 downto 0); -- response type
mi_hrdata : in std_logic_vector(31 downto 0); -- read data bus
mo_hbusreq : out std_ulogic; -- bus request
mo_htrans : out std_logic_vector(1 downto 0); -- transfer type
mo_haddr : out std_logic_vector(31 downto 0); -- address bus (byte)
mo_hwrite : out std_ulogic; -- read/write
mo_hsize : out std_logic_vector(2 downto 0); -- transfer size
mo_hburst : out std_logic_vector(2 downto 0); -- burst type
mo_hwdata : out std_logic_vector(31 downto 0); -- write data bus
-- APB interface
si_psel : in std_logic; -- slave select
si_penable : in std_ulogic; -- strobe
si_paddr : in std_logic_vector(7 downto 0); -- address bus (byte addr)
si_pwrite : in std_ulogic; -- write
si_pwdata : in std_logic_vector(31 downto 0); -- write data bus
so_prdata : out std_logic_vector(31 downto 0); -- read data bus
so_pirq : out std_logic; -- interrupt bus
-- Aux signals
bcsync : in std_logic;
rtsync : out std_logic;
busreset : out std_logic;
rtaddr : in std_logic_vector(4 downto 0);
rtaddrp : in std_logic;
-- 1553 transceiver interface
busainen : out std_logic;
busainp : in std_logic;
busainn : in std_logic;
busaouten : out std_logic;
busaoutp : out std_logic;
busaoutn : out std_logic;
busbinen : out std_logic;
busbinp : in std_logic;
busbinn : in std_logic;
busbouten : out std_logic;
busboutp : out std_logic;
busboutn : out std_logic
);
end;
architecture rtl of gr1553b_stdlogic is
signal gr1553b_txout: gr1553b_txout_type;
signal gr1553b_rxin: gr1553b_rxin_type;
signal mi: ahb_mst_in_type;
signal mo: ahb_mst_out_type;
signal si: apb_slv_in_type;
signal so: apb_slv_out_type;
signal auxin: gr1553b_auxin_type;
signal auxout: gr1553b_auxout_type;
begin
x: gr1553b
generic map (
hindex => 0,
pindex => 0,
paddr => 0,
pmask => 0,
pirq => 0,
bc_enable => bc_enable,
rt_enable => rt_enable,
bm_enable => bm_enable,
bc_timer => bc_timer,
bc_rtbusmask => bc_rtbusmask,
syncrst => syncrst,
extra_regkeys => extra_regkeys,
ahbendian => ahbendian,
bm_filters => bm_filters,
codecfreq => codecfreq,
sameclk => sameclk,
codecver => codecver
)
port map (
clk => clk,
rst => rst,
ahbmi => mi,
ahbmo => mo,
apbsi => si,
apbso => so,
codec_clk => codec_clk,
codec_rst => codec_rst,
txout => gr1553b_txout,
txout_fb => gr1553b_txout,
rxin => gr1553b_rxin,
auxin => auxin,
auxout => auxout
);
mi.hgrant(0) <= mi_hgrant;
mi.hgrant(1 to NAHBMST-1) <= (others => '0');
mi.hready <= mi_hready;
mi.hresp <= mi_hresp;
mi.hrdata <= ahbdrivedata(mi_hrdata);
mi.hirq <= (others => '0');
mi.testen <= '0';
mi.testrst <= '0';
mi.scanen <= '0';
mi.testoen <= '0';
mo_hbusreq <= mo.hbusreq;
mo_htrans <= mo.htrans;
mo_haddr <= mo.haddr;
mo_hwrite <= mo.hwrite;
mo_hsize <= mo.hsize;
mo_hburst <= mo.hburst;
mo_hwdata <= ahbreadword(mo.hwdata);
si.psel(0) <= si_psel;
si.psel(1 to NAPBSLV-1) <= (others => '0');
si.penable <= si_penable;
si.paddr <= x"000000" & si_paddr;
si.pwrite <= si_pwrite;
si.pwdata <= si_pwdata;
si.pirq <= (others => '0');
si.testen <= '0';
si.testrst <= '0';
si.scanen <= '0';
si.testoen <= '0';
so_prdata <= so.prdata;
so_pirq <= so.pirq(0);
auxin.extsync <= bcsync;
auxin.rtaddr <= rtaddr;
auxin.rtpar <= rtaddrp;
rtsync <= auxout.rtsync;
busreset <= auxout.busreset;
busainen <= gr1553b_txout.busA_rxen;
gr1553b_rxin.busA_rxP <= busainp;
gr1553b_rxin.busA_rxN <= busainn;
busaouten <= gr1553b_txout.busA_txen;
busaoutp <= gr1553b_txout.busA_txP;
busaoutn <= gr1553b_txout.busA_txN;
busBinen <= gr1553b_txout.busB_rxen;
gr1553b_rxin.busB_rxP <= busBinp;
gr1553b_rxin.busB_rxN <= busBinn;
busBouten <= gr1553b_txout.busB_txen;
busBoutp <= gr1553b_txout.busB_txP;
busBoutn <= gr1553b_txout.busB_txN;
end;
| gpl-3.0 |
EliasLuiz/TCC | Leon3/lib/gaisler/leon3/leon3.in.vhd | 1 | 3526 | -- LEON3 processor core
constant CFG_LEON3 : integer := CONFIG_LEON3;
constant CFG_NCPU : integer := CONFIG_PROC_NUM;
constant CFG_NWIN : integer := CONFIG_IU_NWINDOWS;
constant CFG_V8 : integer := CFG_IU_V8 + 4*CFG_IU_MUL_STRUCT;
constant CFG_MAC : integer := CONFIG_IU_MUL_MAC;
constant CFG_BP : integer := CONFIG_IU_BP;
constant CFG_SVT : integer := CONFIG_IU_SVT;
constant CFG_RSTADDR : integer := 16#CONFIG_IU_RSTADDR#;
constant CFG_LDDEL : integer := CONFIG_IU_LDELAY;
constant CFG_NOTAG : integer := CONFIG_NOTAG;
constant CFG_NWP : integer := CONFIG_IU_WATCHPOINTS;
constant CFG_PWD : integer := CONFIG_PWD*2;
constant CFG_FPU : integer := CONFIG_FPU + 16*CONFIG_FPU_NETLIST + 32*CONFIG_FPU_GRFPU_SHARED;
constant CFG_GRFPUSH : integer := CONFIG_FPU_GRFPU_SHARED;
constant CFG_ICEN : integer := CONFIG_ICACHE_ENABLE;
constant CFG_ISETS : integer := CFG_IU_ISETS;
constant CFG_ISETSZ : integer := CFG_ICACHE_SZ;
constant CFG_ILINE : integer := CFG_ILINE_SZ;
constant CFG_IREPL : integer := CFG_ICACHE_ALGORND;
constant CFG_ILOCK : integer := CONFIG_ICACHE_LOCK;
constant CFG_ILRAMEN : integer := CONFIG_ICACHE_LRAM;
constant CFG_ILRAMADDR: integer := 16#CONFIG_ICACHE_LRSTART#;
constant CFG_ILRAMSZ : integer := CFG_ILRAM_SIZE;
constant CFG_DCEN : integer := CONFIG_DCACHE_ENABLE;
constant CFG_DSETS : integer := CFG_IU_DSETS;
constant CFG_DSETSZ : integer := CFG_DCACHE_SZ;
constant CFG_DLINE : integer := CFG_DLINE_SZ;
constant CFG_DREPL : integer := CFG_DCACHE_ALGORND;
constant CFG_DLOCK : integer := CONFIG_DCACHE_LOCK;
constant CFG_DSNOOP : integer := CONFIG_DCACHE_SNOOP_SP + CONFIG_DCACHE_SNOOP*2 + 4*CONFIG_DCACHE_SNOOP_SEPTAG;
constant CFG_DFIXED : integer := 16#CONFIG_CACHE_FIXED#;
constant CFG_DLRAMEN : integer := CONFIG_DCACHE_LRAM;
constant CFG_DLRAMADDR: integer := 16#CONFIG_DCACHE_LRSTART#;
constant CFG_DLRAMSZ : integer := CFG_DLRAM_SIZE;
constant CFG_MMUEN : integer := CONFIG_MMUEN;
constant CFG_ITLBNUM : integer := CONFIG_ITLBNUM;
constant CFG_DTLBNUM : integer := CONFIG_DTLBNUM;
constant CFG_TLB_TYPE : integer := CONFIG_TLB_TYPE + CFG_MMU_FASTWB*2;
constant CFG_TLB_REP : integer := CONFIG_TLB_REP;
constant CFG_MMU_PAGE : integer := CONFIG_MMU_PAGE;
constant CFG_DSU : integer := CONFIG_DSU_ENABLE;
constant CFG_ITBSZ : integer := CFG_DSU_ITB + 64*CONFIG_DSU_ITRACE_2P;
constant CFG_ATBSZ : integer := CFG_DSU_ATB;
constant CFG_AHBPF : integer := CFG_DSU_AHBPF;
constant CFG_LEON3FT_EN : integer := CONFIG_LEON3FT_EN;
constant CFG_IUFT_EN : integer := CONFIG_IUFT_EN;
constant CFG_FPUFT_EN : integer := CONFIG_FPUFT;
constant CFG_RF_ERRINJ : integer := CONFIG_RF_ERRINJ;
constant CFG_CACHE_FT_EN : integer := CONFIG_CACHE_FT_EN;
constant CFG_CACHE_ERRINJ : integer := CONFIG_CACHE_ERRINJ;
constant CFG_LEON3_NETLIST: integer := CONFIG_LEON3_NETLIST;
constant CFG_DISAS : integer := CONFIG_IU_DISAS + CONFIG_IU_DISAS_NET;
constant CFG_PCLOW : integer := CFG_DEBUG_PC32;
constant CFG_STAT_ENABLE : integer := CONFIG_STAT_ENABLE;
constant CFG_STAT_CNT : integer := CONFIG_STAT_CNT;
constant CFG_STAT_NMAX : integer := CONFIG_STAT_NMAX;
constant CFG_STAT_DSUEN : integer := CONFIG_STAT_DSUEN;
constant CFG_NP_ASI : integer := CONFIG_NP_ASI;
constant CFG_WRPSR : integer := CONFIG_WRPSR;
constant CFG_ALTWIN : integer := CONFIG_ALTWIN;
constant CFG_REX : integer := CONFIG_REX;
| gpl-3.0 |
EliasLuiz/TCC | Leon3/designs/leon3-digilent-nexys3/config.vhd | 1 | 8129 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := spartan6;
constant CFG_MEMTECH : integer := spartan6;
constant CFG_PADTECH : integer := spartan6;
constant CFG_TRANSTECH : integer := GTP0;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := spartan6;
constant CFG_CLKMUL : integer := (5);
constant CFG_CLKDIV : integer := (10);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 16#32# + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 0;
constant CFG_SVT : integer := 1;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 1;
constant CFG_NWP : integer := (0);
constant CFG_PWD : integer := 0*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 2;
constant CFG_ISETSZ : integer := 8;
constant CFG_ILINE : integer := 4;
constant CFG_IREPL : integer := 2;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 2;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 4;
constant CFG_DREPL : integer := 2;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 0 + 0*2 + 4*0;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 0;
constant CFG_ITLBNUM : integer := 2;
constant CFG_DTLBNUM : integer := 2;
constant CFG_TLB_TYPE : integer := 1 + 0*2;
constant CFG_TLB_REP : integer := 1;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 2 + 64*0;
constant CFG_ATBSZ : integer := 2;
constant CFG_AHBPF : integer := 0;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
constant CFG_STAT_ENABLE : integer := 0;
constant CFG_STAT_CNT : integer := 1;
constant CFG_STAT_NMAX : integer := 0;
constant CFG_STAT_DSUEN : integer := 0;
constant CFG_NP_ASI : integer := 0;
constant CFG_WRPSR : integer := 0;
constant CFG_ALTWIN : integer := 0;
constant CFG_REX : integer := 0;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 1;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 1;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- Ethernet DSU
constant CFG_DSU_ETH : integer := 1 + 0 + 0;
constant CFG_ETH_BUF : integer := 2;
constant CFG_ETH_IPM : integer := 16#C0A8#;
constant CFG_ETH_IPL : integer := 16#0033#;
constant CFG_ETH_ENM : integer := 16#020000#;
constant CFG_ETH_ENL : integer := 16#000000#;
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 1;
constant CFG_MCTRL_RAM8BIT : integer := 0;
constant CFG_MCTRL_RAM16BIT : integer := 1;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 0;
constant CFG_MCTRL_SEPBUS : integer := 0;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 0;
constant CFG_MCTRL_PAGE : integer := 0 + 0;
-- DDR controller
constant CFG_DDR2SP : integer := 0;
constant CFG_DDR2SP_INIT : integer := 0;
constant CFG_DDR2SP_FREQ : integer := 100;
constant CFG_DDR2SP_TRFC : integer := 130;
constant CFG_DDR2SP_DATAWIDTH : integer := 64;
constant CFG_DDR2SP_FTEN : integer := 0;
constant CFG_DDR2SP_FTWIDTH : integer := 0;
constant CFG_DDR2SP_COL : integer := 9;
constant CFG_DDR2SP_SIZE : integer := 8;
constant CFG_DDR2SP_DELAY0 : integer := 0;
constant CFG_DDR2SP_DELAY1 : integer := 0;
constant CFG_DDR2SP_DELAY2 : integer := 0;
constant CFG_DDR2SP_DELAY3 : integer := 0;
constant CFG_DDR2SP_DELAY4 : integer := 0;
constant CFG_DDR2SP_DELAY5 : integer := 0;
constant CFG_DDR2SP_DELAY6 : integer := 0;
constant CFG_DDR2SP_DELAY7 : integer := 0;
constant CFG_DDR2SP_NOSYNC : integer := 0;
-- Xilinx MIG
constant CFG_MIG_DDR2 : integer := 1;
constant CFG_MIG_RANKS : integer := (1);
constant CFG_MIG_COLBITS : integer := (10);
constant CFG_MIG_ROWBITS : integer := (13);
constant CFG_MIG_BANKBITS: integer := (2);
constant CFG_MIG_HMASK : integer := 16#F00#;
-- AHB ROM
constant CFG_AHBROMEN : integer := 0;
constant CFG_AHBROPIP : integer := 0;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#000#;
constant CFG_ROMMASK : integer := 16#E00# + 16#000#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- Gaisler Ethernet core
constant CFG_GRETH : integer := 1;
constant CFG_GRETH1G : integer := 0;
constant CFG_ETH_FIFO : integer := 4;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 1;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 0;
constant CFG_GRGPIO_IMASK : integer := 16#0000#;
constant CFG_GRGPIO_WIDTH : integer := 1;
-- SPI memory controller
constant CFG_SPIMCTRL : integer := 0;
constant CFG_SPIMCTRL_SDCARD : integer := 0;
constant CFG_SPIMCTRL_READCMD : integer := 16#0#;
constant CFG_SPIMCTRL_DUMMYBYTE : integer := 0;
constant CFG_SPIMCTRL_DUALOUTPUT : integer := 0;
constant CFG_SPIMCTRL_SCALER : integer := 1;
constant CFG_SPIMCTRL_ASCALER : integer := 1;
constant CFG_SPIMCTRL_PWRUPCNT : integer := 0;
constant CFG_SPIMCTRL_OFFSET : integer := 16#0#;
-- SPI controller
constant CFG_SPICTRL_ENABLE : integer := 0;
constant CFG_SPICTRL_NUM : integer := 1;
constant CFG_SPICTRL_SLVS : integer := 1;
constant CFG_SPICTRL_FIFO : integer := 1;
constant CFG_SPICTRL_SLVREG : integer := 0;
constant CFG_SPICTRL_ODMODE : integer := 0;
constant CFG_SPICTRL_AM : integer := 0;
constant CFG_SPICTRL_ASEL : integer := 0;
constant CFG_SPICTRL_TWEN : integer := 0;
constant CFG_SPICTRL_MAXWLEN : integer := 0;
constant CFG_SPICTRL_SYNCRAM : integer := 0;
constant CFG_SPICTRL_FT : integer := 0;
-- GRLIB debugging
constant CFG_DUART : integer := 1;
end;
| gpl-3.0 |
EliasLuiz/TCC | Leon3/lib/gaisler/misc/misc.vhd | 1 | 53414 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: misc
-- File: misc.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Misc models
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.devices.all;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
package misc is
-- reset generator with filter
component rstgen
generic (acthigh : integer := 0; syncrst : integer := 0;
scanen : integer := 0; syncin : integer := 0);
port (
rstin : in std_ulogic;
clk : in std_ulogic;
clklock : in std_ulogic;
rstout : out std_ulogic;
rstoutraw : out std_ulogic;
testrst : in std_ulogic := '0';
testen : in std_ulogic := '0');
end component;
type gptimer_in_type is record
dhalt : std_ulogic;
extclk : std_ulogic;
wdogen : std_ulogic;
latchv : std_logic_vector(NAHBIRQ-1 downto 0);
latchd : std_logic_vector(NAHBIRQ-1 downto 0);
end record;
function gpti_dhalt_drive (dhalt : std_ulogic) return gptimer_in_type;
type gptimer_in_vector is array (natural range <>) of gptimer_in_type;
type gptimer_out_type is record
tick : std_logic_vector(0 to 7);
timer1 : std_logic_vector(31 downto 0);
wdogn : std_ulogic;
wdog : std_ulogic;
end record;
type gptimer_out_vector is array (natural range <>) of gptimer_out_type;
constant gptimer_in_none : gptimer_in_type := ('0', '0', '0', zxirq(NAHBIRQ-1 downto 0), zxirq(NAHBIRQ-1 downto 0));
constant gptimer_out_none : gptimer_out_type :=
((others => '0'), (others => '0'), '1', '0');
component gptimer
generic (
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
pirq : integer := 0;
sepirq : integer := 0; -- use separate interrupts for each timer
sbits : integer := 16; -- scaler bits
ntimers : integer range 1 to 7 := 1; -- number of timers
nbits : integer := 32; -- timer bits
wdog : integer := 0;
ewdogen : integer := 0;
glatch : integer := 0;
gextclk : integer := 0;
gset : integer := 0;
gelatch : integer range 0 to 2 := 0;
wdogwin : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
gpti : in gptimer_in_type;
gpto : out gptimer_out_type
);
end component;
-- 32-bit ram with AHB interface
component ahbram
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
tech : integer := DEFMEMTECH;
kbytes : integer := 1;
pipe : integer := 0;
maccsz : integer := AHBDW;
scantest: integer := 0);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type);
end component;
type ahbram_out_type is record
ce : std_ulogic;
end record;
component ftahbram
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
tech : integer := DEFMEMTECH;
kbytes : integer := 1;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
edacen : integer range 0 to 3 := 1; --enable EDAC
autoscrub : integer range 0 to 1 := 0; --enable auto-scrubbing
errcnten : integer range 0 to 1 := 0; --enable error counter in stat.reg
cntbits : integer range 1 to 8 := 1; --errcnt size in bits
ahbpipe : integer range 0 to 1 := 0;
testen : integer := 0);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
aramo : out ahbram_out_type
);
end component;
component ftahbram1 is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
tech : integer := DEFMEMTECH;
kbytes : integer := 1;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
edacen : integer range 0 to 3 := 1;
autoscrub : integer range 0 to 1 := 0;
errcnten : integer range 0 to 1 := 0;
cntbits : integer range 1 to 8 := 1;
ahbpipe : integer range 0 to 1 := 0;
testen : integer := 0);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
aramo : out ahbram_out_type
);
end component;
component ftahbram2 is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
tech : integer := DEFMEMTECH;
kbytes : integer := 1;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
testen : integer := 0;
edacen : integer range 1 to 3 := 1);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
aramo : out ahbram_out_type
);
end component;
component ahbdpram
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
tech : integer := 2;
abits : integer range 8 to 19 := 8;
bytewrite : integer range 0 to 1 := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
clkdp : in std_ulogic;
address : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector(31 downto 0);
dataout : out std_logic_vector(31 downto 0);
enable : in std_ulogic; -- active high chip select
write : in std_logic_vector(0 to 3) -- active high byte write enable
); -- big-endian write: bwrite(0) => data(31:24)
end component;
component ahbtrace is
generic (
hindex : integer := 0;
ioaddr : integer := 16#000#;
iomask : integer := 16#E00#;
tech : integer := DEFMEMTECH;
irq : integer := 0;
kbytes : integer := 1;
bwidth : integer := 32;
ahbfilt : integer := 0;
scantest : integer range 0 to 1 := 0;
exttimer : integer range 0 to 1 := 0;
exten : integer range 0 to 1 := 0);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
timer : in std_logic_vector(30 downto 0) := (others => '0');
astat : out amba_stat_type;
resen : in std_ulogic := '0'
);
end component;
component ahbtrace_mb is
generic (
hindex : integer := 0;
ioaddr : integer := 16#000#;
iomask : integer := 16#E00#;
tech : integer := DEFMEMTECH;
irq : integer := 0;
kbytes : integer := 1;
bwidth : integer := 32;
ahbfilt : integer := 0;
scantest : integer range 0 to 1 := 0;
exttimer : integer range 0 to 1 := 0;
exten : integer range 0 to 1 := 0);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type; -- Register interface
ahbso : out ahb_slv_out_type;
tahbmi : in ahb_mst_in_type; -- Trace
tahbsi : in ahb_slv_in_type;
timer : in std_logic_vector(30 downto 0) := (others => '0');
astat : out amba_stat_type;
resen : in std_ulogic := '0'
);
end component;
component ahbtrace_mmb is
generic (
hindex : integer := 0;
ioaddr : integer := 16#000#;
iomask : integer := 16#E00#;
tech : integer := DEFMEMTECH;
irq : integer := 0;
kbytes : integer := 1;
bwidth : integer := 32;
ahbfilt : integer := 0;
ntrace : integer range 1 to 8 := 1;
scantest : integer range 0 to 1 := 0;
exttimer : integer range 0 to 1 := 0;
exten : integer range 0 to 1 := 0);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type; -- Register interface
ahbso : out ahb_slv_out_type;
tahbmiv : in ahb_mst_in_vector_type(0 to ntrace-1); -- Trace
tahbsiv : in ahb_slv_in_vector_type(0 to ntrace-1);
timer : in std_logic_vector(30 downto 0) := (others => '0');
astat : out amba_stat_type;
resen : in std_ulogic := '0'
);
end component;
type ahbmst2_request is record
req: std_logic; -- Request enable bit
wr: std_logic;
hsize: std_logic_vector(2 downto 0);
hburst: std_logic_vector(2 downto 0);
hprot: std_logic_vector(3 downto 0);
addr: std_logic_vector(32-1 downto 0);
burst_cont: std_logic; -- Set for all except the first request in a burst
burst_wrap: std_logic; -- High for the request where wrap occurs
end record;
constant ahbmst2_request_none: ahbmst2_request := (
req => '0', wr => '0', hsize => "010", hburst => "000", burst_cont => '0',
burst_wrap => '0', addr => (others => '0'), hprot => "0011");
type ahbmst2_in_type is record
request: ahbmst2_request;
wrdata: std_logic_vector(AHBDW-1 downto 0);
-- For back-to-back transfers or bursts, this must be set when done is high
-- and then copied over to request after the rising edge of clk.
next_request: ahbmst2_request;
-- Insert busy cycle, must only be asserted when request and next_request
-- are both part of the same burst.
busy: std_logic;
hlock: std_logic; -- Lock signal, passed through directly to AMBA.
keepreq: std_logic; -- Keep bus request high even when no request needs it.
end record;
type ahbmst2_out_type is record
done: std_logic;
flip: std_logic;
fail: std_logic;
rddata: std_logic_vector(AHBDW-1 downto 0);
end record;
component ahbmst2 is
generic (
hindex: integer := 0;
venid: integer;
devid: integer;
version: integer;
dmastyle: integer range 1 to 3 := 3;
syncrst: integer range 0 to 1 := 1
);
port (
clk: in std_logic;
rst: in std_logic;
ahbi: in ahb_mst_in_type;
ahbo: out ahb_mst_out_type;
m2i: in ahbmst2_in_type;
m2o: out ahbmst2_out_type
);
end component;
type gpio_in_type is record
din : std_logic_vector(31 downto 0);
sig_in : std_logic_vector(31 downto 0);
sig_en : std_logic_vector(31 downto 0);
end record;
type gpio_in_vector is array (natural range <>) of gpio_in_type;
type gpio_out_type is record
dout : std_logic_vector(31 downto 0);
oen : std_logic_vector(31 downto 0);
val : std_logic_vector(31 downto 0);
sig_out : std_logic_vector(31 downto 0);
end record;
type gpio_out_vector is array (natural range <>) of gpio_out_type;
component grgpio
generic (
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
imask : integer := 16#0000#;
nbits : integer := 16; -- GPIO bits
oepol : integer := 0; -- Output enable polarity
syncrst : integer := 0;
bypass : integer := 16#0000#;
scantest : integer := 0;
bpdir : integer := 16#0000#;
pirq : integer := 0;
irqgen : integer := 0;
iflagreg : integer range 0 to 1:= 0;
bpmode : integer range 0 to 1 := 0;
inpen : integer range 0 to 1 := 0;
doutresv : integer := 0;
dirresv : integer := 0;
bpresv : integer := 0;
inpresv : integer := 0;
pulse : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
gpioi : in gpio_in_type;
gpioo : out gpio_out_type
);
end component;
type ahb2ahb_ctrl_type is record
slck : std_ulogic;
blck : std_ulogic;
mlck : std_ulogic;
end record;
constant ahb2ahb_ctrl_none : ahb2ahb_ctrl_type := ('0', '0', '0');
type ahb2ahb_ifctrl_type is record
mstifen : std_ulogic;
slvifen : std_ulogic;
end record;
constant ahb2ahb_ifctrl_none : ahb2ahb_ifctrl_type := ('1', '1');
component ahb2ahb
generic(
memtech : integer := 0;
hsindex : integer := 0;
hmindex : integer := 0;
slv : integer range 0 to 1 := 0;
dir : integer range 0 to 1 := 0; -- 0 - down, 1 - up
ffact : integer range 0 to 15:= 2;
pfen : integer range 0 to 1 := 0;
wburst : integer range 2 to 32 := 8;
iburst : integer range 4 to 8 := 8;
rburst : integer range 2 to 32 := 8;
irqsync : integer range 0 to 3 := 0;
bar0 : integer range 0 to 1073741823 := 0;
bar1 : integer range 0 to 1073741823 := 0;
bar2 : integer range 0 to 1073741823 := 0;
bar3 : integer range 0 to 1073741823 := 0;
sbus : integer := 0;
mbus : integer := 0;
ioarea : integer := 0;
ibrsten : integer := 0;
lckdac : integer range 0 to 2 := 0;
slvmaccsz : integer range 32 to 256 := 32;
mstmaccsz : integer range 32 to 256 := 32;
rdcomb : integer range 0 to 2 := 0;
wrcomb : integer range 0 to 2 := 0;
combmask : integer := 16#ffff#;
allbrst : integer range 0 to 2 := 0;
ifctrlen : integer range 0 to 1 := 0;
fcfs : integer range 0 to NAHBMST := 0;
fcfsmtech : integer range 0 to NTECH := inferred;
scantest : integer range 0 to 1 := 0;
split : integer range 0 to 1 := 1;
pipe : integer range 0 to 128 := 0);
port (
rstn : in std_ulogic;
hclkm : in std_ulogic;
hclks : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type;
ahbso2 : in ahb_slv_out_vector;
lcki : in ahb2ahb_ctrl_type;
lcko : out ahb2ahb_ctrl_type;
ifctrl : in ahb2ahb_ifctrl_type := ahb2ahb_ifctrl_none
);
end component;
component ahbbridge
generic(
memtech : integer := 0;
ffact : integer range 0 to 15 := 2;
-- high-speed bus
hsb_hsindex : integer := 0;
hsb_hmindex : integer := 0;
hsb_iclsize : integer range 4 to 8 := 8;
hsb_bank0 : integer range 0 to 1073741823 := 0;
hsb_bank1 : integer range 0 to 1073741823 := 0;
hsb_bank2 : integer range 0 to 1073741823 := 0;
hsb_bank3 : integer range 0 to 1073741823 := 0;
hsb_ioarea : integer := 0;
-- low-speed bus
lsb_hsindex : integer := 0;
lsb_hmindex : integer := 0;
lsb_rburst : integer range 16 to 32 := 16;
lsb_wburst : integer range 2 to 32 := 8;
lsb_bank0 : integer range 0 to 1073741823 := 0;
lsb_bank1 : integer range 0 to 1073741823 := 0;
lsb_bank2 : integer range 0 to 1073741823 := 0;
lsb_bank3 : integer range 0 to 1073741823 := 0;
lsb_ioarea : integer := 0;
--
lckdac : integer range 0 to 2 := 2;
maccsz : integer range 32 to 256 := 32;
rdcomb : integer range 0 to 2 := 0;
wrcomb : integer range 0 to 2 := 0;
combmask : integer := 16#ffff#;
allbrst : integer range 0 to 2 := 0;
fcfs : integer range 0 to NAHBMST := 0;
scantest : integer range 0 to 1 := 0);
port (
rstn : in std_ulogic;
hsb_clk : in std_ulogic;
lsb_clk : in std_ulogic;
hsb_ahbsi : in ahb_slv_in_type;
hsb_ahbso : out ahb_slv_out_type;
hsb_ahbsov : in ahb_slv_out_vector;
hsb_ahbmi : in ahb_mst_in_type;
hsb_ahbmo : out ahb_mst_out_type;
lsb_ahbsi : in ahb_slv_in_type;
lsb_ahbso : out ahb_slv_out_type;
lsb_ahbsov : in ahb_slv_out_vector;
lsb_ahbmi : in ahb_mst_in_type;
lsb_ahbmo : out ahb_mst_out_type);
end component;
function ahb2ahb_membar(memaddr : ahb_addr_type; prefetch, cache : std_ulogic;
addrmask : ahb_addr_type)
return integer;
function ahb2ahb_iobar(memaddr : ahb_addr_type; addrmask : ahb_addr_type)
return integer;
type ahbstat_in_type is record
cerror : std_logic_vector(0 to NAHBSLV-1);
end record;
constant ahbstat_in_none : ahbstat_in_type :=
(cerror => zero32(NAHBSLV-1 downto 0));
component ahbstat is
generic(
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#FFF#;
pirq : integer := 0;
nftslv : integer range 1 to NAHBSLV - 1 := 3);
port(
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbsi : in ahb_slv_in_type;
stati : in ahbstat_in_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type
);
end component;
type nuhosp3_in_type is record
flash_d : std_logic_vector(15 downto 0);
smsc_data : std_logic_vector(31 downto 0);
smsc_ardy : std_ulogic;
smsc_intr : std_ulogic;
smsc_nldev : std_ulogic;
lcd_data : std_logic_vector(7 downto 0);
end record;
type nuhosp3_out_type is record
flash_a : std_logic_vector(20 downto 0);
flash_d : std_logic_vector(15 downto 0);
flash_oen : std_ulogic;
flash_wen : std_ulogic;
flash_cen : std_ulogic;
smsc_addr : std_logic_vector(14 downto 0);
smsc_data : std_logic_vector(31 downto 0);
smsc_nbe : std_logic_vector(3 downto 0);
smsc_resetn : std_ulogic;
smsc_nrd : std_ulogic;
smsc_nwr : std_ulogic;
smsc_ncs : std_ulogic;
smsc_aen : std_ulogic;
smsc_lclk : std_ulogic;
smsc_wnr : std_ulogic;
smsc_rdyrtn : std_ulogic;
smsc_cycle : std_ulogic;
smsc_nads : std_ulogic;
smsc_ben : std_ulogic;
lcd_data : std_logic_vector(7 downto 0);
lcd_rs : std_ulogic;
lcd_rw : std_ulogic;
lcd_en : std_ulogic;
lcd_backl : std_ulogic;
lcd_ben : std_ulogic;
end record;
component nuhosp3
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
ioaddr : integer := 16#200#;
iomask : integer := 16#fff#);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
nui : in nuhosp3_in_type;
nuo : out nuhosp3_out_type
);
end component;
-- On-chip Logic Analyzer
component logan is
generic (
dbits : integer range 0 to 256 := 32; -- Number of traced signals
depth : integer range 256 to 16384 := 1024; -- Depth of trace buffer
trigl : integer range 1 to 63 := 1; -- Number of trigger levels
usereg : integer range 0 to 1 := 1; -- Use input register
usequal : integer range 0 to 1 := 0;
usediv : integer range 0 to 1 := 1;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#F00#;
memtech : integer := DEFMEMTECH);
port (
rstn : in std_logic;
clk : in std_logic;
tclk : in std_logic;
apbi : in apb_slv_in_type; -- APB in record
apbo : out apb_slv_out_type; -- APB out record
signals : in std_logic_vector(dbits - 1 downto 0)); -- Traced signals
end component;
type ps2_in_type is record
ps2_clk_i : std_ulogic;
ps2_data_i : std_ulogic;
end record;
type ps2_out_type is record
ps2_clk_o : std_ulogic;
ps2_clk_oe : std_ulogic;
ps2_data_o : std_ulogic;
ps2_data_oe : std_ulogic;
end record;
component apbps2
generic(
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
pirq : integer := 0;
fKHz : integer := 50000;
fixed : integer := 0;
oepol : integer range 0 to 1 := 0);
port(
rst : in std_ulogic; -- Global asynchronous reset
clk : in std_ulogic; -- Global clock
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
ps2i : in ps2_in_type;
ps2o : out ps2_out_type
);
end component;
type apbvga_out_type is record
hsync : std_ulogic; -- horizontal sync
vsync : std_ulogic; -- vertical sync
comp_sync : std_ulogic; -- composite sync
blank : std_ulogic; -- blank signal
video_out_r : std_logic_vector(7 downto 0); -- red channel
video_out_g : std_logic_vector(7 downto 0); -- green channel
video_out_b : std_logic_vector(7 downto 0); -- blue channel
bitdepth : std_logic_vector(1 downto 0); -- Bith depth
end record;
component apbvga
generic(
memtech : integer := DEFMEMTECH;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#);
port(
rst : in std_ulogic; -- Global asynchronous reset
clk : in std_ulogic; -- Global clock
vgaclk : in std_ulogic; -- VGA clock
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
vgao : out apbvga_out_type
);
end component;
component svgactrl
generic(
length : integer := 384; -- Fifo-length
part : integer := 128; -- Fifo-part lenght
memtech : integer := DEFMEMTECH;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
hindex : integer := 0;
hirq : integer := 0;
clk0 : integer := 40000;
clk1 : integer := 20000;
clk2 : integer := 15385;
clk3 : integer := 0;
burstlen : integer range 2 to 8 := 8;
ahbaccsz : integer := 32;
asyncrst : integer range 0 to 1 := 0
);
port (
rst : in std_logic;
clk : in std_logic;
vgaclk : in std_logic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
vgao : out apbvga_out_type;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
clk_sel : out std_logic_vector(1 downto 0);
arst : in std_ulogic := '1'
);
end component;
constant vgao_none : apbvga_out_type :=
('0', '0', '0', '0', "00000000", "00000000", "00000000", "00");
constant ps2o_none : ps2_out_type := ('1', '1', '1', '1');
-- component ahbrom
-- generic (
-- hindex : integer := 0;
-- haddr : integer := 0;
-- hmask : integer := 16#fff#;
-- pipe : integer := 0;
-- tech : integer := 0;
-- kbytes : integer := 1);
-- port (
-- rst : in std_ulogic;
-- clk : in std_ulogic;
-- ahbsi : in ahb_slv_in_type;
-- ahbso : out ahb_slv_out_type
-- );
-- end component;
component ahbdma
generic (
hindex : integer := 0;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
pirq : integer := 0;
dbuf : integer := 0);
port (
rst : in std_logic;
clk : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type
);
end component;
-----------------------------------------------------------------------------
-- Interface type declarations for FIFO controller
-----------------------------------------------------------------------------
type FIFO_In_Type is record
Din: Std_Logic_Vector(31 downto 0); -- data input
Pin: Std_Logic_Vector( 3 downto 0); -- parity input
EFn: Std_ULogic; -- empty flag
FFn: Std_ULogic; -- full flag
HFn: Std_ULogic; -- half flag
end record;
type FIFO_Out_Type is record
Dout: Std_Logic_Vector(31 downto 0); -- data output
Den: Std_Logic_Vector(31 downto 0); -- data enable
Pout: Std_Logic_Vector( 3 downto 0); -- parity output
Pen: Std_Logic_Vector( 3 downto 0); -- parity enable
WEn: Std_ULogic; -- write enable
REn: Std_ULogic; -- read enable
end record;
-----------------------------------------------------------------------------
-- Component declaration for GR FIFO Interface
-----------------------------------------------------------------------------
component grfifo is
generic (
hindex: Integer := 0;
pindex: Integer := 0;
paddr: Integer := 0;
pmask: Integer := 16#FFF#;
pirq: Integer := 1; -- index of first irq
dwidth: Integer := 16; -- data width
ptrwidth: Integer range 16 to 16 := 16; -- 16 to 64k bytes
-- 128 to 512k bits
singleirq: Integer range 0 to 1 := 0; -- single irq output
oepol: Integer := 1); -- output enable polarity
port (
rstn: in Std_ULogic;
clk: in Std_ULogic;
apbi: in APB_Slv_In_Type;
apbo: out APB_Slv_Out_Type;
ahbi: in AHB_Mst_In_Type;
ahbo: out AHB_Mst_Out_Type;
fifoi: in FIFO_In_Type;
fifoo: out FIFO_Out_Type);
end component;
-----------------------------------------------------------------------------
-- Interface type declarations for CAN controllers
-----------------------------------------------------------------------------
type Analog_In_Type is record
Ain: Std_Logic_Vector(31 downto 0); -- address input
Din: Std_Logic_Vector(31 downto 0); -- data input
Rdy: Std_ULogic; -- adc ready input
Trig: Std_Logic_Vector( 2 downto 0); -- adc trigger inputs
end record;
type Analog_Out_Type is record
Aout: Std_Logic_Vector(31 downto 0); -- address output
Aen: Std_Logic_Vector(31 downto 0); -- address enable
Dout: Std_Logic_Vector(31 downto 0); -- dac data output
Den: Std_Logic_Vector(31 downto 0); -- dac data enable
Wr: Std_ULogic; -- dac write strobe
CS: Std_ULogic; -- adc chip select
RC: Std_ULogic; -- adc read/convert
end record;
-----------------------------------------------------------------------------
-- Component declaration for GR ADC/DAC Interface
-----------------------------------------------------------------------------
component gradcdac is
generic (
pindex: Integer := 0;
paddr: Integer := 0;
pmask: Integer := 16#FFF#;
pirq: Integer := 1; -- index of first irq
awidth: Integer := 8; -- address width
dwidth: Integer := 16; -- data width
oepol: Integer := 1); -- output enable polarity
port (
rstn: in Std_ULogic;
clk: in Std_ULogic;
apbi: in APB_Slv_In_Type;
apbo: out APB_Slv_Out_Type;
adi: in Analog_In_Type;
ado: out Analog_Out_Type);
end component;
-----------------------------------------------------------------------------
-- AMBA wrapper for System Monitor
-----------------------------------------------------------------------------
type grsysmon_in_type is record
convst : std_ulogic;
convstclk : std_ulogic;
vauxn : std_logic_vector(15 downto 0);
vauxp : std_logic_vector(15 downto 0);
vn : std_ulogic;
vp : std_ulogic;
end record;
type grsysmon_out_type is record
alm : std_logic_vector(2 downto 0);
ot : std_ulogic;
eoc : std_ulogic;
eos : std_ulogic;
channel : std_logic_vector(4 downto 0);
end record;
constant grsysmon_in_gnd : grsysmon_in_type :=
('0', '0', (others => '0'), (others => '0'), '0', '0');
component grsysmon
generic (
-- GRLIB generics
tech : integer := DEFFABTECH;
hindex : integer := 0; -- AHB slave index
hirq : integer := 0; -- Interrupt line
caddr : integer := 16#000#; -- Base address for configuration area
cmask : integer := 16#fff#; -- Area mask
saddr : integer := 16#001#; -- Base address for sysmon register area
smask : integer := 16#fff#; -- Area mask
split : integer := 0; -- Enable AMBA SPLIT support
extconvst : integer := 0; -- Use external CONVST signal
wrdalign : integer := 0; -- Word align System Monitor registers
-- Virtex 5 SYSMON generics
INIT_40 : bit_vector := X"0000";
INIT_41 : bit_vector := X"0000";
INIT_42 : bit_vector := X"0800";
INIT_43 : bit_vector := X"0000";
INIT_44 : bit_vector := X"0000";
INIT_45 : bit_vector := X"0000";
INIT_46 : bit_vector := X"0000";
INIT_47 : bit_vector := X"0000";
INIT_48 : bit_vector := X"0000";
INIT_49 : bit_vector := X"0000";
INIT_4A : bit_vector := X"0000";
INIT_4B : bit_vector := X"0000";
INIT_4C : bit_vector := X"0000";
INIT_4D : bit_vector := X"0000";
INIT_4E : bit_vector := X"0000";
INIT_4F : bit_vector := X"0000";
INIT_50 : bit_vector := X"0000";
INIT_51 : bit_vector := X"0000";
INIT_52 : bit_vector := X"0000";
INIT_53 : bit_vector := X"0000";
INIT_54 : bit_vector := X"0000";
INIT_55 : bit_vector := X"0000";
INIT_56 : bit_vector := X"0000";
INIT_57 : bit_vector := X"0000";
SIM_MONITOR_FILE : string := "sysmon.txt");
port (
rstn : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
sysmoni : in grsysmon_in_type;
sysmono : out grsysmon_out_type
);
end component;
-----------------------------------------------------------------------------
-- AMBA System ACE Interface Controller
-----------------------------------------------------------------------------
type gracectrl_in_type is record
di : std_logic_vector(15 downto 0);
-- brdy : std_ulogic;
irq : std_ulogic;
end record;
type gracectrl_out_type is record
addr : std_logic_vector(6 downto 0);
do : std_logic_vector(15 downto 0);
cen : std_ulogic;
wen : std_ulogic;
oen : std_ulogic;
doen : std_ulogic; -- Data output enable to pad
end record;
constant gracectrl_none : gracectrl_out_type :=
((others => '1'), (others => '1'), '1', '1', '1', '1');
component gracectrl
generic (
hindex : integer := 0; -- AHB slave index
hirq : integer := 0; -- Interrupt line
haddr : integer := 16#000#; -- Base address
hmask : integer := 16#fff#; -- Area mask
split : integer range 0 to 1 := 0; -- Enable AMBA SPLIT support
swap : integer range 0 to 1 := 0;
oepol : integer range 0 to 1 := 0; -- Output enable polarity
mode : integer range 0 to 2 := 0 -- 16/8-bit mode
);
port (
rstn : in std_ulogic;
clk : in std_ulogic;
clkace : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
acei : in gracectrl_in_type;
aceo : out gracectrl_out_type
);
end component;
-----------------------------------------------------------------------------
-- General purpose register
-----------------------------------------------------------------------------
component grgpreg is
generic (
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
nbits : integer range 1 to 64 := 16;
rstval : integer := 0;
rstval2 : integer := 0;
extrst : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
gprego : out std_logic_vector(nbits-1 downto 0);
resval : in std_logic_vector(nbits-1 downto 0) := (others => '0')
);
end component;
component grgprbank is
generic (
pindex: integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
regbits: integer range 1 to 32 := 32;
nregs : integer range 1 to 32 := 1;
rstval: integer := 0;
extrst: integer := 0;
rdataen: integer := 0;
wproten: integer := 0;
partrstmsk: integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
rego : out std_logic_vector(nregs*regbits-1 downto 0);
resval : in std_logic_vector(nregs*regbits-1 downto 0) := (others => '0');
rdata : in std_logic_vector(nregs*regbits-1 downto 0) := (others => '0');
wprot : in std_logic_vector(nregs-1 downto 0) := (others => '0');
partrst : in std_ulogic := '1'
);
end component;
-----------------------------------------------------------------------------
-- EDAC Memory scrubber
-----------------------------------------------------------------------------
type memscrub_in_type is record
cerror : std_logic_vector(0 to NAHBSLV-1);
clrcount: std_logic;
start : std_logic;
end record;
component memscrub is
generic(
hmindex : integer := 0;
hsindex : integer := 0;
ioaddr : integer := 0;
iomask : integer := 16#FFF#;
hirq : integer := 0;
nftslv : integer range 1 to NAHBSLV - 1 := 3;
memwidth: integer := AHBDW;
-- Read block (cache line) burst size, must be even mult of 2
burstlen: integer := 2;
countlen: integer := 8
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
scrubi: in memscrub_in_type
);
end component;
type ahb_mst_iface_in_type is record
req : std_ulogic;
write : std_ulogic;
addr : std_logic_vector(31 downto 0);
data : std_logic_vector(31 downto 0);
size : std_logic_vector(1 downto 0);
end record;
type ahb_mst_iface_out_type is record
grant : std_ulogic;
ready : std_ulogic;
error : std_ulogic;
retry : std_ulogic;
data : std_logic_vector(31 downto 0);
end record;
component ahb_mst_iface is
generic(
hindex : integer;
vendor : integer;
device : integer;
revision : integer);
port(
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type;
msti : in ahb_mst_iface_in_type;
msto : out ahb_mst_iface_out_type
);
end component;
-----------------------------------------------------------------------------
-- Clock gate unit
-----------------------------------------------------------------------------
component grclkgate
generic (
tech : integer := 0;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
ncpu : integer := 1;
nclks : integer := 8;
emask : integer := 0;
extemask : integer := 0;
scantest : integer := 0;
edges : integer := 0;
noinv : integer := 0; -- Do not use inverted clock on gate enable
fpush : integer range 0 to 2 := 0;
ungateen : integer := 0);
port (
rst : in std_ulogic;
clkin : in std_ulogic;
pwd : in std_logic_vector(ncpu-1 downto 0);
fpen : in std_logic_vector(ncpu-1 downto 0); -- Only used with shared FPU
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
gclk : out std_logic_vector(nclks-1 downto 0);
reset : out std_logic_vector(nclks-1 downto 0);
clkahb : out std_ulogic;
clkcpu : out std_logic_vector(ncpu-1 downto 0);
enable : out std_logic_vector(nclks-1 downto 0);
clkfpu : out std_logic_vector((fpush/2)*(ncpu/2-1) downto 0); -- Only used with shared FPU
epwen : in std_logic_vector(nclks-1 downto 0);
ungate : in std_ulogic);
end component;
component grclkgate2x
generic (
tech : integer := 0;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
ncpu : integer := 1;
nclks : integer := 8;
emask : integer := 0;
extemask : integer := 0;
scantest : integer := 0;
edges : integer := 0;
noinv : integer := 0; -- Do not use inverted clock on gate enable
fpush : integer range 0 to 2 := 0;
clk2xen : integer := 0; -- Enable double clocking
ungateen : integer := 0;
fpuclken : integer := 0;
nahbclk : integer := 1;
nahbclk2x: integer := 1;
balance : integer range 0 to 1 := 1
);
port (
rst : in std_ulogic;
clkin : in std_ulogic;
clkin2x : in std_ulogic;
pwd : in std_logic_vector(ncpu-1 downto 0);
fpen : in std_logic_vector(ncpu-1 downto 0);
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
gclk : out std_logic_vector(nclks-1 downto 0);
reset : out std_logic_vector(nclks-1 downto 0);
clkahb : out std_logic_vector(nahbclk-1 downto 0);
clkahb2x : out std_logic_vector(nahbclk2x-1 downto 0);
clkcpu : out std_logic_vector(ncpu-1 downto 0);
enable : out std_logic_vector(nclks-1 downto 0);
clkfpu : out std_logic_vector((fpush/2+fpuclken)*(ncpu/(2-fpuclken)-1) downto 0);
epwen : in std_logic_vector(nclks-1 downto 0);
ungate : in std_ulogic
);
end component;
component grclkgatex
generic (
tech : integer := 0;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
ncpu : integer := 1;
nclks : integer := 8;
emask : integer := 0;
extemask : integer := 0;
scantest : integer := 0;
edges : integer := 0;
noinv : integer := 0; -- Do not use inverted clock on gate enable
fpush : integer range 0 to 2 := 0;
clk2xen : integer := 0; -- Enable double clocking
ungateen : integer := 0;
fpuclken : integer := 0;
nahbclk : integer := 1;
nahbclk2x: integer := 1;
balance : integer range 0 to 1 := 1
);
port (
rst : in std_ulogic;
clkin : in std_ulogic;
clkin2x : in std_ulogic;
pwd : in std_logic_vector(ncpu-1 downto 0);
fpen : in std_logic_vector(ncpu-1 downto 0);
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
gclk : out std_logic_vector(nclks-1 downto 0);
reset : out std_logic_vector(nclks-1 downto 0);
clkahb : out std_logic_vector(nahbclk-1 downto 0);
clkahb2x : out std_logic_vector(nahbclk2x-1 downto 0);
clkcpu : out std_logic_vector(ncpu-1 downto 0);
enable : out std_logic_vector(nclks-1 downto 0);
clkfpu : out std_logic_vector((fpush/2+fpuclken)*(ncpu/(2-fpuclken)-1) downto 0);
epwen : in std_logic_vector(nclks-1 downto 0);
ungate : in std_ulogic
);
end component;
component ahbwbax is
generic (
ahbbits: integer;
blocksz: integer := 16;
mstmode: integer := 0
);
port (
clk: in std_ulogic;
rst: in std_ulogic;
-- Wide-side slave inputs
wi_hready: in std_ulogic;
wi_hsel: in std_ulogic;
wi_htrans: in std_logic_vector(1 downto 0);
wi_hsize: in std_logic_vector(2 downto 0);
wi_hburst: in std_logic_vector(2 downto 0);
wi_hwrite: in std_ulogic;
wi_haddr: in std_logic_vector(31 downto 0);
wi_hwdata: in std_logic_vector(AHBDW-1 downto 0);
wi_hmbsel: in std_logic_vector(0 to NAHBAMR-1);
wi_hmaster: in std_logic_vector(3 downto 0);
wi_hprot: in std_logic_vector(3 downto 0);
wi_hmastlock: in std_ulogic;
-- Wide-side slave outputs
wo_hready: out std_ulogic;
wo_hresp : out std_logic_vector(1 downto 0);
wo_hrdata: out std_logic_vector(AHBDW-1 downto 0);
-- Narrow-side slave inputs
ni_hready: out std_ulogic;
ni_htrans: out std_logic_vector(1 downto 0);
ni_hsize: out std_logic_vector(2 downto 0);
ni_hburst: out std_logic_vector(2 downto 0);
ni_hwrite: out std_ulogic;
ni_haddr: out std_logic_vector(31 downto 0);
ni_hwdata: out std_logic_vector(31 downto 0);
ni_hmbsel: out std_logic_vector(0 to NAHBAMR-1);
ni_hmaster: out std_logic_vector(3 downto 0);
ni_hprot : out std_logic_vector(3 downto 0);
ni_hmastlock: out std_ulogic;
-- Narrow-side slave outputs
no_hready: in std_ulogic;
no_hresp: in std_logic_vector(1 downto 0);
no_hrdata: in std_logic_vector(31 downto 0)
);
end component;
component ahbswba is
generic (
hindex: integer;
ahbbits: integer;
blocksz: integer := 16
);
port (
clk: in std_ulogic;
rst: in std_ulogic;
ahbsi_bus: in ahb_slv_in_type;
ahbso_bus: out ahb_slv_out_type;
ahbsi_slv: out ahb_slv_in_type;
ahbso_slv: in ahb_slv_out_type
);
end component;
component ahbswbav is
generic (
slvmask: integer;
ahbbits: integer;
blocksz: integer
);
port (
clk: in std_ulogic;
rst: in std_ulogic;
ahbsi_bus: in ahb_slv_in_type;
ahbso_bus: out ahb_slv_out_vector;
ahbsi_slv: out ahb_slv_in_vector_type(NAHBSLV-1 downto 0);
ahbso_slv: in ahb_slv_out_vector
);
end component;
component ahbmwba is
generic (
hindex: integer;
ahbbits: integer;
blocksz: integer := 16
);
port (
clk: in std_ulogic;
rst: in std_ulogic;
ahbmo_mst : in ahb_mst_out_type;
ahbmi_mst: out ahb_mst_in_type;
ahbmo_bus: out ahb_mst_out_type;
ahbmi_bus: in ahb_mst_in_type
);
end component;
component ahbpl is
generic (
ahbbits: integer;
blocksz: integer := 16;
prefmask: integer := 16#ffff#;
wrretry: integer range 0 to 2 := 2
);
port (
clk: in std_ulogic;
rst: in std_ulogic;
-- Bus-side slave inputs
bi_hready: in std_ulogic;
bi_hsel: in std_ulogic;
bi_htrans: in std_logic_vector(1 downto 0);
bi_hsize: in std_logic_vector(2 downto 0);
bi_hburst: in std_logic_vector(2 downto 0);
bi_hwrite: in std_ulogic;
bi_haddr: in std_logic_vector(31 downto 0);
bi_hwdata: in std_logic_vector(ahbbits-1 downto 0);
bi_hmbsel: in std_logic_vector(0 to NAHBAMR-1);
bi_hmaster: in std_logic_vector(3 downto 0);
bi_hprot: in std_logic_vector(3 downto 0);
bi_hmastlock: in std_ulogic;
-- Bus-side slave outputs
bo_hready: out std_ulogic;
bo_hresp : out std_logic_vector(1 downto 0);
bo_hrdata: out std_logic_vector(ahbbits-1 downto 0);
-- Slave-side slave inputs
si_hready: out std_ulogic;
si_htrans: out std_logic_vector(1 downto 0);
si_hsize: out std_logic_vector(2 downto 0);
si_hburst: out std_logic_vector(2 downto 0);
si_hwrite: out std_ulogic;
si_haddr: out std_logic_vector(31 downto 0);
si_hwdata: out std_logic_vector(ahbbits-1 downto 0);
si_hmbsel: out std_logic_vector(0 to NAHBAMR-1);
si_hmaster: out std_logic_vector(3 downto 0);
si_hprot : out std_logic_vector(3 downto 0);
si_hmastlock: out std_ulogic;
-- Slave-side slave outputs
so_hready: in std_ulogic;
so_hresp: in std_logic_vector(1 downto 0);
so_hrdata: in std_logic_vector(ahbbits-1 downto 0);
-- For use in master mode
mi_hgrant: in std_ulogic;
mo_hbusreq: out std_ulogic
);
end component;
component ahbpls is
generic (
hindex: integer;
ahbbits: integer;
blocksz: integer := 16;
prefmask: integer := 16#ffff#
);
port (
clk: in std_ulogic;
rst: in std_ulogic;
bi: in ahb_slv_in_type;
bo: out ahb_slv_out_type;
si: out ahb_slv_in_type;
so: in ahb_slv_out_type
);
end component;
component ahbplm is
generic (
hindex: integer;
ahbbits: integer;
blocksz: integer := 16;
prefmask: integer := 16#ffff#
);
port (
clk: in std_ulogic;
rst: in std_ulogic;
mi: out ahb_mst_in_type;
mo: in ahb_mst_out_type;
bi: in ahb_mst_in_type;
bo: out ahb_mst_out_type
);
end component;
-----------------------------------------------------------------------------
-- GRPULSE
-----------------------------------------------------------------------------
component grpulse
generic (
pindex: Integer := 0;
paddr: Integer := 0;
pmask: Integer := 16#fff#;
pirq: Integer := 1; -- Interrupt index
nchannel: Integer := 24; -- Number of channels
npulse: Integer := 8; -- Channels with pulses
imask: Integer := 16#ff0000#; -- Interrupt mask
ioffset: Integer := 8; -- Interrupt offset
invertpulse: Integer := 0; -- Invert pulses
cntrwidth: Integer := 10; -- Width of counter
syncrst: Integer := 1; -- Only synchronous reset
oepol: Integer := 1); -- Output enable polarity
port (
rstn: in Std_ULogic;
clk: in Std_ULogic;
apbi: in apb_slv_in_type;
apbo: out apb_slv_out_type;
gpioi: in gpio_in_type;
gpioo: out gpio_out_type);
end component;
-----------------------------------------------------------------------------
-- GRTIMER
-----------------------------------------------------------------------------
component grtimer is
generic (
pindex: Integer := 0;
paddr: Integer := 0;
pmask: Integer := 16#fff#;
pirq: Integer := 1;
sepirq: Integer := 1; -- separate interrupts
sbits: Integer := 10; -- scaler bits
ntimers: Integer range 1 to 7 := 2; -- number of timers
nbits: Integer := 32; -- timer bits
wdog: Integer := 0;
glatch: Integer := 0;
gextclk: Integer := 0;
gset: Integer := 0);
port (
rst: in Std_ULogic;
clk: in Std_ULogic;
apbi: in apb_slv_in_type;
apbo: out apb_slv_out_type;
gpti: in gptimer_in_type;
gpto: out gptimer_out_type);
end component;
-----------------------------------------------------------------------------
-- GRVERSION
-----------------------------------------------------------------------------
component grversion
generic (
pindex: Integer := 0;
paddr: Integer := 0;
pmask: Integer := 16#fff#;
versionnr: Integer := 16#0123#;
revisionnr: Integer := 16#4567#);
port (
rstn: in Std_ULogic;
clk: in Std_ULogic;
apbi: in APB_Slv_In_Type;
apbo: out APB_Slv_Out_Type);
end component;
-----------------------------------------------------------------------------
-- AHBFROM - Microsemi/Actel Flash ROM
-----------------------------------------------------------------------------
component ahbfrom is
generic (
tech: integer := 0;
hindex: integer := 0;
haddr: integer := 0;
hmask: integer := 16#fff#;
width8: integer := 0;
memoryfile: string := "from.mem";
progfile: string := "from.ufc");
port (
rstn: in std_ulogic;
clk: in std_ulogic;
ahbi: in ahb_slv_in_type;
ahbo: out ahb_slv_out_type);
end component;
-----------------------------------------------------------------------------
-- Interrupt generator
-----------------------------------------------------------------------------
component irqgen
generic (
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
ngen : integer range 1 to 15 := 1
);
port (
rstn : in std_ulogic;
clk : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type
);
end component;
-----------------------------------------------------------------------------
-- Function declarations
-----------------------------------------------------------------------------
-- function nandtree(v : std_logic_vector) return std_ulogic;
end;
package body misc is
function gpti_dhalt_drive (dhalt : std_ulogic) return gptimer_in_type is
variable gpti : gptimer_in_type;
begin
gpti := (dhalt, '0', '0', zxirq, zxirq);
return gpti;
end;
function ahb2ahb_membar(memaddr : ahb_addr_type; prefetch, cache : std_ulogic;
addrmask : ahb_addr_type)
return integer is
variable tmp : std_logic_vector(29 downto 0);
variable bar : std_logic_vector(31 downto 0);
variable res : integer range 0 to 1073741823;
begin
bar := ahb_membar(memaddr, prefetch, cache, addrmask);
tmp := (others => '0');
tmp(29 downto 18) := bar(31 downto 20);
tmp(17 downto 0) := bar(17 downto 0);
res := conv_integer(tmp);
return(res);
end;
function ahb2ahb_iobar(memaddr : ahb_addr_type; addrmask : ahb_addr_type)
return integer is
variable tmp : std_logic_vector(29 downto 0);
variable bar : std_logic_vector(31 downto 0);
variable res : integer range 0 to 1073741823;
begin
bar := ahb_iobar(memaddr, addrmask);
tmp := (others => '0');
tmp(29 downto 18) := bar(31 downto 20);
tmp(17 downto 0) := bar(17 downto 0);
res := conv_integer(tmp);
return(res);
end;
-- function nandtree(v : std_logic_vector) return std_ulogic is
-- variable a : std_logic_vector(v'length-1 downto 0);
-- variable b : std_logic_vector(v'length downto 0);
-- begin
--
-- a := v; b(0) := '1';
--
-- for i in 0 to v'length-1 loop
-- b(i+1) := a(i) nand b(i);
-- end loop;
--
-- return b(v'length);
--
-- end;
end;
| gpl-3.0 |
EliasLuiz/TCC | Leon3/lib/spw/comp/spwcomp.vhd | 1 | 31506 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package spwcomp is
component grspwc2 is
generic(
rmap : integer range 0 to 2 := 0;
rmapcrc : integer range 0 to 1 := 0;
fifosize1 : integer range 4 to 64 := 32;
fifosize2 : integer range 16 to 64 := 64;
rxunaligned : integer range 0 to 1 := 0;
rmapbufs : integer range 2 to 8 := 4;
scantest : integer range 0 to 1 := 0;
ports : integer range 1 to 2 := 1;
dmachan : integer range 1 to 4 := 1;
tech : integer;
input_type : integer range 0 to 4 := 0;
output_type : integer range 0 to 2 := 0;
rxtx_sameclk : integer range 0 to 1 := 0;
nodeaddr : integer range 0 to 255 := 254;
destkey : integer range 0 to 255 := 0;
interruptdist : integer range 0 to 32 := 0;
intscalerbits : integer range 0 to 31 := 0;
intisrtimerbits : integer range 0 to 31 := 0;
intiatimerbits : integer range 0 to 31 := 0;
intctimerbits : integer range 0 to 31 := 0;
tickinasync : integer range 0 to 1 := 0;
pnp : integer range 0 to 2 := 0;
pnpvendid : integer range 0 to 16#FFFF# := 0;
pnpprodid : integer range 0 to 16#FFFF# := 0;
pnpmajorver : integer range 0 to 16#FF# := 0;
pnpminorver : integer range 0 to 16#FF# := 0;
pnppatch : integer range 0 to 16#FF# := 0;
num_txdesc : integer range 64 to 512 := 64;
num_rxdesc : integer range 128 to 1024 := 128
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
rxclk0 : in std_ulogic;
rxclk1 : in std_ulogic;
txclk : in std_ulogic;
txclkn : in std_ulogic;
--ahb mst in
hgrant : in std_ulogic;
hready : in std_ulogic;
hresp : in std_logic_vector(1 downto 0);
hrdata : in std_logic_vector(31 downto 0);
--ahb mst out
hbusreq : out std_ulogic;
hlock : out std_ulogic;
htrans : out std_logic_vector(1 downto 0);
haddr : out std_logic_vector(31 downto 0);
hwrite : out std_ulogic;
hsize : out std_logic_vector(2 downto 0);
hburst : out std_logic_vector(2 downto 0);
hprot : out std_logic_vector(3 downto 0);
hwdata : out std_logic_vector(31 downto 0);
--apb slv in
psel : in std_ulogic;
penable : in std_ulogic;
paddr : in std_logic_vector(31 downto 0);
pwrite : in std_ulogic;
pwdata : in std_logic_vector(31 downto 0);
--apb slv out
prdata : out std_logic_vector(31 downto 0);
--spw in
d : in std_logic_vector(3 downto 0);
dv : in std_logic_vector(3 downto 0);
dconnect : in std_logic_vector(3 downto 0);
--spw out
do : out std_logic_vector(3 downto 0);
so : out std_logic_vector(3 downto 0);
--time iface
tickin : in std_ulogic;
tickinraw : in std_ulogic;
timein : in std_logic_vector(7 downto 0);
tickindone : out std_ulogic;
tickout : out std_ulogic;
tickoutraw : out std_ulogic;
timeout : out std_logic_vector(7 downto 0);
--irq
irq : out std_logic;
--misc
clkdiv10 : in std_logic_vector(7 downto 0);
--rmapen
rmapen : in std_ulogic;
rmapnodeaddr : in std_logic_vector(7 downto 0);
--rx ahb fifo
rxrenable : out std_ulogic;
rxraddress : out std_logic_vector(5 downto 0);
rxwrite : out std_ulogic;
rxwdata : out std_logic_vector(31 downto 0);
rxwaddress : out std_logic_vector(5 downto 0);
rxrdata : in std_logic_vector(31 downto 0);
--tx ahb fifo
txrenable : out std_ulogic;
txraddress : out std_logic_vector(5 downto 0);
txwrite : out std_ulogic;
txwdata : out std_logic_vector(31 downto 0);
txwaddress : out std_logic_vector(5 downto 0);
txrdata : in std_logic_vector(31 downto 0);
--nchar fifo
ncrenable : out std_ulogic;
ncraddress : out std_logic_vector(5 downto 0);
ncwrite : out std_ulogic;
ncwdata : out std_logic_vector(9 downto 0);
ncwaddress : out std_logic_vector(5 downto 0);
ncrdata : in std_logic_vector(9 downto 0);
--rmap buf
rmrenable : out std_ulogic;
rmraddress : out std_logic_vector(7 downto 0);
rmwrite : out std_ulogic;
rmwdata : out std_logic_vector(7 downto 0);
rmwaddress : out std_logic_vector(7 downto 0);
rmrdata : in std_logic_vector(7 downto 0);
linkdis : out std_ulogic;
testrst : in std_ulogic := '0';
testen : in std_ulogic := '0';
--parallel rx data out
rxdav : out std_ulogic;
rxdataout : out std_logic_vector(8 downto 0);
loopback : out std_ulogic;
-- interrupt dist. default values
intpreload : in std_logic_vector(30 downto 0);
inttreload : in std_logic_vector(30 downto 0);
intiareload : in std_logic_vector(30 downto 0);
intcreload : in std_logic_vector(30 downto 0);
irqtxdefault : in std_logic_vector(4 downto 0);
-- SpW PnP enable
pnpen : in std_ulogic;
pnpuvendid : in std_logic_vector(15 downto 0);
pnpuprodid : in std_logic_vector(15 downto 0);
pnpusn : in std_logic_vector(31 downto 0)
);
end component;
component grspwc is
generic(
sysfreq : integer := 40000;
usegen : integer range 0 to 1 := 1;
nsync : integer range 1 to 2 := 1;
rmap : integer range 0 to 2 := 0;
rmapcrc : integer range 0 to 1 := 0;
fifosize1 : integer range 4 to 32 := 32;
fifosize2 : integer range 16 to 64 := 64;
rxunaligned : integer range 0 to 1 := 0;
rmapbufs : integer range 2 to 8 := 4;
scantest : integer range 0 to 1 := 0;
ports : integer range 1 to 2 := 1;
tech : integer;
nodeaddr : integer range 0 to 255 := 254;
destkey : integer range 0 to 255 := 0
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
txclk : in std_ulogic;
--ahb mst in
hgrant : in std_ulogic;
hready : in std_ulogic;
hresp : in std_logic_vector(1 downto 0);
hrdata : in std_logic_vector(31 downto 0);
--ahb mst out
hbusreq : out std_ulogic;
hlock : out std_ulogic;
htrans : out std_logic_vector(1 downto 0);
haddr : out std_logic_vector(31 downto 0);
hwrite : out std_ulogic;
hsize : out std_logic_vector(2 downto 0);
hburst : out std_logic_vector(2 downto 0);
hprot : out std_logic_vector(3 downto 0);
hwdata : out std_logic_vector(31 downto 0);
--apb slv in
psel : in std_ulogic;
penable : in std_ulogic;
paddr : in std_logic_vector(31 downto 0);
pwrite : in std_ulogic;
pwdata : in std_logic_vector(31 downto 0);
--apb slv out
prdata : out std_logic_vector(31 downto 0);
--spw in
d : in std_logic_vector(1 downto 0);
nd : in std_logic_vector(9 downto 0);
dconnect : in std_logic_vector(3 downto 0);
--spw out
do : out std_logic_vector(1 downto 0);
so : out std_logic_vector(1 downto 0);
rxrsto : out std_ulogic;
--time iface
tickin : in std_ulogic;
tickout : out std_ulogic;
--irq
irq : out std_logic;
--misc
clkdiv10 : in std_logic_vector(7 downto 0);
dcrstval : in std_logic_vector(9 downto 0);
timerrstval : in std_logic_vector(11 downto 0);
--rmapen
rmapen : in std_ulogic;
rmapnodeaddr : in std_logic_vector(7 downto 0);
--clk bufs
rxclki : in std_logic_vector(1 downto 0);
--rx ahb fifo
rxrenable : out std_ulogic;
rxraddress : out std_logic_vector(4 downto 0);
rxwrite : out std_ulogic;
rxwdata : out std_logic_vector(31 downto 0);
rxwaddress : out std_logic_vector(4 downto 0);
rxrdata : in std_logic_vector(31 downto 0);
--tx ahb fifo
txrenable : out std_ulogic;
txraddress : out std_logic_vector(4 downto 0);
txwrite : out std_ulogic;
txwdata : out std_logic_vector(31 downto 0);
txwaddress : out std_logic_vector(4 downto 0);
txrdata : in std_logic_vector(31 downto 0);
--nchar fifo
ncrenable : out std_ulogic;
ncraddress : out std_logic_vector(5 downto 0);
ncwrite : out std_ulogic;
ncwdata : out std_logic_vector(8 downto 0);
ncwaddress : out std_logic_vector(5 downto 0);
ncrdata : in std_logic_vector(8 downto 0);
--rmap buf
rmrenable : out std_ulogic;
rmraddress : out std_logic_vector(7 downto 0);
rmwrite : out std_ulogic;
rmwdata : out std_logic_vector(7 downto 0);
rmwaddress : out std_logic_vector(7 downto 0);
rmrdata : in std_logic_vector(7 downto 0);
linkdis : out std_ulogic;
testclk : in std_ulogic := '0';
testrst : in std_ulogic := '0';
testen : in std_ulogic := '0';
rmapact : out std_ulogic
);
end component;
component grspwc_axcelerator is
port(
rst : in std_ulogic;
clk : in std_ulogic;
txclk : in std_ulogic;
--ahb mst in
hgrant : in std_ulogic;
hready : in std_ulogic;
hresp : in std_logic_vector(1 downto 0);
hrdata : in std_logic_vector(31 downto 0);
--ahb mst out
hbusreq : out std_ulogic;
hlock : out std_ulogic;
htrans : out std_logic_vector(1 downto 0);
haddr : out std_logic_vector(31 downto 0);
hwrite : out std_ulogic;
hsize : out std_logic_vector(2 downto 0);
hburst : out std_logic_vector(2 downto 0);
hprot : out std_logic_vector(3 downto 0);
hwdata : out std_logic_vector(31 downto 0);
--apb slv in
psel : in std_ulogic;
penable : in std_ulogic;
paddr : in std_logic_vector(31 downto 0);
pwrite : in std_ulogic;
pwdata : in std_logic_vector(31 downto 0);
--apb slv out
prdata : out std_logic_vector(31 downto 0);
--spw in
d : in std_logic_vector(1 downto 0);
nd : in std_logic_vector(1 downto 0);
--spw out
do : out std_logic_vector(1 downto 0);
so : out std_logic_vector(1 downto 0);
rxrsto : out std_ulogic;
--time iface
tickin : in std_ulogic;
tickout : out std_ulogic;
--irq
irq : out std_logic;
--misc
clkdiv10 : in std_logic_vector(7 downto 0);
dcrstval : in std_logic_vector(9 downto 0);
timerrstval : in std_logic_vector(11 downto 0);
--rmapen
rmapen : in std_ulogic;
rmapnodeaddr : in std_logic_vector(7 downto 0);
--clk bufs
rxclki : in std_logic_vector(1 downto 0);
--rx ahb fifo
rxrenable : out std_ulogic;
rxraddress : out std_logic_vector(4 downto 0);
rxwrite : out std_ulogic;
rxwdata : out std_logic_vector(31 downto 0);
rxwaddress : out std_logic_vector(4 downto 0);
rxrdata : in std_logic_vector(31 downto 0);
--tx ahb fifo
txrenable : out std_ulogic;
txraddress : out std_logic_vector(4 downto 0);
txwrite : out std_ulogic;
txwdata : out std_logic_vector(31 downto 0);
txwaddress : out std_logic_vector(4 downto 0);
txrdata : in std_logic_vector(31 downto 0);
--nchar fifo
ncrenable : out std_ulogic;
ncraddress : out std_logic_vector(5 downto 0);
ncwrite : out std_ulogic;
ncwdata : out std_logic_vector(8 downto 0);
ncwaddress : out std_logic_vector(5 downto 0);
ncrdata : in std_logic_vector(8 downto 0);
--rmap buf
rmrenable : out std_ulogic;
rmraddress : out std_logic_vector(7 downto 0);
rmwrite : out std_ulogic;
rmwdata : out std_logic_vector(7 downto 0);
rmwaddress : out std_logic_vector(7 downto 0);
rmrdata : in std_logic_vector(7 downto 0);
linkdis : out std_ulogic;
testclk : in std_ulogic := '0';
testrst : in std_ulogic := '0';
testen : in std_ulogic := '0'
);
end component;
component grspwc_unisim is
port(
rst : in std_ulogic;
clk : in std_ulogic;
txclk : in std_ulogic;
--ahb mst in
hgrant : in std_ulogic;
hready : in std_ulogic;
hresp : in std_logic_vector(1 downto 0);
hrdata : in std_logic_vector(31 downto 0);
--ahb mst out
hbusreq : out std_ulogic;
hlock : out std_ulogic;
htrans : out std_logic_vector(1 downto 0);
haddr : out std_logic_vector(31 downto 0);
hwrite : out std_ulogic;
hsize : out std_logic_vector(2 downto 0);
hburst : out std_logic_vector(2 downto 0);
hprot : out std_logic_vector(3 downto 0);
hwdata : out std_logic_vector(31 downto 0);
--apb slv in
psel : in std_ulogic;
penable : in std_ulogic;
paddr : in std_logic_vector(31 downto 0);
pwrite : in std_ulogic;
pwdata : in std_logic_vector(31 downto 0);
--apb slv out
prdata : out std_logic_vector(31 downto 0);
--spw in
d : in std_logic_vector(1 downto 0);
nd : in std_logic_vector(1 downto 0);
--spw out
do : out std_logic_vector(1 downto 0);
so : out std_logic_vector(1 downto 0);
rxrsto : out std_ulogic;
--time iface
tickin : in std_ulogic;
tickout : out std_ulogic;
--irq
irq : out std_logic;
--misc
clkdiv10 : in std_logic_vector(7 downto 0);
dcrstval : in std_logic_vector(9 downto 0);
timerrstval : in std_logic_vector(11 downto 0);
--rmapen
rmapen : in std_ulogic;
rmapnodeaddr : in std_logic_vector(7 downto 0);
--clk bufs
rxclki : in std_logic_vector(1 downto 0);
--rx ahb fifo
rxrenable : out std_ulogic;
rxraddress : out std_logic_vector(4 downto 0);
rxwrite : out std_ulogic;
rxwdata : out std_logic_vector(31 downto 0);
rxwaddress : out std_logic_vector(4 downto 0);
rxrdata : in std_logic_vector(31 downto 0);
--tx ahb fifo
txrenable : out std_ulogic;
txraddress : out std_logic_vector(4 downto 0);
txwrite : out std_ulogic;
txwdata : out std_logic_vector(31 downto 0);
txwaddress : out std_logic_vector(4 downto 0);
txrdata : in std_logic_vector(31 downto 0);
--nchar fifo
ncrenable : out std_ulogic;
ncraddress : out std_logic_vector(5 downto 0);
ncwrite : out std_ulogic;
ncwdata : out std_logic_vector(8 downto 0);
ncwaddress : out std_logic_vector(5 downto 0);
ncrdata : in std_logic_vector(8 downto 0);
--rmap buf
rmrenable : out std_ulogic;
rmraddress : out std_logic_vector(7 downto 0);
rmwrite : out std_ulogic;
rmwdata : out std_logic_vector(7 downto 0);
rmwaddress : out std_logic_vector(7 downto 0);
rmrdata : in std_logic_vector(7 downto 0);
linkdis : out std_ulogic;
testclk : in std_ulogic := '0';
testrst : in std_ulogic := '0';
testen : in std_ulogic := '0'
);
end component;
component grspw_gen is
generic(
tech : integer := 0;
sysfreq : integer := 10000;
usegen : integer range 0 to 1 := 1;
nsync : integer range 1 to 2 := 1;
rmap : integer range 0 to 2 := 0;
rmapcrc : integer range 0 to 1 := 0;
fifosize1 : integer range 4 to 32 := 32;
fifosize2 : integer range 16 to 64 := 64;
rxclkbuftype : integer range 0 to 2 := 0;
rxunaligned : integer range 0 to 1 := 0;
rmapbufs : integer range 2 to 8 := 4;
ft : integer range 0 to 2 := 0;
scantest : integer range 0 to 1 := 0;
techfifo : integer range 0 to 1 := 1;
ports : integer range 1 to 2 := 1;
memtech : integer := 0;
nodeaddr : integer range 0 to 255 := 254;
destkey : integer range 0 to 255 := 0
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
txclk : in std_ulogic;
rxclk : in std_logic_vector(1 downto 0);
--ahb mst in
hgrant : in std_ulogic;
hready : in std_ulogic;
hresp : in std_logic_vector(1 downto 0);
hrdata : in std_logic_vector(31 downto 0);
--ahb mst out
hbusreq : out std_ulogic;
hlock : out std_ulogic;
htrans : out std_logic_vector(1 downto 0);
haddr : out std_logic_vector(31 downto 0);
hwrite : out std_ulogic;
hsize : out std_logic_vector(2 downto 0);
hburst : out std_logic_vector(2 downto 0);
hprot : out std_logic_vector(3 downto 0);
hwdata : out std_logic_vector(31 downto 0);
--apb slv in
psel : in std_ulogic;
penable : in std_ulogic;
paddr : in std_logic_vector(31 downto 0);
pwrite : in std_ulogic;
pwdata : in std_logic_vector(31 downto 0);
--apb slv out
prdata : out std_logic_vector(31 downto 0);
--spw in
d : in std_logic_vector(1 downto 0);
nd : in std_logic_vector(9 downto 0);
dconnect : in std_logic_vector(3 downto 0);
--spw out
do : out std_logic_vector(1 downto 0);
so : out std_logic_vector(1 downto 0);
rxrsto : out std_ulogic;
--time iface
tickin : in std_ulogic;
tickout : out std_ulogic;
--irq
irq : out std_logic;
--misc
clkdiv10 : in std_logic_vector(7 downto 0);
dcrstval : in std_logic_vector(9 downto 0);
timerrstval : in std_logic_vector(11 downto 0);
--rmapen
rmapen : in std_ulogic;
rmapnodeaddr : in std_logic_vector(7 downto 0);
linkdis : out std_ulogic;
testclk : in std_ulogic := '0';
testrst : in std_ulogic := '0';
testen : in std_ulogic := '0'
);
end component;
component grspw_codec_core is
generic(
ports : integer range 1 to 2 := 1;
input_type : integer range 0 to 4 := 0;
output_type : integer range 0 to 2 := 0;
rxtx_sameclk : integer range 0 to 1 := 0;
fifosize : integer range 16 to 2048 := 64;
tech : integer;
scantest : integer range 0 to 1 := 0;
inputtest : integer range 0 to 1 := 0
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
rxclk0 : in std_ulogic;
rxclk1 : in std_ulogic;
txclk : in std_ulogic;
txclkn : in std_ulogic;
testen : in std_ulogic;
testrst : in std_ulogic;
--spw in
d : in std_logic_vector(3 downto 0);
dv : in std_logic_vector(3 downto 0);
dconnect : in std_logic_vector(3 downto 0);
--spw out
do : out std_logic_vector(3 downto 0);
so : out std_logic_vector(3 downto 0);
--link fsm
linkdisabled : in std_ulogic;
linkstart : in std_ulogic;
autostart : in std_ulogic;
portsel : in std_ulogic;
noportforce : in std_ulogic;
rdivisor : in std_logic_vector(7 downto 0);
idivisor : in std_logic_vector(7 downto 0);
state : out std_logic_vector(2 downto 0);
actport : out std_ulogic;
dconnecterr : out std_ulogic;
crederr : out std_ulogic;
escerr : out std_ulogic;
parerr : out std_ulogic;
--rx fifo signals
rxrenable : out std_ulogic;
rxraddress : out std_logic_vector(10 downto 0);
rxwrite : out std_ulogic;
rxwdata : out std_logic_vector(9 downto 0);
rxwaddress : out std_logic_vector(10 downto 0);
rxrdata : in std_logic_vector(9 downto 0);
rxaccess : out std_ulogic;
--rx iface
rxicharav : out std_ulogic;
rxicharcnt : out std_logic_vector(11 downto 0);
rxichar : out std_logic_vector(8 downto 0);
rxiread : in std_ulogic;
rxififorst : in std_ulogic;
--tx fifo signals
txrenable : out std_ulogic;
txraddress : out std_logic_vector(10 downto 0);
txwrite : out std_ulogic;
txwdata : out std_logic_vector(8 downto 0);
txwaddress : out std_logic_vector(10 downto 0);
txrdata : in std_logic_vector(8 downto 0);
txaccess : out std_ulogic;
--tx iface
txicharcnt : out std_logic_vector(11 downto 0);
txifull : out std_ulogic;
txiempty : out std_ulogic;
txiwrite : in std_ulogic;
txichar : in std_logic_vector(8 downto 0);
txififorst : in std_ulogic;
txififorstact: out std_ulogic;
--time iface
tickin : in std_ulogic;
timein : in std_logic_vector(7 downto 0);
tickin_done : out std_ulogic;
tickin_busy : out std_ulogic;
tickout : out std_ulogic;
timeout : out std_logic_vector(7 downto 0);
credcnt : out std_logic_vector(5 downto 0);
ocredcnt : out std_logic_vector(5 downto 0);
--misc
powerdown : out std_ulogic;
powerdownrx : out std_ulogic;
-- input timing testing
testdi : in std_logic_vector(1 downto 0) := "00";
testsi : in std_logic_vector(1 downto 0) := "00";
testinput : in std_ulogic := '0'
);
end component;
component grspw2_gen is
generic(
rmap : integer range 0 to 2 := 0;
rmapcrc : integer range 0 to 1 := 0;
fifosize1 : integer range 4 to 64 := 32;
fifosize2 : integer range 16 to 64 := 64;
rxunaligned : integer range 0 to 1 := 0;
rmapbufs : integer range 2 to 8 := 4;
scantest : integer range 0 to 1 := 0;
ports : integer range 1 to 2 := 1;
dmachan : integer range 1 to 4 := 1;
tech : integer;
input_type : integer range 0 to 4 := 0;
output_type : integer range 0 to 2 := 0;
rxtx_sameclk : integer range 0 to 1 := 0;
ft : integer range 0 to 2 := 0;
techfifo : integer range 0 to 1 := 1;
memtech : integer := 0;
nodeaddr : integer range 0 to 255 := 254;
destkey : integer range 0 to 255 := 0;
interruptdist : integer range 0 to 32 := 0;
intscalerbits : integer range 0 to 31 := 0;
intisrtimerbits : integer range 0 to 31 := 0;
intiatimerbits : integer range 0 to 31 := 0;
intctimerbits : integer range 0 to 31 := 0;
tickinasync : integer range 0 to 1 := 0;
pnp : integer range 0 to 2 := 0;
pnpvendid : integer range 0 to 16#FFFF# := 0;
pnpprodid : integer range 0 to 16#FFFF# := 0;
pnpmajorver : integer range 0 to 16#FF# := 0;
pnpminorver : integer range 0 to 16#FF# := 0;
pnppatch : integer range 0 to 16#FF# := 0;
num_txdesc : integer range 64 to 512 := 64;
num_rxdesc : integer range 128 to 1024 := 128
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
rxclk0 : in std_ulogic;
rxclk1 : in std_ulogic;
txclk : in std_ulogic;
txclkn : in std_ulogic;
--ahb mst in
hgrant : in std_ulogic;
hready : in std_ulogic;
hresp : in std_logic_vector(1 downto 0);
hrdata : in std_logic_vector(31 downto 0);
--ahb mst out
hbusreq : out std_ulogic;
hlock : out std_ulogic;
htrans : out std_logic_vector(1 downto 0);
haddr : out std_logic_vector(31 downto 0);
hwrite : out std_ulogic;
hsize : out std_logic_vector(2 downto 0);
hburst : out std_logic_vector(2 downto 0);
hprot : out std_logic_vector(3 downto 0);
hwdata : out std_logic_vector(31 downto 0);
--apb slv in
psel : in std_ulogic;
penable : in std_ulogic;
paddr : in std_logic_vector(31 downto 0);
pwrite : in std_ulogic;
pwdata : in std_logic_vector(31 downto 0);
--apb slv out
prdata : out std_logic_vector(31 downto 0);
--spw in
d : in std_logic_vector(3 downto 0);
dv : in std_logic_vector(3 downto 0);
dconnect : in std_logic_vector(3 downto 0);
--spw out
do : out std_logic_vector(3 downto 0);
so : out std_logic_vector(3 downto 0);
--time iface
tickin : in std_ulogic;
tickinraw : in std_ulogic;
timein : in std_logic_vector(7 downto 0);
tickindone : out std_ulogic;
tickout : out std_ulogic;
tickoutraw : out std_ulogic;
timeout : out std_logic_vector(7 downto 0);
--irq
irq : out std_logic;
--misc
clkdiv10 : in std_logic_vector(7 downto 0);
linkdis : out std_ulogic;
testrst : in std_ulogic := '0';
testen : in std_ulogic := '0';
--rmapen
rmapen : in std_ulogic;
rmapnodeaddr : in std_logic_vector(7 downto 0);
--parallel rx data out
rxdav : out std_ulogic;
rxdataout : out std_logic_vector(8 downto 0);
loopback : out std_ulogic;
-- interrupt dist. default values
intpreload : in std_logic_vector(30 downto 0);
inttreload : in std_logic_vector(30 downto 0);
intiareload : in std_logic_vector(30 downto 0);
intcreload : in std_logic_vector(30 downto 0);
irqtxdefault : in std_logic_vector(4 downto 0);
-- SpW PnP enable
pnpen : in std_ulogic;
pnpuvendid : in std_logic_vector(15 downto 0);
pnpuprodid : in std_logic_vector(15 downto 0);
pnpusn : in std_logic_vector(31 downto 0)
);
end component;
component grspw_codec_gen is
generic(
ports : integer range 1 to 2 := 1;
input_type : integer range 0 to 4 := 0;
output_type : integer range 0 to 2 := 0;
rxtx_sameclk : integer range 0 to 1 := 0;
fifosize : integer range 16 to 2048 := 64;
tech : integer;
scantest : integer range 0 to 1 := 0;
techfifo : integer range 0 to 1 := 0;
ft : integer range 0 to 2 := 0
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
rxclk0 : in std_ulogic;
rxclk1 : in std_ulogic;
txclk : in std_ulogic;
txclkn : in std_ulogic;
testen : in std_ulogic;
testrst : in std_ulogic;
--spw in
d : in std_logic_vector(3 downto 0);
dv : in std_logic_vector(3 downto 0);
dconnect : in std_logic_vector(3 downto 0);
--spw out
do : out std_logic_vector(3 downto 0);
so : out std_logic_vector(3 downto 0);
--link fsm
linkdisabled : in std_ulogic;
linkstart : in std_ulogic;
autostart : in std_ulogic;
portsel : in std_ulogic;
noportforce : in std_ulogic;
rdivisor : in std_logic_vector(7 downto 0);
idivisor : in std_logic_vector(7 downto 0);
state : out std_logic_vector(2 downto 0);
actport : out std_ulogic;
dconnecterr : out std_ulogic;
crederr : out std_ulogic;
escerr : out std_ulogic;
parerr : out std_ulogic;
--rx iface
rxicharav : out std_ulogic;
rxicharcnt : out std_logic_vector(11 downto 0);
rxichar : out std_logic_vector(8 downto 0);
rxiread : in std_ulogic;
rxififorst : in std_ulogic;
--tx iface
txicharcnt : out std_logic_vector(11 downto 0);
txifull : out std_ulogic;
txiempty : out std_ulogic;
txiwrite : in std_ulogic;
txichar : in std_logic_vector(8 downto 0);
txififorst : in std_ulogic;
txififorstact: out std_ulogic;
--time iface
tickin : in std_ulogic;
timein : in std_logic_vector(7 downto 0);
tickin_done : out std_ulogic;
tickout : out std_ulogic;
timeout : out std_logic_vector(7 downto 0);
--misc
merror : out std_ulogic
);
end component;
end package;
| gpl-3.0 |
EliasLuiz/TCC | Leon3/lib/gaisler/leon3v3/leon3x.vhd | 1 | 15958 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
-- Entity: leon3x
-- File: leon3x.vhd
-- Author: Jiri Gaisler, Jan Andersson, Aeroflex Gaisler
-- Description: Top-level LEON3v3 component with all options
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
use techmap.netcomp.all;
library gaisler;
use gaisler.leon3.all;
use gaisler.libiu.all;
use gaisler.libcache.all;
use gaisler.libleon3.all;
use gaisler.libfpu.all;
use gaisler.arith.all;
entity leon3x is
generic (
hindex : integer := 0;
fabtech : integer range 0 to NTECH := DEFFABTECH;
memtech : integer := DEFMEMTECH;
nwindows : integer range 2 to 32 := 8;
dsu : integer range 0 to 1 := 0;
fpu : integer range 0 to 63 := 0;
v8 : integer range 0 to 63 := 0;
cp : integer range 0 to 1 := 0;
mac : integer range 0 to 1 := 0;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
nwp : integer range 0 to 4 := 0;
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 3 := 2;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 3 := 2;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 7 := 0;
ilram : integer range 0 to 2 := 0;
ilramsize : integer range 1 to 512 := 1;
ilramstart : integer range 0 to 255 := 16#8e#;
dlram : integer range 0 to 2 := 0;
dlramsize : integer range 1 to 512 := 1;
dlramstart : integer range 0 to 255 := 16#8f#;
mmuen : integer range 0 to 1 := 0;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
tlb_rep : integer range 0 to 1 := 0;
lddel : integer range 1 to 2 := 2;
disas : integer range 0 to 2 := 0;
tbuf : integer range 0 to 128 := 0;
pwd : integer range 0 to 2 := 2;
svt : integer range 0 to 1 := 1;
rstaddr : integer := 0;
smp : integer range 0 to 15 := 0;
iuft : integer range 0 to 6 := 0;
fpft : integer range 0 to 6 := 0;
cmft : integer range 0 to 1 := 0;
iuinj : integer := 0;
ceinj : integer range 0 to 3 := 0;
cached : integer := 0;
clk2x : integer := 1;
netlist : integer := 0;
scantest : integer := 0;
mmupgsz : integer range 0 to 5 := 0;
bp : integer := 1;
npasi : integer range 0 to 1 := 0;
pwrpsr : integer range 0 to 1 := 0;
rex : integer := 0;
altwin : integer range 0 to 1 := 0
);
port (
clk : in std_ulogic; -- free-running clock
gclk2 : in std_ulogic; -- gated 2x clock
gfclk2 : in std_ulogic; -- gated 2x FPU clock
clk2 : in std_ulogic; -- free-running 2x clock
rstn : in std_ulogic;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : in ahb_slv_out_vector;
irqi : in l3_irq_in_type;
irqo : out l3_irq_out_type;
dbgi : in l3_debug_in_type;
dbgo : out l3_debug_out_type;
fpui : out grfpu_in_type;
fpuo : in grfpu_out_type;
clken : in std_ulogic
);
end;
architecture rtl of leon3x is
constant IRFBITS : integer range 6 to 10 := log2(NWINDOWS+1) + 4;
constant IREGNUM : integer := NWINDOWS * 16 + 8;
constant IRFWT : integer := 1;--regfile_3p_write_through(memtech);
constant fpuarch : integer := fpu mod 16;
constant fpunet : integer := (fpu mod 32) / 16;
constant fpushared : boolean := (fpu / 32) /= 0;
constant MEMTECH_MOD : integer := memtech mod 65536;
constant MEMTECH_VEC : std_logic_vector(31 downto 0) := conv_std_logic_vector(memtech, 32);
constant IURF_INFER : integer := conv_integer(MEMTECH_VEC(17));
constant FPRF_INFER : integer := conv_integer(MEMTECH_VEC(18));
constant FTSUP : integer := 0
;
-- Create an array length mismatch error if the user tries to enable FT
-- features in non-FT release.
constant dummy_ft_consistency_check:
std_logic_vector(FTSUP*(iuft+fpft+cmft) downto (iuft+fpft+cmft)) := "0";
signal holdn : std_logic;
signal rfi : iregfile_in_type;
signal rfo : iregfile_out_type;
signal crami : cram_in_type;
signal cramo : cram_out_type;
signal tbi : tracebuf_in_type;
signal tbo : tracebuf_out_type;
signal tbi_2p : tracebuf_2p_in_type;
signal tbo_2p : tracebuf_2p_out_type;
signal rst : std_ulogic;
signal fpi : fpc_in_type;
signal fpo : fpc_out_type;
signal cpi : fpc_in_type;
signal cpo : fpc_out_type;
signal gnd, vcc : std_logic;
attribute sync_set_reset : string;
attribute sync_set_reset of rst : signal is "true";
begin
gnd <= '0'; vcc <= '1';
vhdl : if netlist = 0 generate
-- leon3 processor core (iu, caches & mul/div)
p0 : proc3
generic map (
hindex, fabtech, memtech, nwindows, dsu, fpuarch, v8, cp, mac, pclow,
notag, nwp, icen, irepl, isets, ilinesize, isetsize, isetlock, dcen,
drepl, dsets, dlinesize, dsetsize, dsetlock, dsnoop, ilram, ilramsize,
ilramstart, dlram, dlramsize, dlramstart, mmuen, itlbnum, dtlbnum,
tlb_type, tlb_rep, lddel, disas, tbuf, pwd, svt, rstaddr, smp,
cached, clk2x, scantest, mmupgsz, bp, npasi, pwrpsr, rex, altwin)
port map (gclk2, rst, holdn, ahbi, ahbo, ahbsi, ahbso, rfi, rfo, crami, cramo,
tbi, tbo, tbi_2p, tbo_2p, fpi, fpo, cpi, cpo, irqi, irqo, dbgi, dbgo, clk, clk2, clken
);
-- IU register file
rf0 : regfile_3p_l3 generic map (MEMTECH_MOD*(1-IURF_INFER), IRFBITS, 32, IRFWT, IREGNUM,
scantest)
port map (gclk2, rfi.waddr(IRFBITS-1 downto 0), rfi.wdata, rfi.wren,
gclk2, rfi.raddr1(IRFBITS-1 downto 0), rfi.ren1, rfo.data1,
rfi.raddr2(IRFBITS-1 downto 0), rfi.ren2, rfo.data2,
ahbi.testin
);
-- cache memory
cmem0 : cachemem
generic map (MEMTECH_MOD, icen, irepl, isets, ilinesize, isetsize, isetlock, dcen,
drepl, dsets, dlinesize, dsetsize, dsetlock, dsnoop, ilram,
ilramsize, dlram, dlramsize, mmuen, scantest
)
port map (gclk2, crami, cramo, clk2, ahbi.testin
);
-- instruction trace buffer memory
tbmem_gen : if (tbuf /= 0) generate
tbmem_1p : if (tbuf <= 64) generate
tbmem0 : tbufmem
generic map (tech => MEMTECH_MOD, tbuf => tbuf, dwidth => 32, testen => scantest)
port map (gclk2, tbi, tbo, ahbi.testin
);
tbo_2p <= tracebuf_2p_out_type_none;
end generate;
tbmem_2p: if (tbuf > 64) generate
tbmem0 : tbufmem_2p
generic map (tech => MEMTECH_MOD, tbuf => (tbuf-64), dwidth => 32, testen => scantest)
port map (gclk2, tbi_2p, tbo_2p, ahbi.testin
);
tbo <= tracebuf_out_type_none;
end generate;
end generate;
notbmem_gen : if (tbuf = 0) generate
tbo <= tracebuf_out_type_none;
tbo_2p <= tracebuf_2p_out_type_none;
end generate;
-- FPU
fpu0 : if (fpu = 0) generate
fpo <= fpc_out_none;
end generate;
fpshare : if fpushared generate
grfpw0gen : if (fpuarch > 0) and (fpuarch < 8) generate
fpu0: grfpwxsh
generic map (MEMTECH_MOD*(1-FPRF_INFER), pclow, dsu, disas, hindex,
scantest
)
port map (rst, gclk2, holdn, fpi, fpo, fpui, fpuo, ahbi.testin
);
end generate;
nogrfpw0gen : if not ((fpuarch > 0) and (fpuarch < 8)) generate
fpui <= grfpu_in_none;
end generate;
end generate;
nofpshare : if not fpushared generate
grfpw1gen : if (fpuarch > 0) and (fpuarch < 8) generate
fpu0: grfpwx
generic map (fabtech, MEMTECH_MOD*(1-FPRF_INFER), (fpuarch-1), pclow, dsu, disas,
fpunet, hindex, scantest)
port map (rst, gfclk2, holdn, fpi, fpo, ahbi.testin
);
end generate;
grlfpc1gen : if (fpuarch >=8) and (fpuarch < 15) generate
fpu0 : grlfpwx
generic map (MEMTECH_MOD*(1-FPRF_INFER), pclow, dsu, disas,
(fpuarch-8), fpunet, hindex, scantest)
port map (rst, gfclk2, holdn, fpi, fpo, ahbi.testin
);
end generate;
fpui <= grfpu_in_none;
end generate;
-- CP
cpo <= fpc_out_none;
-- 1-clock reset delay
rstreg : process(gclk2)
begin if rising_edge(gclk2) then rst <= rstn; end if; end process;
end generate vhdl;
ntl : if netlist /= 0 generate
l3net : leon3_net
generic map (
hindex => hindex,
fabtech => fabtech,
memtech => MEMTECH_MOD,
nwindows => nwindows,
dsu => dsu,
fpu => fpu,
v8 => v8,
cp => cp,
mac => mac,
pclow => pclow,
notag => notag,
nwp => nwp,
icen => icen,
irepl => irepl,
isets => isets,
ilinesize => ilinesize,
isetsize => isetsize,
isetlock => isetlock,
dcen => dcen,
drepl => drepl,
dsets => dsets,
dlinesize => dlinesize,
dsetsize => dsetsize,
dsetlock => dsetlock,
dsnoop => dsnoop,
ilram => ilram,
ilramsize => ilramsize,
ilramstart => ilramstart,
dlram => dlram,
dlramsize => dlramsize,
dlramstart => dlramstart,
mmuen => mmuen,
itlbnum => itlbnum,
dtlbnum => dtlbnum,
tlb_type => tlb_type,
tlb_rep => tlb_rep,
lddel => lddel,
disas => disas,
tbuf => tbuf,
pwd => pwd,
svt => svt,
rstaddr => rstaddr,
smp => smp,
iuft => iuft,
fpft => fpft,
cmft => cmft,
cached => cached,
clk2x => clk2x,
scantest => scantest,
mmupgsz => mmupgsz,
bp => bp,
npasi => npasi,
pwrpsr => pwrpsr)
port map (
clk => clk,
gclk2 => gclk2,
gfclk2 => gfclk2,
clk2 => clk2,
rstn => rstn,
ahbi => ahbi,
ahbo => ahbo,
ahbsi => ahbsi,
--ahbso => ahbso,
irqi_irl => irqi.irl,
irqi_resume => irqi.resume,
irqi_rstrun => irqi.rstrun,
irqi_rstvec => irqi.rstvec,
irqi_index => irqi.index,
irqi_pwdsetaddr => irqi.pwdsetaddr,
irqi_pwdnewaddr => irqi.pwdnewaddr,
irqi_forceerr => irqi.forceerr,
irqo_intack => irqo.intack,
irqo_irl => irqo.irl,
irqo_pwd => irqo.pwd,
irqo_fpen => irqo.fpen,
irqo_err => irqo.err,
dbgi_dsuen => dbgi.dsuen,
dbgi_denable => dbgi.denable,
dbgi_dbreak => dbgi.dbreak,
dbgi_step => dbgi.step,
dbgi_halt => dbgi.halt,
dbgi_reset => dbgi.reset,
dbgi_dwrite => dbgi.dwrite,
dbgi_daddr => dbgi.daddr,
dbgi_ddata => dbgi.ddata,
dbgi_btrapa => dbgi.btrapa,
dbgi_btrape => dbgi.btrape,
dbgi_berror => dbgi.berror,
dbgi_bwatch => dbgi.bwatch,
dbgi_bsoft => dbgi.bsoft,
dbgi_tenable => dbgi.tenable,
dbgi_timer => dbgi.timer,
dbgo_data => dbgo.data,
dbgo_crdy => dbgo.crdy,
dbgo_dsu => dbgo.dsu,
dbgo_dsumode => dbgo.dsumode,
dbgo_error => dbgo.error,
dbgo_halt => dbgo.halt,
dbgo_pwd => dbgo.pwd,
dbgo_idle => dbgo.idle,
dbgo_ipend => dbgo.ipend,
dbgo_icnt => dbgo.icnt,
dbgo_fcnt => dbgo.fcnt,
dbgo_optype => dbgo.optype,
dbgo_bpmiss => dbgo.bpmiss,
dbgo_istat_cmiss => dbgo.istat.cmiss,
dbgo_istat_tmiss => dbgo.istat.tmiss,
dbgo_istat_chold => dbgo.istat.chold,
dbgo_istat_mhold => dbgo.istat.mhold,
dbgo_dstat_cmiss => dbgo.dstat.cmiss,
dbgo_dstat_tmiss => dbgo.dstat.tmiss,
dbgo_dstat_chold => dbgo.dstat.chold,
dbgo_dstat_mhold => dbgo.dstat.mhold,
dbgo_wbhold => dbgo.wbhold,
dbgo_su => dbgo.su,
--fpui => fpui,
--fpuo => fpuo,
clken => clken);
end generate ntl;
-- pragma translate_off
bootmsg : report_version
generic map (
"leon3_" & tost(hindex) & ": LEON3 SPARC V8 processor rev " & tost(LEON3_VERSION)
& ": iuft: " & tost(iuft) & ", fpft: " & tost(fpft) & ", cacheft: " & tost(cmft)
, "leon3_" & tost(hindex) & ": icache " & tost(isets*icen) & "*" & tost(isetsize*icen) &
" kbyte, dcache " & tost(dsets*dcen) & "*" & tost(dsetsize*dcen) & " kbyte"
);
-- pragma translate_on
end;
| gpl-3.0 |
EliasLuiz/TCC | Leon3/designs/leon3-nuhorizons-3s1500/config.vhd | 1 | 6371 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := spartan3;
constant CFG_MEMTECH : integer := spartan3;
constant CFG_PADTECH : integer := spartan3;
constant CFG_TRANSTECH : integer := GTP0;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := spartan3;
constant CFG_CLKMUL : integer := (4);
constant CFG_CLKDIV : integer := (5);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 1;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 2 + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 1;
constant CFG_SVT : integer := 1;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 0;
constant CFG_NWP : integer := (2);
constant CFG_PWD : integer := 1*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 1;
constant CFG_ISETSZ : integer := 8;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 0;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 1;
constant CFG_DSETSZ : integer := 8;
constant CFG_DLINE : integer := 8;
constant CFG_DREPL : integer := 0;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 0 + 1*2 + 4*0;
constant CFG_DFIXED : integer := 16#00f3#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 1;
constant CFG_ITLBNUM : integer := 8;
constant CFG_DTLBNUM : integer := 8;
constant CFG_TLB_TYPE : integer := 0 + 1*2;
constant CFG_TLB_REP : integer := 0;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 2 + 64*0;
constant CFG_ATBSZ : integer := 2;
constant CFG_AHBPF : integer := 0;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
constant CFG_STAT_ENABLE : integer := 0;
constant CFG_STAT_CNT : integer := 1;
constant CFG_STAT_NMAX : integer := 0;
constant CFG_STAT_DSUEN : integer := 0;
constant CFG_NP_ASI : integer := 0;
constant CFG_WRPSR : integer := 0;
constant CFG_ALTWIN : integer := 0;
constant CFG_REX : integer := 0;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 1;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- Ethernet DSU
constant CFG_DSU_ETH : integer := 1 + 0 + 0;
constant CFG_ETH_BUF : integer := 2;
constant CFG_ETH_IPM : integer := 16#C0A8#;
constant CFG_ETH_IPL : integer := 16#0033#;
constant CFG_ETH_ENM : integer := 16#020000#;
constant CFG_ETH_ENL : integer := 16#00002B#;
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 1;
constant CFG_MCTRL_RAM8BIT : integer := 1;
constant CFG_MCTRL_RAM16BIT : integer := 1;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 1;
constant CFG_MCTRL_SEPBUS : integer := 1;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 0;
constant CFG_MCTRL_PAGE : integer := 0 + 0;
-- AHB ROM
constant CFG_AHBROMEN : integer := 0;
constant CFG_AHBROPIP : integer := 0;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#000#;
constant CFG_ROMMASK : integer := 16#E00# + 16#000#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- Gaisler Ethernet core
constant CFG_GRETH : integer := 1;
constant CFG_GRETH1G : integer := 0;
constant CFG_ETH_FIFO : integer := 32;
-- CAN 2.0 interface
constant CFG_CAN : integer := 1;
constant CFG_CANIO : integer := 16#C00#;
constant CFG_CANIRQ : integer := (13);
constant CFG_CANLOOP : integer := 0;
constant CFG_CAN_SYNCRST : integer := 0;
constant CFG_CANFT : integer := 0;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 8;
-- UART 2
constant CFG_UART2_ENABLE : integer := 0;
constant CFG_UART2_FIFO : integer := 1;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#fffe#;
constant CFG_GRGPIO_WIDTH : integer := (16);
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
| gpl-3.0 |
EliasLuiz/TCC | Leon3/lib/techmap/maps/cpu_disas_net.vhd | 1 | 4563 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: cpu_disas_net
-- File: cpu_disas_net.vhd
-- Author: Jiri Gaisler, Gaisler Research
-- Description: SPARC disassembler according to SPARC V8 manual
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library grlib;
use grlib.stdlib.all;
use grlib.sparc.all;
use grlib.sparc_disas.all;
-- pragma translate_on
entity cpu_disas_net is
port (
clk : in std_ulogic;
rstn : in std_ulogic;
dummy : out std_ulogic;
inst : in std_logic_vector(31 downto 0);
pc : in std_logic_vector(31 downto 2);
result: in std_logic_vector(31 downto 0);
index : in std_logic_vector(3 downto 0);
wreg : in std_ulogic;
annul : in std_ulogic;
holdn : in std_ulogic;
pv : in std_ulogic;
trap : in std_ulogic;
disas : in std_ulogic);
end;
architecture behav of cpu_disas_net is
begin
dummy <= '1';
-- pragma translate_off
trc : process(clk)
variable valid : boolean;
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable fpins, fpld : boolean;
variable iindex : integer;
begin
iindex := conv_integer(index);
op := inst(31 downto 30); op3 := inst(24 downto 19);
fpins := (op = FMT3) and ((op3 = FPOP1) or (op3 = FPOP2));
fpld := (op = LDST) and ((op3 = LDF) or (op3 = LDDF) or (op3 = LDFSR));
valid := (((not annul) and pv) = '1') and (not ((fpins or fpld) and (trap = '0')));
valid := valid and (holdn = '1');
if rising_edge(clk) and (rstn = '1') and (disas = '1') then
print_insn (iindex, pc(31 downto 2) & "00", inst,
result, valid, trap = '1', wreg = '1'
);
end if;
end process;
-- pragma translate_on
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library grlib;
use grlib.stdlib.all;
use grlib.sparc.all;
use grlib.sparc_disas.all;
-- pragma translate_on
entity fpu_disas_net is
port (
clk : in std_ulogic;
rstn : in std_ulogic;
dummy : out std_ulogic;
wr2inst : in std_logic_vector(31 downto 0);
wr2pc : in std_logic_vector(31 downto 2);
divinst : in std_logic_vector(31 downto 0);
divpc : in std_logic_vector(31 downto 2);
dbg_wrdata: in std_logic_vector(63 downto 0);
index : in std_logic_vector(3 downto 0);
dbg_wren : in std_logic_vector(1 downto 0);
resv : in std_ulogic;
ld : in std_ulogic;
rdwr : in std_ulogic;
ccwr : in std_ulogic;
rdd : in std_ulogic;
div_valid : in std_ulogic;
holdn : in std_ulogic;
disas : in std_ulogic);
end;
architecture behav of fpu_disas_net is
begin
dummy <= '1';
-- pragma translate_off
trc : process(clk)
variable valid : boolean;
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable fpins, fpld : boolean;
variable iindex : integer;
begin
iindex := conv_integer(index);
if rising_edge(clk) and (rstn = '1') and (disas /= '0') then
valid := ((((rdwr and not ld) or ccwr or (ld and resv)) and holdn) = '1');
print_fpinsn(0, wr2pc(31 downto 2) & "00", wr2inst, dbg_wrdata,
(rdd = '1'), valid, false, (dbg_wren /= "00"));
print_fpinsn(0, divpc(31 downto 2) & "00", divinst, dbg_wrdata,
(rdd = '1'), (div_valid and holdn) = '1', false, (dbg_wren /= "00"));
end if;
end process;
-- pragma translate_on
end;
| gpl-3.0 |
GLADICOS/SPACEWIRESYSTEMC | rtl/RTL_SL/streamtest.vhd | 2 | 16127 | --
-- Test application for spwstream.
--
-- This entity implements one spwstream instance with SpaceWire signals
-- routed to external ports. The SpaceWire port is assumed to be looped back
-- to itself externally, either directly (tx pins wired to rx pins) or
-- through a remote SpaceWire device which is programmed to echo anything
-- it receives.
--
-- This entity submits a series of test patterns to the transmit side of
-- spwstream. At the same time it monitors the receive side of spwstream
-- and verifies that received data matches the transmitted data pattern.
--
-- Link mode and tx bit rate may be programmed through digital inputs
-- (presumably connected to switches or buttons). Link state and progress of
-- the test are reported through digital outputs (presumably connected to
-- LEDs).
--
-- Note: there is no check on the integrity of the first packet received
-- after the link goes up.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.spwpkg.all;
entity streamtest is
generic (
-- System clock frequency in Hz.
sysfreq: real;
-- txclk frequency in Hz (if tximpl = impl_fast).
txclkfreq: real;
-- 2-log of division factor from system clock freq to timecode freq.
tickdiv: integer range 12 to 24 := 20;
-- Receiver front-end implementation.
rximpl: spw_implementation_type := impl_generic;
-- Maximum number of bits received per system clock (impl_fast only).
rxchunk: integer range 1 to 4 := 1;
-- Transmitter implementation.
tximpl: spw_implementation_type := impl_generic;
-- Size of receive FIFO.
rxfifosize_bits: integer range 6 to 14 := 11;
-- Size of transmit FIFO.
txfifosize_bits: integer range 2 to 14 := 11 );
port (
-- System clock.
clk: in std_logic;
-- Receiver sample clock (only for impl_fast).
rxclk: in std_logic;
-- Transmit clock (only for impl_fast).
txclk: in std_logic;
-- Synchronous reset (active-high).
rst: in std_logic;
-- Enables spontaneous link start.
linkstart: in std_logic;
-- Enables automatic link start on receipt of a NULL token.
autostart: in std_logic;
-- Do not start link and/or disconnect current link.
linkdisable: in std_logic;
-- Enable sending test patterns to spwstream.
senddata: in std_logic;
-- Enable sending time codes to spwstream.
sendtick: in std_logic;
-- Scaling factor minus 1 for TX bitrate.
txdivcnt: in std_logic_vector(7 downto 0);
-- Link in state Started.
linkstarted: out std_logic;
-- Link in state Connecting.
linkconnecting: out std_logic;
-- Link in state Run.
linkrun: out std_logic;
-- Link error (one cycle pulse, not directly suitable for LED)
linkerror: out std_logic;
-- High when taking a byte from the receive FIFO.
gotdata: out std_logic;
-- Incorrect or unexpected data received (sticky).
dataerror: out std_logic;
-- Incorrect or unexpected time code received (sticky).
tickerror: out std_logic;
-- SpaceWire signals.
spw_di: in std_logic;
spw_si: in std_logic;
spw_do: out std_logic;
spw_so: out std_logic );
end entity streamtest;
architecture streamtest_arch of streamtest is
-- Update 16-bit maximum length LFSR by 8 steps
function lfsr16(x: in std_logic_vector) return std_logic_vector is
variable y: std_logic_vector(15 downto 0);
begin
-- poly = x^16 + x^14 + x^13 + x^11 + 1
-- tap positions = x(0), x(2), x(3), x(5)
y(7 downto 0) := x(15 downto 8);
y(15 downto 8) := x(7 downto 0) xor x(9 downto 2) xor x(10 downto 3) xor x(12 downto 5);
return y;
end function;
-- Sending side state.
type tx_state_type is ( txst_idle, txst_prepare, txst_data );
-- Receiving side state.
type rx_state_type is ( rxst_idle, rxst_data );
-- Registers.
type regs_type is record
tx_state: tx_state_type;
tx_timecnt: std_logic_vector((tickdiv-1) downto 0);
tx_quietcnt: std_logic_vector(15 downto 0);
tx_pktlen: std_logic_vector(15 downto 0);
tx_lfsr: std_logic_vector(15 downto 0);
tx_enabledata: std_ulogic;
rx_state: rx_state_type;
rx_quietcnt: std_logic_vector(15 downto 0);
rx_enabledata: std_ulogic;
rx_gottick: std_ulogic;
rx_expecttick: std_ulogic;
rx_expectglitch: unsigned(5 downto 0);
rx_badpacket: std_ulogic;
rx_pktlen: std_logic_vector(15 downto 0);
rx_prev: std_logic_vector(15 downto 0);
rx_lfsr: std_logic_vector(15 downto 0);
running: std_ulogic;
tick_in: std_ulogic;
time_in: std_logic_vector(5 downto 0);
txwrite: std_ulogic;
txflag: std_ulogic;
txdata: std_logic_vector(7 downto 0);
rxread: std_ulogic;
gotdata: std_ulogic;
dataerror: std_ulogic;
tickerror: std_ulogic;
end record;
-- Reset state.
constant regs_reset: regs_type := (
tx_state => txst_idle,
tx_timecnt => (others => '0'),
tx_quietcnt => (others => '0'),
tx_pktlen => (others => '0'),
tx_lfsr => (1 => '1', others => '0'),
tx_enabledata => '0',
rx_state => rxst_idle,
rx_quietcnt => (others => '0'),
rx_enabledata => '0',
rx_gottick => '0',
rx_expecttick => '0',
rx_expectglitch => "000001",
rx_badpacket => '0',
rx_pktlen => (others => '0'),
rx_prev => (others => '0'),
rx_lfsr => (others => '0'),
running => '0',
tick_in => '0',
time_in => (others => '0'),
txwrite => '0',
txflag => '0',
txdata => (others => '0'),
rxread => '0',
gotdata => '0',
dataerror => '0',
tickerror => '0' );
signal r: regs_type := regs_reset;
signal rin: regs_type;
-- Interface signals.
signal s_txrdy: std_logic;
signal s_tickout: std_logic;
signal s_timeout: std_logic_vector(5 downto 0);
signal s_rxvalid: std_logic;
signal s_rxflag: std_logic;
signal s_rxdata: std_logic_vector(7 downto 0);
signal s_running: std_logic;
signal s_errdisc: std_logic;
signal s_errpar: std_logic;
signal s_erresc: std_logic;
signal s_errcred: std_logic;
begin
-- spwstream instance
spwstream_inst: spwstream
generic map (
sysfreq => sysfreq,
txclkfreq => txclkfreq,
rximpl => rximpl,
rxchunk => rxchunk,
tximpl => tximpl,
rxfifosize_bits => rxfifosize_bits,
txfifosize_bits => txfifosize_bits )
port map (
clk => clk,
rxclk => rxclk,
txclk => txclk,
rst => rst,
autostart => autostart,
linkstart => linkstart,
linkdis => linkdisable,
txdivcnt => txdivcnt,
tick_in => r.tick_in,
ctrl_in => (others => '0'),
time_in => r.time_in,
txwrite => r.txwrite,
txflag => r.txflag,
txdata => r.txdata,
txrdy => s_txrdy,
txhalff => open,
tick_out => s_tickout,
ctrl_out => open,
time_out => s_timeout,
rxvalid => s_rxvalid,
rxhalff => open,
rxflag => s_rxflag,
rxdata => s_rxdata,
rxread => r.rxread,
started => linkstarted,
connecting => linkconnecting,
running => s_running,
errdisc => s_errdisc,
errpar => s_errpar,
erresc => s_erresc,
errcred => s_errcred,
spw_di => spw_di,
spw_si => spw_si,
spw_do => spw_do,
spw_so => spw_so );
-- Drive status indications.
linkrun <= s_running;
linkerror <= s_errdisc or s_errpar or s_erresc or s_errcred;
gotdata <= r.gotdata;
dataerror <= r.dataerror;
tickerror <= r.tickerror;
process (r, rst, senddata, sendtick, s_txrdy, s_tickout, s_timeout, s_rxvalid, s_rxflag, s_rxdata, s_running) is
variable v: regs_type;
begin
v := r;
-- Initiate timecode transmissions.
v.tx_timecnt := std_logic_vector(unsigned(r.tx_timecnt) + 1);
if unsigned(v.tx_timecnt) = 0 then
v.tick_in := sendtick;
else
v.tick_in := '0';
end if;
if r.tick_in = '1' then
v.time_in := std_logic_vector(unsigned(r.time_in) + 1);
v.rx_expecttick := '1';
v.rx_gottick := '0';
end if;
-- Turn data generator on/off at regular intervals.
v.tx_quietcnt := std_logic_vector(unsigned(r.tx_quietcnt) + 1);
if unsigned(r.tx_quietcnt) = 61000 then
v.tx_quietcnt := (others => '0');
end if;
v.tx_enabledata := senddata and (not r.tx_quietcnt(15));
-- Generate data packets.
case r.tx_state is
when txst_idle =>
-- generate packet length
v.tx_state := txst_prepare;
v.tx_pktlen := r.tx_lfsr;
v.txwrite := '0';
v.tx_lfsr := lfsr16(r.tx_lfsr);
when txst_prepare =>
-- generate first byte of packet
v.tx_state := txst_data;
v.txwrite := r.tx_enabledata;
v.txflag := '0';
v.txdata := r.tx_lfsr(15 downto 8);
v.tx_lfsr := lfsr16(r.tx_lfsr);
when txst_data =>
-- generate data bytes and EOP
v.txwrite := r.tx_enabledata;
if r.txwrite = '1' and s_txrdy = '1' then
-- just sent one byte
v.tx_pktlen := std_logic_vector(unsigned(r.tx_pktlen) - 1);
if unsigned(r.tx_pktlen) = 0 then
-- done with packet
v.tx_state := txst_idle;
v.txwrite := '0';
elsif unsigned(r.tx_pktlen) = 1 then
-- generate EOP
v.txwrite := r.tx_enabledata;
v.txflag := '1';
v.txdata := (others => '0');
v.tx_lfsr := lfsr16(r.tx_lfsr);
else
-- generate next data byte
v.txwrite := r.tx_enabledata;
v.txflag := '0';
v.txdata := r.tx_lfsr(15 downto 8);
v.tx_lfsr := lfsr16(r.tx_lfsr);
end if;
end if;
end case;
-- Blink light when receiving data.
v.gotdata := s_rxvalid and r.rxread;
-- Detect missing timecodes.
if r.tick_in = '1' and r.rx_expecttick = '1' then
-- This is bad; a new timecode is being generated while
-- we have not even received the previous one yet.
v.tickerror := '1';
end if;
-- Receive and check incoming timecodes.
if s_tickout = '1' then
if unsigned(s_timeout) + 1 /= unsigned(r.time_in) then
-- Received time code does not match last transmitted code.
v.tickerror := '1';
end if;
if r.rx_gottick = '1' then
-- Already received the last transmitted time code.
v.tickerror := '1';
end if;
v.rx_expecttick := '0';
v.rx_gottick := '1';
end if;
-- Turn data receiving on/off at regular intervals
v.rx_quietcnt := std_logic_vector(unsigned(r.rx_quietcnt) + 1);
if unsigned(r.rx_quietcnt) = 55000 then
v.rx_quietcnt := (others => '0');
end if;
v.rx_enabledata := not r.rx_quietcnt(15);
case r.rx_state is
when rxst_idle =>
-- get expected packet length
v.rx_state := rxst_data;
v.rx_pktlen := r.rx_lfsr;
v.rx_lfsr := lfsr16(r.rx_lfsr);
v.rx_prev := (others => '0');
when rxst_data =>
v.rxread := r.rx_enabledata;
if r.rxread = '1' and s_rxvalid = '1' then
-- got next byte
v.rx_pktlen := std_logic_vector(unsigned(r.rx_pktlen) - 1);
v.rx_prev := s_rxdata & r.rx_prev(15 downto 8);
if s_rxflag = '1' then
-- got EOP or EEP
v.rxread := '0';
v.rx_state := rxst_idle;
if s_rxdata = "00000000" then
-- got EOP
if unsigned(r.rx_pktlen) /= 0 then
-- unexpected EOP
v.rx_badpacket := '1';
end if;
-- count errors against expected glitches
if v.rx_badpacket = '1' then
-- got glitch
if r.rx_expectglitch = 0 then
v.dataerror := '1';
else
v.rx_expectglitch := r.rx_expectglitch - 1;
end if;
end if;
-- resynchronize LFSR
v.rx_lfsr := lfsr16(lfsr16(r.rx_prev));
else
-- got EEP
v.rx_badpacket := '1';
end if;
v.rx_badpacket := '0';
else
-- got next byte
v.rx_lfsr := lfsr16(r.rx_lfsr);
if unsigned(r.rx_pktlen) = 0 then
-- missing EOP
v.rx_badpacket := '1';
end if;
if s_rxdata /= r.rx_lfsr(15 downto 8) then
-- bad data
v.rx_badpacket := '1';
end if;
end if;
end if;
end case;
-- If the link goes away, we should expect inconsistency on the receiving side.
v.running := s_running;
if r.running = '1' and s_running = '0' then
if r.rx_expectglitch /= "111111" then
v.rx_expectglitch := r.rx_expectglitch + 1;
end if;
end if;
-- If there is no link, we should not expect to receive time codes.
if s_running = '0' then
v.rx_expecttick := '0';
end if;
-- Synchronous reset.
if rst = '1' then
v := regs_reset;
end if;
-- Update registers.
rin <= v;
end process;
-- Update registers.
process (clk) is
begin
if rising_edge(clk) then
r <= rin;
end if;
end process;
end architecture streamtest_arch;
| gpl-3.0 |
EliasLuiz/TCC | Leon3/lib/gaisler/irqmp/irqmp.in.vhd | 4 | 151 | -- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := CONFIG_IRQ3_ENABLE;
constant CFG_IRQ3_NSEC : integer := CONFIG_IRQ3_NSEC;
| gpl-3.0 |
hoglet67/CoPro6502 | src/CPU65C02/fsm_execution_unit.vhd | 1 | 236027 | -- VHDL Entity r65c02_tc.fsm_execution_unit.symbol
--
-- Created:
-- by - eda.UNKNOWN (ENTW-7HPZ200)
-- at - 15:56:20 27.08.2018
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2016.2 (Build 5)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
entity fsm_execution_unit is
port(
adr_nxt_pc_i : in std_logic_vector (15 downto 0);
adr_pc_i : in std_logic_vector (15 downto 0);
adr_sp_i : in std_logic_vector (15 downto 0);
clk_clk_i : in std_logic;
d_alu_i : in std_logic_vector ( 7 downto 0 );
d_alu_prio_i : in std_logic_vector (7 downto 0);
d_i : in std_logic_vector ( 7 downto 0 );
d_regs_out_i : in std_logic_vector ( 7 downto 0 );
irq_n_i : in std_logic;
nmi_i : in std_logic;
q_a_i : in std_logic_vector ( 7 downto 0 );
q_x_i : in std_logic_vector ( 7 downto 0 );
q_y_i : in std_logic_vector ( 7 downto 0 );
rdy_i : in std_logic;
reg_0flag_i : in std_logic;
reg_1flag_i : in std_logic;
reg_7flag_i : in std_logic;
rst_rst_n_i : in std_logic;
so_n_i : in std_logic;
a_o : out std_logic_vector (15 downto 0);
adr_o : out std_logic_vector (15 downto 0);
ch_a_o : out std_logic_vector ( 7 downto 0 );
ch_b_o : out std_logic_vector ( 7 downto 0 );
d_o : out std_logic_vector ( 7 downto 0 );
d_regs_in_o : out std_logic_vector ( 7 downto 0 );
ld_o : out std_logic_vector ( 1 downto 0 );
ld_pc_o : out std_logic;
ld_sp_o : out std_logic;
load_regs_o : out std_logic;
offset_o : out std_logic_vector ( 15 downto 0 );
rd_o : out std_logic;
rst_nmi_o : out std_logic;
sel_pc_in_o : out std_logic;
sel_pc_val_o : out std_logic_vector ( 1 downto 0 );
sel_rb_in_o : out std_logic_vector ( 1 downto 0 );
sel_rb_out_o : out std_logic_vector ( 1 downto 0 );
sel_reg_o : out std_logic_vector ( 1 downto 0 );
sel_sp_as_o : out std_logic;
sel_sp_in_o : out std_logic;
sync_o : out std_logic;
wr_n_o : out std_logic;
wr_o : out std_logic
);
-- Declarations
end fsm_execution_unit ;
-- (C) 2008 - 2018 Jens Gutschmidt
-- (email: [email protected])
--
-- Versions:
-- Revision 1.1202 2018/09/09 17:48:00 jens
-- - RESET generates SYNC now
-- Revision 1.1202 RC 2018/09/09 03:00:00 jens
-- - ADC / SBC flags and A like R65C02 now
-- Revision 1.1202 BETA 2018/09/05 19:35:00 jens
-- - BBRx/BBSx internal cycles like real 65C02 now
-- - Bug Fix ADC and SBC in decimal mode (all op codes -
-- 1 cycle is missing
-- - Bug Fix ADC and SBC in decimal mode (all op codes -
-- "Overflow" flag was computed wrong)
-- Revision 1.1202 BETA 2018/09/02 18:49:00 jens
-- - Interrupt NMI and IRQ processing via FETCH stage now
-- Revision 1.1202 BETA 2018/08/30 15:39:00 jens
-- - Interrupt priority order is now: BRQ - NMI - IRQ
-- - Performance improvements on-going (Mealy -> Moore)
-- Revision 1.1202 BETA 2018/08/23 20:27:00 jens
-- - Bug Fixes All Branch Instructions
-- (BCC, BCS, BEQ, BNE, BPL, BMI, BVC, BVS, BRA)
-- 3 cycles now if branch forward occur and the branch
-- instruction lies on a xxFEh location.
-- (BBR, BBS) 6 cycles now if branch forward occur and the
-- branch instruction lies on a xxFDh location.
-- - Bug Fix Hardware Interrupts NMI & IRQ - 7 cycles & "SYNC" now
-- - Bug Fix Now all cycles are delayable (WR and internal)
--
-- Revision 1.1201 BETA 2014/04/19 14:44:00 jens
-- (never submitted to opencores)
-- - Bug Fix JMP ABS - produced a 6502 like JMP (IND) PCH.
-- When the ABS address data bytes cross the page
-- boundary (e.g. $02FE JMP hhll reads hh from
-- $02FF and ll from $0200, instead $02FF and $0300)
--
-- Revision 1.12 RC 2013/07/31 11:53:00 jens
-- - Bug Fix CMP (IND) - wrongly decoded as function AND
-- - Bug Fix BRK should clear decimal flag P Reg
-- - Bug Fix JMP (ABS,X) - Low Address outputted twice - no High Address
-- - Bug Fix Unknown Ops - Used allways 1b2c NOP ($EA) - new NOPs created
-- - Bug Fix DECIMAL ADC and SBC (all op codes - "C" flag was computed wrong)
-- - Bug Fix INC/DEC ABS,X - N/Z flag wrongly computed
-- - Bug Fix RTI - should increment stack pointer (decremented)
-- - Bug Fix "E" & "B" flags (Bits 5 & 4) - should be always "1" in P Reg. Change "RES", "RTI", "IRQ" & "NMI" substates.
-- - Bug Fix ADC and SBC (all op codes - "Overflow" flag was computed wrong)
-- - Bug Fix RMB, SMB Bug - Bit position decoded wrong.
--
-- Revision 1.11 2013/07/21 11:11:00 jens
-- - Changing the title block and internal revision history
-- - Bug Fix STA [(IND)] op$92 ($92 was missed in the connection list at state FETCH)
--
-- Revision 1.10 2010/02/08 17:34:20 eda
-- BUGFIX for IRQn, NMIn and RTI
-- After detection of NMI or IRQ the address of the next instruction stacked wrong.
-- NMI now overwrites the vector address of IRQ if NMI asserted after IRQ and the
-- vector address is not loaded yet.
--
--
-- Revision 1.9 2010/02/08 17:32:19 eda
-- BUGFIX for IRQn, NMIn and RTI
-- After detection of NMI or IRQ the address of the next instruction stacked wrong.
-- NMI now overwrites the vector address of IRQ if NMI asserted after IRQ and the
-- vector address is not loaded yet.
--
--
-- Revision 1.8 2009/01/04 20:23:42 eda
-- *** EMERGENCY BUGFIX ***
-- - Signal rd_o was corrupted in last version. wr_o and wr_n are not effected.
-- - OP JMP (indirect) produced a 65C02 like jump. On 6502 a special case exist
-- when the (indirect) address cross the page boundary (e.g. JMP (02FF) reads from
-- $02FF and $0200, instead of $02FF and $0300)
--
-- Revision 1.7 2009/01/04 16:54:59 eda
-- - Removed unused bits in ALU (zw_ALUx)
--
-- Revision 1.6 2009/01/04 10:27:49 eda
-- Changes for cosmetic issues only
--
-- Revision 1.5 2009/01/04 10:25:04 eda
-- Changes for cosmetic issues only
--
-- Revision 1.4 2009/01/03 16:53:01 eda
-- - Unused nets and blocks deleted
-- - Re-arragend symbols in block FSM_Execution_Unit
-- - Renamed blocks
-- - Input SO implemented
--
-- Revision 1.3 2009/01/03 16:42:02 eda
-- - Unused nets and blocks deleted
-- - Re-arragend symbols in block FSM_Execution_Unit
-- - Renamed blocks
-- - Input SO implemented
--
-- Revision 1.2 2008/12/31 19:31:24 eda
-- Production Release
--
--
--
-- VHDL Architecture r65c02_tc.fsm_execution_unit.fsm
--
-- Created:
-- by - eda.UNKNOWN (ENTW-7HPZ200)
-- at - 18:23:45 09.09.2018
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2016.2 (Build 5)
--
-- COPYRIGHT (C) 2008 - 2018 by Jens Gutschmidt
--
-- This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version 3 of the License, or any later version.
--
-- This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along with this program. If not, see <http://www.gnu.org/licenses/>.
--
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
architecture fsm of fsm_execution_unit is
-- Architecture Declarations
signal reg_F : std_logic_vector( 7 DOWNTO 0 );
signal reg_PC : std_logic_vector(15 DOWNTO 0);
signal reg_PC1 : std_logic_vector( 15 DOWNTO 0 );
signal reg_sel_pc_in : std_logic;
signal reg_sel_pc_val : std_logic_vector( 1 DOWNTO 0 );
signal reg_sel_rb_in : std_logic_vector( 1 DOWNTO 0 );
signal reg_sel_rb_out : std_logic_vector( 1 DOWNTO 0 );
signal reg_sel_reg : std_logic_vector( 1 DOWNTO 0 );
signal reg_sel_sp_as : std_logic;
signal reg_sel_sp_in : std_logic;
signal sig_D_OUT : std_logic_vector( 7 DOWNTO 0 );
signal sig_PC : std_logic_vector(15 DOWNTO 0);
signal sig_RD : std_logic;
signal sig_RWn : std_logic;
signal sig_SYNC : std_logic;
signal sig_WR : std_logic;
signal zw_100_a : std_logic;
signal zw_100_alu : std_logic;
signal zw_100_d : std_logic;
signal zw_50_a : std_logic;
signal zw_50_alu : std_logic;
signal zw_50_d : std_logic;
signal zw_ALU : std_logic_vector(9 DOWNTO 0);
signal zw_ALU1 : std_logic_vector(9 DOWNTO 0);
signal zw_ALU2 : std_logic_vector(9 DOWNTO 0);
signal zw_ALU3 : std_logic_vector(9 DOWNTO 0);
signal zw_ALU4 : std_logic_vector(9 DOWNTO 0);
signal zw_ALU5 : std_logic_vector(9 DOWNTO 0);
signal zw_ALU6 : std_logic_vector(9 DOWNTO 0);
signal zw_PC : std_logic_vector( 15 DOWNTO 0 );
signal zw_REG_ALU : std_logic_vector( 8 DOWNTO 0 );
signal zw_REG_OP : std_logic_vector( 7 DOWNTO 0 );
signal zw_REG_sig_PC : std_logic_vector(15 DOWNTO 0);
signal zw_b1 : std_logic_vector( 7 DOWNTO 0 );
signal zw_b2 : std_logic_vector( 7 DOWNTO 0 );
signal zw_b3 : std_logic_vector( 7 DOWNTO 0 );
signal zw_b4 : std_logic_vector( 7 DOWNTO 0 );
signal zw_so : std_logic;
signal zw_w1 : std_logic_vector( 15 DOWNTO 0 );
signal zw_w2 : std_logic_vector( 15 DOWNTO 0 );
signal zw_w3 : std_logic_vector( 15 DOWNTO 0 );
subtype state_type is
std_logic_vector(7 downto 0);
-- State vector declaration
attribute state_vector : string;
attribute state_vector of fsm : architecture is "current_state";
-- Hard encoding
constant s544 : state_type := "00000000";
constant s545 : state_type := "00000001";
constant s546 : state_type := "00000011";
constant s547 : state_type := "00000010";
constant s549 : state_type := "00000110";
constant s550 : state_type := "00000111";
constant RES : state_type := "00000101";
constant FETCH : state_type := "00000100";
constant s6 : state_type := "00001100";
constant s7 : state_type := "00001101";
constant s8 : state_type := "00001111";
constant s9 : state_type := "00001110";
constant s10 : state_type := "00001010";
constant s13 : state_type := "00001011";
constant s18 : state_type := "00001001";
constant s19 : state_type := "00001000";
constant s26 : state_type := "00011000";
constant s27 : state_type := "00011001";
constant s203 : state_type := "00011011";
constant s204 : state_type := "00011010";
constant s212 : state_type := "00011110";
constant s216 : state_type := "00011111";
constant s219 : state_type := "00011101";
constant s220 : state_type := "00011100";
constant s227 : state_type := "00010100";
constant s228 : state_type := "00010101";
constant s230 : state_type := "00010111";
constant s231 : state_type := "00010110";
constant s229 : state_type := "00010010";
constant s512 : state_type := "00010011";
constant s554 : state_type := "00010001";
constant s578 : state_type := "00010000";
constant s581 : state_type := "00110000";
constant s582 : state_type := "00110001";
constant s583 : state_type := "00110011";
constant s584 : state_type := "00110010";
constant s585 : state_type := "00110110";
constant s586 : state_type := "00110111";
constant s587 : state_type := "00110101";
constant s580 : state_type := "00110100";
constant s178 : state_type := "00111100";
constant s194 : state_type := "00111101";
constant s195 : state_type := "00111111";
constant s196 : state_type := "00111110";
constant s197 : state_type := "00111010";
constant s198 : state_type := "00111011";
constant s199 : state_type := "00111001";
constant s200 : state_type := "00111000";
constant s205 : state_type := "00101000";
constant s206 : state_type := "00101001";
constant s207 : state_type := "00101011";
constant s208 : state_type := "00101010";
constant s209 : state_type := "00101110";
constant s213 : state_type := "00101111";
constant s214 : state_type := "00101101";
constant s513 : state_type := "00101100";
constant s588 : state_type := "00100100";
constant s589 : state_type := "00100101";
constant s590 : state_type := "00100111";
constant s591 : state_type := "00100110";
constant s592 : state_type := "00100010";
constant s593 : state_type := "00100011";
constant s594 : state_type := "00100001";
constant s595 : state_type := "00100000";
constant s596 : state_type := "01100000";
constant s597 : state_type := "01100001";
constant s405 : state_type := "01100011";
constant s408 : state_type := "01100010";
constant s410 : state_type := "01100110";
constant s411 : state_type := "01100111";
constant s414 : state_type := "01100101";
constant s415 : state_type := "01100100";
constant s417 : state_type := "01101100";
constant s419 : state_type := "01101101";
constant s420 : state_type := "01101111";
constant s598 : state_type := "01101110";
constant s599 : state_type := "01101010";
constant s600 : state_type := "01101011";
constant s268 : state_type := "01101001";
constant s305 : state_type := "01101000";
constant s306 : state_type := "01111000";
constant jmp1 : state_type := "01111001";
constant jmp2_1 : state_type := "01111011";
constant jmp4_12 : state_type := "01111010";
constant jmp_ex : state_type := "01111110";
constant jmp2_2 : state_type := "01111111";
constant jmp3_1 : state_type := "01111101";
constant s402 : state_type := "01111100";
constant s421 : state_type := "01110100";
constant s422 : state_type := "01110101";
constant s423 : state_type := "01110111";
constant s424 : state_type := "01110110";
constant s362 : state_type := "01110010";
constant s221 : state_type := "01110011";
constant s232 : state_type := "01110001";
constant s233 : state_type := "01110000";
constant s234 : state_type := "01010000";
constant s235 : state_type := "01010001";
constant brk1 : state_type := "01010011";
constant brk2 : state_type := "01010010";
constant brk3 : state_type := "01010110";
constant brk4 : state_type := "01010111";
constant brk6 : state_type := "01010101";
constant brk5 : state_type := "01010100";
constant s425 : state_type := "01011100";
constant s426 : state_type := "01011101";
constant s427 : state_type := "01011111";
constant s428 : state_type := "01011110";
constant s429 : state_type := "01011010";
constant s430 : state_type := "01011011";
constant s431 : state_type := "01011001";
constant s432 : state_type := "01011000";
constant s433 : state_type := "01001000";
constant s434 : state_type := "01001001";
constant s236 : state_type := "01001011";
constant s245 : state_type := "01001010";
constant s246 : state_type := "01001110";
constant s248 : state_type := "01001111";
constant s345 : state_type := "01001101";
constant s346 : state_type := "01001100";
constant s252 : state_type := "01000100";
constant s253 : state_type := "01000101";
constant s435 : state_type := "01000111";
constant s436 : state_type := "01000110";
constant s437 : state_type := "01000010";
constant s438 : state_type := "01000011";
constant s439 : state_type := "01000001";
constant s440 : state_type := "01000000";
constant s441 : state_type := "11000000";
constant s442 : state_type := "11000001";
constant s443 : state_type := "11000011";
constant s444 : state_type := "11000010";
constant irq1 : state_type := "11000110";
constant irq2 : state_type := "11000111";
constant irq3 : state_type := "11000101";
constant irq5b : state_type := "11000100";
constant irq5a : state_type := "11001100";
constant irq4 : state_type := "11001101";
constant irq6 : state_type := "11001111";
constant s11 : state_type := "11001110";
constant s12 : state_type := "11001010";
constant s20 : state_type := "11001011";
constant s14 : state_type := "11001001";
constant s21 : state_type := "11001000";
constant s23 : state_type := "11011000";
constant s15 : state_type := "11011001";
constant s25 : state_type := "11011011";
constant s28 : state_type := "11011010";
constant s16 : state_type := "11011110";
constant s30 : state_type := "11011111";
constant s31 : state_type := "11011101";
constant s32 : state_type := "11011100";
constant s33 : state_type := "11010100";
constant s34 : state_type := "11010101";
constant s36 : state_type := "11010111";
constant jmp3_2 : state_type := "11010110";
constant s601 : state_type := "11010010";
constant s602 : state_type := "11010011";
constant s270 : state_type := "11010001";
constant s307 : state_type := "11010000";
constant s308 : state_type := "11110000";
constant s271 : state_type := "11110001";
constant s272 : state_type := "11110011";
constant s309 : state_type := "11110010";
constant RES2 : state_type := "11110110";
-- Declare current and next state signals
signal current_state : state_type;
signal next_state : state_type;
-- Declare any pre-registered internal signals
signal d_o_cld : std_logic_vector ( 7 downto 0 );
signal rd_o_cld : std_logic ;
signal sync_o_cld : std_logic ;
signal wr_n_o_cld : std_logic ;
signal wr_o_cld : std_logic ;
begin
-----------------------------------------------------------------
clocked_proc : process (
clk_clk_i,
rst_rst_n_i
)
-----------------------------------------------------------------
begin
if (rst_rst_n_i = '0') then
current_state <= RES;
-- Default Reset Values
d_o_cld <= X"00";
rd_o_cld <= '0';
sync_o_cld <= '0';
wr_n_o_cld <= '1';
wr_o_cld <= '0';
reg_F <= "00110100";
reg_PC <= X"0000";
reg_PC1 <= X"0000";
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_rb_in <= "00";
reg_sel_rb_out <= "00";
reg_sel_reg <= "00";
reg_sel_sp_as <= '0';
reg_sel_sp_in <= '0';
sig_PC <= X"0000";
zw_PC <= X"0000";
zw_REG_ALU <= '0' & X"00";
zw_REG_OP <= X"00";
zw_REG_sig_PC <= X"0000";
zw_b1 <= X"00";
zw_b2 <= X"00";
zw_b3 <= X"00";
zw_b4 <= X"00";
zw_so <= '0';
zw_w1 <= X"0000";
zw_w2 <= X"0000";
zw_w3 <= X"0000";
elsif (clk_clk_i'event and clk_clk_i = '1') then
current_state <= next_state;
-- Default Assignment To Internals
reg_F <= reg_F(7) & (zw_so OR reg_F(6)) & reg_F(5 downto 0);
reg_PC <= reg_PC;
reg_PC1 <= reg_PC1;
reg_sel_pc_in <= reg_sel_pc_in;
reg_sel_pc_val <= reg_sel_pc_val;
reg_sel_rb_in <= reg_sel_rb_in;
reg_sel_rb_out <= reg_sel_rb_out;
reg_sel_reg <= reg_sel_reg;
reg_sel_sp_as <= reg_sel_sp_as;
reg_sel_sp_in <= reg_sel_sp_in;
sig_PC <= sig_PC;
zw_PC <= zw_PC;
zw_REG_ALU <= zw_REG_ALU;
zw_REG_OP <= zw_REG_OP;
zw_REG_sig_PC <= zw_REG_sig_PC;
zw_b1 <= zw_b1;
zw_b2 <= zw_b2;
zw_b3 <= zw_b3;
zw_b4 <= zw_b4;
zw_so <= (zw_so OR (NOT(so_n_i))) AND (NOT(reg_F(6)));
zw_w1 <= zw_w1;
zw_w2 <= zw_w2;
zw_w3 <= zw_w3;
d_o_cld <= sig_D_OUT;
rd_o_cld <= sig_RD;
sync_o_cld <= sig_SYNC;
wr_n_o_cld <= sig_RWn;
wr_o_cld <= sig_WR;
-- Combined Actions
case current_state is
when s544 =>
if (rdy_i = '1') then
sig_PC <= adr_sp_i;
end if;
when s545 =>
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
if (rdy_i = '1') then
sig_PC <= adr_sp_i;
end if;
when s546 =>
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
end if;
when s547 =>
zw_w1 (7 downto 0) <= d_i;
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
reg_sel_pc_in <= '1';
reg_sel_pc_val <= "11";
end if;
when s549 =>
reg_F(2) <= '1';
reg_F(3) <= '0';
reg_F(5) <= '1';
if (rdy_i = '1') then
sig_PC <= d_i & zw_w1 (7 downto 0);
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s550 =>
if (rdy_i = '1') then
sig_PC <= adr_sp_i;
reg_sel_pc_in <= '1';
reg_sel_pc_val <= "00";
end if;
when RES =>
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
when FETCH =>
zw_REG_OP <= d_i;
if ((d_i = X"00") and (rdy_i = '1')) then
sig_PC <= adr_nxt_pc_i;
elsif ((nmi_i = '1') and (rdy_i = '1')) then
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
sig_PC <= adr_nxt_pc_i;
zw_w3 <= adr_pc_i;
elsif ((irq_n_i = '0' and
reg_F(2) = '0') and (rdy_i = '1')) then
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
sig_PC <= adr_nxt_pc_i;
zw_w3 <= adr_pc_i;
elsif ((d_i = X"58") and (rdy_i = '1')) then
elsif ((d_i = X"28") and (rdy_i = '1')) then
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '0';
elsif ((d_i = X"78") and (rdy_i = '1')) then
elsif ((d_i = X"69" or
d_i = X"65" or
d_i = X"75" or
d_i = X"6D" or
d_i = X"7D" or
d_i = X"79" or
d_i = X"61" or
d_i = X"71" or
d_i = X"72") and (rdy_i = '1')) then
sig_PC <= adr_nxt_pc_i;
reg_sel_reg <= "00";
reg_sel_rb_in <= "11";
elsif ((d_i = X"06" or
d_i = X"16" or
d_i = X"0E" or
d_i = X"1E" or
d_i (3 downto 0) = X"7" or
d_i = X"14" or
d_i = X"04" or
d_i = X"0C" or
d_i = X"1C") and (rdy_i = '1')) then
sig_PC <= adr_nxt_pc_i;
elsif ((d_i = X"90" or
d_i = X"B0" or
d_i = X"F0" or
d_i = X"30" or
d_i = X"D0" or
d_i = X"10" or
d_i = X"50" or
d_i = X"70" or
d_i = X"80") and (rdy_i = '1')) then
sig_PC <= adr_nxt_pc_i;
elsif ((d_i = X"24" or
d_i = X"2C" or
d_i = X"3C" or
d_i = X"34" or
d_i = X"89") and (rdy_i = '1')) then
sig_PC <= adr_nxt_pc_i;
elsif ((d_i = X"18") and (rdy_i = '1')) then
elsif ((d_i = X"D8") and (rdy_i = '1')) then
elsif ((d_i = X"8F" or
d_i = X"9F" or
d_i = X"AF" or
d_i = X"BF" or
d_i = X"CF" or
d_i = X"DF" or
d_i = X"EF" or
d_i = X"FF" or
d_i = X"0F" or
d_i = X"1F" or
d_i = X"2F" or
d_i = X"3F" or
d_i = X"4F" or
d_i = X"5F" or
d_i = X"6F" or
d_i = X"7F") and (rdy_i = '1')) then
sig_PC <= adr_nxt_pc_i;
elsif ((d_i = X"B8") and (rdy_i = '1')) then
elsif ((d_i = X"E0" or
d_i = X"E4" or
d_i = X"EC") and (rdy_i = '1')) then
reg_sel_rb_out <= "01";
sig_PC <= adr_nxt_pc_i;
elsif ((d_i = X"C0" or
d_i = X"C4" or
d_i = X"CC") and (rdy_i = '1')) then
reg_sel_rb_out <= "10";
sig_PC <= adr_nxt_pc_i;
elsif ((d_i = X"C6" or
d_i = X"D6" or
d_i = X"CE" or
d_i = X"DE") and (rdy_i = '1')) then
zw_b4 <= X"FF";
sig_PC <= adr_nxt_pc_i;
elsif ((d_i = X"CA") and (rdy_i = '1')) then
reg_sel_rb_out <= "01";
reg_sel_reg <= "01";
reg_sel_rb_in <= "11";
zw_b4 <= X"FF";
elsif ((d_i = X"88") and (rdy_i = '1')) then
reg_sel_rb_out <= "10";
reg_sel_reg <= "10";
reg_sel_rb_in <= "11";
zw_b4 <= X"FF";
elsif ((d_i = X"49" or
d_i = X"45" or
d_i = X"55" or
d_i = X"4D" or
d_i = X"5D" or
d_i = X"59" or
d_i = X"41" or
d_i = X"51" or
d_i = X"09" or
d_i = X"05" or
d_i = X"15" or
d_i = X"0D" or
d_i = X"1D" or
d_i = X"19" or
d_i = X"01" or
d_i = X"11" or
d_i = X"29" or
d_i = X"25" or
d_i = X"35" or
d_i = X"2D" or
d_i = X"3D" or
d_i = X"39" or
d_i = X"21" or
d_i = X"31" or
d_i = X"C9" or
d_i = X"C5" or
d_i = X"D5" or
d_i = X"CD" or
d_i = X"DD" or
d_i = X"D9" or
d_i = X"C1" or
d_i = X"D1" or
d_i = X"32" or
d_i = X"D2" or
d_i = X"52" or
d_i = X"12") and (rdy_i = '1')) then
reg_sel_rb_out <= "00";
reg_sel_reg <= "00";
reg_sel_rb_in <= "11";
sig_PC <= adr_nxt_pc_i;
elsif ((d_i = X"E6" or
d_i = X"F6" or
d_i = X"EE" or
d_i = X"FE") and (rdy_i = '1')) then
zw_b4 <= X"01";
sig_PC <= adr_nxt_pc_i;
elsif ((d_i = X"E8") and (rdy_i = '1')) then
reg_sel_rb_out <= "01";
reg_sel_reg <= "01";
reg_sel_rb_in <= "11";
zw_b4 <= X"01";
elsif ((d_i = X"C8") and (rdy_i = '1')) then
reg_sel_rb_out <= "10";
reg_sel_reg <= "10";
reg_sel_rb_in <= "11";
zw_b4 <= X"01";
elsif ((d_i = X"4C" or
d_i = X"6C" or
d_i = X"7C") and (rdy_i = '1')) then
sig_PC <= adr_nxt_pc_i;
elsif ((d_i = X"20") and (rdy_i = '1')) then
sig_PC <= adr_nxt_pc_i;
elsif ((d_i = X"A9" or
d_i = X"A5" or
d_i = X"B5" or
d_i = X"AD" or
d_i = X"BD" or
d_i = X"B9" or
d_i = X"A1" or
d_i = X"B1" or
d_i = X"B2") and (rdy_i = '1')) then
reg_sel_reg <= "00";
reg_sel_rb_in <= "11";
sig_PC <= adr_nxt_pc_i;
elsif ((d_i = X"A2" or
d_i = X"A6" or
d_i = X"B6" or
d_i = X"AE" or
d_i = X"BE") and (rdy_i = '1')) then
reg_sel_reg <= "01";
reg_sel_rb_in <= "11";
sig_PC <= adr_nxt_pc_i;
elsif ((d_i = X"A0" or
d_i = X"A4" or
d_i = X"B4" or
d_i = X"AC" or
d_i = X"BC") and (rdy_i = '1')) then
reg_sel_reg <= "10";
reg_sel_rb_in <= "11";
sig_PC <= adr_nxt_pc_i;
elsif ((d_i = X"46" or
d_i = X"56" or
d_i = X"4E" or
d_i = X"5E") and (rdy_i = '1')) then
sig_PC <= adr_nxt_pc_i;
elsif ((d_i = X"EA") and (rdy_i = '1')) then
elsif ((d_i = X"48") and (rdy_i = '1')) then
reg_sel_rb_out <= "00";
sig_PC <= adr_nxt_pc_i;
elsif ((d_i = X"08") and (rdy_i = '1')) then
sig_PC <= adr_nxt_pc_i;
elsif ((d_i = X"7A") and (rdy_i = '1')) then
reg_sel_reg <= "10";
reg_sel_rb_in <= "11";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '0';
elsif ((d_i = X"26" or
d_i = X"36" or
d_i = X"2E" or
d_i = X"3E") and (rdy_i = '1')) then
sig_PC <= adr_nxt_pc_i;
elsif ((d_i = X"66" or
d_i = X"76" or
d_i = X"6E" or
d_i = X"7E") and (rdy_i = '1')) then
sig_PC <= adr_nxt_pc_i;
elsif ((d_i = X"40") and (rdy_i = '1')) then
sig_PC <= adr_nxt_pc_i;
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '0';
elsif ((d_i = X"60") and (rdy_i = '1')) then
sig_PC <= adr_nxt_pc_i;
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '0';
elsif ((d_i = X"E9" or
d_i = X"E5" or
d_i = X"F5" or
d_i = X"ED" or
d_i = X"FD" or
d_i = X"F9" or
d_i = X"E1" or
d_i = X"F1" or
d_i = X"F2") and (rdy_i = '1')) then
sig_PC <= adr_nxt_pc_i;
reg_sel_reg <= "00";
reg_sel_rb_in <= "11";
elsif ((d_i = X"38") and (rdy_i = '1')) then
elsif ((d_i = X"F8") and (rdy_i = '1')) then
elsif ((d_i = X"85" or
d_i = X"95" or
d_i = X"8D" or
d_i = X"9D" or
d_i = X"99" or
d_i = X"81" or
d_i = X"91" or
d_i = X"92") and (rdy_i = '1')) then
reg_sel_rb_out <= "00";
sig_PC <= adr_nxt_pc_i;
elsif ((d_i = X"86" or
d_i = X"96" or
d_i = X"8E") and (rdy_i = '1')) then
reg_sel_rb_out <= "01";
sig_PC <= adr_nxt_pc_i;
elsif ((d_i = X"84" or
d_i = X"94" or
d_i = X"8C") and (rdy_i = '1')) then
reg_sel_rb_out <= "10";
sig_PC <= adr_nxt_pc_i;
elsif ((d_i = X"AA") and (rdy_i = '1')) then
reg_sel_rb_out <= "00";
reg_sel_reg <= "01";
reg_sel_rb_in <= "00";
reg_sel_sp_in <= '1';
reg_sel_sp_as <= '0';
elsif ((d_i = X"0A") and (rdy_i = '1')) then
reg_sel_rb_out <= "00";
reg_sel_reg <= "00";
reg_sel_rb_in <= "11";
elsif ((d_i = X"4A") and (rdy_i = '1')) then
reg_sel_rb_out <= "00";
reg_sel_reg <= "00";
reg_sel_rb_in <= "11";
elsif ((d_i = X"2A") and (rdy_i = '1')) then
reg_sel_rb_out <= "00";
reg_sel_reg <= "00";
reg_sel_rb_in <= "11";
elsif ((d_i = X"6A") and (rdy_i = '1')) then
reg_sel_rb_out <= "00";
reg_sel_reg <= "00";
reg_sel_rb_in <= "11";
elsif ((d_i = X"A8") and (rdy_i = '1')) then
reg_sel_rb_out <= "00";
reg_sel_reg <= "10";
reg_sel_rb_in <= "00";
reg_sel_sp_in <= '1';
reg_sel_sp_as <= '0';
elsif ((d_i = X"98") and (rdy_i = '1')) then
reg_sel_rb_out <= "10";
reg_sel_reg <= "00";
reg_sel_rb_in <= "01";
reg_sel_sp_in <= '1';
reg_sel_sp_as <= '0';
elsif ((d_i = X"BA") and (rdy_i = '1')) then
reg_sel_rb_out <= "01";
reg_sel_reg <= "01";
reg_sel_rb_in <= "11";
reg_sel_sp_in <= '1';
reg_sel_sp_as <= '0';
elsif ((d_i = X"8A") and (rdy_i = '1')) then
reg_sel_rb_out <= "01";
reg_sel_reg <= "00";
reg_sel_rb_in <= "10";
reg_sel_sp_in <= '1';
reg_sel_sp_as <= '0';
elsif ((d_i = X"9A") and (rdy_i = '1')) then
reg_sel_rb_out <= "01";
reg_sel_reg <= "11";
reg_sel_rb_in <= "11";
reg_sel_sp_in <= '1';
reg_sel_sp_as <= '0';
elsif ((d_i = X"DA") and (rdy_i = '1')) then
reg_sel_rb_out <= "01";
sig_PC <= adr_nxt_pc_i;
elsif ((d_i = X"5A") and (rdy_i = '1')) then
reg_sel_rb_out <= "10";
sig_PC <= adr_nxt_pc_i;
elsif ((d_i = X"68") and (rdy_i = '1')) then
reg_sel_reg <= "00";
reg_sel_rb_in <= "11";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '0';
elsif ((d_i = X"FA") and (rdy_i = '1')) then
reg_sel_reg <= "01";
reg_sel_rb_in <= "11";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '0';
elsif ((d_i = X"9C" or
d_i = X"9E" or
d_i = X"64" or
d_i = X"74") and (rdy_i = '1')) then
reg_sel_rb_out <= "11";
sig_PC <= adr_nxt_pc_i;
elsif ((d_i = X"3A") and (rdy_i = '1')) then
reg_sel_rb_out <= "00";
reg_sel_reg <= "00";
reg_sel_rb_in <= "11";
zw_b4 <= X"FF";
elsif ((d_i = X"1A") and (rdy_i = '1')) then
reg_sel_rb_out <= "00";
reg_sel_reg <= "00";
reg_sel_rb_in <= "11";
zw_b4 <= X"01";
elsif ((d_i = X"EA") and (rdy_i = '1')) then
elsif ((d_i = X"02" or
d_i = X"22" or
d_i = X"42" or
d_i = X"62" or
d_i = X"82" or
d_i = X"C2" or
d_i = X"E2") and (rdy_i = '1')) then
elsif ((d_i = X"44") and (rdy_i = '1')) then
elsif ((d_i = X"54" or
d_i = X"D4" or
d_i = X"F4") and (rdy_i = '1')) then
elsif ((d_i = X"DC" or
d_i = X"FC") and (rdy_i = '1')) then
elsif ((d_i = X"5C") and (rdy_i = '1')) then
elsif ((d_i(3 downto 0) = X"3" or
d_i(3 downto 0) = X"B") and (rdy_i = '1')) then
sig_PC <= adr_nxt_pc_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s6 =>
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s7 =>
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
reg_F(0) <= '1';
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s8 =>
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
reg_F(3) <= '1';
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s9 =>
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
reg_F(2) <= '1';
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s10 =>
if (rdy_i = '1' and
zw_REG_OP = X"9A") then
sig_PC <= adr_pc_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
elsif (rdy_i = '1' and
zw_REG_OP = X"BA") then
sig_PC <= adr_pc_i;
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
elsif (rdy_i = '1') then
sig_PC <= adr_pc_i;
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s13 =>
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
reg_F(0) <= '0';
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s18 =>
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
reg_F(3) <= '0';
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s19 =>
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
reg_F(2) <= '0';
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s26 =>
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
reg_F(6) <= '0';
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s27 =>
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s203 =>
if (rdy_i = '1' and
(zw_REG_OP = X"A5" OR zw_REG_OP = X"A6" OR
zw_REG_OP = X"A4" OR zw_REG_OP = X"45" OR
zw_REG_OP = X"05" OR zw_REG_OP = X"25" OR
zw_REG_OP = X"C5" OR zw_REG_OP = X"E4" OR zw_REG_OP = X"C4")) then
sig_PC <= X"00" & d_i;
elsif ((rdy_i = '1' and
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"09" or zw_REG_OP = X"05" or
zw_REG_OP = X"15" or zw_REG_OP = X"0D" or
zw_REG_OP = X"1D" or zw_REG_OP = X"19" or
zw_REG_OP = X"01" or zw_REG_OP = X"11" or
zw_REG_OP = X"12")) then
sig_PC <= adr_nxt_pc_i;
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
elsif ((rdy_i = '1' and
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"49" or zw_REG_OP = X"45" or
zw_REG_OP = X"55" or zw_REG_OP = X"4D" or
zw_REG_OP = X"5D" or zw_REG_OP = X"59" or
zw_REG_OP = X"41" or zw_REG_OP = X"51" or
zw_REG_OP = X"52")) then
sig_PC <= adr_nxt_pc_i;
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
elsif ((rdy_i = '1' and
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"29" or zw_REG_OP = X"25" or
zw_REG_OP = X"35" or zw_REG_OP = X"2D" or
zw_REG_OP = X"3D" or zw_REG_OP = X"39" or
zw_REG_OP = X"21" or zw_REG_OP = X"31" or
zw_REG_OP = X"32")) then
sig_PC <= adr_nxt_pc_i;
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
elsif ((rdy_i = '1' and
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or
zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or
zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or
zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or
zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or
zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or
zw_REG_OP = X"CC" or zw_REG_OP = X"EC" or
zw_REG_OP = X"D2")) then
sig_PC <= adr_nxt_pc_i;
reg_F(7) <= zw_ALU(7);
reg_F(0) <= zw_ALU(8);
reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
(zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
(zw_ALU(0)));
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
elsif (rdy_i = '1' and
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) then
sig_PC <= adr_nxt_pc_i;
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
elsif (rdy_i = '1' and
(zw_REG_OP = X"B5" OR
zw_REG_OP = X"B4" OR
zw_REG_OP = X"55" OR zw_REG_OP = X"15" OR
zw_REG_OP = X"35" OR
zw_REG_OP = X"D5")) then
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
elsif (rdy_i = '1' and
(zw_REG_OP = X"AD" OR
zw_REG_OP = X"AE" OR
zw_REG_OP = X"AC" OR
zw_REG_OP = X"4D" OR
zw_REG_OP = X"0D" OR
zw_REG_OP = X"2D" OR
zw_REG_OP = X"CD" OR
zw_REG_OP = X"EC" OR
zw_REG_OP = X"CC")) then
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_i;
elsif (rdy_i = '1' and
(zw_REG_OP = X"BD" OR
zw_REG_OP = X"BC" OR
zw_REG_OP = X"5D" OR
zw_REG_OP = X"1D" OR
zw_REG_OP = X"3D" OR
zw_REG_OP = X"DD")) then
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_alu_i;
zw_b2(0) <= reg_0flag_i;
elsif (rdy_i = '1' and
(zw_REG_OP = X"B9" OR
zw_REG_OP = X"BE" OR
zw_REG_OP = X"59" OR
zw_REG_OP = X"19" OR
zw_REG_OP = X"39" OR
zw_REG_OP = X"D9")) then
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_alu_i;
zw_b2(0) <= reg_0flag_i;
elsif (rdy_i = '1' and
(zw_REG_OP = X"B1" OR
zw_REG_OP = X"51" OR
zw_REG_OP = X"11" OR
zw_REG_OP = X"31" OR
zw_REG_OP = X"D1")) then
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
elsif (rdy_i = '1' and
(zw_REG_OP = X"A1" OR
zw_REG_OP = X"41" OR
zw_REG_OP = X"01" OR
zw_REG_OP = X"21" OR
zw_REG_OP = X"C1")) then
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"B6") then
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
elsif (rdy_i = '1' and
(zw_REG_OP = X"32" OR
zw_REG_OP = X"D2" OR
zw_REG_OP = X"52" OR
zw_REG_OP = X"B2" OR
zw_REG_OP = X"12")) then
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
end if;
when s204 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
end if;
when s212 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
zw_b3 <= d_alu_i;
end if;
when s216 =>
if (rdy_i = '1') then
sig_PC <= X"00" & zw_b1;
zw_b1 <= d_alu_i;
zw_b2(0) <= reg_0flag_i;
end if;
when s219 =>
if (rdy_i = '1') then
sig_PC <= X"00" & zw_b1;
end if;
when s220 =>
if (rdy_i = '1') then
sig_PC <= X"00" & zw_b1;
end if;
when s227 =>
if (rdy_i = '1') then
sig_PC <= X"00" & d_alu_i;
zw_b1 <= d_i;
end if;
when s228 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
zw_b3 <= d_alu_i;
end if;
when s230 =>
if ((rdy_i = '1') and (zw_REG_OP = X"09" or zw_REG_OP = X"05" or
zw_REG_OP = X"15" or zw_REG_OP = X"0D" or
zw_REG_OP = X"1D" or zw_REG_OP = X"19" or
zw_REG_OP = X"01" or zw_REG_OP = X"11" or
zw_REG_OP = X"12")) then
sig_PC <= adr_pc_i;
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
elsif ((rdy_i = '1') and (zw_REG_OP = X"49" or zw_REG_OP = X"45" or
zw_REG_OP = X"55" or zw_REG_OP = X"4D" or
zw_REG_OP = X"5D" or zw_REG_OP = X"59" or
zw_REG_OP = X"41" or zw_REG_OP = X"51" or
zw_REG_OP = X"52")) then
sig_PC <= adr_pc_i;
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
elsif ((rdy_i = '1') and (zw_REG_OP = X"29" or zw_REG_OP = X"25" or
zw_REG_OP = X"35" or zw_REG_OP = X"2D" or
zw_REG_OP = X"3D" or zw_REG_OP = X"39" or
zw_REG_OP = X"21" or zw_REG_OP = X"31" or
zw_REG_OP = X"32")) then
sig_PC <= adr_pc_i;
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
elsif ((rdy_i = '1') and (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or
zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or
zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or
zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or
zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or
zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or
zw_REG_OP = X"CC" or zw_REG_OP = X"EC" or
zw_REG_OP = X"D2")) then
sig_PC <= adr_pc_i;
reg_F(7) <= zw_ALU(7);
reg_F(0) <= zw_ALU(8);
reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
(zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
(zw_ALU(0)));
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
elsif (rdy_i = '1') then
sig_PC <= adr_pc_i;
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s231 =>
if ((rdy_i = '1' AND
zw_b2(0) = '0') and (zw_REG_OP = X"09" or zw_REG_OP = X"05" or
zw_REG_OP = X"15" or zw_REG_OP = X"0D" or
zw_REG_OP = X"1D" or zw_REG_OP = X"19" or
zw_REG_OP = X"01" or zw_REG_OP = X"11" or
zw_REG_OP = X"12")) then
sig_PC <= adr_pc_i;
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
elsif ((rdy_i = '1' AND
zw_b2(0) = '0') and (zw_REG_OP = X"49" or zw_REG_OP = X"45" or
zw_REG_OP = X"55" or zw_REG_OP = X"4D" or
zw_REG_OP = X"5D" or zw_REG_OP = X"59" or
zw_REG_OP = X"41" or zw_REG_OP = X"51" or
zw_REG_OP = X"52")) then
sig_PC <= adr_pc_i;
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
elsif ((rdy_i = '1' AND
zw_b2(0) = '0') and (zw_REG_OP = X"29" or zw_REG_OP = X"25" or
zw_REG_OP = X"35" or zw_REG_OP = X"2D" or
zw_REG_OP = X"3D" or zw_REG_OP = X"39" or
zw_REG_OP = X"21" or zw_REG_OP = X"31" or
zw_REG_OP = X"32")) then
sig_PC <= adr_pc_i;
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
elsif ((rdy_i = '1' AND
zw_b2(0) = '0') and (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or
zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or
zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or
zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or
zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or
zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or
zw_REG_OP = X"CC" or zw_REG_OP = X"EC" or
zw_REG_OP = X"D2")) then
sig_PC <= adr_pc_i;
reg_F(7) <= zw_ALU(7);
reg_F(0) <= zw_ALU(8);
reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
(zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
(zw_ALU(0)));
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
elsif (rdy_i = '1' AND
zw_b2(0) = '0') then
sig_PC <= adr_pc_i;
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
elsif (rdy_i = '1') then
sig_PC <= zw_b3 & zw_b1;
end if;
when s229 =>
if (rdy_i = '1') then
sig_PC <= X"00" & zw_b1;
zw_b1 <= d_i;
end if;
when s512 =>
if (rdy_i = '1' and
zw_REG_OP = X"65") then
sig_PC <= X"00" & d_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"69" and
reg_F(3) = '0') then
sig_PC <= adr_nxt_pc_i;
reg_F(7) <= zw_ALU(7);
reg_F(6) <= (zw_ALU(7) AND (NOT q_a_i(7)) AND (NOT d_i(7))) OR
(NOT zw_ALU(7) AND (q_a_i(7)) AND (d_i(7)));
reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
(zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
(zw_ALU(0)));
reg_F(0) <= zw_ALU(8);
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
elsif (rdy_i = '1' and
zw_REG_OP = X"75") then
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"6D") then
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"7D") then
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_alu_i;
zw_b2(0) <= reg_0flag_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"79") then
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_alu_i;
zw_b2(0) <= reg_0flag_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"71") then
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"61") then
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"69" and
reg_F(3) = '1') then
sig_PC <= adr_nxt_pc_i;
reg_F(7) <= zw_ALU(7);
reg_F(6) <= (zw_ALU5(3) XOR q_a_i(7)) AND (NOT (q_a_i(7) XOR d_i(7)));
reg_F(1) <= NOT (zw_ALU(7) OR zw_ALU(6) OR zw_ALU(5) OR
zw_ALU(4) OR zw_ALU(3) OR zw_ALU(2) OR zw_ALU(1) OR
zw_ALU(0));
reg_F(0) <= zw_ALU4(4);
elsif (rdy_i = '1' and
zw_REG_OP = X"72") then
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
end if;
when s554 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
end if;
when s578 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
zw_b3 <= d_alu_i;
end if;
when s581 =>
if (rdy_i = '1') then
sig_PC <= X"00" & zw_b1;
zw_b1 <= d_alu_i;
zw_b2(0) <= reg_0flag_i;
end if;
when s582 =>
if (rdy_i = '1') then
sig_PC <= X"00" & zw_b1;
end if;
when s583 =>
if (rdy_i = '1') then
sig_PC <= X"00" & zw_b1;
end if;
when s584 =>
if (rdy_i = '1') then
sig_PC <= X"00" & d_alu_i;
zw_b1 <= d_i;
end if;
when s585 =>
if (rdy_i = '1' AND
zw_b2(0) = '0' and
reg_F(3) = '0') then
sig_PC <= adr_pc_i;
reg_F(7) <= zw_ALU(7);
reg_F(6) <= (zw_ALU(7) AND (NOT q_a_i(7)) AND (NOT d_i(7))) OR
(NOT zw_ALU(7) AND (q_a_i(7)) AND (d_i(7)));
reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
(zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
(zw_ALU(0)));
reg_F(0) <= zw_ALU(8);
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
elsif (rdy_i = '1' AND
zw_b2(0) = '0' and
reg_F(3) = '1') then
sig_PC <= adr_pc_i;
reg_F(7) <= zw_ALU(7);
reg_F(6) <= (zw_ALU5(3) XOR q_a_i(7)) AND (NOT (q_a_i(7) XOR d_i(7)));
reg_F(1) <= NOT (zw_ALU(7) OR zw_ALU(6) OR zw_ALU(5) OR
zw_ALU(4) OR zw_ALU(3) OR zw_ALU(2) OR zw_ALU(1) OR
zw_ALU(0));
reg_F(0) <= zw_ALU4(4);
elsif (rdy_i = '1') then
sig_PC <= zw_b3 & zw_b1;
end if;
when s586 =>
if (rdy_i = '1' and
reg_F(3) = '0') then
sig_PC <= adr_pc_i;
reg_F(7) <= zw_ALU(7);
reg_F(6) <= (zw_ALU(7) AND (NOT q_a_i(7)) AND (NOT d_i(7))) OR
(NOT zw_ALU(7) AND (q_a_i(7)) AND (d_i(7)));
reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
(zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
(zw_ALU(0)));
reg_F(0) <= zw_ALU(8);
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
elsif (rdy_i = '1' and
reg_F(3) = '1') then
sig_PC <= adr_pc_i;
reg_F(7) <= zw_ALU(7);
reg_F(6) <= (zw_ALU5(3) XOR q_a_i(7)) AND (NOT (q_a_i(7) XOR d_i(7)));
reg_F(1) <= NOT (zw_ALU(7) OR zw_ALU(6) OR zw_ALU(5) OR
zw_ALU(4) OR zw_ALU(3) OR zw_ALU(2) OR zw_ALU(1) OR
zw_ALU(0));
reg_F(0) <= zw_ALU4(4);
end if;
when s587 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
zw_b3 <= d_alu_i;
end if;
when s580 =>
if (rdy_i = '1') then
sig_PC <= X"00" & zw_b1;
zw_b1 <= d_i;
end if;
when s178 =>
if (rdy_i = '1' and
(zw_REG_OP = X"85" OR
zw_REG_OP = X"86" OR
zw_REG_OP = X"64" OR
zw_REG_OP = X"84")) then
sig_PC <= X"00" & d_i;
elsif (rdy_i = '1' and
(zw_REG_OP = X"95" OR
zw_REG_OP = X"74" OR
zw_REG_OP = X"94")) then
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
elsif (rdy_i = '1' and
(zw_REG_OP = X"8D" OR
zw_REG_OP = X"8E" OR
zw_REG_OP = X"9C" OR
zw_REG_OP = X"8C")) then
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_i;
elsif (rdy_i = '1' and
(zw_REG_OP = X"9D" OR
zw_REG_OP = X"9E")) then
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_alu_i;
zw_b2(0) <= reg_0flag_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"99") then
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_alu_i;
zw_b2(0) <= reg_0flag_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"91") then
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"81") then
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"96") then
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"92") then
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
end if;
when s194 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
zw_b3 <= d_alu_i;
end if;
when s195 =>
if (rdy_i = '1') then
sig_PC <= X"00" & zw_b1;
zw_b1 <= d_alu_i;
zw_b2(0) <= reg_0flag_i;
end if;
when s196 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
end if;
when s197 =>
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s198 =>
if (rdy_i = '1') then
sig_PC <= X"00" & zw_b1;
end if;
when s199 =>
if (rdy_i = '1') then
sig_PC <= X"00" & zw_b1;
end if;
when s200 =>
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s205 =>
if (rdy_i = '1') then
sig_PC <= X"00" & d_alu_i;
zw_b1 <= d_i;
end if;
when s206 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
zw_b3 <= d_alu_i;
end if;
when s207 =>
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s208 =>
if (rdy_i = '1') then
sig_PC <= zw_b3 & zw_b1;
end if;
when s209 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
end if;
when s213 =>
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s214 =>
if (rdy_i = '1') then
sig_PC <= X"00" & zw_b1;
zw_b1 <= d_i;
end if;
when s513 =>
if (rdy_i = '1' and
zw_REG_OP = X"E5") then
sig_PC <= X"00" & d_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"E9" and
reg_F(3) = '0') then
sig_PC <= adr_nxt_pc_i;
reg_F(7) <= zw_ALU(7);
reg_F(6) <= (zw_ALU(7) AND (NOT q_a_i(7)) AND (d_i(7))) OR
(NOT zw_ALU(7) AND (q_a_i(7)) AND (NOT d_i(7)));
reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
(zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
(zw_ALU(0)));
reg_F(0) <= (zw_ALU(8) AND (NOT q_a_i(7)) AND (NOT d_i(7))) OR
(zw_ALU(8) AND (q_a_i(7)) AND (d_i(7))) OR
(NOT zw_ALU(8) AND (q_a_i(7)) AND (NOT d_i(7))) OR
(zw_ALU(8) AND (q_a_i(7)) AND (NOT d_i(7)));
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
elsif (rdy_i = '1' and
zw_REG_OP = X"F5") then
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"ED") then
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"FD") then
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_alu_i;
zw_b2(0) <= reg_0flag_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"F9") then
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_alu_i;
zw_b2(0) <= reg_0flag_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"F1") then
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"E1") then
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"E9" and
reg_F(3) = '1') then
sig_PC <= adr_nxt_pc_i;
reg_F(7) <= zw_ALU(7);
reg_F(6) <= (zw_ALU2(3) XOR q_a_i(7)) AND (q_a_i(7) XOR d_i(7));
reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
(zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
(zw_ALU(0)));
reg_F(0) <= (zw_ALU2(4));
elsif (rdy_i = '1' and
zw_REG_OP = X"F2") then
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
end if;
when s588 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
end if;
when s589 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
zw_b3 <= d_alu_i;
end if;
when s590 =>
if (rdy_i = '1') then
sig_PC <= X"00" & zw_b1;
zw_b1 <= d_alu_i;
zw_b2(0) <= reg_0flag_i;
end if;
when s591 =>
if (rdy_i = '1') then
sig_PC <= X"00" & zw_b1;
end if;
when s592 =>
if (rdy_i = '1') then
sig_PC <= X"00" & zw_b1;
end if;
when s593 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
zw_b3 <= d_alu_i;
end if;
when s594 =>
if (rdy_i = '1') then
sig_PC <= X"00" & d_alu_i;
zw_b1 <= d_i;
end if;
when s595 =>
if (rdy_i = '1' AND
zw_b2(0) = '0' and
reg_F(3) = '0') then
sig_PC <= adr_pc_i;
reg_F(7) <= zw_ALU(7);
reg_F(6) <= (zw_ALU(7) AND (NOT q_a_i(7)) AND (d_i(7))) OR
(NOT zw_ALU(7) AND (q_a_i(7)) AND (NOT d_i(7)));
reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
(zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
(zw_ALU(0)));
reg_F(0) <= (zw_ALU(8) AND (NOT q_a_i(7)) AND (NOT d_i(7))) OR
(zw_ALU(8) AND (q_a_i(7)) AND (d_i(7))) OR
(NOT zw_ALU(8) AND (q_a_i(7)) AND (NOT d_i(7))) OR
(zw_ALU(8) AND (q_a_i(7)) AND (NOT d_i(7)));
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
elsif (rdy_i = '1' AND
zw_b2(0) = '0' and
reg_F(3) = '1') then
sig_PC <= adr_pc_i;
reg_F(7) <= zw_ALU(7);
reg_F(6) <= (zw_ALU2(3) XOR q_a_i(7)) AND (q_a_i(7) XOR d_i(7));
reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
(zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
(zw_ALU(0)));
reg_F(0) <= (zw_ALU2(4));
elsif (rdy_i = '1') then
sig_PC <= zw_b3 & zw_b1;
end if;
when s596 =>
if (rdy_i = '1' and
reg_F(3) = '0') then
sig_PC <= adr_pc_i;
reg_F(7) <= zw_ALU(7);
reg_F(6) <= (zw_ALU(7) AND (NOT q_a_i(7)) AND (d_i(7))) OR
(NOT zw_ALU(7) AND (q_a_i(7)) AND (NOT d_i(7)));
reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
(zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
(zw_ALU(0)));
reg_F(0) <= (zw_ALU(8) AND (NOT q_a_i(7)) AND (NOT d_i(7))) OR
(zw_ALU(8) AND (q_a_i(7)) AND (d_i(7))) OR
(NOT zw_ALU(8) AND (q_a_i(7)) AND (NOT d_i(7))) OR
(zw_ALU(8) AND (q_a_i(7)) AND (NOT d_i(7)));
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
elsif (rdy_i = '1' and
reg_F(3) = '1') then
sig_PC <= adr_pc_i;
reg_F(7) <= zw_ALU(7);
reg_F(6) <= (zw_ALU2(3) XOR q_a_i(7)) AND (q_a_i(7) XOR d_i(7));
reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
(zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
(zw_ALU(0)));
reg_F(0) <= (zw_ALU2(4));
end if;
when s597 =>
if (rdy_i = '1') then
sig_PC <= X"00" & zw_b1;
zw_b1 <= d_i;
end if;
when s405 =>
if (rdy_i = '1' and
(zw_REG_OP = X"1E" or
zw_REG_OP = X"7E" or
zw_REG_OP = X"3E" or
zw_REG_OP = X"5E")) then
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_alu_i;
zw_b2(0) <= reg_0flag_i;
elsif (rdy_i = '1' and
(zw_REG_OP = X"06" or zw_REG_OP = X"66" or
zw_REG_OP = X"26" or zw_REG_OP = X"46" or
zw_REG_OP = X"04" or zw_REG_OP = X"14")) then
sig_PC <= X"00" & d_i;
elsif (rdy_i = '1' and
(zw_REG_OP = X"16" or
zw_REG_OP = X"76" or
zw_REG_OP = X"36" or
zw_REG_OP = X"56")) then
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
elsif (rdy_i = '1' and
(zw_REG_OP = X"0E" or
zw_REG_OP = X"6E" or
zw_REG_OP = X"2E" or
zw_REG_OP = X"4E"or
zw_REG_OP = X"0C" or
zw_REG_OP = X"1C")) then
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_i;
elsif (rdy_i = '1' and
zw_REG_OP (3 downto 0) = X"7") then
sig_PC <= X"00" & d_i;
end if;
when s408 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
end if;
when s410 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
zw_b3 <= d_alu_i;
end if;
when s411 =>
if (rdy_i = '1') then
sig_PC <= X"00" & zw_b1;
end if;
when s414 =>
if (rdy_i = '1') then
sig_PC <= zw_b3 & zw_b1;
end if;
when s417 =>
if ((rdy_i = '1' and
(zw_REG_OP = X"06" or
zw_REG_OP = X"16" or
zw_REG_OP = X"0E" or
zw_REG_OP = X"1E")) and (rdy_i = '1')) then
zw_b1 <= d_i(6 downto 0) & '0';
zw_b2(0) <= d_i(7);
elsif ((rdy_i = '1' and
(zw_REG_OP = X"46" or
zw_REG_OP = X"56" or
zw_REG_OP = X"4E" or
zw_REG_OP = X"5E")) and (rdy_i = '1')) then
zw_b1 <= '0' & d_i(7 downto 1);
zw_b2(0) <= d_i(0);
elsif ((rdy_i = '1' and
(zw_REG_OP = X"26" or
zw_REG_OP = X"36" or
zw_REG_OP = X"2E" or
zw_REG_OP = X"3E")) and (rdy_i = '1')) then
zw_b1 <= d_i(6 downto 0) & reg_F(0);
zw_b2(0) <= d_i(7);
elsif ((rdy_i = '1' and
(zw_REG_OP = X"66" or
zw_REG_OP = X"76" or
zw_REG_OP = X"6E" or
zw_REG_OP = X"7E")) and (rdy_i = '1')) then
zw_b1 <= reg_F(0) & d_i(7 downto 1);
zw_b2(0) <= d_i(0);
elsif ((rdy_i = '1' and
zw_REG_OP (7) = '0' and
zw_REG_OP (3 downto 0) = X"7") and (rdy_i = '1')) then
elsif ((rdy_i = '1' and
zw_REG_OP (7) = '1' and
zw_REG_OP (3 downto 0) = X"7") and (rdy_i = '1')) then
elsif ((rdy_i = '1' and
(zw_REG_OP = X"14" or
zw_REG_OP = X"1C")) and (rdy_i = '1')) then
zw_b1 <= d_i and q_a_i;
elsif ((rdy_i = '1' and
(zw_REG_OP = X"04" or
zw_REG_OP = X"0C")) and (rdy_i = '1')) then
zw_b1 <= d_i and q_a_i;
end if;
when s419 =>
if ((zw_REG_OP (3 downto 0) = X"7") and (rdy_i = '1')) then
sig_PC <= adr_pc_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
elsif (((zw_REG_OP = X"14" or
zw_REG_OP = X"04" or
zw_REG_OP = X"0C" or
zw_REG_OP = X"1C")) and (rdy_i = '1')) then
reg_F(1) <= reg_1flag_i;
sig_PC <= adr_pc_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
elsif (rdy_i = '1') then
reg_F(0) <= zw_b2(0);
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
sig_PC <= adr_pc_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s420 =>
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
reg_F(0) <= q_a_i(7);
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s598 =>
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
reg_F(0) <= q_a_i(0);
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s599 =>
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
reg_F(0) <= q_a_i(0);
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s600 =>
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
reg_F(0) <= q_a_i(7);
reg_F(0) <= q_a_i(7);
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s268 =>
zw_b1 <= d_i;
zw_b3 <= adr_nxt_pc_i (15 downto 8);
zw_b2 <= d_i;
if (rdy_i = '1' and (
(reg_F(0) = '1' and zw_REG_OP = X"90") or (reg_F(0) = '0' and zw_REG_OP = X"B0") or
(reg_F(1) = '0' and zw_REG_OP = X"F0") or (reg_F(7) = '0' and zw_REG_OP = X"30") or
(reg_F(1) = '1' and zw_REG_OP = X"D0") or (reg_F(7) = '1' and zw_REG_OP = X"10") or
(reg_F(6) = '1' and zw_REG_OP = X"50") or (reg_F(6) = '0' and zw_REG_OP = X"70"))) then
sig_PC <= adr_nxt_pc_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
elsif (rdy_i = '1') then
sig_PC <= adr_nxt_pc_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "10";
end if;
when s305 =>
if (rdy_i = '1' and
zw_b3 = adr_nxt_pc_i (15 downto 8)) then
sig_PC <= adr_nxt_pc_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
elsif (rdy_i = '1') then
sig_PC <= zw_b3 & adr_nxt_pc_i (7 downto 0);
end if;
when s306 =>
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when jmp1 =>
zw_b1 <= d_i;
if (rdy_i = '1' and
zw_REG_OP = X"4C") then
sig_PC <= adr_nxt_pc_i;
reg_sel_pc_in <= '1';
reg_sel_pc_val <= "11";
elsif (rdy_i = '1' and
zw_REG_OP = X"6C") then
sig_PC <= adr_nxt_pc_i;
reg_sel_pc_in <= '1';
reg_sel_pc_val <= "00";
elsif (rdy_i = '1' and
zw_REG_OP = X"7C") then
sig_PC <= adr_nxt_pc_i;
reg_sel_pc_in <= '1';
reg_sel_pc_val <= "10";
end if;
when jmp2_1 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
end if;
when jmp4_12 =>
zw_b1 <= d_i;
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
reg_sel_pc_in <= '1';
reg_sel_pc_val <= "11";
end if;
when jmp_ex =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when jmp2_2 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
end if;
when s402 =>
zw_b1 <= d_i;
if (rdy_i = '1') then
sig_PC <= adr_sp_i;
end if;
when s422 =>
if (rdy_i = '1') then
sig_PC <= adr_sp_i;
end if;
when s423 =>
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
reg_sel_pc_in <= '1';
reg_sel_pc_val <= "11";
end if;
when s424 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1 (7 downto 0);
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s362 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
end if;
when s221 =>
if (rdy_i = '1' and
zw_REG_OP = X"34") then
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"3C") then
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_alu_i;
zw_b2(0) <= reg_0flag_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"24") then
sig_PC <= X"00" & d_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"2C") then
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"89") then
sig_PC <= adr_nxt_pc_i;
reg_F(1) <= reg_1flag_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s232 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
zw_b3 <= d_alu_i;
end if;
when s233 =>
if (rdy_i = '1') then
sig_PC <= X"00" & zw_b1;
end if;
when s234 =>
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
reg_F(7) <= d_i(7);
reg_F(6) <= d_i(6);
reg_F(1) <= reg_1flag_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s235 =>
if (rdy_i = '1' AND
zw_b2(0) = '0') then
sig_PC <= adr_pc_i;
reg_F(7) <= d_i(7);
reg_F(6) <= d_i(6);
reg_F(1) <= reg_1flag_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
elsif (rdy_i = '1') then
sig_PC <= zw_b3 & zw_b1;
end if;
when brk1 =>
if (rdy_i = '1') then
sig_PC <= adr_sp_i;
end if;
when brk2 =>
if (rdy_i = '1') then
sig_PC <= adr_sp_i;
end if;
when brk3 =>
if (rdy_i = '1') then
sig_PC <= adr_sp_i;
end if;
when brk4 =>
if (rdy_i = '1') then
sig_PC <= X"FFFE";
end if;
when brk6 =>
reg_F(2) <= '1';
reg_F(3) <= '0';
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when brk5 =>
zw_b1 <= d_i;
if (rdy_i = '1') then
sig_PC <= X"FFFF";
reg_sel_pc_in <= '1';
reg_sel_pc_val <= "11";
end if;
when s425 =>
if (rdy_i = '1') then
sig_PC <= adr_sp_i;
end if;
when s426 =>
if (rdy_i = '1') then
sig_PC <= adr_sp_i;
end if;
when s427 =>
reg_F(7 downto 6) <= d_i(7 downto 6);
reg_F(3 downto 0) <= d_i(3 downto 0);
if (rdy_i = '1') then
sig_PC <= adr_sp_i;
reg_sel_pc_in <= '1';
reg_sel_pc_val <= "11";
end if;
when s428 =>
zw_b1 <= d_i;
if (rdy_i = '1') then
sig_PC <= adr_sp_i;
end if;
when s429 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s430 =>
if (rdy_i = '1') then
sig_PC <= adr_sp_i;
end if;
when s431 =>
if (rdy_i = '1') then
sig_PC <= adr_sp_i;
end if;
when s432 =>
zw_b1 <= d_i;
if (rdy_i = '1') then
sig_PC <= adr_sp_i;
reg_sel_pc_in <= '1';
reg_sel_pc_val <= "00";
end if;
when s433 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
end if;
when s434 =>
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s236 =>
if (rdy_i = '1' and
(zw_REG_OP = X"C6" OR
zw_REG_OP = X"E6")) then
sig_PC <= X"00" & d_i;
elsif (rdy_i = '1' and
(zw_REG_OP = X"D6" OR
zw_REG_OP = X"F6")) then
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
elsif (rdy_i = '1' and
(zw_REG_OP = X"CE" OR
zw_REG_OP = X"EE")) then
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_i;
elsif (rdy_i = '1' and
(zw_REG_OP = X"DE" OR
zw_REG_OP = X"FE")) then
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_alu_i;
zw_b2(0) <= reg_0flag_i;
end if;
when s245 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
end if;
when s246 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
zw_b3 <= d_alu_i;
end if;
when s248 =>
if (rdy_i = '1') then
sig_PC <= X"00" & zw_b1;
end if;
when s345 =>
if (rdy_i = '1') then
sig_PC <= zw_b3 & zw_b1;
end if;
when s346 =>
if (rdy_i = '1') then
zw_b1 <= d_alu_i;
end if;
when s253 =>
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s435 =>
if (rdy_i = '1') then
sig_PC <= adr_sp_i;
end if;
when s436 =>
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s437 =>
if (rdy_i = '1') then
sig_PC <= adr_sp_i;
end if;
when s438 =>
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s440 =>
if (rdy_i = '1') then
sig_PC <= adr_sp_i;
end if;
when s441 =>
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s443 =>
if (rdy_i = '1') then
sig_PC <= adr_sp_i;
end if;
when s444 =>
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
reg_F(7 downto 6) <= d_i(7 downto 6);
reg_F(3 downto 0) <= d_i(3 downto 0);
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when irq1 =>
if (rdy_i = '1') then
sig_PC <= adr_sp_i;
end if;
when irq2 =>
if (rdy_i = '1') then
sig_PC <= adr_sp_i;
end if;
when irq3 =>
if (rdy_i = '1') then
sig_PC <= adr_sp_i;
end if;
when irq5b =>
zw_b1 <= d_i;
if (rdy_i = '1') then
sig_PC <= X"FFFF";
reg_sel_pc_in <= '1';
reg_sel_pc_val <= "11";
end if;
when irq5a =>
zw_b1 <= d_i;
if (rdy_i = '1') then
sig_PC <= X"FFFB";
reg_sel_pc_in <= '1';
reg_sel_pc_val <= "11";
end if;
when irq4 =>
if (rdy_i = '1' and
nmi_i = '1') then
sig_PC <= X"FFFA";
elsif (rdy_i = '1') then
sig_PC <= X"FFFE";
end if;
when irq6 =>
reg_F(2) <= '1';
reg_F(3) <= '0';
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s11 =>
if (rdy_i = '1') then
sig_PC <= adr_nxt_pc_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s20 =>
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s23 =>
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s28 =>
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s33 =>
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when jmp3_2 =>
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
end if;
when s601 =>
if (rdy_i = '1') then
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s602 =>
if (rdy_i = '1') then
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s270 =>
if (rdy_i = '1') then
sig_PC <= X"00" & d_i;
end if;
when s307 =>
if (rdy_i = '1' and
zw_b3 = adr_nxt_pc_i (15 downto 8)) then
sig_PC <= adr_nxt_pc_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
elsif (rdy_i = '1') then
sig_PC <= zw_b3 & adr_nxt_pc_i (7 downto 0);
end if;
when s308 =>
zw_b2 <= d_i;
zw_b3 <= adr_nxt_pc_i (15 downto 8);
if (rdy_i = '1' and (
(zw_b1(0) = '0' and zw_REG_OP = X"8F") or
(zw_b1(1) = '0' and zw_REG_OP = X"9F") or
(zw_b1(2) = '0' and zw_REG_OP = X"AF") or
(zw_b1(3) = '0' and zw_REG_OP = X"BF") or
(zw_b1(4) = '0' and zw_REG_OP = X"CF") or
(zw_b1(5) = '0' and zw_REG_OP = X"DF") or
(zw_b1(6) = '0' and zw_REG_OP = X"EF") or
(zw_b1(7) = '0' and zw_REG_OP = X"FF") or
(zw_b1(0) = '1' and zw_REG_OP = X"0F") or
(zw_b1(1) = '1' and zw_REG_OP = X"1F") or
(zw_b1(2) = '1' and zw_REG_OP = X"2F") or
(zw_b1(3) = '1' and zw_REG_OP = X"3F") or
(zw_b1(4) = '1' and zw_REG_OP = X"4F") or
(zw_b1(5) = '1' and zw_REG_OP = X"5F") or
(zw_b1(6) = '1' and zw_REG_OP = X"6F") or
(zw_b1(7) = '1' and zw_REG_OP = X"7F"))) then
sig_PC <= adr_nxt_pc_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
elsif (rdy_i = '1') then
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "10";
end if;
when s272 =>
zw_b1 <= d_i;
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
end if;
when s309 =>
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when RES2 =>
sig_PC <= adr_nxt_pc_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
when others =>
null;
end case;
end if;
end process clocked_proc;
-----------------------------------------------------------------
nextstate_proc : process (
adr_nxt_pc_i,
current_state,
d_i,
irq_n_i,
nmi_i,
rdy_i,
reg_F,
zw_REG_OP,
zw_b1,
zw_b2,
zw_b3
)
-----------------------------------------------------------------
begin
case current_state is
when s544 =>
if (rdy_i = '1') then
next_state <= s550;
else
next_state <= s544;
end if;
when s545 =>
if (rdy_i = '1') then
next_state <= s546;
else
next_state <= s545;
end if;
when s546 =>
if (rdy_i = '1') then
next_state <= s547;
else
next_state <= s546;
end if;
when s547 =>
if (rdy_i = '1') then
next_state <= s549;
else
next_state <= s547;
end if;
when s549 =>
if (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= s549;
end if;
when s550 =>
if (rdy_i = '1') then
next_state <= s545;
else
next_state <= s550;
end if;
when RES =>
next_state <= RES2;
when FETCH =>
if ((d_i = X"00") and (rdy_i = '1')) then
next_state <= brk1;
elsif ((nmi_i = '1') and (rdy_i = '1')) then
next_state <= irq1;
elsif ((irq_n_i = '0' and
reg_F(2) = '0') and (rdy_i = '1')) then
next_state <= irq1;
elsif ((d_i = X"58") and (rdy_i = '1')) then
next_state <= s19;
elsif ((d_i = X"28") and (rdy_i = '1')) then
next_state <= s442;
elsif ((d_i = X"78") and (rdy_i = '1')) then
next_state <= s9;
elsif ((d_i = X"69" or
d_i = X"65" or
d_i = X"75" or
d_i = X"6D" or
d_i = X"7D" or
d_i = X"79" or
d_i = X"61" or
d_i = X"71" or
d_i = X"72") and (rdy_i = '1')) then
next_state <= s512;
elsif ((d_i = X"06" or
d_i = X"16" or
d_i = X"0E" or
d_i = X"1E" or
d_i (3 downto 0) = X"7" or
d_i = X"14" or
d_i = X"04" or
d_i = X"0C" or
d_i = X"1C") and (rdy_i = '1')) then
next_state <= s405;
elsif ((d_i = X"90" or
d_i = X"B0" or
d_i = X"F0" or
d_i = X"30" or
d_i = X"D0" or
d_i = X"10" or
d_i = X"50" or
d_i = X"70" or
d_i = X"80") and (rdy_i = '1')) then
next_state <= s268;
elsif ((d_i = X"24" or
d_i = X"2C" or
d_i = X"3C" or
d_i = X"34" or
d_i = X"89") and (rdy_i = '1')) then
next_state <= s221;
elsif ((d_i = X"18") and (rdy_i = '1')) then
next_state <= s13;
elsif ((d_i = X"D8") and (rdy_i = '1')) then
next_state <= s18;
elsif ((d_i = X"8F" or
d_i = X"9F" or
d_i = X"AF" or
d_i = X"BF" or
d_i = X"CF" or
d_i = X"DF" or
d_i = X"EF" or
d_i = X"FF" or
d_i = X"0F" or
d_i = X"1F" or
d_i = X"2F" or
d_i = X"3F" or
d_i = X"4F" or
d_i = X"5F" or
d_i = X"6F" or
d_i = X"7F") and (rdy_i = '1')) then
next_state <= s270;
elsif ((d_i = X"B8") and (rdy_i = '1')) then
next_state <= s26;
elsif ((d_i = X"E0" or
d_i = X"E4" or
d_i = X"EC") and (rdy_i = '1')) then
next_state <= s203;
elsif ((d_i = X"C0" or
d_i = X"C4" or
d_i = X"CC") and (rdy_i = '1')) then
next_state <= s203;
elsif ((d_i = X"C6" or
d_i = X"D6" or
d_i = X"CE" or
d_i = X"DE") and (rdy_i = '1')) then
next_state <= s236;
elsif ((d_i = X"CA") and (rdy_i = '1')) then
next_state <= s27;
elsif ((d_i = X"88") and (rdy_i = '1')) then
next_state <= s27;
elsif ((d_i = X"49" or
d_i = X"45" or
d_i = X"55" or
d_i = X"4D" or
d_i = X"5D" or
d_i = X"59" or
d_i = X"41" or
d_i = X"51" or
d_i = X"09" or
d_i = X"05" or
d_i = X"15" or
d_i = X"0D" or
d_i = X"1D" or
d_i = X"19" or
d_i = X"01" or
d_i = X"11" or
d_i = X"29" or
d_i = X"25" or
d_i = X"35" or
d_i = X"2D" or
d_i = X"3D" or
d_i = X"39" or
d_i = X"21" or
d_i = X"31" or
d_i = X"C9" or
d_i = X"C5" or
d_i = X"D5" or
d_i = X"CD" or
d_i = X"DD" or
d_i = X"D9" or
d_i = X"C1" or
d_i = X"D1" or
d_i = X"32" or
d_i = X"D2" or
d_i = X"52" or
d_i = X"12") and (rdy_i = '1')) then
next_state <= s203;
elsif ((d_i = X"E6" or
d_i = X"F6" or
d_i = X"EE" or
d_i = X"FE") and (rdy_i = '1')) then
next_state <= s236;
elsif ((d_i = X"E8") and (rdy_i = '1')) then
next_state <= s27;
elsif ((d_i = X"C8") and (rdy_i = '1')) then
next_state <= s27;
elsif ((d_i = X"4C" or
d_i = X"6C" or
d_i = X"7C") and (rdy_i = '1')) then
next_state <= jmp1;
elsif ((d_i = X"20") and (rdy_i = '1')) then
next_state <= s402;
elsif ((d_i = X"A9" or
d_i = X"A5" or
d_i = X"B5" or
d_i = X"AD" or
d_i = X"BD" or
d_i = X"B9" or
d_i = X"A1" or
d_i = X"B1" or
d_i = X"B2") and (rdy_i = '1')) then
next_state <= s203;
elsif ((d_i = X"A2" or
d_i = X"A6" or
d_i = X"B6" or
d_i = X"AE" or
d_i = X"BE") and (rdy_i = '1')) then
next_state <= s203;
elsif ((d_i = X"A0" or
d_i = X"A4" or
d_i = X"B4" or
d_i = X"AC" or
d_i = X"BC") and (rdy_i = '1')) then
next_state <= s203;
elsif ((d_i = X"46" or
d_i = X"56" or
d_i = X"4E" or
d_i = X"5E") and (rdy_i = '1')) then
next_state <= s405;
elsif ((d_i = X"EA") and (rdy_i = '1')) then
next_state <= s6;
elsif ((d_i = X"48") and (rdy_i = '1')) then
next_state <= s435;
elsif ((d_i = X"08") and (rdy_i = '1')) then
next_state <= s437;
elsif ((d_i = X"7A") and (rdy_i = '1')) then
next_state <= s439;
elsif ((d_i = X"26" or
d_i = X"36" or
d_i = X"2E" or
d_i = X"3E") and (rdy_i = '1')) then
next_state <= s405;
elsif ((d_i = X"66" or
d_i = X"76" or
d_i = X"6E" or
d_i = X"7E") and (rdy_i = '1')) then
next_state <= s405;
elsif ((d_i = X"40") and (rdy_i = '1')) then
next_state <= s425;
elsif ((d_i = X"60") and (rdy_i = '1')) then
next_state <= s430;
elsif ((d_i = X"E9" or
d_i = X"E5" or
d_i = X"F5" or
d_i = X"ED" or
d_i = X"FD" or
d_i = X"F9" or
d_i = X"E1" or
d_i = X"F1" or
d_i = X"F2") and (rdy_i = '1')) then
next_state <= s513;
elsif ((d_i = X"38") and (rdy_i = '1')) then
next_state <= s7;
elsif ((d_i = X"F8") and (rdy_i = '1')) then
next_state <= s8;
elsif ((d_i = X"85" or
d_i = X"95" or
d_i = X"8D" or
d_i = X"9D" or
d_i = X"99" or
d_i = X"81" or
d_i = X"91" or
d_i = X"92") and (rdy_i = '1')) then
next_state <= s178;
elsif ((d_i = X"86" or
d_i = X"96" or
d_i = X"8E") and (rdy_i = '1')) then
next_state <= s178;
elsif ((d_i = X"84" or
d_i = X"94" or
d_i = X"8C") and (rdy_i = '1')) then
next_state <= s178;
elsif ((d_i = X"AA") and (rdy_i = '1')) then
next_state <= s10;
elsif ((d_i = X"0A") and (rdy_i = '1')) then
next_state <= s420;
elsif ((d_i = X"4A") and (rdy_i = '1')) then
next_state <= s599;
elsif ((d_i = X"2A") and (rdy_i = '1')) then
next_state <= s600;
elsif ((d_i = X"6A") and (rdy_i = '1')) then
next_state <= s598;
elsif ((d_i = X"A8") and (rdy_i = '1')) then
next_state <= s10;
elsif ((d_i = X"98") and (rdy_i = '1')) then
next_state <= s10;
elsif ((d_i = X"BA") and (rdy_i = '1')) then
next_state <= s10;
elsif ((d_i = X"8A") and (rdy_i = '1')) then
next_state <= s10;
elsif ((d_i = X"9A") and (rdy_i = '1')) then
next_state <= s10;
elsif ((d_i = X"DA") and (rdy_i = '1')) then
next_state <= s435;
elsif ((d_i = X"5A") and (rdy_i = '1')) then
next_state <= s435;
elsif ((d_i = X"68") and (rdy_i = '1')) then
next_state <= s439;
elsif ((d_i = X"FA") and (rdy_i = '1')) then
next_state <= s439;
elsif ((d_i = X"9C" or
d_i = X"9E" or
d_i = X"64" or
d_i = X"74") and (rdy_i = '1')) then
next_state <= s178;
elsif ((d_i = X"3A") and (rdy_i = '1')) then
next_state <= s27;
elsif ((d_i = X"1A") and (rdy_i = '1')) then
next_state <= s27;
elsif ((d_i = X"EA") and (rdy_i = '1')) then
next_state <= s6;
elsif ((d_i = X"02" or
d_i = X"22" or
d_i = X"42" or
d_i = X"62" or
d_i = X"82" or
d_i = X"C2" or
d_i = X"E2") and (rdy_i = '1')) then
next_state <= s11;
elsif ((d_i = X"44") and (rdy_i = '1')) then
next_state <= s12;
elsif ((d_i = X"54" or
d_i = X"D4" or
d_i = X"F4") and (rdy_i = '1')) then
next_state <= s14;
elsif ((d_i = X"DC" or
d_i = X"FC") and (rdy_i = '1')) then
next_state <= s15;
elsif ((d_i = X"5C") and (rdy_i = '1')) then
next_state <= s16;
elsif ((d_i(3 downto 0) = X"3" or
d_i(3 downto 0) = X"B") and (rdy_i = '1')) then
next_state <= FETCH;
else
next_state <= FETCH;
end if;
when s6 =>
if (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= s6;
end if;
when s7 =>
if (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= s7;
end if;
when s8 =>
if (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= s8;
end if;
when s9 =>
if (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= s9;
end if;
when s10 =>
if (rdy_i = '1' and
zw_REG_OP = X"9A") then
next_state <= FETCH;
elsif (rdy_i = '1' and
zw_REG_OP = X"BA") then
next_state <= FETCH;
elsif (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= s10;
end if;
when s13 =>
if (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= s13;
end if;
when s18 =>
if (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= s18;
end if;
when s19 =>
if (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= s19;
end if;
when s26 =>
if (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= s26;
end if;
when s27 =>
if (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= s27;
end if;
when s203 =>
if (rdy_i = '1' and
(zw_REG_OP = X"A5" OR zw_REG_OP = X"A6" OR
zw_REG_OP = X"A4" OR zw_REG_OP = X"45" OR
zw_REG_OP = X"05" OR zw_REG_OP = X"25" OR
zw_REG_OP = X"C5" OR zw_REG_OP = X"E4" OR zw_REG_OP = X"C4")) then
next_state <= s230;
elsif ((rdy_i = '1' and
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"09" or zw_REG_OP = X"05" or
zw_REG_OP = X"15" or zw_REG_OP = X"0D" or
zw_REG_OP = X"1D" or zw_REG_OP = X"19" or
zw_REG_OP = X"01" or zw_REG_OP = X"11" or
zw_REG_OP = X"12")) then
next_state <= FETCH;
elsif ((rdy_i = '1' and
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"49" or zw_REG_OP = X"45" or
zw_REG_OP = X"55" or zw_REG_OP = X"4D" or
zw_REG_OP = X"5D" or zw_REG_OP = X"59" or
zw_REG_OP = X"41" or zw_REG_OP = X"51" or
zw_REG_OP = X"52")) then
next_state <= FETCH;
elsif ((rdy_i = '1' and
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"29" or zw_REG_OP = X"25" or
zw_REG_OP = X"35" or zw_REG_OP = X"2D" or
zw_REG_OP = X"3D" or zw_REG_OP = X"39" or
zw_REG_OP = X"21" or zw_REG_OP = X"31" or
zw_REG_OP = X"32")) then
next_state <= FETCH;
elsif ((rdy_i = '1' and
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or
zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or
zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or
zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or
zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or
zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or
zw_REG_OP = X"CC" or zw_REG_OP = X"EC" or
zw_REG_OP = X"D2")) then
next_state <= FETCH;
elsif (rdy_i = '1' and
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) then
next_state <= FETCH;
elsif (rdy_i = '1' and
(zw_REG_OP = X"B5" OR
zw_REG_OP = X"B4" OR
zw_REG_OP = X"55" OR zw_REG_OP = X"15" OR
zw_REG_OP = X"35" OR
zw_REG_OP = X"D5")) then
next_state <= s219;
elsif (rdy_i = '1' and
(zw_REG_OP = X"AD" OR
zw_REG_OP = X"AE" OR
zw_REG_OP = X"AC" OR
zw_REG_OP = X"4D" OR
zw_REG_OP = X"0D" OR
zw_REG_OP = X"2D" OR
zw_REG_OP = X"CD" OR
zw_REG_OP = X"EC" OR
zw_REG_OP = X"CC")) then
next_state <= s204;
elsif (rdy_i = '1' and
(zw_REG_OP = X"BD" OR
zw_REG_OP = X"BC" OR
zw_REG_OP = X"5D" OR
zw_REG_OP = X"1D" OR
zw_REG_OP = X"3D" OR
zw_REG_OP = X"DD")) then
next_state <= s212;
elsif (rdy_i = '1' and
(zw_REG_OP = X"B9" OR
zw_REG_OP = X"BE" OR
zw_REG_OP = X"59" OR
zw_REG_OP = X"19" OR
zw_REG_OP = X"39" OR
zw_REG_OP = X"D9")) then
next_state <= s212;
elsif (rdy_i = '1' and
(zw_REG_OP = X"B1" OR
zw_REG_OP = X"51" OR
zw_REG_OP = X"11" OR
zw_REG_OP = X"31" OR
zw_REG_OP = X"D1")) then
next_state <= s216;
elsif (rdy_i = '1' and
(zw_REG_OP = X"A1" OR
zw_REG_OP = X"41" OR
zw_REG_OP = X"01" OR
zw_REG_OP = X"21" OR
zw_REG_OP = X"C1")) then
next_state <= s220;
elsif (rdy_i = '1' and
zw_REG_OP = X"B6") then
next_state <= s219;
elsif (rdy_i = '1' and
(zw_REG_OP = X"32" OR
zw_REG_OP = X"D2" OR
zw_REG_OP = X"52" OR
zw_REG_OP = X"B2" OR
zw_REG_OP = X"12")) then
next_state <= s229;
else
next_state <= s203;
end if;
when s204 =>
if (rdy_i = '1') then
next_state <= s230;
else
next_state <= s204;
end if;
when s212 =>
if (rdy_i = '1') then
next_state <= s231;
else
next_state <= s212;
end if;
when s216 =>
if (rdy_i = '1') then
next_state <= s228;
else
next_state <= s216;
end if;
when s219 =>
if (rdy_i = '1') then
next_state <= s230;
else
next_state <= s219;
end if;
when s220 =>
if (rdy_i = '1') then
next_state <= s227;
else
next_state <= s220;
end if;
when s227 =>
if (rdy_i = '1') then
next_state <= s204;
else
next_state <= s227;
end if;
when s228 =>
if (rdy_i = '1') then
next_state <= s231;
else
next_state <= s228;
end if;
when s230 =>
if ((rdy_i = '1') and (zw_REG_OP = X"09" or zw_REG_OP = X"05" or
zw_REG_OP = X"15" or zw_REG_OP = X"0D" or
zw_REG_OP = X"1D" or zw_REG_OP = X"19" or
zw_REG_OP = X"01" or zw_REG_OP = X"11" or
zw_REG_OP = X"12")) then
next_state <= FETCH;
elsif ((rdy_i = '1') and (zw_REG_OP = X"49" or zw_REG_OP = X"45" or
zw_REG_OP = X"55" or zw_REG_OP = X"4D" or
zw_REG_OP = X"5D" or zw_REG_OP = X"59" or
zw_REG_OP = X"41" or zw_REG_OP = X"51" or
zw_REG_OP = X"52")) then
next_state <= FETCH;
elsif ((rdy_i = '1') and (zw_REG_OP = X"29" or zw_REG_OP = X"25" or
zw_REG_OP = X"35" or zw_REG_OP = X"2D" or
zw_REG_OP = X"3D" or zw_REG_OP = X"39" or
zw_REG_OP = X"21" or zw_REG_OP = X"31" or
zw_REG_OP = X"32")) then
next_state <= FETCH;
elsif ((rdy_i = '1') and (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or
zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or
zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or
zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or
zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or
zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or
zw_REG_OP = X"CC" or zw_REG_OP = X"EC" or
zw_REG_OP = X"D2")) then
next_state <= FETCH;
elsif (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= s230;
end if;
when s231 =>
if ((rdy_i = '1' AND
zw_b2(0) = '0') and (zw_REG_OP = X"09" or zw_REG_OP = X"05" or
zw_REG_OP = X"15" or zw_REG_OP = X"0D" or
zw_REG_OP = X"1D" or zw_REG_OP = X"19" or
zw_REG_OP = X"01" or zw_REG_OP = X"11" or
zw_REG_OP = X"12")) then
next_state <= FETCH;
elsif ((rdy_i = '1' AND
zw_b2(0) = '0') and (zw_REG_OP = X"49" or zw_REG_OP = X"45" or
zw_REG_OP = X"55" or zw_REG_OP = X"4D" or
zw_REG_OP = X"5D" or zw_REG_OP = X"59" or
zw_REG_OP = X"41" or zw_REG_OP = X"51" or
zw_REG_OP = X"52")) then
next_state <= FETCH;
elsif ((rdy_i = '1' AND
zw_b2(0) = '0') and (zw_REG_OP = X"29" or zw_REG_OP = X"25" or
zw_REG_OP = X"35" or zw_REG_OP = X"2D" or
zw_REG_OP = X"3D" or zw_REG_OP = X"39" or
zw_REG_OP = X"21" or zw_REG_OP = X"31" or
zw_REG_OP = X"32")) then
next_state <= FETCH;
elsif ((rdy_i = '1' AND
zw_b2(0) = '0') and (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or
zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or
zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or
zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or
zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or
zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or
zw_REG_OP = X"CC" or zw_REG_OP = X"EC" or
zw_REG_OP = X"D2")) then
next_state <= FETCH;
elsif (rdy_i = '1' AND
zw_b2(0) = '0') then
next_state <= FETCH;
elsif (rdy_i = '1') then
next_state <= s230;
else
next_state <= s231;
end if;
when s229 =>
if (rdy_i = '1') then
next_state <= s204;
else
next_state <= s229;
end if;
when s512 =>
if (rdy_i = '1' and
zw_REG_OP = X"65") then
next_state <= s586;
elsif (rdy_i = '1' and
zw_REG_OP = X"69" and
reg_F(3) = '0') then
next_state <= FETCH;
elsif (rdy_i = '1' and
zw_REG_OP = X"75") then
next_state <= s582;
elsif (rdy_i = '1' and
zw_REG_OP = X"6D") then
next_state <= s554;
elsif (rdy_i = '1' and
zw_REG_OP = X"7D") then
next_state <= s578;
elsif (rdy_i = '1' and
zw_REG_OP = X"79") then
next_state <= s578;
elsif (rdy_i = '1' and
zw_REG_OP = X"71") then
next_state <= s581;
elsif (rdy_i = '1' and
zw_REG_OP = X"61") then
next_state <= s583;
elsif (rdy_i = '1' and
zw_REG_OP = X"69" and
reg_F(3) = '1') then
next_state <= s601;
elsif (rdy_i = '1' and
zw_REG_OP = X"72") then
next_state <= s580;
else
next_state <= s512;
end if;
when s554 =>
if (rdy_i = '1') then
next_state <= s586;
else
next_state <= s554;
end if;
when s578 =>
if (rdy_i = '1') then
next_state <= s585;
else
next_state <= s578;
end if;
when s581 =>
if (rdy_i = '1') then
next_state <= s587;
else
next_state <= s581;
end if;
when s582 =>
if (rdy_i = '1') then
next_state <= s586;
else
next_state <= s582;
end if;
when s583 =>
if (rdy_i = '1') then
next_state <= s584;
else
next_state <= s583;
end if;
when s584 =>
if (rdy_i = '1') then
next_state <= s554;
else
next_state <= s584;
end if;
when s585 =>
if (rdy_i = '1' AND
zw_b2(0) = '0' and
reg_F(3) = '0') then
next_state <= FETCH;
elsif (rdy_i = '1' AND
zw_b2(0) = '0' and
reg_F(3) = '1') then
next_state <= s601;
elsif (rdy_i = '1') then
next_state <= s586;
else
next_state <= s585;
end if;
when s586 =>
if (rdy_i = '1' and
reg_F(3) = '0') then
next_state <= FETCH;
elsif (rdy_i = '1' and
reg_F(3) = '1') then
next_state <= s601;
else
next_state <= s586;
end if;
when s587 =>
if (rdy_i = '1') then
next_state <= s585;
else
next_state <= s587;
end if;
when s580 =>
if (rdy_i = '1') then
next_state <= s554;
else
next_state <= s580;
end if;
when s178 =>
if (rdy_i = '1' and
(zw_REG_OP = X"85" OR
zw_REG_OP = X"86" OR
zw_REG_OP = X"64" OR
zw_REG_OP = X"84")) then
next_state <= s197;
elsif (rdy_i = '1' and
(zw_REG_OP = X"95" OR
zw_REG_OP = X"74" OR
zw_REG_OP = X"94")) then
next_state <= s198;
elsif (rdy_i = '1' and
(zw_REG_OP = X"8D" OR
zw_REG_OP = X"8E" OR
zw_REG_OP = X"9C" OR
zw_REG_OP = X"8C")) then
next_state <= s196;
elsif (rdy_i = '1' and
(zw_REG_OP = X"9D" OR
zw_REG_OP = X"9E")) then
next_state <= s194;
elsif (rdy_i = '1' and
zw_REG_OP = X"99") then
next_state <= s194;
elsif (rdy_i = '1' and
zw_REG_OP = X"91") then
next_state <= s195;
elsif (rdy_i = '1' and
zw_REG_OP = X"81") then
next_state <= s199;
elsif (rdy_i = '1' and
zw_REG_OP = X"96") then
next_state <= s198;
elsif (rdy_i = '1' and
zw_REG_OP = X"92") then
next_state <= s214;
else
next_state <= s178;
end if;
when s194 =>
if (rdy_i = '1') then
next_state <= s208;
else
next_state <= s194;
end if;
when s195 =>
if (rdy_i = '1') then
next_state <= s206;
else
next_state <= s195;
end if;
when s196 =>
if (rdy_i = '1') then
next_state <= s200;
else
next_state <= s196;
end if;
when s197 =>
if (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= s197;
end if;
when s198 =>
if (rdy_i = '1') then
next_state <= s207;
else
next_state <= s198;
end if;
when s199 =>
if (rdy_i = '1') then
next_state <= s205;
else
next_state <= s199;
end if;
when s200 =>
if (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= s200;
end if;
when s205 =>
if (rdy_i = '1') then
next_state <= s209;
else
next_state <= s205;
end if;
when s206 =>
if (rdy_i = '1') then
next_state <= s208;
else
next_state <= s206;
end if;
when s207 =>
if (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= s207;
end if;
when s208 =>
if (rdy_i = '1') then
next_state <= s213;
end if;
when s209 =>
if (rdy_i = '1') then
next_state <= s213;
end if;
when s213 =>
if (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= s213;
end if;
when s214 =>
if (rdy_i = '1') then
next_state <= s196;
else
next_state <= s214;
end if;
when s513 =>
if (rdy_i = '1' and
zw_REG_OP = X"E5") then
next_state <= s596;
elsif (rdy_i = '1' and
zw_REG_OP = X"E9" and
reg_F(3) = '0') then
next_state <= FETCH;
elsif (rdy_i = '1' and
zw_REG_OP = X"F5") then
next_state <= s591;
elsif (rdy_i = '1' and
zw_REG_OP = X"ED") then
next_state <= s588;
elsif (rdy_i = '1' and
zw_REG_OP = X"FD") then
next_state <= s589;
elsif (rdy_i = '1' and
zw_REG_OP = X"F9") then
next_state <= s589;
elsif (rdy_i = '1' and
zw_REG_OP = X"F1") then
next_state <= s590;
elsif (rdy_i = '1' and
zw_REG_OP = X"E1") then
next_state <= s592;
elsif (rdy_i = '1' and
zw_REG_OP = X"E9" and
reg_F(3) = '1') then
next_state <= s602;
elsif (rdy_i = '1' and
zw_REG_OP = X"F2") then
next_state <= s597;
else
next_state <= s513;
end if;
when s588 =>
if (rdy_i = '1') then
next_state <= s596;
else
next_state <= s588;
end if;
when s589 =>
if (rdy_i = '1') then
next_state <= s595;
else
next_state <= s589;
end if;
when s590 =>
if (rdy_i = '1') then
next_state <= s593;
else
next_state <= s590;
end if;
when s591 =>
if (rdy_i = '1') then
next_state <= s596;
else
next_state <= s591;
end if;
when s592 =>
if (rdy_i = '1') then
next_state <= s594;
else
next_state <= s592;
end if;
when s593 =>
if (rdy_i = '1') then
next_state <= s595;
else
next_state <= s593;
end if;
when s594 =>
if (rdy_i = '1') then
next_state <= s588;
else
next_state <= s594;
end if;
when s595 =>
if (rdy_i = '1' AND
zw_b2(0) = '0' and
reg_F(3) = '0') then
next_state <= FETCH;
elsif (rdy_i = '1' AND
zw_b2(0) = '0' and
reg_F(3) = '1') then
next_state <= s602;
elsif (rdy_i = '1') then
next_state <= s596;
else
next_state <= s595;
end if;
when s596 =>
if (rdy_i = '1' and
reg_F(3) = '0') then
next_state <= FETCH;
elsif (rdy_i = '1' and
reg_F(3) = '1') then
next_state <= s602;
else
next_state <= s596;
end if;
when s597 =>
if (rdy_i = '1') then
next_state <= s588;
else
next_state <= s597;
end if;
when s405 =>
if (rdy_i = '1' and
(zw_REG_OP = X"1E" or
zw_REG_OP = X"7E" or
zw_REG_OP = X"3E" or
zw_REG_OP = X"5E")) then
next_state <= s410;
elsif (rdy_i = '1' and
(zw_REG_OP = X"06" or zw_REG_OP = X"66" or
zw_REG_OP = X"26" or zw_REG_OP = X"46" or
zw_REG_OP = X"04" or zw_REG_OP = X"14")) then
next_state <= s415;
elsif (rdy_i = '1' and
(zw_REG_OP = X"16" or
zw_REG_OP = X"76" or
zw_REG_OP = X"36" or
zw_REG_OP = X"56")) then
next_state <= s411;
elsif (rdy_i = '1' and
(zw_REG_OP = X"0E" or
zw_REG_OP = X"6E" or
zw_REG_OP = X"2E" or
zw_REG_OP = X"4E"or
zw_REG_OP = X"0C" or
zw_REG_OP = X"1C")) then
next_state <= s408;
elsif (rdy_i = '1' and
zw_REG_OP (3 downto 0) = X"7") then
next_state <= s415;
else
next_state <= s405;
end if;
when s408 =>
if (rdy_i = '1') then
next_state <= s415;
else
next_state <= s408;
end if;
when s410 =>
if (rdy_i = '1') then
next_state <= s414;
else
next_state <= s410;
end if;
when s411 =>
if (rdy_i = '1') then
next_state <= s415;
else
next_state <= s411;
end if;
when s414 =>
if (rdy_i = '1') then
next_state <= s417;
else
next_state <= s414;
end if;
when s415 =>
if (rdy_i = '1') then
next_state <= s417;
else
next_state <= s415;
end if;
when s417 =>
if ((rdy_i = '1' and
(zw_REG_OP = X"06" or
zw_REG_OP = X"16" or
zw_REG_OP = X"0E" or
zw_REG_OP = X"1E")) and (rdy_i = '1')) then
next_state <= s419;
elsif ((rdy_i = '1' and
(zw_REG_OP = X"46" or
zw_REG_OP = X"56" or
zw_REG_OP = X"4E" or
zw_REG_OP = X"5E")) and (rdy_i = '1')) then
next_state <= s419;
elsif ((rdy_i = '1' and
(zw_REG_OP = X"26" or
zw_REG_OP = X"36" or
zw_REG_OP = X"2E" or
zw_REG_OP = X"3E")) and (rdy_i = '1')) then
next_state <= s419;
elsif ((rdy_i = '1' and
(zw_REG_OP = X"66" or
zw_REG_OP = X"76" or
zw_REG_OP = X"6E" or
zw_REG_OP = X"7E")) and (rdy_i = '1')) then
next_state <= s419;
elsif ((rdy_i = '1' and
zw_REG_OP (7) = '0' and
zw_REG_OP (3 downto 0) = X"7") and (rdy_i = '1')) then
next_state <= s419;
elsif ((rdy_i = '1' and
zw_REG_OP (7) = '1' and
zw_REG_OP (3 downto 0) = X"7") and (rdy_i = '1')) then
next_state <= s419;
elsif ((rdy_i = '1' and
(zw_REG_OP = X"14" or
zw_REG_OP = X"1C")) and (rdy_i = '1')) then
next_state <= s419;
elsif ((rdy_i = '1' and
(zw_REG_OP = X"04" or
zw_REG_OP = X"0C")) and (rdy_i = '1')) then
next_state <= s419;
else
next_state <= s417;
end if;
when s419 =>
if ((zw_REG_OP (3 downto 0) = X"7") and (rdy_i = '1')) then
next_state <= FETCH;
elsif (((zw_REG_OP = X"14" or
zw_REG_OP = X"04" or
zw_REG_OP = X"0C" or
zw_REG_OP = X"1C")) and (rdy_i = '1')) then
next_state <= FETCH;
elsif (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= s419;
end if;
when s420 =>
if (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= s420;
end if;
when s598 =>
if (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= s598;
end if;
when s599 =>
if (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= s599;
end if;
when s600 =>
if (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= s600;
end if;
when s268 =>
if (rdy_i = '1' and (
(reg_F(0) = '1' and zw_REG_OP = X"90") or (reg_F(0) = '0' and zw_REG_OP = X"B0") or
(reg_F(1) = '0' and zw_REG_OP = X"F0") or (reg_F(7) = '0' and zw_REG_OP = X"30") or
(reg_F(1) = '1' and zw_REG_OP = X"D0") or (reg_F(7) = '1' and zw_REG_OP = X"10") or
(reg_F(6) = '1' and zw_REG_OP = X"50") or (reg_F(6) = '0' and zw_REG_OP = X"70"))) then
next_state <= FETCH;
elsif (rdy_i = '1') then
next_state <= s305;
else
next_state <= s268;
end if;
when s305 =>
if (rdy_i = '1' and
zw_b3 = adr_nxt_pc_i (15 downto 8)) then
next_state <= FETCH;
elsif (rdy_i = '1') then
next_state <= s306;
else
next_state <= s305;
end if;
when s306 =>
if (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= s306;
end if;
when jmp1 =>
if (rdy_i = '1' and
zw_REG_OP = X"4C") then
next_state <= jmp_ex;
elsif (rdy_i = '1' and
zw_REG_OP = X"6C") then
next_state <= jmp2_1;
elsif (rdy_i = '1' and
zw_REG_OP = X"7C") then
next_state <= jmp2_2;
else
next_state <= jmp1;
end if;
when jmp2_1 =>
if (rdy_i = '1') then
next_state <= jmp3_1;
else
next_state <= jmp2_1;
end if;
when jmp4_12 =>
if (rdy_i = '1') then
next_state <= jmp_ex;
else
next_state <= jmp4_12;
end if;
when jmp_ex =>
if (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= jmp_ex;
end if;
when jmp2_2 =>
if (rdy_i = '1') then
next_state <= jmp3_2;
else
next_state <= jmp2_2;
end if;
when jmp3_1 =>
if (rdy_i = '1') then
next_state <= jmp4_12;
else
next_state <= jmp3_1;
end if;
when s402 =>
if (rdy_i = '1') then
next_state <= s421;
else
next_state <= s402;
end if;
when s421 =>
if (rdy_i = '1') then
next_state <= s422;
else
next_state <= s421;
end if;
when s422 =>
if (rdy_i = '1') then
next_state <= s423;
else
next_state <= s422;
end if;
when s423 =>
if (rdy_i = '1') then
next_state <= s424;
else
next_state <= s423;
end if;
when s424 =>
if (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= s424;
end if;
when s362 =>
if (rdy_i = '1') then
next_state <= s234;
else
next_state <= s362;
end if;
when s221 =>
if (rdy_i = '1' and
zw_REG_OP = X"34") then
next_state <= s233;
elsif (rdy_i = '1' and
zw_REG_OP = X"3C") then
next_state <= s232;
elsif (rdy_i = '1' and
zw_REG_OP = X"24") then
next_state <= s234;
elsif (rdy_i = '1' and
zw_REG_OP = X"2C") then
next_state <= s362;
elsif (rdy_i = '1' and
zw_REG_OP = X"89") then
next_state <= FETCH;
else
next_state <= s221;
end if;
when s232 =>
if (rdy_i = '1') then
next_state <= s235;
else
next_state <= s232;
end if;
when s233 =>
if (rdy_i = '1') then
next_state <= s234;
else
next_state <= s233;
end if;
when s234 =>
if (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= s234;
end if;
when s235 =>
if (rdy_i = '1' AND
zw_b2(0) = '0') then
next_state <= FETCH;
elsif (rdy_i = '1') then
next_state <= s234;
else
next_state <= s235;
end if;
when brk1 =>
if (rdy_i = '1') then
next_state <= brk2;
else
next_state <= brk1;
end if;
when brk2 =>
if (rdy_i = '1') then
next_state <= brk3;
else
next_state <= brk2;
end if;
when brk3 =>
if (rdy_i = '1') then
next_state <= brk4;
else
next_state <= brk3;
end if;
when brk4 =>
if (rdy_i = '1') then
next_state <= brk5;
else
next_state <= brk4;
end if;
when brk6 =>
if (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= brk6;
end if;
when brk5 =>
if (rdy_i = '1') then
next_state <= brk6;
else
next_state <= brk5;
end if;
when s425 =>
if (rdy_i = '1') then
next_state <= s426;
else
next_state <= s425;
end if;
when s426 =>
if (rdy_i = '1') then
next_state <= s427;
else
next_state <= s426;
end if;
when s427 =>
if (rdy_i = '1') then
next_state <= s428;
else
next_state <= s427;
end if;
when s428 =>
if (rdy_i = '1') then
next_state <= s429;
else
next_state <= s428;
end if;
when s429 =>
if (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= s429;
end if;
when s430 =>
if (rdy_i = '1') then
next_state <= s431;
else
next_state <= s430;
end if;
when s431 =>
if (rdy_i = '1') then
next_state <= s432;
else
next_state <= s431;
end if;
when s432 =>
if (rdy_i = '1') then
next_state <= s433;
else
next_state <= s432;
end if;
when s433 =>
if (rdy_i = '1') then
next_state <= s434;
else
next_state <= s433;
end if;
when s434 =>
if (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= s434;
end if;
when s236 =>
if (rdy_i = '1' and
(zw_REG_OP = X"C6" OR
zw_REG_OP = X"E6")) then
next_state <= s346;
elsif (rdy_i = '1' and
(zw_REG_OP = X"D6" OR
zw_REG_OP = X"F6")) then
next_state <= s248;
elsif (rdy_i = '1' and
(zw_REG_OP = X"CE" OR
zw_REG_OP = X"EE")) then
next_state <= s245;
elsif (rdy_i = '1' and
(zw_REG_OP = X"DE" OR
zw_REG_OP = X"FE")) then
next_state <= s246;
else
next_state <= s236;
end if;
when s245 =>
if (rdy_i = '1') then
next_state <= s346;
else
next_state <= s245;
end if;
when s246 =>
if (rdy_i = '1') then
next_state <= s345;
else
next_state <= s246;
end if;
when s248 =>
if (rdy_i = '1') then
next_state <= s346;
else
next_state <= s248;
end if;
when s345 =>
if (rdy_i = '1') then
next_state <= s346;
else
next_state <= s345;
end if;
when s346 =>
if (rdy_i = '1') then
next_state <= s252;
else
next_state <= s346;
end if;
when s252 =>
if (rdy_i = '1') then
next_state <= s253;
else
next_state <= s252;
end if;
when s253 =>
if (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= s253;
end if;
when s435 =>
if (rdy_i = '1') then
next_state <= s436;
else
next_state <= s435;
end if;
when s436 =>
if (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= s436;
end if;
when s437 =>
if (rdy_i = '1') then
next_state <= s438;
else
next_state <= s437;
end if;
when s438 =>
if (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= s438;
end if;
when s439 =>
if (rdy_i = '1') then
next_state <= s440;
else
next_state <= s439;
end if;
when s440 =>
if (rdy_i = '1') then
next_state <= s441;
else
next_state <= s440;
end if;
when s441 =>
if (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= s441;
end if;
when s442 =>
if (rdy_i = '1') then
next_state <= s443;
else
next_state <= s442;
end if;
when s443 =>
if (rdy_i = '1') then
next_state <= s444;
else
next_state <= s443;
end if;
when s444 =>
if (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= s444;
end if;
when irq1 =>
if (rdy_i = '1') then
next_state <= irq2;
else
next_state <= irq1;
end if;
when irq2 =>
if (rdy_i = '1') then
next_state <= irq3;
else
next_state <= irq2;
end if;
when irq3 =>
if (rdy_i = '1') then
next_state <= irq4;
else
next_state <= irq3;
end if;
when irq5b =>
if (rdy_i = '1') then
next_state <= irq6;
else
next_state <= irq5b;
end if;
when irq5a =>
if (rdy_i = '1') then
next_state <= irq6;
else
next_state <= irq5a;
end if;
when irq4 =>
if (rdy_i = '1' and
nmi_i = '1') then
next_state <= irq5a;
elsif (rdy_i = '1') then
next_state <= irq5b;
else
next_state <= irq4;
end if;
when irq6 =>
if (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= irq6;
end if;
when s11 =>
if (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= s11;
end if;
when s12 =>
if (rdy_i = '1') then
next_state <= s20;
else
next_state <= s12;
end if;
when s20 =>
if (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= s20;
end if;
when s14 =>
if (rdy_i = '1') then
next_state <= s21;
else
next_state <= s14;
end if;
when s21 =>
if (rdy_i = '1') then
next_state <= s23;
else
next_state <= s21;
end if;
when s23 =>
if (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= s23;
end if;
when s15 =>
if (rdy_i = '1') then
next_state <= s25;
else
next_state <= s15;
end if;
when s25 =>
if (rdy_i = '1') then
next_state <= s28;
else
next_state <= s25;
end if;
when s28 =>
if (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= s28;
end if;
when s16 =>
if (rdy_i = '1') then
next_state <= s30;
else
next_state <= s16;
end if;
when s30 =>
if (rdy_i = '1') then
next_state <= s31;
else
next_state <= s30;
end if;
when s31 =>
if (rdy_i = '1') then
next_state <= s32;
else
next_state <= s31;
end if;
when s32 =>
if (rdy_i = '1') then
next_state <= s34;
else
next_state <= s32;
end if;
when s33 =>
if (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= s33;
end if;
when s34 =>
if (rdy_i = '1') then
next_state <= s36;
else
next_state <= s34;
end if;
when s36 =>
if (rdy_i = '1') then
next_state <= s33;
else
next_state <= s36;
end if;
when jmp3_2 =>
if (rdy_i = '1') then
next_state <= jmp4_12;
else
next_state <= jmp3_2;
end if;
when s601 =>
if (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= s601;
end if;
when s602 =>
if (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= s602;
end if;
when s270 =>
if (rdy_i = '1') then
next_state <= s271;
else
next_state <= s270;
end if;
when s307 =>
if (rdy_i = '1' and
zw_b3 = adr_nxt_pc_i (15 downto 8)) then
next_state <= FETCH;
elsif (rdy_i = '1') then
next_state <= s309;
else
next_state <= s307;
end if;
when s308 =>
if (rdy_i = '1' and (
(zw_b1(0) = '0' and zw_REG_OP = X"8F") or
(zw_b1(1) = '0' and zw_REG_OP = X"9F") or
(zw_b1(2) = '0' and zw_REG_OP = X"AF") or
(zw_b1(3) = '0' and zw_REG_OP = X"BF") or
(zw_b1(4) = '0' and zw_REG_OP = X"CF") or
(zw_b1(5) = '0' and zw_REG_OP = X"DF") or
(zw_b1(6) = '0' and zw_REG_OP = X"EF") or
(zw_b1(7) = '0' and zw_REG_OP = X"FF") or
(zw_b1(0) = '1' and zw_REG_OP = X"0F") or
(zw_b1(1) = '1' and zw_REG_OP = X"1F") or
(zw_b1(2) = '1' and zw_REG_OP = X"2F") or
(zw_b1(3) = '1' and zw_REG_OP = X"3F") or
(zw_b1(4) = '1' and zw_REG_OP = X"4F") or
(zw_b1(5) = '1' and zw_REG_OP = X"5F") or
(zw_b1(6) = '1' and zw_REG_OP = X"6F") or
(zw_b1(7) = '1' and zw_REG_OP = X"7F"))) then
next_state <= FETCH;
elsif (rdy_i = '1') then
next_state <= s307;
else
next_state <= s308;
end if;
when s271 =>
if (rdy_i = '1') then
next_state <= s272;
else
next_state <= s271;
end if;
when s272 =>
if (rdy_i = '1') then
next_state <= s308;
else
next_state <= s272;
end if;
when s309 =>
if (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= s309;
end if;
when RES2 =>
next_state <= s544;
when others =>
next_state <= RES;
end case;
end process nextstate_proc;
-----------------------------------------------------------------
output_proc : process (
adr_nxt_pc_i,
adr_pc_i,
adr_sp_i,
current_state,
d_alu_i,
d_alu_prio_i,
d_i,
d_regs_out_i,
irq_n_i,
nmi_i,
q_a_i,
q_x_i,
q_y_i,
rdy_i,
reg_F,
reg_sel_pc_in,
reg_sel_pc_val,
reg_sel_rb_in,
reg_sel_rb_out,
reg_sel_reg,
reg_sel_sp_as,
reg_sel_sp_in,
sig_PC,
zw_ALU,
zw_ALU1,
zw_ALU2,
zw_ALU3,
zw_ALU4,
zw_ALU5,
zw_ALU6,
zw_REG_OP,
zw_b1,
zw_b2,
zw_b3,
zw_b4,
zw_w1,
zw_w3
)
-----------------------------------------------------------------
begin
-- Default Assignment
a_o <= sig_PC;
adr_o <= X"0000";
ch_a_o <= X"00";
ch_b_o <= X"00";
d_regs_in_o <= X"00";
ld_o <= "00";
ld_pc_o <= '0';
ld_sp_o <= '0';
load_regs_o <= '0';
offset_o <= X"0000";
rst_nmi_o <= '0';
sel_pc_in_o <= reg_sel_pc_in;
sel_pc_val_o <= reg_sel_pc_val;
sel_rb_in_o <= reg_sel_rb_in;
sel_rb_out_o <= reg_sel_rb_out;
sel_reg_o <= reg_sel_reg;
sel_sp_as_o <= reg_sel_sp_as;
sel_sp_in_o <= reg_sel_sp_in;
-- Default Assignment To Internals
sig_D_OUT <= X"00";
sig_RD <= '1';
sig_RWn <= '1';
sig_SYNC <= '0';
sig_WR <= '0';
zw_100_a <= '0';
zw_100_alu <= '0';
zw_100_d <= '0';
zw_50_a <= '0';
zw_50_alu <= '0';
zw_50_d <= '0';
zw_ALU <= "00" & X"00";
zw_ALU1 <= "00" & X"00";
zw_ALU2 <= "00" & X"00";
zw_ALU3 <= "00" & X"00";
zw_ALU4 <= "00" & X"00";
zw_ALU5 <= "00" & X"00";
zw_ALU6 <= "00" & X"00";
-- Combined Actions
case current_state is
when s544 =>
ld_sp_o <= '1';
if (rdy_i = '1') then
ld_o <= "11";
end if;
when s545 =>
adr_o <= X"FFFB";
ld_pc_o <= '1';
if (rdy_i = '1') then
ld_o <= "11";
end if;
when s546 =>
ld_pc_o <= '1';
if (rdy_i = '1') then
ld_o <= "11";
end if;
when s549 =>
ld_pc_o <= '1';
if (rdy_i = '1') then
adr_o <= d_i & zw_w1 (7 downto 0);
ld_o <= "11";
sig_SYNC <= '1';
end if;
when s550 =>
ld_sp_o <= '1';
if (rdy_i = '1') then
ld_o <= "11";
end if;
when RES =>
sig_SYNC <= '1';
when FETCH =>
sig_RWn <= '1';
sig_RD <= '1';
sig_SYNC <= NOT (rdy_i);
ld_pc_o <= '1';
if ((d_i = X"00") and (rdy_i = '1')) then
ld_o <= "11";
elsif ((nmi_i = '1') and (rdy_i = '1')) then
ld_o <= "11";
elsif ((irq_n_i = '0' and
reg_F(2) = '0') and (rdy_i = '1')) then
ld_o <= "11";
elsif ((d_i = X"58") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"28") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"78") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"69" or
d_i = X"65" or
d_i = X"75" or
d_i = X"6D" or
d_i = X"7D" or
d_i = X"79" or
d_i = X"61" or
d_i = X"71" or
d_i = X"72") and (rdy_i = '1')) then
ld_o <= "11";
elsif ((d_i = X"06" or
d_i = X"16" or
d_i = X"0E" or
d_i = X"1E" or
d_i (3 downto 0) = X"7" or
d_i = X"14" or
d_i = X"04" or
d_i = X"0C" or
d_i = X"1C") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"90" or
d_i = X"B0" or
d_i = X"F0" or
d_i = X"30" or
d_i = X"D0" or
d_i = X"10" or
d_i = X"50" or
d_i = X"70" or
d_i = X"80") and (rdy_i = '1')) then
ld_o <= "11";
elsif ((d_i = X"24" or
d_i = X"2C" or
d_i = X"3C" or
d_i = X"34" or
d_i = X"89") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"18") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"D8") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"8F" or
d_i = X"9F" or
d_i = X"AF" or
d_i = X"BF" or
d_i = X"CF" or
d_i = X"DF" or
d_i = X"EF" or
d_i = X"FF" or
d_i = X"0F" or
d_i = X"1F" or
d_i = X"2F" or
d_i = X"3F" or
d_i = X"4F" or
d_i = X"5F" or
d_i = X"6F" or
d_i = X"7F") and (rdy_i = '1')) then
ld_o <= "11";
elsif ((d_i = X"B8") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"E0" or
d_i = X"E4" or
d_i = X"EC") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"C0" or
d_i = X"C4" or
d_i = X"CC") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"C6" or
d_i = X"D6" or
d_i = X"CE" or
d_i = X"DE") and (rdy_i = '1')) then
ld_o <= "11";
elsif ((d_i = X"CA") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"88") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"49" or
d_i = X"45" or
d_i = X"55" or
d_i = X"4D" or
d_i = X"5D" or
d_i = X"59" or
d_i = X"41" or
d_i = X"51" or
d_i = X"09" or
d_i = X"05" or
d_i = X"15" or
d_i = X"0D" or
d_i = X"1D" or
d_i = X"19" or
d_i = X"01" or
d_i = X"11" or
d_i = X"29" or
d_i = X"25" or
d_i = X"35" or
d_i = X"2D" or
d_i = X"3D" or
d_i = X"39" or
d_i = X"21" or
d_i = X"31" or
d_i = X"C9" or
d_i = X"C5" or
d_i = X"D5" or
d_i = X"CD" or
d_i = X"DD" or
d_i = X"D9" or
d_i = X"C1" or
d_i = X"D1" or
d_i = X"32" or
d_i = X"D2" or
d_i = X"52" or
d_i = X"12") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"E6" or
d_i = X"F6" or
d_i = X"EE" or
d_i = X"FE") and (rdy_i = '1')) then
ld_o <= "11";
elsif ((d_i = X"E8") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"C8") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"4C" or
d_i = X"6C" or
d_i = X"7C") and (rdy_i = '1')) then
ld_o <= "11";
elsif ((d_i = X"20") and (rdy_i = '1')) then
ld_o <= "11";
elsif ((d_i = X"A9" or
d_i = X"A5" or
d_i = X"B5" or
d_i = X"AD" or
d_i = X"BD" or
d_i = X"B9" or
d_i = X"A1" or
d_i = X"B1" or
d_i = X"B2") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"A2" or
d_i = X"A6" or
d_i = X"B6" or
d_i = X"AE" or
d_i = X"BE") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"A0" or
d_i = X"A4" or
d_i = X"B4" or
d_i = X"AC" or
d_i = X"BC") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"46" or
d_i = X"56" or
d_i = X"4E" or
d_i = X"5E") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"EA") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"48") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"08") and (rdy_i = '1')) then
ld_o <= "11";
elsif ((d_i = X"7A") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"26" or
d_i = X"36" or
d_i = X"2E" or
d_i = X"3E") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"66" or
d_i = X"76" or
d_i = X"6E" or
d_i = X"7E") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"40") and (rdy_i = '1')) then
ld_o <= "11";
elsif ((d_i = X"60") and (rdy_i = '1')) then
ld_o <= "11";
elsif ((d_i = X"E9" or
d_i = X"E5" or
d_i = X"F5" or
d_i = X"ED" or
d_i = X"FD" or
d_i = X"F9" or
d_i = X"E1" or
d_i = X"F1" or
d_i = X"F2") and (rdy_i = '1')) then
ld_o <= "11";
elsif ((d_i = X"38") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"F8") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"85" or
d_i = X"95" or
d_i = X"8D" or
d_i = X"9D" or
d_i = X"99" or
d_i = X"81" or
d_i = X"91" or
d_i = X"92") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"86" or
d_i = X"96" or
d_i = X"8E") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"84" or
d_i = X"94" or
d_i = X"8C") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"AA") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"0A") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"4A") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"2A") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"6A") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"A8") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"98") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"BA") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"8A") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"9A") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"DA") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"5A") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"68") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"FA") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"9C" or
d_i = X"9E" or
d_i = X"64" or
d_i = X"74") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"3A") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"1A") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"EA") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"02" or
d_i = X"22" or
d_i = X"42" or
d_i = X"62" or
d_i = X"82" or
d_i = X"C2" or
d_i = X"E2") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"44") and (rdy_i = '1')) then
ld_o <= "11";
elsif ((d_i = X"54" or
d_i = X"D4" or
d_i = X"F4") and (rdy_i = '1')) then
ld_o <= "11";
elsif ((d_i = X"DC" or
d_i = X"FC") and (rdy_i = '1')) then
ld_o <= "11";
elsif ((d_i = X"5C") and (rdy_i = '1')) then
ld_o <= "11";
elsif ((d_i(3 downto 0) = X"3" or
d_i(3 downto 0) = X"B") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
sig_SYNC <= '1';
end if;
when s6 =>
if (rdy_i = '1') then
sig_SYNC <= '1';
end if;
when s7 =>
if (rdy_i = '1') then
sig_SYNC <= '1';
end if;
when s8 =>
if (rdy_i = '1') then
sig_SYNC <= '1';
end if;
when s9 =>
if (rdy_i = '1') then
sig_SYNC <= '1';
end if;
when s10 =>
if (rdy_i = '1' and
zw_REG_OP = X"9A") then
adr_o <= X"01" & d_regs_out_i;
ld_o <= "11";
ld_sp_o <= '1';
sig_SYNC <= '1';
elsif (rdy_i = '1' and
zw_REG_OP = X"BA") then
d_regs_in_o <= adr_sp_i (7 downto 0);
ch_a_o <= adr_sp_i (7 downto 0);
ch_b_o <= X"00";
load_regs_o <= '1';
sig_SYNC <= '1';
elsif (rdy_i = '1') then
ch_a_o <= d_regs_out_i;
ch_b_o <= X"00";
load_regs_o <= '1';
sig_SYNC <= '1';
end if;
when s13 =>
if (rdy_i = '1') then
sig_SYNC <= '1';
end if;
when s18 =>
if (rdy_i = '1') then
sig_SYNC <= '1';
end if;
when s19 =>
if (rdy_i = '1') then
sig_SYNC <= '1';
end if;
when s26 =>
if (rdy_i = '1') then
sig_SYNC <= '1';
end if;
when s27 =>
if (rdy_i = '1') then
d_regs_in_o <= d_alu_i;
ch_a_o <= d_regs_out_i;
ch_b_o <= zw_b4;
load_regs_o <= '1';
sig_SYNC <= '1';
end if;
when s203 =>
if (rdy_i = '1' and
(zw_REG_OP = X"A5" OR zw_REG_OP = X"A6" OR
zw_REG_OP = X"A4" OR zw_REG_OP = X"45" OR
zw_REG_OP = X"05" OR zw_REG_OP = X"25" OR
zw_REG_OP = X"C5" OR zw_REG_OP = X"E4" OR zw_REG_OP = X"C4")) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((rdy_i = '1' and
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"09" or zw_REG_OP = X"05" or
zw_REG_OP = X"15" or zw_REG_OP = X"0D" or
zw_REG_OP = X"1D" or zw_REG_OP = X"19" or
zw_REG_OP = X"01" or zw_REG_OP = X"11" or
zw_REG_OP = X"12")) then
ld_o <= "11";
ld_pc_o <= '1';
d_regs_in_o <= d_i OR q_a_i;
load_regs_o <= '1';
ch_a_o <= d_i OR q_a_i;
ch_b_o <= X"00";
sig_SYNC <= '1';
elsif ((rdy_i = '1' and
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"49" or zw_REG_OP = X"45" or
zw_REG_OP = X"55" or zw_REG_OP = X"4D" or
zw_REG_OP = X"5D" or zw_REG_OP = X"59" or
zw_REG_OP = X"41" or zw_REG_OP = X"51" or
zw_REG_OP = X"52")) then
ld_o <= "11";
ld_pc_o <= '1';
d_regs_in_o <= d_i XOR q_a_i;
load_regs_o <= '1';
ch_a_o <= d_i XOR q_a_i;
ch_b_o <= X"00";
sig_SYNC <= '1';
elsif ((rdy_i = '1' and
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"29" or zw_REG_OP = X"25" or
zw_REG_OP = X"35" or zw_REG_OP = X"2D" or
zw_REG_OP = X"3D" or zw_REG_OP = X"39" or
zw_REG_OP = X"21" or zw_REG_OP = X"31" or
zw_REG_OP = X"32")) then
ld_o <= "11";
ld_pc_o <= '1';
d_regs_in_o <= d_i AND q_a_i;
load_regs_o <= '1';
ch_a_o <= d_i AND q_a_i;
ch_b_o <= X"00";
sig_SYNC <= '1';
elsif ((rdy_i = '1' and
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or
zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or
zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or
zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or
zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or
zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or
zw_REG_OP = X"CC" or zw_REG_OP = X"EC" or
zw_REG_OP = X"D2")) then
ld_o <= "11";
ld_pc_o <= '1';
zw_ALU (8 downto 0) <= unsigned ('0' & d_regs_out_i) + unsigned ('0' & NOT (d_i)) + 1;
sig_SYNC <= '1';
elsif (rdy_i = '1' and
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) then
ld_o <= "11";
ld_pc_o <= '1';
d_regs_in_o <= d_i;
load_regs_o <= '1';
ch_a_o <= d_i;
ch_b_o <= X"00";
sig_SYNC <= '1';
elsif (rdy_i = '1' and
(zw_REG_OP = X"B5" OR
zw_REG_OP = X"B4" OR
zw_REG_OP = X"55" OR zw_REG_OP = X"15" OR
zw_REG_OP = X"35" OR
zw_REG_OP = X"D5")) then
ch_a_o <= d_i;
ch_b_o <= q_x_i;
elsif (rdy_i = '1' and
(zw_REG_OP = X"AD" OR
zw_REG_OP = X"AE" OR
zw_REG_OP = X"AC" OR
zw_REG_OP = X"4D" OR
zw_REG_OP = X"0D" OR
zw_REG_OP = X"2D" OR
zw_REG_OP = X"CD" OR
zw_REG_OP = X"EC" OR
zw_REG_OP = X"CC")) then
ld_o <= "11";
ld_pc_o <= '1';
elsif (rdy_i = '1' and
(zw_REG_OP = X"BD" OR
zw_REG_OP = X"BC" OR
zw_REG_OP = X"5D" OR
zw_REG_OP = X"1D" OR
zw_REG_OP = X"3D" OR
zw_REG_OP = X"DD")) then
ld_o <= "11";
ld_pc_o <= '1';
ch_a_o <= d_i;
ch_b_o <= q_x_i;
elsif (rdy_i = '1' and
(zw_REG_OP = X"B9" OR
zw_REG_OP = X"BE" OR
zw_REG_OP = X"59" OR
zw_REG_OP = X"19" OR
zw_REG_OP = X"39" OR
zw_REG_OP = X"D9")) then
ld_o <= "11";
ld_pc_o <= '1';
ch_a_o <= d_i;
ch_b_o <= q_y_i;
elsif (rdy_i = '1' and
(zw_REG_OP = X"B1" OR
zw_REG_OP = X"51" OR
zw_REG_OP = X"11" OR
zw_REG_OP = X"31" OR
zw_REG_OP = X"D1")) then
ch_a_o <= d_i;
ch_b_o <= X"01";
elsif (rdy_i = '1' and
(zw_REG_OP = X"A1" OR
zw_REG_OP = X"41" OR
zw_REG_OP = X"01" OR
zw_REG_OP = X"21" OR
zw_REG_OP = X"C1")) then
ch_a_o <= d_i;
ch_b_o <= q_x_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"B6") then
ch_a_o <= d_i;
ch_b_o <= q_y_i;
elsif (rdy_i = '1' and
(zw_REG_OP = X"32" OR
zw_REG_OP = X"D2" OR
zw_REG_OP = X"52" OR
zw_REG_OP = X"B2" OR
zw_REG_OP = X"12")) then
ch_a_o <= d_i;
ch_b_o <= X"01";
end if;
when s204 =>
if (rdy_i = '1') then
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s212 =>
if (rdy_i = '1') then
ch_a_o <= d_i;
ch_b_o <= "0000000" & zw_b2(0);
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s216 =>
if (rdy_i = '1') then
ch_a_o <= d_i;
ch_b_o <= q_y_i;
end if;
when s219 =>
if (rdy_i = '1') then
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s227 =>
if (rdy_i = '1') then
ch_a_o <= zw_b1;
ch_b_o <= X"01";
end if;
when s228 =>
if (rdy_i = '1') then
ch_a_o <= d_i;
ch_b_o <= "0000000" & zw_b2(0);
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s230 =>
if ((rdy_i = '1') and (zw_REG_OP = X"09" or zw_REG_OP = X"05" or
zw_REG_OP = X"15" or zw_REG_OP = X"0D" or
zw_REG_OP = X"1D" or zw_REG_OP = X"19" or
zw_REG_OP = X"01" or zw_REG_OP = X"11" or
zw_REG_OP = X"12")) then
d_regs_in_o <= d_i OR q_a_i;
load_regs_o <= '1';
ch_a_o <= d_i OR q_a_i;
ch_b_o <= X"00";
sig_SYNC <= '1';
elsif ((rdy_i = '1') and (zw_REG_OP = X"49" or zw_REG_OP = X"45" or
zw_REG_OP = X"55" or zw_REG_OP = X"4D" or
zw_REG_OP = X"5D" or zw_REG_OP = X"59" or
zw_REG_OP = X"41" or zw_REG_OP = X"51" or
zw_REG_OP = X"52")) then
d_regs_in_o <= d_i XOR q_a_i;
load_regs_o <= '1';
ch_a_o <= d_i XOR q_a_i;
ch_b_o <= X"00";
sig_SYNC <= '1';
elsif ((rdy_i = '1') and (zw_REG_OP = X"29" or zw_REG_OP = X"25" or
zw_REG_OP = X"35" or zw_REG_OP = X"2D" or
zw_REG_OP = X"3D" or zw_REG_OP = X"39" or
zw_REG_OP = X"21" or zw_REG_OP = X"31" or
zw_REG_OP = X"32")) then
d_regs_in_o <= d_i AND q_a_i;
load_regs_o <= '1';
ch_a_o <= d_i AND q_a_i;
ch_b_o <= X"00";
sig_SYNC <= '1';
elsif ((rdy_i = '1') and (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or
zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or
zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or
zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or
zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or
zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or
zw_REG_OP = X"CC" or zw_REG_OP = X"EC" or
zw_REG_OP = X"D2")) then
zw_ALU (8 downto 0) <= unsigned ('0' & d_regs_out_i) + unsigned ('0' & NOT (d_i)) + 1;
sig_SYNC <= '1';
elsif (rdy_i = '1') then
d_regs_in_o <= d_i;
load_regs_o <= '1';
ch_a_o <= d_i;
ch_b_o <= X"00";
sig_SYNC <= '1';
end if;
when s231 =>
if ((rdy_i = '1' AND
zw_b2(0) = '0') and (zw_REG_OP = X"09" or zw_REG_OP = X"05" or
zw_REG_OP = X"15" or zw_REG_OP = X"0D" or
zw_REG_OP = X"1D" or zw_REG_OP = X"19" or
zw_REG_OP = X"01" or zw_REG_OP = X"11" or
zw_REG_OP = X"12")) then
d_regs_in_o <= d_i OR q_a_i;
load_regs_o <= '1';
ch_a_o <= d_i OR q_a_i;
ch_b_o <= X"00";
sig_SYNC <= '1';
elsif ((rdy_i = '1' AND
zw_b2(0) = '0') and (zw_REG_OP = X"49" or zw_REG_OP = X"45" or
zw_REG_OP = X"55" or zw_REG_OP = X"4D" or
zw_REG_OP = X"5D" or zw_REG_OP = X"59" or
zw_REG_OP = X"41" or zw_REG_OP = X"51" or
zw_REG_OP = X"52")) then
d_regs_in_o <= d_i XOR q_a_i;
load_regs_o <= '1';
ch_a_o <= d_i XOR q_a_i;
ch_b_o <= X"00";
sig_SYNC <= '1';
elsif ((rdy_i = '1' AND
zw_b2(0) = '0') and (zw_REG_OP = X"29" or zw_REG_OP = X"25" or
zw_REG_OP = X"35" or zw_REG_OP = X"2D" or
zw_REG_OP = X"3D" or zw_REG_OP = X"39" or
zw_REG_OP = X"21" or zw_REG_OP = X"31" or
zw_REG_OP = X"32")) then
d_regs_in_o <= d_i AND q_a_i;
load_regs_o <= '1';
ch_a_o <= d_i AND q_a_i;
ch_b_o <= X"00";
sig_SYNC <= '1';
elsif ((rdy_i = '1' AND
zw_b2(0) = '0') and (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or
zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or
zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or
zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or
zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or
zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or
zw_REG_OP = X"CC" or zw_REG_OP = X"EC" or
zw_REG_OP = X"D2")) then
zw_ALU (8 downto 0) <= unsigned ('0' & d_regs_out_i) + unsigned ('0' & NOT (d_i)) + 1;
sig_SYNC <= '1';
elsif (rdy_i = '1' AND
zw_b2(0) = '0') then
d_regs_in_o <= d_i;
load_regs_o <= '1';
ch_a_o <= d_i;
ch_b_o <= X"00";
sig_SYNC <= '1';
end if;
when s512 =>
ld_pc_o <= '1';
if (rdy_i = '1' and
zw_REG_OP = X"65") then
ld_o <= "11";
elsif (rdy_i = '1' and
zw_REG_OP = X"69" and
reg_F(3) = '0') then
ld_o <= "11";
d_regs_in_o <= zw_ALU(7 downto 0);
load_regs_o <= '1';
zw_ALU(8 downto 0) <= unsigned ('0' & q_a_i) + unsigned ('0' & d_i) + reg_F(0);
sig_SYNC <= '1';
elsif (rdy_i = '1' and
zw_REG_OP = X"75") then
ch_a_o <= d_i;
ch_b_o <= q_x_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"6D") then
ld_o <= "11";
elsif (rdy_i = '1' and
zw_REG_OP = X"7D") then
ld_o <= "11";
ch_a_o <= d_i;
ch_b_o <= q_x_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"79") then
ld_o <= "11";
ch_a_o <= d_i;
ch_b_o <= q_y_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"71") then
ch_a_o <= d_i;
ch_b_o <= X"01";
elsif (rdy_i = '1' and
zw_REG_OP = X"61") then
ch_a_o <= d_i;
ch_b_o <= q_x_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"69" and
reg_F(3) = '1') then
ld_o <= "11";
d_regs_in_o <= zw_ALU(7 downto 0);
load_regs_o <= '1';
zw_ALU(7 downto 4) <= unsigned (zw_ALU5(3 downto 0)) + unsigned (zw_ALU4(8 downto 5));
zw_ALU(3 downto 0) <= unsigned (zw_ALU1(3 downto 0)) + unsigned (zw_ALU3(8 downto 5));
zw_ALU4(8 downto 5) <= '0' & ((zw_ALU4(4))) & ((zw_ALU4(4))) & '0';
zw_ALU4(4) <= zw_ALU5(4) OR
(zw_ALU5(3) AND zw_ALU5(2)) OR
(zw_ALU5(3) AND zw_ALU5(1));
zw_ALU5(4 downto 0) <= unsigned ('0' & q_a_i(7 downto 4)) + unsigned ('0' & d_i(7 downto 4)) + (zw_ALU3(4));
zw_ALU3(8 downto 5) <= '0' & ((zw_ALU3(4))) & ((zw_ALU3(4))) & '0';
zw_ALU3(4) <= zw_ALU1(4) OR
(zw_ALU1(3) AND zw_ALU1(2)) OR
(zw_ALU1(3) AND zw_ALU1(1));
zw_ALU1(4 downto 0) <= unsigned ('0' & q_a_i(3 downto 0)) + unsigned ('0' & d_i(3 downto 0)) + reg_F(0);
elsif (rdy_i = '1' and
zw_REG_OP = X"72") then
ch_a_o <= d_i;
ch_b_o <= X"01";
end if;
when s554 =>
ld_pc_o <= '1';
if (rdy_i = '1') then
ld_o <= "11";
end if;
when s578 =>
ld_pc_o <= '1';
if (rdy_i = '1') then
ch_a_o <= d_i;
ch_b_o <= X"01";
ld_o <= "11";
end if;
when s581 =>
if (rdy_i = '1') then
ch_a_o <= d_i;
ch_b_o <= q_y_i;
end if;
when s582 =>
ld_pc_o <= '1';
if (rdy_i = '1') then
ld_o <= "11";
end if;
when s584 =>
if (rdy_i = '1') then
ch_a_o <= zw_b1;
ch_b_o <= X"01";
end if;
when s585 =>
if (rdy_i = '1' AND
zw_b2(0) = '0' and
reg_F(3) = '0') then
d_regs_in_o <= zw_ALU(7 downto 0);
load_regs_o <= '1';
zw_ALU(8 downto 0) <= unsigned ('0' & q_a_i) + unsigned ('0' & d_i) + reg_F(0);
sig_SYNC <= '1';
elsif (rdy_i = '1' AND
zw_b2(0) = '0' and
reg_F(3) = '1') then
d_regs_in_o <= zw_ALU(7 downto 0);
load_regs_o <= '1';
zw_ALU(7 downto 4) <= unsigned (zw_ALU5(3 downto 0)) + unsigned (zw_ALU4(8 downto 5));
zw_ALU(3 downto 0) <= unsigned (zw_ALU1(3 downto 0)) + unsigned (zw_ALU3(8 downto 5));
zw_ALU4(8 downto 5) <= '0' & ((zw_ALU4(4))) & ((zw_ALU4(4))) & '0';
zw_ALU4(4) <= zw_ALU5(4) OR
(zw_ALU5(3) AND zw_ALU5(2)) OR
(zw_ALU5(3) AND zw_ALU5(1));
zw_ALU5(4 downto 0) <= unsigned ('0' & q_a_i(7 downto 4)) + unsigned ('0' & d_i(7 downto 4)) + (zw_ALU3(4));
zw_ALU3(8 downto 5) <= '0' & ((zw_ALU3(4))) & ((zw_ALU3(4))) & '0';
zw_ALU3(4) <= zw_ALU1(4) OR
(zw_ALU1(3) AND zw_ALU1(2)) OR
(zw_ALU1(3) AND zw_ALU1(1));
zw_ALU1(4 downto 0) <= unsigned ('0' & q_a_i(3 downto 0)) + unsigned ('0' & d_i(3 downto 0)) + reg_F(0);
end if;
when s586 =>
if (rdy_i = '1' and
reg_F(3) = '0') then
d_regs_in_o <= zw_ALU(7 downto 0);
load_regs_o <= '1';
zw_ALU(8 downto 0) <= unsigned ('0' & q_a_i) + unsigned ('0' & d_i) + reg_F(0);
sig_SYNC <= '1';
elsif (rdy_i = '1' and
reg_F(3) = '1') then
d_regs_in_o <= zw_ALU(7 downto 0);
load_regs_o <= '1';
zw_ALU(7 downto 4) <= unsigned (zw_ALU5(3 downto 0)) + unsigned (zw_ALU4(8 downto 5));
zw_ALU(3 downto 0) <= unsigned (zw_ALU1(3 downto 0)) + unsigned (zw_ALU3(8 downto 5));
zw_ALU4(8 downto 5) <= '0' & ((zw_ALU4(4))) & ((zw_ALU4(4))) & '0';
zw_ALU4(4) <= zw_ALU5(4) OR
(zw_ALU5(3) AND zw_ALU5(2)) OR
(zw_ALU5(3) AND zw_ALU5(1));
zw_ALU5(4 downto 0) <= unsigned ('0' & q_a_i(7 downto 4)) + unsigned ('0' & d_i(7 downto 4)) + (zw_ALU3(4));
zw_ALU3(8 downto 5) <= '0' & ((zw_ALU3(4))) & ((zw_ALU3(4))) & '0';
zw_ALU3(4) <= zw_ALU1(4) OR
(zw_ALU1(3) AND zw_ALU1(2)) OR
(zw_ALU1(3) AND zw_ALU1(1));
zw_ALU1(4 downto 0) <= unsigned ('0' & q_a_i(3 downto 0)) + unsigned ('0' & d_i(3 downto 0)) + reg_F(0);
end if;
when s587 =>
ld_pc_o <= '1';
if (rdy_i = '1') then
ch_a_o <= d_i;
ch_b_o <= X"01";
ld_o <= "11";
end if;
when s178 =>
if (rdy_i = '1' and
(zw_REG_OP = X"85" OR
zw_REG_OP = X"86" OR
zw_REG_OP = X"64" OR
zw_REG_OP = X"84")) then
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
sig_D_OUT <= d_regs_out_i;
ld_o <= "11";
ld_pc_o <= '1';
elsif (rdy_i = '1' and
(zw_REG_OP = X"95" OR
zw_REG_OP = X"74" OR
zw_REG_OP = X"94")) then
ch_a_o <= d_i;
ch_b_o <= q_x_i;
elsif (rdy_i = '1' and
(zw_REG_OP = X"8D" OR
zw_REG_OP = X"8E" OR
zw_REG_OP = X"9C" OR
zw_REG_OP = X"8C")) then
ld_o <= "11";
ld_pc_o <= '1';
elsif (rdy_i = '1' and
(zw_REG_OP = X"9D" OR
zw_REG_OP = X"9E")) then
ld_o <= "11";
ld_pc_o <= '1';
ch_a_o <= d_i;
ch_b_o <= q_x_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"99") then
ld_o <= "11";
ld_pc_o <= '1';
ch_a_o <= d_i;
ch_b_o <= q_y_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"91") then
ch_a_o <= d_i;
ch_b_o <= X"01";
elsif (rdy_i = '1' and
zw_REG_OP = X"81") then
ch_a_o <= d_i;
ch_b_o <= q_x_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"96") then
ch_a_o <= d_i;
ch_b_o <= q_y_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"92") then
ch_a_o <= d_i;
ch_b_o <= X"01";
end if;
when s194 =>
if (rdy_i = '1') then
ch_a_o <= d_i;
ch_b_o <= "0000000" & zw_b2(0);
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s195 =>
if (rdy_i = '1') then
ch_a_o <= d_i;
ch_b_o <= q_y_i;
end if;
when s196 =>
if (rdy_i = '1') then
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
sig_D_OUT <= d_regs_out_i;
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s197 =>
if (rdy_i = '1') then
sig_SYNC <= '1';
end if;
when s198 =>
if (rdy_i = '1') then
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
sig_D_OUT <= d_regs_out_i;
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s200 =>
if (rdy_i = '1') then
sig_SYNC <= '1';
end if;
when s205 =>
if (rdy_i = '1') then
ch_a_o <= zw_b1;
ch_b_o <= X"01";
end if;
when s206 =>
if (rdy_i = '1') then
ch_a_o <= d_i;
ch_b_o <= "0000000" & zw_b2(0);
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s207 =>
if (rdy_i = '1') then
sig_SYNC <= '1';
end if;
when s208 =>
if (rdy_i = '1') then
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
sig_D_OUT <= d_regs_out_i;
end if;
when s209 =>
if (rdy_i = '1') then
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
sig_D_OUT <= d_regs_out_i;
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s213 =>
if (rdy_i = '1') then
sig_SYNC <= '1';
end if;
when s513 =>
ld_pc_o <= '1';
if (rdy_i = '1' and
zw_REG_OP = X"E5") then
ld_o <= "11";
elsif (rdy_i = '1' and
zw_REG_OP = X"E9" and
reg_F(3) = '0') then
ld_o <= "11";
d_regs_in_o <= zw_ALU(7 downto 0);
load_regs_o <= '1';
zw_ALU(8 downto 0) <= unsigned ('0' & q_a_i) + unsigned ('0' & NOT (d_i)) + reg_F(0);
sig_SYNC <= '1';
elsif (rdy_i = '1' and
zw_REG_OP = X"F5") then
ch_a_o <= d_i;
ch_b_o <= q_x_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"ED") then
ld_o <= "11";
elsif (rdy_i = '1' and
zw_REG_OP = X"FD") then
ld_o <= "11";
ch_a_o <= d_i;
ch_b_o <= q_x_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"F9") then
ld_o <= "11";
ch_a_o <= d_i;
ch_b_o <= q_y_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"F1") then
ch_a_o <= d_i;
ch_b_o <= X"01";
elsif (rdy_i = '1' and
zw_REG_OP = X"E1") then
ch_a_o <= d_i;
ch_b_o <= q_x_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"E9" and
reg_F(3) = '1') then
ld_o <= "11";
d_regs_in_o <= zw_ALU(7 downto 0);
load_regs_o <= '1';
zw_ALU(7 downto 0) <= unsigned (( zw_ALU2(3 downto 0)) & ( zw_ALU1(3 downto 0))) -
unsigned (zw_ALU6(7 downto 0));
zw_ALU6(7 downto 0) <= '0' &
(NOT zw_ALU2(4)) &
(NOT zw_ALU2(4)) &
'0' &
'0' &
(NOT zw_ALU1(4)) &
(NOT zw_ALU1(4)) &
'0';
zw_ALU2(5 downto 0) <= unsigned ("00" & q_a_i(7 downto 4)) + unsigned ("00" & NOT (d_i(7 downto 4))) +
(zw_ALU1(4));
zw_ALU1(5 downto 0) <= unsigned ("00" & q_a_i(3 downto 0)) + unsigned ("00" & NOT (d_i(3 downto 0))) +
reg_F(0);
elsif (rdy_i = '1' and
zw_REG_OP = X"F2") then
ch_a_o <= d_i;
ch_b_o <= X"01";
end if;
when s588 =>
ld_pc_o <= '1';
if (rdy_i = '1') then
ld_o <= "11";
end if;
when s589 =>
ld_pc_o <= '1';
if (rdy_i = '1') then
ch_a_o <= d_i;
ch_b_o <= X"01";
ld_o <= "11";
end if;
when s590 =>
if (rdy_i = '1') then
ch_a_o <= d_i;
ch_b_o <= q_y_i;
end if;
when s591 =>
ld_pc_o <= '1';
if (rdy_i = '1') then
ld_o <= "11";
end if;
when s593 =>
ld_pc_o <= '1';
if (rdy_i = '1') then
ch_a_o <= d_i;
ch_b_o <= X"01";
ld_o <= "11";
end if;
when s594 =>
if (rdy_i = '1') then
ch_a_o <= zw_b1;
ch_b_o <= X"01";
end if;
when s595 =>
if (rdy_i = '1' AND
zw_b2(0) = '0' and
reg_F(3) = '0') then
d_regs_in_o <= zw_ALU(7 downto 0);
load_regs_o <= '1';
zw_ALU(8 downto 0) <= unsigned ('0' & q_a_i) + unsigned ('0' & NOT (d_i)) + reg_F(0);
sig_SYNC <= '1';
elsif (rdy_i = '1' AND
zw_b2(0) = '0' and
reg_F(3) = '1') then
d_regs_in_o <= zw_ALU(7 downto 0);
load_regs_o <= '1';
zw_ALU(7 downto 0) <= unsigned (( zw_ALU2(3 downto 0)) & ( zw_ALU1(3 downto 0))) -
unsigned (zw_ALU6(7 downto 0));
zw_ALU6(7 downto 0) <= '0' &
(NOT zw_ALU2(4)) &
(NOT zw_ALU2(4)) &
'0' &
'0' &
(NOT zw_ALU1(4)) &
(NOT zw_ALU1(4)) &
'0';
zw_ALU2(5 downto 0) <= unsigned ("00" & q_a_i(7 downto 4)) + unsigned ("00" & NOT (d_i(7 downto 4))) +
(zw_ALU1(4));
zw_ALU1(5 downto 0) <= unsigned ("00" & q_a_i(3 downto 0)) + unsigned ("00" & NOT (d_i(3 downto 0))) +
reg_F(0);
end if;
when s596 =>
if (rdy_i = '1' and
reg_F(3) = '0') then
d_regs_in_o <= zw_ALU(7 downto 0);
load_regs_o <= '1';
zw_ALU(8 downto 0) <= unsigned ('0' & q_a_i) + unsigned ('0' & NOT (d_i)) + reg_F(0);
sig_SYNC <= '1';
elsif (rdy_i = '1' and
reg_F(3) = '1') then
d_regs_in_o <= zw_ALU(7 downto 0);
load_regs_o <= '1';
zw_ALU(7 downto 0) <= unsigned (( zw_ALU2(3 downto 0)) & ( zw_ALU1(3 downto 0))) -
unsigned (zw_ALU6(7 downto 0));
zw_ALU6(7 downto 0) <= '0' &
(NOT zw_ALU2(4)) &
(NOT zw_ALU2(4)) &
'0' &
'0' &
(NOT zw_ALU1(4)) &
(NOT zw_ALU1(4)) &
'0';
zw_ALU2(5 downto 0) <= unsigned ("00" & q_a_i(7 downto 4)) + unsigned ("00" & NOT (d_i(7 downto 4))) +
(zw_ALU1(4));
zw_ALU1(5 downto 0) <= unsigned ("00" & q_a_i(3 downto 0)) + unsigned ("00" & NOT (d_i(3 downto 0))) +
reg_F(0);
end if;
when s405 =>
if (rdy_i = '1' and
(zw_REG_OP = X"1E" or
zw_REG_OP = X"7E" or
zw_REG_OP = X"3E" or
zw_REG_OP = X"5E")) then
ld_o <= "11";
ld_pc_o <= '1';
ch_a_o <= d_i;
ch_b_o <= q_x_i;
elsif (rdy_i = '1' and
(zw_REG_OP = X"06" or zw_REG_OP = X"66" or
zw_REG_OP = X"26" or zw_REG_OP = X"46" or
zw_REG_OP = X"04" or zw_REG_OP = X"14")) then
ld_o <= "11";
ld_pc_o <= '1';
elsif (rdy_i = '1' and
(zw_REG_OP = X"16" or
zw_REG_OP = X"76" or
zw_REG_OP = X"36" or
zw_REG_OP = X"56")) then
ch_a_o <= d_i;
ch_b_o <= q_x_i;
elsif (rdy_i = '1' and
(zw_REG_OP = X"0E" or
zw_REG_OP = X"6E" or
zw_REG_OP = X"2E" or
zw_REG_OP = X"4E"or
zw_REG_OP = X"0C" or
zw_REG_OP = X"1C")) then
ld_o <= "11";
ld_pc_o <= '1';
elsif (rdy_i = '1' and
zw_REG_OP (3 downto 0) = X"7") then
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s408 =>
if (rdy_i = '1') then
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s410 =>
if (rdy_i = '1') then
ch_a_o <= d_i;
ch_b_o <= "0000000" & zw_b2(0);
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s411 =>
if (rdy_i = '1') then
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s417 =>
if ((rdy_i = '1' and
(zw_REG_OP = X"06" or
zw_REG_OP = X"16" or
zw_REG_OP = X"0E" or
zw_REG_OP = X"1E")) and (rdy_i = '1')) then
sig_D_OUT <= d_i(6 downto 0) & '0';
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
elsif ((rdy_i = '1' and
(zw_REG_OP = X"46" or
zw_REG_OP = X"56" or
zw_REG_OP = X"4E" or
zw_REG_OP = X"5E")) and (rdy_i = '1')) then
sig_D_OUT <= '0' & d_i(7 downto 1);
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
elsif ((rdy_i = '1' and
(zw_REG_OP = X"26" or
zw_REG_OP = X"36" or
zw_REG_OP = X"2E" or
zw_REG_OP = X"3E")) and (rdy_i = '1')) then
sig_D_OUT <= d_i(6 downto 0) & reg_F(0);
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
elsif ((rdy_i = '1' and
(zw_REG_OP = X"66" or
zw_REG_OP = X"76" or
zw_REG_OP = X"6E" or
zw_REG_OP = X"7E")) and (rdy_i = '1')) then
sig_D_OUT <= reg_F(0) & d_i(7 downto 1);
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
elsif ((rdy_i = '1' and
zw_REG_OP (7) = '0' and
zw_REG_OP (3 downto 0) = X"7") and (rdy_i = '1')) then
sig_D_OUT <= d_i and NOT (d_alu_prio_i);
ch_a_o <= "00000" & zw_REG_OP (6 downto 4) ;
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
elsif ((rdy_i = '1' and
zw_REG_OP (7) = '1' and
zw_REG_OP (3 downto 0) = X"7") and (rdy_i = '1')) then
sig_D_OUT <= d_i or d_alu_prio_i;
ch_a_o <= "00000" & zw_REG_OP (6 downto 4) ;
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
elsif ((rdy_i = '1' and
(zw_REG_OP = X"14" or
zw_REG_OP = X"1C")) and (rdy_i = '1')) then
sig_D_OUT <= d_i and NOT (q_a_i);
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
elsif ((rdy_i = '1' and
(zw_REG_OP = X"04" or
zw_REG_OP = X"0C")) and (rdy_i = '1')) then
sig_D_OUT <= d_i or q_a_i;
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
end if;
when s419 =>
if ((zw_REG_OP (3 downto 0) = X"7") and (rdy_i = '1')) then
sig_SYNC <= '1';
elsif (((zw_REG_OP = X"14" or
zw_REG_OP = X"04" or
zw_REG_OP = X"0C" or
zw_REG_OP = X"1C")) and (rdy_i = '1')) then
ch_a_o <= zw_b1;
ch_b_o <= X"00";
sig_SYNC <= '1';
elsif (rdy_i = '1') then
ch_a_o <= zw_b1;
ch_b_o <= X"00";
sig_SYNC <= '1';
end if;
when s420 =>
if (rdy_i = '1') then
ch_a_o <= q_a_i (6 downto 0) & '0';
ch_b_o <= X"00";
d_regs_in_o <= q_a_i (6 downto 0) & '0';
load_regs_o <= '1';
sig_SYNC <= '1';
end if;
when s598 =>
if (rdy_i = '1') then
ch_a_o <= reg_F(0) & q_a_i (7 downto 1);
ch_b_o <= X"00";
d_regs_in_o <= reg_F(0) & q_a_i (7 downto 1);
load_regs_o <= '1';
sig_SYNC <= '1';
end if;
when s599 =>
if (rdy_i = '1') then
ch_a_o <= '0' & q_a_i (7 downto 1);
ch_b_o <= X"00";
d_regs_in_o <= '0' & q_a_i (7 downto 1);
load_regs_o <= '1';
sig_SYNC <= '1';
end if;
when s600 =>
if (rdy_i = '1') then
ch_a_o <= q_a_i (6 downto 0) & reg_F(0);
ch_b_o <= X"00";
d_regs_in_o <= q_a_i (6 downto 0) & reg_F(0);
load_regs_o <= '1';
sig_SYNC <= '1';
end if;
when s268 =>
ld_pc_o <= '1';
if (rdy_i = '1' and (
(reg_F(0) = '1' and zw_REG_OP = X"90") or (reg_F(0) = '0' and zw_REG_OP = X"B0") or
(reg_F(1) = '0' and zw_REG_OP = X"F0") or (reg_F(7) = '0' and zw_REG_OP = X"30") or
(reg_F(1) = '1' and zw_REG_OP = X"D0") or (reg_F(7) = '1' and zw_REG_OP = X"10") or
(reg_F(6) = '1' and zw_REG_OP = X"50") or (reg_F(6) = '0' and zw_REG_OP = X"70"))) then
ld_o <= "11";
sig_SYNC <= '1';
elsif (rdy_i = '1') then
ld_o <= "11";
end if;
when s305 =>
offset_o <= (zw_b2(7) & zw_b2(7) &
zw_b2(7) & zw_b2(7) & zw_b2(7) &
zw_b2(7) & zw_b2(7) & zw_b2(7) &
zw_b2(7) & zw_b2(6 downto 0));
ld_pc_o <= '1';
if (rdy_i = '1' and
zw_b3 = adr_nxt_pc_i (15 downto 8)) then
ld_o <= "11";
sig_SYNC <= '1';
elsif (rdy_i = '1') then
ld_o <= "11";
end if;
when s306 =>
offset_o <= (zw_b2(7) & zw_b2(7) & zw_b2(7) &
zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(7) &
zw_b2(7) & zw_b2(7) & zw_b2(6 downto 0));
if (rdy_i = '1') then
sig_SYNC <= '1';
end if;
when jmp1 =>
ld_pc_o <= '1';
when jmp2_1 =>
ld_pc_o <= '1';
if (rdy_i = '1') then
adr_o <= d_i & zw_b1;
ld_o <= "11";
end if;
when jmp_ex =>
ld_pc_o <= '1';
if (rdy_i = '1') then
adr_o <= d_i & zw_b1;
ld_o <= "11";
sig_SYNC <= '1';
end if;
when jmp2_2 =>
offset_o <= (X"00" & q_x_i);
ld_pc_o <= '1';
if (rdy_i = '1') then
adr_o <= d_i & zw_b1;
ld_o <= "11";
end if;
when s402 =>
ld_sp_o <= '1';
ld_pc_o <= '1';
if (rdy_i = '1') then
ld_o <= "11";
end if;
when s421 =>
if (rdy_i = '1') then
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
sig_D_OUT <= adr_pc_i (15 downto 8);
end if;
when s422 =>
ld_sp_o <= '1';
if (rdy_i = '1') then
ld_o <= "11";
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
sig_D_OUT <= adr_pc_i (7 downto 0);
end if;
when s424 =>
ld_pc_o <= '1';
if (rdy_i = '1') then
adr_o <= d_i & zw_b1;
ld_o <= "11";
sig_SYNC <= '1';
end if;
when s362 =>
if (rdy_i = '1') then
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s221 =>
if (rdy_i = '1' and
zw_REG_OP = X"34") then
ch_a_o <= d_i;
ch_b_o <= q_x_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"3C") then
ld_o <= "11";
ld_pc_o <= '1';
ch_a_o <= d_i;
ch_b_o <= q_x_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"24") then
ld_o <= "11";
ld_pc_o <= '1';
elsif (rdy_i = '1' and
zw_REG_OP = X"2C") then
ld_o <= "11";
ld_pc_o <= '1';
elsif (rdy_i = '1' and
zw_REG_OP = X"89") then
ch_a_o <= q_a_i AND d_i;
ch_b_o <= X"00";
ld_o <= "11";
ld_pc_o <= '1';
sig_SYNC <= '1';
end if;
when s232 =>
if (rdy_i = '1') then
ch_a_o <= d_i;
ch_b_o <= "0000000" & zw_b2(0);
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s233 =>
if (rdy_i = '1') then
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s234 =>
if (rdy_i = '1') then
ch_a_o <= q_a_i AND d_i;
ch_b_o <= X"00";
sig_SYNC <= '1';
end if;
when s235 =>
if (rdy_i = '1' AND
zw_b2(0) = '0') then
ch_a_o <= q_a_i AND d_i;
ch_b_o <= X"00";
sig_SYNC <= '1';
end if;
when brk1 =>
ld_sp_o <= '1';
if (rdy_i = '1') then
ld_o <= "11";
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
sig_D_OUT <= adr_nxt_pc_i (15 downto 8);
end if;
when brk2 =>
ld_sp_o <= '1';
if (rdy_i = '1') then
ld_o <= "11";
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
sig_D_OUT <= adr_nxt_pc_i (7 downto 0);
end if;
when brk3 =>
ld_sp_o <= '1';
if (rdy_i = '1') then
ld_o <= "11";
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
sig_D_OUT <= reg_F OR X"30";
end if;
when brk6 =>
ld_pc_o <= '1';
if (rdy_i = '1') then
adr_o <= d_i & zw_b1;
ld_o <= "11";
sig_SYNC <= '1';
end if;
when s425 =>
ld_sp_o <= '1';
if (rdy_i = '1') then
ld_o <= "11";
end if;
when s426 =>
ld_sp_o <= '1';
if (rdy_i = '1') then
ld_o <= "11";
end if;
when s427 =>
ld_sp_o <= '1';
if (rdy_i = '1') then
ld_o <= "11";
end if;
when s429 =>
ld_pc_o <= '1';
if (rdy_i = '1') then
adr_o <= d_i & zw_b1;
ld_o <= "11";
sig_SYNC <= '1';
end if;
when s430 =>
ld_sp_o <= '1';
if (rdy_i = '1') then
ld_o <= "11";
end if;
when s431 =>
ld_sp_o <= '1';
if (rdy_i = '1') then
ld_o <= "11";
end if;
when s433 =>
ld_pc_o <= '1';
if (rdy_i = '1') then
adr_o <= d_i & zw_b1;
ld_o <= "11";
end if;
when s434 =>
if (rdy_i = '1') then
sig_SYNC <= '1';
end if;
when s236 =>
ld_pc_o <= '1';
if (rdy_i = '1' and
(zw_REG_OP = X"C6" OR
zw_REG_OP = X"E6")) then
ld_o <= "11";
elsif (rdy_i = '1' and
(zw_REG_OP = X"D6" OR
zw_REG_OP = X"F6")) then
ch_a_o <= d_i;
ch_b_o <= q_x_i;
elsif (rdy_i = '1' and
(zw_REG_OP = X"CE" OR
zw_REG_OP = X"EE")) then
ld_o <= "11";
elsif (rdy_i = '1' and
(zw_REG_OP = X"DE" OR
zw_REG_OP = X"FE")) then
ld_o <= "11";
ch_a_o <= d_i;
ch_b_o <= q_x_i;
end if;
when s245 =>
ld_pc_o <= '1';
if (rdy_i = '1') then
ld_o <= "11";
end if;
when s246 =>
ld_pc_o <= '1';
if (rdy_i = '1') then
ch_a_o <= d_i;
ch_b_o <= "0000000" & zw_b2(0);
ld_o <= "11";
end if;
when s248 =>
ld_pc_o <= '1';
if (rdy_i = '1') then
ld_o <= "11";
end if;
when s346 =>
if (rdy_i = '1') then
ch_a_o <= d_i;
ch_b_o <= zw_b4;
end if;
when s252 =>
if (rdy_i = '1') then
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
sig_D_OUT <= zw_b1;
end if;
when s253 =>
if (rdy_i = '1') then
ch_a_o <= zw_b1;
ch_b_o <= X"00";
sig_SYNC <= '1';
end if;
when s435 =>
if (rdy_i = '1') then
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
sig_D_OUT <= d_regs_out_i;
ld_o <= "11";
ld_sp_o <= '1';
end if;
when s436 =>
if (rdy_i = '1') then
sig_SYNC <= '1';
end if;
when s437 =>
ld_sp_o <= '1';
if (rdy_i = '1') then
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
sig_D_OUT <= reg_F OR X"30";
ld_o <= "11";
end if;
when s438 =>
if (rdy_i = '1') then
sig_SYNC <= '1';
end if;
when s439 =>
if (rdy_i = '1') then
ld_o <= "11";
ld_sp_o <= '1';
end if;
when s441 =>
if (rdy_i = '1') then
d_regs_in_o <= d_i;
load_regs_o <= '1';
ch_a_o <= d_i;
ch_b_o <= X"00";
sig_SYNC <= '1';
end if;
when s442 =>
if (rdy_i = '1') then
ld_o <= "11";
ld_sp_o <= '1';
end if;
when s444 =>
if (rdy_i = '1') then
sig_SYNC <= '1';
end if;
when irq1 =>
ld_sp_o <= '1';
if (rdy_i = '1') then
ld_o <= "11";
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
sig_D_OUT <= zw_w3 (15 downto 8);
end if;
when irq2 =>
ld_sp_o <= '1';
if (rdy_i = '1') then
ld_o <= "11";
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
sig_D_OUT <= zw_w3 (7 downto 0);
end if;
when irq3 =>
ld_sp_o <= '1';
if (rdy_i = '1') then
ld_o <= "11";
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
sig_D_OUT <= (reg_F AND X"EF");
end if;
when irq6 =>
ld_pc_o <= '1';
if (rdy_i = '1') then
adr_o <= d_i & zw_b1;
rst_nmi_o <= '1';
ld_o <= "11";
sig_SYNC <= '1';
end if;
when s11 =>
if (rdy_i = '1') then
ld_o <= "11";
ld_pc_o <= '1';
sig_SYNC <= '1';
end if;
when s12 =>
ld_pc_o <= '1';
if (rdy_i = '1') then
ld_o <= "11";
end if;
when s20 =>
if (rdy_i = '1') then
sig_SYNC <= '1';
end if;
when s14 =>
ld_pc_o <= '1';
if (rdy_i = '1') then
ld_o <= "11";
end if;
when s23 =>
if (rdy_i = '1') then
sig_SYNC <= '1';
end if;
when s15 =>
ld_pc_o <= '1';
if (rdy_i = '1') then
ld_o <= "11";
end if;
when s25 =>
ld_pc_o <= '1';
if (rdy_i = '1') then
ld_o <= "11";
end if;
when s28 =>
if (rdy_i = '1') then
sig_SYNC <= '1';
end if;
when s16 =>
ld_pc_o <= '1';
if (rdy_i = '1') then
ld_o <= "11";
end if;
when s30 =>
ld_pc_o <= '1';
if (rdy_i = '1') then
ld_o <= "11";
end if;
when s33 =>
if (rdy_i = '1') then
sig_SYNC <= '1';
end if;
when jmp3_2 =>
ld_pc_o <= '1';
if (rdy_i = '1') then
ld_o <= "11";
end if;
when s601 =>
if (rdy_i = '1') then
sig_SYNC <= '1';
end if;
when s602 =>
if (rdy_i = '1') then
sig_SYNC <= '1';
end if;
when s270 =>
ld_pc_o <= '1';
if (rdy_i = '1') then
ld_o <= "11";
end if;
when s307 =>
offset_o <= (zw_b2(7) & zw_b2(7) &
zw_b2(7) & zw_b2(7) & zw_b2(7) &
zw_b2(7) & zw_b2(7) & zw_b2(7) &
zw_b2(7) & zw_b2(6 downto 0));
ld_pc_o <= '1';
if (rdy_i = '1' and
zw_b3 = adr_nxt_pc_i (15 downto 8)) then
ld_o <= "11";
sig_SYNC <= '1';
elsif (rdy_i = '1') then
ld_o <= "11";
end if;
when s308 =>
ld_pc_o <= '1';
if (rdy_i = '1' and (
(zw_b1(0) = '0' and zw_REG_OP = X"8F") or
(zw_b1(1) = '0' and zw_REG_OP = X"9F") or
(zw_b1(2) = '0' and zw_REG_OP = X"AF") or
(zw_b1(3) = '0' and zw_REG_OP = X"BF") or
(zw_b1(4) = '0' and zw_REG_OP = X"CF") or
(zw_b1(5) = '0' and zw_REG_OP = X"DF") or
(zw_b1(6) = '0' and zw_REG_OP = X"EF") or
(zw_b1(7) = '0' and zw_REG_OP = X"FF") or
(zw_b1(0) = '1' and zw_REG_OP = X"0F") or
(zw_b1(1) = '1' and zw_REG_OP = X"1F") or
(zw_b1(2) = '1' and zw_REG_OP = X"2F") or
(zw_b1(3) = '1' and zw_REG_OP = X"3F") or
(zw_b1(4) = '1' and zw_REG_OP = X"4F") or
(zw_b1(5) = '1' and zw_REG_OP = X"5F") or
(zw_b1(6) = '1' and zw_REG_OP = X"6F") or
(zw_b1(7) = '1' and zw_REG_OP = X"7F"))) then
ld_o <= "11";
sig_SYNC <= '1';
elsif (rdy_i = '1') then
ld_o <= "11";
end if;
when s309 =>
offset_o <= (zw_b2(7) & zw_b2(7) & zw_b2(7) &
zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(7) &
zw_b2(7) & zw_b2(7) & zw_b2(6 downto 0));
if (rdy_i = '1') then
sig_SYNC <= '1';
end if;
when RES2 =>
ld_o <= "11";
ld_pc_o <= '1';
ld_sp_o <= '1';
sig_RWn <= '1';
sig_RD <= '1';
when others =>
null;
end case;
end process output_proc;
-- Concurrent Statements
-- Clocked output assignments
d_o <= d_o_cld;
rd_o <= rd_o_cld;
sync_o <= sync_o_cld;
wr_n_o <= wr_n_o_cld;
wr_o <= wr_o_cld;
end fsm;
| gpl-3.0 |
fbelavenuto/msx1fpga | src/video/vdp18/vdp18_core.vhd | 2 | 16669 | -------------------------------------------------------------------------------
--
-- Synthesizable model of TI's TMS9918A, TMS9928A, TMS9929A.
--
-- $Id: vdp18_core.vhd,v 1.28 2006/06/18 10:47:01 arnim Exp $
--
-- Core Toplevel
--
-- Notes:
-- This core implements a simple VRAM interface which is suitable for a
-- synchronous SRAM component. There is currently no support of the
-- original DRAM interface.
--
-- Please be aware that the colors might me slightly different from the
-- original TMS9918. It is assumed that the simplified conversion to RGB
-- encoding is equivalent to the compatability mode of the V9938.
-- Implementing a 100% correct color encoding for RGB would require
-- significantly more logic and 8-bit wide RGB DACs.
--
-- References:
--
-- * TI Data book TMS9918.pdf
-- http://www.bitsavers.org/pdf/ti/_dataBooks/TMS9918.pdf
--
-- * Sean Young's tech article:
-- http://bifi.msxnet.org/msxnet/tech/tms9918a.txt
--
-- * Paul Urbanus' discussion of the timing details
-- http://bifi.msxnet.org/msxnet/tech/tmsposting.txt
--
-- * Richard F. Drushel's article series
-- "This Week With My Coleco ADAM"
-- http://junior.apk.net/~drushel/pub/coleco/twwmca/index.html
--
-------------------------------------------------------------------------------
--
-- Copyright (c) 2006, Arnim Laeuger ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- 2016/11 - Some changes by Fabio Belavenuto
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
use work.vdp18_pack.opmode_t;
use work.vdp18_pack.hv_t;
use work.vdp18_pack.access_t;
use work.vdp18_pack.to_boolean_f;
use work.vdp18_pack.to_std_logic_f;
entity vdp18_core is
generic (
video_opt_g : integer := 0 -- 0 = no dblscan, 1 = dblscan configurable, 2 = dblscan always enabled, 3 = no dblscan and external palette
);
port (
-- Global Interface -------------------------------------------------------
clock_i : in std_logic;
clk_en_10m7_i : in std_logic;
por_i : in std_logic;
reset_i : in std_logic;
-- CPU Interface ----------------------------------------------------------
csr_n_i : in std_logic;
csw_n_i : in std_logic;
mode_i : in std_logic_vector( 0 to 1);
int_n_o : out std_logic;
cd_i : in std_logic_vector( 0 to 7);
cd_o : out std_logic_vector( 0 to 7);
wait_o : out std_logic;
-- VRAM Interface ---------------------------------------------------------
vram_ce_o : out std_logic;
vram_oe_o : out std_logic;
vram_we_o : out std_logic;
vram_a_o : out std_logic_vector( 0 to 13);
vram_d_o : out std_logic_vector( 0 to 7);
vram_d_i : in std_logic_vector( 0 to 7);
-- Video Interface --------------------------------------------------------
vga_en_i : in std_logic;
scanline_en_i : in std_logic;
cnt_hor_o : out std_logic_vector( 8 downto 0);
cnt_ver_o : out std_logic_vector( 7 downto 0);
rgb_r_o : out std_logic_vector( 0 to 3);
rgb_g_o : out std_logic_vector( 0 to 3);
rgb_b_o : out std_logic_vector( 0 to 3);
hsync_n_o : out std_logic;
vsync_n_o : out std_logic;
ntsc_pal_i : in std_logic; -- 0 = NTSC
vertfreq_csw_o : out std_logic;
vertfreq_d_o : out std_logic
);
end vdp18_core;
architecture struct of vdp18_core is
signal por_s : boolean;
signal reset_s : boolean;
signal clk_en_10m7_s,
clk_en_5m37_s,
-- clk_en_3m58_s,
clk_en_acc_s : boolean;
signal opmode_s : opmode_t;
signal access_type_s : access_t;
signal num_pix_s,
num_line_s : hv_t;
signal rgb_hsync_n_s : std_logic;
signal rgb_vsync_n_s : std_logic;
signal vga_hsync_n_s : std_logic;
signal vga_vsync_n_s : std_logic;
signal blank_s : boolean;
signal vert_inc_s : boolean;
signal reg_blank_s,
reg_size1_s,
reg_mag1_s : boolean;
signal spr_5th_s : boolean;
signal spr_5th_num_s : std_logic_vector(0 to 4);
signal stop_sprite_s : boolean;
signal vert_active_s,
hor_active_s : boolean;
signal rd_s,
wr_s : boolean;
signal reg_ntb_s : std_logic_vector(0 to 3);
signal reg_ctb_s : std_logic_vector(0 to 7);
signal reg_pgb_s : std_logic_vector(0 to 2);
signal reg_satb_s : std_logic_vector(0 to 6);
signal reg_spgb_s : std_logic_vector(0 to 2);
signal reg_col1_s,
reg_col0_s : std_logic_vector(0 to 3);
signal cpu_vram_a_s : std_logic_vector(0 to 13);
signal pat_table_s : std_logic_vector(0 to 9);
signal pat_name_s : std_logic_vector(0 to 7);
signal pat_col_s : std_logic_vector(0 to 3);
signal spr_num_s : std_logic_vector(0 to 4);
signal spr_line_s : std_logic_vector(0 to 3);
signal spr_name_s : std_logic_vector(0 to 7);
signal spr0_col_s,
spr1_col_s,
spr2_col_s,
spr3_col_s : std_logic_vector(0 to 3);
signal spr_coll_s : boolean;
signal irq_s : boolean;
signal vram_read_s : boolean;
signal vram_write_s : boolean;
signal col_s : std_logic_vector(0 to 3);
signal col_rgb_s : std_logic_vector(0 to 3);
signal col_vga_s : std_logic_vector(0 to 3);
signal rgb_s : std_logic_vector(0 to 15);
signal palette_idx_s : std_logic_vector(0 to 3);
signal palette_val_s : std_logic_vector(0 to 15);
signal palette_wr_s : std_logic;
signal ntsc_pal_e_s : std_logic;
signal oddline_s : std_logic := '0';
begin
clk_en_10m7_s <= to_boolean_f(clk_en_10m7_i);
rd_s <= not to_boolean_f(csr_n_i);
wr_s <= not to_boolean_f(csw_n_i);
por_s <= por_i = '1';
reset_s <= reset_i = '1';
-----------------------------------------------------------------------------
-- Clock Generator
-----------------------------------------------------------------------------
clk_gen_b: entity work.vdp18_clk_gen
port map (
clock_i => clock_i,
clk_en_10m7_i => clk_en_10m7_i,
reset_i => por_s,
clk_en_5m37_o => clk_en_5m37_s,
clk_en_3m58_o => open, --clk_en_3m58_s,
clk_en_2m68_o => open
);
-----------------------------------------------------------------------------
-- Horizontal and Vertical Timing Generator
-----------------------------------------------------------------------------
hor_vert_b: entity work.vdp18_hor_vert
port map (
clock_i => clock_i,
clk_en_5m37_i => clk_en_5m37_s,
reset_i => por_s,
opmode_i => opmode_s,
ntsc_pal_i => ntsc_pal_e_s,
num_pix_o => num_pix_s,
num_line_o => num_line_s,
vert_inc_o => vert_inc_s,
hsync_n_o => rgb_hsync_n_s,
vsync_n_o => rgb_vsync_n_s,
blank_o => blank_s,
cnt_hor_o => cnt_hor_o,
cnt_ver_o => cnt_ver_o
);
-----------------------------------------------------------------------------
-- Control Module
-----------------------------------------------------------------------------
ctrl_b: entity work.vdp18_ctrl
port map (
clock_i => clock_i,
clk_en_5m37_i => clk_en_5m37_s,
reset_i => reset_s,
opmode_i => opmode_s,
vram_read_i => vram_read_s,
vram_write_i => vram_write_s,
vram_ce_o => vram_ce_o,
vram_oe_o => vram_oe_o,
num_pix_i => num_pix_s,
num_line_i => num_line_s,
vert_inc_i => vert_inc_s,
reg_blank_i => reg_blank_s,
reg_size1_i => reg_size1_s,
stop_sprite_i => stop_sprite_s,
clk_en_acc_o => clk_en_acc_s,
access_type_o => access_type_s,
vert_active_o => vert_active_s,
hor_active_o => hor_active_s,
irq_o => irq_s
);
-----------------------------------------------------------------------------
-- CPU I/O Module
-----------------------------------------------------------------------------
cpu_io_b: entity work.vdp18_cpuio
port map (
clock_i => clock_i,
clk_en_10m7_i => clk_en_10m7_s,
clk_en_acc_i => clk_en_acc_s,
reset_i => por_s,
rd_i => rd_s,
wr_i => wr_s,
mode_i => mode_i,
cd_i => cd_i,
cd_o => cd_o,
cd_oe_o => open,
wait_o => wait_o,
access_type_i => access_type_s,
opmode_o => opmode_s,
vram_read_o => vram_read_s,
vram_write_o => vram_write_s,
vram_we_o => vram_we_o,
vram_a_o => cpu_vram_a_s,
vram_d_o => vram_d_o,
vram_d_i => vram_d_i,
spr_coll_i => spr_coll_s,
spr_5th_i => spr_5th_s,
spr_5th_num_i => spr_5th_num_s,
reg_ev_o => open,
reg_16k_o => open,
reg_blank_o => reg_blank_s,
reg_size1_o => reg_size1_s,
reg_mag1_o => reg_mag1_s,
reg_ntb_o => reg_ntb_s,
reg_ctb_o => reg_ctb_s,
reg_pgb_o => reg_pgb_s,
reg_satb_o => reg_satb_s,
reg_spgb_o => reg_spgb_s,
reg_col1_o => reg_col1_s,
reg_col0_o => reg_col0_s,
palette_idx_o => palette_idx_s,
palette_val_o => palette_val_s,
palette_wr_o => palette_wr_s,
irq_i => irq_s,
int_n_o => int_n_o,
vertfreq_csw_o => vertfreq_csw_o,
vertfreq_d_o => vertfreq_d_o
);
-----------------------------------------------------------------------------
-- VRAM Address Multiplexer
-----------------------------------------------------------------------------
addr_mux_b: entity work.vdp18_addr_mux
port map (
access_type_i => access_type_s,
opmode_i => opmode_s,
num_line_i => num_line_s,
reg_ntb_i => reg_ntb_s,
reg_ctb_i => reg_ctb_s,
reg_pgb_i => reg_pgb_s,
reg_satb_i => reg_satb_s,
reg_spgb_i => reg_spgb_s,
reg_size1_i => reg_size1_s,
cpu_vram_a_i => cpu_vram_a_s,
pat_table_i => pat_table_s,
pat_name_i => pat_name_s,
spr_num_i => spr_num_s,
spr_line_i => spr_line_s,
spr_name_i => spr_name_s,
vram_a_o => vram_a_o
);
-----------------------------------------------------------------------------
-- Pattern Generator
-----------------------------------------------------------------------------
pattern_b: entity work.vdp18_pattern
port map (
clock_i => clock_i,
clk_en_5m37_i => clk_en_5m37_s,
clk_en_acc_i => clk_en_acc_s,
reset_i => reset_s,
opmode_i => opmode_s,
access_type_i => access_type_s,
num_line_i => num_line_s,
vram_d_i => vram_d_i,
vert_inc_i => vert_inc_s,
vsync_n_i => rgb_vsync_n_s,
reg_col1_i => reg_col1_s,
reg_col0_i => reg_col0_s,
pat_table_o => pat_table_s,
pat_name_o => pat_name_s,
pat_col_o => pat_col_s
);
-----------------------------------------------------------------------------
-- Sprite Generator
-----------------------------------------------------------------------------
sprite_b: entity work.vdp18_sprite
port map (
clock_i => clock_i,
clk_en_5m37_i => clk_en_5m37_s,
clk_en_acc_i => clk_en_acc_s,
reset_i => reset_s,
access_type_i => access_type_s,
num_pix_i => num_pix_s,
num_line_i => num_line_s,
vram_d_i => vram_d_i,
vert_inc_i => vert_inc_s,
reg_size1_i => reg_size1_s,
reg_mag1_i => reg_mag1_s,
spr_5th_o => spr_5th_s,
spr_5th_num_o => spr_5th_num_s,
stop_sprite_o => stop_sprite_s,
spr_coll_o => spr_coll_s,
spr_num_o => spr_num_s,
spr_line_o => spr_line_s,
spr_name_o => spr_name_s,
spr0_col_o => spr0_col_s,
spr1_col_o => spr1_col_s,
spr2_col_o => spr2_col_s,
spr3_col_o => spr3_col_s
);
-----------------------------------------------------------------------------
-- Color Multiplexer
-----------------------------------------------------------------------------
col_mux_b: entity work.vdp18_col_mux
port map (
vert_active_i => vert_active_s,
hor_active_i => hor_active_s,
blank_i => blank_s,
reg_col0_i => reg_col0_s,
pat_col_i => pat_col_s,
spr0_col_i => spr0_col_s,
spr1_col_i => spr1_col_s,
spr2_col_i => spr2_col_s,
spr3_col_i => spr3_col_s,
col_o => col_rgb_s
);
von3: if video_opt_g /= 3 generate
ntsc_pal_e_s <= ntsc_pal_i;
-----------------------------------------------------------------------------
-- Palette memory
-----------------------------------------------------------------------------
palette: entity work.vdp18_palette
port map (
reset_i => reset_s,
clock_i => clock_i,
we_i => palette_wr_s,
addr_wr_i => palette_idx_s,
data_i => palette_val_s,
addr_rd_i => col_s,
data_o => rgb_s
);
-----------------------------------------------------------------------------
-- Process rgb_reg
--
-- Purpose:
-- Converts the color information to simple RGB and saves these in
-- output registers.
--
rgb_reg: process (clock_i, por_s)
begin
if por_s then
rgb_r_o <= (others => '0');
rgb_g_o <= (others => '0');
rgb_b_o <= (others => '0');
elsif rising_edge(clock_i) then
if clk_en_10m7_s then
if scanline_en_i = '1' and vga_en_i = '1' then
if rgb_s( 0 to 3) > 1 and oddline_s = '1' then
rgb_r_o <= rgb_s( 0 to 3) - 2;
else
rgb_r_o <= rgb_s( 0 to 3);
end if;
if rgb_s(12 to 15) > 1 and oddline_s = '1' then
rgb_g_o <= rgb_s(12 to 15) - 2;
else
rgb_g_o <= rgb_s(12 to 15);
end if;
if rgb_s( 4 to 7) > 1 and oddline_s = '1' then
rgb_b_o <= rgb_s( 4 to 7) - 2;
else
rgb_b_o <= rgb_s( 4 to 7);
end if;
else
rgb_r_o <= rgb_s( 0 to 3);
rgb_g_o <= rgb_s(12 to 15);
rgb_b_o <= rgb_s( 4 to 7);
end if;
end if;
end if;
end process rgb_reg;
--
-----------------------------------------------------------------------------
end generate;
vo0: if video_opt_g = 0 generate
col_s <= col_rgb_s;
hsync_n_o <= rgb_hsync_n_s;
vsync_n_o <= rgb_vsync_n_s;
end generate;
vo3: if video_opt_g = 3 generate
ntsc_pal_e_s <= '0'; -- Only NTSC
rgb_r_o <= col_rgb_s;
rgb_g_o <= (others => '0');
rgb_b_o <= (others => '0');
hsync_n_o <= rgb_hsync_n_s;
vsync_n_o <= rgb_vsync_n_s;
end generate;
vo1_2: if video_opt_g = 1 or video_opt_g = 2 generate
col_s <= col_vga_s when vga_en_i = '1' or video_opt_g = 2 else col_rgb_s;
scandbl: entity work.dblscan
port map (
-- NOTE CLOCKS MUST BE PHASE LOCKED !!
clk_6m_i => clock_i,
clk_en_6m_i => to_std_logic_f(clk_en_5m37_s),
clk_12m_i => clock_i,
clk_en_12m_i => to_std_logic_f(clk_en_10m7_s),
col_i => col_rgb_s,
col_o => col_vga_s,
oddline_o => oddline_s,
hsync_n_i => rgb_hsync_n_s,
vsync_n_i => rgb_vsync_n_s,
hsync_n_o => vga_hsync_n_s,
vsync_n_o => vga_vsync_n_s
);
hsync_n_o <= vga_hsync_n_s when vga_en_i = '1' or video_opt_g = 2 else rgb_hsync_n_s;
vsync_n_o <= vga_vsync_n_s when vga_en_i = '1' or video_opt_g = 2 else rgb_vsync_n_s;
end generate;
end architecture;
| gpl-3.0 |
hoglet67/AtomBusMon | src/AVR8/spi_mod/spi_slv_sel.vhd | 4 | 2193 | --**********************************************************************************************
-- SPI Peripheral for the AVR Core
-- Version 1.2
-- Modified 10.01.2007
-- Designed by Ruslan Lepetenok
--**********************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
use WORK.std_library.all;
use WORK.avr_adr_pack.all;
entity spi_slv_sel is generic(num_of_slvs : integer := 7);
port(
-- AVR Control
ireset : in std_logic;
cp2 : in std_logic;
adr : in std_logic_vector(15 downto 0);
dbus_in : in std_logic_vector(7 downto 0);
dbus_out : out std_logic_vector(7 downto 0);
iore : in std_logic;
iowe : in std_logic;
out_en : out std_logic;
-- Output
slv_sel_n : out std_logic_vector(num_of_slvs-1 downto 0)
);
end spi_slv_sel;
architecture RTL of spi_slv_sel is
constant SPISlvDcd_Address : integer := PINF_Address;
signal SlvSelRg_Current : std_logic_vector(num_of_slvs-1 downto 0);
signal SlvSelRg_Next : std_logic_vector(num_of_slvs-1 downto 0);
begin
RegWrSeqPrc:process(ireset,cp2)
begin
if (ireset='0') then -- Reset
SlvSelRg_Current <= (others => '0');
elsif (cp2='1' and cp2'event) then -- Clock
SlvSelRg_Current <= SlvSelRg_Next;
end if;
end process;
RegWrComb:process(adr,iowe,dbus_in,SlvSelRg_Current)
begin
SlvSelRg_Next <= SlvSelRg_Current;
if(fn_to_integer(adr)=SPISlvDcd_Address and iowe='1') then
SlvSelRg_Next <= dbus_in(num_of_slvs-1 downto 0);
end if;
end process;
slv_sel_n <= not SlvSelRg_Current(slv_sel_n'range);
out_en <= '1' when (fn_to_integer(adr)=SPISlvDcd_Address and iore='1') else '0';
dbus_out(num_of_slvs-1 downto 0) <= SlvSelRg_Current;
UnusedBits:if(num_of_slvs<8) generate
dbus_out(dbus_out'high downto num_of_slvs) <= (others => '0');
end generate;
end RTL;
| gpl-3.0 |
freecores/camellia-vhdl | pipelining/f_tb.vhd | 1 | 2599 |
--------------------------------------------------------------------------------
-- Designer: Paolo Fulgoni <[email protected]>
--
-- Create Date: 09/14/2007
-- Last Update: 09/25/2007
-- Project Name: camellia-vhdl
-- Description: VHDL Test Bench for module F
--
-- Copyright (C) 2007 Paolo Fulgoni
-- This file is part of camellia-vhdl.
-- camellia-vhdl is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 3 of the License, or
-- (at your option) any later version.
-- camellia-vhdl is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- The Camellia cipher algorithm is 128 bit cipher developed by NTT and
-- Mitsubishi Electric researchers.
-- http://info.isl.ntt.co.jp/crypt/eng/camellia/
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity f_tb is
end f_tb;
ARCHITECTURE behavior of f_tb is
-- Component Declaration for the Unit Under Test (UUT)
component F
port (
reset : in STD_LOGIC;
clk : in STD_LOGIC;
x : in STD_LOGIC_VECTOR (0 to 63);
k : in STD_LOGIC_VECTOR (0 to 63);
z : out STD_LOGIC_VECTOR (0 to 63)
);
end component;
--Inputs
signal reset : STD_LOGIC;
signal clk : STD_LOGIC;
signal x : STD_LOGIC_VECTOR(0 to 63) := (others=>'0');
signal k : STD_LOGIC_VECTOR(0 to 63) := (others=>'0');
--Outputs
signal z : STD_LOGIC_VECTOR(0 to 63);
begin
-- Instantiate the Unit Under Test (UUT)
uut: F port map(
reset => reset,
clk => clk,
x => x,
k => k,
z => z
);
tb : process
begin
reset <= '1';
wait for 10 ns;
reset <= '0';
x <= X"abcdef1234567890";
k <= X"0987654321abcdef";
wait for 30 ns;
x <= X"0000000000000000";
k <= X"0000000000000000";
wait;
end process;
ck : process
begin
clk <= '0';
wait for 15 ns;
clk <= '1';
wait for 15 ns;
end process;
end;
| gpl-3.0 |
freecores/camellia-vhdl | pipelining/keysched256.vhd | 1 | 7666 |
--------------------------------------------------------------------------------
-- Designer: Paolo Fulgoni <[email protected]>
--
-- Create Date: 09/15/2007
-- Last Update: 04/09/2008
-- Project Name: camellia-vhdl
-- Description: Key schedule for 128/192/256-bit keys
--
-- Copyright (C) 2007 Paolo Fulgoni
-- This file is part of camellia-vhdl.
-- camellia-vhdl is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 3 of the License, or
-- (at your option) any later version.
-- camellia-vhdl is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- The Camellia cipher algorithm is 128 bit cipher developed by NTT and
-- Mitsubishi Electric researchers.
-- http://info.isl.ntt.co.jp/crypt/eng/camellia/
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity KEYSCHED256 is
port(
reset : in STD_LOGIC;
clk : in STD_LOGIC;
kl_in : in STD_LOGIC_VECTOR (0 to 127);
kr_in : in STD_LOGIC_VECTOR (0 to 127);
kl_out : out STD_LOGIC_VECTOR (0 to 127);
kr_out : out STD_LOGIC_VECTOR (0 to 127);
ka_out : out STD_LOGIC_VECTOR (0 to 127);
kb_out : out STD_LOGIC_VECTOR (0 to 127)
);
end KEYSCHED256;
architecture RTL of KEYSCHED256 is
component F is
port (
reset : in STD_LOGIC;
clk : in STD_LOGIC;
x : in STD_LOGIC_VECTOR (0 to 63);
k : in STD_LOGIC_VECTOR (0 to 63);
z : out STD_LOGIC_VECTOR (0 to 63)
);
end component;
-- f inputs
signal f1_in : STD_LOGIC_VECTOR (0 to 63);
signal f2_in : STD_LOGIC_VECTOR (0 to 63);
signal f3_in : STD_LOGIC_VECTOR (0 to 63);
signal f4_in : STD_LOGIC_VECTOR (0 to 63);
signal f5_in : STD_LOGIC_VECTOR (0 to 63);
signal f6_in : STD_LOGIC_VECTOR (0 to 63);
-- f outputs
signal f1_out : STD_LOGIC_VECTOR (0 to 63);
signal f2_out : STD_LOGIC_VECTOR (0 to 63);
signal f3_out : STD_LOGIC_VECTOR (0 to 63);
signal f4_out : STD_LOGIC_VECTOR (0 to 63);
signal f5_out : STD_LOGIC_VECTOR (0 to 63);
signal f6_out : STD_LOGIC_VECTOR (0 to 63);
-- intermediate registers
signal reg1_l : STD_LOGIC_VECTOR (0 to 63);
signal reg1_r : STD_LOGIC_VECTOR (0 to 63);
signal reg1_kl : STD_LOGIC_VECTOR (0 to 127);
signal reg1_kr : STD_LOGIC_VECTOR (0 to 127);
signal reg2_l : STD_LOGIC_VECTOR (0 to 63);
signal reg2_r : STD_LOGIC_VECTOR (0 to 63);
signal reg2_kl : STD_LOGIC_VECTOR (0 to 127);
signal reg2_kr : STD_LOGIC_VECTOR (0 to 127);
signal reg3_l : STD_LOGIC_VECTOR (0 to 63);
signal reg3_r : STD_LOGIC_VECTOR (0 to 63);
signal reg3_kl : STD_LOGIC_VECTOR (0 to 127);
signal reg3_kr : STD_LOGIC_VECTOR (0 to 127);
signal reg4_l : STD_LOGIC_VECTOR (0 to 63);
signal reg4_r : STD_LOGIC_VECTOR (0 to 63);
signal reg4_kl : STD_LOGIC_VECTOR (0 to 127);
signal reg4_kr : STD_LOGIC_VECTOR (0 to 127);
signal reg5_l : STD_LOGIC_VECTOR (0 to 63);
signal reg5_r : STD_LOGIC_VECTOR (0 to 63);
signal reg5_kl : STD_LOGIC_VECTOR (0 to 127);
signal reg5_kr : STD_LOGIC_VECTOR (0 to 127);
signal reg5_ka : STD_LOGIC_VECTOR (0 to 127);
signal reg6_l : STD_LOGIC_VECTOR (0 to 63);
signal reg6_r : STD_LOGIC_VECTOR (0 to 63);
signal reg6_kl : STD_LOGIC_VECTOR (0 to 127);
signal reg6_kr : STD_LOGIC_VECTOR (0 to 127);
signal reg6_ka : STD_LOGIC_VECTOR (0 to 127);
-- constant keys
constant k1 : STD_LOGIC_VECTOR (0 to 63) := X"A09E667F3BCC908B";
constant k2 : STD_LOGIC_VECTOR (0 to 63) := X"B67AE8584CAA73B2";
constant k3 : STD_LOGIC_VECTOR (0 to 63) := X"C6EF372FE94F82BE";
constant k4 : STD_LOGIC_VECTOR (0 to 63) := X"54FF53A5F1D36F1C";
constant k5 : STD_LOGIC_VECTOR (0 to 63) := X"10E527FADE682D1D";
constant k6 : STD_LOGIC_VECTOR (0 to 63) := X"B05688C2B3E6C1FD";
-- intermediate signals
signal inter1 : STD_LOGIC_VECTOR (0 to 127);
signal inter2 : STD_LOGIC_VECTOR (0 to 127);
signal ka_tmp : STD_LOGIC_VECTOR (0 to 127);
begin
F1 : F
port map(reset, clk, f1_in, k1, f1_out);
F2 : F
port map(reset, clk, f2_in, k2, f2_out);
F3 : F
port map(reset, clk, f3_in, k3, f3_out);
F4 : F
port map(reset, clk, f4_in, k4, f4_out);
F5 : F
port map(reset, clk, f5_in, k5, f5_out);
F6 : F
port map(reset, clk, f6_in, k6, f6_out);
REG : process(reset, clk)
begin
if (reset = '1') then
reg1_l <= (others=>'0');
reg1_r <= (others=>'0');
reg1_kl <= (others=>'0');
reg1_kr <= (others=>'0');
reg2_l <= (others=>'0');
reg2_r <= (others=>'0');
reg2_kl <= (others=>'0');
reg2_kr <= (others=>'0');
reg3_l <= (others=>'0');
reg3_r <= (others=>'0');
reg3_kl <= (others=>'0');
reg3_kr <= (others=>'0');
reg4_l <= (others=>'0');
reg4_r <= (others=>'0');
reg4_kl <= (others=>'0');
reg4_kr <= (others=>'0');
reg5_l <= (others=>'0');
reg5_r <= (others=>'0');
reg5_kl <= (others=>'0');
reg5_kr <= (others=>'0');
reg5_ka <= (others=>'0');
reg6_l <= (others=>'0');
reg6_r <= (others=>'0');
reg6_kl <= (others=>'0');
reg6_kr <= (others=>'0');
reg6_ka <= (others=>'0');
else
if (rising_edge(clk)) then -- rising clock edge
reg1_l <= f1_in;
reg1_r <= kl_in(64 to 127) xor kr_in(64 to 127);
reg1_kl <= kl_in;
reg1_kr <= kr_in;
reg2_l <= f2_in;
reg2_r <= reg1_l;
reg2_kl <= reg1_kl;
reg2_kr <= reg1_kr;
reg3_l <= f3_in;
reg3_r <= inter1(64 to 127);
reg3_kl <= reg2_kl;
reg3_kr <= reg2_kr;
reg4_l <= f4_in;
reg4_r <= reg3_l;
reg4_kl <= reg3_kl;
reg4_kr <= reg3_kr;
reg5_l <= f5_in;
reg5_r <= inter2(64 to 127);
reg5_kl <= reg4_kl;
reg5_kr <= reg4_kr;
reg5_ka <= ka_tmp;
reg6_l <= f6_in;
reg6_r <= reg5_l;
reg6_kl <= reg5_kl;
reg6_kr <= reg5_kr;
reg6_ka <= reg5_ka;
end if;
end if;
end process;
inter1 <= ((f2_out xor reg2_r) & reg2_l) xor reg2_kl;
ka_tmp <= (f4_out xor reg4_r) & reg4_l;
inter2 <= ka_tmp xor reg4_kr;
-- f inputs
f1_in <= kl_in(0 to 63) xor kr_in(0 to 63);
f2_in <= f1_out xor reg1_r;
f3_in <= inter1(0 to 63);
f4_in <= f3_out xor reg3_r;
f5_in <= inter2(0 to 63);
f6_in <= f5_out xor reg5_r;
-- output
kl_out <= reg6_kl;
kr_out <= reg6_kr;
ka_out <= reg6_ka;
kb_out <= (f6_out xor reg6_r) & reg6_l;
end RTL;
| gpl-3.0 |
hoglet67/AtomBusMon | src/AVR8/Peripheral/SynchronizerLatch.vhd | 4 | 840 | --**********************************************************************************************
-- Transparent latch(used in the synchronizer instead of the first DFF)
-- Version 0.2
-- Modified 10.08.2003
-- Designed by Ruslan Lepetenok
--**********************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
entity SynchronizerLatch is port(
D : in std_logic;
G : in std_logic;
Q : out std_logic;
QN : out std_logic);
end SynchronizerLatch;
architecture RTL of SynchronizerLatch is
signal Q_Tmp : std_logic;
begin
TransparentLatch:process(G,D)
begin
if G='1' then -- Latch is transparent
Q_Tmp <= D;
end if;
end process;
Q <= Q_Tmp;
QN <= not Q_Tmp;
end RTL;
| gpl-3.0 |
fbelavenuto/msx1fpga | src/audio/dac_dsm2v.vhd | 2 | 2099 | -------------------------------------------------------------------------------
-- Title : DAC_DSM2 - sigma-delta DAC converter with double loop
-- Project :
-------------------------------------------------------------------------------
-- File : dac_dsm2.vhd
-- Author : Wojciech M. Zabolotny ( wzab[at]ise.pw.edu.pl )
-- Company :
-- Created : 2009-04-28
-- Last update: 2009-04-29
-- Platform :
-- Standard : VHDL'93c
-------------------------------------------------------------------------------
-- Description: Implementation with use of variables inside of process
-------------------------------------------------------------------------------
-- Copyright (c) 2009 - THIS IS PUBLIC DOMAIN CODE!!!
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2009-04-28 1.0 wzab Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity dac_dsm2v is
generic (
nbits_g : integer := 16
);
port (
reset_i : in std_logic;
clock_i : in std_logic;
dac_i : in signed((nbits_g-1) downto 0);
dac_o : out std_logic
);
end entity;
architecture beh1 of dac_dsm2v is
signal del1_s, del2_s, d_q : signed(nbits_g+2 downto 0) := (others => '0');
constant c1_c : signed(nbits_g+2 downto 0) := to_signed(1, nbits_g+3);
constant c_1_c : signed(nbits_g+2 downto 0) := to_signed(-1, nbits_g+3);
begin
process (clock_i, reset_i)
variable v1_v, v2_v : signed(nbits_g+2 downto 0) := (others => '0');
begin
if reset_i = '1' then
del1_s <= (others => '0');
del2_s <= (others => '0');
dac_o <= '0';
elsif rising_edge(clock_i) then
v1_v := dac_i - d_q + del1_s;
v2_v := v1_v - d_q + del2_s;
if v2_v > 0 then
d_q <= shift_left(c1_c, nbits_g);
dac_o <= '1';
else
d_q <= shift_left(c_1_c, nbits_g);
dac_o <= '0';
end if;
del1_s <= v1_v;
del2_s <= v2_v;
end if;
end process;
end architecture; | gpl-3.0 |
freecores/camellia-vhdl | looping/control.vhd | 1 | 35313 |
--------------------------------------------------------------------------------
-- Designer: Paolo Fulgoni <[email protected]>
--
-- Create Date: 01/31/2008
-- Last Update: 03/28/2008
-- Project Name: camellia-vhdl
-- Description: Control unit and key handling
--
-- Copyright (C) 2008 Paolo Fulgoni
-- This file is part of camellia-vhdl.
-- camellia-vhdl is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 3 of the License, or
-- (at your option) any later version.
-- camellia-vhdl is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- The Camellia cipher algorithm is 128 bit cipher developed by NTT and
-- Mitsubishi Electric researchers.
-- http://info.isl.ntt.co.jp/crypt/eng/camellia/
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity control is
port (
clk : in STD_LOGIC;
reset : in STD_LOGIC;
data_in : in STD_LOGIC_VECTOR (0 to 127);
enc_dec : in STD_LOGIC;
data_rdy : in STD_LOGIC;
data_acq : out STD_LOGIC;
key_in : in STD_LOGIC_VECTOR (0 to 255);
k_len : in STD_LOGIC_VECTOR (0 to 1);
key_rdy : in STD_LOGIC;
key_acq : out STD_LOGIC;
data_to : out STD_LOGIC_VECTOR (0 to 127); -- data to datapath
output_rdy : out STD_LOGIC;
k1 : out STD_LOGIC_VECTOR (0 to 63);
k2 : out STD_LOGIC_VECTOR (0 to 63);
newdata : out STD_LOGIC;
sel : out STD_LOGIC;
pre_xor : out STD_LOGIC_VECTOR (0 to 127);
post_xor : out STD_LOGIC_VECTOR (0 to 127);
data_from : in STD_LOGIC_VECTOR (0 to 127) -- data from datapath
);
end control;
architecture RTL of control is
type STATUS is (KEYa, KEYb, KEYc, KEYd, KEYe, KEYf,
SIX1a, SIX1b, SIX1c, SIX1d, SIX1e, SIX1f,
FL1,
SIX2a, SIX2b, SIX2c, SIX2d, SIX2e, SIX2f,
FL2,
SIX3a, SIX3b, SIX3c, SIX3d, SIX3e, SIX3f,
FL3,
SIX4a, SIX4b, SIX4c, SIX4d, SIX4e, SIX4f,
WT
);
signal PS, NS : STATUS;
type K1_TYPE is (SIG1, SIG2, SIG3, SIG4, SIG5, SIG6,
KL_L, KL_R, KR_L, KR_R, KA_L, KA_R, KB_L, KB_R);
signal k1_sel : K1_TYPE;
type K2_TYPE is (KL_L, KL_R, KR_L, KR_R, KA_L, KA_R, KB_L, KB_R);
signal k2_sel : K2_TYPE;
type POSTXOR_TYPE is (KL, KA, KB, ZERO);
signal postxor_sel : POSTXOR_TYPE;
type PREXOR_TYPE is (KL, KR, KA, KB, ZERO);
signal prexor_sel : PREXOR_TYPE;
-- keys
signal reg_kl : STD_LOGIC_VECTOR (0 to 127);
signal reg_kr : STD_LOGIC_VECTOR (0 to 127);
signal reg_ka : STD_LOGIC_VECTOR (0 to 127);
signal reg_kb : STD_LOGIC_VECTOR (0 to 127);
--keys shifted each step
signal reg_kl_s : STD_LOGIC_VECTOR (0 to 127);
signal reg_kr_s : STD_LOGIC_VECTOR (0 to 127);
signal reg_ka_s : STD_LOGIC_VECTOR (0 to 127);
signal reg_kb_s : STD_LOGIC_VECTOR (0 to 127);
signal reg_k_len : STD_LOGIC_VECTOR (0 to 1);
signal reg_enc_dec : STD_LOGIC;
-- input constant
constant KLEN_128 : STD_LOGIC_VECTOR (0 to 1) := "00";
constant KLEN_192 : STD_LOGIC_VECTOR (0 to 1) := "01";
constant KLEN_256 : STD_LOGIC_VECTOR (0 to 1) := "10";
constant ENC : STD_LOGIC := '0';
constant DEC : STD_LOGIC := '1';
constant SEL_F : STD_LOGIC := '0';
constant SEL_FL : STD_LOGIC := '1';
-- constant keys
constant sigma1 : STD_LOGIC_VECTOR (0 to 63) := X"A09E667F3BCC908B";
constant sigma2 : STD_LOGIC_VECTOR (0 to 63) := X"B67AE8584CAA73B2";
constant sigma3 : STD_LOGIC_VECTOR (0 to 63) := X"C6EF372FE94F82BE";
constant sigma4 : STD_LOGIC_VECTOR (0 to 63) := X"54FF53A5F1D36F1C";
constant sigma5 : STD_LOGIC_VECTOR (0 to 63) := X"10E527FADE682D1D";
constant sigma6 : STD_LOGIC_VECTOR (0 to 63) := X"B05688C2B3E6C1FD";
begin
with k1_sel select
k1 <= sigma1 when SIG1,
sigma2 when SIG2,
sigma3 when SIG3,
sigma4 when SIG4,
sigma5 when SIG5,
sigma6 when SIG6,
reg_kl_s(0 to 63) when KL_L,
reg_kl_s(64 to 127) when KL_R,
reg_kr_s(0 to 63) when KR_L,
reg_kr_s(64 to 127) when KR_R,
reg_ka_s(0 to 63) when KA_L,
reg_ka_s(64 to 127) when KA_R,
reg_kb_s(0 to 63) when KB_L,
reg_kb_s(64 to 127) when others;
with k2_sel select
k2 <= reg_kl_s(0 to 63) when KL_L,
reg_kl_s(64 to 127) when KL_R,
reg_kr_s(0 to 63) when KR_L,
reg_kr_s(64 to 127) when KR_R,
reg_ka_s(0 to 63) when KA_L,
reg_ka_s(64 to 127) when KA_R,
reg_kb_s(0 to 63) when KB_L,
reg_kb_s(64 to 127) when others;
with postxor_sel select
post_xor <= reg_kl_s(64 to 127) & reg_kl_s(0 to 63) when KL,
reg_ka_s(64 to 127) & reg_ka_s(0 to 63) when KA,
reg_kb_s(64 to 127) & reg_kb_s(0 to 63) when KB,
(others=>'0') when others;
with prexor_sel select
pre_xor <= reg_kl_s when KL,
reg_kr_s when KR,
reg_ka_s when KA,
reg_kb_s when KB,
(others=>'0') when others;
REGISTERS_UPDATE : process(reset, clk)
variable coming_from_key : STD_LOGIC;
begin
if (reset = '1') then
reg_kl <= (others=>'0');
reg_kr <= (others=>'0');
reg_ka <= (others=>'0');
reg_kb <= (others=>'0');
reg_kl_s <= (others=>'0');
reg_kr_s <= (others=>'0');
reg_ka_s <= (others=>'0');
reg_kb_s <= (others=>'0');
reg_enc_dec <= '0';
reg_k_len <= (others=>'0');
output_rdy <= '0';
coming_from_key := '0';
else
if (clk'event and clk = '1') then
case PS is
when KEYa =>
coming_from_key := '1';
reg_kl <= key_in(0 to 127);
reg_kl_s <= key_in(0 to 127);
reg_k_len <= k_len;
case k_len is
when KLEN_192 =>
reg_kr <= key_in(128 to 191) & not (key_in(128 to 191));
reg_kr_s <= key_in(128 to 191) & not (key_in(128 to 191));
when KLEN_256 =>
reg_kr <= key_in(128 to 255);
reg_kr_s <= key_in(128 to 255);
when others =>
reg_kr <= (others=>'0');
reg_kr_s <= (others=>'0');
end case;
k1_sel <= SIG1;
when KEYb =>
k1_sel <= SIG2;
when KEYc =>
k1_sel <= SIG3;
when KEYd =>
k1_sel <= SIG4;
when KEYe =>
reg_ka <= data_from;
reg_ka_s <= data_from;
k1_sel <= SIG5;
when KEYf =>
k1_sel <= SIG6;
when SIX1a =>
if (enc_dec = ENC) then
if (coming_from_key = '1') then
if (reg_k_len = KLEN_128) then
reg_ka <= data_from;
reg_ka_s <= data_from;
else
reg_kb <= data_from;
reg_kb_s <= data_from;
end if;
else
reg_ka_s <= reg_ka;
reg_kb_s <= reg_kb;
reg_kl_s <= reg_kl;
reg_kr_s <= reg_kr;
end if;
if (reg_k_len = KLEN_128) then
k1_sel <= KA_L;
else
k1_sel <= KB_L;
end if;
else -- DEC
if (coming_from_key = '1') then
if (reg_k_len = KLEN_128) then
reg_ka <= data_from;
reg_ka_s <= data_from(111 to 127) & data_from(0 to 110); -- >>> 17
else
reg_kb <= data_from;
reg_kb_s <= data_from(111 to 127) & data_from(0 to 110); -- >>> 17
reg_ka_s <= reg_ka_s(111 to 127) & reg_ka_s(0 to 110); -- >>> 17
reg_kr_s <= reg_kr_s(111 to 127) & reg_kr_s(0 to 110); -- >>> 17
end if;
reg_kl_s <= reg_kl_s(111 to 127) & reg_kl_s(0 to 110); -- >>> 17
else
reg_ka_s <= reg_ka(111 to 127) & reg_ka(0 to 110); -- >>> 17
reg_kb_s <= reg_kb(111 to 127) & reg_kb(0 to 110); -- >>> 17
reg_kl_s <= key_in(111 to 127) & key_in(0 to 110); --kl >>> 17
reg_kr_s <= reg_kr(111 to 127) & reg_kr(0 to 110); -- >>> 17
end if;
k1_sel <= KL_R;
end if;
reg_enc_dec <= enc_dec;
when SIX1b =>
coming_from_key := '0';
if (reg_enc_dec = ENC) then
if (reg_k_len = KLEN_128) then
k1_sel <= KA_R;
else
k1_sel <= KB_R;
end if;
else -- DEC
k1_sel <= KL_L; -- for each value of reg_k_len
end if;
when SIX1c =>
if (reg_enc_dec = ENC) then
if (reg_k_len = KLEN_128) then
k1_sel <= KL_L;
reg_kl_s <= reg_kl_s(15 to 127) & reg_kl_s(0 to 14); -- <<< 15
else
k1_sel <= KR_L;
reg_kr_s <= reg_kr_s(15 to 127) & reg_kr_s(0 to 14); -- <<< 15
end if;
else -- DEC
reg_ka_s <= reg_ka_s(111 to 127) & reg_ka_s(0 to 110); -- >>> 17
k1_sel <= KA_R; -- for each value of reg_k_len
end if;
when SIX1d =>
if (reg_enc_dec = ENC) then
if (reg_k_len = KLEN_128) then
k1_sel <= KL_R;
else
k1_sel <= KR_R;
end if;
else -- DEC
k1_sel <= KA_L; -- for each value of reg_k_len
end if;
when SIX1e =>
if (reg_enc_dec = ENC) then
if (reg_k_len = KLEN_128) then
reg_ka_s <= reg_ka_s(15 to 127) & reg_ka_s(0 to 14); -- <<< 15
else
reg_ka_s <= reg_ka_s(15 to 127) & reg_ka_s(0 to 14); -- <<< 15
end if;
k1_sel <= KA_L;
else -- DEC
if (reg_k_len = KLEN_128) then
reg_kl_s <= reg_kl_s(111 to 127) & reg_kl_s(0 to 110); -- >>> 17
k1_sel <= KL_R;
else
reg_kr_s <= reg_kr_s(111 to 127) & reg_kr_s(0 to 110); -- >>> 17
k1_sel <= KR_R;
end if;
end if;
when SIX1f =>
if (reg_enc_dec = ENC) then
k1_sel <= KA_R;
else -- DEC
if (reg_k_len = KLEN_128) then
k1_sel <= KL_L;
else
k1_sel <= KR_L;
end if;
end if;
when FL1 =>
if (reg_enc_dec = ENC) then
if (reg_k_len = KLEN_128) then
k1_sel <= KA_L;
k2_sel <= KA_R;
reg_kl_s <= reg_kl_s(15 to 127) & reg_kl_s(0 to 14); -- <<< 15
reg_ka_s <= reg_ka_s(15 to 127) & reg_ka_s(0 to 14); -- <<< 15
else
k1_sel <= KR_L;
k2_sel <= KR_R;
reg_kb_s <= reg_kb_s(15 to 127) & reg_kb_s(0 to 14); -- <<< 15
reg_kr_s <= reg_kr_s(15 to 127) & reg_kr_s(0 to 14); -- <<< 15
end if;
else -- DEC
if (reg_k_len = KLEN_128) then
k1_sel <= KL_R;
k2_sel <= KL_L;
else
k1_sel <= KA_R;
k2_sel <= KA_L;
end if;
reg_ka_s <= reg_ka_s(111 to 127) & reg_ka_s(0 to 110); -- >>> 17
reg_kl_s <= reg_kl_s(111 to 127) & reg_kl_s(0 to 110); -- >>> 17
end if;
when SIX2a =>
if (reg_enc_dec = ENC) then
if (reg_k_len = KLEN_128) then
k1_sel <= KL_L;
reg_kl_s <= reg_kl_s(15 to 127) & reg_kl_s(0 to 14); -- <<< 15
else
k1_sel <= KB_L;
reg_kb_s <= reg_kb_s(15 to 127) & reg_kb_s(0 to 14); -- <<< 15
reg_kl_s <= reg_kl_s(15 to 127) & reg_kl_s(0 to 14); -- <<< 15
end if;
else -- DEC
if (reg_k_len = KLEN_128) then
k1_sel <= KA_R;
reg_ka_s <= reg_ka_s(111 to 127) & reg_ka_s(0 to 110); -- >>> 17
else
k1_sel <= KL_R;
reg_kb_s <= reg_kb_s(111 to 127) & reg_kb_s(0 to 110); -- >>> 17
reg_kl_s <= reg_kl_s(111 to 127) & reg_kl_s(0 to 110); -- >>> 17
end if;
end if;
when SIX2b =>
if (reg_enc_dec = ENC) then
if (reg_k_len = KLEN_128) then
k1_sel <= KL_R;
else
k1_sel <= KB_R;
reg_kl_s <= reg_kl_s(15 to 127) & reg_kl_s(0 to 14); -- <<< 15
end if;
else -- DEC
if (reg_k_len = KLEN_128) then
k1_sel <= KA_L;
else
k1_sel <= KL_L;
reg_kb_s <= reg_kb_s(111 to 127) & reg_kb_s(0 to 110); -- >>> 17
end if;
end if;
when SIX2c =>
if (reg_enc_dec = ENC) then
if (reg_k_len = KLEN_128) then
k1_sel <= KA_L;
reg_ka_s <= reg_ka_s(15 to 127) & reg_ka_s(0 to 14); -- <<< 15
else
k1_sel <= KL_L;
reg_kl_s <= reg_kl_s(15 to 127) & reg_kl_s(0 to 14); -- <<< 15
end if;
else -- DEC
if (reg_k_len = KLEN_128) then
k1_sel <= KL_R;
reg_kl_s <= reg_kl_s(111 to 127) & reg_kl_s(0 to 110); -- >>> 17
else
k1_sel <= KB_R;
reg_kb_s <= reg_kb_s(111 to 127) & reg_kb_s(0 to 110); -- >>> 17
end if;
end if;
when SIX2d =>
if (reg_enc_dec = ENC) then
if (reg_k_len = KLEN_128) then
reg_kl_s <= reg_kl_s(15 to 127) & reg_kl_s(0 to 14); -- <<< 15
else
reg_ka_s <= reg_ka_s(15 to 127) & reg_ka_s(0 to 14); -- <<< 15
end if;
k1_sel <= KL_R;
else -- DEC
if (reg_k_len = KLEN_128) then
k1_sel <= KA_L;
reg_ka_s <= reg_ka_s(113 to 127) & reg_ka_s(0 to 112); -- >>> 15
else
k1_sel <= KB_L;
reg_kr_s <= reg_kr_s(111 to 127) & reg_kr_s(0 to 110); -- >>> 17
end if;
end if;
when SIX2e =>
if (reg_enc_dec = ENC) then
if (reg_k_len = KLEN_128) then
reg_ka_s <= reg_ka_s(15 to 127) & reg_ka_s(0 to 14); -- <<< 15
else
reg_ka_s <= reg_ka_s(15 to 127) & reg_ka_s(0 to 14); -- <<< 15
end if;
k1_sel <= KA_L;
else -- DEC
if (reg_k_len = KLEN_128) then
k1_sel <= KL_R;
reg_kl_s <= reg_kl_s(113 to 127) & reg_kl_s(0 to 112); -- >>> 15
else
k1_sel <= KR_R;
reg_kr_s <= reg_kr_s(111 to 127) & reg_kr_s(0 to 110); -- >>> 17
end if;
end if;
when SIX2f =>
if (reg_enc_dec = ENC) then
k1_sel <= KA_R;
else -- DEC
if (reg_k_len = KLEN_128) then
k1_sel <= KL_L;
else
k1_sel <= KR_L;
end if;
end if;
when FL2 =>
if (reg_enc_dec = ENC) then
if (reg_k_len = KLEN_128) then
reg_kl_s <= reg_kl_s(17 to 127) & reg_kl_s(0 to 16); -- <<< 17
else
reg_kr_s <= reg_kr_s(15 to 127) & reg_kr_s(0 to 14); -- <<< 15
reg_kl_s <= reg_kl_s(15 to 127) & reg_kl_s(0 to 14); -- <<< 15
end if;
k1_sel <= KL_L;
k2_sel <= KL_R;
else -- DEC
if (reg_k_len = KLEN_128) then
k1_sel <= KA_R;
k2_sel <= KA_L;
reg_ka_s <= reg_ka_s(113 to 127) & reg_ka_s(0 to 112); -- >>> 15
else
k1_sel <= KL_R;
k2_sel <= KL_L;
reg_ka_s <= reg_ka_s(111 to 127) & reg_ka_s(0 to 110); -- >>> 17
reg_kl_s <= reg_kl_s(111 to 127) & reg_kl_s(0 to 110); -- >>> 17
end if;
end if;
when SIX3a =>
if (reg_enc_dec = ENC) then
if (reg_k_len = KLEN_128) then
k1_sel <= KL_L;
reg_kl_s <= reg_kl_s(17 to 127) & reg_kl_s(0 to 16); -- <<< 17
else
k1_sel <= KR_L;
reg_kr_s <= reg_kr_s(15 to 127) & reg_kr_s(0 to 14); -- <<< 15
end if;
else -- DEC
if (reg_k_len = KLEN_128) then
k1_sel <= KA_R;
else
k1_sel <= KA_R;
end if;
reg_ka_s <= reg_ka_s(113 to 127) & reg_ka_s(0 to 112); -- >>> 15
end if;
when SIX3b =>
if (reg_enc_dec = ENC) then
if (reg_k_len = KLEN_128) then
k1_sel <= KL_R;
reg_ka_s <= reg_ka_s(17 to 127) & reg_ka_s(0 to 16); -- <<< 17
else
k1_sel <= KR_R;
reg_kb_s <= reg_kb_s(15 to 127) & reg_kb_s(0 to 14); -- <<< 15
end if;
else -- DEC
if (reg_k_len = KLEN_128) then
k1_sel <= KA_L;
reg_kl_s <= reg_kl_s(113 to 127) & reg_kl_s(0 to 112); -- >>> 15
else
k1_sel <= KA_L;
end if;
end if;
when SIX3c =>
if (reg_enc_dec = ENC) then
if (reg_k_len = KLEN_128) then
k1_sel <= KA_L;
reg_ka_s <= reg_ka_s(17 to 127) & reg_ka_s(0 to 16); -- <<< 17
else
k1_sel <= KB_L;
reg_kb_s <= reg_kb_s(15 to 127) & reg_kb_s(0 to 14); -- <<< 15
end if;
else -- DEC
if (reg_k_len = KLEN_128) then
k1_sel <= KL_R;
else
k1_sel <= KL_R;
end if;
reg_kl_s <= reg_kl_s(113 to 127) & reg_kl_s(0 to 112); -- >>> 15
end if;
when SIX3d =>
if (reg_enc_dec = ENC) then
if (reg_k_len = KLEN_128) then
k1_sel <= KA_R;
else
k1_sel <= KB_R;
end if;
else -- DEC
if (reg_k_len = KLEN_128) then
k1_sel <= KL_L;
else
k1_sel <= KL_L;
reg_kb_s <= reg_kb_s(113 to 127) & reg_kb_s(0 to 112); -- >>> 15
end if;
end if;
when SIX3e =>
if (reg_enc_dec = ENC) then
if (reg_k_len = KLEN_128) then
reg_kl_s <= reg_kl_s(17 to 127) & reg_kl_s(0 to 16); -- <<< 17
else
reg_kl_s <= reg_kl_s(17 to 127) & reg_kl_s(0 to 16); -- <<< 17
end if;
k1_sel <= KL_L;
else -- DEC
if (reg_k_len = KLEN_128) then
k1_sel <= KA_R;
reg_ka_s <= reg_ka_s(113 to 127) & reg_ka_s(0 to 112); -- >>> 15
else
k1_sel <= KB_R;
reg_kb_s <= reg_kb_s(113 to 127) & reg_kb_s(0 to 112); -- >>> 15
end if;
end if;
when SIX3f =>
if (reg_enc_dec = ENC) then
if (reg_k_len = KLEN_128) then
reg_ka_s <= reg_ka_s(17 to 127) & reg_ka_s(0 to 16); -- <<< 17
else
reg_ka_s <= reg_ka_s(15 to 127) & reg_ka_s(0 to 14); -- <<< 15
end if;
k1_sel <= KL_R;
else -- DEC
if (reg_k_len = KLEN_128) then
k1_sel <= KA_L;
reg_kl_s <= reg_kl_s(113 to 127) & reg_kl_s(0 to 112); -- >>> 15
else
k1_sel <= KB_L;
reg_kr_s <= reg_kr_s(113 to 127) & reg_kr_s(0 to 112); -- >>> 15
end if;
end if;
when FL3 =>
if (reg_enc_dec = ENC) then
k1_sel <= KA_L;
k2_sel <= KA_R;
reg_kr_s <= reg_kr_s(17 to 127) & reg_kr_s(0 to 16); -- <<< 17
reg_ka_s <= reg_ka_s(17 to 127) & reg_ka_s(0 to 16); -- <<< 17
else -- DEC
k1_sel <= KR_R;
k2_sel <= KR_L;
reg_ka_s <= reg_ka_s(113 to 127) & reg_ka_s(0 to 112); -- >>> 15
reg_kr_s <= reg_kr_s(113 to 127) & reg_kr_s(0 to 112); -- >>> 15
end if;
when SIX4a =>
if (reg_enc_dec = ENC) then
k1_sel <= KR_L;
reg_kr_s <= reg_kr_s(17 to 127) & reg_kr_s(0 to 16); -- <<< 17
else -- DEC
k1_sel <= KA_R;
reg_ka_s <= reg_ka_s(113 to 127) & reg_ka_s(0 to 112); -- >>> 15
end if;
when SIX4b =>
if (reg_enc_dec = ENC) then
k1_sel <= KR_R;
else -- DEC
k1_sel <= KA_L;
end if;
when SIX4c =>
if (reg_enc_dec = ENC) then
k1_sel <= KA_L;
reg_ka_s <= reg_ka_s(17 to 127) & reg_ka_s(0 to 16); -- <<< 17
else -- DEC
k1_sel <= KR_R;
reg_kr_s <= reg_kr_s(113 to 127) & reg_kr_s(0 to 112); -- >>> 15
end if;
when SIX4d =>
if (reg_enc_dec = ENC) then
k1_sel <= KA_R;
reg_kl_s <= reg_kl_s(17 to 127) & reg_kl_s(0 to 16); -- <<< 17
reg_kb_s <= reg_kb_s(17 to 127) & reg_kb_s(0 to 16); -- <<< 17
else -- DEC
k1_sel <= KR_L;
reg_kb_s <= reg_kb_s(113 to 127) & reg_kb_s(0 to 112); -- >>> 15
reg_kl_s <= reg_kl_s(113 to 127) & reg_kl_s(0 to 112); -- >>> 15
end if;
when SIX4e =>
if (reg_enc_dec = ENC) then
k1_sel <= KL_L;
reg_kl_s <= reg_kl_s(17 to 127) & reg_kl_s(0 to 16); -- <<< 17
reg_kb_s <= reg_kb_s(17 to 127) & reg_kb_s(0 to 16); -- <<< 17
else -- DEC
k1_sel <= KB_R;
reg_kb_s <= reg_kb_s(113 to 127) & reg_kb_s(0 to 112); -- >>> 15
reg_kl_s <= reg_kl_s(113 to 127) & reg_kl_s(0 to 112); -- >>> 15
end if;
when SIX4f =>
if (reg_enc_dec = ENC) then
k1_sel <= KL_R;
reg_kb_s <= reg_kb_s(17 to 127) & reg_kb_s(0 to 16); -- <<< 17
else -- DEC
k1_sel <= KB_L;
reg_kl_s <= reg_kl_s(113 to 127) & reg_kl_s(0 to 112); -- >>> 15
end if;
when WT =>
-- do nothing
end case;
if (PS = KEYa) then
data_to <= key_in(0 to 127); --kl
else
data_to <= data_in;
end if;
case PS is
when KEYc =>
prexor_sel <= KL;
when KEYa | KEYe =>
prexor_sel <= KR;
when SIX1a =>
if (enc_dec = ENC) then
prexor_sel <= KL;
else
if (reg_k_len = KLEN_128) then
prexor_sel <= KA;
else
prexor_sel <= KB;
end if;
end if;
when others =>
prexor_sel <= ZERO;
end case;
case PS is
when SIX3f =>
if (reg_k_len = KLEN_128) then
if (reg_enc_dec = ENC) then
postxor_sel <= KA;
else
postxor_sel <= KL;
end if;
else
postxor_sel <= ZERO;
end if;
when SIX4f =>
if (reg_enc_dec = ENC) then
postxor_sel <= KB;
else
postxor_sel <= KL;
end if;
when others =>
postxor_sel <= ZERO;
end case;
if (PS = SIX1a or PS = KEYa) then
newdata <= '1';
else
newdata <= '0';
end if;
if ((PS = SIX3f and reg_k_len = KLEN_128) or PS = SIX4f) then
output_rdy <= '1';
else
output_rdy <= '0';
end if;
if (PS = FL1 or PS = FL2 or PS = FL3) then
sel <= SEL_FL;
else
sel <= SEL_F;
end if;
if (PS = KEYb) then
key_acq <= '1';
else
key_acq <= '0';
end if;
if (PS = SIX1b) then
data_acq <= '1';
else
data_acq <= '0';
end if;
end if;
end if;
end process;
STATE_UPDATE: process (reset, clk)
begin
if (reset = '1') then
PS <= KEYa;
else
if (clk'event and clk = '1') then
PS <= NS;
end if;
end if;
end process;
NEXT_STATE: process (PS, data_rdy, key_rdy)
begin
case PS is
when KEYa =>
if(key_rdy = '1') then
NS <= KEYb;
else
NS <= KEYa;
end if;
when KEYb =>
NS <= KEYc;
when KEYc =>
NS <= KEYd;
when KEYd =>
if (reg_k_len = KLEN_128) then
NS <= SIX1a;
else
NS <= KEYe;
end if;
when KEYe =>
NS <= KEYf;
when KEYf =>
NS <= SIX1a;
when SIX1a =>
if(data_rdy = '1') then
NS <= SIX1b;
else
NS <= SIX1a;
end if;
when SIX1b =>
NS <= SIX1c;
when SIX1c =>
NS <= SIX1d;
when SIX1d =>
NS <= SIX1e;
when SIX1e =>
NS <= SIX1f;
when SIX1f =>
NS <= FL1;
when FL1 =>
NS <= SIX2a;
when SIX2a =>
NS <= SIX2b;
when SIX2b =>
NS <= SIX2c;
when SIX2c =>
NS <= SIX2d;
when SIX2d =>
NS <= SIX2e;
when SIX2e =>
NS <= SIX2f;
when SIX2f =>
NS <= FL2;
when FL2 =>
NS <= SIX3a;
when SIX3a =>
NS <= SIX3b;
when SIX3b =>
NS <= SIX3c;
when SIX3c =>
NS <= SIX3d;
when SIX3d =>
NS <= SIX3e;
when SIX3e =>
NS <= SIX3f;
when SIX3f =>
if (reg_k_len = KLEN_128) then
if (key_rdy = '1') then
NS <= KEYa;
else
if (data_rdy = '1') then
NS <= SIX1a;
else
NS <= WT;
end if;
end if;
else
NS <= FL3;
end if;
when FL3 =>
NS <= SIX4a;
when SIX4a =>
NS <= SIX4b;
when SIX4b =>
NS <= SIX4c;
when SIX4c =>
NS <= SIX4d;
when SIX4d =>
NS <= SIX4e;
when SIX4e =>
NS <= SIX4f;
when SIX4f =>
if (key_rdy = '1') then
NS <= KEYa;
else
if (data_rdy = '1') then
NS <= SIX1a;
else
NS <= WT;
end if;
end if;
when WT =>
if (key_rdy = '1') then
NS <= KEYa;
else
if (data_rdy = '1') then
NS <= SIX1a;
else
NS <= WT;
end if;
end if;
end case;
end process;
end RTL;
| gpl-3.0 |
fbelavenuto/msx1fpga | src/hdmi/encoder.vhd | 2 | 4437 | -------------------------------------------------------------------[01.11.2014]
-- Encoder
-------------------------------------------------------------------------------
-- Engineer: MVV <[email protected]>
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity encoder is
port (
CLK : in STD_LOGIC;
DATA : in STD_LOGIC_VECTOR (7 downto 0);
C : in STD_LOGIC_VECTOR (1 downto 0);
VDE : in STD_LOGIC; -- Video Data Enable (VDE)
ADE : in STD_LOGIC; -- Audio/auxiliary Data Enable (ADE)
AUX : in STD_LOGIC_VECTOR (3 downto 0);
ENCODED : out STD_LOGIC_VECTOR (9 downto 0));
end encoder;
architecture rtl of encoder is
signal xored : STD_LOGIC_VECTOR (8 downto 0);
signal xnored : STD_LOGIC_VECTOR (8 downto 0);
signal ones : STD_LOGIC_VECTOR (3 downto 0);
signal data_word : STD_LOGIC_VECTOR (8 downto 0);
signal data_word_inv : STD_LOGIC_VECTOR (8 downto 0);
signal data_word_disparity : STD_LOGIC_VECTOR (3 downto 0);
signal dc_bias : STD_LOGIC_VECTOR (3 downto 0) := (others => '0');
begin
-- Work our the two different encodings for the byte
xored(0) <= DATA(0);
xored(1) <= DATA(1) xor xored(0);
xored(2) <= DATA(2) xor xored(1);
xored(3) <= DATA(3) xor xored(2);
xored(4) <= DATA(4) xor xored(3);
xored(5) <= DATA(5) xor xored(4);
xored(6) <= DATA(6) xor xored(5);
xored(7) <= DATA(7) xor xored(6);
xored(8) <= '1';
xnored(0) <= DATA(0);
xnored(1) <= DATA(1) xnor xnored(0);
xnored(2) <= DATA(2) xnor xnored(1);
xnored(3) <= DATA(3) xnor xnored(2);
xnored(4) <= DATA(4) xnor xnored(3);
xnored(5) <= DATA(5) xnor xnored(4);
xnored(6) <= DATA(6) xnor xnored(5);
xnored(7) <= DATA(7) xnor xnored(6);
xnored(8) <= '0';
-- Count how many ones are set in data
ones <= "0000" + DATA(0) + DATA(1) + DATA(2) + DATA(3) + DATA(4) + DATA(5) + DATA(6) + DATA(7);
-- Decide which encoding to use
process (ones, DATA(0), xnored, xored)
begin
if ones > 4 or (ones = 4 and DATA(0) = '0') then
data_word <= xnored;
data_word_inv <= NOT(xnored);
else
data_word <= xored;
data_word_inv <= NOT(xored);
end if;
end process;
-- Work out the DC bias of the dataword;
data_word_disparity <= "1100" + data_word(0) + data_word(1) + data_word(2) + data_word(3) + data_word(4) + data_word(5) + data_word(6) + data_word(7);
-- Now work out what the output should be
process(CLK)
begin
if (CLK'event and CLK = '1') then
-- Video Data Coding
if VDE = '1' then
if dc_bias = "00000" or data_word_disparity = 0 then
-- dataword has no disparity
if data_word(8) = '1' then
ENCODED <= "01" & data_word(7 downto 0);
dc_bias <= dc_bias + data_word_disparity;
else
ENCODED <= "10" & data_word_inv(7 downto 0);
dc_bias <= dc_bias - data_word_disparity;
end if;
elsif (dc_bias(3) = '0' and data_word_disparity(3) = '0') or
(dc_bias(3) = '1' and data_word_disparity(3) = '1') then
ENCODED <= '1' & data_word(8) & data_word_inv(7 downto 0);
dc_bias <= dc_bias + data_word(8) - data_word_disparity;
else
ENCODED <= '0' & data_word;
dc_bias <= dc_bias - data_word_inv(8) + data_word_disparity;
end if;
-- TERC4 Coding
elsif ADE = '1' then
case AUX is
when "0000" => ENCODED <= "1010011100";
when "0001" => ENCODED <= "1001100011";
when "0010" => ENCODED <= "1011100100";
when "0011" => ENCODED <= "1011100010";
when "0100" => ENCODED <= "0101110001";
when "0101" => ENCODED <= "0100011110";
when "0110" => ENCODED <= "0110001110";
when "0111" => ENCODED <= "0100111100";
when "1000" => ENCODED <= "1011001100";
when "1001" => ENCODED <= "0100111001";
when "1010" => ENCODED <= "0110011100";
when "1011" => ENCODED <= "1011000110";
when "1100" => ENCODED <= "1010001110";
when "1101" => ENCODED <= "1001110001";
when "1110" => ENCODED <= "0101100011";
when others => ENCODED <= "1011000011";
end case;
else
-- In the control periods, all values have and have balanced bit count
case C is
when "00" => ENCODED <= "1101010100";
when "01" => ENCODED <= "0010101011";
when "10" => ENCODED <= "0101010100";
when others => ENCODED <= "1010101011";
end case;
dc_bias <= (others => '0');
end if;
end if;
end process;
end rtl;
| gpl-3.0 |
fbelavenuto/msx1fpga | src/tb_msx/ipl_rom.vhd | 2 | 64082 | -- generated with romgen v3.0 by MikeJ
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity ipl_rom is
port (
clk : in std_logic;
addr : in std_logic_vector(12 downto 0);
data : out std_logic_vector(7 downto 0)
);
end;
architecture rtl of ipl_rom is
type ROM_ARRAY is array(0 to 8191) of std_logic_vector(7 downto 0);
constant ROM : ROM_ARRAY := (
x"F3",x"3E",x"28",x"D3",x"40",x"3E",x"12",x"D3", -- 0x0000
x"48",x"3E",x"01",x"D3",x"49",x"0E",x"49",x"3E", -- 0x0008
x"0B",x"D3",x"48",x"ED",x"78",x"3E",x"0C",x"D3", -- 0x0010
x"48",x"ED",x"78",x"AF",x"D3",x"99",x"3E",x"40", -- 0x0018
x"D3",x"99",x"00",x"AF",x"D3",x"98",x"3C",x"18", -- 0x0020
x"FB",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0028
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0030
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0038
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0040
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0048
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0050
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0058
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0060
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0068
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0070
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0078
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0080
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0088
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0090
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0098
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x00A0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x00A8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x00B0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x00B8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x00C0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x00C8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x00D0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x00D8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x00E0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x00E8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x00F0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x00F8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0100
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0108
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0110
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0118
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0120
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0128
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0130
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0138
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0140
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0148
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0150
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0158
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0160
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0168
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0170
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0178
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0180
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0188
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0190
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0198
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x01A0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x01A8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x01B0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x01B8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x01C0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x01C8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x01D0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x01D8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x01E0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x01E8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x01F0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x01F8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0200
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0208
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0210
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0218
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0220
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0228
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0230
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0238
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0240
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0248
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0250
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0258
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0260
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0268
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0270
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0278
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0280
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0288
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0290
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0298
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x02A0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x02A8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x02B0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x02B8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x02C0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x02C8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x02D0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x02D8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x02E0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x02E8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x02F0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x02F8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0300
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0308
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0310
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0318
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0320
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0328
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0330
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0338
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0340
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0348
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0350
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0358
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0360
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0368
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0370
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0378
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0380
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0388
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0390
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0398
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x03A0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x03A8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x03B0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x03B8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x03C0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x03C8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x03D0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x03D8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x03E0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x03E8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x03F0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x03F8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0400
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0408
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0410
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0418
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0420
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0428
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0430
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0438
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0440
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0448
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0450
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0458
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0460
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0468
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0470
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0478
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0480
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0488
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0490
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0498
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x04A0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x04A8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x04B0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x04B8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x04C0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x04C8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x04D0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x04D8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x04E0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x04E8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x04F0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x04F8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0500
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0508
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0510
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0518
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0520
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0528
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0530
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0538
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0540
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0548
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0550
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0558
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0560
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0568
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0570
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0578
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0580
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0588
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0590
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0598
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x05A0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x05A8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x05B0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x05B8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x05C0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x05C8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x05D0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x05D8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x05E0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x05E8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x05F0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x05F8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0600
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0608
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0610
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0618
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0620
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0628
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0630
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0638
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0640
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0648
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0650
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0658
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0660
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0668
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0670
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0678
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0680
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0688
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0690
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0698
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x06A0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x06A8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x06B0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x06B8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x06C0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x06C8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x06D0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x06D8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x06E0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x06E8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x06F0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x06F8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0700
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0708
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0710
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0718
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0720
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0728
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0730
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0738
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0740
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0748
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0750
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0758
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0760
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0768
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0770
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0778
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0780
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0788
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0790
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0798
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x07A0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x07A8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x07B0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x07B8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x07C0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x07C8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x07D0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x07D8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x07E0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x07E8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x07F0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x07F8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0800
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0808
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0810
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0818
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0820
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0828
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0830
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0838
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0840
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0848
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0850
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0858
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0860
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0868
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0870
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0878
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0880
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0888
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0890
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0898
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x08A0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x08A8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x08B0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x08B8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x08C0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x08C8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x08D0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x08D8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x08E0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x08E8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x08F0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x08F8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0900
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0908
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0910
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0918
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0920
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0928
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0930
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0938
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0940
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0948
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0950
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0958
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0960
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0968
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0970
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0978
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0980
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0988
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0990
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0998
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x09A0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x09A8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x09B0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x09B8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x09C0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x09C8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x09D0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x09D8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x09E0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x09E8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x09F0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x09F8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0A00
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0A08
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0A10
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0A18
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0A20
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0A28
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0A30
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0A38
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0A40
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0A48
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0A50
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0A58
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0A60
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0A68
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0A70
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0A78
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0A80
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0A88
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0A90
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0A98
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0AA0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0AA8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0AB0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0AB8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0AC0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0AC8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0AD0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0AD8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0AE0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0AE8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0AF0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0AF8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0B00
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0B08
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0B10
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0B18
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0B20
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0B28
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0B30
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0B38
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0B40
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0B48
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0B50
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0B58
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0B60
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0B68
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0B70
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0B78
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0B80
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0B88
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0B90
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0B98
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0BA0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0BA8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0BB0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0BB8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0BC0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0BC8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0BD0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0BD8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0BE0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0BE8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0BF0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0BF8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0C00
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0C08
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0C10
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0C18
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0C20
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0C28
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0C30
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0C38
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0C40
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0C48
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0C50
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0C58
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0C60
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0C68
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0C70
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0C78
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0C80
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0C88
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0C90
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0C98
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0CA0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0CA8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0CB0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0CB8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0CC0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0CC8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0CD0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0CD8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0CE0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0CE8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0CF0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0CF8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0D00
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0D08
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0D10
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0D18
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0D20
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0D28
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0D30
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0D38
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0D40
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0D48
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0D50
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0D58
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0D60
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0D68
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0D70
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0D78
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0D80
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0D88
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0D90
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0D98
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0DA0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0DA8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0DB0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0DB8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0DC0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0DC8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0DD0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0DD8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0DE0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0DE8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0DF0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0DF8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0E00
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0E08
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0E10
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0E18
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0E20
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0E28
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0E30
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0E38
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0E40
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0E48
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0E50
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0E58
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0E60
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0E68
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0E70
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0E78
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0E80
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0E88
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0E90
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0E98
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0EA0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0EA8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0EB0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0EB8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0EC0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0EC8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0ED0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0ED8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0EE0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0EE8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0EF0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0EF8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0F00
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0F08
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0F10
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0F18
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0F20
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0F28
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0F30
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0F38
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0F40
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0F48
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0F50
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0F58
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0F60
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0F68
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0F70
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0F78
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0F80
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0F88
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0F90
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0F98
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0FA0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0FA8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0FB0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0FB8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0FC0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0FC8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0FD0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0FD8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0FE0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0FE8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0FF0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0FF8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1000
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1008
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1010
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1018
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1020
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1028
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1030
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1038
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1040
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1048
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1050
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1058
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1060
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1068
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1070
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1078
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1080
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1088
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1090
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1098
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x10A0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x10A8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x10B0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x10B8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x10C0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x10C8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x10D0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x10D8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x10E0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x10E8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x10F0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x10F8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1100
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1108
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1110
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1118
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1120
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1128
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1130
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1138
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1140
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1148
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1150
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1158
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1160
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1168
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1170
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1178
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1180
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1188
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1190
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1198
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x11A0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x11A8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x11B0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x11B8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x11C0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x11C8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x11D0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x11D8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x11E0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x11E8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x11F0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x11F8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1200
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1208
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1210
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1218
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1220
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1228
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1230
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1238
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1240
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1248
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1250
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1258
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1260
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1268
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1270
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1278
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1280
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1288
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1290
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1298
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x12A0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x12A8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x12B0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x12B8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x12C0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x12C8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x12D0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x12D8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x12E0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x12E8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x12F0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x12F8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1300
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1308
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1310
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1318
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1320
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1328
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1330
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1338
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1340
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1348
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1350
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1358
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1360
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1368
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1370
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1378
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1380
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1388
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1390
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1398
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x13A0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x13A8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x13B0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x13B8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x13C0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x13C8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x13D0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x13D8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x13E0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x13E8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x13F0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x13F8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1400
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1408
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1410
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1418
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1420
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1428
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1430
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1438
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1440
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1448
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1450
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1458
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1460
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1468
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1470
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1478
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1480
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1488
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1490
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1498
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x14A0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x14A8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x14B0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x14B8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x14C0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x14C8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x14D0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x14D8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x14E0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x14E8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x14F0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x14F8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1500
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1508
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1510
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1518
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1520
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1528
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1530
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1538
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1540
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1548
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1550
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1558
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1560
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1568
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1570
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1578
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1580
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1588
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1590
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1598
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x15A0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x15A8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x15B0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x15B8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x15C0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x15C8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x15D0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x15D8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x15E0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x15E8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x15F0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x15F8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1600
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1608
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1610
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1618
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1620
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1628
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1630
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1638
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1640
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1648
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1650
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1658
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1660
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1668
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1670
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1678
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1680
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1688
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1690
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1698
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x16A0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x16A8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x16B0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x16B8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x16C0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x16C8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x16D0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x16D8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x16E0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x16E8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x16F0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x16F8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1700
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1708
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1710
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1718
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1720
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1728
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1730
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1738
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1740
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1748
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1750
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1758
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1760
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1768
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1770
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1778
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1780
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1788
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1790
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1798
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x17A0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x17A8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x17B0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x17B8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x17C0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x17C8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x17D0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x17D8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x17E0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x17E8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x17F0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x17F8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1800
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1808
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1810
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1818
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1820
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1828
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1830
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1838
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1840
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1848
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1850
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1858
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1860
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1868
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1870
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1878
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1880
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1888
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1890
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1898
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x18A0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x18A8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x18B0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x18B8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x18C0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x18C8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x18D0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x18D8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x18E0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x18E8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x18F0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x18F8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1900
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1908
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1910
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1918
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1920
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1928
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1930
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1938
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1940
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1948
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1950
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1958
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1960
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1968
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1970
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1978
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1980
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1988
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1990
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1998
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x19A0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x19A8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x19B0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x19B8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x19C0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x19C8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x19D0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x19D8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x19E0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x19E8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x19F0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x19F8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1A00
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1A08
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1A10
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1A18
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1A20
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1A28
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1A30
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1A38
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1A40
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1A48
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1A50
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1A58
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1A60
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1A68
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1A70
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1A78
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1A80
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1A88
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1A90
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1A98
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1AA0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1AA8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1AB0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1AB8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1AC0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1AC8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1AD0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1AD8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1AE0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1AE8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1AF0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1AF8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1B00
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1B08
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1B10
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1B18
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1B20
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1B28
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1B30
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1B38
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1B40
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1B48
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1B50
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1B58
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1B60
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1B68
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1B70
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1B78
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1B80
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1B88
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1B90
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1B98
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1BA0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1BA8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1BB0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1BB8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1BC0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1BC8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1BD0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1BD8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1BE0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1BE8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1BF0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1BF8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1C00
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1C08
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1C10
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1C18
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1C20
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1C28
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1C30
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1C38
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1C40
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1C48
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1C50
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1C58
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1C60
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1C68
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1C70
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1C78
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1C80
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1C88
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1C90
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1C98
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1CA0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1CA8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1CB0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1CB8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1CC0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1CC8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1CD0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1CD8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1CE0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1CE8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1CF0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1CF8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1D00
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1D08
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1D10
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1D18
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1D20
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1D28
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1D30
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1D38
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1D40
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1D48
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1D50
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1D58
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1D60
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1D68
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1D70
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1D78
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1D80
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1D88
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1D90
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1D98
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1DA0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1DA8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1DB0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1DB8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1DC0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1DC8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1DD0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1DD8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1DE0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1DE8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1DF0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1DF8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1E00
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1E08
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1E10
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1E18
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1E20
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1E28
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1E30
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1E38
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1E40
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1E48
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1E50
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1E58
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1E60
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1E68
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1E70
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1E78
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1E80
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1E88
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1E90
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1E98
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1EA0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1EA8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1EB0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1EB8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1EC0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1EC8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1ED0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1ED8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1EE0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1EE8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1EF0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1EF8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1F00
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1F08
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1F10
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1F18
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1F20
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1F28
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1F30
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1F38
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1F40
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1F48
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1F50
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1F58
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1F60
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1F68
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1F70
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1F78
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1F80
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1F88
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1F90
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1F98
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1FA0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1FA8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1FB0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1FB8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1FC0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1FC8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1FD0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1FD8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1FE0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1FE8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1FF0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF" -- 0x1FF8
);
begin
process(clk)
begin
if rising_edge(clk) then
data <= ROM(to_integer(unsigned(addr)));
end if;
end process;
end RTL;
| gpl-3.0 |
freecores/camellia-vhdl | pipelining/sbox2.vhd | 1 | 2421 |
--------------------------------------------------------------------------------
-- Designer: Paolo Fulgoni <[email protected]>
--
-- Create Date: 09/14/2007
-- Last Update: 04/09/2008
-- Project Name: camellia-vhdl
-- Description: Dual-port SBOX2
--
-- Copyright (C) 2007 Paolo Fulgoni
-- This file is part of camellia-vhdl.
-- camellia-vhdl is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 3 of the License, or
-- (at your option) any later version.
-- camellia-vhdl is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- The Camellia cipher algorithm is 128 bit cipher developed by NTT and
-- Mitsubishi Electric researchers.
-- http://info.isl.ntt.co.jp/crypt/eng/camellia/
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity SBOX2 is
port (
clk : IN STD_LOGIC;
addra : IN STD_LOGIC_VECTOR(0 to 7);
addrb : IN STD_LOGIC_VECTOR(0 to 7);
douta : OUT STD_LOGIC_VECTOR(0 to 7);
doutb : OUT STD_LOGIC_VECTOR(0 to 7)
);
end SBOX2;
architecture RTL of SBOX2 is
component SBOX1 is
port (
clk : IN STD_LOGIC;
addra : IN STD_LOGIC_VECTOR(0 to 7);
addrb : IN STD_LOGIC_VECTOR(0 to 7);
douta : OUT STD_LOGIC_VECTOR(0 to 7);
doutb : OUT STD_LOGIC_VECTOR(0 to 7)
);
end component;
-- SBOX1 signals
signal s1_addra : STD_LOGIC_VECTOR(0 to 7);
signal s1_addrb : STD_LOGIC_VECTOR(0 to 7);
signal s1_clk : STD_LOGIC;
signal s1_douta : STD_LOGIC_VECTOR(0 to 7);
signal s1_doutb : STD_LOGIC_VECTOR(0 to 7);
begin
S1 : SBOX1
port map(s1_clk, s1_addra, s1_addrb, s1_douta, s1_doutb);
s1_clk <= clk;
s1_addra <= addra;
s1_addrb <= addrb;
douta <= s1_douta(1 to 7) & s1_douta(0);
doutb <= s1_doutb(1 to 7) & s1_doutb(0);
end RTL;
| gpl-3.0 |
hoglet67/AtomBusMon | src/Z80CpuMonALS.vhd | 2 | 6358 | --------------------------------------------------------------------------------
-- Copyright (c) 2019 David Banks
--
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ /
-- \ \ \/
-- \ \
-- / / Filename : Z80CpuMonALS.vhd
-- /___/ /\ Timestamp : 29/09/2019
-- \ \ / \
-- \___\/\___\
--
--Design Name: Z80CpuMon
--Device: XC6SLX9
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity Z80CpuMonALS is
generic (
num_comparators : integer := 8; -- default value for lx9core board
avr_prog_mem_size : integer := 1024 * 16 -- default value for lx9core board
);
port (
clock : in std_logic;
-- Z80 Signals
RESET_n : in std_logic;
CLK_n : in std_logic;
WAIT_n : in std_logic;
INT_n : in std_logic;
NMI_n : in std_logic;
BUSRQ_n : in std_logic;
M1_n : out std_logic;
MREQ_n : out std_logic;
IORQ_n : out std_logic;
RD_n : out std_logic;
WR_n : out std_logic;
RFSH_n : out std_logic;
HALT_n : out std_logic;
BUSAK_n : out std_logic;
Addr : out std_logic_vector(15 downto 0);
Data : inout std_logic_vector(7 downto 0);
-- Level Shifers Controls
OEC_n : out std_logic;
OEA1_n : out std_logic;
OEA2_n : out std_logic;
OED_n : out std_logic;
DIRD : out std_logic;
-- External trigger inputs
trig : in std_logic_vector(1 downto 0);
-- ID/mode inputs
mode : in std_logic;
id : in std_logic_vector(3 downto 0);
-- Serial Console
avr_RxD : in std_logic;
avr_TxD : out std_logic;
-- Switches
sw1 : in std_logic;
sw2 : in std_logic;
-- LEDs
led1 : out std_logic;
led2 : out std_logic;
led3 : out std_logic;
-- Optional OHO_DY1 connected to test connector
tmosi : out std_logic;
tdin : out std_logic;
tcclk : out std_logic;
-- Optional Debugging signals
test : out std_logic_vector(9 downto 0)
);
end Z80CpuMonALS;
architecture behavioral of Z80CpuMonALS is
signal MREQ_n_int : std_logic;
signal IORQ_n_int : std_logic;
signal M1_n_int : std_logic;
signal RD_n_int : std_logic;
signal WR_n_int : std_logic;
signal RFSH_n_int : std_logic;
signal HALT_n_int : std_logic;
signal BUSAK_n_int : std_logic;
signal tristate_n : std_logic;
signal tristate_ad_n: std_logic;
signal sw_reset_cpu : std_logic;
signal sw_reset_avr : std_logic;
signal led_bkpt : std_logic;
signal led_trig0 : std_logic;
signal led_trig1 : std_logic;
signal TState : std_logic_vector(2 downto 0);
begin
sw_reset_cpu <= not sw1;
sw_reset_avr <= not sw2;
led1 <= led_bkpt;
led2 <= led_trig0;
led3 <= led_trig1;
MREQ_n <= MREQ_n_int;
IORQ_n <= IORQ_n_int;
M1_n <= M1_n_int;
RD_n <= RD_n_int;
WR_n <= WR_n_int;
RFSH_n <= RFSH_n_int;
HALT_n <= HALT_n_int;
BUSAK_n <= BUSAK_n_int;
OEC_n <= not tristate_n;
OEA1_n <= not tristate_ad_n;
OEA2_n <= not tristate_ad_n;
OED_n <= not tristate_ad_n;
wrapper : entity work.Z80CpuMon
generic map (
ClkMult => 12,
ClkDiv => 25,
ClkPer => 20.000,
num_comparators => num_comparators,
avr_prog_mem_size => avr_prog_mem_size
)
port map (
clock => clock,
-- Z80 Signals
RESET_n => RESET_n,
CLK_n => CLK_n,
WAIT_n => WAIT_n,
INT_n => INT_n,
NMI_n => NMI_n,
BUSRQ_n => BUSRQ_n,
M1_n => M1_n_int,
MREQ_n => MREQ_n_int,
IORQ_n => IORQ_n_int,
RD_n => RD_n_int,
WR_n => WR_n_int,
RFSH_n => RFSH_n_int,
HALT_n => HALT_n_int,
BUSAK_n => BUSAK_n_int,
Addr => Addr,
Data => Data,
-- Buffer Control Signals
DIRD => DIRD,
tristate_n => tristate_n,
tristate_ad_n => tristate_ad_n,
-- Mode jumper, tie low to generate NOPs when paused
mode => mode,
-- External trigger inputs
trig => trig,
-- Serial Console
avr_RxD => avr_RxD,
avr_TxD => avr_TxD,
-- Switches
sw_reset_cpu => sw_reset_cpu,
sw_reset_avr => sw_reset_avr,
-- LEDs
led_bkpt => led_bkpt,
led_trig0 => led_trig0,
led_trig1 => led_trig1,
-- OHO_DY1 connected to test connector
tmosi => tmosi,
tdin => tdin,
tcclk => tcclk,
-- Debugging signals
test1 => open,
test2 => TState(0),
test3 => TState(1),
test4 => TSTate(2)
);
-- Test outputs
test(0) <= M1_n_int;
test(1) <= RD_n_int;
test(2) <= WR_n_int;
test(3) <= MREQ_n_int;
test(4) <= IORQ_n_int;
test(5) <= WAIT_n;
test(6) <= CLK_n;
test(7) <= TState(2);
test(8) <= TState(1);
test(9) <= TState(0);
end behavioral;
| gpl-3.0 |
fbelavenuto/msx1fpga | src/syn-de2/pll1.vhd | 1 | 18187 | -- megafunction wizard: %ALTPLL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altpll
-- ============================================================
-- File Name: pll1.vhd
-- Megafunction Name(s):
-- altpll
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY pll1 IS
PORT
(
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ;
c1 : OUT STD_LOGIC ;
c2 : OUT STD_LOGIC ;
locked : OUT STD_LOGIC
);
END pll1;
ARCHITECTURE SYN OF pll1 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2 : STD_LOGIC ;
SIGNAL sub_wire3 : STD_LOGIC ;
SIGNAL sub_wire4 : STD_LOGIC ;
SIGNAL sub_wire5 : STD_LOGIC ;
SIGNAL sub_wire6 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL sub_wire7_bv : BIT_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire7 : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT altpll
GENERIC (
clk0_divide_by : NATURAL;
clk0_duty_cycle : NATURAL;
clk0_multiply_by : NATURAL;
clk0_phase_shift : STRING;
clk1_divide_by : NATURAL;
clk1_duty_cycle : NATURAL;
clk1_multiply_by : NATURAL;
clk1_phase_shift : STRING;
clk2_divide_by : NATURAL;
clk2_duty_cycle : NATURAL;
clk2_multiply_by : NATURAL;
clk2_phase_shift : STRING;
compensate_clock : STRING;
gate_lock_signal : STRING;
inclk0_input_frequency : NATURAL;
intended_device_family : STRING;
invalid_lock_multiplier : NATURAL;
lpm_hint : STRING;
lpm_type : STRING;
operation_mode : STRING;
port_activeclock : STRING;
port_areset : STRING;
port_clkbad0 : STRING;
port_clkbad1 : STRING;
port_clkloss : STRING;
port_clkswitch : STRING;
port_configupdate : STRING;
port_fbin : STRING;
port_inclk0 : STRING;
port_inclk1 : STRING;
port_locked : STRING;
port_pfdena : STRING;
port_phasecounterselect : STRING;
port_phasedone : STRING;
port_phasestep : STRING;
port_phaseupdown : STRING;
port_pllena : STRING;
port_scanaclr : STRING;
port_scanclk : STRING;
port_scanclkena : STRING;
port_scandata : STRING;
port_scandataout : STRING;
port_scandone : STRING;
port_scanread : STRING;
port_scanwrite : STRING;
port_clk0 : STRING;
port_clk1 : STRING;
port_clk2 : STRING;
port_clk3 : STRING;
port_clk4 : STRING;
port_clk5 : STRING;
port_clkena0 : STRING;
port_clkena1 : STRING;
port_clkena2 : STRING;
port_clkena3 : STRING;
port_clkena4 : STRING;
port_clkena5 : STRING;
port_extclk0 : STRING;
port_extclk1 : STRING;
port_extclk2 : STRING;
port_extclk3 : STRING;
valid_lock_multiplier : NATURAL
);
PORT (
clk : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
locked : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
sub_wire7_bv(0 DOWNTO 0) <= "0";
sub_wire7 <= To_stdlogicvector(sub_wire7_bv);
sub_wire4 <= sub_wire0(2);
sub_wire3 <= sub_wire0(0);
sub_wire1 <= sub_wire0(1);
c1 <= sub_wire1;
locked <= sub_wire2;
c0 <= sub_wire3;
c2 <= sub_wire4;
sub_wire5 <= inclk0;
sub_wire6 <= sub_wire7(0 DOWNTO 0) & sub_wire5;
altpll_component : altpll
GENERIC MAP (
clk0_divide_by => 7,
clk0_duty_cycle => 50,
clk0_multiply_by => 3,
clk0_phase_shift => "0",
clk1_divide_by => 7,
clk1_duty_cycle => 50,
clk1_multiply_by => 12,
clk1_phase_shift => "0",
clk2_divide_by => 7,
clk2_duty_cycle => 50,
clk2_multiply_by => 12,
clk2_phase_shift => "-2917",
compensate_clock => "CLK0",
gate_lock_signal => "NO",
inclk0_input_frequency => 20000,
intended_device_family => "Cyclone II",
invalid_lock_multiplier => 5,
lpm_hint => "CBX_MODULE_PREFIX=pll1",
lpm_type => "altpll",
operation_mode => "NORMAL",
port_activeclock => "PORT_UNUSED",
port_areset => "PORT_UNUSED",
port_clkbad0 => "PORT_UNUSED",
port_clkbad1 => "PORT_UNUSED",
port_clkloss => "PORT_UNUSED",
port_clkswitch => "PORT_UNUSED",
port_configupdate => "PORT_UNUSED",
port_fbin => "PORT_UNUSED",
port_inclk0 => "PORT_USED",
port_inclk1 => "PORT_UNUSED",
port_locked => "PORT_USED",
port_pfdena => "PORT_UNUSED",
port_phasecounterselect => "PORT_UNUSED",
port_phasedone => "PORT_UNUSED",
port_phasestep => "PORT_UNUSED",
port_phaseupdown => "PORT_UNUSED",
port_pllena => "PORT_UNUSED",
port_scanaclr => "PORT_UNUSED",
port_scanclk => "PORT_UNUSED",
port_scanclkena => "PORT_UNUSED",
port_scandata => "PORT_UNUSED",
port_scandataout => "PORT_UNUSED",
port_scandone => "PORT_UNUSED",
port_scanread => "PORT_UNUSED",
port_scanwrite => "PORT_UNUSED",
port_clk0 => "PORT_USED",
port_clk1 => "PORT_USED",
port_clk2 => "PORT_USED",
port_clk3 => "PORT_UNUSED",
port_clk4 => "PORT_UNUSED",
port_clk5 => "PORT_UNUSED",
port_clkena0 => "PORT_UNUSED",
port_clkena1 => "PORT_UNUSED",
port_clkena2 => "PORT_UNUSED",
port_clkena3 => "PORT_UNUSED",
port_clkena4 => "PORT_UNUSED",
port_clkena5 => "PORT_UNUSED",
port_extclk0 => "PORT_UNUSED",
port_extclk1 => "PORT_UNUSED",
port_extclk2 => "PORT_UNUSED",
port_extclk3 => "PORT_UNUSED",
valid_lock_multiplier => 1
)
PORT MAP (
inclk => sub_wire6,
clk => sub_wire0,
locked => sub_wire2
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "1"
-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "7"
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "7"
-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "7"
-- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "7"
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "21.428572"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "85.714287"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "85.714287"
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps"
-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "3"
-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "12"
-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "12"
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "21.42857100"
-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "100.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "100.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "-90.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ps"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg"
-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
-- Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll1.mif"
-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK2 STRING "1"
-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
-- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "7"
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "3"
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "7"
-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "12"
-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "7"
-- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "12"
-- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "-2917"
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
-- Retrieval info: CONSTANT: GATE_LOCK_SIGNAL STRING "NO"
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: CONSTANT: INVALID_LOCK_MULTIPLIER NUMERIC "5"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: VALID_LOCK_MULTIPLIER NUMERIC "1"
-- Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT_CLK_EXT VCC "@clk[5..0]"
-- Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT_CLK_EXT VCC "@extclk[3..0]"
-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
-- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
-- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll1.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll1.ppf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll1.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll1.cmp FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll1.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll1_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
-- Retrieval info: CBX_MODULE_PREFIX: ON
| gpl-3.0 |
hoglet67/AtomBusMon | src/AVR8/CommonPacks/AVRuCPackage.vhd | 3 | 10818 | -- *****************************************************************************************
-- AVR constants and type declarations
-- Version 1.0A(Special version for the JTAG OCD)
-- Modified 05.05.2004
-- Designed by Ruslan Lepetenok
-- *****************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use WORK.SynthCtrlPack.all;
package AVRuCPackage is
-- Old package
type ext_mux_din_type is array(0 to CExtMuxInSize-1) of std_logic_vector(7 downto 0);
subtype ext_mux_en_type is std_logic_vector(0 to CExtMuxInSize-1);
-- End of old package
constant IOAdrWidth : positive := 16;
type AVRIOAdr_Type is array(0 to 63) of std_logic_vector(IOAdrWidth-1 downto 0);
constant CAVRIOAdr : AVRIOAdr_Type :=("0000000000000000","0000000000000001","0000000000000010","0000000000000011",
"0000000000000100","0000000000000101","0000000000000110","0000000000000111",
"0000000000001000","0000000000001001","0000000000001010","0000000000001011",
"0000000000001100","0000000000001101","0000000000001110","0000000000001111",
"0000000000010000","0000000000010001","0000000000010010","0000000000010011",
"0000000000010100","0000000000010101","0000000000010110","0000000000010111",
"0000000000011000","0000000000011001","0000000000011010","0000000000011011",
"0000000000011100","0000000000011101","0000000000011110","0000000000011111",
"0000000000100000","0000000000100001","0000000000100010","0000000000100011",
"0000000000100100","0000000000100101","0000000000100110","0000000000100111",
"0000000000101000","0000000000101001","0000000000101010","0000000000101011",
"0000000000101100","0000000000101101","0000000000101110","0000000000101111",
"0000000000110000","0000000000110001","0000000000110010","0000000000110011",
"0000000000110100","0000000000110101","0000000000110110","0000000000110111",
"0000000000111000","0000000000111001","0000000000111010","0000000000111011",
"0000000000111100","0000000000111101","0000000000111110","0000000000111111"); -- I/O port addresses
-- I/O register file
constant RAMPZ_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#3B#);
constant SPL_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#3D#);
constant SPH_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#3E#);
constant SREG_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#3F#);
-- End of I/O register file
-- UART
constant UDR_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#0C#);
constant UBRR_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#09#);
constant USR_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#0B#);
constant UCR_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#0A#);
-- End of UART
-- Timer/Counter
constant TCCR0_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#33#);
constant TCCR1A_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#2F#);
constant TCCR1B_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#2E#);
constant TCCR2_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#25#);
constant ASSR_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#30#);
constant TIMSK_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#37#);
constant TIFR_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#36#);
constant TCNT0_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#32#);
constant TCNT2_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#24#);
constant OCR0_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#31#);
constant OCR2_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#23#);
constant TCNT1H_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#2D#);
constant TCNT1L_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#2C#);
constant OCR1AH_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#2B#);
constant OCR1AL_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#2A#);
constant OCR1BH_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#29#);
constant OCR1BL_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#28#);
constant ICR1AH_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#27#);
constant ICR1AL_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#26#);
-- End of Timer/Counter
-- Service module
constant MCUCR_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#35#);
constant EIMSK_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#39#);
constant EIFR_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#38#);
constant EICR_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#3A#);
constant MCUSR_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#34#);
constant XDIV_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#3C#);
-- End of service module
-- EEPROM
constant EEARH_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#1F#);
constant EEARL_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#1E#);
constant EEDR_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#1D#);
constant EECR_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#1C#);
-- End of EEPROM
-- SPI
constant SPDR_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#0F#);
constant SPSR_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#0E#);
constant SPCR_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#0D#);
-- End of SPI
-- PORTA addresses
constant PORTA_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#1B#);
constant DDRA_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#1A#);
constant PINA_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#19#);
-- PORTB addresses
constant PORTB_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#18#);
constant DDRB_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#17#);
constant PINB_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#16#);
-- PORTC addresses
constant PORTC_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#15#);
constant DDRC_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#14#);
constant PINC_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#13#);
-- PORTD addresses
constant PORTD_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#12#);
constant DDRD_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#11#);
constant PIND_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#10#);
-- PORTE addresses
constant PORTE_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#03#);
constant DDRE_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#02#);
constant PINE_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#01#);
-- PORTF addresses
constant PORTF_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#07#);
constant DDRF_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#08#);
constant PINF_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#00#);
-- ******************** Parallel port address table **************************************
constant CMaxNumOfPPort : positive := 6;
type PPortAdrTbl_Type is record Port_Adr : std_logic_vector(IOAdrWidth-1 downto 0);
DDR_Adr : std_logic_vector(IOAdrWidth-1 downto 0);
Pin_Adr : std_logic_vector(IOAdrWidth-1 downto 0);
end record;
type PPortAdrTblArray_Type is array (0 to CMaxNumOfPPort-1) of PPortAdrTbl_Type;
constant PPortAdrArray : PPortAdrTblArray_Type := ((PORTA_Address,DDRA_Address,PINA_Address), -- PORTA
(PORTB_Address,DDRB_Address,PINB_Address), -- PORTB
(PORTC_Address,DDRC_Address,PINC_Address), -- PORTC
(PORTD_Address,DDRD_Address,PIND_Address), -- PORTD
(PORTE_Address,DDRE_Address,PINE_Address), -- PORTE
(PORTF_Address,DDRF_Address,PINF_Address)); -- PORTF
-- ***************************************************************************************
-- Analog to digital converter
constant ADCL_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#04#);
constant ADCH_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#05#);
constant ADCSR_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#06#);
constant ADMUX_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#07#);
-- Analog comparator
constant ACSR_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#08#);
-- Watchdog
constant WDTCR_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#21#);
-- JTAG OCDR (ATmega128)
constant OCDR_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#22#);
-- JTAG OCDR (ATmega16)
--constant OCDR_Address : std_logic_vector(IOAdrWidth-1 downto 0) := CAVRIOAdr(16#31#);
-- ***************************************************************************************
-- Function declaration
function LOG2(Number : positive) return natural;
end AVRuCPackage;
package body AVRuCPackage is
-- Functions
function LOG2(Number : positive) return natural is
variable Temp : positive;
begin
Temp := 1;
if Number>1 then
for i in 1 to integer'high loop
Temp := 2*Temp;
if Temp>=Number then
return i;
end if;
end loop;
end if;
return 0;
end LOG2;
-- End of functions
end AVRuCPackage;
| gpl-3.0 |
hoglet67/AtomBusMon | src/T80/T80a.vhd | 1 | 11094 | --
-- Z80 compatible microprocessor core, asynchronous top level
--
-- Version : 0247a
--
-- Copyright (c) 2001-2002 Daniel Wallner ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t80/
--
-- Limitations :
--
-- File history :
--
-- 0208 : First complete release
--
-- 0211 : Fixed interrupt cycle
--
-- 0235 : Updated for T80 interface change
--
-- 0238 : Updated for T80 interface change
--
-- 0240 : Updated for T80 interface change
--
-- 0242 : Updated for T80 interface change
--
-- 0247 : Fixed bus req/ack cycle
--
-- 0247a: 7th of September, 2003 by Kazuhiro Tsujikawa ([email protected])
-- Fixed IORQ_n, RD_n, WR_n bus timing
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.T80_Pack.all;
entity T80a is
generic(
Mode : integer := 0 -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
);
port(
-- Additions
TS : out std_logic_vector(2 downto 0);
Regs : out std_logic_vector(255 downto 0);
PdcData : out std_logic_vector(7 downto 0);
-- Original Signals
RESET_n : in std_logic;
CLK_n : in std_logic;
CEN : in std_logic;
WAIT_n : in std_logic;
INT_n : in std_logic;
NMI_n : in std_logic;
BUSRQ_n : in std_logic;
M1_n : out std_logic;
MREQ_n : out std_logic;
IORQ_n : out std_logic;
RD_n : out std_logic;
WR_n : out std_logic;
RFSH_n : out std_logic;
HALT_n : out std_logic;
BUSAK_n : out std_logic;
A : out std_logic_vector(15 downto 0);
Din : in std_logic_vector(7 downto 0);
Dout : out std_logic_vector(7 downto 0);
Den : out std_logic
);
end T80a;
architecture rtl of T80a is
signal Reset_s : std_logic;
signal IntCycle_n : std_logic;
signal NMICycle_n : std_logic;
signal IORQ : std_logic;
signal NoRead : std_logic;
signal Write : std_logic;
signal MREQ : std_logic;
signal MReq_Inhibit : std_logic;
signal IReq_Inhibit : std_logic; -- 0247a
signal Req_Inhibit : std_logic;
signal RD : std_logic;
signal MREQ_n_i : std_logic;
signal IORQ_n_i : std_logic;
signal RD_n_i : std_logic;
signal WR_n_i : std_logic;
signal WR_n_j : std_logic; -- 0247a
signal RFSH_n_i : std_logic;
signal BUSAK_n_i : std_logic;
signal A_i : std_logic_vector(15 downto 0);
signal DO : std_logic_vector(7 downto 0);
signal DI_Reg : std_logic_vector (7 downto 0); -- Input synchroniser
signal Wait_s : std_logic;
signal MCycle : std_logic_vector(2 downto 0);
signal TState : std_logic_vector(2 downto 0);
signal HALT_n_int : std_logic;
signal iack1 : std_logic;
signal iack2 : std_logic;
begin
BUSAK_n <= BUSAK_n_i;
MREQ_n_i <= not MREQ or (Req_Inhibit and MReq_Inhibit);
RD_n_i <= not RD or (IORQ and IReq_Inhibit) or Req_Inhibit; -- DMB
WR_n_j <= WR_n_i or (IORQ and IReq_Inhibit); -- DMB
HALT_n <= HALT_n_int;
--Remove tristate as in ICE-Z80 this is implmeneted in Z80CpuMon
--MREQ_n <= MREQ_n_i; when BUSAK_n_i = '1' else 'Z';
--IORQ_n <= IORQ_n_i or IReq_Inhibit when BUSAK_n_i = '1' else 'Z'; -- 0247a
--RD_n <= RD_n_i when BUSAK_n_i = '1' else 'Z';
--WR_n <= WR_n_j when BUSAK_n_i = '1' else 'Z'; -- 0247a
--RFSH_n <= RFSH_n_i when BUSAK_n_i = '1' else 'Z';
--A <= A_i when BUSAK_n_i = '1' else (others => 'Z');
MREQ_n <= MREQ_n_i;
IORQ_n <= IORQ_n_i or IReq_Inhibit or Req_inhibit; --DMB
RD_n <= RD_n_i;
WR_n <= WR_n_j; -- 0247a
RFSH_n <= RFSH_n_i;
A <= A_i;
Dout <= DO;
Den <= Write and BUSAK_n_i;
process (RESET_n, CLK_n)
begin
if RESET_n = '0' then
Reset_s <= '0';
elsif CLK_n'event and CLK_n = '1' then
Reset_s <= '1';
end if;
end process;
u0 : T80
generic map(
Mode => Mode,
IOWait => 1)
port map(
CEN => CEN,
M1_n => M1_n,
IORQ => IORQ,
NoRead => NoRead,
Write => Write,
RFSH_n => RFSH_n_i,
HALT_n => HALT_n_int,
WAIT_n => Wait_s,
INT_n => INT_n,
NMI_n => NMI_n,
RESET_n => Reset_s,
BUSRQ_n => BUSRQ_n,
BUSAK_n => BUSAK_n_i,
CLK_n => CLK_n,
A => A_i,
DInst => Din,
DI => DI_Reg,
DO => DO,
MC => MCycle,
TS => TState,
IntCycle_n => IntCycle_n,
NMICycle_n => NMICycle_n,
REG => Regs(211 downto 0),
DIRSet => '0',
DIR => (others => '0')
);
Regs(255 downto 212) <= (others => '0');
process (CLK_n)
begin
if CLK_n'event and CLK_n = '0' then
if CEN = '1' then
Wait_s <= WAIT_n or (IORQ_n_i and MREQ_n_i);
if TState = "011" and BUSAK_n_i = '1' then
DI_Reg <= to_x01(Din);
end if;
end if;
end if;
end process;
process (CLK_n) -- 0247a
begin
if CLK_n'event and CLK_n = '1' then
IReq_Inhibit <= (not IORQ) and IntCycle_n;
end if;
end process;
process (Reset_s,CLK_n) -- 0247a
begin
if Reset_s = '0' then
WR_n_i <= '1';
elsif CLK_n'event and CLK_n = '0' then
if CEN = '1' then
if (IORQ = '0') then
if TState = "010" then
WR_n_i <= not Write;
elsif Tstate = "011" then
WR_n_i <= '1';
end if;
else
if TState = "001" then -- DMB
WR_n_i <= not Write;
elsif Tstate = "011" then
WR_n_i <= '1';
end if;
end if;
end if;
end if;
end process;
process (Reset_s,CLK_n) -- 0247a
begin
if Reset_s = '0' then
Req_Inhibit <= '0';
elsif CLK_n'event and CLK_n = '1' then
if CEN = '1' then
if MCycle = "001" and TState = "010" and wait_s = '1' then
Req_Inhibit <= '1';
else
Req_Inhibit <= '0';
end if;
end if;
end if;
end process;
process (Reset_s,CLK_n)
begin
if Reset_s = '0' then
MReq_Inhibit <= '0';
elsif CLK_n'event and CLK_n = '0' then
if CEN = '1' then
if MCycle = "001" and TState = "010" then
MReq_Inhibit <= '1';
else
MReq_Inhibit <= '0';
end if;
end if;
end if;
end process;
process(Reset_s,CLK_n) -- 0247a
begin
if Reset_s = '0' then
RD <= '0';
IORQ_n_i <= '1';
MREQ <= '0';
iack1 <= '0';
iack2 <= '0';
elsif CLK_n'event and CLK_n = '0' then
if CEN = '1' then
if MCycle = "001" then
if IntCycle_n = '1' then
-- Normal M1 Cycle
if TState = "001" then
RD <= '1';
MREQ <= '1';
IORQ_n_i <= '1';
end if;
else
-- Interupt Ack Cycle
-- 5 T-states: T1 T1 (auto wait) T1 (auto wait) T2 T3
-- Assert IORQ in middle of third T1
if TState = "001" then
iack1 <= '1';
iack2 <= iack1;
else
iack1 <= '0';
iack2 <= '0';
end if;
if iack2 = '1' then
IORQ_n_i <= '0';
end if;
end if;
if TState = "011" then
RD <= '0';
IORQ_n_i <= '1';
MREQ <= '1';
end if;
if TState = "100" then
MREQ <= '0';
end if;
else
if TState = "001" and NoRead = '0' then
IORQ_n_i <= not IORQ;
MREQ <= not IORQ;
RD <= not Write; -- DMB
end if;
if TState = "011" then
RD <= '0';
IORQ_n_i <= '1';
MREQ <= '0';
end if;
end if;
end if;
end if;
end process;
TS <= TState;
PdcData <= (not HALT_n_int) & (not NMICycle_n) & (not IntCycle_n) & "00000";
end;
| gpl-3.0 |
fbelavenuto/msx1fpga | src/video/vdp18/vdp18_ctrl.vhd | 2 | 11567 | -------------------------------------------------------------------------------
--
-- Synthesizable model of TI's TMS9918A, TMS9928A, TMS9929A.
--
-- $Id: vdp18_ctrl.vhd,v 1.26 2006/06/18 10:47:01 arnim Exp $
--
-- Timing Controller
--
-------------------------------------------------------------------------------
--
-- Copyright (c) 2006, Arnim Laeuger ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.vdp18_pack.opmode_t;
use work.vdp18_pack.hv_t;
use work.vdp18_pack.access_t;
entity vdp18_ctrl is
port (
clock_i : in std_logic;
clk_en_5m37_i : in boolean;
reset_i : in boolean;
opmode_i : in opmode_t;
vram_read_i : in boolean;
vram_write_i : in boolean;
vram_ce_o : out std_logic;
vram_oe_o : out std_logic;
num_pix_i : in hv_t;
num_line_i : in hv_t;
vert_inc_i : in boolean;
reg_blank_i : in boolean;
reg_size1_i : in boolean;
stop_sprite_i : in boolean;
clk_en_acc_o : out boolean;
access_type_o : out access_t;
vert_active_o : out boolean;
hor_active_o : out boolean;
irq_o : out boolean
);
end vdp18_ctrl;
use work.vdp18_pack.all;
architecture rtl of vdp18_ctrl is
-----------------------------------------------------------------------------
-- This enables a workaround for a bug in XST.
-- ISE 8.1.02i implements wrong functionality otherwise :-(
--
constant xst_bug_wa_c : boolean := true;
--
-----------------------------------------------------------------------------
signal access_type_s : access_t;
-- pragma translate_off
-- Testbench signals --------------------------------------------------------
--
signal ac_s : std_logic_vector(3 downto 0);
--
-----------------------------------------------------------------------------
-- pragma translate_on
signal vert_active_q,
hor_active_q : boolean;
signal sprite_active_q : boolean;
signal sprite_line_act_q : boolean;
begin
-- pragma translate_off
-- Testbench signals --------------------------------------------------------
--
ac_s <= enum_to_vec_f(access_type_s);
--
-----------------------------------------------------------------------------
-- pragma translate_on
-----------------------------------------------------------------------------
-- Process decode_access
--
-- Purpose:
-- Decode horizontal counter value to access type.
--
decode_access: process (opmode_i,num_pix_i,vert_active_q,sprite_line_act_q,reg_size1_i)
variable num_pix_plus_6_v : hv_t;
variable mod_6_v : hv_t;
variable num_pix_plus_8_v : hv_t;
variable num_pix_plus_32_v : hv_t;
variable num_pix_spr_v : integer;
begin
-- default assignment
access_type_s <= AC_CPU;
-- prepare number of pixels for pattern operations
num_pix_plus_6_v := num_pix_i + 6;
num_pix_plus_8_v := num_pix_i + 8;
num_pix_plus_32_v := num_pix_i + 32;
num_pix_spr_v := to_integer(num_pix_i and "111111110");
case opmode_i is
-- Graphics I, II and Multicolor Mode -----------------------------------
when OPMODE_GRAPH1 |
OPMODE_GRAPH2 |
OPMODE_MULTIC =>
--
-- Patterns
--
if vert_active_q then
if num_pix_plus_8_v(0) = '0' then
if not xst_bug_wa_c then
-- original code, we want this
case num_pix_plus_8_v(6 to 7) is
when "01" =>
access_type_s <= AC_PNT;
when "10" =>
if opmode_i /= OPMODE_MULTIC then
-- no access to pattern color table in multicolor mode
access_type_s <= AC_PCT;
end if;
when "11" =>
access_type_s <= AC_PGT;
when others =>
null;
end case;
else
-- workaround for XST bug, we need this
if num_pix_plus_8_v(6 to 7) = "01" then
access_type_s <= AC_PNT;
elsif num_pix_plus_8_v(6 to 7) = "10" then
if opmode_i /= OPMODE_MULTIC then
access_type_s <= AC_PCT;
end if;
elsif num_pix_plus_8_v(6 to 7) = "11" then
access_type_s <= AC_PGT;
end if;
end if;
end if;
end if;
--
-- Sprite test
--
if sprite_line_act_q then
if num_pix_i(0) = '0' and
num_pix_i(0 to 5) /= "011111" and
num_pix_i(6 to 7) = "00" and
num_pix_i(4 to 5) /= "00" then
-- sprite test interleaved with pattern accesses
access_type_s <= AC_STST;
end if;
if (num_pix_plus_32_v(0 to 4) = "00000" or
num_pix_plus_32_v(0 to 5) = "000010") and
num_pix_plus_32_v(6 to 7) /= "00" then
-- sprite tests before starting pattern phase
access_type_s <= AC_STST;
end if;
--
-- Sprite Attribute Table and Sprite Pattern Table
--
case num_pix_spr_v is
when 250 | -78 |
-62 | -46 =>
access_type_s <= AC_SATY;
when 254 | -76 |
-60 | -44 =>
access_type_s <= AC_SATX;
when 252 | -74 |
-58 | -42 =>
access_type_s <= AC_SATN;
when -86 | -70 |
-54 | -38 =>
access_type_s <= AC_SATC;
when -84 | -68 |
-52 | -36 =>
access_type_s <= AC_SPTH;
when -82 | -66 |
-50 | -34 =>
if reg_size1_i then
access_type_s <= AC_SPTL;
end if;
when others =>
null;
end case;
end if;
-- Text Mode ------------------------------------------------------------
when OPMODE_TEXTM =>
if vert_active_q and
num_pix_plus_6_v(0) = '0' and
num_pix_plus_6_v(0 to 4) /= "01111" then
--
mod_6_v := mod_6_f(num_pix_plus_6_v);
case mod_6_v(6 to 7) is
when "00" =>
access_type_s <= AC_PNT;
when "10" =>
access_type_s <= AC_PGT;
when others =>
null;
end case;
end if;
-- Unknown --------------------------------------------------------------
when others =>
null;
end case;
end process decode_access;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Process vert_flags
--
-- Purpose:
-- Track the vertical position with flags.
--
vert_flags: process (clock_i, reset_i)
begin
if reset_i then
vert_active_q <= false;
sprite_active_q <= false;
sprite_line_act_q <= false;
elsif clock_i'event and clock_i = '1' then
if clk_en_5m37_i then
-- line-local sprite processing
if sprite_active_q then
-- sprites are globally enabled
if vert_inc_i then
-- reload at beginning of every new line
-- => scan with STST
sprite_line_act_q <= true;
end if;
if num_pix_i = hv_sprite_start_c then
-- reload when access to sprite memory starts
sprite_line_act_q <= true;
end if;
end if;
if vert_inc_i then
-- global sprite processing
if reg_blank_i then
sprite_active_q <= false;
sprite_line_act_q <= false;
elsif num_line_i = -2 then
-- start at line -1
sprite_active_q <= true;
-- initialize immediately
sprite_line_act_q <= true;
elsif num_line_i = 191 then
-- stop at line 192
sprite_active_q <= false;
-- force stop
sprite_line_act_q <= false;
end if;
-- global vertical display
if reg_blank_i then
vert_active_q <= false;
elsif num_line_i = -1 then
-- start vertical display at line 0
vert_active_q <= true;
elsif num_line_i = 191 then
-- stop at line 192
vert_active_q <= false;
end if;
end if;
if stop_sprite_i then
-- stop processing of sprites in this line
sprite_line_act_q <= false;
end if;
end if;
end if;
end process vert_flags;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Process hor_flags
--
-- Purpose:
-- Track the horizontal position.
--
hor_flags: process (clock_i, reset_i)
begin
if reset_i then
hor_active_q <= false;
elsif clock_i'event and clock_i = '1' then
if clk_en_5m37_i then
if not reg_blank_i and num_pix_i = -1 then
hor_active_q <= true;
end if;
if opmode_i = OPMODE_TEXTM then
if num_pix_i = 239 then
hor_active_q <= false;
end if;
else
if num_pix_i = 255 then
hor_active_q <= false;
end if;
end if;
end if;
end if;
end process hor_flags;
--
-----------------------------------------------------------------------------
vram_ctrl: process (clock_i)
variable read_b_v : boolean;
begin
if rising_edge(clock_i) then
if clk_en_5m37_i then
vram_ce_o <= '0';
vram_oe_o <= '0';
if access_type_s = AC_CPU then
if vram_read_i and not read_b_v then
vram_ce_o <= '1';
vram_oe_o <= '1';
read_b_v := true;
elsif vram_write_i and not read_b_v then
vram_ce_o <= '1';
--
read_b_v := true;
else
read_b_v := false;
end if;
else
if not read_b_v then
vram_ce_o <= '1';
vram_oe_o <= '1';
read_b_v := true;
else
read_b_v := false;
end if;
end if;
end if;
end if;
end process;
-----------------------------------------------------------------------------
-- Ouput mapping
-----------------------------------------------------------------------------
-- generate clock enable for flip-flops working on access_type
clk_en_acc_o <= clk_en_5m37_i and num_pix_i(8) = '1';
access_type_o <= access_type_s;
vert_active_o <= vert_active_q;
hor_active_o <= hor_active_q;
irq_o <= vert_inc_i and num_line_i = 191;
end rtl;
| gpl-3.0 |
fbelavenuto/msx1fpga | src/peripheral/ps2_iobase.vhd | 2 | 6297 | -------------------------------------------------------------------------------
-- Title : MC613
-- Project : PS2 Basic Protocol
-- Details : www.ic.unicamp.br/~corte/mc613/
-- www.computer-engineering.org/ps2protocol/
-------------------------------------------------------------------------------
-- File : ps2_base.vhd
-- Author : Thiago Borges Abdnur
-- Company : IC - UNICAMP
-- Last update: 2010/04/12
-------------------------------------------------------------------------------
-- Description:
-- PS2 basic control
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
entity ps2_iobase is
port(
enable_i : in std_logic; -- Enable
clock_i : in std_logic; -- system clock
reset_i : in std_logic; -- Reset when '1'
ps2_data_io : inout std_logic; -- PS2 data pin
ps2_clk_io : inout std_logic; -- PS2 clock pin
data_rdy_i : in std_logic; -- Rise this to signal data is ready to be sent to device
data_i : in std_logic_vector(7 downto 0); -- Data to be sent to device
data_rdy_o : out std_logic; -- '1' when data from device has arrived
data_o : out std_logic_vector(7 downto 0) -- Data from device
);
end;
architecture rtl of ps2_iobase is
signal clk_syn_s : std_logic;
signal dat_syn_s : std_logic;
signal clk_nedge_s : std_logic;
signal timeout_q : unsigned(15 downto 0) := X"0000";
signal sdata_s : std_logic_vector(7 downto 0);
signal hdata_s : std_logic_vector(7 downto 0);
signal parchecked_s : std_logic;
signal sigsending_s : std_logic;
signal sigsendend_s : std_logic;
signal sigclkreleased : std_logic;
signal sigclkheld : std_logic;
begin
-- Synchronizing signals
process (reset_i, clock_i)
variable clk_sync_v : std_logic_vector(1 downto 0);
variable dat_sync_v : std_logic_vector(1 downto 0);
begin
if reset_i = '1' then
clk_sync_v := "00";
dat_sync_v := "00";
elsif rising_edge(clock_i) then
clk_sync_v := clk_sync_v(0) & ps2_clk_io;
dat_sync_v := dat_sync_v(0) & ps2_data_io;
end if;
clk_syn_s <= clk_sync_v(1);
dat_syn_s <= dat_sync_v(1);
end process;
-- Detect edge
process (reset_i, clock_i)
variable edge_detect_v : std_logic_vector(15 downto 0);
begin
if reset_i = '1' then
edge_detect_v := (others => '0');
elsif rising_edge(clock_i) then
edge_detect_v := edge_detect_v(14 downto 0) & clk_syn_s;
end if;
clk_nedge_s <= '0';
if edge_detect_v = X"F000" then
clk_nedge_s <= '1';
end if;
end process;
-- Receive
process (reset_i, sigsending_s, clock_i)
variable count_v : integer range 0 to 11;
begin
if reset_i = '1' or sigsending_s = '1' then
sdata_s <= (others => '0');
parchecked_s <= '0';
count_v := 0;
elsif rising_edge(clock_i) then
parchecked_s <= '0';
if clk_nedge_s = '1' then
timeout_q <= (others => '0');
if count_v = 0 then
-- Idle state, check for start bit (0) only and don't
-- start counting bits until we get it
if dat_syn_s = '0' then
-- This is a start bit
count_v := count_v + 1;
end if;
else
-- Running. 8-bit data comes in LSb first followed by
-- a single stop bit (1)
if count_v < 9 then
sdata_s(count_v - 1) <= dat_syn_s;
end if;
if count_v = 9 then
if (not (sdata_s(0) xor sdata_s(1) xor sdata_s(2) xor sdata_s(3) xor sdata_s(4) xor sdata_s(5) xor sdata_s(6) xor sdata_s(7))) = dat_syn_s then
parchecked_s <= '1';
end if;
end if;
count_v := count_v + 1;
if count_v = 11 then
count_v := 0;
end if;
end if;
else
if count_v /= 0 then
timeout_q <= timeout_q + 1;
if timeout_q = X"FFFF" then
count_v := 0;
end if;
end if;
end if;
end if;
end process;
data_rdy_o <= enable_i and parchecked_s;
data_o <= sdata_s;
-- Edge triggered send register
-- Host input data register
process (sigsendend_s, reset_i, clock_i)
begin
if reset_i = '1' or sigsendend_s = '1' then
sigsending_s <= '0';
hdata_s <= (others => '0');
elsif rising_edge(clock_i) then
if data_rdy_i = '1' then
sigsending_s <= '1';
hdata_s <= data_i;
end if;
end if;
end process;
-- PS2 clock control
process (enable_i, reset_i, sigsendend_s, clock_i)
constant US100CNT : integer := 3570 / 10;
variable count_v : integer range 0 to US100CNT + 101;
begin
if enable_i = '0' or reset_i = '1' or sigsendend_s = '1' then
ps2_clk_io <= 'Z';
sigclkreleased <= '1';
sigclkheld <= '0';
count_v := 0;
elsif rising_edge(clock_i) then
if sigsending_s = '1' then
if count_v < US100CNT + 50 then
count_v := count_v + 1;
ps2_clk_io <= '0';
sigclkreleased <= '0';
sigclkheld <= '0';
elsif count_v < US100CNT + 100 then
count_v := count_v + 1;
ps2_clk_io <= '0';
sigclkreleased <= '0';
sigclkheld <= '1';
else
ps2_clk_io <= 'Z';
sigclkreleased <= '1';
sigclkheld <= '0';
end if;
end if;
end if;
end process;
-- Sending control
TOPS2:
process (enable_i, reset_i, sigsending_s, sigclkheld, clock_i)
variable count_v : integer range 0 to 11;
begin
if enable_i = '0' or reset_i = '1' or sigsending_s = '0' then
ps2_data_io <= 'Z';
sigsendend_s <= '0';
count_v := 0;
elsif sigclkheld = '1' then
ps2_data_io <= '0';
sigsendend_s <= '0';
count_v := 0;
elsif rising_edge(clock_i) then
if clk_nedge_s = '1' and sigclkreleased = '1' and sigsending_s = '1' then
if count_v >= 0 and count_v < 8 then
ps2_data_io <= hdata_s(count_v);
sigsendend_s <= '0';
end if;
if count_v = 8 then
ps2_data_io <= (not (hdata_s(0) xor hdata_s(1) xor hdata_s(2) xor hdata_s(3) xor hdata_s(4) xor hdata_s(5) xor hdata_s(6) xor hdata_s(7)));
sigsendend_s <= '0';
end if;
if count_v = 9 then
ps2_data_io <= 'Z';
sigsendend_s <= '0';
end if;
if count_v = 10 then
ps2_data_io <= 'Z';
sigsendend_s <= '1';
count_v := 0;
end if;
count_v := count_v + 1;
end if;
end if;
end process;
end architecture; | gpl-3.0 |
z3774/sparcv8-monocycle | sparcv8_v2_tb.vhd | 1 | 2225 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 21:26:45 10/11/2015
-- Design Name:
-- Module Name: C:/Users/Felipe/Desktop/sparcv8/sparcv8_v2_tb.vhd
-- Project Name: sparcv8
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: sparcv8_v2
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY sparcv8_v2_tb IS
END sparcv8_v2_tb;
ARCHITECTURE behavior OF sparcv8_v2_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT sparcv8_v2
PORT(
clk : IN std_logic;
reset : IN std_logic;
alurs : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal reset : std_logic := '0';
--Outputs
signal alurs : std_logic_vector(31 downto 0);
-- Clock period definitions
constant clk_period : time := 20 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: sparcv8_v2 PORT MAP (
clk => clk,
reset => reset,
alurs => alurs
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
reset <= '1';
wait for clk_period;
reset <= '0';
wait;
end process;
END;
| gpl-3.0 |
hoglet67/AtomBusMon | src/oho_dy1/Oho_Dy1.vhd | 2 | 5559 | ----------------------------------------------------------------------------------
-- Company: OHO-Elektronik
-- Engineer: M.Randelzhofer
--
-- Create Date: 20:55:43 02/02/2009
-- Design Name:
-- Module Name: Oho_Dy1 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 1.00 - File Created
-- Revision 1.01 - Brightness support
-- Revision 1.02 - Added display test
-- Revision 1.03 - display update support, new interface signal names
-- Additional Comments:
-- Dispay module OHO_DY1 core
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all ;
use work.OhoPack.all ;
entity Oho_Dy1 is
Port (
dy_clock: in std_logic ;
dy_rst_n: in std_logic ;
dy_data: in y2d_type ;
dy_update: in std_logic ;
dy_frame: out std_logic ;
dy_frameend: out std_logic ;
dy_frameend_c: out std_logic ;
dy_pwm: in std_logic_vector(3 downto 0) ;
dy_counter: out std_logic_vector(31 downto 0) ;
dy_sclk: out std_logic ;
dy_ser: out std_logic ;
dy_rclk: out std_logic
) ;
end Oho_Dy1 ;
-- display core for OHO_DY1 module
architecture Behavioral of Oho_Dy1 is
signal sclk: std_logic ;
signal ser: std_logic ;
signal rclk: std_logic ;
signal frameend: std_logic ;
signal frameend_q: std_logic ;
signal frameend_c: std_logic ;
signal frame: std_logic ;
signal actualdigit: std_logic_vector (8 downto 0) ;
signal dupcnt: std_logic_vector (11 downto 0) ;
signal displaycounter: std_logic_vector (31 downto 0) ;
begin
-- display up to 15 digits on 5 stacked OHO_DY1 modules
Display_Proc: process(dy_clock,dy_rst_n)
begin
if (dy_rst_n = '0') then
-- init signals on reset
displaycounter <= (others => '0') ;
dupcnt <= (others => '0') ;
frame <= '0' ;
frameend <= '1' ;
frameend_q <= '1' ;
frameend_c <= '0' ;
sclk <= '0' ;
ser <= '0' ;
rclk <= '1' ;
elsif rising_edge(dy_clock) then
-- use a free running binary counter as a timing source
displaycounter <= std_logic_vector(unsigned(displaycounter) + 1) ;
-- start of display frame
-- generate frame and rising edge of rclk
if (displaycounter(15 downto 0) = X"0000") then
-- decrease display update counter dupcnt
if (dupcnt /= X"000") then
dupcnt <= std_logic_vector(unsigned(dupcnt) - 1) ;
frame <= '1' ; -- indicate start of display frame
frameend <= '0' ; -- inactivate frameend
else
frame <= '0' ; -- indicate end of sclk/ser, rclk still active
end if ;
-- generate rclk rising edge
if (frame = '1') then
rclk <= '1' ;
end if ;
else
-- remaining display frame
if (frame = '0') then
-- display frame end, set rclk low on next sclk rising
if (displaycounter(8) = '1') then
rclk <= '0' ;
frameend <= '1' ;
end if ;
else
-- display frame continues with PWM brightness control
if (displaycounter(15 downto 12) = not dy_pwm) and (displaycounter(8) = '1') then
rclk <= '0' ;
end if ;
end if ;
end if ;
-- setup display update counter (must be after dupcnt-1 statement)
if (dy_update = '1') then -- display update
dupcnt <= DupVal ;
end if ;
-- use dy_clock/256 as shift register clock
sclk <= frame and displaycounter(8) ;
-- feed display data from function SerialHexDecode in OhoPack.vhd
ser <= frame and not SerialHexDecode(displaycounter(11 downto 9),actualdigit) ;
-- digit data 16:1 mux
case displaycounter(15 downto 12) is
-- first shift out 16. digit, normally not used
when "0000" => actualdigit <= "000000000" ; -- blank
-- 15. digit is on the 5.th stacked module on the left side
when "0001" => actualdigit <= dy_data(14) ;
-- 14. digit is on the 5.th stacked module in the middle
when "0010" => actualdigit <= dy_data(13) ;
-- 13. digit is on the 5.th stacked module on the right side
when "0011" => actualdigit <= dy_data(12) ;
when "0100" => actualdigit <= dy_data(11) ;
when "0101" => actualdigit <= dy_data(10) ;
when "0110" => actualdigit <= dy_data(9) ;
when "0111" => actualdigit <= dy_data(8) ;
when "1000" => actualdigit <= dy_data(7) ;
when "1001" => actualdigit <= dy_data(6) ;
when "1010" => actualdigit <= dy_data(5) ;
when "1011" => actualdigit <= dy_data(4) ;
when "1100" => actualdigit <= dy_data(3) ;
when "1101" => actualdigit <= dy_data(2) ;
when "1110" => actualdigit <= dy_data(1) ;
-- first digit on the first module on the right side
when "1111" => actualdigit <= dy_data(0) ;
when others =>
end case ;
-- generate single frameend clock pulse
frameend_q <= frameend ;
if Rise(frameend,frameend_q) then
frameend_c <= '1' ;
else
frameend_c <= '0' ;
end if ;
-- use output registers for the display signals
dy_sclk <= sclk ;
dy_ser <= ser ;
dy_rclk <= rclk ;
end if ;
end process ;
-- making internal signals externally available
dy_counter <= displaycounter ;
dy_frame <= frame ;
dy_frameend <= frameend_q ;
dy_frameend_c <= frameend_c ;
end Behavioral;
| gpl-3.0 |
fbelavenuto/msx1fpga | src/audio/vm2413/operator.vhd | 2 | 5318 | --
-- Operator.vhd
--
-- Copyright (c) 2006 Mitsutaka Okazaki ([email protected])
-- All rights reserved.
--
-- Redistribution and use of this source code or any derivative works, are
-- permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
-- 3. Redistributions may not be sold, nor may they be used in a commercial
-- product or activity without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
-- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
-- CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-- EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-- PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
-- OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-- WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
-- OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
--
-- modified by t.hara
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use work.vm2413.all;
entity Operator is
port (
clk : in std_logic;
reset : in std_logic;
clkena : in std_logic;
slot : in std_logic_vector( 4 downto 0 );
stage : in std_logic_vector( 1 downto 0 );
rhythm : in std_logic;
WF : in std_logic;
FB : in std_logic_vector(2 downto 0);
noise : in std_logic;
pgout : in std_logic_vector( 17 downto 0 ); -- 9bit, 9bit
egout : in std_logic_vector( 12 downto 0 );
faddr : out integer range 0 to 9-1;
fdata : in SIGNED_LI_TYPE;
opout : out std_logic_vector( 13 downto 0 ) -- 8bit, 6bit
);
end entity;
architecture rtl of Operator is
signal addr : std_logic_vector( 17 downto 0 );
signal data : std_logic_vector( 13 downto 0 );
signal w_is_carrier : std_logic;
signal w_modula_m : std_logic_vector( LI_TYPE'high + 2 + 9 downto 0 );
signal w_modula_c : std_logic_vector( LI_TYPE'high + 2 + 9 downto 0 );
signal w_modula : std_logic_vector( LI_TYPE'high + 2 + 9 downto 0 );
signal ff_egout : std_logic_vector( 12 downto 0 );
begin
-- TCgiÎ\»j--------------------------------------------------
-- addr wèµ½XTCNÉ data ªoÄé
--
-- stage X 00 X 01 X 10 X 11 X 00
-- addr X mè
-- data X mè
-- opout X mè
--
u_sine_table : entity work.SineTable
port map(
clk => clk,
clkena => clkena,
wf => wf,
addr => addr,
data => data
);
w_is_carrier <= slot(0);
w_modula_m <= (others => '0') when( fb = "000" )else
shr( '0' & fdata.value & '0' & "000000000", "111" xor fb );
w_modula_c <= fdata.value & "00" & "000000000";
w_modula <= w_modula_c when( w_is_carrier = '1' )else
w_modula_m;
process( reset, clk )
variable opout_buf : std_logic_vector( 13 downto 0 ); -- ® 8bit, ¬ 6bit
begin
if( reset = '1' )then
opout <= (others => '0');
ff_egout <= (others => '0');
elsif( clk'event and clk='1' )then
if( clkena = '1' )then
if( stage = "00" )then
-- TCgÌQÆAhXiÊjðè·éXe[W
if( rhythm = '1' and ( slot = 14 or slot = 17 ))then -- HH or CYM
addr <= (not noise) & "01111111" & "000000000";
elsif( rhythm = '1' and slot = 15 )then -- SD
addr <= (not pgout(pgout'high)) & "01111111" & "000000000";
elsif( rhythm = '1' and slot = 16 )then -- TOM
addr <= pgout;
else
if( fdata.sign = '0' )then -- modula Í fdata ÌâÎlðVtgµ½l¾©çA±±ÅµÄé
addr <= pgout + w_modula(pgout'range);
else
addr <= pgout - w_modula(pgout'range);
end if;
end if;
elsif( stage = "01" )then
-- è³ê½QÆAhXª u_sine_table Ö³êéXe[W
elsif( stage = "10" )then
ff_egout <= egout;
-- tB[hobNÌAhXðßéXe[W
if( slot(0) = '1' )then
if( conv_integer(slot)/2 = 8 )then
faddr <= 0;
else
faddr <= conv_integer(slot)/2 + 1; -- ÌW
[^ÌAhXÈÌÅ +1
end if;
end if;
elsif( stage = "11" )then
-- SineTable ©çf[^ªoÄéXe[W
if ( ( '0' & ff_egout ) + ('0'& data(12 downto 0) ) ) < "10000000000000" then
opout_buf := data(13) & (ff_egout + data(12 downto 0) );
else
opout_buf := data(13) & "1111111111111";
end if;
opout <= opout_buf;
-- è³ê½tB[hobNAhXª FeedBackMemory Ö³êéXe[W
end if;
end if;
end if;
end process;
end architecture;
| gpl-3.0 |
hoglet67/AtomBusMon | src/AVR8/JTAG_OCD_Prg/JTAGPack.vhd | 4 | 3224 | --**********************************************************************************************
-- Constants for OCD and "Flash" controller for AVR Core
-- Version 0.31
-- Modified 04.06.2004
-- Designed by Ruslan Lepetenok
--**********************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
package JTAGPack is
constant CInstrLength : positive := 4;
-- JTAG instructions
constant C_BYPASS : std_logic_vector(CInstrLength-1 downto 0) := x"F";
constant C_SAMPLE_PRELOAD : std_logic_vector(CInstrLength-1 downto 0) := x"2";
constant C_EXTEST : std_logic_vector(CInstrLength-1 downto 0) := x"0";
constant C_IDCODE : std_logic_vector(CInstrLength-1 downto 0) := x"1";
constant C_AVR_RESET : std_logic_vector(CInstrLength-1 downto 0) := x"C";
-- Program
constant C_PROG_ENABLE : std_logic_vector(CInstrLength-1 downto 0) := x"4";
constant C_PROG_COMMANDS : std_logic_vector(CInstrLength-1 downto 0) := x"5";
constant C_PROG_PAGELOAD : std_logic_vector(CInstrLength-1 downto 0) := x"6";
constant C_PROG_PAGEREAD : std_logic_vector(CInstrLength-1 downto 0) := x"7";
-- OCD (Private)
constant C_FORCE_BREAK : std_logic_vector(CInstrLength-1 downto 0) := x"8";
constant C_RUN : std_logic_vector(CInstrLength-1 downto 0) := x"9";
constant C_EX_INST : std_logic_vector(CInstrLength-1 downto 0) := x"A";
constant C_OCD_ACCESS : std_logic_vector(CInstrLength-1 downto 0) := x"B";
constant C_UNUSED_3 : std_logic_vector(CInstrLength-1 downto 0) := x"3";
constant C_UNUSED_D : std_logic_vector(CInstrLength-1 downto 0) := x"D";
constant C_UNUSED_E : std_logic_vector(CInstrLength-1 downto 0) := x"E";
constant CInitInstrRegVal : std_logic_vector(CInstrLength-1 downto 0) := C_IDCODE; -- May be C_IDCODE or C_BYPASS
-- IDCODE register fields
--constant CVersion : std_logic_vector(3 downto 0) := x"E"; -- Version Number (ATmega16)
--constant CPartNumber : std_logic_vector(15 downto 0) := x"9403"; -- Part Number (ATmega16)
constant CVersion : std_logic_vector(3 downto 0) := x"6"; -- Version Number (ATmega128)
constant CPartNumber : std_logic_vector(15 downto 0) := x"9702"; -- Part Number (ATmega128)
constant CManufacturerId : std_logic_vector(10 downto 0) := "000"&x"1F"; -- Manufacturer ID(Atmel)
constant C_ProgEnableVect : std_logic_vector(15 downto 0) := x"A370";
-- OCD register addresses
constant C_OCDPSB0Adr : std_logic_vector(3 downto 0) := x"0";
constant C_OCDPSB1Adr : std_logic_vector(3 downto 0) := x"1";
constant C_OCDPDMSBAdr : std_logic_vector(3 downto 0) := x"2";
constant C_OCDPDSBAdr : std_logic_vector(3 downto 0) := x"3";
constant C_OCDBCRAdr : std_logic_vector(3 downto 0) := x"8";
constant C_OCDBSRAdr : std_logic_vector(3 downto 0) := x"9";
constant C_OCDOCDRAdr : std_logic_vector(3 downto 0) := x"C";
constant C_OCDCSRAdr : std_logic_vector(3 downto 0) := x"D";
constant C_AVRBreakInst : std_logic_vector(15 downto 0) := x"9598";
constant C_MaxEraseAdr : std_logic_vector(15 downto 0) := x"FFFF";
end JTAGPack;
| gpl-3.0 |
fbelavenuto/msx1fpga | src/audio/vm2413/outputmemory.vhd | 2 | 2982 | --
-- OutputMemory.vhd
--
-- Copyright (c) 2006 Mitsutaka Okazaki ([email protected])
-- All rights reserved.
--
-- Redistribution and use of this source code or any derivative works, are
-- permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
-- 3. Redistributions may not be sold, nor may they be used in a commercial
-- product or activity without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
-- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
-- CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-- EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-- PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
-- OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-- WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
-- OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use work.vm2413.all;
entity OutputMemory is
port (
clk : in std_logic;
reset : in std_logic;
wr : in std_logic;
addr : in std_logic_vector( 4 downto 0 );
wdata : in SIGNED_LI_TYPE;
rdata : out SIGNED_LI_TYPE;
addr2 : in std_logic_vector( 4 downto 0 );
rdata2 : out SIGNED_LI_TYPE
);
end entity;
architecture RTL of OutputMemory is
type SIGNED_LI_ARRAY_TYPE is array (0 to 18) of SIGNED_LI_VECTOR_TYPE;
signal data_array : SIGNED_LI_ARRAY_TYPE;
signal init_ch : integer range 0 to 18;
signal mem_wr_s : std_logic;
signal mem_addr_s : integer;
signal mem_data_s : SIGNED_LI_VECTOR_TYPE;
attribute ram_style : string;
attribute ram_style of data_array : signal is "block";
begin
mem_wr_s <= '1' when init_ch /= 18 else wr;
mem_addr_s <= init_ch when init_ch /= 18 else conv_integer(addr);
mem_data_s <= (others => '0') when init_ch /= 18 else CONV_SIGNED_LI_VECTOR(wdata);
process(clk, reset)
begin
if (reset = '1') then
init_ch <= 0;
elsif clk'event and clk='1' then
if mem_wr_s = '1' then
data_array(mem_addr_s) <= mem_data_s;
end if;
rdata <= CONV_SIGNED_LI(data_array(conv_integer(addr)));
rdata2 <= CONV_SIGNED_LI(data_array(conv_integer(addr2)));
if init_ch /= 18 then
init_ch <= init_ch + 1;
end if;
end if;
end process;
end architecture; | gpl-3.0 |
fbelavenuto/msx1fpga | src/peripheral/memoryctl.vhd | 2 | 8549 | -------------------------------------------------------------------------------
--
-- MSX1 FPGA project
--
-- Copyright (c) 2016, Fabio Belavenuto ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity memoryctl is
generic (
ramsize_g : integer := 512 -- 512, 2048 or 8192
);
port (
cpu_addr_i : in std_logic_vector(15 downto 0);
use_rom_in_ram_i : in std_logic;
--
rom_cs_i : in std_logic;
extrom_cs_i : in std_logic;
xb2rom_cs_i : in std_logic;
nxt_rom_cs_i : in std_logic;
nxt_rom_page_i : in std_logic_vector( 2 downto 0);
ipl_cs_i : in std_logic;
ipl_rampage_i : in std_logic_vector( 8 downto 0);
mr_ram_cs_i : in std_logic;
mr_ram_addr_i : in std_logic_vector(19 downto 0); -- 1MB
ram_cs_i : in std_logic;
ram_page_i : in std_logic_vector( 7 downto 0);
--
ram_addr_o : out std_logic_vector(22 downto 0); -- Max 8MB
mapper_mask_o : out std_logic_vector( 7 downto 0)
);
end entity;
architecture Behavior of memoryctl is
begin
m512: if ramsize_g = 512 generate
-- RAM map
-- Address Range System Size A22-A14 IPL Pages range
-- 00 0000-01 FFFF NEXTOR 128K 0000 00xxx 000-007
-- 02 0000-03 FFFF Mapper RAM 128K 0000 01xxx 008-00F
-- 04 0000-07 FFFF SCC/Megaram 256K 0000 1xxxx 010-01F
-- OR
-- 04 0000-05 FFFF SCC/Megaram 128K 0000 10xxx 020-023
-- 06 0000-07 7FFF (empty) 96K 0000 11... 024-029
-- 07 8000-07 FFFF ROM 32K 0000 1111x 01E-01F
process (nxt_rom_cs_i, ipl_cs_i, cpu_addr_i, nxt_rom_page_i,
ram_page_i, ipl_rampage_i, ram_cs_i, mr_ram_addr_i,
use_rom_in_ram_i, mr_ram_cs_i, rom_cs_i)
begin
ram_addr_o <= (others => '0');
if nxt_rom_cs_i = '1' then -- Nextor
ram_addr_o <= "000000" & nxt_rom_page_i & cpu_addr_i(13 downto 0);
elsif ipl_cs_i = '1' and cpu_addr_i(15 downto 14) = "01" then -- RAM 16K (IPL) ($4000-$7FFF)
ram_addr_o <= "000001111" & cpu_addr_i(13 downto 0);
elsif ipl_cs_i = '1' and cpu_addr_i(15) = '1' then -- All RAM (IPL) ($8000-$FFFF)
ram_addr_o <= "0000" & ipl_rampage_i(4 downto 0) & cpu_addr_i(13 downto 0);
elsif mr_ram_cs_i = '1' then -- SCC/Megaram (only 128 or 256K)
if use_rom_in_ram_i = '1' then
ram_addr_o <= "000010" & mr_ram_addr_i(16 downto 0);
else
ram_addr_o <= "00001" & mr_ram_addr_i(17 downto 0);
end if;
elsif rom_cs_i = '1' and use_rom_in_ram_i = '1' then -- ROM
ram_addr_o <= "00001111" & cpu_addr_i(14 downto 0);
elsif ram_cs_i = '1' then -- Mapper (only 128K)
ram_addr_o <= "000001" & ram_page_i(2 downto 0) & cpu_addr_i(13 downto 0);
else
null;
end if;
end process;
mapper_mask_o <= "00000111"; -- 128K
end generate;
m2M: if ramsize_g = 2048 generate
-- RAM map
-- Address Range System Size A22-A14 IPL Pages range
-- 00 0000-00 7FFF ROM BIOS 32K 00 000000x 000-001
-- 00 8000-00 BFFF EXT ROM 16K 00 0000010 002-002
-- 00 C000-00 FFFF XBASIC2 ROM 16K 00 0000011 003-003
-- 01 0000-01 FFFF (empty) 64K 00 00001xx 004-007
-- 02 0000-03 FFFF Nextor ROM 128K 00 0001xxx 008-00F
-- 04 0000-07 FFFF (empty) 256K 00 001xxxx 010-01F
-- 08 0000-0F FFFF ESCCI 512K 00 01xxxxx 020-03F
-- 10 0000-1F FFFF RAM Mapper 1MB 00 1xxxxxx 040-07F
process (nxt_rom_cs_i, ipl_cs_i, cpu_addr_i, nxt_rom_page_i,
ram_page_i, ipl_rampage_i, ram_cs_i, mr_ram_addr_i,
use_rom_in_ram_i, mr_ram_cs_i, rom_cs_i, extrom_cs_i,
xb2rom_cs_i)
begin
ram_addr_o <= (others => '0');
if rom_cs_i = '1' then -- ROM
ram_addr_o <= "00000000" & cpu_addr_i(14 downto 0);
elsif extrom_cs_i = '1' then -- Extension ROM
ram_addr_o <= "000000010" & cpu_addr_i(13 downto 0);
elsif xb2rom_cs_i = '1' then -- XBASIC2 ROM
ram_addr_o <= "000000011" & cpu_addr_i(13 downto 0);
elsif nxt_rom_cs_i = '1' then -- Nextor
ram_addr_o <= "000001" & nxt_rom_page_i & cpu_addr_i(13 downto 0);
elsif mr_ram_cs_i = '1' then -- SCC/Megaram (only 512K)
ram_addr_o <= "0001" & mr_ram_addr_i(18 downto 0);
elsif ram_cs_i = '1' then -- Mapper (only 1MB)
ram_addr_o <= "001" & ram_page_i(5 downto 0) & cpu_addr_i(13 downto 0);
elsif ipl_cs_i = '1' and cpu_addr_i(15 downto 14) = "01" then -- RAM 16K (IPL) ($4000-$7FFF)
ram_addr_o <= "001111111" & cpu_addr_i(13 downto 0);
elsif ipl_cs_i = '1' and cpu_addr_i(15) = '1' then -- All RAM (IPL) ($8000-$FFFF)
ram_addr_o <= "00" & ipl_rampage_i(6 downto 0) & cpu_addr_i(13 downto 0);
else
null;
end if;
end process;
mapper_mask_o <= "00111111"; -- 1MB
end generate;
m8M: if ramsize_g = 8192 generate
-- RAM map
-- Address Range System Size A22-A14 IPL Pages range
-- 00 0000-00 7FFF ROM BIOS 32K 00 000000x 000-001
-- 00 8000-00 BFFF EXT ROM 16K 00 0000010 002-002
-- 00 C000-00 FFFF XBASIC2 ROM 16K 00 0000011 003-003
-- 01 0000-01 FFFF (empty) 64K 00 00001xx 004-007
-- 02 0000-03 FFFF Nextor ROM 128K 00 0001xxx 008-00F
-- 04 0000-07 FFFF (empty) 256K 00 001xxxx 010-01F
-- 08 0000-0F FFFF (empty) 512K 00 01xxxxx 020-03F
-- 10 0000-1F FFFF ESCCI 1MB 00 1xxxxxx 040-07F
-- 20 0000-3F FFFF (empty) 2MB 01 xxxxxxx 080-0FF
-- 40 0000-7F FFFF RAM Mapper 4MB 1x xxxxxxx 100-1FF
process (nxt_rom_cs_i, ipl_cs_i, cpu_addr_i, nxt_rom_page_i,
ram_page_i, ipl_rampage_i, ram_cs_i, mr_ram_addr_i,
mr_ram_cs_i, rom_cs_i, extrom_cs_i, xb2rom_cs_i)
begin
ram_addr_o <= (others => '0');
if rom_cs_i = '1' then -- ROM
ram_addr_o <= "00000000" & cpu_addr_i(14 downto 0);
elsif extrom_cs_i = '1' then -- Extension ROM
ram_addr_o <= "000000010" & cpu_addr_i(13 downto 0);
elsif xb2rom_cs_i = '1' then -- XBASIC2 ROM
ram_addr_o <= "000000011" & cpu_addr_i(13 downto 0);
elsif nxt_rom_cs_i = '1' then -- Nextor
ram_addr_o <= "000001" & nxt_rom_page_i & cpu_addr_i(13 downto 0);
elsif mr_ram_cs_i = '1' then -- SCC/Megaram
ram_addr_o <= "001" & mr_ram_addr_i;
elsif ram_cs_i = '1' then -- Mapper
ram_addr_o <= "1" & ram_page_i & cpu_addr_i(13 downto 0);
elsif ipl_cs_i = '1' and cpu_addr_i(15 downto 14) = "01" then -- RAM 16K (IPL) ($4000-$7FFF)
ram_addr_o <= "111111111" & cpu_addr_i(13 downto 0);
elsif ipl_cs_i = '1' and cpu_addr_i(15) = '1' then -- All RAM (IPL) ($8000-$FFFF)
ram_addr_o <= ipl_rampage_i & cpu_addr_i(13 downto 0);
else
null;
end if;
end process;
mapper_mask_o <= "11111111"; -- 4MB
end generate;
end architecture;
| gpl-3.0 |
sukinull/vivado_zed_pieces | axigpio_w_linux_uio/project_uio/project_uio.srcs/sources_1/bd/base_zynq_design/hdl/base_zynq_design.vhd | 1 | 150913 | --Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2014.4 (lin64) Build 1071353 Tue Nov 18 16:47:07 MST 2014
--Date : Wed Aug 26 21:30:37 2015
--Host : localhost.localdomain running 64-bit CentOS release 6.7 (Final)
--Command : generate_target base_zynq_design.bd
--Design : base_zynq_design
--Purpose : IP block netlist
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity m00_couplers_imp_1R5MXF4 is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_araddr : out STD_LOGIC_VECTOR ( 8 downto 0 );
M_AXI_arready : in STD_LOGIC;
M_AXI_arvalid : out STD_LOGIC;
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 8 downto 0 );
M_AXI_awready : in STD_LOGIC;
M_AXI_awvalid : out STD_LOGIC;
M_AXI_bready : out STD_LOGIC;
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC;
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC;
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arready : out STD_LOGIC;
S_AXI_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arvalid : in STD_LOGIC;
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awready : out STD_LOGIC;
S_AXI_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awvalid : in STD_LOGIC;
S_AXI_bready : in STD_LOGIC;
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC;
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rlast : out STD_LOGIC;
S_AXI_rready : in STD_LOGIC;
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC;
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wlast : in STD_LOGIC;
S_AXI_wready : out STD_LOGIC;
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC
);
end m00_couplers_imp_1R5MXF4;
architecture STRUCTURE of m00_couplers_imp_1R5MXF4 is
component base_zynq_design_auto_pc_0 is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
end component base_zynq_design_auto_pc_0;
signal S_ACLK_1 : STD_LOGIC;
signal S_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal auto_pc_to_m00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_m00_couplers_ARREADY : STD_LOGIC;
signal auto_pc_to_m00_couplers_ARVALID : STD_LOGIC;
signal auto_pc_to_m00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_m00_couplers_AWREADY : STD_LOGIC;
signal auto_pc_to_m00_couplers_AWVALID : STD_LOGIC;
signal auto_pc_to_m00_couplers_BREADY : STD_LOGIC;
signal auto_pc_to_m00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_pc_to_m00_couplers_BVALID : STD_LOGIC;
signal auto_pc_to_m00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_m00_couplers_RREADY : STD_LOGIC;
signal auto_pc_to_m00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_pc_to_m00_couplers_RVALID : STD_LOGIC;
signal auto_pc_to_m00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_m00_couplers_WREADY : STD_LOGIC;
signal auto_pc_to_m00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_pc_to_m00_couplers_WVALID : STD_LOGIC;
signal m00_couplers_to_auto_pc_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_auto_pc_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_auto_pc_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_auto_pc_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal m00_couplers_to_auto_pc_ARLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_auto_pc_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_auto_pc_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_auto_pc_ARREADY : STD_LOGIC;
signal m00_couplers_to_auto_pc_ARREGION : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_auto_pc_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_auto_pc_ARVALID : STD_LOGIC;
signal m00_couplers_to_auto_pc_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_auto_pc_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_auto_pc_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_auto_pc_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal m00_couplers_to_auto_pc_AWLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_auto_pc_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_auto_pc_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_auto_pc_AWREADY : STD_LOGIC;
signal m00_couplers_to_auto_pc_AWREGION : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_auto_pc_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_auto_pc_AWVALID : STD_LOGIC;
signal m00_couplers_to_auto_pc_BREADY : STD_LOGIC;
signal m00_couplers_to_auto_pc_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_auto_pc_BVALID : STD_LOGIC;
signal m00_couplers_to_auto_pc_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_auto_pc_RLAST : STD_LOGIC;
signal m00_couplers_to_auto_pc_RREADY : STD_LOGIC;
signal m00_couplers_to_auto_pc_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_auto_pc_RVALID : STD_LOGIC;
signal m00_couplers_to_auto_pc_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_auto_pc_WLAST : STD_LOGIC;
signal m00_couplers_to_auto_pc_WREADY : STD_LOGIC;
signal m00_couplers_to_auto_pc_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_auto_pc_WVALID : STD_LOGIC;
signal NLW_auto_pc_m_axi_arprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_auto_pc_m_axi_awprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
begin
M_AXI_araddr(8 downto 0) <= auto_pc_to_m00_couplers_ARADDR(8 downto 0);
M_AXI_arvalid <= auto_pc_to_m00_couplers_ARVALID;
M_AXI_awaddr(8 downto 0) <= auto_pc_to_m00_couplers_AWADDR(8 downto 0);
M_AXI_awvalid <= auto_pc_to_m00_couplers_AWVALID;
M_AXI_bready <= auto_pc_to_m00_couplers_BREADY;
M_AXI_rready <= auto_pc_to_m00_couplers_RREADY;
M_AXI_wdata(31 downto 0) <= auto_pc_to_m00_couplers_WDATA(31 downto 0);
M_AXI_wstrb(3 downto 0) <= auto_pc_to_m00_couplers_WSTRB(3 downto 0);
M_AXI_wvalid <= auto_pc_to_m00_couplers_WVALID;
S_ACLK_1 <= S_ACLK;
S_ARESETN_1(0) <= S_ARESETN(0);
S_AXI_arready <= m00_couplers_to_auto_pc_ARREADY;
S_AXI_awready <= m00_couplers_to_auto_pc_AWREADY;
S_AXI_bresp(1 downto 0) <= m00_couplers_to_auto_pc_BRESP(1 downto 0);
S_AXI_bvalid <= m00_couplers_to_auto_pc_BVALID;
S_AXI_rdata(31 downto 0) <= m00_couplers_to_auto_pc_RDATA(31 downto 0);
S_AXI_rlast <= m00_couplers_to_auto_pc_RLAST;
S_AXI_rresp(1 downto 0) <= m00_couplers_to_auto_pc_RRESP(1 downto 0);
S_AXI_rvalid <= m00_couplers_to_auto_pc_RVALID;
S_AXI_wready <= m00_couplers_to_auto_pc_WREADY;
auto_pc_to_m00_couplers_ARREADY <= M_AXI_arready;
auto_pc_to_m00_couplers_AWREADY <= M_AXI_awready;
auto_pc_to_m00_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
auto_pc_to_m00_couplers_BVALID <= M_AXI_bvalid;
auto_pc_to_m00_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
auto_pc_to_m00_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
auto_pc_to_m00_couplers_RVALID <= M_AXI_rvalid;
auto_pc_to_m00_couplers_WREADY <= M_AXI_wready;
m00_couplers_to_auto_pc_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
m00_couplers_to_auto_pc_ARBURST(1 downto 0) <= S_AXI_arburst(1 downto 0);
m00_couplers_to_auto_pc_ARCACHE(3 downto 0) <= S_AXI_arcache(3 downto 0);
m00_couplers_to_auto_pc_ARLEN(7 downto 0) <= S_AXI_arlen(7 downto 0);
m00_couplers_to_auto_pc_ARLOCK(0) <= S_AXI_arlock(0);
m00_couplers_to_auto_pc_ARPROT(2 downto 0) <= S_AXI_arprot(2 downto 0);
m00_couplers_to_auto_pc_ARQOS(3 downto 0) <= S_AXI_arqos(3 downto 0);
m00_couplers_to_auto_pc_ARREGION(3 downto 0) <= S_AXI_arregion(3 downto 0);
m00_couplers_to_auto_pc_ARSIZE(2 downto 0) <= S_AXI_arsize(2 downto 0);
m00_couplers_to_auto_pc_ARVALID <= S_AXI_arvalid;
m00_couplers_to_auto_pc_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
m00_couplers_to_auto_pc_AWBURST(1 downto 0) <= S_AXI_awburst(1 downto 0);
m00_couplers_to_auto_pc_AWCACHE(3 downto 0) <= S_AXI_awcache(3 downto 0);
m00_couplers_to_auto_pc_AWLEN(7 downto 0) <= S_AXI_awlen(7 downto 0);
m00_couplers_to_auto_pc_AWLOCK(0) <= S_AXI_awlock(0);
m00_couplers_to_auto_pc_AWPROT(2 downto 0) <= S_AXI_awprot(2 downto 0);
m00_couplers_to_auto_pc_AWQOS(3 downto 0) <= S_AXI_awqos(3 downto 0);
m00_couplers_to_auto_pc_AWREGION(3 downto 0) <= S_AXI_awregion(3 downto 0);
m00_couplers_to_auto_pc_AWSIZE(2 downto 0) <= S_AXI_awsize(2 downto 0);
m00_couplers_to_auto_pc_AWVALID <= S_AXI_awvalid;
m00_couplers_to_auto_pc_BREADY <= S_AXI_bready;
m00_couplers_to_auto_pc_RREADY <= S_AXI_rready;
m00_couplers_to_auto_pc_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
m00_couplers_to_auto_pc_WLAST <= S_AXI_wlast;
m00_couplers_to_auto_pc_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
m00_couplers_to_auto_pc_WVALID <= S_AXI_wvalid;
auto_pc: component base_zynq_design_auto_pc_0
port map (
aclk => S_ACLK_1,
aresetn => S_ARESETN_1(0),
m_axi_araddr(31 downto 0) => auto_pc_to_m00_couplers_ARADDR(31 downto 0),
m_axi_arprot(2 downto 0) => NLW_auto_pc_m_axi_arprot_UNCONNECTED(2 downto 0),
m_axi_arready => auto_pc_to_m00_couplers_ARREADY,
m_axi_arvalid => auto_pc_to_m00_couplers_ARVALID,
m_axi_awaddr(31 downto 0) => auto_pc_to_m00_couplers_AWADDR(31 downto 0),
m_axi_awprot(2 downto 0) => NLW_auto_pc_m_axi_awprot_UNCONNECTED(2 downto 0),
m_axi_awready => auto_pc_to_m00_couplers_AWREADY,
m_axi_awvalid => auto_pc_to_m00_couplers_AWVALID,
m_axi_bready => auto_pc_to_m00_couplers_BREADY,
m_axi_bresp(1 downto 0) => auto_pc_to_m00_couplers_BRESP(1 downto 0),
m_axi_bvalid => auto_pc_to_m00_couplers_BVALID,
m_axi_rdata(31 downto 0) => auto_pc_to_m00_couplers_RDATA(31 downto 0),
m_axi_rready => auto_pc_to_m00_couplers_RREADY,
m_axi_rresp(1 downto 0) => auto_pc_to_m00_couplers_RRESP(1 downto 0),
m_axi_rvalid => auto_pc_to_m00_couplers_RVALID,
m_axi_wdata(31 downto 0) => auto_pc_to_m00_couplers_WDATA(31 downto 0),
m_axi_wready => auto_pc_to_m00_couplers_WREADY,
m_axi_wstrb(3 downto 0) => auto_pc_to_m00_couplers_WSTRB(3 downto 0),
m_axi_wvalid => auto_pc_to_m00_couplers_WVALID,
s_axi_araddr(31 downto 0) => m00_couplers_to_auto_pc_ARADDR(31 downto 0),
s_axi_arburst(1 downto 0) => m00_couplers_to_auto_pc_ARBURST(1 downto 0),
s_axi_arcache(3 downto 0) => m00_couplers_to_auto_pc_ARCACHE(3 downto 0),
s_axi_arlen(7 downto 0) => m00_couplers_to_auto_pc_ARLEN(7 downto 0),
s_axi_arlock(0) => m00_couplers_to_auto_pc_ARLOCK(0),
s_axi_arprot(2 downto 0) => m00_couplers_to_auto_pc_ARPROT(2 downto 0),
s_axi_arqos(3 downto 0) => m00_couplers_to_auto_pc_ARQOS(3 downto 0),
s_axi_arready => m00_couplers_to_auto_pc_ARREADY,
s_axi_arregion(3 downto 0) => m00_couplers_to_auto_pc_ARREGION(3 downto 0),
s_axi_arsize(2 downto 0) => m00_couplers_to_auto_pc_ARSIZE(2 downto 0),
s_axi_arvalid => m00_couplers_to_auto_pc_ARVALID,
s_axi_awaddr(31 downto 0) => m00_couplers_to_auto_pc_AWADDR(31 downto 0),
s_axi_awburst(1 downto 0) => m00_couplers_to_auto_pc_AWBURST(1 downto 0),
s_axi_awcache(3 downto 0) => m00_couplers_to_auto_pc_AWCACHE(3 downto 0),
s_axi_awlen(7 downto 0) => m00_couplers_to_auto_pc_AWLEN(7 downto 0),
s_axi_awlock(0) => m00_couplers_to_auto_pc_AWLOCK(0),
s_axi_awprot(2 downto 0) => m00_couplers_to_auto_pc_AWPROT(2 downto 0),
s_axi_awqos(3 downto 0) => m00_couplers_to_auto_pc_AWQOS(3 downto 0),
s_axi_awready => m00_couplers_to_auto_pc_AWREADY,
s_axi_awregion(3 downto 0) => m00_couplers_to_auto_pc_AWREGION(3 downto 0),
s_axi_awsize(2 downto 0) => m00_couplers_to_auto_pc_AWSIZE(2 downto 0),
s_axi_awvalid => m00_couplers_to_auto_pc_AWVALID,
s_axi_bready => m00_couplers_to_auto_pc_BREADY,
s_axi_bresp(1 downto 0) => m00_couplers_to_auto_pc_BRESP(1 downto 0),
s_axi_bvalid => m00_couplers_to_auto_pc_BVALID,
s_axi_rdata(31 downto 0) => m00_couplers_to_auto_pc_RDATA(31 downto 0),
s_axi_rlast => m00_couplers_to_auto_pc_RLAST,
s_axi_rready => m00_couplers_to_auto_pc_RREADY,
s_axi_rresp(1 downto 0) => m00_couplers_to_auto_pc_RRESP(1 downto 0),
s_axi_rvalid => m00_couplers_to_auto_pc_RVALID,
s_axi_wdata(31 downto 0) => m00_couplers_to_auto_pc_WDATA(31 downto 0),
s_axi_wlast => m00_couplers_to_auto_pc_WLAST,
s_axi_wready => m00_couplers_to_auto_pc_WREADY,
s_axi_wstrb(3 downto 0) => m00_couplers_to_auto_pc_WSTRB(3 downto 0),
s_axi_wvalid => m00_couplers_to_auto_pc_WVALID
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity m01_couplers_imp_19312F is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_araddr : out STD_LOGIC_VECTOR ( 12 downto 0 );
M_AXI_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
M_AXI_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 12 downto 0 );
M_AXI_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
M_AXI_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rlast : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_rready : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wlast : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_araddr : in STD_LOGIC_VECTOR ( 12 downto 0 );
S_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 12 downto 0 );
S_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rlast : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wlast : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end m01_couplers_imp_19312F;
architecture STRUCTURE of m01_couplers_imp_19312F is
signal m01_couplers_to_m01_couplers_ARADDR : STD_LOGIC_VECTOR ( 12 downto 0 );
signal m01_couplers_to_m01_couplers_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m01_couplers_to_m01_couplers_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m01_couplers_to_m01_couplers_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal m01_couplers_to_m01_couplers_ARLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_m01_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m01_couplers_to_m01_couplers_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_m01_couplers_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m01_couplers_to_m01_couplers_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_m01_couplers_AWADDR : STD_LOGIC_VECTOR ( 12 downto 0 );
signal m01_couplers_to_m01_couplers_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m01_couplers_to_m01_couplers_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m01_couplers_to_m01_couplers_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal m01_couplers_to_m01_couplers_AWLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_m01_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m01_couplers_to_m01_couplers_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_m01_couplers_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m01_couplers_to_m01_couplers_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_m01_couplers_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_m01_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m01_couplers_to_m01_couplers_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_m01_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_m01_couplers_RLAST : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_m01_couplers_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_m01_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m01_couplers_to_m01_couplers_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_m01_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_m01_couplers_WLAST : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_m01_couplers_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_m01_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m01_couplers_to_m01_couplers_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
begin
M_AXI_araddr(12 downto 0) <= m01_couplers_to_m01_couplers_ARADDR(12 downto 0);
M_AXI_arburst(1 downto 0) <= m01_couplers_to_m01_couplers_ARBURST(1 downto 0);
M_AXI_arcache(3 downto 0) <= m01_couplers_to_m01_couplers_ARCACHE(3 downto 0);
M_AXI_arlen(7 downto 0) <= m01_couplers_to_m01_couplers_ARLEN(7 downto 0);
M_AXI_arlock(0) <= m01_couplers_to_m01_couplers_ARLOCK(0);
M_AXI_arprot(2 downto 0) <= m01_couplers_to_m01_couplers_ARPROT(2 downto 0);
M_AXI_arsize(2 downto 0) <= m01_couplers_to_m01_couplers_ARSIZE(2 downto 0);
M_AXI_arvalid(0) <= m01_couplers_to_m01_couplers_ARVALID(0);
M_AXI_awaddr(12 downto 0) <= m01_couplers_to_m01_couplers_AWADDR(12 downto 0);
M_AXI_awburst(1 downto 0) <= m01_couplers_to_m01_couplers_AWBURST(1 downto 0);
M_AXI_awcache(3 downto 0) <= m01_couplers_to_m01_couplers_AWCACHE(3 downto 0);
M_AXI_awlen(7 downto 0) <= m01_couplers_to_m01_couplers_AWLEN(7 downto 0);
M_AXI_awlock(0) <= m01_couplers_to_m01_couplers_AWLOCK(0);
M_AXI_awprot(2 downto 0) <= m01_couplers_to_m01_couplers_AWPROT(2 downto 0);
M_AXI_awsize(2 downto 0) <= m01_couplers_to_m01_couplers_AWSIZE(2 downto 0);
M_AXI_awvalid(0) <= m01_couplers_to_m01_couplers_AWVALID(0);
M_AXI_bready(0) <= m01_couplers_to_m01_couplers_BREADY(0);
M_AXI_rready(0) <= m01_couplers_to_m01_couplers_RREADY(0);
M_AXI_wdata(31 downto 0) <= m01_couplers_to_m01_couplers_WDATA(31 downto 0);
M_AXI_wlast(0) <= m01_couplers_to_m01_couplers_WLAST(0);
M_AXI_wstrb(3 downto 0) <= m01_couplers_to_m01_couplers_WSTRB(3 downto 0);
M_AXI_wvalid(0) <= m01_couplers_to_m01_couplers_WVALID(0);
S_AXI_arready(0) <= m01_couplers_to_m01_couplers_ARREADY(0);
S_AXI_awready(0) <= m01_couplers_to_m01_couplers_AWREADY(0);
S_AXI_bresp(1 downto 0) <= m01_couplers_to_m01_couplers_BRESP(1 downto 0);
S_AXI_bvalid(0) <= m01_couplers_to_m01_couplers_BVALID(0);
S_AXI_rdata(31 downto 0) <= m01_couplers_to_m01_couplers_RDATA(31 downto 0);
S_AXI_rlast(0) <= m01_couplers_to_m01_couplers_RLAST(0);
S_AXI_rresp(1 downto 0) <= m01_couplers_to_m01_couplers_RRESP(1 downto 0);
S_AXI_rvalid(0) <= m01_couplers_to_m01_couplers_RVALID(0);
S_AXI_wready(0) <= m01_couplers_to_m01_couplers_WREADY(0);
m01_couplers_to_m01_couplers_ARADDR(12 downto 0) <= S_AXI_araddr(12 downto 0);
m01_couplers_to_m01_couplers_ARBURST(1 downto 0) <= S_AXI_arburst(1 downto 0);
m01_couplers_to_m01_couplers_ARCACHE(3 downto 0) <= S_AXI_arcache(3 downto 0);
m01_couplers_to_m01_couplers_ARLEN(7 downto 0) <= S_AXI_arlen(7 downto 0);
m01_couplers_to_m01_couplers_ARLOCK(0) <= S_AXI_arlock(0);
m01_couplers_to_m01_couplers_ARPROT(2 downto 0) <= S_AXI_arprot(2 downto 0);
m01_couplers_to_m01_couplers_ARREADY(0) <= M_AXI_arready(0);
m01_couplers_to_m01_couplers_ARSIZE(2 downto 0) <= S_AXI_arsize(2 downto 0);
m01_couplers_to_m01_couplers_ARVALID(0) <= S_AXI_arvalid(0);
m01_couplers_to_m01_couplers_AWADDR(12 downto 0) <= S_AXI_awaddr(12 downto 0);
m01_couplers_to_m01_couplers_AWBURST(1 downto 0) <= S_AXI_awburst(1 downto 0);
m01_couplers_to_m01_couplers_AWCACHE(3 downto 0) <= S_AXI_awcache(3 downto 0);
m01_couplers_to_m01_couplers_AWLEN(7 downto 0) <= S_AXI_awlen(7 downto 0);
m01_couplers_to_m01_couplers_AWLOCK(0) <= S_AXI_awlock(0);
m01_couplers_to_m01_couplers_AWPROT(2 downto 0) <= S_AXI_awprot(2 downto 0);
m01_couplers_to_m01_couplers_AWREADY(0) <= M_AXI_awready(0);
m01_couplers_to_m01_couplers_AWSIZE(2 downto 0) <= S_AXI_awsize(2 downto 0);
m01_couplers_to_m01_couplers_AWVALID(0) <= S_AXI_awvalid(0);
m01_couplers_to_m01_couplers_BREADY(0) <= S_AXI_bready(0);
m01_couplers_to_m01_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
m01_couplers_to_m01_couplers_BVALID(0) <= M_AXI_bvalid(0);
m01_couplers_to_m01_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
m01_couplers_to_m01_couplers_RLAST(0) <= M_AXI_rlast(0);
m01_couplers_to_m01_couplers_RREADY(0) <= S_AXI_rready(0);
m01_couplers_to_m01_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
m01_couplers_to_m01_couplers_RVALID(0) <= M_AXI_rvalid(0);
m01_couplers_to_m01_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
m01_couplers_to_m01_couplers_WLAST(0) <= S_AXI_wlast(0);
m01_couplers_to_m01_couplers_WREADY(0) <= M_AXI_wready(0);
m01_couplers_to_m01_couplers_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
m01_couplers_to_m01_couplers_WVALID(0) <= S_AXI_wvalid(0);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity s00_couplers_imp_1UTISAU is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_arid : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
M_AXI_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_arready : in STD_LOGIC;
M_AXI_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arvalid : out STD_LOGIC;
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_awid : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
M_AXI_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_awready : in STD_LOGIC;
M_AXI_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_awvalid : out STD_LOGIC;
M_AXI_bid : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_bready : out STD_LOGIC;
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC;
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rid : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_rlast : in STD_LOGIC;
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wlast : out STD_LOGIC;
M_AXI_wready : in STD_LOGIC;
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S_AXI_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arready : out STD_LOGIC;
S_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arvalid : in STD_LOGIC;
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S_AXI_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awready : out STD_LOGIC;
S_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awvalid : in STD_LOGIC;
S_AXI_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
S_AXI_bready : in STD_LOGIC;
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC;
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
S_AXI_rlast : out STD_LOGIC;
S_AXI_rready : in STD_LOGIC;
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC;
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S_AXI_wlast : in STD_LOGIC;
S_AXI_wready : out STD_LOGIC;
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC
);
end s00_couplers_imp_1UTISAU;
architecture STRUCTURE of s00_couplers_imp_1UTISAU is
component base_zynq_design_auto_pc_1 is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_awid : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wlast : out STD_LOGIC;
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bid : in STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_arid : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
end component base_zynq_design_auto_pc_1;
signal S_ACLK_1 : STD_LOGIC;
signal S_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal auto_pc_to_s00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_s00_couplers_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_pc_to_s00_couplers_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_pc_to_s00_couplers_ARID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal auto_pc_to_s00_couplers_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal auto_pc_to_s00_couplers_ARLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal auto_pc_to_s00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal auto_pc_to_s00_couplers_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_pc_to_s00_couplers_ARREADY : STD_LOGIC;
signal auto_pc_to_s00_couplers_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal auto_pc_to_s00_couplers_ARVALID : STD_LOGIC;
signal auto_pc_to_s00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_s00_couplers_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_pc_to_s00_couplers_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_pc_to_s00_couplers_AWID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal auto_pc_to_s00_couplers_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal auto_pc_to_s00_couplers_AWLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal auto_pc_to_s00_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal auto_pc_to_s00_couplers_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_pc_to_s00_couplers_AWREADY : STD_LOGIC;
signal auto_pc_to_s00_couplers_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal auto_pc_to_s00_couplers_AWVALID : STD_LOGIC;
signal auto_pc_to_s00_couplers_BID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal auto_pc_to_s00_couplers_BREADY : STD_LOGIC;
signal auto_pc_to_s00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_pc_to_s00_couplers_BVALID : STD_LOGIC;
signal auto_pc_to_s00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_s00_couplers_RID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal auto_pc_to_s00_couplers_RLAST : STD_LOGIC;
signal auto_pc_to_s00_couplers_RREADY : STD_LOGIC;
signal auto_pc_to_s00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_pc_to_s00_couplers_RVALID : STD_LOGIC;
signal auto_pc_to_s00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_s00_couplers_WLAST : STD_LOGIC;
signal auto_pc_to_s00_couplers_WREADY : STD_LOGIC;
signal auto_pc_to_s00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_pc_to_s00_couplers_WVALID : STD_LOGIC;
signal s00_couplers_to_auto_pc_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_auto_pc_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_ARID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s00_couplers_to_auto_pc_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_auto_pc_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_ARREADY : STD_LOGIC;
signal s00_couplers_to_auto_pc_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_auto_pc_ARVALID : STD_LOGIC;
signal s00_couplers_to_auto_pc_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_auto_pc_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_AWID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s00_couplers_to_auto_pc_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_AWLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_auto_pc_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_AWREADY : STD_LOGIC;
signal s00_couplers_to_auto_pc_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_auto_pc_AWVALID : STD_LOGIC;
signal s00_couplers_to_auto_pc_BID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s00_couplers_to_auto_pc_BREADY : STD_LOGIC;
signal s00_couplers_to_auto_pc_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_BVALID : STD_LOGIC;
signal s00_couplers_to_auto_pc_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_auto_pc_RID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s00_couplers_to_auto_pc_RLAST : STD_LOGIC;
signal s00_couplers_to_auto_pc_RREADY : STD_LOGIC;
signal s00_couplers_to_auto_pc_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_RVALID : STD_LOGIC;
signal s00_couplers_to_auto_pc_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_auto_pc_WID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s00_couplers_to_auto_pc_WLAST : STD_LOGIC;
signal s00_couplers_to_auto_pc_WREADY : STD_LOGIC;
signal s00_couplers_to_auto_pc_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_WVALID : STD_LOGIC;
signal NLW_auto_pc_m_axi_arregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_auto_pc_m_axi_awregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
begin
M_AXI_araddr(31 downto 0) <= auto_pc_to_s00_couplers_ARADDR(31 downto 0);
M_AXI_arburst(1 downto 0) <= auto_pc_to_s00_couplers_ARBURST(1 downto 0);
M_AXI_arcache(3 downto 0) <= auto_pc_to_s00_couplers_ARCACHE(3 downto 0);
M_AXI_arid(11 downto 0) <= auto_pc_to_s00_couplers_ARID(11 downto 0);
M_AXI_arlen(7 downto 0) <= auto_pc_to_s00_couplers_ARLEN(7 downto 0);
M_AXI_arlock(0) <= auto_pc_to_s00_couplers_ARLOCK(0);
M_AXI_arprot(2 downto 0) <= auto_pc_to_s00_couplers_ARPROT(2 downto 0);
M_AXI_arqos(3 downto 0) <= auto_pc_to_s00_couplers_ARQOS(3 downto 0);
M_AXI_arsize(2 downto 0) <= auto_pc_to_s00_couplers_ARSIZE(2 downto 0);
M_AXI_arvalid <= auto_pc_to_s00_couplers_ARVALID;
M_AXI_awaddr(31 downto 0) <= auto_pc_to_s00_couplers_AWADDR(31 downto 0);
M_AXI_awburst(1 downto 0) <= auto_pc_to_s00_couplers_AWBURST(1 downto 0);
M_AXI_awcache(3 downto 0) <= auto_pc_to_s00_couplers_AWCACHE(3 downto 0);
M_AXI_awid(11 downto 0) <= auto_pc_to_s00_couplers_AWID(11 downto 0);
M_AXI_awlen(7 downto 0) <= auto_pc_to_s00_couplers_AWLEN(7 downto 0);
M_AXI_awlock(0) <= auto_pc_to_s00_couplers_AWLOCK(0);
M_AXI_awprot(2 downto 0) <= auto_pc_to_s00_couplers_AWPROT(2 downto 0);
M_AXI_awqos(3 downto 0) <= auto_pc_to_s00_couplers_AWQOS(3 downto 0);
M_AXI_awsize(2 downto 0) <= auto_pc_to_s00_couplers_AWSIZE(2 downto 0);
M_AXI_awvalid <= auto_pc_to_s00_couplers_AWVALID;
M_AXI_bready <= auto_pc_to_s00_couplers_BREADY;
M_AXI_rready <= auto_pc_to_s00_couplers_RREADY;
M_AXI_wdata(31 downto 0) <= auto_pc_to_s00_couplers_WDATA(31 downto 0);
M_AXI_wlast <= auto_pc_to_s00_couplers_WLAST;
M_AXI_wstrb(3 downto 0) <= auto_pc_to_s00_couplers_WSTRB(3 downto 0);
M_AXI_wvalid <= auto_pc_to_s00_couplers_WVALID;
S_ACLK_1 <= S_ACLK;
S_ARESETN_1(0) <= S_ARESETN(0);
S_AXI_arready <= s00_couplers_to_auto_pc_ARREADY;
S_AXI_awready <= s00_couplers_to_auto_pc_AWREADY;
S_AXI_bid(11 downto 0) <= s00_couplers_to_auto_pc_BID(11 downto 0);
S_AXI_bresp(1 downto 0) <= s00_couplers_to_auto_pc_BRESP(1 downto 0);
S_AXI_bvalid <= s00_couplers_to_auto_pc_BVALID;
S_AXI_rdata(31 downto 0) <= s00_couplers_to_auto_pc_RDATA(31 downto 0);
S_AXI_rid(11 downto 0) <= s00_couplers_to_auto_pc_RID(11 downto 0);
S_AXI_rlast <= s00_couplers_to_auto_pc_RLAST;
S_AXI_rresp(1 downto 0) <= s00_couplers_to_auto_pc_RRESP(1 downto 0);
S_AXI_rvalid <= s00_couplers_to_auto_pc_RVALID;
S_AXI_wready <= s00_couplers_to_auto_pc_WREADY;
auto_pc_to_s00_couplers_ARREADY <= M_AXI_arready;
auto_pc_to_s00_couplers_AWREADY <= M_AXI_awready;
auto_pc_to_s00_couplers_BID(11 downto 0) <= M_AXI_bid(11 downto 0);
auto_pc_to_s00_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
auto_pc_to_s00_couplers_BVALID <= M_AXI_bvalid;
auto_pc_to_s00_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
auto_pc_to_s00_couplers_RID(11 downto 0) <= M_AXI_rid(11 downto 0);
auto_pc_to_s00_couplers_RLAST <= M_AXI_rlast;
auto_pc_to_s00_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
auto_pc_to_s00_couplers_RVALID <= M_AXI_rvalid;
auto_pc_to_s00_couplers_WREADY <= M_AXI_wready;
s00_couplers_to_auto_pc_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
s00_couplers_to_auto_pc_ARBURST(1 downto 0) <= S_AXI_arburst(1 downto 0);
s00_couplers_to_auto_pc_ARCACHE(3 downto 0) <= S_AXI_arcache(3 downto 0);
s00_couplers_to_auto_pc_ARID(11 downto 0) <= S_AXI_arid(11 downto 0);
s00_couplers_to_auto_pc_ARLEN(3 downto 0) <= S_AXI_arlen(3 downto 0);
s00_couplers_to_auto_pc_ARLOCK(1 downto 0) <= S_AXI_arlock(1 downto 0);
s00_couplers_to_auto_pc_ARPROT(2 downto 0) <= S_AXI_arprot(2 downto 0);
s00_couplers_to_auto_pc_ARQOS(3 downto 0) <= S_AXI_arqos(3 downto 0);
s00_couplers_to_auto_pc_ARSIZE(2 downto 0) <= S_AXI_arsize(2 downto 0);
s00_couplers_to_auto_pc_ARVALID <= S_AXI_arvalid;
s00_couplers_to_auto_pc_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
s00_couplers_to_auto_pc_AWBURST(1 downto 0) <= S_AXI_awburst(1 downto 0);
s00_couplers_to_auto_pc_AWCACHE(3 downto 0) <= S_AXI_awcache(3 downto 0);
s00_couplers_to_auto_pc_AWID(11 downto 0) <= S_AXI_awid(11 downto 0);
s00_couplers_to_auto_pc_AWLEN(3 downto 0) <= S_AXI_awlen(3 downto 0);
s00_couplers_to_auto_pc_AWLOCK(1 downto 0) <= S_AXI_awlock(1 downto 0);
s00_couplers_to_auto_pc_AWPROT(2 downto 0) <= S_AXI_awprot(2 downto 0);
s00_couplers_to_auto_pc_AWQOS(3 downto 0) <= S_AXI_awqos(3 downto 0);
s00_couplers_to_auto_pc_AWSIZE(2 downto 0) <= S_AXI_awsize(2 downto 0);
s00_couplers_to_auto_pc_AWVALID <= S_AXI_awvalid;
s00_couplers_to_auto_pc_BREADY <= S_AXI_bready;
s00_couplers_to_auto_pc_RREADY <= S_AXI_rready;
s00_couplers_to_auto_pc_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
s00_couplers_to_auto_pc_WID(11 downto 0) <= S_AXI_wid(11 downto 0);
s00_couplers_to_auto_pc_WLAST <= S_AXI_wlast;
s00_couplers_to_auto_pc_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
s00_couplers_to_auto_pc_WVALID <= S_AXI_wvalid;
auto_pc: component base_zynq_design_auto_pc_1
port map (
aclk => S_ACLK_1,
aresetn => S_ARESETN_1(0),
m_axi_araddr(31 downto 0) => auto_pc_to_s00_couplers_ARADDR(31 downto 0),
m_axi_arburst(1 downto 0) => auto_pc_to_s00_couplers_ARBURST(1 downto 0),
m_axi_arcache(3 downto 0) => auto_pc_to_s00_couplers_ARCACHE(3 downto 0),
m_axi_arid(11 downto 0) => auto_pc_to_s00_couplers_ARID(11 downto 0),
m_axi_arlen(7 downto 0) => auto_pc_to_s00_couplers_ARLEN(7 downto 0),
m_axi_arlock(0) => auto_pc_to_s00_couplers_ARLOCK(0),
m_axi_arprot(2 downto 0) => auto_pc_to_s00_couplers_ARPROT(2 downto 0),
m_axi_arqos(3 downto 0) => auto_pc_to_s00_couplers_ARQOS(3 downto 0),
m_axi_arready => auto_pc_to_s00_couplers_ARREADY,
m_axi_arregion(3 downto 0) => NLW_auto_pc_m_axi_arregion_UNCONNECTED(3 downto 0),
m_axi_arsize(2 downto 0) => auto_pc_to_s00_couplers_ARSIZE(2 downto 0),
m_axi_arvalid => auto_pc_to_s00_couplers_ARVALID,
m_axi_awaddr(31 downto 0) => auto_pc_to_s00_couplers_AWADDR(31 downto 0),
m_axi_awburst(1 downto 0) => auto_pc_to_s00_couplers_AWBURST(1 downto 0),
m_axi_awcache(3 downto 0) => auto_pc_to_s00_couplers_AWCACHE(3 downto 0),
m_axi_awid(11 downto 0) => auto_pc_to_s00_couplers_AWID(11 downto 0),
m_axi_awlen(7 downto 0) => auto_pc_to_s00_couplers_AWLEN(7 downto 0),
m_axi_awlock(0) => auto_pc_to_s00_couplers_AWLOCK(0),
m_axi_awprot(2 downto 0) => auto_pc_to_s00_couplers_AWPROT(2 downto 0),
m_axi_awqos(3 downto 0) => auto_pc_to_s00_couplers_AWQOS(3 downto 0),
m_axi_awready => auto_pc_to_s00_couplers_AWREADY,
m_axi_awregion(3 downto 0) => NLW_auto_pc_m_axi_awregion_UNCONNECTED(3 downto 0),
m_axi_awsize(2 downto 0) => auto_pc_to_s00_couplers_AWSIZE(2 downto 0),
m_axi_awvalid => auto_pc_to_s00_couplers_AWVALID,
m_axi_bid(11 downto 0) => auto_pc_to_s00_couplers_BID(11 downto 0),
m_axi_bready => auto_pc_to_s00_couplers_BREADY,
m_axi_bresp(1 downto 0) => auto_pc_to_s00_couplers_BRESP(1 downto 0),
m_axi_bvalid => auto_pc_to_s00_couplers_BVALID,
m_axi_rdata(31 downto 0) => auto_pc_to_s00_couplers_RDATA(31 downto 0),
m_axi_rid(11 downto 0) => auto_pc_to_s00_couplers_RID(11 downto 0),
m_axi_rlast => auto_pc_to_s00_couplers_RLAST,
m_axi_rready => auto_pc_to_s00_couplers_RREADY,
m_axi_rresp(1 downto 0) => auto_pc_to_s00_couplers_RRESP(1 downto 0),
m_axi_rvalid => auto_pc_to_s00_couplers_RVALID,
m_axi_wdata(31 downto 0) => auto_pc_to_s00_couplers_WDATA(31 downto 0),
m_axi_wlast => auto_pc_to_s00_couplers_WLAST,
m_axi_wready => auto_pc_to_s00_couplers_WREADY,
m_axi_wstrb(3 downto 0) => auto_pc_to_s00_couplers_WSTRB(3 downto 0),
m_axi_wvalid => auto_pc_to_s00_couplers_WVALID,
s_axi_araddr(31 downto 0) => s00_couplers_to_auto_pc_ARADDR(31 downto 0),
s_axi_arburst(1 downto 0) => s00_couplers_to_auto_pc_ARBURST(1 downto 0),
s_axi_arcache(3 downto 0) => s00_couplers_to_auto_pc_ARCACHE(3 downto 0),
s_axi_arid(11 downto 0) => s00_couplers_to_auto_pc_ARID(11 downto 0),
s_axi_arlen(3 downto 0) => s00_couplers_to_auto_pc_ARLEN(3 downto 0),
s_axi_arlock(1 downto 0) => s00_couplers_to_auto_pc_ARLOCK(1 downto 0),
s_axi_arprot(2 downto 0) => s00_couplers_to_auto_pc_ARPROT(2 downto 0),
s_axi_arqos(3 downto 0) => s00_couplers_to_auto_pc_ARQOS(3 downto 0),
s_axi_arready => s00_couplers_to_auto_pc_ARREADY,
s_axi_arsize(2 downto 0) => s00_couplers_to_auto_pc_ARSIZE(2 downto 0),
s_axi_arvalid => s00_couplers_to_auto_pc_ARVALID,
s_axi_awaddr(31 downto 0) => s00_couplers_to_auto_pc_AWADDR(31 downto 0),
s_axi_awburst(1 downto 0) => s00_couplers_to_auto_pc_AWBURST(1 downto 0),
s_axi_awcache(3 downto 0) => s00_couplers_to_auto_pc_AWCACHE(3 downto 0),
s_axi_awid(11 downto 0) => s00_couplers_to_auto_pc_AWID(11 downto 0),
s_axi_awlen(3 downto 0) => s00_couplers_to_auto_pc_AWLEN(3 downto 0),
s_axi_awlock(1 downto 0) => s00_couplers_to_auto_pc_AWLOCK(1 downto 0),
s_axi_awprot(2 downto 0) => s00_couplers_to_auto_pc_AWPROT(2 downto 0),
s_axi_awqos(3 downto 0) => s00_couplers_to_auto_pc_AWQOS(3 downto 0),
s_axi_awready => s00_couplers_to_auto_pc_AWREADY,
s_axi_awsize(2 downto 0) => s00_couplers_to_auto_pc_AWSIZE(2 downto 0),
s_axi_awvalid => s00_couplers_to_auto_pc_AWVALID,
s_axi_bid(11 downto 0) => s00_couplers_to_auto_pc_BID(11 downto 0),
s_axi_bready => s00_couplers_to_auto_pc_BREADY,
s_axi_bresp(1 downto 0) => s00_couplers_to_auto_pc_BRESP(1 downto 0),
s_axi_bvalid => s00_couplers_to_auto_pc_BVALID,
s_axi_rdata(31 downto 0) => s00_couplers_to_auto_pc_RDATA(31 downto 0),
s_axi_rid(11 downto 0) => s00_couplers_to_auto_pc_RID(11 downto 0),
s_axi_rlast => s00_couplers_to_auto_pc_RLAST,
s_axi_rready => s00_couplers_to_auto_pc_RREADY,
s_axi_rresp(1 downto 0) => s00_couplers_to_auto_pc_RRESP(1 downto 0),
s_axi_rvalid => s00_couplers_to_auto_pc_RVALID,
s_axi_wdata(31 downto 0) => s00_couplers_to_auto_pc_WDATA(31 downto 0),
s_axi_wid(11 downto 0) => s00_couplers_to_auto_pc_WID(11 downto 0),
s_axi_wlast => s00_couplers_to_auto_pc_WLAST,
s_axi_wready => s00_couplers_to_auto_pc_WREADY,
s_axi_wstrb(3 downto 0) => s00_couplers_to_auto_pc_WSTRB(3 downto 0),
s_axi_wvalid => s00_couplers_to_auto_pc_WVALID
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity base_zynq_design_processing_system7_0_axi_periph_0 is
port (
ACLK : in STD_LOGIC;
ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_ACLK : in STD_LOGIC;
M00_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_araddr : out STD_LOGIC_VECTOR ( 8 downto 0 );
M00_AXI_arready : in STD_LOGIC;
M00_AXI_arvalid : out STD_LOGIC;
M00_AXI_awaddr : out STD_LOGIC_VECTOR ( 8 downto 0 );
M00_AXI_awready : in STD_LOGIC;
M00_AXI_awvalid : out STD_LOGIC;
M00_AXI_bready : out STD_LOGIC;
M00_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_bvalid : in STD_LOGIC;
M00_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_rready : out STD_LOGIC;
M00_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_rvalid : in STD_LOGIC;
M00_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_wready : in STD_LOGIC;
M00_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_wvalid : out STD_LOGIC;
M01_ACLK : in STD_LOGIC;
M01_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M01_AXI_araddr : out STD_LOGIC_VECTOR ( 12 downto 0 );
M01_AXI_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
M01_AXI_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
M01_AXI_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
M01_AXI_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
M01_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M01_AXI_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
M01_AXI_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
M01_AXI_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M01_AXI_awaddr : out STD_LOGIC_VECTOR ( 12 downto 0 );
M01_AXI_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
M01_AXI_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
M01_AXI_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
M01_AXI_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
M01_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M01_AXI_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
M01_AXI_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
M01_AXI_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M01_AXI_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
M01_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M01_AXI_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M01_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M01_AXI_rlast : in STD_LOGIC_VECTOR ( 0 to 0 );
M01_AXI_rready : out STD_LOGIC_VECTOR ( 0 to 0 );
M01_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M01_AXI_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M01_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M01_AXI_wlast : out STD_LOGIC_VECTOR ( 0 to 0 );
M01_AXI_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
M01_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M01_AXI_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S00_ACLK : in STD_LOGIC;
S00_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S00_AXI_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arready : out STD_LOGIC;
S00_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_arvalid : in STD_LOGIC;
S00_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S00_AXI_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_awready : out STD_LOGIC;
S00_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_awvalid : in STD_LOGIC;
S00_AXI_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
S00_AXI_bready : in STD_LOGIC;
S00_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_bvalid : out STD_LOGIC;
S00_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
S00_AXI_rlast : out STD_LOGIC;
S00_AXI_rready : in STD_LOGIC;
S00_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_rvalid : out STD_LOGIC;
S00_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_wid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S00_AXI_wlast : in STD_LOGIC;
S00_AXI_wready : out STD_LOGIC;
S00_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_wvalid : in STD_LOGIC
);
end base_zynq_design_processing_system7_0_axi_periph_0;
architecture STRUCTURE of base_zynq_design_processing_system7_0_axi_periph_0 is
component base_zynq_design_xbar_0 is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awvalid : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awready : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_wlast : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_wvalid : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_wready : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_bvalid : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bready : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arvalid : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arready : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_rlast : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rvalid : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rready : out STD_LOGIC_VECTOR ( 1 downto 0 )
);
end component base_zynq_design_xbar_0;
signal M00_ACLK_1 : STD_LOGIC;
signal M00_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal M01_ACLK_1 : STD_LOGIC;
signal M01_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal S00_ACLK_1 : STD_LOGIC;
signal S00_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_ARADDR : STD_LOGIC_VECTOR ( 8 downto 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_ARREADY : STD_LOGIC;
signal m00_couplers_to_processing_system7_0_axi_periph_ARVALID : STD_LOGIC;
signal m00_couplers_to_processing_system7_0_axi_periph_AWADDR : STD_LOGIC_VECTOR ( 8 downto 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_AWREADY : STD_LOGIC;
signal m00_couplers_to_processing_system7_0_axi_periph_AWVALID : STD_LOGIC;
signal m00_couplers_to_processing_system7_0_axi_periph_BREADY : STD_LOGIC;
signal m00_couplers_to_processing_system7_0_axi_periph_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_BVALID : STD_LOGIC;
signal m00_couplers_to_processing_system7_0_axi_periph_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_RREADY : STD_LOGIC;
signal m00_couplers_to_processing_system7_0_axi_periph_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_RVALID : STD_LOGIC;
signal m00_couplers_to_processing_system7_0_axi_periph_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_WREADY : STD_LOGIC;
signal m00_couplers_to_processing_system7_0_axi_periph_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_WVALID : STD_LOGIC;
signal m01_couplers_to_processing_system7_0_axi_periph_ARADDR : STD_LOGIC_VECTOR ( 12 downto 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_ARLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_AWADDR : STD_LOGIC_VECTOR ( 12 downto 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_AWLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_RLAST : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_WLAST : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal processing_system7_0_axi_periph_ACLK_net : STD_LOGIC;
signal processing_system7_0_axi_periph_ARESETN_net : STD_LOGIC_VECTOR ( 0 to 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_ARID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_ARREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_ARVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_AWID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_AWLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_AWREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_AWVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_BID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_BREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_BVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_RID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_RLAST : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_RREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_RVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_WID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_WLAST : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_WREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_WVALID : STD_LOGIC;
signal s00_couplers_to_xbar_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_xbar_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_xbar_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_xbar_ARID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s00_couplers_to_xbar_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal s00_couplers_to_xbar_ARLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_xbar_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_xbar_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_xbar_ARVALID : STD_LOGIC;
signal s00_couplers_to_xbar_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_xbar_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_xbar_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_xbar_AWID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s00_couplers_to_xbar_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal s00_couplers_to_xbar_AWLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_xbar_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_xbar_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_xbar_AWVALID : STD_LOGIC;
signal s00_couplers_to_xbar_BID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s00_couplers_to_xbar_BREADY : STD_LOGIC;
signal s00_couplers_to_xbar_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_xbar_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_xbar_RID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s00_couplers_to_xbar_RLAST : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_RREADY : STD_LOGIC;
signal s00_couplers_to_xbar_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_xbar_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_xbar_WLAST : STD_LOGIC;
signal s00_couplers_to_xbar_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_xbar_WVALID : STD_LOGIC;
signal xbar_to_m00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m00_couplers_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m00_couplers_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal xbar_to_m00_couplers_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal xbar_to_m00_couplers_ARLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal xbar_to_m00_couplers_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal xbar_to_m00_couplers_ARREADY : STD_LOGIC;
signal xbar_to_m00_couplers_ARREGION : STD_LOGIC_VECTOR ( 3 downto 0 );
signal xbar_to_m00_couplers_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal xbar_to_m00_couplers_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m00_couplers_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m00_couplers_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal xbar_to_m00_couplers_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal xbar_to_m00_couplers_AWLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal xbar_to_m00_couplers_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal xbar_to_m00_couplers_AWREADY : STD_LOGIC;
signal xbar_to_m00_couplers_AWREGION : STD_LOGIC_VECTOR ( 3 downto 0 );
signal xbar_to_m00_couplers_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal xbar_to_m00_couplers_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m00_couplers_BVALID : STD_LOGIC;
signal xbar_to_m00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m00_couplers_RLAST : STD_LOGIC;
signal xbar_to_m00_couplers_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m00_couplers_RVALID : STD_LOGIC;
signal xbar_to_m00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m00_couplers_WLAST : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_WREADY : STD_LOGIC;
signal xbar_to_m00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal xbar_to_m00_couplers_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m01_couplers_ARADDR : STD_LOGIC_VECTOR ( 63 downto 32 );
signal xbar_to_m01_couplers_ARBURST : STD_LOGIC_VECTOR ( 3 downto 2 );
signal xbar_to_m01_couplers_ARCACHE : STD_LOGIC_VECTOR ( 7 downto 4 );
signal xbar_to_m01_couplers_ARLEN : STD_LOGIC_VECTOR ( 15 downto 8 );
signal xbar_to_m01_couplers_ARLOCK : STD_LOGIC_VECTOR ( 1 to 1 );
signal xbar_to_m01_couplers_ARPROT : STD_LOGIC_VECTOR ( 5 downto 3 );
signal xbar_to_m01_couplers_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m01_couplers_ARSIZE : STD_LOGIC_VECTOR ( 5 downto 3 );
signal xbar_to_m01_couplers_ARVALID : STD_LOGIC_VECTOR ( 1 to 1 );
signal xbar_to_m01_couplers_AWADDR : STD_LOGIC_VECTOR ( 63 downto 32 );
signal xbar_to_m01_couplers_AWBURST : STD_LOGIC_VECTOR ( 3 downto 2 );
signal xbar_to_m01_couplers_AWCACHE : STD_LOGIC_VECTOR ( 7 downto 4 );
signal xbar_to_m01_couplers_AWLEN : STD_LOGIC_VECTOR ( 15 downto 8 );
signal xbar_to_m01_couplers_AWLOCK : STD_LOGIC_VECTOR ( 1 to 1 );
signal xbar_to_m01_couplers_AWPROT : STD_LOGIC_VECTOR ( 5 downto 3 );
signal xbar_to_m01_couplers_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m01_couplers_AWSIZE : STD_LOGIC_VECTOR ( 5 downto 3 );
signal xbar_to_m01_couplers_AWVALID : STD_LOGIC_VECTOR ( 1 to 1 );
signal xbar_to_m01_couplers_BREADY : STD_LOGIC_VECTOR ( 1 to 1 );
signal xbar_to_m01_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m01_couplers_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m01_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m01_couplers_RLAST : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m01_couplers_RREADY : STD_LOGIC_VECTOR ( 1 to 1 );
signal xbar_to_m01_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m01_couplers_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m01_couplers_WDATA : STD_LOGIC_VECTOR ( 63 downto 32 );
signal xbar_to_m01_couplers_WLAST : STD_LOGIC_VECTOR ( 1 to 1 );
signal xbar_to_m01_couplers_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m01_couplers_WSTRB : STD_LOGIC_VECTOR ( 7 downto 4 );
signal xbar_to_m01_couplers_WVALID : STD_LOGIC_VECTOR ( 1 to 1 );
signal NLW_xbar_m_axi_arqos_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 4 );
signal NLW_xbar_m_axi_arregion_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 4 );
signal NLW_xbar_m_axi_awqos_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 4 );
signal NLW_xbar_m_axi_awregion_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 4 );
begin
M00_ACLK_1 <= M00_ACLK;
M00_ARESETN_1(0) <= M00_ARESETN(0);
M00_AXI_araddr(8 downto 0) <= m00_couplers_to_processing_system7_0_axi_periph_ARADDR(8 downto 0);
M00_AXI_arvalid <= m00_couplers_to_processing_system7_0_axi_periph_ARVALID;
M00_AXI_awaddr(8 downto 0) <= m00_couplers_to_processing_system7_0_axi_periph_AWADDR(8 downto 0);
M00_AXI_awvalid <= m00_couplers_to_processing_system7_0_axi_periph_AWVALID;
M00_AXI_bready <= m00_couplers_to_processing_system7_0_axi_periph_BREADY;
M00_AXI_rready <= m00_couplers_to_processing_system7_0_axi_periph_RREADY;
M00_AXI_wdata(31 downto 0) <= m00_couplers_to_processing_system7_0_axi_periph_WDATA(31 downto 0);
M00_AXI_wstrb(3 downto 0) <= m00_couplers_to_processing_system7_0_axi_periph_WSTRB(3 downto 0);
M00_AXI_wvalid <= m00_couplers_to_processing_system7_0_axi_periph_WVALID;
M01_ACLK_1 <= M01_ACLK;
M01_ARESETN_1(0) <= M01_ARESETN(0);
M01_AXI_araddr(12 downto 0) <= m01_couplers_to_processing_system7_0_axi_periph_ARADDR(12 downto 0);
M01_AXI_arburst(1 downto 0) <= m01_couplers_to_processing_system7_0_axi_periph_ARBURST(1 downto 0);
M01_AXI_arcache(3 downto 0) <= m01_couplers_to_processing_system7_0_axi_periph_ARCACHE(3 downto 0);
M01_AXI_arlen(7 downto 0) <= m01_couplers_to_processing_system7_0_axi_periph_ARLEN(7 downto 0);
M01_AXI_arlock(0) <= m01_couplers_to_processing_system7_0_axi_periph_ARLOCK(0);
M01_AXI_arprot(2 downto 0) <= m01_couplers_to_processing_system7_0_axi_periph_ARPROT(2 downto 0);
M01_AXI_arsize(2 downto 0) <= m01_couplers_to_processing_system7_0_axi_periph_ARSIZE(2 downto 0);
M01_AXI_arvalid(0) <= m01_couplers_to_processing_system7_0_axi_periph_ARVALID(0);
M01_AXI_awaddr(12 downto 0) <= m01_couplers_to_processing_system7_0_axi_periph_AWADDR(12 downto 0);
M01_AXI_awburst(1 downto 0) <= m01_couplers_to_processing_system7_0_axi_periph_AWBURST(1 downto 0);
M01_AXI_awcache(3 downto 0) <= m01_couplers_to_processing_system7_0_axi_periph_AWCACHE(3 downto 0);
M01_AXI_awlen(7 downto 0) <= m01_couplers_to_processing_system7_0_axi_periph_AWLEN(7 downto 0);
M01_AXI_awlock(0) <= m01_couplers_to_processing_system7_0_axi_periph_AWLOCK(0);
M01_AXI_awprot(2 downto 0) <= m01_couplers_to_processing_system7_0_axi_periph_AWPROT(2 downto 0);
M01_AXI_awsize(2 downto 0) <= m01_couplers_to_processing_system7_0_axi_periph_AWSIZE(2 downto 0);
M01_AXI_awvalid(0) <= m01_couplers_to_processing_system7_0_axi_periph_AWVALID(0);
M01_AXI_bready(0) <= m01_couplers_to_processing_system7_0_axi_periph_BREADY(0);
M01_AXI_rready(0) <= m01_couplers_to_processing_system7_0_axi_periph_RREADY(0);
M01_AXI_wdata(31 downto 0) <= m01_couplers_to_processing_system7_0_axi_periph_WDATA(31 downto 0);
M01_AXI_wlast(0) <= m01_couplers_to_processing_system7_0_axi_periph_WLAST(0);
M01_AXI_wstrb(3 downto 0) <= m01_couplers_to_processing_system7_0_axi_periph_WSTRB(3 downto 0);
M01_AXI_wvalid(0) <= m01_couplers_to_processing_system7_0_axi_periph_WVALID(0);
S00_ACLK_1 <= S00_ACLK;
S00_ARESETN_1(0) <= S00_ARESETN(0);
S00_AXI_arready <= processing_system7_0_axi_periph_to_s00_couplers_ARREADY;
S00_AXI_awready <= processing_system7_0_axi_periph_to_s00_couplers_AWREADY;
S00_AXI_bid(11 downto 0) <= processing_system7_0_axi_periph_to_s00_couplers_BID(11 downto 0);
S00_AXI_bresp(1 downto 0) <= processing_system7_0_axi_periph_to_s00_couplers_BRESP(1 downto 0);
S00_AXI_bvalid <= processing_system7_0_axi_periph_to_s00_couplers_BVALID;
S00_AXI_rdata(31 downto 0) <= processing_system7_0_axi_periph_to_s00_couplers_RDATA(31 downto 0);
S00_AXI_rid(11 downto 0) <= processing_system7_0_axi_periph_to_s00_couplers_RID(11 downto 0);
S00_AXI_rlast <= processing_system7_0_axi_periph_to_s00_couplers_RLAST;
S00_AXI_rresp(1 downto 0) <= processing_system7_0_axi_periph_to_s00_couplers_RRESP(1 downto 0);
S00_AXI_rvalid <= processing_system7_0_axi_periph_to_s00_couplers_RVALID;
S00_AXI_wready <= processing_system7_0_axi_periph_to_s00_couplers_WREADY;
m00_couplers_to_processing_system7_0_axi_periph_ARREADY <= M00_AXI_arready;
m00_couplers_to_processing_system7_0_axi_periph_AWREADY <= M00_AXI_awready;
m00_couplers_to_processing_system7_0_axi_periph_BRESP(1 downto 0) <= M00_AXI_bresp(1 downto 0);
m00_couplers_to_processing_system7_0_axi_periph_BVALID <= M00_AXI_bvalid;
m00_couplers_to_processing_system7_0_axi_periph_RDATA(31 downto 0) <= M00_AXI_rdata(31 downto 0);
m00_couplers_to_processing_system7_0_axi_periph_RRESP(1 downto 0) <= M00_AXI_rresp(1 downto 0);
m00_couplers_to_processing_system7_0_axi_periph_RVALID <= M00_AXI_rvalid;
m00_couplers_to_processing_system7_0_axi_periph_WREADY <= M00_AXI_wready;
m01_couplers_to_processing_system7_0_axi_periph_ARREADY(0) <= M01_AXI_arready(0);
m01_couplers_to_processing_system7_0_axi_periph_AWREADY(0) <= M01_AXI_awready(0);
m01_couplers_to_processing_system7_0_axi_periph_BRESP(1 downto 0) <= M01_AXI_bresp(1 downto 0);
m01_couplers_to_processing_system7_0_axi_periph_BVALID(0) <= M01_AXI_bvalid(0);
m01_couplers_to_processing_system7_0_axi_periph_RDATA(31 downto 0) <= M01_AXI_rdata(31 downto 0);
m01_couplers_to_processing_system7_0_axi_periph_RLAST(0) <= M01_AXI_rlast(0);
m01_couplers_to_processing_system7_0_axi_periph_RRESP(1 downto 0) <= M01_AXI_rresp(1 downto 0);
m01_couplers_to_processing_system7_0_axi_periph_RVALID(0) <= M01_AXI_rvalid(0);
m01_couplers_to_processing_system7_0_axi_periph_WREADY(0) <= M01_AXI_wready(0);
processing_system7_0_axi_periph_ACLK_net <= ACLK;
processing_system7_0_axi_periph_ARESETN_net(0) <= ARESETN(0);
processing_system7_0_axi_periph_to_s00_couplers_ARADDR(31 downto 0) <= S00_AXI_araddr(31 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_ARBURST(1 downto 0) <= S00_AXI_arburst(1 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_ARCACHE(3 downto 0) <= S00_AXI_arcache(3 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_ARID(11 downto 0) <= S00_AXI_arid(11 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_ARLEN(3 downto 0) <= S00_AXI_arlen(3 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_ARLOCK(1 downto 0) <= S00_AXI_arlock(1 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_ARPROT(2 downto 0) <= S00_AXI_arprot(2 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_ARQOS(3 downto 0) <= S00_AXI_arqos(3 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_ARSIZE(2 downto 0) <= S00_AXI_arsize(2 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_ARVALID <= S00_AXI_arvalid;
processing_system7_0_axi_periph_to_s00_couplers_AWADDR(31 downto 0) <= S00_AXI_awaddr(31 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_AWBURST(1 downto 0) <= S00_AXI_awburst(1 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_AWCACHE(3 downto 0) <= S00_AXI_awcache(3 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_AWID(11 downto 0) <= S00_AXI_awid(11 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_AWLEN(3 downto 0) <= S00_AXI_awlen(3 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_AWLOCK(1 downto 0) <= S00_AXI_awlock(1 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_AWPROT(2 downto 0) <= S00_AXI_awprot(2 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_AWQOS(3 downto 0) <= S00_AXI_awqos(3 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_AWSIZE(2 downto 0) <= S00_AXI_awsize(2 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_AWVALID <= S00_AXI_awvalid;
processing_system7_0_axi_periph_to_s00_couplers_BREADY <= S00_AXI_bready;
processing_system7_0_axi_periph_to_s00_couplers_RREADY <= S00_AXI_rready;
processing_system7_0_axi_periph_to_s00_couplers_WDATA(31 downto 0) <= S00_AXI_wdata(31 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_WID(11 downto 0) <= S00_AXI_wid(11 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_WLAST <= S00_AXI_wlast;
processing_system7_0_axi_periph_to_s00_couplers_WSTRB(3 downto 0) <= S00_AXI_wstrb(3 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_WVALID <= S00_AXI_wvalid;
m00_couplers: entity work.m00_couplers_imp_1R5MXF4
port map (
M_ACLK => M00_ACLK_1,
M_ARESETN(0) => M00_ARESETN_1(0),
M_AXI_araddr(8 downto 0) => m00_couplers_to_processing_system7_0_axi_periph_ARADDR(8 downto 0),
M_AXI_arready => m00_couplers_to_processing_system7_0_axi_periph_ARREADY,
M_AXI_arvalid => m00_couplers_to_processing_system7_0_axi_periph_ARVALID,
M_AXI_awaddr(8 downto 0) => m00_couplers_to_processing_system7_0_axi_periph_AWADDR(8 downto 0),
M_AXI_awready => m00_couplers_to_processing_system7_0_axi_periph_AWREADY,
M_AXI_awvalid => m00_couplers_to_processing_system7_0_axi_periph_AWVALID,
M_AXI_bready => m00_couplers_to_processing_system7_0_axi_periph_BREADY,
M_AXI_bresp(1 downto 0) => m00_couplers_to_processing_system7_0_axi_periph_BRESP(1 downto 0),
M_AXI_bvalid => m00_couplers_to_processing_system7_0_axi_periph_BVALID,
M_AXI_rdata(31 downto 0) => m00_couplers_to_processing_system7_0_axi_periph_RDATA(31 downto 0),
M_AXI_rready => m00_couplers_to_processing_system7_0_axi_periph_RREADY,
M_AXI_rresp(1 downto 0) => m00_couplers_to_processing_system7_0_axi_periph_RRESP(1 downto 0),
M_AXI_rvalid => m00_couplers_to_processing_system7_0_axi_periph_RVALID,
M_AXI_wdata(31 downto 0) => m00_couplers_to_processing_system7_0_axi_periph_WDATA(31 downto 0),
M_AXI_wready => m00_couplers_to_processing_system7_0_axi_periph_WREADY,
M_AXI_wstrb(3 downto 0) => m00_couplers_to_processing_system7_0_axi_periph_WSTRB(3 downto 0),
M_AXI_wvalid => m00_couplers_to_processing_system7_0_axi_periph_WVALID,
S_ACLK => processing_system7_0_axi_periph_ACLK_net,
S_ARESETN(0) => processing_system7_0_axi_periph_ARESETN_net(0),
S_AXI_araddr(31 downto 0) => xbar_to_m00_couplers_ARADDR(31 downto 0),
S_AXI_arburst(1 downto 0) => xbar_to_m00_couplers_ARBURST(1 downto 0),
S_AXI_arcache(3 downto 0) => xbar_to_m00_couplers_ARCACHE(3 downto 0),
S_AXI_arlen(7 downto 0) => xbar_to_m00_couplers_ARLEN(7 downto 0),
S_AXI_arlock(0) => xbar_to_m00_couplers_ARLOCK(0),
S_AXI_arprot(2 downto 0) => xbar_to_m00_couplers_ARPROT(2 downto 0),
S_AXI_arqos(3 downto 0) => xbar_to_m00_couplers_ARQOS(3 downto 0),
S_AXI_arready => xbar_to_m00_couplers_ARREADY,
S_AXI_arregion(3 downto 0) => xbar_to_m00_couplers_ARREGION(3 downto 0),
S_AXI_arsize(2 downto 0) => xbar_to_m00_couplers_ARSIZE(2 downto 0),
S_AXI_arvalid => xbar_to_m00_couplers_ARVALID(0),
S_AXI_awaddr(31 downto 0) => xbar_to_m00_couplers_AWADDR(31 downto 0),
S_AXI_awburst(1 downto 0) => xbar_to_m00_couplers_AWBURST(1 downto 0),
S_AXI_awcache(3 downto 0) => xbar_to_m00_couplers_AWCACHE(3 downto 0),
S_AXI_awlen(7 downto 0) => xbar_to_m00_couplers_AWLEN(7 downto 0),
S_AXI_awlock(0) => xbar_to_m00_couplers_AWLOCK(0),
S_AXI_awprot(2 downto 0) => xbar_to_m00_couplers_AWPROT(2 downto 0),
S_AXI_awqos(3 downto 0) => xbar_to_m00_couplers_AWQOS(3 downto 0),
S_AXI_awready => xbar_to_m00_couplers_AWREADY,
S_AXI_awregion(3 downto 0) => xbar_to_m00_couplers_AWREGION(3 downto 0),
S_AXI_awsize(2 downto 0) => xbar_to_m00_couplers_AWSIZE(2 downto 0),
S_AXI_awvalid => xbar_to_m00_couplers_AWVALID(0),
S_AXI_bready => xbar_to_m00_couplers_BREADY(0),
S_AXI_bresp(1 downto 0) => xbar_to_m00_couplers_BRESP(1 downto 0),
S_AXI_bvalid => xbar_to_m00_couplers_BVALID,
S_AXI_rdata(31 downto 0) => xbar_to_m00_couplers_RDATA(31 downto 0),
S_AXI_rlast => xbar_to_m00_couplers_RLAST,
S_AXI_rready => xbar_to_m00_couplers_RREADY(0),
S_AXI_rresp(1 downto 0) => xbar_to_m00_couplers_RRESP(1 downto 0),
S_AXI_rvalid => xbar_to_m00_couplers_RVALID,
S_AXI_wdata(31 downto 0) => xbar_to_m00_couplers_WDATA(31 downto 0),
S_AXI_wlast => xbar_to_m00_couplers_WLAST(0),
S_AXI_wready => xbar_to_m00_couplers_WREADY,
S_AXI_wstrb(3 downto 0) => xbar_to_m00_couplers_WSTRB(3 downto 0),
S_AXI_wvalid => xbar_to_m00_couplers_WVALID(0)
);
m01_couplers: entity work.m01_couplers_imp_19312F
port map (
M_ACLK => M01_ACLK_1,
M_ARESETN(0) => M01_ARESETN_1(0),
M_AXI_araddr(12 downto 0) => m01_couplers_to_processing_system7_0_axi_periph_ARADDR(12 downto 0),
M_AXI_arburst(1 downto 0) => m01_couplers_to_processing_system7_0_axi_periph_ARBURST(1 downto 0),
M_AXI_arcache(3 downto 0) => m01_couplers_to_processing_system7_0_axi_periph_ARCACHE(3 downto 0),
M_AXI_arlen(7 downto 0) => m01_couplers_to_processing_system7_0_axi_periph_ARLEN(7 downto 0),
M_AXI_arlock(0) => m01_couplers_to_processing_system7_0_axi_periph_ARLOCK(0),
M_AXI_arprot(2 downto 0) => m01_couplers_to_processing_system7_0_axi_periph_ARPROT(2 downto 0),
M_AXI_arready(0) => m01_couplers_to_processing_system7_0_axi_periph_ARREADY(0),
M_AXI_arsize(2 downto 0) => m01_couplers_to_processing_system7_0_axi_periph_ARSIZE(2 downto 0),
M_AXI_arvalid(0) => m01_couplers_to_processing_system7_0_axi_periph_ARVALID(0),
M_AXI_awaddr(12 downto 0) => m01_couplers_to_processing_system7_0_axi_periph_AWADDR(12 downto 0),
M_AXI_awburst(1 downto 0) => m01_couplers_to_processing_system7_0_axi_periph_AWBURST(1 downto 0),
M_AXI_awcache(3 downto 0) => m01_couplers_to_processing_system7_0_axi_periph_AWCACHE(3 downto 0),
M_AXI_awlen(7 downto 0) => m01_couplers_to_processing_system7_0_axi_periph_AWLEN(7 downto 0),
M_AXI_awlock(0) => m01_couplers_to_processing_system7_0_axi_periph_AWLOCK(0),
M_AXI_awprot(2 downto 0) => m01_couplers_to_processing_system7_0_axi_periph_AWPROT(2 downto 0),
M_AXI_awready(0) => m01_couplers_to_processing_system7_0_axi_periph_AWREADY(0),
M_AXI_awsize(2 downto 0) => m01_couplers_to_processing_system7_0_axi_periph_AWSIZE(2 downto 0),
M_AXI_awvalid(0) => m01_couplers_to_processing_system7_0_axi_periph_AWVALID(0),
M_AXI_bready(0) => m01_couplers_to_processing_system7_0_axi_periph_BREADY(0),
M_AXI_bresp(1 downto 0) => m01_couplers_to_processing_system7_0_axi_periph_BRESP(1 downto 0),
M_AXI_bvalid(0) => m01_couplers_to_processing_system7_0_axi_periph_BVALID(0),
M_AXI_rdata(31 downto 0) => m01_couplers_to_processing_system7_0_axi_periph_RDATA(31 downto 0),
M_AXI_rlast(0) => m01_couplers_to_processing_system7_0_axi_periph_RLAST(0),
M_AXI_rready(0) => m01_couplers_to_processing_system7_0_axi_periph_RREADY(0),
M_AXI_rresp(1 downto 0) => m01_couplers_to_processing_system7_0_axi_periph_RRESP(1 downto 0),
M_AXI_rvalid(0) => m01_couplers_to_processing_system7_0_axi_periph_RVALID(0),
M_AXI_wdata(31 downto 0) => m01_couplers_to_processing_system7_0_axi_periph_WDATA(31 downto 0),
M_AXI_wlast(0) => m01_couplers_to_processing_system7_0_axi_periph_WLAST(0),
M_AXI_wready(0) => m01_couplers_to_processing_system7_0_axi_periph_WREADY(0),
M_AXI_wstrb(3 downto 0) => m01_couplers_to_processing_system7_0_axi_periph_WSTRB(3 downto 0),
M_AXI_wvalid(0) => m01_couplers_to_processing_system7_0_axi_periph_WVALID(0),
S_ACLK => processing_system7_0_axi_periph_ACLK_net,
S_ARESETN(0) => processing_system7_0_axi_periph_ARESETN_net(0),
S_AXI_araddr(12 downto 0) => xbar_to_m01_couplers_ARADDR(44 downto 32),
S_AXI_arburst(1 downto 0) => xbar_to_m01_couplers_ARBURST(3 downto 2),
S_AXI_arcache(3 downto 0) => xbar_to_m01_couplers_ARCACHE(7 downto 4),
S_AXI_arlen(7 downto 0) => xbar_to_m01_couplers_ARLEN(15 downto 8),
S_AXI_arlock(0) => xbar_to_m01_couplers_ARLOCK(1),
S_AXI_arprot(2 downto 0) => xbar_to_m01_couplers_ARPROT(5 downto 3),
S_AXI_arready(0) => xbar_to_m01_couplers_ARREADY(0),
S_AXI_arsize(2 downto 0) => xbar_to_m01_couplers_ARSIZE(5 downto 3),
S_AXI_arvalid(0) => xbar_to_m01_couplers_ARVALID(1),
S_AXI_awaddr(12 downto 0) => xbar_to_m01_couplers_AWADDR(44 downto 32),
S_AXI_awburst(1 downto 0) => xbar_to_m01_couplers_AWBURST(3 downto 2),
S_AXI_awcache(3 downto 0) => xbar_to_m01_couplers_AWCACHE(7 downto 4),
S_AXI_awlen(7 downto 0) => xbar_to_m01_couplers_AWLEN(15 downto 8),
S_AXI_awlock(0) => xbar_to_m01_couplers_AWLOCK(1),
S_AXI_awprot(2 downto 0) => xbar_to_m01_couplers_AWPROT(5 downto 3),
S_AXI_awready(0) => xbar_to_m01_couplers_AWREADY(0),
S_AXI_awsize(2 downto 0) => xbar_to_m01_couplers_AWSIZE(5 downto 3),
S_AXI_awvalid(0) => xbar_to_m01_couplers_AWVALID(1),
S_AXI_bready(0) => xbar_to_m01_couplers_BREADY(1),
S_AXI_bresp(1 downto 0) => xbar_to_m01_couplers_BRESP(1 downto 0),
S_AXI_bvalid(0) => xbar_to_m01_couplers_BVALID(0),
S_AXI_rdata(31 downto 0) => xbar_to_m01_couplers_RDATA(31 downto 0),
S_AXI_rlast(0) => xbar_to_m01_couplers_RLAST(0),
S_AXI_rready(0) => xbar_to_m01_couplers_RREADY(1),
S_AXI_rresp(1 downto 0) => xbar_to_m01_couplers_RRESP(1 downto 0),
S_AXI_rvalid(0) => xbar_to_m01_couplers_RVALID(0),
S_AXI_wdata(31 downto 0) => xbar_to_m01_couplers_WDATA(63 downto 32),
S_AXI_wlast(0) => xbar_to_m01_couplers_WLAST(1),
S_AXI_wready(0) => xbar_to_m01_couplers_WREADY(0),
S_AXI_wstrb(3 downto 0) => xbar_to_m01_couplers_WSTRB(7 downto 4),
S_AXI_wvalid(0) => xbar_to_m01_couplers_WVALID(1)
);
s00_couplers: entity work.s00_couplers_imp_1UTISAU
port map (
M_ACLK => processing_system7_0_axi_periph_ACLK_net,
M_ARESETN(0) => processing_system7_0_axi_periph_ARESETN_net(0),
M_AXI_araddr(31 downto 0) => s00_couplers_to_xbar_ARADDR(31 downto 0),
M_AXI_arburst(1 downto 0) => s00_couplers_to_xbar_ARBURST(1 downto 0),
M_AXI_arcache(3 downto 0) => s00_couplers_to_xbar_ARCACHE(3 downto 0),
M_AXI_arid(11 downto 0) => s00_couplers_to_xbar_ARID(11 downto 0),
M_AXI_arlen(7 downto 0) => s00_couplers_to_xbar_ARLEN(7 downto 0),
M_AXI_arlock(0) => s00_couplers_to_xbar_ARLOCK(0),
M_AXI_arprot(2 downto 0) => s00_couplers_to_xbar_ARPROT(2 downto 0),
M_AXI_arqos(3 downto 0) => s00_couplers_to_xbar_ARQOS(3 downto 0),
M_AXI_arready => s00_couplers_to_xbar_ARREADY(0),
M_AXI_arsize(2 downto 0) => s00_couplers_to_xbar_ARSIZE(2 downto 0),
M_AXI_arvalid => s00_couplers_to_xbar_ARVALID,
M_AXI_awaddr(31 downto 0) => s00_couplers_to_xbar_AWADDR(31 downto 0),
M_AXI_awburst(1 downto 0) => s00_couplers_to_xbar_AWBURST(1 downto 0),
M_AXI_awcache(3 downto 0) => s00_couplers_to_xbar_AWCACHE(3 downto 0),
M_AXI_awid(11 downto 0) => s00_couplers_to_xbar_AWID(11 downto 0),
M_AXI_awlen(7 downto 0) => s00_couplers_to_xbar_AWLEN(7 downto 0),
M_AXI_awlock(0) => s00_couplers_to_xbar_AWLOCK(0),
M_AXI_awprot(2 downto 0) => s00_couplers_to_xbar_AWPROT(2 downto 0),
M_AXI_awqos(3 downto 0) => s00_couplers_to_xbar_AWQOS(3 downto 0),
M_AXI_awready => s00_couplers_to_xbar_AWREADY(0),
M_AXI_awsize(2 downto 0) => s00_couplers_to_xbar_AWSIZE(2 downto 0),
M_AXI_awvalid => s00_couplers_to_xbar_AWVALID,
M_AXI_bid(11 downto 0) => s00_couplers_to_xbar_BID(11 downto 0),
M_AXI_bready => s00_couplers_to_xbar_BREADY,
M_AXI_bresp(1 downto 0) => s00_couplers_to_xbar_BRESP(1 downto 0),
M_AXI_bvalid => s00_couplers_to_xbar_BVALID(0),
M_AXI_rdata(31 downto 0) => s00_couplers_to_xbar_RDATA(31 downto 0),
M_AXI_rid(11 downto 0) => s00_couplers_to_xbar_RID(11 downto 0),
M_AXI_rlast => s00_couplers_to_xbar_RLAST(0),
M_AXI_rready => s00_couplers_to_xbar_RREADY,
M_AXI_rresp(1 downto 0) => s00_couplers_to_xbar_RRESP(1 downto 0),
M_AXI_rvalid => s00_couplers_to_xbar_RVALID(0),
M_AXI_wdata(31 downto 0) => s00_couplers_to_xbar_WDATA(31 downto 0),
M_AXI_wlast => s00_couplers_to_xbar_WLAST,
M_AXI_wready => s00_couplers_to_xbar_WREADY(0),
M_AXI_wstrb(3 downto 0) => s00_couplers_to_xbar_WSTRB(3 downto 0),
M_AXI_wvalid => s00_couplers_to_xbar_WVALID,
S_ACLK => S00_ACLK_1,
S_ARESETN(0) => S00_ARESETN_1(0),
S_AXI_araddr(31 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_ARADDR(31 downto 0),
S_AXI_arburst(1 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_ARBURST(1 downto 0),
S_AXI_arcache(3 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_ARCACHE(3 downto 0),
S_AXI_arid(11 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_ARID(11 downto 0),
S_AXI_arlen(3 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_ARLEN(3 downto 0),
S_AXI_arlock(1 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_ARLOCK(1 downto 0),
S_AXI_arprot(2 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_ARPROT(2 downto 0),
S_AXI_arqos(3 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_ARQOS(3 downto 0),
S_AXI_arready => processing_system7_0_axi_periph_to_s00_couplers_ARREADY,
S_AXI_arsize(2 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_ARSIZE(2 downto 0),
S_AXI_arvalid => processing_system7_0_axi_periph_to_s00_couplers_ARVALID,
S_AXI_awaddr(31 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_AWADDR(31 downto 0),
S_AXI_awburst(1 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_AWBURST(1 downto 0),
S_AXI_awcache(3 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_AWCACHE(3 downto 0),
S_AXI_awid(11 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_AWID(11 downto 0),
S_AXI_awlen(3 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_AWLEN(3 downto 0),
S_AXI_awlock(1 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_AWLOCK(1 downto 0),
S_AXI_awprot(2 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_AWPROT(2 downto 0),
S_AXI_awqos(3 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_AWQOS(3 downto 0),
S_AXI_awready => processing_system7_0_axi_periph_to_s00_couplers_AWREADY,
S_AXI_awsize(2 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_AWSIZE(2 downto 0),
S_AXI_awvalid => processing_system7_0_axi_periph_to_s00_couplers_AWVALID,
S_AXI_bid(11 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_BID(11 downto 0),
S_AXI_bready => processing_system7_0_axi_periph_to_s00_couplers_BREADY,
S_AXI_bresp(1 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_BRESP(1 downto 0),
S_AXI_bvalid => processing_system7_0_axi_periph_to_s00_couplers_BVALID,
S_AXI_rdata(31 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_RDATA(31 downto 0),
S_AXI_rid(11 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_RID(11 downto 0),
S_AXI_rlast => processing_system7_0_axi_periph_to_s00_couplers_RLAST,
S_AXI_rready => processing_system7_0_axi_periph_to_s00_couplers_RREADY,
S_AXI_rresp(1 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_RRESP(1 downto 0),
S_AXI_rvalid => processing_system7_0_axi_periph_to_s00_couplers_RVALID,
S_AXI_wdata(31 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_WDATA(31 downto 0),
S_AXI_wid(11 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_WID(11 downto 0),
S_AXI_wlast => processing_system7_0_axi_periph_to_s00_couplers_WLAST,
S_AXI_wready => processing_system7_0_axi_periph_to_s00_couplers_WREADY,
S_AXI_wstrb(3 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_WSTRB(3 downto 0),
S_AXI_wvalid => processing_system7_0_axi_periph_to_s00_couplers_WVALID
);
xbar: component base_zynq_design_xbar_0
port map (
aclk => processing_system7_0_axi_periph_ACLK_net,
aresetn => processing_system7_0_axi_periph_ARESETN_net(0),
m_axi_araddr(63 downto 32) => xbar_to_m01_couplers_ARADDR(63 downto 32),
m_axi_araddr(31 downto 0) => xbar_to_m00_couplers_ARADDR(31 downto 0),
m_axi_arburst(3 downto 2) => xbar_to_m01_couplers_ARBURST(3 downto 2),
m_axi_arburst(1 downto 0) => xbar_to_m00_couplers_ARBURST(1 downto 0),
m_axi_arcache(7 downto 4) => xbar_to_m01_couplers_ARCACHE(7 downto 4),
m_axi_arcache(3 downto 0) => xbar_to_m00_couplers_ARCACHE(3 downto 0),
m_axi_arlen(15 downto 8) => xbar_to_m01_couplers_ARLEN(15 downto 8),
m_axi_arlen(7 downto 0) => xbar_to_m00_couplers_ARLEN(7 downto 0),
m_axi_arlock(1) => xbar_to_m01_couplers_ARLOCK(1),
m_axi_arlock(0) => xbar_to_m00_couplers_ARLOCK(0),
m_axi_arprot(5 downto 3) => xbar_to_m01_couplers_ARPROT(5 downto 3),
m_axi_arprot(2 downto 0) => xbar_to_m00_couplers_ARPROT(2 downto 0),
m_axi_arqos(7 downto 4) => NLW_xbar_m_axi_arqos_UNCONNECTED(7 downto 4),
m_axi_arqos(3 downto 0) => xbar_to_m00_couplers_ARQOS(3 downto 0),
m_axi_arready(1) => xbar_to_m01_couplers_ARREADY(0),
m_axi_arready(0) => xbar_to_m00_couplers_ARREADY,
m_axi_arregion(7 downto 4) => NLW_xbar_m_axi_arregion_UNCONNECTED(7 downto 4),
m_axi_arregion(3 downto 0) => xbar_to_m00_couplers_ARREGION(3 downto 0),
m_axi_arsize(5 downto 3) => xbar_to_m01_couplers_ARSIZE(5 downto 3),
m_axi_arsize(2 downto 0) => xbar_to_m00_couplers_ARSIZE(2 downto 0),
m_axi_arvalid(1) => xbar_to_m01_couplers_ARVALID(1),
m_axi_arvalid(0) => xbar_to_m00_couplers_ARVALID(0),
m_axi_awaddr(63 downto 32) => xbar_to_m01_couplers_AWADDR(63 downto 32),
m_axi_awaddr(31 downto 0) => xbar_to_m00_couplers_AWADDR(31 downto 0),
m_axi_awburst(3 downto 2) => xbar_to_m01_couplers_AWBURST(3 downto 2),
m_axi_awburst(1 downto 0) => xbar_to_m00_couplers_AWBURST(1 downto 0),
m_axi_awcache(7 downto 4) => xbar_to_m01_couplers_AWCACHE(7 downto 4),
m_axi_awcache(3 downto 0) => xbar_to_m00_couplers_AWCACHE(3 downto 0),
m_axi_awlen(15 downto 8) => xbar_to_m01_couplers_AWLEN(15 downto 8),
m_axi_awlen(7 downto 0) => xbar_to_m00_couplers_AWLEN(7 downto 0),
m_axi_awlock(1) => xbar_to_m01_couplers_AWLOCK(1),
m_axi_awlock(0) => xbar_to_m00_couplers_AWLOCK(0),
m_axi_awprot(5 downto 3) => xbar_to_m01_couplers_AWPROT(5 downto 3),
m_axi_awprot(2 downto 0) => xbar_to_m00_couplers_AWPROT(2 downto 0),
m_axi_awqos(7 downto 4) => NLW_xbar_m_axi_awqos_UNCONNECTED(7 downto 4),
m_axi_awqos(3 downto 0) => xbar_to_m00_couplers_AWQOS(3 downto 0),
m_axi_awready(1) => xbar_to_m01_couplers_AWREADY(0),
m_axi_awready(0) => xbar_to_m00_couplers_AWREADY,
m_axi_awregion(7 downto 4) => NLW_xbar_m_axi_awregion_UNCONNECTED(7 downto 4),
m_axi_awregion(3 downto 0) => xbar_to_m00_couplers_AWREGION(3 downto 0),
m_axi_awsize(5 downto 3) => xbar_to_m01_couplers_AWSIZE(5 downto 3),
m_axi_awsize(2 downto 0) => xbar_to_m00_couplers_AWSIZE(2 downto 0),
m_axi_awvalid(1) => xbar_to_m01_couplers_AWVALID(1),
m_axi_awvalid(0) => xbar_to_m00_couplers_AWVALID(0),
m_axi_bready(1) => xbar_to_m01_couplers_BREADY(1),
m_axi_bready(0) => xbar_to_m00_couplers_BREADY(0),
m_axi_bresp(3 downto 2) => xbar_to_m01_couplers_BRESP(1 downto 0),
m_axi_bresp(1 downto 0) => xbar_to_m00_couplers_BRESP(1 downto 0),
m_axi_bvalid(1) => xbar_to_m01_couplers_BVALID(0),
m_axi_bvalid(0) => xbar_to_m00_couplers_BVALID,
m_axi_rdata(63 downto 32) => xbar_to_m01_couplers_RDATA(31 downto 0),
m_axi_rdata(31 downto 0) => xbar_to_m00_couplers_RDATA(31 downto 0),
m_axi_rlast(1) => xbar_to_m01_couplers_RLAST(0),
m_axi_rlast(0) => xbar_to_m00_couplers_RLAST,
m_axi_rready(1) => xbar_to_m01_couplers_RREADY(1),
m_axi_rready(0) => xbar_to_m00_couplers_RREADY(0),
m_axi_rresp(3 downto 2) => xbar_to_m01_couplers_RRESP(1 downto 0),
m_axi_rresp(1 downto 0) => xbar_to_m00_couplers_RRESP(1 downto 0),
m_axi_rvalid(1) => xbar_to_m01_couplers_RVALID(0),
m_axi_rvalid(0) => xbar_to_m00_couplers_RVALID,
m_axi_wdata(63 downto 32) => xbar_to_m01_couplers_WDATA(63 downto 32),
m_axi_wdata(31 downto 0) => xbar_to_m00_couplers_WDATA(31 downto 0),
m_axi_wlast(1) => xbar_to_m01_couplers_WLAST(1),
m_axi_wlast(0) => xbar_to_m00_couplers_WLAST(0),
m_axi_wready(1) => xbar_to_m01_couplers_WREADY(0),
m_axi_wready(0) => xbar_to_m00_couplers_WREADY,
m_axi_wstrb(7 downto 4) => xbar_to_m01_couplers_WSTRB(7 downto 4),
m_axi_wstrb(3 downto 0) => xbar_to_m00_couplers_WSTRB(3 downto 0),
m_axi_wvalid(1) => xbar_to_m01_couplers_WVALID(1),
m_axi_wvalid(0) => xbar_to_m00_couplers_WVALID(0),
s_axi_araddr(31 downto 0) => s00_couplers_to_xbar_ARADDR(31 downto 0),
s_axi_arburst(1 downto 0) => s00_couplers_to_xbar_ARBURST(1 downto 0),
s_axi_arcache(3 downto 0) => s00_couplers_to_xbar_ARCACHE(3 downto 0),
s_axi_arid(11 downto 0) => s00_couplers_to_xbar_ARID(11 downto 0),
s_axi_arlen(7 downto 0) => s00_couplers_to_xbar_ARLEN(7 downto 0),
s_axi_arlock(0) => s00_couplers_to_xbar_ARLOCK(0),
s_axi_arprot(2 downto 0) => s00_couplers_to_xbar_ARPROT(2 downto 0),
s_axi_arqos(3 downto 0) => s00_couplers_to_xbar_ARQOS(3 downto 0),
s_axi_arready(0) => s00_couplers_to_xbar_ARREADY(0),
s_axi_arsize(2 downto 0) => s00_couplers_to_xbar_ARSIZE(2 downto 0),
s_axi_arvalid(0) => s00_couplers_to_xbar_ARVALID,
s_axi_awaddr(31 downto 0) => s00_couplers_to_xbar_AWADDR(31 downto 0),
s_axi_awburst(1 downto 0) => s00_couplers_to_xbar_AWBURST(1 downto 0),
s_axi_awcache(3 downto 0) => s00_couplers_to_xbar_AWCACHE(3 downto 0),
s_axi_awid(11 downto 0) => s00_couplers_to_xbar_AWID(11 downto 0),
s_axi_awlen(7 downto 0) => s00_couplers_to_xbar_AWLEN(7 downto 0),
s_axi_awlock(0) => s00_couplers_to_xbar_AWLOCK(0),
s_axi_awprot(2 downto 0) => s00_couplers_to_xbar_AWPROT(2 downto 0),
s_axi_awqos(3 downto 0) => s00_couplers_to_xbar_AWQOS(3 downto 0),
s_axi_awready(0) => s00_couplers_to_xbar_AWREADY(0),
s_axi_awsize(2 downto 0) => s00_couplers_to_xbar_AWSIZE(2 downto 0),
s_axi_awvalid(0) => s00_couplers_to_xbar_AWVALID,
s_axi_bid(11 downto 0) => s00_couplers_to_xbar_BID(11 downto 0),
s_axi_bready(0) => s00_couplers_to_xbar_BREADY,
s_axi_bresp(1 downto 0) => s00_couplers_to_xbar_BRESP(1 downto 0),
s_axi_bvalid(0) => s00_couplers_to_xbar_BVALID(0),
s_axi_rdata(31 downto 0) => s00_couplers_to_xbar_RDATA(31 downto 0),
s_axi_rid(11 downto 0) => s00_couplers_to_xbar_RID(11 downto 0),
s_axi_rlast(0) => s00_couplers_to_xbar_RLAST(0),
s_axi_rready(0) => s00_couplers_to_xbar_RREADY,
s_axi_rresp(1 downto 0) => s00_couplers_to_xbar_RRESP(1 downto 0),
s_axi_rvalid(0) => s00_couplers_to_xbar_RVALID(0),
s_axi_wdata(31 downto 0) => s00_couplers_to_xbar_WDATA(31 downto 0),
s_axi_wlast(0) => s00_couplers_to_xbar_WLAST,
s_axi_wready(0) => s00_couplers_to_xbar_WREADY(0),
s_axi_wstrb(3 downto 0) => s00_couplers_to_xbar_WSTRB(3 downto 0),
s_axi_wvalid(0) => s00_couplers_to_xbar_WVALID
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity base_zynq_design is
port (
DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_cas_n : inout STD_LOGIC;
DDR_ck_n : inout STD_LOGIC;
DDR_ck_p : inout STD_LOGIC;
DDR_cke : inout STD_LOGIC;
DDR_cs_n : inout STD_LOGIC;
DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_odt : inout STD_LOGIC;
DDR_ras_n : inout STD_LOGIC;
DDR_reset_n : inout STD_LOGIC;
DDR_we_n : inout STD_LOGIC;
FIXED_IO_ddr_vrn : inout STD_LOGIC;
FIXED_IO_ddr_vrp : inout STD_LOGIC;
FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
FIXED_IO_ps_clk : inout STD_LOGIC;
FIXED_IO_ps_porb : inout STD_LOGIC;
FIXED_IO_ps_srstb : inout STD_LOGIC;
btns_5bits_tri_i : in STD_LOGIC_VECTOR ( 4 downto 0 );
leds_8bits_tri_o : out STD_LOGIC_VECTOR ( 7 downto 0 )
);
end base_zynq_design;
architecture STRUCTURE of base_zynq_design is
component base_zynq_design_processing_system7_0_0 is
port (
ENET0_PTP_DELAY_REQ_RX : out STD_LOGIC;
ENET0_PTP_DELAY_REQ_TX : out STD_LOGIC;
ENET0_PTP_PDELAY_REQ_RX : out STD_LOGIC;
ENET0_PTP_PDELAY_REQ_TX : out STD_LOGIC;
ENET0_PTP_PDELAY_RESP_RX : out STD_LOGIC;
ENET0_PTP_PDELAY_RESP_TX : out STD_LOGIC;
ENET0_PTP_SYNC_FRAME_RX : out STD_LOGIC;
ENET0_PTP_SYNC_FRAME_TX : out STD_LOGIC;
ENET0_SOF_RX : out STD_LOGIC;
ENET0_SOF_TX : out STD_LOGIC;
I2C1_SDA_I : in STD_LOGIC;
I2C1_SDA_O : out STD_LOGIC;
I2C1_SDA_T : out STD_LOGIC;
I2C1_SCL_I : in STD_LOGIC;
I2C1_SCL_O : out STD_LOGIC;
I2C1_SCL_T : out STD_LOGIC;
TTC0_WAVE0_OUT : out STD_LOGIC;
TTC0_WAVE1_OUT : out STD_LOGIC;
TTC0_WAVE2_OUT : out STD_LOGIC;
USB0_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 );
USB0_VBUS_PWRSELECT : out STD_LOGIC;
USB0_VBUS_PWRFAULT : in STD_LOGIC;
M_AXI_GP0_ARVALID : out STD_LOGIC;
M_AXI_GP0_AWVALID : out STD_LOGIC;
M_AXI_GP0_BREADY : out STD_LOGIC;
M_AXI_GP0_RREADY : out STD_LOGIC;
M_AXI_GP0_WLAST : out STD_LOGIC;
M_AXI_GP0_WVALID : out STD_LOGIC;
M_AXI_GP0_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_WID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ACLK : in STD_LOGIC;
M_AXI_GP0_ARREADY : in STD_LOGIC;
M_AXI_GP0_AWREADY : in STD_LOGIC;
M_AXI_GP0_BVALID : in STD_LOGIC;
M_AXI_GP0_RLAST : in STD_LOGIC;
M_AXI_GP0_RVALID : in STD_LOGIC;
M_AXI_GP0_WREADY : in STD_LOGIC;
M_AXI_GP0_BID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_RID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
IRQ_F2P : in STD_LOGIC_VECTOR ( 0 to 0 );
DMA0_DATYPE : out STD_LOGIC_VECTOR ( 1 downto 0 );
DMA0_DAVALID : out STD_LOGIC;
DMA0_DRREADY : out STD_LOGIC;
DMA2_DATYPE : out STD_LOGIC_VECTOR ( 1 downto 0 );
DMA2_DAVALID : out STD_LOGIC;
DMA2_DRREADY : out STD_LOGIC;
DMA0_ACLK : in STD_LOGIC;
DMA0_DAREADY : in STD_LOGIC;
DMA0_DRLAST : in STD_LOGIC;
DMA0_DRVALID : in STD_LOGIC;
DMA2_ACLK : in STD_LOGIC;
DMA2_DAREADY : in STD_LOGIC;
DMA2_DRLAST : in STD_LOGIC;
DMA2_DRVALID : in STD_LOGIC;
DMA0_DRTYPE : in STD_LOGIC_VECTOR ( 1 downto 0 );
DMA2_DRTYPE : in STD_LOGIC_VECTOR ( 1 downto 0 );
FCLK_CLK0 : out STD_LOGIC;
FCLK_CLK1 : out STD_LOGIC;
FCLK_CLK2 : out STD_LOGIC;
FCLK_RESET0_N : out STD_LOGIC;
FCLK_RESET1_N : out STD_LOGIC;
FCLK_RESET2_N : out STD_LOGIC;
MIO : inout STD_LOGIC_VECTOR ( 53 downto 0 );
DDR_CAS_n : inout STD_LOGIC;
DDR_CKE : inout STD_LOGIC;
DDR_Clk_n : inout STD_LOGIC;
DDR_Clk : inout STD_LOGIC;
DDR_CS_n : inout STD_LOGIC;
DDR_DRSTB : inout STD_LOGIC;
DDR_ODT : inout STD_LOGIC;
DDR_RAS_n : inout STD_LOGIC;
DDR_WEB : inout STD_LOGIC;
DDR_BankAddr : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_Addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_VRN : inout STD_LOGIC;
DDR_VRP : inout STD_LOGIC;
DDR_DM : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQ : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_DQS_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQS : inout STD_LOGIC_VECTOR ( 3 downto 0 );
PS_SRSTB : inout STD_LOGIC;
PS_CLK : inout STD_LOGIC;
PS_PORB : inout STD_LOGIC
);
end component base_zynq_design_processing_system7_0_0;
component base_zynq_design_axi_gpio_0_0 is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
ip2intc_irpt : out STD_LOGIC;
gpio_io_o : out STD_LOGIC_VECTOR ( 7 downto 0 );
gpio2_io_i : in STD_LOGIC_VECTOR ( 4 downto 0 )
);
end component base_zynq_design_axi_gpio_0_0;
component base_zynq_design_blk_mem_gen_0_0 is
port (
clka : in STD_LOGIC;
rsta : in STD_LOGIC;
ena : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 3 downto 0 );
addra : in STD_LOGIC_VECTOR ( 31 downto 0 );
dina : in STD_LOGIC_VECTOR ( 31 downto 0 );
douta : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
end component base_zynq_design_blk_mem_gen_0_0;
component base_zynq_design_axi_bram_ctrl_0_0 is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 12 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC;
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 12 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC;
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
bram_rst_a : out STD_LOGIC;
bram_clk_a : out STD_LOGIC;
bram_en_a : out STD_LOGIC;
bram_we_a : out STD_LOGIC_VECTOR ( 3 downto 0 );
bram_addr_a : out STD_LOGIC_VECTOR ( 12 downto 0 );
bram_wrdata_a : out STD_LOGIC_VECTOR ( 31 downto 0 );
bram_rddata_a : in STD_LOGIC_VECTOR ( 31 downto 0 )
);
end component base_zynq_design_axi_bram_ctrl_0_0;
component base_zynq_design_rst_processing_system7_0_100M_0 is
port (
slowest_sync_clk : in STD_LOGIC;
ext_reset_in : in STD_LOGIC;
aux_reset_in : in STD_LOGIC;
mb_debug_sys_rst : in STD_LOGIC;
dcm_locked : in STD_LOGIC;
mb_reset : out STD_LOGIC;
bus_struct_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
interconnect_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 )
);
end component base_zynq_design_rst_processing_system7_0_100M_0;
component base_zynq_design_xlconcat_0_0 is
port (
In0 : in STD_LOGIC_VECTOR ( 0 to 0 );
dout : out STD_LOGIC_VECTOR ( 0 to 0 )
);
end component base_zynq_design_xlconcat_0_0;
signal GND_1 : STD_LOGIC;
signal VCC_1 : STD_LOGIC;
signal axi_bram_ctrl_0_BRAM_PORTA_ADDR : STD_LOGIC_VECTOR ( 12 downto 0 );
signal axi_bram_ctrl_0_BRAM_PORTA_CLK : STD_LOGIC;
signal axi_bram_ctrl_0_BRAM_PORTA_DIN : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_bram_ctrl_0_BRAM_PORTA_DOUT : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_bram_ctrl_0_BRAM_PORTA_EN : STD_LOGIC;
signal axi_bram_ctrl_0_BRAM_PORTA_RST : STD_LOGIC;
signal axi_bram_ctrl_0_BRAM_PORTA_WE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_gpio_0_GPIO2_TRI_I : STD_LOGIC_VECTOR ( 4 downto 0 );
signal axi_gpio_0_GPIO_TRI_O : STD_LOGIC_VECTOR ( 7 downto 0 );
signal axi_gpio_0_ip2intc_irpt : STD_LOGIC;
signal processing_system7_0_DDR_ADDR : STD_LOGIC_VECTOR ( 14 downto 0 );
signal processing_system7_0_DDR_BA : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_DDR_CAS_N : STD_LOGIC;
signal processing_system7_0_DDR_CKE : STD_LOGIC;
signal processing_system7_0_DDR_CK_N : STD_LOGIC;
signal processing_system7_0_DDR_CK_P : STD_LOGIC;
signal processing_system7_0_DDR_CS_N : STD_LOGIC;
signal processing_system7_0_DDR_DM : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_DDR_DQ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_DDR_DQS_N : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_DDR_DQS_P : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_DDR_ODT : STD_LOGIC;
signal processing_system7_0_DDR_RAS_N : STD_LOGIC;
signal processing_system7_0_DDR_RESET_N : STD_LOGIC;
signal processing_system7_0_DDR_WE_N : STD_LOGIC;
signal processing_system7_0_FCLK_CLK0 : STD_LOGIC;
signal processing_system7_0_FCLK_CLK1 : STD_LOGIC;
signal processing_system7_0_FCLK_RESET0_N : STD_LOGIC;
signal processing_system7_0_FIXED_IO_DDR_VRN : STD_LOGIC;
signal processing_system7_0_FIXED_IO_DDR_VRP : STD_LOGIC;
signal processing_system7_0_FIXED_IO_MIO : STD_LOGIC_VECTOR ( 53 downto 0 );
signal processing_system7_0_FIXED_IO_PS_CLK : STD_LOGIC;
signal processing_system7_0_FIXED_IO_PS_PORB : STD_LOGIC;
signal processing_system7_0_FIXED_IO_PS_SRSTB : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARREADY : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARVALID : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWREADY : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWVALID : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_BID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_M_AXI_GP0_BREADY : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_M_AXI_GP0_BVALID : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_M_AXI_GP0_RID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_M_AXI_GP0_RLAST : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_RREADY : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_M_AXI_GP0_RVALID : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_M_AXI_GP0_WID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_M_AXI_GP0_WLAST : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_WREADY : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP0_WVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M00_AXI_ARADDR : STD_LOGIC_VECTOR ( 8 downto 0 );
signal processing_system7_0_axi_periph_M00_AXI_ARREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M00_AXI_ARVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M00_AXI_AWADDR : STD_LOGIC_VECTOR ( 8 downto 0 );
signal processing_system7_0_axi_periph_M00_AXI_AWREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M00_AXI_AWVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M00_AXI_BREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M00_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_M00_AXI_BVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M00_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M00_AXI_RREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M00_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_M00_AXI_RVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M00_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M00_AXI_WREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M00_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_M00_AXI_WVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M01_AXI_ARADDR : STD_LOGIC_VECTOR ( 12 downto 0 );
signal processing_system7_0_axi_periph_M01_AXI_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_M01_AXI_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_M01_AXI_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal processing_system7_0_axi_periph_M01_AXI_ARLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal processing_system7_0_axi_periph_M01_AXI_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_axi_periph_M01_AXI_ARREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M01_AXI_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_axi_periph_M01_AXI_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal processing_system7_0_axi_periph_M01_AXI_AWADDR : STD_LOGIC_VECTOR ( 12 downto 0 );
signal processing_system7_0_axi_periph_M01_AXI_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_M01_AXI_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_M01_AXI_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal processing_system7_0_axi_periph_M01_AXI_AWLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal processing_system7_0_axi_periph_M01_AXI_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_axi_periph_M01_AXI_AWREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M01_AXI_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_axi_periph_M01_AXI_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal processing_system7_0_axi_periph_M01_AXI_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal processing_system7_0_axi_periph_M01_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_M01_AXI_BVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M01_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M01_AXI_RLAST : STD_LOGIC;
signal processing_system7_0_axi_periph_M01_AXI_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal processing_system7_0_axi_periph_M01_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_M01_AXI_RVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M01_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M01_AXI_WLAST : STD_LOGIC_VECTOR ( 0 to 0 );
signal processing_system7_0_axi_periph_M01_AXI_WREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M01_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_M01_AXI_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal rst_processing_system7_0_100M_interconnect_aresetn : STD_LOGIC_VECTOR ( 0 to 0 );
signal rst_processing_system7_0_100M_peripheral_aresetn : STD_LOGIC_VECTOR ( 0 to 0 );
signal xlconcat_0_dout : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_blk_mem_gen_0_addra_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 13 );
signal NLW_processing_system7_0_DMA0_DAVALID_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_DMA0_DRREADY_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_DMA2_DAVALID_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_DMA2_DRREADY_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_ENET0_PTP_DELAY_REQ_RX_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_ENET0_PTP_DELAY_REQ_TX_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_ENET0_PTP_PDELAY_REQ_RX_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_ENET0_PTP_PDELAY_REQ_TX_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_ENET0_PTP_PDELAY_RESP_RX_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_ENET0_PTP_PDELAY_RESP_TX_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_ENET0_PTP_SYNC_FRAME_RX_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_ENET0_PTP_SYNC_FRAME_TX_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_ENET0_SOF_RX_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_ENET0_SOF_TX_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_FCLK_CLK2_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_FCLK_RESET1_N_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_FCLK_RESET2_N_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_I2C1_SCL_O_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_I2C1_SCL_T_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_I2C1_SDA_O_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_I2C1_SDA_T_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_TTC0_WAVE0_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_TTC0_WAVE1_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_TTC0_WAVE2_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_USB0_VBUS_PWRSELECT_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_DMA0_DATYPE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_processing_system7_0_DMA2_DATYPE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_processing_system7_0_USB0_PORT_INDCTL_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_rst_processing_system7_0_50M_mb_reset_UNCONNECTED : STD_LOGIC;
signal NLW_rst_processing_system7_0_50M_bus_struct_reset_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_rst_processing_system7_0_50M_peripheral_reset_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
attribute BMM_INFO_ADDRESS_SPACE : string;
attribute BMM_INFO_ADDRESS_SPACE of axi_bram_ctrl_0 : label is "byte 0x40000000 32 > base_zynq_design blk_mem_gen_0";
attribute KEEP_HIERARCHY : string;
attribute KEEP_HIERARCHY of axi_bram_ctrl_0 : label is "yes";
attribute BMM_INFO_PROCESSOR : string;
attribute BMM_INFO_PROCESSOR of processing_system7_0 : label is "ARM > base_zynq_design axi_bram_ctrl_0";
attribute KEEP_HIERARCHY of processing_system7_0 : label is "yes";
begin
axi_gpio_0_GPIO2_TRI_I(4 downto 0) <= btns_5bits_tri_i(4 downto 0);
leds_8bits_tri_o(7 downto 0) <= axi_gpio_0_GPIO_TRI_O(7 downto 0);
GND: unisim.vcomponents.GND
port map (
G => GND_1
);
VCC: unisim.vcomponents.VCC
port map (
P => VCC_1
);
axi_bram_ctrl_0: component base_zynq_design_axi_bram_ctrl_0_0
port map (
bram_addr_a(12 downto 0) => axi_bram_ctrl_0_BRAM_PORTA_ADDR(12 downto 0),
bram_clk_a => axi_bram_ctrl_0_BRAM_PORTA_CLK,
bram_en_a => axi_bram_ctrl_0_BRAM_PORTA_EN,
bram_rddata_a(31 downto 0) => axi_bram_ctrl_0_BRAM_PORTA_DOUT(31 downto 0),
bram_rst_a => axi_bram_ctrl_0_BRAM_PORTA_RST,
bram_we_a(3 downto 0) => axi_bram_ctrl_0_BRAM_PORTA_WE(3 downto 0),
bram_wrdata_a(31 downto 0) => axi_bram_ctrl_0_BRAM_PORTA_DIN(31 downto 0),
s_axi_aclk => processing_system7_0_FCLK_CLK0,
s_axi_araddr(12 downto 0) => processing_system7_0_axi_periph_M01_AXI_ARADDR(12 downto 0),
s_axi_arburst(1 downto 0) => processing_system7_0_axi_periph_M01_AXI_ARBURST(1 downto 0),
s_axi_arcache(3 downto 0) => processing_system7_0_axi_periph_M01_AXI_ARCACHE(3 downto 0),
s_axi_aresetn => rst_processing_system7_0_100M_peripheral_aresetn(0),
s_axi_arlen(7 downto 0) => processing_system7_0_axi_periph_M01_AXI_ARLEN(7 downto 0),
s_axi_arlock => processing_system7_0_axi_periph_M01_AXI_ARLOCK(0),
s_axi_arprot(2 downto 0) => processing_system7_0_axi_periph_M01_AXI_ARPROT(2 downto 0),
s_axi_arready => processing_system7_0_axi_periph_M01_AXI_ARREADY,
s_axi_arsize(2 downto 0) => processing_system7_0_axi_periph_M01_AXI_ARSIZE(2 downto 0),
s_axi_arvalid => processing_system7_0_axi_periph_M01_AXI_ARVALID(0),
s_axi_awaddr(12 downto 0) => processing_system7_0_axi_periph_M01_AXI_AWADDR(12 downto 0),
s_axi_awburst(1 downto 0) => processing_system7_0_axi_periph_M01_AXI_AWBURST(1 downto 0),
s_axi_awcache(3 downto 0) => processing_system7_0_axi_periph_M01_AXI_AWCACHE(3 downto 0),
s_axi_awlen(7 downto 0) => processing_system7_0_axi_periph_M01_AXI_AWLEN(7 downto 0),
s_axi_awlock => processing_system7_0_axi_periph_M01_AXI_AWLOCK(0),
s_axi_awprot(2 downto 0) => processing_system7_0_axi_periph_M01_AXI_AWPROT(2 downto 0),
s_axi_awready => processing_system7_0_axi_periph_M01_AXI_AWREADY,
s_axi_awsize(2 downto 0) => processing_system7_0_axi_periph_M01_AXI_AWSIZE(2 downto 0),
s_axi_awvalid => processing_system7_0_axi_periph_M01_AXI_AWVALID(0),
s_axi_bready => processing_system7_0_axi_periph_M01_AXI_BREADY(0),
s_axi_bresp(1 downto 0) => processing_system7_0_axi_periph_M01_AXI_BRESP(1 downto 0),
s_axi_bvalid => processing_system7_0_axi_periph_M01_AXI_BVALID,
s_axi_rdata(31 downto 0) => processing_system7_0_axi_periph_M01_AXI_RDATA(31 downto 0),
s_axi_rlast => processing_system7_0_axi_periph_M01_AXI_RLAST,
s_axi_rready => processing_system7_0_axi_periph_M01_AXI_RREADY(0),
s_axi_rresp(1 downto 0) => processing_system7_0_axi_periph_M01_AXI_RRESP(1 downto 0),
s_axi_rvalid => processing_system7_0_axi_periph_M01_AXI_RVALID,
s_axi_wdata(31 downto 0) => processing_system7_0_axi_periph_M01_AXI_WDATA(31 downto 0),
s_axi_wlast => processing_system7_0_axi_periph_M01_AXI_WLAST(0),
s_axi_wready => processing_system7_0_axi_periph_M01_AXI_WREADY,
s_axi_wstrb(3 downto 0) => processing_system7_0_axi_periph_M01_AXI_WSTRB(3 downto 0),
s_axi_wvalid => processing_system7_0_axi_periph_M01_AXI_WVALID(0)
);
axi_gpio_0: component base_zynq_design_axi_gpio_0_0
port map (
gpio2_io_i(4 downto 0) => axi_gpio_0_GPIO2_TRI_I(4 downto 0),
gpio_io_o(7 downto 0) => axi_gpio_0_GPIO_TRI_O(7 downto 0),
ip2intc_irpt => axi_gpio_0_ip2intc_irpt,
s_axi_aclk => processing_system7_0_FCLK_CLK0,
s_axi_araddr(8 downto 0) => processing_system7_0_axi_periph_M00_AXI_ARADDR(8 downto 0),
s_axi_aresetn => rst_processing_system7_0_100M_peripheral_aresetn(0),
s_axi_arready => processing_system7_0_axi_periph_M00_AXI_ARREADY,
s_axi_arvalid => processing_system7_0_axi_periph_M00_AXI_ARVALID,
s_axi_awaddr(8 downto 0) => processing_system7_0_axi_periph_M00_AXI_AWADDR(8 downto 0),
s_axi_awready => processing_system7_0_axi_periph_M00_AXI_AWREADY,
s_axi_awvalid => processing_system7_0_axi_periph_M00_AXI_AWVALID,
s_axi_bready => processing_system7_0_axi_periph_M00_AXI_BREADY,
s_axi_bresp(1 downto 0) => processing_system7_0_axi_periph_M00_AXI_BRESP(1 downto 0),
s_axi_bvalid => processing_system7_0_axi_periph_M00_AXI_BVALID,
s_axi_rdata(31 downto 0) => processing_system7_0_axi_periph_M00_AXI_RDATA(31 downto 0),
s_axi_rready => processing_system7_0_axi_periph_M00_AXI_RREADY,
s_axi_rresp(1 downto 0) => processing_system7_0_axi_periph_M00_AXI_RRESP(1 downto 0),
s_axi_rvalid => processing_system7_0_axi_periph_M00_AXI_RVALID,
s_axi_wdata(31 downto 0) => processing_system7_0_axi_periph_M00_AXI_WDATA(31 downto 0),
s_axi_wready => processing_system7_0_axi_periph_M00_AXI_WREADY,
s_axi_wstrb(3 downto 0) => processing_system7_0_axi_periph_M00_AXI_WSTRB(3 downto 0),
s_axi_wvalid => processing_system7_0_axi_periph_M00_AXI_WVALID
);
blk_mem_gen_0: component base_zynq_design_blk_mem_gen_0_0
port map (
addra(31 downto 13) => NLW_blk_mem_gen_0_addra_UNCONNECTED(31 downto 13),
addra(12 downto 0) => axi_bram_ctrl_0_BRAM_PORTA_ADDR(12 downto 0),
clka => axi_bram_ctrl_0_BRAM_PORTA_CLK,
dina(31 downto 0) => axi_bram_ctrl_0_BRAM_PORTA_DIN(31 downto 0),
douta(31 downto 0) => axi_bram_ctrl_0_BRAM_PORTA_DOUT(31 downto 0),
ena => axi_bram_ctrl_0_BRAM_PORTA_EN,
rsta => axi_bram_ctrl_0_BRAM_PORTA_RST,
wea(3 downto 0) => axi_bram_ctrl_0_BRAM_PORTA_WE(3 downto 0)
);
processing_system7_0: component base_zynq_design_processing_system7_0_0
port map (
DDR_Addr(14 downto 0) => DDR_addr(14 downto 0),
DDR_BankAddr(2 downto 0) => DDR_ba(2 downto 0),
DDR_CAS_n => DDR_cas_n,
DDR_CKE => DDR_cke,
DDR_CS_n => DDR_cs_n,
DDR_Clk => DDR_ck_p,
DDR_Clk_n => DDR_ck_n,
DDR_DM(3 downto 0) => DDR_dm(3 downto 0),
DDR_DQ(31 downto 0) => DDR_dq(31 downto 0),
DDR_DQS(3 downto 0) => DDR_dqs_p(3 downto 0),
DDR_DQS_n(3 downto 0) => DDR_dqs_n(3 downto 0),
DDR_DRSTB => DDR_reset_n,
DDR_ODT => DDR_odt,
DDR_RAS_n => DDR_ras_n,
DDR_VRN => FIXED_IO_ddr_vrn,
DDR_VRP => FIXED_IO_ddr_vrp,
DDR_WEB => DDR_we_n,
DMA0_ACLK => processing_system7_0_FCLK_CLK1,
DMA0_DAREADY => GND_1,
DMA0_DATYPE(1 downto 0) => NLW_processing_system7_0_DMA0_DATYPE_UNCONNECTED(1 downto 0),
DMA0_DAVALID => NLW_processing_system7_0_DMA0_DAVALID_UNCONNECTED,
DMA0_DRLAST => GND_1,
DMA0_DRREADY => NLW_processing_system7_0_DMA0_DRREADY_UNCONNECTED,
DMA0_DRTYPE(1) => GND_1,
DMA0_DRTYPE(0) => GND_1,
DMA0_DRVALID => GND_1,
DMA2_ACLK => processing_system7_0_FCLK_CLK1,
DMA2_DAREADY => GND_1,
DMA2_DATYPE(1 downto 0) => NLW_processing_system7_0_DMA2_DATYPE_UNCONNECTED(1 downto 0),
DMA2_DAVALID => NLW_processing_system7_0_DMA2_DAVALID_UNCONNECTED,
DMA2_DRLAST => GND_1,
DMA2_DRREADY => NLW_processing_system7_0_DMA2_DRREADY_UNCONNECTED,
DMA2_DRTYPE(1) => GND_1,
DMA2_DRTYPE(0) => GND_1,
DMA2_DRVALID => GND_1,
ENET0_PTP_DELAY_REQ_RX => NLW_processing_system7_0_ENET0_PTP_DELAY_REQ_RX_UNCONNECTED,
ENET0_PTP_DELAY_REQ_TX => NLW_processing_system7_0_ENET0_PTP_DELAY_REQ_TX_UNCONNECTED,
ENET0_PTP_PDELAY_REQ_RX => NLW_processing_system7_0_ENET0_PTP_PDELAY_REQ_RX_UNCONNECTED,
ENET0_PTP_PDELAY_REQ_TX => NLW_processing_system7_0_ENET0_PTP_PDELAY_REQ_TX_UNCONNECTED,
ENET0_PTP_PDELAY_RESP_RX => NLW_processing_system7_0_ENET0_PTP_PDELAY_RESP_RX_UNCONNECTED,
ENET0_PTP_PDELAY_RESP_TX => NLW_processing_system7_0_ENET0_PTP_PDELAY_RESP_TX_UNCONNECTED,
ENET0_PTP_SYNC_FRAME_RX => NLW_processing_system7_0_ENET0_PTP_SYNC_FRAME_RX_UNCONNECTED,
ENET0_PTP_SYNC_FRAME_TX => NLW_processing_system7_0_ENET0_PTP_SYNC_FRAME_TX_UNCONNECTED,
ENET0_SOF_RX => NLW_processing_system7_0_ENET0_SOF_RX_UNCONNECTED,
ENET0_SOF_TX => NLW_processing_system7_0_ENET0_SOF_TX_UNCONNECTED,
FCLK_CLK0 => processing_system7_0_FCLK_CLK0,
FCLK_CLK1 => processing_system7_0_FCLK_CLK1,
FCLK_CLK2 => NLW_processing_system7_0_FCLK_CLK2_UNCONNECTED,
FCLK_RESET0_N => processing_system7_0_FCLK_RESET0_N,
FCLK_RESET1_N => NLW_processing_system7_0_FCLK_RESET1_N_UNCONNECTED,
FCLK_RESET2_N => NLW_processing_system7_0_FCLK_RESET2_N_UNCONNECTED,
I2C1_SCL_I => GND_1,
I2C1_SCL_O => NLW_processing_system7_0_I2C1_SCL_O_UNCONNECTED,
I2C1_SCL_T => NLW_processing_system7_0_I2C1_SCL_T_UNCONNECTED,
I2C1_SDA_I => GND_1,
I2C1_SDA_O => NLW_processing_system7_0_I2C1_SDA_O_UNCONNECTED,
I2C1_SDA_T => NLW_processing_system7_0_I2C1_SDA_T_UNCONNECTED,
IRQ_F2P(0) => xlconcat_0_dout(0),
MIO(53 downto 0) => FIXED_IO_mio(53 downto 0),
M_AXI_GP0_ACLK => processing_system7_0_FCLK_CLK0,
M_AXI_GP0_ARADDR(31 downto 0) => processing_system7_0_M_AXI_GP0_ARADDR(31 downto 0),
M_AXI_GP0_ARBURST(1 downto 0) => processing_system7_0_M_AXI_GP0_ARBURST(1 downto 0),
M_AXI_GP0_ARCACHE(3 downto 0) => processing_system7_0_M_AXI_GP0_ARCACHE(3 downto 0),
M_AXI_GP0_ARID(11 downto 0) => processing_system7_0_M_AXI_GP0_ARID(11 downto 0),
M_AXI_GP0_ARLEN(3 downto 0) => processing_system7_0_M_AXI_GP0_ARLEN(3 downto 0),
M_AXI_GP0_ARLOCK(1 downto 0) => processing_system7_0_M_AXI_GP0_ARLOCK(1 downto 0),
M_AXI_GP0_ARPROT(2 downto 0) => processing_system7_0_M_AXI_GP0_ARPROT(2 downto 0),
M_AXI_GP0_ARQOS(3 downto 0) => processing_system7_0_M_AXI_GP0_ARQOS(3 downto 0),
M_AXI_GP0_ARREADY => processing_system7_0_M_AXI_GP0_ARREADY,
M_AXI_GP0_ARSIZE(2 downto 0) => processing_system7_0_M_AXI_GP0_ARSIZE(2 downto 0),
M_AXI_GP0_ARVALID => processing_system7_0_M_AXI_GP0_ARVALID,
M_AXI_GP0_AWADDR(31 downto 0) => processing_system7_0_M_AXI_GP0_AWADDR(31 downto 0),
M_AXI_GP0_AWBURST(1 downto 0) => processing_system7_0_M_AXI_GP0_AWBURST(1 downto 0),
M_AXI_GP0_AWCACHE(3 downto 0) => processing_system7_0_M_AXI_GP0_AWCACHE(3 downto 0),
M_AXI_GP0_AWID(11 downto 0) => processing_system7_0_M_AXI_GP0_AWID(11 downto 0),
M_AXI_GP0_AWLEN(3 downto 0) => processing_system7_0_M_AXI_GP0_AWLEN(3 downto 0),
M_AXI_GP0_AWLOCK(1 downto 0) => processing_system7_0_M_AXI_GP0_AWLOCK(1 downto 0),
M_AXI_GP0_AWPROT(2 downto 0) => processing_system7_0_M_AXI_GP0_AWPROT(2 downto 0),
M_AXI_GP0_AWQOS(3 downto 0) => processing_system7_0_M_AXI_GP0_AWQOS(3 downto 0),
M_AXI_GP0_AWREADY => processing_system7_0_M_AXI_GP0_AWREADY,
M_AXI_GP0_AWSIZE(2 downto 0) => processing_system7_0_M_AXI_GP0_AWSIZE(2 downto 0),
M_AXI_GP0_AWVALID => processing_system7_0_M_AXI_GP0_AWVALID,
M_AXI_GP0_BID(11 downto 0) => processing_system7_0_M_AXI_GP0_BID(11 downto 0),
M_AXI_GP0_BREADY => processing_system7_0_M_AXI_GP0_BREADY,
M_AXI_GP0_BRESP(1 downto 0) => processing_system7_0_M_AXI_GP0_BRESP(1 downto 0),
M_AXI_GP0_BVALID => processing_system7_0_M_AXI_GP0_BVALID,
M_AXI_GP0_RDATA(31 downto 0) => processing_system7_0_M_AXI_GP0_RDATA(31 downto 0),
M_AXI_GP0_RID(11 downto 0) => processing_system7_0_M_AXI_GP0_RID(11 downto 0),
M_AXI_GP0_RLAST => processing_system7_0_M_AXI_GP0_RLAST,
M_AXI_GP0_RREADY => processing_system7_0_M_AXI_GP0_RREADY,
M_AXI_GP0_RRESP(1 downto 0) => processing_system7_0_M_AXI_GP0_RRESP(1 downto 0),
M_AXI_GP0_RVALID => processing_system7_0_M_AXI_GP0_RVALID,
M_AXI_GP0_WDATA(31 downto 0) => processing_system7_0_M_AXI_GP0_WDATA(31 downto 0),
M_AXI_GP0_WID(11 downto 0) => processing_system7_0_M_AXI_GP0_WID(11 downto 0),
M_AXI_GP0_WLAST => processing_system7_0_M_AXI_GP0_WLAST,
M_AXI_GP0_WREADY => processing_system7_0_M_AXI_GP0_WREADY,
M_AXI_GP0_WSTRB(3 downto 0) => processing_system7_0_M_AXI_GP0_WSTRB(3 downto 0),
M_AXI_GP0_WVALID => processing_system7_0_M_AXI_GP0_WVALID,
PS_CLK => FIXED_IO_ps_clk,
PS_PORB => FIXED_IO_ps_porb,
PS_SRSTB => FIXED_IO_ps_srstb,
TTC0_WAVE0_OUT => NLW_processing_system7_0_TTC0_WAVE0_OUT_UNCONNECTED,
TTC0_WAVE1_OUT => NLW_processing_system7_0_TTC0_WAVE1_OUT_UNCONNECTED,
TTC0_WAVE2_OUT => NLW_processing_system7_0_TTC0_WAVE2_OUT_UNCONNECTED,
USB0_PORT_INDCTL(1 downto 0) => NLW_processing_system7_0_USB0_PORT_INDCTL_UNCONNECTED(1 downto 0),
USB0_VBUS_PWRFAULT => GND_1,
USB0_VBUS_PWRSELECT => NLW_processing_system7_0_USB0_VBUS_PWRSELECT_UNCONNECTED
);
processing_system7_0_axi_periph: entity work.base_zynq_design_processing_system7_0_axi_periph_0
port map (
ACLK => processing_system7_0_FCLK_CLK0,
ARESETN(0) => rst_processing_system7_0_100M_interconnect_aresetn(0),
M00_ACLK => processing_system7_0_FCLK_CLK0,
M00_ARESETN(0) => rst_processing_system7_0_100M_peripheral_aresetn(0),
M00_AXI_araddr(8 downto 0) => processing_system7_0_axi_periph_M00_AXI_ARADDR(8 downto 0),
M00_AXI_arready => processing_system7_0_axi_periph_M00_AXI_ARREADY,
M00_AXI_arvalid => processing_system7_0_axi_periph_M00_AXI_ARVALID,
M00_AXI_awaddr(8 downto 0) => processing_system7_0_axi_periph_M00_AXI_AWADDR(8 downto 0),
M00_AXI_awready => processing_system7_0_axi_periph_M00_AXI_AWREADY,
M00_AXI_awvalid => processing_system7_0_axi_periph_M00_AXI_AWVALID,
M00_AXI_bready => processing_system7_0_axi_periph_M00_AXI_BREADY,
M00_AXI_bresp(1 downto 0) => processing_system7_0_axi_periph_M00_AXI_BRESP(1 downto 0),
M00_AXI_bvalid => processing_system7_0_axi_periph_M00_AXI_BVALID,
M00_AXI_rdata(31 downto 0) => processing_system7_0_axi_periph_M00_AXI_RDATA(31 downto 0),
M00_AXI_rready => processing_system7_0_axi_periph_M00_AXI_RREADY,
M00_AXI_rresp(1 downto 0) => processing_system7_0_axi_periph_M00_AXI_RRESP(1 downto 0),
M00_AXI_rvalid => processing_system7_0_axi_periph_M00_AXI_RVALID,
M00_AXI_wdata(31 downto 0) => processing_system7_0_axi_periph_M00_AXI_WDATA(31 downto 0),
M00_AXI_wready => processing_system7_0_axi_periph_M00_AXI_WREADY,
M00_AXI_wstrb(3 downto 0) => processing_system7_0_axi_periph_M00_AXI_WSTRB(3 downto 0),
M00_AXI_wvalid => processing_system7_0_axi_periph_M00_AXI_WVALID,
M01_ACLK => processing_system7_0_FCLK_CLK0,
M01_ARESETN(0) => rst_processing_system7_0_100M_peripheral_aresetn(0),
M01_AXI_araddr(12 downto 0) => processing_system7_0_axi_periph_M01_AXI_ARADDR(12 downto 0),
M01_AXI_arburst(1 downto 0) => processing_system7_0_axi_periph_M01_AXI_ARBURST(1 downto 0),
M01_AXI_arcache(3 downto 0) => processing_system7_0_axi_periph_M01_AXI_ARCACHE(3 downto 0),
M01_AXI_arlen(7 downto 0) => processing_system7_0_axi_periph_M01_AXI_ARLEN(7 downto 0),
M01_AXI_arlock(0) => processing_system7_0_axi_periph_M01_AXI_ARLOCK(0),
M01_AXI_arprot(2 downto 0) => processing_system7_0_axi_periph_M01_AXI_ARPROT(2 downto 0),
M01_AXI_arready(0) => processing_system7_0_axi_periph_M01_AXI_ARREADY,
M01_AXI_arsize(2 downto 0) => processing_system7_0_axi_periph_M01_AXI_ARSIZE(2 downto 0),
M01_AXI_arvalid(0) => processing_system7_0_axi_periph_M01_AXI_ARVALID(0),
M01_AXI_awaddr(12 downto 0) => processing_system7_0_axi_periph_M01_AXI_AWADDR(12 downto 0),
M01_AXI_awburst(1 downto 0) => processing_system7_0_axi_periph_M01_AXI_AWBURST(1 downto 0),
M01_AXI_awcache(3 downto 0) => processing_system7_0_axi_periph_M01_AXI_AWCACHE(3 downto 0),
M01_AXI_awlen(7 downto 0) => processing_system7_0_axi_periph_M01_AXI_AWLEN(7 downto 0),
M01_AXI_awlock(0) => processing_system7_0_axi_periph_M01_AXI_AWLOCK(0),
M01_AXI_awprot(2 downto 0) => processing_system7_0_axi_periph_M01_AXI_AWPROT(2 downto 0),
M01_AXI_awready(0) => processing_system7_0_axi_periph_M01_AXI_AWREADY,
M01_AXI_awsize(2 downto 0) => processing_system7_0_axi_periph_M01_AXI_AWSIZE(2 downto 0),
M01_AXI_awvalid(0) => processing_system7_0_axi_periph_M01_AXI_AWVALID(0),
M01_AXI_bready(0) => processing_system7_0_axi_periph_M01_AXI_BREADY(0),
M01_AXI_bresp(1 downto 0) => processing_system7_0_axi_periph_M01_AXI_BRESP(1 downto 0),
M01_AXI_bvalid(0) => processing_system7_0_axi_periph_M01_AXI_BVALID,
M01_AXI_rdata(31 downto 0) => processing_system7_0_axi_periph_M01_AXI_RDATA(31 downto 0),
M01_AXI_rlast(0) => processing_system7_0_axi_periph_M01_AXI_RLAST,
M01_AXI_rready(0) => processing_system7_0_axi_periph_M01_AXI_RREADY(0),
M01_AXI_rresp(1 downto 0) => processing_system7_0_axi_periph_M01_AXI_RRESP(1 downto 0),
M01_AXI_rvalid(0) => processing_system7_0_axi_periph_M01_AXI_RVALID,
M01_AXI_wdata(31 downto 0) => processing_system7_0_axi_periph_M01_AXI_WDATA(31 downto 0),
M01_AXI_wlast(0) => processing_system7_0_axi_periph_M01_AXI_WLAST(0),
M01_AXI_wready(0) => processing_system7_0_axi_periph_M01_AXI_WREADY,
M01_AXI_wstrb(3 downto 0) => processing_system7_0_axi_periph_M01_AXI_WSTRB(3 downto 0),
M01_AXI_wvalid(0) => processing_system7_0_axi_periph_M01_AXI_WVALID(0),
S00_ACLK => processing_system7_0_FCLK_CLK0,
S00_ARESETN(0) => rst_processing_system7_0_100M_peripheral_aresetn(0),
S00_AXI_araddr(31 downto 0) => processing_system7_0_M_AXI_GP0_ARADDR(31 downto 0),
S00_AXI_arburst(1 downto 0) => processing_system7_0_M_AXI_GP0_ARBURST(1 downto 0),
S00_AXI_arcache(3 downto 0) => processing_system7_0_M_AXI_GP0_ARCACHE(3 downto 0),
S00_AXI_arid(11 downto 0) => processing_system7_0_M_AXI_GP0_ARID(11 downto 0),
S00_AXI_arlen(3 downto 0) => processing_system7_0_M_AXI_GP0_ARLEN(3 downto 0),
S00_AXI_arlock(1 downto 0) => processing_system7_0_M_AXI_GP0_ARLOCK(1 downto 0),
S00_AXI_arprot(2 downto 0) => processing_system7_0_M_AXI_GP0_ARPROT(2 downto 0),
S00_AXI_arqos(3 downto 0) => processing_system7_0_M_AXI_GP0_ARQOS(3 downto 0),
S00_AXI_arready => processing_system7_0_M_AXI_GP0_ARREADY,
S00_AXI_arsize(2 downto 0) => processing_system7_0_M_AXI_GP0_ARSIZE(2 downto 0),
S00_AXI_arvalid => processing_system7_0_M_AXI_GP0_ARVALID,
S00_AXI_awaddr(31 downto 0) => processing_system7_0_M_AXI_GP0_AWADDR(31 downto 0),
S00_AXI_awburst(1 downto 0) => processing_system7_0_M_AXI_GP0_AWBURST(1 downto 0),
S00_AXI_awcache(3 downto 0) => processing_system7_0_M_AXI_GP0_AWCACHE(3 downto 0),
S00_AXI_awid(11 downto 0) => processing_system7_0_M_AXI_GP0_AWID(11 downto 0),
S00_AXI_awlen(3 downto 0) => processing_system7_0_M_AXI_GP0_AWLEN(3 downto 0),
S00_AXI_awlock(1 downto 0) => processing_system7_0_M_AXI_GP0_AWLOCK(1 downto 0),
S00_AXI_awprot(2 downto 0) => processing_system7_0_M_AXI_GP0_AWPROT(2 downto 0),
S00_AXI_awqos(3 downto 0) => processing_system7_0_M_AXI_GP0_AWQOS(3 downto 0),
S00_AXI_awready => processing_system7_0_M_AXI_GP0_AWREADY,
S00_AXI_awsize(2 downto 0) => processing_system7_0_M_AXI_GP0_AWSIZE(2 downto 0),
S00_AXI_awvalid => processing_system7_0_M_AXI_GP0_AWVALID,
S00_AXI_bid(11 downto 0) => processing_system7_0_M_AXI_GP0_BID(11 downto 0),
S00_AXI_bready => processing_system7_0_M_AXI_GP0_BREADY,
S00_AXI_bresp(1 downto 0) => processing_system7_0_M_AXI_GP0_BRESP(1 downto 0),
S00_AXI_bvalid => processing_system7_0_M_AXI_GP0_BVALID,
S00_AXI_rdata(31 downto 0) => processing_system7_0_M_AXI_GP0_RDATA(31 downto 0),
S00_AXI_rid(11 downto 0) => processing_system7_0_M_AXI_GP0_RID(11 downto 0),
S00_AXI_rlast => processing_system7_0_M_AXI_GP0_RLAST,
S00_AXI_rready => processing_system7_0_M_AXI_GP0_RREADY,
S00_AXI_rresp(1 downto 0) => processing_system7_0_M_AXI_GP0_RRESP(1 downto 0),
S00_AXI_rvalid => processing_system7_0_M_AXI_GP0_RVALID,
S00_AXI_wdata(31 downto 0) => processing_system7_0_M_AXI_GP0_WDATA(31 downto 0),
S00_AXI_wid(11 downto 0) => processing_system7_0_M_AXI_GP0_WID(11 downto 0),
S00_AXI_wlast => processing_system7_0_M_AXI_GP0_WLAST,
S00_AXI_wready => processing_system7_0_M_AXI_GP0_WREADY,
S00_AXI_wstrb(3 downto 0) => processing_system7_0_M_AXI_GP0_WSTRB(3 downto 0),
S00_AXI_wvalid => processing_system7_0_M_AXI_GP0_WVALID
);
rst_processing_system7_0_50M: component base_zynq_design_rst_processing_system7_0_100M_0
port map (
aux_reset_in => VCC_1,
bus_struct_reset(0) => NLW_rst_processing_system7_0_50M_bus_struct_reset_UNCONNECTED(0),
dcm_locked => VCC_1,
ext_reset_in => processing_system7_0_FCLK_RESET0_N,
interconnect_aresetn(0) => rst_processing_system7_0_100M_interconnect_aresetn(0),
mb_debug_sys_rst => GND_1,
mb_reset => NLW_rst_processing_system7_0_50M_mb_reset_UNCONNECTED,
peripheral_aresetn(0) => rst_processing_system7_0_100M_peripheral_aresetn(0),
peripheral_reset(0) => NLW_rst_processing_system7_0_50M_peripheral_reset_UNCONNECTED(0),
slowest_sync_clk => processing_system7_0_FCLK_CLK0
);
xlconcat_0: component base_zynq_design_xlconcat_0_0
port map (
In0(0) => axi_gpio_0_ip2intc_irpt,
dout(0) => xlconcat_0_dout(0)
);
end STRUCTURE;
| gpl-3.0 |
freecores/usb_fpga_1_2 | examples/usb-fpga-1.11/1.11b/lightshow/fpga/lightshow.vhd | 36 | 2235 | library ieee;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity lightshow is
port(
led : out std_logic_vector(11 downto 0);
CLK : in std_logic -- 32 MHz
);
end lightshow;
--signal declaration
architecture RTL of lightshow is
type tPattern is array(11 downto 0) of integer range 0 to 15;
signal pattern1 : tPattern := (0, 1, 2, 3, 4, 5, 6, 5, 4, 3, 2, 1);
signal pattern2 : tPattern := (6, 5, 4, 3, 2, 1, 0, 1, 2, 3, 4, 5);
signal pattern3 : tPattern := (0, 1, 4, 9, 4, 1, 0, 0, 0, 0, 0, 0);
type tXlatTable1 is array(0 to 12) of integer range 0 to 1023;
constant xt1 : tXlatTable1 := (0, 0, 1, 4, 13, 31, 64, 118, 202, 324, 493, 722, 1023);
type tXlatTable2 is array(0 to 9) of integer range 0 to 255;
--constant xt2 : tXlatTable2 := (0, 1, 11, 38, 90, 175, 303, 481, 718, 1023);
constant xt2 : tXlatTable2 := (0, 0, 3, 9, 22, 44, 76, 120, 179, 255);
signal cp1 : std_logic_vector(22 downto 0);
signal cp2 : std_logic_vector(22 downto 0);
signal cp3 : std_logic_vector(22 downto 0);
signal d : std_logic_vector(16 downto 0);
begin
dpCLK: process(CLK)
begin
if CLK' event and CLK = '1' then
if ( cp1 = conv_std_logic_vector(3000000,23) )
then
pattern1(10 downto 0) <= pattern1(11 downto 1);
pattern1(11) <= pattern1(0);
cp1 <= (others => '0');
else
cp1 <= cp1 + 1;
end if;
if ( cp2 = conv_std_logic_vector(2200000,23) )
then
pattern2(10 downto 0) <= pattern2(11 downto 1);
pattern2(11) <= pattern2(0);
cp2 <= (others => '0');
else
cp2 <= cp2 + 1;
end if;
if ( cp3 = conv_std_logic_vector(1500000,23) )
then
pattern3(11 downto 1) <= pattern3(10 downto 0);
pattern3(0) <= pattern3(11);
cp3 <= (others => '0');
else
cp3 <= cp3 + 1;
end if;
if ( d = conv_std_logic_vector(1278*64-1,17) )
then
d <= (others => '0');
else
d <= d + 1;
end if;
for i in 0 to 11 loop
if ( d(16 downto 6) < conv_std_logic_vector( xt1(pattern1(i) + pattern2(i)) + xt2(pattern3(i)) ,11) )
then
led(i) <= '1';
else
led(i) <= '0';
end if;
end loop;
end if;
end process dpCLK;
end RTL;
| gpl-3.0 |
asicguy/gplgpu | hdl/sim_lib/alt_dspbuilder_package.vhd | 1 | 50563 | -- Copyright (C) 1991-2011 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- Quartus II 11.0 Build 157 04/27/2011
--------------------------------------------------------------------------------------------
-- DSP Builder (Version 7.2)
-- Quartus II development tool and MATLAB/Simulink Interface
--------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
package alt_dspbuilder_package is
constant M_MAX : NATURAL := 64;
constant MAXROM : positive := 4096;
constant altversion : string := "DSP Builder - Quartus II development tool and MATLAB/Simulink Interface - Version 7.2";
constant DSPBuilderQTB : string := "on";
constant DSPBuilderVersion : string := "7.2";
constant DSPBuilderProduct : string := "DSP Builder";
Subtype max_vector is Std_Logic_Vector(M_MAX downto 0);
type vector_2D is array(NATURAL RANGE <>) of max_vector;
type STD_LOGIC_2DSPBUILDER is array (NATURAL RANGE <>, NATURAL RANGE <>)of std_logic ;
type STD_LOGIC_3D is array (NATURAL RANGE <>, NATURAL RANGE <>,NATURAL RANGE <>) of std_logic;
type integer_2D is array(NATURAL RANGE <>) of integer;
type LogicalOperator is (AltAND, AltOR, AltXOR, AltNAND, ALtNOR, AltNOT, AltShiftLeft, AltShiftRight, AltRotateRight, AltRotateLeft);
type CompareOperator is (Altaeb, Altaneb, Altagb, Altageb, Altalb, Altaleb);
type AddSubOperator is (AddAdd, AddSub, SubAdd, SubSub);
type BusArithm is (BusIsSigned, BusIsUnsigned, RoundLsb ,TruncateLsb, SaturMsb, TruncateMsb);
type RegisterStructure is (None, DataInputs, MultiplierOutput, DataInputsandMultiplier,
NoRegister, InputsOnly, MultiplierOnly, AdderOnly, InputsandMultiplier,
InputsandAdder,MultiplierandAdder,InputsMultiplierandAdder);
function nbitnecessary(value: integer) return integer;
function Nstd_bitnecessary(DSigned : std_logic_vector) return integer;
function nSignbitnecessary(value: integer) return integer;
function int2ustd(value : integer; width : integer) return std_logic_vector;
function bitvec2std(bv : bit_vector) return std_logic_vector;
function int2sstd(value : integer; width : integer) return std_logic_vector;
function int2bit(value : integer) return std_logic;
function cal_width_lpm_mult(b: boolean ; w : integer) return positive;
function integer_is_even(i: integer ) return boolean;
function ceil_divide(i:integer;d:integer) return integer;
function floor_divide(i:integer;d:integer) return integer;
function ToNatural(i:integer) return integer;
function To_String (Value: Integer) return STRING;
function To_String (Value: Std_logic_vector) return String;
function To_Character (Value: Std_logic) return Character;
function cp_str(s1: string; s2: string) return boolean;
function StdPowerOfTwo(DSigned : std_logic_vector) return integer; -- return -1 if not power of tow otherwisse return power of two
component alt_dspbuilder_SBF
generic (
width_inl : natural ;
width_inr : natural ;
width_outl : natural ;
width_outr : natural ;
round : natural ;
satur : natural ;
lpm_signed : BusArithm
);
port (
xin : in std_logic_vector(width_inl+width_inr-1 downto 0);
yout : out std_logic_vector(width_outl+width_outr-1 downto 0)
);
end component ;
component alt_dspbuilder_SRED
generic (
widthin : natural ;
widthout : natural ;
msb : natural ;
lsb : natural ;
round : natural ;
satur : natural ;
lpm_signed : BusArithm
);
port (
xin : in std_logic_vector(widthin-1 downto 0);
yout : out std_logic_vector(widthout-1 downto 0)
);
end component ;
component alt_dspbuilder_SDelay
generic (
lpm_width : positive ;
lpm_delay : positive ;
SequenceLength : positive ;
SequenceValue : std_logic_vector
);
port (
dataa : in std_logic_vector(lpm_width-1 downto 0);
clock : in std_logic ;
ena : in std_logic ;
aclr : in std_logic ;
user_aclr : in std_logic ;
sclr : in std_logic ;
result : out std_logic_vector(lpm_width-1 downto 0)
);
end component ;
component alt_dspbuilder_SInitDelay
generic (
lpm_width : positive ;
lpm_delay : positive ;
SequenceLength : positive ;
SequenceValue : std_logic_vector;
ResetValue : std_logic_vector
);
port (
dataa : in std_logic_vector(lpm_width-1 downto 0);
clock : in std_logic;
ena : in std_logic;
aclr : in std_logic;
user_aclr : in std_logic;
sclr : in std_logic;
result : out std_logic_vector(lpm_width-1 downto 0)
);
end component ;
component alt_dspbuilder_sAltrPropagate
generic (
WIDTH : positive ;
QTB : string;
QTB_PRODUCT : string;
QTB_VERSION : string
);
port (
d : in std_logic_vector(WIDTH-1 downto 0);
r : out std_logic_vector(WIDTH-1 downto 0)
);
end component ;
component alt_dspbuilder_sAltrBitPropagate
generic (
QTB : string;
QTB_PRODUCT : string;
QTB_VERSION : string
);
port (
d : in std_logic;
r : out std_logic
);
end component ;
component alt_dspbuilder_UpsampleAltr
generic (
lpm_width : positive ;
SamplingFactor : positive
);
port (
dataa : in std_logic_vector(lpm_width-1 downto 0);
clock : in std_logic ;
aclr : in std_logic ;
user_aclr : in std_logic ;
sclr : in std_logic ;
result : out std_logic_vector(lpm_width-1 downto 0)
);
end component;
component alt_dspbuilder_SDownSampleAltr
generic (
lpm_width : positive ;
SamplingFactor : positive
);
port (
dataa : in std_logic_vector(lpm_width-1 downto 0);
clock : in std_logic ;
aclr : in std_logic ;
user_aclr : in std_logic ;
sclr : in std_logic ;
result : out std_logic_vector(lpm_width-1 downto 0)
);
end component;
component alt_dspbuilder_sBin2BcdAltr
port
(
d : in std_logic_vector (3 downto 0);
r : out std_logic_vector (6 downto 0)
);
end component;
component alt_dspbuilder_SBitLogical
generic (
lpm_width : positive ;
lop : LogicalOperator
);
port (
dataa : in std_logic_vector(lpm_width-1 downto 0);
result : out std_logic
);
end component;
component alt_dspbuilder_SBusLogical
generic (
lpm_width : positive ;
lop : LogicalOperator ;
mask : natural;
valmask : std_logic_vector;
sgnext_rshift : natural
);
port (
dataa : in std_logic_vector(lpm_width-1 downto 0);
result : out std_logic_vector(lpm_width-1 downto 0)
);
end component ;
component alt_dspbuilder_AltiMult
generic (
lpm_widtha : positive ;
lpm_widthb : positive ;
dspb_widthr : positive ;
lpm_hint : string ;
cst_val : std_logic_vector ;
one_input : integer ;
pipeline : natural ;
SequenceLength : positive ;
SequenceValue : std_logic_vector;
lpm : natural );
port (
dataa : in std_logic_vector(lpm_widtha-1 downto 0);
datab : in std_logic_vector(lpm_widthb-1 downto 0) :=(others=>'0');
clock : in std_logic ;
ena : in std_logic ;
aclr : in std_logic ;
user_aclr : in std_logic ;
part_sclr : in std_logic := '0';
result : out std_logic_vector(dspb_widthr-1 downto 0)
);
end component ;
component alt_dspbuilder_BEXT
generic (
delay : integer ;
widthin : positive;
widthout : positive
);
port (
din : in std_logic_vector(widthin-1 downto 0);
clock : in std_logic;
aclr : in std_logic;
sclr : in std_logic;
ena : in std_logic;
dout : out std_logic_vector(widthout-1 downto 0)
);
end component;
component alt_dspbuilder_nBEXT
generic (
delay : integer ;
widthin : positive;
widthout : positive
);
port (
din : in std_logic_vector(widthin-1 downto 0);
clock : in std_logic;
aclr : in std_logic;
sclr : in std_logic;
ena : in std_logic;
dout : out std_logic_vector(widthout-1 downto 0)
);
end component;
component alt_dspbuilder_IncDecAltr
generic (
lpm_width : positive ;
cst_val : std_logic_vector ;
direction : integer ;
lpm : natural ;
SequenceLength : positive ;
SequenceValue : std_logic_vector ;
Isunsigned : natural
);
port (
clock : in std_logic :='0';
ena : in std_logic :='1';
aclr : in std_logic :='0';
user_aclr : in std_logic :='0';
sclr : in std_logic :='0';
result : out std_logic_vector(lpm_width-1 downto 0)
);
end component ;
component alt_dspbuilder_AROUND
generic (
widthin : natural ;
widthout : natural
);
port (
xin : in std_logic_vector(widthin-1 downto 0);
yout : out std_logic_vector(widthout-1 downto 0)
);
end component ;
component alt_dspbuilder_SAdderSub
generic (
lpm_width : positive ; -- input bus width
pipeline : natural ;
SequenceLength : positive ;
SequenceValue : std_logic_vector ;
AddSubVal : AddSubOperator :=AddAdd -- SubSub is illegal
);
port (
dataa : in std_logic_vector(lpm_width-1 downto 0) ;
datab : in std_logic_vector(lpm_width-1 downto 0) ;
clock : in std_logic ;
ena : in std_logic ;
aclr : in std_logic ;
user_aclr : in std_logic ;
seq_sclr : in std_logic := '0';
result : out std_logic_vector(lpm_width downto 0)
);
end component;
component alt_dspbuilder_ASAT
generic (
widthin : natural ;
widthout : natural ;
lpm_signed : BusArithm
);
port
(
xin : in std_logic_vector(widthin-1 downto 0);
yout : out std_logic_vector(widthout-1 downto 0)
);
end component ;
component alt_dspbuilder_comparatorAltr
generic (
lpm_width : natural ;
direction : CompareOperator ;
lpm : integer
);
port (
dataa : in std_logic_vector(lpm_width-1 downto 0);
datab : in std_logic_vector(lpm_width-1 downto 0);
result : out std_logic
);
end component ;
component alt_dspbuilder_vecseq
generic (
SequenceLength : positive ;
SequenceValue : std_logic_vector
);
port (
clock : in std_logic ;
ena : in std_logic ;
aclr : in std_logic ;
sclr : in std_logic ;
yout : out std_logic
);
end component ;
component alt_dspbuilder_seq
generic (
SequenceLength : positive ;
SequenceValue : positive
);
port (
clock : in std_logic ;
ena : in std_logic ;
aclr : in std_logic ;
sclr : in std_logic ;
yout : out std_logic
);
end component ;
component alt_dspbuilder_sync_dpram_single_clock
generic (
lpm_widthad : integer ;
lpm_width : integer
);
port (
wraddress : in std_logic_vector(lpm_widthad-1 downto 0);
rdaddress : in std_logic_vector(lpm_widthad-1 downto 0);
data : in std_logic_vector(lpm_width-1 downto 0);
q : out std_logic_vector(lpm_width-1 downto 0);
wr : in std_logic ;
rden : in std_logic ;
clock : in std_logic
);
end component;
component alt_dspbuilder_SDpram
generic (
LPM_WIDTH : positive ;
LPM_WIDTHAD : positive ;
ram_block_type : STRING ;
SequenceLength : positive ;
SequenceValue : std_logic_vector
);
port (
data : in std_logic_vector(lpm_width-1 downto 0);
rdaddress : in std_logic_vector(LPM_WIDTHAD-1 downto 0);
wraddress : in std_logic_vector(LPM_WIDTHAD-1 downto 0);
clock : in std_logic ;
wren : in std_logic ;
sclr : in std_logic ;
aclr : in std_logic ;
user_aclr : in std_logic ;
q : out std_logic_vector(lpm_width-1 downto 0)
);
end component ;
component alt_dspbuilder_SLRom_AltSyncRam
generic
(
width_a : natural ;
widthad_a : natural ;
register_output : string ;
intended_device_family : string ;
init_file : string
);
port
(
address : in std_logic_vector (widthad_a-1 downto 0);
aclr : in std_logic ;
user_aclr : in std_logic ;
clken : in std_logic ;
clock : in std_logic ;
q : out std_logic_vector (width_a-1 downto 0)
);
end component;
component alt_dspbuilder_SLRom
generic (
LPM_WIDTH : positive;
LPM_WIDTHAD : positive;
SequenceLength : positive;
SequenceValue : std_logic_vector;
XFILE : string;
intended_device_family : string;
stratix_type : natural;
is_unsigned : natural
);
port (
address : in std_logic_vector(LPM_WIDTHAD-1 downto 0);
clock : in std_logic ;
aclr : in std_logic ;
user_aclr : in std_logic ;
ena : in std_logic :='1';
q : out std_logic_vector(lpm_width+is_unsigned-1 downto 0)
);
end component ;
component alt_dspbuilder_SUsgn
generic (
LPM_WIDTHL : positive ;
LPM_WIDTHR : positive
);
port (
data : in std_logic_vector(LPM_WIDTHL+LPM_WIDTHR-1 downto 0);
q : out std_logic_vector(LPM_WIDTHL downto 0)
);
end component ;
component alt_dspbuilder_SShiftTap
generic (
width : positive ;
number_of_taps : positive ;
use_dedicated_circuitry : natural;
lpm_hint : string ;
tap_distance : positive
);
port (
data : in std_logic_vector(width-1 downto 0);
clock : in std_logic;
aclr : in std_logic;
user_aclr : in std_logic;
sclr : in std_logic;
ena : in std_logic;
taps : out std_logic_vector(width*number_of_taps-1 downto 0);
shiftout : out std_logic_vector(width-1 downto 0)
);
end component ;
component alt_dspbuilder_AltiSMac
generic (
width_a : positive ;
width_b : positive ;
width_result : positive ;
use_dedicated_circuitry : natural ;
RegStruct : RegisterStructure
);
port (
dataa : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (width_b-1 DOWNTO 0);
addnsub : IN STD_LOGIC := '1';
accum_sload : IN STD_LOGIC := '0';
clock : IN STD_LOGIC := '1';
ena : IN STD_LOGIC := '1';
aclr : IN STD_LOGIC := '0';
result : out STD_LOGIC_VECTOR (width_result-1 DOWNTO 0);
overflow : OUT STD_LOGIC
);
end component ;
component alt_dspbuilder_AltiSMacMF
generic (
width_a : positive ;
width_b : positive ;
width_result : positive ;
RegStruct : RegisterStructure
);
port (
dataa : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (width_b-1 DOWNTO 0);
addnsub : IN STD_LOGIC := '1';
accum_sload : IN STD_LOGIC := '0';
clock : IN STD_LOGIC := '1';
ena : IN STD_LOGIC := '1';
aclr : IN STD_LOGIC := '0';
result : out STD_LOGIC_VECTOR (width_result-1 DOWNTO 0);
overflow : OUT STD_LOGIC
);
end component ;
component alt_dspbuilder_AltiSMacUsg
generic (
width_a : positive ;
width_b : positive ;
width_result : positive ;
use_dedicated_circuitry : natural ;
RegStruct : RegisterStructure
);
port (
dataa : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (width_b-1 DOWNTO 0);
addnsub : IN STD_LOGIC := '1';
accum_sload : IN STD_LOGIC := '0';
clock : IN STD_LOGIC := '1';
ena : IN STD_LOGIC := '1';
aclr : IN STD_LOGIC := '0';
user_aclr : IN STD_LOGIC := '0';
result : out STD_LOGIC_VECTOR (width_result-1 DOWNTO 0);
overflow : OUT STD_LOGIC
);
end component ;
component alt_dspbuilder_CST_MULT is
GENERIC (
widthin : positive ;
widthcoef : positive ;
widthr : positive ;
cst : std_logic_vector ;
lpm_hint : string ;
pipeline : natural );
PORT (
clock : in std_logic;
aclr : in std_logic;
part_sclr : in std_logic := '0';
ena : in std_logic;
data : in std_logic_vector (widthin-1 DOWNTO 0);
result : out std_logic_vector (widthr-1 DOWNTO 0)
);
end component ;
component alt_dspbuilder_MultAdd
generic (
width_a : positive ;
width_r : positive ;
direction : AddSubOperator ;
nMult : positive ;
intended_device_family : string;
use_dedicated_circuitry : natural ;
representation : string ;
regstruct : registerstructure
);
port (
dat1aa : in std_logic_vector (width_a-1 downto 0);
dat1ab : in std_logic_vector (width_a-1 downto 0);
dat2aa : in std_logic_vector (width_a-1 downto 0);
dat2ab : in std_logic_vector (width_a-1 downto 0);
dat3aa : in std_logic_vector (width_a-1 downto 0):=(others=>'0');
dat3ab : in std_logic_vector (width_a-1 downto 0):=(others=>'0');
dat4aa : in std_logic_vector (width_a-1 downto 0):=(others=>'0');
dat4ab : in std_logic_vector (width_a-1 downto 0):=(others=>'0');
clock : in std_logic := '1';
ena : in std_logic := '1';
part_sclr : in std_logic := '0';
aclr : in std_logic := '0';
user_aclr : in std_logic := '0';
result : out std_logic_vector (width_r-1 downto 0)
);
end component ;
component alt_dspbuilder_MultAddMF
generic (
width_a : positive ;
width_r : positive ;
direction : AddSubOperator ;
nMult : positive ;
intended_device_family : string ;
representation : string ;
regstruct : registerstructure
);
port (
dat1aa : in std_logic_vector (width_a-1 downto 0);
dat1ab : in std_logic_vector (width_a-1 downto 0);
dat2aa : in std_logic_vector (width_a-1 downto 0);
dat2ab : in std_logic_vector (width_a-1 downto 0);
dat3aa : in std_logic_vector (width_a-1 downto 0):=(others=>'0');
dat3ab : in std_logic_vector (width_a-1 downto 0):=(others=>'0');
dat4aa : in std_logic_vector (width_a-1 downto 0):=(others=>'0');
dat4ab : in std_logic_vector (width_a-1 downto 0):=(others=>'0');
clock : in std_logic := '1';
ena : in std_logic := '1';
aclr : in std_logic := '0';
result : out std_logic_vector (width_r-1 downto 0)
);
end component ;
component alt_dspbuilder_signaltapunit
generic (upper_limit: integer ;
lower_limit: integer );
port(
data_in : in std_logic_vector(upper_limit downto lower_limit);
data_out : out std_logic_vector(upper_limit downto lower_limit));
end component ;
component alt_dspbuilder_CplxMult
generic (
width : positive
);
port (
dataareal : in std_logic_vector (width-1 downto 0);
dataaimag : in std_logic_vector (width-1 downto 0);
databreal : in std_logic_vector (width-1 downto 0);
databimag : in std_logic_vector (width-1 downto 0);
resultreal : out std_logic_vector (2*width downto 0):=(others=>'0');
resultimag : out std_logic_vector (2*width downto 0):=(others=>'0')
);
end component ;
component alt_dspbuilder_AltMultConst
generic (
CA : std_logic_vector ;
CB : std_logic_vector ;
CC : std_logic_vector ;
CD : std_logic_vector ;
width_a : positive ;
width_r : positive ;
regstruct : registerstructure :=NoRegister
);
port (
datain : in std_logic_vector (width_a-1 downto 0);
datbin : in std_logic_vector (width_a-1 downto 0);
datcin : in std_logic_vector (width_a-1 downto 0);
datdin : in std_logic_vector (width_a-1 downto 0);
dataout : out std_logic_vector (width_r-1 downto 0);
clock : in std_logic := '1';
ena : in std_logic := '1';
sclr : in std_logic := '0';
aclr : in std_logic := '0';
user_aclr : in std_logic := '0'
);
end component ;
component alt_dspbuilder_Par2Ser
generic (
msbfirst : boolean ;
repeatlastbit : boolean ;
widthin : natural
);
port (
xin : in std_logic_vector(widthin-1 downto 0):=(others=>'0');
ena : in std_logic :='1';
load : in std_logic :='0';
clock : in std_logic;
aclr : in std_logic :='0';
sclr : in std_logic :='0';
sout : out std_logic
);
end component;
component alt_dspbuilder_Ser2Par
generic (
msbfirst : boolean ;
widthin : natural
);
port (
sin : in std_logic :='0';
clock : in std_logic ;
ena : in std_logic :='1';
sclr : in std_logic :='0';
aclr : in std_logic :='0';
xout : out std_logic_vector(widthin-1 downto 0)
);
end component ;
component alt_dspbuilder_dividerAltr
generic (
widthin : natural;
isunsigned : natural ;
pipeline : natural
);
port
(
clock : in std_logic := '0';
aclr : in std_logic := '0';
user_aclr : in std_logic := '0';
clken : in std_logic := '1';
numer : in std_logic_vector (widthin-1 downto 0);
denom : in std_logic_vector (widthin-1 downto 0);
quotient : out std_logic_vector (widthin-1 downto 0);
remain : out std_logic_vector (widthin-1 downto 0)
);
end component ;
component alt_dspbuilder_butterflyAltr
generic (
WidthIn : positive ;
WidthOut : positive ;
WidthOutLsb : natural ;
pipeline : natural;
W_is_constant : natural;
W_real : std_logic_vector;
W_imag : std_logic_vector;
lpm_hint : string;
DecimationInTime : natural
);
port (
clock : in std_logic:= '0';
aclr : in std_logic:= '0' ;
user_aclr : in std_logic:= '0' ;
ena : in std_logic:= '1' ;
part_sclr : in std_logic:= '0' ;
areal : in std_logic_vector (WidthIn-1 downto 0);
aimag : in std_logic_vector (WidthIn-1 downto 0);
breal : in std_logic_vector (WidthIn-1 downto 0);
bimag : in std_logic_vector (WidthIn-1 downto 0);
wreal : in std_logic_vector (WidthIn-1 downto 0);
wimag : in std_logic_vector (WidthIn-1 downto 0);
rAreal : out std_logic_vector (WidthOut-1 downto 0);
rAimag : out std_logic_vector (WidthOut-1 downto 0);
rBreal : out std_logic_vector (WidthOut-1 downto 0);
rBimag : out std_logic_vector (WidthOut-1 downto 0)
);
end component ;
component alt_dspbuilder_sLpmAddSub
generic
(
width : positive;
isunsigned : natural;
pipeline : natural
);
port
(
add_sub : in std_logic ;
dataa : in std_logic_vector (width-1 downto 0);
datab : in std_logic_vector (width-1 downto 0);
cin : in std_logic :='0';
clock : in std_logic :='0';
aclr : in std_logic :='0';
user_aclr : in std_logic :='0';
clken : in std_logic :='1';
result : out std_logic_vector (width-1 downto 0);
cout : out std_logic
);
end component;
component alt_dspbuilder_sLpmCount
GENERIC
(
width : NATURAL ;
modulus : NATURAL
);
PORT
(
data : IN STD_LOGIC_VECTOR (width-1 DOWNTO 0);
sload : IN STD_LOGIC ;
updown : IN STD_LOGIC ;
clk_en : IN STD_LOGIC ;
sclr : IN STD_LOGIC ;
clock : IN STD_LOGIC ;
aclr : IN STD_LOGIC ;
user_aclr : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (width-1 DOWNTO 0)
);
END component;
component alt_dspbuilder_sIntegratorAltr
GENERIC
(
width : natural ;
depth : positive
);
PORT
(
data : IN STD_LOGIC_VECTOR (width-1 DOWNTO 0);
clk_en : IN STD_LOGIC ;
sclr : IN STD_LOGIC ;
clock : IN STD_LOGIC ;
aclr : IN STD_LOGIC ;
user_aclr : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (width-1 DOWNTO 0)
);
END component;
component alt_dspbuilder_sdecoderaltr
GENERIC
(
width : NATURAL ;
pipeline : NATURAL ;
decode : std_logic_vector
);
PORT
(
clock : in std_logic;
aclr : IN STD_LOGIC ;
user_aclr : IN STD_LOGIC ;
sclr : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (width-1 DOWNTO 0);
dec : OUT STD_LOGIC
);
end component;
component alt_dspbuilder_sDifferentiatorAltr
GENERIC
(
width : natural ;
depth : positive
);
PORT
(
data : IN STD_LOGIC_VECTOR (width-1 DOWNTO 0);
clk_en : IN STD_LOGIC ;
sclr : IN STD_LOGIC ;
clock : IN STD_LOGIC ;
aclr : IN STD_LOGIC ;
user_aclr : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (width-1 DOWNTO 0)
);
END component;
component alt_dspbuilder_sFir4TapCoefSerialAltr
GENERIC
(
representation : STRING;
width : NATURAL
);
PORT
(
clock0 : IN STD_LOGIC ;
dataa_0 : IN STD_LOGIC_VECTOR (width-1 DOWNTO 0) ;
aclr : IN STD_LOGIC ;
user_aclr : IN STD_LOGIC ;
datab_0 : IN STD_LOGIC_VECTOR (width-1 DOWNTO 0);
ena0 : IN STD_LOGIC ;
shiftouta : OUT STD_LOGIC_VECTOR (width-1 DOWNTO 0);
shiftoutb : OUT STD_LOGIC_VECTOR (width-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (2*width+1 DOWNTO 0)
);
end component;
component alt_dspbuilder_sFir4TapCoefParAltr
GENERIC
(
representation : STRING;
Ntap : NATURAL;
width : NATURAL
);
PORT
(
clock : IN STD_LOGIC ;
aclr : IN STD_LOGIC ;
user_aclr : IN STD_LOGIC ;
ena : IN STD_LOGIC ;
dataa : IN STD_LOGIC_VECTOR (width-1 DOWNTO 0);
coef_0 : IN STD_LOGIC_VECTOR (width-1 DOWNTO 0) ;
coef_1 : IN STD_LOGIC_VECTOR (width-1 DOWNTO 0) ;
coef_2 : IN STD_LOGIC_VECTOR (width-1 DOWNTO 0);
coef_3 : IN STD_LOGIC_VECTOR (width-1 DOWNTO 0);
sout : OUT STD_LOGIC_VECTOR (width-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (2*width+1 DOWNTO 0)
);
end component;
component alt_dspbuilder_sFir2TapCoefParAltr
GENERIC
(
representation : STRING;
Ntap : NATURAL;
width : NATURAL
);
PORT
(
clock : IN STD_LOGIC ;
aclr : IN STD_LOGIC ;
user_aclr : IN STD_LOGIC ;
ena : IN STD_LOGIC ;
dataa : IN STD_LOGIC_VECTOR (width-1 DOWNTO 0);
coef_0 : IN STD_LOGIC_VECTOR (width-1 DOWNTO 0) ;
coef_1 : IN STD_LOGIC_VECTOR (width-1 DOWNTO 0) ;
sout : OUT STD_LOGIC_VECTOR (width-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (2*width DOWNTO 0)
);
end component;
component alt_dspbuilder_DFFEALTR
GENERIC
(
width : NATURAL
);
PORT
(
d : IN STD_LOGIC_VECTOR(width-1 DOWNTO 0);
clock : IN STD_LOGIC;
ena : IN STD_LOGIC;
prn : IN STD_LOGIC;
clrn : IN STD_LOGIC;
q : OUT STD_LOGIC_VECTOR(width-1 DOWNTO 0)
);
END component;
component alt_dspbuilder_TFFEALTR
GENERIC
(
width : NATURAL
);
PORT
(
t : IN STD_LOGIC_VECTOR(width-1 DOWNTO 0);
clock : IN STD_LOGIC;
ena : IN STD_LOGIC;
prn : IN STD_LOGIC;
clrn : IN STD_LOGIC;
q : OUT STD_LOGIC_VECTOR(width-1 DOWNTO 0)
);
END component;
component alt_dspbuilder_sCFifoAltr
generic
(
width : natural ;
widthud : natural ;
numwords : natural ;
lpm_hint : string ;
intended_device_family : string ;
showahead_mode : string ;
use_eab : string
);
port
(
data : in std_logic_vector (width-1 downto 0);
wrreq : in std_logic ;
rdreq : in std_logic ;
clock : in std_logic ;
aclr : in std_logic ;
user_aclr : in std_logic ;
sclr : in std_logic ;
q : out std_logic_vector (width-1 downto 0);
full : out std_logic ;
empty : out std_logic ;
usedw : out std_logic_vector (widthud-1 downto 0)
);
end component;
component alt_dspbuilder_sRounderAltr
generic (
widthin : natural;
widthout : natural ;
bround : natural ;
pipeline : natural ;
lpm_representation: string
);
port (
clock : in std_logic;
aclr : in std_logic;
user_aclr : in std_logic;
sclr : in std_logic;
xin : in std_logic_vector(widthin-1 downto 0);
yout : out std_logic_vector(widthout-1 downto 0)
);
end component;
component alt_dspbuilder_ASATPIPE
generic (
widthin : natural ;
widthout : natural ;
bsat : natural ;
lpm_signed : BusArithm ;
pipeline : natural ;
UseCustomValue : natural ;
UpperValue : std_logic_vector ;
LowerValue : std_logic_vector
);
port (
clock : in std_logic;
aclr : in std_logic;
user_aclr : in std_logic;
ena : in std_logic;
sclr : in std_logic;
xin : in std_logic_vector(widthin-1 downto 0);
sat_flag : out std_logic;
yout : out std_logic_vector(widthout-1 downto 0)
);
end component;
component alt_dspbuilder_BarrelShiftAltr
generic (
widthin : natural ;
widthd : natural ;
pipeline : natural ;
ndirection : natural ;
use_dedicated_circuitry : natural
);
port (
xin : in std_logic_vector(widthin-1 downto 0);
distance : in std_logic_vector(widthd-1 downto 0);
sclr : in std_logic;
ena : in std_logic;
clock : in std_logic;
aclr : in std_logic;
direction : in std_logic;
yout : out std_logic_vector(widthin-1 downto 0)
);
end component;
component alt_dspbuilder_BarrelShiftAltrUsg
generic (
widthin : natural ;
widthd : natural ;
pipeline : natural ;
ndirection : natural ;
use_dedicated_circuitry : natural
);
port (
xin : in std_logic_vector(widthin-1 downto 0);
distance : in std_logic_vector(widthd-1 downto 0);
sclr : in std_logic;
clock : in std_logic;
aclr : in std_logic;
user_aclr : in std_logic;
direction : in std_logic;
yout : out std_logic_vector(widthin-1 downto 0)
);
end component;
component alt_dspbuilder_sLFSRAltr
generic (
width : natural ;
LFSRPrimPoly : std_logic_vector ;
RegisterInitialValuesBin : std_logic_vector ;
LFSRstructure : natural;
XorType : natural
);
port (
sclr : in std_logic;
clock : in std_logic;
aclr : in std_logic;
user_aclr : in std_logic;
ena : in std_logic;
sout : out std_logic;
pout : out std_logic_vector(width-1 downto 0)
);
end component;
component alt_dspbuilder_sMultiBitAddSub
generic (
NumberOfInputBits : positive ;
dspb_widthr : positive ;
pipeline : natural ;
lpm_widthcoef : positive ;
coef0 : std_logic_vector ;
coef1 : std_logic_vector ;
coef2 : std_logic_vector ;
coef3 : std_logic_vector ;
coef4 : std_logic_vector ;
coef5 : std_logic_vector ;
coef6 : std_logic_vector ;
coef7 : std_logic_vector
);
port (
clock : in std_logic;
ena : in std_logic;
aclr : in std_logic;
sclr : in std_logic;
dataa : in std_logic_vector(NumberOfInputBits-1 downto 0);
result : out std_logic_vector(dspb_widthr-1 downto 0)
);
end component;
component alt_dspbuilder_sDAMultAddAltr
generic (
nTap : positive ;
widthdata : positive ;
widthrbit : positive ;
widthr : positive ;
widtho : positive ;
vlsb : natural ;
pipeline : natural ;
widthcoef : positive ;
lpm_hint : string ;
coef0 : std_logic_vector ;
coef1 : std_logic_vector ;
coef2 : std_logic_vector ;
coef3 : std_logic_vector ;
coef4 : std_logic_vector ;
coef5 : std_logic_vector ;
coef6 : std_logic_vector ;
coef7 : std_logic_vector
);
port (
clock : in std_logic:='0';
ena : in std_logic:='1';
user_aclr : in std_logic:='0';
aclr : in std_logic:='0';
part_sclr : in std_logic:='0';
dataa0 : in std_logic_vector(widthdata-1 downto 0):=(others=>'0');
dataa1 : in std_logic_vector(widthdata-1 downto 0):=(others=>'0');
dataa2 : in std_logic_vector(widthdata-1 downto 0):=(others=>'0');
dataa3 : in std_logic_vector(widthdata-1 downto 0):=(others=>'0');
dataa4 : in std_logic_vector(widthdata-1 downto 0):=(others=>'0');
dataa5 : in std_logic_vector(widthdata-1 downto 0):=(others=>'0');
dataa6 : in std_logic_vector(widthdata-1 downto 0):=(others=>'0');
dataa7 : in std_logic_vector(widthdata-1 downto 0):=(others=>'0');
result : out std_logic_vector(widtho-vlsb-1 downto 0)
);
end component;
component alt_dspbuilder_sMultAltr
generic (
lpm_widtha : positive ;
lpm_widthb : positive ;
lpm_representation : string ;
lpm_hint : string ;
OutputMsb : natural ;
OutputLsb : natural ;
pipeline : natural
);
port (
clock : in std_logic;
ena : in std_logic;
aclr : in std_logic;
user_aclr : in std_logic;
dataa : in std_logic_vector(lpm_widtha-1 downto 0);
datab : in std_logic_vector(lpm_widthb-1 downto 0);
result : out std_logic_vector(OutputMsb-OutputLsb downto 0)
);
end component;
component alt_dspbuilder_sBitWiseBusOpaltr
generic (
lpm_width : positive ;
Lop : LogicalOperator
);
port (
dataa : in std_logic_vector(lpm_width-1 downto 0);
datab : in std_logic_vector(lpm_width-1 downto 0);
result : out std_logic_vector(lpm_width-1 downto 0)
);
end component;
component alt_dspbuilder_sPaddAltr
generic (
width : positive ;
size : positive ;
pipeline : natural ;
SequenceLength : positive ;
SequenceValue : std_logic_vector ;
widthr : positive
);
port (
dataa : in std_logic_vector(width*size-1 downto 0);
clock : in std_logic;
ena : in std_logic;
sclr : in std_logic;
aclr : in std_logic;
user_aclr : in std_logic;
result : out std_logic_vector(widthr-1 downto 0)
);
end component;
component alt_dspbuilder_sMuxAltr
generic ( lpm_pipeline : NATURAL:=0;
lpm_size : positive;
lpm_widths : positive;
lpm_width : positive;
SelOneHot : natural);
PORT ( clock : in std_logic ;
aclr : in std_logic := '0';
user_aclr : in std_logic := '0';
ena : in std_logic := '1';
data : in std_logic_vector (lpm_width*lpm_size-1 downto 0);
sel : in std_logic_vector (lpm_widths-1 downto 0);
result : out std_logic_vector (lpm_width-1 downto 0));
end component;
component alt_dspbuilder_ClkDivAltr
GENERIC
(
widthcnt : NATURAL
);
PORT
(
aclr : IN STD_LOGIC;
clock : IN STD_LOGIC ;
clock_out : out STD_LOGIC
);
end component;
COMPONENT alt_dspbuilder_parallel_add_db
GENERIC (
width : NATURAL;
representation : STRING;
size : NATURAL;
msw_subtract : STRING;
pipeline : NATURAL;
result_alignment : STRING;
widthr : NATURAL;
shift : NATURAL
);
PORT (
clken : IN STD_LOGIC ;
clock : IN STD_LOGIC ;
aclr : IN STD_LOGIC ;
data : IN STD_LOGIC_2DSPBUILDER (size-1 DOWNTO 0, width-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (widthr-1 DOWNTO 0)
);
END COMPONENT;
component alt_dspbuilder_SDemuxAltr
generic (
width : natural ;
widthsel : natural ;
size : natural
);
port (
din : in std_logic_vector(width-1 downto 0);
sel : in std_logic_vector(widthsel-1 downto 0);
clock : in std_logic;
ena : in std_logic;
sclr : in std_logic;
aclr : in std_logic;
user_aclr : in std_logic;
result : out std_logic_vector(size*width-1 downto 0)
);
end component ;
component alt_dspbuilder_sDcFifoAltr
generic (
intended_device_family : STRING;
lpm_width : NATURAL;
lpm_numwords : NATURAL;
lpm_hint : STRING;
clocks_are_synchronized : STRING;
lpm_widthu : NATURAL);
port (data : in STD_LOGIC_VECTOR (lpm_width-1 downto 0);
wrclk : in STD_LOGIC ;
aclr : in STD_LOGIC ;
user_aclr : in STD_LOGIC ;
rdreq : in STD_LOGIC ;
wrreq : in STD_LOGIC ;
rdclk : in STD_LOGIC ;
rdfull : out STD_LOGIC ;
rdempty : out STD_LOGIC ;
wrusedw : out STD_LOGIC_VECTOR (lpm_widthu-1 downto 0):=(others=>'0');
wrfull : out STD_LOGIC ;
wrempty : out STD_LOGIC ;
q : out STD_LOGIC_VECTOR (lpm_width-1 downto 0);
rdusedw : out STD_LOGIC_VECTOR (lpm_widthu-1 downto 0):=(others=>'0'));
end component;
component alt_dspbuilder_sSqrAltr
generic ( lpm_width : positive;
q_port_width : positive;
r_port_width : positive;
pipeline : NATURAL);
port ( radical : in STD_LOGIC_VECTOR (lpm_width-1 downto 0);
clock : in STD_LOGIC;
aclr : in STD_LOGIC;
user_aclr : in STD_LOGIC;
ena : in STD_LOGIC;
q : out STD_LOGIC_VECTOR (q_port_width-1 downto 0);
remainder : out STD_LOGIC_VECTOR (r_port_width-1 downto 0));
end component;
component alt_dspbuilder_sStepAltr
generic (
StepDelay : positive ;
direction : natural
);
port (
clock : in std_logic;
ena : in std_logic;
sclr : in std_logic;
aclr : in std_logic;
user_aclr : in std_logic;
q : out std_logic
);
end component ;
component alt_dspbuilder_sImpulse11Altr
port (
clock : in std_logic;
ena : in std_logic :='1';
sclr : in std_logic :='0';
aclr : in std_logic :='0';
q : out std_logic
);
end component ;
component alt_dspbuilder_sImpulse1nAltr
generic (
Impulsewidth : positive
);
port (
clock : in std_logic;
ena : in std_logic :='1';
sclr : in std_logic :='0';
aclr : in std_logic :='0';
q : out std_logic
);
end component ;
component alt_dspbuilder_sImpulsen1Altr
generic (
Impulsedelay : positive
);
port (
clock : in std_logic;
ena : in std_logic :='1';
sclr : in std_logic :='0';
aclr : in std_logic :='0';
q : out std_logic
);
end component ;
component alt_dspbuilder_sImpulsennAltr
generic (
Impulsedelay : positive ;
Impulsewidth : positive
);
port (
clock : in std_logic ;
ena : in std_logic ;
sclr : in std_logic ;
aclr : in std_logic :='0';
q : out std_logic
);
end component ;
component alt_dspbuilder_sImpulseAltr
generic (
Impulsedelay : positive ;
Impulsewidth : positive
);
port (
clock : in std_logic;
ena : in std_logic;
sclr : in std_logic;
aclr : in std_logic;
user_aclr : in std_logic;
q : out std_logic
);
end component ;
component alt_dspbuilder_jtag_node is
generic (
width : positive := 8;
-- Node Info ID that uniquely identifies a instance of the node.
-- MFG ID: 110 (0x6E)
-- NODE ID: 6 (0x6) (HIL)
-- Version: 0 (0x0)
-- Instance ID: 0 (0x0)
sld_node_info : positive := 3173888); -- 0x00306E00
port (
-- Shared JTAG ports
raw_tck : in std_logic; -- JTAG test clock
raw_tms : in std_logic; -- JTAG test mode select signal
tdi : in std_logic; -- JTAG test data input, comes LSB first
jtag_state_tlr : in std_logic; -- Signals that the JSM is in the Test_Logic_Reset state
jtag_state_rti : in std_logic; -- Signals that the JSM is in the Run_Test/Idle state
jtag_state_sdrs : in std_logic; -- Signals that the JSM is in the Select_DR_Scan state
jtag_state_cdr : in std_logic; -- Signals that the JSM is in the Capture_DR state
jtag_state_sdr : in std_logic; -- Signals that the JSM is in the Shift_DR state
jtag_state_e1dr : in std_logic; -- Signals that the JSM is in the Exit1_DR state
jtag_state_pdr : in std_logic; -- Signals that the JSM is in the Pause_DR state
jtag_state_e2dr : in std_logic; -- Signals that the JSM is in the Exit2_DR state
jtag_state_udr : in std_logic; -- Signals that the JSM is in the Update_DR state
jtag_state_sirs : in std_logic; -- Signals that the JSM is in the Select_IR_Scan state
jtag_state_cir : in std_logic; -- Signals that the JSM is in the Capture_IR state
jtag_state_sir : in std_logic; -- Signals that the JSM is in the Shift_IR state
jtag_state_e1ir : in std_logic; -- Signals that the JSM is in the Exit1_IR state
jtag_state_pir : in std_logic; -- Signals that the JSM is in the Pause_IR state
jtag_state_e2ir : in std_logic; -- Signals that the JSM is in the Exit2_IR state
jtag_state_uir : in std_logic; -- Signals that the JSM is in the Update_IR state
usr1 : in std_logic; -- Signals that the current instruction in the JSM is the USER1 instruction
clrn : in std_logic; -- Asynchronous clear
-- Node-specific JTAG ports
ena : in std_logic; -- Indicates that the current instruction in the Hub is for Node i
ir_in : in std_logic_vector(width-1 downto 0); -- Node i IR
tdo : out std_logic; -- Node i JTAG test data out
ir_out : out std_logic_vector(width-1 downto 0); -- Node i IR capture port
-- Interface to node
user_clk : in std_logic;
user_tck : out std_logic;
node_state_uir : out std_logic;
node_state_sdr : out std_logic;
user_tdi : out std_logic;
user_tdo : out std_logic;
user_IRin : out std_logic_vector(width-1 downto 0);
user_IRout : in std_logic_vector(width-1 downto 0);
user_cir : out std_logic; -- Capture IR
user_sir : out std_logic; -- Shift IR
user_uir : out std_logic; -- Update IR
user_cdr : out std_logic; -- Capture DR
user_sdr : out std_logic; -- Shift DR
user_udr : out std_logic); -- Update DR
end component;
component alt_dspbuilder_clock_crossing_enable is
port (
source_clk : in std_logic;
source_ena : in std_logic;
dest_clk : in std_logic;
dest_ena : out std_logic);
end component;
end alt_dspbuilder_package ;
package body alt_dspbuilder_package is
function nbitnecessary(value: integer) return integer is
-- return the number of bit necessary to code the positive value-1
variable inc: integer ;
variable tmp: integer ;
begin
tmp := value-1;
inc := 0;
if (tmp>0) then
for i in 0 to value+1 loop
if (tmp > 0 ) then
tmp := tmp / 2;
inc := inc +1;
end if ;
end loop ;
else
inc :=0;
end if ;
return inc;
end nbitnecessary;
function nSignbitnecessary(value: integer) return integer is
-- return the number of bit necessary to code value-1
variable inc: integer ;
variable ttmp: integer ;
variable tmp: integer ;
begin
if (value<0) then
ttmp:=-value;
else
ttmp:=value;
end if;
tmp := ttmp;
inc := 0;
if (ttmp>0) then
for i in 0 to ttmp+2 loop
if (tmp > 0 ) then
tmp := tmp / 2;
inc := inc +1;
end if ;
end loop ;
else
inc :=1;
end if ;
return inc+1;
end nSignbitnecessary;
function Nstd_bitnecessary(DSigned : std_logic_vector) return integer is
-- return the number of bit necessary for teh signed inpt constant
-- of type std_logic_vector
constant w : integer :=DSigned'Length;
variable r : integer :=w;
variable d : integer :=w-2;
constant svec : std_logic_vector(w-1 downto 0):=DSigned;
begin
if (d>0) then
if (svec(w-1)='0') then
while (svec(d)='0' and d>0) loop
d:=d-1;
end loop;
else
while (svec(d)='1' and d>0) loop
d:=d-1;
end loop;
end if;
d:=d+2;
if (d<r) then
r := d;
end if;
end if;
return r;
end Nstd_bitnecessary;
function StdPowerOfTwo(DSigned : std_logic_vector) return integer is -- return 0 if not power of tow otherwisse return power of two
constant w : integer :=DSigned'Length;
variable r : integer :=0;
variable p : integer :=0;
variable np : integer :=0;
constant svec : std_logic_vector(w-1 downto 0):=DSigned;
begin
for i in 0 to w-1 loop
if svec(i) = '1' then
p:=i;
np:=np+1;
end if;
end loop;
if (np=1) then
r:= p;
end if;
return r;
end;
function int2ustd(value : integer; width : integer) return std_logic_vector is
-- convert integer to unsigned std_logicvector
begin
return conv_std_logic_vector(CONV_UNSIGNED(value, width ), width);
end int2ustd;
function int2sstd(value : integer; width : integer) return std_logic_vector is
-- convert integer to signed std_logicvector
begin
if (value<0) then
return conv_std_logic_vector(CONV_UNSIGNED(((2**(width))+value), width ), width);
else
return conv_std_logic_vector(CONV_UNSIGNED(value, width ), width);
end if;
end int2sstd;
function int2bit(value : integer) return std_logic is
-- convert integer to signed std_logicvector
begin
if (value>0) then
return '1';
else
return '0';
end if;
end int2bit;
function bitvec2std(bv : bit_vector) return std_logic_vector is
-- convert bit_vector to std_logic_vector
variable s : std_logic_vector(bv'length-1 downto 0) :=(others=>'0');
begin
for i in 0 to bv'length-1 loop
if '1'=bv(i) then
s(i) :='1';
else
s(i) :='0';
end if;
end loop;
return s;
end bitvec2std;
function cal_width_lpm_mult(b: boolean ; w : integer) return positive is
-- Check if the multipler reach the max negative number
variable i : positive;
begin
if b then
i := w-1;
else
i := w;
end if;
return i;
end cal_width_lpm_mult;
function integer_is_even(i: integer ) return boolean is
variable even : boolean;
begin
even:= ((i+1)/2) = (i/2);
return even;
end integer_is_even;
function ceil_divide(i:integer;d:integer) return integer is
variable res : integer;
begin
if d/=0 then
if ((i rem d)>0) then
res := i/d+1;
else
res := i/d;
end if ;
else
res :=0;
end if ;
return res;
end ;
function floor_divide(i:integer;d:integer) return integer is
begin
if d/=0 then
return i/d;
else
return 0;
end if ;
end ;
function ToNatural(i:integer) return integer is
variable inc: integer ;
begin
if (i<0) then
inc := 0;
else
inc :=i;
end if ;
return inc;
end ;
function To_String (Value: Integer) return String is
variable V: Integer;
variable Result: String(1 to 11);
variable Width: Natural := 0;
begin
V := abs Value;
for I in Result'Reverse_range loop
case V mod 10 is
when 0 => Result(I) := '0';
when 1 => Result(I) := '1';
when 2 => Result(I) := '2';
when 3 => Result(I) := '3';
when 4 => Result(I) := '4';
when 5 => Result(I) := '5';
when 6 => Result(I) := '6';
when 7 => Result(I) := '7';
when 8 => Result(I) := '8';
when 9 => Result(I) := '9';
when others =>
Result(I) := '?';
end case;
if V > 0 then
Width := Width + 1;
end if;
V := V / 10;
end loop;
if Width = 0 then
Width := 1;
end if;
if Value < 0 then
Result(Result'Length - Width) := '-';
Width := Width + 1;
end if;
return Result(Result'Length - Width + 1 to Result'Length);
end To_String;
function To_Character (Value: Std_logic) return Character is
begin
case Value is
when 'U' => return 'U';
when 'X' => return 'X';
when '0' => return '0';
when '1' => return '1';
when 'W' => return 'W';
when 'L' => return 'L';
when 'H' => return 'H';
when 'Z' => return 'Z';
when '-' => return '-';
end case;
end To_Character;
function To_String (Value: Std_logic_vector) return String is
constant V: Std_logic_vector(1 to Value'Length) := Value;
variable Result: String(1 to Value'Length);
begin
for I in Result'Range loop
Result(I) := To_character(V(I));
end loop;
return Result;
end To_String;
function cp_str(s1: string; s2: string) return boolean is
variable b : boolean :=false;
begin
if (s1'Length=s2'Length) then
if s1=s2 then
b:=true;
end if;
end if;
return b;
end cp_str;
end alt_dspbuilder_package;
| gpl-3.0 |
asicguy/gplgpu | hdl/sim_lib/arriaii_components.vhd | 1 | 78191 | -- Copyright (C) 1991-2011 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- Quartus II 11.0 Build 157 04/27/2011
LIBRARY IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;
use work.arriaii_atom_pack.all;
package arriaii_components is
--
-- arriaii_lcell_comb
--
COMPONENT arriaii_lcell_comb
generic (
lut_mask : std_logic_vector(63 downto 0) := (OTHERS => '1');
shared_arith : string := "off";
extended_lut : string := "off";
dont_touch : string := "off";
lpm_type : string := "arriaii_lcell_comb";
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*";
tpd_dataa_combout : VitalDelayType01 := DefPropDelay01;
tpd_datab_combout : VitalDelayType01 := DefPropDelay01;
tpd_datac_combout : VitalDelayType01 := DefPropDelay01;
tpd_datad_combout : VitalDelayType01 := DefPropDelay01;
tpd_datae_combout : VitalDelayType01 := DefPropDelay01;
tpd_dataf_combout : VitalDelayType01 := DefPropDelay01;
tpd_datag_combout : VitalDelayType01 := DefPropDelay01;
tpd_dataa_sumout : VitalDelayType01 := DefPropDelay01;
tpd_datab_sumout : VitalDelayType01 := DefPropDelay01;
tpd_datac_sumout : VitalDelayType01 := DefPropDelay01;
tpd_datad_sumout : VitalDelayType01 := DefPropDelay01;
tpd_dataf_sumout : VitalDelayType01 := DefPropDelay01;
tpd_cin_sumout : VitalDelayType01 := DefPropDelay01;
tpd_sharein_sumout : VitalDelayType01 := DefPropDelay01;
tpd_dataa_cout : VitalDelayType01 := DefPropDelay01;
tpd_datab_cout : VitalDelayType01 := DefPropDelay01;
tpd_datac_cout : VitalDelayType01 := DefPropDelay01;
tpd_datad_cout : VitalDelayType01 := DefPropDelay01;
tpd_dataf_cout : VitalDelayType01 := DefPropDelay01;
tpd_cin_cout : VitalDelayType01 := DefPropDelay01;
tpd_sharein_cout : VitalDelayType01 := DefPropDelay01;
tpd_dataa_shareout : VitalDelayType01 := DefPropDelay01;
tpd_datab_shareout : VitalDelayType01 := DefPropDelay01;
tpd_datac_shareout : VitalDelayType01 := DefPropDelay01;
tpd_datad_shareout : VitalDelayType01 := DefPropDelay01;
tipd_dataa : VitalDelayType01 := DefPropDelay01;
tipd_datab : VitalDelayType01 := DefPropDelay01;
tipd_datac : VitalDelayType01 := DefPropDelay01;
tipd_datad : VitalDelayType01 := DefPropDelay01;
tipd_datae : VitalDelayType01 := DefPropDelay01;
tipd_dataf : VitalDelayType01 := DefPropDelay01;
tipd_datag : VitalDelayType01 := DefPropDelay01;
tipd_cin : VitalDelayType01 := DefPropDelay01;
tipd_sharein : VitalDelayType01 := DefPropDelay01
);
port (
dataa : in std_logic := '0';
datab : in std_logic := '0';
datac : in std_logic := '0';
datad : in std_logic := '0';
datae : in std_logic := '0';
dataf : in std_logic := '0';
datag : in std_logic := '0';
cin : in std_logic := '0';
sharein : in std_logic := '0';
combout : out std_logic;
sumout : out std_logic;
cout : out std_logic;
shareout : out std_logic
);
END COMPONENT;
--
-- arriaii_routing_wire
--
COMPONENT arriaii_routing_wire
generic (
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
tpd_datain_dataout : VitalDelayType01 := DefPropDelay01;
tpd_datainglitch_dataout : VitalDelayType01 := DefPropDelay01;
tipd_datain : VitalDelayType01 := DefPropDelay01
);
PORT (
datain : in std_logic;
dataout : out std_logic
);
END COMPONENT;
--
-- arriaii_lvds_transmitter
--
COMPONENT arriaii_lvds_transmitter
GENERIC ( channel_width : integer := 10;
bypass_serializer : String := "false";
invert_clock : String := "false";
use_falling_clock_edge : String := "false";
use_serial_data_input : String := "false";
use_post_dpa_serial_data_input : String := "false";
is_used_as_outclk : String := "false";
tx_output_path_delay_engineering_bits : Integer := -1;
enable_dpaclk_to_lvdsout : string := "off";
preemphasis_setting : integer := 0;
vod_setting : integer := 0;
differential_drive : integer := 0;
lpm_type : string := "arriaii_lvds_transmitter";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tpd_clk0_dataout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clk0_dataout_negedge : VitalDelayType01 := DefPropDelay01;
tpd_serialdatain_dataout : VitalDelayType01 := DefPropDelay01;
tpd_dpaclkin_dataout : VitalDelayType01 := DefPropDelay01;
tpd_postdpaserialdatain_dataout : VitalDelayType01 := DefPropDelay01;
tipd_clk0 : VitalDelayType01 := DefpropDelay01;
tipd_enable0 : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayArrayType01(9 downto 0) := (OTHERS => DefpropDelay01);
tipd_serialdatain : VitalDelayType01 := DefpropDelay01;
tipd_dpaclkin : VitalDelayType01 := DefpropDelay01;
tipd_postdpaserialdatain : VitalDelayType01 := DefpropDelay01
);
PORT ( clk0 : in std_logic;
enable0 : in std_logic := '0';
datain : in std_logic_vector(channel_width - 1 downto 0) := (OTHERS => '0');
serialdatain : in std_logic := '0';
postdpaserialdatain : in std_logic := '0';
dpaclkin : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
dataout : out std_logic;
serialfdbkout : out std_logic
);
END COMPONENT;
--
-- arriaii_rublock
--
COMPONENT arriaii_rublock
generic
(
sim_init_config : string := "factory";
sim_init_watchdog_value : integer := 0;
sim_init_status : integer := 0;
lpm_type : string := "arriaii_rublock"
);
port
(
clk : in std_logic;
shiftnld : in std_logic;
captnupdt : in std_logic;
regin : in std_logic;
rsttimer : in std_logic;
rconfig : in std_logic;
regout : out std_logic
);
END COMPONENT;
--
-- arriaii_oscillator
--
COMPONENT arriaii_oscillator
generic
(
lpm_type: string := "arriaii_oscillator";
TimingChecksOn: Boolean := True;
XOn: Boolean := DefGlitchXOn;
MsgOn: Boolean := DefGlitchMsgOn;
tpd_oscena_clkout_posedge : VitalDelayType01 := DefPropDelay01;
tipd_oscena : VitalDelayType01 := DefPropDelay01
);
port
(
oscena : in std_logic;
clkout : out std_logic
);
END COMPONENT;
--
-- arriaii_ram_block
--
COMPONENT arriaii_ram_block
GENERIC (
operation_mode : STRING := "single_port";
mixed_port_feed_through_mode : STRING := "dont_care";
ram_block_type : STRING := "auto";
logical_ram_name : STRING := "ram_name";
init_file : STRING := "init_file.hex";
init_file_layout : STRING := "none";
enable_ecc : STRING := "false";
width_eccstatus : INTEGER := 3;
data_interleave_width_in_bits : INTEGER := 1;
data_interleave_offset_in_bits : INTEGER := 1;
port_a_logical_ram_depth : INTEGER := 0;
port_a_logical_ram_width : INTEGER := 0;
port_a_first_address : INTEGER := 0;
port_a_last_address : INTEGER := 0;
port_a_first_bit_number : INTEGER := 0;
port_a_address_clear : STRING := "none";
port_a_data_out_clear : STRING := "none";
port_a_data_in_clock : STRING := "clock0";
port_a_address_clock : STRING := "clock0";
port_a_write_enable_clock : STRING := "clock0";
port_a_read_enable_clock : STRING := "clock0";
port_a_byte_enable_clock : STRING := "clock0";
port_a_data_out_clock : STRING := "none";
port_a_data_width : INTEGER := 1;
port_a_address_width : INTEGER := 1;
port_a_byte_enable_mask_width : INTEGER := 1;
port_b_logical_ram_depth : INTEGER := 0;
port_b_logical_ram_width : INTEGER := 0;
port_b_first_address : INTEGER := 0;
port_b_last_address : INTEGER := 0;
port_b_first_bit_number : INTEGER := 0;
port_b_address_clear : STRING := "none";
port_b_data_out_clear : STRING := "none";
port_b_data_in_clock : STRING := "clock1";
port_b_address_clock : STRING := "clock1";
port_b_write_enable_clock: STRING := "clock1";
port_b_read_enable_clock: STRING := "clock1";
port_b_byte_enable_clock : STRING := "clock1";
port_b_data_out_clock : STRING := "none";
port_b_data_width : INTEGER := 1;
port_b_address_width : INTEGER := 1;
port_b_byte_enable_mask_width : INTEGER := 1;
port_a_read_during_write_mode : STRING := "new_data_no_nbe_read";
port_b_read_during_write_mode : STRING := "new_data_no_nbe_read";
power_up_uninitialized : STRING := "false";
port_b_byte_size : INTEGER := 0;
port_a_byte_size : INTEGER := 0;
lpm_type : string := "arriaii_ram_block";
lpm_hint : string := "true";
clk0_input_clock_enable : STRING := "none"; -- ena0,ena2,none
clk0_core_clock_enable : STRING := "none"; -- ena0,ena2,none
clk0_output_clock_enable : STRING := "none"; -- ena0,none
clk1_input_clock_enable : STRING := "none"; -- ena1,ena3,none
clk1_core_clock_enable : STRING := "none"; -- ena1,ena3,none
clk1_output_clock_enable : STRING := "none"; -- ena1,none
clock_duty_cycle_dependence : STRING := "On";
mem_init0 : BIT_VECTOR := X"0";
mem_init1 : BIT_VECTOR := X"0";
mem_init2 : BIT_VECTOR := X"0";
mem_init3 : BIT_VECTOR := X"0";
mem_init4 : BIT_VECTOR := X"0";
mem_init5 : BIT_VECTOR := X"0";
mem_init6 : BIT_VECTOR := X"0";
mem_init7 : BIT_VECTOR := X"0";
mem_init8 : BIT_VECTOR := X"0";
mem_init9 : BIT_VECTOR := X"0";
mem_init10 : BIT_VECTOR := X"0";
mem_init11 : BIT_VECTOR := X"0";
mem_init12 : BIT_VECTOR := X"0";
mem_init13 : BIT_VECTOR := X"0";
mem_init14 : BIT_VECTOR := X"0";
mem_init15 : BIT_VECTOR := X"0";
mem_init16 : BIT_VECTOR := X"0";
mem_init17 : BIT_VECTOR := X"0";
mem_init18 : BIT_VECTOR := X"0";
mem_init19 : BIT_VECTOR := X"0";
mem_init20 : BIT_VECTOR := X"0";
mem_init21 : BIT_VECTOR := X"0";
mem_init22 : BIT_VECTOR := X"0";
mem_init23 : BIT_VECTOR := X"0";
mem_init24 : BIT_VECTOR := X"0";
mem_init25 : BIT_VECTOR := X"0";
mem_init26 : BIT_VECTOR := X"0";
mem_init27 : BIT_VECTOR := X"0";
mem_init28 : BIT_VECTOR := X"0";
mem_init29 : BIT_VECTOR := X"0";
mem_init30 : BIT_VECTOR := X"0";
mem_init31 : BIT_VECTOR := X"0";
mem_init32 : BIT_VECTOR := X"0";
mem_init33 : BIT_VECTOR := X"0";
mem_init34 : BIT_VECTOR := X"0";
mem_init35 : BIT_VECTOR := X"0";
mem_init36 : BIT_VECTOR := X"0";
mem_init37 : BIT_VECTOR := X"0";
mem_init38 : BIT_VECTOR := X"0";
mem_init39 : BIT_VECTOR := X"0";
mem_init40 : BIT_VECTOR := X"0";
mem_init41 : BIT_VECTOR := X"0";
mem_init42 : BIT_VECTOR := X"0";
mem_init43 : BIT_VECTOR := X"0";
mem_init44 : BIT_VECTOR := X"0";
mem_init45 : BIT_VECTOR := X"0";
mem_init46 : BIT_VECTOR := X"0";
mem_init47 : BIT_VECTOR := X"0";
mem_init48 : BIT_VECTOR := X"0";
mem_init49 : BIT_VECTOR := X"0";
mem_init50 : BIT_VECTOR := X"0";
mem_init51 : BIT_VECTOR := X"0";
mem_init52 : BIT_VECTOR := X"0";
mem_init53 : BIT_VECTOR := X"0";
mem_init54 : BIT_VECTOR := X"0";
mem_init55 : BIT_VECTOR := X"0";
mem_init56 : BIT_VECTOR := X"0";
mem_init57 : BIT_VECTOR := X"0";
mem_init58 : BIT_VECTOR := X"0";
mem_init59 : BIT_VECTOR := X"0";
mem_init60 : BIT_VECTOR := X"0";
mem_init61 : BIT_VECTOR := X"0";
mem_init62 : BIT_VECTOR := X"0";
mem_init63 : BIT_VECTOR := X"0";
mem_init64 : BIT_VECTOR := X"0";
mem_init65 : BIT_VECTOR := X"0";
mem_init66 : BIT_VECTOR := X"0";
mem_init67 : BIT_VECTOR := X"0";
mem_init68 : BIT_VECTOR := X"0";
mem_init69 : BIT_VECTOR := X"0";
mem_init70 : BIT_VECTOR := X"0";
mem_init71 : BIT_VECTOR := X"0";
connectivity_checking : string := "off"
);
PORT (
portadatain : IN STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0) := (OTHERS => '0');
portaaddr : IN STD_LOGIC_VECTOR(port_a_address_width - 1 DOWNTO 0) := (OTHERS => '0');
portawe : IN STD_LOGIC := '0';
portare : IN STD_LOGIC := '1';
portbdatain : IN STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0) := (OTHERS => '0');
portbaddr : IN STD_LOGIC_VECTOR(port_b_address_width - 1 DOWNTO 0) := (OTHERS => '0');
portbwe : IN STD_LOGIC := '0';
portbre : IN STD_LOGIC := '1';
clk0 : IN STD_LOGIC := '0';
clk1 : IN STD_LOGIC := '0';
ena0 : IN STD_LOGIC := '1';
ena1 : IN STD_LOGIC := '1';
ena2 : IN STD_LOGIC := '1';
ena3 : IN STD_LOGIC := '1';
clr0 : IN STD_LOGIC := '0';
clr1 : IN STD_LOGIC := '0';
portabyteenamasks : IN STD_LOGIC_VECTOR(port_a_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '1');
portbbyteenamasks : IN STD_LOGIC_VECTOR(port_b_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '1');
devclrn : IN STD_LOGIC := '1';
devpor : IN STD_LOGIC := '1';
portaaddrstall : IN STD_LOGIC := '0';
portbaddrstall : IN STD_LOGIC := '0';
eccstatus : OUT STD_LOGIC_VECTOR(width_eccstatus - 1 DOWNTO 0) := (OTHERS => '0');
dftout : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := "000000000";
portadataout : OUT STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0);
portbdataout : OUT STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0)
);
END COMPONENT;
--
-- arriaii_ff
--
COMPONENT arriaii_ff
generic (
power_up : string := "low";
x_on_violation : string := "on";
lpm_type : string := "arriaii_ff";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clrn_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_asdata_q: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_asdata : VitalDelayType01 := DefPropDelay01;
tipd_sclr : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_clrn : VitalDelayType01 := DefPropDelay01;
tipd_aload : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*"
);
port (
d : in std_logic := '0';
clk : in std_logic := '0';
clrn : in std_logic := '1';
aload : in std_logic := '0';
sclr : in std_logic := '0';
sload : in std_logic := '0';
ena : in std_logic := '1';
asdata : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
q : out std_logic
);
END COMPONENT;
--
-- arriaii_clkselect
--
COMPONENT arriaii_clkselect
generic (
lpm_type : STRING := "arriaii_clkselect";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tipd_inclk : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tipd_clkselect : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tpd_inclk_outclk : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tpd_clkselect_outclk : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01)
);
port (
inclk : in std_logic_vector(3 downto 0) := "0000";
clkselect : in std_logic_vector(1 downto 0) := "00";
outclk : out std_logic
);
END COMPONENT;
--
-- arriaii_clkena
--
COMPONENT arriaii_clkena
generic (
clock_type : STRING := "Auto";
lpm_type : STRING := "arriaii_clkena";
ena_register_mode : STRING := "Falling Edge";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tipd_inclk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01
);
port (
inclk : in std_logic := '0';
ena : in std_logic := '1';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
enaout : out std_logic;
outclk : out std_logic
);
END COMPONENT;
--
-- arriaii_mlab_cell
--
COMPONENT arriaii_mlab_cell
GENERIC (
logical_ram_name : STRING := "lutram";
init_file : STRING := "UNUSED";
data_interleave_offset_in_bits : INTEGER := 1;
logical_ram_depth : INTEGER := 0;
logical_ram_width : INTEGER := 0;
first_address : INTEGER := 0;
last_address : INTEGER := 0;
first_bit_number : INTEGER := 0;
data_width : INTEGER := 1;
address_width : INTEGER := 1;
byte_enable_mask_width : INTEGER := 1;
byte_size : INTEGER := 1;
lpm_type : string := "arriaii_mlab_cell";
lpm_hint : string := "true";
mixed_port_feed_through_mode : string := "dont_care";
mem_init0 : BIT_VECTOR := X"0";
tipd_clk0 : VitalDelayType01 := DefPropDelay01;
tipd_ena0 : VitalDelayType01 := DefPropDelay01;
tipd_portaaddr : VitalDelayArrayType01(7 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_portbaddr : VitalDelayArrayType01(7 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_portabyteenamasks : VitalDelayArrayType01(20 DOWNTO 0) := (OTHERS => DefPropDelay01);
tsetup_portaaddr_clk0_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
tsetup_portabyteenamasks_clk0_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena0_clk0_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_portaaddr_clk0_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_portabyteenamasks_clk0_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_ena0_clk0_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_portbaddr_portbdataout : VitalDelayType01 := DefPropDelay01
);
PORT (
portadatain : IN STD_LOGIC_VECTOR(data_width - 1 DOWNTO 0) := (OTHERS => '0');
portaaddr : IN STD_LOGIC_VECTOR(address_width - 1 DOWNTO 0) := (OTHERS => '0');
portabyteenamasks : IN STD_LOGIC_VECTOR(byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '1');
portbaddr : IN STD_LOGIC_VECTOR(address_width - 1 DOWNTO 0) := (OTHERS => '0');
clk0 : IN STD_LOGIC := '0';
ena0 : IN STD_LOGIC := '1';
portbdataout : OUT STD_LOGIC_VECTOR(data_width - 1 DOWNTO 0)
);
END COMPONENT;
--
-- arriaii_io_ibuf
--
COMPONENT arriaii_io_ibuf
GENERIC (
tipd_i : VitalDelayType01 := DefPropDelay01;
tipd_ibar : VitalDelayType01 := DefPropDelay01;
tpd_i_o : VitalDelayType01 := DefPropDelay01;
tpd_ibar_o : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
differential_mode : string := "false";
bus_hold : string := "false";
simulate_z_as : string := "Z";
lpm_type : string := "arriaii_io_ibuf"
);
PORT (
i : IN std_logic := '0';
ibar : IN std_logic := '0';
o : OUT std_logic
);
END COMPONENT;
--
-- arriaii_io_obuf
--
COMPONENT arriaii_io_obuf
GENERIC (
tipd_i : VitalDelayType01 := DefPropDelay01;
tipd_oe : VitalDelayType01 := DefPropDelay01;
tipd_seriesterminationcontrol : VitalDelayArrayType01(15 DOWNTO 0) := (others => DefPropDelay01 );
tpd_i_o : VitalDelayType01 := DefPropDelay01;
tpd_oe_o : VitalDelayType01 := DefPropDelay01;
tpd_i_obar : VitalDelayType01 := DefPropDelay01;
tpd_oe_obar : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
open_drain_output : string := "false";
bus_hold : string := "false";
lpm_type : string := "arriaii_io_obuf"
);
PORT (
i : IN std_logic := '0';
oe : IN std_logic := '1';
seriesterminationcontrol : IN std_logic_vector(15 DOWNTO 0) := (others => '0');
devoe : IN std_logic := '1';
o : OUT std_logic;
obar : OUT std_logic
);
END COMPONENT;
--
-- arriaii_ddio_in
--
COMPONENT arriaii_ddio_in
generic(
tipd_datain : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_clkn : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_sreset : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
power_up : string := "low";
async_mode : string := "none";
sync_mode : string := "none";
use_clkn : string := "false";
lpm_type : string := "arriaii_ddio_in"
);
PORT (
datain : IN std_logic := '0';
clk : IN std_logic := '0';
clkn : IN std_logic := '0';
ena : IN std_logic := '1';
areset : IN std_logic := '0';
sreset : IN std_logic := '0';
regoutlo : OUT std_logic;
regouthi : OUT std_logic;
dfflo : OUT std_logic;
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END COMPONENT;
--
-- arriaii_ddio_oe
--
COMPONENT arriaii_ddio_oe
generic(
tipd_oe : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_sreset : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
power_up : string := "low";
async_mode : string := "none";
sync_mode : string := "none";
lpm_type : string := "arriaii_ddio_oe"
);
PORT (
oe : IN std_logic := '1';
clk : IN std_logic := '0';
ena : IN std_logic := '1';
areset : IN std_logic := '0';
sreset : IN std_logic := '0';
dataout : OUT std_logic;
dfflo : OUT std_logic;
dffhi : OUT std_logic;
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END COMPONENT;
--
-- arriaii_ddio_out
--
COMPONENT arriaii_ddio_out
generic(
tipd_datainlo : VitalDelayType01 := DefPropDelay01;
tipd_datainhi : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_clkhi : VitalDelayType01 := DefPropDelay01;
tipd_clklo : VitalDelayType01 := DefPropDelay01;
tipd_muxsel : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_sreset : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
power_up : string := "low";
async_mode : string := "none";
sync_mode : string := "none";
half_rate_mode : string := "false";
use_new_clocking_model : string := "false";
lpm_type : string := "arriaii_ddio_out"
);
PORT (
datainlo : IN std_logic := '0';
datainhi : IN std_logic := '0';
clk : IN std_logic := '0';
clkhi : IN std_logic := '0';
clklo : IN std_logic := '0';
muxsel : IN std_logic := '0';
ena : IN std_logic := '1';
areset : IN std_logic := '0';
sreset : IN std_logic := '0';
dataout : OUT std_logic;
dfflo : OUT std_logic;
dffhi : OUT std_logic_vector(1 downto 0) ;
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END COMPONENT;
--
-- arriaii_dll
--
COMPONENT arriaii_dll
GENERIC (
input_frequency : string := "0 ps";
delay_buffer_mode : string := "low";
delay_chain_length : integer := 12;
delayctrlout_mode : string := "normal";
jitter_reduction : string := "false";
use_upndnin : string := "false";
use_upndninclkena : string := "false";
dual_phase_comparators : string := "true";
sim_valid_lock : integer := 16;
sim_valid_lockcount : integer := 0; -- 10000 = 1000 + 100*dllcounter
sim_low_buffer_intrinsic_delay : integer := 350;
sim_high_buffer_intrinsic_delay : integer := 175;
sim_buffer_delay_increment : integer := 10;
static_delay_ctrl : integer := 0;
lpm_type : string := "arriaii_dll";
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_aload : VitalDelayType01 := DefpropDelay01;
tipd_upndnin : VitalDelayType01 := DefpropDelay01;
tipd_upndninclkena : VitalDelayType01 := DefpropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tsetup_upndnin_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_upndnin_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_upndninclkena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_upndninclkena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_upndnout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clk_delayctrlout_posedge : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01)
);
PORT ( clk : IN std_logic := '0';
aload : IN std_logic := '0';
upndnin : IN std_logic := '1';
upndninclkena : IN std_logic := '1';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '0';
delayctrlout : OUT std_logic_vector(5 DOWNTO 0);
dqsupdate : OUT std_logic;
offsetdelayctrlout : OUT std_logic_vector(5 DOWNTO 0);
offsetdelayctrlclkout : OUT std_logic;
upndnout : OUT std_logic
);
END COMPONENT;
--
-- arriaii_dll_offset_ctrl
--
COMPONENT arriaii_dll_offset_ctrl
GENERIC (
use_offset : string := "false";
static_offset : string := "0";
delay_buffer_mode : string := "low";
lpm_type : string := "arriaii_dll_offset_ctrl";
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_aload : VitalDelayType01 := DefpropDelay01;
tipd_offset : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01);
tipd_offsetdelayctrlin : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01);
tipd_addnsub : VitalDelayType01 := DefpropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tsetup_offset_clk_noedge_posedge : VitalDelayArrayType(5 downto 0) := (OTHERS => DefSetupHoldCnst);
thold_offset_clk_noedge_posedge : VitalDelayArrayType(5 downto 0) := (OTHERS => DefSetupHoldCnst);
tsetup_addnsub_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_addnsub_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_offsetctrlout_posedge : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01)
);
PORT ( clk : IN std_logic := '0';
aload : IN std_logic := '0';
offsetdelayctrlin : IN std_logic_vector(5 DOWNTO 0) := "000000";
offset : IN std_logic_vector(5 DOWNTO 0) := "000000";
addnsub : IN std_logic := '1';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '0';
offsettestout : OUT std_logic_vector(5 DOWNTO 0);
offsetctrlout : OUT std_logic_vector(5 DOWNTO 0)
);
END COMPONENT;
--
-- arriaii_dqs_enable
--
COMPONENT arriaii_dqs_enable
GENERIC (
lpm_type : string := "arriaii_dqs_enable";
tipd_dqsin : VitalDelayType01 := DefpropDelay01;
tipd_dqsenable : VitalDelayType01 := DefpropDelay01;
tpd_dqsin_dqsbusout : VitalDelayType01 := DefPropDelay01;
tpd_dqsenable_dqsbusout : VitalDelayType01 := DefPropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*"
);
PORT (
dqsin : IN std_logic := '0';
dqsenable : IN std_logic := '1';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
dqsbusout : OUT std_logic
);
END COMPONENT;
--
-- arriaii_mac_mult
--
COMPONENT arriaii_mac_mult
GENERIC (
dataa_width : integer := 18;
datab_width : integer := 18;
dataa_clock : string := "none";
datab_clock : string := "none";
signa_clock : string := "none";
signb_clock : string := "none";
scanouta_clock : string := "none";
dataa_clear : string := "none";
datab_clear : string := "none";
signa_clear : string := "none";
signb_clear : string := "none";
scanouta_clear : string := "none";
signa_internally_grounded : string := "false";
signb_internally_grounded : string := "false";
lpm_type : string := "arriaii_mac_mult"
);
PORT (
dataa : IN std_logic_vector(dataa_width - 1 DOWNTO 0):= (others => '1');
datab : IN std_logic_vector(datab_width - 1 DOWNTO 0):= (others => '1');
signa : IN std_logic := '1';
signb : IN std_logic := '1';
clk : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
aclr : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
ena : IN std_logic_vector(3 DOWNTO 0) := (others => '1');
dataout : OUT std_logic_vector(dataa_width + datab_width - 1 DOWNTO 0);
scanouta : OUT std_logic_vector(dataa_width - 1 DOWNTO 0);
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END COMPONENT;
--
-- arriaii_mac_out
--
COMPONENT arriaii_mac_out
GENERIC (
operation_mode : string := "output_only";
dataa_width : integer := 1;
datab_width : integer := 1;
datac_width : integer := 1;
datad_width : integer := 1;
chainin_width : integer := 1;
round_width : integer := 15;
round_chain_out_width : integer := 15;
saturate_width : integer := 15;
saturate_chain_out_width : integer := 15;
first_adder0_clock : string := "none";
first_adder0_clear : string := "none";
first_adder1_clock : string := "none";
first_adder1_clear : string := "none";
second_adder_clock : string := "none";
second_adder_clear : string := "none";
output_clock : string := "none";
output_clear : string := "none";
signa_clock : string := "none";
signa_clear : string := "none";
signb_clock : string := "none";
signb_clear : string := "none";
round_clock : string := "none";
round_clear : string := "none";
roundchainout_clock : string := "none";
roundchainout_clear : string := "none";
saturate_clock : string := "none";
saturate_clear : string := "none";
saturatechainout_clock : string := "none";
saturatechainout_clear : string := "none";
zeroacc_clock : string := "none";
zeroacc_clear : string := "none";
zeroloopback_clock : string := "none";
zeroloopback_clear : string := "none";
rotate_clock : string := "none";
rotate_clear : string := "none";
shiftright_clock : string := "none";
shiftright_clear : string := "none";
signa_pipeline_clock : string := "none";
signa_pipeline_clear : string := "none";
signb_pipeline_clock : string := "none";
signb_pipeline_clear : string := "none";
round_pipeline_clock : string := "none";
round_pipeline_clear : string := "none";
roundchainout_pipeline_clock : string := "none";
roundchainout_pipeline_clear : string := "none";
saturate_pipeline_clock : string := "none";
saturate_pipeline_clear : string := "none";
saturatechainout_pipeline_clock: string := "none";
saturatechainout_pipeline_clear: string := "none";
zeroacc_pipeline_clock : string := "none";
zeroacc_pipeline_clear : string := "none";
zeroloopback_pipeline_clock : string := "none";
zeroloopback_pipeline_clear : string := "none";
rotate_pipeline_clock : string := "none";
rotate_pipeline_clear : string := "none";
shiftright_pipeline_clock : string := "none";
shiftright_pipeline_clear : string := "none";
roundchainout_output_clock : string := "none";
roundchainout_output_clear : string := "none";
saturatechainout_output_clock : string := "none";
saturatechainout_output_clear : string := "none";
zerochainout_output_clock : string := "none";
zerochainout_output_clear : string := "none";
zeroloopback_output_clock : string := "none";
zeroloopback_output_clear : string := "none";
rotate_output_clock : string := "none";
rotate_output_clear : string := "none";
shiftright_output_clock : string := "none";
shiftright_output_clear : string := "none";
first_adder0_mode : string := "add";
first_adder1_mode : string := "add";
acc_adder_operation : string := "add";
round_mode : string := "nearest_integer";
round_chain_out_mode : string := "nearest_integer";
saturate_mode : string := "asymmetric";
saturate_chain_out_mode : string := "asymmetric";
multa_signa_internally_grounded : string := "false";
multa_signb_internally_grounded : string := "false";
multb_signa_internally_grounded : string := "false";
multb_signb_internally_grounded : string := "false";
multc_signa_internally_grounded : string := "false";
multc_signb_internally_grounded : string := "false";
multd_signa_internally_grounded : string := "false";
multd_signb_internally_grounded : string := "false";
lpm_type : string := "arriaii_mac_out";
dataout_width : integer:=72
);
PORT (
dataa : IN std_logic_vector(dataa_width - 1 DOWNTO 0):= (others => '1');
datab : IN std_logic_vector(datab_width - 1 DOWNTO 0):= (others => '1');
datac : IN std_logic_vector(datac_width - 1 DOWNTO 0):= (others => '1');
datad : IN std_logic_vector(datad_width - 1 DOWNTO 0):= (others => '1');
signa : IN std_logic := '1';
signb : IN std_logic := '1';
chainin : IN std_logic_vector(chainin_width - 1 DOWNTO 0):= (others => '0');
round : IN std_logic := '0';
saturate : IN std_logic := '0';
zeroacc : IN std_logic := '0';
roundchainout : IN std_logic := '0';
saturatechainout : IN std_logic := '0';
zerochainout : IN std_logic := '0';
zeroloopback : IN std_logic := '0';
rotate : IN std_logic := '0';
shiftright : IN std_logic := '0';
clk : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
ena : IN std_logic_vector(3 DOWNTO 0) := (others => '1');
aclr : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
loopbackout : OUT std_logic_vector(17 DOWNTO 0):= (others => '0');
dataout : OUT std_logic_vector(71 DOWNTO 0) := (others => '0');
overflow : OUT std_logic := '0';
saturatechainoutoverflow: OUT std_logic := '0';
dftout : OUT std_logic := '0';
devpor : IN std_logic := '1';
devclrn : IN std_logic := '1'
);
END COMPONENT;
--
-- arriaii_io_pad
--
COMPONENT arriaii_io_pad
GENERIC (
lpm_type : string := "arriaii_io_pad");
PORT (
padin : IN std_logic := '0'; -- Input Pad
padout : OUT std_logic); -- Output Pad
END COMPONENT;
--
-- arriaii_pll
--
COMPONENT arriaii_pll
GENERIC (
operation_mode : string := "normal";
pll_type : string := "auto"; -- AUTO/FAST/ENHANCED/LEFT_RIGHT/TOP_BOTTOM
compensate_clock : string := "clock0";
inclk0_input_frequency : integer := 0;
inclk1_input_frequency : integer := 0;
self_reset_on_loss_lock : string := "off";
switch_over_type : string := "auto";
switch_over_counter : integer := 1;
enable_switch_over_counter : string := "off";
dpa_multiply_by : integer := 0;
dpa_divide_by : integer := 0;
dpa_divider : integer := 0;
bandwidth : integer := 0;
bandwidth_type : string := "auto";
use_dc_coupling : string := "false";
lock_c : integer := 4;
sim_gate_lock_device_behavior : string := "off";
lock_high : integer := 0;
lock_low : integer := 0;
lock_window_ui : string := "0.05";
lock_window : time := 5 ps;
test_bypass_lock_detect : string := "off";
clk0_output_frequency : integer := 0;
clk0_multiply_by : integer := 0;
clk0_divide_by : integer := 0;
clk0_phase_shift : string := "0";
clk0_duty_cycle : integer := 50;
clk1_output_frequency : integer := 0;
clk1_multiply_by : integer := 0;
clk1_divide_by : integer := 0;
clk1_phase_shift : string := "0";
clk1_duty_cycle : integer := 50;
clk2_output_frequency : integer := 0;
clk2_multiply_by : integer := 0;
clk2_divide_by : integer := 0;
clk2_phase_shift : string := "0";
clk2_duty_cycle : integer := 50;
clk3_output_frequency : integer := 0;
clk3_multiply_by : integer := 0;
clk3_divide_by : integer := 0;
clk3_phase_shift : string := "0";
clk3_duty_cycle : integer := 50;
clk4_output_frequency : integer := 0;
clk4_multiply_by : integer := 0;
clk4_divide_by : integer := 0;
clk4_phase_shift : string := "0";
clk4_duty_cycle : integer := 50;
clk5_output_frequency : integer := 0;
clk5_multiply_by : integer := 0;
clk5_divide_by : integer := 0;
clk5_phase_shift : string := "0";
clk5_duty_cycle : integer := 50;
clk6_output_frequency : integer := 0;
clk6_multiply_by : integer := 0;
clk6_divide_by : integer := 0;
clk6_phase_shift : string := "0";
clk6_duty_cycle : integer := 50;
clk7_output_frequency : integer := 0;
clk7_multiply_by : integer := 0;
clk7_divide_by : integer := 0;
clk7_phase_shift : string := "0";
clk7_duty_cycle : integer := 50;
clk8_output_frequency : integer := 0;
clk8_multiply_by : integer := 0;
clk8_divide_by : integer := 0;
clk8_phase_shift : string := "0";
clk8_duty_cycle : integer := 50;
clk9_output_frequency : integer := 0;
clk9_multiply_by : integer := 0;
clk9_divide_by : integer := 0;
clk9_phase_shift : string := "0";
clk9_duty_cycle : integer := 50;
pfd_min : integer := 0;
pfd_max : integer := 0;
vco_min : integer := 0;
vco_max : integer := 0;
vco_center : integer := 0;
m_initial : integer := 1;
m : integer := 0;
n : integer := 1;
c0_high : integer := 1;
c0_low : integer := 1;
c0_initial : integer := 1;
c0_mode : string := "bypass";
c0_ph : integer := 0;
c1_high : integer := 1;
c1_low : integer := 1;
c1_initial : integer := 1;
c1_mode : string := "bypass";
c1_ph : integer := 0;
c2_high : integer := 1;
c2_low : integer := 1;
c2_initial : integer := 1;
c2_mode : string := "bypass";
c2_ph : integer := 0;
c3_high : integer := 1;
c3_low : integer := 1;
c3_initial : integer := 1;
c3_mode : string := "bypass";
c3_ph : integer := 0;
c4_high : integer := 1;
c4_low : integer := 1;
c4_initial : integer := 1;
c4_mode : string := "bypass";
c4_ph : integer := 0;
c5_high : integer := 1;
c5_low : integer := 1;
c5_initial : integer := 1;
c5_mode : string := "bypass";
c5_ph : integer := 0;
c6_high : integer := 1;
c6_low : integer := 1;
c6_initial : integer := 1;
c6_mode : string := "bypass";
c6_ph : integer := 0;
c7_high : integer := 1;
c7_low : integer := 1;
c7_initial : integer := 1;
c7_mode : string := "bypass";
c7_ph : integer := 0;
c8_high : integer := 1;
c8_low : integer := 1;
c8_initial : integer := 1;
c8_mode : string := "bypass";
c8_ph : integer := 0;
c9_high : integer := 1;
c9_low : integer := 1;
c9_initial : integer := 1;
c9_mode : string := "bypass";
c9_ph : integer := 0;
m_ph : integer := 0;
clk0_counter : string := "unused";
clk1_counter : string := "unused";
clk2_counter : string := "unused";
clk3_counter : string := "unused";
clk4_counter : string := "unused";
clk5_counter : string := "unused";
clk6_counter : string := "unused";
clk7_counter : string := "unused";
clk8_counter : string := "unused";
clk9_counter : string := "unused";
c1_use_casc_in : string := "off";
c2_use_casc_in : string := "off";
c3_use_casc_in : string := "off";
c4_use_casc_in : string := "off";
c5_use_casc_in : string := "off";
c6_use_casc_in : string := "off";
c7_use_casc_in : string := "off";
c8_use_casc_in : string := "off";
c9_use_casc_in : string := "off";
m_test_source : integer := -1;
c0_test_source : integer := -1;
c1_test_source : integer := -1;
c2_test_source : integer := -1;
c3_test_source : integer := -1;
c4_test_source : integer := -1;
c5_test_source : integer := -1;
c6_test_source : integer := -1;
c7_test_source : integer := -1;
c8_test_source : integer := -1;
c9_test_source : integer := -1;
vco_multiply_by : integer := 0;
vco_divide_by : integer := 0;
vco_post_scale : integer := 1;
vco_frequency_control : string := "auto";
vco_phase_shift_step : integer := 0;
charge_pump_current : integer := 10;
loop_filter_r : string := " 1.0";
loop_filter_c : integer := 0;
pll_compensation_delay : integer := 0;
simulation_type : string := "functional";
lpm_type : string := "arriaii_pll";
clk0_use_even_counter_mode : string := "off";
clk1_use_even_counter_mode : string := "off";
clk2_use_even_counter_mode : string := "off";
clk3_use_even_counter_mode : string := "off";
clk4_use_even_counter_mode : string := "off";
clk5_use_even_counter_mode : string := "off";
clk6_use_even_counter_mode : string := "off";
clk7_use_even_counter_mode : string := "off";
clk8_use_even_counter_mode : string := "off";
clk9_use_even_counter_mode : string := "off";
clk0_use_even_counter_value : string := "off";
clk1_use_even_counter_value : string := "off";
clk2_use_even_counter_value : string := "off";
clk3_use_even_counter_value : string := "off";
clk4_use_even_counter_value : string := "off";
clk5_use_even_counter_value : string := "off";
clk6_use_even_counter_value : string := "off";
clk7_use_even_counter_value : string := "off";
clk8_use_even_counter_value : string := "off";
clk9_use_even_counter_value : string := "off";
init_block_reset_a_count : integer := 1;
init_block_reset_b_count : integer := 1;
charge_pump_current_bits : integer := 0;
lock_window_ui_bits : integer := 0;
loop_filter_c_bits : integer := 0;
loop_filter_r_bits : integer := 0;
test_counter_c0_delay_chain_bits : integer := 0;
test_counter_c1_delay_chain_bits : integer := 0;
test_counter_c2_delay_chain_bits : integer := 0;
test_counter_c3_delay_chain_bits : integer := 0;
test_counter_c4_delay_chain_bits : integer := 0;
test_counter_c5_delay_chain_bits : integer := 0;
test_counter_c6_delay_chain_bits : integer := 0;
test_counter_c7_delay_chain_bits : integer := 0;
test_counter_c8_delay_chain_bits : integer := 0;
test_counter_c9_delay_chain_bits : integer := 0;
test_counter_m_delay_chain_bits : integer := 0;
test_counter_n_delay_chain_bits : integer := 0;
test_feedback_comp_delay_chain_bits : integer := 0;
test_input_comp_delay_chain_bits : integer := 0;
test_volt_reg_output_mode_bits : integer := 0;
test_volt_reg_output_voltage_bits : integer := 0;
test_volt_reg_test_mode : string := "false";
vco_range_detector_high_bits : integer := -1;
vco_range_detector_low_bits : integer := -1;
scan_chain_mif_file : string := "";
dpa_output_clock_phase_shift : integer := 0;
test_counter_c3_sclk_delay_chain_bits : integer := -1;
test_counter_c4_sclk_delay_chain_bits : integer := -1;
test_counter_c5_lden_delay_chain_bits : integer := -1;
test_counter_c6_lden_delay_chain_bits : integer := -1;
auto_settings : string := "true";
family_name : string := "PiranhaIII";
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
TimingChecksOn : Boolean := true;
InstancePath : STRING := "*";
tipd_inclk : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_pfdena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_fbin : VitalDelayType01 := DefPropDelay01;
tipd_scanclk : VitalDelayType01 := DefPropDelay01;
tipd_scanclkena : VitalDelayType01 := DefPropDelay01;
tipd_scandata : VitalDelayType01 := DefPropDelay01;
tipd_configupdate : VitalDelayType01 := DefPropDelay01;
tipd_clkswitch : VitalDelayType01 := DefPropDelay01;
tipd_phaseupdown : VitalDelayType01 := DefPropDelay01;
tipd_phasecounterselect : VitalDelayArrayType01(3 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_phasestep : VitalDelayType01 := DefPropDelay01;
tsetup_scandata_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_scandata_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
tsetup_scanclkena_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_scanclkena_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
use_vco_bypass : string := "false"
);
PORT
(
inclk : in std_logic_vector(1 downto 0);
fbin : in std_logic := '0';
fbout : out std_logic;
clkswitch : in std_logic := '0';
areset : in std_logic := '0';
pfdena : in std_logic := '1';
scandata : in std_logic := '0';
scanclk : in std_logic := '0';
scanclkena : in std_logic := '1';
configupdate : in std_logic := '0';
clk : out std_logic_vector(9 downto 0);
phasecounterselect : in std_logic_vector(3 downto 0) := "0000";
phaseupdown : in std_logic := '0';
phasestep : in std_logic := '0';
clkbad : out std_logic_vector(1 downto 0);
activeclock : out std_logic;
locked : out std_logic;
scandataout : out std_logic;
scandone : out std_logic;
phasedone : out std_logic;
vcooverrange : out std_logic;
vcounderrange : out std_logic
);
END COMPONENT;
--
-- arriaii_asmiblock
--
COMPONENT arriaii_asmiblock
generic (
lpm_type : string := "arriaii_asmiblock"
);
port (
dclkin : in std_logic := '0';
scein : in std_logic := '0';
sdoin : in std_logic := '0';
data0in : in std_logic := '0';
oe : in std_logic := '0';
dclkout : out std_logic;
sceout : out std_logic;
sdoout : out std_logic;
data0out: out std_logic
);
END COMPONENT;
--
-- arriaii_lvds_receiver
--
COMPONENT arriaii_lvds_receiver
GENERIC ( channel_width : integer := 10;
data_align_rollover : integer := 2;
enable_dpa : string := "off";
lose_lock_on_one_change : string := "off";
reset_fifo_at_first_lock : string := "on";
align_to_rising_edge_only : string := "on";
use_serial_feedback_input : string := "off";
dpa_debug : string := "off";
enable_soft_cdr : string := "off";
dpa_output_clock_phase_shift : INTEGER := 0 ;
enable_dpa_initial_phase_selection : string := "off";
dpa_initial_phase_value : INTEGER := 0;
enable_dpa_align_to_rising_edge_only : string := "off";
net_ppm_variation : INTEGER := 0;
is_negative_ppm_drift : string := "off";
rx_input_path_delay_engineering_bits : INTEGER := 2;
x_on_bitslip : string := "on";
lpm_type : string := "arriaii_lvds_receiver";
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tipd_clk0 : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayType01 := DefpropDelay01;
tipd_enable0 : VitalDelayType01 := DefpropDelay01;
tipd_dpareset : VitalDelayType01 := DefpropDelay01;
tipd_dpahold : VitalDelayType01 := DefpropDelay01;
tipd_dpaswitch : VitalDelayType01 := DefpropDelay01;
tipd_fiforeset : VitalDelayType01 := DefpropDelay01;
tipd_bitslip : VitalDelayType01 := DefpropDelay01;
tipd_bitslipreset : VitalDelayType01 := DefpropDelay01;
tipd_serialfbk : VitalDelayType01 := DefpropDelay01;
tpd_clk0_dpalock_posedge : VitalDelayType01 := DefPropDelay01
);
PORT ( clk0 : IN std_logic;
datain : IN std_logic := '0';
enable0 : IN std_logic := '0';
dpareset : IN std_logic := '0';
dpahold : IN std_logic := '0';
dpaswitch : IN std_logic := '0';
fiforeset : IN std_logic := '0';
bitslip : IN std_logic := '0';
bitslipreset : IN std_logic := '0';
serialfbk : IN std_logic := '0';
dataout : OUT std_logic_vector(channel_width - 1 DOWNTO 0);
dpalock : OUT std_logic:= '0';
bitslipmax : OUT std_logic;
serialdataout : OUT std_logic;
postdpaserialdataout : OUT std_logic;
divfwdclk : OUT std_logic;
dpaclkout : OUT std_logic;
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END COMPONENT;
--
-- arriaii_pseudo_diff_out
--
COMPONENT arriaii_pseudo_diff_out
GENERIC (
tipd_i : VitalDelayType01 := DefPropDelay01;
tpd_i_o : VitalDelayType01 := DefPropDelay01;
tpd_i_obar : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
lpm_type : string := "arriaii_pseudo_diff_out"
);
PORT (
i : IN std_logic := '0';
o : OUT std_logic;
obar : OUT std_logic
);
END COMPONENT;
--
-- arriaii_dqs_delay_chain
--
COMPONENT arriaii_dqs_delay_chain
GENERIC (
lpm_type : STRING := "arriaii_dqs_delay_chain";
delay_buffer_mode : STRING := "low";
dqs_ctrl_latches_enable : STRING := "false";
dqs_input_frequency : string := "unused" ;
dqs_offsetctrl_enable : STRING := "false";
dqs_phase_shift : INTEGER := 0;
phase_setting : INTEGER := 0;
sim_buffer_delay_increment : INTEGER := 10;
sim_high_buffer_intrinsic_delay : INTEGER := 175;
sim_low_buffer_intrinsic_delay : INTEGER := 350;
test_enable : STRING := "false";
test_select : INTEGER := 0 ;
tipd_dqsin : VitalDelayType01 := DefpropDelay01;
tipd_delayctrlin : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01);
tipd_offsetctrlin : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01);
tipd_dqsupdateen : VitalDelayType01 := DefpropDelay01;
tpd_dqsin_dqsbusout : VitalDelayType01 := DefPropDelay01;
tsetup_delayctrlin_dqsupdateen_noedge_posedge : VitalDelayArrayType(5 downto 0) := (OTHERS => DefSetupHoldCnst);
thold_delayctrlin_dqsupdateen_noedge_posedge : VitalDelayArrayType(5 downto 0) := (OTHERS => DefSetupHoldCnst);
tsetup_offsetctrlin_dqsupdateen_noedge_posedge : VitalDelayArrayType(5 downto 0) := (OTHERS => DefSetupHoldCnst);
thold_offsetctrlin_dqsupdateen_noedge_posedge : VitalDelayArrayType(5 downto 0) := (OTHERS => DefSetupHoldCnst);
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*"
);
PORT (
delayctrlin : IN STD_LOGIC_VECTOR(5 DOWNTO 0):= (OTHERS => '0');
dqsin : IN STD_LOGIC := '0';
dqsupdateen : IN STD_LOGIC := '1';
offsetctrlin : IN STD_LOGIC_VECTOR(5 DOWNTO 0):= (OTHERS => '0');
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
dqsbusout : OUT STD_LOGIC
);
END COMPONENT;
--
-- arriaii_dqs_enable_ctrl
--
COMPONENT arriaii_dqs_enable_ctrl
GENERIC (
lpm_type : STRING := "arriaii_dqs_enable_ctrl";
delay_dqs_enable_by_half_cycle : STRING := "false" ;
tipd_dqsenablein : VitalDelayType01 := DefpropDelay01;
tipd_clk : VitalDelayType01 := DefpropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*"
);
PORT (
clk : IN STD_LOGIC := '0';
dqsenablein : IN STD_LOGIC := '1';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
dqsenableout : OUT STD_LOGIC
);
END COMPONENT;
--
-- arriaii_jtag
--
COMPONENT arriaii_jtag
generic (
lpm_type : string := "arriaii_jtag"
);
port (
tms : in std_logic := '0';
tck : in std_logic := '0';
tdi : in std_logic := '0';
tdoutap : in std_logic := '0';
tdouser : in std_logic := '0';
tdo: out std_logic;
tmsutap: out std_logic;
tckutap: out std_logic;
tdiutap: out std_logic;
shiftuser: out std_logic;
clkdruser: out std_logic;
updateuser: out std_logic;
runidleuser: out std_logic;
usr1user: out std_logic
);
END COMPONENT;
--
-- arriaii_crcblock
--
COMPONENT arriaii_crcblock
generic (
oscillator_divider : integer := 1;
crc_deld_disable : string := "off";
error_delay : integer := 0 ;
error_dra_dl_bypass : string := "off";
lpm_type : string := "arriaii_crcblock"
);
port (
clk : in std_logic := '0';
shiftnld : in std_logic := '0';
crcerror : out std_logic;
regout : out std_logic
);
END COMPONENT;
--
-- arriaii_controller
--
COMPONENT arriaii_controller
generic (
lpm_type : string := "arriaii_controller"
);
port (
nceout : out std_logic
);
END COMPONENT;
--
-- arriaii_termination_logic
--
COMPONENT arriaii_termination_logic
GENERIC (
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
TimingChecksOn : Boolean := True;
tipd_terminationclock : VitalDelayType01 := DefpropDelay01;
tipd_terminationselect : VitalDelayType01 := DefpropDelay01;
tipd_terminationdata : VitalDelayType01 := DefpropDelay01;
lpm_type : STRING := "arriaii_termination_logic"
);
PORT (
terminationclock : IN STD_LOGIC := '0';
terminationdata : IN STD_LOGIC := '0';
terminationselect : IN STD_LOGIC := '0';
terminationcontrol : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END COMPONENT;
--
-- arriaii_termination
--
COMPONENT arriaii_termination
GENERIC (
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
TimingChecksOn : Boolean := True;
tipd_scanshiftmux : VitalDelayType01 := DefpropDelay01;
tipd_scaninmux : VitalDelayType01 := DefpropDelay01;
tipd_scanin : VitalDelayType01 := DefpropDelay01;
tipd_terminationuserclock : VitalDelayType01 := DefpropDelay01;
tipd_scanclock : VitalDelayType01 := DefpropDelay01;
tipd_terminationuserclear : VitalDelayType01 := DefpropDelay01;
tipd_rdn : VitalDelayType01 := DefpropDelay01;
tipd_rup : VitalDelayType01 := DefpropDelay01;
lpm_type : STRING := "arriaii_termination";
runtime_control : STRING := "false"
);
PORT (
rdn : IN STD_LOGIC := '0';
rup : IN STD_LOGIC := '0';
scanclock : IN STD_LOGIC := '0';
scanin : IN STD_LOGIC := '0';
scaninmux : IN STD_LOGIC := '0';
scanshiftmux : IN STD_LOGIC := '0';
terminationuserclear : IN STD_LOGIC := '0';
terminationuserclock : IN STD_LOGIC := '0';
comparatorprobe : OUT STD_LOGIC;
scanout : OUT STD_LOGIC;
terminationclockout : OUT STD_LOGIC;
terminationcontrolprobe : OUT STD_LOGIC;
terminationdataout : OUT STD_LOGIC;
terminationdone : OUT STD_LOGIC;
terminationselectout : OUT STD_LOGIC
);
END COMPONENT;
end arriaii_components;
| gpl-3.0 |
asicguy/gplgpu | hdl/sim_lib/stratixv_hssi_atoms.vhd | 1 | 363400 | -- Copyright (C) 1991-2011 Altera Corporation
-- This simulation model contains highly confidential and
-- proprietary information of Altera and is being provided
-- in accordance with and subject to the protections of the
-- applicable Altera Program License Subscription Agreement
-- which governs its use and disclosure. Your use of Altera
-- Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions,
-- and any output files any of the foregoing (including device
-- programming or simulation files), and any associated
-- documentation or information are expressly subject to the
-- terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other
-- applicable license agreement, including, without limitation,
-- that your use is for the sole purpose of simulating designs for
-- use exclusively in logic devices manufactured by Altera and sold
-- by Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details. Altera products and
-- services are protected under numerous U.S. and foreign patents,
-- maskwork rights, copyrights and other intellectual property laws.
-- Altera assumes no responsibility or liability arising out of the
-- application or use of this simulation model.
-- Quartus II 11.0 Build 157 04/27/2011
library IEEE;
use IEEE.std_logic_1164.all;
entity stratixv_atx_pll is
generic (
avmm_group_channel_index : integer := 0 ;
output_clock_frequency : string := "" ;
reference_clock_frequency : string := "" ;
use_default_base_address : string := "true" ;
user_base_address0 : integer := 0 ;
user_base_address1 : integer := 0 ;
user_base_address2 : integer := 0 ;
cp_current_ctrl : integer := 300 ;
cp_current_test : string := "enable_ch_pump_normal" ;
cp_hs_levshift_power_supply_setting : integer := 1 ;
cp_replica_bias_ctrl : string := "disable_replica_bias_ctrl" ;
cp_rgla_bypass : string := "false" ;
cp_rgla_volt_inc : string := "boost_30pct" ;
l_counter : integer := 1 ;
lcpll_atb_select : string := "atb_disable" ;
lcpll_d2a_sel : string := "volt_1p02v" ;
lcpll_hclk_driver_enable : string := "driver_off" ;
lcvco_gear_sel : string := "high_gear" ;
lcvco_sel : string := "high_freq_14g" ;
lpf_ripple_cap_ctrl : string := "none" ;
lpf_rxpll_pfd_bw_ctrl : integer := 2400 ;
m_counter : integer := 4 ;
ref_clk_div : integer := 1 ;
refclk_sel : string := "refclk" ;
vreg1_lcvco_volt_inc : string := "volt_1p1v" ;
vreg1_vccehlow : string := "normal_operation" ;
vreg2_lcpll_volt_sel : string := "vreg2_volt_1p0v" ;
vreg3_lcpll_volt_sel : string := "vreg3_volt_1p0v"
);
port (
avmmaddress : in std_logic_vector( 10 downto 0 );
avmmbyteen : in std_logic_vector( 1 downto 0 );
avmmclk : in std_logic;
avmmread : in std_logic;
avmmrstn : in std_logic;
avmmwrite : in std_logic;
avmmwritedata : in std_logic_vector( 15 downto 0 );
avmmreaddata : out std_logic_vector( 15 downto 0 );
blockselect : out std_logic;
ch0rcsrlc : in std_logic_vector( 31 downto 0 );
ch1rcsrlc : in std_logic_vector( 31 downto 0 );
ch2rcsrlc : in std_logic_vector( 31 downto 0 );
cmurstn : in std_logic;
cmurstnlpf : in std_logic;
extfbclk : in std_logic;
iqclklc : in std_logic;
pldclklc : in std_logic;
pllfbswblc : in std_logic;
pllfbswtlc : in std_logic;
refclklc : in std_logic;
clk010g : out std_logic;
clk025g : out std_logic;
clk18010g : out std_logic;
clk18025g : out std_logic;
clk33cmu : out std_logic;
clklowcmu : out std_logic;
frefcmu : out std_logic;
iqclkatt : out std_logic;
pfdmodelockcmu : out std_logic;
pldclkatt : out std_logic;
refclkatt : out std_logic;
txpllhclk : out std_logic
);
end stratixv_atx_pll;
architecture behavior of stratixv_atx_pll is
component stratixv_atx_pll_encrypted
generic (
avmm_group_channel_index : integer := 0 ;
output_clock_frequency : string := "" ;
reference_clock_frequency : string := "" ;
use_default_base_address : string := "true" ;
user_base_address0 : integer := 0 ;
user_base_address1 : integer := 0 ;
user_base_address2 : integer := 0 ;
cp_current_ctrl : integer := 300 ;
cp_current_test : string := "enable_ch_pump_normal" ;
cp_hs_levshift_power_supply_setting : integer := 1 ;
cp_replica_bias_ctrl : string := "disable_replica_bias_ctrl" ;
cp_rgla_bypass : string := "false" ;
cp_rgla_volt_inc : string := "boost_30pct" ;
l_counter : integer := 1 ;
lcpll_atb_select : string := "atb_disable" ;
lcpll_d2a_sel : string := "volt_1p02v" ;
lcpll_hclk_driver_enable : string := "driver_off" ;
lcvco_gear_sel : string := "high_gear" ;
lcvco_sel : string := "high_freq_14g" ;
lpf_ripple_cap_ctrl : string := "none" ;
lpf_rxpll_pfd_bw_ctrl : integer := 2400 ;
m_counter : integer := 4 ;
ref_clk_div : integer := 1 ;
refclk_sel : string := "refclk" ;
vreg1_lcvco_volt_inc : string := "volt_1p1v" ;
vreg1_vccehlow : string := "normal_operation" ;
vreg2_lcpll_volt_sel : string := "vreg2_volt_1p0v" ;
vreg3_lcpll_volt_sel : string := "vreg3_volt_1p0v"
);
port (
avmmaddress : in std_logic_vector( 10 downto 0 );
avmmbyteen : in std_logic_vector( 1 downto 0 );
avmmclk : in std_logic;
avmmread : in std_logic;
avmmrstn : in std_logic;
avmmwrite : in std_logic;
avmmwritedata : in std_logic_vector( 15 downto 0 );
avmmreaddata : out std_logic_vector( 15 downto 0 );
blockselect : out std_logic;
ch0rcsrlc : in std_logic_vector( 31 downto 0 );
ch1rcsrlc : in std_logic_vector( 31 downto 0 );
ch2rcsrlc : in std_logic_vector( 31 downto 0 );
cmurstn : in std_logic;
cmurstnlpf : in std_logic;
extfbclk : in std_logic;
iqclklc : in std_logic;
pldclklc : in std_logic;
pllfbswblc : in std_logic;
pllfbswtlc : in std_logic;
refclklc : in std_logic;
clk010g : out std_logic;
clk025g : out std_logic;
clk18010g : out std_logic;
clk18025g : out std_logic;
clk33cmu : out std_logic;
clklowcmu : out std_logic;
frefcmu : out std_logic;
iqclkatt : out std_logic;
pfdmodelockcmu : out std_logic;
pldclkatt : out std_logic;
refclkatt : out std_logic;
txpllhclk : out std_logic
);
end component;
begin
inst : stratixv_atx_pll_encrypted
generic map (
avmm_group_channel_index => avmm_group_channel_index ,
output_clock_frequency => output_clock_frequency ,
reference_clock_frequency => reference_clock_frequency ,
use_default_base_address => use_default_base_address ,
user_base_address0 => user_base_address0 ,
user_base_address1 => user_base_address1 ,
user_base_address2 => user_base_address2 ,
cp_current_ctrl => cp_current_ctrl ,
cp_current_test => cp_current_test ,
cp_hs_levshift_power_supply_setting => cp_hs_levshift_power_supply_setting ,
cp_replica_bias_ctrl => cp_replica_bias_ctrl ,
cp_rgla_bypass => cp_rgla_bypass ,
cp_rgla_volt_inc => cp_rgla_volt_inc ,
l_counter => l_counter ,
lcpll_atb_select => lcpll_atb_select ,
lcpll_d2a_sel => lcpll_d2a_sel ,
lcpll_hclk_driver_enable => lcpll_hclk_driver_enable ,
lcvco_gear_sel => lcvco_gear_sel ,
lcvco_sel => lcvco_sel ,
lpf_ripple_cap_ctrl => lpf_ripple_cap_ctrl ,
lpf_rxpll_pfd_bw_ctrl => lpf_rxpll_pfd_bw_ctrl ,
m_counter => m_counter ,
ref_clk_div => ref_clk_div ,
refclk_sel => refclk_sel ,
vreg1_lcvco_volt_inc => vreg1_lcvco_volt_inc ,
vreg1_vccehlow => vreg1_vccehlow ,
vreg2_lcpll_volt_sel => vreg2_lcpll_volt_sel ,
vreg3_lcpll_volt_sel => vreg3_lcpll_volt_sel
)
port map (
avmmaddress => avmmaddress ,
avmmbyteen => avmmbyteen ,
avmmclk => avmmclk ,
avmmread => avmmread ,
avmmrstn => avmmrstn ,
avmmwrite => avmmwrite ,
avmmwritedata => avmmwritedata ,
avmmreaddata => avmmreaddata ,
blockselect => blockselect ,
ch0rcsrlc => ch0rcsrlc ,
ch1rcsrlc => ch1rcsrlc ,
ch2rcsrlc => ch2rcsrlc ,
cmurstn => cmurstn ,
cmurstnlpf => cmurstnlpf ,
extfbclk => extfbclk ,
iqclklc => iqclklc ,
pldclklc => pldclklc ,
pllfbswblc => pllfbswblc ,
pllfbswtlc => pllfbswtlc ,
refclklc => refclklc ,
clk010g => clk010g ,
clk025g => clk025g ,
clk18010g => clk18010g ,
clk18025g => clk18025g ,
clk33cmu => clk33cmu ,
clklowcmu => clklowcmu ,
frefcmu => frefcmu ,
iqclkatt => iqclkatt ,
pfdmodelockcmu => pfdmodelockcmu ,
pldclkatt => pldclkatt ,
refclkatt => refclkatt ,
txpllhclk => txpllhclk
);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
entity stratixv_channel_pll is
generic
(
avmm_group_channel_index : integer := 0;
output_clock_frequency : string := "0 ps";
reference_clock_frequency : string := "0 ps";
sim_use_fast_model : string := "true";
use_default_base_address : string := "true";
user_base_address : integer := 0;
bbpd_salatch_offset_ctrl_clk0 : string := "clk0_offset_0mv";
bbpd_salatch_offset_ctrl_clk180 : string := "clk180_offset_0mv";
bbpd_salatch_offset_ctrl_clk270 : string := "clk270_offset_0mv";
bbpd_salatch_offset_ctrl_clk90 : string := "clk90_offset_0mv";
bbpd_salatch_sel : string := "normal";
bypass_cp_rgla : string := "false";
cdr_atb_select : string := "atb_disable";
cgb_clk_enable : string := "false";
charge_pump_current_test : string := "enable_ch_pump_normal";
clklow_fref_to_ppm_div_sel : integer := 1;
clock_monitor : string := "lpbk_data";
diag_rev_lpbk : string := "false";
eye_monitor_bbpd_data_ctrl : string := "cdr_data";
fast_lock_mode : string := "false";
fb_sel : string := "vcoclk";
gpon_lock2ref_ctrl : string := "lck2ref";
hs_levshift_power_supply_setting : integer := 1;
ignore_phslock : string := "false";
l_counter_pd_clock_disable : string := "false";
m_counter : integer := 25;
pcie_freq_control : string := "pcie_100mhz";
pd_charge_pump_current_ctrl : integer := 5;
pd_l_counter : integer := 1;
pfd_charge_pump_current_ctrl : integer := 20;
pfd_l_counter : integer := 1;
powerdown : string := "false";
ref_clk_div : integer := 1;
regulator_volt_inc : string := "volt_inc_0pct";
replica_bias_ctrl : string := "true";
reverse_serial_lpbk : string := "false";
ripple_cap_ctrl : string := "none";
rxpll_pd_bw_ctrl : integer := 300;
rxpll_pfd_bw_ctrl : integer := 3200;
txpll_hclk_driver_enable : string := "false";
vco_overange_ref : string := "off";
vco_range_ctrl_en : string := "false"
);
port
(
avmmaddress : in std_logic_vector(10 downto 0);
avmmbyteen : in std_logic;
avmmclk : in std_logic;
avmmread : in std_logic;
avmmrstn : in std_logic;
avmmwrite : in std_logic;
avmmwritedata : in std_logic_vector(15 downto 0);
clk270eye : in std_logic;
clk270beyerm : in std_logic;
clk90eye : in std_logic;
clk90beyerm : in std_logic;
clkindeser : in std_logic;
crurstb : in std_logic;
deeye : in std_logic;
deeyerm : in std_logic;
doeye : in std_logic;
doeyerm : in std_logic;
earlyeios : in std_logic;
extclk : in std_logic;
extfbctrla : in std_logic;
extfbctrlb : in std_logic;
gpblck2refb : in std_logic;
lpbkpreen : in std_logic;
ltd : in std_logic;
ltr : in std_logic;
occalen : in std_logic;
pciel : in std_logic;
pciem : in std_logic;
pciesw : in std_logic_vector(1 downto 0);
ppmlock : in std_logic;
refclk : in std_logic;
rstn : in std_logic;
rxp : in std_logic;
sd : in std_logic;
avmmreaddata : out std_logic_vector(15 downto 0);
blockselect : out std_logic;
ck0pd : out std_logic;
ck180pd : out std_logic;
ck270pd : out std_logic;
ck90pd : out std_logic;
clk270bcdr : out std_logic;
clk270bdes : out std_logic;
clk90bcdr : out std_logic;
clk90bdes : out std_logic;
clkcdr : out std_logic;
clklow : out std_logic;
decdr : out std_logic;
deven : out std_logic;
docdr : out std_logic;
dodd : out std_logic;
fref : out std_logic;
pdof : out std_logic_vector(3 downto 0);
pfdmodelock : out std_logic;
rxlpbdp : out std_logic;
rxlpbp : out std_logic;
rxplllock : out std_logic;
txpllhclk : out std_logic;
txrlpbk : out std_logic;
vctrloverrange : out std_logic
);
end stratixv_channel_pll;
architecture behavior of stratixv_channel_pll is
component stratixv_channel_pll_encrypted
generic (
avmm_group_channel_index : integer := 0;
output_clock_frequency : string := "0 ps";
reference_clock_frequency : string := "0 ps";
sim_use_fast_model : string := "true";
use_default_base_address : string := "true";
user_base_address : integer := 0;
bbpd_salatch_offset_ctrl_clk0 : string := "clk0_offset_0mv";
bbpd_salatch_offset_ctrl_clk180 : string := "clk180_offset_0mv";
bbpd_salatch_offset_ctrl_clk270 : string := "clk270_offset_0mv";
bbpd_salatch_offset_ctrl_clk90 : string := "clk90_offset_0mv";
bbpd_salatch_sel : string := "normal";
bypass_cp_rgla : string := "false";
cdr_atb_select : string := "atb_disable";
cgb_clk_enable : string := "false";
charge_pump_current_test : string := "enable_ch_pump_normal";
clklow_fref_to_ppm_div_sel : integer := 1;
clock_monitor : string := "lpbk_data";
diag_rev_lpbk : string := "false";
eye_monitor_bbpd_data_ctrl : string := "cdr_data";
fast_lock_mode : string := "false";
fb_sel : string := "vcoclk";
gpon_lock2ref_ctrl : string := "lck2ref";
hs_levshift_power_supply_setting : integer := 1;
ignore_phslock : string := "false";
l_counter_pd_clock_disable : string := "false";
m_counter : integer := 25;
pcie_freq_control : string := "pcie_100mhz";
pd_charge_pump_current_ctrl : integer := 5;
pd_l_counter : integer := 1;
pfd_charge_pump_current_ctrl : integer := 20;
pfd_l_counter : integer := 1;
powerdown : string := "false";
ref_clk_div : integer := 1;
regulator_volt_inc : string := "volt_inc_0pct";
replica_bias_ctrl : string := "true";
reverse_serial_lpbk : string := "false";
ripple_cap_ctrl : string := "none";
rxpll_pd_bw_ctrl : integer := 300;
rxpll_pfd_bw_ctrl : integer := 3200;
txpll_hclk_driver_enable : string := "false";
vco_overange_ref : string := "off";
vco_range_ctrl_en : string := "false"
);
port (
avmmaddress : in std_logic_vector(10 downto 0);
avmmbyteen : in std_logic;
avmmclk : in std_logic;
avmmread : in std_logic;
avmmrstn : in std_logic;
avmmwrite : in std_logic;
avmmwritedata : in std_logic_vector(15 downto 0);
clk270eye : in std_logic;
clk270beyerm : in std_logic;
clk90eye : in std_logic;
clk90beyerm : in std_logic;
clkindeser : in std_logic;
crurstb : in std_logic;
deeye : in std_logic;
deeyerm : in std_logic;
doeye : in std_logic;
doeyerm : in std_logic;
earlyeios : in std_logic;
extclk : in std_logic;
extfbctrla : in std_logic;
extfbctrlb : in std_logic;
gpblck2refb : in std_logic;
lpbkpreen : in std_logic;
ltd : in std_logic;
ltr : in std_logic;
occalen : in std_logic;
pciel : in std_logic;
pciem : in std_logic;
pciesw : in std_logic_vector(1 downto 0);
ppmlock : in std_logic;
refclk : in std_logic;
rstn : in std_logic;
rxp : in std_logic;
sd : in std_logic;
avmmreaddata : out std_logic_vector(15 downto 0);
blockselect : out std_logic;
ck0pd : out std_logic;
ck180pd : out std_logic;
ck270pd : out std_logic;
ck90pd : out std_logic;
clk270bcdr : out std_logic;
clk270bdes : out std_logic;
clk90bcdr : out std_logic;
clk90bdes : out std_logic;
clkcdr : out std_logic;
clklow : out std_logic;
decdr : out std_logic;
deven : out std_logic;
docdr : out std_logic;
dodd : out std_logic;
fref : out std_logic;
pdof : out std_logic_vector(3 downto 0);
pfdmodelock : out std_logic;
rxlpbdp : out std_logic;
rxlpbp : out std_logic;
rxplllock : out std_logic;
txpllhclk : out std_logic;
txrlpbk : out std_logic;
vctrloverrange : out std_logic
);
end component;
begin
inst : stratixv_channel_pll_encrypted
generic map
(
avmm_group_channel_index => avmm_group_channel_index,
output_clock_frequency => output_clock_frequency,
reference_clock_frequency => reference_clock_frequency,
sim_use_fast_model => sim_use_fast_model,
use_default_base_address => use_default_base_address,
user_base_address => user_base_address,
bbpd_salatch_offset_ctrl_clk0 => bbpd_salatch_offset_ctrl_clk0,
bbpd_salatch_offset_ctrl_clk180 => bbpd_salatch_offset_ctrl_clk180,
bbpd_salatch_offset_ctrl_clk270 => bbpd_salatch_offset_ctrl_clk270,
bbpd_salatch_offset_ctrl_clk90 => bbpd_salatch_offset_ctrl_clk90,
bbpd_salatch_sel => bbpd_salatch_sel,
bypass_cp_rgla => bypass_cp_rgla,
cdr_atb_select => cdr_atb_select,
cgb_clk_enable => cgb_clk_enable,
charge_pump_current_test => charge_pump_current_test,
clklow_fref_to_ppm_div_sel => clklow_fref_to_ppm_div_sel,
clock_monitor => clock_monitor,
diag_rev_lpbk => diag_rev_lpbk,
eye_monitor_bbpd_data_ctrl => eye_monitor_bbpd_data_ctrl,
fast_lock_mode => fast_lock_mode,
fb_sel => fb_sel,
gpon_lock2ref_ctrl => gpon_lock2ref_ctrl,
hs_levshift_power_supply_setting => hs_levshift_power_supply_setting,
ignore_phslock => ignore_phslock,
l_counter_pd_clock_disable => l_counter_pd_clock_disable,
m_counter => m_counter,
pcie_freq_control => pcie_freq_control,
pd_charge_pump_current_ctrl => pd_charge_pump_current_ctrl,
pd_l_counter => pd_l_counter,
pfd_charge_pump_current_ctrl => pfd_charge_pump_current_ctrl,
pfd_l_counter => pfd_l_counter,
powerdown => powerdown,
ref_clk_div => ref_clk_div,
regulator_volt_inc => regulator_volt_inc,
replica_bias_ctrl => replica_bias_ctrl,
reverse_serial_lpbk => reverse_serial_lpbk,
ripple_cap_ctrl => ripple_cap_ctrl,
rxpll_pd_bw_ctrl => rxpll_pd_bw_ctrl,
rxpll_pfd_bw_ctrl => rxpll_pfd_bw_ctrl,
txpll_hclk_driver_enable => txpll_hclk_driver_enable,
vco_overange_ref => vco_overange_ref,
vco_range_ctrl_en => vco_range_ctrl_en
)
port map
(
avmmaddress => avmmaddress,
avmmbyteen => avmmbyteen,
avmmclk => avmmclk,
avmmread => avmmread,
avmmrstn => avmmrstn,
avmmwrite => avmmwrite,
avmmwritedata => avmmwritedata,
clk270eye => clk270eye,
clk270beyerm => clk270beyerm,
clk90eye => clk90eye,
clk90beyerm => clk90beyerm,
clkindeser => clkindeser,
crurstb => crurstb,
deeye => deeye,
deeyerm => deeyerm,
doeye => doeye,
doeyerm => doeyerm,
earlyeios => earlyeios,
extclk => extclk,
extfbctrla => extfbctrla,
extfbctrlb => extfbctrlb,
gpblck2refb => gpblck2refb,
lpbkpreen => lpbkpreen,
ltd => ltd,
ltr => ltr,
occalen => occalen,
pciel => pciel,
pciem => pciem,
pciesw => pciesw,
ppmlock => ppmlock,
refclk => refclk,
rstn => rstn,
rxp => rxp,
sd => sd,
avmmreaddata => avmmreaddata,
blockselect => blockselect,
ck0pd => ck0pd,
ck180pd => ck180pd,
ck270pd => ck270pd,
ck90pd => ck90pd,
clk270bcdr => clk270bcdr,
clk270bdes => clk270bdes,
clk90bcdr => clk90bcdr,
clk90bdes => clk90bdes,
clkcdr => clkcdr,
clklow => clklow,
decdr => decdr,
deven => deven,
docdr => docdr,
dodd => dodd,
fref => fref,
pdof => pdof,
pfdmodelock => pfdmodelock,
rxlpbdp => rxlpbdp,
rxlpbp => rxlpbp,
rxplllock => rxplllock,
txpllhclk => txpllhclk,
txrlpbk => txrlpbk,
vctrloverrange => vctrloverrange
);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
entity stratixv_hssi_8g_pcs_aggregate is
generic (
xaui_sm_operation : string := "en_xaui_sm";
dskw_sm_operation : string := "dskw_xaui_sm";
data_agg_bonding : string := "agg_disable";
prot_mode_tx : string := "pipe_g1_tx";
pcs_dw_datapath : string := "sw_data_path";
dskw_control : string := "dskw_write_control";
refclkdig_sel : string := "dis_refclk_dig_sel"
);
port (
refclkdig : in std_logic_vector(0 downto 0);
scanmoden : in std_logic_vector(0 downto 0);
scanshiftn : in std_logic_vector(0 downto 0);
txpmaclk : in std_logic_vector(0 downto 0);
rcvdclkch0 : in std_logic_vector(0 downto 0);
rcvdclkch1 : in std_logic_vector(0 downto 0);
hardrst : in std_logic_vector(0 downto 0);
txpcsrst : in std_logic_vector(0 downto 0);
rxpcsrst : in std_logic_vector(0 downto 0);
dprioagg : in std_logic_vector(63 downto 0);
rcvdclkout : out std_logic_vector(0 downto 0);
rcvdclkouttop : out std_logic_vector(0 downto 0);
rcvdclkoutbot : out std_logic_vector(0 downto 0);
rdenablesynctopch1 : in std_logic_vector(0 downto 0);
txdatatctopch1 : in std_logic_vector(7 downto 0);
txctltctopch1 : in std_logic_vector(0 downto 0);
syncstatustopch1 : in std_logic_vector(0 downto 0);
rdaligntopch1 : in std_logic_vector(1 downto 0);
aligndetsynctopch1 : in std_logic_vector(1 downto 0);
fifordintopch1 : in std_logic_vector(0 downto 0);
alignstatussynctopch1 : in std_logic_vector(0 downto 0);
cgcomprddintopch1 : in std_logic_vector(1 downto 0);
cgcompwrintopch1 : in std_logic_vector(1 downto 0);
delcondmetintopch1 : in std_logic_vector(0 downto 0);
fifoovrintopch1 : in std_logic_vector(0 downto 0);
latencycompintopch1 : in std_logic_vector(0 downto 0);
insertincompleteintopch1 : in std_logic_vector(0 downto 0);
decdatatopch1 : in std_logic_vector(7 downto 0);
decctltopch1 : in std_logic_vector(0 downto 0);
decdatavalidtopch1 : in std_logic_vector(0 downto 0);
runningdisptopch1 : in std_logic_vector(1 downto 0);
txdatatstopch1 : out std_logic_vector(7 downto 0);
txctltstopch1 : out std_logic_vector(0 downto 0);
fiforstrdqdtopch1 : out std_logic_vector(0 downto 0);
endskwqdtopch1 : out std_logic_vector(0 downto 0);
endskwrdptrstopch1 : out std_logic_vector(0 downto 0);
alignstatustopch1 : out std_logic_vector(0 downto 0);
alignstatussync0topch1 : out std_logic_vector(0 downto 0);
fifordoutcomp0topch1 : out std_logic_vector(0 downto 0);
cgcomprddalltopch1 : out std_logic_vector(0 downto 0);
cgcompwralltopch1 : out std_logic_vector(0 downto 0);
delcondmet0topch1 : out std_logic_vector(0 downto 0);
insertincomplete0topch1 : out std_logic_vector(0 downto 0);
fifoovr0topch1 : out std_logic_vector(0 downto 0);
latencycomp0topch1 : out std_logic_vector(0 downto 0);
rxdatarstopch1 : out std_logic_vector(7 downto 0);
rxctlrstopch1 : out std_logic_vector(0 downto 0);
rdenablesynctopch0 : in std_logic_vector(0 downto 0);
txdatatctopch0 : in std_logic_vector(7 downto 0);
txctltctopch0 : in std_logic_vector(0 downto 0);
syncstatustopch0 : in std_logic_vector(0 downto 0);
rdaligntopch0 : in std_logic_vector(1 downto 0);
aligndetsynctopch0 : in std_logic_vector(1 downto 0);
fifordintopch0 : in std_logic_vector(0 downto 0);
alignstatussynctopch0 : in std_logic_vector(0 downto 0);
cgcomprddintopch0 : in std_logic_vector(1 downto 0);
cgcompwrintopch0 : in std_logic_vector(1 downto 0);
delcondmetintopch0 : in std_logic_vector(0 downto 0);
fifoovrintopch0 : in std_logic_vector(0 downto 0);
latencycompintopch0 : in std_logic_vector(0 downto 0);
insertincompleteintopch0 : in std_logic_vector(0 downto 0);
decdatatopch0 : in std_logic_vector(7 downto 0);
decctltopch0 : in std_logic_vector(0 downto 0);
decdatavalidtopch0 : in std_logic_vector(0 downto 0);
runningdisptopch0 : in std_logic_vector(1 downto 0);
txdatatstopch0 : out std_logic_vector(7 downto 0);
txctltstopch0 : out std_logic_vector(0 downto 0);
fiforstrdqdtopch0 : out std_logic_vector(0 downto 0);
endskwqdtopch0 : out std_logic_vector(0 downto 0);
endskwrdptrstopch0 : out std_logic_vector(0 downto 0);
alignstatustopch0 : out std_logic_vector(0 downto 0);
alignstatussync0topch0 : out std_logic_vector(0 downto 0);
fifordoutcomp0topch0 : out std_logic_vector(0 downto 0);
cgcomprddalltopch0 : out std_logic_vector(0 downto 0);
cgcompwralltopch0 : out std_logic_vector(0 downto 0);
delcondmet0topch0 : out std_logic_vector(0 downto 0);
insertincomplete0topch0 : out std_logic_vector(0 downto 0);
fifoovr0topch0 : out std_logic_vector(0 downto 0);
latencycomp0topch0 : out std_logic_vector(0 downto 0);
rxdatarstopch0 : out std_logic_vector(7 downto 0);
rxctlrstopch0 : out std_logic_vector(0 downto 0);
rdenablesyncch2 : in std_logic_vector(0 downto 0);
txdatatcch2 : in std_logic_vector(7 downto 0);
txctltcch2 : in std_logic_vector(0 downto 0);
syncstatusch2 : in std_logic_vector(0 downto 0);
rdalignch2 : in std_logic_vector(1 downto 0);
aligndetsyncch2 : in std_logic_vector(1 downto 0);
fifordinch2 : in std_logic_vector(0 downto 0);
alignstatussyncch2 : in std_logic_vector(0 downto 0);
cgcomprddinch2 : in std_logic_vector(1 downto 0);
cgcompwrinch2 : in std_logic_vector(1 downto 0);
delcondmetinch2 : in std_logic_vector(0 downto 0);
fifoovrinch2 : in std_logic_vector(0 downto 0);
latencycompinch2 : in std_logic_vector(0 downto 0);
insertincompleteinch2 : in std_logic_vector(0 downto 0);
decdatach2 : in std_logic_vector(7 downto 0);
decctlch2 : in std_logic_vector(0 downto 0);
decdatavalidch2 : in std_logic_vector(0 downto 0);
runningdispch2 : in std_logic_vector(1 downto 0);
txdatatsch2 : out std_logic_vector(7 downto 0);
txctltsch2 : out std_logic_vector(0 downto 0);
fiforstrdqdch2 : out std_logic_vector(0 downto 0);
endskwqdch2 : out std_logic_vector(0 downto 0);
endskwrdptrsch2 : out std_logic_vector(0 downto 0);
alignstatusch2 : out std_logic_vector(0 downto 0);
alignstatussync0ch2 : out std_logic_vector(0 downto 0);
fifordoutcomp0ch2 : out std_logic_vector(0 downto 0);
cgcomprddallch2 : out std_logic_vector(0 downto 0);
cgcompwrallch2 : out std_logic_vector(0 downto 0);
delcondmet0ch2 : out std_logic_vector(0 downto 0);
insertincomplete0ch2 : out std_logic_vector(0 downto 0);
fifoovr0ch2 : out std_logic_vector(0 downto 0);
latencycomp0ch2 : out std_logic_vector(0 downto 0);
rxdatarsch2 : out std_logic_vector(7 downto 0);
rxctlrsch2 : out std_logic_vector(0 downto 0);
rdenablesyncch1 : in std_logic_vector(0 downto 0);
txdatatcch1 : in std_logic_vector(7 downto 0);
txctltcch1 : in std_logic_vector(0 downto 0);
syncstatusch1 : in std_logic_vector(0 downto 0);
rdalignch1 : in std_logic_vector(1 downto 0);
aligndetsyncch1 : in std_logic_vector(1 downto 0);
fifordinch1 : in std_logic_vector(0 downto 0);
alignstatussyncch1 : in std_logic_vector(0 downto 0);
cgcomprddinch1 : in std_logic_vector(1 downto 0);
cgcompwrinch1 : in std_logic_vector(1 downto 0);
delcondmetinch1 : in std_logic_vector(0 downto 0);
fifoovrinch1 : in std_logic_vector(0 downto 0);
latencycompinch1 : in std_logic_vector(0 downto 0);
insertincompleteinch1 : in std_logic_vector(0 downto 0);
decdatach1 : in std_logic_vector(7 downto 0);
decctlch1 : in std_logic_vector(0 downto 0);
decdatavalidch1 : in std_logic_vector(0 downto 0);
runningdispch1 : in std_logic_vector(1 downto 0);
txdatatsch1 : out std_logic_vector(7 downto 0);
txctltsch1 : out std_logic_vector(0 downto 0);
fiforstrdqdch1 : out std_logic_vector(0 downto 0);
endskwqdch1 : out std_logic_vector(0 downto 0);
endskwrdptrsch1 : out std_logic_vector(0 downto 0);
alignstatusch1 : out std_logic_vector(0 downto 0);
alignstatussync0ch1 : out std_logic_vector(0 downto 0);
fifordoutcomp0ch1 : out std_logic_vector(0 downto 0);
cgcomprddallch1 : out std_logic_vector(0 downto 0);
cgcompwrallch1 : out std_logic_vector(0 downto 0);
delcondmet0ch1 : out std_logic_vector(0 downto 0);
insertincomplete0ch1 : out std_logic_vector(0 downto 0);
fifoovr0ch1 : out std_logic_vector(0 downto 0);
latencycomp0ch1 : out std_logic_vector(0 downto 0);
rxdatarsch1 : out std_logic_vector(7 downto 0);
rxctlrsch1 : out std_logic_vector(0 downto 0);
rdenablesyncch0 : in std_logic_vector(0 downto 0);
txdatatcch0 : in std_logic_vector(7 downto 0);
txctltcch0 : in std_logic_vector(0 downto 0);
syncstatusch0 : in std_logic_vector(0 downto 0);
rdalignch0 : in std_logic_vector(1 downto 0);
aligndetsyncch0 : in std_logic_vector(1 downto 0);
fifordinch0 : in std_logic_vector(0 downto 0);
alignstatussyncch0 : in std_logic_vector(0 downto 0);
cgcomprddinch0 : in std_logic_vector(1 downto 0);
cgcompwrinch0 : in std_logic_vector(1 downto 0);
delcondmetinch0 : in std_logic_vector(0 downto 0);
fifoovrinch0 : in std_logic_vector(0 downto 0);
latencycompinch0 : in std_logic_vector(0 downto 0);
insertincompleteinch0 : in std_logic_vector(0 downto 0);
decdatach0 : in std_logic_vector(7 downto 0);
decctlch0 : in std_logic_vector(0 downto 0);
decdatavalidch0 : in std_logic_vector(0 downto 0);
runningdispch0 : in std_logic_vector(1 downto 0);
txdatatsch0 : out std_logic_vector(7 downto 0);
txctltsch0 : out std_logic_vector(0 downto 0);
fiforstrdqdch0 : out std_logic_vector(0 downto 0);
endskwqdch0 : out std_logic_vector(0 downto 0);
endskwrdptrsch0 : out std_logic_vector(0 downto 0);
alignstatusch0 : out std_logic_vector(0 downto 0);
alignstatussync0ch0 : out std_logic_vector(0 downto 0);
fifordoutcomp0ch0 : out std_logic_vector(0 downto 0);
cgcomprddallch0 : out std_logic_vector(0 downto 0);
cgcompwrallch0 : out std_logic_vector(0 downto 0);
delcondmet0ch0 : out std_logic_vector(0 downto 0);
insertincomplete0ch0 : out std_logic_vector(0 downto 0);
fifoovr0ch0 : out std_logic_vector(0 downto 0);
latencycomp0ch0 : out std_logic_vector(0 downto 0);
rxdatarsch0 : out std_logic_vector(7 downto 0);
rxctlrsch0 : out std_logic_vector(0 downto 0);
rdenablesyncbotch2 : in std_logic_vector(0 downto 0);
txdatatcbotch2 : in std_logic_vector(7 downto 0);
txctltcbotch2 : in std_logic_vector(0 downto 0);
syncstatusbotch2 : in std_logic_vector(0 downto 0);
rdalignbotch2 : in std_logic_vector(1 downto 0);
aligndetsyncbotch2 : in std_logic_vector(1 downto 0);
fifordinbotch2 : in std_logic_vector(0 downto 0);
alignstatussyncbotch2 : in std_logic_vector(0 downto 0);
cgcomprddinbotch2 : in std_logic_vector(1 downto 0);
cgcompwrinbotch2 : in std_logic_vector(1 downto 0);
delcondmetinbotch2 : in std_logic_vector(0 downto 0);
fifoovrinbotch2 : in std_logic_vector(0 downto 0);
latencycompinbotch2 : in std_logic_vector(0 downto 0);
insertincompleteinbotch2 : in std_logic_vector(0 downto 0);
decdatabotch2 : in std_logic_vector(7 downto 0);
decctlbotch2 : in std_logic_vector(0 downto 0);
decdatavalidbotch2 : in std_logic_vector(0 downto 0);
runningdispbotch2 : in std_logic_vector(1 downto 0);
txdatatsbotch2 : out std_logic_vector(7 downto 0);
txctltsbotch2 : out std_logic_vector(0 downto 0);
fiforstrdqdbotch2 : out std_logic_vector(0 downto 0);
endskwqdbotch2 : out std_logic_vector(0 downto 0);
endskwrdptrsbotch2 : out std_logic_vector(0 downto 0);
alignstatusbotch2 : out std_logic_vector(0 downto 0);
alignstatussync0botch2 : out std_logic_vector(0 downto 0);
fifordoutcomp0botch2 : out std_logic_vector(0 downto 0);
cgcomprddallbotch2 : out std_logic_vector(0 downto 0);
cgcompwrallbotch2 : out std_logic_vector(0 downto 0);
delcondmet0botch2 : out std_logic_vector(0 downto 0);
insertincomplete0botch2 : out std_logic_vector(0 downto 0);
fifoovr0botch2 : out std_logic_vector(0 downto 0);
latencycomp0botch2 : out std_logic_vector(0 downto 0);
rxdatarsbotch2 : out std_logic_vector(7 downto 0);
rxctlrsbotch2 : out std_logic_vector(0 downto 0)
);
end stratixv_hssi_8g_pcs_aggregate;
architecture behavior of stratixv_hssi_8g_pcs_aggregate is
component stratixv_hssi_8g_pcs_aggregate_encrypted
generic (
xaui_sm_operation : string := "en_xaui_sm";
dskw_sm_operation : string := "dskw_xaui_sm";
data_agg_bonding : string := "agg_disable";
prot_mode_tx : string := "pipe_g1_tx";
pcs_dw_datapath : string := "sw_data_path";
dskw_control : string := "dskw_write_control";
refclkdig_sel : string := "dis_refclk_dig_sel"
);
port (
refclkdig : in std_logic_vector(0 downto 0);
scanmoden : in std_logic_vector(0 downto 0);
scanshiftn : in std_logic_vector(0 downto 0);
txpmaclk : in std_logic_vector(0 downto 0);
rcvdclkch0 : in std_logic_vector(0 downto 0);
rcvdclkch1 : in std_logic_vector(0 downto 0);
hardrst : in std_logic_vector(0 downto 0);
txpcsrst : in std_logic_vector(0 downto 0);
rxpcsrst : in std_logic_vector(0 downto 0);
dprioagg : in std_logic_vector(63 downto 0);
rcvdclkout : out std_logic_vector(0 downto 0);
rcvdclkouttop : out std_logic_vector(0 downto 0);
rcvdclkoutbot : out std_logic_vector(0 downto 0);
rdenablesynctopch1 : in std_logic_vector(0 downto 0);
txdatatctopch1 : in std_logic_vector(7 downto 0);
txctltctopch1 : in std_logic_vector(0 downto 0);
syncstatustopch1 : in std_logic_vector(0 downto 0);
rdaligntopch1 : in std_logic_vector(1 downto 0);
aligndetsynctopch1 : in std_logic_vector(1 downto 0);
fifordintopch1 : in std_logic_vector(0 downto 0);
alignstatussynctopch1 : in std_logic_vector(0 downto 0);
cgcomprddintopch1 : in std_logic_vector(1 downto 0);
cgcompwrintopch1 : in std_logic_vector(1 downto 0);
delcondmetintopch1 : in std_logic_vector(0 downto 0);
fifoovrintopch1 : in std_logic_vector(0 downto 0);
latencycompintopch1 : in std_logic_vector(0 downto 0);
insertincompleteintopch1 : in std_logic_vector(0 downto 0);
decdatatopch1 : in std_logic_vector(7 downto 0);
decctltopch1 : in std_logic_vector(0 downto 0);
decdatavalidtopch1 : in std_logic_vector(0 downto 0);
runningdisptopch1 : in std_logic_vector(1 downto 0);
txdatatstopch1 : out std_logic_vector(7 downto 0);
txctltstopch1 : out std_logic_vector(0 downto 0);
fiforstrdqdtopch1 : out std_logic_vector(0 downto 0);
endskwqdtopch1 : out std_logic_vector(0 downto 0);
endskwrdptrstopch1 : out std_logic_vector(0 downto 0);
alignstatustopch1 : out std_logic_vector(0 downto 0);
alignstatussync0topch1 : out std_logic_vector(0 downto 0);
fifordoutcomp0topch1 : out std_logic_vector(0 downto 0);
cgcomprddalltopch1 : out std_logic_vector(0 downto 0);
cgcompwralltopch1 : out std_logic_vector(0 downto 0);
delcondmet0topch1 : out std_logic_vector(0 downto 0);
insertincomplete0topch1 : out std_logic_vector(0 downto 0);
fifoovr0topch1 : out std_logic_vector(0 downto 0);
latencycomp0topch1 : out std_logic_vector(0 downto 0);
rxdatarstopch1 : out std_logic_vector(7 downto 0);
rxctlrstopch1 : out std_logic_vector(0 downto 0);
rdenablesynctopch0 : in std_logic_vector(0 downto 0);
txdatatctopch0 : in std_logic_vector(7 downto 0);
txctltctopch0 : in std_logic_vector(0 downto 0);
syncstatustopch0 : in std_logic_vector(0 downto 0);
rdaligntopch0 : in std_logic_vector(1 downto 0);
aligndetsynctopch0 : in std_logic_vector(1 downto 0);
fifordintopch0 : in std_logic_vector(0 downto 0);
alignstatussynctopch0 : in std_logic_vector(0 downto 0);
cgcomprddintopch0 : in std_logic_vector(1 downto 0);
cgcompwrintopch0 : in std_logic_vector(1 downto 0);
delcondmetintopch0 : in std_logic_vector(0 downto 0);
fifoovrintopch0 : in std_logic_vector(0 downto 0);
latencycompintopch0 : in std_logic_vector(0 downto 0);
insertincompleteintopch0 : in std_logic_vector(0 downto 0);
decdatatopch0 : in std_logic_vector(7 downto 0);
decctltopch0 : in std_logic_vector(0 downto 0);
decdatavalidtopch0 : in std_logic_vector(0 downto 0);
runningdisptopch0 : in std_logic_vector(1 downto 0);
txdatatstopch0 : out std_logic_vector(7 downto 0);
txctltstopch0 : out std_logic_vector(0 downto 0);
fiforstrdqdtopch0 : out std_logic_vector(0 downto 0);
endskwqdtopch0 : out std_logic_vector(0 downto 0);
endskwrdptrstopch0 : out std_logic_vector(0 downto 0);
alignstatustopch0 : out std_logic_vector(0 downto 0);
alignstatussync0topch0 : out std_logic_vector(0 downto 0);
fifordoutcomp0topch0 : out std_logic_vector(0 downto 0);
cgcomprddalltopch0 : out std_logic_vector(0 downto 0);
cgcompwralltopch0 : out std_logic_vector(0 downto 0);
delcondmet0topch0 : out std_logic_vector(0 downto 0);
insertincomplete0topch0 : out std_logic_vector(0 downto 0);
fifoovr0topch0 : out std_logic_vector(0 downto 0);
latencycomp0topch0 : out std_logic_vector(0 downto 0);
rxdatarstopch0 : out std_logic_vector(7 downto 0);
rxctlrstopch0 : out std_logic_vector(0 downto 0);
rdenablesyncch2 : in std_logic_vector(0 downto 0);
txdatatcch2 : in std_logic_vector(7 downto 0);
txctltcch2 : in std_logic_vector(0 downto 0);
syncstatusch2 : in std_logic_vector(0 downto 0);
rdalignch2 : in std_logic_vector(1 downto 0);
aligndetsyncch2 : in std_logic_vector(1 downto 0);
fifordinch2 : in std_logic_vector(0 downto 0);
alignstatussyncch2 : in std_logic_vector(0 downto 0);
cgcomprddinch2 : in std_logic_vector(1 downto 0);
cgcompwrinch2 : in std_logic_vector(1 downto 0);
delcondmetinch2 : in std_logic_vector(0 downto 0);
fifoovrinch2 : in std_logic_vector(0 downto 0);
latencycompinch2 : in std_logic_vector(0 downto 0);
insertincompleteinch2 : in std_logic_vector(0 downto 0);
decdatach2 : in std_logic_vector(7 downto 0);
decctlch2 : in std_logic_vector(0 downto 0);
decdatavalidch2 : in std_logic_vector(0 downto 0);
runningdispch2 : in std_logic_vector(1 downto 0);
txdatatsch2 : out std_logic_vector(7 downto 0);
txctltsch2 : out std_logic_vector(0 downto 0);
fiforstrdqdch2 : out std_logic_vector(0 downto 0);
endskwqdch2 : out std_logic_vector(0 downto 0);
endskwrdptrsch2 : out std_logic_vector(0 downto 0);
alignstatusch2 : out std_logic_vector(0 downto 0);
alignstatussync0ch2 : out std_logic_vector(0 downto 0);
fifordoutcomp0ch2 : out std_logic_vector(0 downto 0);
cgcomprddallch2 : out std_logic_vector(0 downto 0);
cgcompwrallch2 : out std_logic_vector(0 downto 0);
delcondmet0ch2 : out std_logic_vector(0 downto 0);
insertincomplete0ch2 : out std_logic_vector(0 downto 0);
fifoovr0ch2 : out std_logic_vector(0 downto 0);
latencycomp0ch2 : out std_logic_vector(0 downto 0);
rxdatarsch2 : out std_logic_vector(7 downto 0);
rxctlrsch2 : out std_logic_vector(0 downto 0);
rdenablesyncch1 : in std_logic_vector(0 downto 0);
txdatatcch1 : in std_logic_vector(7 downto 0);
txctltcch1 : in std_logic_vector(0 downto 0);
syncstatusch1 : in std_logic_vector(0 downto 0);
rdalignch1 : in std_logic_vector(1 downto 0);
aligndetsyncch1 : in std_logic_vector(1 downto 0);
fifordinch1 : in std_logic_vector(0 downto 0);
alignstatussyncch1 : in std_logic_vector(0 downto 0);
cgcomprddinch1 : in std_logic_vector(1 downto 0);
cgcompwrinch1 : in std_logic_vector(1 downto 0);
delcondmetinch1 : in std_logic_vector(0 downto 0);
fifoovrinch1 : in std_logic_vector(0 downto 0);
latencycompinch1 : in std_logic_vector(0 downto 0);
insertincompleteinch1 : in std_logic_vector(0 downto 0);
decdatach1 : in std_logic_vector(7 downto 0);
decctlch1 : in std_logic_vector(0 downto 0);
decdatavalidch1 : in std_logic_vector(0 downto 0);
runningdispch1 : in std_logic_vector(1 downto 0);
txdatatsch1 : out std_logic_vector(7 downto 0);
txctltsch1 : out std_logic_vector(0 downto 0);
fiforstrdqdch1 : out std_logic_vector(0 downto 0);
endskwqdch1 : out std_logic_vector(0 downto 0);
endskwrdptrsch1 : out std_logic_vector(0 downto 0);
alignstatusch1 : out std_logic_vector(0 downto 0);
alignstatussync0ch1 : out std_logic_vector(0 downto 0);
fifordoutcomp0ch1 : out std_logic_vector(0 downto 0);
cgcomprddallch1 : out std_logic_vector(0 downto 0);
cgcompwrallch1 : out std_logic_vector(0 downto 0);
delcondmet0ch1 : out std_logic_vector(0 downto 0);
insertincomplete0ch1 : out std_logic_vector(0 downto 0);
fifoovr0ch1 : out std_logic_vector(0 downto 0);
latencycomp0ch1 : out std_logic_vector(0 downto 0);
rxdatarsch1 : out std_logic_vector(7 downto 0);
rxctlrsch1 : out std_logic_vector(0 downto 0);
rdenablesyncch0 : in std_logic_vector(0 downto 0);
txdatatcch0 : in std_logic_vector(7 downto 0);
txctltcch0 : in std_logic_vector(0 downto 0);
syncstatusch0 : in std_logic_vector(0 downto 0);
rdalignch0 : in std_logic_vector(1 downto 0);
aligndetsyncch0 : in std_logic_vector(1 downto 0);
fifordinch0 : in std_logic_vector(0 downto 0);
alignstatussyncch0 : in std_logic_vector(0 downto 0);
cgcomprddinch0 : in std_logic_vector(1 downto 0);
cgcompwrinch0 : in std_logic_vector(1 downto 0);
delcondmetinch0 : in std_logic_vector(0 downto 0);
fifoovrinch0 : in std_logic_vector(0 downto 0);
latencycompinch0 : in std_logic_vector(0 downto 0);
insertincompleteinch0 : in std_logic_vector(0 downto 0);
decdatach0 : in std_logic_vector(7 downto 0);
decctlch0 : in std_logic_vector(0 downto 0);
decdatavalidch0 : in std_logic_vector(0 downto 0);
runningdispch0 : in std_logic_vector(1 downto 0);
txdatatsch0 : out std_logic_vector(7 downto 0);
txctltsch0 : out std_logic_vector(0 downto 0);
fiforstrdqdch0 : out std_logic_vector(0 downto 0);
endskwqdch0 : out std_logic_vector(0 downto 0);
endskwrdptrsch0 : out std_logic_vector(0 downto 0);
alignstatusch0 : out std_logic_vector(0 downto 0);
alignstatussync0ch0 : out std_logic_vector(0 downto 0);
fifordoutcomp0ch0 : out std_logic_vector(0 downto 0);
cgcomprddallch0 : out std_logic_vector(0 downto 0);
cgcompwrallch0 : out std_logic_vector(0 downto 0);
delcondmet0ch0 : out std_logic_vector(0 downto 0);
insertincomplete0ch0 : out std_logic_vector(0 downto 0);
fifoovr0ch0 : out std_logic_vector(0 downto 0);
latencycomp0ch0 : out std_logic_vector(0 downto 0);
rxdatarsch0 : out std_logic_vector(7 downto 0);
rxctlrsch0 : out std_logic_vector(0 downto 0);
rdenablesyncbotch2 : in std_logic_vector(0 downto 0);
txdatatcbotch2 : in std_logic_vector(7 downto 0);
txctltcbotch2 : in std_logic_vector(0 downto 0);
syncstatusbotch2 : in std_logic_vector(0 downto 0);
rdalignbotch2 : in std_logic_vector(1 downto 0);
aligndetsyncbotch2 : in std_logic_vector(1 downto 0);
fifordinbotch2 : in std_logic_vector(0 downto 0);
alignstatussyncbotch2 : in std_logic_vector(0 downto 0);
cgcomprddinbotch2 : in std_logic_vector(1 downto 0);
cgcompwrinbotch2 : in std_logic_vector(1 downto 0);
delcondmetinbotch2 : in std_logic_vector(0 downto 0);
fifoovrinbotch2 : in std_logic_vector(0 downto 0);
latencycompinbotch2 : in std_logic_vector(0 downto 0);
insertincompleteinbotch2 : in std_logic_vector(0 downto 0);
decdatabotch2 : in std_logic_vector(7 downto 0);
decctlbotch2 : in std_logic_vector(0 downto 0);
decdatavalidbotch2 : in std_logic_vector(0 downto 0);
runningdispbotch2 : in std_logic_vector(1 downto 0);
txdatatsbotch2 : out std_logic_vector(7 downto 0);
txctltsbotch2 : out std_logic_vector(0 downto 0);
fiforstrdqdbotch2 : out std_logic_vector(0 downto 0);
endskwqdbotch2 : out std_logic_vector(0 downto 0);
endskwrdptrsbotch2 : out std_logic_vector(0 downto 0);
alignstatusbotch2 : out std_logic_vector(0 downto 0);
alignstatussync0botch2 : out std_logic_vector(0 downto 0);
fifordoutcomp0botch2 : out std_logic_vector(0 downto 0);
cgcomprddallbotch2 : out std_logic_vector(0 downto 0);
cgcompwrallbotch2 : out std_logic_vector(0 downto 0);
delcondmet0botch2 : out std_logic_vector(0 downto 0);
insertincomplete0botch2 : out std_logic_vector(0 downto 0);
fifoovr0botch2 : out std_logic_vector(0 downto 0);
latencycomp0botch2 : out std_logic_vector(0 downto 0);
rxdatarsbotch2 : out std_logic_vector(7 downto 0);
rxctlrsbotch2 : out std_logic_vector(0 downto 0)
);
end component;
begin
inst : stratixv_hssi_8g_pcs_aggregate_encrypted
generic map (
xaui_sm_operation => xaui_sm_operation,
dskw_sm_operation => dskw_sm_operation,
data_agg_bonding => data_agg_bonding,
prot_mode_tx => prot_mode_tx,
pcs_dw_datapath => pcs_dw_datapath,
dskw_control => dskw_control,
refclkdig_sel => refclkdig_sel
)
port map (
refclkdig => refclkdig,
scanmoden => scanmoden,
scanshiftn => scanshiftn,
txpmaclk => txpmaclk,
rcvdclkch0 => rcvdclkch0,
rcvdclkch1 => rcvdclkch1,
hardrst => hardrst,
txpcsrst => txpcsrst,
rxpcsrst => rxpcsrst,
dprioagg => dprioagg,
rcvdclkout => rcvdclkout,
rcvdclkouttop => rcvdclkouttop,
rcvdclkoutbot => rcvdclkoutbot,
rdenablesynctopch1 => rdenablesynctopch1,
txdatatctopch1 => txdatatctopch1,
txctltctopch1 => txctltctopch1,
syncstatustopch1 => syncstatustopch1,
rdaligntopch1 => rdaligntopch1,
aligndetsynctopch1 => aligndetsynctopch1,
fifordintopch1 => fifordintopch1,
alignstatussynctopch1 => alignstatussynctopch1,
cgcomprddintopch1 => cgcomprddintopch1,
cgcompwrintopch1 => cgcompwrintopch1,
delcondmetintopch1 => delcondmetintopch1,
fifoovrintopch1 => fifoovrintopch1,
latencycompintopch1 => latencycompintopch1,
insertincompleteintopch1 => insertincompleteintopch1,
decdatatopch1 => decdatatopch1,
decctltopch1 => decctltopch1,
decdatavalidtopch1 => decdatavalidtopch1,
runningdisptopch1 => runningdisptopch1,
txdatatstopch1 => txdatatstopch1,
txctltstopch1 => txctltstopch1,
fiforstrdqdtopch1 => fiforstrdqdtopch1,
endskwqdtopch1 => endskwqdtopch1,
endskwrdptrstopch1 => endskwrdptrstopch1,
alignstatustopch1 => alignstatustopch1,
alignstatussync0topch1 => alignstatussync0topch1,
fifordoutcomp0topch1 => fifordoutcomp0topch1,
cgcomprddalltopch1 => cgcomprddalltopch1,
cgcompwralltopch1 => cgcompwralltopch1,
delcondmet0topch1 => delcondmet0topch1,
insertincomplete0topch1 => insertincomplete0topch1,
fifoovr0topch1 => fifoovr0topch1,
latencycomp0topch1 => latencycomp0topch1,
rxdatarstopch1 => rxdatarstopch1,
rxctlrstopch1 => rxctlrstopch1,
rdenablesynctopch0 => rdenablesynctopch0,
txdatatctopch0 => txdatatctopch0,
txctltctopch0 => txctltctopch0,
syncstatustopch0 => syncstatustopch0,
rdaligntopch0 => rdaligntopch0,
aligndetsynctopch0 => aligndetsynctopch0,
fifordintopch0 => fifordintopch0,
alignstatussynctopch0 => alignstatussynctopch0,
cgcomprddintopch0 => cgcomprddintopch0,
cgcompwrintopch0 => cgcompwrintopch0,
delcondmetintopch0 => delcondmetintopch0,
fifoovrintopch0 => fifoovrintopch0,
latencycompintopch0 => latencycompintopch0,
insertincompleteintopch0 => insertincompleteintopch0,
decdatatopch0 => decdatatopch0,
decctltopch0 => decctltopch0,
decdatavalidtopch0 => decdatavalidtopch0,
runningdisptopch0 => runningdisptopch0,
txdatatstopch0 => txdatatstopch0,
txctltstopch0 => txctltstopch0,
fiforstrdqdtopch0 => fiforstrdqdtopch0,
endskwqdtopch0 => endskwqdtopch0,
endskwrdptrstopch0 => endskwrdptrstopch0,
alignstatustopch0 => alignstatustopch0,
alignstatussync0topch0 => alignstatussync0topch0,
fifordoutcomp0topch0 => fifordoutcomp0topch0,
cgcomprddalltopch0 => cgcomprddalltopch0,
cgcompwralltopch0 => cgcompwralltopch0,
delcondmet0topch0 => delcondmet0topch0,
insertincomplete0topch0 => insertincomplete0topch0,
fifoovr0topch0 => fifoovr0topch0,
latencycomp0topch0 => latencycomp0topch0,
rxdatarstopch0 => rxdatarstopch0,
rxctlrstopch0 => rxctlrstopch0,
rdenablesyncch2 => rdenablesyncch2,
txdatatcch2 => txdatatcch2,
txctltcch2 => txctltcch2,
syncstatusch2 => syncstatusch2,
rdalignch2 => rdalignch2,
aligndetsyncch2 => aligndetsyncch2,
fifordinch2 => fifordinch2,
alignstatussyncch2 => alignstatussyncch2,
cgcomprddinch2 => cgcomprddinch2,
cgcompwrinch2 => cgcompwrinch2,
delcondmetinch2 => delcondmetinch2,
fifoovrinch2 => fifoovrinch2,
latencycompinch2 => latencycompinch2,
insertincompleteinch2 => insertincompleteinch2,
decdatach2 => decdatach2,
decctlch2 => decctlch2,
decdatavalidch2 => decdatavalidch2,
runningdispch2 => runningdispch2,
txdatatsch2 => txdatatsch2,
txctltsch2 => txctltsch2,
fiforstrdqdch2 => fiforstrdqdch2,
endskwqdch2 => endskwqdch2,
endskwrdptrsch2 => endskwrdptrsch2,
alignstatusch2 => alignstatusch2,
alignstatussync0ch2 => alignstatussync0ch2,
fifordoutcomp0ch2 => fifordoutcomp0ch2,
cgcomprddallch2 => cgcomprddallch2,
cgcompwrallch2 => cgcompwrallch2,
delcondmet0ch2 => delcondmet0ch2,
insertincomplete0ch2 => insertincomplete0ch2,
fifoovr0ch2 => fifoovr0ch2,
latencycomp0ch2 => latencycomp0ch2,
rxdatarsch2 => rxdatarsch2,
rxctlrsch2 => rxctlrsch2,
rdenablesyncch1 => rdenablesyncch1,
txdatatcch1 => txdatatcch1,
txctltcch1 => txctltcch1,
syncstatusch1 => syncstatusch1,
rdalignch1 => rdalignch1,
aligndetsyncch1 => aligndetsyncch1,
fifordinch1 => fifordinch1,
alignstatussyncch1 => alignstatussyncch1,
cgcomprddinch1 => cgcomprddinch1,
cgcompwrinch1 => cgcompwrinch1,
delcondmetinch1 => delcondmetinch1,
fifoovrinch1 => fifoovrinch1,
latencycompinch1 => latencycompinch1,
insertincompleteinch1 => insertincompleteinch1,
decdatach1 => decdatach1,
decctlch1 => decctlch1,
decdatavalidch1 => decdatavalidch1,
runningdispch1 => runningdispch1,
txdatatsch1 => txdatatsch1,
txctltsch1 => txctltsch1,
fiforstrdqdch1 => fiforstrdqdch1,
endskwqdch1 => endskwqdch1,
endskwrdptrsch1 => endskwrdptrsch1,
alignstatusch1 => alignstatusch1,
alignstatussync0ch1 => alignstatussync0ch1,
fifordoutcomp0ch1 => fifordoutcomp0ch1,
cgcomprddallch1 => cgcomprddallch1,
cgcompwrallch1 => cgcompwrallch1,
delcondmet0ch1 => delcondmet0ch1,
insertincomplete0ch1 => insertincomplete0ch1,
fifoovr0ch1 => fifoovr0ch1,
latencycomp0ch1 => latencycomp0ch1,
rxdatarsch1 => rxdatarsch1,
rxctlrsch1 => rxctlrsch1,
rdenablesyncch0 => rdenablesyncch0,
txdatatcch0 => txdatatcch0,
txctltcch0 => txctltcch0,
syncstatusch0 => syncstatusch0,
rdalignch0 => rdalignch0,
aligndetsyncch0 => aligndetsyncch0,
fifordinch0 => fifordinch0,
alignstatussyncch0 => alignstatussyncch0,
cgcomprddinch0 => cgcomprddinch0,
cgcompwrinch0 => cgcompwrinch0,
delcondmetinch0 => delcondmetinch0,
fifoovrinch0 => fifoovrinch0,
latencycompinch0 => latencycompinch0,
insertincompleteinch0 => insertincompleteinch0,
decdatach0 => decdatach0,
decctlch0 => decctlch0,
decdatavalidch0 => decdatavalidch0,
runningdispch0 => runningdispch0,
txdatatsch0 => txdatatsch0,
txctltsch0 => txctltsch0,
fiforstrdqdch0 => fiforstrdqdch0,
endskwqdch0 => endskwqdch0,
endskwrdptrsch0 => endskwrdptrsch0,
alignstatusch0 => alignstatusch0,
alignstatussync0ch0 => alignstatussync0ch0,
fifordoutcomp0ch0 => fifordoutcomp0ch0,
cgcomprddallch0 => cgcomprddallch0,
cgcompwrallch0 => cgcompwrallch0,
delcondmet0ch0 => delcondmet0ch0,
insertincomplete0ch0 => insertincomplete0ch0,
fifoovr0ch0 => fifoovr0ch0,
latencycomp0ch0 => latencycomp0ch0,
rxdatarsch0 => rxdatarsch0,
rxctlrsch0 => rxctlrsch0,
rdenablesyncbotch2 => rdenablesyncbotch2,
txdatatcbotch2 => txdatatcbotch2,
txctltcbotch2 => txctltcbotch2,
syncstatusbotch2 => syncstatusbotch2,
rdalignbotch2 => rdalignbotch2,
aligndetsyncbotch2 => aligndetsyncbotch2,
fifordinbotch2 => fifordinbotch2,
alignstatussyncbotch2 => alignstatussyncbotch2,
cgcomprddinbotch2 => cgcomprddinbotch2,
cgcompwrinbotch2 => cgcompwrinbotch2,
delcondmetinbotch2 => delcondmetinbotch2,
fifoovrinbotch2 => fifoovrinbotch2,
latencycompinbotch2 => latencycompinbotch2,
insertincompleteinbotch2 => insertincompleteinbotch2,
decdatabotch2 => decdatabotch2,
decctlbotch2 => decctlbotch2,
decdatavalidbotch2 => decdatavalidbotch2,
runningdispbotch2 => runningdispbotch2,
txdatatsbotch2 => txdatatsbotch2,
txctltsbotch2 => txctltsbotch2,
fiforstrdqdbotch2 => fiforstrdqdbotch2,
endskwqdbotch2 => endskwqdbotch2,
endskwrdptrsbotch2 => endskwrdptrsbotch2,
alignstatusbotch2 => alignstatusbotch2,
alignstatussync0botch2 => alignstatussync0botch2,
fifordoutcomp0botch2 => fifordoutcomp0botch2,
cgcomprddallbotch2 => cgcomprddallbotch2,
cgcompwrallbotch2 => cgcompwrallbotch2,
delcondmet0botch2 => delcondmet0botch2,
insertincomplete0botch2 => insertincomplete0botch2,
fifoovr0botch2 => fifoovr0botch2,
latencycomp0botch2 => latencycomp0botch2,
rxdatarsbotch2 => rxdatarsbotch2,
rxctlrsbotch2 => rxctlrsbotch2
);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
entity stratixv_hssi_8g_rx_pcs is
generic (
prot_mode : string := "gige";
tx_rx_parallel_loopback : string := "dis_plpbk";
pma_dw : string := "eight_bit";
pcs_bypass : string := "dis_pcs_bypass";
polarity_inversion : string := "dis_pol_inv";
wa_pd : string := "wa_pd_10";
wa_pd_data : bit_vector := B"0000000000000000000000000000000000000000";
wa_boundary_lock_ctrl : string := "bit_slip";
wa_pld_controlled : string := "dis_pld_ctrl";
wa_sync_sm_ctrl : string := "gige_sync_sm";
wa_rknumber_data : bit_vector := B"00000000";
wa_renumber_data : bit_vector := B"000000";
wa_rgnumber_data : bit_vector := B"00000000";
wa_rosnumber_data : bit_vector := B"00";
wa_kchar : string := "dis_kchar";
wa_det_latency_sync_status_beh : string := "assert_sync_status_non_imm";
wa_clk_slip_spacing : string := "min_clk_slip_spacing";
wa_clk_slip_spacing_data : bit_vector := B"0000010000";
bit_reversal : string := "dis_bit_reversal";
symbol_swap : string := "dis_symbol_swap";
deskew_pattern : bit_vector := B"1101101000";
deskew_prog_pattern_only : string := "en_deskew_prog_pat_only";
rate_match : string := "dis_rm";
eightb_tenb_decoder : string := "dis_8b10b";
err_flags_sel : string := "err_flags_wa";
polinv_8b10b_dec : string := "dis_polinv_8b10b_dec";
eightbtenb_decoder_output_sel : string := "data_8b10b_decoder";
invalid_code_flag_only : string := "dis_invalid_code_only";
auto_error_replacement : string := "dis_err_replace";
pad_or_edb_error_replace : string := "replace_edb";
byte_deserializer : string := "dis_bds";
byte_order : string := "dis_bo";
re_bo_on_wa : string := "dis_re_bo_on_wa";
bo_pattern : bit_vector := B"00000000000000000000";
bo_pad : bit_vector := B"0000000000";
phase_compensation_fifo : string := "low_latency";
prbs_ver : string := "dis_prbs";
cid_pattern : string := "cid_pattern_0";
cid_pattern_len : bit_vector := B"00000000";
bist_ver : string := "dis_bist";
cdr_ctrl : string := "dis_cdr_ctrl";
cdr_ctrl_rxvalid_mask : string := "dis_rxvalid_mask";
wait_cnt : bit_vector := B"00000000";
mask_cnt : bit_vector := B"1111111111";
auto_deassert_pc_rst_cnt_data : bit_vector := B"00000";
auto_pc_en_cnt_data : bit_vector := B"0000000";
eidle_entry_sd : string := "dis_eidle_sd";
eidle_entry_eios : string := "dis_eidle_eios";
eidle_entry_iei : string := "dis_eidle_iei";
rx_rcvd_clk : string := "rcvd_clk_rcvd_clk";
rx_clk1 : string := "rcvd_clk_clk1";
rx_clk2 : string := "rcvd_clk_clk2";
rx_rd_clk : string := "pld_rx_clk";
dw_one_or_two_symbol_bo : string := "donot_care_one_two_bo";
comp_fifo_rst_pld_ctrl : string := "dis_comp_fifo_rst_pld_ctrl";
bypass_pipeline_reg : string := "dis_bypass_pipeline";
agg_block_sel : string := "same_smrt_pack";
test_bus_sel : string := "test_bus_sel";
wa_rvnumber_data : bit_vector := B"0000000000000";
ctrl_plane_bonding_compensation : string := "dis_compensation";
clock_gate_rx : string := "dis_clk_gating";
prbs_ver_clr_flag : string := "dis_prbs_clr_flag";
hip_mode : string := "dis_hip";
ctrl_plane_bonding_distribution : string := "not_master_chnl_distr";
ctrl_plane_bonding_consumption : string := "individual";
pma_done_count : bit_vector := B"000000000000000000";
test_mode : string := "prbs";
bist_ver_clr_flag : string := "dis_bist_clr_flag";
wa_disp_err_flag : string := "dis_disp_err_flag";
wait_for_phfifo_cnt_data : bit_vector := B"000000";
runlength_check : string := "en_runlength_sw";
test_bus_sel_val : bit_vector := B"0000";
runlength_val : bit_vector := B"000000";
force_signal_detect : string := "en_force_signal_detect";
deskew : string := "dis_deskew";
rx_wr_clk : string := "rx_clk2_div_1_2_4";
rx_clk_free_running : string := "en_rx_clk_free_run";
rx_pcs_urst : string := "en_rx_pcs_urst";
self_switch_dw_scaling : string := "dis_self_switch_dw_scaling";
pipe_if_enable : string := "dis_pipe_rx";
pc_fifo_rst_pld_ctrl : string := "dis_pc_fifo_rst_pld_ctrl";
auto_speed_nego_gen2 : string := "dis_auto_speed_nego_g2";
auto_speed_nego_gen3 : string := "dis_auto_speed_nego_g3";
ibm_invalid_code : string := "dis_ibm_invalid_code";
channel_number : string := "int";
rx_refclk : string := "dis_refclk_sel"
);
port (
hrdrst : in std_logic_vector(0 downto 0);
rxpcsrst : in std_logic_vector(0 downto 0);
rmfifouserrst : in std_logic_vector(0 downto 0);
phfifouserrst : in std_logic_vector(0 downto 0);
scanmode : in std_logic_vector(0 downto 0);
enablecommadetect : in std_logic_vector(0 downto 0);
a1a2size : in std_logic_vector(0 downto 0);
bitslip : in std_logic_vector(0 downto 0);
rmfiforeadenable : in std_logic_vector(0 downto 0);
rmfifowriteenable : in std_logic_vector(0 downto 0);
pldrxclk : in std_logic_vector(0 downto 0);
softresetrclk1 : out std_logic_vector(0 downto 0);
polinvrx : in std_logic_vector(0 downto 0);
bitreversalenable : in std_logic_vector(0 downto 0);
bytereversalenable : in std_logic_vector(0 downto 0);
rcvdclkpma : in std_logic_vector(0 downto 0);
datain : in std_logic_vector(19 downto 0);
sigdetfrompma : in std_logic_vector(0 downto 0);
fiforstrdqd : in std_logic_vector(0 downto 0);
endskwqd : in std_logic_vector(0 downto 0);
endskwrdptrs : in std_logic_vector(0 downto 0);
alignstatus : in std_logic_vector(0 downto 0);
fiforstrdqdtoporbot : in std_logic_vector(0 downto 0);
endskwqdtoporbot : in std_logic_vector(0 downto 0);
endskwrdptrstoporbot : in std_logic_vector(0 downto 0);
alignstatustoporbot : in std_logic_vector(0 downto 0);
datafrinaggblock : in std_logic_vector(7 downto 0);
ctrlfromaggblock : in std_logic_vector(0 downto 0);
rxdatarstoporbot : in std_logic_vector(7 downto 0);
rxcontrolrstoporbot : in std_logic_vector(0 downto 0);
rcvdclk0pma : in std_logic_vector(0 downto 0);
parallelloopback : in std_logic_vector(19 downto 0);
txpmaclk : in std_logic_vector(0 downto 0);
byteorder : in std_logic_vector(0 downto 0);
pxfifowrdisable : in std_logic_vector(0 downto 0);
pcfifordenable : in std_logic_vector(0 downto 0);
pmatestbus : in std_logic_vector(7 downto 0);
encodertestbus : in std_logic_vector(9 downto 0);
txctrltestbus : in std_logic_vector(9 downto 0);
phystatusinternal : in std_logic_vector(0 downto 0);
rxvalidinternal : in std_logic_vector(0 downto 0);
rxstatusinternal : in std_logic_vector(2 downto 0);
phystatuspcsgen3 : in std_logic_vector(0 downto 0);
rxvalidpcsgen3 : in std_logic_vector(0 downto 0);
rxstatuspcsgen3 : in std_logic_vector(2 downto 0);
rxdatavalidpcsgen3 : in std_logic_vector(3 downto 0);
rxblkstartpcsgen3 : in std_logic_vector(3 downto 0);
rxsynchdrpcsgen3 : in std_logic_vector(1 downto 0);
rxdatapcsgen3 : in std_logic_vector(63 downto 0);
pipepowerdown : in std_logic_vector(1 downto 0);
rateswitchcontrol : in std_logic_vector(0 downto 0);
gen2ngen1 : in std_logic_vector(0 downto 0);
gen2ngen1bundle : in std_logic_vector(0 downto 0);
eidleinfersel : in std_logic_vector(2 downto 0);
pipeloopbk : in std_logic_vector(0 downto 0);
pldltr : in std_logic_vector(0 downto 0);
prbscidenable : in std_logic_vector(0 downto 0);
txdiv2syncoutpipeup : in std_logic_vector(0 downto 0);
fifoselectoutpipeup : in std_logic_vector(0 downto 0);
txwrenableoutpipeup : in std_logic_vector(0 downto 0);
txrdenableoutpipeup : in std_logic_vector(0 downto 0);
txdiv2syncoutpipedown : in std_logic_vector(0 downto 0);
fifoselectoutpipedown : in std_logic_vector(0 downto 0);
txwrenableoutpipedown : in std_logic_vector(0 downto 0);
txrdenableoutpipedown : in std_logic_vector(0 downto 0);
alignstatussync0 : in std_logic_vector(0 downto 0);
rmfifordincomp0 : in std_logic_vector(0 downto 0);
cgcomprddall : in std_logic_vector(0 downto 0);
cgcompwrall : in std_logic_vector(0 downto 0);
delcondmet0 : in std_logic_vector(0 downto 0);
fifoovr0 : in std_logic_vector(0 downto 0);
latencycomp0 : in std_logic_vector(0 downto 0);
insertincomplete0 : in std_logic_vector(0 downto 0);
alignstatussync0toporbot : in std_logic_vector(0 downto 0);
fifordincomp0toporbot : in std_logic_vector(0 downto 0);
cgcomprddalltoporbot : in std_logic_vector(0 downto 0);
cgcompwralltoporbot : in std_logic_vector(0 downto 0);
delcondmet0toporbot : in std_logic_vector(0 downto 0);
fifoovr0toporbot : in std_logic_vector(0 downto 0);
latencycomp0toporbot : in std_logic_vector(0 downto 0);
insertincomplete0toporbot : in std_logic_vector(0 downto 0);
alignstatussync : out std_logic_vector(0 downto 0);
fifordoutcomp : out std_logic_vector(0 downto 0);
cgcomprddout : out std_logic_vector(1 downto 0);
cgcompwrout : out std_logic_vector(1 downto 0);
delcondmetout : out std_logic_vector(0 downto 0);
fifoovrout : out std_logic_vector(0 downto 0);
latencycompout : out std_logic_vector(0 downto 0);
insertincompleteout : out std_logic_vector(0 downto 0);
dataout : out std_logic_vector(63 downto 0);
parallelrevloopback : out std_logic_vector(19 downto 0);
clocktopld : out std_logic_vector(0 downto 0);
bisterr : out std_logic_vector(0 downto 0);
clk2b : out std_logic_vector(0 downto 0);
rcvdclkpmab : out std_logic_vector(0 downto 0);
syncstatus : out std_logic_vector(0 downto 0);
decoderdatavalid : out std_logic_vector(0 downto 0);
decoderdata : out std_logic_vector(7 downto 0);
decoderctrl : out std_logic_vector(0 downto 0);
runningdisparity : out std_logic_vector(1 downto 0);
selftestdone : out std_logic_vector(0 downto 0);
selftesterr : out std_logic_vector(0 downto 0);
errdata : out std_logic_vector(15 downto 0);
errctrl : out std_logic_vector(1 downto 0);
prbsdone : out std_logic_vector(0 downto 0);
prbserrlt : out std_logic_vector(0 downto 0);
signaldetectout : out std_logic_vector(0 downto 0);
aligndetsync : out std_logic_vector(1 downto 0);
rdalign : out std_logic_vector(1 downto 0);
bistdone : out std_logic_vector(0 downto 0);
runlengthviolation : out std_logic_vector(0 downto 0);
rlvlt : out std_logic_vector(0 downto 0);
rmfifopartialfull : out std_logic_vector(0 downto 0);
rmfifofull : out std_logic_vector(0 downto 0);
rmfifopartialempty : out std_logic_vector(0 downto 0);
rmfifoempty : out std_logic_vector(0 downto 0);
pcfifofull : out std_logic_vector(0 downto 0);
pcfifoempty : out std_logic_vector(0 downto 0);
a1a2k1k2flag : out std_logic_vector(3 downto 0);
byteordflag : out std_logic_vector(0 downto 0);
rxpipeclk : out std_logic_vector(0 downto 0);
channeltestbusout : out std_logic_vector(9 downto 0);
rxpipesoftreset : out std_logic_vector(0 downto 0);
phystatus : out std_logic_vector(0 downto 0);
rxvalid : out std_logic_vector(0 downto 0);
rxstatus : out std_logic_vector(2 downto 0);
pipedata : out std_logic_vector(63 downto 0);
rxdatavalid : out std_logic_vector(3 downto 0);
rxblkstart : out std_logic_vector(3 downto 0);
rxsynchdr : out std_logic_vector(1 downto 0);
speedchange : out std_logic_vector(0 downto 0);
eidledetected : out std_logic_vector(0 downto 0);
wordalignboundary : out std_logic_vector(4 downto 0);
rxclkslip : out std_logic_vector(0 downto 0);
eidleexit : out std_logic_vector(0 downto 0);
earlyeios : out std_logic_vector(0 downto 0);
ltr : out std_logic_vector(0 downto 0);
pcswrapbackin : in std_logic_vector(69 downto 0);
rxdivsyncinchnlup : in std_logic_vector(1 downto 0);
rxdivsyncinchnldown : in std_logic_vector(1 downto 0);
wrenableinchnlup : in std_logic_vector(0 downto 0);
wrenableinchnldown : in std_logic_vector(0 downto 0);
rdenableinchnlup : in std_logic_vector(0 downto 0);
rdenableinchnldown : in std_logic_vector(0 downto 0);
rxweinchnlup : in std_logic_vector(1 downto 0);
rxweinchnldown : in std_logic_vector(1 downto 0);
resetpcptrsinchnlup : in std_logic_vector(0 downto 0);
resetpcptrsinchnldown : in std_logic_vector(0 downto 0);
configselinchnlup : in std_logic_vector(0 downto 0);
configselinchnldown : in std_logic_vector(0 downto 0);
speedchangeinchnlup : in std_logic_vector(0 downto 0);
speedchangeinchnldown : in std_logic_vector(0 downto 0);
pcieswitch : out std_logic_vector(0 downto 0);
rxdivsyncoutchnlup : out std_logic_vector(1 downto 0);
rxweoutchnlup : out std_logic_vector(1 downto 0);
wrenableoutchnlup : out std_logic_vector(0 downto 0);
rdenableoutchnlup : out std_logic_vector(0 downto 0);
resetpcptrsoutchnlup : out std_logic_vector(0 downto 0);
speedchangeoutchnlup : out std_logic_vector(0 downto 0);
configseloutchnlup : out std_logic_vector(0 downto 0);
rxdivsyncoutchnldown : out std_logic_vector(1 downto 0);
rxweoutchnldown : out std_logic_vector(1 downto 0);
wrenableoutchnldown : out std_logic_vector(0 downto 0);
rdenableoutchnldown : out std_logic_vector(0 downto 0);
resetpcptrsoutchnldown : out std_logic_vector(0 downto 0);
speedchangeoutchnldown : out std_logic_vector(0 downto 0);
configseloutchnldown : out std_logic_vector(0 downto 0);
resetpcptrsinchnluppipe : out std_logic_vector(0 downto 0);
resetpcptrsinchnldownpipe : out std_logic_vector(0 downto 0);
speedchangeinchnluppipe : out std_logic_vector(0 downto 0);
speedchangeinchnldownpipe : out std_logic_vector(0 downto 0);
disablepcfifobyteserdes : out std_logic_vector(0 downto 0);
resetpcptrs : out std_logic_vector(0 downto 0);
rcvdclkagg : in std_logic_vector(0 downto 0);
rcvdclkaggtoporbot : in std_logic_vector(0 downto 0);
dispcbytegen3 : in std_logic_vector(0 downto 0);
refclkdig : in std_logic_vector(0 downto 0);
txfifordclkraw : in std_logic_vector(0 downto 0);
resetpcptrsgen3 : in std_logic_vector(0 downto 0);
syncdatain : out std_logic_vector(0 downto 0);
observablebyteserdesclock : out std_logic_vector(0 downto 0)
);
end stratixv_hssi_8g_rx_pcs;
architecture behavior of stratixv_hssi_8g_rx_pcs is
component stratixv_hssi_8g_rx_pcs_encrypted
generic (
prot_mode : string := "gige";
tx_rx_parallel_loopback : string := "dis_plpbk";
pma_dw : string := "eight_bit";
pcs_bypass : string := "dis_pcs_bypass";
polarity_inversion : string := "dis_pol_inv";
wa_pd : string := "wa_pd_10";
wa_pd_data : bit_vector := B"0000000000000000000000000000000000000000";
wa_boundary_lock_ctrl : string := "bit_slip";
wa_pld_controlled : string := "dis_pld_ctrl";
wa_sync_sm_ctrl : string := "gige_sync_sm";
wa_rknumber_data : bit_vector := B"00000000";
wa_renumber_data : bit_vector := B"000000";
wa_rgnumber_data : bit_vector := B"00000000";
wa_rosnumber_data : bit_vector := B"00";
wa_kchar : string := "dis_kchar";
wa_det_latency_sync_status_beh : string := "assert_sync_status_non_imm";
wa_clk_slip_spacing : string := "min_clk_slip_spacing";
wa_clk_slip_spacing_data : bit_vector := B"0000010000";
bit_reversal : string := "dis_bit_reversal";
symbol_swap : string := "dis_symbol_swap";
deskew_pattern : bit_vector := B"1101101000";
deskew_prog_pattern_only : string := "en_deskew_prog_pat_only";
rate_match : string := "dis_rm";
eightb_tenb_decoder : string := "dis_8b10b";
err_flags_sel : string := "err_flags_wa";
polinv_8b10b_dec : string := "dis_polinv_8b10b_dec";
eightbtenb_decoder_output_sel : string := "data_8b10b_decoder";
invalid_code_flag_only : string := "dis_invalid_code_only";
auto_error_replacement : string := "dis_err_replace";
pad_or_edb_error_replace : string := "replace_edb";
byte_deserializer : string := "dis_bds";
byte_order : string := "dis_bo";
re_bo_on_wa : string := "dis_re_bo_on_wa";
bo_pattern : bit_vector := B"00000000000000000000";
bo_pad : bit_vector := B"0000000000";
phase_compensation_fifo : string := "low_latency";
prbs_ver : string := "dis_prbs";
cid_pattern : string := "cid_pattern_0";
cid_pattern_len : bit_vector := B"00000000";
bist_ver : string := "dis_bist";
cdr_ctrl : string := "dis_cdr_ctrl";
cdr_ctrl_rxvalid_mask : string := "dis_rxvalid_mask";
wait_cnt : bit_vector := B"00000000";
mask_cnt : bit_vector := B"1111111111";
auto_deassert_pc_rst_cnt_data : bit_vector := B"00000";
auto_pc_en_cnt_data : bit_vector := B"0000000";
eidle_entry_sd : string := "dis_eidle_sd";
eidle_entry_eios : string := "dis_eidle_eios";
eidle_entry_iei : string := "dis_eidle_iei";
rx_rcvd_clk : string := "rcvd_clk_rcvd_clk";
rx_clk1 : string := "rcvd_clk_clk1";
rx_clk2 : string := "rcvd_clk_clk2";
rx_rd_clk : string := "pld_rx_clk";
dw_one_or_two_symbol_bo : string := "donot_care_one_two_bo";
comp_fifo_rst_pld_ctrl : string := "dis_comp_fifo_rst_pld_ctrl";
bypass_pipeline_reg : string := "dis_bypass_pipeline";
agg_block_sel : string := "same_smrt_pack";
test_bus_sel : string := "test_bus_sel";
wa_rvnumber_data : bit_vector := B"0000000000000";
ctrl_plane_bonding_compensation : string := "dis_compensation";
clock_gate_rx : string := "dis_clk_gating";
prbs_ver_clr_flag : string := "dis_prbs_clr_flag";
hip_mode : string := "dis_hip";
ctrl_plane_bonding_distribution : string := "not_master_chnl_distr";
ctrl_plane_bonding_consumption : string := "individual";
pma_done_count : bit_vector := B"000000000000000000";
test_mode : string := "prbs";
bist_ver_clr_flag : string := "dis_bist_clr_flag";
wa_disp_err_flag : string := "dis_disp_err_flag";
wait_for_phfifo_cnt_data : bit_vector := B"000000";
runlength_check : string := "en_runlength_sw";
test_bus_sel_val : bit_vector := B"0000";
runlength_val : bit_vector := B"000000";
force_signal_detect : string := "en_force_signal_detect";
deskew : string := "dis_deskew";
rx_wr_clk : string := "rx_clk2_div_1_2_4";
rx_clk_free_running : string := "en_rx_clk_free_run";
rx_pcs_urst : string := "en_rx_pcs_urst";
self_switch_dw_scaling : string := "dis_self_switch_dw_scaling";
pipe_if_enable : string := "dis_pipe_rx";
pc_fifo_rst_pld_ctrl : string := "dis_pc_fifo_rst_pld_ctrl";
auto_speed_nego_gen2 : string := "dis_auto_speed_nego_g2";
auto_speed_nego_gen3 : string := "dis_auto_speed_nego_g3";
ibm_invalid_code : string := "dis_ibm_invalid_code";
channel_number : string := "int";
rx_refclk : string := "dis_refclk_sel"
);
port (
hrdrst : in std_logic_vector(0 downto 0);
rxpcsrst : in std_logic_vector(0 downto 0);
rmfifouserrst : in std_logic_vector(0 downto 0);
phfifouserrst : in std_logic_vector(0 downto 0);
scanmode : in std_logic_vector(0 downto 0);
enablecommadetect : in std_logic_vector(0 downto 0);
a1a2size : in std_logic_vector(0 downto 0);
bitslip : in std_logic_vector(0 downto 0);
rmfiforeadenable : in std_logic_vector(0 downto 0);
rmfifowriteenable : in std_logic_vector(0 downto 0);
pldrxclk : in std_logic_vector(0 downto 0);
softresetrclk1 : out std_logic_vector(0 downto 0);
polinvrx : in std_logic_vector(0 downto 0);
bitreversalenable : in std_logic_vector(0 downto 0);
bytereversalenable : in std_logic_vector(0 downto 0);
rcvdclkpma : in std_logic_vector(0 downto 0);
datain : in std_logic_vector(19 downto 0);
sigdetfrompma : in std_logic_vector(0 downto 0);
fiforstrdqd : in std_logic_vector(0 downto 0);
endskwqd : in std_logic_vector(0 downto 0);
endskwrdptrs : in std_logic_vector(0 downto 0);
alignstatus : in std_logic_vector(0 downto 0);
fiforstrdqdtoporbot : in std_logic_vector(0 downto 0);
endskwqdtoporbot : in std_logic_vector(0 downto 0);
endskwrdptrstoporbot : in std_logic_vector(0 downto 0);
alignstatustoporbot : in std_logic_vector(0 downto 0);
datafrinaggblock : in std_logic_vector(7 downto 0);
ctrlfromaggblock : in std_logic_vector(0 downto 0);
rxdatarstoporbot : in std_logic_vector(7 downto 0);
rxcontrolrstoporbot : in std_logic_vector(0 downto 0);
rcvdclk0pma : in std_logic_vector(0 downto 0);
parallelloopback : in std_logic_vector(19 downto 0);
txpmaclk : in std_logic_vector(0 downto 0);
byteorder : in std_logic_vector(0 downto 0);
pxfifowrdisable : in std_logic_vector(0 downto 0);
pcfifordenable : in std_logic_vector(0 downto 0);
pmatestbus : in std_logic_vector(7 downto 0);
encodertestbus : in std_logic_vector(9 downto 0);
txctrltestbus : in std_logic_vector(9 downto 0);
phystatusinternal : in std_logic_vector(0 downto 0);
rxvalidinternal : in std_logic_vector(0 downto 0);
rxstatusinternal : in std_logic_vector(2 downto 0);
phystatuspcsgen3 : in std_logic_vector(0 downto 0);
rxvalidpcsgen3 : in std_logic_vector(0 downto 0);
rxstatuspcsgen3 : in std_logic_vector(2 downto 0);
rxdatavalidpcsgen3 : in std_logic_vector(3 downto 0);
rxblkstartpcsgen3 : in std_logic_vector(3 downto 0);
rxsynchdrpcsgen3 : in std_logic_vector(1 downto 0);
rxdatapcsgen3 : in std_logic_vector(63 downto 0);
pipepowerdown : in std_logic_vector(1 downto 0);
rateswitchcontrol : in std_logic_vector(0 downto 0);
gen2ngen1 : in std_logic_vector(0 downto 0);
gen2ngen1bundle : in std_logic_vector(0 downto 0);
eidleinfersel : in std_logic_vector(2 downto 0);
pipeloopbk : in std_logic_vector(0 downto 0);
pldltr : in std_logic_vector(0 downto 0);
prbscidenable : in std_logic_vector(0 downto 0);
txdiv2syncoutpipeup : in std_logic_vector(0 downto 0);
fifoselectoutpipeup : in std_logic_vector(0 downto 0);
txwrenableoutpipeup : in std_logic_vector(0 downto 0);
txrdenableoutpipeup : in std_logic_vector(0 downto 0);
txdiv2syncoutpipedown : in std_logic_vector(0 downto 0);
fifoselectoutpipedown : in std_logic_vector(0 downto 0);
txwrenableoutpipedown : in std_logic_vector(0 downto 0);
txrdenableoutpipedown : in std_logic_vector(0 downto 0);
alignstatussync0 : in std_logic_vector(0 downto 0);
rmfifordincomp0 : in std_logic_vector(0 downto 0);
cgcomprddall : in std_logic_vector(0 downto 0);
cgcompwrall : in std_logic_vector(0 downto 0);
delcondmet0 : in std_logic_vector(0 downto 0);
fifoovr0 : in std_logic_vector(0 downto 0);
latencycomp0 : in std_logic_vector(0 downto 0);
insertincomplete0 : in std_logic_vector(0 downto 0);
alignstatussync0toporbot : in std_logic_vector(0 downto 0);
fifordincomp0toporbot : in std_logic_vector(0 downto 0);
cgcomprddalltoporbot : in std_logic_vector(0 downto 0);
cgcompwralltoporbot : in std_logic_vector(0 downto 0);
delcondmet0toporbot : in std_logic_vector(0 downto 0);
fifoovr0toporbot : in std_logic_vector(0 downto 0);
latencycomp0toporbot : in std_logic_vector(0 downto 0);
insertincomplete0toporbot : in std_logic_vector(0 downto 0);
alignstatussync : out std_logic_vector(0 downto 0);
fifordoutcomp : out std_logic_vector(0 downto 0);
cgcomprddout : out std_logic_vector(1 downto 0);
cgcompwrout : out std_logic_vector(1 downto 0);
delcondmetout : out std_logic_vector(0 downto 0);
fifoovrout : out std_logic_vector(0 downto 0);
latencycompout : out std_logic_vector(0 downto 0);
insertincompleteout : out std_logic_vector(0 downto 0);
dataout : out std_logic_vector(63 downto 0);
parallelrevloopback : out std_logic_vector(19 downto 0);
clocktopld : out std_logic_vector(0 downto 0);
bisterr : out std_logic_vector(0 downto 0);
clk2b : out std_logic_vector(0 downto 0);
rcvdclkpmab : out std_logic_vector(0 downto 0);
syncstatus : out std_logic_vector(0 downto 0);
decoderdatavalid : out std_logic_vector(0 downto 0);
decoderdata : out std_logic_vector(7 downto 0);
decoderctrl : out std_logic_vector(0 downto 0);
runningdisparity : out std_logic_vector(1 downto 0);
selftestdone : out std_logic_vector(0 downto 0);
selftesterr : out std_logic_vector(0 downto 0);
errdata : out std_logic_vector(15 downto 0);
errctrl : out std_logic_vector(1 downto 0);
prbsdone : out std_logic_vector(0 downto 0);
prbserrlt : out std_logic_vector(0 downto 0);
signaldetectout : out std_logic_vector(0 downto 0);
aligndetsync : out std_logic_vector(1 downto 0);
rdalign : out std_logic_vector(1 downto 0);
bistdone : out std_logic_vector(0 downto 0);
runlengthviolation : out std_logic_vector(0 downto 0);
rlvlt : out std_logic_vector(0 downto 0);
rmfifopartialfull : out std_logic_vector(0 downto 0);
rmfifofull : out std_logic_vector(0 downto 0);
rmfifopartialempty : out std_logic_vector(0 downto 0);
rmfifoempty : out std_logic_vector(0 downto 0);
pcfifofull : out std_logic_vector(0 downto 0);
pcfifoempty : out std_logic_vector(0 downto 0);
a1a2k1k2flag : out std_logic_vector(3 downto 0);
byteordflag : out std_logic_vector(0 downto 0);
rxpipeclk : out std_logic_vector(0 downto 0);
channeltestbusout : out std_logic_vector(9 downto 0);
rxpipesoftreset : out std_logic_vector(0 downto 0);
phystatus : out std_logic_vector(0 downto 0);
rxvalid : out std_logic_vector(0 downto 0);
rxstatus : out std_logic_vector(2 downto 0);
pipedata : out std_logic_vector(63 downto 0);
rxdatavalid : out std_logic_vector(3 downto 0);
rxblkstart : out std_logic_vector(3 downto 0);
rxsynchdr : out std_logic_vector(1 downto 0);
speedchange : out std_logic_vector(0 downto 0);
eidledetected : out std_logic_vector(0 downto 0);
wordalignboundary : out std_logic_vector(4 downto 0);
rxclkslip : out std_logic_vector(0 downto 0);
eidleexit : out std_logic_vector(0 downto 0);
earlyeios : out std_logic_vector(0 downto 0);
ltr : out std_logic_vector(0 downto 0);
pcswrapbackin : in std_logic_vector(69 downto 0);
rxdivsyncinchnlup : in std_logic_vector(1 downto 0);
rxdivsyncinchnldown : in std_logic_vector(1 downto 0);
wrenableinchnlup : in std_logic_vector(0 downto 0);
wrenableinchnldown : in std_logic_vector(0 downto 0);
rdenableinchnlup : in std_logic_vector(0 downto 0);
rdenableinchnldown : in std_logic_vector(0 downto 0);
rxweinchnlup : in std_logic_vector(1 downto 0);
rxweinchnldown : in std_logic_vector(1 downto 0);
resetpcptrsinchnlup : in std_logic_vector(0 downto 0);
resetpcptrsinchnldown : in std_logic_vector(0 downto 0);
configselinchnlup : in std_logic_vector(0 downto 0);
configselinchnldown : in std_logic_vector(0 downto 0);
speedchangeinchnlup : in std_logic_vector(0 downto 0);
speedchangeinchnldown : in std_logic_vector(0 downto 0);
pcieswitch : out std_logic_vector(0 downto 0);
rxdivsyncoutchnlup : out std_logic_vector(1 downto 0);
rxweoutchnlup : out std_logic_vector(1 downto 0);
wrenableoutchnlup : out std_logic_vector(0 downto 0);
rdenableoutchnlup : out std_logic_vector(0 downto 0);
resetpcptrsoutchnlup : out std_logic_vector(0 downto 0);
speedchangeoutchnlup : out std_logic_vector(0 downto 0);
configseloutchnlup : out std_logic_vector(0 downto 0);
rxdivsyncoutchnldown : out std_logic_vector(1 downto 0);
rxweoutchnldown : out std_logic_vector(1 downto 0);
wrenableoutchnldown : out std_logic_vector(0 downto 0);
rdenableoutchnldown : out std_logic_vector(0 downto 0);
resetpcptrsoutchnldown : out std_logic_vector(0 downto 0);
speedchangeoutchnldown : out std_logic_vector(0 downto 0);
configseloutchnldown : out std_logic_vector(0 downto 0);
resetpcptrsinchnluppipe : out std_logic_vector(0 downto 0);
resetpcptrsinchnldownpipe : out std_logic_vector(0 downto 0);
speedchangeinchnluppipe : out std_logic_vector(0 downto 0);
speedchangeinchnldownpipe : out std_logic_vector(0 downto 0);
disablepcfifobyteserdes : out std_logic_vector(0 downto 0);
resetpcptrs : out std_logic_vector(0 downto 0);
rcvdclkagg : in std_logic_vector(0 downto 0);
rcvdclkaggtoporbot : in std_logic_vector(0 downto 0);
dispcbytegen3 : in std_logic_vector(0 downto 0);
refclkdig : in std_logic_vector(0 downto 0);
txfifordclkraw : in std_logic_vector(0 downto 0);
resetpcptrsgen3 : in std_logic_vector(0 downto 0);
syncdatain : out std_logic_vector(0 downto 0);
observablebyteserdesclock : out std_logic_vector(0 downto 0)
);
end component;
begin
inst : stratixv_hssi_8g_rx_pcs_encrypted
generic map (
prot_mode => prot_mode,
tx_rx_parallel_loopback => tx_rx_parallel_loopback,
pma_dw => pma_dw,
pcs_bypass => pcs_bypass,
polarity_inversion => polarity_inversion,
wa_pd => wa_pd,
wa_pd_data => wa_pd_data,
wa_boundary_lock_ctrl => wa_boundary_lock_ctrl,
wa_pld_controlled => wa_pld_controlled,
wa_sync_sm_ctrl => wa_sync_sm_ctrl,
wa_rknumber_data => wa_rknumber_data,
wa_renumber_data => wa_renumber_data,
wa_rgnumber_data => wa_rgnumber_data,
wa_rosnumber_data => wa_rosnumber_data,
wa_kchar => wa_kchar,
wa_det_latency_sync_status_beh => wa_det_latency_sync_status_beh,
wa_clk_slip_spacing => wa_clk_slip_spacing,
wa_clk_slip_spacing_data => wa_clk_slip_spacing_data,
bit_reversal => bit_reversal,
symbol_swap => symbol_swap,
deskew_pattern => deskew_pattern,
deskew_prog_pattern_only => deskew_prog_pattern_only,
rate_match => rate_match,
eightb_tenb_decoder => eightb_tenb_decoder,
err_flags_sel => err_flags_sel,
polinv_8b10b_dec => polinv_8b10b_dec,
eightbtenb_decoder_output_sel => eightbtenb_decoder_output_sel,
invalid_code_flag_only => invalid_code_flag_only,
auto_error_replacement => auto_error_replacement,
pad_or_edb_error_replace => pad_or_edb_error_replace,
byte_deserializer => byte_deserializer,
byte_order => byte_order,
re_bo_on_wa => re_bo_on_wa,
bo_pattern => bo_pattern,
bo_pad => bo_pad,
phase_compensation_fifo => phase_compensation_fifo,
prbs_ver => prbs_ver,
cid_pattern => cid_pattern,
cid_pattern_len => cid_pattern_len,
bist_ver => bist_ver,
cdr_ctrl => cdr_ctrl,
cdr_ctrl_rxvalid_mask => cdr_ctrl_rxvalid_mask,
wait_cnt => wait_cnt,
mask_cnt => mask_cnt,
auto_deassert_pc_rst_cnt_data => auto_deassert_pc_rst_cnt_data,
auto_pc_en_cnt_data => auto_pc_en_cnt_data,
eidle_entry_sd => eidle_entry_sd,
eidle_entry_eios => eidle_entry_eios,
eidle_entry_iei => eidle_entry_iei,
rx_rcvd_clk => rx_rcvd_clk,
rx_clk1 => rx_clk1,
rx_clk2 => rx_clk2,
rx_rd_clk => rx_rd_clk,
dw_one_or_two_symbol_bo => dw_one_or_two_symbol_bo,
comp_fifo_rst_pld_ctrl => comp_fifo_rst_pld_ctrl,
bypass_pipeline_reg => bypass_pipeline_reg,
agg_block_sel => agg_block_sel,
test_bus_sel => test_bus_sel,
wa_rvnumber_data => wa_rvnumber_data,
ctrl_plane_bonding_compensation => ctrl_plane_bonding_compensation,
clock_gate_rx => clock_gate_rx,
prbs_ver_clr_flag => prbs_ver_clr_flag,
hip_mode => hip_mode,
ctrl_plane_bonding_distribution => ctrl_plane_bonding_distribution,
ctrl_plane_bonding_consumption => ctrl_plane_bonding_consumption,
pma_done_count => pma_done_count,
test_mode => test_mode,
bist_ver_clr_flag => bist_ver_clr_flag,
wa_disp_err_flag => wa_disp_err_flag,
wait_for_phfifo_cnt_data => wait_for_phfifo_cnt_data,
runlength_check => runlength_check,
test_bus_sel_val => test_bus_sel_val,
runlength_val => runlength_val,
force_signal_detect => force_signal_detect,
deskew => deskew,
rx_wr_clk => rx_wr_clk,
rx_clk_free_running => rx_clk_free_running,
rx_pcs_urst => rx_pcs_urst,
self_switch_dw_scaling => self_switch_dw_scaling,
pipe_if_enable => pipe_if_enable,
pc_fifo_rst_pld_ctrl => pc_fifo_rst_pld_ctrl,
auto_speed_nego_gen2 => auto_speed_nego_gen2,
auto_speed_nego_gen3 => auto_speed_nego_gen3,
ibm_invalid_code => ibm_invalid_code,
channel_number => channel_number,
rx_refclk => rx_refclk
)
port map (
hrdrst => hrdrst,
rxpcsrst => rxpcsrst,
rmfifouserrst => rmfifouserrst,
phfifouserrst => phfifouserrst,
scanmode => scanmode,
enablecommadetect => enablecommadetect,
a1a2size => a1a2size,
bitslip => bitslip,
rmfiforeadenable => rmfiforeadenable,
rmfifowriteenable => rmfifowriteenable,
pldrxclk => pldrxclk,
softresetrclk1 => softresetrclk1,
polinvrx => polinvrx,
bitreversalenable => bitreversalenable,
bytereversalenable => bytereversalenable,
rcvdclkpma => rcvdclkpma,
datain => datain,
sigdetfrompma => sigdetfrompma,
fiforstrdqd => fiforstrdqd,
endskwqd => endskwqd,
endskwrdptrs => endskwrdptrs,
alignstatus => alignstatus,
fiforstrdqdtoporbot => fiforstrdqdtoporbot,
endskwqdtoporbot => endskwqdtoporbot,
endskwrdptrstoporbot => endskwrdptrstoporbot,
alignstatustoporbot => alignstatustoporbot,
datafrinaggblock => datafrinaggblock,
ctrlfromaggblock => ctrlfromaggblock,
rxdatarstoporbot => rxdatarstoporbot,
rxcontrolrstoporbot => rxcontrolrstoporbot,
rcvdclk0pma => rcvdclk0pma,
parallelloopback => parallelloopback,
txpmaclk => txpmaclk,
byteorder => byteorder,
pxfifowrdisable => pxfifowrdisable,
pcfifordenable => pcfifordenable,
pmatestbus => pmatestbus,
encodertestbus => encodertestbus,
txctrltestbus => txctrltestbus,
phystatusinternal => phystatusinternal,
rxvalidinternal => rxvalidinternal,
rxstatusinternal => rxstatusinternal,
phystatuspcsgen3 => phystatuspcsgen3,
rxvalidpcsgen3 => rxvalidpcsgen3,
rxstatuspcsgen3 => rxstatuspcsgen3,
rxdatavalidpcsgen3 => rxdatavalidpcsgen3,
rxblkstartpcsgen3 => rxblkstartpcsgen3,
rxsynchdrpcsgen3 => rxsynchdrpcsgen3,
rxdatapcsgen3 => rxdatapcsgen3,
pipepowerdown => pipepowerdown,
rateswitchcontrol => rateswitchcontrol,
gen2ngen1 => gen2ngen1,
gen2ngen1bundle => gen2ngen1bundle,
eidleinfersel => eidleinfersel,
pipeloopbk => pipeloopbk,
pldltr => pldltr,
prbscidenable => prbscidenable,
txdiv2syncoutpipeup => txdiv2syncoutpipeup,
fifoselectoutpipeup => fifoselectoutpipeup,
txwrenableoutpipeup => txwrenableoutpipeup,
txrdenableoutpipeup => txrdenableoutpipeup,
txdiv2syncoutpipedown => txdiv2syncoutpipedown,
fifoselectoutpipedown => fifoselectoutpipedown,
txwrenableoutpipedown => txwrenableoutpipedown,
txrdenableoutpipedown => txrdenableoutpipedown,
alignstatussync0 => alignstatussync0,
rmfifordincomp0 => rmfifordincomp0,
cgcomprddall => cgcomprddall,
cgcompwrall => cgcompwrall,
delcondmet0 => delcondmet0,
fifoovr0 => fifoovr0,
latencycomp0 => latencycomp0,
insertincomplete0 => insertincomplete0,
alignstatussync0toporbot => alignstatussync0toporbot,
fifordincomp0toporbot => fifordincomp0toporbot,
cgcomprddalltoporbot => cgcomprddalltoporbot,
cgcompwralltoporbot => cgcompwralltoporbot,
delcondmet0toporbot => delcondmet0toporbot,
fifoovr0toporbot => fifoovr0toporbot,
latencycomp0toporbot => latencycomp0toporbot,
insertincomplete0toporbot => insertincomplete0toporbot,
alignstatussync => alignstatussync,
fifordoutcomp => fifordoutcomp,
cgcomprddout => cgcomprddout,
cgcompwrout => cgcompwrout,
delcondmetout => delcondmetout,
fifoovrout => fifoovrout,
latencycompout => latencycompout,
insertincompleteout => insertincompleteout,
dataout => dataout,
parallelrevloopback => parallelrevloopback,
clocktopld => clocktopld,
bisterr => bisterr,
clk2b => clk2b,
rcvdclkpmab => rcvdclkpmab,
syncstatus => syncstatus,
decoderdatavalid => decoderdatavalid,
decoderdata => decoderdata,
decoderctrl => decoderctrl,
runningdisparity => runningdisparity,
selftestdone => selftestdone,
selftesterr => selftesterr,
errdata => errdata,
errctrl => errctrl,
prbsdone => prbsdone,
prbserrlt => prbserrlt,
signaldetectout => signaldetectout,
aligndetsync => aligndetsync,
rdalign => rdalign,
bistdone => bistdone,
runlengthviolation => runlengthviolation,
rlvlt => rlvlt,
rmfifopartialfull => rmfifopartialfull,
rmfifofull => rmfifofull,
rmfifopartialempty => rmfifopartialempty,
rmfifoempty => rmfifoempty,
pcfifofull => pcfifofull,
pcfifoempty => pcfifoempty,
a1a2k1k2flag => a1a2k1k2flag,
byteordflag => byteordflag,
rxpipeclk => rxpipeclk,
channeltestbusout => channeltestbusout,
rxpipesoftreset => rxpipesoftreset,
phystatus => phystatus,
rxvalid => rxvalid,
rxstatus => rxstatus,
pipedata => pipedata,
rxdatavalid => rxdatavalid,
rxblkstart => rxblkstart,
rxsynchdr => rxsynchdr,
speedchange => speedchange,
eidledetected => eidledetected,
wordalignboundary => wordalignboundary,
rxclkslip => rxclkslip,
eidleexit => eidleexit,
earlyeios => earlyeios,
ltr => ltr,
pcswrapbackin => pcswrapbackin,
rxdivsyncinchnlup => rxdivsyncinchnlup,
rxdivsyncinchnldown => rxdivsyncinchnldown,
wrenableinchnlup => wrenableinchnlup,
wrenableinchnldown => wrenableinchnldown,
rdenableinchnlup => rdenableinchnlup,
rdenableinchnldown => rdenableinchnldown,
rxweinchnlup => rxweinchnlup,
rxweinchnldown => rxweinchnldown,
resetpcptrsinchnlup => resetpcptrsinchnlup,
resetpcptrsinchnldown => resetpcptrsinchnldown,
configselinchnlup => configselinchnlup,
configselinchnldown => configselinchnldown,
speedchangeinchnlup => speedchangeinchnlup,
speedchangeinchnldown => speedchangeinchnldown,
pcieswitch => pcieswitch,
rxdivsyncoutchnlup => rxdivsyncoutchnlup,
rxweoutchnlup => rxweoutchnlup,
wrenableoutchnlup => wrenableoutchnlup,
rdenableoutchnlup => rdenableoutchnlup,
resetpcptrsoutchnlup => resetpcptrsoutchnlup,
speedchangeoutchnlup => speedchangeoutchnlup,
configseloutchnlup => configseloutchnlup,
rxdivsyncoutchnldown => rxdivsyncoutchnldown,
rxweoutchnldown => rxweoutchnldown,
wrenableoutchnldown => wrenableoutchnldown,
rdenableoutchnldown => rdenableoutchnldown,
resetpcptrsoutchnldown => resetpcptrsoutchnldown,
speedchangeoutchnldown => speedchangeoutchnldown,
configseloutchnldown => configseloutchnldown,
resetpcptrsinchnluppipe => resetpcptrsinchnluppipe,
resetpcptrsinchnldownpipe => resetpcptrsinchnldownpipe,
speedchangeinchnluppipe => speedchangeinchnluppipe,
speedchangeinchnldownpipe => speedchangeinchnldownpipe,
disablepcfifobyteserdes => disablepcfifobyteserdes,
resetpcptrs => resetpcptrs,
rcvdclkagg => rcvdclkagg,
rcvdclkaggtoporbot => rcvdclkaggtoporbot,
dispcbytegen3 => dispcbytegen3,
refclkdig => refclkdig,
txfifordclkraw => txfifordclkraw,
resetpcptrsgen3 => resetpcptrsgen3,
syncdatain => syncdatain,
observablebyteserdesclock => observablebyteserdesclock
);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
entity stratixv_hssi_8g_tx_pcs is
generic (
prot_mode : string := "basic";
hip_mode : string := "dis_hip";
pma_dw : string := "eight_bit";
pcs_bypass : string := "dis_pcs_bypass";
phase_compensation_fifo : string := "low_latency";
tx_compliance_controlled_disparity : string := "dis_txcompliance";
force_kchar : string := "dis_force_kchar";
force_echar : string := "dis_force_echar";
byte_serializer : string := "dis_bs";
data_selection_8b10b_encoder_input : string := "normal_data_path";
eightb_tenb_disp_ctrl : string := "dis_disp_ctrl";
eightb_tenb_encoder : string := "dis_8b10b";
prbs_gen : string := "dis_prbs";
cid_pattern : string := "cid_pattern_0";
cid_pattern_len : bit_vector := B"00000000";
bist_gen : string := "dis_bist";
bit_reversal : string := "dis_bit_reversal";
symbol_swap : string := "dis_symbol_swap";
polarity_inversion : string := "dis_polinv";
tx_bitslip : string := "dis_tx_bitslip";
agg_block_sel : string := "same_smrt_pack";
revloop_back_rm : string := "dis_rev_loopback_rx_rm";
phfifo_write_clk_sel : string := "pld_tx_clk";
ctrl_plane_bonding_consumption : string := "individual";
bypass_pipeline_reg : string := "dis_bypass_pipeline";
ctrl_plane_bonding_distribution : string := "not_master_chnl_distr";
test_mode : string := "prbs";
clock_gate_tx : string := "dis_clk_gating";
self_switch_dw_scaling : string := "dis_self_switch_dw_scaling";
ctrl_plane_bonding_compensation : string := "dis_compensation";
refclk_b_clk_sel : string := "tx_pma_clock";
auto_speed_nego_gen2 : string := "dis_auto_speed_nego_g2";
auto_speed_nego_gen3 : string := "dis_auto_speed_nego_g3";
channel_number : string := "int"
);
port (
txpcsreset : in std_logic_vector(0 downto 0);
refclkdig : in std_logic_vector(0 downto 0);
scanmode : in std_logic_vector(0 downto 0);
datain : in std_logic_vector(43 downto 0);
coreclk : in std_logic_vector(0 downto 0);
invpol : in std_logic_vector(0 downto 0);
xgmdatain : in std_logic_vector(7 downto 0);
xgmctrl : in std_logic_vector(0 downto 0);
xgmdataintoporbottom : in std_logic_vector(7 downto 0);
xgmctrltoporbottom : in std_logic_vector(0 downto 0);
txpmalocalclk : in std_logic_vector(0 downto 0);
enrevparallellpbk : in std_logic_vector(0 downto 0);
revparallellpbkdata : in std_logic_vector(19 downto 0);
phfifowrenable : in std_logic_vector(0 downto 0);
phfiforddisable : in std_logic_vector(0 downto 0);
phfiforeset : in std_logic_vector(0 downto 0);
detectrxloopin : in std_logic_vector(0 downto 0);
powerdn : in std_logic_vector(1 downto 0);
pipeenrevparallellpbkin : in std_logic_vector(0 downto 0);
pipetxswing : in std_logic_vector(0 downto 0);
pipetxdeemph : in std_logic_vector(0 downto 0);
pipetxmargin : in std_logic_vector(2 downto 0);
rxpolarityin : in std_logic_vector(0 downto 0);
polinvrxin : in std_logic_vector(0 downto 0);
elecidleinfersel : in std_logic_vector(2 downto 0);
rateswitch : in std_logic_vector(0 downto 0);
rateswitchbundle : in std_logic_vector(0 downto 0);
prbscidenable : in std_logic_vector(0 downto 0);
bitslipboundaryselect : in std_logic_vector(4 downto 0);
phfifooverflow : out std_logic_vector(0 downto 0);
phfifounderflow : out std_logic_vector(0 downto 0);
clkout : out std_logic_vector(0 downto 0);
clkoutgen3 : out std_logic_vector(0 downto 0);
xgmdataout : out std_logic_vector(7 downto 0);
xgmctrlenable : out std_logic_vector(0 downto 0);
dataout : out std_logic_vector(19 downto 0);
rdenablesync : out std_logic_vector(0 downto 0);
refclkb : out std_logic_vector(0 downto 0);
parallelfdbkout : out std_logic_vector(19 downto 0);
txpipeclk : out std_logic_vector(0 downto 0);
encodertestbus : out std_logic_vector(9 downto 0);
txctrltestbus : out std_logic_vector(9 downto 0);
txpipesoftreset : out std_logic_vector(0 downto 0);
txpipeelectidle : out std_logic_vector(0 downto 0);
detectrxloopout : out std_logic_vector(0 downto 0);
pipepowerdownout : out std_logic_vector(1 downto 0);
pipeenrevparallellpbkout : out std_logic_vector(0 downto 0);
phfifotxswing : out std_logic_vector(0 downto 0);
phfifotxdeemph : out std_logic_vector(0 downto 0);
phfifotxmargin : out std_logic_vector(2 downto 0);
txdataouttogen3 : out std_logic_vector(31 downto 0);
txdatakouttogen3 : out std_logic_vector(3 downto 0);
txdatavalidouttogen3 : out std_logic_vector(3 downto 0);
txblkstartout : out std_logic_vector(3 downto 0);
txsynchdrout : out std_logic_vector(1 downto 0);
txcomplianceout : out std_logic_vector(0 downto 0);
txelecidleout : out std_logic_vector(0 downto 0);
rxpolarityout : out std_logic_vector(0 downto 0);
polinvrxout : out std_logic_vector(0 downto 0);
grayelecidleinferselout : out std_logic_vector(2 downto 0);
txdivsyncinchnlup : in std_logic_vector(1 downto 0);
txdivsyncinchnldown : in std_logic_vector(1 downto 0);
wrenableinchnlup : in std_logic_vector(0 downto 0);
wrenableinchnldown : in std_logic_vector(0 downto 0);
rdenableinchnlup : in std_logic_vector(0 downto 0);
rdenableinchnldown : in std_logic_vector(0 downto 0);
fifoselectinchnlup : in std_logic_vector(1 downto 0);
fifoselectinchnldown : in std_logic_vector(1 downto 0);
resetpcptrs : in std_logic_vector(0 downto 0);
resetpcptrsinchnlup : in std_logic_vector(0 downto 0);
resetpcptrsinchnldown : in std_logic_vector(0 downto 0);
dispcbyte : in std_logic_vector(0 downto 0);
txdivsyncoutchnlup : out std_logic_vector(1 downto 0);
txdivsyncoutchnldown : out std_logic_vector(1 downto 0);
rdenableoutchnlup : out std_logic_vector(0 downto 0);
rdenableoutchnldown : out std_logic_vector(0 downto 0);
wrenableoutchnlup : out std_logic_vector(0 downto 0);
wrenableoutchnldown : out std_logic_vector(0 downto 0);
fifoselectoutchnlup : out std_logic_vector(1 downto 0);
fifoselectoutchnldown : out std_logic_vector(1 downto 0);
txfifordclkraw : out std_logic_vector(0 downto 0);
syncdatain : out std_logic_vector(0 downto 0);
observablebyteserdesclock : out std_logic_vector(0 downto 0)
);
end stratixv_hssi_8g_tx_pcs;
architecture behavior of stratixv_hssi_8g_tx_pcs is
component stratixv_hssi_8g_tx_pcs_encrypted
generic (
prot_mode : string := "basic";
hip_mode : string := "dis_hip";
pma_dw : string := "eight_bit";
pcs_bypass : string := "dis_pcs_bypass";
phase_compensation_fifo : string := "low_latency";
tx_compliance_controlled_disparity : string := "dis_txcompliance";
force_kchar : string := "dis_force_kchar";
force_echar : string := "dis_force_echar";
byte_serializer : string := "dis_bs";
data_selection_8b10b_encoder_input : string := "normal_data_path";
eightb_tenb_disp_ctrl : string := "dis_disp_ctrl";
eightb_tenb_encoder : string := "dis_8b10b";
prbs_gen : string := "dis_prbs";
cid_pattern : string := "cid_pattern_0";
cid_pattern_len : bit_vector := B"00000000";
bist_gen : string := "dis_bist";
bit_reversal : string := "dis_bit_reversal";
symbol_swap : string := "dis_symbol_swap";
polarity_inversion : string := "dis_polinv";
tx_bitslip : string := "dis_tx_bitslip";
agg_block_sel : string := "same_smrt_pack";
revloop_back_rm : string := "dis_rev_loopback_rx_rm";
phfifo_write_clk_sel : string := "pld_tx_clk";
ctrl_plane_bonding_consumption : string := "individual";
bypass_pipeline_reg : string := "dis_bypass_pipeline";
ctrl_plane_bonding_distribution : string := "not_master_chnl_distr";
test_mode : string := "prbs";
clock_gate_tx : string := "dis_clk_gating";
self_switch_dw_scaling : string := "dis_self_switch_dw_scaling";
ctrl_plane_bonding_compensation : string := "dis_compensation";
refclk_b_clk_sel : string := "tx_pma_clock";
auto_speed_nego_gen2 : string := "dis_auto_speed_nego_g2";
auto_speed_nego_gen3 : string := "dis_auto_speed_nego_g3";
channel_number : string := "int"
);
port (
txpcsreset : in std_logic_vector(0 downto 0);
refclkdig : in std_logic_vector(0 downto 0);
scanmode : in std_logic_vector(0 downto 0);
datain : in std_logic_vector(43 downto 0);
coreclk : in std_logic_vector(0 downto 0);
invpol : in std_logic_vector(0 downto 0);
xgmdatain : in std_logic_vector(7 downto 0);
xgmctrl : in std_logic_vector(0 downto 0);
xgmdataintoporbottom : in std_logic_vector(7 downto 0);
xgmctrltoporbottom : in std_logic_vector(0 downto 0);
txpmalocalclk : in std_logic_vector(0 downto 0);
enrevparallellpbk : in std_logic_vector(0 downto 0);
revparallellpbkdata : in std_logic_vector(19 downto 0);
phfifowrenable : in std_logic_vector(0 downto 0);
phfiforddisable : in std_logic_vector(0 downto 0);
phfiforeset : in std_logic_vector(0 downto 0);
detectrxloopin : in std_logic_vector(0 downto 0);
powerdn : in std_logic_vector(1 downto 0);
pipeenrevparallellpbkin : in std_logic_vector(0 downto 0);
pipetxswing : in std_logic_vector(0 downto 0);
pipetxdeemph : in std_logic_vector(0 downto 0);
pipetxmargin : in std_logic_vector(2 downto 0);
rxpolarityin : in std_logic_vector(0 downto 0);
polinvrxin : in std_logic_vector(0 downto 0);
elecidleinfersel : in std_logic_vector(2 downto 0);
rateswitch : in std_logic_vector(0 downto 0);
rateswitchbundle : in std_logic_vector(0 downto 0);
prbscidenable : in std_logic_vector(0 downto 0);
bitslipboundaryselect : in std_logic_vector(4 downto 0);
phfifooverflow : out std_logic_vector(0 downto 0);
phfifounderflow : out std_logic_vector(0 downto 0);
clkout : out std_logic_vector(0 downto 0);
clkoutgen3 : out std_logic_vector(0 downto 0);
xgmdataout : out std_logic_vector(7 downto 0);
xgmctrlenable : out std_logic_vector(0 downto 0);
dataout : out std_logic_vector(19 downto 0);
rdenablesync : out std_logic_vector(0 downto 0);
refclkb : out std_logic_vector(0 downto 0);
parallelfdbkout : out std_logic_vector(19 downto 0);
txpipeclk : out std_logic_vector(0 downto 0);
encodertestbus : out std_logic_vector(9 downto 0);
txctrltestbus : out std_logic_vector(9 downto 0);
txpipesoftreset : out std_logic_vector(0 downto 0);
txpipeelectidle : out std_logic_vector(0 downto 0);
detectrxloopout : out std_logic_vector(0 downto 0);
pipepowerdownout : out std_logic_vector(1 downto 0);
pipeenrevparallellpbkout : out std_logic_vector(0 downto 0);
phfifotxswing : out std_logic_vector(0 downto 0);
phfifotxdeemph : out std_logic_vector(0 downto 0);
phfifotxmargin : out std_logic_vector(2 downto 0);
txdataouttogen3 : out std_logic_vector(31 downto 0);
txdatakouttogen3 : out std_logic_vector(3 downto 0);
txdatavalidouttogen3 : out std_logic_vector(3 downto 0);
txblkstartout : out std_logic_vector(3 downto 0);
txsynchdrout : out std_logic_vector(1 downto 0);
txcomplianceout : out std_logic_vector(0 downto 0);
txelecidleout : out std_logic_vector(0 downto 0);
rxpolarityout : out std_logic_vector(0 downto 0);
polinvrxout : out std_logic_vector(0 downto 0);
grayelecidleinferselout : out std_logic_vector(2 downto 0);
txdivsyncinchnlup : in std_logic_vector(1 downto 0);
txdivsyncinchnldown : in std_logic_vector(1 downto 0);
wrenableinchnlup : in std_logic_vector(0 downto 0);
wrenableinchnldown : in std_logic_vector(0 downto 0);
rdenableinchnlup : in std_logic_vector(0 downto 0);
rdenableinchnldown : in std_logic_vector(0 downto 0);
fifoselectinchnlup : in std_logic_vector(1 downto 0);
fifoselectinchnldown : in std_logic_vector(1 downto 0);
resetpcptrs : in std_logic_vector(0 downto 0);
resetpcptrsinchnlup : in std_logic_vector(0 downto 0);
resetpcptrsinchnldown : in std_logic_vector(0 downto 0);
dispcbyte : in std_logic_vector(0 downto 0);
txdivsyncoutchnlup : out std_logic_vector(1 downto 0);
txdivsyncoutchnldown : out std_logic_vector(1 downto 0);
rdenableoutchnlup : out std_logic_vector(0 downto 0);
rdenableoutchnldown : out std_logic_vector(0 downto 0);
wrenableoutchnlup : out std_logic_vector(0 downto 0);
wrenableoutchnldown : out std_logic_vector(0 downto 0);
fifoselectoutchnlup : out std_logic_vector(1 downto 0);
fifoselectoutchnldown : out std_logic_vector(1 downto 0);
txfifordclkraw : out std_logic_vector(0 downto 0);
syncdatain : out std_logic_vector(0 downto 0);
observablebyteserdesclock : out std_logic_vector(0 downto 0)
);
end component;
begin
inst : stratixv_hssi_8g_tx_pcs_encrypted
generic map (
prot_mode => prot_mode,
hip_mode => hip_mode,
pma_dw => pma_dw,
pcs_bypass => pcs_bypass,
phase_compensation_fifo => phase_compensation_fifo,
tx_compliance_controlled_disparity => tx_compliance_controlled_disparity,
force_kchar => force_kchar,
force_echar => force_echar,
byte_serializer => byte_serializer,
data_selection_8b10b_encoder_input => data_selection_8b10b_encoder_input,
eightb_tenb_disp_ctrl => eightb_tenb_disp_ctrl,
eightb_tenb_encoder => eightb_tenb_encoder,
prbs_gen => prbs_gen,
cid_pattern => cid_pattern,
cid_pattern_len => cid_pattern_len,
bist_gen => bist_gen,
bit_reversal => bit_reversal,
symbol_swap => symbol_swap,
polarity_inversion => polarity_inversion,
tx_bitslip => tx_bitslip,
agg_block_sel => agg_block_sel,
revloop_back_rm => revloop_back_rm,
phfifo_write_clk_sel => phfifo_write_clk_sel,
ctrl_plane_bonding_consumption => ctrl_plane_bonding_consumption,
bypass_pipeline_reg => bypass_pipeline_reg,
ctrl_plane_bonding_distribution => ctrl_plane_bonding_distribution,
test_mode => test_mode,
clock_gate_tx => clock_gate_tx,
self_switch_dw_scaling => self_switch_dw_scaling,
ctrl_plane_bonding_compensation => ctrl_plane_bonding_compensation,
refclk_b_clk_sel => refclk_b_clk_sel,
auto_speed_nego_gen2 => auto_speed_nego_gen2,
auto_speed_nego_gen3 => auto_speed_nego_gen3,
channel_number => channel_number
)
port map (
txpcsreset => txpcsreset,
refclkdig => refclkdig,
scanmode => scanmode,
datain => datain,
coreclk => coreclk,
invpol => invpol,
xgmdatain => xgmdatain,
xgmctrl => xgmctrl,
xgmdataintoporbottom => xgmdataintoporbottom,
xgmctrltoporbottom => xgmctrltoporbottom,
txpmalocalclk => txpmalocalclk,
enrevparallellpbk => enrevparallellpbk,
revparallellpbkdata => revparallellpbkdata,
phfifowrenable => phfifowrenable,
phfiforddisable => phfiforddisable,
phfiforeset => phfiforeset,
detectrxloopin => detectrxloopin,
powerdn => powerdn,
pipeenrevparallellpbkin => pipeenrevparallellpbkin,
pipetxswing => pipetxswing,
pipetxdeemph => pipetxdeemph,
pipetxmargin => pipetxmargin,
rxpolarityin => rxpolarityin,
polinvrxin => polinvrxin,
elecidleinfersel => elecidleinfersel,
rateswitch => rateswitch,
rateswitchbundle => rateswitchbundle,
prbscidenable => prbscidenable,
bitslipboundaryselect => bitslipboundaryselect,
phfifooverflow => phfifooverflow,
phfifounderflow => phfifounderflow,
clkout => clkout,
clkoutgen3 => clkoutgen3,
xgmdataout => xgmdataout,
xgmctrlenable => xgmctrlenable,
dataout => dataout,
rdenablesync => rdenablesync,
refclkb => refclkb,
parallelfdbkout => parallelfdbkout,
txpipeclk => txpipeclk,
encodertestbus => encodertestbus,
txctrltestbus => txctrltestbus,
txpipesoftreset => txpipesoftreset,
txpipeelectidle => txpipeelectidle,
detectrxloopout => detectrxloopout,
pipepowerdownout => pipepowerdownout,
pipeenrevparallellpbkout => pipeenrevparallellpbkout,
phfifotxswing => phfifotxswing,
phfifotxdeemph => phfifotxdeemph,
phfifotxmargin => phfifotxmargin,
txdataouttogen3 => txdataouttogen3,
txdatakouttogen3 => txdatakouttogen3,
txdatavalidouttogen3 => txdatavalidouttogen3,
txblkstartout => txblkstartout,
txsynchdrout => txsynchdrout,
txcomplianceout => txcomplianceout,
txelecidleout => txelecidleout,
rxpolarityout => rxpolarityout,
polinvrxout => polinvrxout,
grayelecidleinferselout => grayelecidleinferselout,
txdivsyncinchnlup => txdivsyncinchnlup,
txdivsyncinchnldown => txdivsyncinchnldown,
wrenableinchnlup => wrenableinchnlup,
wrenableinchnldown => wrenableinchnldown,
rdenableinchnlup => rdenableinchnlup,
rdenableinchnldown => rdenableinchnldown,
fifoselectinchnlup => fifoselectinchnlup,
fifoselectinchnldown => fifoselectinchnldown,
resetpcptrs => resetpcptrs,
resetpcptrsinchnlup => resetpcptrsinchnlup,
resetpcptrsinchnldown => resetpcptrsinchnldown,
dispcbyte => dispcbyte,
txdivsyncoutchnlup => txdivsyncoutchnlup,
txdivsyncoutchnldown => txdivsyncoutchnldown,
rdenableoutchnlup => rdenableoutchnlup,
rdenableoutchnldown => rdenableoutchnldown,
wrenableoutchnlup => wrenableoutchnlup,
wrenableoutchnldown => wrenableoutchnldown,
fifoselectoutchnlup => fifoselectoutchnlup,
fifoselectoutchnldown => fifoselectoutchnldown,
txfifordclkraw => txfifordclkraw,
syncdatain => syncdatain,
observablebyteserdesclock => observablebyteserdesclock
);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
entity stratixv_hssi_pipe_gen1_2 is
generic (
prot_mode : string := "pipe_g1";
hip_mode : string := "dis_hip";
tx_pipe_enable : string := "dis_pipe_tx";
rx_pipe_enable : string := "dis_pipe_rx";
pipe_byte_de_serializer_en : string := "dont_care_bds";
txswing : string := "dis_txswing";
rxdetect_bypass : string := "dis_rxdetect_bypass";
error_replace_pad : string := "replace_edb";
ind_error_reporting : string := "dis_ind_error_reporting";
phystatus_rst_toggle : string := "dis_phystatus_rst_toggle";
elecidle_delay : string := "elec_idle_delay";
elec_idle_delay_val : bit_vector := B"000";
phy_status_delay : string := "phystatus_delay";
phystatus_delay_val : bit_vector := B"000";
ctrl_plane_bonding_consumption : string := "individual";
byte_deserializer : string := "dis_bds"
);
port (
pipetxclk : in std_logic_vector(0 downto 0);
piperxclk : in std_logic_vector(0 downto 0);
refclkb : in std_logic_vector(0 downto 0);
txpipereset : in std_logic_vector(0 downto 0);
rxpipereset : in std_logic_vector(0 downto 0);
refclkbreset : in std_logic_vector(0 downto 0);
rrdwidthrx : in std_logic_vector(0 downto 0);
txdetectrxloopback : in std_logic_vector(0 downto 0);
txelecidlein : in std_logic_vector(0 downto 0);
powerdown : in std_logic_vector(1 downto 0);
txdeemph : in std_logic_vector(0 downto 0);
txmargin : in std_logic_vector(2 downto 0);
txswingport : in std_logic_vector(0 downto 0);
txdch : in std_logic_vector(43 downto 0);
rxpolarity : in std_logic_vector(0 downto 0);
sigdetni : in std_logic_vector(0 downto 0);
rxvalid : out std_logic_vector(0 downto 0);
rxelecidle : out std_logic_vector(0 downto 0);
rxstatus : out std_logic_vector(2 downto 0);
rxdch : out std_logic_vector(63 downto 0);
phystatus : out std_logic_vector(0 downto 0);
revloopback : in std_logic_vector(0 downto 0);
polinvrx : in std_logic_vector(0 downto 0);
txd : out std_logic_vector(43 downto 0);
revloopbk : out std_logic_vector(0 downto 0);
revloopbkpcsgen3 : in std_logic_vector(0 downto 0);
rxelectricalidlepcsgen3 : in std_logic_vector(0 downto 0);
txelecidlecomp : in std_logic_vector(0 downto 0);
rindvrx : in std_logic_vector(0 downto 0);
rmasterrx : in std_logic_vector(1 downto 0);
speedchange : in std_logic_vector(0 downto 0);
speedchangechnlup : in std_logic_vector(0 downto 0);
speedchangechnldown : in std_logic_vector(0 downto 0);
rxd : in std_logic_vector(63 downto 0);
txelecidleout : out std_logic_vector(0 downto 0);
txdetectrx : out std_logic_vector(0 downto 0);
powerstate : out std_logic_vector(3 downto 0);
rxfound : in std_logic_vector(0 downto 0);
rxdetectvalid : in std_logic_vector(0 downto 0);
rxelectricalidle : in std_logic_vector(0 downto 0);
powerstatetransitiondone : in std_logic_vector(0 downto 0);
powerstatetransitiondoneena : in std_logic_vector(0 downto 0);
txdeemphint : out std_logic_vector(0 downto 0);
txmarginint : out std_logic_vector(2 downto 0);
txswingint : out std_logic_vector(0 downto 0);
rxelectricalidleout : out std_logic_vector(0 downto 0);
rxpolaritypcsgen3 : in std_logic_vector(0 downto 0);
polinvrxint : out std_logic_vector(0 downto 0);
speedchangeout : out std_logic_vector(0 downto 0)
);
end stratixv_hssi_pipe_gen1_2;
architecture behavior of stratixv_hssi_pipe_gen1_2 is
component stratixv_hssi_pipe_gen1_2_encrypted
generic (
prot_mode : string := "pipe_g1";
hip_mode : string := "dis_hip";
tx_pipe_enable : string := "dis_pipe_tx";
rx_pipe_enable : string := "dis_pipe_rx";
pipe_byte_de_serializer_en : string := "dont_care_bds";
txswing : string := "dis_txswing";
rxdetect_bypass : string := "dis_rxdetect_bypass";
error_replace_pad : string := "replace_edb";
ind_error_reporting : string := "dis_ind_error_reporting";
phystatus_rst_toggle : string := "dis_phystatus_rst_toggle";
elecidle_delay : string := "elec_idle_delay";
elec_idle_delay_val : bit_vector := B"000";
phy_status_delay : string := "phystatus_delay";
phystatus_delay_val : bit_vector := B"000";
ctrl_plane_bonding_consumption : string := "individual";
byte_deserializer : string := "dis_bds"
);
port (
pipetxclk : in std_logic_vector(0 downto 0);
piperxclk : in std_logic_vector(0 downto 0);
refclkb : in std_logic_vector(0 downto 0);
txpipereset : in std_logic_vector(0 downto 0);
rxpipereset : in std_logic_vector(0 downto 0);
refclkbreset : in std_logic_vector(0 downto 0);
rrdwidthrx : in std_logic_vector(0 downto 0);
txdetectrxloopback : in std_logic_vector(0 downto 0);
txelecidlein : in std_logic_vector(0 downto 0);
powerdown : in std_logic_vector(1 downto 0);
txdeemph : in std_logic_vector(0 downto 0);
txmargin : in std_logic_vector(2 downto 0);
txswingport : in std_logic_vector(0 downto 0);
txdch : in std_logic_vector(43 downto 0);
rxpolarity : in std_logic_vector(0 downto 0);
sigdetni : in std_logic_vector(0 downto 0);
rxvalid : out std_logic_vector(0 downto 0);
rxelecidle : out std_logic_vector(0 downto 0);
rxstatus : out std_logic_vector(2 downto 0);
rxdch : out std_logic_vector(63 downto 0);
phystatus : out std_logic_vector(0 downto 0);
revloopback : in std_logic_vector(0 downto 0);
polinvrx : in std_logic_vector(0 downto 0);
txd : out std_logic_vector(43 downto 0);
revloopbk : out std_logic_vector(0 downto 0);
revloopbkpcsgen3 : in std_logic_vector(0 downto 0);
rxelectricalidlepcsgen3 : in std_logic_vector(0 downto 0);
txelecidlecomp : in std_logic_vector(0 downto 0);
rindvrx : in std_logic_vector(0 downto 0);
rmasterrx : in std_logic_vector(1 downto 0);
speedchange : in std_logic_vector(0 downto 0);
speedchangechnlup : in std_logic_vector(0 downto 0);
speedchangechnldown : in std_logic_vector(0 downto 0);
rxd : in std_logic_vector(63 downto 0);
txelecidleout : out std_logic_vector(0 downto 0);
txdetectrx : out std_logic_vector(0 downto 0);
powerstate : out std_logic_vector(3 downto 0);
rxfound : in std_logic_vector(0 downto 0);
rxdetectvalid : in std_logic_vector(0 downto 0);
rxelectricalidle : in std_logic_vector(0 downto 0);
powerstatetransitiondone : in std_logic_vector(0 downto 0);
powerstatetransitiondoneena : in std_logic_vector(0 downto 0);
txdeemphint : out std_logic_vector(0 downto 0);
txmarginint : out std_logic_vector(2 downto 0);
txswingint : out std_logic_vector(0 downto 0);
rxelectricalidleout : out std_logic_vector(0 downto 0);
rxpolaritypcsgen3 : in std_logic_vector(0 downto 0);
polinvrxint : out std_logic_vector(0 downto 0);
speedchangeout : out std_logic_vector(0 downto 0)
);
end component;
begin
inst : stratixv_hssi_pipe_gen1_2_encrypted
generic map (
prot_mode => prot_mode,
hip_mode => hip_mode,
tx_pipe_enable => tx_pipe_enable,
rx_pipe_enable => rx_pipe_enable,
pipe_byte_de_serializer_en => pipe_byte_de_serializer_en,
txswing => txswing,
rxdetect_bypass => rxdetect_bypass,
error_replace_pad => error_replace_pad,
ind_error_reporting => ind_error_reporting,
phystatus_rst_toggle => phystatus_rst_toggle,
elecidle_delay => elecidle_delay,
elec_idle_delay_val => elec_idle_delay_val,
phy_status_delay => phy_status_delay,
phystatus_delay_val => phystatus_delay_val,
ctrl_plane_bonding_consumption => ctrl_plane_bonding_consumption,
byte_deserializer => byte_deserializer
)
port map (
pipetxclk => pipetxclk,
piperxclk => piperxclk,
refclkb => refclkb,
txpipereset => txpipereset,
rxpipereset => rxpipereset,
refclkbreset => refclkbreset,
rrdwidthrx => rrdwidthrx,
txdetectrxloopback => txdetectrxloopback,
txelecidlein => txelecidlein,
powerdown => powerdown,
txdeemph => txdeemph,
txmargin => txmargin,
txswingport => txswingport,
txdch => txdch,
rxpolarity => rxpolarity,
sigdetni => sigdetni,
rxvalid => rxvalid,
rxelecidle => rxelecidle,
rxstatus => rxstatus,
rxdch => rxdch,
phystatus => phystatus,
revloopback => revloopback,
polinvrx => polinvrx,
txd => txd,
revloopbk => revloopbk,
revloopbkpcsgen3 => revloopbkpcsgen3,
rxelectricalidlepcsgen3 => rxelectricalidlepcsgen3,
txelecidlecomp => txelecidlecomp,
rindvrx => rindvrx,
rmasterrx => rmasterrx,
speedchange => speedchange,
speedchangechnlup => speedchangechnlup,
speedchangechnldown => speedchangechnldown,
rxd => rxd,
txelecidleout => txelecidleout,
txdetectrx => txdetectrx,
powerstate => powerstate,
rxfound => rxfound,
rxdetectvalid => rxdetectvalid,
rxelectricalidle => rxelectricalidle,
powerstatetransitiondone => powerstatetransitiondone,
powerstatetransitiondoneena => powerstatetransitiondoneena,
txdeemphint => txdeemphint,
txmarginint => txmarginint,
txswingint => txswingint,
rxelectricalidleout => rxelectricalidleout,
rxpolaritypcsgen3 => rxpolaritypcsgen3,
polinvrxint => polinvrxint,
speedchangeout => speedchangeout
);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
entity stratixv_hssi_pipe_gen3 is
generic (
mode : string := "pipe_g1";
ctrl_plane_bonding : string := "individual";
pipe_clk_sel : string := "func_clk";
rate_match_pad_insertion : string := "dis_rm_fifo_pad_ins";
ind_error_reporting : string := "dis_ind_error_reporting";
phystatus_rst_toggle_g3 : string := "dis_phystatus_rst_toggle_g3";
phystatus_rst_toggle_g12 : string := "dis_phystatus_rst_toggle";
cdr_control : string := "en_cdr_ctrl";
cid_enable : string := "en_cid_mode";
parity_chk_ts1 : string := "en_ts1_parity_chk";
rxvalid_mask : string := "rxvalid_mask_en";
ph_fifo_reg_mode : string := "phfifo_reg_mode_dis";
test_mode_timers : string := "dis_test_mode_timers";
inf_ei_enable : string := "dis_inf_ei";
spd_chnge_g2_sel : string := "false";
cp_up_mstr : string := "false";
cp_dwn_mstr : string := "false";
cp_cons_sel : string := "cp_cons_default";
elecidle_delay_g12_data : bit_vector := B"000";
elecidle_delay_g12 : string := "elecidle_delay_g12";
elecidle_delay_g3_data : bit_vector := B"000";
elecidle_delay_g3 : string := "elecidle_delay_g3";
phy_status_delay_g12_data : bit_vector := B"000";
phy_status_delay_g12 : string := "phy_status_delay_g12";
phy_status_delay_g3_data : bit_vector := B"000";
phy_status_delay_g3 : string := "phy_status_delay_g3";
sigdet_wait_counter_data : bit_vector := B"00000000";
sigdet_wait_counter : string := "sigdet_wait_counter";
data_mask_count_val : bit_vector := B"0000000000";
data_mask_count : string := "data_mask_count";
pma_done_counter_data : bit_vector := B"000000000000000000";
pma_done_counter : string := "pma_done_count";
pc_en_counter_data : bit_vector := B"00000";
pc_en_counter : string := "pc_en_count";
pc_rst_counter_data : bit_vector := B"0000";
pc_rst_counter : string := "pc_rst_count";
phfifo_flush_wait_data : bit_vector := B"000000";
phfifo_flush_wait : string := "phfifo_flush_wait";
asn_clk_enable : string := "false";
free_run_clk_enable : string := "true";
asn_enable : string := "dis_asn"
);
port (
rcvdclk : in std_logic_vector(0 downto 0);
txpmaclk : in std_logic_vector(0 downto 0);
pcsdigclk : in std_logic_vector(0 downto 0);
pllfixedclk : in std_logic_vector(0 downto 0);
rtxgen3capen : in std_logic_vector(0 downto 0);
rrxgen3capen : in std_logic_vector(0 downto 0);
rtxdigclksel : in std_logic_vector(0 downto 0);
rrxdigclksel : in std_logic_vector(0 downto 0);
rxrstn : in std_logic_vector(0 downto 0);
txrstn : in std_logic_vector(0 downto 0);
scanmoden : in std_logic_vector(0 downto 0);
pldasyncstatus : out std_logic_vector(5 downto 0);
testout : out std_logic_vector(19 downto 0);
gen3datasel : out std_logic_vector(0 downto 0);
gen3clksel : out std_logic_vector(0 downto 0);
pcsrst : out std_logic_vector(0 downto 0);
dispcbyte : out std_logic_vector(0 downto 0);
resetpcprts : out std_logic_vector(0 downto 0);
shutdownclk : out std_logic_vector(0 downto 0);
txdata : in std_logic_vector(31 downto 0);
txdatak : in std_logic_vector(3 downto 0);
txdataskip : in std_logic_vector(0 downto 0);
txsynchdr : in std_logic_vector(1 downto 0);
txblkstart : in std_logic_vector(0 downto 0);
txelecidle : in std_logic_vector(0 downto 0);
txdetectrxloopback : in std_logic_vector(0 downto 0);
txcompliance : in std_logic_vector(0 downto 0);
rxpolarity : in std_logic_vector(0 downto 0);
powerdown : in std_logic_vector(1 downto 0);
rate : in std_logic_vector(1 downto 0);
txmargin : in std_logic_vector(2 downto 0);
txdeemph : in std_logic_vector(0 downto 0);
txswing : in std_logic_vector(0 downto 0);
eidleinfersel : in std_logic_vector(2 downto 0);
currentcoeff : in std_logic_vector(17 downto 0);
currentrxpreset : in std_logic_vector(2 downto 0);
rxupdatefc : in std_logic_vector(0 downto 0);
rxdataskip : out std_logic_vector(3 downto 0);
rxsynchdr : out std_logic_vector(1 downto 0);
rxblkstart : out std_logic_vector(3 downto 0);
rxvalid : out std_logic_vector(0 downto 0);
phystatus : out std_logic_vector(0 downto 0);
rxelecidle : out std_logic_vector(0 downto 0);
rxstatus : out std_logic_vector(2 downto 0);
rxdataint : in std_logic_vector(31 downto 0);
rxdatakint : in std_logic_vector(3 downto 0);
rxdataskipint : in std_logic_vector(0 downto 0);
rxsynchdrint : in std_logic_vector(1 downto 0);
rxblkstartint : in std_logic_vector(0 downto 0);
txdataint : out std_logic_vector(31 downto 0);
txdatakint : out std_logic_vector(3 downto 0);
txdataskipint : out std_logic_vector(0 downto 0);
txsynchdrint : out std_logic_vector(1 downto 0);
txblkstartint : out std_logic_vector(0 downto 0);
testinfei : out std_logic_vector(18 downto 0);
eidetint : in std_logic_vector(0 downto 0);
eipartialdetint : in std_logic_vector(0 downto 0);
idetint : in std_logic_vector(0 downto 0);
blkalgndint : in std_logic_vector(0 downto 0);
clkcompinsertint : in std_logic_vector(0 downto 0);
clkcompdeleteint : in std_logic_vector(0 downto 0);
clkcompoverflint : in std_logic_vector(0 downto 0);
clkcompundflint : in std_logic_vector(0 downto 0);
errdecodeint : in std_logic_vector(0 downto 0);
rcvlfsrchkint : in std_logic_vector(0 downto 0);
errencodeint : in std_logic_vector(0 downto 0);
rxpolarityint : out std_logic_vector(0 downto 0);
revlpbkint : out std_logic_vector(0 downto 0);
inferredrxvalidint : out std_logic_vector(0 downto 0);
rxd8gpcsin : in std_logic_vector(63 downto 0);
rxelecidle8gpcsin : in std_logic_vector(0 downto 0);
pldltr : in std_logic_vector(0 downto 0);
rxd8gpcsout : out std_logic_vector(63 downto 0);
revlpbk8gpcsout : out std_logic_vector(0 downto 0);
pmarxdetectvalid : in std_logic_vector(0 downto 0);
pmarxfound : in std_logic_vector(0 downto 0);
pmasignaldet : in std_logic_vector(0 downto 0);
pmapcieswdone : in std_logic_vector(1 downto 0);
pmapcieswitch : out std_logic_vector(1 downto 0);
pmatxmargin : out std_logic_vector(2 downto 0);
pmatxdeemph : out std_logic_vector(0 downto 0);
pmatxswing : out std_logic_vector(0 downto 0);
pmacurrentcoeff : out std_logic_vector(17 downto 0);
pmacurrentrxpreset : out std_logic_vector(2 downto 0);
pmatxelecidle : out std_logic_vector(0 downto 0);
pmatxdetectrx : out std_logic_vector(0 downto 0);
ppmeidleexit : out std_logic_vector(0 downto 0);
pmaltr : out std_logic_vector(0 downto 0);
pmaearlyeios : out std_logic_vector(0 downto 0);
pmarxdetpd : out std_logic_vector(0 downto 0);
bundlingindown : in std_logic_vector(9 downto 0);
bundlingoutdown : out std_logic_vector(9 downto 0);
rxpolarity8gpcsout : out std_logic_vector(0 downto 0);
speedchangeg2 : in std_logic_vector(0 downto 0);
bundlingoutup : out std_logic_vector(9 downto 0);
bundlinginup : in std_logic_vector(9 downto 0);
masktxpll : out std_logic_vector(0 downto 0)
);
end stratixv_hssi_pipe_gen3;
architecture behavior of stratixv_hssi_pipe_gen3 is
component stratixv_hssi_pipe_gen3_encrypted
generic (
mode : string := "pipe_g1";
ctrl_plane_bonding : string := "individual";
pipe_clk_sel : string := "func_clk";
rate_match_pad_insertion : string := "dis_rm_fifo_pad_ins";
ind_error_reporting : string := "dis_ind_error_reporting";
phystatus_rst_toggle_g3 : string := "dis_phystatus_rst_toggle_g3";
phystatus_rst_toggle_g12 : string := "dis_phystatus_rst_toggle";
cdr_control : string := "en_cdr_ctrl";
cid_enable : string := "en_cid_mode";
parity_chk_ts1 : string := "en_ts1_parity_chk";
rxvalid_mask : string := "rxvalid_mask_en";
ph_fifo_reg_mode : string := "phfifo_reg_mode_dis";
test_mode_timers : string := "dis_test_mode_timers";
inf_ei_enable : string := "dis_inf_ei";
spd_chnge_g2_sel : string := "false";
cp_up_mstr : string := "false";
cp_dwn_mstr : string := "false";
cp_cons_sel : string := "cp_cons_default";
elecidle_delay_g12_data : bit_vector := B"000";
elecidle_delay_g12 : string := "elecidle_delay_g12";
elecidle_delay_g3_data : bit_vector := B"000";
elecidle_delay_g3 : string := "elecidle_delay_g3";
phy_status_delay_g12_data : bit_vector := B"000";
phy_status_delay_g12 : string := "phy_status_delay_g12";
phy_status_delay_g3_data : bit_vector := B"000";
phy_status_delay_g3 : string := "phy_status_delay_g3";
sigdet_wait_counter_data : bit_vector := B"00000000";
sigdet_wait_counter : string := "sigdet_wait_counter";
data_mask_count_val : bit_vector := B"0000000000";
data_mask_count : string := "data_mask_count";
pma_done_counter_data : bit_vector := B"000000000000000000";
pma_done_counter : string := "pma_done_count";
pc_en_counter_data : bit_vector := B"00000";
pc_en_counter : string := "pc_en_count";
pc_rst_counter_data : bit_vector := B"0000";
pc_rst_counter : string := "pc_rst_count";
phfifo_flush_wait_data : bit_vector := B"000000";
phfifo_flush_wait : string := "phfifo_flush_wait";
asn_clk_enable : string := "false";
free_run_clk_enable : string := "true";
asn_enable : string := "dis_asn"
);
port (
rcvdclk : in std_logic_vector(0 downto 0);
txpmaclk : in std_logic_vector(0 downto 0);
pcsdigclk : in std_logic_vector(0 downto 0);
pllfixedclk : in std_logic_vector(0 downto 0);
rtxgen3capen : in std_logic_vector(0 downto 0);
rrxgen3capen : in std_logic_vector(0 downto 0);
rtxdigclksel : in std_logic_vector(0 downto 0);
rrxdigclksel : in std_logic_vector(0 downto 0);
rxrstn : in std_logic_vector(0 downto 0);
txrstn : in std_logic_vector(0 downto 0);
scanmoden : in std_logic_vector(0 downto 0);
pldasyncstatus : out std_logic_vector(5 downto 0);
testout : out std_logic_vector(19 downto 0);
gen3datasel : out std_logic_vector(0 downto 0);
gen3clksel : out std_logic_vector(0 downto 0);
pcsrst : out std_logic_vector(0 downto 0);
dispcbyte : out std_logic_vector(0 downto 0);
resetpcprts : out std_logic_vector(0 downto 0);
shutdownclk : out std_logic_vector(0 downto 0);
txdata : in std_logic_vector(31 downto 0);
txdatak : in std_logic_vector(3 downto 0);
txdataskip : in std_logic_vector(0 downto 0);
txsynchdr : in std_logic_vector(1 downto 0);
txblkstart : in std_logic_vector(0 downto 0);
txelecidle : in std_logic_vector(0 downto 0);
txdetectrxloopback : in std_logic_vector(0 downto 0);
txcompliance : in std_logic_vector(0 downto 0);
rxpolarity : in std_logic_vector(0 downto 0);
powerdown : in std_logic_vector(1 downto 0);
rate : in std_logic_vector(1 downto 0);
txmargin : in std_logic_vector(2 downto 0);
txdeemph : in std_logic_vector(0 downto 0);
txswing : in std_logic_vector(0 downto 0);
eidleinfersel : in std_logic_vector(2 downto 0);
currentcoeff : in std_logic_vector(17 downto 0);
currentrxpreset : in std_logic_vector(2 downto 0);
rxupdatefc : in std_logic_vector(0 downto 0);
rxdataskip : out std_logic_vector(3 downto 0);
rxsynchdr : out std_logic_vector(1 downto 0);
rxblkstart : out std_logic_vector(3 downto 0);
rxvalid : out std_logic_vector(0 downto 0);
phystatus : out std_logic_vector(0 downto 0);
rxelecidle : out std_logic_vector(0 downto 0);
rxstatus : out std_logic_vector(2 downto 0);
rxdataint : in std_logic_vector(31 downto 0);
rxdatakint : in std_logic_vector(3 downto 0);
rxdataskipint : in std_logic_vector(0 downto 0);
rxsynchdrint : in std_logic_vector(1 downto 0);
rxblkstartint : in std_logic_vector(0 downto 0);
txdataint : out std_logic_vector(31 downto 0);
txdatakint : out std_logic_vector(3 downto 0);
txdataskipint : out std_logic_vector(0 downto 0);
txsynchdrint : out std_logic_vector(1 downto 0);
txblkstartint : out std_logic_vector(0 downto 0);
testinfei : out std_logic_vector(18 downto 0);
eidetint : in std_logic_vector(0 downto 0);
eipartialdetint : in std_logic_vector(0 downto 0);
idetint : in std_logic_vector(0 downto 0);
blkalgndint : in std_logic_vector(0 downto 0);
clkcompinsertint : in std_logic_vector(0 downto 0);
clkcompdeleteint : in std_logic_vector(0 downto 0);
clkcompoverflint : in std_logic_vector(0 downto 0);
clkcompundflint : in std_logic_vector(0 downto 0);
errdecodeint : in std_logic_vector(0 downto 0);
rcvlfsrchkint : in std_logic_vector(0 downto 0);
errencodeint : in std_logic_vector(0 downto 0);
rxpolarityint : out std_logic_vector(0 downto 0);
revlpbkint : out std_logic_vector(0 downto 0);
inferredrxvalidint : out std_logic_vector(0 downto 0);
rxd8gpcsin : in std_logic_vector(63 downto 0);
rxelecidle8gpcsin : in std_logic_vector(0 downto 0);
pldltr : in std_logic_vector(0 downto 0);
rxd8gpcsout : out std_logic_vector(63 downto 0);
revlpbk8gpcsout : out std_logic_vector(0 downto 0);
pmarxdetectvalid : in std_logic_vector(0 downto 0);
pmarxfound : in std_logic_vector(0 downto 0);
pmasignaldet : in std_logic_vector(0 downto 0);
pmapcieswdone : in std_logic_vector(1 downto 0);
pmapcieswitch : out std_logic_vector(1 downto 0);
pmatxmargin : out std_logic_vector(2 downto 0);
pmatxdeemph : out std_logic_vector(0 downto 0);
pmatxswing : out std_logic_vector(0 downto 0);
pmacurrentcoeff : out std_logic_vector(17 downto 0);
pmacurrentrxpreset : out std_logic_vector(2 downto 0);
pmatxelecidle : out std_logic_vector(0 downto 0);
pmatxdetectrx : out std_logic_vector(0 downto 0);
ppmeidleexit : out std_logic_vector(0 downto 0);
pmaltr : out std_logic_vector(0 downto 0);
pmaearlyeios : out std_logic_vector(0 downto 0);
pmarxdetpd : out std_logic_vector(0 downto 0);
bundlingindown : in std_logic_vector(9 downto 0);
bundlingoutdown : out std_logic_vector(9 downto 0);
rxpolarity8gpcsout : out std_logic_vector(0 downto 0);
speedchangeg2 : in std_logic_vector(0 downto 0);
bundlingoutup : out std_logic_vector(9 downto 0);
bundlinginup : in std_logic_vector(9 downto 0);
masktxpll : out std_logic_vector(0 downto 0)
);
end component;
begin
inst : stratixv_hssi_pipe_gen3_encrypted
generic map (
mode => mode,
ctrl_plane_bonding => ctrl_plane_bonding,
pipe_clk_sel => pipe_clk_sel,
rate_match_pad_insertion => rate_match_pad_insertion,
ind_error_reporting => ind_error_reporting,
phystatus_rst_toggle_g3 => phystatus_rst_toggle_g3,
phystatus_rst_toggle_g12 => phystatus_rst_toggle_g12,
cdr_control => cdr_control,
cid_enable => cid_enable,
parity_chk_ts1 => parity_chk_ts1,
rxvalid_mask => rxvalid_mask,
ph_fifo_reg_mode => ph_fifo_reg_mode,
test_mode_timers => test_mode_timers,
inf_ei_enable => inf_ei_enable,
spd_chnge_g2_sel => spd_chnge_g2_sel,
cp_up_mstr => cp_up_mstr,
cp_dwn_mstr => cp_dwn_mstr,
cp_cons_sel => cp_cons_sel,
elecidle_delay_g12_data => elecidle_delay_g12_data,
elecidle_delay_g12 => elecidle_delay_g12,
elecidle_delay_g3_data => elecidle_delay_g3_data,
elecidle_delay_g3 => elecidle_delay_g3,
phy_status_delay_g12_data => phy_status_delay_g12_data,
phy_status_delay_g12 => phy_status_delay_g12,
phy_status_delay_g3_data => phy_status_delay_g3_data,
phy_status_delay_g3 => phy_status_delay_g3,
sigdet_wait_counter_data => sigdet_wait_counter_data,
sigdet_wait_counter => sigdet_wait_counter,
data_mask_count_val => data_mask_count_val,
data_mask_count => data_mask_count,
pma_done_counter_data => pma_done_counter_data,
pma_done_counter => pma_done_counter,
pc_en_counter_data => pc_en_counter_data,
pc_en_counter => pc_en_counter,
pc_rst_counter_data => pc_rst_counter_data,
pc_rst_counter => pc_rst_counter,
phfifo_flush_wait_data => phfifo_flush_wait_data,
phfifo_flush_wait => phfifo_flush_wait,
asn_clk_enable => asn_clk_enable,
free_run_clk_enable => free_run_clk_enable,
asn_enable => asn_enable
)
port map (
rcvdclk => rcvdclk,
txpmaclk => txpmaclk,
pcsdigclk => pcsdigclk,
pllfixedclk => pllfixedclk,
rtxgen3capen => rtxgen3capen,
rrxgen3capen => rrxgen3capen,
rtxdigclksel => rtxdigclksel,
rrxdigclksel => rrxdigclksel,
rxrstn => rxrstn,
txrstn => txrstn,
scanmoden => scanmoden,
pldasyncstatus => pldasyncstatus,
testout => testout,
gen3datasel => gen3datasel,
gen3clksel => gen3clksel,
pcsrst => pcsrst,
dispcbyte => dispcbyte,
resetpcprts => resetpcprts,
shutdownclk => shutdownclk,
txdata => txdata,
txdatak => txdatak,
txdataskip => txdataskip,
txsynchdr => txsynchdr,
txblkstart => txblkstart,
txelecidle => txelecidle,
txdetectrxloopback => txdetectrxloopback,
txcompliance => txcompliance,
rxpolarity => rxpolarity,
powerdown => powerdown,
rate => rate,
txmargin => txmargin,
txdeemph => txdeemph,
txswing => txswing,
eidleinfersel => eidleinfersel,
currentcoeff => currentcoeff,
currentrxpreset => currentrxpreset,
rxupdatefc => rxupdatefc,
rxdataskip => rxdataskip,
rxsynchdr => rxsynchdr,
rxblkstart => rxblkstart,
rxvalid => rxvalid,
phystatus => phystatus,
rxelecidle => rxelecidle,
rxstatus => rxstatus,
rxdataint => rxdataint,
rxdatakint => rxdatakint,
rxdataskipint => rxdataskipint,
rxsynchdrint => rxsynchdrint,
rxblkstartint => rxblkstartint,
txdataint => txdataint,
txdatakint => txdatakint,
txdataskipint => txdataskipint,
txsynchdrint => txsynchdrint,
txblkstartint => txblkstartint,
testinfei => testinfei,
eidetint => eidetint,
eipartialdetint => eipartialdetint,
idetint => idetint,
blkalgndint => blkalgndint,
clkcompinsertint => clkcompinsertint,
clkcompdeleteint => clkcompdeleteint,
clkcompoverflint => clkcompoverflint,
clkcompundflint => clkcompundflint,
errdecodeint => errdecodeint,
rcvlfsrchkint => rcvlfsrchkint,
errencodeint => errencodeint,
rxpolarityint => rxpolarityint,
revlpbkint => revlpbkint,
inferredrxvalidint => inferredrxvalidint,
rxd8gpcsin => rxd8gpcsin,
rxelecidle8gpcsin => rxelecidle8gpcsin,
pldltr => pldltr,
rxd8gpcsout => rxd8gpcsout,
revlpbk8gpcsout => revlpbk8gpcsout,
pmarxdetectvalid => pmarxdetectvalid,
pmarxfound => pmarxfound,
pmasignaldet => pmasignaldet,
pmapcieswdone => pmapcieswdone,
pmapcieswitch => pmapcieswitch,
pmatxmargin => pmatxmargin,
pmatxdeemph => pmatxdeemph,
pmatxswing => pmatxswing,
pmacurrentcoeff => pmacurrentcoeff,
pmacurrentrxpreset => pmacurrentrxpreset,
pmatxelecidle => pmatxelecidle,
pmatxdetectrx => pmatxdetectrx,
ppmeidleexit => ppmeidleexit,
pmaltr => pmaltr,
pmaearlyeios => pmaearlyeios,
pmarxdetpd => pmarxdetpd,
bundlingindown => bundlingindown,
bundlingoutdown => bundlingoutdown,
rxpolarity8gpcsout => rxpolarity8gpcsout,
speedchangeg2 => speedchangeg2,
bundlingoutup => bundlingoutup,
bundlinginup => bundlinginup,
masktxpll => masktxpll
);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
entity stratixv_hssi_pma_cdr_refclk_select_mux is
generic (
lpm_type : string := "stratixv_hssi_pma_cdr_refclk_select_mux";
channel_number : integer := 0;
refclk_select : string := "ref_iqclk0";
mux_type : string := "cdr_refclk_select_mux";
reference_clock_frequency : string := "0 ps"
);
port (
calclk : in std_logic;
ffplloutbot : in std_logic;
ffpllouttop : in std_logic;
pldclk : in std_logic;
refiqclk0 : in std_logic;
refiqclk1 : in std_logic;
refiqclk10 : in std_logic;
refiqclk2 : in std_logic;
refiqclk3 : in std_logic;
refiqclk4 : in std_logic;
refiqclk5 : in std_logic;
refiqclk6 : in std_logic;
refiqclk7 : in std_logic;
refiqclk8 : in std_logic;
refiqclk9 : in std_logic;
rxiqclk0 : in std_logic;
rxiqclk1 : in std_logic;
rxiqclk10 : in std_logic;
rxiqclk2 : in std_logic;
rxiqclk3 : in std_logic;
rxiqclk4 : in std_logic;
rxiqclk5 : in std_logic;
rxiqclk6 : in std_logic;
rxiqclk7 : in std_logic;
rxiqclk8 : in std_logic;
rxiqclk9 : in std_logic;
clkout : out std_logic
);
end stratixv_hssi_pma_cdr_refclk_select_mux;
architecture behavior of stratixv_hssi_pma_cdr_refclk_select_mux is
component stratixv_hssi_pma_cdr_refclk_select_mux_encrypted
generic (
lpm_type : string := "stratixv_hssi_pma_cdr_refclk_select_mux";
channel_number : integer := 0;
refclk_select : string := "ref_iqclk0";
reference_clock_frequency : string := "0 ps"
);
port (
calclk : in std_logic;
ffplloutbot : in std_logic;
ffpllouttop : in std_logic;
pldclk : in std_logic;
refiqclk0 : in std_logic;
refiqclk1 : in std_logic;
refiqclk10 : in std_logic;
refiqclk2 : in std_logic;
refiqclk3 : in std_logic;
refiqclk4 : in std_logic;
refiqclk5 : in std_logic;
refiqclk6 : in std_logic;
refiqclk7 : in std_logic;
refiqclk8 : in std_logic;
refiqclk9 : in std_logic;
rxiqclk0 : in std_logic;
rxiqclk1 : in std_logic;
rxiqclk10 : in std_logic;
rxiqclk2 : in std_logic;
rxiqclk3 : in std_logic;
rxiqclk4 : in std_logic;
rxiqclk5 : in std_logic;
rxiqclk6 : in std_logic;
rxiqclk7 : in std_logic;
rxiqclk8 : in std_logic;
rxiqclk9 : in std_logic;
clkout : out std_logic
);
end component;
begin
inst : stratixv_hssi_pma_cdr_refclk_select_mux_encrypted
generic map (
lpm_type => lpm_type,
channel_number => channel_number,
refclk_select => refclk_select,
reference_clock_frequency => reference_clock_frequency
)
port map (
calclk => calclk,
ffplloutbot => ffplloutbot,
ffpllouttop => ffpllouttop,
pldclk => pldclk,
refiqclk0 => refiqclk0,
refiqclk1 => refiqclk1,
refiqclk10 => refiqclk10,
refiqclk2 => refiqclk2,
refiqclk3 => refiqclk3,
refiqclk4 => refiqclk4,
refiqclk5 => refiqclk5,
refiqclk6 => refiqclk6,
refiqclk7 => refiqclk7,
refiqclk8 => refiqclk8,
refiqclk9 => refiqclk9,
rxiqclk0 => rxiqclk0,
rxiqclk1 => rxiqclk1,
rxiqclk10 => rxiqclk10,
rxiqclk2 => rxiqclk2,
rxiqclk3 => rxiqclk3,
rxiqclk4 => rxiqclk4,
rxiqclk5 => rxiqclk5,
rxiqclk6 => rxiqclk6,
rxiqclk7 => rxiqclk7,
rxiqclk8 => rxiqclk8,
rxiqclk9 => rxiqclk9,
clkout => clkout
);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
entity stratixv_hssi_pma_rx_buf is
generic (
lpm_type : string := "stratixv_hssi_pma_rx_buf";
adce_pd : string := "false";
bypass_eqz_stages_123 : string := "all_stages_enabled";
eq_bw_sel : string := "bw_full_12p5";
input_vcm_sel : string := "high_vcm";
pdb_dfe : string := "false";
pdb_sd : string := "false";
qpi_enable : string := "false";
rx_dc_gain : string := "dc_gain_0db";
rx_sel_bias_source : string := "bias_vcmdrv";
sd_off : string := "clk_divrx_2";
sd_on : string := "data_pulse_6";
sd_threshold : string := "sdlv_30mv";
serial_loopback : string := "lpbkp_dis";
term_sel : string := "r_100ohm";
vccela_supply_voltage : string := "vccela_1p0v";
vcm_sel : string := "vtt_0p7v";
channel_number : integer := 0
);
port (
adaptcapture : in std_logic;
adaptdone : out std_logic;
adcestandby : in std_logic;
hardoccaldone : out std_logic;
hardoccalen : in std_logic;
eyemonitor : in std_logic_vector(4 downto 0);
ck0sigdet : in std_logic;
datain : in std_logic;
fined2aout : in std_logic;
lpbkp : in std_logic;
refclklpbk : in std_logic;
rstn : in std_logic;
rxqpipulldn : in std_logic;
slpbk : in std_logic;
dataout : out std_logic;
nonuserfrompmaux : out std_logic;
rdlpbkp : out std_logic;
rxpadce : out std_logic;
sd : out std_logic
);
end stratixv_hssi_pma_rx_buf;
architecture behavior of stratixv_hssi_pma_rx_buf is
component stratixv_hssi_pma_rx_buf_encrypted
generic (
lpm_type : string := "stratixv_hssi_pma_rx_buf";
adce_pd : string := "false";
bypass_eqz_stages_123 : string := "all_stages_enabled";
eq_bw_sel : string := "bw_full_12p5";
input_vcm_sel : string := "high_vcm";
pdb_dfe : string := "false";
pdb_sd : string := "false";
qpi_enable : string := "false";
rx_dc_gain : string := "dc_gain_0db";
rx_sel_bias_source : string := "bias_vcmdrv";
sd_off : string := "clk_divrx_2";
sd_on : string := "data_pulse_6";
sd_threshold : string := "sdlv_30mv";
serial_loopback : string := "lpbkp_dis";
term_sel : string := "r_100ohm";
vccela_supply_voltage : string := "vccela_1p0v";
vcm_sel : string := "vtt_0p7v";
channel_number : integer := 0
);
port (
ck0sigdet : in std_logic;
datain : in std_logic;
fined2aout : in std_logic;
lpbkp : in std_logic;
adaptcapture : in std_logic;
adaptdone : out std_logic;
adcestandby : in std_logic;
hardoccaldone : out std_logic;
hardoccalen : in std_logic;
eyemonitor : in std_logic_vector(4 downto 0);
refclklpbk : in std_logic;
rstn : in std_logic;
rxqpipulldn : in std_logic;
slpbk : in std_logic;
dataout : out std_logic;
nonuserfrompmaux : out std_logic;
rdlpbkp : out std_logic;
rxpadce : out std_logic;
sd : out std_logic
);
end component;
begin
inst : stratixv_hssi_pma_rx_buf_encrypted
generic map (
lpm_type => lpm_type,
adce_pd => adce_pd,
bypass_eqz_stages_123 => bypass_eqz_stages_123,
eq_bw_sel => eq_bw_sel,
input_vcm_sel => input_vcm_sel,
pdb_dfe => pdb_dfe,
pdb_sd => pdb_sd,
qpi_enable => qpi_enable,
rx_dc_gain => rx_dc_gain,
rx_sel_bias_source => rx_sel_bias_source,
sd_off => sd_off,
sd_on => sd_on,
sd_threshold => sd_threshold,
serial_loopback => serial_loopback,
term_sel => term_sel,
vccela_supply_voltage => vccela_supply_voltage,
vcm_sel => vcm_sel,
channel_number => channel_number
)
port map (
ck0sigdet => ck0sigdet,
datain => datain,
fined2aout => fined2aout,
lpbkp => lpbkp,
hardoccalen => hardoccalen,
refclklpbk => refclklpbk,
rstn => rstn,
rxqpipulldn => rxqpipulldn,
slpbk => slpbk,
dataout => dataout,
nonuserfrompmaux => nonuserfrompmaux,
rdlpbkp => rdlpbkp,
rxpadce => rxpadce,
sd => sd,
adaptcapture => adaptcapture,
adaptdone => adaptdone,
adcestandby => adcestandby,
hardoccaldone => hardoccaldone,
eyemonitor => eyemonitor
);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
entity stratixv_hssi_pma_rx_deser is
generic (
lpm_type : string := "stratixv_hssi_pma_rx_deser";
auto_negotiation : string := "false";
bit_slip_bypass : string := "false";
mode : integer := 8;
sdclk_enable : string := "false";
vco_bypass : string := "vco_bypass_normal";
channel_number : integer := 0;
clk_forward_only_mode : string := "false"
);
port (
bslip : in std_logic;
clk90b : in std_logic;
clk270b : in std_logic;
deven : in std_logic;
dodd : in std_logic;
pciesw : in std_logic_vector(1 downto 0);
pfdmodelock : in std_logic;
rstn : in std_logic;
clk33pcs : out std_logic;
clkdivrx : out std_logic;
clkdivrxrx : out std_logic;
dout : out std_logic_vector(39 downto 0);
pciel : out std_logic;
pciem : out std_logic
);
end stratixv_hssi_pma_rx_deser;
architecture behavior of stratixv_hssi_pma_rx_deser is
component stratixv_hssi_pma_rx_deser_encrypted
generic (
lpm_type : string := "stratixv_hssi_pma_rx_deser";
auto_negotiation : string := "false";
bit_slip_bypass : string := "false";
mode : integer := 8;
sdclk_enable : string := "false";
vco_bypass : string := "vco_bypass_normal";
channel_number : integer := 0;
clk_forward_only_mode : string := "false"
);
port (
bslip : in std_logic;
clk90b : in std_logic;
clk270b : in std_logic;
deven : in std_logic;
dodd : in std_logic;
pciesw : in std_logic_vector(1 downto 0);
pfdmodelock : in std_logic;
rstn : in std_logic;
clk33pcs : out std_logic;
clkdivrx : out std_logic;
clkdivrxrx : out std_logic;
dout : out std_logic_vector(39 downto 0);
pciel : out std_logic;
pciem : out std_logic
);
end component;
begin
inst : stratixv_hssi_pma_rx_deser_encrypted
generic map (
lpm_type => lpm_type,
auto_negotiation => auto_negotiation,
bit_slip_bypass => bit_slip_bypass,
mode => mode,
sdclk_enable => sdclk_enable,
vco_bypass => vco_bypass,
channel_number => channel_number,
clk_forward_only_mode => clk_forward_only_mode
)
port map (
bslip => bslip,
clk90b => clk90b,
clk270b => clk270b,
deven => deven,
dodd => dodd,
pciesw => pciesw,
pfdmodelock => pfdmodelock,
rstn => rstn,
clk33pcs => clk33pcs,
clkdivrx => clkdivrx,
clkdivrxrx => clkdivrxrx,
dout => dout,
pciel => pciel,
pciem => pciem
);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
entity stratixv_hssi_pma_tx_buf is
generic (
lpm_type : string := "stratixv_hssi_pma_tx_buf";
elec_idl_gate_ctrl : string := "true";
pre_emp_switching_ctrl_1st_post_tap : string := "fir_1pt_disabled";
pre_emp_switching_ctrl_2nd_post_tap : string := "fir_2pt_disabled";
pre_emp_switching_ctrl_pre_tap : string := "fir_pre_disabled";
qpi_en : string := "false";
rx_det : string := "mode_0";
rx_det_output_sel : string := "rx_det_pcie_out";
rx_det_pdb : string := "true";
sig_inv_2nd_tap : string := "false";
sig_inv_pre_tap : string := "false";
slew_rate_ctrl : string := "slew_30ps";
term_sel : string := "r_100ohm";
vod_switching_ctrl_main_tap : string := "fir_main_2p0ma";
channel_number : integer := 0
);
port (
datain : in std_logic;
rxdetclk : in std_logic;
txdetrx : in std_logic;
txelecidl : in std_logic;
txqpipulldn : in std_logic;
txqpipullup : in std_logic;
compass : out std_logic;
dataout : out std_logic;
detecton : out std_logic_vector(1 downto 0);
fixedclkout : out std_logic;
nonuserfrompmaux : out std_logic;
probepass : out std_logic;
rxdetectvalid : out std_logic;
rxfound : out std_logic
);
end stratixv_hssi_pma_tx_buf;
architecture behavior of stratixv_hssi_pma_tx_buf is
component stratixv_hssi_pma_tx_buf_encrypted
generic (
lpm_type : string := "stratixv_hssi_pma_tx_buf";
elec_idl_gate_ctrl : string := "true";
pre_emp_switching_ctrl_1st_post_tap : string := "fir_1pt_disabled";
pre_emp_switching_ctrl_2nd_post_tap : string := "fir_2pt_disabled";
pre_emp_switching_ctrl_pre_tap : string := "fir_pre_disabled";
qpi_en : string := "false";
rx_det : string := "mode_0";
rx_det_output_sel : string := "rx_det_pcie_out";
rx_det_pdb : string := "true";
sig_inv_2nd_tap : string := "false";
sig_inv_pre_tap : string := "false";
slew_rate_ctrl : string := "slew_30ps";
term_sel : string := "r_100ohm";
vod_switching_ctrl_main_tap : string := "fir_main_2p0ma";
channel_number : integer := 0
);
port (
datain : in std_logic;
rxdetclk : in std_logic;
txdetrx : in std_logic;
txelecidl : in std_logic;
txqpipulldn : in std_logic;
txqpipullup : in std_logic;
compass : out std_logic;
dataout : out std_logic;
detecton : out std_logic_vector(1 downto 0);
fixedclkout : out std_logic;
nonuserfrompmaux : out std_logic;
probepass : out std_logic;
rxdetectvalid : out std_logic;
rxfound : out std_logic
);
end component;
begin
inst : stratixv_hssi_pma_tx_buf_encrypted
generic map (
lpm_type => lpm_type,
elec_idl_gate_ctrl => elec_idl_gate_ctrl,
pre_emp_switching_ctrl_1st_post_tap => pre_emp_switching_ctrl_1st_post_tap,
pre_emp_switching_ctrl_2nd_post_tap => pre_emp_switching_ctrl_2nd_post_tap,
pre_emp_switching_ctrl_pre_tap => pre_emp_switching_ctrl_pre_tap,
qpi_en => qpi_en,
rx_det => rx_det,
rx_det_output_sel => rx_det_output_sel,
rx_det_pdb => rx_det_pdb,
sig_inv_2nd_tap => sig_inv_2nd_tap,
sig_inv_pre_tap => sig_inv_pre_tap,
slew_rate_ctrl => slew_rate_ctrl,
term_sel => term_sel,
vod_switching_ctrl_main_tap => vod_switching_ctrl_main_tap,
channel_number => channel_number
)
port map (
datain => datain,
rxdetclk => rxdetclk,
txdetrx => txdetrx,
txelecidl => txelecidl,
txqpipulldn => txqpipulldn,
txqpipullup => txqpipullup,
compass => compass,
dataout => dataout,
detecton => detecton,
fixedclkout => fixedclkout,
nonuserfrompmaux => nonuserfrompmaux,
probepass => probepass,
rxdetectvalid => rxdetectvalid,
rxfound => rxfound
);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
entity stratixv_hssi_pma_tx_cgb is
generic (
lpm_type : string := "stratixv_hssi_pma_tx_cgb";
auto_negotiation : string := "false";
x1_div_m_sel : integer := 1;
channel_number : integer := 0;
data_rate : string := "";
mode : integer := 8;
rx_iqclk_sel : string := "cgb_x1_n_div";
tx_mux_power_down : string := "normal";
x1_clock_source_sel : string := "x1_clk_unused";
xn_clock_source_sel : string := "cgb_xn_unused";
xn_network_driver : string := "enable_clock_entwork_driver";
cgb_iqclk_sel : string := "cgb_x1_n_div";
ht_delay_enable : string := "false"
);
port (
clkbcdr1adj : in std_logic;
clkbcdr1loc : in std_logic;
clkbcdrloc : in std_logic;
clkbdnseg : in std_logic;
clkbffpll : in std_logic;
clkblcb : in std_logic;
clkblct : in std_logic;
clkbupseg : in std_logic;
clkcdr1adj : in std_logic;
clkcdr1loc : in std_logic;
clkcdrloc : in std_logic;
clkdnseg : in std_logic;
clkffpll : in std_logic;
clklcb : in std_logic;
clklct : in std_logic;
clkupseg : in std_logic;
cpulsex6adj : in std_logic;
cpulsex6loc : in std_logic;
cpulsexndn : in std_logic;
cpulsexnup : in std_logic;
hfclknx6adj : in std_logic;
hfclknx6loc : in std_logic;
hfclknxndn : in std_logic;
hfclknxnup : in std_logic;
hfclkpx6adj : in std_logic;
hfclkpx6loc : in std_logic;
hfclkpxndn : in std_logic;
hfclkpxnup : in std_logic;
lfclknx6adj : in std_logic;
lfclknx6loc : in std_logic;
lfclknxndn : in std_logic;
lfclknxnup : in std_logic;
lfclkpx6adj : in std_logic;
lfclkpx6loc : in std_logic;
lfclkpxndn : in std_logic;
lfclkpxnup : in std_logic;
pciesw : in std_logic_vector(1 downto 0);
pclk0x6adj : in std_logic;
pclk0x6loc : in std_logic;
pclk0xndn : in std_logic;
pclk0xnup : in std_logic;
pclk1x6adj : in std_logic;
pclk1x6loc : in std_logic;
pclk1xndn : in std_logic;
pclk1xnup : in std_logic;
pclkx6adj : in std_logic_vector(2 downto 0);
pclkx6loc : in std_logic_vector(2 downto 0);
pclkxndn : in std_logic_vector(2 downto 0);
pclkxnup : in std_logic_vector(2 downto 0);
rxclk : in std_logic;
txpmarstb : in std_logic;
txpmasyncp : in std_logic;
xnresetin : in std_logic;
cpulse : out std_logic;
cpulseout : out std_logic;
hfclkn : out std_logic;
hfclknout : out std_logic;
hfclkp : out std_logic;
hfclkpout : out std_logic;
lfclkn : out std_logic;
lfclknout : out std_logic;
lfclkp : out std_logic;
lfclkpout : out std_logic;
pcieswdone : out std_logic_vector(1 downto 0);
pclk0 : out std_logic;
pclk0out : out std_logic;
pclk1 : out std_logic;
pclk1out : out std_logic;
pclk : out std_logic_vector(2 downto 0);
pclkout : out std_logic_vector(2 downto 0);
rxiqclk : out std_logic;
xnresetout : out std_logic
);
end stratixv_hssi_pma_tx_cgb;
architecture behavior of stratixv_hssi_pma_tx_cgb is
component stratixv_hssi_pma_tx_cgb_encrypted
generic (
lpm_type : string := "stratixv_hssi_pma_tx_cgb";
auto_negotiation : string := "false";
x1_div_m_sel : integer := 1;
channel_number : integer := 0;
data_rate : string := "";
mode : integer := 8;
rx_iqclk_sel : string := "cgb_x1_n_div";
tx_mux_power_down : string := "normal";
x1_clock_source_sel : string := "x1_clk_unused";
xn_clock_source_sel : string := "cgb_xn_unused";
xn_network_driver : string := "enable_clock_entwork_driver";
cgb_iqclk_sel : string := "cgb_x1_n_div";
ht_delay_enable : string := "false"
);
port (
clkbcdr1adj : in std_logic;
clkbcdr1loc : in std_logic;
clkbcdrloc : in std_logic;
clkbdnseg : in std_logic;
clkbffpll : in std_logic;
clkblcb : in std_logic;
clkblct : in std_logic;
clkbupseg : in std_logic;
clkcdr1adj : in std_logic;
clkcdr1loc : in std_logic;
clkcdrloc : in std_logic;
clkdnseg : in std_logic;
clkffpll : in std_logic;
clklcb : in std_logic;
clklct : in std_logic;
clkupseg : in std_logic;
cpulsex6adj : in std_logic;
cpulsex6loc : in std_logic;
cpulsexndn : in std_logic;
cpulsexnup : in std_logic;
hfclknx6adj : in std_logic;
hfclknx6loc : in std_logic;
hfclknxndn : in std_logic;
hfclknxnup : in std_logic;
hfclkpx6adj : in std_logic;
hfclkpx6loc : in std_logic;
hfclkpxndn : in std_logic;
hfclkpxnup : in std_logic;
lfclknx6adj : in std_logic;
lfclknx6loc : in std_logic;
lfclknxndn : in std_logic;
lfclknxnup : in std_logic;
lfclkpx6adj : in std_logic;
lfclkpx6loc : in std_logic;
lfclkpxndn : in std_logic;
lfclkpxnup : in std_logic;
pciesw : in std_logic_vector(1 downto 0);
pclk0x6adj : in std_logic;
pclk0x6loc : in std_logic;
pclk0xndn : in std_logic;
pclk0xnup : in std_logic;
pclk1x6adj : in std_logic;
pclk1x6loc : in std_logic;
pclk1xndn : in std_logic;
pclk1xnup : in std_logic;
pclkx6adj : in std_logic_vector(2 downto 0);
pclkx6loc : in std_logic_vector(2 downto 0);
pclkxndn : in std_logic_vector(2 downto 0);
pclkxnup : in std_logic_vector(2 downto 0);
rxclk : in std_logic;
txpmarstb : in std_logic;
txpmasyncp : in std_logic;
xnresetin : in std_logic;
cpulse : out std_logic;
cpulseout : out std_logic;
hfclkn : out std_logic;
hfclknout : out std_logic;
hfclkp : out std_logic;
hfclkpout : out std_logic;
lfclkn : out std_logic;
lfclknout : out std_logic;
lfclkp : out std_logic;
lfclkpout : out std_logic;
pcieswdone : out std_logic_vector(1 downto 0);
pclk0 : out std_logic;
pclk0out : out std_logic;
pclk1 : out std_logic;
pclk1out : out std_logic;
pclk : out std_logic_vector(2 downto 0);
pclkout : out std_logic_vector(2 downto 0);
rxiqclk : out std_logic;
xnresetout : out std_logic
);
end component;
begin
inst : stratixv_hssi_pma_tx_cgb_encrypted
generic map (
lpm_type => lpm_type,
auto_negotiation => auto_negotiation,
x1_div_m_sel => x1_div_m_sel,
channel_number => channel_number,
data_rate => data_rate,
mode => mode,
rx_iqclk_sel => rx_iqclk_sel,
tx_mux_power_down => tx_mux_power_down,
x1_clock_source_sel => x1_clock_source_sel,
xn_clock_source_sel => xn_clock_source_sel,
xn_network_driver => xn_network_driver,
cgb_iqclk_sel => cgb_iqclk_sel,
ht_delay_enable => ht_delay_enable
)
port map (
clkbcdr1adj => clkbcdr1adj,
clkbcdr1loc => clkbcdr1loc,
clkbcdrloc => clkbcdrloc,
clkbdnseg => clkbdnseg,
clkbffpll => clkbffpll,
clkblcb => clkblcb,
clkblct => clkblct,
clkbupseg => clkbupseg,
clkcdr1adj => clkcdr1adj,
clkcdr1loc => clkcdr1loc,
clkcdrloc => clkcdrloc,
clkdnseg => clkdnseg,
clkffpll => clkffpll,
clklcb => clklcb,
clklct => clklct,
clkupseg => clkupseg,
cpulsex6adj => cpulsex6adj,
cpulsex6loc => cpulsex6loc,
cpulsexndn => cpulsexndn,
cpulsexnup => cpulsexnup,
hfclknx6adj => hfclknx6adj,
hfclknx6loc => hfclknx6loc,
hfclknxndn => hfclknxndn,
hfclknxnup => hfclknxnup,
hfclkpx6adj => hfclkpx6adj,
hfclkpx6loc => hfclkpx6loc,
hfclkpxndn => hfclkpxndn,
hfclkpxnup => hfclkpxnup,
lfclknx6adj => lfclknx6adj,
lfclknx6loc => lfclknx6loc,
lfclknxndn => lfclknxndn,
lfclknxnup => lfclknxnup,
lfclkpx6adj => lfclkpx6adj,
lfclkpx6loc => lfclkpx6loc,
lfclkpxndn => lfclkpxndn,
lfclkpxnup => lfclkpxnup,
pciesw => pciesw,
pclk0x6adj => pclk0x6adj,
pclk0x6loc => pclk0x6loc,
pclk0xndn => pclk0xndn,
pclk0xnup => pclk0xnup,
pclk1x6adj => pclk1x6adj,
pclk1x6loc => pclk1x6loc,
pclk1xndn => pclk1xndn,
pclk1xnup => pclk1xnup,
pclkx6adj => pclkx6adj,
pclkx6loc => pclkx6loc,
pclkxndn => pclkxndn,
pclkxnup => pclkxnup,
rxclk => rxclk,
txpmarstb => txpmarstb,
txpmasyncp => txpmasyncp,
xnresetin => xnresetin,
cpulse => cpulse,
cpulseout => cpulseout,
hfclkn => hfclkn,
hfclknout => hfclknout,
hfclkp => hfclkp,
hfclkpout => hfclkpout,
lfclkn => lfclkn,
lfclknout => lfclknout,
lfclkp => lfclkp,
lfclkpout => lfclkpout,
pcieswdone => pcieswdone,
pclk0 => pclk0,
pclk0out => pclk0out,
pclk1 => pclk1,
pclk1out => pclk1out,
pclk => pclk,
pclkout => pclkout,
rxiqclk => rxiqclk,
xnresetout => xnresetout
);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
entity stratixv_hssi_pma_tx_ser is
generic (
lpm_type : string := "stratixv_hssi_pma_tx_ser";
auto_negotiation : string := "false";
clk_divtx_deskew : string := "deskew_delay1";
mode : integer := 8;
post_tap_1_en : string := "false";
post_tap_2_en : string := "false";
pre_tap_en : string := "false";
ser_loopback : string := "false";
pclksel : string := "local_pclk";
channel_number : integer := 0;
clk_forward_only_mode : string := "false"
);
port (
cpulse : in std_logic;
datain : in std_logic_vector(39 downto 0);
hfclk : in std_logic;
hfclkn : in std_logic;
lfclk : in std_logic;
lfclkn : in std_logic;
pciesw : in std_logic_vector(1 downto 0);
pclk0 : in std_logic;
pclk1 : in std_logic;
pclk2 : in std_logic;
pclk : in std_logic_vector(2 downto 0);
rstn : in std_logic;
clkdivtx : out std_logic;
dataout : out std_logic;
div5 : out std_logic;
lbvop : out std_logic
);
end stratixv_hssi_pma_tx_ser;
architecture behavior of stratixv_hssi_pma_tx_ser is
component stratixv_hssi_pma_tx_ser_encrypted
generic (
lpm_type : string := "stratixv_hssi_pma_tx_ser";
auto_negotiation : string := "false";
clk_divtx_deskew : string := "deskew_delay1";
mode : integer := 8;
post_tap_1_en : string := "false";
post_tap_2_en : string := "false";
pre_tap_en : string := "false";
ser_loopback : string := "false";
pclksel : string := "local_pclk";
channel_number : integer := 0;
clk_forward_only_mode : string := "false"
);
port (
cpulse : in std_logic;
datain : in std_logic_vector(39 downto 0);
hfclk : in std_logic;
hfclkn : in std_logic;
lfclk : in std_logic;
lfclkn : in std_logic;
pciesw : in std_logic_vector(1 downto 0);
pclk0 : in std_logic;
pclk1 : in std_logic;
pclk2 : in std_logic;
pclk : in std_logic_vector(2 downto 0);
rstn : in std_logic;
clkdivtx : out std_logic;
dataout : out std_logic;
div5 : out std_logic;
lbvop : out std_logic
);
end component;
begin
inst : stratixv_hssi_pma_tx_ser_encrypted
generic map (
lpm_type => lpm_type,
auto_negotiation => auto_negotiation,
clk_divtx_deskew => clk_divtx_deskew,
mode => mode,
post_tap_1_en => post_tap_1_en,
post_tap_2_en => post_tap_2_en,
pre_tap_en => pre_tap_en,
ser_loopback => ser_loopback,
pclksel => pclksel,
channel_number => channel_number,
clk_forward_only_mode => clk_forward_only_mode
)
port map (
cpulse => cpulse,
datain => datain,
hfclk => hfclk,
hfclkn => hfclkn,
lfclk => lfclk,
lfclkn => lfclkn,
pciesw => pciesw,
pclk0 => pclk0,
pclk1 => pclk1,
pclk2 => pclk2,
pclk => pclk,
rstn => rstn,
clkdivtx => clkdivtx,
dataout => dataout,
div5 => div5,
lbvop => lbvop
);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
entity stratixv_hssi_common_pcs_pma_interface is
generic (
lpm_type : string := "stratixv_hssi_common_pcs_pma_interface";
auto_speed_ena : string := "dis_auto_speed_ena";
force_freqdet : string := "force_freqdet_dis";
func_mode : string := "disable";
pcie_gen3_cap : string := "non_pcie_gen3_cap";
pipe_if_g3pcs : string := "pipe_if_8gpcs";
pma_if_dft_en : string := "dft_dis";
pma_if_dft_val : string := "dft_0";
ppm_cnt_rst : string := "ppm_cnt_rst_dis";
ppm_deassert_early : string := "deassert_early_dis";
ppm_gen1_2_cnt : string := "cnt_32k";
ppm_post_eidle_delay : string := "cnt_200_cycles";
ppmsel : string := "ppmsel_default";
prot_mode : string := "disabled_prot_mode";
refclk_dig_sel : string := "refclk_dig_dis";
selectpcs : string := "eight_g_pcs";
sup_mode : string := "full_mode"
);
port (
fref : in std_logic;
clklow : in std_logic;
pmapcieswdone : in std_logic_vector(1 downto 0);
pmarxfound : in std_logic;
pmarxdetectvalid : in std_logic;
pmahclk : in std_logic;
pldoffcalen : in std_logic;
aggrcvdclkagg : in std_logic;
aggtxdatats : in std_logic_vector(7 downto 0);
aggtxctlts : in std_logic;
aggfiforstrdqd : in std_logic;
aggendskwqd : in std_logic;
aggendskwrdptrs : in std_logic;
aggalignstatus : in std_logic;
aggalignstatussync0 : in std_logic;
aggcgcomprddall : in std_logic;
aggcgcompwrall : in std_logic;
aggfifordincomp0 : in std_logic;
aggdelcondmet0 : in std_logic;
agginsertincomplete0 : in std_logic;
aggfifoovr0 : in std_logic;
agglatencycomp0 : in std_logic;
aggrxdatars : in std_logic_vector(7 downto 0);
aggrxcontrolrs : in std_logic;
aggrcvdclkaggtoporbot : in std_logic;
aggtxdatatstoporbot : in std_logic_vector(7 downto 0);
aggtxctltstoporbot : in std_logic;
aggfiforstrdqdtoporbot : in std_logic;
aggendskwqdtoporbot : in std_logic;
aggendskwrdptrstoporbot : in std_logic;
aggalignstatustoporbot : in std_logic;
aggalignstatussync0toporbot : in std_logic;
aggcgcomprddalltoporbot : in std_logic;
aggcgcompwralltoporbot : in std_logic;
aggfifordincomp0toporbot : in std_logic;
aggdelcondmet0toporbot : in std_logic;
agginsertincomplete0toporbot : in std_logic;
aggfifoovr0toporbot : in std_logic;
agglatencycomp0toporbot : in std_logic;
aggrxdatarstoporbot : in std_logic_vector(7 downto 0);
aggrxcontrolrstoporbot : in std_logic;
pcsgen3pmapcieswitch : in std_logic_vector(1 downto 0);
pcsgen3pmatxmargin : in std_logic_vector(2 downto 0);
pcsgen3pmatxdeemph : in std_logic;
pcsgen3pmatxswing : in std_logic;
pcsgen3pmacurrentcoeff : in std_logic_vector(17 downto 0);
pcsgen3pmacurrentrxpreset : in std_logic_vector(2 downto 0);
pcsgen3pmatxelecidle : in std_logic;
pcsgen3pmatxdetectrx : in std_logic;
pcsgen3ppmeidleexit : in std_logic;
pcsgen3pmaltr : in std_logic;
pcsgen3pmaearlyeios : in std_logic;
pcs8gpcieswitch : in std_logic;
pcs8gtxelecidle : in std_logic;
pcs8gtxdetectrx : in std_logic;
pcs8gearlyeios : in std_logic;
pcs8gtxdeemphpma : in std_logic;
pcs8gtxmarginpma : in std_logic_vector(2 downto 0);
pcs8gtxswingpma : in std_logic;
pcs8gltrpma : in std_logic;
pcs8geidleexit : in std_logic;
pcsaggtxpcsrst : in std_logic;
pcsaggrxpcsrst : in std_logic;
pcsaggtxdatatc : in std_logic_vector(7 downto 0);
pcsaggtxctltc : in std_logic;
pcsaggrdenablesync : in std_logic;
pcsaggsyncstatus : in std_logic;
pcsaggaligndetsync : in std_logic_vector(1 downto 0);
pcsaggrdalign : in std_logic_vector(1 downto 0);
pcsaggalignstatussync : in std_logic;
pcsaggfifordoutcomp : in std_logic;
pcsaggcgcomprddout : in std_logic_vector(1 downto 0);
pcsaggcgcompwrout : in std_logic_vector(1 downto 0);
pcsaggdelcondmetout : in std_logic;
pcsaggfifoovrout : in std_logic;
pcsagglatencycompout : in std_logic;
pcsagginsertincompleteout : in std_logic;
pcsaggdecdatavalid : in std_logic;
pcsaggdecdata : in std_logic_vector(7 downto 0);
pcsaggdecctl : in std_logic;
pcsaggrunningdisp : in std_logic_vector(1 downto 0);
pldrxclkslip : in std_logic;
pldhardreset : in std_logic;
pcsscanmoden : in std_logic;
pcsscanshiftn : in std_logic;
pcsrefclkdig : in std_logic;
pcsaggscanmoden : in std_logic;
pcsaggscanshiftn : in std_logic;
pcsaggrefclkdig : in std_logic;
pcsgen3gen3datasel : in std_logic;
pldlccmurstb : in std_logic;
pmaoffcaldonein : in std_logic;
pmarxpmarstb : in std_logic;
pmahardreset : out std_logic;
freqlock : out std_logic;
pmapcieswitch : out std_logic_vector(1 downto 0);
pmaearlyeios : out std_logic;
pmatxdetectrx : out std_logic;
pmatxelecidle : out std_logic;
pmatxdeemph : out std_logic;
pmatxswing : out std_logic;
pmatxmargin : out std_logic_vector(2 downto 0);
pmacurrentcoeff : out std_logic_vector(17 downto 0);
pmacurrentrxpreset : out std_logic_vector(2 downto 0);
pmaoffcaldoneout : out std_logic;
pmalccmurstb : out std_logic;
pmaltr : out std_logic;
aggtxpcsrst : out std_logic;
aggrxpcsrst : out std_logic;
aggtxdatatc : out std_logic_vector(7 downto 0);
aggtxctltc : out std_logic;
aggrdenablesync : out std_logic;
aggsyncstatus : out std_logic;
aggaligndetsync : out std_logic_vector(1 downto 0);
aggrdalign : out std_logic_vector(1 downto 0);
aggalignstatussync : out std_logic;
aggfifordoutcomp : out std_logic;
aggcgcomprddout : out std_logic_vector(1 downto 0);
aggcgcompwrout : out std_logic_vector(1 downto 0);
aggdelcondmetout : out std_logic;
aggfifoovrout : out std_logic;
agglatencycompout : out std_logic;
agginsertincompleteout : out std_logic;
aggdecdatavalid : out std_logic;
aggdecdata : out std_logic_vector(7 downto 0);
aggdecctl : out std_logic;
aggrunningdisp : out std_logic_vector(1 downto 0);
pcsgen3pmarxdetectvalid : out std_logic;
pcsgen3pmarxfound : out std_logic;
pcsgen3pmapcieswdone : out std_logic_vector(1 downto 0);
pcsgen3pllfixedclk : out std_logic;
pcsaggrcvdclkagg : out std_logic;
pcsaggtxdatats : out std_logic_vector(7 downto 0);
pcsaggtxctlts : out std_logic;
pcsaggfiforstrdqd : out std_logic;
pcsaggendskwqd : out std_logic;
pcsaggendskwrdptrs : out std_logic;
pcsaggalignstatus : out std_logic;
pcsaggalignstatussync0 : out std_logic;
pcsaggcgcomprddall : out std_logic;
pcsaggcgcompwrall : out std_logic;
pcsaggfifordincomp0 : out std_logic;
pcsaggdelcondmet0 : out std_logic;
pcsagginsertincomplete0 : out std_logic;
pcsaggfifoovr0 : out std_logic;
pcsagglatencycomp0 : out std_logic;
pcsaggrxdatars : out std_logic_vector(7 downto 0);
pcsaggrxcontrolrs : out std_logic;
pcsaggrcvdclkaggtoporbot : out std_logic;
pcsaggtxdatatstoporbot : out std_logic_vector(7 downto 0);
pcsaggtxctltstoporbot : out std_logic;
pcsaggfiforstrdqdtoporbot : out std_logic;
pcsaggendskwqdtoporbot : out std_logic;
pcsaggendskwrdptrstoporbot : out std_logic;
pcsaggalignstatustoporbot : out std_logic;
pcsaggalignstatussync0toporbot : out std_logic;
pcsaggcgcomprddalltoporbot : out std_logic;
pcsaggcgcompwralltoporbot : out std_logic;
pcsaggfifordincomp0toporbot : out std_logic;
pcsaggdelcondmet0toporbot : out std_logic;
pcsagginsertincomplete0toporbot : out std_logic;
pcsaggfifoovr0toporbot : out std_logic;
pcsagglatencycomp0toporbot : out std_logic;
pcsaggrxdatarstoporbot : out std_logic_vector(7 downto 0);
pcsaggrxcontrolrstoporbot : out std_logic;
pcs8grxdetectvalid : out std_logic;
pcs8gpmarxfound : out std_logic;
pcs8ggen2ngen1 : out std_logic;
pcs8gpowerstatetransitiondone : out std_logic;
ppmcntlatch : out std_logic_vector(7 downto 0);
pldhclkout : out std_logic;
aggscanmoden : out std_logic;
aggscanshiftn : out std_logic;
aggrefclkdig : out std_logic;
pmaoffcalen : out std_logic;
pmafrefout : out std_logic;
pmaclklowout : out std_logic
);
end stratixv_hssi_common_pcs_pma_interface;
architecture behavior of stratixv_hssi_common_pcs_pma_interface is
component stratixv_hssi_common_pcs_pma_interface_encrypted
generic (
lpm_type : string := "stratixv_hssi_common_pcs_pma_interface";
auto_speed_ena : string := "dis_auto_speed_ena";
force_freqdet : string := "force_freqdet_dis";
func_mode : string := "disable";
pcie_gen3_cap : string := "non_pcie_gen3_cap";
pipe_if_g3pcs : string := "pipe_if_8gpcs";
pma_if_dft_en : string := "dft_dis";
pma_if_dft_val : string := "dft_0";
ppm_cnt_rst : string := "ppm_cnt_rst_dis";
ppm_deassert_early : string := "deassert_early_dis";
ppm_gen1_2_cnt : string := "cnt_32k";
ppm_post_eidle_delay : string := "cnt_200_cycles";
ppmsel : string := "ppmsel_default";
prot_mode : string := "disabled_prot_mode";
refclk_dig_sel : string := "refclk_dig_dis";
selectpcs : string := "eight_g_pcs";
sup_mode : string := "full_mode"
);
port (
fref : in std_logic;
clklow : in std_logic;
pmapcieswdone : in std_logic_vector(1 downto 0);
pmarxfound : in std_logic;
pmarxdetectvalid : in std_logic;
pmahclk : in std_logic;
pldoffcalen : in std_logic;
aggrcvdclkagg : in std_logic;
aggtxdatats : in std_logic_vector(7 downto 0);
aggtxctlts : in std_logic;
aggfiforstrdqd : in std_logic;
aggendskwqd : in std_logic;
aggendskwrdptrs : in std_logic;
aggalignstatus : in std_logic;
aggalignstatussync0 : in std_logic;
aggcgcomprddall : in std_logic;
aggcgcompwrall : in std_logic;
aggfifordincomp0 : in std_logic;
aggdelcondmet0 : in std_logic;
agginsertincomplete0 : in std_logic;
aggfifoovr0 : in std_logic;
agglatencycomp0 : in std_logic;
aggrxdatars : in std_logic_vector(7 downto 0);
aggrxcontrolrs : in std_logic;
aggrcvdclkaggtoporbot : in std_logic;
aggtxdatatstoporbot : in std_logic_vector(7 downto 0);
aggtxctltstoporbot : in std_logic;
aggfiforstrdqdtoporbot : in std_logic;
aggendskwqdtoporbot : in std_logic;
aggendskwrdptrstoporbot : in std_logic;
aggalignstatustoporbot : in std_logic;
aggalignstatussync0toporbot : in std_logic;
aggcgcomprddalltoporbot : in std_logic;
aggcgcompwralltoporbot : in std_logic;
aggfifordincomp0toporbot : in std_logic;
aggdelcondmet0toporbot : in std_logic;
agginsertincomplete0toporbot : in std_logic;
aggfifoovr0toporbot : in std_logic;
agglatencycomp0toporbot : in std_logic;
aggrxdatarstoporbot : in std_logic_vector(7 downto 0);
aggrxcontrolrstoporbot : in std_logic;
pcsgen3pmapcieswitch : in std_logic_vector(1 downto 0);
pcsgen3pmatxmargin : in std_logic_vector(2 downto 0);
pcsgen3pmatxdeemph : in std_logic;
pcsgen3pmatxswing : in std_logic;
pcsgen3pmacurrentcoeff : in std_logic_vector(17 downto 0);
pcsgen3pmacurrentrxpreset : in std_logic_vector(2 downto 0);
pcsgen3pmatxelecidle : in std_logic;
pcsgen3pmatxdetectrx : in std_logic;
pcsgen3ppmeidleexit : in std_logic;
pcsgen3pmaltr : in std_logic;
pcsgen3pmaearlyeios : in std_logic;
pcs8gpcieswitch : in std_logic;
pcs8gtxelecidle : in std_logic;
pcs8gtxdetectrx : in std_logic;
pcs8gearlyeios : in std_logic;
pcs8gtxdeemphpma : in std_logic;
pcs8gtxmarginpma : in std_logic_vector(2 downto 0);
pcs8gtxswingpma : in std_logic;
pcs8gltrpma : in std_logic;
pcs8geidleexit : in std_logic;
pcsaggtxpcsrst : in std_logic;
pcsaggrxpcsrst : in std_logic;
pcsaggtxdatatc : in std_logic_vector(7 downto 0);
pcsaggtxctltc : in std_logic;
pcsaggrdenablesync : in std_logic;
pcsaggsyncstatus : in std_logic;
pcsaggaligndetsync : in std_logic_vector(1 downto 0);
pcsaggrdalign : in std_logic_vector(1 downto 0);
pcsaggalignstatussync : in std_logic;
pcsaggfifordoutcomp : in std_logic;
pcsaggcgcomprddout : in std_logic_vector(1 downto 0);
pcsaggcgcompwrout : in std_logic_vector(1 downto 0);
pcsaggdelcondmetout : in std_logic;
pcsaggfifoovrout : in std_logic;
pcsagglatencycompout : in std_logic;
pcsagginsertincompleteout : in std_logic;
pcsaggdecdatavalid : in std_logic;
pcsaggdecdata : in std_logic_vector(7 downto 0);
pcsaggdecctl : in std_logic;
pcsaggrunningdisp : in std_logic_vector(1 downto 0);
pldrxclkslip : in std_logic;
pldhardreset : in std_logic;
pcsscanmoden : in std_logic;
pcsscanshiftn : in std_logic;
pcsrefclkdig : in std_logic;
pcsaggscanmoden : in std_logic;
pcsaggscanshiftn : in std_logic;
pcsaggrefclkdig : in std_logic;
pcsgen3gen3datasel : in std_logic;
pldlccmurstb : in std_logic;
pmaoffcaldonein : in std_logic;
pmarxpmarstb : in std_logic;
pmahardreset : out std_logic;
freqlock : out std_logic;
pmapcieswitch : out std_logic_vector(1 downto 0);
pmaearlyeios : out std_logic;
pmatxdetectrx : out std_logic;
pmatxelecidle : out std_logic;
pmatxdeemph : out std_logic;
pmatxswing : out std_logic;
pmatxmargin : out std_logic_vector(2 downto 0);
pmacurrentcoeff : out std_logic_vector(17 downto 0);
pmacurrentrxpreset : out std_logic_vector(2 downto 0);
pmaoffcaldoneout : out std_logic;
pmalccmurstb : out std_logic;
pmaltr : out std_logic;
aggtxpcsrst : out std_logic;
aggrxpcsrst : out std_logic;
aggtxdatatc : out std_logic_vector(7 downto 0);
aggtxctltc : out std_logic;
aggrdenablesync : out std_logic;
aggsyncstatus : out std_logic;
aggaligndetsync : out std_logic_vector(1 downto 0);
aggrdalign : out std_logic_vector(1 downto 0);
aggalignstatussync : out std_logic;
aggfifordoutcomp : out std_logic;
aggcgcomprddout : out std_logic_vector(1 downto 0);
aggcgcompwrout : out std_logic_vector(1 downto 0);
aggdelcondmetout : out std_logic;
aggfifoovrout : out std_logic;
agglatencycompout : out std_logic;
agginsertincompleteout : out std_logic;
aggdecdatavalid : out std_logic;
aggdecdata : out std_logic_vector(7 downto 0);
aggdecctl : out std_logic;
aggrunningdisp : out std_logic_vector(1 downto 0);
pcsgen3pmarxdetectvalid : out std_logic;
pcsgen3pmarxfound : out std_logic;
pcsgen3pmapcieswdone : out std_logic_vector(1 downto 0);
pcsgen3pllfixedclk : out std_logic;
pcsaggrcvdclkagg : out std_logic;
pcsaggtxdatats : out std_logic_vector(7 downto 0);
pcsaggtxctlts : out std_logic;
pcsaggfiforstrdqd : out std_logic;
pcsaggendskwqd : out std_logic;
pcsaggendskwrdptrs : out std_logic;
pcsaggalignstatus : out std_logic;
pcsaggalignstatussync0 : out std_logic;
pcsaggcgcomprddall : out std_logic;
pcsaggcgcompwrall : out std_logic;
pcsaggfifordincomp0 : out std_logic;
pcsaggdelcondmet0 : out std_logic;
pcsagginsertincomplete0 : out std_logic;
pcsaggfifoovr0 : out std_logic;
pcsagglatencycomp0 : out std_logic;
pcsaggrxdatars : out std_logic_vector(7 downto 0);
pcsaggrxcontrolrs : out std_logic;
pcsaggrcvdclkaggtoporbot : out std_logic;
pcsaggtxdatatstoporbot : out std_logic_vector(7 downto 0);
pcsaggtxctltstoporbot : out std_logic;
pcsaggfiforstrdqdtoporbot : out std_logic;
pcsaggendskwqdtoporbot : out std_logic;
pcsaggendskwrdptrstoporbot : out std_logic;
pcsaggalignstatustoporbot : out std_logic;
pcsaggalignstatussync0toporbot : out std_logic;
pcsaggcgcomprddalltoporbot : out std_logic;
pcsaggcgcompwralltoporbot : out std_logic;
pcsaggfifordincomp0toporbot : out std_logic;
pcsaggdelcondmet0toporbot : out std_logic;
pcsagginsertincomplete0toporbot : out std_logic;
pcsaggfifoovr0toporbot : out std_logic;
pcsagglatencycomp0toporbot : out std_logic;
pcsaggrxdatarstoporbot : out std_logic_vector(7 downto 0);
pcsaggrxcontrolrstoporbot : out std_logic;
pcs8grxdetectvalid : out std_logic;
pcs8gpmarxfound : out std_logic;
pcs8ggen2ngen1 : out std_logic;
pcs8gpowerstatetransitiondone : out std_logic;
ppmcntlatch : out std_logic_vector(7 downto 0);
pldhclkout : out std_logic;
aggscanmoden : out std_logic;
aggscanshiftn : out std_logic;
aggrefclkdig : out std_logic;
pmaoffcalen : out std_logic;
pmafrefout : out std_logic;
pmaclklowout : out std_logic
);
end component;
begin
inst : stratixv_hssi_common_pcs_pma_interface_encrypted
generic map (
lpm_type => lpm_type,
auto_speed_ena => auto_speed_ena,
force_freqdet => force_freqdet,
func_mode => func_mode,
pcie_gen3_cap => pcie_gen3_cap,
pipe_if_g3pcs => pipe_if_g3pcs,
pma_if_dft_en => pma_if_dft_en,
pma_if_dft_val => pma_if_dft_val,
ppm_cnt_rst => ppm_cnt_rst,
ppm_deassert_early => ppm_deassert_early,
ppm_gen1_2_cnt => ppm_gen1_2_cnt,
ppm_post_eidle_delay => ppm_post_eidle_delay,
ppmsel => ppmsel,
prot_mode => prot_mode,
refclk_dig_sel => refclk_dig_sel,
selectpcs => selectpcs,
sup_mode => sup_mode
)
port map (
fref => fref,
clklow => clklow,
pmapcieswdone => pmapcieswdone,
pmarxfound => pmarxfound,
pmarxdetectvalid => pmarxdetectvalid,
pmahclk => pmahclk,
pldoffcalen => pldoffcalen,
aggrcvdclkagg => aggrcvdclkagg,
aggtxdatats => aggtxdatats,
aggtxctlts => aggtxctlts,
aggfiforstrdqd => aggfiforstrdqd,
aggendskwqd => aggendskwqd,
aggendskwrdptrs => aggendskwrdptrs,
aggalignstatus => aggalignstatus,
aggalignstatussync0 => aggalignstatussync0,
aggcgcomprddall => aggcgcomprddall,
aggcgcompwrall => aggcgcompwrall,
aggfifordincomp0 => aggfifordincomp0,
aggdelcondmet0 => aggdelcondmet0,
agginsertincomplete0 => agginsertincomplete0,
aggfifoovr0 => aggfifoovr0,
agglatencycomp0 => agglatencycomp0,
aggrxdatars => aggrxdatars,
aggrxcontrolrs => aggrxcontrolrs,
aggrcvdclkaggtoporbot => aggrcvdclkaggtoporbot,
aggtxdatatstoporbot => aggtxdatatstoporbot,
aggtxctltstoporbot => aggtxctltstoporbot,
aggfiforstrdqdtoporbot => aggfiforstrdqdtoporbot,
aggendskwqdtoporbot => aggendskwqdtoporbot,
aggendskwrdptrstoporbot => aggendskwrdptrstoporbot,
aggalignstatustoporbot => aggalignstatustoporbot,
aggalignstatussync0toporbot => aggalignstatussync0toporbot,
aggcgcomprddalltoporbot => aggcgcomprddalltoporbot,
aggcgcompwralltoporbot => aggcgcompwralltoporbot,
aggfifordincomp0toporbot => aggfifordincomp0toporbot,
aggdelcondmet0toporbot => aggdelcondmet0toporbot,
agginsertincomplete0toporbot => agginsertincomplete0toporbot,
aggfifoovr0toporbot => aggfifoovr0toporbot,
agglatencycomp0toporbot => agglatencycomp0toporbot,
aggrxdatarstoporbot => aggrxdatarstoporbot,
aggrxcontrolrstoporbot => aggrxcontrolrstoporbot,
pcsgen3pmapcieswitch => pcsgen3pmapcieswitch,
pcsgen3pmatxmargin => pcsgen3pmatxmargin,
pcsgen3pmatxdeemph => pcsgen3pmatxdeemph,
pcsgen3pmatxswing => pcsgen3pmatxswing,
pcsgen3pmacurrentcoeff => pcsgen3pmacurrentcoeff,
pcsgen3pmacurrentrxpreset => pcsgen3pmacurrentrxpreset,
pcsgen3pmatxelecidle => pcsgen3pmatxelecidle,
pcsgen3pmatxdetectrx => pcsgen3pmatxdetectrx,
pcsgen3ppmeidleexit => pcsgen3ppmeidleexit,
pcsgen3pmaltr => pcsgen3pmaltr,
pcsgen3pmaearlyeios => pcsgen3pmaearlyeios,
pcs8gpcieswitch => pcs8gpcieswitch,
pcs8gtxelecidle => pcs8gtxelecidle,
pcs8gtxdetectrx => pcs8gtxdetectrx,
pcs8gearlyeios => pcs8gearlyeios,
pcs8gtxdeemphpma => pcs8gtxdeemphpma,
pcs8gtxmarginpma => pcs8gtxmarginpma,
pcs8gtxswingpma => pcs8gtxswingpma,
pcs8gltrpma => pcs8gltrpma,
pcs8geidleexit => pcs8geidleexit,
pcsaggtxpcsrst => pcsaggtxpcsrst,
pcsaggrxpcsrst => pcsaggrxpcsrst,
pcsaggtxdatatc => pcsaggtxdatatc,
pcsaggtxctltc => pcsaggtxctltc,
pcsaggrdenablesync => pcsaggrdenablesync,
pcsaggsyncstatus => pcsaggsyncstatus,
pcsaggaligndetsync => pcsaggaligndetsync,
pcsaggrdalign => pcsaggrdalign,
pcsaggalignstatussync => pcsaggalignstatussync,
pcsaggfifordoutcomp => pcsaggfifordoutcomp,
pcsaggcgcomprddout => pcsaggcgcomprddout,
pcsaggcgcompwrout => pcsaggcgcompwrout,
pcsaggdelcondmetout => pcsaggdelcondmetout,
pcsaggfifoovrout => pcsaggfifoovrout,
pcsagglatencycompout => pcsagglatencycompout,
pcsagginsertincompleteout => pcsagginsertincompleteout,
pcsaggdecdatavalid => pcsaggdecdatavalid,
pcsaggdecdata => pcsaggdecdata,
pcsaggdecctl => pcsaggdecctl,
pcsaggrunningdisp => pcsaggrunningdisp,
pldrxclkslip => pldrxclkslip,
pldhardreset => pldhardreset,
pcsscanmoden => pcsscanmoden,
pcsscanshiftn => pcsscanshiftn,
pcsrefclkdig => pcsrefclkdig,
pcsaggscanmoden => pcsaggscanmoden,
pcsaggscanshiftn => pcsaggscanshiftn,
pcsaggrefclkdig => pcsaggrefclkdig,
pcsgen3gen3datasel => pcsgen3gen3datasel,
pldlccmurstb => pldlccmurstb,
pmaoffcaldonein => pmaoffcaldonein,
pmarxpmarstb => pmarxpmarstb,
pmahardreset => pmahardreset,
freqlock => freqlock,
pmapcieswitch => pmapcieswitch,
pmaearlyeios => pmaearlyeios,
pmatxdetectrx => pmatxdetectrx,
pmatxelecidle => pmatxelecidle,
pmatxdeemph => pmatxdeemph,
pmatxswing => pmatxswing,
pmatxmargin => pmatxmargin,
pmacurrentcoeff => pmacurrentcoeff,
pmacurrentrxpreset => pmacurrentrxpreset,
pmaoffcaldoneout => pmaoffcaldoneout,
pmalccmurstb => pmalccmurstb,
pmaltr => pmaltr,
aggtxpcsrst => aggtxpcsrst,
aggrxpcsrst => aggrxpcsrst,
aggtxdatatc => aggtxdatatc,
aggtxctltc => aggtxctltc,
aggrdenablesync => aggrdenablesync,
aggsyncstatus => aggsyncstatus,
aggaligndetsync => aggaligndetsync,
aggrdalign => aggrdalign,
aggalignstatussync => aggalignstatussync,
aggfifordoutcomp => aggfifordoutcomp,
aggcgcomprddout => aggcgcomprddout,
aggcgcompwrout => aggcgcompwrout,
aggdelcondmetout => aggdelcondmetout,
aggfifoovrout => aggfifoovrout,
agglatencycompout => agglatencycompout,
agginsertincompleteout => agginsertincompleteout,
aggdecdatavalid => aggdecdatavalid,
aggdecdata => aggdecdata,
aggdecctl => aggdecctl,
aggrunningdisp => aggrunningdisp,
pcsgen3pmarxdetectvalid => pcsgen3pmarxdetectvalid,
pcsgen3pmarxfound => pcsgen3pmarxfound,
pcsgen3pmapcieswdone => pcsgen3pmapcieswdone,
pcsgen3pllfixedclk => pcsgen3pllfixedclk,
pcsaggrcvdclkagg => pcsaggrcvdclkagg,
pcsaggtxdatats => pcsaggtxdatats,
pcsaggtxctlts => pcsaggtxctlts,
pcsaggfiforstrdqd => pcsaggfiforstrdqd,
pcsaggendskwqd => pcsaggendskwqd,
pcsaggendskwrdptrs => pcsaggendskwrdptrs,
pcsaggalignstatus => pcsaggalignstatus,
pcsaggalignstatussync0 => pcsaggalignstatussync0,
pcsaggcgcomprddall => pcsaggcgcomprddall,
pcsaggcgcompwrall => pcsaggcgcompwrall,
pcsaggfifordincomp0 => pcsaggfifordincomp0,
pcsaggdelcondmet0 => pcsaggdelcondmet0,
pcsagginsertincomplete0 => pcsagginsertincomplete0,
pcsaggfifoovr0 => pcsaggfifoovr0,
pcsagglatencycomp0 => pcsagglatencycomp0,
pcsaggrxdatars => pcsaggrxdatars,
pcsaggrxcontrolrs => pcsaggrxcontrolrs,
pcsaggrcvdclkaggtoporbot => pcsaggrcvdclkaggtoporbot,
pcsaggtxdatatstoporbot => pcsaggtxdatatstoporbot,
pcsaggtxctltstoporbot => pcsaggtxctltstoporbot,
pcsaggfiforstrdqdtoporbot => pcsaggfiforstrdqdtoporbot,
pcsaggendskwqdtoporbot => pcsaggendskwqdtoporbot,
pcsaggendskwrdptrstoporbot => pcsaggendskwrdptrstoporbot,
pcsaggalignstatustoporbot => pcsaggalignstatustoporbot,
pcsaggalignstatussync0toporbot => pcsaggalignstatussync0toporbot,
pcsaggcgcomprddalltoporbot => pcsaggcgcomprddalltoporbot,
pcsaggcgcompwralltoporbot => pcsaggcgcompwralltoporbot,
pcsaggfifordincomp0toporbot => pcsaggfifordincomp0toporbot,
pcsaggdelcondmet0toporbot => pcsaggdelcondmet0toporbot,
pcsagginsertincomplete0toporbot => pcsagginsertincomplete0toporbot,
pcsaggfifoovr0toporbot => pcsaggfifoovr0toporbot,
pcsagglatencycomp0toporbot => pcsagglatencycomp0toporbot,
pcsaggrxdatarstoporbot => pcsaggrxdatarstoporbot,
pcsaggrxcontrolrstoporbot => pcsaggrxcontrolrstoporbot,
pcs8grxdetectvalid => pcs8grxdetectvalid,
pcs8gpmarxfound => pcs8gpmarxfound,
pcs8ggen2ngen1 => pcs8ggen2ngen1,
pcs8gpowerstatetransitiondone => pcs8gpowerstatetransitiondone,
ppmcntlatch => ppmcntlatch,
pldhclkout => pldhclkout,
aggscanmoden => aggscanmoden,
aggscanshiftn => aggscanshiftn,
aggrefclkdig => aggrefclkdig,
pmaoffcalen => pmaoffcalen,
pmafrefout => pmafrefout,
pmaclklowout => pmaclklowout
);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
entity stratixv_hssi_common_pld_pcs_interface is
generic (
lpm_type : string := "stratixv_hssi_common_pld_pcs_interface";
data_source : string := "pld";
emsip_enable : string := "emsip_disable";
selectpcs : string := "eight_g_pcs"
);
port (
pldhardresetin : in std_logic;
pldscanmoden : in std_logic;
pldscanshiftn : in std_logic;
pldgen3refclkdig : in std_logic;
pld10grefclkdig : in std_logic;
pld8grefclkdig : in std_logic;
pldaggrefclkdig : in std_logic;
pldpcspmaifrefclkdig : in std_logic;
pldrate : in std_logic_vector(1 downto 0);
pldeidleinfersel : in std_logic_vector(2 downto 0);
pld8gsoftresetallhssi : in std_logic;
pld8gplniotri : in std_logic;
pld8gprbsciden : in std_logic;
pld8gltr : in std_logic;
pld8gtxelecidle : in std_logic;
pld8gtxdetectrxloopback : in std_logic;
pld8gtxdeemph : in std_logic;
pld8gtxmargin : in std_logic_vector(2 downto 0);
pld8gtxswing : in std_logic;
pld8grxpolarity : in std_logic;
pld8gpowerdown : in std_logic_vector(1 downto 0);
pldgen3currentcoeff : in std_logic_vector(17 downto 0);
pldgen3currentrxpreset : in std_logic_vector(2 downto 0);
pcs10gtestdata : in std_logic_vector(19 downto 0);
pcs8gchnltestbusout : in std_logic_vector(9 downto 0);
pcs8grxvalid : in std_logic;
pcs8grxelecidle : in std_logic;
pcs8grxstatus : in std_logic_vector(2 downto 0);
pcs8gphystatus : in std_logic;
pldhclkin : in std_logic;
pcsgen3pldasyncstatus : in std_logic_vector(5 downto 0);
pcsgen3testout : in std_logic_vector(19 downto 0);
emsippcsreset : in std_logic_vector(2 downto 0);
emsippcsctrl : in std_logic_vector(38 downto 0);
pmafref : in std_logic;
pmaclklow : in std_logic;
pmaoffcaldone : in std_logic;
pldoffcalenin : in std_logic;
pcsgen3masktxpll : in std_logic;
rcomemsip : in std_logic;
rcomhipena : in std_logic;
rcomblocksel : in std_logic_vector(1 downto 0);
pldtestdata : out std_logic_vector(19 downto 0);
pld8grxvalid : out std_logic;
pld8grxelecidle : out std_logic;
pld8grxstatus : out std_logic_vector(2 downto 0);
pld8gphystatus : out std_logic;
pldgen3pldasyncstatus : out std_logic_vector(5 downto 0);
pcs10ghardresetn : out std_logic;
pcs10gscanmoden : out std_logic;
pcs10gscanshiftn : out std_logic;
pcs10grefclkdig : out std_logic;
pcs8ghardreset : out std_logic;
pcs8gsoftresetallhssi : out std_logic;
pcs8gplniotri : out std_logic;
pcs8gscanmoden : out std_logic;
pcs8gscanshiftn : out std_logic;
pcs8grefclkdig : out std_logic;
pcs8gprbsciden : out std_logic;
pcs8gltr : out std_logic;
pcs8gtxelecidle : out std_logic;
pcs8gtxdetectrxloopback : out std_logic;
pcs8gtxdeemph : out std_logic;
pcs8gtxmargin : out std_logic_vector(2 downto 0);
pcs8gtxswing : out std_logic;
pcs8grxpolarity : out std_logic;
pcs8grate : out std_logic;
pcs8gpowerdown : out std_logic_vector(1 downto 0);
pcs8geidleinfersel : out std_logic_vector(2 downto 0);
pcsgen3pcsdigclk : out std_logic;
pcsgen3rate : out std_logic_vector(1 downto 0);
pcsgen3eidleinfersel : out std_logic_vector(2 downto 0);
pcsgen3scanmoden : out std_logic;
pcsgen3scanshiftn : out std_logic;
pcsgen3pldltr : out std_logic;
pldhardresetout : out std_logic;
pcsgen3currentcoeff : out std_logic_vector(17 downto 0);
pcsgen3currentrxpreset : out std_logic_vector(2 downto 0);
pcsaggrefclkdig : out std_logic;
pcspcspmaifrefclkdig : out std_logic;
pcsaggscanmoden : out std_logic;
pcsaggscanshiftn : out std_logic;
pcspcspmaifscanmoden : out std_logic;
pcspcspmaifscanshiftn : out std_logic;
emsippcsclkout : out std_logic_vector(2 downto 0);
emsippcsstatus : out std_logic_vector(13 downto 0);
pldfref : out std_logic;
pldclklow : out std_logic;
emsipenabledusermode : out std_logic;
pldoffcalenout : out std_logic;
pldoffcaldone : out std_logic;
pldgen3masktxpll : out std_logic
);
end stratixv_hssi_common_pld_pcs_interface;
architecture behavior of stratixv_hssi_common_pld_pcs_interface is
component stratixv_hssi_common_pld_pcs_interface_encrypted
generic (
lpm_type : string := "stratixv_hssi_common_pld_pcs_interface";
data_source : string := "pld";
emsip_enable : string := "emsip_disable";
selectpcs : string := "eight_g_pcs"
);
port (
pldhardresetin : in std_logic;
pldscanmoden : in std_logic;
pldscanshiftn : in std_logic;
pldgen3refclkdig : in std_logic;
pld10grefclkdig : in std_logic;
pld8grefclkdig : in std_logic;
pldaggrefclkdig : in std_logic;
pldpcspmaifrefclkdig : in std_logic;
pldrate : in std_logic_vector(1 downto 0);
pldeidleinfersel : in std_logic_vector(2 downto 0);
pld8gsoftresetallhssi : in std_logic;
pld8gplniotri : in std_logic;
pld8gprbsciden : in std_logic;
pld8gltr : in std_logic;
pld8gtxelecidle : in std_logic;
pld8gtxdetectrxloopback : in std_logic;
pld8gtxdeemph : in std_logic;
pld8gtxmargin : in std_logic_vector(2 downto 0);
pld8gtxswing : in std_logic;
pld8grxpolarity : in std_logic;
pld8gpowerdown : in std_logic_vector(1 downto 0);
pldgen3currentcoeff : in std_logic_vector(17 downto 0);
pldgen3currentrxpreset : in std_logic_vector(2 downto 0);
pcs10gtestdata : in std_logic_vector(19 downto 0);
pcs8gchnltestbusout : in std_logic_vector(9 downto 0);
pcs8grxvalid : in std_logic;
pcs8grxelecidle : in std_logic;
pcs8grxstatus : in std_logic_vector(2 downto 0);
pcs8gphystatus : in std_logic;
pldhclkin : in std_logic;
pcsgen3pldasyncstatus : in std_logic_vector(5 downto 0);
pcsgen3testout : in std_logic_vector(19 downto 0);
emsippcsreset : in std_logic_vector(2 downto 0);
emsippcsctrl : in std_logic_vector(38 downto 0);
pmafref : in std_logic;
pmaclklow : in std_logic;
pmaoffcaldone : in std_logic;
pldoffcalenin : in std_logic;
pcsgen3masktxpll : in std_logic;
rcomemsip : in std_logic;
rcomhipena : in std_logic;
rcomblocksel : in std_logic_vector(1 downto 0);
pldtestdata : out std_logic_vector(19 downto 0);
pld8grxvalid : out std_logic;
pld8grxelecidle : out std_logic;
pld8grxstatus : out std_logic_vector(2 downto 0);
pld8gphystatus : out std_logic;
pldgen3pldasyncstatus : out std_logic_vector(5 downto 0);
pcs10ghardresetn : out std_logic;
pcs10gscanmoden : out std_logic;
pcs10gscanshiftn : out std_logic;
pcs10grefclkdig : out std_logic;
pcs8ghardreset : out std_logic;
pcs8gsoftresetallhssi : out std_logic;
pcs8gplniotri : out std_logic;
pcs8gscanmoden : out std_logic;
pcs8gscanshiftn : out std_logic;
pcs8grefclkdig : out std_logic;
pcs8gprbsciden : out std_logic;
pcs8gltr : out std_logic;
pcs8gtxelecidle : out std_logic;
pcs8gtxdetectrxloopback : out std_logic;
pcs8gtxdeemph : out std_logic;
pcs8gtxmargin : out std_logic_vector(2 downto 0);
pcs8gtxswing : out std_logic;
pcs8grxpolarity : out std_logic;
pcs8grate : out std_logic;
pcs8gpowerdown : out std_logic_vector(1 downto 0);
pcs8geidleinfersel : out std_logic_vector(2 downto 0);
pcsgen3pcsdigclk : out std_logic;
pcsgen3rate : out std_logic_vector(1 downto 0);
pcsgen3eidleinfersel : out std_logic_vector(2 downto 0);
pcsgen3scanmoden : out std_logic;
pcsgen3scanshiftn : out std_logic;
pcsgen3pldltr : out std_logic;
pldhardresetout : out std_logic;
pcsgen3currentcoeff : out std_logic_vector(17 downto 0);
pcsgen3currentrxpreset : out std_logic_vector(2 downto 0);
pcsaggrefclkdig : out std_logic;
pcspcspmaifrefclkdig : out std_logic;
pcsaggscanmoden : out std_logic;
pcsaggscanshiftn : out std_logic;
pcspcspmaifscanmoden : out std_logic;
pcspcspmaifscanshiftn : out std_logic;
emsippcsclkout : out std_logic_vector(2 downto 0);
emsippcsstatus : out std_logic_vector(13 downto 0);
pldfref : out std_logic;
pldclklow : out std_logic;
emsipenabledusermode : out std_logic;
pldoffcalenout : out std_logic;
pldoffcaldone : out std_logic;
pldgen3masktxpll : out std_logic
);
end component;
begin
inst : stratixv_hssi_common_pld_pcs_interface_encrypted
generic map (
lpm_type => lpm_type,
data_source => data_source,
emsip_enable => emsip_enable,
selectpcs => selectpcs
)
port map (
pldhardresetin => pldhardresetin,
pldscanmoden => pldscanmoden,
pldscanshiftn => pldscanshiftn,
pldgen3refclkdig => pldgen3refclkdig,
pld10grefclkdig => pld10grefclkdig,
pld8grefclkdig => pld8grefclkdig,
pldaggrefclkdig => pldaggrefclkdig,
pldpcspmaifrefclkdig => pldpcspmaifrefclkdig,
pldrate => pldrate,
pldeidleinfersel => pldeidleinfersel,
pld8gsoftresetallhssi => pld8gsoftresetallhssi,
pld8gplniotri => pld8gplniotri,
pld8gprbsciden => pld8gprbsciden,
pld8gltr => pld8gltr,
pld8gtxelecidle => pld8gtxelecidle,
pld8gtxdetectrxloopback => pld8gtxdetectrxloopback,
pld8gtxdeemph => pld8gtxdeemph,
pld8gtxmargin => pld8gtxmargin,
pld8gtxswing => pld8gtxswing,
pld8grxpolarity => pld8grxpolarity,
pld8gpowerdown => pld8gpowerdown,
pldgen3currentcoeff => pldgen3currentcoeff,
pldgen3currentrxpreset => pldgen3currentrxpreset,
pcs10gtestdata => pcs10gtestdata,
pcs8gchnltestbusout => pcs8gchnltestbusout,
pcs8grxvalid => pcs8grxvalid,
pcs8grxelecidle => pcs8grxelecidle,
pcs8grxstatus => pcs8grxstatus,
pcs8gphystatus => pcs8gphystatus,
pldhclkin => pldhclkin,
pcsgen3pldasyncstatus => pcsgen3pldasyncstatus,
pcsgen3testout => pcsgen3testout,
emsippcsreset => emsippcsreset,
emsippcsctrl => emsippcsctrl,
pmafref => pmafref,
pmaclklow => pmaclklow,
pmaoffcaldone => pmaoffcaldone,
pldoffcalenin => pldoffcalenin,
pcsgen3masktxpll => pcsgen3masktxpll,
rcomemsip => rcomemsip,
rcomhipena => rcomhipena,
rcomblocksel => rcomblocksel,
pldtestdata => pldtestdata,
pld8grxvalid => pld8grxvalid,
pld8grxelecidle => pld8grxelecidle,
pld8grxstatus => pld8grxstatus,
pld8gphystatus => pld8gphystatus,
pldgen3pldasyncstatus => pldgen3pldasyncstatus,
pcs10ghardresetn => pcs10ghardresetn,
pcs10gscanmoden => pcs10gscanmoden,
pcs10gscanshiftn => pcs10gscanshiftn,
pcs10grefclkdig => pcs10grefclkdig,
pcs8ghardreset => pcs8ghardreset,
pcs8gsoftresetallhssi => pcs8gsoftresetallhssi,
pcs8gplniotri => pcs8gplniotri,
pcs8gscanmoden => pcs8gscanmoden,
pcs8gscanshiftn => pcs8gscanshiftn,
pcs8grefclkdig => pcs8grefclkdig,
pcs8gprbsciden => pcs8gprbsciden,
pcs8gltr => pcs8gltr,
pcs8gtxelecidle => pcs8gtxelecidle,
pcs8gtxdetectrxloopback => pcs8gtxdetectrxloopback,
pcs8gtxdeemph => pcs8gtxdeemph,
pcs8gtxmargin => pcs8gtxmargin,
pcs8gtxswing => pcs8gtxswing,
pcs8grxpolarity => pcs8grxpolarity,
pcs8grate => pcs8grate,
pcs8gpowerdown => pcs8gpowerdown,
pcs8geidleinfersel => pcs8geidleinfersel,
pcsgen3pcsdigclk => pcsgen3pcsdigclk,
pcsgen3rate => pcsgen3rate,
pcsgen3eidleinfersel => pcsgen3eidleinfersel,
pcsgen3scanmoden => pcsgen3scanmoden,
pcsgen3scanshiftn => pcsgen3scanshiftn,
pcsgen3pldltr => pcsgen3pldltr,
pldhardresetout => pldhardresetout,
pcsgen3currentcoeff => pcsgen3currentcoeff,
pcsgen3currentrxpreset => pcsgen3currentrxpreset,
pcsaggrefclkdig => pcsaggrefclkdig,
pcspcspmaifrefclkdig => pcspcspmaifrefclkdig,
pcsaggscanmoden => pcsaggscanmoden,
pcsaggscanshiftn => pcsaggscanshiftn,
pcspcspmaifscanmoden => pcspcspmaifscanmoden,
pcspcspmaifscanshiftn => pcspcspmaifscanshiftn,
emsippcsclkout => emsippcsclkout,
emsippcsstatus => emsippcsstatus,
pldfref => pldfref,
pldclklow => pldclklow,
emsipenabledusermode => emsipenabledusermode,
pldoffcalenout => pldoffcalenout,
pldoffcaldone => pldoffcaldone,
pldgen3masktxpll => pldgen3masktxpll
);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
entity stratixv_hssi_rx_pcs_pma_interface is
generic (
lpm_type : string := "stratixv_hssi_rx_pcs_pma_interface";
clkslip_sel : string := "pld";
prot_mode : string := "other_protocols";
selectpcs : string := "eight_g_pcs"
);
port (
clockinfrompma : in std_logic;
datainfrompma : in std_logic_vector(39 downto 0);
pmasigdet : in std_logic;
pmasignalok : in std_logic;
pcs10grxclkiqout : in std_logic;
pcsgen3rxclkiqout : in std_logic;
pcs8grxclkiqout : in std_logic;
pcs8grxclkslip : in std_logic;
pmaclkdiv33txorrxin : in std_logic;
pmarxplllockin : in std_logic;
pldrxpmarstb : in std_logic;
pldrxclkslip : in std_logic;
rrxblocksel : in std_logic_vector(1 downto 0);
rrxclkslipsel : in std_logic;
pmarxclkslip : out std_logic;
pmarxclkout : out std_logic;
clkoutto10gpcs : out std_logic;
dataoutto10gpcs : out std_logic_vector(39 downto 0);
pcs10gsignalok : out std_logic;
clockouttogen3pcs : out std_logic;
dataouttogen3pcs : out std_logic_vector(31 downto 0);
pcsgen3pmasignaldet : out std_logic;
clockoutto8gpcs : out std_logic;
dataoutto8gpcs : out std_logic_vector(19 downto 0);
pcs8gsigdetni : out std_logic;
pmaclkdiv33txorrxout : out std_logic;
pcs10gclkdiv33txorrx : out std_logic;
pmarxpmarstb : out std_logic;
pmarxplllockout : out std_logic
);
end stratixv_hssi_rx_pcs_pma_interface;
architecture behavior of stratixv_hssi_rx_pcs_pma_interface is
component stratixv_hssi_rx_pcs_pma_interface_encrypted
generic (
lpm_type : string := "stratixv_hssi_rx_pcs_pma_interface";
clkslip_sel : string := "pld";
prot_mode : string := "other_protocols";
selectpcs : string := "eight_g_pcs"
);
port (
clockinfrompma : in std_logic;
datainfrompma : in std_logic_vector(39 downto 0);
pmasigdet : in std_logic;
pmasignalok : in std_logic;
pcs10grxclkiqout : in std_logic;
pcsgen3rxclkiqout : in std_logic;
pcs8grxclkiqout : in std_logic;
pcs8grxclkslip : in std_logic;
pmaclkdiv33txorrxin : in std_logic;
pmarxplllockin : in std_logic;
pldrxpmarstb : in std_logic;
pldrxclkslip : in std_logic;
rrxblocksel : in std_logic_vector(1 downto 0);
rrxclkslipsel : in std_logic;
pmarxclkslip : out std_logic;
pmarxclkout : out std_logic;
clkoutto10gpcs : out std_logic;
dataoutto10gpcs : out std_logic_vector(39 downto 0);
pcs10gsignalok : out std_logic;
clockouttogen3pcs : out std_logic;
dataouttogen3pcs : out std_logic_vector(31 downto 0);
pcsgen3pmasignaldet : out std_logic;
clockoutto8gpcs : out std_logic;
dataoutto8gpcs : out std_logic_vector(19 downto 0);
pcs8gsigdetni : out std_logic;
pmaclkdiv33txorrxout : out std_logic;
pcs10gclkdiv33txorrx : out std_logic;
pmarxpmarstb : out std_logic;
pmarxplllockout : out std_logic
);
end component;
begin
inst : stratixv_hssi_rx_pcs_pma_interface_encrypted
generic map (
lpm_type => lpm_type,
clkslip_sel => clkslip_sel,
prot_mode => prot_mode,
selectpcs => selectpcs
)
port map (
clockinfrompma => clockinfrompma,
datainfrompma => datainfrompma,
pmasigdet => pmasigdet,
pmasignalok => pmasignalok,
pcs10grxclkiqout => pcs10grxclkiqout,
pcsgen3rxclkiqout => pcsgen3rxclkiqout,
pcs8grxclkiqout => pcs8grxclkiqout,
pcs8grxclkslip => pcs8grxclkslip,
pmaclkdiv33txorrxin => pmaclkdiv33txorrxin,
pmarxplllockin => pmarxplllockin,
pldrxpmarstb => pldrxpmarstb,
pldrxclkslip => pldrxclkslip,
rrxblocksel => rrxblocksel,
rrxclkslipsel => rrxclkslipsel,
pmarxclkslip => pmarxclkslip,
pmarxclkout => pmarxclkout,
clkoutto10gpcs => clkoutto10gpcs,
dataoutto10gpcs => dataoutto10gpcs,
pcs10gsignalok => pcs10gsignalok,
clockouttogen3pcs => clockouttogen3pcs,
dataouttogen3pcs => dataouttogen3pcs,
pcsgen3pmasignaldet => pcsgen3pmasignaldet,
clockoutto8gpcs => clockoutto8gpcs,
dataoutto8gpcs => dataoutto8gpcs,
pcs8gsigdetni => pcs8gsigdetni,
pmaclkdiv33txorrxout => pmaclkdiv33txorrxout,
pcs10gclkdiv33txorrx => pcs10gclkdiv33txorrx,
pmarxpmarstb => pmarxpmarstb,
pmarxplllockout => pmarxplllockout
);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
entity stratixv_hssi_rx_pld_pcs_interface is
generic (
lpm_type : string := "stratixv_hssi_rx_pld_pcs_interface";
data_source : string := "pld";
is_10g_0ppm : string := "false";
is_8g_0ppm : string := "false";
selectpcs : string := "eight_g_pcs"
);
port (
pld10grxpldclk : in std_logic;
pld10grxpldrstn : in std_logic;
pld10grxalignen : in std_logic;
pld10grxalignclr : in std_logic;
pld10grxrden : in std_logic;
pld10grxdispclr : in std_logic;
pld10grxclrerrblkcnt : in std_logic;
pld10grxclrbercount : in std_logic;
pld10grxprbserrclr : in std_logic;
pld10grxbitslip : in std_logic;
pld8grxurstpma : in std_logic;
pld8grxurstpcs : in std_logic;
pld8gcmpfifourst : in std_logic;
pld8gphfifourstrx : in std_logic;
pld8gencdt : in std_logic;
pld8ga1a2size : in std_logic;
pld8gbitslip : in std_logic;
pld8grdenablermf : in std_logic;
pld8gwrenablermf : in std_logic;
pld8gpldrxclk : in std_logic;
pld8gpolinvrx : in std_logic;
pld8gbitlocreven : in std_logic;
pld8gbytereven : in std_logic;
pld8gbytordpld : in std_logic;
pld8gwrdisablerx : in std_logic;
pld8grdenablerx : in std_logic;
pldgen3rxrstn : in std_logic;
pldrxclkslipin : in std_logic;
pld8gpldextrain : in std_logic_vector(3 downto 0);
clockinfrom10gpcs : in std_logic;
pcs10grxdatavalid : in std_logic;
datainfrom10gpcs : in std_logic_vector(63 downto 0);
pcs10grxcontrol : in std_logic_vector(9 downto 0);
pcs10grxempty : in std_logic;
pcs10grxpempty : in std_logic;
pcs10grxpfull : in std_logic;
pcs10grxoflwerr : in std_logic;
pcs10grxalignval : in std_logic;
pcs10grxblklock : in std_logic;
pcs10grxhiber : in std_logic;
pcs10grxframelock : in std_logic;
pcs10grxrdpossts : in std_logic;
pcs10grxrdnegsts : in std_logic;
pcs10grxskipins : in std_logic;
pcs10grxrxframe : in std_logic;
pcs10grxpyldins : in std_logic;
pcs10grxsyncerr : in std_logic;
pcs10grxscrmerr : in std_logic;
pcs10grxskiperr : in std_logic;
pcs10grxdiagerr : in std_logic;
pcs10grxsherr : in std_logic;
pcs10grxmfrmerr : in std_logic;
pcs10grxcrc32err : in std_logic;
pcs10grxdiagstatus : in std_logic_vector(1 downto 0);
datainfrom8gpcs : in std_logic_vector(63 downto 0);
clockinfrom8gpcs : in std_logic;
pcs8gbisterr : in std_logic;
pcs8grcvdclkpmab : in std_logic;
pcs8gsignaldetectout : in std_logic;
pcs8gbistdone : in std_logic;
pcs8grlvlt : in std_logic;
pcs8gfullrmf : in std_logic;
pcs8gemptyrmf : in std_logic;
pcs8gfullrx : in std_logic;
pcs8gemptyrx : in std_logic;
pcs8ga1a2k1k2flag : in std_logic_vector(3 downto 0);
pcs8gbyteordflag : in std_logic;
pcs8gwaboundary : in std_logic_vector(4 downto 0);
pcs8grxdatavalid : in std_logic_vector(3 downto 0);
pcs8grxsynchdr : in std_logic_vector(1 downto 0);
pcs8grxblkstart : in std_logic_vector(3 downto 0);
pmaclkdiv33txorrx : in std_logic;
emsippcsrxclkin : in std_logic_vector(2 downto 0);
emsippcsrxreset : in std_logic_vector(6 downto 0);
emsippcsrxctrl : in std_logic_vector(24 downto 0);
pmarxplllock : in std_logic;
pldrxpmarstbin : in std_logic;
rrxblocksel : in std_logic_vector(1 downto 0);
rrxemsip : in std_logic;
emsipenabledusermode : in std_logic;
pcs10grxfifoinsert : in std_logic;
pld8gsyncsmeninput : in std_logic;
pcs10grxfifodel : in std_logic;
dataouttopld : out std_logic_vector(63 downto 0);
pld10grxclkout : out std_logic;
pld10grxdatavalid : out std_logic;
pld10grxcontrol : out std_logic_vector(9 downto 0);
pld10grxempty : out std_logic;
pld10grxpempty : out std_logic;
pld10grxpfull : out std_logic;
pld10grxoflwerr : out std_logic;
pld10grxalignval : out std_logic;
pld10grxblklock : out std_logic;
pld10grxhiber : out std_logic;
pld10grxframelock : out std_logic;
pld10grxrdpossts : out std_logic;
pld10grxrdnegsts : out std_logic;
pld10grxskipins : out std_logic;
pld10grxrxframe : out std_logic;
pld10grxpyldins : out std_logic;
pld10grxsyncerr : out std_logic;
pld10grxscrmerr : out std_logic;
pld10grxskiperr : out std_logic;
pld10grxdiagerr : out std_logic;
pld10grxsherr : out std_logic;
pld10grxmfrmerr : out std_logic;
pld10grxcrc32err : out std_logic;
pld10grxdiagstatus : out std_logic_vector(1 downto 0);
pld8grxclkout : out std_logic;
pld8gbisterr : out std_logic;
pld8grcvdclkpmab : out std_logic;
pld8gsignaldetectout : out std_logic;
pld8gbistdone : out std_logic;
pld8grlvlt : out std_logic;
pld8gfullrmf : out std_logic;
pld8gemptyrmf : out std_logic;
pld8gfullrx : out std_logic;
pld8gemptyrx : out std_logic;
pld8ga1a2k1k2flag : out std_logic_vector(3 downto 0);
pld8gbyteordflag : out std_logic;
pld8gwaboundary : out std_logic_vector(4 downto 0);
pld8grxdatavalid : out std_logic_vector(3 downto 0);
pld8grxsynchdr : out std_logic_vector(1 downto 0);
pld8grxblkstart : out std_logic_vector(3 downto 0);
pcs10grxpldclk : out std_logic;
pcs10grxpldrstn : out std_logic;
pcs10grxalignen : out std_logic;
pcs10grxalignclr : out std_logic;
pcs10grxrden : out std_logic;
pcs10grxdispclr : out std_logic;
pcs10grxclrerrblkcnt : out std_logic;
pcs10grxclrbercount : out std_logic;
pcs10grxprbserrclr : out std_logic;
pcs10grxbitslip : out std_logic;
pcs8grxurstpma : out std_logic;
pcs8grxurstpcs : out std_logic;
pcs8gcmpfifourst : out std_logic;
pcs8gphfifourstrx : out std_logic;
pcs8gencdt : out std_logic;
pcs8ga1a2size : out std_logic;
pcs8gbitslip : out std_logic;
pcs8grdenablermf : out std_logic;
pcs8gwrenablermf : out std_logic;
pcs8gpldrxclk : out std_logic;
pcs8gpolinvrx : out std_logic;
pcs8gbitlocreven : out std_logic;
pcs8gbytereven : out std_logic;
pcs8gbytordpld : out std_logic;
pcs8gwrdisablerx : out std_logic;
pcs8grdenablerx : out std_logic;
pcs8gpldextrain : out std_logic_vector(3 downto 0);
pcsgen3rxrstn : out std_logic;
pldrxclkslipout : out std_logic;
pldclkdiv33txorrx : out std_logic;
emsiprxdata : out std_logic_vector(63 downto 0);
emsippcsrxclkout : out std_logic_vector(3 downto 0);
emsippcsrxstatus : out std_logic_vector(63 downto 0);
pldrxpmarstbout : out std_logic;
pldrxplllock : out std_logic;
pld10grxfifodel : out std_logic;
pldrxiqclkout : out std_logic;
pld10grxfifoinsert : out std_logic;
pcs8gsyncsmenoutput : out std_logic
);
end stratixv_hssi_rx_pld_pcs_interface;
architecture behavior of stratixv_hssi_rx_pld_pcs_interface is
component stratixv_hssi_rx_pld_pcs_interface_encrypted
generic (
lpm_type : string := "stratixv_hssi_rx_pld_pcs_interface";
data_source : string := "pld";
is_10g_0ppm : string := "false";
is_8g_0ppm : string := "false";
selectpcs : string := "eight_g_pcs"
);
port (
pld10grxpldclk : in std_logic;
pld10grxpldrstn : in std_logic;
pld10grxalignen : in std_logic;
pld10grxalignclr : in std_logic;
pld10grxrden : in std_logic;
pld10grxdispclr : in std_logic;
pld10grxclrerrblkcnt : in std_logic;
pld10grxclrbercount : in std_logic;
pld10grxprbserrclr : in std_logic;
pld10grxbitslip : in std_logic;
pld8grxurstpma : in std_logic;
pld8grxurstpcs : in std_logic;
pld8gcmpfifourst : in std_logic;
pld8gphfifourstrx : in std_logic;
pld8gencdt : in std_logic;
pld8ga1a2size : in std_logic;
pld8gbitslip : in std_logic;
pld8grdenablermf : in std_logic;
pld8gwrenablermf : in std_logic;
pld8gpldrxclk : in std_logic;
pld8gpolinvrx : in std_logic;
pld8gbitlocreven : in std_logic;
pld8gbytereven : in std_logic;
pld8gbytordpld : in std_logic;
pld8gwrdisablerx : in std_logic;
pld8grdenablerx : in std_logic;
pldgen3rxrstn : in std_logic;
pldrxclkslipin : in std_logic;
pld8gpldextrain : in std_logic_vector(3 downto 0);
clockinfrom10gpcs : in std_logic;
pcs10grxdatavalid : in std_logic;
datainfrom10gpcs : in std_logic_vector(63 downto 0);
pcs10grxcontrol : in std_logic_vector(9 downto 0);
pcs10grxempty : in std_logic;
pcs10grxpempty : in std_logic;
pcs10grxpfull : in std_logic;
pcs10grxoflwerr : in std_logic;
pcs10grxalignval : in std_logic;
pcs10grxblklock : in std_logic;
pcs10grxhiber : in std_logic;
pcs10grxframelock : in std_logic;
pcs10grxrdpossts : in std_logic;
pcs10grxrdnegsts : in std_logic;
pcs10grxskipins : in std_logic;
pcs10grxrxframe : in std_logic;
pcs10grxpyldins : in std_logic;
pcs10grxsyncerr : in std_logic;
pcs10grxscrmerr : in std_logic;
pcs10grxskiperr : in std_logic;
pcs10grxdiagerr : in std_logic;
pcs10grxsherr : in std_logic;
pcs10grxmfrmerr : in std_logic;
pcs10grxcrc32err : in std_logic;
pcs10grxdiagstatus : in std_logic_vector(1 downto 0);
datainfrom8gpcs : in std_logic_vector(63 downto 0);
clockinfrom8gpcs : in std_logic;
pcs8gbisterr : in std_logic;
pcs8grcvdclkpmab : in std_logic;
pcs8gsignaldetectout : in std_logic;
pcs8gbistdone : in std_logic;
pcs8grlvlt : in std_logic;
pcs8gfullrmf : in std_logic;
pcs8gemptyrmf : in std_logic;
pcs8gfullrx : in std_logic;
pcs8gemptyrx : in std_logic;
pcs8ga1a2k1k2flag : in std_logic_vector(3 downto 0);
pcs8gbyteordflag : in std_logic;
pcs8gwaboundary : in std_logic_vector(4 downto 0);
pcs8grxdatavalid : in std_logic_vector(3 downto 0);
pcs8grxsynchdr : in std_logic_vector(1 downto 0);
pcs8grxblkstart : in std_logic_vector(3 downto 0);
pmaclkdiv33txorrx : in std_logic;
emsippcsrxclkin : in std_logic_vector(2 downto 0);
emsippcsrxreset : in std_logic_vector(6 downto 0);
emsippcsrxctrl : in std_logic_vector(24 downto 0);
pmarxplllock : in std_logic;
pldrxpmarstbin : in std_logic;
rrxblocksel : in std_logic_vector(1 downto 0);
rrxemsip : in std_logic;
emsipenabledusermode : in std_logic;
pcs10grxfifoinsert : in std_logic;
pld8gsyncsmeninput : in std_logic;
pcs10grxfifodel : in std_logic;
dataouttopld : out std_logic_vector(63 downto 0);
pld10grxclkout : out std_logic;
pld10grxdatavalid : out std_logic;
pld10grxcontrol : out std_logic_vector(9 downto 0);
pld10grxempty : out std_logic;
pld10grxpempty : out std_logic;
pld10grxpfull : out std_logic;
pld10grxoflwerr : out std_logic;
pld10grxalignval : out std_logic;
pld10grxblklock : out std_logic;
pld10grxhiber : out std_logic;
pld10grxframelock : out std_logic;
pld10grxrdpossts : out std_logic;
pld10grxrdnegsts : out std_logic;
pld10grxskipins : out std_logic;
pld10grxrxframe : out std_logic;
pld10grxpyldins : out std_logic;
pld10grxsyncerr : out std_logic;
pld10grxscrmerr : out std_logic;
pld10grxskiperr : out std_logic;
pld10grxdiagerr : out std_logic;
pld10grxsherr : out std_logic;
pld10grxmfrmerr : out std_logic;
pld10grxcrc32err : out std_logic;
pld10grxdiagstatus : out std_logic_vector(1 downto 0);
pld8grxclkout : out std_logic;
pld8gbisterr : out std_logic;
pld8grcvdclkpmab : out std_logic;
pld8gsignaldetectout : out std_logic;
pld8gbistdone : out std_logic;
pld8grlvlt : out std_logic;
pld8gfullrmf : out std_logic;
pld8gemptyrmf : out std_logic;
pld8gfullrx : out std_logic;
pld8gemptyrx : out std_logic;
pld8ga1a2k1k2flag : out std_logic_vector(3 downto 0);
pld8gbyteordflag : out std_logic;
pld8gwaboundary : out std_logic_vector(4 downto 0);
pld8grxdatavalid : out std_logic_vector(3 downto 0);
pld8grxsynchdr : out std_logic_vector(1 downto 0);
pld8grxblkstart : out std_logic_vector(3 downto 0);
pcs10grxpldclk : out std_logic;
pcs10grxpldrstn : out std_logic;
pcs10grxalignen : out std_logic;
pcs10grxalignclr : out std_logic;
pcs10grxrden : out std_logic;
pcs10grxdispclr : out std_logic;
pcs10grxclrerrblkcnt : out std_logic;
pcs10grxclrbercount : out std_logic;
pcs10grxprbserrclr : out std_logic;
pcs10grxbitslip : out std_logic;
pcs8grxurstpma : out std_logic;
pcs8grxurstpcs : out std_logic;
pcs8gcmpfifourst : out std_logic;
pcs8gphfifourstrx : out std_logic;
pcs8gencdt : out std_logic;
pcs8ga1a2size : out std_logic;
pcs8gbitslip : out std_logic;
pcs8grdenablermf : out std_logic;
pcs8gwrenablermf : out std_logic;
pcs8gpldrxclk : out std_logic;
pcs8gpolinvrx : out std_logic;
pcs8gbitlocreven : out std_logic;
pcs8gbytereven : out std_logic;
pcs8gbytordpld : out std_logic;
pcs8gwrdisablerx : out std_logic;
pcs8grdenablerx : out std_logic;
pcs8gpldextrain : out std_logic_vector(3 downto 0);
pcsgen3rxrstn : out std_logic;
pldrxclkslipout : out std_logic;
pldclkdiv33txorrx : out std_logic;
emsiprxdata : out std_logic_vector(63 downto 0);
emsippcsrxclkout : out std_logic_vector(3 downto 0);
emsippcsrxstatus : out std_logic_vector(63 downto 0);
pldrxpmarstbout : out std_logic;
pldrxplllock : out std_logic;
pld10grxfifodel : out std_logic;
pldrxiqclkout : out std_logic;
pld10grxfifoinsert : out std_logic;
pcs8gsyncsmenoutput : out std_logic
);
end component;
begin
inst : stratixv_hssi_rx_pld_pcs_interface_encrypted
generic map (
lpm_type => lpm_type,
data_source => data_source,
is_10g_0ppm => is_10g_0ppm,
is_8g_0ppm => is_8g_0ppm,
selectpcs => selectpcs
)
port map (
pld10grxpldclk => pld10grxpldclk,
pld10grxpldrstn => pld10grxpldrstn,
pld10grxalignen => pld10grxalignen,
pld10grxalignclr => pld10grxalignclr,
pld10grxrden => pld10grxrden,
pld10grxdispclr => pld10grxdispclr,
pld10grxclrerrblkcnt => pld10grxclrerrblkcnt,
pld10grxclrbercount => pld10grxclrbercount,
pld10grxprbserrclr => pld10grxprbserrclr,
pld10grxbitslip => pld10grxbitslip,
pld8grxurstpma => pld8grxurstpma,
pld8grxurstpcs => pld8grxurstpcs,
pld8gcmpfifourst => pld8gcmpfifourst,
pld8gphfifourstrx => pld8gphfifourstrx,
pld8gencdt => pld8gencdt,
pld8ga1a2size => pld8ga1a2size,
pld8gbitslip => pld8gbitslip,
pld8grdenablermf => pld8grdenablermf,
pld8gwrenablermf => pld8gwrenablermf,
pld8gpldrxclk => pld8gpldrxclk,
pld8gpolinvrx => pld8gpolinvrx,
pld8gbitlocreven => pld8gbitlocreven,
pld8gbytereven => pld8gbytereven,
pld8gbytordpld => pld8gbytordpld,
pld8gwrdisablerx => pld8gwrdisablerx,
pld8grdenablerx => pld8grdenablerx,
pldgen3rxrstn => pldgen3rxrstn,
pldrxclkslipin => pldrxclkslipin,
pld8gpldextrain => pld8gpldextrain,
clockinfrom10gpcs => clockinfrom10gpcs,
pcs10grxdatavalid => pcs10grxdatavalid,
datainfrom10gpcs => datainfrom10gpcs,
pcs10grxcontrol => pcs10grxcontrol,
pcs10grxempty => pcs10grxempty,
pcs10grxpempty => pcs10grxpempty,
pcs10grxpfull => pcs10grxpfull,
pcs10grxoflwerr => pcs10grxoflwerr,
pcs10grxalignval => pcs10grxalignval,
pcs10grxblklock => pcs10grxblklock,
pcs10grxhiber => pcs10grxhiber,
pcs10grxframelock => pcs10grxframelock,
pcs10grxrdpossts => pcs10grxrdpossts,
pcs10grxrdnegsts => pcs10grxrdnegsts,
pcs10grxskipins => pcs10grxskipins,
pcs10grxrxframe => pcs10grxrxframe,
pcs10grxpyldins => pcs10grxpyldins,
pcs10grxsyncerr => pcs10grxsyncerr,
pcs10grxscrmerr => pcs10grxscrmerr,
pcs10grxskiperr => pcs10grxskiperr,
pcs10grxdiagerr => pcs10grxdiagerr,
pcs10grxsherr => pcs10grxsherr,
pcs10grxmfrmerr => pcs10grxmfrmerr,
pcs10grxcrc32err => pcs10grxcrc32err,
pcs10grxdiagstatus => pcs10grxdiagstatus,
datainfrom8gpcs => datainfrom8gpcs,
clockinfrom8gpcs => clockinfrom8gpcs,
pcs8gbisterr => pcs8gbisterr,
pcs8grcvdclkpmab => pcs8grcvdclkpmab,
pcs8gsignaldetectout => pcs8gsignaldetectout,
pcs8gbistdone => pcs8gbistdone,
pcs8grlvlt => pcs8grlvlt,
pcs8gfullrmf => pcs8gfullrmf,
pcs8gemptyrmf => pcs8gemptyrmf,
pcs8gfullrx => pcs8gfullrx,
pcs8gemptyrx => pcs8gemptyrx,
pcs8ga1a2k1k2flag => pcs8ga1a2k1k2flag,
pcs8gbyteordflag => pcs8gbyteordflag,
pcs8gwaboundary => pcs8gwaboundary,
pcs8grxdatavalid => pcs8grxdatavalid,
pcs8grxsynchdr => pcs8grxsynchdr,
pcs8grxblkstart => pcs8grxblkstart,
pmaclkdiv33txorrx => pmaclkdiv33txorrx,
emsippcsrxclkin => emsippcsrxclkin,
emsippcsrxreset => emsippcsrxreset,
emsippcsrxctrl => emsippcsrxctrl,
pmarxplllock => pmarxplllock,
pldrxpmarstbin => pldrxpmarstbin,
rrxblocksel => rrxblocksel,
rrxemsip => rrxemsip,
emsipenabledusermode => emsipenabledusermode,
pcs10grxfifoinsert => pcs10grxfifoinsert,
pld8gsyncsmeninput => pld8gsyncsmeninput,
pcs10grxfifodel => pcs10grxfifodel,
dataouttopld => dataouttopld,
pld10grxclkout => pld10grxclkout,
pld10grxdatavalid => pld10grxdatavalid,
pld10grxcontrol => pld10grxcontrol,
pld10grxempty => pld10grxempty,
pld10grxpempty => pld10grxpempty,
pld10grxpfull => pld10grxpfull,
pld10grxoflwerr => pld10grxoflwerr,
pld10grxalignval => pld10grxalignval,
pld10grxblklock => pld10grxblklock,
pld10grxhiber => pld10grxhiber,
pld10grxframelock => pld10grxframelock,
pld10grxrdpossts => pld10grxrdpossts,
pld10grxrdnegsts => pld10grxrdnegsts,
pld10grxskipins => pld10grxskipins,
pld10grxrxframe => pld10grxrxframe,
pld10grxpyldins => pld10grxpyldins,
pld10grxsyncerr => pld10grxsyncerr,
pld10grxscrmerr => pld10grxscrmerr,
pld10grxskiperr => pld10grxskiperr,
pld10grxdiagerr => pld10grxdiagerr,
pld10grxsherr => pld10grxsherr,
pld10grxmfrmerr => pld10grxmfrmerr,
pld10grxcrc32err => pld10grxcrc32err,
pld10grxdiagstatus => pld10grxdiagstatus,
pld8grxclkout => pld8grxclkout,
pld8gbisterr => pld8gbisterr,
pld8grcvdclkpmab => pld8grcvdclkpmab,
pld8gsignaldetectout => pld8gsignaldetectout,
pld8gbistdone => pld8gbistdone,
pld8grlvlt => pld8grlvlt,
pld8gfullrmf => pld8gfullrmf,
pld8gemptyrmf => pld8gemptyrmf,
pld8gfullrx => pld8gfullrx,
pld8gemptyrx => pld8gemptyrx,
pld8ga1a2k1k2flag => pld8ga1a2k1k2flag,
pld8gbyteordflag => pld8gbyteordflag,
pld8gwaboundary => pld8gwaboundary,
pld8grxdatavalid => pld8grxdatavalid,
pld8grxsynchdr => pld8grxsynchdr,
pld8grxblkstart => pld8grxblkstart,
pcs10grxpldclk => pcs10grxpldclk,
pcs10grxpldrstn => pcs10grxpldrstn,
pcs10grxalignen => pcs10grxalignen,
pcs10grxalignclr => pcs10grxalignclr,
pcs10grxrden => pcs10grxrden,
pcs10grxdispclr => pcs10grxdispclr,
pcs10grxclrerrblkcnt => pcs10grxclrerrblkcnt,
pcs10grxclrbercount => pcs10grxclrbercount,
pcs10grxprbserrclr => pcs10grxprbserrclr,
pcs10grxbitslip => pcs10grxbitslip,
pcs8grxurstpma => pcs8grxurstpma,
pcs8grxurstpcs => pcs8grxurstpcs,
pcs8gcmpfifourst => pcs8gcmpfifourst,
pcs8gphfifourstrx => pcs8gphfifourstrx,
pcs8gencdt => pcs8gencdt,
pcs8ga1a2size => pcs8ga1a2size,
pcs8gbitslip => pcs8gbitslip,
pcs8grdenablermf => pcs8grdenablermf,
pcs8gwrenablermf => pcs8gwrenablermf,
pcs8gpldrxclk => pcs8gpldrxclk,
pcs8gpolinvrx => pcs8gpolinvrx,
pcs8gbitlocreven => pcs8gbitlocreven,
pcs8gbytereven => pcs8gbytereven,
pcs8gbytordpld => pcs8gbytordpld,
pcs8gwrdisablerx => pcs8gwrdisablerx,
pcs8grdenablerx => pcs8grdenablerx,
pcs8gpldextrain => pcs8gpldextrain,
pcsgen3rxrstn => pcsgen3rxrstn,
pldrxclkslipout => pldrxclkslipout,
pldclkdiv33txorrx => pldclkdiv33txorrx,
emsiprxdata => emsiprxdata,
emsippcsrxclkout => emsippcsrxclkout,
emsippcsrxstatus => emsippcsrxstatus,
pldrxpmarstbout => pldrxpmarstbout,
pldrxplllock => pldrxplllock,
pld10grxfifodel => pld10grxfifodel,
pldrxiqclkout => pldrxiqclkout,
pld10grxfifoinsert => pld10grxfifoinsert,
pcs8gsyncsmenoutput => pcs8gsyncsmenoutput
);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
entity stratixv_hssi_tx_pcs_pma_interface is
generic (
lpm_type : string := "stratixv_hssi_tx_pcs_pma_interface";
selectpcs : string := "eight_g_pcs"
);
port (
clockinfrompma : in std_logic;
datainfrom10gpcs : in std_logic_vector(39 downto 0);
pcs10gtxclkiqout : in std_logic;
pcsgen3txclkiqout : in std_logic;
datainfromgen3pcs : in std_logic_vector(31 downto 0);
pcs8gtxclkiqout : in std_logic;
datainfrom8gpcs : in std_logic_vector(19 downto 0);
pmaclkdiv33lcin : in std_logic;
pmatxlcplllockin : in std_logic;
pmatxcmuplllockin : in std_logic;
rtxblocksel : in std_logic_vector(1 downto 0);
pcsgen3gen3datasel : in std_logic;
pldtxpmasyncp : in std_logic;
dataouttopma : out std_logic_vector(39 downto 0);
pmatxclkout : out std_logic;
clockoutto10gpcs : out std_logic;
clockoutto8gpcs : out std_logic;
pmaclkdiv33lcout : out std_logic;
pcs10gclkdiv33lc : out std_logic;
pmatxlcplllockout : out std_logic;
pmatxcmuplllockout : out std_logic;
pmatxpmasyncp : out std_logic
);
end stratixv_hssi_tx_pcs_pma_interface;
architecture behavior of stratixv_hssi_tx_pcs_pma_interface is
component stratixv_hssi_tx_pcs_pma_interface_encrypted
generic (
lpm_type : string := "stratixv_hssi_tx_pcs_pma_interface";
selectpcs : string := "eight_g_pcs"
);
port (
clockinfrompma : in std_logic;
datainfrom10gpcs : in std_logic_vector(39 downto 0);
pcs10gtxclkiqout : in std_logic;
pcsgen3txclkiqout : in std_logic;
datainfromgen3pcs : in std_logic_vector(31 downto 0);
pcs8gtxclkiqout : in std_logic;
datainfrom8gpcs : in std_logic_vector(19 downto 0);
pmaclkdiv33lcin : in std_logic;
pmatxlcplllockin : in std_logic;
pmatxcmuplllockin : in std_logic;
rtxblocksel : in std_logic_vector(1 downto 0);
pcsgen3gen3datasel : in std_logic;
pldtxpmasyncp : in std_logic;
dataouttopma : out std_logic_vector(39 downto 0);
pmatxclkout : out std_logic;
clockoutto10gpcs : out std_logic;
clockoutto8gpcs : out std_logic;
pmaclkdiv33lcout : out std_logic;
pcs10gclkdiv33lc : out std_logic;
pmatxlcplllockout : out std_logic;
pmatxcmuplllockout : out std_logic;
pmatxpmasyncp : out std_logic
);
end component;
begin
inst : stratixv_hssi_tx_pcs_pma_interface_encrypted
generic map (
lpm_type => lpm_type,
selectpcs => selectpcs
)
port map (
clockinfrompma => clockinfrompma,
datainfrom10gpcs => datainfrom10gpcs,
pcs10gtxclkiqout => pcs10gtxclkiqout,
pcsgen3txclkiqout => pcsgen3txclkiqout,
datainfromgen3pcs => datainfromgen3pcs,
pcs8gtxclkiqout => pcs8gtxclkiqout,
datainfrom8gpcs => datainfrom8gpcs,
pmaclkdiv33lcin => pmaclkdiv33lcin,
pmatxlcplllockin => pmatxlcplllockin,
pmatxcmuplllockin => pmatxcmuplllockin,
rtxblocksel => rtxblocksel,
pcsgen3gen3datasel => pcsgen3gen3datasel,
pldtxpmasyncp => pldtxpmasyncp,
dataouttopma => dataouttopma,
pmatxclkout => pmatxclkout,
clockoutto10gpcs => clockoutto10gpcs,
clockoutto8gpcs => clockoutto8gpcs,
pmaclkdiv33lcout => pmaclkdiv33lcout,
pcs10gclkdiv33lc => pcs10gclkdiv33lc,
pmatxlcplllockout => pmatxlcplllockout,
pmatxcmuplllockout => pmatxcmuplllockout,
pmatxpmasyncp => pmatxpmasyncp
);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
entity stratixv_hssi_tx_pld_pcs_interface is
generic (
lpm_type : string := "stratixv_hssi_tx_pld_pcs_interface";
data_source : string := "pld";
is_10g_0ppm : string := "false";
is_8g_0ppm : string := "false"
);
port (
datainfrompld : in std_logic_vector(63 downto 0);
pld10gtxpldclk : in std_logic;
pld10gtxpldrstn : in std_logic;
pld10gtxdatavalid : in std_logic;
pld10gtxcontrol : in std_logic_vector(8 downto 0);
pld10gtxbitslip : in std_logic_vector(6 downto 0);
pld10gtxdiagstatus : in std_logic_vector(1 downto 0);
pld10gtxwordslip : in std_logic;
pld10gtxbursten : in std_logic;
pld8gpldtxclk : in std_logic;
pld8gpolinvtx : in std_logic;
pld8grevloopbk : in std_logic;
pld8gwrenabletx : in std_logic;
pld8grddisabletx : in std_logic;
pld8gphfifoursttx : in std_logic;
pld8gtxboundarysel : in std_logic_vector(4 downto 0);
pld8gtxdatavalid : in std_logic_vector(3 downto 0);
pld8gtxsynchdr : in std_logic_vector(1 downto 0);
pld8gtxblkstart : in std_logic_vector(3 downto 0);
pldgen3txrstn : in std_logic;
pld8gtxurstpcs : in std_logic;
clockinfrom10gpcs : in std_logic;
pcs10gtxempty : in std_logic;
pcs10gtxpempty : in std_logic;
pcs10gtxpfull : in std_logic;
pcs10gtxfull : in std_logic;
pcs10gtxframe : in std_logic;
pcs10gtxburstenexe : in std_logic;
pcs10gtxwordslipexe : in std_logic;
pcs8gfulltx : in std_logic;
pcs8gemptytx : in std_logic;
clockinfrom8gpcs : in std_logic;
pmaclkdiv33lc : in std_logic;
emsiptxdata : in std_logic_vector(63 downto 0);
emsippcstxclkin : in std_logic_vector(2 downto 0);
emsippcstxreset : in std_logic_vector(5 downto 0);
emsippcstxctrl : in std_logic_vector(43 downto 0);
pmatxlcplllock : in std_logic;
pmatxcmuplllock : in std_logic;
pldtxpmarstbin : in std_logic;
pldlccmurstbin : in std_logic;
rtxemsip : in std_logic;
emsipenabledusermode : in std_logic;
pcs10gextraout : in std_logic_vector(3 downto 0);
pldtxpmasyncpin : in std_logic;
pcs10gtxfifoinsert : in std_logic;
pcs10gtxfifodel : in std_logic;
pld10gextrain : in std_logic_vector(3 downto 0);
pld10gtxclkout : out std_logic;
pld10gtxempty : out std_logic;
pld10gtxpempty : out std_logic;
pld10gtxpfull : out std_logic;
pld10gtxfull : out std_logic;
pld10gtxframe : out std_logic;
pld10gtxburstenexe : out std_logic;
pld10gtxwordslipexe : out std_logic;
pld8gfulltx : out std_logic;
pld8gemptytx : out std_logic;
pld8gtxclkout : out std_logic;
pcs10gtxpldclk : out std_logic;
pcs10gtxpldrstn : out std_logic;
pcs10gtxdatavalid : out std_logic;
dataoutto10gpcs : out std_logic_vector(63 downto 0);
pcs10gtxcontrol : out std_logic_vector(8 downto 0);
pcs10gtxbitslip : out std_logic_vector(6 downto 0);
pcs10gtxdiagstatus : out std_logic_vector(1 downto 0);
pcs10gtxwordslip : out std_logic;
pcs10gtxbursten : out std_logic;
pcs8gtxurstpcs : out std_logic;
dataoutto8gpcs : out std_logic_vector(43 downto 0);
pcs8gpldtxclk : out std_logic;
pcs8gpolinvtx : out std_logic;
pcs8grevloopbk : out std_logic;
pcs8gwrenabletx : out std_logic;
pcs8grddisabletx : out std_logic;
pcs8gphfifoursttx : out std_logic;
pcs8gtxboundarysel : out std_logic_vector(4 downto 0);
pcs8gtxdatavalid : out std_logic_vector(3 downto 0);
pcs8gtxsynchdr : out std_logic_vector(1 downto 0);
pcs8gtxblkstart : out std_logic_vector(3 downto 0);
pcsgen3txrstn : out std_logic;
pldclkdiv33lc : out std_logic;
emsippcstxclkout : out std_logic_vector(2 downto 0);
emsippcstxstatus : out std_logic_vector(16 downto 0);
pldtxpmarstbout : out std_logic;
pldlccmurstbout : out std_logic;
pldtxlcplllock : out std_logic;
pldtxcmuplllock : out std_logic;
pldtxiqclkout : out std_logic;
pcs10gextrain : out std_logic_vector(3 downto 0);
pld10gtxfifodel : out std_logic;
pldtxpmasyncpout : out std_logic;
pld10gtxfifoinsert : out std_logic;
pld10gextraout : out std_logic_vector(3 downto 0)
);
end stratixv_hssi_tx_pld_pcs_interface;
architecture behavior of stratixv_hssi_tx_pld_pcs_interface is
component stratixv_hssi_tx_pld_pcs_interface_encrypted
generic (
lpm_type : string := "stratixv_hssi_tx_pld_pcs_interface";
data_source : string := "pld";
is_10g_0ppm : string := "false";
is_8g_0ppm : string := "false"
);
port (
datainfrompld : in std_logic_vector(63 downto 0);
pld10gtxpldclk : in std_logic;
pld10gtxpldrstn : in std_logic;
pld10gtxdatavalid : in std_logic;
pld10gtxcontrol : in std_logic_vector(8 downto 0);
pld10gtxbitslip : in std_logic_vector(6 downto 0);
pld10gtxdiagstatus : in std_logic_vector(1 downto 0);
pld10gtxwordslip : in std_logic;
pld10gtxbursten : in std_logic;
pld8gpldtxclk : in std_logic;
pld8gpolinvtx : in std_logic;
pld8grevloopbk : in std_logic;
pld8gwrenabletx : in std_logic;
pld8grddisabletx : in std_logic;
pld8gphfifoursttx : in std_logic;
pld8gtxboundarysel : in std_logic_vector(4 downto 0);
pld8gtxdatavalid : in std_logic_vector(3 downto 0);
pld8gtxsynchdr : in std_logic_vector(1 downto 0);
pld8gtxblkstart : in std_logic_vector(3 downto 0);
pldgen3txrstn : in std_logic;
pld8gtxurstpcs : in std_logic;
clockinfrom10gpcs : in std_logic;
pcs10gtxempty : in std_logic;
pcs10gtxpempty : in std_logic;
pcs10gtxpfull : in std_logic;
pcs10gtxfull : in std_logic;
pcs10gtxframe : in std_logic;
pcs10gtxburstenexe : in std_logic;
pcs10gtxwordslipexe : in std_logic;
pcs8gfulltx : in std_logic;
pcs8gemptytx : in std_logic;
clockinfrom8gpcs : in std_logic;
pmaclkdiv33lc : in std_logic;
emsiptxdata : in std_logic_vector(63 downto 0);
emsippcstxclkin : in std_logic_vector(2 downto 0);
emsippcstxreset : in std_logic_vector(5 downto 0);
emsippcstxctrl : in std_logic_vector(43 downto 0);
pmatxlcplllock : in std_logic;
pmatxcmuplllock : in std_logic;
pldtxpmarstbin : in std_logic;
pldlccmurstbin : in std_logic;
rtxemsip : in std_logic;
emsipenabledusermode : in std_logic;
pcs10gextraout : in std_logic_vector(3 downto 0);
pldtxpmasyncpin : in std_logic;
pcs10gtxfifoinsert : in std_logic;
pcs10gtxfifodel : in std_logic;
pld10gextrain : in std_logic_vector(3 downto 0);
pld10gtxclkout : out std_logic;
pld10gtxempty : out std_logic;
pld10gtxpempty : out std_logic;
pld10gtxpfull : out std_logic;
pld10gtxfull : out std_logic;
pld10gtxframe : out std_logic;
pld10gtxburstenexe : out std_logic;
pld10gtxwordslipexe : out std_logic;
pld8gfulltx : out std_logic;
pld8gemptytx : out std_logic;
pld8gtxclkout : out std_logic;
pcs10gtxpldclk : out std_logic;
pcs10gtxpldrstn : out std_logic;
pcs10gtxdatavalid : out std_logic;
dataoutto10gpcs : out std_logic_vector(63 downto 0);
pcs10gtxcontrol : out std_logic_vector(8 downto 0);
pcs10gtxbitslip : out std_logic_vector(6 downto 0);
pcs10gtxdiagstatus : out std_logic_vector(1 downto 0);
pcs10gtxwordslip : out std_logic;
pcs10gtxbursten : out std_logic;
pcs8gtxurstpcs : out std_logic;
dataoutto8gpcs : out std_logic_vector(43 downto 0);
pcs8gpldtxclk : out std_logic;
pcs8gpolinvtx : out std_logic;
pcs8grevloopbk : out std_logic;
pcs8gwrenabletx : out std_logic;
pcs8grddisabletx : out std_logic;
pcs8gphfifoursttx : out std_logic;
pcs8gtxboundarysel : out std_logic_vector(4 downto 0);
pcs8gtxdatavalid : out std_logic_vector(3 downto 0);
pcs8gtxsynchdr : out std_logic_vector(1 downto 0);
pcs8gtxblkstart : out std_logic_vector(3 downto 0);
pcsgen3txrstn : out std_logic;
pldclkdiv33lc : out std_logic;
emsippcstxclkout : out std_logic_vector(2 downto 0);
emsippcstxstatus : out std_logic_vector(16 downto 0);
pldtxpmarstbout : out std_logic;
pldlccmurstbout : out std_logic;
pldtxlcplllock : out std_logic;
pldtxcmuplllock : out std_logic;
pldtxiqclkout : out std_logic;
pcs10gextrain : out std_logic_vector(3 downto 0);
pld10gtxfifodel : out std_logic;
pldtxpmasyncpout : out std_logic;
pld10gtxfifoinsert : out std_logic;
pld10gextraout : out std_logic_vector(3 downto 0)
);
end component;
begin
inst : stratixv_hssi_tx_pld_pcs_interface_encrypted
generic map (
lpm_type => lpm_type,
data_source => data_source,
is_10g_0ppm => is_10g_0ppm,
is_8g_0ppm => is_8g_0ppm
)
port map (
datainfrompld => datainfrompld,
pld10gtxpldclk => pld10gtxpldclk,
pld10gtxpldrstn => pld10gtxpldrstn,
pld10gtxdatavalid => pld10gtxdatavalid,
pld10gtxcontrol => pld10gtxcontrol,
pld10gtxbitslip => pld10gtxbitslip,
pld10gtxdiagstatus => pld10gtxdiagstatus,
pld10gtxwordslip => pld10gtxwordslip,
pld10gtxbursten => pld10gtxbursten,
pld8gpldtxclk => pld8gpldtxclk,
pld8gpolinvtx => pld8gpolinvtx,
pld8grevloopbk => pld8grevloopbk,
pld8gwrenabletx => pld8gwrenabletx,
pld8grddisabletx => pld8grddisabletx,
pld8gphfifoursttx => pld8gphfifoursttx,
pld8gtxboundarysel => pld8gtxboundarysel,
pld8gtxdatavalid => pld8gtxdatavalid,
pld8gtxsynchdr => pld8gtxsynchdr,
pld8gtxblkstart => pld8gtxblkstart,
pldgen3txrstn => pldgen3txrstn,
pld8gtxurstpcs => pld8gtxurstpcs,
clockinfrom10gpcs => clockinfrom10gpcs,
pcs10gtxempty => pcs10gtxempty,
pcs10gtxpempty => pcs10gtxpempty,
pcs10gtxpfull => pcs10gtxpfull,
pcs10gtxfull => pcs10gtxfull,
pcs10gtxframe => pcs10gtxframe,
pcs10gtxburstenexe => pcs10gtxburstenexe,
pcs10gtxwordslipexe => pcs10gtxwordslipexe,
pcs8gfulltx => pcs8gfulltx,
pcs8gemptytx => pcs8gemptytx,
clockinfrom8gpcs => clockinfrom8gpcs,
pmaclkdiv33lc => pmaclkdiv33lc,
emsiptxdata => emsiptxdata,
emsippcstxclkin => emsippcstxclkin,
emsippcstxreset => emsippcstxreset,
emsippcstxctrl => emsippcstxctrl,
pmatxlcplllock => pmatxlcplllock,
pmatxcmuplllock => pmatxcmuplllock,
pldtxpmarstbin => pldtxpmarstbin,
pldlccmurstbin => pldlccmurstbin,
rtxemsip => rtxemsip,
emsipenabledusermode => emsipenabledusermode,
pcs10gextraout => pcs10gextraout,
pldtxpmasyncpin => pldtxpmasyncpin,
pcs10gtxfifoinsert => pcs10gtxfifoinsert,
pcs10gtxfifodel => pcs10gtxfifodel,
pld10gextrain => pld10gextrain,
pld10gtxclkout => pld10gtxclkout,
pld10gtxempty => pld10gtxempty,
pld10gtxpempty => pld10gtxpempty,
pld10gtxpfull => pld10gtxpfull,
pld10gtxfull => pld10gtxfull,
pld10gtxframe => pld10gtxframe,
pld10gtxburstenexe => pld10gtxburstenexe,
pld10gtxwordslipexe => pld10gtxwordslipexe,
pld8gfulltx => pld8gfulltx,
pld8gemptytx => pld8gemptytx,
pld8gtxclkout => pld8gtxclkout,
pcs10gtxpldclk => pcs10gtxpldclk,
pcs10gtxpldrstn => pcs10gtxpldrstn,
pcs10gtxdatavalid => pcs10gtxdatavalid,
dataoutto10gpcs => dataoutto10gpcs,
pcs10gtxcontrol => pcs10gtxcontrol,
pcs10gtxbitslip => pcs10gtxbitslip,
pcs10gtxdiagstatus => pcs10gtxdiagstatus,
pcs10gtxwordslip => pcs10gtxwordslip,
pcs10gtxbursten => pcs10gtxbursten,
pcs8gtxurstpcs => pcs8gtxurstpcs,
dataoutto8gpcs => dataoutto8gpcs,
pcs8gpldtxclk => pcs8gpldtxclk,
pcs8gpolinvtx => pcs8gpolinvtx,
pcs8grevloopbk => pcs8grevloopbk,
pcs8gwrenabletx => pcs8gwrenabletx,
pcs8grddisabletx => pcs8grddisabletx,
pcs8gphfifoursttx => pcs8gphfifoursttx,
pcs8gtxboundarysel => pcs8gtxboundarysel,
pcs8gtxdatavalid => pcs8gtxdatavalid,
pcs8gtxsynchdr => pcs8gtxsynchdr,
pcs8gtxblkstart => pcs8gtxblkstart,
pcsgen3txrstn => pcsgen3txrstn,
pldclkdiv33lc => pldclkdiv33lc,
emsippcstxclkout => emsippcstxclkout,
emsippcstxstatus => emsippcstxstatus,
pldtxpmarstbout => pldtxpmarstbout,
pldlccmurstbout => pldlccmurstbout,
pldtxlcplllock => pldtxlcplllock,
pldtxcmuplllock => pldtxcmuplllock,
pldtxiqclkout => pldtxiqclkout,
pcs10gextrain => pcs10gextrain,
pld10gtxfifodel => pld10gtxfifodel,
pldtxpmasyncpout => pldtxpmasyncpout,
pld10gtxfifoinsert => pld10gtxfifoinsert,
pld10gextraout => pld10gextraout
);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
entity stratixv_hssi_10g_rx_pcs is
generic (
prot_mode : string := "disable_mode";
sup_mode : string := "full_mode";
dis_signal_ok : string := "dis_signal_ok_dis";
gb_rx_idwidth : string := "idwidth_32";
gb_rx_odwidth : string := "odwidth_66";
bit_reverse : string := "bit_reverse_dis";
gb_sel_mode : string := "internal";
lpbk_mode : string := "lpbk_dis";
test_mode : string := "test_off";
blksync_bypass : string := "blksync_bypass_dis";
blksync_pipeln : string := "blksync_pipeln_dis";
blksync_knum_sh_cnt_prelock : string := "int";
blksync_knum_sh_cnt_postlock : string := "int";
blksync_enum_invalid_sh_cnt : string := "int";
blksync_bitslip_wait_cnt : string := "int";
bitslip_wait_cnt_user : string := "int";
blksync_bitslip_type : string := "bitslip_comb";
blksync_bitslip_wait_type : string := "bitslip_match";
dispchk_bypass : string := "dispchk_bypass_dis";
dispchk_rd_level : string := "dispchk_rd_level_min";
dispchk_rd_level_user : string := "int";
dispchk_pipeln : string := "dispchk_pipeln_dis";
descrm_bypass : string := "descrm_bypass_en";
descrm_mode : string := "async";
frmsync_bypass : string := "frmsync_bypass_dis";
frmsync_pipeln : string := "frmsync_pipeln_dis";
frmsync_mfrm_length : string := "int";
frmsync_mfrm_length_user : string := "int";
frmsync_knum_sync : string := "int";
frmsync_enum_sync : string := "int";
frmsync_enum_scrm : string := "int";
frmsync_flag_type : string := "all_framing_words";
dec_64b66b_10g_mode : string := "dec_64b66b_10g_mode_en";
dec_64b66b_rxsm_bypass : string := "dec_64b66b_rxsm_bypass_dis";
rx_sm_bypass : string := "rx_sm_bypass_dis";
rx_sm_pipeln : string := "rx_sm_pipeln_dis";
rx_sm_hiber : string := "rx_sm_hiber_en";
ber_xus_timer_window : string := "int";
ber_bit_err_total_cnt : string := "int";
crcchk_bypass : string := "crcchk_bypass_dis";
crcchk_pipeln : string := "crcchk_pipeln_dis";
crcflag_pipeln : string := "crcflag_pipeln_dis";
crcchk_init : string := "crcchk_init_user_setting";
crcchk_init_user : bit_vector := B"11111111111111111111111111111111";
crcchk_inv : string := "crcchk_inv_dis";
force_align : string := "force_align_dis";
align_del : string := "align_del_en";
control_del : bit_vector := B"11110000";
rxfifo_mode : string := "phase_comp";
master_clk_sel : string := "master_rx_pma_clk";
rd_clk_sel : string := "rd_rx_pma_clk";
gbexp_clken : string := "gbexp_clk_dis";
prbs_clken : string := "prbs_clk_dis";
blksync_clken : string := "blksync_clk_dis";
dispchk_clken : string := "dispchk_clk_dis";
descrm_clken : string := "descrm_clk_dis";
frmsync_clken : string := "frmsync_clk_dis";
dec64b66b_clken : string := "dec64b66b_clk_dis";
ber_clken : string := "ber_clk_dis";
rand_clken : string := "rand_clk_dis";
crcchk_clken : string := "crcchk_clk_dis";
wrfifo_clken : string := "wrfifo_clk_dis";
rdfifo_clken : string := "rdfifo_clk_dis";
rxfifo_pempty : string := "pempty_default";
rxfifo_pfull : string := "pfull_default";
rxfifo_full : string := "full_default";
rxfifo_empty : string := "pempty_default";
bitslip_mode : string := "bitslip_dis";
fast_path : string := "fast_path_dis";
stretch_num_stages : string := "zero_stage";
stretch_en : string := "stretch_en";
iqtxrx_clkout_sel : string := "iq_rx_clk_out";
channel_number : integer := 0;
frmgen_diag_word : bit_vector := B"0000000000000000011001000000000000000000000000000000000000000000";
frmgen_scrm_word : bit_vector := B"0000000000000000001010000000000000000000000000000000000000000000";
frmgen_skip_word : bit_vector := B"0000000000000000000111100001111000011110000111100001111000011110";
frmgen_sync_word : bit_vector := B"0000000000000000011110001111011001111000111101100111100011110110";
test_bus_mode : string := "tx"
);
port (
bercount : out std_logic_vector(5 downto 0);
errorblockcount : out std_logic_vector(7 downto 0);
pcsstatus : out std_logic_vector(0 downto 0);
randomerrorcount : out std_logic_vector(15 downto 0);
prbserrorlatch : out std_logic_vector(0 downto 0);
txpmaclk : in std_logic_vector(0 downto 0);
rxpmaclk : in std_logic_vector(0 downto 0);
pmaclkdiv33txorrx : in std_logic_vector(0 downto 0);
rxpmadatavalid : in std_logic_vector(0 downto 0);
hardresetn : in std_logic_vector(0 downto 0);
rxpldclk : in std_logic_vector(0 downto 0);
rxpldrstn : in std_logic_vector(0 downto 0);
refclkdig : in std_logic_vector(0 downto 0);
rxalignen : in std_logic_vector(0 downto 0);
rxalignclr : in std_logic_vector(0 downto 0);
rxrden : in std_logic_vector(0 downto 0);
rxdisparityclr : in std_logic_vector(0 downto 0);
rxclrerrorblockcount : in std_logic_vector(0 downto 0);
rxclrbercount : in std_logic_vector(0 downto 0);
rxbitslip : in std_logic_vector(0 downto 0);
rxprbserrorclr : in std_logic_vector(0 downto 0);
rxclkout : out std_logic_vector(0 downto 0);
rxclkiqout : out std_logic_vector(0 downto 0);
rxdatavalid : out std_logic_vector(0 downto 0);
rxfifoempty : out std_logic_vector(0 downto 0);
rxfifopartialempty : out std_logic_vector(0 downto 0);
rxfifopartialfull : out std_logic_vector(0 downto 0);
rxfifofull : out std_logic_vector(0 downto 0);
rxalignval : out std_logic_vector(0 downto 0);
rxblocklock : out std_logic_vector(0 downto 0);
rxsyncheadererror : out std_logic_vector(0 downto 0);
rxhighber : out std_logic_vector(0 downto 0);
rxframelock : out std_logic_vector(0 downto 0);
rxrdpossts : out std_logic_vector(0 downto 0);
rxrdnegsts : out std_logic_vector(0 downto 0);
rxskipinserted : out std_logic_vector(0 downto 0);
rxrxframe : out std_logic_vector(0 downto 0);
rxpayloadinserted : out std_logic_vector(0 downto 0);
rxsyncworderror : out std_logic_vector(0 downto 0);
rxscramblererror : out std_logic_vector(0 downto 0);
rxskipworderror : out std_logic_vector(0 downto 0);
rxdiagnosticerror : out std_logic_vector(0 downto 0);
rxmetaframeerror : out std_logic_vector(0 downto 0);
rxcrc32error : out std_logic_vector(0 downto 0);
rxdiagnosticstatus : out std_logic_vector(1 downto 0);
rxdata : out std_logic_vector(63 downto 0);
rxcontrol : out std_logic_vector(9 downto 0);
accumdisparity : out std_logic_vector(8 downto 0);
loopbackdatain : in std_logic_vector(39 downto 0);
rxpmadata : in std_logic_vector(39 downto 0);
rxtestdata : out std_logic_vector(19 downto 0);
syncdatain : out std_logic_vector(0 downto 0)
);
end stratixv_hssi_10g_rx_pcs;
architecture behavior of stratixv_hssi_10g_rx_pcs is
component stratixv_hssi_10g_rx_pcs_encrypted
generic (
prot_mode : string := "disable_mode";
sup_mode : string := "full_mode";
dis_signal_ok : string := "dis_signal_ok_dis";
gb_rx_idwidth : string := "idwidth_32";
gb_rx_odwidth : string := "odwidth_66";
bit_reverse : string := "bit_reverse_dis";
gb_sel_mode : string := "internal";
lpbk_mode : string := "lpbk_dis";
test_mode : string := "test_off";
blksync_bypass : string := "blksync_bypass_dis";
blksync_pipeln : string := "blksync_pipeln_dis";
blksync_knum_sh_cnt_prelock : string := "int";
blksync_knum_sh_cnt_postlock : string := "int";
blksync_enum_invalid_sh_cnt : string := "int";
blksync_bitslip_wait_cnt : string := "int";
bitslip_wait_cnt_user : string := "int";
blksync_bitslip_type : string := "bitslip_comb";
blksync_bitslip_wait_type : string := "bitslip_match";
dispchk_bypass : string := "dispchk_bypass_dis";
dispchk_rd_level : string := "dispchk_rd_level_min";
dispchk_rd_level_user : string := "int";
dispchk_pipeln : string := "dispchk_pipeln_dis";
descrm_bypass : string := "descrm_bypass_en";
descrm_mode : string := "async";
frmsync_bypass : string := "frmsync_bypass_dis";
frmsync_pipeln : string := "frmsync_pipeln_dis";
frmsync_mfrm_length : string := "int";
frmsync_mfrm_length_user : string := "int";
frmsync_knum_sync : string := "int";
frmsync_enum_sync : string := "int";
frmsync_enum_scrm : string := "int";
frmsync_flag_type : string := "all_framing_words";
dec_64b66b_10g_mode : string := "dec_64b66b_10g_mode_en";
dec_64b66b_rxsm_bypass : string := "dec_64b66b_rxsm_bypass_dis";
rx_sm_bypass : string := "rx_sm_bypass_dis";
rx_sm_pipeln : string := "rx_sm_pipeln_dis";
rx_sm_hiber : string := "rx_sm_hiber_en";
ber_xus_timer_window : string := "int";
ber_bit_err_total_cnt : string := "int";
crcchk_bypass : string := "crcchk_bypass_dis";
crcchk_pipeln : string := "crcchk_pipeln_dis";
crcflag_pipeln : string := "crcflag_pipeln_dis";
crcchk_init : string := "crcchk_init_user_setting";
crcchk_init_user : bit_vector := B"11111111111111111111111111111111";
crcchk_inv : string := "crcchk_inv_dis";
force_align : string := "force_align_dis";
align_del : string := "align_del_en";
control_del : bit_vector := B"11110000";
rxfifo_mode : string := "phase_comp";
master_clk_sel : string := "master_rx_pma_clk";
rd_clk_sel : string := "rd_rx_pma_clk";
gbexp_clken : string := "gbexp_clk_dis";
prbs_clken : string := "prbs_clk_dis";
blksync_clken : string := "blksync_clk_dis";
dispchk_clken : string := "dispchk_clk_dis";
descrm_clken : string := "descrm_clk_dis";
frmsync_clken : string := "frmsync_clk_dis";
dec64b66b_clken : string := "dec64b66b_clk_dis";
ber_clken : string := "ber_clk_dis";
rand_clken : string := "rand_clk_dis";
crcchk_clken : string := "crcchk_clk_dis";
wrfifo_clken : string := "wrfifo_clk_dis";
rdfifo_clken : string := "rdfifo_clk_dis";
rxfifo_pempty : string := "pempty_default";
rxfifo_pfull : string := "pfull_default";
rxfifo_full : string := "full_default";
rxfifo_empty : string := "pempty_default";
bitslip_mode : string := "bitslip_dis";
fast_path : string := "fast_path_dis";
stretch_num_stages : string := "zero_stage";
stretch_en : string := "stretch_en";
iqtxrx_clkout_sel : string := "iq_rx_clk_out";
channel_number : integer := 0;
frmgen_diag_word : bit_vector := B"0000000000000000011001000000000000000000000000000000000000000000";
frmgen_scrm_word : bit_vector := B"0000000000000000001010000000000000000000000000000000000000000000";
frmgen_skip_word : bit_vector := B"0000000000000000000111100001111000011110000111100001111000011110";
frmgen_sync_word : bit_vector := B"0000000000000000011110001111011001111000111101100111100011110110";
test_bus_mode : string := "tx"
);
port (
bercount : out std_logic_vector(5 downto 0);
errorblockcount : out std_logic_vector(7 downto 0);
pcsstatus : out std_logic_vector(0 downto 0);
randomerrorcount : out std_logic_vector(15 downto 0);
prbserrorlatch : out std_logic_vector(0 downto 0);
txpmaclk : in std_logic_vector(0 downto 0);
rxpmaclk : in std_logic_vector(0 downto 0);
pmaclkdiv33txorrx : in std_logic_vector(0 downto 0);
rxpmadatavalid : in std_logic_vector(0 downto 0);
hardresetn : in std_logic_vector(0 downto 0);
rxpldclk : in std_logic_vector(0 downto 0);
rxpldrstn : in std_logic_vector(0 downto 0);
refclkdig : in std_logic_vector(0 downto 0);
rxalignen : in std_logic_vector(0 downto 0);
rxalignclr : in std_logic_vector(0 downto 0);
rxrden : in std_logic_vector(0 downto 0);
rxdisparityclr : in std_logic_vector(0 downto 0);
rxclrerrorblockcount : in std_logic_vector(0 downto 0);
rxclrbercount : in std_logic_vector(0 downto 0);
rxbitslip : in std_logic_vector(0 downto 0);
rxprbserrorclr : in std_logic_vector(0 downto 0);
rxclkout : out std_logic_vector(0 downto 0);
rxclkiqout : out std_logic_vector(0 downto 0);
rxdatavalid : out std_logic_vector(0 downto 0);
rxfifoempty : out std_logic_vector(0 downto 0);
rxfifopartialempty : out std_logic_vector(0 downto 0);
rxfifopartialfull : out std_logic_vector(0 downto 0);
rxfifofull : out std_logic_vector(0 downto 0);
rxalignval : out std_logic_vector(0 downto 0);
rxblocklock : out std_logic_vector(0 downto 0);
rxsyncheadererror : out std_logic_vector(0 downto 0);
rxhighber : out std_logic_vector(0 downto 0);
rxframelock : out std_logic_vector(0 downto 0);
rxrdpossts : out std_logic_vector(0 downto 0);
rxrdnegsts : out std_logic_vector(0 downto 0);
rxskipinserted : out std_logic_vector(0 downto 0);
rxrxframe : out std_logic_vector(0 downto 0);
rxpayloadinserted : out std_logic_vector(0 downto 0);
rxsyncworderror : out std_logic_vector(0 downto 0);
rxscramblererror : out std_logic_vector(0 downto 0);
rxskipworderror : out std_logic_vector(0 downto 0);
rxdiagnosticerror : out std_logic_vector(0 downto 0);
rxmetaframeerror : out std_logic_vector(0 downto 0);
rxcrc32error : out std_logic_vector(0 downto 0);
rxdiagnosticstatus : out std_logic_vector(1 downto 0);
rxdata : out std_logic_vector(63 downto 0);
rxcontrol : out std_logic_vector(9 downto 0);
accumdisparity : out std_logic_vector(8 downto 0);
loopbackdatain : in std_logic_vector(39 downto 0);
rxpmadata : in std_logic_vector(39 downto 0);
rxtestdata : out std_logic_vector(19 downto 0);
syncdatain : out std_logic_vector(0 downto 0)
);
end component;
begin
inst : stratixv_hssi_10g_rx_pcs_encrypted
generic map (
prot_mode => prot_mode,
sup_mode => sup_mode,
dis_signal_ok => dis_signal_ok,
gb_rx_idwidth => gb_rx_idwidth,
gb_rx_odwidth => gb_rx_odwidth,
bit_reverse => bit_reverse,
gb_sel_mode => gb_sel_mode,
lpbk_mode => lpbk_mode,
test_mode => test_mode,
blksync_bypass => blksync_bypass,
blksync_pipeln => blksync_pipeln,
blksync_knum_sh_cnt_prelock => blksync_knum_sh_cnt_prelock,
blksync_knum_sh_cnt_postlock => blksync_knum_sh_cnt_postlock,
blksync_enum_invalid_sh_cnt => blksync_enum_invalid_sh_cnt,
blksync_bitslip_wait_cnt => blksync_bitslip_wait_cnt,
bitslip_wait_cnt_user => bitslip_wait_cnt_user,
blksync_bitslip_type => blksync_bitslip_type,
blksync_bitslip_wait_type => blksync_bitslip_wait_type,
dispchk_bypass => dispchk_bypass,
dispchk_rd_level => dispchk_rd_level,
dispchk_rd_level_user => dispchk_rd_level_user,
dispchk_pipeln => dispchk_pipeln,
descrm_bypass => descrm_bypass,
descrm_mode => descrm_mode,
frmsync_bypass => frmsync_bypass,
frmsync_pipeln => frmsync_pipeln,
frmsync_mfrm_length => frmsync_mfrm_length,
frmsync_mfrm_length_user => frmsync_mfrm_length_user,
frmsync_knum_sync => frmsync_knum_sync,
frmsync_enum_sync => frmsync_enum_sync,
frmsync_enum_scrm => frmsync_enum_scrm,
frmsync_flag_type => frmsync_flag_type,
dec_64b66b_10g_mode => dec_64b66b_10g_mode,
dec_64b66b_rxsm_bypass => dec_64b66b_rxsm_bypass,
rx_sm_bypass => rx_sm_bypass,
rx_sm_pipeln => rx_sm_pipeln,
rx_sm_hiber => rx_sm_hiber,
ber_xus_timer_window => ber_xus_timer_window,
ber_bit_err_total_cnt => ber_bit_err_total_cnt,
crcchk_bypass => crcchk_bypass,
crcchk_pipeln => crcchk_pipeln,
crcflag_pipeln => crcflag_pipeln,
crcchk_init => crcchk_init,
crcchk_init_user => crcchk_init_user,
crcchk_inv => crcchk_inv,
force_align => force_align,
align_del => align_del,
control_del => control_del,
rxfifo_mode => rxfifo_mode,
master_clk_sel => master_clk_sel,
rd_clk_sel => rd_clk_sel,
gbexp_clken => gbexp_clken,
prbs_clken => prbs_clken,
blksync_clken => blksync_clken,
dispchk_clken => dispchk_clken,
descrm_clken => descrm_clken,
frmsync_clken => frmsync_clken,
dec64b66b_clken => dec64b66b_clken,
ber_clken => ber_clken,
rand_clken => rand_clken,
crcchk_clken => crcchk_clken,
wrfifo_clken => wrfifo_clken,
rdfifo_clken => rdfifo_clken,
rxfifo_pempty => rxfifo_pempty,
rxfifo_pfull => rxfifo_pfull,
rxfifo_full => rxfifo_full,
rxfifo_empty => rxfifo_empty,
bitslip_mode => bitslip_mode,
fast_path => fast_path,
stretch_num_stages => stretch_num_stages,
stretch_en => stretch_en,
iqtxrx_clkout_sel => iqtxrx_clkout_sel,
channel_number => channel_number,
frmgen_diag_word => frmgen_diag_word,
frmgen_scrm_word => frmgen_scrm_word,
frmgen_skip_word => frmgen_skip_word,
frmgen_sync_word => frmgen_sync_word,
test_bus_mode => test_bus_mode
)
port map (
bercount => bercount,
errorblockcount => errorblockcount,
pcsstatus => pcsstatus,
randomerrorcount => randomerrorcount,
prbserrorlatch => prbserrorlatch,
txpmaclk => txpmaclk,
rxpmaclk => rxpmaclk,
pmaclkdiv33txorrx => pmaclkdiv33txorrx,
rxpmadatavalid => rxpmadatavalid,
hardresetn => hardresetn,
rxpldclk => rxpldclk,
rxpldrstn => rxpldrstn,
refclkdig => refclkdig,
rxalignen => rxalignen,
rxalignclr => rxalignclr,
rxrden => rxrden,
rxdisparityclr => rxdisparityclr,
rxclrerrorblockcount => rxclrerrorblockcount,
rxclrbercount => rxclrbercount,
rxbitslip => rxbitslip,
rxprbserrorclr => rxprbserrorclr,
rxclkout => rxclkout,
rxclkiqout => rxclkiqout,
rxdatavalid => rxdatavalid,
rxfifoempty => rxfifoempty,
rxfifopartialempty => rxfifopartialempty,
rxfifopartialfull => rxfifopartialfull,
rxfifofull => rxfifofull,
rxalignval => rxalignval,
rxblocklock => rxblocklock,
rxsyncheadererror => rxsyncheadererror,
rxhighber => rxhighber,
rxframelock => rxframelock,
rxrdpossts => rxrdpossts,
rxrdnegsts => rxrdnegsts,
rxskipinserted => rxskipinserted,
rxrxframe => rxrxframe,
rxpayloadinserted => rxpayloadinserted,
rxsyncworderror => rxsyncworderror,
rxscramblererror => rxscramblererror,
rxskipworderror => rxskipworderror,
rxdiagnosticerror => rxdiagnosticerror,
rxmetaframeerror => rxmetaframeerror,
rxcrc32error => rxcrc32error,
rxdiagnosticstatus => rxdiagnosticstatus,
rxdata => rxdata,
rxcontrol => rxcontrol,
accumdisparity => accumdisparity,
loopbackdatain => loopbackdatain,
rxpmadata => rxpmadata,
rxtestdata => rxtestdata,
syncdatain => syncdatain
);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
entity stratixv_hssi_10g_tx_pcs is
generic (
prot_mode : string := "disable_mode";
sup_mode : string := "full_mode";
ctrl_plane_bonding : string := "individual";
master_clk_sel : string := "master_tx_pma_clk";
wr_clk_sel : string := "wr_tx_pma_clk";
wrfifo_clken : string := "wrfifo_clk_dis";
rdfifo_clken : string := "rdfifo_clk_dis";
frmgen_clken : string := "frmgen_clk_dis";
crcgen_clken : string := "crcgen_clk_dis";
enc64b66b_txsm_clken : string := "enc64b66b_txsm_clk_dis";
scrm_clken : string := "scrm_clk_dis";
dispgen_clken : string := "dispgen_clk_dis";
prbs_clken : string := "prbs_clk_dis";
sqwgen_clken : string := "sqwgen_clk_dis";
gbred_clken : string := "gbred_clk_dis";
gb_tx_idwidth : string := "idwidth_50";
gb_tx_odwidth : string := "odwidth_32";
txfifo_mode : string := "phase_comp";
txfifo_pempty : string := "pempty_default";
txfifo_pfull : string := "pfull_default";
txfifo_empty : string := "empty_default";
txfifo_full : string := "full_default";
frmgen_bypass : string := "frmgen_bypass_dis";
frmgen_pipeln : string := "frmgen_pipeln_dis";
frmgen_mfrm_length : string := "frmgen_mfrm_length_min";
frmgen_mfrm_length_user : string := "int";
frmgen_pyld_ins : string := "frmgen_pyld_ins_dis";
sh_err : string := "sh_err_dis";
frmgen_burst : string := "frmgen_burst_dis";
frmgen_wordslip : string := "frmgen_wordslip_dis";
crcgen_bypass : string := "crcgen_bypass_dis";
crcgen_init : string := "crcgen_init_user_setting";
crcgen_init_user : bit_vector := B"11111111111111111111111111111111";
crcgen_inv : string := "crcgen_inv_dis";
crcgen_err : string := "crcgen_err_dis";
enc_64b66b_10g_mode : string := "enc_64b66b_10g_mode_en";
enc_64b66b_txsm_bypass : string := "enc_64b66b_txsm_bypass_dis";
tx_sm_bypass : string := "tx_sm_bypass_dis";
tx_sm_pipeln : string := "tx_sm_pipeln_dis";
scrm_bypass : string := "scrm_bypass_dis";
test_mode : string := "test_off";
pseudo_random : string := "all_0";
pseudo_seed_a : string := "pseudo_seed_a_user_setting";
pseudo_seed_a_user : bit_vector := B"1111111111111111111111111111111111111111111111111111111111";
pseudo_seed_b : string := "pseudo_seed_b_user_setting";
pseudo_seed_b_user : bit_vector := B"1111111111111111111111111111111111111111111111111111111111";
bit_reverse : string := "bit_reverse_dis";
scrm_seed : string := "scram_seed_user_setting";
scrm_seed_user : bit_vector := B"1111111111111111111111111111111111111111111111111111111111";
scrm_mode : string := "async";
dispgen_bypass : string := "dispgen_bypass_dis";
dispgen_err : string := "dispgen_err_dis";
dispgen_pipeln : string := "dispgen_pipeln_dis";
gb_sel_mode : string := "internal";
sq_wave : string := "sq_wave_4";
bitslip_en : string := "bitslip_dis";
fastpath : string := "fastpath_dis";
distup_bypass_pipeln : string := "distup_bypass_pipeln_dis";
distup_master : string := "distup_master_en";
distdwn_bypass_pipeln : string := "distdwn_bypass_pipeln_dis";
distdwn_master : string := "distdwn_master_en";
compin_sel : string := "compin_master";
comp_cnt : string := "comp_cnt_00";
indv : string := "indv_en";
stretch_num_stages : string := "zero_stage";
stretch_en : string := "stretch_en";
iqtxrx_clkout_sel : string := "iq_tx_pma_clk";
channel_number : integer := 0;
frmgen_sync_word : bit_vector := B"0000000000000000011110001111011001111000111101100111100011110110";
frmgen_scrm_word : bit_vector := B"0000000000000000001010000000000000000000000000000000000000000000";
frmgen_skip_word : bit_vector := B"0000000000000000000111100001111000011110000111100001111000011110";
frmgen_diag_word : bit_vector := B"0000000000000000011001000000000000000000000000000000000000000000";
test_bus_mode : string := "tx";
lpm_type : string := "stratixv_hssi_10g_tx_pcs"
);
port (
txpmaclk : in std_logic_vector(0 downto 0);
pmaclkdiv33lc : in std_logic_vector(0 downto 0);
hardresetn : in std_logic_vector(0 downto 0);
txpldclk : in std_logic_vector(0 downto 0);
txpldrstn : in std_logic_vector(0 downto 0);
refclkdig : in std_logic_vector(0 downto 0);
txdatavalid : in std_logic_vector(0 downto 0);
txbitslip : in std_logic_vector(6 downto 0);
txdiagnosticstatus : in std_logic_vector(1 downto 0);
txwordslip : in std_logic_vector(0 downto 0);
txbursten : in std_logic_vector(0 downto 0);
txdisparityclr : in std_logic_vector(0 downto 0);
txclkout : out std_logic_vector(0 downto 0);
txclkiqout : out std_logic_vector(0 downto 0);
txfifoempty : out std_logic_vector(0 downto 0);
txfifopartialempty : out std_logic_vector(0 downto 0);
txfifopartialfull : out std_logic_vector(0 downto 0);
txfifofull : out std_logic_vector(0 downto 0);
txframe : out std_logic_vector(0 downto 0);
txburstenexe : out std_logic_vector(0 downto 0);
txwordslipexe : out std_logic_vector(0 downto 0);
distupindv : in std_logic_vector(0 downto 0);
distdwnindv : in std_logic_vector(0 downto 0);
distupinwren : in std_logic_vector(0 downto 0);
distdwninwren : in std_logic_vector(0 downto 0);
distupinrden : in std_logic_vector(0 downto 0);
distdwninrden : in std_logic_vector(0 downto 0);
distupoutdv : out std_logic_vector(0 downto 0);
distdwnoutdv : out std_logic_vector(0 downto 0);
distupoutwren : out std_logic_vector(0 downto 0);
distdwnoutwren : out std_logic_vector(0 downto 0);
distupoutrden : out std_logic_vector(0 downto 0);
distdwnoutrden : out std_logic_vector(0 downto 0);
txtestdata : out std_logic_vector(19 downto 0);
txdata : in std_logic_vector(63 downto 0);
txcontrol : in std_logic_vector(8 downto 0);
loopbackdataout : out std_logic_vector(39 downto 0);
txpmadata : out std_logic_vector(39 downto 0);
syncdatain : out std_logic_vector(0 downto 0)
);
end stratixv_hssi_10g_tx_pcs;
architecture behavior of stratixv_hssi_10g_tx_pcs is
component stratixv_hssi_10g_tx_pcs_encrypted
generic (
prot_mode : string := "disable_mode";
sup_mode : string := "full_mode";
ctrl_plane_bonding : string := "individual";
master_clk_sel : string := "master_tx_pma_clk";
wr_clk_sel : string := "wr_tx_pma_clk";
wrfifo_clken : string := "wrfifo_clk_dis";
rdfifo_clken : string := "rdfifo_clk_dis";
frmgen_clken : string := "frmgen_clk_dis";
crcgen_clken : string := "crcgen_clk_dis";
enc64b66b_txsm_clken : string := "enc64b66b_txsm_clk_dis";
scrm_clken : string := "scrm_clk_dis";
dispgen_clken : string := "dispgen_clk_dis";
prbs_clken : string := "prbs_clk_dis";
sqwgen_clken : string := "sqwgen_clk_dis";
gbred_clken : string := "gbred_clk_dis";
gb_tx_idwidth : string := "idwidth_50";
gb_tx_odwidth : string := "odwidth_32";
txfifo_mode : string := "phase_comp";
txfifo_pempty : string := "pempty_default";
txfifo_pfull : string := "pfull_default";
txfifo_empty : string := "empty_default";
txfifo_full : string := "full_default";
frmgen_bypass : string := "frmgen_bypass_dis";
frmgen_pipeln : string := "frmgen_pipeln_dis";
frmgen_mfrm_length : string := "frmgen_mfrm_length_min";
frmgen_mfrm_length_user : string := "int";
frmgen_pyld_ins : string := "frmgen_pyld_ins_dis";
sh_err : string := "sh_err_dis";
frmgen_burst : string := "frmgen_burst_dis";
frmgen_wordslip : string := "frmgen_wordslip_dis";
crcgen_bypass : string := "crcgen_bypass_dis";
crcgen_init : string := "crcgen_init_user_setting";
crcgen_init_user : bit_vector := B"11111111111111111111111111111111";
crcgen_inv : string := "crcgen_inv_dis";
crcgen_err : string := "crcgen_err_dis";
enc_64b66b_10g_mode : string := "enc_64b66b_10g_mode_en";
enc_64b66b_txsm_bypass : string := "enc_64b66b_txsm_bypass_dis";
tx_sm_bypass : string := "tx_sm_bypass_dis";
tx_sm_pipeln : string := "tx_sm_pipeln_dis";
scrm_bypass : string := "scrm_bypass_dis";
test_mode : string := "test_off";
pseudo_random : string := "all_0";
pseudo_seed_a : string := "pseudo_seed_a_user_setting";
pseudo_seed_a_user : bit_vector := B"1111111111111111111111111111111111111111111111111111111111";
pseudo_seed_b : string := "pseudo_seed_b_user_setting";
pseudo_seed_b_user : bit_vector := B"1111111111111111111111111111111111111111111111111111111111";
bit_reverse : string := "bit_reverse_dis";
scrm_seed : string := "scram_seed_user_setting";
scrm_seed_user : bit_vector := B"1111111111111111111111111111111111111111111111111111111111";
scrm_mode : string := "async";
dispgen_bypass : string := "dispgen_bypass_dis";
dispgen_err : string := "dispgen_err_dis";
dispgen_pipeln : string := "dispgen_pipeln_dis";
gb_sel_mode : string := "internal";
sq_wave : string := "sq_wave_4";
bitslip_en : string := "bitslip_dis";
fastpath : string := "fastpath_dis";
distup_bypass_pipeln : string := "distup_bypass_pipeln_dis";
distup_master : string := "distup_master_en";
distdwn_bypass_pipeln : string := "distdwn_bypass_pipeln_dis";
distdwn_master : string := "distdwn_master_en";
compin_sel : string := "compin_master";
comp_cnt : string := "comp_cnt_00";
indv : string := "indv_en";
stretch_num_stages : string := "zero_stage";
stretch_en : string := "stretch_en";
iqtxrx_clkout_sel : string := "iq_tx_pma_clk";
channel_number : integer := 0;
frmgen_sync_word : bit_vector := B"0000000000000000011110001111011001111000111101100111100011110110";
frmgen_scrm_word : bit_vector := B"0000000000000000001010000000000000000000000000000000000000000000";
frmgen_skip_word : bit_vector := B"0000000000000000000111100001111000011110000111100001111000011110";
frmgen_diag_word : bit_vector := B"0000000000000000011001000000000000000000000000000000000000000000";
test_bus_mode : string := "tx";
lpm_type : string := "stratixv_hssi_10g_tx_pcs"
);
port (
txpmaclk : in std_logic_vector(0 downto 0);
pmaclkdiv33lc : in std_logic_vector(0 downto 0);
hardresetn : in std_logic_vector(0 downto 0);
txpldclk : in std_logic_vector(0 downto 0);
txpldrstn : in std_logic_vector(0 downto 0);
refclkdig : in std_logic_vector(0 downto 0);
txdatavalid : in std_logic_vector(0 downto 0);
txbitslip : in std_logic_vector(6 downto 0);
txdiagnosticstatus : in std_logic_vector(1 downto 0);
txwordslip : in std_logic_vector(0 downto 0);
txbursten : in std_logic_vector(0 downto 0);
txdisparityclr : in std_logic_vector(0 downto 0);
txclkout : out std_logic_vector(0 downto 0);
txclkiqout : out std_logic_vector(0 downto 0);
txfifoempty : out std_logic_vector(0 downto 0);
txfifopartialempty : out std_logic_vector(0 downto 0);
txfifopartialfull : out std_logic_vector(0 downto 0);
txfifofull : out std_logic_vector(0 downto 0);
txframe : out std_logic_vector(0 downto 0);
txburstenexe : out std_logic_vector(0 downto 0);
txwordslipexe : out std_logic_vector(0 downto 0);
distupindv : in std_logic_vector(0 downto 0);
distdwnindv : in std_logic_vector(0 downto 0);
distupinwren : in std_logic_vector(0 downto 0);
distdwninwren : in std_logic_vector(0 downto 0);
distupinrden : in std_logic_vector(0 downto 0);
distdwninrden : in std_logic_vector(0 downto 0);
distupoutdv : out std_logic_vector(0 downto 0);
distdwnoutdv : out std_logic_vector(0 downto 0);
distupoutwren : out std_logic_vector(0 downto 0);
distdwnoutwren : out std_logic_vector(0 downto 0);
distupoutrden : out std_logic_vector(0 downto 0);
distdwnoutrden : out std_logic_vector(0 downto 0);
txtestdata : out std_logic_vector(19 downto 0);
txdata : in std_logic_vector(63 downto 0);
txcontrol : in std_logic_vector(8 downto 0);
loopbackdataout : out std_logic_vector(39 downto 0);
txpmadata : out std_logic_vector(39 downto 0);
syncdatain : out std_logic_vector(0 downto 0)
);
end component;
begin
inst : stratixv_hssi_10g_tx_pcs_encrypted
generic map (
prot_mode => prot_mode,
sup_mode => sup_mode,
ctrl_plane_bonding => ctrl_plane_bonding,
master_clk_sel => master_clk_sel,
wr_clk_sel => wr_clk_sel,
wrfifo_clken => wrfifo_clken,
rdfifo_clken => rdfifo_clken,
frmgen_clken => frmgen_clken,
crcgen_clken => crcgen_clken,
enc64b66b_txsm_clken => enc64b66b_txsm_clken,
scrm_clken => scrm_clken,
dispgen_clken => dispgen_clken,
prbs_clken => prbs_clken,
sqwgen_clken => sqwgen_clken,
gbred_clken => gbred_clken,
gb_tx_idwidth => gb_tx_idwidth,
gb_tx_odwidth => gb_tx_odwidth,
txfifo_mode => txfifo_mode,
txfifo_pempty => txfifo_pempty,
txfifo_pfull => txfifo_pfull,
txfifo_empty => txfifo_empty,
txfifo_full => txfifo_full,
frmgen_bypass => frmgen_bypass,
frmgen_pipeln => frmgen_pipeln,
frmgen_mfrm_length => frmgen_mfrm_length,
frmgen_mfrm_length_user => frmgen_mfrm_length_user,
frmgen_pyld_ins => frmgen_pyld_ins,
sh_err => sh_err,
frmgen_burst => frmgen_burst,
frmgen_wordslip => frmgen_wordslip,
crcgen_bypass => crcgen_bypass,
crcgen_init => crcgen_init,
crcgen_init_user => crcgen_init_user,
crcgen_inv => crcgen_inv,
crcgen_err => crcgen_err,
enc_64b66b_10g_mode => enc_64b66b_10g_mode,
enc_64b66b_txsm_bypass => enc_64b66b_txsm_bypass,
tx_sm_bypass => tx_sm_bypass,
tx_sm_pipeln => tx_sm_pipeln,
scrm_bypass => scrm_bypass,
test_mode => test_mode,
pseudo_random => pseudo_random,
pseudo_seed_a => pseudo_seed_a,
pseudo_seed_a_user => pseudo_seed_a_user,
pseudo_seed_b => pseudo_seed_b,
pseudo_seed_b_user => pseudo_seed_b_user,
bit_reverse => bit_reverse,
scrm_seed => scrm_seed,
scrm_seed_user => scrm_seed_user,
scrm_mode => scrm_mode,
dispgen_bypass => dispgen_bypass,
dispgen_err => dispgen_err,
dispgen_pipeln => dispgen_pipeln,
gb_sel_mode => gb_sel_mode,
sq_wave => sq_wave,
bitslip_en => bitslip_en,
fastpath => fastpath,
distup_bypass_pipeln => distup_bypass_pipeln,
distup_master => distup_master,
distdwn_bypass_pipeln => distdwn_bypass_pipeln,
distdwn_master => distdwn_master,
compin_sel => compin_sel,
comp_cnt => comp_cnt,
indv => indv,
stretch_num_stages => stretch_num_stages,
stretch_en => stretch_en,
iqtxrx_clkout_sel => iqtxrx_clkout_sel,
channel_number => channel_number,
frmgen_sync_word => frmgen_sync_word,
frmgen_scrm_word => frmgen_scrm_word,
frmgen_skip_word => frmgen_skip_word,
frmgen_diag_word => frmgen_diag_word,
test_bus_mode => test_bus_mode,
lpm_type => lpm_type
)
port map (
txpmaclk => txpmaclk,
pmaclkdiv33lc => pmaclkdiv33lc,
hardresetn => hardresetn,
txpldclk => txpldclk,
txpldrstn => txpldrstn,
refclkdig => refclkdig,
txdatavalid => txdatavalid,
txbitslip => txbitslip,
txdiagnosticstatus => txdiagnosticstatus,
txwordslip => txwordslip,
txbursten => txbursten,
txdisparityclr => txdisparityclr,
txclkout => txclkout,
txclkiqout => txclkiqout,
txfifoempty => txfifoempty,
txfifopartialempty => txfifopartialempty,
txfifopartialfull => txfifopartialfull,
txfifofull => txfifofull,
txframe => txframe,
txburstenexe => txburstenexe,
txwordslipexe => txwordslipexe,
distupindv => distupindv,
distdwnindv => distdwnindv,
distupinwren => distupinwren,
distdwninwren => distdwninwren,
distupinrden => distupinrden,
distdwninrden => distdwninrden,
distupoutdv => distupoutdv,
distdwnoutdv => distdwnoutdv,
distupoutwren => distupoutwren,
distdwnoutwren => distdwnoutwren,
distupoutrden => distupoutrden,
distdwnoutrden => distdwnoutrden,
txtestdata => txtestdata,
txdata => txdata,
txcontrol => txcontrol,
loopbackdataout => loopbackdataout,
txpmadata => txpmadata,
syncdatain => syncdatain
);
end behavior;
------------------------------------------------------------------------------------
-- This is the HSSI Simulation Atom Model Encryption wrapper for the AVMM Interface
-- Entity Name : stratixv_hssi_avmm_interface
------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity stratixv_hssi_avmm_interface is
generic (
num_ch0_atoms : integer := 0;
num_ch1_atoms : integer := 0;
num_ch2_atoms : integer := 0
);
port (
avmmrstn : in std_logic_vector(0 downto 0);
avmmclk : in std_logic_vector(0 downto 0);
avmmwrite : in std_logic_vector(0 downto 0);
avmmread : in std_logic_vector(0 downto 0);
avmmbyteen : in std_logic_vector(1 downto 0);
avmmaddress : in std_logic_vector(10 downto 0);
avmmwritedata : in std_logic_vector(15 downto 0);
blockselect : in std_logic_vector(90-1 downto 0);
readdatachnl : in std_logic_vector(90*16-1 downto 0);
avmmreaddata : out std_logic_vector(15 downto 0);
clkchnl : out std_logic_vector(0 downto 0);
rstnchnl : out std_logic_vector(0 downto 0);
writedatachnl : out std_logic_vector(15 downto 0);
regaddrchnl : out std_logic_vector(10 downto 0);
writechnl : out std_logic_vector(0 downto 0);
readchnl : out std_logic_vector(0 downto 0);
byteenchnl : out std_logic_vector(1 downto 0);
-- The following ports are not modelled. They exist to match the avmm interface atom interface
refclkdig : in std_logic_vector(0 downto 0);
avmmreservedin : in std_logic_vector(0 downto 0);
avmmreservedout : out std_logic_vector(0 downto 0);
dpriorstntop : out std_logic_vector(0 downto 0);
dprioclktop : out std_logic_vector(0 downto 0);
mdiodistopchnl : out std_logic_vector(0 downto 0);
dpriorstnmid : out std_logic_vector(0 downto 0);
dprioclkmid : out std_logic_vector(0 downto 0);
mdiodismidchnl : out std_logic_vector(0 downto 0);
dpriorstnbot : out std_logic_vector(0 downto 0);
dprioclkbot : out std_logic_vector(0 downto 0);
mdiodisbotchnl : out std_logic_vector(0 downto 0);
dpriotestsitopchnl : out std_logic_vector(3 downto 0);
dpriotestsimidchnl : out std_logic_vector(3 downto 0);
dpriotestsibotchnl : out std_logic_vector(3 downto 0);
-- The following ports belong to pm_adce and pm_tst_mux blocks in the PMA
pmatestbus : out std_logic_vector(23 downto 0);
pmatestbussel : in std_logic_vector(11 downto 0);
scanmoden : in std_logic_vector(0 downto 0);
scanshiftn : in std_logic_vector(0 downto 0);
interfacesel : in std_logic_vector(0 downto 0);
sershiftload : in std_logic_vector(0 downto 0)
);
end stratixv_hssi_avmm_interface;
architecture behavior of stratixv_hssi_avmm_interface is
component stratixv_hssi_avmm_interface_encrypted
generic (
num_ch0_atoms : integer := 0;
num_ch1_atoms : integer := 0;
num_ch2_atoms : integer := 0
);
port (
avmmrstn : in std_logic_vector(0 downto 0);
avmmclk : in std_logic_vector(0 downto 0);
avmmwrite : in std_logic_vector(0 downto 0);
avmmread : in std_logic_vector(0 downto 0);
avmmbyteen : in std_logic_vector(1 downto 0);
avmmaddress : in std_logic_vector(10 downto 0);
avmmwritedata : in std_logic_vector(15 downto 0);
blockselect : in std_logic_vector(90-1 downto 0);
readdatachnl : in std_logic_vector(90*16-1 downto 0);
avmmreaddata : out std_logic_vector(15 downto 0);
clkchnl : out std_logic_vector(0 downto 0);
rstnchnl : out std_logic_vector(0 downto 0);
writedatachnl : out std_logic_vector(15 downto 0);
regaddrchnl : out std_logic_vector(10 downto 0);
writechnl : out std_logic_vector(0 downto 0);
readchnl : out std_logic_vector(0 downto 0);
byteenchnl : out std_logic_vector(1 downto 0);
refclkdig : in std_logic_vector(0 downto 0);
avmmreservedin : in std_logic_vector(0 downto 0);
avmmreservedout : out std_logic_vector(0 downto 0);
dpriorstntop : out std_logic_vector(0 downto 0);
dprioclktop : out std_logic_vector(0 downto 0);
mdiodistopchnl : out std_logic_vector(0 downto 0);
dpriorstnmid : out std_logic_vector(0 downto 0);
dprioclkmid : out std_logic_vector(0 downto 0);
mdiodismidchnl : out std_logic_vector(0 downto 0);
dpriorstnbot : out std_logic_vector(0 downto 0);
dprioclkbot : out std_logic_vector(0 downto 0);
mdiodisbotchnl : out std_logic_vector(0 downto 0);
dpriotestsitopchnl : out std_logic_vector(3 downto 0);
dpriotestsimidchnl : out std_logic_vector(3 downto 0);
dpriotestsibotchnl : out std_logic_vector(3 downto 0);
pmatestbus : out std_logic_vector(23 downto 0);
pmatestbussel : in std_logic_vector(11 downto 0);
scanmoden : in std_logic_vector(0 downto 0);
scanshiftn : in std_logic_vector(0 downto 0);
interfacesel : in std_logic_vector(0 downto 0);
sershiftload : in std_logic_vector(0 downto 0)
);
end component;
begin
inst : stratixv_hssi_avmm_interface_encrypted
generic map (
num_ch0_atoms => num_ch0_atoms,
num_ch1_atoms => num_ch1_atoms,
num_ch2_atoms => num_ch2_atoms
)
port map (
avmmrstn => avmmrstn ,
avmmclk => avmmclk ,
avmmwrite => avmmwrite ,
avmmread => avmmread ,
avmmbyteen => avmmbyteen ,
avmmaddress => avmmaddress ,
avmmwritedata => avmmwritedata ,
blockselect => blockselect ,
readdatachnl => readdatachnl ,
avmmreaddata => avmmreaddata ,
clkchnl => clkchnl ,
rstnchnl => rstnchnl ,
writedatachnl => writedatachnl ,
regaddrchnl => regaddrchnl ,
writechnl => writechnl ,
readchnl => readchnl ,
byteenchnl => byteenchnl ,
refclkdig => refclkdig ,
avmmreservedin => avmmreservedin ,
avmmreservedout => avmmreservedout ,
dpriorstntop => dpriorstntop ,
dprioclktop => dprioclktop ,
mdiodistopchnl => mdiodistopchnl ,
dpriorstnmid => dpriorstnmid ,
dprioclkmid => dprioclkmid ,
mdiodismidchnl => mdiodismidchnl ,
dpriorstnbot => dpriorstnbot ,
dprioclkbot => dprioclkbot ,
mdiodisbotchnl => mdiodisbotchnl ,
dpriotestsitopchnl => dpriotestsitopchnl ,
dpriotestsimidchnl => dpriotestsimidchnl ,
dpriotestsibotchnl => dpriotestsibotchnl ,
pmatestbus => pmatestbus ,
pmatestbussel => pmatestbussel ,
scanmoden => scanmoden ,
scanshiftn => scanshiftn ,
interfacesel => interfacesel ,
sershiftload => sershiftload
);
end behavior;
| gpl-3.0 |
asicguy/gplgpu | hdl/sim_lib/stratixiv_hssi_components.vhd | 1 | 127621 | -- Copyright (C) Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
LIBRARY IEEE;
use IEEE.STD_LOGIC_1164.all;
USE IEEE.vital_timing.ALL;
USE IEEE.vital_primitives.ALL;
package STRATIXIV_HSSI_COMPONENTS is
-- VITAL constants BEGIN
-- default generic values
CONSTANT DefWireDelay : VitalDelayType01 := (0 ns, 0 ns);
CONSTANT DefPropDelay01 : VitalDelayType01 := (0 ns, 0 ns);
CONSTANT DefPropDelay01Z : VitalDelayType01Z := (OTHERS => 0 ns);
CONSTANT DefSetupHoldCnst : TIME := 0 ns;
CONSTANT DefPulseWdthCnst : TIME := 0 ns;
-- default control options
-- CONSTANT DefGlitchMode : VitalGlitchKindType := OnEvent;
-- change default delay type to Transport : for spr 68748
CONSTANT DefGlitchMode : VitalGlitchKindType := VitalTransport;
CONSTANT DefGlitchMsgOn : BOOLEAN := FALSE;
CONSTANT DefGlitchXOn : BOOLEAN := FALSE;
CONSTANT DefMsgOnChecks : BOOLEAN := TRUE;
CONSTANT DefXOnChecks : BOOLEAN := TRUE;
-- output strength mapping
-- UX01ZWHL-
CONSTANT PullUp : VitalOutputMapType := "UX01HX01X";
CONSTANT NoPullUpZ : VitalOutputMapType := "UX01ZX01X";
CONSTANT PullDown : VitalOutputMapType := "UX01LX01X";
-- primitive result strength mapping
CONSTANT wiredOR : VitalResultMapType := ( 'U', 'X', 'L', '1' );
CONSTANT wiredAND : VitalResultMapType := ( 'U', 'X', '0', 'H' );
CONSTANT L : VitalTableSymbolType := '0';
CONSTANT H : VitalTableSymbolType := '1';
CONSTANT x : VitalTableSymbolType := '-';
CONSTANT S : VitalTableSymbolType := 'S';
CONSTANT R : VitalTableSymbolType := '/';
CONSTANT U : VitalTableSymbolType := 'X';
CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising)
-- VITAL constants END
-- GENERIC utility functions BEGIN
function bin2int (s : std_logic_vector) return integer;
function bin2int (s : std_logic) return integer;
function int2bit (arg : boolean) return std_logic;
function str2bin (s : string) return std_logic_vector;
function str2int (s : string) return integer;
function int2bin (arg : integer; size : integer) return std_logic_vector;
function int2bin (arg : boolean; size : integer) return std_logic_vector;
function int2bit (arg : integer) return std_logic;
function tx_top_ctrl_in_width(
double_data_mode : string;
ser_double_data_mode : string
) return integer;
function rx_top_a1k1_out_width(des_double_data_mode : string) return integer;
function rx_top_ctrl_out_width(
double_data_mode : string;
des_double_data_mode : string
) return integer;
function rx_top_basic_width (channel_width : integer) return integer;
function rx_top_num_of_basic (channel_width : integer) return integer;
function hssiSelectDelay (CONSTANT Paths: IN VitalPathArray01Type) return TIME;
function mux_select (sel : boolean; data1 : std_logic_vector; data2 : std_logic_vector) return std_logic_vector;
function mux_select (sel : bit; data1 : std_logic_vector; data2 : std_logic_vector) return std_logic_vector;
function mux_select (sel : boolean; data1 : std_logic; data2 : std_logic) return std_logic;
function mux_select (sel : bit; data1 : std_logic; data2 : std_logic) return std_logic;
function reduction_or (val : std_logic_vector) return std_logic;
function reduction_nor (val : std_logic_vector) return std_logic;
function reduction_xor (val : std_logic_vector) return std_logic;
function reduction_and (val : std_logic_vector) return std_logic;
function reduction_nand (val : std_logic_vector) return std_logic;
function alpha_tolower (given_string : string) return string;
function stratixiv_tx_pcs_mph_fifo_xn_mapping (ph_fifo_xn_select : integer; ph_fifo_xn_mapping0 : string; ph_fifo_xn_mapping1 : string; ph_fifo_xn_mapping2 : string) return string;
function stratixiv_tx_pcs_mphfifo_index ( ph_fifo_xn_select : integer) return integer;
function stratixiv_tx_pcs_miqp_phfifo_index ( ph_fifo_xn_select : integer) return integer;
-- GENERIC utility functions END
TYPE CMU_MULT_STATE_TYPE IS (INITIAL,INACTIVE,ACTIVE);
--
-- stratixiv_hssi_clock_divider
--
COMPONENT stratixiv_hssi_clock_divider
GENERIC (
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
TimingChecksOn : Boolean := True;
tipd_refclkin :VitalDelayArrayType01(2 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_rateswitchdonein :VitalDelayArrayType01(2 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_dpriodisable : VitalDelayType01 := DefpropDelay01;
tipd_quadreset : VitalDelayType01 := DefpropDelay01;
tipd_clk0in :VitalDelayArrayType01(4 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_vcobypassin : VitalDelayType01 := DefpropDelay01;
tipd_clk1in :VitalDelayArrayType01(4 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_rateswitchbaseclkin :VitalDelayArrayType01(2 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_refclkdig : VitalDelayType01 := DefpropDelay01;
tipd_dprioin :VitalDelayArrayType01(100 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_powerdn : VitalDelayType01 := DefpropDelay01;
tipd_rateswitch : VitalDelayType01 := DefpropDelay01;
lpm_type : STRING := "stratixiv_hssi_clock_divider";
channel_num : INTEGER := 0;
coreclk_out_gated_by_quad_reset : STRING := "false";
data_rate : INTEGER := 0;
divide_by : INTEGER := 4;
divider_type : STRING := "CHANNEL_REGULAR";
dprio_config_mode : STD_LOGIC_VECTOR(5 DOWNTO 0) := "000000";
effective_data_rate : STRING := "unused";
enable_dynamic_divider : STRING := "false";
enable_refclk_out : STRING := "false";
inclk_select : INTEGER := 0;
logical_channel_address : INTEGER := 0;
pre_divide_by : INTEGER := 1;
rate_switch_base_clk_in_select : INTEGER := 0;
rate_switch_done_in_select : INTEGER := 0;
refclk_divide_by : INTEGER := 0;
refclk_multiply_by : INTEGER := 0;
refclkin_select : INTEGER := 0;
select_local_rate_switch_base_clock : STRING := "false";
select_local_rate_switch_done : STRING := "true"; -- shawn
select_local_refclk : STRING := "false";
select_refclk_dig : STRING := "false";
sim_analogfastrefclkout_phase_shift : INTEGER := 0;
sim_analogrefclkout_phase_shift : INTEGER := 0;
sim_coreclkout_phase_shift : INTEGER := 0;
sim_refclkout_phase_shift : INTEGER := 0;
use_coreclk_out_post_divider : STRING := "false";
use_refclk_post_divider : STRING := "false";
use_vco_bypass : STRING := "false"
);
PORT (
clk0in : IN STD_LOGIC_VECTOR(4 - 1 DOWNTO 0) := (others => '0');
clk1in : IN STD_LOGIC_VECTOR(4 - 1 DOWNTO 0) := (others => '0');
dpriodisable : IN STD_LOGIC := '1';
dprioin : IN STD_LOGIC_VECTOR(100 - 1 DOWNTO 0) := (others => '0');
powerdn : IN STD_LOGIC := '0';
quadreset : IN STD_LOGIC := '0';
rateswitch : IN STD_LOGIC := '0';
rateswitchbaseclkin : IN STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (others => '0');
rateswitchdonein : IN STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (others => '0');
refclkdig : IN STD_LOGIC := '0';
refclkin : IN STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (others => '0');
vcobypassin : IN STD_LOGIC := '0';
analogfastrefclkout : OUT STD_LOGIC_VECTOR(2 - 1 DOWNTO 0);
analogfastrefclkoutshifted : OUT STD_LOGIC_VECTOR(2 - 1 DOWNTO 0);
analogrefclkout : OUT STD_LOGIC_VECTOR(2 - 1 DOWNTO 0);
analogrefclkoutshifted : OUT STD_LOGIC_VECTOR(2 - 1 DOWNTO 0);
analogrefclkpulse : OUT STD_LOGIC;
analogrefclkpulseshifted : OUT STD_LOGIC;
coreclkout : OUT STD_LOGIC;
dprioout : OUT STD_LOGIC_VECTOR(100 - 1 DOWNTO 0);
rateswitchbaseclock : OUT STD_LOGIC;
rateswitchdone : OUT STD_LOGIC;
rateswitchout : OUT STD_LOGIC;
refclkout : OUT STD_LOGIC
);
END COMPONENT;
--
-- stratixiv_hssi_pll
--
COMPONENT stratixiv_hssi_pll
GENERIC (
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
TimingChecksOn : Boolean := True;
tipd_dpriodisable : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayType01 := DefpropDelay01;
tipd_areset : VitalDelayType01 := DefpropDelay01;
tipd_earlyeios : VitalDelayType01 := DefpropDelay01;
tipd_locktorefclk : VitalDelayType01 := DefpropDelay01;
tipd_pfdfbclk : VitalDelayType01 := DefpropDelay01;
tipd_powerdown : VitalDelayType01 := DefpropDelay01;
tipd_inclk :VitalDelayArrayType01(10 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_dprioin :VitalDelayArrayType01(300 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_rateswitch : VitalDelayType01 := DefpropDelay01;
tpd_inclk_clk : VitalDelayType01 := DefPropDelay01;
lpm_type : STRING := "stratixiv_hssi_pll";
auto_settings : STRING := "true";
bandwidth_type : STRING := "Auto";
base_data_rate : STRING := "unused";
channel_num : INTEGER := 0;
charge_pump_current_bits : INTEGER := 0;
charge_pump_mode_bits : INTEGER := 0;
charge_pump_test_enable : STRING := "false";
dprio_config_mode : STD_LOGIC_VECTOR(5 DOWNTO 0) := "000000";
effective_data_rate : STRING := "unused";
enable_dynamic_divider : STRING := "false";
fast_lock_control : STRING := "false";
inclk0_input_period : INTEGER := 0;
inclk1_input_period : INTEGER := 0;
inclk2_input_period : INTEGER := 0;
inclk3_input_period : INTEGER := 0;
inclk4_input_period : INTEGER := 0;
inclk5_input_period : INTEGER := 0;
inclk6_input_period : INTEGER := 0;
inclk7_input_period : INTEGER := 0;
inclk8_input_period : INTEGER := 0;
inclk9_input_period : INTEGER := 0;
input_clock_frequency : STRING := "unused";
logical_channel_address : INTEGER := 0;
logical_tx_pll_number : INTEGER := 0;
loop_filter_c_bits : INTEGER := 0;
loop_filter_r_bits : INTEGER := 0;
m : INTEGER := 0;
n : INTEGER := 0;
pd_charge_pump_current_bits : INTEGER := 0;
pd_loop_filter_r_bits : INTEGER := 0;
pfd_clk_select : INTEGER := 0;
pfd_fb_select : STRING := "internal";
pll_type : STRING := "Auto";
protocol_hint : STRING := "basic";
refclk_divide_by : INTEGER := 0;
refclk_multiply_by : INTEGER := 0;
sim_is_negative_ppm_drift : STRING := "false";
sim_net_ppm_variation : INTEGER := 0;
test_charge_pump_current_down : STRING := "false";
test_charge_pump_current_up : STRING := "false";
use_refclk_pin : STRING := "false";
vco_data_rate : INTEGER := 0;
vco_divide_by : INTEGER := 0;
vco_range : STRING := "low";
vco_multiply_by : INTEGER := 0;
vco_post_scale : INTEGER := 0;
vco_tuning_bits : INTEGER := 0;
volt_reg_control_bits : INTEGER := 0;
volt_reg_output_bits : INTEGER := 0;
sim_clkout_phase_shift : INTEGER := 0;
sim_clkout_latency : INTEGER := 0;
PARAM_DELAY : INTEGER := 0
);
PORT (
areset : IN STD_LOGIC := '0';
datain : IN STD_LOGIC := '0';
dpriodisable : IN STD_LOGIC := '1';
dprioin : IN STD_LOGIC_VECTOR(300 - 1 DOWNTO 0) := (others => '0');
earlyeios : IN STD_LOGIC := '0';
extra10gin : IN STD_LOGIC_VECTOR(6 - 1 DOWNTO 0) := (others => '0');
inclk : IN STD_LOGIC_VECTOR(10 - 1 DOWNTO 0) := (others => '0');
locktorefclk : IN STD_LOGIC := '1';
pfdfbclk : IN STD_LOGIC := '0';
powerdown : IN STD_LOGIC := '0';
rateswitch : IN STD_LOGIC := '0';
clk : OUT STD_LOGIC_VECTOR(4 - 1 DOWNTO 0);
dataout : OUT STD_LOGIC_VECTOR(2 - 1 DOWNTO 0);
dprioout : OUT STD_LOGIC_VECTOR(300 - 1 DOWNTO 0);
freqlocked : OUT STD_LOGIC;
locked : OUT STD_LOGIC;
pfdfbclkout : OUT STD_LOGIC;
pfdrefclkout : OUT STD_LOGIC;
vcobypassout : OUT STD_LOGIC
);
END COMPONENT;
--
-- stratixiv_hssi_tx_pma
--
COMPONENT stratixiv_hssi_tx_pma
GENERIC (
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
TimingChecksOn : Boolean := True;
tipd_datain :VitalDelayArrayType01(64 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_datainfull :VitalDelayArrayType01(20 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_refclk0inpulse : VitalDelayType01 := DefpropDelay01;
tipd_forceelecidle : VitalDelayType01 := DefpropDelay01;
tipd_pclk : VitalDelayArrayType01(5 - 1 DOWNTO 0) := (OTHERS => DefpropDelay01);
tipd_fastrefclk4in : VitalDelayArrayType01(2 - 1 DOWNTO 0) := (OTHERS => DefpropDelay01);
tipd_refclk1in :VitalDelayArrayType01(2 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_refclk0in :VitalDelayArrayType01(2 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_refclk4inpulse : VitalDelayType01 := DefpropDelay01;
tipd_refclk4in : VitalDelayArrayType01(2 - 1 DOWNTO 0) := (OTHERS => DefpropDelay01);
tipd_dpriodisable : VitalDelayType01 := DefpropDelay01;
tipd_rxdetecten : VitalDelayType01 := DefpropDelay01;
tipd_refclk1inpulse : VitalDelayType01 := DefpropDelay01;
tipd_fastrefclk3in :VitalDelayArrayType01(2 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_txpmareset : VitalDelayType01 := DefpropDelay01;
tipd_fastrefclk0in :VitalDelayArrayType01(2 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_revserialfdbk : VitalDelayType01 := DefpropDelay01;
tipd_refclk3in :VitalDelayArrayType01(2 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_powerdn : VitalDelayType01 := DefpropDelay01;
tipd_fastrefclk2in :VitalDelayArrayType01(2 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_detectrxpowerdown : VitalDelayType01 := DefpropDelay01;
tipd_refclk3inpulse : VitalDelayType01 := DefpropDelay01;
tipd_refclk2inpulse : VitalDelayType01 := DefpropDelay01;
tipd_refclk2in :VitalDelayArrayType01(2 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_rxdetectclk : VitalDelayType01 := DefpropDelay01;
tipd_fastrefclk1in :VitalDelayArrayType01(2 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_dprioin :VitalDelayArrayType01(300 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
lpm_type : STRING := "stratixiv_hssi_tx_pma";
analog_power : STRING := "1.5V";
channel_number : INTEGER := 9999;
channel_type : STRING := "auto";
clkin_select : INTEGER := 0; -- 9999; out of bound in loading
clkmux_delay : STRING := "false";
common_mode : STRING := "0.6V";
dprio_config_mode : STD_LOGIC_VECTOR(5 DOWNTO 0) := "000000";
enable_reverse_serial_loopback : STRING := "false";
logical_channel_address : INTEGER := 0;
logical_protocol_hint_0 : STRING := "basic";
logical_protocol_hint_1 : STRING := "basic";
logical_protocol_hint_2 : STRING := "basic";
logical_protocol_hint_3 : STRING := "basic";
low_speed_test_select : INTEGER := 9999;
physical_clkin0_mapping : STRING := "x1";
physical_clkin1_mapping : STRING := "x4";
physical_clkin2_mapping : STRING := "xn_top";
physical_clkin3_mapping : STRING := "xn_bottom";
physical_clkin4_mapping : STRING := "hypertransport";
preemp_pretap : INTEGER := 0;
preemp_pretap_inv : STRING := "false";
preemp_tap_1 : INTEGER := 0;
preemp_tap_1_a : INTEGER := 0;
preemp_tap_1_b : INTEGER := 0;
preemp_tap_1_c : INTEGER := 0;
preemp_tap_2 : INTEGER := 0;
preemp_tap_2_inv : STRING := "false";
protocol_hint : STRING := "basic";
rx_detect : INTEGER := 9999;
serialization_factor : INTEGER := 8;
slew_rate : STRING := "low";
termination : STRING := "OCT 100 Ohms";
use_external_termination : STRING := "false";
use_pclk : STRING := "false";
use_pma_direct : STRING := "false";
use_rx_detect : STRING := "false";
use_ser_double_data_mode : STRING := "false";
vod_selection : INTEGER := 0;
vod_selection_a : INTEGER := 0;
vod_selection_b : INTEGER := 0;
vod_selection_c : INTEGER := 0;
vod_selection_d : INTEGER := 0
);
PORT (
datain : IN STD_LOGIC_VECTOR(64 - 1 DOWNTO 0) := (others => '0');
datainfull : IN STD_LOGIC_VECTOR(20 - 1 DOWNTO 0) := (others => '0');
detectrxpowerdown : IN STD_LOGIC := '0';
dpriodisable : IN STD_LOGIC := '1';
dprioin : IN STD_LOGIC_VECTOR(300 - 1 DOWNTO 0) := (others => '0');
extra10gin : IN STD_LOGIC_VECTOR(11 - 1 DOWNTO 0) := (others => '0');
fastrefclk0in : IN STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (others => '0');
fastrefclk1in : IN STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (others => '0');
fastrefclk2in : IN STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (others => '0');
fastrefclk3in : IN STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (others => '0');
fastrefclk4in : IN STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (OTHERS => '0');
forceelecidle : IN STD_LOGIC := '0';
pclk : IN STD_LOGIC_VECTOR(5 - 1 DOWNTO 0) := (OTHERS => '0');
powerdn : IN STD_LOGIC := '0';
refclk0in : IN STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (others => '0');
refclk0inpulse : IN STD_LOGIC := '0';
refclk1in : IN STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (others => '0');
refclk1inpulse : IN STD_LOGIC := '0';
refclk2in : IN STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (others => '0');
refclk2inpulse : IN STD_LOGIC := '0';
refclk3in : IN STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (others => '0');
refclk3inpulse : IN STD_LOGIC := '0';
refclk4in : IN STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (OTHERS => '0');
refclk4inpulse : IN STD_LOGIC := '0';
revserialfdbk : IN STD_LOGIC := '0';
rxdetectclk : IN STD_LOGIC := '0';
rxdetecten : IN STD_LOGIC := '0';
txpmareset : IN STD_LOGIC := '0';
clockout : OUT STD_LOGIC;
dataout : OUT STD_LOGIC;
dftout : OUT STD_LOGIC_VECTOR(6 - 1 DOWNTO 0);
dprioout : OUT STD_LOGIC_VECTOR(300 - 1 DOWNTO 0);
rxdetectvalidout : OUT STD_LOGIC;
rxfoundout : OUT STD_LOGIC;
seriallpbkout : OUT STD_LOGIC
);
END COMPONENT;
--
-- stratixiv_hssi_rx_pma
--
COMPONENT stratixiv_hssi_rx_pma
GENERIC (
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
TimingChecksOn : Boolean := True;
tipd_ppmdetectdividedclk : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayType01 := DefpropDelay01;
tipd_rxpmareset : VitalDelayType01 := DefpropDelay01;
tipd_plllocked : VitalDelayType01 := DefpropDelay01;
tipd_dpriodisable : VitalDelayType01 := DefpropDelay01;
tipd_ignorephslck : VitalDelayType01 := DefpropDelay01;
tipd_locktoref : VitalDelayType01 := DefpropDelay01;
tipd_adcepowerdn : VitalDelayType01 := DefpropDelay01;
tipd_ppmdetectrefclk : VitalDelayType01 := DefpropDelay01;
tipd_adcestandby : VitalDelayType01 := DefpropDelay01;
tipd_powerdn : VitalDelayType01 := DefpropDelay01;
tipd_seriallpbken : VitalDelayType01 := DefpropDelay01;
tipd_adcereset : VitalDelayType01 := DefpropDelay01;
tipd_deserclock :VitalDelayArrayType01(4 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_locktodata : VitalDelayType01 := DefpropDelay01;
tipd_freqlock : VitalDelayType01 := DefpropDelay01;
tipd_offsetcancellationen : VitalDelayType01 := DefpropDelay01;
tipd_testbussel :VitalDelayArrayType01(4 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_recoverdatain :VitalDelayArrayType01(2 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_seriallpbkin : VitalDelayType01 := DefpropDelay01;
tipd_dprioin :VitalDelayArrayType01(300 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_adaptcapture : VitalDelayType01 := DefpropDelay01;
lpm_type : STRING := "stratixiv_hssi_rx_pma";
adaptive_equalization_mode : STRING := "none";
allow_serial_loopback : STRING := "false";
allow_vco_bypass : INTEGER := 0;
analog_power : STRING := "1.4V";
channel_number : INTEGER := 0;
channel_type : STRING := "auto";
common_mode : STRING := "0.82V";
deserialization_factor : INTEGER := 8;
dfe_piclk_bandwidth : INTEGER := 0;
dfe_piclk_phase : INTEGER := 0;
dfe_piclk_sel : INTEGER := 0;
dprio_config_mode : STD_LOGIC_VECTOR(5 DOWNTO 0) := "000000";
enable_ltd : STRING := "false";
enable_ltr : STRING := "false";
eq_adapt_seq_control : INTEGER := 0;
eq_dc_gain : INTEGER := 0;
eq_max_gradient_control : INTEGER := 0;
eqa_ctrl : INTEGER := 0;
eqb_ctrl : INTEGER := 0;
eqc_ctrl : INTEGER := 0;
eqd_ctrl : INTEGER := 0;
eqv_ctrl : INTEGER := 0;
eyemon_bandwidth : INTEGER := 0;
force_signal_detect : STRING := "true";
ignore_lock_detect : STRING := "false";
logical_channel_address : INTEGER := 0;
low_speed_test_select : INTEGER := 0;
offset_cancellation : INTEGER := 0;
ppm_gen1_2_xcnt_en : INTEGER := 1;
ppm_post_eidle : INTEGER := 0;
ppmselect : INTEGER := 0;
protocol_hint : STRING := "basic";
send_direct_reverse_serial_loopback : STRING := "None";
signal_detect_hysteresis : INTEGER := 4;
signal_detect_hysteresis_valid_threshold : INTEGER := 2;
signal_detect_loss_threshold : INTEGER := 3;
termination : STRING := "OCT 100 Ohms";
use_deser_double_data_width : STRING := "false";
use_external_termination : STRING := "false";
use_pma_direct : STRING := "false";
PARAM_DELAY : INTEGER := 0
);
PORT (
adaptcapture : IN STD_LOGIC := '0';
adcepowerdn : IN STD_LOGIC := '0';
adcereset : IN STD_LOGIC := '0';
adcestandby : IN STD_LOGIC := '0';
datain : IN STD_LOGIC := '0';
deserclock : IN STD_LOGIC_VECTOR(4 - 1 DOWNTO 0) := (others => '0');
dpriodisable : IN STD_LOGIC := '1';
dprioin : IN STD_LOGIC_VECTOR(300 - 1 DOWNTO 0) := (others => '0');
extra10gin : IN STD_LOGIC_VECTOR(38 - 1 DOWNTO 0) := (others => '0');
freqlock : IN STD_LOGIC := '0';
ignorephslck : IN STD_LOGIC := '0';
locktodata : IN STD_LOGIC := '0';
locktoref : IN STD_LOGIC := '0';
offsetcancellationen : IN STD_LOGIC := '0';
plllocked : IN STD_LOGIC := '0';
powerdn : IN STD_LOGIC := '0';
ppmdetectdividedclk : IN STD_LOGIC := '0';
ppmdetectrefclk : IN STD_LOGIC := '0';
recoverdatain : IN STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (others => '0');
rxpmareset : IN STD_LOGIC := '0';
seriallpbken : IN STD_LOGIC := '0';
seriallpbkin : IN STD_LOGIC := '0';
testbussel : IN STD_LOGIC_VECTOR(4 - 1 DOWNTO 0) := (others => '0');
adaptdone : OUT STD_LOGIC;
analogtestbus : OUT STD_LOGIC_VECTOR(8 - 1 DOWNTO 0);
clockout : OUT STD_LOGIC;
dataout : OUT STD_LOGIC;
dataoutfull : OUT STD_LOGIC_VECTOR(20 - 1 DOWNTO 0);
dprioout : OUT STD_LOGIC_VECTOR(300 - 1 DOWNTO 0);
locktorefout : OUT STD_LOGIC;
ppmdetectclkrel : OUT STD_LOGIC;
recoverdataout : OUT STD_LOGIC_VECTOR(64 - 1 DOWNTO 0);
reverselpbkout : OUT STD_LOGIC;
revserialfdbkout : OUT STD_LOGIC;
signaldetect : OUT STD_LOGIC
);
END COMPONENT;
--
-- stratixiv_hssi_tx_pcs
--
COMPONENT stratixiv_hssi_tx_pcs
GENERIC (
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
TimingChecksOn : Boolean := True;
tipd_bitslipboundaryselect :VitalDelayArrayType01(4 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_coreclk : VitalDelayType01 := DefpropDelay01;
tipd_ctrlenable :VitalDelayArrayType01(3 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_datain :VitalDelayArrayType01(39 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_datainfull :VitalDelayArrayType01(43 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_detectrxloop : VitalDelayType01 := DefpropDelay01;
tipd_digitalreset : VitalDelayType01 := DefpropDelay01;
tipd_dispval :VitalDelayArrayType01(3 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_dpriodisable : VitalDelayType01 := DefpropDelay01;
tipd_dprioin :VitalDelayArrayType01(149 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_enrevparallellpbk : VitalDelayType01 := DefpropDelay01;
tipd_forcedisp :VitalDelayArrayType01(3 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_forcedispcompliance : VitalDelayType01 := DefpropDelay01;
tipd_forceelecidle : VitalDelayType01 := DefpropDelay01;
tipd_freezptr : VitalDelayType01 := DefpropDelay01;
tipd_hipdatain :VitalDelayArrayType01(9 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_hipforceelecidle : VitalDelayType01 := DefpropDelay01;
tipd_hiptxdeemph : VitalDelayType01 := DefpropDelay01;
tipd_hiptxmargin :VitalDelayArrayType01(2 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_hippowerdn :VitalDelayArrayType01(1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_hipdetectrxloop : VitalDelayType01 := DefpropDelay01;
tipd_invpol : VitalDelayType01 := DefpropDelay01;
tipd_iqpphfifoxnwrenable :VitalDelayArrayType01(1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_iqpphfifoxnrdenable :VitalDelayArrayType01(1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_iqpphfifoxnbytesel :VitalDelayArrayType01(1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_iqpphfifoxnrdclk :VitalDelayArrayType01(1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_localrefclk : VitalDelayType01 := DefpropDelay01;
tipd_phfifobyteserdisable : VitalDelayType01 := DefpropDelay01;
tipd_phfifoxnbytesel :VitalDelayArrayType01(2 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_phfifoxnbottomwrenable : VitalDelayType01 := DefpropDelay01;
tipd_phfifoxntopwrenable : VitalDelayType01 := DefpropDelay01;
tipd_phfifoptrsreset : VitalDelayType01 := DefpropDelay01;
tipd_phfifoxnptrsreset :VitalDelayArrayType01(2 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_phfifoxnrdenable :VitalDelayArrayType01(2 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_phfiforddisable : VitalDelayType01 := DefpropDelay01;
tipd_phfifoxntopbytesel : VitalDelayType01 := DefpropDelay01;
tipd_phfifoxntoprdclk : VitalDelayType01 := DefpropDelay01;
tipd_phfifox4bytesel : VitalDelayType01 := DefpropDelay01;
tipd_phfifox4rdclk : VitalDelayType01 := DefpropDelay01;
tipd_phfiforeset : VitalDelayType01 := DefpropDelay01;
tipd_phfifox4rdenable : VitalDelayType01 := DefpropDelay01;
tipd_phfifowrenable : VitalDelayType01 := DefpropDelay01;
tipd_phfifoxnbottombytesel : VitalDelayType01 := DefpropDelay01;
tipd_phfifoxntoprdenable : VitalDelayType01 := DefpropDelay01;
tipd_phfifoxnrdclk :VitalDelayArrayType01(2 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_phfifox4wrenable : VitalDelayType01 := DefpropDelay01;
tipd_phfifoxnbottomrdenable : VitalDelayType01 := DefpropDelay01;
tipd_phfifoxnbottomrdclk : VitalDelayType01 := DefpropDelay01;
tipd_phfifoxnwrenable :VitalDelayArrayType01(2 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_pipestatetransdone : VitalDelayType01 := DefpropDelay01;
tipd_pipetxswing : VitalDelayType01 := DefpropDelay01;
tipd_pipetxmargin :VitalDelayArrayType01(2 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_pipetxdeemph : VitalDelayType01 := DefpropDelay01;
tipd_powerdn :VitalDelayArrayType01(1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_prbscidenable : VitalDelayType01 := DefpropDelay01;
tipd_rateswitch : VitalDelayType01 := DefpropDelay01;
tipd_rateswitchisdone : VitalDelayType01 := DefpropDelay01;
tipd_rateswitchxndone : VitalDelayType01 := DefpropDelay01;
tipd_refclk : VitalDelayType01 := DefpropDelay01;
tipd_revparallelfdbk :VitalDelayArrayType01(19 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_quadreset : VitalDelayType01 := DefpropDelay01;
tipd_xgmctrl : VitalDelayType01 := DefpropDelay01;
tipd_xgmdatain :VitalDelayArrayType01(7 DOWNTO 0) := (OTHERS => DefPropDelay01);
tsetup_ctrlenable_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_datain_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_detectrxloop_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_dispval_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_forcedisp_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_forcedispcompliance_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_phfifowrenable_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_forceelecidle_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_powerdn_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_pipetxdeemph_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_pipetxswing_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_pipetxmargin_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ctrlenable_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_datain_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_detectrxloop_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_dispval_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_forcedisp_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_forcedispcompliance_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_phfifowrenable_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_forceelecidle_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_powerdn_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_pipetxdeemph_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_pipetxswing_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_pipetxmargin_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_coreclk_phfifooverflow_posedge : VitalDelayType01 := DefPropDelay01;
tpd_coreclk_phfifounderflow_posedge : VitalDelayType01 := DefPropDelay01;
lpm_type : STRING := "stratixiv_hssi_tx_pcs";
allow_polarity_inversion : STRING := "false";
auto_spd_self_switch_enable : STRING := "false";
bitslip_enable : STRING := "false";
channel_bonding : STRING := "none"; -- none, x8, x4
channel_number : INTEGER := 0;
channel_width : INTEGER := 8;
core_clock_0ppm : STRING := "false";
datapath_low_latency_mode : STRING := "false"; --NEW_PARAM, RTL=
datapath_protocol : STRING := "basic"; --replaced by protocol_hint
disable_ph_low_latency_mode : STRING := "false";
disparity_mode : STRING := "none"; -- legacy, new, none
dprio_config_mode : STD_LOGIC_VECTOR(5 DOWNTO 0) := "000000";
elec_idle_delay : INTEGER := 6; -- new in 6.0 <3-6>
enable_bit_reversal : STRING := "false";
enable_idle_selection : STRING := "false";
enable_phfifo_bypass : STRING := "false";
enable_reverse_parallel_loopback : STRING := "false";
enable_self_test_mode : STRING := "false";
enable_symbol_swap : STRING := "false";
enc_8b_10b_compatibility_mode : STRING := "true";
enc_8b_10b_mode : STRING := "none"; -- cascade, normal, none
force_echar : STRING := "false";
force_kchar : STRING := "false";
hip_enable : STRING := "false";
iqp_bypass : STRING := "false";
iqp_ph_fifo_xn_select : INTEGER := 9999;
logical_channel_address : INTEGER := 0;
migrated_from_prev_family : STRING := "false";
ph_fifo_reg_mode : STRING := "false";
ph_fifo_reset_enable : STRING := "false";
ph_fifo_user_ctrl_enable : STRING := "false";
ph_fifo_xn_mapping0 : STRING := "none";
ph_fifo_xn_mapping1 : STRING := "none";
ph_fifo_xn_mapping2 : STRING := "none";
ph_fifo_xn_select : INTEGER := 9999;
pipe_auto_speed_nego_enable : STRING := "false";
pipe_freq_scale_mode : STRING := "Data width";
pipe_voltage_swing_control : STRING := "false"; --NEW_PARAM, RTL=
prbs_all_one_detect : STRING := "false";
prbs_cid_pattern : STRING := "false";
prbs_cid_pattern_length : INTEGER := 0;
protocol_hint : STRING := "basic";
refclk_select : STRING := "local"; -- cmu_clk_divider
reset_clock_output_during_digital_reset : STRING := "false";
self_test_mode : STRING := "incremental";
use_double_data_mode : STRING := "false";
use_serializer_double_data_mode : STRING := "false";
wr_clk_mux_select : STRING := "core_clk"; -- INT_CLK // int_clk
use_top_quad_as_mater : STRING := "true"; -- NEW_PARAM todo: select top/bottom to provide phfifo pointers
dprio_width : INTEGER := 150
);
PORT (
bitslipboundaryselect : IN STD_LOGIC_VECTOR(4 DOWNTO 0) := (others => '0');
coreclk : IN STD_LOGIC := '0';
ctrlenable : IN STD_LOGIC_VECTOR(3 DOWNTO 0) := (others => '0');
datain : IN STD_LOGIC_VECTOR(39 DOWNTO 0) := (others => '0');
datainfull : IN STD_LOGIC_VECTOR(43 DOWNTO 0) := (others => '0'); -- WYS_TO_CHANGE
detectrxloop : IN STD_LOGIC := '0';
digitalreset : IN STD_LOGIC := '0';
dispval : IN STD_LOGIC_VECTOR(3 DOWNTO 0) := (others => '0');
dpriodisable : IN STD_LOGIC := '1';
dprioin : IN STD_LOGIC_VECTOR(149 DOWNTO 0) := (others => '0');
elecidleinfersel : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (others => '0');
enrevparallellpbk : IN STD_LOGIC := '0';
forcedisp : IN STD_LOGIC_VECTOR(3 DOWNTO 0) := (others => '0'); --fix_width
forcedispcompliance : IN STD_LOGIC := '0';
forceelecidle : IN STD_LOGIC := '0';
freezptr : IN STD_LOGIC := '0';
hipdatain : IN STD_LOGIC_VECTOR(9 DOWNTO 0) := (others => '0');
hipdetectrxloop : IN STD_LOGIC := '0';
hipelecidleinfersel : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (others => '0');
hipforceelecidle : IN STD_LOGIC := '0';
hippowerdn : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (others => '0');
hiptxdeemph : IN STD_LOGIC := '0';
hiptxmargin : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (others => '0');
invpol : IN STD_LOGIC := '0';
iqpphfifoxnbytesel : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (others => '0');
iqpphfifoxnrdclk : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (others => '0');
iqpphfifoxnrdenable : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (others => '0');
iqpphfifoxnwrenable : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (others => '0');
localrefclk : IN STD_LOGIC := '0';
phfifobyteserdisable : IN STD_LOGIC := '0';
phfifoptrsreset : IN STD_LOGIC := '0';
phfiforddisable : IN STD_LOGIC := '0';
phfiforeset : IN STD_LOGIC := '0';
phfifowrenable : IN STD_LOGIC := '1';
phfifox4bytesel : IN STD_LOGIC := '0';
phfifox4rdclk : IN STD_LOGIC := '0';
phfifox4rdenable : IN STD_LOGIC := '0';
phfifox4wrenable : IN STD_LOGIC := '0';
phfifoxnbottombytesel : IN STD_LOGIC := '0';
phfifoxnbottomrdclk : IN STD_LOGIC := '0';
phfifoxnbottomrdenable : IN STD_LOGIC := '0';
phfifoxnbottomwrenable : IN STD_LOGIC := '0';
phfifoxnbytesel : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (others => '0');
phfifoxnptrsreset : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (others => '0');
phfifoxnrdclk : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (others => '0');
phfifoxnrdenable : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (others => '0');
phfifoxntopbytesel : IN STD_LOGIC := '0';
phfifoxntoprdclk : IN STD_LOGIC := '0';
phfifoxntoprdenable : IN STD_LOGIC := '0';
phfifoxntopwrenable : IN STD_LOGIC := '0';
phfifoxnwrenable : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (others => '0');
pipestatetransdone : IN STD_LOGIC := '0';
pipetxdeemph : IN STD_LOGIC := '0'; --NEW; RTL=txdeemph;
pipetxmargin : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (others => '0'); --NEW; RTL=txmargin[2:0]
pipetxswing : IN STD_LOGIC := '0'; --NEW; RTL=txswing
powerdn : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (others => '0');
prbscidenable : IN STD_LOGIC := '0';
quadreset : IN STD_LOGIC := '0';
rateswitch : IN STD_LOGIC := '0'; --NEW, RTL=rate
rateswitchisdone : IN STD_LOGIC := '0';
rateswitchxndone : IN STD_LOGIC := '0';
refclk : IN STD_LOGIC := '0';
revparallelfdbk : IN STD_LOGIC_VECTOR(19 DOWNTO 0) := (others => '0');
xgmctrl : IN STD_LOGIC := '0';
xgmdatain : IN STD_LOGIC_VECTOR(7 DOWNTO 0) := (others => '0');
clkout : OUT STD_LOGIC;
coreclkout : OUT STD_LOGIC;
dataout : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
dprioout : OUT STD_LOGIC_VECTOR(149 DOWNTO 0);
forceelecidleout : OUT STD_LOGIC;
grayelecidleinferselout : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
hiptxclkout : OUT STD_LOGIC;
iqpphfifobyteselout : OUT STD_LOGIC;
iqpphfifordclkout : OUT STD_LOGIC;
iqpphfifordenableout : OUT STD_LOGIC;
iqpphfifowrenableout : OUT STD_LOGIC;
parallelfdbkout : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
phfifobyteselout : OUT STD_LOGIC;
phfifooverflow : OUT STD_LOGIC;
phfifordclkout : OUT STD_LOGIC;
phfiforddisableout : OUT STD_LOGIC;
phfifordenableout : OUT STD_LOGIC;
phfiforesetout : OUT STD_LOGIC;
phfifounderflow : OUT STD_LOGIC;
phfifowrenableout : OUT STD_LOGIC;
pipeenrevparallellpbkout : OUT STD_LOGIC;
pipepowerdownout : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
pipepowerstateout : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
rateswitchout : OUT STD_LOGIC;
rdenablesync : OUT STD_LOGIC;
txdetectrx : OUT STD_LOGIC;
xgmctrlenable : OUT STD_LOGIC;
xgmdataout : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
--
-- stratixiv_hssi_rx_pcs
--
COMPONENT stratixiv_hssi_rx_pcs
GENERIC (
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
TimingChecksOn : Boolean := True;
tipd_phfifox8bytesel : VitalDelayType01 := DefpropDelay01;
tipd_xgmctrlin : VitalDelayType01 := DefpropDelay01;
tipd_pipepowerdown :VitalDelayArrayType01(1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_parallelfdbk :VitalDelayArrayType01(19 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_masterclk : VitalDelayType01 := DefpropDelay01;
tipd_iqpphfifoxnwrclk :VitalDelayArrayType01(1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_rxelecidlerateswitch : VitalDelayType01 := DefpropDelay01;
tipd_pipepowerstate :VitalDelayArrayType01(3 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_alignstatussync : VitalDelayType01 := DefpropDelay01;
tipd_powerdn :VitalDelayArrayType01(1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_refclk : VitalDelayType01 := DefpropDelay01;
tipd_phfifox4bytesel : VitalDelayType01 := DefpropDelay01;
tipd_bitslip : VitalDelayType01 := DefpropDelay01;
tipd_phfiforeset : VitalDelayType01 := DefpropDelay01;
tipd_dprioin :VitalDelayArrayType01(399 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_disablefifowrin : VitalDelayType01 := DefpropDelay01;
tipd_ppmdetectdividedclk : VitalDelayType01 := DefpropDelay01;
tipd_datain :VitalDelayArrayType01(19 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_enabledeskew : VitalDelayType01 := DefpropDelay01;
tipd_hippowerdown :VitalDelayArrayType01(1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_revbyteorderwa : VitalDelayType01 := DefpropDelay01;
tipd_phfifox4wrenable : VitalDelayType01 := DefpropDelay01;
tipd_dpriodisable : VitalDelayType01 := DefpropDelay01;
tipd_phfifox8wrclk : VitalDelayType01 := DefpropDelay01;
tipd_enabyteord : VitalDelayType01 := DefpropDelay01;
tipd_invpol : VitalDelayType01 := DefpropDelay01;
tipd_phfifox8rdenable : VitalDelayType01 := DefpropDelay01;
tipd_revbitorderwa : VitalDelayType01 := DefpropDelay01;
tipd_localrefclk : VitalDelayType01 := DefpropDelay01;
tipd_enapatternalign : VitalDelayType01 := DefpropDelay01;
tipd_iqpphfifoxnrdenable :VitalDelayArrayType01(1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_iqpphfifoxnptrsreset :VitalDelayArrayType01(1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_phfifowrdisable : VitalDelayType01 := DefpropDelay01;
tipd_signaldetected : VitalDelayType01 := DefpropDelay01;
tipd_alignstatus : VitalDelayType01 := DefpropDelay01;
tipd_rxdetectvalid : VitalDelayType01 := DefpropDelay01;
tipd_quadreset : VitalDelayType01 := DefpropDelay01;
tipd_autospdxnconfigsel :VitalDelayArrayType01(2 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_recoveredclk : VitalDelayType01 := DefpropDelay01;
tipd_hiprateswitch : VitalDelayType01 := DefpropDelay01;
tipd_phfifordenable : VitalDelayType01 := DefpropDelay01;
tipd_phfifox4wrclk : VitalDelayType01 := DefpropDelay01;
tipd_phfifoxnbytesel :VitalDelayArrayType01(2 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_rmfifowrena : VitalDelayType01 := DefpropDelay01;
tipd_a1a2size : VitalDelayType01 := DefpropDelay01;
tipd_phfifox8wrenable : VitalDelayType01 := DefpropDelay01;
tipd_phfifoxnptrsreset :VitalDelayArrayType01(2 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_iqpphfifoxnwrenable :VitalDelayArrayType01(1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_phfifoxnrdenable :VitalDelayArrayType01(2 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_rateswitchisdone : VitalDelayType01 := DefpropDelay01;
tipd_elecidleinfersel :VitalDelayArrayType01(2 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_hip8b10binvpolarity : VitalDelayType01 := DefpropDelay01;
tipd_rateswitchxndone : VitalDelayType01 := DefpropDelay01;
tipd_iqpautospdxnspgchg :VitalDelayArrayType01(1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_rmfiforeset : VitalDelayType01 := DefpropDelay01;
tipd_coreclk : VitalDelayType01 := DefpropDelay01;
tipd_rmfifordena : VitalDelayType01 := DefpropDelay01;
tipd_disablefifordin : VitalDelayType01 := DefpropDelay01;
tipd_rateswitch : VitalDelayType01 := DefpropDelay01;
tipd_hipelecidleinfersel :VitalDelayArrayType01(2 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_phfifox4rdenable : VitalDelayType01 := DefpropDelay01;
tipd_pipe8b10binvpolarity : VitalDelayType01 := DefpropDelay01;
tipd_fifordin : VitalDelayType01 := DefpropDelay01;
tipd_ppmdetectrefclk : VitalDelayType01 := DefpropDelay01;
tipd_prbscidenable : VitalDelayType01 := DefpropDelay01;
tipd_digitalreset : VitalDelayType01 := DefpropDelay01;
tipd_rxfound :VitalDelayArrayType01(1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_cdrctrllocktorefcl : VitalDelayType01 := DefpropDelay01;
tipd_phfifoxnwrclk :VitalDelayArrayType01(2 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_iqpphfifoxnbytesel :VitalDelayArrayType01(1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_autospdxnspdchg :VitalDelayArrayType01(2 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_phfifoxnwrenable :VitalDelayArrayType01(2 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_fiforesetrd : VitalDelayType01 := DefpropDelay01;
tipd_xgmdatain :VitalDelayArrayType01(7 DOWNTO 0) := (OTHERS => DefPropDelay01);
tsetup_phfifordenable_coreclk_noedge_posedge: VitalDelayType := DefSetupHoldCnst;
thold_phfifordenable_coreclk_noedge_posedge: VitalDelayType := DefSetupHoldCnst;
tpd_coreclk_a1a2sizeout_posedge: VitalDelayType01 := DefPropDelay01;
tpd_coreclk_ctrldetect_posedge: VitalDelayType01 := DefPropDelay01;
tpd_coreclk_dataout_posedge: VitalDelayType01 := DefPropDelay01;
tpd_coreclk_dataoutfull_posedge: VitalDelayType01 := DefPropDelay01;
tpd_coreclk_disperr_posedge: VitalDelayType01 := DefPropDelay01;
tpd_coreclk_errdetect_posedge: VitalDelayType01 := DefPropDelay01;
tpd_coreclk_patterndetect_posedge: VitalDelayType01 := DefPropDelay01;
tpd_coreclk_rmfifodatadeleted_posedge: VitalDelayType01 := DefPropDelay01;
tpd_coreclk_rmfifodatainserted_posedge: VitalDelayType01 := DefPropDelay01;
tpd_coreclk_runningdisp_posedge: VitalDelayType01 := DefPropDelay01;
tpd_coreclk_syncstatus_posedge: VitalDelayType01 := DefPropDelay01;
tpd_coreclk_pipebufferstat_posedge : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tpd_coreclk_byteorderalignstatus_posedge: VitalDelayType01 := DefPropDelay01;
tpd_coreclk_phfifooverflow_posedge: VitalDelayType01 := DefPropDelay01;
tpd_coreclk_phfifounderflow_posedge: VitalDelayType01 := DefPropDelay01;
tpd_coreclk_pipestatus_posedge: VitalDelayType01 := DefPropDelay01;
tpd_coreclk_pipephydonestatus_posedge: VitalDelayType01 := DefPropDelay01;
tpd_coreclk_pipedatavalid_posedge: VitalDelayType01 := DefPropDelay01;
lpm_type : STRING := "stratixiv_hssi_rx_pcs";
align_ordered_set_based : STRING := "false";
align_pattern : STRING := "0101111100"; -- word align: size of align_pattern_length;
align_pattern_length : INTEGER := 10; -- <7, 8, 10, 16, 20, 32, 40>;
align_to_deskew_pattern_pos_disp_only : STRING := "false"; -- <true/false>;
allow_align_polarity_inversion : STRING := "false";
allow_pipe_polarity_inversion : STRING := "false";
auto_spd_deassert_ph_fifo_rst_count : INTEGER := 0;
auto_spd_phystatus_notify_count : INTEGER := 0;
auto_spd_self_switch_enable : STRING := "false";
bit_slip_enable : STRING := "false";
byte_order_back_compat_enable : STRING := "false";
byte_order_double_data_mode_mask_enable : STRING := "false";
byte_order_invalid_code_or_run_disp_error : STRING := "false";
byte_order_mode : STRING := "none"; --NEW_PARAM_replace byte_ordering_mode
byte_order_pad_pattern : STRING := "0101111100"; -- <10-bit binary string>;
byte_order_pattern : STRING := "0101111100"; -- <10-bit binary string>;
byte_order_pld_ctrl_enable : STRING := "false"; --ww47_cram added in build 165
cdrctrl_bypass_ppm_detector_cycle : INTEGER := 0;
cdrctrl_cid_mode_enable : STRING := "false";
cdrctrl_enable : STRING := "false";
cdrctrl_mask_cycle : INTEGER := 0;
cdrctrl_min_lock_to_ref_cycle : INTEGER := 0;
cdrctrl_rxvalid_mask : STRING := "false";
channel_bonding : STRING := "none"; -- <none, x4, x8>;
channel_number : INTEGER := 0; -- <integer 0-3>;
channel_width : INTEGER := 10; -- <integer 8,10,16,20,32,40>;
clk1_mux_select : STRING := "recvd_clk"; -- <RECVD_CLK, MASTER_CLK, LOCAL_REFCLK, DIGITAL_REFCLK>;
clk2_mux_select : STRING := "recvd_clk"; -- <RECVD_CLK, LOCAL_REFCLK, DIGITAL_REFCLK, CORE_CLK>;
clk_pd_enable : STRING := "false"; --ww47_cram_p1
core_clock_0ppm : STRING := "false";
datapath_low_latency_mode : STRING := "false";
datapath_protocol : STRING := "basic"; -- <basic/pipe/xaui> replaced by protocol_hint
dec_8b_10b_compatibility_mode : STRING := "true";
dec_8b_10b_mode : STRING := "none"; -- <normal/cascaded/none>;
dec_8b_10b_polarity_inv_enable : STRING := "false";
deskew_pattern : STRING := "1100111100"; -- K28.3
disable_auto_idle_insertion : STRING := "false";
disable_running_disp_in_word_align : STRING := "false";
disallow_kchar_after_pattern_ordered_set : STRING := "false";
dprio_config_mode : STD_LOGIC_VECTOR(5 DOWNTO 0) := "000000";
elec_idle_eios_detect_priority_over_eidle_disable : STRING := "false";
elec_idle_gen1_sigdet_enable : STRING := "false";
elec_idle_infer_enable : STRING := "false";
elec_idle_k_detect : STRING := "false";
elec_idle_num_com_detect : INTEGER := 0;
enable_bit_reversal : STRING := "false";
enable_deep_align : STRING := "false";
enable_deep_align_byte_swap : STRING := "false";
enable_self_test_mode : STRING := "false";
enable_true_complement_match_in_word_align : STRING := "true";
error_from_wa_or_8b_10b_select : STRING := "false";
force_signal_detect_dig : STRING := "false";
hip_enable : STRING := "false";
infiniband_invalid_code : INTEGER := 0; -- <integer 0-3>;
insert_pad_on_underflow : STRING := "false";
iqp_bypass : STRING := "false";
iqp_ph_fifo_xn_select : INTEGER := 9999;
logical_channel_address : INTEGER := 0;
migrated_from_prev_family : STRING := "false"; -- b165
num_align_code_groups_in_ordered_set : INTEGER := 1; -- <integer 0-3>;
num_align_cons_good_data : INTEGER := 3; -- wordalign<Integer 1-256>;
num_align_cons_pat : INTEGER := 4; -- <Integer 1-256>;
num_align_loss_sync_error : INTEGER := 1; --NEW_PARAM_replace align_loss_sync_error_num
ph_fifo_disable : STRING := "false";
ph_fifo_low_latency_enable : STRING := "false";
ph_fifo_reg_mode : STRING := "false";
ph_fifo_reset_enable : STRING := "false";
ph_fifo_user_ctrl_enable : STRING := "false";
ph_fifo_xn_mapping0 : STRING := "none"; --ww47_cram_p1
ph_fifo_xn_mapping1 : STRING := "none"; --ww47_cram_p1
ph_fifo_xn_mapping2 : STRING := "none"; --ww47_cram_p1
ph_fifo_xn_select : INTEGER := 9999;
phystatus_delay : INTEGER := 0;
phystatus_reset_toggle : STRING := "false";
pipe_auto_speed_nego_enable : STRING := "false";
pipe_freq_scale_mode : STRING := "Data width";
pipe_hip_enable : STRING := "false"; --NEW_PARAM todo: remove
pma_done_count : INTEGER := 53392; --ww47_cram_p1
prbs_all_one_detect : STRING := "false";
prbs_cid_pattern : STRING := "false";
prbs_cid_pattern_length : INTEGER := 0;
protocol_hint : STRING := "basic";
rate_match_almost_empty_threshold : INTEGER := 11; -- <integer 0-15>;
rate_match_almost_full_threshold : INTEGER := 13; -- <integer 0-15>;
rate_match_back_to_back : STRING := "false";
rate_match_delete_threshold : INTEGER := 13;
rate_match_empty_threshold : INTEGER := 5;
rate_match_fifo_mode : STRING := "false"; -- <normal/cascaded/generic/cascaded_generic/none> in s2gx, bool in s4gx;
rate_match_full_threshold : INTEGER := 20;
rate_match_insert_threshold : INTEGER := 11;
rate_match_ordered_set_based : STRING := "false"; -- <integer 10 or 20>;
rate_match_pattern1 : STRING := "00000000000010111100"; -- <20-bit binary string>;
rate_match_pattern2 : STRING := "00000000000010111100"; -- <20-bit binary string>;
rate_match_pattern_size : INTEGER := 10; -- <integer 10 or 20>;
rate_match_pipe_enable : STRING := "false";
rate_match_reset_enable : STRING := "true"; --NEW_PARAM - default diff from atom
rate_match_skip_set_based : STRING := "false";
rate_match_start_threshold : INTEGER := 7;
rd_clk_mux_select : STRING := "int_clk"; -- <INT_CLK, CORE_CLK>;
recovered_clk_mux_select : STRING := "recvd_clk"; -- <RECVD_CLK, LOCAL_REFCLK, DIGITAL_REFCLK>;
reset_clock_output_during_digital_reset : STRING := "false";
run_length : INTEGER := 200; -- <5-320 or 4-254 depending on the deserialization factor>;
run_length_enable : STRING := "false";
rx_detect_bypass : STRING := "false";
rx_phfifo_wait_cnt : INTEGER := 32;
rxstatus_error_report_mode : INTEGER := 0;
self_test_mode : STRING := "incremental"; -- <PRBS_7,PRBS_8,PRBS_10,PRBS_23,low_freq,mixed_freq,high_freq,incremental,cjpat,crpat>;
test_bus_sel : INTEGER := 0;
use_alignment_state_machine : STRING := "false";
use_deserializer_double_data_mode : STRING := "false";
use_deskew_fifo : STRING := "false";
use_double_data_mode : STRING := "false";
use_parallel_loopback : STRING := "false";
use_rising_edge_triggered_pattern_align : STRING := "false"; -- <true/false>; //83 para: new=23 rem=40
enable_phfifo_bypass : STRING := "false"
);
PORT (
a1a2size : IN STD_LOGIC := '0';
alignstatus : IN STD_LOGIC := '0';
alignstatussync : IN STD_LOGIC := '0';
autospdxnconfigsel : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (others => '0'); -- config_sel_centrl, quad_up, quad_down
autospdxnspdchg : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (others => '0'); -- From CMU.spped-change_centrl, rx3(up), rx0(down)
bitslip : IN STD_LOGIC := '0';
cdrctrllocktorefcl : IN STD_LOGIC := '0'; -- pld_ltr
coreclk : IN STD_LOGIC := '0';
datain : IN STD_LOGIC_VECTOR(19 DOWNTO 0) := (others => '0'); --NEW: updated width
digitalreset : IN STD_LOGIC := '0';
disablefifordin : IN STD_LOGIC := '0';
disablefifowrin : IN STD_LOGIC := '0';
dpriodisable : IN STD_LOGIC := '1';
dprioin : IN STD_LOGIC_VECTOR(399 DOWNTO 0) := (others => '0');
elecidleinfersel : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (others => '0');
enabledeskew : IN STD_LOGIC := '0';
enabyteord : IN STD_LOGIC := '0';
enapatternalign : IN STD_LOGIC := '0';
fifordin : IN STD_LOGIC := '0';
fiforesetrd : IN STD_LOGIC := '0';
grayelecidleinferselfromtx : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (others => '0');
hip8b10binvpolarity : IN STD_LOGIC := '0'; -- hip_rxpolarity
hipelecidleinfersel : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (others => '0'); -- hip_eidleinfersel_ch
hippowerdown : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (others => '0'); -- hip_powerdown_ch
hiprateswitch : IN STD_LOGIC := '0'; -- hip_rate
invpol : IN STD_LOGIC := '0';
iqpautospdxnspgchg : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (others => '0'); -- speed_change_in_pipe_quad_up, down
iqpphfifoxnbytesel : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (others => '0'); -- wr_enable_ptrs_in_pipe_quad_up, down
iqpphfifoxnptrsreset : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (others => '0'); -- reset_pc_ptrs_in_pipe_quad_up, down
iqpphfifoxnrdenable : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (others => '0'); -- rd_enable_ptrs_in_pipe_quad_up, down
iqpphfifoxnwrclk : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (others => '0'); -- rx_div2_sync_in_pipe_quad_up, down
iqpphfifoxnwrenable : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (others => '0'); -- wr_enable_ptrs_in_pipe_quad_up, down
localrefclk : IN STD_LOGIC := '0';
masterclk : IN STD_LOGIC := '0';
parallelfdbk : IN STD_LOGIC_VECTOR(19 DOWNTO 0) := (others => '0');
phfifordenable : IN STD_LOGIC := '1';
phfiforeset : IN STD_LOGIC := '0';
phfifowrdisable : IN STD_LOGIC := '0';
phfifox4bytesel : IN STD_LOGIC := '0';
phfifox4rdenable : IN STD_LOGIC := '0';
phfifox4wrclk : IN STD_LOGIC := '0';
phfifox4wrenable : IN STD_LOGIC := '0';
phfifox8bytesel : IN STD_LOGIC := '0';
phfifox8rdenable : IN STD_LOGIC := '0';
phfifox8wrclk : IN STD_LOGIC := '0';
phfifox8wrenable : IN STD_LOGIC := '0';
phfifoxnbytesel : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (others => '0'); -- rx_we_in_centrl, quad_up, quad_down
phfifoxnptrsreset : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (others => '0'); -- ph fifo. From CMU to both RX & TX.
phfifoxnrdenable : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (others => '0'); -- rd_enable_in_centrl, quad_up, quad_down
phfifoxnwrclk : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (others => '0'); -- ph fifo. From CMU to RX.
phfifoxnwrenable : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (others => '0'); -- wr_enable_in_centrl, quad_up, quad_down
pipe8b10binvpolarity : IN STD_LOGIC := '0';
pipeenrevparallellpbkfromtx : IN STD_LOGIC := '0';
pipepowerdown : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (others => '0');
pipepowerstate : IN STD_LOGIC_VECTOR(3 DOWNTO 0) := (others => '0');
pmatestbusin : IN STD_LOGIC_VECTOR(7 DOWNTO 0) := (others => '0');
powerdn : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (others => '0');
ppmdetectdividedclk : IN STD_LOGIC := '0';
ppmdetectrefclk : IN STD_LOGIC := '0';
prbscidenable : IN STD_LOGIC := '0'; -- prbs_cid_en
quadreset : IN STD_LOGIC := '0';
rateswitch : IN STD_LOGIC := '0';
rateswitchisdone : IN STD_LOGIC := '0';
rateswitchxndone : IN STD_LOGIC := '0';
recoveredclk : IN STD_LOGIC := '0';
refclk : IN STD_LOGIC := '0';
revbitorderwa : IN STD_LOGIC := '0';
revbyteorderwa : IN STD_LOGIC := '0';
rmfifordena : IN STD_LOGIC := '0';
rmfiforeset : IN STD_LOGIC := '0';
rmfifowrena : IN STD_LOGIC := '0';
rxdetectvalid : IN STD_LOGIC := '0';
rxelecidlerateswitch : IN STD_LOGIC := '0';
rxfound : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (others => '0');
signaldetected : IN STD_LOGIC := '0';
wareset : IN STD_LOGIC := '0'; -- new in 9.1
xauidelcondmet : IN STD_LOGIC := '0';
xauififoovr : IN STD_LOGIC := '0';
xauiinsertincomplete : IN STD_LOGIC := '0';
xauilatencycomp : IN STD_LOGIC := '0';
xgmctrlin : IN STD_LOGIC := '0';
xgmdatain : IN STD_LOGIC_VECTOR(7 DOWNTO 0) := (others => '0'); --54 ins ---
a1a2sizeout : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
a1detect : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
a2detect : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
adetectdeskew : OUT STD_LOGIC;
alignstatussyncout : OUT STD_LOGIC;
autospdrateswitchout : OUT STD_LOGIC;
autospdspdchgout : OUT STD_LOGIC; --ww47_out speed_chang_out_pipe
bistdone : OUT STD_LOGIC;
bisterr : OUT STD_LOGIC;
bitslipboundaryselectout : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); --ww47_out wa_boundary
byteorderalignstatus : OUT STD_LOGIC;
cdrctrlearlyeios : OUT STD_LOGIC; --ww47_out Asserted when K_I or K_X_I is detected on the incoming data. To PMA and/or PLD?
cdrctrllocktorefclkout : OUT STD_LOGIC; --ww47_out Force CDR(RX PLL) to LTR.
clkout : OUT STD_LOGIC;
coreclkout : OUT STD_LOGIC; --ww47_out Sim Only. From RX Ch0 to CMU
ctrldetect : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
dataout : OUT STD_LOGIC_VECTOR(39 DOWNTO 0);
dataoutfull : OUT STD_LOGIC_VECTOR(63 DOWNTO 0); -- new in 6.1
digitaltestout : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
disablefifordout : OUT STD_LOGIC;
disablefifowrout : OUT STD_LOGIC;
disperr : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
dprioout : OUT STD_LOGIC_VECTOR(399 DOWNTO 0);
errdetect : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
fifordout : OUT STD_LOGIC;
hipdataout : OUT STD_LOGIC_VECTOR(8 DOWNTO 0); --ww47_out hip_rxd_ch(8:0)
hipdatavalid : OUT STD_LOGIC; --ww47_out hip_rxvalid
hipelecidle : OUT STD_LOGIC; --ww47_out hip_rxelecidle
hipphydonestatus : OUT STD_LOGIC; --ww47_out hip_phystatus
hipstatus : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); --ww47_out hip_rxstatus_ch(2:0)
iqpphfifobyteselout : OUT STD_LOGIC; --ww47_out rx_we_out_pipe
iqpphfifoptrsresetout : OUT STD_LOGIC; --ww47_out reset_pc_pters_out_pipe
iqpphfifordenableout : OUT STD_LOGIC; --ww47_out rd_enable_pipe_out
iqpphfifowrclkout : OUT STD_LOGIC; --ww47_out rx_div2_sync_out_pipe
iqpphfifowrenableout : OUT STD_LOGIC; --ww47_out wr_enable_out_pipe
k1detect : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
k2detect : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
patterndetect : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
phfifobyteselout : OUT STD_LOGIC;
phfifobyteserdisableout : OUT STD_LOGIC; --ww47_out From Auto Speed Neg to TX
phfifooverflow : OUT STD_LOGIC;
phfifoptrsresetout : OUT STD_LOGIC; --ww47_out From Auto Speed Neg to TX
phfifordenableout : OUT STD_LOGIC;
phfiforesetout : OUT STD_LOGIC; --ww47_out Sim Only. From RX Ch0 to CMU
phfifounderflow : OUT STD_LOGIC;
phfifowrclkout : OUT STD_LOGIC;
phfifowrdisableout : OUT STD_LOGIC; --ww47_out Sim Only. From RX Ch0 to CMU
phfifowrenableout : OUT STD_LOGIC;
pipebufferstat : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
pipedatavalid : OUT STD_LOGIC;
pipeelecidle : OUT STD_LOGIC;
pipephydonestatus : OUT STD_LOGIC;
pipestatus : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
pipestatetransdoneout : OUT STD_LOGIC;
rateswitchout : OUT STD_LOGIC;
rdalign : OUT STD_LOGIC;
revparallelfdbkdata : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
rlv : OUT STD_LOGIC;
rmfifoalmostempty : OUT STD_LOGIC;
rmfifoalmostfull : OUT STD_LOGIC;
rmfifodatadeleted : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
rmfifodatainserted : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
rmfifoempty : OUT STD_LOGIC;
rmfifofull : OUT STD_LOGIC;
runningdisp : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
signaldetect : OUT STD_LOGIC;
syncstatus : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
syncstatusdeskew : OUT STD_LOGIC;
xauidelcondmetout : OUT STD_LOGIC;
xauififoovrout : OUT STD_LOGIC;
xauiinsertincompleteout : OUT STD_LOGIC;
xauilatencycompout : OUT STD_LOGIC;
xgmctrldet : OUT STD_LOGIC;
xgmdataout : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
xgmdatavalid : OUT STD_LOGIC;
xgmrunningdisp : OUT STD_LOGIC
);
END COMPONENT;
--
-- stratixiv_hssi_cmu
--
COMPONENT stratixiv_hssi_cmu
GENERIC (
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
TimingChecksOn : Boolean := True;
tipd_txphfiforddisable : VitalDelayType01 := DefpropDelay01;
tipd_txctrl : VitalDelayArrayType01(3 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_rxdatain : VitalDelayArrayType01(31 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_txclk : VitalDelayType01 := DefpropDelay01;
tipd_syncstatus : VitalDelayArrayType01(3 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_rxpcsdprioin : VitalDelayArrayType01(1599 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_txdigitalreset : VitalDelayArrayType01(3 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_txdatain : VitalDelayArrayType01(31 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_scanclk : VitalDelayType01 := DefpropDelay01;
tipd_rateswitchdonein : VitalDelayType01 := DefpropDelay01;
tipd_rdenablesync : VitalDelayType01 := DefpropDelay01;
tipd_dpclk : VitalDelayType01 := DefpropDelay01;
tipd_rxphfiforeset : VitalDelayType01 := DefpropDelay01;
tipd_testin : VitalDelayArrayType01(9999 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_txpllreset : VitalDelayArrayType01(1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_rxrunningdisp : VitalDelayArrayType01(3 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_rxdatavalid : VitalDelayArrayType01(3 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_refclkdividerdprioin : VitalDelayArrayType01(1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_txpcsdprioin : VitalDelayArrayType01(599 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_dprioin : VitalDelayType01 := DefpropDelay01;
tipd_rateswitch : VitalDelayType01 := DefpropDelay01;
tipd_rxctrl : VitalDelayArrayType01(3 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_rxanalogreset : VitalDelayArrayType01(5 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_rxclk : VitalDelayType01 := DefpropDelay01;
tipd_txphfifowrenable : VitalDelayType01 := DefpropDelay01;
tipd_rxphfifowrdisable : VitalDelayType01 := DefpropDelay01;
tipd_rdalign : VitalDelayArrayType01(3 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_fixedclk : VitalDelayArrayType01(5 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_dpriodisable : VitalDelayType01 := DefpropDelay01;
tipd_scanmode : VitalDelayType01 := DefpropDelay01;
tipd_rxphfifordenable : VitalDelayType01 := DefpropDelay01;
tipd_cmuplldprioin : VitalDelayArrayType01(1799 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_txphfiforeset : VitalDelayType01 := DefpropDelay01;
tipd_txcoreclk : VitalDelayType01 := DefpropDelay01;
tipd_adet : VitalDelayArrayType01(3 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_rxdigitalreset : VitalDelayArrayType01(3 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_rxpmadprioin : VitalDelayArrayType01(1799 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_cmudividerdprioin : VitalDelayArrayType01(599 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_rxcoreclk : VitalDelayType01 := DefpropDelay01;
tipd_dprioload : VitalDelayType01 := DefpropDelay01;
tipd_scanin : VitalDelayArrayType01(22 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_quadreset : VitalDelayType01 := DefpropDelay01;
tipd_nonuserfromcal : VitalDelayType01 := DefpropDelay01;
tipd_scanshift : VitalDelayType01 := DefpropDelay01;
tipd_txpmadprioin : VitalDelayArrayType01(1799 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_recovclk : VitalDelayType01 := DefpropDelay01;
tipd_rxpowerdown : VitalDelayArrayType01(5 DOWNTO 0) := (OTHERS => DefPropDelay01);
tsetup_dprioin_dpclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_dprioin_dpclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_dpclk_dprioout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_dpclk_dpriooe_posedge : VitalDelayType01 := DefPropDelay01;
lpm_type : STRING := "stratixiv_hssi_cmu";
analog_test_bus_enable : STRING := "false";
auto_spd_deassert_ph_fifo_rst_count : INTEGER := 0;
auto_spd_phystatus_notify_count : INTEGER := 0;
bonded_quad_mode : STRING := "none";
bypass_bandgap : STRING := "false";
central_test_bus_select : INTEGER := 0;
cmu_type : STRING := "regular";
devaddr : INTEGER := 1;
dprio_config_mode : STD_LOGIC_VECTOR(5 DOWNTO 0) := "000000";
in_xaui_mode : STRING := "false";
migrated_from_prev_family : STRING := "false";
num_con_align_chars_for_align : INTEGER := 4;
num_con_errors_for_align_loss : INTEGER := 2;
num_con_good_data_for_align_approach : INTEGER := 3;
offset_all_errors_align : STRING := "false";
pipe_auto_speed_nego_enable : STRING := "false";
pipe_freq_scale_mode : STRING := "Data width";
pma_done_count : INTEGER := 0;
portaddr : INTEGER := 1;
rx0_auto_spd_self_switch_enable : STRING := "false";
rx0_channel_bonding : STRING := "none";
rx0_clk1_mux_select : STRING := "recovered clock";
rx0_clk2_mux_select : STRING := "recovered clock";
rx0_clk_pd_enable : STRING := "false";
rx0_ph_fifo_reg_mode : STRING := "false";
rx0_ph_fifo_reset_enable : STRING := "false";
rx0_ph_fifo_user_ctrl_enable : STRING := "false";
rx0_phfifo_wait_cnt : INTEGER := 0;
rx0_rd_clk_mux_select : STRING := "int clock";
rx0_recovered_clk_mux_select : STRING := "recovered clock";
rx0_reset_clock_output_during_digital_reset : STRING := "false";
rx0_use_double_data_mode : STRING := "false";
rx_master_direction : STRING := "none";
rx_xaui_sm_backward_compatible_enable : STRING := "false";
test_mode : STRING := "false";
tx0_auto_spd_self_switch_enable : STRING := "false";
tx0_channel_bonding : STRING := "none";
tx0_clk_pd_enable : STRING := "false";
tx0_ph_fifo_reg_mode : STRING := "false";
tx0_ph_fifo_reset_enable : STRING := "false";
tx0_ph_fifo_user_ctrl_enable : STRING := "false";
tx0_rd_clk_mux_select : STRING := "int clock";
tx0_reset_clock_output_during_digital_reset : STRING := "false";
tx0_use_double_data_mode : STRING := "false";
tx0_wr_clk_mux_select : STRING := "int_clk";
tx_master_direction : STRING := "none";
tx_pll0_used_as_rx_cdr : STRING := "false";
tx_pll1_used_as_rx_cdr : STRING := "false";
tx_xaui_sm_backward_compatible_enable : STRING := "false";
use_deskew_fifo : STRING := "false";
vcceh_voltage : STRING := "3.0V";
vcceh_voltage_user_specified_auto : STRING := "true";
protocol_hint : STRING := "basic";
clkdiv0_inclk0_logical_to_physical_mapping : STRING := "pll0";
clkdiv0_inclk1_logical_to_physical_mapping : STRING := "pll1";
clkdiv1_inclk0_logical_to_physical_mapping : STRING := "pll0";
clkdiv1_inclk1_logical_to_physical_mapping : STRING := "pll1";
clkdiv2_inclk0_logical_to_physical_mapping : STRING := "pll0";
clkdiv2_inclk1_logical_to_physical_mapping : STRING := "pll1";
clkdiv3_inclk0_logical_to_physical_mapping : STRING := "pll0";
clkdiv3_inclk1_logical_to_physical_mapping : STRING := "pll1";
clkdiv4_inclk0_logical_to_physical_mapping : STRING := "pll0";
clkdiv4_inclk1_logical_to_physical_mapping : STRING := "pll1";
clkdiv5_inclk0_logical_to_physical_mapping : STRING := "pll0";
clkdiv5_inclk1_logical_to_physical_mapping : STRING := "pll1";
cmu_divider0_inclk0_physical_mapping : STRING := "pll0";
cmu_divider0_inclk1_physical_mapping : STRING := "pll1";
cmu_divider0_inclk2_physical_mapping : STRING := "x4";
cmu_divider0_inclk3_physical_mapping : STRING := "xn_t";
cmu_divider0_inclk4_physical_mapping : STRING := "xn_b";
cmu_divider1_inclk0_physical_mapping : STRING := "pll0";
cmu_divider1_inclk1_physical_mapping : STRING := "pll1";
cmu_divider1_inclk2_physical_mapping : STRING := "x4";
cmu_divider1_inclk3_physical_mapping : STRING := "xn_t";
cmu_divider1_inclk4_physical_mapping : STRING := "xn_b";
cmu_divider2_inclk0_physical_mapping : STRING := "pll0";
cmu_divider2_inclk1_physical_mapping : STRING := "pll1";
cmu_divider2_inclk2_physical_mapping : STRING := "x4";
cmu_divider2_inclk3_physical_mapping : STRING := "xn_t";
cmu_divider2_inclk4_physical_mapping : STRING := "xn_b";
cmu_divider3_inclk0_physical_mapping : STRING := "pll0";
cmu_divider3_inclk1_physical_mapping : STRING := "pll1";
cmu_divider3_inclk2_physical_mapping : STRING := "x4";
cmu_divider3_inclk3_physical_mapping : STRING := "xn_t";
cmu_divider3_inclk4_physical_mapping : STRING := "xn_b";
cmu_divider4_inclk0_physical_mapping : STRING := "pll0";
cmu_divider4_inclk1_physical_mapping : STRING := "pll1";
cmu_divider4_inclk2_physical_mapping : STRING := "x4";
cmu_divider4_inclk3_physical_mapping : STRING := "xn_t";
cmu_divider4_inclk4_physical_mapping : STRING := "xn_b";
cmu_divider5_inclk0_physical_mapping : STRING := "pll0";
cmu_divider5_inclk1_physical_mapping : STRING := "pll1";
cmu_divider5_inclk2_physical_mapping : STRING := "x4";
cmu_divider5_inclk3_physical_mapping : STRING := "xn_t";
cmu_divider5_inclk4_physical_mapping : STRING := "xn_b";
pll0_inclk0_logical_to_physical_mapping : STRING := "clkrefclk0";
pll0_inclk1_logical_to_physical_mapping : STRING := "clkrefclk1";
pll0_inclk2_logical_to_physical_mapping : STRING := "iq2";
pll0_inclk3_logical_to_physical_mapping : STRING := "iq3";
pll0_inclk4_logical_to_physical_mapping : STRING := "iq4";
pll0_inclk5_logical_to_physical_mapping : STRING := "iq5";
pll0_inclk6_logical_to_physical_mapping : STRING := "iq6";
pll0_inclk7_logical_to_physical_mapping : STRING := "iq7";
pll0_inclk8_logical_to_physical_mapping : STRING := "pld_clk";
pll0_inclk9_logical_to_physical_mapping : STRING := "gpll_clk";
pll1_inclk0_logical_to_physical_mapping : STRING := "clkrefclk0";
pll1_inclk1_logical_to_physical_mapping : STRING := "clkrefclk1";
pll1_inclk2_logical_to_physical_mapping : STRING := "iq2";
pll1_inclk3_logical_to_physical_mapping : STRING := "iq3";
pll1_inclk4_logical_to_physical_mapping : STRING := "iq4";
pll1_inclk5_logical_to_physical_mapping : STRING := "iq5";
pll1_inclk6_logical_to_physical_mapping : STRING := "iq6";
pll1_inclk7_logical_to_physical_mapping : STRING := "iq7";
pll1_inclk8_logical_to_physical_mapping : STRING := "pld_clk";
pll1_inclk9_logical_to_physical_mapping : STRING := "gpll_clk";
pll2_inclk0_logical_to_physical_mapping : STRING := "clkrefclk0";
pll2_inclk1_logical_to_physical_mapping : STRING := "clkrefclk1";
pll2_inclk2_logical_to_physical_mapping : STRING := "iq2";
pll2_inclk3_logical_to_physical_mapping : STRING := "iq3";
pll2_inclk4_logical_to_physical_mapping : STRING := "iq4";
pll2_inclk5_logical_to_physical_mapping : STRING := "iq5";
pll2_inclk6_logical_to_physical_mapping : STRING := "iq6";
pll2_inclk7_logical_to_physical_mapping : STRING := "iq7";
pll2_inclk8_logical_to_physical_mapping : STRING := "pld_clk";
pll2_inclk9_logical_to_physical_mapping : STRING := "gpll_clk";
pll3_inclk0_logical_to_physical_mapping : STRING := "clkrefclk0";
pll3_inclk1_logical_to_physical_mapping : STRING := "clkrefclk1";
pll3_inclk2_logical_to_physical_mapping : STRING := "iq2";
pll3_inclk3_logical_to_physical_mapping : STRING := "iq3";
pll3_inclk4_logical_to_physical_mapping : STRING := "iq4";
pll3_inclk5_logical_to_physical_mapping : STRING := "iq5";
pll3_inclk6_logical_to_physical_mapping : STRING := "iq6";
pll3_inclk7_logical_to_physical_mapping : STRING := "iq7";
pll3_inclk8_logical_to_physical_mapping : STRING := "pld_clk";
pll3_inclk9_logical_to_physical_mapping : STRING := "gpll_clk";
pll4_inclk0_logical_to_physical_mapping : STRING := "clkrefclk0";
pll4_inclk1_logical_to_physical_mapping : STRING := "clkrefclk1";
pll4_inclk2_logical_to_physical_mapping : STRING := "iq2";
pll4_inclk3_logical_to_physical_mapping : STRING := "iq3";
pll4_inclk4_logical_to_physical_mapping : STRING := "iq4";
pll4_inclk5_logical_to_physical_mapping : STRING := "iq5";
pll4_inclk6_logical_to_physical_mapping : STRING := "iq6";
pll4_inclk7_logical_to_physical_mapping : STRING := "iq7";
pll4_inclk8_logical_to_physical_mapping : STRING := "pld_clk";
pll4_inclk9_logical_to_physical_mapping : STRING := "gpll_clk";
pll5_inclk0_logical_to_physical_mapping : STRING := "clkrefclk0";
pll5_inclk1_logical_to_physical_mapping : STRING := "clkrefclk1";
pll5_inclk2_logical_to_physical_mapping : STRING := "iq2";
pll5_inclk3_logical_to_physical_mapping : STRING := "iq3";
pll5_inclk4_logical_to_physical_mapping : STRING := "iq4";
pll5_inclk5_logical_to_physical_mapping : STRING := "iq5";
pll5_inclk6_logical_to_physical_mapping : STRING := "iq6";
pll5_inclk7_logical_to_physical_mapping : STRING := "iq7";
pll5_inclk8_logical_to_physical_mapping : STRING := "pld_clk";
pll5_inclk9_logical_to_physical_mapping : STRING := "gpll_clk";
pll0_logical_to_physical_mapping : INTEGER := 0;
pll1_logical_to_physical_mapping : INTEGER := 1;
pll2_logical_to_physical_mapping : INTEGER := 2;
pll3_logical_to_physical_mapping : INTEGER := 3;
pll4_logical_to_physical_mapping : INTEGER := 4;
pll5_logical_to_physical_mapping : INTEGER := 5;
refclk_divider0_logical_to_physical_mapping : INTEGER := 0;
refclk_divider1_logical_to_physical_mapping : INTEGER := 1;
rx0_logical_to_physical_mapping : INTEGER := 0;
rx1_logical_to_physical_mapping : INTEGER := 1;
rx2_logical_to_physical_mapping : INTEGER := 2;
rx3_logical_to_physical_mapping : INTEGER := 3;
rx4_logical_to_physical_mapping : INTEGER := 4;
rx5_logical_to_physical_mapping : INTEGER := 5;
tx0_logical_to_physical_mapping : INTEGER := 0;
tx1_logical_to_physical_mapping : INTEGER := 1;
tx2_logical_to_physical_mapping : INTEGER := 2;
tx3_logical_to_physical_mapping : INTEGER := 3;
tx4_logical_to_physical_mapping : INTEGER := 4;
tx5_logical_to_physical_mapping : INTEGER := 5;
tx0_pma_inclk0_logical_to_physical_mapping : STRING := "x1";
tx0_pma_inclk1_logical_to_physical_mapping : STRING := "x4";
tx0_pma_inclk2_logical_to_physical_mapping : STRING := "xn_top";
tx0_pma_inclk3_logical_to_physical_mapping : STRING := "xn_bottom";
tx0_pma_inclk4_logical_to_physical_mapping : STRING := "hypertransport";
tx1_pma_inclk0_logical_to_physical_mapping : STRING := "x1";
tx1_pma_inclk1_logical_to_physical_mapping : STRING := "x4";
tx1_pma_inclk2_logical_to_physical_mapping : STRING := "xn_top";
tx1_pma_inclk3_logical_to_physical_mapping : STRING := "xn_bottom";
tx1_pma_inclk4_logical_to_physical_mapping : STRING := "hypertransport";
tx2_pma_inclk0_logical_to_physical_mapping : STRING := "x1";
tx2_pma_inclk1_logical_to_physical_mapping : STRING := "x4";
tx2_pma_inclk2_logical_to_physical_mapping : STRING := "xn_top";
tx2_pma_inclk3_logical_to_physical_mapping : STRING := "xn_bottom";
tx2_pma_inclk4_logical_to_physical_mapping : STRING := "hypertransport";
tx3_pma_inclk0_logical_to_physical_mapping : STRING := "x1";
tx3_pma_inclk1_logical_to_physical_mapping : STRING := "x4";
tx3_pma_inclk2_logical_to_physical_mapping : STRING := "xn_top";
tx3_pma_inclk3_logical_to_physical_mapping : STRING := "xn_bottom";
tx3_pma_inclk4_logical_to_physical_mapping : STRING := "hypertransport";
tx4_pma_inclk0_logical_to_physical_mapping : STRING := "x1";
tx4_pma_inclk1_logical_to_physical_mapping : STRING := "x4";
tx4_pma_inclk2_logical_to_physical_mapping : STRING := "xn_top";
tx4_pma_inclk3_logical_to_physical_mapping : STRING := "xn_bottom";
tx4_pma_inclk4_logical_to_physical_mapping : STRING := "hypertransport";
tx5_pma_inclk0_logical_to_physical_mapping : STRING := "x1";
tx5_pma_inclk1_logical_to_physical_mapping : STRING := "x4";
tx5_pma_inclk2_logical_to_physical_mapping : STRING := "xn_top";
tx5_pma_inclk3_logical_to_physical_mapping : STRING := "xn_bottom";
tx5_pma_inclk4_logical_to_physical_mapping : STRING := "hypertransport";
sim_dump_dprio_internal_reg_at_time : INTEGER := 0; -- in ps
sim_dump_filename : STRING := "sim_dprio_dump.txt" -- over-write when multiple CMUs
);
PORT (
adet : IN STD_LOGIC_VECTOR(3 DOWNTO 0) := (others => '0');
cmudividerdprioin : IN STD_LOGIC_VECTOR(599 DOWNTO 0) := (others => '0');
cmuplldprioin : IN STD_LOGIC_VECTOR(1799 DOWNTO 0) := (others => '0');
dpclk : IN STD_LOGIC := '0';
dpriodisable : IN STD_LOGIC := '1';
dprioin : IN STD_LOGIC := '0';
dprioload : IN STD_LOGIC := '0';
extra10gin : IN STD_LOGIC_VECTOR(6 DOWNTO 0) := (others => '0');
fixedclk : IN STD_LOGIC_VECTOR(5 DOWNTO 0) := (others => '0');
lccmurtestbussel : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (others => '0');
nonuserfromcal : IN STD_LOGIC := '0';
pmacramtest : IN STD_LOGIC := '0'; -- new 9.0 ww47
quadreset : IN STD_LOGIC := '0';
rateswitch : IN STD_LOGIC := '0';
rateswitchdonein : IN STD_LOGIC := '0';
rdalign : IN STD_LOGIC_VECTOR(3 DOWNTO 0) := (others => '0');
rdenablesync : IN STD_LOGIC := '0';
recovclk : IN STD_LOGIC := '0';
refclkdividerdprioin : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (others => '0');
rxanalogreset : IN STD_LOGIC_VECTOR(5 DOWNTO 0) := (others => '0');
rxclk : IN STD_LOGIC := '0';
rxcoreclk : IN STD_LOGIC := '0';
rxctrl : IN STD_LOGIC_VECTOR(3 DOWNTO 0) := (others => '0');
rxdatain : IN STD_LOGIC_VECTOR(31 DOWNTO 0) := (others => '0');
rxdatavalid : IN STD_LOGIC_VECTOR(3 DOWNTO 0) := (others => '0');
rxdigitalreset : IN STD_LOGIC_VECTOR(3 DOWNTO 0) := (others => '0');
rxpcsdprioin : IN STD_LOGIC_VECTOR(1599 DOWNTO 0) := (others => '0');
rxphfifordenable : IN STD_LOGIC := '0';
rxphfiforeset : IN STD_LOGIC := '0';
rxphfifowrdisable : IN STD_LOGIC := '0';
rxpmadprioin : IN STD_LOGIC_VECTOR(1799 DOWNTO 0) := (others => '0');
rxpowerdown : IN STD_LOGIC_VECTOR(5 DOWNTO 0) := (others => '0');
rxrunningdisp : IN STD_LOGIC_VECTOR(3 DOWNTO 0) := (others => '0');
scanclk : IN STD_LOGIC := '0';
scanin : IN STD_LOGIC_VECTOR(22 DOWNTO 0) := (others => '0');
scanmode : IN STD_LOGIC := '0';
scanshift : IN STD_LOGIC := '0';
syncstatus : IN STD_LOGIC_VECTOR(3 DOWNTO 0) := (others => '0');
testin : IN STD_LOGIC_VECTOR(9999 DOWNTO 0) := (others => '0');
txclk : IN STD_LOGIC := '0';
txcoreclk : IN STD_LOGIC := '0';
txctrl : IN STD_LOGIC_VECTOR(3 DOWNTO 0) := (others => '0');
txdatain : IN STD_LOGIC_VECTOR(31 DOWNTO 0) := (others => '0');
txdigitalreset : IN STD_LOGIC_VECTOR(3 DOWNTO 0) := (others => '0');
txpcsdprioin : IN STD_LOGIC_VECTOR(599 DOWNTO 0) := (others => '0');
txphfiforddisable : IN STD_LOGIC := '0';
txphfiforeset : IN STD_LOGIC := '0';
txphfifowrenable : IN STD_LOGIC := '0';
txpllreset : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (others => '0');
txpmadprioin : IN STD_LOGIC_VECTOR(1799 DOWNTO 0) := (others => '0');
alignstatus : OUT STD_LOGIC;
autospdx4configsel : OUT STD_LOGIC;
autospdx4rateswitchout : OUT STD_LOGIC;
autospdx4spdchg : OUT STD_LOGIC;
clkdivpowerdn : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
cmudividerdprioout : OUT STD_LOGIC_VECTOR(599 DOWNTO 0);
cmuplldprioout : OUT STD_LOGIC_VECTOR(1799 DOWNTO 0);
digitaltestout : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
dpriodisableout : OUT STD_LOGIC;
dpriooe : OUT STD_LOGIC;
dprioout : OUT STD_LOGIC;
enabledeskew : OUT STD_LOGIC;
extra10gout : OUT STD_LOGIC;
fiforesetrd : OUT STD_LOGIC;
lccmutestbus : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
phfifiox4ptrsreset : OUT STD_LOGIC;
pllpowerdn : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
pllresetout : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
quadresetout : OUT STD_LOGIC;
refclkdividerdprioout : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
rxadcepowerdown : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
rxadceresetout : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
rxanalogresetout : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
rxcrupowerdown : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
rxcruresetout : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
rxctrlout : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
rxdataout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
rxdigitalresetout : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
rxibpowerdown : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
rxpcsdprioout : OUT STD_LOGIC_VECTOR(1599 DOWNTO 0);
rxphfifox4byteselout : OUT STD_LOGIC;
rxphfifox4wrclkout : OUT STD_LOGIC;
rxphfifox4rdenableout : OUT STD_LOGIC;
rxphfifox4wrenableout : OUT STD_LOGIC;
rxpmadprioout : OUT STD_LOGIC_VECTOR(1799 DOWNTO 0);
scanout : OUT STD_LOGIC_VECTOR(22 DOWNTO 0);
testout : OUT STD_LOGIC_VECTOR(6999 DOWNTO 0);
txanalogresetout : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
txctrlout : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
txdataout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
txdetectrxpowerdown : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
txdigitalresetout : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
txdividerpowerdown : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
txobpowerdown : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
txpcsdprioout : OUT STD_LOGIC_VECTOR(599 DOWNTO 0);
txphfifox4byteselout : OUT STD_LOGIC;
txphfifox4rdclkout : OUT STD_LOGIC;
txphfifox4rdenableout : OUT STD_LOGIC;
txphfifox4wrenableout : OUT STD_LOGIC;
txpmadprioout : OUT STD_LOGIC_VECTOR(1799 DOWNTO 0)
);
END COMPONENT;
--
-- stratixiv_hssi_calibration_block
--
COMPONENT stratixiv_hssi_calibration_block
GENERIC (
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
TimingChecksOn : Boolean := True;
tipd_clk : VitalDelayType01 := DefpropDelay01;
lpm_type : string := "stratixiv_hssi_calibration_block";
cont_cal_mode : string := "false";
enable_rx_cal_tw : string := "false";
enable_tx_cal_tw : string := "false";
migrated_from_prev_family : string := "false";
rtest : string := "false";
rx_cal_wt_value : integer := 0;
send_rx_cal_status : string := "true";
tx_cal_wt_value : integer := 1);
PORT (
clk : IN std_logic := '0';
enabletestbus : IN std_logic := '0';
powerdn : IN std_logic := '0';
testctrl : IN std_logic := '0';
calibrationstatus : OUT std_logic_vector(4 DOWNTO 0);
nonusertocmu : OUT std_logic);
END COMPONENT;
--
-- stratixiv_hssi_refclk_divider
--
COMPONENT stratixiv_hssi_refclk_divider
GENERIC (
divider_number : INTEGER := 0; -- 0 or 1 for logical numbering
enable_divider : STRING := "false";
lpm_type : STRING := "stratixiv_hssi_refclk_divider";
refclk_coupling_termination : STRING := "dc_coupling_external_termination";
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
tipd_dpriodisable : VitalDelayType01 := DefPropDelay01;
tipd_dprioin : VitalDelayType01 := DefPropDelay01;
tipd_inclk : VitalDelayType01 := DefPropDelay01;
tpd_inclk_clkout : VitalDelayType01 := DefPropDelay01
);
PORT (
dpriodisable : IN STD_LOGIC := '1';
dprioin : IN STD_LOGIC := '0';
inclk : IN STD_LOGIC:= '0';
clkout : OUT STD_LOGIC;
dprioout : OUT STD_LOGIC);
END COMPONENT;
end stratixiv_hssi_components;
package body STRATIXIV_HSSI_COMPONENTS is
function bin2int (s : std_logic_vector) return integer is
constant temp : std_logic_vector(s'high-s'low DOWNTO 0) := s;
variable result : integer := 0;
begin
for i in temp'range loop
if (temp(i) = '1') then
result := result + (2**i);
end if;
end loop;
return(result);
end bin2int;
function bin2int (s : std_logic) return integer is
constant temp : std_logic := s;
variable result : integer := 0;
begin
if (temp = '1') then
result := 1;
else
result := 0;
end if;
return(result);
end bin2int;
function str2bin (s : string) return std_logic_vector is
variable len : integer := s'length;
variable result : std_logic_vector(39 DOWNTO 0) := (OTHERS => '0');
variable i : integer;
begin
for i in 1 to len loop
case s(i) is
when '0' => result(len - i) := '0';
when '1' => result(len - i) := '1';
when others =>
ASSERT FALSE
REPORT "Illegal Character "& s(i) & "in string parameter! "
SEVERITY ERROR;
end case;
end loop;
return result;
end;
function str2int (s : string) return integer is
variable len : integer := s'length;
variable newdigit : integer := 0;
variable sign : integer := 1;
variable digit : integer := 0;
begin
for i in 1 to len loop
case s(i) is
when '-' =>
if i = 1 then
sign := -1;
else
ASSERT FALSE
REPORT "Illegal Character "& s(i) & "i n string parameter! " SEVERITY ERROR;
end if;
when '0' =>
digit := 0;
when '1' =>
digit := 1;
when '2' =>
digit := 2;
when '3' =>
digit := 3;
when '4' =>
digit := 4;
when '5' =>
digit := 5;
when '6' =>
digit := 6;
when '7' =>
digit := 7;
when '8' =>
digit := 8;
when '9' =>
digit := 9;
when others =>
ASSERT FALSE
REPORT "Illegal Character "& s(i) & "in string parameter! "
SEVERITY ERROR;
end case;
newdigit := newdigit * 10 + digit;
end loop;
return (sign*newdigit);
end;
function int2bin (arg : integer; size : integer) return std_logic_vector is
variable int_val : integer := arg;
variable result : std_logic_vector(size-1 downto 0);
begin
for i in 0 to result'left loop
if ((int_val mod 2) = 0) then
result(i) := '0';
else
result(i) := '1';
end if;
int_val := int_val/2;
end loop;
return result;
end int2bin;
function int2bin (arg : boolean; size : integer) return std_logic_vector is
variable result : std_logic_vector(size-1 downto 0);
begin
if(arg)then
result := (OTHERS => '1');
else
result := (OTHERS => '0');
end if;
return result;
end int2bin;
function int2bit (arg : integer) return std_logic is
variable int_val : integer := arg;
variable result : std_logic;
begin
if (int_val = 0) then
result := '0';
else
result := '1';
end if;
return result;
end int2bit;
function int2bit (arg : boolean) return std_logic is
variable int_val : boolean := arg;
variable result : std_logic;
begin
if (int_val ) then
result := '1';
else
result := '0';
end if;
return result;
end int2bit;
function tx_top_ctrl_in_width(double_data_mode : string;
ser_double_data_mode : string
) return integer is
variable real_widthb : integer;
begin
real_widthb := 1;
if (ser_double_data_mode = "true" AND double_data_mode = "true") then
real_widthb := 4;
elsif (ser_double_data_mode = "false" AND double_data_mode = "false") then
real_widthb := 1;
else
real_widthb := 2;
end if;
return real_widthb;
end tx_top_ctrl_in_width;
function rx_top_a1k1_out_width(des_double_data_mode : string) return integer is
variable real_widthb : integer;
begin
if (des_double_data_mode = "true") then
real_widthb := 2;
else
real_widthb := 1;
end if;
return real_widthb;
end rx_top_a1k1_out_width;
function rx_top_ctrl_out_width(double_data_mode : string;
des_double_data_mode : string
) return integer is
variable real_widthb : integer;
begin
real_widthb := 1;
if (des_double_data_mode = "true" AND double_data_mode = "true") then
real_widthb := 4;
elsif (des_double_data_mode = "false" AND double_data_mode = "false") then
real_widthb := 1;
else
real_widthb := 2;
end if;
return real_widthb;
end rx_top_ctrl_out_width;
function hssiSelectDelay (CONSTANT Paths : IN VitalPathArray01Type) return TIME IS
variable Temp : TIME;
variable TransitionTime : TIME := TIME'HIGH;
variable PathDelay : TIME := TIME'HIGH;
begin
for i IN Paths'RANGE loop
next when not Paths(i).PathCondition;
next when Paths(i).InputChangeTime > TransitionTime;
Temp := Paths(i).PathDelay(tr01);
if Paths(i).InputChangeTime < TransitionTime then
PathDelay := Temp;
else
if Temp < PathDelay then
PathDelay := Temp;
end if;
end if;
TransitionTime := Paths(i).InputChangeTime;
end loop;
return PathDelay;
end;
function mux_select (sel : boolean; data1 : std_logic_vector; data2 : std_logic_vector) return std_logic_vector is
variable dataout : std_logic_vector(data1'range);
begin
if(sel) then
dataout := data1;
else
dataout := data2;
end if;
return (dataout);
end mux_select;
function mux_select (sel : boolean; data1 : std_logic; data2 : std_logic) return std_logic is
variable dataout : std_logic;
begin
if(sel) then
dataout := data1;
else
dataout := data2;
end if;
return (dataout);
end mux_select;
function mux_select (sel : bit; data1 : std_logic_vector; data2 : std_logic_vector) return std_logic_vector is
variable dataout : std_logic_vector(data1'range);
begin
if(sel = '1') then
dataout := data1;
else
dataout := data2;
end if;
return (dataout);
end mux_select;
function mux_select (sel : bit; data1 : std_logic; data2 : std_logic) return std_logic is
variable dataout : std_logic;
begin
if(sel = '1') then
dataout := data1;
else
dataout := data2;
end if;
return (dataout);
end mux_select;
function rx_top_basic_width (channel_width : integer) return integer is
variable basic_width : integer;
begin
if (channel_width mod 10 = 0) then
basic_width := 10;
else
basic_width := 8;
end if;
return(basic_width);
end rx_top_basic_width;
function rx_top_num_of_basic (channel_width : integer) return integer is
variable num_of_basic : integer;
begin
if (channel_width mod 10 = 0) then
num_of_basic := channel_width/10;
else
num_of_basic := channel_width/8;
end if;
return(num_of_basic);
end rx_top_num_of_basic;
function reduction_or (
val : std_logic_vector) return std_logic is
variable result : std_logic := '0';
begin
for i in val'range loop
result := result or val(i);
end loop;
return(result);
end reduction_or;
function reduction_nor (
val : std_logic_vector) return std_logic is
variable result : std_logic := '0';
begin
for i in val'range loop
result := result or val(i);
end loop;
return(not result);
end reduction_nor;
function reduction_xor (
val : std_logic_vector) return std_logic is
variable result : std_logic := '0';
begin
for i in val'range loop
result := result xor val(i);
end loop;
return(result);
end reduction_xor;
function reduction_and (
val : std_logic_vector) return std_logic is
variable result : std_logic := '1';
begin
for i in val'range loop
result := result and val(i);
end loop;
return(result);
end reduction_and;
function reduction_nand (
val : std_logic_vector) return std_logic is
variable result : std_logic := '1';
begin
for i in val'range loop
result := result and val(i);
end loop;
return(not result);
end reduction_nand;
function alpha_tolower (given_string : string) return string is
-- VARIABLE DECLARATION
variable string_length : integer := given_string'length;
variable result_string : string(1 to 25) := " ";
begin
for i in 1 to string_length loop
case given_string(i) is
when 'A' => result_string(i) := 'a';
when 'B' => result_string(i) := 'b';
when 'C' => result_string(i) := 'c';
when 'D' => result_string(i) := 'd';
when 'E' => result_string(i) := 'e';
when 'F' => result_string(i) := 'f';
when 'G' => result_string(i) := 'g';
when 'H' => result_string(i) := 'h';
when 'I' => result_string(i) := 'i';
when 'J' => result_string(i) := 'j';
when 'K' => result_string(i) := 'k';
when 'L' => result_string(i) := 'l';
when 'M' => result_string(i) := 'm';
when 'N' => result_string(i) := 'n';
when 'O' => result_string(i) := 'o';
when 'P' => result_string(i) := 'p';
when 'Q' => result_string(i) := 'q';
when 'R' => result_string(i) := 'r';
when 'S' => result_string(i) := 's';
when 'T' => result_string(i) := 't';
when 'U' => result_string(i) := 'u';
when 'V' => result_string(i) := 'v';
when 'W' => result_string(i) := 'w';
when 'X' => result_string(i) := 'x';
when 'Y' => result_string(i) := 'y';
when 'Z' => result_string(i) := 'z';
when others => result_string(i) := given_string(i);
end case;
end loop;
return (result_string(1 to string_length));
end alpha_tolower;
function stratixiv_tx_pcs_mph_fifo_xn_mapping (ph_fifo_xn_select : integer; ph_fifo_xn_mapping0 : string; ph_fifo_xn_mapping1 : string; ph_fifo_xn_mapping2 : string) return string is
begin
CASE ph_fifo_xn_select IS
WHEN 0 => RETURN ph_fifo_xn_mapping0;
WHEN 1 => RETURN ph_fifo_xn_mapping1;
WHEN 2 => RETURN ph_fifo_xn_mapping2;
WHEN OTHERS => RETURN "none";
END CASE;
end stratixiv_tx_pcs_mph_fifo_xn_mapping;
function stratixiv_tx_pcs_mphfifo_index ( ph_fifo_xn_select : integer) return integer is
variable fifo_index : integer;
begin
if ((ph_fifo_xn_select = 0) OR (ph_fifo_xn_select = 1) or (ph_fifo_xn_select = 2)) then
fifo_index := ph_fifo_xn_select;
else
fifo_index := 0;
end if;
return(fifo_index);
end stratixiv_tx_pcs_mphfifo_index;
function stratixiv_tx_pcs_miqp_phfifo_index ( ph_fifo_xn_select : integer) return integer is
variable fifo_index : integer;
begin
if ((ph_fifo_xn_select = 0) OR (ph_fifo_xn_select = 1)) then
fifo_index := ph_fifo_xn_select;
else
fifo_index := 0;
end if;
return(fifo_index);
end stratixiv_tx_pcs_miqp_phfifo_index;
end STRATIXIV_HSSI_COMPONENTS;
| gpl-3.0 |
asicguy/gplgpu | hdl/sim_lib/arriagx_components.vhd | 1 | 50871 | -- Copyright (C) 1991-2011 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- Quartus II 11.0 Build 157 04/27/2011
LIBRARY IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;
use work.arriagx_atom_pack.all;
package arriagx_components is
--
-- arriagx_ram_block
--
COMPONENT arriagx_ram_block
GENERIC (
operation_mode : STRING := "single_port";
mixed_port_feed_through_mode : STRING := "dont_care";
ram_block_type : STRING := "auto";
logical_ram_name : STRING := "ram_name";
init_file : STRING := "init_file.hex";
init_file_layout : STRING := "none";
data_interleave_width_in_bits : INTEGER := 1;
data_interleave_offset_in_bits : INTEGER := 1;
port_a_logical_ram_depth : INTEGER := 0;
port_a_logical_ram_width : INTEGER := 0;
port_a_first_address : INTEGER := 0;
port_a_last_address : INTEGER := 0;
port_a_first_bit_number : INTEGER := 0;
port_a_data_in_clear : STRING := "none";
port_a_address_clear : STRING := "none";
port_a_write_enable_clear : STRING := "none";
port_a_data_out_clear : STRING := "none";
port_a_byte_enable_clear : STRING := "none";
port_a_data_in_clock : STRING := "clock0";
port_a_address_clock : STRING := "clock0";
port_a_write_enable_clock : STRING := "clock0";
port_a_byte_enable_clock : STRING := "clock0";
port_a_data_out_clock : STRING := "none";
port_a_data_width : INTEGER := 1;
port_a_address_width : INTEGER := 1;
port_a_byte_enable_mask_width : INTEGER := 1;
port_b_logical_ram_depth : INTEGER := 0;
port_b_logical_ram_width : INTEGER := 0;
port_b_first_address : INTEGER := 0;
port_b_last_address : INTEGER := 0;
port_b_first_bit_number : INTEGER := 0;
port_b_data_in_clear : STRING := "none";
port_b_address_clear : STRING := "none";
port_b_read_enable_write_enable_clear: STRING := "none";
port_b_byte_enable_clear : STRING := "none";
port_b_data_out_clear : STRING := "none";
port_b_data_in_clock : STRING := "clock1";
port_b_address_clock : STRING := "clock1";
port_b_read_enable_write_enable_clock: STRING := "clock1";
port_b_byte_enable_clock : STRING := "clock1";
port_b_data_out_clock : STRING := "none";
port_b_data_width : INTEGER := 1;
port_b_address_width : INTEGER := 1;
port_b_byte_enable_mask_width : INTEGER := 1;
power_up_uninitialized : STRING := "false";
port_b_disable_ce_on_output_registers : STRING := "off";
port_b_disable_ce_on_input_registers : STRING := "off";
port_b_byte_size : INTEGER := 0;
port_a_disable_ce_on_output_registers : STRING := "off";
port_a_disable_ce_on_input_registers : STRING := "off";
port_a_byte_size : INTEGER := 0;
lpm_type : string := "arriagx_ram_block";
lpm_hint : string := "true";
mem_init0 : BIT_VECTOR := X"0";
mem_init1 : BIT_VECTOR := X"0";
connectivity_checking : string := "off"
);
PORT (
portadatain : IN STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0) := (OTHERS => '0');
portaaddr : IN STD_LOGIC_VECTOR(port_a_address_width - 1 DOWNTO 0) := (OTHERS => '0');
portawe : IN STD_LOGIC := '0';
portbdatain : IN STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0) := (OTHERS => '0');
portbaddr : IN STD_LOGIC_VECTOR(port_b_address_width - 1 DOWNTO 0) := (OTHERS => '0');
portbrewe : IN STD_LOGIC := '0';
clk0 : IN STD_LOGIC := '0';
clk1 : IN STD_LOGIC := '0';
ena0 : IN STD_LOGIC := '1';
ena1 : IN STD_LOGIC := '1';
clr0 : IN STD_LOGIC := '0';
clr1 : IN STD_LOGIC := '0';
portabyteenamasks : IN STD_LOGIC_VECTOR(port_a_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '1');
portbbyteenamasks : IN STD_LOGIC_VECTOR(port_b_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '1');
devclrn : IN STD_LOGIC := '1';
devpor : IN STD_LOGIC := '1';
portaaddrstall : IN STD_LOGIC := '0';
portbaddrstall : IN STD_LOGIC := '0';
portadataout : OUT STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0);
portbdataout : OUT STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0)
);
END COMPONENT;
--
-- arriagx_jtag
--
COMPONENT arriagx_jtag
generic (
lpm_type : string := "arriagx_jtag"
);
port (
tms : in std_logic := '0';
tck : in std_logic := '0';
tdi : in std_logic := '0';
ntrst : in std_logic := '0';
tdoutap : in std_logic := '0';
tdouser : in std_logic := '0';
tdo: out std_logic;
tmsutap: out std_logic;
tckutap: out std_logic;
tdiutap: out std_logic;
shiftuser: out std_logic;
clkdruser: out std_logic;
updateuser: out std_logic;
runidleuser: out std_logic;
usr1user: out std_logic
);
END COMPONENT;
--
-- arriagx_crcblock
--
COMPONENT arriagx_crcblock
generic (
oscillator_divider : integer := 1;
lpm_type : string := "arriagx_crcblock"
);
port (
clk : in std_logic := '0';
shiftnld : in std_logic := '0';
ldsrc : in std_logic := '0';
crcerror : out std_logic;
regout : out std_logic
);
END COMPONENT;
--
-- arriagx_asmiblock
--
COMPONENT arriagx_asmiblock
generic (
lpm_type : string := "arriagx_asmiblock"
);
port (dclkin : in std_logic;
scein : in std_logic;
sdoin : in std_logic;
oe : in std_logic;
data0out: out std_logic);
END COMPONENT;
--
-- arriagx_lcell_ff
--
COMPONENT arriagx_lcell_ff
generic (
x_on_violation : string := "on";
lpm_type : string := "arriagx_lcell_ff";
tsetup_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_adatasdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_adatasdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_regout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_aclr_regout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_aload_regout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_adatasdata_regout: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_datain : VitalDelayType01 := DefPropDelay01;
tipd_adatasdata : VitalDelayType01 := DefPropDelay01;
tipd_sclr : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tipd_aload : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*"
);
port (
datain : in std_logic := '0';
clk : in std_logic := '0';
aclr : in std_logic := '0';
aload : in std_logic := '0';
sclr : in std_logic := '0';
sload : in std_logic := '0';
ena : in std_logic := '1';
adatasdata : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
regout : out std_logic
);
END COMPONENT;
--
-- arriagx_lcell_comb
--
COMPONENT arriagx_lcell_comb
generic (
lut_mask : std_logic_vector(63 downto 0) := (OTHERS => '1');
shared_arith : string := "off";
extended_lut : string := "off";
lpm_type : string := "arriagx_lcell_comb";
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*";
tpd_dataa_combout : VitalDelayType01 := DefPropDelay01;
tpd_datab_combout : VitalDelayType01 := DefPropDelay01;
tpd_datac_combout : VitalDelayType01 := DefPropDelay01;
tpd_datad_combout : VitalDelayType01 := DefPropDelay01;
tpd_datae_combout : VitalDelayType01 := DefPropDelay01;
tpd_dataf_combout : VitalDelayType01 := DefPropDelay01;
tpd_datag_combout : VitalDelayType01 := DefPropDelay01;
tpd_dataa_sumout : VitalDelayType01 := DefPropDelay01;
tpd_datab_sumout : VitalDelayType01 := DefPropDelay01;
tpd_datac_sumout : VitalDelayType01 := DefPropDelay01;
tpd_datad_sumout : VitalDelayType01 := DefPropDelay01;
tpd_dataf_sumout : VitalDelayType01 := DefPropDelay01;
tpd_cin_sumout : VitalDelayType01 := DefPropDelay01;
tpd_sharein_sumout : VitalDelayType01 := DefPropDelay01;
tpd_dataa_cout : VitalDelayType01 := DefPropDelay01;
tpd_datab_cout : VitalDelayType01 := DefPropDelay01;
tpd_datac_cout : VitalDelayType01 := DefPropDelay01;
tpd_datad_cout : VitalDelayType01 := DefPropDelay01;
tpd_dataf_cout : VitalDelayType01 := DefPropDelay01;
tpd_cin_cout : VitalDelayType01 := DefPropDelay01;
tpd_sharein_cout : VitalDelayType01 := DefPropDelay01;
tpd_dataa_shareout : VitalDelayType01 := DefPropDelay01;
tpd_datab_shareout : VitalDelayType01 := DefPropDelay01;
tpd_datac_shareout : VitalDelayType01 := DefPropDelay01;
tpd_datad_shareout : VitalDelayType01 := DefPropDelay01;
tipd_dataa : VitalDelayType01 := DefPropDelay01;
tipd_datab : VitalDelayType01 := DefPropDelay01;
tipd_datac : VitalDelayType01 := DefPropDelay01;
tipd_datad : VitalDelayType01 := DefPropDelay01;
tipd_datae : VitalDelayType01 := DefPropDelay01;
tipd_dataf : VitalDelayType01 := DefPropDelay01;
tipd_datag : VitalDelayType01 := DefPropDelay01;
tipd_cin : VitalDelayType01 := DefPropDelay01;
tipd_sharein : VitalDelayType01 := DefPropDelay01
);
port (
dataa : in std_logic := '0';
datab : in std_logic := '0';
datac : in std_logic := '0';
datad : in std_logic := '0';
datae : in std_logic := '0';
dataf : in std_logic := '0';
datag : in std_logic := '0';
cin : in std_logic := '0';
sharein : in std_logic := '0';
combout : out std_logic;
sumout : out std_logic;
cout : out std_logic;
shareout : out std_logic
);
END COMPONENT;
--
-- arriagx_clkctrl
--
COMPONENT arriagx_clkctrl
generic (
clock_type : STRING := "Auto";
lpm_type : STRING := "arriagx_clkctrl";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tipd_inclk : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tipd_clkselect : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tipd_ena : VitalDelayType01 := DefPropDelay01
);
port (
inclk : in std_logic_vector(3 downto 0) := "0000";
clkselect : in std_logic_vector(1 downto 0) := "00";
ena : in std_logic := '1';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
outclk : out std_logic
);
END COMPONENT;
--
-- arriagx_io
--
COMPONENT arriagx_io
generic (
operation_mode : string := "input";
ddio_mode : string := "none";
open_drain_output : string := "false";
bus_hold : string := "false";
output_register_mode : string := "none";
output_async_reset : string := "none";
output_power_up : string := "low";
output_sync_reset : string := "none";
tie_off_output_clock_enable : string := "false";
oe_register_mode : string := "none";
oe_async_reset : string := "none";
oe_power_up : string := "low";
oe_sync_reset : string := "none";
tie_off_oe_clock_enable : string := "false";
input_register_mode : string := "none";
input_async_reset : string := "none";
input_power_up : string := "low";
input_sync_reset : string := "none";
extend_oe_disable : string := "false";
dqs_input_frequency : string := "10000 ps";
dqs_out_mode : string := "none";
dqs_delay_buffer_mode : string := "low";
dqs_phase_shift : integer := 0;
inclk_input : string := "normal";
ddioinclk_input : string := "negated_inclk";
dqs_offsetctrl_enable : string := "false";
dqs_ctrl_latches_enable : string := "false";
dqs_edge_detect_enable : string := "false";
gated_dqs : string := "false";
sim_dqs_intrinsic_delay : integer := 0;
sim_dqs_delay_increment : integer := 0;
sim_dqs_offset_increment : integer := 0;
lpm_type : string := "arriagx_io"
);
port (
datain : in std_logic := '0';
ddiodatain : in std_logic := '0';
oe : in std_logic := '1';
outclk : in std_logic := '0';
outclkena : in std_logic := '1';
inclk : in std_logic := '0';
inclkena : in std_logic := '1';
areset : in std_logic := '0';
sreset : in std_logic := '0';
ddioinclk : in std_logic := '0';
delayctrlin : in std_logic_vector(5 downto 0) := "000000";
offsetctrlin : in std_logic_vector(5 downto 0) := "000000";
dqsupdateen : in std_logic := '0';
linkin : in std_logic := '0';
terminationcontrol : in std_logic_vector(13 downto 0) := "00000000000000";
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
devoe : in std_logic := '0';
padio : inout std_logic;
combout : out std_logic;
regout : out std_logic;
ddioregout : out std_logic;
dqsbusout : out std_logic;
linkout : out std_logic
);
END COMPONENT;
--
-- arriagx_pll
--
COMPONENT arriagx_pll
GENERIC (
operation_mode : string := "normal";
pll_type : string := "auto"; -- EGPP/FAST/AUTO
compensate_clock : string := "clk0";
feedback_source : string := "clk0";
qualify_conf_done : string := "off";
test_input_comp_delay : integer := 0;
test_feedback_comp_delay : integer := 0;
inclk0_input_frequency : integer := 10000;
inclk1_input_frequency : integer := 10000;
gate_lock_signal : string := "no";
gate_lock_counter : integer := 1;
self_reset_on_gated_loss_lock : string := "off";
valid_lock_multiplier : integer := 1;
invalid_lock_multiplier : integer := 5;
sim_gate_lock_device_behavior : string := "off";
switch_over_type : string := "auto";
switch_over_on_lossclk : string := "off";
switch_over_on_gated_lock : string := "off";
switch_over_counter : integer := 1;
enable_switch_over_counter : string := "on";
bandwidth : integer := 0;
bandwidth_type : string := "auto";
down_spread : string := "0.0";
spread_frequency : integer := 0;
clk0_output_frequency : integer := 0;
clk0_multiply_by : integer := 1;
clk0_divide_by : integer := 1;
clk0_phase_shift : string := "0";
clk0_duty_cycle : integer := 50;
clk1_output_frequency : integer := 0;
clk1_multiply_by : integer := 1;
clk1_divide_by : integer := 1;
clk1_phase_shift : string := "0";
clk1_duty_cycle : integer := 50;
clk2_output_frequency : integer := 0;
clk2_multiply_by : integer := 1;
clk2_divide_by : integer := 1;
clk2_phase_shift : string := "0";
clk2_duty_cycle : integer := 50;
clk3_output_frequency : integer := 0;
clk3_multiply_by : integer := 1;
clk3_divide_by : integer := 1;
clk3_phase_shift : string := "0";
clk3_duty_cycle : integer := 50;
clk4_output_frequency : integer := 0;
clk4_multiply_by : integer := 1;
clk4_divide_by : integer := 1;
clk4_phase_shift : string := "0";
clk4_duty_cycle : integer := 50;
clk5_output_frequency : integer := 0;
clk5_multiply_by : integer := 1;
clk5_divide_by : integer := 1;
clk5_phase_shift : string := "0";
clk5_duty_cycle : integer := 50;
pfd_min : integer := 0;
pfd_max : integer := 0;
vco_min : integer := 0;
vco_max : integer := 0;
vco_center : integer := 0;
m_initial : integer := 1;
m : integer := 0;
n : integer := 1;
m2 : integer := 1;
n2 : integer := 1;
ss : integer := 0;
c0_high : integer := 1;
c0_low : integer := 1;
c0_initial : integer := 1;
c0_mode : string := "bypass";
c0_ph : integer := 0;
c1_high : integer := 1;
c1_low : integer := 1;
c1_initial : integer := 1;
c1_mode : string := "bypass";
c1_ph : integer := 0;
c2_high : integer := 1;
c2_low : integer := 1;
c2_initial : integer := 1;
c2_mode : string := "bypass";
c2_ph : integer := 0;
c3_high : integer := 1;
c3_low : integer := 1;
c3_initial : integer := 1;
c3_mode : string := "bypass";
c3_ph : integer := 0;
c4_high : integer := 1;
c4_low : integer := 1;
c4_initial : integer := 1;
c4_mode : string := "bypass";
c4_ph : integer := 0;
c5_high : integer := 1;
c5_low : integer := 1;
c5_initial : integer := 1;
c5_mode : string := "bypass";
c5_ph : integer := 0;
m_ph : integer := 0;
clk0_counter : string := "c0";
clk1_counter : string := "c1";
clk2_counter : string := "c2";
clk3_counter : string := "c3";
clk4_counter : string := "c4";
clk5_counter : string := "c5";
c1_use_casc_in : string := "off";
c2_use_casc_in : string := "off";
c3_use_casc_in : string := "off";
c4_use_casc_in : string := "off";
c5_use_casc_in : string := "off";
m_test_source : integer := 5;
c0_test_source : integer := 5;
c1_test_source : integer := 5;
c2_test_source : integer := 5;
c3_test_source : integer := 5;
c4_test_source : integer := 5;
c5_test_source : integer := 5;
enable0_counter : string := "c0";
enable1_counter : string := "c1";
sclkout0_phase_shift : string := "0";
sclkout1_phase_shift : string := "0";
charge_pump_current : integer := 52;
loop_filter_r : string := " 1.000000";
loop_filter_c : integer := 16;
common_rx_tx : string := "off";
use_vco_bypass : string := "false";
use_dc_coupling : string := "false";
pll_compensation_delay : integer := 0;
simulation_type : string := "functional";
lpm_type : string := "arriagx_pll";
family_name : string := "StratixIIGXLITE";
clk0_use_even_counter_mode : string := "off";
clk1_use_even_counter_mode : string := "off";
clk2_use_even_counter_mode : string := "off";
clk3_use_even_counter_mode : string := "off";
clk4_use_even_counter_mode : string := "off";
clk5_use_even_counter_mode : string := "off";
clk0_use_even_counter_value : string := "off";
clk1_use_even_counter_value : string := "off";
clk2_use_even_counter_value : string := "off";
clk3_use_even_counter_value : string := "off";
clk4_use_even_counter_value : string := "off";
clk5_use_even_counter_value : string := "off";
vco_multiply_by : integer := 0;
vco_divide_by : integer := 0;
scan_chain_mif_file : string := "";
vco_post_scale : integer := 1;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
TimingChecksOn : Boolean := true;
InstancePath : STRING := "*";
tipd_inclk : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_pfdena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_fbin : VitalDelayType01 := DefPropDelay01;
tipd_scanclk : VitalDelayType01 := DefPropDelay01;
tipd_scanread : VitalDelayType01 := DefPropDelay01;
tipd_scandata : VitalDelayType01 := DefPropDelay01;
tipd_scanwrite : VitalDelayType01 := DefPropDelay01;
tipd_clkswitch : VitalDelayType01 := DefPropDelay01;
tsetup_scandata_scanclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_scandata_scanclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_scanread_scanclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_scanread_scanclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_scanwrite_scanclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_scanwrite_scanclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst
);
PORT
(
inclk : in std_logic_vector(1 downto 0);
fbin : in std_logic := '0';
ena : in std_logic := '1';
clkswitch : in std_logic := '0';
areset : in std_logic := '0';
pfdena : in std_logic := '1';
scanread : in std_logic := '0';
scanwrite : in std_logic := '0';
scandata : in std_logic := '0';
scanclk : in std_logic := '0';
testin : in std_logic_vector(3 downto 0) := "0000";
clk : out std_logic_vector(5 downto 0);
clkbad : out std_logic_vector(1 downto 0);
activeclock : out std_logic;
locked : out std_logic;
clkloss : out std_logic;
scandataout : out std_logic;
scandone : out std_logic;
testupout : out std_logic;
testdownout : out std_logic;
enable0 : out std_logic;
enable1 : out std_logic;
sclkout : out std_logic_vector(1 downto 0)
);
END COMPONENT;
--
-- arriagx_mac_mult
--
COMPONENT arriagx_mac_mult
GENERIC (
dataa_width : integer := 18;
datab_width : integer := 18;
dataa_clock : string := "none";
datab_clock : string := "none";
signa_clock : string := "none";
signb_clock : string := "none";
round_clock : string := "none";
saturate_clock : string := "none";
output_clock : string := "none";
round_clear : string := "none";
saturate_clear : string := "none";
dataa_clear : string := "none";
datab_clear : string := "none";
signa_clear : string := "none";
signb_clear : string := "none";
output_clear : string := "none";
bypass_multiplier : string := "no";
mode_clock : string := "none";
zeroacc_clock : string := "none";
mode_clear : string := "none";
zeroacc_clear : string := "none";
signa_internally_grounded : string := "false";
signb_internally_grounded : string := "false";
lpm_hint : string := "true";
lpm_type : string := "arriagx_mac_mult";
dynamic_mode : string := "no");
PORT (
dataa : IN std_logic_vector(dataa_width-1 DOWNTO 0) := (others => '1');
datab : IN std_logic_vector(datab_width-1 DOWNTO 0) := (others => '1');
scanina : IN std_logic_vector(dataa_width-1 DOWNTO 0) := (others => '0');
scaninb : IN std_logic_vector(datab_width-1 DOWNTO 0) := (others => '0');
sourcea : IN std_logic := '0';
sourceb : IN std_logic := '0';
signa : IN std_logic := '1';
signb : IN std_logic := '1';
round : IN std_logic := '0';
saturate : IN std_logic := '0';
clk : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
aclr : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
ena : IN std_logic_vector(3 DOWNTO 0) := (others => '1');
mode : IN std_logic := '0';
zeroacc : IN std_logic := '0';
dataout : OUT std_logic_vector((dataa_width+datab_width)-1 DOWNTO 0) := (others => '0');
scanouta : OUT std_logic_vector(dataa_width-1 DOWNTO 0) := (others => '0');
scanoutb : OUT std_logic_vector(datab_width-1 DOWNTO 0) := (others => '0');
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END COMPONENT;
--
-- arriagx_mac_out
--
COMPONENT arriagx_mac_out
GENERIC (
operation_mode : string := "output_only";
dataa_width : integer := 1;
datab_width : integer := 1;
datac_width : integer := 1;
datad_width : integer := 1;
dataout_width : integer := 144;
tmp_width : integer := 144;
addnsub0_clock : string := "none";
addnsub1_clock : string := "none";
zeroacc_clock : string := "none";
round0_clock : string := "none";
round1_clock : string := "none";
saturate_clock : string := "none";
multabsaturate_clock : string := "none";
multcdsaturate_clock : string := "none";
signa_clock : string := "none";
signb_clock : string := "none";
output_clock : string := "none";
addnsub0_clear : string := "none";
addnsub1_clear : string := "none";
zeroacc_clear : string := "none";
round0_clear : string := "none";
round1_clear : string := "none";
saturate_clear : string := "none";
multabsaturate_clear : string := "none";
multcdsaturate_clear : string := "none";
signa_clear : string := "none";
signb_clear : string := "none";
output_clear : string := "none";
addnsub0_pipeline_clock : string := "none";
addnsub1_pipeline_clock : string := "none";
round0_pipeline_clock : string := "none";
round1_pipeline_clock : string := "none";
saturate_pipeline_clock : string := "none";
multabsaturate_pipeline_clock : string := "none";
multcdsaturate_pipeline_clock : string := "none";
zeroacc_pipeline_clock : string := "none";
signa_pipeline_clock : string := "none";
signb_pipeline_clock : string := "none";
addnsub0_pipeline_clear : string := "none";
addnsub1_pipeline_clear : string := "none";
round0_pipeline_clear : string := "none";
round1_pipeline_clear : string := "none";
saturate_pipeline_clear : string := "none";
multabsaturate_pipeline_clear : string := "none";
multcdsaturate_pipeline_clear : string := "none";
zeroacc_pipeline_clear : string := "none";
signa_pipeline_clear : string := "none";
signb_pipeline_clear : string := "none";
mode0_clock : string := "none";
mode1_clock : string := "none";
zeroacc1_clock : string := "none";
saturate1_clock : string := "none";
output1_clock : string := "none";
output2_clock : string := "none";
output3_clock : string := "none";
output4_clock : string := "none";
output5_clock : string := "none";
output6_clock : string := "none";
output7_clock : string := "none";
mode0_clear : string := "none";
mode1_clear : string := "none";
zeroacc1_clear : string := "none";
saturate1_clear : string := "none";
output1_clear : string := "none";
output2_clear : string := "none";
output3_clear : string := "none";
output4_clear : string := "none";
output5_clear : string := "none";
output6_clear : string := "none";
output7_clear : string := "none";
mode0_pipeline_clock : string := "none";
mode1_pipeline_clock : string := "none";
zeroacc1_pipeline_clock : string := "none";
saturate1_pipeline_clock : string := "none";
mode0_pipeline_clear : string := "none";
mode1_pipeline_clear : string := "none";
zeroacc1_pipeline_clear : string := "none";
saturate1_pipeline_clear : string := "none";
dataa_forced_to_zero : string := "no";
datac_forced_to_zero : string := "no";
lpm_hint : string := "true";
lpm_type : string := "arriagx_mac_out");
PORT (
dataa : IN std_logic_vector(dataa_width-1 DOWNTO 0) := (others => '1');
datab : IN std_logic_vector(datab_width-1 DOWNTO 0) := (others => '1');
datac : IN std_logic_vector(datac_width-1 DOWNTO 0) := (others => '1');
datad : IN std_logic_vector(datad_width-1 DOWNTO 0) := (others => '1');
zeroacc : IN std_logic := '0';
addnsub0 : IN std_logic := '1';
addnsub1 : IN std_logic := '1';
round0 : IN std_logic := '0';
round1 : IN std_logic := '0';
saturate : IN std_logic := '0';
multabsaturate : IN std_logic := '0';
multcdsaturate : IN std_logic := '0';
signa : IN std_logic := '1';
signb : IN std_logic := '1';
clk : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
aclr : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
ena : IN std_logic_vector(3 DOWNTO 0) := (others => '1');
mode0 : IN std_logic := '0';
mode1 : IN std_logic := '0';
zeroacc1 : IN std_logic := '0';
saturate1 : IN std_logic := '0';
dataout : OUT std_logic_vector(dataout_width -1 DOWNTO 0) := (others => '0');
accoverflow : OUT std_logic := '0';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END COMPONENT;
--
-- arriagx_lvds_transmitter
--
COMPONENT arriagx_lvds_transmitter
GENERIC ( channel_width : integer := 10;
bypass_serializer : String := "false";
invert_clock : String := "false";
use_falling_clock_edge : String := "false";
use_serial_data_input : String := "false";
use_post_dpa_serial_data_input : String := "false";
preemphasis_setting : integer := 0;
vod_setting : integer := 0;
differential_drive : integer := 0;
lpm_type : string := "arriagx_lvds_transmitter";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tpd_clk0_dataout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clk0_dataout_negedge : VitalDelayType01 := DefPropDelay01;
tpd_serialdatain_dataout : VitalDelayType01 := DefPropDelay01;
tpd_postdpaserialdatain_dataout : VitalDelayType01 := DefPropDelay01;
tipd_clk0 : VitalDelayType01 := DefpropDelay01;
tipd_enable0 : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayArrayType01(9 downto 0) := (OTHERS => DefpropDelay01);
tipd_serialdatain : VitalDelayType01 := DefpropDelay01;
tipd_postdpaserialdatain : VitalDelayType01 := DefpropDelay01
);
PORT ( clk0 : in std_logic;
enable0 : in std_logic := '0';
datain : in std_logic_vector(channel_width - 1 downto 0) := (OTHERS => '0');
serialdatain : in std_logic := '0';
postdpaserialdatain : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
dataout : out std_logic;
serialfdbkout : out std_logic
);
END COMPONENT;
--
-- arriagx_lvds_receiver
--
COMPONENT arriagx_lvds_receiver
GENERIC ( channel_width : integer := 10;
data_align_rollover : integer := 2;
enable_dpa : string := "off";
lose_lock_on_one_change : string := "off";
reset_fifo_at_first_lock : string := "on";
align_to_rising_edge_only : string := "on";
use_serial_feedback_input : string := "off";
dpa_debug : string := "off";
x_on_bitslip : string := "on";
lpm_type : string := "arriagx_lvds_receiver";
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tipd_clk0 : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayType01 := DefpropDelay01;
tipd_enable0 : VitalDelayType01 := DefpropDelay01;
tipd_dpareset : VitalDelayType01 := DefpropDelay01;
tipd_dpahold : VitalDelayType01 := DefpropDelay01;
tipd_dpaswitch : VitalDelayType01 := DefpropDelay01;
tipd_fiforeset : VitalDelayType01 := DefpropDelay01;
tipd_bitslip : VitalDelayType01 := DefpropDelay01;
tipd_bitslipreset : VitalDelayType01 := DefpropDelay01;
tipd_serialfbk : VitalDelayType01 := DefpropDelay01;
tpd_clk0_dpalock_posedge : VitalDelayType01 := DefPropDelay01
);
PORT ( clk0 : IN std_logic;
datain : IN std_logic := '0';
enable0 : IN std_logic := '0';
dpareset : IN std_logic := '0';
dpahold : IN std_logic := '0';
dpaswitch : IN std_logic := '0';
fiforeset : IN std_logic := '0';
bitslip : IN std_logic := '0';
bitslipreset : IN std_logic := '0';
serialfbk : IN std_logic := '0';
dataout : OUT std_logic_vector(channel_width - 1 DOWNTO 0);
dpalock : OUT std_logic;
bitslipmax : OUT std_logic;
serialdataout : OUT std_logic;
postdpaserialdataout : OUT std_logic;
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END COMPONENT;
--
-- arriagx_dll
--
COMPONENT arriagx_dll
GENERIC (
input_frequency : string := "10000 ps";
delay_chain_length : integer := 16;
delay_buffer_mode : string := "low";
delayctrlout_mode : string := "normal";
static_delay_ctrl : integer := 0;
offsetctrlout_mode : string := "static";
static_offset : string := "0";
jitter_reduction : string := "false";
use_upndnin : string := "false";
use_upndninclkena : string := "false";
sim_valid_lock : integer := 1;
sim_loop_intrinsic_delay : integer := 1000;
sim_loop_delay_increment : integer := 100;
sim_valid_lockcount : integer := 90; -- 10000 = 1000 + 100*dllcounter
lpm_type : string := "arriagx_dll";
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_aload : VitalDelayType01 := DefpropDelay01;
tipd_offset : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01);
tipd_upndnin : VitalDelayType01 := DefpropDelay01;
tipd_upndninclkena : VitalDelayType01 := DefpropDelay01;
tipd_addnsub : VitalDelayType01 := DefpropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tpd_offset_delayctrlout : VitalDelayType01 := DefPropDelay01;
tpd_clk_upndnout_posedge : VitalDelayType01 := DefPropDelay01;
tsetup_offset_clk_noedge_posedge : VitalDelayArrayType(5 downto 0) := (OTHERS => DefSetupHoldCnst);
thold_offset_clk_noedge_posedge : VitalDelayArrayType(5 downto 0) := (OTHERS => DefSetupHoldCnst);
tsetup_upndnin_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_upndnin_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_upndninclkena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_upndninclkena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_addnsub_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_addnsub_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_delayctrlout_posedge : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01)
);
PORT ( clk : IN std_logic := '0';
aload : IN std_logic := '0';
offset : IN std_logic_vector(5 DOWNTO 0) := "000000";
upndnin : IN std_logic := '1';
upndninclkena : IN std_logic := '1';
addnsub : IN std_logic := '1';
delayctrlout : OUT std_logic_vector(5 DOWNTO 0);
offsetctrlout : OUT std_logic_vector(5 DOWNTO 0);
dqsupdate : OUT std_logic;
upndnout : OUT std_logic;
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END COMPONENT;
--
-- arriagx_rublock
--
COMPONENT arriagx_rublock
generic
(
operation_mode : string := "remote";
sim_init_config : string := "factory";
sim_init_watchdog_value : integer := 0;
sim_init_page_select : integer := 0;
sim_init_status : integer := 0;
lpm_type : string := "arriagx_rublock"
);
port
(
clk : in std_logic;
shiftnld : in std_logic;
captnupdt : in std_logic;
regin : in std_logic;
rsttimer : in std_logic;
rconfig : in std_logic;
regout : out std_logic;
pgmout : out std_logic_vector(2 downto 0)
);
END COMPONENT;
--
-- arriagx_termination
--
COMPONENT arriagx_termination
GENERIC (
runtime_control : string := "false";
use_core_control : string := "false";
pullup_control_to_core : string := "true";
use_high_voltage_compare : string := "true";
use_both_compares : string := "false";
pullup_adder : integer := 0;
pulldown_adder : integer := 0;
half_rate_clock : string := "false";
power_down : string := "true";
left_shift : string := "false";
test_mode : string := "false";
lpm_type : string := "arriagx_termination";
tipd_rup : VitalDelayType01 := DefpropDelay01;
tipd_rdn : VitalDelayType01 := DefpropDelay01;
tipd_terminationclock : VitalDelayType01 := DefpropDelay01;
tipd_terminationclear : VitalDelayType01 := DefpropDelay01;
tipd_terminationenable : VitalDelayType01 := DefpropDelay01;
tipd_terminationpullup : VitalDelayArrayType01(6 downto 0) := (OTHERS => DefPropDelay01);
tipd_terminationpulldown : VitalDelayArrayType01(6 downto 0) := (OTHERS => DefPropDelay01);
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tpd_terminationclock_terminationcontrol_posedge : VitalDelayArrayType01(13 downto 0) := (OTHERS => DefPropDelay01);
tpd_terminationclock_terminationcontrolprobe_posedge : VitalDelayArrayType01(6 downto 0) := (OTHERS => DefPropDelay01)
);
PORT (
rup : IN std_logic := '0';
rdn : IN std_logic := '0';
terminationclock : IN std_logic := '0';
terminationclear : IN std_logic := '0';
terminationenable : IN std_logic := '1';
terminationpullup : IN std_logic_vector(6 DOWNTO 0) := "0000000";
terminationpulldown : IN std_logic_vector(6 DOWNTO 0) := "0000000";
devclrn : IN std_logic := '1';
devpor : IN std_logic := '0';
incrup : OUT std_logic;
incrdn : OUT std_logic;
terminationcontrol : OUT std_logic_vector(13 DOWNTO 0);
terminationcontrolprobe : OUT std_logic_vector(6 DOWNTO 0)
);
END COMPONENT;
--
-- arriagx_routing_wire
--
COMPONENT arriagx_routing_wire
generic (
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
tpd_datain_dataout : VitalDelayType01 := DefPropDelay01;
tpd_datainglitch_dataout : VitalDelayType01 := DefPropDelay01;
tipd_datain : VitalDelayType01 := DefPropDelay01
);
PORT (
datain : in std_logic;
dataout : out std_logic
);
END COMPONENT;
end arriagx_components;
| gpl-3.0 |
asicguy/gplgpu | hdl/altera_ddr3_128_sim/ddr3_int_phy_alt_mem_phy_seq.vhd | 2 | 647873 | --
-- -----------------------------------------------------------------------------
-- Abstract : constants package for the non-levelling AFI PHY sequencer
-- The constant package (alt_mem_phy_constants_pkg) contains global
-- 'constants' which are fixed thoughout the sequencer and will not
-- change (for constants which may change between sequencer
-- instances generics are used)
-- -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--
package ddr3_int_phy_alt_mem_phy_constants_pkg is
-- -------------------------------
-- Register number definitions
-- -------------------------------
constant c_max_mode_reg_index : natural := 13; -- number of MR bits..
-- Top bit of vector (i.e. width -1) used for address decoding :
constant c_debug_reg_addr_top : natural := 3;
constant c_mmi_access_codeword : std_logic_vector(31 downto 0) := X"00D0_0DEB"; -- to check for legal Avalon interface accesses
-- Register addresses.
constant c_regofst_cal_status : natural := 0;
constant c_regofst_debug_access : natural := 1;
constant c_regofst_hl_css : natural := 2;
constant c_regofst_mr_register_a : natural := 5;
constant c_regofst_mr_register_b : natural := 6;
constant c_regofst_codvw_status : natural := 12;
constant c_regofst_if_param : natural := 13;
constant c_regofst_if_test : natural := 14; -- pll_phs_shft, ac_1t, extra stuff
constant c_regofst_test_status : natural := 15;
constant c_hl_css_reg_cal_dis_bit : natural := 0;
constant c_hl_css_reg_phy_initialise_dis_bit : natural := 1;
constant c_hl_css_reg_init_dram_dis_bit : natural := 2;
constant c_hl_css_reg_write_ihi_dis_bit : natural := 3;
constant c_hl_css_reg_write_btp_dis_bit : natural := 4;
constant c_hl_css_reg_write_mtp_dis_bit : natural := 5;
constant c_hl_css_reg_read_mtp_dis_bit : natural := 6;
constant c_hl_css_reg_rrp_reset_dis_bit : natural := 7;
constant c_hl_css_reg_rrp_sweep_dis_bit : natural := 8;
constant c_hl_css_reg_rrp_seek_dis_bit : natural := 9;
constant c_hl_css_reg_rdv_dis_bit : natural := 10;
constant c_hl_css_reg_poa_dis_bit : natural := 11;
constant c_hl_css_reg_was_dis_bit : natural := 12;
constant c_hl_css_reg_adv_rd_lat_dis_bit : natural := 13;
constant c_hl_css_reg_adv_wr_lat_dis_bit : natural := 14;
constant c_hl_css_reg_prep_customer_mr_setup_dis_bit : natural := 15;
constant c_hl_css_reg_tracking_dis_bit : natural := 16;
constant c_hl_ccs_num_stages : natural := 17;
-- -----------------------------------------------------
-- Constants for DRAM addresses used during calibration:
-- -----------------------------------------------------
-- the mtp training pattern is x30F5
-- 1. write 0011 0000 and 1100 0000 such that one location will contains 0011 0000
-- 2. write in 1111 0101
-- also require locations containing all ones and all zeros
-- default choice of calibration burst length (overriden to 8 for reads for DDR3 devices)
constant c_cal_burst_len : natural := 4;
constant c_cal_ofs_step_size : natural := 8;
constant c_cal_ofs_zeros : natural := 0 * c_cal_ofs_step_size;
constant c_cal_ofs_ones : natural := 1 * c_cal_ofs_step_size;
constant c_cal_ofs_x30_almt_0 : natural := 2 * c_cal_ofs_step_size;
constant c_cal_ofs_x30_almt_1 : natural := 3 * c_cal_ofs_step_size;
constant c_cal_ofs_xF5 : natural := 5 * c_cal_ofs_step_size;
constant c_cal_ofs_wd_lat : natural := 6 * c_cal_ofs_step_size;
constant c_cal_data_len : natural := c_cal_ofs_wd_lat + c_cal_ofs_step_size;
constant c_cal_ofs_mtp : natural := 6*c_cal_ofs_step_size;
constant c_cal_ofs_mtp_len : natural := 4*4;
constant c_cal_ofs_01_pairs : natural := 2 * c_cal_burst_len;
constant c_cal_ofs_10_pairs : natural := 3 * c_cal_burst_len;
constant c_cal_ofs_1100_step : natural := 4 * c_cal_burst_len;
constant c_cal_ofs_0011_step : natural := 5 * c_cal_burst_len;
-- -----------------------------------------------------
-- Reset values. - These are chosen as default values for one PHY variation
-- with DDR2 memory and CAS latency 6, however in each calibration
-- mode these values will be set for a given PHY configuration.
-- -----------------------------------------------------
constant c_default_rd_lat : natural := 20;
constant c_default_wr_lat : natural := 5;
-- -----------------------------------------------------
-- Errorcodes
-- -----------------------------------------------------
-- implemented
constant C_SUCCESS : natural := 0;
constant C_ERR_RESYNC_NO_VALID_PHASES : natural := 5; -- No valid data-valid windows found
constant C_ERR_RESYNC_MULTIPLE_EQUAL_WINDOWS : natural := 6; -- Multiple equally-sized data valid windows
constant C_ERR_RESYNC_NO_INVALID_PHASES : natural := 7; -- No invalid data-valid windows found. Training patterns are designed so that there should always be at least one invalid phase.
constant C_ERR_CRITICAL : natural := 15; -- A condition that can't happen just happened.
constant C_ERR_READ_MTP_NO_VALID_ALMT : natural := 23;
constant C_ERR_READ_MTP_BOTH_ALMT_PASS : natural := 24;
constant C_ERR_WD_LAT_DISAGREEMENT : natural := 22; -- MEM_IF_DWIDTH/MEM_IF_DQ_PER_DQS copies of write-latency are written to memory. If all of these are not the same this error is generated.
constant C_ERR_MAX_RD_LAT_EXCEEDED : natural := 25;
constant C_ERR_MAX_TRK_SHFT_EXCEEDED : natural := 26;
-- not implemented yet
constant c_err_ac_lat_some_beats_are_different : natural := 1; -- implies DQ_1T setup failure or earlier.
constant c_err_could_not_find_read_lat : natural := 2; -- dodgy RDP setup
constant c_err_could_not_find_write_lat : natural := 3; -- dodgy WDP setup
constant c_err_clock_cycle_iteration_timeout : natural := 8; -- depends on srate calling error -- GENERIC
constant c_err_clock_cycle_it_timeout_rdp : natural := 9;
constant c_err_clock_cycle_it_timeout_rdv : natural := 10;
constant c_err_clock_cycle_it_timeout_poa : natural := 11;
constant c_err_pll_ack_timeout : natural := 13;
constant c_err_WindowProc_multiple_rsc_windows : natural := 16;
constant c_err_WindowProc_window_det_no_ones : natural := 17;
constant c_err_WindowProc_window_det_no_zeros : natural := 18;
constant c_err_WindowProc_undefined : natural := 19; -- catch all
constant c_err_tracked_mmc_offset_overflow : natural := 20;
constant c_err_no_mimic_feedback : natural := 21;
constant c_err_ctrl_ack_timeout : natural := 32;
constant c_err_ctrl_done_timeout : natural := 33;
-- -----------------------------------------------------
-- PLL phase locations per device family
-- (unused but a limited set is maintained here for reference)
-- -----------------------------------------------------
constant c_pll_resync_phs_select_ciii : natural := 5;
constant c_pll_mimic_phs_select_ciii : natural := 4;
constant c_pll_resync_phs_select_siii : natural := 5;
constant c_pll_mimic_phs_select_siii : natural := 7;
-- -----------------------------------------------------
-- Maximum sizing constraints
-- -----------------------------------------------------
constant C_MAX_NUM_PLL_RSC_PHASES : natural := 32;
-- -----------------------------------------------------
-- IO control Params
-- -----------------------------------------------------
constant c_set_oct_to_rs : std_logic := '0';
constant c_set_oct_to_rt : std_logic := '1';
constant c_set_odt_rt : std_logic := '1';
constant c_set_odt_off : std_logic := '0';
--
end ddr3_int_phy_alt_mem_phy_constants_pkg;
--
-- -----------------------------------------------------------------------------
-- Abstract : record package for the non-levelling AFI sequencer
-- The record package (alt_mem_phy_record_pkg) is used to combine
-- command and status signals (into records) to be passed between
-- sequencer blocks. It also contains type and record definitions
-- for the stages of DRAM memory calibration.
-- -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--
package ddr3_int_phy_alt_mem_phy_record_pkg is
-- set some maximum constraints to bound natural numbers below
constant c_max_num_dqs_groups : natural := 24;
constant c_max_num_pins : natural := 8;
constant c_max_ranks : natural := 16;
constant c_max_pll_steps : natural := 80;
-- a prefix for all report signals to identify phy and sequencer block
--
constant record_report_prefix : string := "ddr3_int_phy_alt_mem_phy_record_pkg : ";
type t_family is (
cyclone3,
stratix2,
stratix3
);
-- -----------------------------------------------------------------------
-- the following are required for the non-levelling AFI PHY sequencer block interfaces
-- -----------------------------------------------------------------------
-- admin mode register settings (from mmi block)
type t_admin_ctrl is record
mr0 : std_logic_vector(12 downto 0);
mr1 : std_logic_vector(12 downto 0);
mr2 : std_logic_vector(12 downto 0);
mr3 : std_logic_vector(12 downto 0);
end record;
function defaults return t_admin_ctrl;
-- current admin status
type t_admin_stat is record
mr0 : std_logic_vector(12 downto 0);
mr1 : std_logic_vector(12 downto 0);
mr2 : std_logic_vector(12 downto 0);
mr3 : std_logic_vector(12 downto 0);
init_done : std_logic;
end record;
function defaults return t_admin_stat;
-- mmi to iram ctrl signals
type t_iram_ctrl is record
addr : natural range 0 to 1023;
wdata : std_logic_vector(31 downto 0);
write : std_logic;
read : std_logic;
end record;
function defaults return t_iram_ctrl;
-- broadcast iram status to mmi and dgrb
type t_iram_stat is record
rdata : std_logic_vector(31 downto 0);
done : std_logic;
err : std_logic;
err_code : std_logic_vector(3 downto 0);
init_done : std_logic;
out_of_mem : std_logic;
contested_access : std_logic;
end record;
function defaults return t_iram_stat;
-- codvw status signals from dgrb to mmi block
type t_dgrb_mmi is record
cal_codvw_phase : std_logic_vector(7 downto 0);
cal_codvw_size : std_logic_vector(7 downto 0);
codvw_trk_shift : std_logic_vector(11 downto 0);
codvw_grt_one_dvw : std_logic;
end record;
function defaults return t_dgrb_mmi;
-- signal to id which block is active
type t_ctrl_active_block is (
idle,
admin,
dgwb,
dgrb,
proc, -- unused in non-levelling AFI sequencer
setup, -- unused in non-levelling AFI sequencer
iram
);
function ret_proc return t_ctrl_active_block;
function ret_dgrb return t_ctrl_active_block;
-- control record for dgwb, dgrb, iram and admin blocks:
-- the possible commands
type t_ctrl_cmd_id is (
cmd_idle,
-- initialisation stages
cmd_phy_initialise,
cmd_init_dram,
cmd_prog_cal_mr,
cmd_write_ihi,
-- calibration stages
cmd_write_btp,
cmd_write_mtp,
cmd_read_mtp,
cmd_rrp_reset,
cmd_rrp_sweep,
cmd_rrp_seek,
cmd_rdv,
cmd_poa,
cmd_was,
-- advertise controller settings and re-configure for customer operation mode.
cmd_prep_adv_rd_lat,
cmd_prep_adv_wr_lat,
cmd_prep_customer_mr_setup,
cmd_tr_due
);
-- which block should execute each command
function curr_active_block (
ctrl_cmd_id : t_ctrl_cmd_id
) return t_ctrl_active_block;
-- specify command operands as a record
type t_command_op is record
current_cs : natural range 0 to c_max_ranks-1; -- which chip select is being calibrated
single_bit : std_logic; -- current operation should be single bit
mtp_almt : natural range 0 to 1; -- signals mtp alignment to be used for operation
end record;
function defaults return t_command_op;
-- command request record (sent to each block)
type t_ctrl_command is record
command : t_ctrl_cmd_id;
command_op : t_command_op;
command_req : std_logic;
end record;
function defaults return t_ctrl_command;
-- a generic status record for each block
type t_ctrl_stat is record
command_ack : std_logic;
command_done : std_logic;
command_result : std_logic_vector(7 downto 0 );
command_err : std_logic;
end record;
function defaults return t_ctrl_stat;
-- push interface for dgwb / dgrb blocks (only the dgrb uses this interface at present)
type t_iram_push is record
iram_done : std_logic;
iram_write : std_logic;
iram_wordnum : natural range 0 to 511; -- acts as an offset to current location (max = 80 pll steps *2 sweeps and 80 pins)
iram_bitnum : natural range 0 to 31; -- for bitwise packing modes
iram_pushdata : std_logic_vector(31 downto 0); -- only bit zero used for bitwise packing_mode
end record;
function defaults return t_iram_push;
-- control block "master" state machine
type t_master_sm_state is
(
s_reset,
s_phy_initialise, -- wait for dll lock and init done flag from iram
s_init_dram, -- dram initialisation - reset sequence
s_prog_cal_mr, -- dram initialisation - programming mode registers (once per chip select)
s_write_ihi, -- write header information in iRAM
s_cal, -- check if calibration to be executed
s_write_btp, -- write burst training pattern
s_write_mtp, -- write more training pattern
s_read_mtp, -- read training patterns to find correct alignment for 1100 burst
-- (this is a special case of s_rrp_seek with no resych phase setting)
s_rrp_reset, -- read resync phase setup - reset initial conditions
s_rrp_sweep, -- read resync phase setup - sweep phases per chip select
s_rrp_seek, -- read resync phase setup - seek correct phase
s_rdv, -- read data valid setup
s_was, -- write datapath setup (ac to write data timing)
s_adv_rd_lat, -- advertise read latency
s_adv_wr_lat, -- advertise write latency
s_poa, -- calibrate the postamble (dqs based capture only)
s_tracking_setup, -- perform tracking (1st pass to setup mimic window)
s_prep_customer_mr_setup, -- apply user mode register settings (in admin block)
s_tracking, -- perform tracking (subsequent passes in user mode)
s_operational, -- calibration successful and in user mode
s_non_operational -- calibration unsuccessful and in user mode
);
-- record (set in mmi block) to disable calibration states
type t_hl_css_reg is record
phy_initialise_dis : std_logic;
init_dram_dis : std_logic;
write_ihi_dis : std_logic;
cal_dis : std_logic;
write_btp_dis : std_logic;
write_mtp_dis : std_logic;
read_mtp_dis : std_logic;
rrp_reset_dis : std_logic;
rrp_sweep_dis : std_logic;
rrp_seek_dis : std_logic;
rdv_dis : std_logic;
poa_dis : std_logic;
was_dis : std_logic;
adv_rd_lat_dis : std_logic;
adv_wr_lat_dis : std_logic;
prep_customer_mr_setup_dis : std_logic;
tracking_dis : std_logic;
end record;
function defaults return t_hl_css_reg;
-- record (set in ctrl block) to identify when a command has been acknowledged
type t_cal_stage_ack_seen is record
cal : std_logic;
phy_initialise : std_logic;
init_dram : std_logic;
write_ihi : std_logic;
write_btp : std_logic;
write_mtp : std_logic;
read_mtp : std_logic;
rrp_reset : std_logic;
rrp_sweep : std_logic;
rrp_seek : std_logic;
rdv : std_logic;
poa : std_logic;
was : std_logic;
adv_rd_lat : std_logic;
adv_wr_lat : std_logic;
prep_customer_mr_setup : std_logic;
tracking_setup : std_logic;
end record;
function defaults return t_cal_stage_ack_seen;
-- ctrl to mmi block interface (calibration status)
type t_ctrl_mmi is record
master_state_r : t_master_sm_state;
ctrl_calibration_success : std_logic;
ctrl_calibration_fail : std_logic;
ctrl_current_stage_done : std_logic;
ctrl_current_stage : t_ctrl_cmd_id;
ctrl_current_active_block : t_ctrl_active_block;
ctrl_cal_stage_ack_seen : t_cal_stage_ack_seen;
ctrl_err_code : std_logic_vector(7 downto 0);
end record;
function defaults return t_ctrl_mmi;
-- mmi to ctrl block interface (calibration control signals)
type t_mmi_ctrl is record
hl_css : t_hl_css_reg;
calibration_start : std_logic;
tracking_period_ms : natural range 0 to 255;
tracking_orvd_to_10ms : std_logic;
end record;
function defaults return t_mmi_ctrl;
-- algorithm parameterisation (generated in mmi block)
type t_algm_paramaterisation is record
num_phases_per_tck_pll : natural range 1 to c_max_pll_steps;
nominal_dqs_delay : natural range 0 to 4;
pll_360_sweeps : natural range 0 to 15;
nominal_poa_phase_lead : natural range 0 to 7;
maximum_poa_delay : natural range 0 to 15;
odt_enabled : boolean;
extend_octrt_by : natural range 0 to 15;
delay_octrt_by : natural range 0 to 15;
tracking_period_ms : natural range 0 to 255;
end record;
-- interface between mmi and pll to control phase shifting
type t_mmi_pll_reconfig is record
pll_phs_shft_phase_sel : natural range 0 to 15;
pll_phs_shft_up_wc : std_logic;
pll_phs_shft_dn_wc : std_logic;
end record;
type t_pll_mmi is record
pll_busy : std_logic;
err : std_logic_vector(1 downto 0);
end record;
-- specify the iram configuration this is default
-- currently always dq_bitwise packing and a write mode of overwrite_ram
type t_iram_packing_mode is (
dq_bitwise,
dq_wordwise
);
type t_iram_write_mode is (
overwrite_ram,
or_into_ram,
and_into_ram
);
type t_ctrl_iram is record
packing_mode : t_iram_packing_mode;
write_mode : t_iram_write_mode;
active_block : t_ctrl_active_block;
end record;
function defaults return t_ctrl_iram;
-- -----------------------------------------------------------------------
-- the following are required for compliance to levelling AFI PHY interface but
-- are non-functional for non-levelling AFI PHY sequencer
-- -----------------------------------------------------------------------
type t_sc_ctrl_if is record
read : std_logic;
write : std_logic;
dqs_group_sel : std_logic_vector( 4 downto 0);
sc_in_group_sel : std_logic_vector( 5 downto 0);
wdata : std_logic_vector(45 downto 0);
op_type : std_logic_vector( 1 downto 0);
end record;
function defaults return t_sc_ctrl_if;
type t_sc_stat is record
rdata : std_logic_vector(45 downto 0);
busy : std_logic;
error_det : std_logic;
err_code : std_logic_vector(1 downto 0);
sc_cap : std_logic_vector(7 downto 0);
end record;
function defaults return t_sc_stat;
type t_element_to_reconfigure is (
pp_t9,
pp_t10,
pp_t1,
dqslb_rsc_phs,
dqslb_poa_phs_ofst,
dqslb_dqs_phs,
dqslb_dq_phs_ofst,
dqslb_dq_1t,
dqslb_dqs_1t,
dqslb_rsc_1t,
dqslb_div2_phs,
dqslb_oct_t9,
dqslb_oct_t10,
dqslb_poa_t7,
dqslb_poa_t11,
dqslb_dqs_dly,
dqslb_lvlng_byps
);
type t_sc_type is (
DQS_LB,
DQS_DQ_DM_PINS,
DQ_DM_PINS,
dqs_dqsn_pins,
dq_pin,
dqs_pin,
dm_pin,
dq_pins
);
type t_sc_int_ctrl is record
group_num : natural range 0 to c_max_num_dqs_groups;
group_type : t_sc_type;
pin_num : natural range 0 to c_max_num_pins;
sc_element : t_element_to_reconfigure;
prog_val : std_logic_vector(3 downto 0);
ram_set : std_logic;
sc_update : std_logic;
end record;
function defaults return t_sc_int_ctrl;
-- -----------------------------------------------------------------------
-- record and functions for instant on mode
-- -----------------------------------------------------------------------
-- ranges on the below are not important because this logic is not synthesised
type t_preset_cal is record
codvw_phase : natural range 0 to 2*c_max_pll_steps;-- rsc phase
codvw_size : natural range 0 to c_max_pll_steps; -- rsc size (unused but reported)
rlat : natural; -- advertised read latency ctl_rlat (in phy clock cycles)
rdv_lat : natural; -- read data valid latency decrements needed (in memory clock cycles)
wlat : natural; -- advertised write latency ctl_wlat (in phy clock cycles)
ac_1t : std_logic; -- address / command 1t delay setting (HR only)
poa_lat : natural; -- poa latency decrements needed (in memory clock cycles)
end record;
-- the below are hardcoded (do not change)
constant c_ddr_default_cl : natural := 3;
constant c_ddr2_default_cl : natural := 6;
constant c_ddr3_default_cl : natural := 6;
constant c_ddr2_default_cwl : natural := 5;
constant c_ddr3_default_cwl : natural := 5;
constant c_ddr2_default_al : natural := 0;
constant c_ddr3_default_al : natural := 0;
constant c_ddr_default_rl : integer := c_ddr_default_cl;
constant c_ddr2_default_rl : integer := c_ddr2_default_cl + c_ddr2_default_al;
constant c_ddr3_default_rl : integer := c_ddr3_default_cl + c_ddr3_default_al;
constant c_ddr_default_wl : integer := 1;
constant c_ddr2_default_wl : integer := c_ddr2_default_cwl + c_ddr2_default_al;
constant c_ddr3_default_wl : integer := c_ddr3_default_cwl + c_ddr3_default_al;
function defaults return t_preset_cal;
function setup_instant_on (sim_time_red : natural;
family_id : natural;
memory_type : string;
dwidth_ratio : natural;
pll_steps : natural;
mr0 : std_logic_vector(15 downto 0);
mr1 : std_logic_vector(15 downto 0);
mr2 : std_logic_vector(15 downto 0)) return t_preset_cal;
--
end ddr3_int_phy_alt_mem_phy_record_pkg;
--
package body ddr3_int_phy_alt_mem_phy_record_pkg IS
-- -----------------------------------------------------------------------
-- function implementations for the above declarations
-- these are mainly default conditions for records
-- -----------------------------------------------------------------------
function defaults return t_admin_ctrl is
variable output : t_admin_ctrl;
begin
output.mr0 := (others => '0');
output.mr1 := (others => '0');
output.mr2 := (others => '0');
output.mr3 := (others => '0');
return output;
end function;
function defaults return t_admin_stat is
variable output : t_admin_stat;
begin
output.mr0 := (others => '0');
output.mr1 := (others => '0');
output.mr2 := (others => '0');
output.mr3 := (others => '0');
return output;
end function;
function defaults return t_iram_ctrl is
variable output : t_iram_ctrl;
begin
output.addr := 0;
output.wdata := (others => '0');
output.write := '0';
output.read := '0';
return output;
end function;
function defaults return t_iram_stat is
variable output : t_iram_stat;
begin
output.rdata := (others => '0');
output.done := '0';
output.err := '0';
output.err_code := (others => '0');
output.init_done := '0';
output.out_of_mem := '0';
output.contested_access := '0';
return output;
end function;
function defaults return t_dgrb_mmi is
variable output : t_dgrb_mmi;
begin
output.cal_codvw_phase := (others => '0');
output.cal_codvw_size := (others => '0');
output.codvw_trk_shift := (others => '0');
output.codvw_grt_one_dvw := '0';
return output;
end function;
function ret_proc return t_ctrl_active_block is
variable output : t_ctrl_active_block;
begin
output := proc;
return output;
end function;
function ret_dgrb return t_ctrl_active_block is
variable output : t_ctrl_active_block;
begin
output := dgrb;
return output;
end function;
function defaults return t_ctrl_iram is
variable output : t_ctrl_iram;
begin
output.packing_mode := dq_bitwise;
output.write_mode := overwrite_ram;
output.active_block := idle;
return output;
end function;
function defaults return t_command_op is
variable output : t_command_op;
begin
output.current_cs := 0;
output.single_bit := '0';
output.mtp_almt := 0;
return output;
end function;
function defaults return t_ctrl_command is
variable output : t_ctrl_command;
begin
output.command := cmd_idle;
output.command_req := '0';
output.command_op := defaults;
return output;
end function;
-- decode which block is associated with which command
function curr_active_block (
ctrl_cmd_id : t_ctrl_cmd_id
) return t_ctrl_active_block is
begin
case ctrl_cmd_id is
when cmd_idle => return idle;
when cmd_phy_initialise => return idle;
when cmd_init_dram => return admin;
when cmd_prog_cal_mr => return admin;
when cmd_write_ihi => return iram;
when cmd_write_btp => return dgwb;
when cmd_write_mtp => return dgwb;
when cmd_read_mtp => return dgrb;
when cmd_rrp_reset => return dgrb;
when cmd_rrp_sweep => return dgrb;
when cmd_rrp_seek => return dgrb;
when cmd_rdv => return dgrb;
when cmd_poa => return dgrb;
when cmd_was => return dgwb;
when cmd_prep_adv_rd_lat => return dgrb;
when cmd_prep_adv_wr_lat => return dgrb;
when cmd_prep_customer_mr_setup => return admin;
when cmd_tr_due => return dgrb;
when others => return idle;
end case;
end function;
function defaults return t_ctrl_stat is
variable output : t_ctrl_stat;
begin
output.command_ack := '0';
output.command_done := '0';
output.command_err := '0';
output.command_result := (others => '0');
return output;
end function;
function defaults return t_iram_push is
variable output : t_iram_push;
begin
output.iram_done := '0';
output.iram_write := '0';
output.iram_wordnum := 0;
output.iram_bitnum := 0;
output.iram_pushdata := (others => '0');
return output;
end function;
function defaults return t_hl_css_reg is
variable output : t_hl_css_reg;
begin
output.phy_initialise_dis := '0';
output.init_dram_dis := '0';
output.write_ihi_dis := '0';
output.cal_dis := '0';
output.write_btp_dis := '0';
output.write_mtp_dis := '0';
output.read_mtp_dis := '0';
output.rrp_reset_dis := '0';
output.rrp_sweep_dis := '0';
output.rrp_seek_dis := '0';
output.rdv_dis := '0';
output.poa_dis := '0';
output.was_dis := '0';
output.adv_rd_lat_dis := '0';
output.adv_wr_lat_dis := '0';
output.prep_customer_mr_setup_dis := '0';
output.tracking_dis := '0';
return output;
end function;
function defaults return t_cal_stage_ack_seen is
variable output : t_cal_stage_ack_seen;
begin
output.cal := '0';
output.phy_initialise := '0';
output.init_dram := '0';
output.write_ihi := '0';
output.write_btp := '0';
output.write_mtp := '0';
output.read_mtp := '0';
output.rrp_reset := '0';
output.rrp_sweep := '0';
output.rrp_seek := '0';
output.rdv := '0';
output.poa := '0';
output.was := '0';
output.adv_rd_lat := '0';
output.adv_wr_lat := '0';
output.prep_customer_mr_setup := '0';
output.tracking_setup := '0';
return output;
end function;
function defaults return t_mmi_ctrl is
variable output : t_mmi_ctrl;
begin
output.hl_css := defaults;
output.calibration_start := '0';
output.tracking_period_ms := 0;
output.tracking_orvd_to_10ms := '0';
return output;
end function;
function defaults return t_ctrl_mmi is
variable output : t_ctrl_mmi;
begin
output.master_state_r := s_reset;
output.ctrl_calibration_success := '0';
output.ctrl_calibration_fail := '0';
output.ctrl_current_stage_done := '0';
output.ctrl_current_stage := cmd_idle;
output.ctrl_current_active_block := idle;
output.ctrl_cal_stage_ack_seen := defaults;
output.ctrl_err_code := (others => '0');
return output;
end function;
-------------------------------------------------------------------------
-- the following are required for compliance to levelling AFI PHY interface but
-- are non-functional for non-levelling AFi PHY sequencer
-------------------------------------------------------------------------
function defaults return t_sc_ctrl_if is
variable output : t_sc_ctrl_if;
begin
output.read := '0';
output.write := '0';
output.dqs_group_sel := (others => '0');
output.sc_in_group_sel := (others => '0');
output.wdata := (others => '0');
output.op_type := (others => '0');
return output;
end function;
function defaults return t_sc_stat is
variable output : t_sc_stat;
begin
output.rdata := (others => '0');
output.busy := '0';
output.error_det := '0';
output.err_code := (others => '0');
output.sc_cap := (others => '0');
return output;
end function;
function defaults return t_sc_int_ctrl is
variable output : t_sc_int_ctrl;
begin
output.group_num := 0;
output.group_type := DQ_PIN;
output.pin_num := 0;
output.sc_element := pp_t9;
output.prog_val := (others => '0');
output.ram_set := '0';
output.sc_update := '0';
return output;
end function;
-- -----------------------------------------------------------------------
-- functions for instant on mode
--
--
-- Guide on how to use:
--
-- The following factors effect the setup of the PHY:
-- - AC Phase - phase at which address/command signals launched wrt PHY clock
-- - this effects the read/write latency
-- - MR settings - CL, CWL, AL
-- - Data rate - HR or FR (DDR/DDR2 only)
-- - Family - datapaths are subtly different for each
-- - Memory type - DDR/DDR2/DDR3 (different latency behaviour - see specs)
--
-- Instant on mode is designed to work for the following subset of the
-- above factors:
-- - AC Phase - out of the box defaults, which is 240 degrees for SIII type
-- families (includes SIV, HCIII, HCIV), else 90 degrees
-- - MR Settings - DDR - CL 3 only
-- - DDR2 - CL 3,4,5,6, AL 0
-- - DDR3 - CL 5,6 CWL 5, AL 0
-- - Data rate - All
-- - Families - All
-- - Memory type - All
--
-- Hints on bespoke setup for parameters outside the above or if the
-- datapath is modified (only for VHDL sim mode):
--
-- Step 1 - Run simulation with REDUCE_SIM_TIME mode 2 (FAST)
--
-- Step 2 - From the output log find the following text:
-- # -----------------------------------------------------------------------
-- **** ALTMEMPHY CALIBRATION has completed ****
-- Status:
-- calibration has : PASSED
-- PHY read latency (ctl_rlat) is : 14
-- address/command to PHY write latency (ctl_wlat) is : 2
-- read resynch phase calibration report:
-- calibrated centre of data valid window phase : 32
-- calibrated centre of data valid window size : 24
-- chosen address and command 1T delay: no 1T delay
-- poa 'dec' adjustments = 27
-- rdv 'dec' adjustments = 25
-- # -----------------------------------------------------------------------
--
-- Step 3 - Convert the text to bespoke instant on settings at the end of the
-- setup_instant_on function using the
-- override_instant_on function, note type is t_preset_cal
--
-- The mapping is as follows:
--
-- PHY read latency (ctl_rlat) is : 14 => rlat := 14
-- address/command to PHY write latency (ctl_wlat) is : 2 => wlat := 2
-- read resynch phase calibration report:
-- calibrated centre of data valid window phase : 32 => codvw_phase := 32
-- calibrated centre of data valid window size : 24 => codvw_size := 24
-- chosen address and command 1T delay: no 1T delay => ac_1t := '0'
-- poa 'dec' adjustments = 27 => poa_lat := 27
-- rdv 'dec' adjustments = 25 => rdv_lat := 25
--
-- Step 4 - Try running in REDUCE_SIM_TIME mode 1 (SUPERFAST mode)
--
-- Step 5 - If still fails observe the behaviour of the controller, for the
-- following symptoms:
-- - If first 2 beats of read data lost (POA enable too late) - inc poa_lat by 1 (poa_lat is number of POA decrements not actual latency)
-- - If last 2 beats of read data lost (POA enable too early) - dec poa_lat by 1
-- - If ctl_rdata_valid misaligned to ctl_rdata then alter number of RDV adjustments (rdv_lat)
-- - If write data is not 4-beat aligned (when written into memory) toggle ac_1t (HR only)
-- - If read data is not 4-beat aligned (but write data is) add 360 degrees to phase (PLL_STEPS_PER_CYCLE) mod 2*PLL_STEPS_PER_CYCLE (HR only)
--
-- Step 6 - If the above fails revert to REDUCE_SIM_TIME = 2 (FAST) mode
--
-- --------------------------------------------------------------------------
-- defaults
function defaults return t_preset_cal is
variable output : t_preset_cal;
begin
output.codvw_phase := 0;
output.codvw_size := 0;
output.wlat := 0;
output.rlat := 0;
output.rdv_lat := 0;
output.ac_1t := '1'; -- default on for FR
output.poa_lat := 0;
return output;
end function;
-- Functions to extract values from MR
-- return cl (for DDR memory 2*cl because of 1/2 cycle latencies)
procedure mr0_to_cl (memory_type : string;
mr0 : std_logic_vector(15 downto 0);
cl : out natural;
half_cl : out std_logic) is
variable v_cl : natural;
begin
half_cl := '0';
if memory_type = "DDR" then -- DDR memories
-- returns cl*2 because of 1/2 latencies
v_cl := to_integer(unsigned(mr0(5 downto 4)));
-- integer values of cl
if mr0(6) = '0' then
assert v_cl > 1 report record_report_prefix & "invalid cas latency for DDR memory, should be in range 1.5-3" severity failure;
end if;
if mr0(6) = '1' then
assert (v_cl = 1 or v_cl = 2) report record_report_prefix & "invalid cas latency for DDR memory, should be in range 1.5-3" severity failure;
half_cl := '1';
end if;
elsif memory_type = "DDR2" then -- DDR2 memories
v_cl := to_integer(unsigned(mr0(6 downto 4)));
-- sanity checks
assert (v_cl > 1 and v_cl < 7) report record_report_prefix & "invalid cas latency for DDR2 memory, should be in range 2-6 but equals " & integer'image(v_cl) severity failure;
elsif memory_type = "DDR3" then -- DDR3 memories
v_cl := to_integer(unsigned(mr0(6 downto 4)))+4;
--sanity checks
assert mr0(2) = '0' report record_report_prefix & "invalid cas latency for DDR3 memory, bit a2 in mr0 is set" severity failure;
assert v_cl /= 4 report record_report_prefix & "invalid cas latency for DDR3 memory, bits a6:4 set to zero" severity failure;
else
report record_report_prefix & "Undefined memory type " & memory_type severity failure;
end if;
cl := v_cl;
end procedure;
function mr1_to_al (memory_type : string;
mr1 : std_logic_vector(15 downto 0);
cl : natural) return natural is
variable al : natural;
begin
if memory_type = "DDR" then -- DDR memories
-- unsupported so return zero
al := 0;
elsif memory_type = "DDR2" then -- DDR2 memories
al := to_integer(unsigned(mr1(5 downto 3)));
assert al < 6 report record_report_prefix & "invalid additive latency for DDR2 memory, should be in range 0-5 but equals " & integer'image(al) severity failure;
elsif memory_type = "DDR3" then -- DDR3 memories
al := to_integer(unsigned(mr1(4 downto 3)));
assert al /= 3 report record_report_prefix & "invalid additive latency for DDR2 memory, should be in range 0-5 but equals " & integer'image(al) severity failure;
if al /= 0 then -- CL-1 or CL-2
al := cl - al;
end if;
else
report record_report_prefix & "Undefined memory type " & memory_type severity failure;
end if;
return al;
end function;
-- return cwl
function mr2_to_cwl (memory_type : string;
mr2 : std_logic_vector(15 downto 0);
cl : natural) return natural is
variable cwl : natural;
begin
if memory_type = "DDR" then -- DDR memories
cwl := 1;
elsif memory_type = "DDR2" then -- DDR2 memories
cwl := cl - 1;
elsif memory_type = "DDR3" then -- DDR3 memories
cwl := to_integer(unsigned(mr2(5 downto 3))) + 5;
--sanity checks
assert cwl < 9 report record_report_prefix & "invalid cas write latency for DDR3 memory, should be in range 5-8 but equals " & integer'image(cwl) severity failure;
else
report record_report_prefix & "Undefined memory type " & memory_type severity failure;
end if;
return cwl;
end function;
-- -----------------------------------
-- Functions to determine which family group
-- Include any family alias here
-- -----------------------------------
function is_siii(family_id : natural) return boolean is
begin
if family_id = 3 or family_id = 5 then
return true;
else
return false;
end if;
end function;
function is_ciii(family_id : natural) return boolean is
begin
if family_id = 2 then
return true;
else
return false;
end if;
end function;
function is_aii(family_id : natural) return boolean is
begin
if family_id = 4 then
return true;
else
return false;
end if;
end function;
function is_sii(family_id : natural) return boolean is
begin
if family_id = 1 then
return true;
else
return false;
end if;
end function;
-- -----------------------------------
-- Functions to lookup hardcoded values
-- on per family basis
-- DDR: CL = 3
-- DDR2: CL = 6, CWL = 5, AL = 0
-- DDR3: CL = 6, CWL = 5, AL = 0
-- -----------------------------------
-- default ac phase = 240
function siii_family_settings (dwidth_ratio : integer;
memory_type : string;
pll_steps : natural
) return t_preset_cal is
variable v_output : t_preset_cal;
begin
v_output := defaults;
if memory_type = "DDR" then -- CAS = 3
if dwidth_ratio = 2 then
v_output.codvw_phase := pll_steps/4;
v_output.wlat := 1;
v_output.rlat := 15;
v_output.rdv_lat := 11;
v_output.poa_lat := 11;
else
v_output.codvw_phase := pll_steps/4;
v_output.wlat := 1;
v_output.rlat := 15;
v_output.rdv_lat := 23;
v_output.ac_1t := '0';
v_output.poa_lat := 24;
end if;
elsif memory_type = "DDR2" then -- CAS = 6
if dwidth_ratio = 2 then
v_output.codvw_phase := pll_steps/4;
v_output.wlat := 5;
v_output.rlat := 16;
v_output.rdv_lat := 10;
v_output.poa_lat := 8;
else
v_output.codvw_phase := pll_steps/4;
v_output.wlat := 3;
v_output.rlat := 16;
v_output.rdv_lat := 21;
v_output.ac_1t := '0';
v_output.poa_lat := 22;
end if;
elsif memory_type = "DDR3" then -- HR only, CAS = 6
v_output.codvw_phase := pll_steps/4;
v_output.wlat := 2;
v_output.rlat := 15;
v_output.rdv_lat := 23;
v_output.ac_1t := '0';
v_output.poa_lat := 24;
end if;
-- adapt settings for ac_phase (default 240 degrees so leave commented)
-- if dwidth_ratio = 2 then
-- v_output.wlat := v_output.wlat - 1;
-- v_output.rlat := v_output.rlat - 1;
-- v_output.rdv_lat := v_output.rdv_lat + 1;
-- v_output.poa_lat := v_output.poa_lat + 1;
-- else
-- v_output.ac_1t := not v_output.ac_1t;
-- end if;
v_output.codvw_size := pll_steps;
return v_output;
end function;
-- default ac phase = 90
function ciii_family_settings (dwidth_ratio : integer;
memory_type : string;
pll_steps : natural) return t_preset_cal is
variable v_output : t_preset_cal;
begin
v_output := defaults;
if memory_type = "DDR" then -- CAS = 3
if dwidth_ratio = 2 then
v_output.codvw_phase := 3*pll_steps/4;
v_output.wlat := 1;
v_output.rlat := 15;
v_output.rdv_lat := 11;
v_output.poa_lat := 11; --unused
else
v_output.codvw_phase := 3*pll_steps/4;
v_output.wlat := 1;
v_output.rlat := 13;
v_output.rdv_lat := 27;
v_output.ac_1t := '1';
v_output.poa_lat := 27; --unused
end if;
elsif memory_type = "DDR2" then -- CAS = 6
if dwidth_ratio = 2 then
v_output.codvw_phase := 3*pll_steps/4;
v_output.wlat := 5;
v_output.rlat := 18;
v_output.rdv_lat := 8;
v_output.poa_lat := 8; --unused
else
v_output.codvw_phase := pll_steps + 3*pll_steps/4;
v_output.wlat := 3;
v_output.rlat := 14;
v_output.rdv_lat := 25;
v_output.ac_1t := '1';
v_output.poa_lat := 25; --unused
end if;
end if;
-- adapt settings for ac_phase (hardcode for 90 degrees)
if dwidth_ratio = 2 then
v_output.wlat := v_output.wlat + 1;
v_output.rlat := v_output.rlat + 1;
v_output.rdv_lat := v_output.rdv_lat - 1;
v_output.poa_lat := v_output.poa_lat - 1;
else
v_output.ac_1t := not v_output.ac_1t;
end if;
v_output.codvw_size := pll_steps/2;
return v_output;
end function;
-- default ac phase = 90
function sii_family_settings (dwidth_ratio : integer;
memory_type : string;
pll_steps : natural) return t_preset_cal is
variable v_output : t_preset_cal;
begin
v_output := defaults;
if memory_type = "DDR" then -- CAS = 3
if dwidth_ratio = 2 then
v_output.codvw_phase := pll_steps/4;
v_output.wlat := 1;
v_output.rlat := 15;
v_output.rdv_lat := 11;
v_output.poa_lat := 13;
else
v_output.codvw_phase := pll_steps/4;
v_output.wlat := 1;
v_output.rlat := 13;
v_output.rdv_lat := 27;
v_output.ac_1t := '1';
v_output.poa_lat := 22;
end if;
elsif memory_type = "DDR2" then
if dwidth_ratio = 2 then
v_output.codvw_phase := pll_steps/4;
v_output.wlat := 5;
v_output.rlat := 18;
v_output.rdv_lat := 8;
v_output.poa_lat := 10;
else
v_output.codvw_phase := pll_steps + pll_steps/4;
v_output.wlat := 3;
v_output.rlat := 14;
v_output.rdv_lat := 25;
v_output.ac_1t := '1';
v_output.poa_lat := 20;
end if;
end if;
-- adapt settings for ac_phase (hardcode for 90 degrees)
if dwidth_ratio = 2 then
v_output.wlat := v_output.wlat + 1;
v_output.rlat := v_output.rlat + 1;
v_output.rdv_lat := v_output.rdv_lat - 1;
v_output.poa_lat := v_output.poa_lat - 1;
else
v_output.ac_1t := not v_output.ac_1t;
end if;
v_output.codvw_size := pll_steps;
return v_output;
end function;
-- default ac phase = 90
function aii_family_settings (dwidth_ratio : integer;
memory_type : string;
pll_steps : natural) return t_preset_cal is
variable v_output : t_preset_cal;
begin
v_output := defaults;
if memory_type = "DDR" then -- CAS = 3
if dwidth_ratio = 2 then
v_output.codvw_phase := pll_steps/4;
v_output.wlat := 1;
v_output.rlat := 16;
v_output.rdv_lat := 10;
v_output.poa_lat := 15;
else
v_output.codvw_phase := pll_steps/4;
v_output.wlat := 1;
v_output.rlat := 13;
v_output.rdv_lat := 27;
v_output.ac_1t := '1';
v_output.poa_lat := 24;
end if;
elsif memory_type = "DDR2" then
if dwidth_ratio = 2 then
v_output.codvw_phase := pll_steps/4;
v_output.wlat := 5;
v_output.rlat := 19;
v_output.rdv_lat := 7;
v_output.poa_lat := 12;
else
v_output.codvw_phase := pll_steps + pll_steps/4;
v_output.wlat := 3;
v_output.rlat := 14;
v_output.rdv_lat := 25;
v_output.ac_1t := '1';
v_output.poa_lat := 22;
end if;
elsif memory_type = "DDR3" then -- HR only, CAS = 6
v_output.codvw_phase := pll_steps + pll_steps/4;
v_output.wlat := 3;
v_output.rlat := 14;
v_output.rdv_lat := 25;
v_output.ac_1t := '1';
v_output.poa_lat := 22;
end if;
-- adapt settings for ac_phase (hardcode for 90 degrees)
if dwidth_ratio = 2 then
v_output.wlat := v_output.wlat + 1;
v_output.rlat := v_output.rlat + 1;
v_output.rdv_lat := v_output.rdv_lat - 1;
v_output.poa_lat := v_output.poa_lat - 1;
else
v_output.ac_1t := not v_output.ac_1t;
end if;
v_output.codvw_size := pll_steps;
return v_output;
end function;
function is_odd(num : integer) return boolean is
variable v_num : integer;
begin
v_num := num;
if v_num - (v_num/2)*2 = 0 then
return false;
else
return true;
end if;
end function;
------------------------------------------------
-- top level function to setup instant on mode
------------------------------------------------
function override_instant_on return t_preset_cal is
variable v_output : t_preset_cal;
begin
v_output := defaults;
-- add in overrides here
return v_output;
end function;
function setup_instant_on (sim_time_red : natural;
family_id : natural;
memory_type : string;
dwidth_ratio : natural;
pll_steps : natural;
mr0 : std_logic_vector(15 downto 0);
mr1 : std_logic_vector(15 downto 0);
mr2 : std_logic_vector(15 downto 0)) return t_preset_cal is
variable v_output : t_preset_cal;
variable v_cl : natural; -- cas latency
variable v_half_cl : std_logic; -- + 0.5 cycles (DDR only)
variable v_al : natural; -- additive latency (ddr2/ddr3 only)
variable v_cwl : natural; -- cas write latency (ddr3 only)
variable v_rl : integer range 0 to 15;
variable v_wl : integer;
variable v_delta_rl : integer range -10 to 10; -- from given defaults
variable v_delta_wl : integer; -- from given defaults
variable v_debug : boolean;
begin
v_debug := true;
v_output := defaults;
if sim_time_red = 1 then -- only set if STR equals 1
-- ----------------------------------------
-- extract required parameters from MRs
-- ----------------------------------------
mr0_to_cl(memory_type, mr0, v_cl, v_half_cl);
v_al := mr1_to_al(memory_type, mr1, v_cl);
v_cwl := mr2_to_cwl(memory_type, mr2, v_cl);
v_rl := v_cl + v_al;
v_wl := v_cwl + v_al;
if v_debug then
report record_report_prefix & "Extracted MR parameters" & LF &
"CAS = " & integer'image(v_cl) & LF &
"CWL = " & integer'image(v_cwl) & LF &
"AL = " & integer'image(v_al) & LF;
end if;
-- ----------------------------------------
-- apply per family, memory type and dwidth_ratio static setup
-- ----------------------------------------
if is_siii(family_id) then
v_output := siii_family_settings(dwidth_ratio, memory_type, pll_steps);
elsif is_ciii(family_id) then
v_output := ciii_family_settings(dwidth_ratio, memory_type, pll_steps);
elsif is_aii(family_id) then
v_output := aii_family_settings(dwidth_ratio, memory_type, pll_steps);
elsif is_sii(family_id) then
v_output := sii_family_settings(dwidth_ratio, memory_type, pll_steps);
end if;
-- ----------------------------------------
-- correct for different cwl, cl and al settings
-- ----------------------------------------
if memory_type = "DDR" then
v_delta_rl := v_rl - c_ddr_default_rl;
v_delta_wl := v_wl - c_ddr_default_wl;
elsif memory_type = "DDR2" then
v_delta_rl := v_rl - c_ddr2_default_rl;
v_delta_wl := v_wl - c_ddr2_default_wl;
else -- DDR3
v_delta_rl := v_rl - c_ddr3_default_rl;
v_delta_wl := v_wl - c_ddr3_default_wl;
end if;
if v_debug then
report record_report_prefix & "Extracted memory latency (and delta from default)" & LF &
"RL = " & integer'image(v_rl) & LF &
"WL = " & integer'image(v_wl) & LF &
"delta RL = " & integer'image(v_delta_rl) & LF &
"delta WL = " & integer'image(v_delta_wl) & LF;
end if;
if dwidth_ratio = 2 then
-- adjust rdp settings
v_output.rlat := v_output.rlat + v_delta_rl;
v_output.rdv_lat := v_output.rdv_lat - v_delta_rl;
v_output.poa_lat := v_output.poa_lat - v_delta_rl;
-- adjust wdp settings
v_output.wlat := v_output.wlat + v_delta_wl;
elsif dwidth_ratio = 4 then
-- adjust wdp settings
v_output.wlat := v_output.wlat + v_delta_wl/2;
if is_odd(v_delta_wl) then -- add / sub 1t write latency
-- toggle ac_1t in all cases
v_output.ac_1t := not v_output.ac_1t;
if v_delta_wl < 0 then -- sub 1 from latency
if v_output.ac_1t = '0' then -- phy_clk cc boundary
v_output.wlat := v_output.wlat - 1;
end if;
else -- add 1 to latency
if v_output.ac_1t = '1' then -- phy_clk cc boundary
v_output.wlat := v_output.wlat + 1;
end if;
end if;
-- update read latency
if v_output.ac_1t = '1' then -- added 1t to address/command so inc read_lat
v_delta_rl := v_delta_rl + 1;
else -- subtracted 1t from address/command so dec read_lat
v_delta_rl := v_delta_rl - 1;
end if;
end if;
-- adjust rdp settings
v_output.rlat := v_output.rlat + v_delta_rl/2;
v_output.rdv_lat := v_output.rdv_lat - v_delta_rl;
v_output.poa_lat := v_output.poa_lat - v_delta_rl;
if memory_type = "DDR3" then
if is_odd(v_delta_rl) xor is_odd(v_delta_wl) then
if is_aii(family_id) then
v_output.rdv_lat := v_output.rdv_lat - 1;
v_output.poa_lat := v_output.poa_lat - 1;
else
v_output.rdv_lat := v_output.rdv_lat + 1;
v_output.poa_lat := v_output.poa_lat + 1;
end if;
end if;
end if;
if is_odd(v_delta_rl) then
if v_delta_rl > 0 then -- add 1t
if v_output.codvw_phase < pll_steps then
v_output.codvw_phase := v_output.codvw_phase + pll_steps;
else
v_output.codvw_phase := v_output.codvw_phase - pll_steps;
v_output.rlat := v_output.rlat + 1;
end if;
else -- subtract 1t
if v_output.codvw_phase < pll_steps then
v_output.codvw_phase := v_output.codvw_phase + pll_steps;
v_output.rlat := v_output.rlat - 1;
else
v_output.codvw_phase := v_output.codvw_phase - pll_steps;
end if;
end if;
end if;
end if;
if v_half_cl = '1' and is_ciii(family_id) then
v_output.codvw_phase := v_output.codvw_phase - pll_steps/2;
end if;
end if;
return v_output;
end function;
--
END ddr3_int_phy_alt_mem_phy_record_pkg;
--/* Legal Notice: (C)2006 Altera Corporation. All rights reserved. Your
-- use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any
-- output files any of the foregoing (including device programming or
-- simulation files), and any associated documentation or information are
-- expressly subject to the terms and conditions of the Altera Program
-- License Subscription Agreement or other applicable license agreement,
-- including, without limitation, that your use is for the sole purpose
-- of programming logic devices manufactured by Altera and sold by Altera
-- or its authorized distributors. Please refer to the applicable
-- agreement for further details. */
--
-- -----------------------------------------------------------------------------
-- Abstract : address and command package, shared between all variations of
-- the AFI sequencer
-- The address and command package (alt_mem_phy_addr_cmd_pkg) is
-- used to combine DRAM address and command signals in one record
-- and unify the functions operating on this record.
--
--
-- -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--
package ddr3_int_phy_alt_mem_phy_addr_cmd_pkg is
-- the following are bounds on the maximum range of address and command signals
constant c_max_addr_bits : natural := 15;
constant c_max_ba_bits : natural := 3;
constant c_max_ranks : natural := 16;
constant c_max_mode_reg_bit : natural := 12;
constant c_max_cmds_per_clk : natural := 4; -- quarter rate
-- a prefix for all report signals to identify phy and sequencer block
--
constant ac_report_prefix : string := "ddr3_int_phy_alt_mem_phy_seq (addr_cmd_pkg) : ";
-- -------------------------------------------------------------
-- this record represents a single mem_clk command cycle
-- -------------------------------------------------------------
type t_addr_cmd is record
addr : natural range 0 to 2**c_max_addr_bits - 1;
ba : natural range 0 to 2**c_max_ba_bits - 1;
cas_n : boolean;
ras_n : boolean;
we_n : boolean;
cke : natural range 0 to 2**c_max_ranks - 1; -- bounded max of 8 ranks
cs_n : natural range 2**c_max_ranks - 1 downto 0; -- bounded max of 8 ranks
odt : natural range 0 to 2**c_max_ranks - 1; -- bounded max of 8 ranks
rst_n : boolean;
end record t_addr_cmd;
-- -------------------------------------------------------------
-- this vector is used to describe the fact that for slower clock domains
-- mutiple commands per clock can be issued and encapsulates all these options in a
-- type which can scale with rate
-- -------------------------------------------------------------
type t_addr_cmd_vector is array (natural range <>) of t_addr_cmd;
-- -------------------------------------------------------------
-- this record is used to define the memory interface type and allow packing and checking
-- (it should be used as a generic to a entity or from a poject level constant)
-- -------------------------------------------------------------
-- enumeration for mem_type
type t_mem_type is
(
DDR,
DDR2,
DDR3
);
-- memory interface configuration parameters
type t_addr_cmd_config_rec is record
num_addr_bits : natural;
num_ba_bits : natural;
num_cs_bits : natural;
num_ranks : natural;
cmds_per_clk : natural range 1 to c_max_cmds_per_clk; -- commands per clock cycle (equal to DWIDTH_RATIO/2)
mem_type : t_mem_type;
end record;
-- -----------------------------------
-- the following type is used to switch between signals
-- (for example, in the mask function below)
-- -----------------------------------
type t_addr_cmd_signals is
(
addr,
ba,
cas_n,
ras_n,
we_n,
cke,
cs_n,
odt,
rst_n
);
-- -----------------------------------
-- odt record
-- to hold the odt settings
-- (an odt_record) per rank (in odt_array)
-- -----------------------------------
type t_odt_record is record
write : natural;
read : natural;
end record t_odt_record;
type t_odt_array is array (natural range <>) of t_odt_record;
-- -------------------------------------------------------------
-- exposed functions and procedures
--
-- these functions cover the following memory types:
-- DDR3, DDR2, DDR
--
-- and the following operations:
-- MRS, REF, PRE, PREA, ACT,
-- WR, WRS8, WRS4, WRA, WRAS8, WRAS4,
-- RD, RDS8, RDS4, RDA, RDAS8, RDAS4,
--
-- for DDR3 on the fly burst length setting for reads/writes
-- is supported
-- -------------------------------------------------------------
function defaults ( config_rec : in t_addr_cmd_config_rec
) return t_addr_cmd_vector;
function reset ( config_rec : in t_addr_cmd_config_rec
) return t_addr_cmd_vector;
function int_pup_reset ( config_rec : in t_addr_cmd_config_rec
) return t_addr_cmd_vector;
function deselect ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector
) return t_addr_cmd_vector;
function precharge_all ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
ranks : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector;
function precharge_all ( config_rec : in t_addr_cmd_config_rec;
ranks : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector;
function precharge_bank ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
ranks : in natural range 0 to 2**c_max_ranks -1;
bank : in natural range 0 to 2**c_max_ba_bits -1
) return t_addr_cmd_vector;
function activate ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
bank : in natural range 0 to 2**c_max_ba_bits -1;
row : in natural range 0 to 2**c_max_addr_bits -1;
ranks : in natural range 0 to 2**c_max_ranks - 1
) return t_addr_cmd_vector;
function write ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
bank : in natural range 0 to 2**c_max_ba_bits -1;
col : in natural range 0 to 2**c_max_addr_bits -1;
ranks : in natural range 0 to 2**c_max_ranks - 1;
op_length : in natural range 1 to 8;
auto_prech : in boolean
) return t_addr_cmd_vector;
function read ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
bank : in natural range 0 to 2**c_max_ba_bits -1;
col : in natural range 0 to 2**c_max_addr_bits -1;
ranks : in natural range 0 to 2**c_max_ranks - 1;
op_length : in natural range 1 to 8;
auto_prech : in boolean
) return t_addr_cmd_vector;
function refresh ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
ranks : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector;
function self_refresh_entry ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
ranks : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector;
function load_mode ( config_rec : in t_addr_cmd_config_rec;
mode_register_num : in natural range 0 to 3;
mode_reg_value : in std_logic_vector(c_max_mode_reg_bit downto 0);
ranks : in natural range 0 to 2**c_max_ranks -1;
remap_addr_and_ba : in boolean
) return t_addr_cmd_vector;
function dll_reset ( config_rec : in t_addr_cmd_config_rec;
mode_reg_val : in std_logic_vector;
rank_num : in natural range 0 to 2**c_max_ranks - 1;
reorder_addr_bits : in boolean
) return t_addr_cmd_vector;
function enter_sr_pd_mode ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
ranks : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector;
function maintain_pd_or_sr ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
ranks : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector;
function exit_sr_pd_mode ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
ranks : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector;
function ZQCS ( config_rec : in t_addr_cmd_config_rec;
rank : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector;
function ZQCL ( config_rec : in t_addr_cmd_config_rec;
rank : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector;
function all_unreversed_ranks ( config_rec : in t_addr_cmd_config_rec;
record_to_mask : in t_addr_cmd_vector;
mem_ac_swapped_ranks : in std_logic_vector
) return t_addr_cmd_vector;
function all_reversed_ranks ( config_rec : in t_addr_cmd_config_rec;
record_to_mask : in t_addr_cmd_vector;
mem_ac_swapped_ranks : in std_logic_vector
) return t_addr_cmd_vector;
function program_rdimm_register ( config_rec : in t_addr_cmd_config_rec;
control_word_addr : in std_logic_vector(3 downto 0);
control_word_data : in std_logic_vector(3 downto 0)
) return t_addr_cmd_vector;
-- -------------------------------------------------------------
-- the following function sets up the odt settings
-- NOTES: currently only supports DDR/DDR2 memories
-- -------------------------------------------------------------
-- odt setting as implemented in the altera high-performance controller for ddr2 memories
function set_odt_values (ranks : natural;
ranks_per_slot : natural;
mem_type : in string
) return t_odt_array;
-- -------------------------------------------------------------
-- the following function enables assignment to the constant config_rec
-- -------------------------------------------------------------
function set_config_rec ( num_addr_bits : in natural;
num_ba_bits : in natural;
num_cs_bits : in natural;
num_ranks : in natural;
dwidth_ratio : in natural range 1 to c_max_cmds_per_clk;
mem_type : in string
) return t_addr_cmd_config_rec;
-- The non-levelled sequencer doesn't make a distinction between CS_WIDTH and NUM_RANKS. In this case,
-- just set the two to be the same.
function set_config_rec ( num_addr_bits : in natural;
num_ba_bits : in natural;
num_cs_bits : in natural;
dwidth_ratio : in natural range 1 to c_max_cmds_per_clk;
mem_type : in string
) return t_addr_cmd_config_rec;
-- -------------------------------------------------------------
-- the following function and procedure unpack address and
-- command signals from the t_addr_cmd_vector format
-- -------------------------------------------------------------
procedure unpack_addr_cmd_vector( addr_cmd_vector : in t_addr_cmd_vector;
config_rec : in t_addr_cmd_config_rec;
addr : out std_logic_vector;
ba : out std_logic_vector;
cas_n : out std_logic_vector;
ras_n : out std_logic_vector;
we_n : out std_logic_vector;
cke : out std_logic_vector;
cs_n : out std_logic_vector;
odt : out std_logic_vector;
rst_n : out std_logic_vector);
procedure unpack_addr_cmd_vector( config_rec : in t_addr_cmd_config_rec;
addr_cmd_vector : in t_addr_cmd_vector;
signal addr : out std_logic_vector;
signal ba : out std_logic_vector;
signal cas_n : out std_logic_vector;
signal ras_n : out std_logic_vector;
signal we_n : out std_logic_vector;
signal cke : out std_logic_vector;
signal cs_n : out std_logic_vector;
signal odt : out std_logic_vector;
signal rst_n : out std_logic_vector);
-- -------------------------------------------------------------
-- the following functions perform bit masking to 0 or 1 (as
-- specified by mask_value) to a chosen address/command signal (signal_name)
-- across all signal bits or to a selected bit (mask_bit)
-- -------------------------------------------------------------
-- mask all signal bits procedure
function mask ( config_rec : in t_addr_cmd_config_rec;
addr_cmd_vector : in t_addr_cmd_vector;
signal_name : in t_addr_cmd_signals;
mask_value : in std_logic) return t_addr_cmd_vector;
procedure mask( config_rec : in t_addr_cmd_config_rec;
signal addr_cmd_vector : inout t_addr_cmd_vector;
signal_name : in t_addr_cmd_signals;
mask_value : in std_logic);
-- mask signal bit (mask_bit) procedure
function mask ( config_rec : in t_addr_cmd_config_rec;
addr_cmd_vector : in t_addr_cmd_vector;
signal_name : in t_addr_cmd_signals;
mask_value : in std_logic;
mask_bit : in natural) return t_addr_cmd_vector;
--
end ddr3_int_phy_alt_mem_phy_addr_cmd_pkg;
--
package body ddr3_int_phy_alt_mem_phy_addr_cmd_pkg IS
-- -------------------------------------------------------------
-- Basic functions for a single command
-- -------------------------------------------------------------
-- -------------------------------------------------------------
-- defaults the bus no JEDEC abbreviated name
-- -------------------------------------------------------------
function defaults ( config_rec : in t_addr_cmd_config_rec
) return t_addr_cmd
is
variable v_retval : t_addr_cmd;
begin
v_retval.addr := 0;
v_retval.ba := 0;
v_retval.cas_n := false;
v_retval.ras_n := false;
v_retval.we_n := false;
v_retval.cke := (2 ** config_rec.num_ranks) -1;
v_retval.cs_n := (2 ** config_rec.num_cs_bits) -1;
v_retval.odt := 0;
v_retval.rst_n := false;
return v_retval;
end function;
-- -------------------------------------------------------------
-- resets the addr/cmd signal (Same as default with cke and rst_n 0 )
-- -------------------------------------------------------------
function reset ( config_rec : in t_addr_cmd_config_rec
) return t_addr_cmd
is
variable v_retval : t_addr_cmd;
begin
v_retval := defaults(config_rec);
v_retval.cke := 0;
if config_rec.mem_type = DDR3 then
v_retval.rst_n := true;
end if;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues deselect (command) JEDEC abbreviated name: DES
-- -------------------------------------------------------------
function deselect ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd
) return t_addr_cmd
is
variable v_retval : t_addr_cmd;
begin
v_retval := previous;
v_retval.cs_n := (2 ** config_rec.num_cs_bits) -1;
v_retval.cke := (2 ** config_rec.num_ranks) -1;
v_retval.rst_n := false;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a precharge all command JEDEC abbreviated name: PREA
-- -------------------------------------------------------------
function precharge_all( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd;
ranks : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd
is
variable v_retval : t_addr_cmd;
variable v_addr : unsigned( c_max_addr_bits -1 downto 0);
begin
v_retval := previous;
v_addr := to_unsigned(previous.addr, c_max_addr_bits);
v_addr(10) := '1'; -- set AP bit high
v_retval.addr := to_integer(v_addr);
v_retval.ras_n := true;
v_retval.cas_n := false;
v_retval.we_n := true;
v_retval.cs_n := (2 ** config_rec.num_cs_bits) - 1 - ranks;
v_retval.cke := (2 ** config_rec.num_ranks) -1;
v_retval.rst_n := false;
return v_retval;
end function;
-- -------------------------------------------------------------
-- precharge (close) a bank JEDEC abbreviated name: PRE
-- -------------------------------------------------------------
function precharge_bank( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd;
ranks : in natural range 0 to 2**c_max_ranks -1;
bank : in natural range 0 to 2**c_max_ba_bits -1
) return t_addr_cmd
is
variable v_retval : t_addr_cmd;
variable v_addr : unsigned( c_max_addr_bits -1 downto 0);
begin
v_retval := previous;
v_addr := to_unsigned(previous.addr, c_max_addr_bits);
v_addr(10) := '0'; -- set AP bit low
v_retval.addr := to_integer(v_addr);
v_retval.ba := bank;
v_retval.ras_n := true;
v_retval.cas_n := false;
v_retval.we_n := true;
v_retval.cs_n := (2 ** config_rec.num_cs_bits) - ranks;
v_retval.cke := (2 ** config_rec.num_ranks) -1;
v_retval.rst_n := false;
return v_retval;
end function;
-- -------------------------------------------------------------
-- Issues a activate (open row) JEDEC abbreviated name: ACT
-- -------------------------------------------------------------
function activate (config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd;
bank : in natural range 0 to 2**c_max_ba_bits - 1;
row : in natural range 0 to 2**c_max_addr_bits - 1;
ranks : in natural range 0 to 2**c_max_ranks - 1
) return t_addr_cmd
is
variable v_retval : t_addr_cmd;
begin
v_retval.addr := row;
v_retval.ba := bank;
v_retval.cas_n := false;
v_retval.ras_n := true;
v_retval.we_n := false;
v_retval.cke := (2 ** config_rec.num_ranks) -1;
v_retval.cs_n := (2 ** config_rec.num_cs_bits) -1 - ranks;
v_retval.odt := previous.odt;
v_retval.rst_n := false;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a write command JEDEC abbreviated name:WR, WRA
-- WRS4, WRAS4
-- WRS8, WRAS8
-- has the ability to support:
-- DDR3:
-- BL4, BL8, fixed BL
-- Auto Precharge (AP)
-- DDR2, DDR:
-- fixed BL
-- Auto Precharge (AP)
-- -------------------------------------------------------------
function write (config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd;
bank : in natural range 0 to 2**c_max_ba_bits -1;
col : in natural range 0 to 2**c_max_addr_bits -1;
ranks : in natural range 0 to 2**c_max_ranks -1;
op_length : in natural range 1 to 8;
auto_prech : in boolean
) return t_addr_cmd
is
variable v_retval : t_addr_cmd;
variable v_addr : unsigned(c_max_addr_bits-1 downto 0);
begin
-- calculate correct address signal
v_addr := to_unsigned(col, c_max_addr_bits);
-- note pin A10 is used for AP, therfore shift the value from A10 onto A11.
v_retval.addr := to_integer(v_addr(9 downto 0));
if v_addr(10) = '1' then
v_retval.addr := v_retval.addr + 2**11;
end if;
if auto_prech = true then -- set AP bit (A10)
v_retval.addr := v_retval.addr + 2**10;
end if;
if config_rec.mem_type = DDR3 then
if op_length = 8 then -- set BL_OTF sel bit (A12)
v_retval.addr := v_retval.addr + 2**12;
elsif op_length = 4 then
null;
else
report ac_report_prefix & "DDR3 DRAM only supports writes of burst length 4 or 8, the requested length was: " & integer'image(op_length) severity failure;
end if;
elsif config_rec.mem_type = DDR2 or config_rec.mem_type = DDR then
null;
else
report ac_report_prefix & "only DDR memories are supported for memory writes" severity failure;
end if;
-- set a/c signal assignments for write
v_retval.ba := bank;
v_retval.cas_n := true;
v_retval.ras_n := false;
v_retval.we_n := true;
v_retval.cke := (2 ** config_rec.num_ranks) -1;
v_retval.cs_n := (2 ** config_rec.num_cs_bits) -1 - ranks;
v_retval.odt := ranks;
v_retval.rst_n := false;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a read command JEDEC abbreviated name: RD, RDA
-- RDS4, RDAS4
-- RDS8, RDAS8
-- has the ability to support:
-- DDR3:
-- BL4, BL8, fixed BL
-- Auto Precharge (AP)
-- DDR2, DDR:
-- fixed BL, Auto Precharge (AP)
-- -------------------------------------------------------------
function read (config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd;
bank : in natural range 0 to 2**c_max_ba_bits -1;
col : in natural range 0 to 2**c_max_addr_bits -1;
ranks : in natural range 0 to 2**c_max_ranks -1;
op_length : in natural range 1 to 8;
auto_prech : in boolean
) return t_addr_cmd
is
variable v_retval : t_addr_cmd;
variable v_addr : unsigned(c_max_addr_bits-1 downto 0);
begin
-- calculate correct address signal
v_addr := to_unsigned(col, c_max_addr_bits);
-- note pin A10 is used for AP, therfore shift the value from A10 onto A11.
v_retval.addr := to_integer(v_addr(9 downto 0));
if v_addr(10) = '1' then
v_retval.addr := v_retval.addr + 2**11;
end if;
if auto_prech = true then -- set AP bit (A10)
v_retval.addr := v_retval.addr + 2**10;
end if;
if config_rec.mem_type = DDR3 then
if op_length = 8 then -- set BL_OTF sel bit (A12)
v_retval.addr := v_retval.addr + 2**12;
elsif op_length = 4 then
null;
else
report ac_report_prefix & "DDR3 DRAM only supports reads of burst length 4 or 8" severity failure;
end if;
elsif config_rec.mem_type = DDR2 or config_rec.mem_type = DDR then
null;
else
report ac_report_prefix & "only DDR memories are supported for memory reads" severity failure;
end if;
-- set a/c signals for read command
v_retval.ba := bank;
v_retval.cas_n := true;
v_retval.ras_n := false;
v_retval.we_n := false;
v_retval.cke := (2 ** config_rec.num_ranks) -1;
v_retval.cs_n := (2 ** config_rec.num_cs_bits) -1 - ranks;
v_retval.odt := 0;
v_retval.rst_n := false;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a refresh command JEDEC abbreviated name: REF
-- -------------------------------------------------------------
function refresh (config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd;
ranks : in natural range 0 to 2**c_max_ranks -1
)
return t_addr_cmd
is
variable v_retval : t_addr_cmd;
begin
v_retval := previous;
v_retval.cas_n := true;
v_retval.ras_n := true;
v_retval.we_n := false;
v_retval.cke := (2 ** config_rec.num_ranks) -1;
v_retval.cs_n := (2 ** config_rec.num_cs_bits) -1 - ranks;
v_retval.rst_n := false;
-- addr, BA and ODT are don't care therfore leave as previous value
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a mode register set command JEDEC abbreviated name: MRS
-- -------------------------------------------------------------
function load_mode ( config_rec : in t_addr_cmd_config_rec;
mode_register_num : in natural range 0 to 3;
mode_reg_value : in std_logic_vector(c_max_mode_reg_bit downto 0);
ranks : in natural range 0 to 2**c_max_ranks -1;
remap_addr_and_ba : in boolean
) return t_addr_cmd
is
variable v_retval : t_addr_cmd;
variable v_addr_remap : unsigned(c_max_mode_reg_bit downto 0);
begin
v_retval.cas_n := true;
v_retval.ras_n := true;
v_retval.we_n := true;
v_retval.cke := (2 ** config_rec.num_ranks) -1;
v_retval.cs_n := (2 ** config_rec.num_cs_bits) -1 - ranks;
v_retval.odt := 0;
v_retval.rst_n := false;
v_retval.ba := mode_register_num;
v_retval.addr := to_integer(unsigned(mode_reg_value));
if remap_addr_and_ba = true then
v_addr_remap := unsigned(mode_reg_value);
v_addr_remap(8 downto 7) := v_addr_remap(7) & v_addr_remap(8);
v_addr_remap(6 downto 5) := v_addr_remap(5) & v_addr_remap(6);
v_addr_remap(4 downto 3) := v_addr_remap(3) & v_addr_remap(4);
v_retval.addr := to_integer(v_addr_remap);
v_addr_remap := to_unsigned(mode_register_num, c_max_mode_reg_bit + 1);
v_addr_remap(1 downto 0) := v_addr_remap(0) & v_addr_remap(1);
v_retval.ba := to_integer(v_addr_remap);
end if;
return v_retval;
end function;
-- -------------------------------------------------------------
-- maintains SR or PD mode on slected ranks.
-- -------------------------------------------------------------
function maintain_pd_or_sr (config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd;
ranks : in natural range 0 to 2**c_max_ranks -1
)
return t_addr_cmd
is
variable v_retval : t_addr_cmd;
begin
v_retval := previous;
v_retval.cke := (2 ** config_rec.num_ranks) - 1 - ranks;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a ZQ cal (short) JEDEC abbreviated name: ZQCS
-- NOTE - can only be issued to a single RANK at a time.
-- -------------------------------------------------------------
function ZQCS (config_rec : in t_addr_cmd_config_rec;
rank : in natural range 0 to 2**c_max_ranks -1
)
return t_addr_cmd
is
variable v_retval : t_addr_cmd;
begin
v_retval.cas_n := false;
v_retval.ras_n := false;
v_retval.we_n := true;
v_retval.cke := (2 ** config_rec.num_ranks) -1;
v_retval.cs_n := (2 ** config_rec.num_cs_bits) -1 - rank;
v_retval.rst_n := false;
v_retval.addr := 0; -- clear bit 10
v_retval.ba := 0;
v_retval.odt := 0;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a ZQ cal (long) JEDEC abbreviated name: ZQCL
-- NOTE - can only be issued to a single RANK at a time.
-- -------------------------------------------------------------
function ZQCL (config_rec : in t_addr_cmd_config_rec;
rank : in natural range 0 to 2**c_max_ranks -1
)
return t_addr_cmd
is
variable v_retval : t_addr_cmd;
begin
v_retval.cas_n := false;
v_retval.ras_n := false;
v_retval.we_n := true;
v_retval.cke := (2 ** config_rec.num_ranks) -1;
v_retval.cs_n := (2 ** config_rec.num_cs_bits) -1 - rank;
v_retval.rst_n := false;
v_retval.addr := 1024; -- set bit 10
v_retval.ba := 0;
v_retval.odt := 0;
return v_retval;
end function;
-- -------------------------------------------------------------
-- functions acting on all clock cycles from whatever rate
-- in halfrate clock domain issues 1 command per clock
-- in quarter rate issues 1 command per clock
-- In the above cases they will be correctly aligned using the
-- ALTMEMPHY 2T and 4T SDC
-- -------------------------------------------------------------
-- -------------------------------------------------------------
-- defaults the bus no JEDEC abbreviated name
-- -------------------------------------------------------------
function defaults (config_rec : in t_addr_cmd_config_rec
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
begin
v_retval := (others => defaults(config_rec));
return v_retval;
end function;
-- -------------------------------------------------------------
-- resets the addr/cmd signal (same as default with cke 0)
-- -------------------------------------------------------------
function reset (config_rec : in t_addr_cmd_config_rec
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
begin
v_retval := (others => reset(config_rec));
return v_retval;
end function;
function int_pup_reset (config_rec : in t_addr_cmd_config_rec
) return t_addr_cmd_vector
is
variable v_addr_cmd_config_rst : t_addr_cmd_config_rec;
begin
v_addr_cmd_config_rst := config_rec;
v_addr_cmd_config_rst.num_ranks := c_max_ranks;
return reset(v_addr_cmd_config_rst);
end function;
-- -------------------------------------------------------------
-- issues a deselect command JEDEC abbreviated name: DES
-- -------------------------------------------------------------
function deselect ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector
) return t_addr_cmd_vector
is
alias a_previous : t_addr_cmd_vector(previous'range) is previous;
variable v_retval : t_addr_cmd_vector(a_previous'range);
begin
for rate in a_previous'range loop
v_retval(rate) := deselect(config_rec, a_previous(a_previous'high));
end loop;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a precharge all command JEDEC abbreviated name: PREA
-- -------------------------------------------------------------
function precharge_all ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
ranks : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector
is
alias a_previous : t_addr_cmd_vector(previous'range) is previous;
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
begin
for rate in a_previous'range loop
v_retval(rate) := precharge_all(config_rec, previous(a_previous'high), ranks);
-- use dwidth_ratio/2 as in FR = 0 , HR = 1, and in future QR = 2 tCK setup + 1 tCK hold
if rate /= config_rec.cmds_per_clk/2 then
v_retval(rate).cs_n := (2 ** config_rec.num_cs_bits) -1;
end if;
end loop;
return v_retval;
end function;
-- -------------------------------------------------------------
-- precharge (close) a bank JEDEC abbreviated name: PRE
-- -------------------------------------------------------------
function precharge_bank ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
ranks : in natural range 0 to 2**c_max_ranks -1;
bank : in natural range 0 to 2**c_max_ba_bits -1
) return t_addr_cmd_vector
is
alias a_previous : t_addr_cmd_vector(previous'range) is previous;
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
begin
for rate in a_previous'range loop
v_retval(rate) := precharge_bank(config_rec, previous(a_previous'high), ranks, bank);
-- use dwidth_ratio/2 as in FR = 0 , HR = 1, and in future QR = 2 tCK setup + 1 tCK hold
if rate /= config_rec.cmds_per_clk/2 then
v_retval(rate).cs_n := (2 ** config_rec.num_cs_bits) -1;
end if;
end loop;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a activate (open row) JEDEC abbreviated name: ACT
-- -------------------------------------------------------------
function activate ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
bank : in natural range 0 to 2**c_max_ba_bits -1;
row : in natural range 0 to 2**c_max_addr_bits -1;
ranks : in natural range 0 to 2**c_max_ranks - 1
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
begin
for rate in previous'range loop
v_retval(rate) := activate(config_rec, previous(previous'high), bank, row, ranks);
-- use dwidth_ratio/2 as in FR = 0 , HR = 1, and in future QR = 2 tCK setup + 1 tCK hold
if rate /= config_rec.cmds_per_clk/2 then
v_retval(rate).cs_n := (2 ** config_rec.num_cs_bits) -1;
end if;
end loop;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a write command JEDEC abbreviated name:WR, WRA
-- WRS4, WRAS4
-- WRS8, WRAS8
--
-- has the ability to support:
-- DDR3:
-- BL4, BL8, fixed BL
-- Auto Precharge (AP)
-- DDR2, DDR:
-- fixed BL
-- Auto Precharge (AP)
-- -------------------------------------------------------------
function write ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
bank : in natural range 0 to 2**c_max_ba_bits -1;
col : in natural range 0 to 2**c_max_addr_bits -1;
ranks : in natural range 0 to 2**c_max_ranks - 1;
op_length : in natural range 1 to 8;
auto_prech : in boolean
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
begin
for rate in previous'range loop
v_retval(rate) := write(config_rec, previous(previous'high), bank, col, ranks, op_length, auto_prech);
-- use dwidth_ratio/2 as in FR = 0 , HR = 1, and in future QR = 2 tCK setup + 1 tCK hold
if rate /= config_rec.cmds_per_clk/2 then
v_retval(rate).cs_n := (2 ** config_rec.num_cs_bits) -1;
end if;
end loop;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a read command JEDEC abbreviated name: RD, RDA
-- RDS4, RDAS4
-- RDS8, RDAS8
-- has the ability to support:
-- DDR3:
-- BL4, BL8, fixed BL
-- Auto Precharge (AP)
-- DDR2, DDR:
-- fixed BL, Auto Precharge (AP)
-- -------------------------------------------------------------
function read ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
bank : in natural range 0 to 2**c_max_ba_bits -1;
col : in natural range 0 to 2**c_max_addr_bits -1;
ranks : in natural range 0 to 2**c_max_ranks - 1;
op_length : in natural range 1 to 8;
auto_prech : in boolean
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
begin
for rate in previous'range loop
v_retval(rate) := read(config_rec, previous(previous'high), bank, col, ranks, op_length, auto_prech);
-- use dwidth_ratio/2 as in FR = 0 , HR = 1, and in future QR = 2 tCK setup + 1 tCK hold
if rate /= config_rec.cmds_per_clk/2 then
v_retval(rate).cs_n := (2 ** config_rec.num_cs_bits) -1;
end if;
end loop;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a refresh command JEDEC abbreviated name: REF
-- -------------------------------------------------------------
function refresh (config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
ranks : in natural range 0 to 2**c_max_ranks -1
)return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
begin
for rate in previous'range loop
v_retval(rate) := refresh(config_rec, previous(previous'high), ranks);
if rate /= config_rec.cmds_per_clk/2 then
v_retval(rate).cs_n := (2 ** config_rec.num_cs_bits) -1;
end if;
end loop;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a self_refresh_entry command JEDEC abbreviated name: SRE
-- -------------------------------------------------------------
function self_refresh_entry (config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
ranks : in natural range 0 to 2**c_max_ranks -1
)return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
begin
v_retval := enter_sr_pd_mode(config_rec, refresh(config_rec, previous, ranks), ranks);
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a self_refresh exit or power_down exit command
-- JEDEC abbreviated names: SRX, PDX
-- -------------------------------------------------------------
function exit_sr_pd_mode ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
ranks : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
variable v_mask_workings : std_logic_vector(config_rec.num_ranks -1 downto 0);
variable v_mask_workings_b : std_logic_vector(config_rec.num_ranks -1 downto 0);
begin
v_retval := maintain_pd_or_sr(config_rec, previous, ranks);
v_mask_workings_b := std_logic_vector(to_unsigned(ranks, config_rec.num_ranks));
for rate in 0 to config_rec.cmds_per_clk - 1 loop
v_mask_workings := std_logic_vector(to_unsigned(v_retval(rate).cke, config_rec.num_ranks));
for i in v_mask_workings_b'range loop
v_mask_workings(i) := v_mask_workings(i) or v_mask_workings_b(i);
end loop;
if rate >= config_rec.cmds_per_clk / 2 then -- maintain command but clear CS of subsequenct command slots
v_retval(rate).cke := to_integer(unsigned(v_mask_workings)); -- almost irrelevant. but optimises logic slightly for Quater rate
end if;
end loop;
return v_retval;
end function;
-- -------------------------------------------------------------
-- cause the selected ranks to enter Self-refresh or Powerdown mode
-- JEDEC abbreviated names: PDE,
-- SRE (if a refresh is concurrently issued to the same ranks)
-- -------------------------------------------------------------
function enter_sr_pd_mode ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
ranks : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
variable v_mask_workings : std_logic_vector(config_rec.num_ranks -1 downto 0);
variable v_mask_workings_b : std_logic_vector(config_rec.num_ranks -1 downto 0);
begin
v_retval := previous;
v_mask_workings_b := std_logic_vector(to_unsigned(ranks, config_rec.num_ranks));
for rate in 0 to config_rec.cmds_per_clk - 1 loop
if rate >= config_rec.cmds_per_clk / 2 then -- maintain command but clear CS of subsequenct command slots
v_mask_workings := std_logic_vector(to_unsigned(v_retval(rate).cke, config_rec.num_ranks));
for i in v_mask_workings_b'range loop
v_mask_workings(i) := v_mask_workings(i) and not v_mask_workings_b(i);
end loop;
v_retval(rate).cke := to_integer(unsigned(v_mask_workings)); -- almost irrelevant. but optimises logic slightly for Quater rate
end if;
end loop;
return v_retval;
end function;
-- -------------------------------------------------------------
-- Issues a mode register set command JEDEC abbreviated name: MRS
-- -------------------------------------------------------------
function load_mode ( config_rec : in t_addr_cmd_config_rec;
mode_register_num : in natural range 0 to 3;
mode_reg_value : in std_logic_vector(c_max_mode_reg_bit downto 0);
ranks : in natural range 0 to 2**c_max_ranks -1;
remap_addr_and_ba : in boolean
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
begin
v_retval := (others => load_mode(config_rec, mode_register_num, mode_reg_value, ranks, remap_addr_and_ba));
for rate in v_retval'range loop
if rate /= config_rec.cmds_per_clk/2 then
v_retval(rate).cs_n := (2 ** config_rec.num_cs_bits) -1;
end if;
end loop;
return v_retval;
end function;
-- -------------------------------------------------------------
-- maintains SR or PD mode on slected ranks.
-- NOTE: does not affect previous command
-- -------------------------------------------------------------
function maintain_pd_or_sr ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
ranks : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
begin
for command in v_retval'range loop
v_retval(command) := maintain_pd_or_sr(config_rec, previous(command), ranks);
end loop;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a ZQ cal (long) JEDEC abbreviated name: ZQCL
-- NOTE - can only be issued to a single RANK ata a time.
-- -------------------------------------------------------------
function ZQCL ( config_rec : in t_addr_cmd_config_rec;
rank : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1) := defaults(config_rec);
begin
for command in v_retval'range loop
v_retval(command) := ZQCL(config_rec, rank);
if command * 2 /= config_rec.cmds_per_clk then
v_retval(command).cs_n := (2 ** config_rec.num_cs_bits) -1;
end if;
end loop;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a ZQ cal (short) JEDEC abbreviated name: ZQCS
-- NOTE - can only be issued to a single RANK ata a time.
-- -------------------------------------------------------------
function ZQCS ( config_rec : in t_addr_cmd_config_rec;
rank : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1) := defaults(config_rec);
begin
for command in v_retval'range loop
v_retval(command) := ZQCS(config_rec, rank);
if command * 2 /= config_rec.cmds_per_clk then
v_retval(command).cs_n := (2 ** config_rec.num_cs_bits) -1;
end if;
end loop;
return v_retval;
end function;
-- ----------------------
-- Additional Rank manipulation functions (main use DDR3)
-- -------------
-- -----------------------------------
-- set the chip select for a group of ranks
-- -----------------------------------
function all_reversed_ranks ( config_rec : in t_addr_cmd_config_rec;
record_to_mask : in t_addr_cmd;
mem_ac_swapped_ranks : in std_logic_vector
) return t_addr_cmd
is
variable v_retval : t_addr_cmd;
variable v_mask_workings : std_logic_vector(config_rec.num_cs_bits-1 downto 0);
begin
v_retval := record_to_mask;
v_mask_workings := std_logic_vector(to_unsigned(record_to_mask.cs_n, config_rec.num_cs_bits));
for i in mem_ac_swapped_ranks'range loop
v_mask_workings(i):= v_mask_workings(i) or not mem_ac_swapped_ranks(i);
end loop;
v_retval.cs_n := to_integer(unsigned(v_mask_workings));
return v_retval;
end function;
-- -----------------------------------
-- inverse of the above
-- -----------------------------------
function all_unreversed_ranks ( config_rec : in t_addr_cmd_config_rec;
record_to_mask : in t_addr_cmd;
mem_ac_swapped_ranks : in std_logic_vector
) return t_addr_cmd
is
variable v_retval : t_addr_cmd;
variable v_mask_workings : std_logic_vector(config_rec.num_cs_bits-1 downto 0);
begin
v_retval := record_to_mask;
v_mask_workings := std_logic_vector(to_unsigned(record_to_mask.cs_n, config_rec.num_cs_bits));
for i in mem_ac_swapped_ranks'range loop
v_mask_workings(i):= v_mask_workings(i) or mem_ac_swapped_ranks(i);
end loop;
v_retval.cs_n := to_integer(unsigned(v_mask_workings));
return v_retval;
end function;
-- -----------------------------------
-- set the chip select for a group of ranks in a way which handles diffrent rates
-- -----------------------------------
function all_unreversed_ranks ( config_rec : in t_addr_cmd_config_rec;
record_to_mask : in t_addr_cmd_vector;
mem_ac_swapped_ranks : in std_logic_vector
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1) := defaults(config_rec);
begin
for command in record_to_mask'range loop
v_retval(command) := all_unreversed_ranks(config_rec, record_to_mask(command), mem_ac_swapped_ranks);
end loop;
return v_retval;
end function;
-- -----------------------------------
-- inverse of the above handling ranks
-- -----------------------------------
function all_reversed_ranks ( config_rec : in t_addr_cmd_config_rec;
record_to_mask : in t_addr_cmd_vector;
mem_ac_swapped_ranks : in std_logic_vector
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1) := defaults(config_rec);
begin
for command in record_to_mask'range loop
v_retval(command) := all_reversed_ranks(config_rec, record_to_mask(command), mem_ac_swapped_ranks);
end loop;
return v_retval;
end function;
-- --------------------------------------------------
-- Program a single control word onto RDIMM.
-- This is accomplished rather goofily by asserting all chip selects
-- and then writing out both the addr/data of the word onto the addr/ba bus
-- --------------------------------------------------
function program_rdimm_register ( config_rec : in t_addr_cmd_config_rec;
control_word_addr : in std_logic_vector(3 downto 0);
control_word_data : in std_logic_vector(3 downto 0)
) return t_addr_cmd
is
variable v_retval : t_addr_cmd;
variable ba : std_logic_vector(2 downto 0);
variable addr : std_logic_vector(4 downto 0);
begin
v_retval := defaults(config_rec);
v_retval.cs_n := 0;
ba := control_word_addr(3) & control_word_data(3) & control_word_data(2);
v_retval.ba := to_integer(unsigned(ba));
addr := control_word_data(1) & control_word_data(0) & control_word_addr(2) &
control_word_addr(1) & control_word_addr(0);
v_retval.addr := to_integer(unsigned(addr));
return v_retval;
end function;
function program_rdimm_register ( config_rec : in t_addr_cmd_config_rec;
control_word_addr : in std_logic_vector(3 downto 0);
control_word_data : in std_logic_vector(3 downto 0)
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
begin
v_retval := (others => program_rdimm_register(config_rec, control_word_addr, control_word_data));
return v_retval;
end function;
-- --------------------------------------------------
-- overloaded functions, to simplify use, or provide simplified functionality
-- --------------------------------------------------
-- ----------------------------------------------------
-- Precharge all, defaulting all bits.
-- ----------------------------------------------------
function precharge_all ( config_rec : in t_addr_cmd_config_rec;
ranks : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1) := defaults(config_rec);
begin
v_retval := precharge_all(config_rec, v_retval, ranks);
return v_retval;
end function;
-- ----------------------------------------------------
-- perform DLL reset through mode registers
-- ----------------------------------------------------
function dll_reset ( config_rec : in t_addr_cmd_config_rec;
mode_reg_val : in std_logic_vector;
rank_num : in natural range 0 to 2**c_max_ranks - 1;
reorder_addr_bits : in boolean
) return t_addr_cmd_vector is
variable int_mode_reg : std_logic_vector(mode_reg_val'range);
variable output : t_addr_cmd_vector(0 to config_rec.cmds_per_clk - 1);
begin
int_mode_reg := mode_reg_val;
int_mode_reg(8) := '1'; -- set DLL reset bit.
output := load_mode(config_rec, 0, int_mode_reg, rank_num, reorder_addr_bits);
return output;
end function;
-- -------------------------------------------------------------
-- package configuration functions
-- -------------------------------------------------------------
-- -------------------------------------------------------------
-- the following function sets up the odt settings
-- NOTES: supports DDR/DDR2/DDR3 SDRAM memories
-- -------------------------------------------------------------
function set_odt_values (ranks : natural;
ranks_per_slot : natural;
mem_type : in string
) return t_odt_array is
variable v_num_slots : natural;
variable v_cs : natural range 0 to ranks-1;
variable v_odt_values : t_odt_array(0 to ranks-1);
variable v_cs_addr : unsigned(ranks-1 downto 0);
begin
if mem_type = "DDR" then
-- ODT not supported for DDR memory so set default off
for v_cs in 0 to ranks-1 loop
v_odt_values(v_cs).write := 0;
v_odt_values(v_cs).read := 0;
end loop;
elsif mem_type = "DDR2" then
-- odt setting as implemented in the altera high-performance controller for ddr2 memories
assert (ranks rem ranks_per_slot = 0) report ac_report_prefix & "number of ranks per slot must be a multiple of number of ranks" severity failure;
v_num_slots := ranks/ranks_per_slot;
if v_num_slots = 1 then
-- special condition for 1 slot (i.e. DIMM) (2^n, n=0,1,2,... ranks only)
-- set odt on one chip for writes and no odt for reads
for v_cs in 0 to ranks-1 loop
v_odt_values(v_cs).write := 2**v_cs; -- on on the rank being written to
v_odt_values(v_cs).read := 0;
end loop;
else
-- if > 1 slot, set 1 odt enable on neighbouring slot for read and write
-- as an example consider the below for 4 slots with 2 ranks per slot
-- access to CS[0] or CS[1], enable ODT[2] or ODT[3]
-- access to CS[2] or CS[3], enable ODT[0] or ODT[1]
-- access to CS[4] or CS[5], enable ODT[6] or ODT[7]
-- access to CS[6] or CS[7], enable ODT[4] or ODT[5]
-- the logic below implements the above for varying ranks and ranks_per slot
-- under the condition that ranks/ranks_per_slot is integer
for v_cs in 0 to ranks-1 loop
v_cs_addr := to_unsigned(v_cs, ranks);
v_cs_addr(ranks_per_slot-1) := not v_cs_addr(ranks_per_slot-1);
v_odt_values(v_cs).write := 2**to_integer(v_cs_addr);
v_odt_values(v_cs).read := v_odt_values(v_cs).write;
end loop;
end if;
elsif mem_type = "DDR3" then
assert (ranks rem ranks_per_slot = 0) report ac_report_prefix & "number of ranks per slot must be a multiple of number of ranks" severity failure;
v_num_slots := ranks/ranks_per_slot;
if v_num_slots = 1 then
-- special condition for 1 slot (i.e. DIMM) (2^n, n=0,1,2,... ranks only)
-- set odt on one chip for writes and no odt for reads
for v_cs in 0 to ranks-1 loop
v_odt_values(v_cs).write := 2**v_cs; -- on on the rank being written to
v_odt_values(v_cs).read := 0;
end loop;
else
-- if > 1 slot, set 1 odt enable on neighbouring slot for read and write
-- as an example consider the below for 4 slots with 2 ranks per slot
-- access to CS[0] or CS[1], enable ODT[2] or ODT[3]
-- access to CS[2] or CS[3], enable ODT[0] or ODT[1]
-- access to CS[4] or CS[5], enable ODT[6] or ODT[7]
-- access to CS[6] or CS[7], enable ODT[4] or ODT[5]
-- the logic below implements the above for varying ranks and ranks_per slot
-- under the condition that ranks/ranks_per_slot is integer
for v_cs in 0 to ranks-1 loop
v_cs_addr := to_unsigned(v_cs, ranks);
v_cs_addr(ranks_per_slot-1) := not v_cs_addr(ranks_per_slot-1);
v_odt_values(v_cs).write := 2**to_integer(v_cs_addr) + 2**(v_cs); -- turn on a neighbouring slots cs and current rank being written to
v_odt_values(v_cs).read := 2**to_integer(v_cs_addr);
end loop;
end if;
else
report ac_report_prefix & "unknown mem_type specified in the set_odt_values function in addr_cmd_pkg package" severity failure;
end if;
return v_odt_values;
end function;
-- -----------------------------------------------------------
-- set constant values to config_rec
-- ----------------------------------------------------------
function set_config_rec ( num_addr_bits : in natural;
num_ba_bits : in natural;
num_cs_bits : in natural;
num_ranks : in natural;
dwidth_ratio : in natural range 1 to c_max_cmds_per_clk;
mem_type : in string
) return t_addr_cmd_config_rec
is
variable v_config_rec : t_addr_cmd_config_rec;
begin
v_config_rec.num_addr_bits := num_addr_bits;
v_config_rec.num_ba_bits := num_ba_bits;
v_config_rec.num_cs_bits := num_cs_bits;
v_config_rec.num_ranks := num_ranks;
v_config_rec.cmds_per_clk := dwidth_ratio/2;
if mem_type = "DDR" then
v_config_rec.mem_type := DDR;
elsif mem_type = "DDR2" then
v_config_rec.mem_type := DDR2;
elsif mem_type = "DDR3" then
v_config_rec.mem_type := DDR3;
else
report ac_report_prefix & "unknown mem_type specified in the set_config_rec function in addr_cmd_pkg package" severity failure;
end if;
return v_config_rec;
end function;
-- The non-levelled sequencer doesn't make a distinction between CS_WIDTH and NUM_RANKS. In this case,
-- just set the two to be the same.
function set_config_rec ( num_addr_bits : in natural;
num_ba_bits : in natural;
num_cs_bits : in natural;
dwidth_ratio : in natural range 1 to c_max_cmds_per_clk;
mem_type : in string
) return t_addr_cmd_config_rec
is
begin
return set_config_rec(num_addr_bits, num_ba_bits, num_cs_bits, num_cs_bits, dwidth_ratio, mem_type);
end function;
-- -----------------------------------------------------------
-- unpack and pack address and command signals from and to t_addr_cmd_vector
-- -----------------------------------------------------------
-- -------------------------------------------------------------
-- convert from t_addr_cmd_vector to expanded addr/cmd signals
-- -------------------------------------------------------------
procedure unpack_addr_cmd_vector( addr_cmd_vector : in t_addr_cmd_vector;
config_rec : in t_addr_cmd_config_rec;
addr : out std_logic_vector;
ba : out std_logic_vector;
cas_n : out std_logic_vector;
ras_n : out std_logic_vector;
we_n : out std_logic_vector;
cke : out std_logic_vector;
cs_n : out std_logic_vector;
odt : out std_logic_vector;
rst_n : out std_logic_vector
)
is
variable v_mem_if_ranks : natural range 0 to 2**c_max_ranks - 1;
variable v_vec_len : natural range 1 to 4;
variable v_addr : std_logic_vector(config_rec.cmds_per_clk * config_rec.num_addr_bits - 1 downto 0);
variable v_ba : std_logic_vector(config_rec.cmds_per_clk * config_rec.num_ba_bits - 1 downto 0);
variable v_odt : std_logic_vector(config_rec.cmds_per_clk * config_rec.num_ranks - 1 downto 0);
variable v_cs_n : std_logic_vector(config_rec.cmds_per_clk * config_rec.num_cs_bits - 1 downto 0);
variable v_cke : std_logic_vector(config_rec.cmds_per_clk * config_rec.num_ranks - 1 downto 0);
variable v_cas_n : std_logic_vector(config_rec.cmds_per_clk - 1 downto 0);
variable v_ras_n : std_logic_vector(config_rec.cmds_per_clk - 1 downto 0);
variable v_we_n : std_logic_vector(config_rec.cmds_per_clk - 1 downto 0);
variable v_rst_n : std_logic_vector(config_rec.cmds_per_clk - 1 downto 0);
begin
v_vec_len := config_rec.cmds_per_clk;
v_mem_if_ranks := config_rec.num_ranks;
for v_i in 0 to v_vec_len-1 loop
assert addr_cmd_vector(v_i).addr < 2**config_rec.num_addr_bits report ac_report_prefix &
"value of addr exceeds range of number of address bits in unpack_addr_cmd_vector procedure" severity failure;
assert addr_cmd_vector(v_i).ba < 2**config_rec.num_ba_bits report ac_report_prefix &
"value of ba exceeds range of number of bank address bits in unpack_addr_cmd_vector procedure" severity failure;
assert addr_cmd_vector(v_i).odt < 2**v_mem_if_ranks report ac_report_prefix &
"value of odt exceeds range of number of ranks in unpack_addr_cmd_vector procedure" severity failure;
assert addr_cmd_vector(v_i).cs_n < 2**config_rec.num_cs_bits report ac_report_prefix &
"value of cs_n exceeds range of number of ranks in unpack_addr_cmd_vector procedure" severity failure;
assert addr_cmd_vector(v_i).cke < 2**v_mem_if_ranks report ac_report_prefix &
"value of cke exceeds range of number of ranks in unpack_addr_cmd_vector procedure" severity failure;
v_addr((v_i+1)*config_rec.num_addr_bits - 1 downto v_i*config_rec.num_addr_bits) := std_logic_vector(to_unsigned(addr_cmd_vector(v_i).addr,config_rec.num_addr_bits));
v_ba((v_i+1)*config_rec.num_ba_bits - 1 downto v_i*config_rec.num_ba_bits) := std_logic_vector(to_unsigned(addr_cmd_vector(v_i).ba,config_rec.num_ba_bits));
v_cke((v_i+1)*v_mem_if_ranks - 1 downto v_i*v_mem_if_ranks) := std_logic_vector(to_unsigned(addr_cmd_vector(v_i).cke,v_mem_if_ranks));
v_cs_n((v_i+1)*config_rec.num_cs_bits - 1 downto v_i*config_rec.num_cs_bits) := std_logic_vector(to_unsigned(addr_cmd_vector(v_i).cs_n,config_rec.num_cs_bits));
v_odt((v_i+1)*v_mem_if_ranks - 1 downto v_i*v_mem_if_ranks) := std_logic_vector(to_unsigned(addr_cmd_vector(v_i).odt,v_mem_if_ranks));
if (addr_cmd_vector(v_i).cas_n) then v_cas_n(v_i) := '0'; else v_cas_n(v_i) := '1'; end if;
if (addr_cmd_vector(v_i).ras_n) then v_ras_n(v_i) := '0'; else v_ras_n(v_i) := '1'; end if;
if (addr_cmd_vector(v_i).we_n) then v_we_n(v_i) := '0'; else v_we_n(v_i) := '1'; end if;
if (addr_cmd_vector(v_i).rst_n) then v_rst_n(v_i) := '0'; else v_rst_n(v_i) := '1'; end if;
end loop;
addr := v_addr;
ba := v_ba;
cke := v_cke;
cs_n := v_cs_n;
odt := v_odt;
cas_n := v_cas_n;
ras_n := v_ras_n;
we_n := v_we_n;
rst_n := v_rst_n;
end procedure;
procedure unpack_addr_cmd_vector( config_rec : in t_addr_cmd_config_rec;
addr_cmd_vector : in t_addr_cmd_vector;
signal addr : out std_logic_vector;
signal ba : out std_logic_vector;
signal cas_n : out std_logic_vector;
signal ras_n : out std_logic_vector;
signal we_n : out std_logic_vector;
signal cke : out std_logic_vector;
signal cs_n : out std_logic_vector;
signal odt : out std_logic_vector;
signal rst_n : out std_logic_vector
)
is
variable v_mem_if_ranks : natural range 0 to 2**c_max_ranks - 1;
variable v_vec_len : natural range 1 to 4;
variable v_seq_ac_addr : std_logic_vector(config_rec.cmds_per_clk * config_rec.num_addr_bits - 1 downto 0);
variable v_seq_ac_ba : std_logic_vector(config_rec.cmds_per_clk * config_rec.num_ba_bits - 1 downto 0);
variable v_seq_ac_cas_n : std_logic_vector(config_rec.cmds_per_clk - 1 downto 0);
variable v_seq_ac_ras_n : std_logic_vector(config_rec.cmds_per_clk - 1 downto 0);
variable v_seq_ac_we_n : std_logic_vector(config_rec.cmds_per_clk - 1 downto 0);
variable v_seq_ac_cke : std_logic_vector(config_rec.cmds_per_clk * config_rec.num_ranks - 1 downto 0);
variable v_seq_ac_cs_n : std_logic_vector(config_rec.cmds_per_clk * config_rec.num_cs_bits - 1 downto 0);
variable v_seq_ac_odt : std_logic_vector(config_rec.cmds_per_clk * config_rec.num_ranks - 1 downto 0);
variable v_seq_ac_rst_n : std_logic_vector(config_rec.cmds_per_clk - 1 downto 0);
begin
unpack_addr_cmd_vector (
addr_cmd_vector,
config_rec,
v_seq_ac_addr,
v_seq_ac_ba,
v_seq_ac_cas_n,
v_seq_ac_ras_n,
v_seq_ac_we_n,
v_seq_ac_cke,
v_seq_ac_cs_n,
v_seq_ac_odt,
v_seq_ac_rst_n);
addr <= v_seq_ac_addr;
ba <= v_seq_ac_ba;
cas_n <= v_seq_ac_cas_n;
ras_n <= v_seq_ac_ras_n;
we_n <= v_seq_ac_we_n;
cke <= v_seq_ac_cke;
cs_n <= v_seq_ac_cs_n;
odt <= v_seq_ac_odt;
rst_n <= v_seq_ac_rst_n;
end procedure;
-- -----------------------------------------------------------
-- function to mask each bit of signal signal_name in addr_cmd_
-- -----------------------------------------------------------
-- -----------------------------------------------------------
-- function to mask each bit of signal signal_name in addr_cmd_vector with mask_value
-- -----------------------------------------------------------
function mask ( config_rec : in t_addr_cmd_config_rec;
addr_cmd_vector : in t_addr_cmd_vector;
signal_name : in t_addr_cmd_signals;
mask_value : in std_logic
) return t_addr_cmd_vector
is
variable v_i : integer;
variable v_addr_cmd_vector : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
begin
v_addr_cmd_vector := addr_cmd_vector;
for v_i in 0 to (config_rec.cmds_per_clk)-1 loop
case signal_name is
when addr => if (mask_value = '0') then v_addr_cmd_vector(v_i).addr := 0; else v_addr_cmd_vector(v_i).addr := (2 ** config_rec.num_addr_bits) - 1; end if;
when ba => if (mask_value = '0') then v_addr_cmd_vector(v_i).ba := 0; else v_addr_cmd_vector(v_i).ba := (2 ** config_rec.num_ba_bits) - 1; end if;
when cas_n => if (mask_value = '0') then v_addr_cmd_vector(v_i).cas_n := true; else v_addr_cmd_vector(v_i).cas_n := false; end if;
when ras_n => if (mask_value = '0') then v_addr_cmd_vector(v_i).ras_n := true; else v_addr_cmd_vector(v_i).ras_n := false; end if;
when we_n => if (mask_value = '0') then v_addr_cmd_vector(v_i).we_n := true; else v_addr_cmd_vector(v_i).we_n := false; end if;
when cke => if (mask_value = '0') then v_addr_cmd_vector(v_i).cke := 0; else v_addr_cmd_vector(v_i).cke := (2**config_rec.num_ranks) -1; end if;
when cs_n => if (mask_value = '0') then v_addr_cmd_vector(v_i).cs_n := 0; else v_addr_cmd_vector(v_i).cs_n := (2**config_rec.num_cs_bits) -1; end if;
when odt => if (mask_value = '0') then v_addr_cmd_vector(v_i).odt := 0; else v_addr_cmd_vector(v_i).odt := (2**config_rec.num_ranks) -1; end if;
when rst_n => if (mask_value = '0') then v_addr_cmd_vector(v_i).rst_n := true; else v_addr_cmd_vector(v_i).rst_n := false; end if;
when others => report ac_report_prefix & "bit masking not supported for the given signal name" severity failure;
end case;
end loop;
return v_addr_cmd_vector;
end function;
-- -----------------------------------------------------------
-- procedure to mask each bit of signal signal_name in addr_cmd_vector with mask_value
-- -----------------------------------------------------------
procedure mask( config_rec : in t_addr_cmd_config_rec;
signal addr_cmd_vector : inout t_addr_cmd_vector;
signal_name : in t_addr_cmd_signals;
mask_value : in std_logic
)
is
variable v_i : integer;
begin
for v_i in 0 to (config_rec.cmds_per_clk)-1 loop
case signal_name is
when addr => if (mask_value = '0') then addr_cmd_vector(v_i).addr <= 0; else addr_cmd_vector(v_i).addr <= (2 ** config_rec.num_addr_bits) - 1; end if;
when ba => if (mask_value = '0') then addr_cmd_vector(v_i).ba <= 0; else addr_cmd_vector(v_i).ba <= (2 ** config_rec.num_ba_bits) - 1; end if;
when cas_n => if (mask_value = '0') then addr_cmd_vector(v_i).cas_n <= true; else addr_cmd_vector(v_i).cas_n <= false; end if;
when ras_n => if (mask_value = '0') then addr_cmd_vector(v_i).ras_n <= true; else addr_cmd_vector(v_i).ras_n <= false; end if;
when we_n => if (mask_value = '0') then addr_cmd_vector(v_i).we_n <= true; else addr_cmd_vector(v_i).we_n <= false; end if;
when cke => if (mask_value = '0') then addr_cmd_vector(v_i).cke <= 0; else addr_cmd_vector(v_i).cke <= (2**config_rec.num_ranks) -1; end if;
when cs_n => if (mask_value = '0') then addr_cmd_vector(v_i).cs_n <= 0; else addr_cmd_vector(v_i).cs_n <= (2**config_rec.num_cs_bits) -1; end if;
when odt => if (mask_value = '0') then addr_cmd_vector(v_i).odt <= 0; else addr_cmd_vector(v_i).odt <= (2**config_rec.num_ranks) -1; end if;
when rst_n => if (mask_value = '0') then addr_cmd_vector(v_i).rst_n <= true; else addr_cmd_vector(v_i).rst_n <= false; end if;
when others => report ac_report_prefix & "masking not supported for the given signal name" severity failure;
end case;
end loop;
end procedure;
-- -----------------------------------------------------------
-- function to mask a given bit (mask_bit) of signal signal_name in addr_cmd_vector with mask_value
-- -----------------------------------------------------------
function mask ( config_rec : in t_addr_cmd_config_rec;
addr_cmd_vector : in t_addr_cmd_vector;
signal_name : in t_addr_cmd_signals;
mask_value : in std_logic;
mask_bit : in natural
) return t_addr_cmd_vector
is
variable v_i : integer;
variable v_addr : std_logic_vector(config_rec.num_addr_bits-1 downto 0); -- v_addr is bit vector of address
variable v_ba : std_logic_vector(config_rec.num_ba_bits-1 downto 0); -- v_addr is bit vector of bank address
variable v_vec_len : natural range 0 to 4;
variable v_addr_cmd_vector : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
begin
v_addr_cmd_vector := addr_cmd_vector;
v_vec_len := config_rec.cmds_per_clk;
for v_i in 0 to v_vec_len-1 loop
case signal_name is
when addr =>
v_addr := std_logic_vector(to_unsigned(v_addr_cmd_vector(v_i).addr,v_addr'length));
v_addr(mask_bit) := mask_value;
v_addr_cmd_vector(v_i).addr := to_integer(unsigned(v_addr));
when ba =>
v_ba := std_logic_vector(to_unsigned(v_addr_cmd_vector(v_i).ba,v_ba'length));
v_ba(mask_bit) := mask_value;
v_addr_cmd_vector(v_i).ba := to_integer(unsigned(v_ba));
when others =>
report ac_report_prefix & "bit masking not supported for the given signal name" severity failure;
end case;
end loop;
return v_addr_cmd_vector;
end function;
--
end ddr3_int_phy_alt_mem_phy_addr_cmd_pkg;
--
-- -----------------------------------------------------------------------------
-- Abstract : iram addressing package for the non-levelling AFI PHY sequencer
-- The iram address package (alt_mem_phy_iram_addr_pkg) is
-- used to define the base addresses used for iram writes
-- during calibration.
-- -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--
package ddr3_int_phy_alt_mem_phy_iram_addr_pkg IS
constant c_ihi_size : natural := 8;
type t_base_hdr_addresses is record
base_hdr : natural;
rrp : natural;
safe_dummy : natural;
required_addr_bits : natural;
end record;
function defaults return t_base_hdr_addresses;
function rrp_pll_phase_mult (dwidth_ratio : in natural;
dqs_capture : in natural
)
return natural;
function iram_wd_for_full_rrp ( dwidth_ratio : in natural;
pll_phases : in natural;
dq_pins : in natural;
dqs_capture : in natural
)
return natural;
function iram_wd_for_one_pin_rrp ( dwidth_ratio : in natural;
pll_phases : in natural;
dq_pins : in natural;
dqs_capture : in natural
)
return natural;
function calc_iram_addresses ( dwidth_ratio : in natural;
pll_phases : in natural;
dq_pins : in natural;
num_ranks : in natural;
dqs_capture : in natural
)
return t_base_hdr_addresses;
--
end ddr3_int_phy_alt_mem_phy_iram_addr_pkg;
--
package body ddr3_int_phy_alt_mem_phy_iram_addr_pkg IS
-- set some safe default values
function defaults return t_base_hdr_addresses is
variable temp : t_base_hdr_addresses;
begin
temp.base_hdr := 0;
temp.rrp := 0;
temp.safe_dummy := 0;
temp.required_addr_bits := 1;
return temp;
end function;
-- this function determines now many times the PLL phases are swept through per pin
-- i.e. an n * 360 degree phase sweep
function rrp_pll_phase_mult (dwidth_ratio : in natural;
dqs_capture : in natural
)
return natural
is
variable v_output : natural;
begin
if dwidth_ratio = 2 and dqs_capture = 1 then
v_output := 2; -- if dqs_capture then a 720 degree sweep needed in FR
else
v_output := (dwidth_ratio/2);
end if;
return v_output;
end function;
-- function to calculate how many words are required for a rrp sweep over all pins
function iram_wd_for_full_rrp ( dwidth_ratio : in natural;
pll_phases : in natural;
dq_pins : in natural;
dqs_capture : in natural
)
return natural
is
variable v_output : natural;
variable v_phase_mul : natural;
begin
-- determine the n * 360 degrees of sweep required
v_phase_mul := rrp_pll_phase_mult(dwidth_ratio, dqs_capture);
-- calculate output size
v_output := dq_pins * (((v_phase_mul * pll_phases) + 31) / 32);
return v_output;
end function;
-- function to calculate how many words are required for a rrp sweep over all pins
function iram_wd_for_one_pin_rrp ( dwidth_ratio : in natural;
pll_phases : in natural;
dq_pins : in natural;
dqs_capture : in natural
)
return natural
is
variable v_output : natural;
variable v_phase_mul : natural;
begin
-- determine the n * 360 degrees of sweep required
v_phase_mul := rrp_pll_phase_mult(dwidth_ratio, dqs_capture);
-- calculate output size
v_output := ((v_phase_mul * pll_phases) + 31) / 32;
return v_output;
end function;
-- return iram addresses
function calc_iram_addresses ( dwidth_ratio : in natural;
pll_phases : in natural;
dq_pins : in natural;
num_ranks : in natural;
dqs_capture : in natural
)
return t_base_hdr_addresses
is
variable working : t_base_hdr_addresses;
variable temp : natural;
variable v_required_words : natural;
begin
working.base_hdr := 0;
working.rrp := working.base_hdr + c_ihi_size;
-- work out required number of address bits
-- + for 1 full rrp calibration
v_required_words := iram_wd_for_full_rrp(dwidth_ratio, pll_phases, dq_pins, dqs_capture) + 2; -- +2 for header + footer
-- * loop per cs
v_required_words := v_required_words * num_ranks;
-- + for 1 rrp_seek result
v_required_words := v_required_words + 3; -- 1 header, 1 word result, 1 footer
-- + 2 mtp_almt passes
v_required_words := v_required_words + 2 * (iram_wd_for_one_pin_rrp(dwidth_ratio, pll_phases, dq_pins, dqs_capture) + 2);
-- + for 2 read_mtp result calculation
v_required_words := v_required_words + 3*2; -- 1 header, 1 word result, 1 footer
-- * possible dwidth_ratio/2 iterations for different ac_nt settings
v_required_words := v_required_words * (dwidth_ratio / 2);
working.safe_dummy := working.rrp + v_required_words;
temp := working.safe_dummy;
working.required_addr_bits := 0;
while (temp >= 1) loop
working.required_addr_bits := working.required_addr_bits + 1;
temp := temp /2;
end loop;
return working;
end function calc_iram_addresses;
--
END ddr3_int_phy_alt_mem_phy_iram_addr_pkg;
--
-- -----------------------------------------------------------------------------
-- Abstract : register package for the non-levelling AFI PHY sequencer
-- The registers package (alt_mem_phy_regs_pkg) is used to
-- combine the definition of the registers for the mmi status
-- registers and functions/procedures applied to the registers
-- -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
-- The record package (alt_mem_phy_record_pkg) is used to combine command and status signals
-- (into records) to be passed between sequencer blocks. It also contains type and record definitions
-- for the stages of DRAM memory calibration.
--
use work.ddr3_int_phy_alt_mem_phy_record_pkg.all;
-- The constant package (alt_mem_phy_constants_pkg) contains global 'constants' which are fixed
-- thoughout the sequencer and will not change (for constants which may change between sequencer
-- instances generics are used)
--
use work.ddr3_int_phy_alt_mem_phy_constants_pkg.all;
--
package ddr3_int_phy_alt_mem_phy_regs_pkg is
-- a prefix for all report signals to identify phy and sequencer block
--
constant regs_report_prefix : string := "ddr3_int_phy_alt_mem_phy_seq (register package) : ";
-- ---------------------------------------------------------------
-- register declarations with associated functions of:
-- default - assign default values
-- write - write data into the reg (from avalon i/f)
-- read - read data from the reg (sent to the avalon i/f)
-- write_clear - clear reg to all zeros
-- ---------------------------------------------------------------
-- TYPE DECLARATIONS
-- >>>>>>>>>>>>>>>>>>>>>>>>
-- Read Only Registers
-- >>>>>>>>>>>>>>>>>>>>>>>>
-- cal_status
type t_cal_status is record
iram_addr_width : std_logic_vector(3 downto 0);
out_of_mem : std_logic;
contested_access : std_logic;
cal_fail : std_logic;
cal_success : std_logic;
ctrl_err_code : std_logic_vector(7 downto 0);
trefi_failure : std_logic;
int_ac_1t : std_logic;
dqs_capture : std_logic;
iram_present : std_logic;
active_block : std_logic_vector(3 downto 0);
current_stage : std_logic_vector(7 downto 0);
end record;
-- codvw status
type t_codvw_status is record
cal_codvw_phase : std_logic_vector(7 downto 0);
cal_codvw_size : std_logic_vector(7 downto 0);
codvw_trk_shift : std_logic_vector(11 downto 0);
codvw_grt_one_dvw : std_logic;
end record t_codvw_status;
-- test status report
type t_test_status is record
ack_seen : std_logic_vector(c_hl_ccs_num_stages-1 downto 0);
pll_mmi_err : std_logic_vector(1 downto 0);
pll_busy : std_logic;
end record;
-- define all the read only registers :
type t_ro_regs is record
cal_status : t_cal_status;
codvw_status : t_codvw_status;
test_status : t_test_status;
end record;
-- >>>>>>>>>>>>>>>>>>>>>>>>
-- Read / Write Registers
-- >>>>>>>>>>>>>>>>>>>>>>>>
-- Calibration control register
type t_hl_css is record
hl_css : std_logic_vector(c_hl_ccs_num_stages-1 downto 0);
cal_start : std_logic;
end record t_hl_css;
-- Mode register A
type t_mr_register_a is record
mr0 : std_logic_vector(c_max_mode_reg_index -1 downto 0);
mr1 : std_logic_vector(c_max_mode_reg_index -1 downto 0);
end record t_mr_register_a;
-- Mode register B
type t_mr_register_b is record
mr2 : std_logic_vector(c_max_mode_reg_index -1 downto 0);
mr3 : std_logic_vector(c_max_mode_reg_index -1 downto 0);
end record t_mr_register_b;
-- algorithm parameterisation register
type t_parameterisation_reg_a is record
nominal_poa_phase_lead : std_logic_vector(3 downto 0);
maximum_poa_delay : std_logic_vector(3 downto 0);
num_phases_per_tck_pll : std_logic_vector(3 downto 0);
pll_360_sweeps : std_logic_vector(3 downto 0);
nominal_dqs_delay : std_logic_vector(2 downto 0);
extend_octrt_by : std_logic_vector(3 downto 0);
delay_octrt_by : std_logic_vector(3 downto 0);
end record;
-- test signal register
type t_if_test_reg is record
pll_phs_shft_phase_sel : natural range 0 to 15;
pll_phs_shft_up_wc : std_logic;
pll_phs_shft_dn_wc : std_logic;
ac_1t_toggle : std_logic; -- unused
tracking_period_ms : std_logic_vector(7 downto 0); -- 0 = as fast as possible approx in ms
tracking_units_are_10us : std_logic;
end record;
-- define all the read/write registers
type t_rw_regs is record
mr_reg_a : t_mr_register_a;
mr_reg_b : t_mr_register_b;
rw_hl_css : t_hl_css;
rw_param_reg : t_parameterisation_reg_a;
rw_if_test : t_if_test_reg;
end record;
-- >>>>>>>>>>>>>>>>>>>>>>>
-- Group all registers
-- >>>>>>>>>>>>>>>>>>>>>>>
type t_mmi_regs is record
rw_regs : t_rw_regs;
ro_regs : t_ro_regs;
enable_writes : std_logic;
end record;
-- FUNCTION DECLARATIONS
-- >>>>>>>>>>>>>>>>>>>>>>>>
-- Read Only Registers
-- >>>>>>>>>>>>>>>>>>>>>>>>
-- cal_status
function defaults return t_cal_status;
function defaults ( ctrl_mmi : in t_ctrl_mmi;
USE_IRAM : in std_logic;
dqs_capture : in natural;
int_ac_1t : in std_logic;
trefi_failure : in std_logic;
iram_status : in t_iram_stat;
IRAM_AWIDTH : in natural
) return t_cal_status;
function read (reg : t_cal_status) return std_logic_vector;
-- codvw status
function defaults return t_codvw_status;
function defaults ( dgrb_mmi : t_dgrb_mmi
) return t_codvw_status;
function read (reg : in t_codvw_status) return std_logic_vector;
-- test status report
function defaults return t_test_status;
function defaults ( ctrl_mmi : in t_ctrl_mmi;
pll_mmi : in t_pll_mmi;
rw_if_test : t_if_test_reg
) return t_test_status;
function read (reg : t_test_status) return std_logic_vector;
-- define all the read only registers
function defaults return t_ro_regs;
function defaults (dgrb_mmi : t_dgrb_mmi;
ctrl_mmi : t_ctrl_mmi;
pll_mmi : t_pll_mmi;
rw_if_test : t_if_test_reg;
USE_IRAM : std_logic;
dqs_capture : natural;
int_ac_1t : std_logic;
trefi_failure : std_logic;
iram_status : t_iram_stat;
IRAM_AWIDTH : natural
) return t_ro_regs;
-- >>>>>>>>>>>>>>>>>>>>>>>>
-- Read / Write Registers
-- >>>>>>>>>>>>>>>>>>>>>>>>
-- Calibration control register
-- high level calibration stage set register comprises a bit vector for
-- the calibration stage coding and the 1 control bit.
function defaults return t_hl_css;
function write (wdata_in : std_logic_vector(31 downto 0)) return t_hl_css;
function read (reg : in t_hl_css) return std_logic_vector;
procedure write_clear (signal reg : inout t_hl_css);
-- Mode register A
-- mode registers 0 and 1 (mr and emr1)
function defaults return t_mr_register_a;
function defaults ( mr0 : in std_logic_vector;
mr1 : in std_logic_vector
) return t_mr_register_a;
function write (wdata_in : std_logic_vector(31 downto 0)) return t_mr_register_a;
function read (reg : in t_mr_register_a) return std_logic_vector;
-- Mode register B
-- mode registers 2 and 3 (emr2 and emr3) - not present in ddr DRAM
function defaults return t_mr_register_b;
function defaults ( mr2 : in std_logic_vector;
mr3 : in std_logic_vector
) return t_mr_register_b;
function write (wdata_in : std_logic_vector(31 downto 0)) return t_mr_register_b;
function read (reg : in t_mr_register_b) return std_logic_vector;
-- algorithm parameterisation register
function defaults return t_parameterisation_reg_a;
function defaults ( NOM_DQS_PHASE_SETTING : in natural;
PLL_STEPS_PER_CYCLE : in natural;
pll_360_sweeps : in natural
) return t_parameterisation_reg_a;
function read ( reg : in t_parameterisation_reg_a) return std_logic_vector;
function write (wdata_in : std_logic_vector(31 downto 0)) return t_parameterisation_reg_a;
-- test signal register
function defaults return t_if_test_reg;
function defaults ( TRACKING_INTERVAL_IN_MS : in natural
) return t_if_test_reg;
function read ( reg : in t_if_test_reg) return std_logic_vector;
function write (wdata_in : std_logic_vector(31 downto 0)) return t_if_test_reg;
procedure write_clear (signal reg : inout t_if_test_reg);
-- define all the read/write registers
function defaults return t_rw_regs;
function defaults(
mr0 : in std_logic_vector;
mr1 : in std_logic_vector;
mr2 : in std_logic_vector;
mr3 : in std_logic_vector;
NOM_DQS_PHASE_SETTING : in natural;
PLL_STEPS_PER_CYCLE : in natural;
pll_360_sweeps : in natural;
TRACKING_INTERVAL_IN_MS : in natural;
C_HL_STAGE_ENABLE : in std_logic_vector(c_hl_ccs_num_stages-1 downto 0)
)return t_rw_regs;
procedure write_clear (signal regs : inout t_rw_regs);
-- >>>>>>>>>>>>>>>>>>>>>>>
-- Group all registers
-- >>>>>>>>>>>>>>>>>>>>>>>
function defaults return t_mmi_regs;
function v_read (mmi_regs : in t_mmi_regs;
address : in natural
) return std_logic_vector;
function read (signal mmi_regs : in t_mmi_regs;
address : in natural
) return std_logic_vector;
procedure write (mmi_regs : inout t_mmi_regs;
address : in natural;
wdata : in std_logic_vector(31 downto 0));
-- >>>>>>>>>>>>>>>>>>>>>>>
-- functions to communicate register settings to other sequencer blocks
-- >>>>>>>>>>>>>>>>>>>>>>>
function pack_record (ip_regs : t_rw_regs) return t_mmi_pll_reconfig;
function pack_record (ip_regs : t_rw_regs) return t_admin_ctrl;
function pack_record (ip_regs : t_rw_regs) return t_mmi_ctrl;
function pack_record ( ip_regs : t_rw_regs) return t_algm_paramaterisation;
-- >>>>>>>>>>>>>>>>>>>>>>>
-- helper functions
-- >>>>>>>>>>>>>>>>>>>>>>>
function to_t_hl_css_reg (hl_css : t_hl_css ) return t_hl_css_reg;
function pack_ack_seen ( cal_stage_ack_seen : in t_cal_stage_ack_seen
) return std_logic_vector;
-- encoding of stage and active block for register setting
function encode_current_stage (ctrl_cmd_id : t_ctrl_cmd_id) return std_logic_vector;
function encode_active_block (active_block : t_ctrl_active_block) return std_logic_vector;
--
end ddr3_int_phy_alt_mem_phy_regs_pkg;
--
package body ddr3_int_phy_alt_mem_phy_regs_pkg is
-- >>>>>>>>>>>>>>>>>>>>
-- Read Only Registers
-- >>>>>>>>>>>>>>>>>>>
-- ---------------------------------------------------------------
-- CODVW status report
-- ---------------------------------------------------------------
function defaults return t_codvw_status is
variable temp: t_codvw_status;
begin
temp.cal_codvw_phase := (others => '0');
temp.cal_codvw_size := (others => '0');
temp.codvw_trk_shift := (others => '0');
temp.codvw_grt_one_dvw := '0';
return temp;
end function;
function defaults ( dgrb_mmi : t_dgrb_mmi
) return t_codvw_status is
variable temp: t_codvw_status;
begin
temp := defaults;
temp.cal_codvw_phase := dgrb_mmi.cal_codvw_phase;
temp.cal_codvw_size := dgrb_mmi.cal_codvw_size;
temp.codvw_trk_shift := dgrb_mmi.codvw_trk_shift;
temp.codvw_grt_one_dvw := dgrb_mmi.codvw_grt_one_dvw;
return temp;
end function;
function read (reg : in t_codvw_status) return std_logic_vector is
variable temp : std_logic_vector(31 downto 0);
begin
temp := (others => '0');
temp(31 downto 24) := reg.cal_codvw_phase;
temp(23 downto 16) := reg.cal_codvw_size;
temp(15 downto 4) := reg.codvw_trk_shift;
temp(0) := reg.codvw_grt_one_dvw;
return temp;
end function;
-- ---------------------------------------------------------------
-- Calibration status report
-- ---------------------------------------------------------------
function defaults return t_cal_status is
variable temp: t_cal_status;
begin
temp.iram_addr_width := (others => '0');
temp.out_of_mem := '0';
temp.contested_access := '0';
temp.cal_fail := '0';
temp.cal_success := '0';
temp.ctrl_err_code := (others => '0');
temp.trefi_failure := '0';
temp.int_ac_1t := '0';
temp.dqs_capture := '0';
temp.iram_present := '0';
temp.active_block := (others => '0');
temp.current_stage := (others => '0');
return temp;
end function;
function defaults ( ctrl_mmi : in t_ctrl_mmi;
USE_IRAM : in std_logic;
dqs_capture : in natural;
int_ac_1t : in std_logic;
trefi_failure : in std_logic;
iram_status : in t_iram_stat;
IRAM_AWIDTH : in natural
) return t_cal_status is
variable temp : t_cal_status;
begin
temp := defaults;
temp.iram_addr_width := std_logic_vector(to_unsigned(IRAM_AWIDTH, temp.iram_addr_width'length));
temp.out_of_mem := iram_status.out_of_mem;
temp.contested_access := iram_status.contested_access;
temp.cal_fail := ctrl_mmi.ctrl_calibration_fail;
temp.cal_success := ctrl_mmi.ctrl_calibration_success;
temp.ctrl_err_code := ctrl_mmi.ctrl_err_code;
temp.trefi_failure := trefi_failure;
temp.int_ac_1t := int_ac_1t;
if dqs_capture = 1 then
temp.dqs_capture := '1';
elsif dqs_capture = 0 then
temp.dqs_capture := '0';
else
report regs_report_prefix & " invalid value for dqs_capture constant of " & integer'image(dqs_capture) severity failure;
end if;
temp.iram_present := USE_IRAM;
temp.active_block := encode_active_block(ctrl_mmi.ctrl_current_active_block);
temp.current_stage := encode_current_stage(ctrl_mmi.ctrl_current_stage);
return temp;
end function;
-- read for mmi status register
function read ( reg : t_cal_status
) return std_logic_vector is
variable output : std_logic_vector(31 downto 0);
begin
output := (others => '0');
output( 7 downto 0) := reg.current_stage;
output(11 downto 8) := reg.active_block;
output(12) := reg.iram_present;
output(13) := reg.dqs_capture;
output(14) := reg.int_ac_1t;
output(15) := reg.trefi_failure;
output(23 downto 16) := reg.ctrl_err_code;
output(24) := reg.cal_success;
output(25) := reg.cal_fail;
output(26) := reg.contested_access;
output(27) := reg.out_of_mem;
output(31 downto 28) := reg.iram_addr_width;
return output;
end function;
-- ---------------------------------------------------------------
-- Test status report
-- ---------------------------------------------------------------
function defaults return t_test_status is
variable temp: t_test_status;
begin
temp.ack_seen := (others => '0');
temp.pll_mmi_err := (others => '0');
temp.pll_busy := '0';
return temp;
end function;
function defaults ( ctrl_mmi : in t_ctrl_mmi;
pll_mmi : in t_pll_mmi;
rw_if_test : t_if_test_reg
) return t_test_status is
variable temp : t_test_status;
begin
temp := defaults;
temp.ack_seen := pack_ack_seen(ctrl_mmi.ctrl_cal_stage_ack_seen);
temp.pll_mmi_err := pll_mmi.err;
temp.pll_busy := pll_mmi.pll_busy or rw_if_test.pll_phs_shft_up_wc or rw_if_test.pll_phs_shft_dn_wc;
return temp;
end function;
-- read for mmi status register
function read ( reg : t_test_status
) return std_logic_vector is
variable output : std_logic_vector(31 downto 0);
begin
output := (others => '0');
output(31 downto 32-c_hl_ccs_num_stages) := reg.ack_seen;
output( 5 downto 4) := reg.pll_mmi_err;
output(0) := reg.pll_busy;
return output;
end function;
-------------------------------------------------
-- FOR ALL RO REGS:
-------------------------------------------------
function defaults return t_ro_regs is
variable temp: t_ro_regs;
begin
temp.cal_status := defaults;
temp.codvw_status := defaults;
return temp;
end function;
function defaults (dgrb_mmi : t_dgrb_mmi;
ctrl_mmi : t_ctrl_mmi;
pll_mmi : t_pll_mmi;
rw_if_test : t_if_test_reg;
USE_IRAM : std_logic;
dqs_capture : natural;
int_ac_1t : std_logic;
trefi_failure : std_logic;
iram_status : t_iram_stat;
IRAM_AWIDTH : natural
) return t_ro_regs is
variable output : t_ro_regs;
begin
output := defaults;
output.cal_status := defaults(ctrl_mmi, USE_IRAM, dqs_capture, int_ac_1t, trefi_failure, iram_status, IRAM_AWIDTH);
output.codvw_status := defaults(dgrb_mmi);
output.test_status := defaults(ctrl_mmi, pll_mmi, rw_if_test);
return output;
end function;
-- >>>>>>>>>>>>>>>>>>>>>>>>
-- Read / Write registers
-- >>>>>>>>>>>>>>>>>>>>>>>>
-- ---------------------------------------------------------------
-- mode register set A
-- ---------------------------------------------------------------
function defaults return t_mr_register_a is
variable temp :t_mr_register_a;
begin
temp.mr0 := (others => '0');
temp.mr1 := (others => '0');
return temp;
end function;
-- apply default mode register settings to register
function defaults ( mr0 : in std_logic_vector;
mr1 : in std_logic_vector
) return t_mr_register_a is
variable temp :t_mr_register_a;
begin
temp := defaults;
temp.mr0 := mr0(temp.mr0'range);
temp.mr1 := mr1(temp.mr1'range);
return temp;
end function;
function write (wdata_in : std_logic_vector(31 downto 0)) return t_mr_register_a is
variable temp :t_mr_register_a;
begin
temp.mr0 := wdata_in(c_max_mode_reg_index -1 downto 0);
temp.mr1 := wdata_in(c_max_mode_reg_index -1 + 16 downto 16);
return temp;
end function;
function read (reg : in t_mr_register_a) return std_logic_vector is
variable temp : std_logic_vector(31 downto 0) := (others => '0');
begin
temp(c_max_mode_reg_index -1 downto 0) := reg.mr0;
temp(c_max_mode_reg_index -1 + 16 downto 16) := reg.mr1;
return temp;
end function;
-- ---------------------------------------------------------------
-- mode register set B
-- ---------------------------------------------------------------
function defaults return t_mr_register_b is
variable temp :t_mr_register_b;
begin
temp.mr2 := (others => '0');
temp.mr3 := (others => '0');
return temp;
end function;
-- apply default mode register settings to register
function defaults ( mr2 : in std_logic_vector;
mr3 : in std_logic_vector
) return t_mr_register_b is
variable temp :t_mr_register_b;
begin
temp := defaults;
temp.mr2 := mr2(temp.mr2'range);
temp.mr3 := mr3(temp.mr3'range);
return temp;
end function;
function write (wdata_in : std_logic_vector(31 downto 0)) return t_mr_register_b is
variable temp :t_mr_register_b;
begin
temp.mr2 := wdata_in(c_max_mode_reg_index -1 downto 0);
temp.mr3 := wdata_in(c_max_mode_reg_index -1 + 16 downto 16);
return temp;
end function;
function read (reg : in t_mr_register_b) return std_logic_vector is
variable temp : std_logic_vector(31 downto 0) := (others => '0');
begin
temp(c_max_mode_reg_index -1 downto 0) := reg.mr2;
temp(c_max_mode_reg_index -1 + 16 downto 16) := reg.mr3;
return temp;
end function;
-- ---------------------------------------------------------------
-- HL CSS (high level calibration state status)
-- ---------------------------------------------------------------
function defaults return t_hl_css is
variable temp : t_hl_css;
begin
temp.hl_css := (others => '0');
temp.cal_start := '0';
return temp;
end function;
function defaults ( C_HL_STAGE_ENABLE : in std_logic_vector(c_hl_ccs_num_stages-1 downto 0)
) return t_hl_css is
variable temp: t_hl_css;
begin
temp := defaults;
temp.hl_css := temp.hl_css OR C_HL_STAGE_ENABLE;
return temp;
end function;
function read ( reg : in t_hl_css) return std_logic_vector is
variable temp : std_logic_vector (31 downto 0) := (others => '0');
begin
temp(30 downto 30-c_hl_ccs_num_stages+1) := reg.hl_css;
temp(0) := reg.cal_start;
return temp;
end function;
function write (wdata_in : std_logic_vector(31 downto 0) )return t_hl_css is
variable reg : t_hl_css;
begin
reg.hl_css := wdata_in(30 downto 30-c_hl_ccs_num_stages+1);
reg.cal_start := wdata_in(0);
return reg;
end function;
procedure write_clear (signal reg : inout t_hl_css) is
begin
reg.cal_start <= '0';
end procedure;
-- ---------------------------------------------------------------
-- paramaterisation of sequencer through Avalon interface
-- ---------------------------------------------------------------
function defaults return t_parameterisation_reg_a is
variable temp : t_parameterisation_reg_a;
begin
temp.nominal_poa_phase_lead := (others => '0');
temp.maximum_poa_delay := (others => '0');
temp.pll_360_sweeps := "0000";
temp.num_phases_per_tck_pll := "0011";
temp.nominal_dqs_delay := (others => '0');
temp.extend_octrt_by := "0100";
temp.delay_octrt_by := "0000";
return temp;
end function;
-- reset the paramterisation reg to given values
function defaults ( NOM_DQS_PHASE_SETTING : in natural;
PLL_STEPS_PER_CYCLE : in natural;
pll_360_sweeps : in natural
) return t_parameterisation_reg_a is
variable temp: t_parameterisation_reg_a;
begin
temp := defaults;
temp.num_phases_per_tck_pll := std_logic_vector(to_unsigned(PLL_STEPS_PER_CYCLE /8 , temp.num_phases_per_tck_pll'high + 1 ));
temp.pll_360_sweeps := std_logic_vector(to_unsigned(pll_360_sweeps , temp.pll_360_sweeps'high + 1 ));
temp.nominal_dqs_delay := std_logic_vector(to_unsigned(NOM_DQS_PHASE_SETTING , temp.nominal_dqs_delay'high + 1 ));
temp.extend_octrt_by := std_logic_vector(to_unsigned(5 , temp.extend_octrt_by'high + 1 ));
temp.delay_octrt_by := std_logic_vector(to_unsigned(6 , temp.delay_octrt_by'high + 1 ));
return temp;
end function;
function read ( reg : in t_parameterisation_reg_a) return std_logic_vector is
variable temp : std_logic_vector (31 downto 0) := (others => '0');
begin
temp( 3 downto 0) := reg.pll_360_sweeps;
temp( 7 downto 4) := reg.num_phases_per_tck_pll;
temp(10 downto 8) := reg.nominal_dqs_delay;
temp(19 downto 16) := reg.nominal_poa_phase_lead;
temp(23 downto 20) := reg.maximum_poa_delay;
temp(27 downto 24) := reg.extend_octrt_by;
temp(31 downto 28) := reg.delay_octrt_by;
return temp;
end function;
function write (wdata_in : std_logic_vector(31 downto 0)) return t_parameterisation_reg_a is
variable reg : t_parameterisation_reg_a;
begin
reg.pll_360_sweeps := wdata_in( 3 downto 0);
reg.num_phases_per_tck_pll := wdata_in( 7 downto 4);
reg.nominal_dqs_delay := wdata_in(10 downto 8);
reg.nominal_poa_phase_lead := wdata_in(19 downto 16);
reg.maximum_poa_delay := wdata_in(23 downto 20);
reg.extend_octrt_by := wdata_in(27 downto 24);
reg.delay_octrt_by := wdata_in(31 downto 28);
return reg;
end function;
-- ---------------------------------------------------------------
-- t_if_test_reg - additional test support register
-- ---------------------------------------------------------------
function defaults return t_if_test_reg is
variable temp : t_if_test_reg;
begin
temp.pll_phs_shft_phase_sel := 0;
temp.pll_phs_shft_up_wc := '0';
temp.pll_phs_shft_dn_wc := '0';
temp.ac_1t_toggle := '0';
temp.tracking_period_ms := "10000000"; -- 127 ms interval
temp.tracking_units_are_10us := '0';
return temp;
end function;
-- reset the paramterisation reg to given values
function defaults ( TRACKING_INTERVAL_IN_MS : in natural
) return t_if_test_reg is
variable temp: t_if_test_reg;
begin
temp := defaults;
temp.tracking_period_ms := std_logic_vector(to_unsigned(TRACKING_INTERVAL_IN_MS, temp.tracking_period_ms'length));
return temp;
end function;
function read ( reg : in t_if_test_reg) return std_logic_vector is
variable temp : std_logic_vector (31 downto 0) := (others => '0');
begin
temp( 3 downto 0) := std_logic_vector(to_unsigned(reg.pll_phs_shft_phase_sel,4));
temp(4) := reg.pll_phs_shft_up_wc;
temp(5) := reg.pll_phs_shft_dn_wc;
temp(16) := reg.ac_1t_toggle;
temp(15 downto 8) := reg.tracking_period_ms;
temp(20) := reg.tracking_units_are_10us;
return temp;
end function;
function write (wdata_in : std_logic_vector(31 downto 0)) return t_if_test_reg is
variable reg : t_if_test_reg;
begin
reg.pll_phs_shft_phase_sel := to_integer(unsigned(wdata_in( 3 downto 0)));
reg.pll_phs_shft_up_wc := wdata_in(4);
reg.pll_phs_shft_dn_wc := wdata_in(5);
reg.ac_1t_toggle := wdata_in(16);
reg.tracking_period_ms := wdata_in(15 downto 8);
reg.tracking_units_are_10us := wdata_in(20);
return reg;
end function;
procedure write_clear (signal reg : inout t_if_test_reg) is
begin
reg.ac_1t_toggle <= '0';
reg.pll_phs_shft_up_wc <= '0';
reg.pll_phs_shft_dn_wc <= '0';
end procedure;
-- ---------------------------------------------------------------
-- RW Regs, record of read/write register records (to simplify handling)
-- ---------------------------------------------------------------
function defaults return t_rw_regs is
variable temp : t_rw_regs;
begin
temp.mr_reg_a := defaults;
temp.mr_reg_b := defaults;
temp.rw_hl_css := defaults;
temp.rw_param_reg := defaults;
temp.rw_if_test := defaults;
return temp;
end function;
function defaults(
mr0 : in std_logic_vector;
mr1 : in std_logic_vector;
mr2 : in std_logic_vector;
mr3 : in std_logic_vector;
NOM_DQS_PHASE_SETTING : in natural;
PLL_STEPS_PER_CYCLE : in natural;
pll_360_sweeps : in natural;
TRACKING_INTERVAL_IN_MS : in natural;
C_HL_STAGE_ENABLE : in std_logic_vector(c_hl_ccs_num_stages-1 downto 0)
)return t_rw_regs is
variable temp : t_rw_regs;
begin
temp := defaults;
temp.mr_reg_a := defaults(mr0, mr1);
temp.mr_reg_b := defaults(mr2, mr3);
temp.rw_param_reg := defaults(NOM_DQS_PHASE_SETTING,
PLL_STEPS_PER_CYCLE,
pll_360_sweeps);
temp.rw_if_test := defaults(TRACKING_INTERVAL_IN_MS);
temp.rw_hl_css := defaults(C_HL_STAGE_ENABLE);
return temp;
end function;
procedure write_clear (signal regs : inout t_rw_regs) is
begin
write_clear(regs.rw_if_test);
write_clear(regs.rw_hl_css);
end procedure;
-- >>>>>>>>>>>>>>>>>>>>>>>>>>
-- All mmi registers:
-- >>>>>>>>>>>>>>>>>>>>>>>>>>
function defaults return t_mmi_regs is
variable v_mmi_regs : t_mmi_regs;
begin
v_mmi_regs.rw_regs := defaults;
v_mmi_regs.ro_regs := defaults;
v_mmi_regs.enable_writes := '0';
return v_mmi_regs;
end function;
function v_read (mmi_regs : in t_mmi_regs;
address : in natural
) return std_logic_vector is
variable output : std_logic_vector(31 downto 0);
begin
output := (others => '0');
case address is
-- status register
when c_regofst_cal_status => output := read (mmi_regs.ro_regs.cal_status);
-- debug access register
when c_regofst_debug_access =>
if (mmi_regs.enable_writes = '1') then
output := c_mmi_access_codeword;
else
output := (others => '0');
end if;
-- test i/f to check which stages have acknowledged a command and pll checks
when c_regofst_test_status => output := read(mmi_regs.ro_regs.test_status);
-- mode registers
when c_regofst_mr_register_a => output := read(mmi_regs.rw_regs.mr_reg_a);
when c_regofst_mr_register_b => output := read(mmi_regs.rw_regs.mr_reg_b);
-- codvw r/o status register
when c_regofst_codvw_status => output := read(mmi_regs.ro_regs.codvw_status);
-- read/write registers
when c_regofst_hl_css => output := read(mmi_regs.rw_regs.rw_hl_css);
when c_regofst_if_param => output := read(mmi_regs.rw_regs.rw_param_reg);
when c_regofst_if_test => output := read(mmi_regs.rw_regs.rw_if_test);
when others => report regs_report_prefix & "MMI registers detected an attempt to read to non-existant register location" severity warning;
-- set illegal addr interrupt.
end case;
return output;
end function;
function read (signal mmi_regs : in t_mmi_regs;
address : in natural
) return std_logic_vector is
variable output : std_logic_vector(31 downto 0);
variable v_mmi_regs : t_mmi_regs;
begin
v_mmi_regs := mmi_regs;
output := v_read(v_mmi_regs, address);
return output;
end function;
procedure write (mmi_regs : inout t_mmi_regs;
address : in natural;
wdata : in std_logic_vector(31 downto 0)) is
begin
-- intercept writes to codeword. This needs to be set for iRAM access :
if address = c_regofst_debug_access then
if wdata = c_mmi_access_codeword then
mmi_regs.enable_writes := '1';
else
mmi_regs.enable_writes := '0';
end if;
else
case address is
-- read only registers
when c_regofst_cal_status |
c_regofst_codvw_status |
c_regofst_test_status =>
report regs_report_prefix & "MMI registers detected an attempt to write to read only register number" & integer'image(address) severity failure;
-- read/write registers
when c_regofst_mr_register_a => mmi_regs.rw_regs.mr_reg_a := write(wdata);
when c_regofst_mr_register_b => mmi_regs.rw_regs.mr_reg_b := write(wdata);
when c_regofst_hl_css => mmi_regs.rw_regs.rw_hl_css := write(wdata);
when c_regofst_if_param => mmi_regs.rw_regs.rw_param_reg := write(wdata);
when c_regofst_if_test => mmi_regs.rw_regs.rw_if_test := write(wdata);
when others => -- set illegal addr interrupt.
report regs_report_prefix & "MMI registers detected an attempt to write to non existant register, with expected number" & integer'image(address) severity failure;
end case;
end if;
end procedure;
-- >>>>>>>>>>>>>>>>>>>>>>>>>>
-- the following functions enable register data to be communicated to other sequencer blocks
-- >>>>>>>>>>>>>>>>>>>>>>>>>>
function pack_record ( ip_regs : t_rw_regs
) return t_algm_paramaterisation is
variable output : t_algm_paramaterisation;
begin
-- default assignments
output.num_phases_per_tck_pll := 16;
output.pll_360_sweeps := 1;
output.nominal_dqs_delay := 2;
output.nominal_poa_phase_lead := 1;
output.maximum_poa_delay := 5;
output.odt_enabled := false;
output.num_phases_per_tck_pll := to_integer(unsigned(ip_regs.rw_param_reg.num_phases_per_tck_pll)) * 8;
case ip_regs.rw_param_reg.nominal_dqs_delay is
when "010" => output.nominal_dqs_delay := 2;
when "001" => output.nominal_dqs_delay := 1;
when "000" => output.nominal_dqs_delay := 0;
when "011" => output.nominal_dqs_delay := 3;
when others => report regs_report_prefix &
"there is a unsupported number of DQS taps (" &
natural'image(to_integer(unsigned(ip_regs.rw_param_reg.nominal_dqs_delay))) &
") being advertised as the standard value" severity error;
end case;
case ip_regs.rw_param_reg.nominal_poa_phase_lead is
when "0001" => output.nominal_poa_phase_lead := 1;
when "0010" => output.nominal_poa_phase_lead := 2;
when "0011" => output.nominal_poa_phase_lead := 3;
when "0000" => output.nominal_poa_phase_lead := 0;
when others => report regs_report_prefix &
"there is an unsupported nominal postamble phase lead paramater set (" &
natural'image(to_integer(unsigned(ip_regs.rw_param_reg.nominal_poa_phase_lead))) &
")" severity error;
end case;
if ( (ip_regs.mr_reg_a.mr1(2) = '1')
or (ip_regs.mr_reg_a.mr1(6) = '1')
or (ip_regs.mr_reg_a.mr1(9) = '1')
) then
output.odt_enabled := true;
end if;
output.pll_360_sweeps := to_integer(unsigned(ip_regs.rw_param_reg.pll_360_sweeps));
output.maximum_poa_delay := to_integer(unsigned(ip_regs.rw_param_reg.maximum_poa_delay));
output.extend_octrt_by := to_integer(unsigned(ip_regs.rw_param_reg.extend_octrt_by));
output.delay_octrt_by := to_integer(unsigned(ip_regs.rw_param_reg.delay_octrt_by));
output.tracking_period_ms := to_integer(unsigned(ip_regs.rw_if_test.tracking_period_ms));
return output;
end function;
function pack_record (ip_regs : t_rw_regs) return t_mmi_pll_reconfig is
variable output : t_mmi_pll_reconfig;
begin
output.pll_phs_shft_phase_sel := ip_regs.rw_if_test.pll_phs_shft_phase_sel;
output.pll_phs_shft_up_wc := ip_regs.rw_if_test.pll_phs_shft_up_wc;
output.pll_phs_shft_dn_wc := ip_regs.rw_if_test.pll_phs_shft_dn_wc;
return output;
end function;
function pack_record (ip_regs : t_rw_regs) return t_admin_ctrl is
variable output : t_admin_ctrl := defaults;
begin
output.mr0 := ip_regs.mr_reg_a.mr0;
output.mr1 := ip_regs.mr_reg_a.mr1;
output.mr2 := ip_regs.mr_reg_b.mr2;
output.mr3 := ip_regs.mr_reg_b.mr3;
return output;
end function;
function pack_record (ip_regs : t_rw_regs) return t_mmi_ctrl is
variable output : t_mmi_ctrl := defaults;
begin
output.hl_css := to_t_hl_css_reg (ip_regs.rw_hl_css);
output.calibration_start := ip_regs.rw_hl_css.cal_start;
output.tracking_period_ms := to_integer(unsigned(ip_regs.rw_if_test.tracking_period_ms));
output.tracking_orvd_to_10ms := ip_regs.rw_if_test.tracking_units_are_10us;
return output;
end function;
-- >>>>>>>>>>>>>>>>>>>>>>>>>>
-- Helper functions :
-- >>>>>>>>>>>>>>>>>>>>>>>>>>
function to_t_hl_css_reg (hl_css : t_hl_css
) return t_hl_css_reg is
variable output : t_hl_css_reg := defaults;
begin
output.phy_initialise_dis := hl_css.hl_css(c_hl_css_reg_phy_initialise_dis_bit);
output.init_dram_dis := hl_css.hl_css(c_hl_css_reg_init_dram_dis_bit);
output.write_ihi_dis := hl_css.hl_css(c_hl_css_reg_write_ihi_dis_bit);
output.cal_dis := hl_css.hl_css(c_hl_css_reg_cal_dis_bit);
output.write_btp_dis := hl_css.hl_css(c_hl_css_reg_write_btp_dis_bit);
output.write_mtp_dis := hl_css.hl_css(c_hl_css_reg_write_mtp_dis_bit);
output.read_mtp_dis := hl_css.hl_css(c_hl_css_reg_read_mtp_dis_bit);
output.rrp_reset_dis := hl_css.hl_css(c_hl_css_reg_rrp_reset_dis_bit);
output.rrp_sweep_dis := hl_css.hl_css(c_hl_css_reg_rrp_sweep_dis_bit);
output.rrp_seek_dis := hl_css.hl_css(c_hl_css_reg_rrp_seek_dis_bit);
output.rdv_dis := hl_css.hl_css(c_hl_css_reg_rdv_dis_bit);
output.poa_dis := hl_css.hl_css(c_hl_css_reg_poa_dis_bit);
output.was_dis := hl_css.hl_css(c_hl_css_reg_was_dis_bit);
output.adv_rd_lat_dis := hl_css.hl_css(c_hl_css_reg_adv_rd_lat_dis_bit);
output.adv_wr_lat_dis := hl_css.hl_css(c_hl_css_reg_adv_wr_lat_dis_bit);
output.prep_customer_mr_setup_dis := hl_css.hl_css(c_hl_css_reg_prep_customer_mr_setup_dis_bit);
output.tracking_dis := hl_css.hl_css(c_hl_css_reg_tracking_dis_bit);
return output;
end function;
-- pack the ack seen record element into a std_logic_vector
function pack_ack_seen ( cal_stage_ack_seen : in t_cal_stage_ack_seen
) return std_logic_vector is
variable v_output: std_logic_vector(c_hl_ccs_num_stages-1 downto 0);
variable v_start : natural range 0 to c_hl_ccs_num_stages-1;
begin
v_output := (others => '0');
v_output(c_hl_css_reg_cal_dis_bit ) := cal_stage_ack_seen.cal;
v_output(c_hl_css_reg_phy_initialise_dis_bit ) := cal_stage_ack_seen.phy_initialise;
v_output(c_hl_css_reg_init_dram_dis_bit ) := cal_stage_ack_seen.init_dram;
v_output(c_hl_css_reg_write_ihi_dis_bit ) := cal_stage_ack_seen.write_ihi;
v_output(c_hl_css_reg_write_btp_dis_bit ) := cal_stage_ack_seen.write_btp;
v_output(c_hl_css_reg_write_mtp_dis_bit ) := cal_stage_ack_seen.write_mtp;
v_output(c_hl_css_reg_read_mtp_dis_bit ) := cal_stage_ack_seen.read_mtp;
v_output(c_hl_css_reg_rrp_reset_dis_bit ) := cal_stage_ack_seen.rrp_reset;
v_output(c_hl_css_reg_rrp_sweep_dis_bit ) := cal_stage_ack_seen.rrp_sweep;
v_output(c_hl_css_reg_rrp_seek_dis_bit ) := cal_stage_ack_seen.rrp_seek;
v_output(c_hl_css_reg_rdv_dis_bit ) := cal_stage_ack_seen.rdv;
v_output(c_hl_css_reg_poa_dis_bit ) := cal_stage_ack_seen.poa;
v_output(c_hl_css_reg_was_dis_bit ) := cal_stage_ack_seen.was;
v_output(c_hl_css_reg_adv_rd_lat_dis_bit ) := cal_stage_ack_seen.adv_rd_lat;
v_output(c_hl_css_reg_adv_wr_lat_dis_bit ) := cal_stage_ack_seen.adv_wr_lat;
v_output(c_hl_css_reg_prep_customer_mr_setup_dis_bit) := cal_stage_ack_seen.prep_customer_mr_setup;
v_output(c_hl_css_reg_tracking_dis_bit ) := cal_stage_ack_seen.tracking_setup;
return v_output;
end function;
-- reg encoding of current stage
function encode_current_stage (ctrl_cmd_id : t_ctrl_cmd_id
) return std_logic_vector is
variable output : std_logic_vector(7 downto 0);
begin
case ctrl_cmd_id is
when cmd_idle => output := X"00";
when cmd_phy_initialise => output := X"01";
when cmd_init_dram |
cmd_prog_cal_mr => output := X"02";
when cmd_write_ihi => output := X"03";
when cmd_write_btp => output := X"04";
when cmd_write_mtp => output := X"05";
when cmd_read_mtp => output := X"06";
when cmd_rrp_reset => output := X"07";
when cmd_rrp_sweep => output := X"08";
when cmd_rrp_seek => output := X"09";
when cmd_rdv => output := X"0A";
when cmd_poa => output := X"0B";
when cmd_was => output := X"0C";
when cmd_prep_adv_rd_lat => output := X"0D";
when cmd_prep_adv_wr_lat => output := X"0E";
when cmd_prep_customer_mr_setup => output := X"0F";
when cmd_tr_due => output := X"10";
when others =>
null;
report regs_report_prefix & "unknown cal command (" & t_ctrl_cmd_id'image(ctrl_cmd_id) & ") seen in encode_current_stage function" severity failure;
end case;
return output;
end function;
-- reg encoding of current active block
function encode_active_block (active_block : t_ctrl_active_block
) return std_logic_vector is
variable output : std_logic_vector(3 downto 0);
begin
case active_block is
when idle => output := X"0";
when admin => output := X"1";
when dgwb => output := X"2";
when dgrb => output := X"3";
when proc => output := X"4";
when setup => output := X"5";
when iram => output := X"6";
when others =>
output := X"7";
report regs_report_prefix & "unknown active_block seen in encode_active_block function" severity failure;
end case;
return output;
end function;
--
end ddr3_int_phy_alt_mem_phy_regs_pkg;
--
-- -----------------------------------------------------------------------------
-- Abstract : mmi block for the non-levelling AFI PHY sequencer
-- This is an optional block with an Avalon interface and status
-- register instantiations to enhance the debug capabilities of
-- the sequencer. The format of the block is:
-- a) an Avalon interface which supports different avalon and
-- sequencer clock sources
-- b) mmi status registers (which hold information about the
-- successof the calibration)
-- c) a read interface to the iram to enable debug through the
-- avalon interface.
-- -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
-- The record package (alt_mem_phy_record_pkg) is used to combine command and status signals
-- (into records) to be passed between sequencer blocks. It also contains type and record definitions
-- for the stages of DRAM memory calibration.
--
use work.ddr3_int_phy_alt_mem_phy_record_pkg.all;
--
entity ddr3_int_phy_alt_mem_phy_mmi is
generic (
-- physical interface width definitions
MEM_IF_DQS_WIDTH : natural;
MEM_IF_DWIDTH : natural;
MEM_IF_DM_WIDTH : natural;
MEM_IF_DQ_PER_DQS : natural;
MEM_IF_DQS_CAPTURE : natural;
DWIDTH_RATIO : natural;
CLOCK_INDEX_WIDTH : natural;
MEM_IF_CLK_PAIR_COUNT : natural;
MEM_IF_ADDR_WIDTH : natural;
MEM_IF_BANKADDR_WIDTH : natural;
MEM_IF_NUM_RANKS : natural;
ADV_LAT_WIDTH : natural;
RESYNCHRONISE_AVALON_DBG : natural;
AV_IF_ADDR_WIDTH : natural;
MEM_IF_MEMTYPE : string;
-- setup / algorithm information
NOM_DQS_PHASE_SETTING : natural;
SCAN_CLK_DIVIDE_BY : natural;
RDP_ADDR_WIDTH : natural;
PLL_STEPS_PER_CYCLE : natural;
IOE_PHASES_PER_TCK : natural;
IOE_DELAYS_PER_PHS : natural;
MEM_IF_CLK_PS : natural;
-- initial mode register settings
PHY_DEF_MR_1ST : std_logic_vector(15 downto 0);
PHY_DEF_MR_2ND : std_logic_vector(15 downto 0);
PHY_DEF_MR_3RD : std_logic_vector(15 downto 0);
PHY_DEF_MR_4TH : std_logic_vector(15 downto 0);
PRESET_RLAT : natural; -- read latency preset value
CAPABILITIES : natural; -- sequencer capabilities flags
USE_IRAM : std_logic; -- RFU
IRAM_AWIDTH : natural;
TRACKING_INTERVAL_IN_MS : natural;
READ_LAT_WIDTH : natural
);
port (
-- clk / reset
clk : in std_logic;
rst_n : in std_logic;
--synchronous Avalon debug interface (internally re-synchronised to input clock)
dbg_seq_clk : in std_logic;
dbg_seq_rst_n : in std_logic;
dbg_seq_addr : in std_logic_vector(AV_IF_ADDR_WIDTH -1 downto 0);
dbg_seq_wr : in std_logic;
dbg_seq_rd : in std_logic;
dbg_seq_cs : in std_logic;
dbg_seq_wr_data : in std_logic_vector(31 downto 0);
seq_dbg_rd_data : out std_logic_vector(31 downto 0);
seq_dbg_waitrequest : out std_logic;
-- mmi to admin interface
regs_admin_ctrl : out t_admin_ctrl;
admin_regs_status : in t_admin_stat;
trefi_failure : in std_logic;
-- mmi to iram interface
mmi_iram : out t_iram_ctrl;
mmi_iram_enable_writes : out std_logic;
iram_status : in t_iram_stat;
-- mmi to control interface
mmi_ctrl : out t_mmi_ctrl;
ctrl_mmi : in t_ctrl_mmi;
int_ac_1t : in std_logic;
invert_ac_1t : out std_logic;
-- global parameterisation record
parameterisation_rec : out t_algm_paramaterisation;
-- mmi pll interface
pll_mmi : in t_pll_mmi;
mmi_pll : out t_mmi_pll_reconfig;
-- codvw status signals
dgrb_mmi : in t_dgrb_mmi
);
end entity;
library work;
-- The registers package (alt_mem_phy_regs_pkg) is used to combine the definition of the
-- registers for the mmi status registers and functions/procedures applied to the registers
--
use work.ddr3_int_phy_alt_mem_phy_regs_pkg.all;
-- The iram address package (alt_mem_phy_iram_addr_pkg) is used to define the base addresses used
-- for iram writes during calibration
--
use work.ddr3_int_phy_alt_mem_phy_iram_addr_pkg.all;
-- The constant package (alt_mem_phy_constants_pkg) contains global 'constants' which are fixed
-- thoughout the sequencer and will not change (for constants which may change between sequencer
-- instances generics are used)
--
use work.ddr3_int_phy_alt_mem_phy_constants_pkg.all;
--
architecture struct of ddr3_int_phy_alt_mem_phy_mmi IS
-- maximum function
function max (a, b : natural) return natural is
begin
if a > b then
return a;
else
return b;
end if;
end function;
-- -------------------------------------------
-- constant definitions
-- -------------------------------------------
constant c_pll_360_sweeps : natural := rrp_pll_phase_mult(DWIDTH_RATIO, MEM_IF_DQS_CAPTURE);
constant c_response_lat : natural := 6;
constant c_codeword : std_logic_vector(31 downto 0) := c_mmi_access_codeword;
constant c_int_iram_start_size : natural := max(IRAM_AWIDTH, 4);
-- enable for ctrl state machine states
constant c_slv_hl_stage_enable : std_logic_vector(31 downto 0) := std_logic_vector(to_unsigned(CAPABILITIES, 32));
constant c_hl_stage_enable : std_logic_vector(c_hl_ccs_num_stages-1 downto 0) := c_slv_hl_stage_enable(c_hl_ccs_num_stages-1 downto 0);
-- a prefix for all report signals to identify phy and sequencer block
--
constant mmi_report_prefix : string := "ddr3_int_phy_alt_mem_phy_seq (mmi) : ";
-- --------------------------------------------
-- internal signals
-- --------------------------------------------
-- internal clock domain register interface signals
signal int_wdata : std_logic_vector(31 downto 0);
signal int_rdata : std_logic_vector(31 downto 0);
signal int_address : std_logic_vector(AV_IF_ADDR_WIDTH-1 downto 0);
signal int_read : std_logic;
signal int_cs : std_logic;
signal int_write : std_logic;
signal waitreq_int : std_logic;
-- register storage
-- contains:
-- read only (ro_regs)
-- read/write (rw_regs)
-- enable_writes flag
signal mmi_regs : t_mmi_regs := defaults;
signal mmi_rw_regs_initialised : std_logic;
-- this counter ensures that the mmi waits for c_response_lat clocks before
-- responding to a new Avalon request
signal waitreq_count : natural range 0 to 15;
signal waitreq_count_is_zero : std_logic;
-- register error signals
signal int_ac_1t_r : std_logic;
signal trefi_failure_r : std_logic;
-- iram ready - calibration complete and USE_IRAM high
signal iram_ready : std_logic;
begin -- architecture struct
-- the following signals are reserved for future use
invert_ac_1t <= '0';
-- --------------------------------------------------------------
-- generate for synchronous avalon interface
-- --------------------------------------------------------------
simply_registered_avalon : if RESYNCHRONISE_AVALON_DBG = 0 generate
begin
process (rst_n, clk)
begin
if rst_n = '0' then
int_wdata <= (others => '0');
int_address <= (others => '0');
int_read <= '0';
int_write <= '0';
int_cs <= '0';
elsif rising_edge(clk) then
int_wdata <= dbg_seq_wr_data;
int_address <= dbg_seq_addr;
int_read <= dbg_seq_rd;
int_write <= dbg_seq_wr;
int_cs <= dbg_seq_cs;
end if;
end process;
seq_dbg_rd_data <= int_rdata;
seq_dbg_waitrequest <= waitreq_int and (dbg_seq_rd or dbg_seq_wr) and dbg_seq_cs;
end generate simply_registered_avalon;
-- --------------------------------------------------------------
-- clock domain crossing for asynchronous mmi interface
-- --------------------------------------------------------------
re_synchronise_avalon : if RESYNCHRONISE_AVALON_DBG = 1 generate
--clock domain crossing signals
signal ccd_new_cmd : std_logic;
signal ccd_new_cmd_ack : std_logic;
signal ccd_cmd_done : std_logic;
signal ccd_cmd_done_ack : std_logic;
signal ccd_rd_data : std_logic_vector(dbg_seq_wr_data'range);
signal ccd_cmd_done_ack_t : std_logic;
signal ccd_cmd_done_ack_2t : std_logic;
signal ccd_cmd_done_ack_3t : std_logic;
signal ccd_cmd_done_t : std_logic;
signal ccd_cmd_done_2t : std_logic;
signal ccd_cmd_done_3t : std_logic;
signal ccd_new_cmd_t : std_logic;
signal ccd_new_cmd_2t : std_logic;
signal ccd_new_cmd_3t : std_logic;
signal ccd_new_cmd_ack_t : std_logic;
signal ccd_new_cmd_ack_2t : std_logic;
signal ccd_new_cmd_ack_3t : std_logic;
signal cmd_pending : std_logic;
signal seq_clk_waitreq_int : std_logic;
begin
process (rst_n, clk)
begin
if rst_n = '0' then
int_wdata <= (others => '0');
int_address <= (others => '0');
int_read <= '0';
int_write <= '0';
int_cs <= '0';
ccd_new_cmd_ack <= '0';
ccd_new_cmd_t <= '0';
ccd_new_cmd_2t <= '0';
ccd_new_cmd_3t <= '0';
elsif rising_edge(clk) then
ccd_new_cmd_t <= ccd_new_cmd;
ccd_new_cmd_2t <= ccd_new_cmd_t;
ccd_new_cmd_3t <= ccd_new_cmd_2t;
if ccd_new_cmd_3t = '0' and ccd_new_cmd_2t = '1' then
int_wdata <= dbg_seq_wr_data;
int_address <= dbg_seq_addr;
int_read <= dbg_seq_rd;
int_write <= dbg_seq_wr;
int_cs <= '1';
ccd_new_cmd_ack <= '1';
elsif ccd_new_cmd_3t = '1' and ccd_new_cmd_2t = '0' then
ccd_new_cmd_ack <= '0';
end if;
if int_cs = '1' and waitreq_int= '0' then
int_cs <= '0';
int_read <= '0';
int_write <= '0';
end if;
end if;
end process;
-- process to generate new cmd
process (dbg_seq_rst_n, dbg_seq_clk)
begin
if dbg_seq_rst_n = '0' then
ccd_new_cmd <= '0';
ccd_new_cmd_ack_t <= '0';
ccd_new_cmd_ack_2t <= '0';
ccd_new_cmd_ack_3t <= '0';
cmd_pending <= '0';
elsif rising_edge(dbg_seq_clk) then
ccd_new_cmd_ack_t <= ccd_new_cmd_ack;
ccd_new_cmd_ack_2t <= ccd_new_cmd_ack_t;
ccd_new_cmd_ack_3t <= ccd_new_cmd_ack_2t;
if ccd_new_cmd = '0' and dbg_seq_cs = '1' and cmd_pending = '0' then
ccd_new_cmd <= '1';
cmd_pending <= '1';
elsif ccd_new_cmd_ack_2t = '1' and ccd_new_cmd_ack_3t = '0' then
ccd_new_cmd <= '0';
end if;
-- use falling edge of cmd_done
if cmd_pending = '1' and ccd_cmd_done_2t = '0' and ccd_cmd_done_3t = '1' then
cmd_pending <= '0';
end if;
end if;
end process;
-- process to take read data back and transfer it across the clock domains
process (rst_n, clk)
begin
if rst_n = '0' then
ccd_cmd_done <= '0';
ccd_rd_data <= (others => '0');
ccd_cmd_done_ack_3t <= '0';
ccd_cmd_done_ack_2t <= '0';
ccd_cmd_done_ack_t <= '0';
elsif rising_edge(clk) then
if ccd_cmd_done_ack_2t = '1' and ccd_cmd_done_ack_3t = '0' then
ccd_cmd_done <= '0';
elsif waitreq_int = '0' then
ccd_cmd_done <= '1';
ccd_rd_data <= int_rdata;
end if;
ccd_cmd_done_ack_3t <= ccd_cmd_done_ack_2t;
ccd_cmd_done_ack_2t <= ccd_cmd_done_ack_t;
ccd_cmd_done_ack_t <= ccd_cmd_done_ack;
end if;
end process;
process (dbg_seq_rst_n, dbg_seq_clk)
begin
if dbg_seq_rst_n = '0' then
ccd_cmd_done_ack <= '0';
ccd_cmd_done_3t <= '0';
ccd_cmd_done_2t <= '0';
ccd_cmd_done_t <= '0';
seq_dbg_rd_data <= (others => '0');
seq_clk_waitreq_int <= '1';
elsif rising_edge(dbg_seq_clk) then
seq_clk_waitreq_int <= '1';
if ccd_cmd_done_2t = '1' and ccd_cmd_done_3t = '0' then
seq_clk_waitreq_int <= '0';
ccd_cmd_done_ack <= '1';
seq_dbg_rd_data <= ccd_rd_data; -- if read
elsif ccd_cmd_done_2t = '0' and ccd_cmd_done_3t = '1' then
ccd_cmd_done_ack <= '0';
end if;
ccd_cmd_done_3t <= ccd_cmd_done_2t;
ccd_cmd_done_2t <= ccd_cmd_done_t;
ccd_cmd_done_t <= ccd_cmd_done;
end if;
end process;
seq_dbg_waitrequest <= seq_clk_waitreq_int and (dbg_seq_rd or dbg_seq_wr) and dbg_seq_cs;
end generate re_synchronise_avalon;
-- register some inputs for speed.
process (rst_n, clk)
begin
if rst_n = '0' then
int_ac_1t_r <= '0';
trefi_failure_r <= '0';
elsif rising_edge(clk) then
int_ac_1t_r <= int_ac_1t;
trefi_failure_r <= trefi_failure;
end if;
end process;
-- mmi not able to write to iram in current instance of mmi block
mmi_iram_enable_writes <= '0';
-- check if iram ready
process (rst_n, clk)
begin
if rst_n = '0' then
iram_ready <= '0';
elsif rising_edge(clk) then
if USE_IRAM = '0' then
iram_ready <= '0';
else
if ctrl_mmi.ctrl_calibration_success = '1' or ctrl_mmi.ctrl_calibration_fail = '1' then
iram_ready <= '1';
else
iram_ready <= '0';
end if;
end if;
end if;
end process;
-- --------------------------------------------------------------
-- single registered process for mmi access.
-- --------------------------------------------------------------
process (rst_n, clk)
variable v_mmi_regs : t_mmi_regs;
begin
if rst_n = '0' then
mmi_regs <= defaults;
mmi_rw_regs_initialised <= '0';
-- this register records whether the c_codeword has been written to address 0x0001
-- once it has, then other writes are accepted.
mmi_regs.enable_writes <= '0';
int_rdata <= (others => '0');
waitreq_int <= '1';
-- clear wait request counter
waitreq_count <= 0;
waitreq_count_is_zero <= '1';
-- iram interface defaults
mmi_iram <= defaults;
elsif rising_edge(clk) then
-- default assignment
waitreq_int <= '1';
write_clear(mmi_regs.rw_regs);
-- only initialise rw_regs once after hard reset
if mmi_rw_regs_initialised = '0' then
mmi_rw_regs_initialised <= '1';
--reset all read/write regs and read path ouput registers and apply default MRS Settings.
mmi_regs.rw_regs <= defaults(PHY_DEF_MR_1ST,
PHY_DEF_MR_2ND,
PHY_DEF_MR_3RD,
PHY_DEF_MR_4TH,
NOM_DQS_PHASE_SETTING,
PLL_STEPS_PER_CYCLE,
c_pll_360_sweeps, -- number of times 360 degrees is swept
TRACKING_INTERVAL_IN_MS,
c_hl_stage_enable);
end if;
-- bit packing input data structures into the ro_regs structure, for reading
mmi_regs.ro_regs <= defaults(dgrb_mmi,
ctrl_mmi,
pll_mmi,
mmi_regs.rw_regs.rw_if_test,
USE_IRAM,
MEM_IF_DQS_CAPTURE,
int_ac_1t_r,
trefi_failure_r,
iram_status,
IRAM_AWIDTH);
-- write has priority over read
if int_write = '1' and int_cs = '1' and waitreq_count_is_zero = '1' and waitreq_int = '1' then
-- mmi local register write
if to_integer(unsigned(int_address(int_address'high downto 4))) = 0 then
v_mmi_regs := mmi_regs;
write(v_mmi_regs, to_integer(unsigned(int_address(3 downto 0))), int_wdata);
if mmi_regs.enable_writes = '1' then
v_mmi_regs.rw_regs.rw_hl_css.hl_css := c_hl_stage_enable or v_mmi_regs.rw_regs.rw_hl_css.hl_css;
end if;
mmi_regs <= v_mmi_regs;
-- handshake for safe transactions
waitreq_int <= '0';
waitreq_count <= c_response_lat;
-- iram write just handshake back (no write supported)
else
waitreq_int <= '0';
waitreq_count <= c_response_lat;
end if;
elsif int_read = '1' and int_cs = '1' and waitreq_count_is_zero = '1' and waitreq_int = '1' then
-- mmi local register read
if to_integer(unsigned(int_address(int_address'high downto 4))) = 0 then
int_rdata <= read(mmi_regs, to_integer(unsigned(int_address(3 downto 0))));
waitreq_count <= c_response_lat;
waitreq_int <= '0'; -- acknowledge read command regardless.
-- iram being addressed
elsif to_integer(unsigned(int_address(int_address'high downto c_int_iram_start_size))) = 1
and iram_ready = '1'
then
mmi_iram.read <= '1';
mmi_iram.addr <= to_integer(unsigned(int_address(IRAM_AWIDTH -1 downto 0)));
if iram_status.done = '1' then
waitreq_int <= '0';
mmi_iram.read <= '0';
waitreq_count <= c_response_lat;
int_rdata <= iram_status.rdata;
end if;
else -- respond and keep the interface from hanging
int_rdata <= x"DEADBEEF";
waitreq_int <= '0';
waitreq_count <= c_response_lat;
end if;
elsif waitreq_count /= 0 then
waitreq_count <= waitreq_count -1;
-- if performing a write, set back to defaults. If not, default anyway
mmi_iram <= defaults;
end if;
if waitreq_count = 1 or waitreq_count = 0 then
waitreq_count_is_zero <= '1'; -- as it will be next clock cycle
else
waitreq_count_is_zero <= '0';
end if;
-- supply iram read data when ready
if iram_status.done = '1' then
int_rdata <= iram_status.rdata;
end if;
end if;
end process;
-- pack the registers into the output data structures
regs_admin_ctrl <= pack_record(mmi_regs.rw_regs);
parameterisation_rec <= pack_record(mmi_regs.rw_regs);
mmi_pll <= pack_record(mmi_regs.rw_regs);
mmi_ctrl <= pack_record(mmi_regs.rw_regs);
end architecture struct;
--
-- -----------------------------------------------------------------------------
-- Abstract : admin block for the non-levelling AFI PHY sequencer
-- The admin block supports the autonomy of the sequencer from
-- the memory interface controller. In this task admin handles
-- memory initialisation (incl. the setting of mode registers)
-- and memory refresh, bank activation and pre-charge commands
-- (during memory interface calibration). Once calibration is
-- complete admin is 'idle' and control of the memory device is
-- passed to the users chosen memory interface controller. The
-- supported memory types are exclusively DDR, DDR2 and DDR3.
-- -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
-- The record package (alt_mem_phy_record_pkg) is used to combine command and status signals
-- (into records) to be passed between sequencer blocks. It also contains type and record definitions
-- for the stages of DRAM memory calibration.
--
use work.ddr3_int_phy_alt_mem_phy_record_pkg.all;
-- The address and command package (alt_mem_phy_addr_cmd_pkg) is used to combine DRAM address
-- and command signals in one record and unify the functions operating on this record.
--
use work.ddr3_int_phy_alt_mem_phy_addr_cmd_pkg.all;
--
entity ddr3_int_phy_alt_mem_phy_admin is
generic (
-- physical interface width definitions
MEM_IF_DQS_WIDTH : natural;
MEM_IF_DWIDTH : natural;
MEM_IF_DM_WIDTH : natural;
MEM_IF_DQ_PER_DQS : natural;
DWIDTH_RATIO : natural;
CLOCK_INDEX_WIDTH : natural;
MEM_IF_CLK_PAIR_COUNT : natural;
MEM_IF_ADDR_WIDTH : natural;
MEM_IF_BANKADDR_WIDTH : natural;
MEM_IF_NUM_RANKS : natural;
ADV_LAT_WIDTH : natural;
MEM_IF_DQSN_EN : natural;
MEM_IF_MEMTYPE : string;
-- calibration address information
MEM_IF_CAL_BANK : natural; -- Bank to which calibration data is written
MEM_IF_CAL_BASE_ROW : natural;
GENERATE_ADDITIONAL_DBG_RTL : natural;
NON_OP_EVAL_MD : string; -- non_operational evaluation mode (used when GENERATE_ADDITIONAL_DBG_RTL = 1)
-- timing parameters
MEM_IF_CLK_PS : natural;
TINIT_TCK : natural; -- initial delay
TINIT_RST : natural -- used for DDR3 device support
);
port (
-- clk / reset
clk : in std_logic;
rst_n : in std_logic;
-- the 2 signals below are unused for non-levelled sequencer (maintained for equivalent interface to levelled sequencer)
mem_ac_swapped_ranks : in std_logic_vector(MEM_IF_NUM_RANKS - 1 downto 0);
ctl_cal_byte_lanes : in std_logic_vector(MEM_IF_NUM_RANKS * MEM_IF_DQS_WIDTH - 1 downto 0);
-- addr/cmd interface
seq_ac : out t_addr_cmd_vector(0 to (DWIDTH_RATIO/2)-1);
seq_ac_sel : out std_logic;
-- determined from MR settings
enable_odt : out std_logic;
-- interface to the mmi block
regs_admin_ctrl_rec : in t_admin_ctrl;
admin_regs_status_rec : out t_admin_stat;
trefi_failure : out std_logic;
-- interface to the ctrl block
ctrl_admin : in t_ctrl_command;
admin_ctrl : out t_ctrl_stat;
-- interface with dgrb/dgwb blocks
ac_access_req : in std_logic;
ac_access_gnt : out std_logic;
-- calibration status signals (from ctrl block)
cal_fail : in std_logic;
cal_success : in std_logic;
-- recalibrate request issued
ctl_recalibrate_req : in std_logic
);
end entity;
library work;
-- The constant package (alt_mem_phy_constants_pkg) contains global 'constants' which are fixed
-- thoughout the sequencer and will not change (for constants which may change between sequencer
-- instances generics are used)
--
use work.ddr3_int_phy_alt_mem_phy_constants_pkg.all;
--
architecture struct of ddr3_int_phy_alt_mem_phy_admin is
constant c_max_mode_reg_index : natural := 12;
-- timing below is safe for range 80-400MHz operation - taken from worst case DDR2 (JEDEC JESD79-2E) / DDR3 (JESD79-3B)
-- Note: timings account for worst case use for both full rate and half rate ALTMEMPHY interfaces
constant c_init_prech_delay : natural := 162; -- precharge delay (360ns = tRFC+10ns) (TXPR for DDR3)
constant c_trp_in_clks : natural := 8; -- set equal to trp / tck (trp = 15ns)
constant c_tmrd_in_clks : natural := 4; -- maximum 4 clock cycles (DDR3)
constant c_tmod_in_clks : natural := 8; -- ODT update from MRS command (tmod = 12ns (DDR2))
constant c_trrd_min_in_clks : natural := 4; -- minimum clk cycles between bank activate cmds (10ns)
constant c_trcd_min_in_clks : natural := 8; -- minimum bank activate to read/write cmd (15ns)
-- the 2 constants below are parameterised to MEM_IF_CLK_PS due to the large range of possible clock frequency
constant c_trfc_min_in_clks : natural := (350000/MEM_IF_CLK_PS)/(DWIDTH_RATIO/2) + 2; -- refresh-refresh timing (worst case trfc = 350 ns (DDR3))
constant c_trefi_min_in_clks : natural := (3900000/MEM_IF_CLK_PS)/(DWIDTH_RATIO/2) - 2; -- average refresh interval worst case trefi = 3.9 us (industrial grade devices)
constant c_max_num_stacked_refreshes : natural := 8; -- max no. of stacked refreshes allowed
constant c_max_wait_value : natural := 4; -- delay before moving from s_idle to s_refresh_state
-- DDR3 specific:
constant c_zq_init_duration_clks : natural := 514; -- full rate (worst case) cycle count for tZQCL init
constant c_tzqcs : natural := 66; -- number of full rate clock cycles
-- below is a record which is used to parameterise the address and command signals (addr_cmd) used in this block
constant c_seq_addr_cmd_config : t_addr_cmd_config_rec := set_config_rec(MEM_IF_ADDR_WIDTH, MEM_IF_BANKADDR_WIDTH, MEM_IF_NUM_RANKS, DWIDTH_RATIO, MEM_IF_MEMTYPE);
-- a prefix for all report signals to identify phy and sequencer block
--
constant admin_report_prefix : string := "ddr3_int_phy_alt_mem_phy_seq (admin) : ";
-- state type for admin_state (main state machine of admin block)
type t_admin_state is
(
s_reset, -- reset state
s_run_init_seq, -- run the initialisation sequence (up to but not including MR setting)
s_program_cal_mrs, -- program the mode registers ready for calibration (this is the user settings
-- with some overloads and extra init functionality)
s_idle, -- idle (i.e. maintaining refresh to max)
s_topup_refresh, -- make sure refreshes are maxed out before going on.
s_topup_refresh_done, -- wait for tRFC after refresh command
s_zq_cal_short, -- ZQCAL short command (issued prior to activate) - DDR3 only
s_access_act, -- activate
s_access, -- dgrb, dgwb accesses,
s_access_precharge, -- precharge all memory banks
s_prog_user_mrs, -- program user mode register settings
s_dummy_wait, -- wait before going to s_refresh state
s_refresh, -- issue a memory refresh command
s_refresh_done, -- wait for trfc after refresh command
s_non_operational -- special debug state to toggle interface if calibration fails
);
signal state : t_admin_state; -- admin block state machine
-- state type for ac_state
type t_ac_state is
( s_0 ,
s_1 ,
s_2 ,
s_3 ,
s_4 ,
s_5 ,
s_6 ,
s_7 ,
s_8 ,
s_9 ,
s_10,
s_11,
s_12,
s_13,
s_14);
-- enforce one-hot fsm encoding
attribute syn_encoding : string;
attribute syn_encoding of t_ac_state : TYPE is "one-hot";
signal ac_state : t_ac_state; -- state machine for sub-states of t_admin_state states
signal stage_counter : natural range 0 to 2**18 - 1; -- counter to support memory timing delays
signal stage_counter_zero : std_logic;
signal addr_cmd : t_addr_cmd_vector(0 to (DWIDTH_RATIO/2)-1); -- internal copy of output DRAM addr/cmd signals
signal mem_init_complete : std_logic; -- signifies memory initialisation is complete
signal cal_complete : std_logic; -- calibration complete (equals: cal_success OR cal_fail)
signal int_mr0 : std_logic_vector(regs_admin_ctrl_rec.mr0'range); -- an internal copy of mode register settings
signal int_mr1 : std_logic_vector(regs_admin_ctrl_rec.mr0'range);
signal int_mr2 : std_logic_vector(regs_admin_ctrl_rec.mr0'range);
signal int_mr3 : std_logic_vector(regs_admin_ctrl_rec.mr0'range);
signal refresh_count : natural range c_trefi_min_in_clks downto 0; -- determine when refresh is due
signal refresh_due : std_logic; -- need to do a refresh now
signal refresh_done : std_logic; -- pulse when refresh complete
signal num_stacked_refreshes : natural range 0 to c_max_num_stacked_refreshes - 1; -- can stack upto 8 refreshes (for DDR2)
signal refreshes_maxed : std_logic; -- signal refreshes are maxed out
signal initial_refresh_issued : std_logic; -- to start the refresh counter off
signal ctrl_rec : t_ctrl_command;
-- last state logic
signal command_started : std_logic; -- provides a pulse when admin starts processing a command
signal command_done : std_logic; -- provides a pulse when admin completes processing a command is completed
signal finished_state : std_logic; -- finished current t_admin_state state
signal admin_req_extended : std_logic; -- keep requests for this block asserted until it is an ack is asserted
signal current_cs : natural range 0 to MEM_IF_NUM_RANKS - 1; -- which chip select being programmed at this instance
signal per_cs_init_seen : std_logic_vector(MEM_IF_NUM_RANKS - 1 downto 0);
-- some signals to enable non_operational debug (optimised away if GENERATE_ADDITIONAL_DBG_RTL = 0)
signal nop_toggle_signal : t_addr_cmd_signals;
signal nop_toggle_pin : natural range 0 to MEM_IF_ADDR_WIDTH - 1; -- track which pin in a signal to toggle
signal nop_toggle_value : std_logic;
begin -- architecture struct
-- concurrent assignment of internal addr_cmd to output port seq_ac
process (addr_cmd)
begin
seq_ac <= addr_cmd;
end process;
-- generate calibration complete signal
process (cal_success, cal_fail)
begin
cal_complete <= cal_success or cal_fail;
end process;
-- register the control command record
process (clk, rst_n)
begin
if rst_n = '0' then
ctrl_rec <= defaults;
elsif rising_edge(clk) then
ctrl_rec <= ctrl_admin;
end if;
end process;
-- extend the admin block request until ack is asserted
process (clk, rst_n)
begin
if rst_n = '0' then
admin_req_extended <= '0';
elsif rising_edge(clk) then
if ( (ctrl_rec.command_req = '1') and ( curr_active_block(ctrl_rec.command) = admin) ) then
admin_req_extended <= '1';
elsif command_started = '1' then -- this is effectively a copy of command_ack generation
admin_req_extended <= '0';
end if;
end if;
end process;
-- generate the current_cs signal to track which cs accessed by PHY at any instance
process (clk, rst_n)
begin
if rst_n = '0' then
current_cs <= 0;
elsif rising_edge(clk) then
if ctrl_rec.command_req = '1' then
current_cs <= ctrl_rec.command_op.current_cs;
end if;
end if;
end process;
-- -----------------------------------------------------------------------------
-- refresh logic: DDR/DDR2/DDR3 allows upto 8 refreshes to be "stacked" or queued up.
-- In the idle state, will ensure refreshes are issued when necessary. Then,
-- when an access_request is received, 7 topup refreshes will be done to max out
-- the number of queued refreshes. That way, we know we have the maximum time
-- available before another refresh is due.
-- -----------------------------------------------------------------------------
-- initial_refresh_issued flag: used to sync refresh_count
process (clk, rst_n)
begin
if rst_n = '0' then
initial_refresh_issued <= '0';
elsif rising_edge(clk) then
if cal_complete = '1' then
initial_refresh_issued <= '0';
else
if state = s_refresh_done or
state = s_topup_refresh_done then
initial_refresh_issued <= '1';
end if;
end if;
end if;
end process;
-- refresh timer: used to work out when a refresh is due
process (clk, rst_n)
begin
if rst_n = '0' then
refresh_count <= c_trefi_min_in_clks;
elsif rising_edge(clk) then
if cal_complete = '1' then
refresh_count <= c_trefi_min_in_clks;
else
if refresh_count = 0 or
initial_refresh_issued = '0' or
(refreshes_maxed = '1' and refresh_done = '1') then -- if refresh issued when already maxed
refresh_count <= c_trefi_min_in_clks;
else
refresh_count <= refresh_count - 1;
end if;
end if;
end if;
end process;
-- refresh_due generation: 1 cycle pulse to indicate that c_trefi_min_in_clks has elapsed, and
-- therefore a refresh is due
process (clk, rst_n)
begin
if rst_n = '0' then
refresh_due <= '0';
elsif rising_edge(clk) then
if refresh_count = 0 and cal_complete = '0' then
refresh_due <= '1';
else
refresh_due <= '0';
end if;
end if;
end process;
-- counter to keep track of number of refreshes "stacked". NB: Up to 8
-- refreshes can be stacked.
process (clk, rst_n)
begin
if rst_n = '0' then
num_stacked_refreshes <= 0;
trefi_failure <= '0'; -- default no trefi failure
elsif rising_edge (clk) then
if state = s_reset then
trefi_failure <= '0'; -- default no trefi failure (in restart)
end if;
if cal_complete = '1' then
num_stacked_refreshes <= 0;
else
if refresh_due = '1' and num_stacked_refreshes /= 0 then
num_stacked_refreshes <= num_stacked_refreshes - 1;
elsif refresh_done = '1' and num_stacked_refreshes /= c_max_num_stacked_refreshes - 1 then
num_stacked_refreshes <= num_stacked_refreshes + 1;
end if;
-- debug message if stacked refreshes are depleted and refresh is due
if refresh_due = '1' and num_stacked_refreshes = 0 and initial_refresh_issued = '1' then
report admin_report_prefix & "error refresh is due and num_stacked_refreshes is zero" severity error;
trefi_failure <= '1'; -- persist
end if;
end if;
end if;
end process;
-- generate signal to state if refreshes are maxed out
process (clk, rst_n)
begin
if rst_n = '0' then
refreshes_maxed <= '0';
elsif rising_edge (clk) then
if num_stacked_refreshes < c_max_num_stacked_refreshes - 1 then
refreshes_maxed <= '0';
else
refreshes_maxed <= '1';
end if;
end if;
end process;
-- ----------------------------------------------------
-- Mode register selection
-- -----------------------------------------------------
int_mr0(regs_admin_ctrl_rec.mr0'range) <= regs_admin_ctrl_rec.mr0;
int_mr1(regs_admin_ctrl_rec.mr1'range) <= regs_admin_ctrl_rec.mr1;
int_mr2(regs_admin_ctrl_rec.mr2'range) <= regs_admin_ctrl_rec.mr2;
int_mr3(regs_admin_ctrl_rec.mr3'range) <= regs_admin_ctrl_rec.mr3;
-- -------------------------------------------------------
-- State machine
-- -------------------------------------------------------
process(rst_n, clk)
begin
if rst_n = '0' then
state <= s_reset;
command_done <= '0';
command_started <= '0';
elsif rising_edge(clk) then
-- Last state logic
command_done <= '0';
command_started <= '0';
case state is
when s_reset |
s_non_operational =>
if ctrl_rec.command = cmd_init_dram and admin_req_extended = '1' then
state <= s_run_init_seq;
command_started <= '1';
end if;
when s_run_init_seq =>
if finished_state = '1' then
state <= s_idle;
command_done <= '1';
end if;
when s_program_cal_mrs =>
if finished_state = '1' then
if refreshes_maxed = '0' and mem_init_complete = '1' then -- only refresh if all ranks initialised
state <= s_topup_refresh;
else
state <= s_idle;
end if;
command_done <= '1';
end if;
when s_idle =>
if ac_access_req = '1' then
state <= s_topup_refresh;
elsif ctrl_rec.command = cmd_init_dram and admin_req_extended = '1' then -- start initialisation sequence
state <= s_run_init_seq;
command_started <= '1';
elsif ctrl_rec.command = cmd_prog_cal_mr and admin_req_extended = '1' then -- program mode registers (used for >1 chip select)
state <= s_program_cal_mrs;
command_started <= '1';
-- always enter s_prog_user_mrs via topup refresh
elsif ctrl_rec.command = cmd_prep_customer_mr_setup and admin_req_extended = '1' then
state <= s_topup_refresh;
elsif refreshes_maxed = '0' and mem_init_complete = '1' then -- only refresh once all ranks initialised
state <= s_dummy_wait;
end if;
when s_dummy_wait =>
if finished_state = '1' then
state <= s_refresh;
end if;
when s_topup_refresh =>
if finished_state = '1' then
state <= s_topup_refresh_done;
end if;
when s_topup_refresh_done =>
if finished_state = '1' then -- to ensure trfc is not violated
if refreshes_maxed = '0' then
state <= s_topup_refresh;
elsif ctrl_rec.command = cmd_prep_customer_mr_setup and admin_req_extended = '1' then
state <= s_prog_user_mrs;
command_started <= '1';
elsif ac_access_req = '1' then
if MEM_IF_MEMTYPE = "DDR3" then
state <= s_zq_cal_short;
else
state <= s_access_act;
end if;
else
state <= s_idle;
end if;
end if;
when s_zq_cal_short => -- DDR3 only
if finished_state = '1' then
state <= s_access_act;
end if;
when s_access_act =>
if finished_state = '1' then
state <= s_access;
end if;
when s_access =>
if ac_access_req = '0' then
state <= s_access_precharge;
end if;
when s_access_precharge =>
-- ensure precharge all timer has elapsed.
if finished_state = '1' then
state <= s_idle;
end if;
when s_prog_user_mrs =>
if finished_state = '1' then
state <= s_idle;
command_done <= '1';
end if;
when s_refresh =>
if finished_state = '1' then
state <= s_refresh_done;
end if;
when s_refresh_done =>
if finished_state = '1' then -- to ensure trfc is not violated
if refreshes_maxed = '0' then
state <= s_refresh;
else
state <= s_idle;
end if;
end if;
when others =>
state <= s_reset;
end case;
if cal_complete = '1' then
state <= s_idle;
if GENERATE_ADDITIONAL_DBG_RTL = 1 and cal_success = '0' then
state <= s_non_operational; -- if calibration failed and debug enabled then toggle pins in pre-defined pattern
end if;
end if;
-- if recalibrating then put admin in reset state to
-- avoid issuing refresh commands when not needed
if ctl_recalibrate_req = '1' then
state <= s_reset;
end if;
end if;
end process;
-- --------------------------------------------------
-- process to generate initialisation complete
-- --------------------------------------------------
process (rst_n, clk)
begin
if rst_n = '0' then
mem_init_complete <= '0';
elsif rising_edge(clk) then
if to_integer(unsigned(per_cs_init_seen)) = 2**MEM_IF_NUM_RANKS - 1 then
mem_init_complete <= '1';
else
mem_init_complete <= '0';
end if;
end if;
end process;
-- --------------------------------------------------
-- process to generate addr/cmd.
-- --------------------------------------------------
process(rst_n, clk)
variable v_mr_overload : std_logic_vector(regs_admin_ctrl_rec.mr0'range);
-- required for non_operational state only
variable v_nop_ac_0 : t_addr_cmd_vector(0 to (DWIDTH_RATIO/2)-1);
variable v_nop_ac_1 : t_addr_cmd_vector(0 to (DWIDTH_RATIO/2)-1);
begin
if rst_n = '0' then
ac_state <= s_0;
stage_counter <= 0;
stage_counter_zero <= '1';
finished_state <= '0';
seq_ac_sel <= '1';
refresh_done <= '0';
per_cs_init_seen <= (others => '0');
addr_cmd <= int_pup_reset(c_seq_addr_cmd_config);
if GENERATE_ADDITIONAL_DBG_RTL = 1 then
nop_toggle_signal <= addr;
nop_toggle_pin <= 0;
nop_toggle_value <= '0';
end if;
elsif rising_edge(clk) then
finished_state <= '0';
refresh_done <= '0';
-- address / command path control
-- if seq_ac_sel = 1 then sequencer has control of a/c
-- if seq_ac_sel = 0 then memory controller has control of a/c
seq_ac_sel <= '1';
if cal_complete = '1' then
if cal_success = '1' or
GENERATE_ADDITIONAL_DBG_RTL = 0 then -- hand over interface if cal successful or no debug enabled
seq_ac_sel <= '0';
end if;
end if;
-- if recalibration request then take control of a/c path
if ctl_recalibrate_req = '1' then
seq_ac_sel <= '1';
end if;
if state = s_reset then
addr_cmd <= reset(c_seq_addr_cmd_config);
stage_counter <= 0;
elsif state /= s_run_init_seq and
state /= s_non_operational then
addr_cmd <= deselect(c_seq_addr_cmd_config, -- configuration
addr_cmd); -- previous value
end if;
if (stage_counter = 1 or stage_counter = 0) then
stage_counter_zero <= '1';
else
stage_counter_zero <= '0';
end if;
if stage_counter_zero /= '1' and state /= s_reset then
stage_counter <= stage_counter -1;
else
stage_counter_zero <= '0';
case state is
when s_run_init_seq =>
per_cs_init_seen <= (others => '0'); -- per cs test
if MEM_IF_MEMTYPE = "DDR" or MEM_IF_MEMTYPE = "DDR2" then
case ac_state is
-- JEDEC (JESD79-2E) stage c
when s_0 to s_9 =>
ac_state <= t_ac_state'succ(ac_state);
stage_counter <= (TINIT_TCK/10)+1;
addr_cmd <= maintain_pd_or_sr(c_seq_addr_cmd_config,
deselect(c_seq_addr_cmd_config, addr_cmd),
2**MEM_IF_NUM_RANKS -1);
-- JEDEC (JESD79-2E) stage d
when s_10 =>
ac_state <= s_11;
stage_counter <= c_init_prech_delay;
addr_cmd <= deselect(c_seq_addr_cmd_config, -- configuration
addr_cmd); -- previous value
when s_11 =>
ac_state <= s_0;
stage_counter <= 1;
finished_state <= '1';
-- finish sequence by going into s_program_cal_mrs state
when others =>
ac_state <= s_0;
end case;
elsif MEM_IF_MEMTYPE = "DDR3" then -- DDR3 specific initialisation sequence
case ac_state is
when s_0 =>
ac_state <= s_1;
stage_counter <= TINIT_RST + 1;
addr_cmd <= reset(c_seq_addr_cmd_config);
when s_1 to s_10 =>
ac_state <= t_ac_state'succ(ac_state);
stage_counter <= (TINIT_TCK/10) + 1;
addr_cmd <= maintain_pd_or_sr(c_seq_addr_cmd_config,
deselect(c_seq_addr_cmd_config, addr_cmd),
2**MEM_IF_NUM_RANKS -1);
when s_11 =>
ac_state <= s_12;
stage_counter <= c_init_prech_delay;
addr_cmd <= deselect(c_seq_addr_cmd_config, addr_cmd);
when s_12 =>
ac_state <= s_0;
stage_counter <= 1;
finished_state <= '1';
-- finish sequence by going into s_program_cal_mrs state
when others =>
ac_state <= s_0;
end case;
else
report admin_report_prefix & "unsupported memory type specified" severity error;
end if;
-- end of initialisation sequence
when s_program_cal_mrs =>
if MEM_IF_MEMTYPE = "DDR2" then -- DDR2 style mode register settings
case ac_state is
when s_0 =>
ac_state <= s_1;
stage_counter <= 1;
addr_cmd <= deselect(c_seq_addr_cmd_config, -- configuration
addr_cmd); -- previous value
-- JEDEC (JESD79-2E) stage d
when s_1 =>
ac_state <= s_2;
stage_counter <= c_trp_in_clks;
addr_cmd <= precharge_all(c_seq_addr_cmd_config, -- configuration
2**current_cs); -- rank
-- JEDEC (JESD79-2E) stage e
when s_2 =>
ac_state <= s_3;
stage_counter <= c_tmrd_in_clks;
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
2, -- mode register number
int_mr2(c_max_mode_reg_index downto 0), -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
-- JEDEC (JESD79-2E) stage f
when s_3 =>
ac_state <= s_4;
stage_counter <= c_tmrd_in_clks;
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
3, -- mode register number
int_mr3(c_max_mode_reg_index downto 0), -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
-- JEDEC (JESD79-2E) stage g
when s_4 =>
ac_state <= s_5;
stage_counter <= c_tmrd_in_clks;
v_mr_overload := int_mr1(c_max_mode_reg_index downto 0);
v_mr_overload(0) := '0'; -- override DLL enable
v_mr_overload(9 downto 7) := "000"; -- required in JESD79-2E (but not in JESD79-2B)
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
1, -- mode register number
v_mr_overload , -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
-- JEDEC (JESD79-2E) stage h
when s_5 =>
ac_state <= s_6;
stage_counter <= c_tmod_in_clks;
addr_cmd <= dll_reset(c_seq_addr_cmd_config, -- configuration
int_mr0(c_max_mode_reg_index downto 0), -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
-- JEDEC (JESD79-2E) stage i
when s_6 =>
ac_state <= s_7;
stage_counter <= c_trp_in_clks;
addr_cmd <= precharge_all(c_seq_addr_cmd_config, -- configuration
2**MEM_IF_NUM_RANKS - 1); -- rank(s)
-- JEDEC (JESD79-2E) stage j
when s_7 =>
ac_state <= s_8;
stage_counter <= c_trfc_min_in_clks;
addr_cmd <= refresh(c_seq_addr_cmd_config, -- configuration
addr_cmd, -- previous value
2**current_cs); -- rank
-- JEDEC (JESD79-2E) stage j - second refresh
when s_8 =>
ac_state <= s_9;
stage_counter <= c_trfc_min_in_clks;
addr_cmd <= refresh(c_seq_addr_cmd_config, -- configuration
addr_cmd, -- previous value
2**current_cs); -- rank
-- JEDEC (JESD79-2E) stage k
when s_9 =>
ac_state <= s_10;
stage_counter <= c_tmrd_in_clks;
v_mr_overload := int_mr0(c_max_mode_reg_index downto 3) & "010"; -- override to burst length 4
v_mr_overload(8) := '0'; -- required in JESD79-2E
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
0, -- mode register number
v_mr_overload, -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
-- JEDEC (JESD79-2E) stage l - wait 200 cycles
when s_10 =>
ac_state <= s_11;
stage_counter <= 200;
addr_cmd <= deselect(c_seq_addr_cmd_config, -- configuration
addr_cmd); -- previous value
-- JEDEC (JESD79-2E) stage l - OCD default
when s_11 =>
ac_state <= s_12;
stage_counter <= c_tmrd_in_clks;
v_mr_overload := int_mr1(c_max_mode_reg_index downto 0);
v_mr_overload(9 downto 7) := "111"; -- OCD calibration default (i.e. OCD unused)
v_mr_overload(0) := '0'; -- override for DLL enable
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
1, -- mode register number
v_mr_overload , -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
-- JEDEC (JESD79-2E) stage l - OCD cal exit
when s_12 =>
ac_state <= s_13;
stage_counter <= c_tmod_in_clks;
v_mr_overload := int_mr1(c_max_mode_reg_index downto 0);
v_mr_overload(9 downto 7) := "000"; -- OCD calibration exit
v_mr_overload(0) := '0'; -- override for DLL enable
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
1, -- mode register number
v_mr_overload , -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
per_cs_init_seen(current_cs) <= '1';
-- JEDEC (JESD79-2E) stage m - cal finished
when s_13 =>
ac_state <= s_0;
stage_counter <= 1;
finished_state <= '1';
when others =>
null;
end case;
elsif MEM_IF_MEMTYPE = "DDR" then -- DDR style mode register setting following JEDEC (JESD79E)
case ac_state is
when s_0 =>
ac_state <= s_1;
stage_counter <= 1;
addr_cmd <= deselect(c_seq_addr_cmd_config, -- configuration
addr_cmd); -- previous value
when s_1 =>
ac_state <= s_2;
stage_counter <= c_trp_in_clks;
addr_cmd <= precharge_all(c_seq_addr_cmd_config, -- configuration
2**current_cs); -- rank(s)
when s_2 =>
ac_state <= s_3;
stage_counter <= c_tmrd_in_clks;
v_mr_overload := int_mr1(c_max_mode_reg_index downto 0);
v_mr_overload(0) := '0'; -- override DLL enable
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
1, -- mode register number
v_mr_overload , -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
when s_3 =>
ac_state <= s_4;
stage_counter <= c_tmod_in_clks;
addr_cmd <= dll_reset(c_seq_addr_cmd_config, -- configuration
int_mr0(c_max_mode_reg_index downto 0), -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
when s_4 =>
ac_state <= s_5;
stage_counter <= c_trp_in_clks;
addr_cmd <= precharge_all(c_seq_addr_cmd_config, -- configuration
2**MEM_IF_NUM_RANKS - 1); -- rank(s)
when s_5 =>
ac_state <= s_6;
stage_counter <= c_trfc_min_in_clks;
addr_cmd <= refresh(c_seq_addr_cmd_config, -- configuration
addr_cmd, -- previous value
2**current_cs); -- rank
when s_6 =>
ac_state <= s_7;
stage_counter <= c_trfc_min_in_clks;
addr_cmd <= refresh(c_seq_addr_cmd_config, -- configuration
addr_cmd, -- previous value
2**current_cs); -- rank
when s_7 =>
ac_state <= s_8;
stage_counter <= c_tmrd_in_clks;
v_mr_overload := int_mr0(c_max_mode_reg_index downto 3) & "010"; -- override to burst length 4
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
0, -- mode register number
v_mr_overload, -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
when s_8 =>
ac_state <= s_9;
stage_counter <= 200;
addr_cmd <= deselect(c_seq_addr_cmd_config, -- configuration
addr_cmd); -- previous value
per_cs_init_seen(current_cs) <= '1';
when s_9 =>
ac_state <= s_0;
stage_counter <= 1;
finished_state <= '1';
when others =>
null;
end case;
elsif MEM_IF_MEMTYPE = "DDR3" then
case ac_state is
when s_0 =>
ac_state <= s_1;
stage_counter <= c_trp_in_clks;
addr_cmd <= deselect(c_seq_addr_cmd_config, -- configuration
addr_cmd); -- previous value
when s_1 =>
ac_state <= s_2;
stage_counter <= c_tmrd_in_clks;
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
2, -- mode register number
int_mr2(c_max_mode_reg_index downto 0), -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
when s_2 =>
ac_state <= s_3;
stage_counter <= c_tmrd_in_clks;
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
3, -- mode register number
int_mr3(c_max_mode_reg_index downto 0), -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
when s_3 =>
ac_state <= s_4;
stage_counter <= c_tmrd_in_clks;
v_mr_overload := int_mr1(c_max_mode_reg_index downto 0);
v_mr_overload(0) := '0'; -- Override for DLL enable
v_mr_overload(12) := '0'; -- output buffer enable.
v_mr_overload(7) := '0'; -- Disable Write levelling
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
1, -- mode register number
v_mr_overload, -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
when s_4 =>
ac_state <= s_5;
stage_counter <= c_tmod_in_clks;
v_mr_overload := int_mr0(c_max_mode_reg_index downto 0);
v_mr_overload(1 downto 0) := "01"; -- override to on the fly burst length choice
v_mr_overload(7) := '0'; -- test mode not enabled
v_mr_overload(8) := '1'; -- DLL reset
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
0, -- mode register number
v_mr_overload, -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
when s_5 =>
ac_state <= s_6;
stage_counter <= c_zq_init_duration_clks;
addr_cmd <= ZQCL(c_seq_addr_cmd_config, -- configuration
2**current_cs); -- rank
per_cs_init_seen(current_cs) <= '1';
when s_6 =>
ac_state <= s_0;
stage_counter <= 1;
finished_state <= '1';
when others =>
ac_state <= s_0;
end case;
else
report admin_report_prefix & "unsupported memory type specified" severity error;
end if;
-- end of s_program_cal_mrs case
when s_prog_user_mrs =>
case ac_state is
when s_0 =>
ac_state <= s_1;
stage_counter <= 1;
addr_cmd <= deselect(c_seq_addr_cmd_config, -- configuration
addr_cmd); -- previous value
when s_1 =>
if MEM_IF_MEMTYPE = "DDR" then -- for DDR memory skip MR2/3 because not present
ac_state <= s_4;
else -- for DDR2/DDR3 all MRs programmed
ac_state <= s_2;
end if;
stage_counter <= c_trp_in_clks;
addr_cmd <= precharge_all(c_seq_addr_cmd_config, -- configuration
2**MEM_IF_NUM_RANKS - 1); -- rank(s)
when s_2 =>
ac_state <= s_3;
stage_counter <= c_tmrd_in_clks;
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
2, -- mode register number
int_mr2(c_max_mode_reg_index downto 0), -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
when s_3 =>
ac_state <= s_4;
stage_counter <= c_tmrd_in_clks;
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
3, -- mode register number
int_mr3(c_max_mode_reg_index downto 0), -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
if to_integer(unsigned(int_mr3)) /= 0 then
report admin_report_prefix & " mode register 3 is expected to have a value of 0 but has a value of : " &
integer'image(to_integer(unsigned(int_mr3))) severity warning;
end if;
when s_4 =>
ac_state <= s_5;
stage_counter <= c_tmrd_in_clks;
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
1, -- mode register number
int_mr1(c_max_mode_reg_index downto 0), -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
if (MEM_IF_DQSN_EN = 0) and (int_mr1(10) = '0') and (MEM_IF_MEMTYPE = "DDR2") then
report admin_report_prefix & "mode register and generic conflict:" & LF &
"* generic MEM_IF_DQSN_EN is set to 'disable' DQSN" & LF &
"* user mode register MEM_IF_MR1 bit 10 is set to 'enable' DQSN" severity warning;
end if;
when s_5 =>
ac_state <= s_6;
stage_counter <= c_tmod_in_clks;
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
0, -- mode register number
int_mr0(c_max_mode_reg_index downto 0), -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
when s_6 =>
ac_state <= s_7;
stage_counter <= 1;
when s_7 =>
ac_state <= s_0;
stage_counter <= 1;
finished_state <= '1';
when others =>
ac_state <= s_0;
end case;
-- end of s_prog_user_mr case
when s_access_precharge =>
case ac_state is
when s_0 =>
ac_state <= s_1;
stage_counter <= 8;
addr_cmd <= deselect(c_seq_addr_cmd_config, -- configuration
addr_cmd); -- previous value
when s_1 =>
ac_state <= s_2;
stage_counter <= c_trp_in_clks;
addr_cmd <= precharge_all(c_seq_addr_cmd_config, -- configuration
2**MEM_IF_NUM_RANKS - 1); -- rank(s)
when s_2 =>
ac_state <= s_0;
stage_counter <= 1;
finished_state <= '1';
when others =>
ac_state <= s_0;
end case;
when s_topup_refresh | s_refresh =>
case ac_state is
when s_0 =>
ac_state <= s_1;
stage_counter <= 1;
when s_1 =>
ac_state <= s_2;
stage_counter <= 1;
addr_cmd <= refresh(c_seq_addr_cmd_config, -- configuration
addr_cmd, -- previous value
2**MEM_IF_NUM_RANKS - 1); -- rank
when s_2 =>
ac_state <= s_0;
stage_counter <= 1;
finished_state <= '1';
when others =>
ac_state <= s_0;
end case;
when s_topup_refresh_done | s_refresh_done =>
case ac_state is
when s_0 =>
ac_state <= s_1;
stage_counter <= c_trfc_min_in_clks;
refresh_done <= '1'; -- ensure trfc not violated
when s_1 =>
ac_state <= s_0;
stage_counter <= 1;
finished_state <= '1';
when others =>
ac_state <= s_0;
end case;
when s_zq_cal_short =>
case ac_state is
when s_0 =>
ac_state <= s_1;
stage_counter <= 1;
when s_1 =>
ac_state <= s_2;
stage_counter <= c_tzqcs;
addr_cmd <= ZQCS(c_seq_addr_cmd_config, -- configuration
2**current_cs); -- all ranks
when s_2 =>
ac_state <= s_0;
stage_counter <= 1;
finished_state <= '1';
when others =>
ac_state <= s_0;
end case;
when s_access_act =>
case ac_state is
when s_0 =>
ac_state <= s_1;
stage_counter <= c_trrd_min_in_clks;
when s_1 =>
ac_state <= s_2;
stage_counter <= c_trcd_min_in_clks;
addr_cmd <= activate(c_seq_addr_cmd_config, -- configuration
addr_cmd, -- previous value
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_ROW, -- row address
2**current_cs); -- rank
when s_2 =>
ac_state <= s_0;
stage_counter <= 1;
finished_state <= '1';
when others =>
ac_state <= s_0;
end case;
-- counter to delay transition from s_idle to s_refresh - this is to ensure a refresh command is not sent
-- just as we enter operational state (could cause a trfc violation)
when s_dummy_wait =>
case ac_state is
when s_0 =>
ac_state <= s_1;
stage_counter <= c_max_wait_value;
when s_1 =>
ac_state <= s_0;
stage_counter <= 1;
finished_state <= '1';
when others =>
ac_state <= s_0;
end case;
when s_reset =>
stage_counter <= 1;
-- default some s_non_operational signals
if GENERATE_ADDITIONAL_DBG_RTL = 1 then
nop_toggle_signal <= addr;
nop_toggle_pin <= 0;
nop_toggle_value <= '0';
end if;
when s_non_operational => -- if failed then output a recognised pattern to the memory (Only executes if GENERATE_ADDITIONAL_DBG_RTL set)
addr_cmd <= deselect(c_seq_addr_cmd_config, -- configuration
addr_cmd); -- previous value
if NON_OP_EVAL_MD = "PIN_FINDER" then -- toggle pins in turn for 200 memory clk cycles
stage_counter <= 200/(DWIDTH_RATIO/2); -- 200 mem_clk cycles
case nop_toggle_signal is
when addr =>
addr_cmd <= mask (c_seq_addr_cmd_config, addr_cmd, addr, '0');
addr_cmd <= mask (c_seq_addr_cmd_config, addr_cmd, addr, nop_toggle_value, nop_toggle_pin);
nop_toggle_value <= not nop_toggle_value;
if nop_toggle_value = '1' then
if nop_toggle_pin = MEM_IF_ADDR_WIDTH-1 then
nop_toggle_signal <= ba;
nop_toggle_pin <= 0;
else
nop_toggle_pin <= nop_toggle_pin + 1;
end if;
end if;
when ba =>
addr_cmd <= mask (c_seq_addr_cmd_config, addr_cmd, ba, '0');
addr_cmd <= mask (c_seq_addr_cmd_config, addr_cmd, ba, nop_toggle_value, nop_toggle_pin);
nop_toggle_value <= not nop_toggle_value;
if nop_toggle_value = '1' then
if nop_toggle_pin = MEM_IF_BANKADDR_WIDTH-1 then
nop_toggle_signal <= cas_n;
nop_toggle_pin <= 0;
else
nop_toggle_pin <= nop_toggle_pin + 1;
end if;
end if;
when cas_n =>
addr_cmd <= mask (c_seq_addr_cmd_config, addr_cmd, cas_n, nop_toggle_value);
nop_toggle_value <= not nop_toggle_value;
if nop_toggle_value = '1' then
nop_toggle_signal <= ras_n;
end if;
when ras_n =>
addr_cmd <= mask (c_seq_addr_cmd_config, addr_cmd, ras_n, nop_toggle_value);
nop_toggle_value <= not nop_toggle_value;
if nop_toggle_value = '1' then
nop_toggle_signal <= we_n;
end if;
when we_n =>
addr_cmd <= mask (c_seq_addr_cmd_config, addr_cmd, we_n, nop_toggle_value);
nop_toggle_value <= not nop_toggle_value;
if nop_toggle_value = '1' then
nop_toggle_signal <= addr;
end if;
when others =>
report admin_report_prefix & " an attempt to toggle a non addr/cmd pin detected" severity failure;
end case;
elsif NON_OP_EVAL_MD = "SI_EVALUATOR" then -- toggle all addr/cmd pins at fmax
stage_counter <= 0; -- every mem_clk cycle
stage_counter_zero <= '1';
v_nop_ac_0 := mask (c_seq_addr_cmd_config, addr_cmd, addr, nop_toggle_value);
v_nop_ac_0 := mask (c_seq_addr_cmd_config, v_nop_ac_0, ba, nop_toggle_value);
v_nop_ac_0 := mask (c_seq_addr_cmd_config, v_nop_ac_0, we_n, nop_toggle_value);
v_nop_ac_0 := mask (c_seq_addr_cmd_config, v_nop_ac_0, ras_n, nop_toggle_value);
v_nop_ac_0 := mask (c_seq_addr_cmd_config, v_nop_ac_0, cas_n, nop_toggle_value);
v_nop_ac_1 := mask (c_seq_addr_cmd_config, addr_cmd, addr, not nop_toggle_value);
v_nop_ac_1 := mask (c_seq_addr_cmd_config, v_nop_ac_1, ba, not nop_toggle_value);
v_nop_ac_1 := mask (c_seq_addr_cmd_config, v_nop_ac_1, we_n, not nop_toggle_value);
v_nop_ac_1 := mask (c_seq_addr_cmd_config, v_nop_ac_1, ras_n, not nop_toggle_value);
v_nop_ac_1 := mask (c_seq_addr_cmd_config, v_nop_ac_1, cas_n, not nop_toggle_value);
for i in 0 to DWIDTH_RATIO/2 - 1 loop
if i mod 2 = 0 then
addr_cmd(i) <= v_nop_ac_0(i);
else
addr_cmd(i) <= v_nop_ac_1(i);
end if;
end loop;
if DWIDTH_RATIO = 2 then
nop_toggle_value <= not nop_toggle_value;
end if;
else
report admin_report_prefix & "unknown non-operational evaluation mode " & NON_OP_EVAL_MD severity failure;
end if;
when others =>
addr_cmd <= deselect(c_seq_addr_cmd_config, -- configuration
addr_cmd); -- previous value
stage_counter <= 1;
end case;
end if;
end if;
end process;
-- -------------------------------------------------------------------
-- output packing of mode register settings and enabling of ODT
-- -------------------------------------------------------------------
process (int_mr0, int_mr1, int_mr2, int_mr3, mem_init_complete)
begin
admin_regs_status_rec.mr0 <= int_mr0;
admin_regs_status_rec.mr1 <= int_mr1;
admin_regs_status_rec.mr2 <= int_mr2;
admin_regs_status_rec.mr3 <= int_mr3;
admin_regs_status_rec.init_done <= mem_init_complete;
enable_odt <= int_mr1(2) or int_mr1(6); -- if ODT enabled in MR settings (i.e. MR1 bits 2 or 6 /= 0)
end process;
-- --------------------------------------------------------------------------------
-- generation of handshake signals with ctrl, dgrb and dgwb blocks (this includes
-- command ack, command done for ctrl and access grant for dgrb/dgwb)
-- --------------------------------------------------------------------------------
process (rst_n, clk)
begin
if rst_n = '0' then
admin_ctrl <= defaults;
ac_access_gnt <= '0';
elsif rising_edge(clk) then
admin_ctrl <= defaults;
ac_access_gnt <= '0';
admin_ctrl.command_ack <= command_started;
admin_ctrl.command_done <= command_done;
if state = s_access then
ac_access_gnt <= '1';
end if;
end if;
end process;
end architecture struct;
--
-- -----------------------------------------------------------------------------
-- Abstract : inferred ram for the non-levelling AFI PHY sequencer
-- The inferred ram is used in the iram block to store
-- debug information about the sequencer. It is variable in
-- size based on the IRAM_AWIDTH generic and is of size
-- 32 * (2 ** IRAM_ADDR_WIDTH) bits
-- -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
-- The record package (alt_mem_phy_record_pkg) is used to combine command and status signals
-- (into records) to be passed between sequencer blocks. It also contains type and record definitions
-- for the stages of DRAM memory calibration.
--
use work.ddr3_int_phy_alt_mem_phy_record_pkg.all;
--
entity ddr3_int_phy_alt_mem_phy_iram_ram IS
generic (
IRAM_AWIDTH : natural
);
port (
clk : in std_logic;
rst_n : in std_logic;
-- ram ports
addr : in unsigned(IRAM_AWIDTH-1 downto 0);
wdata : in std_logic_vector(31 downto 0);
write : in std_logic;
rdata : out std_logic_vector(31 downto 0)
);
end entity;
--
architecture struct of ddr3_int_phy_alt_mem_phy_iram_ram is
-- infer ram
constant c_max_ram_address : natural := 2**IRAM_AWIDTH -1;
-- registered ram signals
signal addr_r : unsigned(IRAM_AWIDTH-1 downto 0);
signal wdata_r : std_logic_vector(31 downto 0);
signal write_r : std_logic;
signal rdata_r : std_logic_vector(31 downto 0);
-- ram storage array
type t_iram is array (0 to c_max_ram_address) of std_logic_vector(31 downto 0);
signal iram_ram : t_iram;
attribute altera_attribute : string;
attribute altera_attribute of iram_ram : signal is "-name ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS ""OFF""";
begin -- architecture struct
-- inferred ram instance - standard ram logic
process (clk, rst_n)
begin
if rst_n = '0' then
rdata_r <= (others => '0');
elsif rising_edge(clk) then
if write_r = '1' then
iram_ram(to_integer(addr_r)) <= wdata_r;
end if;
rdata_r <= iram_ram(to_integer(addr_r));
end if;
end process;
-- register i/o for speed
process (clk, rst_n)
begin
if rst_n = '0' then
rdata <= (others => '0');
write_r <= '0';
addr_r <= (others => '0');
wdata_r <= (others => '0');
elsif rising_edge(clk) then
rdata <= rdata_r;
write_r <= write;
addr_r <= addr;
wdata_r <= wdata;
end if;
end process;
end architecture struct;
--
-- -----------------------------------------------------------------------------
-- Abstract : iram block for the non-levelling AFI PHY sequencer
-- This block is an optional storage of debug information for
-- the sequencer. In the current form the iram stores header
-- information about the arrangement of the sequencer and pass/
-- fail information for per-delay/phase/pin sweeps for the
-- read resynch phase calibration stage. Support for debug of
-- additional commands can be added at a later date
-- -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
-- The record package (alt_mem_phy_record_pkg) is used to combine command and status signals
-- (into records) to be passed between sequencer blocks. It also contains type and record definitions
-- for the stages of DRAM memory calibration.
--
use work.ddr3_int_phy_alt_mem_phy_record_pkg.all;
-- The altmemphy iram ram (alt_mem_phy_iram_ram) is an inferred ram memory to implement the debug
-- iram ram block
--
use work.ddr3_int_phy_alt_mem_phy_iram_ram;
--
entity ddr3_int_phy_alt_mem_phy_iram is
generic (
-- physical interface width definitions
MEM_IF_MEMTYPE : string;
FAMILYGROUP_ID : natural;
MEM_IF_DQS_WIDTH : natural;
MEM_IF_DQ_PER_DQS : natural;
MEM_IF_DWIDTH : natural;
MEM_IF_DM_WIDTH : natural;
MEM_IF_NUM_RANKS : natural;
IRAM_AWIDTH : natural;
REFRESH_COUNT_INIT : natural;
PRESET_RLAT : natural;
PLL_STEPS_PER_CYCLE : natural;
CAPABILITIES : natural;
IP_BUILDNUM : natural
);
port (
-- clk / reset
clk : in std_logic;
rst_n : in std_logic;
-- read interface from mmi block:
mmi_iram : in t_iram_ctrl;
mmi_iram_enable_writes : in std_logic;
--iram status signal (includes read data from iram)
iram_status : out t_iram_stat;
iram_push_done : out std_logic;
-- from ctrl block
ctrl_iram : in t_ctrl_command;
-- from dgrb block
dgrb_iram : in t_iram_push;
-- from admin block
admin_regs_status_rec : in t_admin_stat;
-- current write position in the iram
ctrl_idib_top : in natural range 0 to 2 ** IRAM_AWIDTH - 1;
ctrl_iram_push : in t_ctrl_iram;
-- the following signals are unused and reserved for future use
dgwb_iram : in t_iram_push
);
end entity;
library work;
-- The registers package (alt_mem_phy_regs_pkg) is used to combine the definition of the
-- registers for the mmi status registers and functions/procedures applied to the registers
--
use work.ddr3_int_phy_alt_mem_phy_regs_pkg.all;
--
architecture struct of ddr3_int_phy_alt_mem_phy_iram is
-- -------------------------------------------
-- IHI fields
-- -------------------------------------------
-- memory type , Quartus Build No., Quartus release, sequencer architecture version :
signal memtype : std_logic_vector(7 downto 0);
signal ihi_self_description : std_logic_vector(31 downto 0);
signal ihi_self_description_extra : std_logic_vector(31 downto 0);
-- for iram address generation:
signal curr_iram_offset : natural range 0 to 2 ** IRAM_AWIDTH - 1;
-- set read latency for iram_rdata_valid signal control:
constant c_iram_rlat : natural := 3; -- iram read latency (increment if read pipelining added
-- for rdata valid generation:
signal read_valid_ctr : natural range 0 to c_iram_rlat;
signal iram_addr_r : unsigned(IRAM_AWIDTH downto 0);
constant c_ihi_phys_if_desc : std_logic_vector(31 downto 0) := std_logic_vector (to_unsigned(MEM_IF_NUM_RANKS,8) & to_unsigned(MEM_IF_DM_WIDTH,8) & to_unsigned(MEM_IF_DQS_WIDTH,8) & to_unsigned(MEM_IF_DWIDTH,8));
constant c_ihi_timing_info : std_logic_vector(31 downto 0) := X"DEADDEAD";
constant c_ihi_ctrl_ss_word2 : std_logic_vector(31 downto 0) := std_logic_vector (to_unsigned(PRESET_RLAT,16) & X"0000");
-- IDIB header codes
constant c_idib_header_code0 : std_logic_vector(7 downto 0) := X"4A";
constant c_idib_footer_code : std_logic_vector(7 downto 0) := X"5A";
-- encoded Quartus version
-- constant c_quartus_version : natural := 0; -- Quartus 7.2
-- constant c_quartus_version : natural := 1; -- Quartus 8.0
--constant c_quartus_version : natural := 2; -- Quartus 8.1
--constant c_quartus_version : natural := 3; -- Quartus 9.0
--constant c_quartus_version : natural := 4; -- Quartus 9.0sp2
--constant c_quartus_version : natural := 5; -- Quartus 9.1
--constant c_quartus_version : natural := 6; -- Quartus 9.1sp1?
--constant c_quartus_version : natural := 7; -- Quartus 9.1sp2?
constant c_quartus_version : natural := 8; -- Quartus 10.0
-- constant c_quartus_version : natural := 114; -- reserved
-- allow for different variants for debug i/f
constant c_dbg_if_version : natural := 2;
-- sequencer type 1 for levelling, 2 for non-levelling
constant c_sequencer_type : natural := 2;
-- a prefix for all report signals to identify phy and sequencer block
--
constant iram_report_prefix : string := "ddr3_int_phy_alt_mem_phy_seq (iram) : ";
-- -------------------------------------------
-- signal and type declarations
-- -------------------------------------------
type t_iram_state is ( s_reset, -- system reset
s_pre_init_ram, -- identify pre-initialisation
s_init_ram, -- zero all locations
s_idle, -- default state
s_word_access_ram, -- mmi access to the iram (post-calibration)
s_word_fetch_ram_rdata, -- sample read data from RAM
s_word_fetch_ram_rdata_r,-- register the sampling of data from RAM (to improve timing)
s_word_complete, -- finalise iram ram write
s_idib_header_write, -- when starting a command
s_idib_header_inc_addr, -- address increment
s_idib_footer_write, -- unique footer to indicate end of data
s_cal_data_read, -- read RAM location (read occurs continuously from idle state)
s_cal_data_read_r,
s_cal_data_modify, -- modify RAM location (read occurs continuously)
s_cal_data_write, -- write modified value back to RAM
s_ihi_header_word0_wr, -- from 0 to 6 writing iram header info
s_ihi_header_word1_wr,
s_ihi_header_word2_wr,
s_ihi_header_word3_wr,
s_ihi_header_word4_wr,
s_ihi_header_word5_wr,
s_ihi_header_word6_wr,
s_ihi_header_word7_wr-- end writing iram header info
);
signal state : t_iram_state;
signal contested_access : std_logic;
signal idib_header_count : std_logic_vector(7 downto 0);
-- register a new cmd request
signal new_cmd : std_logic;
signal cmd_processed : std_logic;
-- signals to control dgrb writes
signal iram_modified_data : std_logic_vector(31 downto 0); -- scratchpad memory for read-modify-write
-- -------------------------------------------
-- physical ram connections
-- -------------------------------------------
-- Note that the iram_addr here is created IRAM_AWIDTH downto 0, and not
-- IRAM_AWIDTH-1 downto 0. This means that the MSB is outside the addressable
-- area of the RAM. The purpose of this is that this shall be our memory
-- overflow bit. It shall be directly connected to the iram_out_of_memory flag
-- 32-bit interface port (read and write)
signal iram_addr : unsigned(IRAM_AWIDTH downto 0);
signal iram_wdata : std_logic_vector(31 downto 0);
signal iram_rdata : std_logic_vector(31 downto 0);
signal iram_write : std_logic;
-- signal generated external to the iram to say when read data is valid
signal iram_rdata_valid : std_logic;
-- The FSM owns local storage that is loaded with the wdata/addr from the
-- requesting sub-block, which is then fed to the iram's wdata/addr in turn
-- until all data has gone across
signal fsm_read : std_logic;
-- -------------------------------------------
-- multiplexed push data
-- -------------------------------------------
signal iram_done : std_logic; -- unused
signal iram_pushdata : std_logic_vector(31 downto 0);
signal pending_push : std_logic; -- push data to RAM
signal iram_wordnum : natural range 0 to 511;
signal iram_bitnum : natural range 0 to 31;
begin -- architecture struct
-- -------------------------------------------
-- iram ram instantiation
-- -------------------------------------------
-- Note that the IRAM_AWIDTH is the physical number of address bits that the RAM has.
-- However, for out of range access detection purposes, an additional bit is added to
-- the various address signals. The iRAM does not register any of its inputs as the addr,
-- wdata etc are registered directly before being driven to it.
-- The dgrb accesses are of format read-modify-write to a single bit of a 32-bit word, the
-- mmi reads and header writes are in 32-bit words
--
ram : entity ddr3_int_phy_alt_mem_phy_iram_ram
generic map (
IRAM_AWIDTH => IRAM_AWIDTH
)
port map (
clk => clk,
rst_n => rst_n,
addr => iram_addr(IRAM_AWIDTH-1 downto 0),
wdata => iram_wdata,
write => iram_write,
rdata => iram_rdata
);
-- -------------------------------------------
-- IHI fields
-- asynchronously
-- -------------------------------------------
-- this field identifies the type of memory
memtype <= X"03" when (MEM_IF_MEMTYPE = "DDR3") else
X"02" when (MEM_IF_MEMTYPE = "DDR2") else
X"01" when (MEM_IF_MEMTYPE = "DDR") else
X"10" when (MEM_IF_MEMTYPE = "QDRII") else
X"00" ;
-- this field indentifies the gross level description of the sequencer
ihi_self_description <= memtype
& std_logic_vector(to_unsigned(IP_BUILDNUM,8))
& std_logic_vector(to_unsigned(c_quartus_version,8))
& std_logic_vector(to_unsigned(c_dbg_if_version,8));
-- some extra information for the debug gui - sequencer type and familygroup
ihi_self_description_extra <= std_logic_vector(to_unsigned(FAMILYGROUP_ID,4))
& std_logic_vector(to_unsigned(c_sequencer_type,4))
& x"000000";
-- -------------------------------------------
-- check for contested memory accesses
-- -------------------------------------------
process(clk,rst_n)
begin
if rst_n = '0' then
contested_access <= '0';
elsif rising_edge(clk) then
contested_access <= '0';
if mmi_iram.read = '1' and pending_push = '1' then
report iram_report_prefix & "contested memory accesses to the iram" severity failure;
contested_access <= '1';
end if;
-- sanity checks
if mmi_iram.write = '1' then
report iram_report_prefix & "mmi writes to the iram unsupported for non-levelling AFI PHY sequencer" severity failure;
end if;
if dgwb_iram.iram_write = '1' then
report iram_report_prefix & "dgwb writes to the iram unsupported for non-levelling AFI PHY sequencer" severity failure;
end if;
end if;
end process;
-- -------------------------------------------
-- mux push data and associated signals
-- note: single bit taken for iram_pushdata because 1-bit read-modify-write to
-- a 32-bit word in the ram. This interface style is maintained for future
-- scalability / wider application of the iram block.
-- -------------------------------------------
process(clk,rst_n)
begin
if rst_n = '0' then
iram_done <= '0';
iram_pushdata <= (others => '0');
pending_push <= '0';
iram_wordnum <= 0;
iram_bitnum <= 0;
elsif rising_edge(clk) then
case curr_active_block(ctrl_iram.command) is
when dgrb =>
iram_done <= dgrb_iram.iram_done;
iram_pushdata <= dgrb_iram.iram_pushdata;
pending_push <= dgrb_iram.iram_write;
iram_wordnum <= dgrb_iram.iram_wordnum;
iram_bitnum <= dgrb_iram.iram_bitnum;
when others => -- default dgrb
iram_done <= dgrb_iram.iram_done;
iram_pushdata <= dgrb_iram.iram_pushdata;
pending_push <= dgrb_iram.iram_write;
iram_wordnum <= dgrb_iram.iram_wordnum;
iram_bitnum <= dgrb_iram.iram_bitnum;
end case;
end if;
end process;
-- -------------------------------------------
-- generate write signal for the ram
-- -------------------------------------------
process(clk, rst_n)
begin
if rst_n = '0' then
iram_write <= '0';
elsif rising_edge(clk) then
case state is
when s_idle =>
iram_write <= '0';
when s_pre_init_ram |
s_init_ram =>
iram_write <= '1';
when s_ihi_header_word0_wr |
s_ihi_header_word1_wr |
s_ihi_header_word2_wr |
s_ihi_header_word3_wr |
s_ihi_header_word4_wr |
s_ihi_header_word5_wr |
s_ihi_header_word6_wr |
s_ihi_header_word7_wr =>
iram_write <= '1';
when s_idib_header_write =>
iram_write <= '1';
when s_idib_footer_write =>
iram_write <= '1';
when s_cal_data_write =>
iram_write <= '1';
when others =>
iram_write <= '0'; -- default
end case;
end if;
end process;
-- -------------------------------------------
-- generate wdata for the ram
-- -------------------------------------------
process(clk, rst_n)
variable v_current_cs : std_logic_vector(3 downto 0);
variable v_mtp_alignment : std_logic_vector(0 downto 0);
variable v_single_bit : std_logic;
begin
if rst_n = '0' then
iram_wdata <= (others => '0');
elsif rising_edge(clk) then
case state is
when s_pre_init_ram |
s_init_ram =>
iram_wdata <= (others => '0');
when s_ihi_header_word0_wr =>
iram_wdata <= ihi_self_description;
when s_ihi_header_word1_wr =>
iram_wdata <= c_ihi_phys_if_desc;
when s_ihi_header_word2_wr =>
iram_wdata <= c_ihi_timing_info;
when s_ihi_header_word3_wr =>
iram_wdata <= ( others => '0');
iram_wdata(admin_regs_status_rec.mr0'range) <= admin_regs_status_rec.mr0;
iram_wdata(admin_regs_status_rec.mr1'high + 16 downto 16) <= admin_regs_status_rec.mr1;
when s_ihi_header_word4_wr =>
iram_wdata <= ( others => '0');
iram_wdata(admin_regs_status_rec.mr2'range) <= admin_regs_status_rec.mr2;
iram_wdata(admin_regs_status_rec.mr3'high + 16 downto 16) <= admin_regs_status_rec.mr3;
when s_ihi_header_word5_wr =>
iram_wdata <= c_ihi_ctrl_ss_word2;
when s_ihi_header_word6_wr =>
iram_wdata <= std_logic_vector(to_unsigned(IRAM_AWIDTH,32)); -- tbd write the occupancy at end of cal
when s_ihi_header_word7_wr =>
iram_wdata <= ihi_self_description_extra;
when s_idib_header_write =>
-- encode command_op for current operation
v_current_cs := std_logic_vector(to_unsigned(ctrl_iram.command_op.current_cs, 4));
v_mtp_alignment := std_logic_vector(to_unsigned(ctrl_iram.command_op.mtp_almt, 1));
v_single_bit := ctrl_iram.command_op.single_bit;
iram_wdata <= encode_current_stage(ctrl_iram.command) & -- which command being executed (currently this should only be cmd_rrp_sweep (8 bits)
v_current_cs & -- which chip select being processed (4 bits)
v_mtp_alignment & -- currently used MTP alignment (1 bit)
v_single_bit & -- is single bit calibration selected (1 bit) - used during MTP alignment
"00" & -- RFU
idib_header_count & -- unique ID to how many headers have been written (8 bits)
c_idib_header_code0; -- unique ID for headers (8 bits)
when s_idib_footer_write =>
iram_wdata <= c_idib_footer_code & c_idib_footer_code & c_idib_footer_code & c_idib_footer_code;
when s_cal_data_modify =>
-- default don't overwrite
iram_modified_data <= iram_rdata;
-- update iram data based on packing and write modes
if ctrl_iram_push.packing_mode = dq_bitwise then
case ctrl_iram_push.write_mode is
when overwrite_ram =>
iram_modified_data(iram_bitnum) <= iram_pushdata(0);
when or_into_ram =>
iram_modified_data(iram_bitnum) <= iram_pushdata(0) or iram_rdata(0);
when and_into_ram =>
iram_modified_data(iram_bitnum) <= iram_pushdata(0) and iram_rdata(0);
when others =>
report iram_report_prefix & "unidentified write mode of " & t_iram_write_mode'image(ctrl_iram_push.write_mode) &
" specified when generating iram write data" severity failure;
end case;
elsif ctrl_iram_push.packing_mode = dq_wordwise then
case ctrl_iram_push.write_mode is
when overwrite_ram =>
iram_modified_data <= iram_pushdata;
when or_into_ram =>
iram_modified_data <= iram_pushdata or iram_rdata;
when and_into_ram =>
iram_modified_data <= iram_pushdata and iram_rdata;
when others =>
report iram_report_prefix & "unidentified write mode of " & t_iram_write_mode'image(ctrl_iram_push.write_mode) &
" specified when generating iram write data" severity failure;
end case;
else
report iram_report_prefix & "unidentified packing mode of " & t_iram_packing_mode'image(ctrl_iram_push.packing_mode) &
" specified when generating iram write data" severity failure;
end if;
when s_cal_data_write =>
iram_wdata <= iram_modified_data;
when others =>
iram_wdata <= (others => '0');
end case;
end if;
end process;
-- -------------------------------------------
-- generate addr for the ram
-- -------------------------------------------
process(clk, rst_n)
begin
if rst_n = '0' then
iram_addr <= (others => '0');
curr_iram_offset <= 0;
elsif rising_edge(clk) then
case (state) is
when s_idle =>
if mmi_iram.read = '1' then -- pre-set mmi read location address
iram_addr <= ('0' & to_unsigned(mmi_iram.addr,IRAM_AWIDTH)); -- Pad MSB
else -- default get next push data location from iram
iram_addr <= to_unsigned(curr_iram_offset + iram_wordnum, IRAM_AWIDTH+1);
end if;
when s_word_access_ram =>
-- calculate the address
if mmi_iram.read = '1' then -- mmi access
iram_addr <= ('0' & to_unsigned(mmi_iram.addr,IRAM_AWIDTH)); -- Pad MSB
end if;
when s_ihi_header_word0_wr =>
iram_addr <= (others => '0');
-- increment address for IHI word writes :
when s_ihi_header_word1_wr |
s_ihi_header_word2_wr |
s_ihi_header_word3_wr |
s_ihi_header_word4_wr |
s_ihi_header_word5_wr |
s_ihi_header_word6_wr |
s_ihi_header_word7_wr =>
iram_addr <= iram_addr + 1;
when s_idib_header_write =>
iram_addr <= '0' & to_unsigned(ctrl_idib_top, IRAM_AWIDTH); -- Always write header at idib_top location
when s_idib_footer_write =>
iram_addr <= to_unsigned(curr_iram_offset + iram_wordnum, IRAM_AWIDTH+1); -- active block communicates where to put the footer with done signal
when s_idib_header_inc_addr =>
iram_addr <= iram_addr + 1;
curr_iram_offset <= to_integer('0' & iram_addr) + 1;
when s_init_ram =>
if iram_addr(IRAM_AWIDTH) = '1' then
iram_addr <= (others => '0'); -- this prevents erroneous out-of-mem flag after initialisation
else
iram_addr <= iram_addr + 1;
end if;
when others =>
iram_addr <= iram_addr;
end case;
end if;
end process;
-- -------------------------------------------
-- generate new cmd signal to register the command_req signal
-- -------------------------------------------
process(clk, rst_n)
begin
if rst_n = '0' then
new_cmd <= '0';
elsif rising_edge(clk) then
if ctrl_iram.command_req = '1' then
case ctrl_iram.command is
when cmd_rrp_sweep | -- only prompt new_cmd for commands we wish to write headers for
cmd_rrp_seek |
cmd_read_mtp |
cmd_write_ihi =>
new_cmd <= '1';
when others =>
new_cmd <= '0';
end case;
end if;
if cmd_processed = '1' then
new_cmd <= '0';
end if;
end if;
end process;
-- -------------------------------------------
-- generate read valid signal which takes account of pipelining of reads
-- -------------------------------------------
process(clk, rst_n)
begin
if rst_n = '0' then
iram_rdata_valid <= '0';
read_valid_ctr <= 0;
iram_addr_r <= (others => '0');
elsif rising_edge(clk) then
if read_valid_ctr < c_iram_rlat then
iram_rdata_valid <= '0';
read_valid_ctr <= read_valid_ctr + 1;
else
iram_rdata_valid <= '1';
end if;
if to_integer(iram_addr) /= to_integer(iram_addr_r) or
iram_write = '1' then
read_valid_ctr <= 0;
iram_rdata_valid <= '0';
end if;
-- register iram address
iram_addr_r <= iram_addr;
end if;
end process;
-- -------------------------------------------
-- state machine
-- -------------------------------------------
process(clk, rst_n)
begin
if rst_n = '0' then
state <= s_reset;
cmd_processed <= '0';
elsif rising_edge(clk) then
cmd_processed <= '0';
case state is
when s_reset =>
state <= s_pre_init_ram;
when s_pre_init_ram =>
state <= s_init_ram;
-- remain in the init_ram state until all the ram locations have been zero'ed
when s_init_ram =>
if iram_addr(IRAM_AWIDTH) = '1' then
state <= s_idle;
end if;
-- default state after reset
when s_idle =>
if pending_push = '1' then
state <= s_cal_data_read;
elsif iram_done = '1' then
state <= s_idib_footer_write;
elsif new_cmd = '1' then
case ctrl_iram.command is
when cmd_rrp_sweep |
cmd_rrp_seek |
cmd_read_mtp => state <= s_idib_header_write;
when cmd_write_ihi => state <= s_ihi_header_word0_wr;
when others => state <= state;
end case;
cmd_processed <= '1';
elsif mmi_iram.read = '1' then
state <= s_word_access_ram;
end if;
-- mmi read accesses
when s_word_access_ram => state <= s_word_fetch_ram_rdata;
when s_word_fetch_ram_rdata => state <= s_word_fetch_ram_rdata_r;
when s_word_fetch_ram_rdata_r => if iram_rdata_valid = '1' then
state <= s_word_complete;
end if;
when s_word_complete => if iram_rdata_valid = '1' then -- return to idle when iram_rdata stable
state <= s_idle;
end if;
-- header write (currently only for cmp_rrp stage)
when s_idib_header_write => state <= s_idib_header_inc_addr;
when s_idib_header_inc_addr => state <= s_idle; -- return to idle to wait for push
when s_idib_footer_write => state <= s_word_complete;
-- push data accesses (only used by the dgrb block at present)
when s_cal_data_read => state <= s_cal_data_read_r;
when s_cal_data_read_r => if iram_rdata_valid = '1' then
state <= s_cal_data_modify;
end if;
when s_cal_data_modify => state <= s_cal_data_write;
when s_cal_data_write => state <= s_word_complete;
-- IHI Header write accesses
when s_ihi_header_word0_wr => state <= s_ihi_header_word1_wr;
when s_ihi_header_word1_wr => state <= s_ihi_header_word2_wr;
when s_ihi_header_word2_wr => state <= s_ihi_header_word3_wr;
when s_ihi_header_word3_wr => state <= s_ihi_header_word4_wr;
when s_ihi_header_word4_wr => state <= s_ihi_header_word5_wr;
when s_ihi_header_word5_wr => state <= s_ihi_header_word6_wr;
when s_ihi_header_word6_wr => state <= s_ihi_header_word7_wr;
when s_ihi_header_word7_wr => state <= s_idle;
when others => state <= state;
end case;
end if;
end process;
-- -------------------------------------------
-- drive read data and responses back.
-- -------------------------------------------
process(clk, rst_n)
begin
if rst_n = '0' then
iram_status <= defaults;
iram_push_done <= '0';
idib_header_count <= (others => '0');
fsm_read <= '0';
elsif rising_edge(clk) then
-- defaults
iram_status <= defaults;
iram_status.done <= '0';
iram_status.rdata <= (others => '0');
iram_push_done <= '0';
if state = s_init_ram then
iram_status.out_of_mem <= '0';
else
iram_status.out_of_mem <= iram_addr(IRAM_AWIDTH);
end if;
-- register read flag for 32 bit accesses
if state = s_idle then
fsm_read <= mmi_iram.read;
end if;
if state = s_word_complete then
iram_status.done <= '1';
if fsm_read = '1' then
iram_status.rdata <= iram_rdata;
else
iram_status.rdata <= (others => '0');
end if;
end if;
-- if another access is ever presented while the FSM is busy, set the contested flag
if contested_access = '1' then
iram_status.contested_access <= '1';
end if;
-- set (and keep set) the iram_init_done output once initialisation of the RAM is complete
if (state /= s_init_ram) and (state /= s_pre_init_ram) and (state /= s_reset) then
iram_status.init_done <= '1';
end if;
if state = s_ihi_header_word7_wr then
iram_push_done <= '1';
end if;
-- if completing push or footer write then acknowledge
if state = s_cal_data_modify or state = s_idib_footer_write then
iram_push_done <= '1';
end if;
-- increment IDIB header count each time a header is written
if state = s_idib_header_write then
idib_header_count <= std_logic_vector(unsigned(idib_header_count) + to_unsigned(1,idib_header_count'high +1));
end if;
end if;
end process;
end architecture struct;
--
-- -----------------------------------------------------------------------------
-- Abstract : data gatherer (read bias) [dgrb] block for the non-levelling
-- AFI PHY sequencer
-- This block handles all calibration commands which require
-- memory read operations.
--
-- These include:
-- Resync phase calibration - sweep of phases, calculation of
-- result and optional storage to iram
-- Postamble calibration - clock cycle calibration of the postamble
-- enable signal
-- Read data valid signal alignment
-- Calculation of advertised read and write latencies
-- -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
-- The record package (alt_mem_phy_record_pkg) is used to combine command and status signals
-- (into records) to be passed between sequencer blocks. It also contains type and record definitions
-- for the stages of DRAM memory calibration.
--
use work.ddr3_int_phy_alt_mem_phy_record_pkg.all;
-- The address and command package (alt_mem_phy_addr_cmd_pkg) is used to combine DRAM address
-- and command signals in one record and unify the functions operating on this record.
--
use work.ddr3_int_phy_alt_mem_phy_addr_cmd_pkg.all;
-- The iram address package (alt_mem_phy_iram_addr_pkg) is used to define the base addresses used
-- for iram writes during calibration
--
use work.ddr3_int_phy_alt_mem_phy_iram_addr_pkg.all;
-- The constant package (alt_mem_phy_constants_pkg) contains global 'constants' which are fixed
-- thoughout the sequencer and will not change (for constants which may change between sequencer
-- instances generics are used)
--
use work.ddr3_int_phy_alt_mem_phy_constants_pkg.all;
--
entity ddr3_int_phy_alt_mem_phy_dgrb is
generic (
MEM_IF_DQS_WIDTH : natural;
MEM_IF_DQ_PER_DQS : natural;
MEM_IF_DWIDTH : natural;
MEM_IF_DM_WIDTH : natural;
MEM_IF_DQS_CAPTURE : natural;
MEM_IF_ADDR_WIDTH : natural;
MEM_IF_BANKADDR_WIDTH : natural;
MEM_IF_NUM_RANKS : natural;
MEM_IF_MEMTYPE : string;
ADV_LAT_WIDTH : natural;
CLOCK_INDEX_WIDTH : natural;
DWIDTH_RATIO : natural;
PRESET_RLAT : natural;
PLL_STEPS_PER_CYCLE : natural; -- number of PLL phase steps per PHY clock cycle
SIM_TIME_REDUCTIONS : natural;
GENERATE_ADDITIONAL_DBG_RTL : natural;
PRESET_CODVW_PHASE : natural;
PRESET_CODVW_SIZE : natural;
-- base column address to which calibration data is written
-- memory at MEM_IF_CAL_BASE_COL - MEM_IF_CAL_BASE_COL + C_CAL_DATA_LEN - 1
-- is assumed to contain the proper data
MEM_IF_CAL_BANK : natural; -- bank to which calibration data is written
MEM_IF_CAL_BASE_COL : natural;
EN_OCT : natural
);
port (
-- clk / reset
clk : in std_logic;
rst_n : in std_logic;
-- control interface
dgrb_ctrl : out t_ctrl_stat;
ctrl_dgrb : in t_ctrl_command;
parameterisation_rec : in t_algm_paramaterisation;
-- PLL reconfig interface
phs_shft_busy : in std_logic;
seq_pll_inc_dec_n : out std_logic;
seq_pll_select : out std_logic_vector(CLOCK_INDEX_WIDTH - 1 DOWNTO 0);
seq_pll_start_reconfig : out std_logic;
pll_resync_clk_index : in std_logic_vector(CLOCK_INDEX_WIDTH - 1 downto 0); -- PLL phase used to select resync clock
pll_measure_clk_index : in std_logic_vector(CLOCK_INDEX_WIDTH - 1 downto 0); -- PLL phase used to select mimic / aka measure clock
-- iram 'push' interface
dgrb_iram : out t_iram_push;
iram_push_done : in std_logic;
-- addr/cmd output for write commands
dgrb_ac : out t_addr_cmd_vector(0 to (DWIDTH_RATIO/2)-1);
-- admin block req/gnt interface
dgrb_ac_access_req : out std_logic;
dgrb_ac_access_gnt : in std_logic;
-- RDV latency controls
seq_rdata_valid_lat_inc : out std_logic;
seq_rdata_valid_lat_dec : out std_logic;
-- POA latency controls
seq_poa_lat_dec_1x : out std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
seq_poa_lat_inc_1x : out std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
-- read datapath interface
rdata_valid : in std_logic_vector(DWIDTH_RATIO/2 - 1 downto 0);
rdata : in std_logic_vector(DWIDTH_RATIO * MEM_IF_DWIDTH - 1 downto 0);
doing_rd : out std_logic_vector(MEM_IF_DQS_WIDTH * DWIDTH_RATIO/2 - 1 downto 0);
rd_lat : out std_logic_vector(ADV_LAT_WIDTH - 1 downto 0);
-- advertised write latency
wd_lat : out std_logic_vector(ADV_LAT_WIDTH - 1 downto 0);
-- OCT control
seq_oct_value : out std_logic;
dgrb_wdp_ovride : out std_logic;
-- mimic path interface
seq_mmc_start : out std_logic;
mmc_seq_done : in std_logic;
mmc_seq_value : in std_logic;
-- calibration byte lane select (reserved for future use - RFU)
ctl_cal_byte_lanes : in std_logic_vector(MEM_IF_NUM_RANKS * MEM_IF_DQS_WIDTH - 1 downto 0);
-- odt settings per chip select
odt_settings : in t_odt_array(0 to MEM_IF_NUM_RANKS-1);
-- signal to identify if a/c nt setting is correct (set after wr_lat calculation)
-- NOTE: labelled nt for future scalability to quarter rate interfaces
dgrb_ctrl_ac_nt_good : out std_logic;
-- status signals on calibrated cdvw
dgrb_mmi : out t_dgrb_mmi
);
end entity;
--
architecture struct of ddr3_int_phy_alt_mem_phy_dgrb is
-- ------------------------------------------------------------------
-- constant declarations
-- ------------------------------------------------------------------
constant c_seq_addr_cmd_config : t_addr_cmd_config_rec := set_config_rec(MEM_IF_ADDR_WIDTH, MEM_IF_BANKADDR_WIDTH, MEM_IF_NUM_RANKS, DWIDTH_RATIO, MEM_IF_MEMTYPE);
-- command/result length
constant c_command_result_len : natural := 8;
-- burst characteristics and latency characteristics
constant c_max_read_lat : natural := 2**rd_lat'length - 1; -- maximum read latency in phy clock-cycles
-- training pattern characteristics
constant c_cal_mtp_len : natural := 16;
constant c_cal_mtp : std_logic_vector(c_cal_mtp_len - 1 downto 0) := x"30F5";
constant c_cal_mtp_t : natural := c_cal_mtp_len / DWIDTH_RATIO; -- number of phy-clk cycles required to read BTP
-- read/write latency defaults
constant c_default_rd_lat_slv : std_logic_vector(ADV_LAT_WIDTH - 1 downto 0) := std_logic_vector(to_unsigned(c_default_rd_lat, ADV_LAT_WIDTH));
constant c_default_wd_lat_slv : std_logic_vector(ADV_LAT_WIDTH - 1 downto 0) := std_logic_vector(to_unsigned(c_default_wr_lat, ADV_LAT_WIDTH));
-- tracking reporting parameters
constant c_max_rsc_drift_in_phases : natural := 127; -- this must be a value of < 2^10 - 1 because of the range of signal codvw_trk_shift
-- Returns '1' when boolean b is True; '0' otherwise.
function active_high(b : in boolean) return std_logic is
variable r : std_logic;
begin
if b then
r := '1';
else
r := '0';
end if;
return r;
end function;
-- a prefix for all report signals to identify phy and sequencer block
--
constant dgrb_report_prefix : string := "ddr3_int_phy_alt_mem_phy_seq (dgrb) : ";
-- Return the number of clock periods the resync clock should sweep.
--
-- On half-rate systems and in DQS-capture based systems a 720
-- to guarantee the resync window can be properly observed.
function rsc_sweep_clk_periods return natural is
variable v_num_periods : natural;
begin
if DWIDTH_RATIO = 2 then
if MEM_IF_DQS_CAPTURE = 1 then -- families which use DQS capture require a 720 degree sweep for FR to show a window
v_num_periods := 2;
else
v_num_periods := 1;
end if;
elsif DWIDTH_RATIO = 4 then
v_num_periods := 2;
else
report dgrb_report_prefix & "unsupported DWIDTH_RATIO." severity failure;
end if;
return v_num_periods;
end function;
-- window for PLL sweep
constant c_max_phase_shifts : natural := rsc_sweep_clk_periods*PLL_STEPS_PER_CYCLE;
constant c_pll_phs_inc : std_logic := '1';
constant c_pll_phs_dec : std_logic := not c_pll_phs_inc;
-- ------------------------------------------------------------------
-- type declarations
-- ------------------------------------------------------------------
-- dgrb main state machine
type t_dgrb_state is (
-- idle state
s_idle,
-- request access to memory address/command bus from the admin block
s_wait_admin,
-- relinquish address/command bus access
s_release_admin,
-- wind back resync phase to a 'zero' point
s_reset_cdvw,
-- perform resync phase sweep (used for MTP alignment checking and actual RRP sweep)
s_test_phases,
-- processing to when checking MTP alignment
s_read_mtp,
-- processing for RRP (read resync phase) sweep
s_seek_cdvw,
-- clock cycle alignment of read data valid signal
s_rdata_valid_align,
-- calculate advertised read latency
s_adv_rd_lat_setup,
s_adv_rd_lat,
-- calculate advertised write latency
s_adv_wd_lat,
-- postamble clock cycle calibration
s_poa_cal,
-- tracking - setup and periodic update
s_track
);
-- dgrb slave state machine for addr/cmd signals
type t_ac_state is (
-- idle state
s_ac_idle,
-- wait X cycles (issuing NOP command) to flush address/command and DQ buses
s_ac_relax,
-- read MTP pattern
s_ac_read_mtp,
-- read pattern for read data valid alignment
s_ac_read_rdv,
-- read pattern for POA calibration
s_ac_read_poa_mtp,
-- read pattern to calculate advertised write latency
s_ac_read_wd_lat
);
-- dgrb slave state machine for read resync phase calibration
type t_resync_state is (
-- idle state
s_rsc_idle,
-- shift resync phase by one
s_rsc_next_phase,
-- start test sequence for current pin and current phase
s_rsc_test_phase,
-- flush the read datapath
s_rsc_wait_for_idle_dimm, -- wait until no longer driving
s_rsc_flush_datapath, -- flush a/c path
-- sample DQ data to test phase
s_rsc_test_dq,
-- reset rsc phase to a zero position
s_rsc_reset_cdvw,
s_rsc_rewind_phase,
-- calculate the centre of resync window
s_rsc_cdvw_calc,
s_rsc_cdvw_wait, -- wait for calc result
-- set rsc clock phase to centre of data valid window
s_rsc_seek_cdvw,
-- wait until all results written to iram
s_rsc_wait_iram -- only entered if GENERATE_ADDITIONAL_DBG_RTL = 1
);
-- record definitions for window processing
type t_win_processing_status is ( calculating,
valid_result,
no_invalid_phases,
multiple_equal_windows,
no_valid_phases
);
type t_window_processing is record
working_window : std_logic_vector( c_max_phase_shifts - 1 downto 0);
first_good_edge : natural range 0 to c_max_phase_shifts - 1; -- pointer to first detected good edge
current_window_start : natural range 0 to c_max_phase_shifts - 1;
current_window_size : natural range 0 to c_max_phase_shifts - 1;
current_window_centre : natural range 0 to c_max_phase_shifts - 1;
largest_window_start : natural range 0 to c_max_phase_shifts - 1;
largest_window_size : natural range 0 to c_max_phase_shifts - 1;
largest_window_centre : natural range 0 to c_max_phase_shifts - 1;
current_bit : natural range 0 to c_max_phase_shifts - 1;
window_centre_update : std_logic;
last_bit_value : std_logic;
valid_phase_seen : boolean;
invalid_phase_seen : boolean;
first_cycle : boolean;
multiple_eq_windows : boolean;
found_a_good_edge : boolean;
status : t_win_processing_status;
windows_seen : natural range 0 to c_max_phase_shifts/2 - 1;
end record;
-- ------------------------------------------------------------------
-- function and procedure definitions
-- ------------------------------------------------------------------
-- Returns a string representation of a std_logic_vector.
-- Not synthesizable.
function str(v: std_logic_vector) return string is
variable str_value : string (1 to v'length);
variable str_len : integer;
variable c : character;
begin
str_len := 1;
for i in v'range loop
case v(i) is
when '0' => c := '0';
when '1' => c := '1';
when others => c := '?';
end case;
str_value(str_len) := c;
str_len := str_len + 1;
end loop;
return str_value;
end str;
-- functions and procedures for window processing
function defaults return t_window_processing is
variable output : t_window_processing;
begin
output.working_window := (others => '1');
output.last_bit_value := '1';
output.first_good_edge := 0;
output.current_window_start := 0;
output.current_window_size := 0;
output.current_window_centre := 0;
output.largest_window_start := 0;
output.largest_window_size := 0;
output.largest_window_centre := 0;
output.window_centre_update := '1';
output.current_bit := 0;
output.multiple_eq_windows := false;
output.valid_phase_seen := false;
output.invalid_phase_seen := false;
output.found_a_good_edge := false;
output.status := no_valid_phases;
output.first_cycle := false;
output.windows_seen := 0;
return output;
end function defaults;
procedure initialise_window_for_proc ( working : inout t_window_processing ) is
variable v_working_window : std_logic_vector( c_max_phase_shifts - 1 downto 0);
begin
v_working_window := working.working_window;
working := defaults;
working.working_window := v_working_window;
working.status := calculating;
working.first_cycle := true;
working.window_centre_update := '1';
working.windows_seen := 0;
end procedure initialise_window_for_proc;
procedure shift_window (working : inout t_window_processing;
num_phases : in natural range 1 to c_max_phase_shifts
)
is
begin
if working.working_window(0) = '0' then
working.invalid_phase_seen := true;
else
working.valid_phase_seen := true;
end if;
-- general bit serial shifting of window and incrementing of current bit counter.
if working.current_bit < num_phases - 1 then
working.current_bit := working.current_bit + 1;
else
working.current_bit := 0;
end if;
working.last_bit_value := working.working_window(0);
working.working_window := working.working_window(0) & working.working_window(working.working_window'high downto 1);
--synopsis translate_off
-- for simulation to make it simpler to see IF we are not using all the bits in the window
working.working_window(working.working_window'high) := 'H'; -- for visual debug
--synopsis translate_on
working.working_window(num_phases -1) := working.last_bit_value;
working.first_cycle := false;
end procedure shift_window;
procedure find_centre_of_largest_data_valid_window
( working : inout t_window_processing;
num_phases : in natural range 1 to c_max_phase_shifts
) is
begin
if working.first_cycle = false then -- not first call to procedure, then handle end conditions
if working.current_bit = 0 and working.found_a_good_edge = false then -- have been all way arround window (circular)
if working.valid_phase_seen = false then
working.status := no_valid_phases;
elsif working.invalid_phase_seen = false then
working.status := no_invalid_phases;
end if;
elsif working.current_bit = working.first_good_edge then -- if have found a good edge then complete a circular sweep to that edge
if working.multiple_eq_windows = true then
working.status := multiple_equal_windows;
else
working.status := valid_result;
end if;
end if;
end if;
-- start of a window condition
if working.last_bit_value = '0' and working.working_window(0) = '1' then
working.current_window_start := working.current_bit;
working.current_window_size := working.current_window_size + 1; -- equivalent to assigning to one because if not in a window then it is set to 0
working.window_centre_update := not working.window_centre_update;
working.current_window_centre := working.current_bit;
if working.found_a_good_edge /= true then -- if have not yet found a good edge then store this value
working.first_good_edge := working.current_bit;
working.found_a_good_edge := true;
end if;
-- end of window conditions
elsif working.last_bit_value = '1' and working.working_window(0) = '0' then
if working.current_window_size > working.largest_window_size then
working.largest_window_size := working.current_window_size;
working.largest_window_start := working.current_window_start;
working.largest_window_centre := working.current_window_centre;
working.multiple_eq_windows := false;
elsif working.current_window_size = working.largest_window_size then
working.multiple_eq_windows := true;
end if;
-- put counter in here because start of window 1 is observed twice
if working.found_a_good_edge = true then
working.windows_seen := working.windows_seen + 1;
end if;
working.current_window_size := 0;
elsif working.last_bit_value = '1' and working.working_window(0) = '1' and (working.found_a_good_edge = true) then --note operand in brackets is excessive but for may provide power savings and makes visual inspection of simulatuion easier
if working.window_centre_update = '1' then
if working.current_window_centre < num_phases -1 then
working.current_window_centre := working.current_window_centre + 1;
else
working.current_window_centre := 0;
end if;
end if;
working.window_centre_update := not working.window_centre_update;
working.current_window_size := working.current_window_size + 1;
end if;
shift_window(working,num_phases);
end procedure find_centre_of_largest_data_valid_window;
procedure find_last_failing_phase
( working : inout t_window_processing;
num_phases : in natural range 1 to c_max_phase_shifts + 1
) is
begin
if working.first_cycle = false then -- not first call to procedure
if working.current_bit = 0 then -- and working.found_a_good_edge = false then
if working.valid_phase_seen = false then
working.status := no_valid_phases;
elsif working.invalid_phase_seen = false then
working.status := no_invalid_phases;
else
working.status := valid_result;
end if;
end if;
end if;
if working.working_window(1) = '1' and working.working_window(0) = '0' and working.status = calculating then
working.current_window_start := working.current_bit;
end if;
shift_window(working, num_phases); -- shifts window and sets first_cycle = false
end procedure find_last_failing_phase;
procedure find_first_passing_phase
( working : inout t_window_processing;
num_phases : in natural range 1 to c_max_phase_shifts
) is
begin
if working.first_cycle = false then -- not first call to procedure
if working.current_bit = 0 then -- and working.found_a_good_edge = false then
if working.valid_phase_seen = false then
working.status := no_valid_phases;
elsif working.invalid_phase_seen = false then
working.status := no_invalid_phases;
else
working.status := valid_result;
end if;
end if;
end if;
if working.working_window(0) = '1' and working.last_bit_value = '0' and working.status = calculating then
working.current_window_start := working.current_bit;
end if;
shift_window(working, num_phases); -- shifts window and sets first_cycle = false
end procedure find_first_passing_phase;
-- shift in current pass/fail result to the working window
procedure shift_in(
working : inout t_window_processing;
status : in std_logic;
num_phases : in natural range 1 to c_max_phase_shifts
) is
begin
working.last_bit_value := working.working_window(0);
working.working_window(num_phases-1 downto 0) := (working.working_window(0) and status) & working.working_window(num_phases-1 downto 1);
end procedure;
-- The following function sets the width over which
-- write latency should be repeated on the dq bus
-- the default value is MEM_IF_DQ_PER_DQS
function set_wlat_dq_rep_width return natural is
begin
for i in 1 to MEM_IF_DWIDTH/MEM_IF_DQ_PER_DQS loop
if (i*MEM_IF_DQ_PER_DQS) >= ADV_LAT_WIDTH then
return i*MEM_IF_DQ_PER_DQS;
end if;
end loop;
report dgrb_report_prefix & "the specified maximum write latency cannot be fully represented in the given number of DQ pins" & LF &
"** NOTE: This may cause overflow when setting ctl_wlat signal" severity warning;
return MEM_IF_DQ_PER_DQS;
end function;
-- extract PHY 'addr/cmd' to 'wdata_valid' write latency from current read data
function wd_lat_from_rdata(signal rdata : in std_logic_vector(DWIDTH_RATIO * MEM_IF_DWIDTH - 1 downto 0))
return std_logic_vector is
variable v_wd_lat : std_logic_vector(ADV_LAT_WIDTH - 1 downto 0);
begin
v_wd_lat := (others => '0');
if set_wlat_dq_rep_width >= ADV_LAT_WIDTH then
v_wd_lat := rdata(v_wd_lat'high downto 0);
else
v_wd_lat := (others => '0');
v_wd_lat(set_wlat_dq_rep_width - 1 downto 0) := rdata(set_wlat_dq_rep_width - 1 downto 0);
end if;
return v_wd_lat;
end function;
-- check if rdata_valid is correctly aligned
function rdata_valid_aligned(
signal rdata : in std_logic_vector(DWIDTH_RATIO * MEM_IF_DWIDTH - 1 downto 0);
signal rdata_valid : in std_logic_vector(DWIDTH_RATIO/2 - 1 downto 0)
) return std_logic is
variable v_dq_rdata : std_logic_vector(DWIDTH_RATIO - 1 downto 0);
variable v_aligned : std_logic;
begin
-- Look at data from a single DQ pin 0 (DWIDTH_RATIO data bits)
for i in 0 to DWIDTH_RATIO - 1 loop
v_dq_rdata(i) := rdata(i*MEM_IF_DWIDTH);
end loop;
-- Check each alignment (necessary because in the HR case rdata can be in any alignment)
v_aligned := '0';
for i in 0 to DWIDTH_RATIO/2 - 1 loop
if rdata_valid(i) = '1' then
if v_dq_rdata(2*i + 1 downto 2*i) = "00" then
v_aligned := '1';
end if;
end if;
end loop;
return v_aligned;
end function;
-- set severity level for calibration failures
function set_cal_fail_sev_level (
generate_additional_debug_rtl : natural
) return severity_level is
begin
if generate_additional_debug_rtl = 1 then
return warning;
else
return failure;
end if;
end function;
constant cal_fail_sev_level : severity_level := set_cal_fail_sev_level(GENERATE_ADDITIONAL_DBG_RTL);
-- ------------------------------------------------------------------
-- signal declarations
-- rsc = resync - the mechanism of capturing DQ pin data onto a local clock domain
-- trk = tracking - a mechanism to track rsc clock phase with PVT variations
-- poa = postamble - protection circuitry from postamble glitched on DQS
-- ac = memory address / command signals
-- ------------------------------------------------------------------
-- main state machine
signal sig_dgrb_state : t_dgrb_state;
signal sig_dgrb_last_state : t_dgrb_state;
signal sig_rsc_req : t_resync_state; -- tells resync block which state to transition to.
-- centre of data-valid window process
signal sig_cdvw_state : t_window_processing;
-- control signals for the address/command process
signal sig_addr_cmd : t_addr_cmd_vector(0 to (DWIDTH_RATIO/2)-1);
signal sig_ac_req : t_ac_state;
signal sig_dimm_driving_dq : std_logic;
signal sig_doing_rd : std_logic_vector(MEM_IF_DQS_WIDTH * DWIDTH_RATIO/2 - 1 downto 0);
signal sig_ac_even : std_logic; -- odd/even count of PHY clock cycles.
--
-- sig_ac_even behaviour
--
-- sig_ac_even is always '1' on the cycle a command is issued. It will
-- be '1' on even clock cycles thereafter and '0' otherwise.
--
-- ; ; ; ; ; ;
-- ; _______ ; ; ; ; ;
-- XXXXX / \ XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
-- addr/cmd XXXXXX CMD XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
-- XXXXX \_______/ XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- _________ _________ _________
-- sig_ac_even ____| |_________| |_________| |__________
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- phy clk
-- count (0) (1) (2) (3) (4)
--
--
-- resync related signals
signal sig_rsc_ack : std_logic;
signal sig_rsc_err : std_logic;
signal sig_rsc_result : std_logic_vector(c_command_result_len - 1 downto 0 );
signal sig_rsc_cdvw_phase : std_logic;
signal sig_rsc_cdvw_shift_in : std_logic;
signal sig_rsc_cdvw_calc : std_logic;
signal sig_rsc_pll_start_reconfig : std_logic;
signal sig_rsc_pll_inc_dec_n : std_logic;
signal sig_rsc_ac_access_req : std_logic; -- High when the resync block requires a training pattern to be read.
-- tracking related signals
signal sig_trk_ack : std_logic;
signal sig_trk_err : std_logic;
signal sig_trk_result : std_logic_vector(c_command_result_len - 1 downto 0 );
signal sig_trk_cdvw_phase : std_logic;
signal sig_trk_cdvw_shift_in : std_logic;
signal sig_trk_cdvw_calc : std_logic;
signal sig_trk_pll_start_reconfig : std_logic;
signal sig_trk_pll_select : std_logic_vector(CLOCK_INDEX_WIDTH - 1 DOWNTO 0);
signal sig_trk_pll_inc_dec_n : std_logic;
signal sig_trk_rsc_drift : integer range -c_max_rsc_drift_in_phases to c_max_rsc_drift_in_phases; -- stores total change in rsc phase from first calibration
-- phs_shft_busy could (potentially) be asynchronous
-- triple register it for metastability hardening
-- these signals are the taps on the shift register
signal sig_phs_shft_busy : std_logic;
signal sig_phs_shft_busy_1t : std_logic;
signal sig_phs_shft_start : std_logic;
signal sig_phs_shft_end : std_logic;
-- locally register crl_dgrb to minimise fan out
signal ctrl_dgrb_r : t_ctrl_command;
-- command_op signals
signal current_cs : natural range 0 to MEM_IF_NUM_RANKS - 1;
signal current_mtp_almt : natural range 0 to 1;
signal single_bit_cal : std_logic;
-- codvw status signals (packed into record and sent to mmi block)
signal cal_codvw_phase : std_logic_vector(7 downto 0);
signal codvw_trk_shift : std_logic_vector(11 downto 0);
signal cal_codvw_size : std_logic_vector(7 downto 0);
-- error signal and result from main state machine (operations other than rsc or tracking)
signal sig_cmd_err : std_logic;
signal sig_cmd_result : std_logic_vector(c_command_result_len - 1 downto 0 );
-- signals that the training pattern matched correctly on the last clock
-- cycle.
signal sig_dq_pin_ctr : natural range 0 to MEM_IF_DWIDTH - 1;
signal sig_mtp_match : std_logic;
-- controls postamble match and timing.
signal sig_poa_match_en : std_logic;
signal sig_poa_match : std_logic;
-- postamble signals
signal sig_poa_ack : std_logic; -- '1' for postamble block to acknowledge.
-- calibration byte lane select
signal cal_byte_lanes : std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
signal codvw_grt_one_dvw : std_logic;
begin
doing_rd <= sig_doing_rd;
-- pack record of codvw status signals
dgrb_mmi.cal_codvw_phase <= cal_codvw_phase;
dgrb_mmi.codvw_trk_shift <= codvw_trk_shift;
dgrb_mmi.cal_codvw_size <= cal_codvw_size;
dgrb_mmi.codvw_grt_one_dvw <= codvw_grt_one_dvw;
-- map some internal signals to outputs
dgrb_ac <= sig_addr_cmd;
-- locally register crl_dgrb to minimise fan out
process (clk, rst_n)
begin
if rst_n = '0' then
ctrl_dgrb_r <= defaults;
elsif rising_edge(clk) then
ctrl_dgrb_r <= ctrl_dgrb;
end if;
end process;
-- generate the current_cs signal to track which cs accessed by PHY at any instance
current_cs_proc : process (clk, rst_n)
begin
if rst_n = '0' then
current_cs <= 0;
current_mtp_almt <= 0;
single_bit_cal <= '0';
cal_byte_lanes <= (others => '0');
elsif rising_edge(clk) then
if ctrl_dgrb_r.command_req = '1' then
current_cs <= ctrl_dgrb_r.command_op.current_cs;
current_mtp_almt <= ctrl_dgrb_r.command_op.mtp_almt;
single_bit_cal <= ctrl_dgrb_r.command_op.single_bit;
end if;
-- mux byte lane select for given chip select
for i in 0 to MEM_IF_DQS_WIDTH - 1 loop
cal_byte_lanes(i) <= ctl_cal_byte_lanes((current_cs * MEM_IF_DQS_WIDTH) + i);
end loop;
assert ctl_cal_byte_lanes(0) = '1' report dgrb_report_prefix & " Byte lane 0 (chip select 0) disable is not supported - ending simulation" severity failure;
end if;
end process;
-- ------------------------------------------------------------------
-- main state machine for dgrb architecture
--
-- process of commands from control (ctrl) block and overall control of
-- the subsequent calibration processing functions
-- also communicates completion and any errors back to the ctrl block
-- read data valid alignment and advertised latency calculations are
-- included in this block
-- ------------------------------------------------------------------
dgrb_main_block : block
signal sig_count : natural range 0 to 2**8 - 1;
signal sig_wd_lat : std_logic_vector(ADV_LAT_WIDTH - 1 downto 0);
begin
dgrb_state_proc : process(rst_n, clk)
begin
if rst_n = '0' then
-- initialise state
sig_dgrb_state <= s_idle;
sig_dgrb_last_state <= s_idle;
sig_ac_req <= s_ac_idle;
sig_rsc_req <= s_rsc_idle;
-- set up rd_lat defaults
rd_lat <= c_default_rd_lat_slv;
wd_lat <= c_default_wd_lat_slv;
-- set up rdata_valid latency control defaults
seq_rdata_valid_lat_inc <= '0';
seq_rdata_valid_lat_dec <= '0';
-- reset counter
sig_count <= 0;
-- error signals
sig_cmd_err <= '0';
sig_cmd_result <= (others => '0');
-- sig_wd_lat
sig_wd_lat <= (others => '0');
-- status of the ac_nt alignment
dgrb_ctrl_ac_nt_good <= '1';
elsif rising_edge(clk) then
sig_dgrb_last_state <= sig_dgrb_state;
sig_rsc_req <= s_rsc_idle;
-- set up rdata_valid latency control defaults
seq_rdata_valid_lat_inc <= '0';
seq_rdata_valid_lat_dec <= '0';
-- error signals
sig_cmd_err <= '0';
sig_cmd_result <= (others => '0');
-- register wd_lat output.
wd_lat <= sig_wd_lat;
case sig_dgrb_state is
when s_idle =>
sig_count <= 0;
if ctrl_dgrb_r.command_req = '1' then
if curr_active_block(ctrl_dgrb_r.command) = dgrb then
sig_dgrb_state <= s_wait_admin;
end if;
end if;
sig_ac_req <= s_ac_idle;
when s_wait_admin =>
sig_dgrb_state <= s_wait_admin;
case ctrl_dgrb_r.command is
when cmd_read_mtp => sig_dgrb_state <= s_read_mtp;
when cmd_rrp_reset => sig_dgrb_state <= s_reset_cdvw;
when cmd_rrp_sweep => sig_dgrb_state <= s_test_phases;
when cmd_rrp_seek => sig_dgrb_state <= s_seek_cdvw;
when cmd_rdv => sig_dgrb_state <= s_rdata_valid_align;
when cmd_prep_adv_rd_lat => sig_dgrb_state <= s_adv_rd_lat_setup;
when cmd_prep_adv_wr_lat => sig_dgrb_state <= s_adv_wd_lat;
when cmd_tr_due => sig_dgrb_state <= s_track;
when cmd_poa => sig_dgrb_state <= s_poa_cal;
when others =>
report dgrb_report_prefix & "unknown command" severity failure;
sig_dgrb_state <= s_idle;
end case;
when s_reset_cdvw =>
-- the cdvw proc watches for this state and resets the cdvw
-- state block.
if sig_rsc_ack = '1' then
sig_dgrb_state <= s_release_admin;
else
sig_rsc_req <= s_rsc_reset_cdvw;
end if;
when s_test_phases =>
if sig_rsc_ack = '1' then
sig_dgrb_state <= s_release_admin;
else
sig_rsc_req <= s_rsc_test_phase;
if sig_rsc_ac_access_req = '1' then
sig_ac_req <= s_ac_read_mtp;
else
sig_ac_req <= s_ac_idle;
end if;
end if;
when s_seek_cdvw | s_read_mtp =>
if sig_rsc_ack = '1' then
sig_dgrb_state <= s_release_admin;
else
sig_rsc_req <= s_rsc_cdvw_calc;
end if;
when s_release_admin =>
sig_ac_req <= s_ac_idle;
if dgrb_ac_access_gnt = '0' and sig_dimm_driving_dq = '0' then
sig_dgrb_state <= s_idle;
end if;
when s_rdata_valid_align =>
sig_ac_req <= s_ac_read_rdv;
seq_rdata_valid_lat_dec <= '0';
seq_rdata_valid_lat_inc <= '0';
if sig_dimm_driving_dq = '1' then
-- only do comparison if rdata_valid is all 'ones'
if rdata_valid /= std_logic_vector(to_unsigned(0, DWIDTH_RATIO/2)) then
-- rdata_valid is all ones
if rdata_valid_aligned(rdata, rdata_valid) = '1' then
-- success: rdata_valid and rdata are properly aligned
sig_dgrb_state <= s_release_admin;
else
-- misaligned: bring in rdata_valid by a clock cycle
seq_rdata_valid_lat_dec <= '1';
end if;
end if;
end if;
when s_adv_rd_lat_setup =>
-- wait for sig_doing_rd to go high
sig_ac_req <= s_ac_read_rdv;
if sig_dgrb_state /= sig_dgrb_last_state then
rd_lat <= (others => '0');
sig_count <= 0;
elsif sig_dimm_driving_dq = '1' and sig_doing_rd(MEM_IF_DQS_WIDTH*(DWIDTH_RATIO/2-1)) = '1' then
-- a read has started: start counter
sig_dgrb_state <= s_adv_rd_lat;
end if;
when s_adv_rd_lat =>
sig_ac_req <= s_ac_read_rdv;
if sig_dimm_driving_dq = '1' then
if sig_count >= 2**rd_lat'length then
report dgrb_report_prefix & "maximum read latency exceeded while waiting for rdata_valid" severity cal_fail_sev_level;
sig_cmd_err <= '1';
sig_cmd_result <= std_logic_vector(to_unsigned(C_ERR_MAX_RD_LAT_EXCEEDED,sig_cmd_result'length));
end if;
if rdata_valid /= std_logic_vector(to_unsigned(0, rdata_valid'length)) then
-- have found the read latency
sig_dgrb_state <= s_release_admin;
else
sig_count <= sig_count + 1;
end if;
rd_lat <= std_logic_vector(to_unsigned(sig_count, rd_lat'length));
end if;
when s_adv_wd_lat =>
sig_ac_req <= s_ac_read_wd_lat;
if sig_dgrb_state /= sig_dgrb_last_state then
sig_wd_lat <= (others => '0');
else
if sig_dimm_driving_dq = '1' and rdata_valid /= std_logic_vector(to_unsigned(0, rdata_valid'length)) then
-- construct wd_lat using data from the lowest addresses
-- wd_lat <= rdata(MEM_IF_DQ_PER_DQS - 1 downto 0);
sig_wd_lat <= wd_lat_from_rdata(rdata);
sig_dgrb_state <= s_release_admin;
-- check data integrity
for i in 1 to MEM_IF_DWIDTH/set_wlat_dq_rep_width - 1 loop
-- wd_lat is copied across MEM_IF_DWIDTH bits in fields of width MEM_IF_DQ_PER_DQS.
-- All of these fields must have the same value or it is an error.
-- only check if byte lane not disabled
if cal_byte_lanes((i*set_wlat_dq_rep_width)/MEM_IF_DQ_PER_DQS) = '1' then
if rdata(set_wlat_dq_rep_width - 1 downto 0) /= rdata((i+1)*set_wlat_dq_rep_width - 1 downto i*set_wlat_dq_rep_width) then
-- signal write latency different between DQS groups
report dgrb_report_prefix & "the write latency read from memory is different accross dqs groups" severity cal_fail_sev_level;
sig_cmd_err <= '1';
sig_cmd_result <= std_logic_vector(to_unsigned(C_ERR_WD_LAT_DISAGREEMENT, sig_cmd_result'length));
end if;
end if;
end loop;
-- check if ac_nt alignment is ok
-- in this condition all DWIDTH_RATIO copies of rdata should be identical
dgrb_ctrl_ac_nt_good <= '1';
if DWIDTH_RATIO /= 2 then
for j in 0 to DWIDTH_RATIO/2 - 1 loop
if rdata(j*MEM_IF_DWIDTH + MEM_IF_DQ_PER_DQS - 1 downto j*MEM_IF_DWIDTH) /= rdata((j+2)*MEM_IF_DWIDTH + MEM_IF_DQ_PER_DQS - 1 downto (j+2)*MEM_IF_DWIDTH) then
dgrb_ctrl_ac_nt_good <= '0';
end if;
end loop;
end if;
end if;
end if;
when s_poa_cal =>
-- Request the address/command block begins reading the "M"
-- training pattern here. There is no provision for doing
-- refreshes so this limits the time spent in this state
-- to 9 x tREFI (by the DDR2 JEDEC spec). Instead of the
-- maximum value, a maximum "safe" time in this postamble
-- state is chosen to be tpoamax = 5 x tREFI = 5 x 3.9us.
-- When entering this s_poa_cal state it must be guaranteed
-- that the number of stacked refreshes is at maximum.
--
-- Minimum clock freq supported by DRAM is fck,min=125MHz.
-- Each adjustment to postamble latency requires 16*clock
-- cycles (time to read "M" training pattern twice) so
-- maximum number of adjustments to POA latency (n) is:
--
-- n = (5 x trefi x fck,min) / 16
-- = (5 x 3.9us x 125MHz) / 16
-- ~ 152
--
-- Postamble latency must be adjusted less than 152 cycles
-- to meet this requirement.
--
sig_ac_req <= s_ac_read_poa_mtp;
if sig_poa_ack = '1' then
sig_dgrb_state <= s_release_admin;
end if;
when s_track =>
if sig_trk_ack = '1' then
sig_dgrb_state <= s_release_admin;
end if;
when others => null;
report dgrb_report_prefix & "undefined state" severity failure;
sig_dgrb_state <= s_idle;
end case;
-- default if not calibrating go to idle state via s_release_admin
if ctrl_dgrb_r.command = cmd_idle and
sig_dgrb_state /= s_idle and
sig_dgrb_state /= s_release_admin then
sig_dgrb_state <= s_release_admin;
end if;
end if;
end process;
end block;
-- ------------------------------------------------------------------
-- metastability hardening of potentially async phs_shift_busy signal
--
-- Triple register it for metastability hardening. This process
-- creates the shift register. Also add a sig_phs_shft_busy and
-- an sig_phs_shft_busy_1t echo because various other processes find
-- this useful.
-- ------------------------------------------------------------------
phs_shft_busy_reg: block
signal phs_shft_busy_1r : std_logic;
signal phs_shft_busy_2r : std_logic;
signal phs_shft_busy_3r : std_logic;
begin
phs_shift_busy_sync : process (clk, rst_n)
begin
if rst_n = '0' then
sig_phs_shft_busy <= '0';
sig_phs_shft_busy_1t <= '0';
phs_shft_busy_1r <= '0';
phs_shft_busy_2r <= '0';
phs_shft_busy_3r <= '0';
sig_phs_shft_start <= '0';
sig_phs_shft_end <= '0';
elsif rising_edge(clk) then
sig_phs_shft_busy_1t <= phs_shft_busy_3r;
sig_phs_shft_busy <= phs_shft_busy_2r;
-- register the below to reduce fan out on sig_phs_shft_busy and sig_phs_shft_busy_1t
sig_phs_shft_start <= phs_shft_busy_3r or phs_shft_busy_2r;
sig_phs_shft_end <= phs_shft_busy_3r and not(phs_shft_busy_2r);
phs_shft_busy_3r <= phs_shft_busy_2r;
phs_shft_busy_2r <= phs_shft_busy_1r;
phs_shft_busy_1r <= phs_shft_busy;
end if;
end process;
end block;
-- ------------------------------------------------------------------
-- PLL reconfig MUX
--
-- switches PLL Reconfig input between tracking and resync blocks
-- ------------------------------------------------------------------
pll_reconf_mux : process (clk, rst_n)
begin
if rst_n = '0' then
seq_pll_inc_dec_n <= '0';
seq_pll_select <= (others => '0');
seq_pll_start_reconfig <= '0';
elsif rising_edge(clk) then
if sig_dgrb_state = s_seek_cdvw or
sig_dgrb_state = s_test_phases or
sig_dgrb_state = s_reset_cdvw then
seq_pll_select <= pll_resync_clk_index;
seq_pll_inc_dec_n <= sig_rsc_pll_inc_dec_n;
seq_pll_start_reconfig <= sig_rsc_pll_start_reconfig;
elsif sig_dgrb_state = s_track then
seq_pll_select <= sig_trk_pll_select;
seq_pll_inc_dec_n <= sig_trk_pll_inc_dec_n;
seq_pll_start_reconfig <= sig_trk_pll_start_reconfig;
else
seq_pll_select <= pll_measure_clk_index;
seq_pll_inc_dec_n <= '0';
seq_pll_start_reconfig <= '0';
end if;
end if;
end process;
-- ------------------------------------------------------------------
-- Centre of data valid window calculation block
--
-- This block handles the sharing of the centre of window calculation
-- logic between the rsc and trk operations. Functions defined in the
-- header of this entity are called to do this.
-- ------------------------------------------------------------------
cdvw_block : block
signal sig_cdvw_calc_1t : std_logic;
begin
-- purpose: manages centre of data valid window calculations
-- type : sequential
-- inputs : clk, rst_n
-- outputs: sig_cdvw_state
cdvw_proc: process (clk, rst_n)
variable v_cdvw_state : t_window_processing;
variable v_start_calc : std_logic;
variable v_shift_in : std_logic;
variable v_phase : std_logic;
begin -- process cdvw_proc
if rst_n = '0' then -- asynchronous reset (active low)
sig_cdvw_state <= defaults;
sig_cdvw_calc_1t <= '0';
elsif rising_edge(clk) then -- rising clock edge
v_cdvw_state := sig_cdvw_state;
case sig_dgrb_state is
when s_track =>
v_start_calc := sig_trk_cdvw_calc;
v_phase := sig_trk_cdvw_phase;
v_shift_in := sig_trk_cdvw_shift_in;
when s_read_mtp | s_seek_cdvw | s_test_phases =>
v_start_calc := sig_rsc_cdvw_calc;
v_phase := sig_rsc_cdvw_phase;
v_shift_in := sig_rsc_cdvw_shift_in;
when others =>
v_start_calc := '0';
v_phase := '0';
v_shift_in := '0';
end case;
if sig_dgrb_state = s_reset_cdvw or (sig_dgrb_state = s_track and sig_dgrb_last_state /= s_track) then
-- reset *C*entre of *D*ata *V*alid *W*indow
v_cdvw_state := defaults;
elsif sig_cdvw_calc_1t /= '1' and v_start_calc = '1' then
initialise_window_for_proc(v_cdvw_state);
elsif v_cdvw_state.status = calculating then
if sig_dgrb_state = s_track then -- ensure 360 degrees sweep
find_centre_of_largest_data_valid_window(v_cdvw_state, PLL_STEPS_PER_CYCLE);
else -- can be a 720 degrees sweep
find_centre_of_largest_data_valid_window(v_cdvw_state, c_max_phase_shifts);
end if;
elsif v_shift_in = '1' then
if sig_dgrb_state = s_track then -- ensure 360 degrees sweep
shift_in(v_cdvw_state, v_phase, PLL_STEPS_PER_CYCLE);
else
shift_in(v_cdvw_state, v_phase, c_max_phase_shifts);
end if;
end if;
sig_cdvw_calc_1t <= v_start_calc;
sig_cdvw_state <= v_cdvw_state;
end if;
end process cdvw_proc;
end block;
-- ------------------------------------------------------------------
-- block for resync calculation.
--
-- This block implements the following:
-- 1) Control logic for the rsc slave state machine
-- 2) Processing of resync operations - through reports form cdvw block and
-- test pattern match blocks
-- 3) Shifting of the resync phase for rsc sweeps
-- 4) Writing of results to iram (optional)
-- ------------------------------------------------------------------
rsc_block : block
signal sig_rsc_state : t_resync_state;
signal sig_rsc_last_state : t_resync_state;
signal sig_num_phase_shifts : natural range c_max_phase_shifts - 1 downto 0;
signal sig_rewind_direction : std_logic;
signal sig_count : natural range 0 to 2**8 - 1;
signal sig_test_dq_expired : std_logic;
signal sig_chkd_all_dq_pins : std_logic;
-- prompts to write data to iram
signal sig_dgrb_iram : t_iram_push; -- internal copy of dgrb to iram control signals
signal sig_rsc_push_rrp_sweep : std_logic; -- push result of a rrp sweep pass (for cmd_rrp_sweep)
signal sig_rsc_push_rrp_pass : std_logic; -- result of a rrp sweep result (for cmd_rrp_sweep)
signal sig_rsc_push_rrp_seek : std_logic; -- write seek results (for cmd_rrp_seek / cmd_read_mtp states)
signal sig_rsc_push_footer : std_logic; -- write a footer
signal sig_dq_pin_ctr_r : natural range 0 to MEM_IF_DWIDTH - 1; -- registered version of dq_pin_ctr
signal sig_rsc_curr_phase : natural range 0 to c_max_phase_shifts - 1; -- which phase is being processed
signal sig_iram_idle : std_logic; -- track if iram currently writing data
signal sig_mtp_match_en : std_logic;
-- current byte lane disabled?
signal sig_curr_byte_ln_dis : std_logic;
signal sig_iram_wds_req : integer; -- words required for a given iram dump (used to locate where to write footer)
begin
-- When using DQS capture or not at full-rate only match on "even" clock cycles.
sig_mtp_match_en <= active_high(sig_ac_even = '1' or MEM_IF_DQS_CAPTURE = 0 or DWIDTH_RATIO /= 2);
-- register current byte lane disable mux for speed
byte_lane_dis: process (clk, rst_n)
begin
if rst_n = '0' then
sig_curr_byte_ln_dis <= '0';
elsif rising_edge(clk) then
sig_curr_byte_ln_dis <= cal_byte_lanes(sig_dq_pin_ctr/MEM_IF_DQ_PER_DQS);
end if;
end process;
-- check if all dq pins checked in rsc sweep
chkd_dq : process (clk, rst_n)
begin
if rst_n = '0' then
sig_chkd_all_dq_pins <= '0';
elsif rising_edge(clk) then
if sig_dq_pin_ctr = 0 then
sig_chkd_all_dq_pins <= '1';
else
sig_chkd_all_dq_pins <= '0';
end if;
end if;
end process;
-- main rsc process
rsc_proc : process (clk, rst_n)
-- these are temporary variables which should not infer FFs and
-- are not guaranteed to be initialized by s_rsc_idle.
variable v_rdata_correct : std_logic;
variable v_phase_works : std_logic;
begin
if rst_n = '0' then
-- initialise signals
sig_rsc_state <= s_rsc_idle;
sig_rsc_last_state <= s_rsc_idle;
sig_dq_pin_ctr <= 0;
sig_num_phase_shifts <= c_max_phase_shifts - 1; -- want c_max_phase_shifts-1 inc / decs of phase
sig_count <= 0;
sig_test_dq_expired <= '0';
v_phase_works := '0';
-- interface to other processes to tell them when we are done.
sig_rsc_ack <= '0';
sig_rsc_err <= '0';
sig_rsc_result <= std_logic_vector(to_unsigned(C_SUCCESS, c_command_result_len));
-- centre of data valid window functions
sig_rsc_cdvw_phase <= '0';
sig_rsc_cdvw_shift_in <= '0';
sig_rsc_cdvw_calc <= '0';
-- set up PLL reconfig interface controls
sig_rsc_pll_start_reconfig <= '0';
sig_rsc_pll_inc_dec_n <= c_pll_phs_inc;
sig_rewind_direction <= c_pll_phs_dec;
-- True when access to the ac_block is required.
sig_rsc_ac_access_req <= '0';
-- default values on centre and size of data valid window
if SIM_TIME_REDUCTIONS = 1 then
cal_codvw_phase <= std_logic_vector(to_unsigned(PRESET_CODVW_PHASE, 8));
cal_codvw_size <= std_logic_vector(to_unsigned(PRESET_CODVW_SIZE, 8));
else
cal_codvw_phase <= (others => '0');
cal_codvw_size <= (others => '0');
end if;
sig_rsc_push_rrp_sweep <= '0';
sig_rsc_push_rrp_seek <= '0';
sig_rsc_push_rrp_pass <= '0';
sig_rsc_push_footer <= '0';
codvw_grt_one_dvw <= '0';
elsif rising_edge(clk) then
-- default values assigned to some signals
sig_rsc_ack <= '0';
sig_rsc_cdvw_phase <= '0';
sig_rsc_cdvw_shift_in <= '0';
sig_rsc_cdvw_calc <= '0';
sig_rsc_pll_start_reconfig <= '0';
sig_rsc_pll_inc_dec_n <= c_pll_phs_inc;
sig_rewind_direction <= c_pll_phs_dec;
-- by default don't ask the resync block to read anything
sig_rsc_ac_access_req <= '0';
sig_rsc_push_rrp_sweep <= '0';
sig_rsc_push_rrp_seek <= '0';
sig_rsc_push_rrp_pass <= '0';
sig_rsc_push_footer <= '0';
sig_test_dq_expired <= '0';
-- resync state machine
case sig_rsc_state is
when s_rsc_idle =>
-- initialize those signals we are ready to use.
sig_dq_pin_ctr <= 0;
sig_count <= 0;
if sig_rsc_state = sig_rsc_last_state then -- avoid transition when acknowledging a command has finished
if sig_rsc_req = s_rsc_test_phase then
sig_rsc_state <= s_rsc_test_phase;
elsif sig_rsc_req = s_rsc_cdvw_calc then
sig_rsc_state <= s_rsc_cdvw_calc;
elsif sig_rsc_req = s_rsc_seek_cdvw then
sig_rsc_state <= s_rsc_seek_cdvw;
elsif sig_rsc_req = s_rsc_reset_cdvw then
sig_rsc_state <= s_rsc_reset_cdvw;
else
sig_rsc_state <= s_rsc_idle;
end if;
end if;
when s_rsc_next_phase =>
sig_rsc_pll_inc_dec_n <= c_pll_phs_inc;
sig_rsc_pll_start_reconfig <= '1';
if sig_phs_shft_start = '1' then
-- PLL phase shift started - so stop requesting a shift
sig_rsc_pll_start_reconfig <= '0';
end if;
if sig_phs_shft_end = '1' then
-- PLL phase shift finished - so proceed to flush the datapath
sig_num_phase_shifts <= sig_num_phase_shifts - 1;
sig_rsc_state <= s_rsc_test_phase;
end if;
when s_rsc_test_phase =>
v_phase_works := '1';
-- Note: For single pin single CS calibration set sig_dq_pin_ctr to 0 to
-- ensure that only 1 pin calibrated
sig_rsc_state <= s_rsc_wait_for_idle_dimm;
if single_bit_cal = '1' then
sig_dq_pin_ctr <= 0;
else
sig_dq_pin_ctr <= MEM_IF_DWIDTH-1;
end if;
when s_rsc_wait_for_idle_dimm =>
if sig_dimm_driving_dq = '0' then
sig_rsc_state <= s_rsc_flush_datapath;
end if;
when s_rsc_flush_datapath =>
sig_rsc_ac_access_req <= '1';
if sig_rsc_state /= sig_rsc_last_state then
-- reset variables we are interested in when we first arrive in this state.
sig_count <= c_max_read_lat - 1;
else
if sig_dimm_driving_dq = '1' then
if sig_count = 0 then
sig_rsc_state <= s_rsc_test_dq;
else
sig_count <= sig_count - 1;
end if;
end if;
end if;
when s_rsc_test_dq =>
sig_rsc_ac_access_req <= '1';
if sig_rsc_state /= sig_rsc_last_state then
-- reset variables we are interested in when we first arrive in this state.
sig_count <= 2*c_cal_mtp_t;
else
if sig_dimm_driving_dq = '1' then
if (
(sig_mtp_match = '1' and sig_mtp_match_en = '1') or -- have a pattern match
(sig_test_dq_expired = '1') or -- time in this phase has expired.
sig_curr_byte_ln_dis = '0' -- byte lane disabled
) then
v_phase_works := v_phase_works and ((sig_mtp_match and sig_mtp_match_en) or (not sig_curr_byte_ln_dis));
sig_rsc_push_rrp_sweep <= '1';
sig_rsc_push_rrp_pass <= (sig_mtp_match and sig_mtp_match_en) or (not sig_curr_byte_ln_dis);
if sig_chkd_all_dq_pins = '1' then
-- finished checking all dq pins.
-- done checking this phase.
-- shift phase status into
sig_rsc_cdvw_phase <= v_phase_works;
sig_rsc_cdvw_shift_in <= '1';
if sig_num_phase_shifts /= 0 then
-- there are more phases to test so shift to next phase
sig_rsc_state <= s_rsc_next_phase;
else
-- no more phases to check.
-- clean up after ourselves by
-- going into s_rsc_rewind_phase
sig_rsc_state <= s_rsc_rewind_phase;
sig_rewind_direction <= c_pll_phs_dec;
sig_num_phase_shifts <= c_max_phase_shifts - 1;
end if;
else
-- shift to next dq pin
if MEM_IF_DWIDTH > 71 and -- if >= 72 pins then:
(sig_dq_pin_ctr mod 64) = 0 then -- ensure refreshes at least once every 64 pins
sig_rsc_state <= s_rsc_wait_for_idle_dimm;
else -- otherwise continue sweep
sig_rsc_state <= s_rsc_flush_datapath;
end if;
sig_dq_pin_ctr <= sig_dq_pin_ctr - 1;
end if;
else
sig_count <= sig_count - 1;
if sig_count = 1 then
sig_test_dq_expired <= '1';
end if;
end if;
end if;
end if;
when s_rsc_reset_cdvw =>
sig_rsc_state <= s_rsc_rewind_phase;
-- determine the amount to rewind by (may be wind forward depending on tracking behaviour)
if to_integer(unsigned(cal_codvw_phase)) + sig_trk_rsc_drift < 0 then
sig_num_phase_shifts <= - (to_integer(unsigned(cal_codvw_phase)) + sig_trk_rsc_drift);
sig_rewind_direction <= c_pll_phs_inc;
else
sig_num_phase_shifts <= (to_integer(unsigned(cal_codvw_phase)) + sig_trk_rsc_drift);
sig_rewind_direction <= c_pll_phs_dec;
end if;
-- reset the calibrated phase and size to zero (because un-doing prior calibration here)
cal_codvw_phase <= (others => '0');
cal_codvw_size <= (others => '0');
when s_rsc_rewind_phase =>
-- rewinds the resync PLL by sig_num_phase_shifts steps and returns to idle state
if sig_num_phase_shifts = 0 then
-- no more steps to take off, go to next state
sig_num_phase_shifts <= c_max_phase_shifts - 1;
if GENERATE_ADDITIONAL_DBG_RTL = 1 then -- if iram present hold off until access finished
sig_rsc_state <= s_rsc_wait_iram;
else
sig_rsc_ack <= '1';
sig_rsc_state <= s_rsc_idle;
end if;
else
sig_rsc_pll_inc_dec_n <= sig_rewind_direction;
-- request a phase shift
sig_rsc_pll_start_reconfig <= '1';
if sig_phs_shft_busy = '1' then
-- inhibit a phase shift if phase shift is busy.
sig_rsc_pll_start_reconfig <= '0';
end if;
if sig_phs_shft_busy_1t = '1' and sig_phs_shft_busy /= '1' then
-- we've just successfully removed a phase step
-- decrement counter
sig_num_phase_shifts <= sig_num_phase_shifts - 1;
sig_rsc_pll_start_reconfig <= '0';
end if;
end if;
when s_rsc_cdvw_calc =>
if sig_rsc_state /= sig_rsc_last_state then
if sig_dgrb_state = s_read_mtp then
report dgrb_report_prefix & "gathered resync phase samples (for mtp alignment " & natural'image(current_mtp_almt) & ") is DGRB_PHASE_SAMPLES: " & str(sig_cdvw_state.working_window) severity note;
else
report dgrb_report_prefix & "gathered resync phase samples DGRB_PHASE_SAMPLES: " & str(sig_cdvw_state.working_window) severity note;
end if;
sig_rsc_cdvw_calc <= '1'; -- begin calculating result
else
sig_rsc_state <= s_rsc_cdvw_wait;
end if;
when s_rsc_cdvw_wait =>
if sig_cdvw_state.status /= calculating then
-- a result has been reached.
if sig_dgrb_state = s_read_mtp then -- if doing mtp alignment then skip setting phase
if GENERATE_ADDITIONAL_DBG_RTL = 1 then -- if iram present hold off until access finished
sig_rsc_state <= s_rsc_wait_iram;
else
sig_rsc_ack <= '1';
sig_rsc_state <= s_rsc_idle;
end if;
else
if sig_cdvw_state.status = valid_result then
-- calculation successfully found a
-- data-valid window to seek to.
sig_rsc_state <= s_rsc_seek_cdvw;
sig_rsc_result <= std_logic_vector(to_unsigned(C_SUCCESS, sig_rsc_result'length));
-- If more than one data valid window was seen, then set the result code :
if (sig_cdvw_state.windows_seen > 1) then
report dgrb_report_prefix & "Warning : multiple data-valid windows found, largest chosen." severity note;
codvw_grt_one_dvw <= '1';
else
report dgrb_report_prefix & "data-valid window found successfully." severity note;
end if;
else
-- calculation failed to find a data-valid window.
report dgrb_report_prefix & "couldn't find a data-valid window in resync." severity warning;
sig_rsc_ack <= '1';
sig_rsc_err <= '1';
sig_rsc_state <= s_rsc_idle;
-- set resync result code
case sig_cdvw_state.status is
when no_invalid_phases =>
sig_rsc_result <= std_logic_vector(to_unsigned(C_ERR_RESYNC_NO_VALID_PHASES, sig_rsc_result'length));
when multiple_equal_windows =>
sig_rsc_result <= std_logic_vector(to_unsigned(C_ERR_RESYNC_MULTIPLE_EQUAL_WINDOWS, sig_rsc_result'length));
when no_valid_phases =>
sig_rsc_result <= std_logic_vector(to_unsigned(C_ERR_RESYNC_NO_VALID_PHASES, sig_rsc_result'length));
when others =>
sig_rsc_result <= std_logic_vector(to_unsigned(C_ERR_CRITICAL, sig_rsc_result'length));
end case;
end if;
end if;
-- signal to write a rrp_sweep result to iram
if GENERATE_ADDITIONAL_DBG_RTL = 1 then
sig_rsc_push_rrp_seek <= '1';
end if;
end if;
when s_rsc_seek_cdvw =>
if sig_rsc_state /= sig_rsc_last_state then
-- reset variables we are interested in when we first arrive in this state
sig_count <= sig_cdvw_state.largest_window_centre;
else
if sig_count = 0 or
((MEM_IF_DQS_CAPTURE = 1 and DWIDTH_RATIO = 2) and
sig_count = PLL_STEPS_PER_CYCLE) -- if FR and DQS capture ensure within 0-360 degrees phase
then
-- ready to transition to next state
if GENERATE_ADDITIONAL_DBG_RTL = 1 then -- if iram present hold off until access finished
sig_rsc_state <= s_rsc_wait_iram;
else
sig_rsc_ack <= '1';
sig_rsc_state <= s_rsc_idle;
end if;
-- return largest window centre and size in the result
-- perform cal_codvw phase / size update only if a valid result is found
if sig_cdvw_state.status = valid_result then
cal_codvw_phase <= std_logic_vector(to_unsigned(sig_cdvw_state.largest_window_centre, 8));
cal_codvw_size <= std_logic_vector(to_unsigned(sig_cdvw_state.largest_window_size, 8));
end if;
-- leaving sig_rsc_err or sig_rsc_result at
-- their default values (of success)
else
sig_rsc_pll_inc_dec_n <= c_pll_phs_inc;
-- request a phase shift
sig_rsc_pll_start_reconfig <= '1';
if sig_phs_shft_start = '1' then
-- inhibit a phase shift if phase shift is busy
sig_rsc_pll_start_reconfig <= '0';
end if;
if sig_phs_shft_end = '1' then
-- we've just successfully removed a phase step
-- decrement counter
sig_count <= sig_count - 1;
end if;
end if;
end if;
when s_rsc_wait_iram =>
-- hold off check 1 clock cycle to enable last rsc push operations to start
if sig_rsc_state = sig_rsc_last_state then
if sig_iram_idle = '1' then
sig_rsc_ack <= '1';
sig_rsc_state <= s_rsc_idle;
if sig_dgrb_state = s_test_phases or
sig_dgrb_state = s_seek_cdvw or
sig_dgrb_state = s_read_mtp then
sig_rsc_push_footer <= '1';
end if;
end if;
end if;
when others =>
null;
end case;
sig_rsc_last_state <= sig_rsc_state;
end if;
end process;
-- write results to the iram
iram_push: process (clk, rst_n)
begin
if rst_n = '0' then
sig_dgrb_iram <= defaults;
sig_iram_idle <= '0';
sig_dq_pin_ctr_r <= 0;
sig_rsc_curr_phase <= 0;
sig_iram_wds_req <= 0;
elsif rising_edge(clk) then
if GENERATE_ADDITIONAL_DBG_RTL = 1 then
if sig_dgrb_iram.iram_write = '1' and sig_dgrb_iram.iram_done = '1' then
report dgrb_report_prefix & "iram_done and iram_write signals concurrently set - iram contents may be corrupted" severity failure;
end if;
if sig_dgrb_iram.iram_write = '0' and sig_dgrb_iram.iram_done = '0' then
sig_iram_idle <= '1';
else
sig_iram_idle <= '0';
end if;
-- registered sig_dq_pin_ctr to align with rrp_sweep result
sig_dq_pin_ctr_r <= sig_dq_pin_ctr;
-- calculate current phase (registered to align with rrp_sweep result)
sig_rsc_curr_phase <= (c_max_phase_shifts - 1) - sig_num_phase_shifts;
-- serial push of rrp_sweep results into memory
if sig_rsc_push_rrp_sweep = '1' then
-- signal an iram write and track a write pending
sig_dgrb_iram.iram_write <= '1';
sig_iram_idle <= '0';
-- if not single_bit_cal then pack pin phase results in MEM_IF_DWIDTH word blocks
if single_bit_cal = '1' then
sig_dgrb_iram.iram_wordnum <= sig_dq_pin_ctr_r + (sig_rsc_curr_phase/32);
sig_iram_wds_req <= iram_wd_for_one_pin_rrp( DWIDTH_RATIO, PLL_STEPS_PER_CYCLE, MEM_IF_DWIDTH, MEM_IF_DQS_CAPTURE); -- note total word requirement
else
sig_dgrb_iram.iram_wordnum <= sig_dq_pin_ctr_r + (sig_rsc_curr_phase/32) * MEM_IF_DWIDTH;
sig_iram_wds_req <= iram_wd_for_full_rrp( DWIDTH_RATIO, PLL_STEPS_PER_CYCLE, MEM_IF_DWIDTH, MEM_IF_DQS_CAPTURE); -- note total word requirement
end if;
-- check if current pin and phase passed:
sig_dgrb_iram.iram_pushdata(0) <= sig_rsc_push_rrp_pass;
-- bit offset is modulo phase
sig_dgrb_iram.iram_bitnum <= sig_rsc_curr_phase mod 32;
end if;
-- write result of rrp_calc to iram when completed
if sig_rsc_push_rrp_seek = '1' then -- a result found
sig_dgrb_iram.iram_write <= '1';
sig_iram_idle <= '0';
sig_dgrb_iram.iram_wordnum <= 0;
sig_iram_wds_req <= 1; -- note total word requirement
if sig_cdvw_state.status = valid_result then -- result is valid
sig_dgrb_iram.iram_pushdata <= x"0000" &
std_logic_vector(to_unsigned(sig_cdvw_state.largest_window_centre, 8)) &
std_logic_vector(to_unsigned(sig_cdvw_state.largest_window_size, 8));
else -- invalid result (error code communicated elsewhere)
sig_dgrb_iram.iram_pushdata <= x"FFFF" & -- signals an error condition
x"0000";
end if;
end if;
-- when stage finished write footer
if sig_rsc_push_footer = '1' then
sig_dgrb_iram.iram_done <= '1';
sig_iram_idle <= '0';
-- set address location of footer
sig_dgrb_iram.iram_wordnum <= sig_iram_wds_req;
end if;
-- if write completed deassert iram_write and done signals
if iram_push_done = '1' then
sig_dgrb_iram.iram_write <= '0';
sig_dgrb_iram.iram_done <= '0';
end if;
else
sig_iram_idle <= '0';
sig_dq_pin_ctr_r <= 0;
sig_rsc_curr_phase <= 0;
sig_dgrb_iram <= defaults;
end if;
end if;
end process;
-- concurrently assign sig_dgrb_iram to dgrb_iram
dgrb_iram <= sig_dgrb_iram;
end block; -- resync calculation
-- ------------------------------------------------------------------
-- test pattern match block
--
-- This block handles the sharing of logic for test pattern matching
-- which is used in resync and postamble calibration / code blocks
-- ------------------------------------------------------------------
tp_match_block : block
--
-- Ascii Waveforms:
--
-- ; ; ; ; ; ;
-- ____ ____ ____ ____ ____ ____
-- delayed_dqs |____| |____| |____| |____| |____| |____| |____|
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- ; _______ ; _______ ; _______ ; _______ ; _______ _______
-- XXXXX / \ / \ / \ / \ / \ / \
-- c0,c1 XXXXXX A B X C D X E F X G H X I J X L M X captured data
-- XXXXX \_______/ \_______/ \_______/ \_______/ \_______/ \_______/
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- ____; ____; ____ ____ ____ ____ ____
-- 180-resync_clk |____| |____| |____| |____| |____| |____| | 180deg shift from delayed dqs
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- ; _______ _______ _______ _______ _______ ____
-- XXXXXXXXXX / \ / \ / \ / \ / \ /
-- 180-r0,r1 XXXXXXXXXXX A B X C D X E F X G H X I J X L resync data
-- XXXXXXXXXX \_______/ \_______/ \_______/ \_______/ \_______/ \____
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- ____ ____ ____ ____ ____ ____
-- 360-resync_clk ____| |____| |____| |____| |____| |____| |____|
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- ; ; _______ ; _______ ; _______ ; _______ ; _______
-- XXXXXXXXXXXXXXX / \ / \ / \ / \ / \
-- 360-r0,r1 XXXXXXXXXXXXXXXX A B X C D X E F X G H X I J X resync data
-- XXXXXXXXXXXXXXX \_______/ \_______/ \_______/ \_______/ \_______/
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- ____ ____ ____ ____ ____ ____ ____
-- 540-resync_clk |____| |____| |____| |____| |____| |____| |
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- ; ; _______ _______ _______ _______ ____
-- XXXXXXXXXXXXXXXXXXX / \ / \ / \ / \ /
-- 540-r0,r1 XXXXXXXXXXXXXXXXXXXX A B X C D X E F X G H X I resync data
-- XXXXXXXXXXXXXXXXXXX \_______/ \_______/ \_______/ \_______/ \____
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- ;____ ____ ____ ____ ____ ____
-- phy_clk |____| |____| |____| |____| |____| |____| |____|
--
-- 0 1 2 3 4 5 6
--
--
-- |<- Aligned Data ->|
-- phy_clk 180-r0,r1 540-r0,r1 sig_mtp_match_en (generated from sig_ac_even)
-- 0 XXXXXXXX XXXXXXXX '1'
-- 1 XXXXXXAB XXXXXXXX '0'
-- 2 XXXXABCD XXXXXXAB '1'
-- 3 XXABCDEF XXXXABCD '0'
-- 4 ABCDEFGH XXABCDEF '1'
-- 5 CDEFGHAB ABCDEFGH '0'
--
-- In DQS-based capture, sweeping resync_clk from 180 degrees to 360
-- does not necessarily result in a failure because the setup/hold
-- requirements are so small. The data comparison needs to fail when
-- the resync_clk is shifted more than 360 degrees. The
-- sig_mtp_match_en signal allows the sequencer to blind itself
-- training pattern matches that occur above 360 degrees.
--
--
--
--
--
-- Asserts sig_mtp_match.
--
-- Data comes in from rdata and is pushed into a two-bit wide shift register.
-- It is a critical assumption that the rdata comes back byte aligned.
--
--
--sig_mtp_match_valid
-- rdata_valid (shift-enable)
-- |
-- |
-- +-----------------------+-----------+------------------+
-- ___ | | |
-- dq(0) >---| \ | Shift Register |
-- dq(1) >---| \ +------+ +------+ +------------------+
-- dq(2) >---| )--->| D(0) |-+->| D(1) |-+->...-+->| D(c_cal_mtp_len - 1) |
-- ... | / +------+ | +------+ | | +------------------+
-- dq(n-1) >---|___/ +-----------++-...-+
-- | || +---+
-- | (==)--------> sig_mtp_match_0t ---->| |-->sig_mtp_match_1t-->sig_mtp_match
-- | || +---+
-- | +-----------++...-+
-- sig_dq_pin_ctr >-+ +------+ | +------+ | | +------------------+
-- | P(0) |-+ | P(1) |-+ ...-+->| P(c_cal_mtp_len - 1) |
-- +------+ +------+ +------------------+
--
--
--
--
signal sig_rdata_current_pin : std_logic_vector(c_cal_mtp_len - 1 downto 0);
-- A fundamental assumption here is that rdata_valid is all
-- ones or all zeros - not both.
signal sig_rdata_valid_1t : std_logic; -- rdata_valid delayed by 1 clock period.
signal sig_rdata_valid_2t : std_logic; -- rdata_valid delayed by 2 clock periods.
begin
rdata_valid_1t_proc : process (clk, rst_n)
begin
if rst_n = '0' then
sig_rdata_valid_1t <= '0';
sig_rdata_valid_2t <= '0';
elsif rising_edge(clk) then
sig_rdata_valid_2t <= sig_rdata_valid_1t;
sig_rdata_valid_1t <= rdata_valid(0);
end if;
end process;
-- MUX data into sig_rdata_current_pin shift register.
rdata_current_pin_proc: process (clk, rst_n)
begin
if rst_n = '0' then
sig_rdata_current_pin <= (others => '0');
elsif rising_edge(clk) then
-- shift old data down the shift register
sig_rdata_current_pin(sig_rdata_current_pin'high - DWIDTH_RATIO downto 0) <=
sig_rdata_current_pin(sig_rdata_current_pin'high downto DWIDTH_RATIO);
-- shift new data into the bottom of the shift register.
for i in 0 to DWIDTH_RATIO - 1 loop
sig_rdata_current_pin(sig_rdata_current_pin'high - DWIDTH_RATIO + 1 + i) <= rdata(i*MEM_IF_DWIDTH + sig_dq_pin_ctr);
end loop;
end if;
end process;
mtp_match_proc : process (clk, rst_n)
begin
if rst_n = '0' then -- * when at least c_max_read_lat clock cycles have passed
sig_mtp_match <= '0';
elsif rising_edge(clk) then
sig_mtp_match <= '0';
if sig_rdata_current_pin = c_cal_mtp then
sig_mtp_match <= '1';
end if;
end if;
end process;
poa_match_proc : process (clk, rst_n)
-- poa_match_Calibration Strategy
--
-- Ascii Waveforms:
--
-- __ __ __ __ __ __ __ __ __
-- clk __| |__| |__| |__| |__| |__| |__| |__| |__| |
--
-- ; ; ; ;
-- _________________
-- rdata_valid ________| |___________________________
--
-- ; ; ; ;
-- _____
-- poa_match_en ______________________________________| |_______________
--
-- ; ; ; ;
-- _____
-- poa_match XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX
--
--
-- Notes:
-- -poa_match is only valid while poa_match_en is asserted.
--
--
--
--
--
--
begin
if rst_n = '0' then
sig_poa_match_en <= '0';
sig_poa_match <= '0';
elsif rising_edge(clk) then
sig_poa_match <= '0';
sig_poa_match_en <= '0';
if sig_rdata_valid_2t = '1' and sig_rdata_valid_1t = '0' then
sig_poa_match_en <= '1';
end if;
if DWIDTH_RATIO = 2 then
if sig_rdata_current_pin(sig_rdata_current_pin'high downto sig_rdata_current_pin'length - 6) = "111100" then
sig_poa_match <= '1';
end if;
elsif DWIDTH_RATIO = 4 then
if sig_rdata_current_pin(sig_rdata_current_pin'high downto sig_rdata_current_pin'length - 8) = "11111100" then
sig_poa_match <= '1';
end if;
else
report dgrb_report_prefix & "unsupported DWIDTH_RATIO" severity failure;
end if;
end if;
end process;
end block;
-- ------------------------------------------------------------------
-- Postamble calibration
--
-- Implements the postamble slave state machine and collates the
-- processing data from the test pattern match block.
-- ------------------------------------------------------------------
poa_block : block
-- Postamble Calibration Strategy
--
-- Ascii Waveforms:
--
-- c_read_burst_t c_read_burst_t
-- ;<------->; ;<------->;
-- ; ; ; ;
-- __ / / __
-- mem_dq[0] ___________| |_____\ \________| |___
--
-- ; ; ; ;
-- ; ; ; ;
-- _________ / / _________
-- poa_enable ______| |___\ \_| |___
-- ; ; ; ;
-- ; ; ; ;
-- __ / / ______
-- rdata[0] ___________| |______\ \_______|
-- ; ; ; ;
-- ; ; ; ;
-- ; ; ; ;
-- _ / / _
-- poa_match_en _____________| |___\ \___________| |_
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- / / _
-- poa_match ___________________\ \___________| |_
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- _ / /
-- seq_poa_lat_dec _______________| |_\ \_______________
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- / /
-- seq_poa_lat_inc ___________________\ \_______________
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
--
-- (1) (2)
--
--
-- (1) poa_enable signal is late, and the zeros on mem_dq after (1)
-- are captured.
-- (2) poa_enable signal is aligned. Zeros following (2) are not
-- captured rdata remains at '1'.
--
-- The DQS capture circuit wth the dqs enable asynchronous set.
--
--
--
-- dqs_en_async_preset ----------+
-- |
-- v
-- +---------+
-- +--|Q SET D|----------- gnd
-- | | <O---+
-- | +---------+ |
-- | |
-- | |
-- +--+---. |
-- |AND )--------+------- dqs_bus
-- delayed_dqs -----+---^
--
--
--
-- _____ _____ _____ _____
-- dqs ____| |_____| |_____| |_____| |_____XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
-- ; ; ; ; ;
-- ; ; ; ;
-- _____ _____ _____ _____
-- delayed_dqs _______| |_____| |_____| |_____| |_____XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
--
-- ; ; ; ; ;
-- ; ______________________________________________________________
-- dqs_en_async_ _____________________________| |_____
-- preset
-- ; ; ; ; ;
-- ; ; ; ; ;
-- _____ _____ _____
-- dqs_bus _______| |_________________| |_____| |_____XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
--
-- ; ;
-- (1) (2)
--
--
-- Notes:
-- (1) The dqs_bus pulse here comes because the last value of Q
-- is '1' until the first DQS pulse clocks gnd into the FF,
-- brings low the AND gate, and disables dqs_bus. A training
-- pattern could potentially match at this point even though
-- between (1) and (2) there are no dqs_bus triggers. Data
-- is frozen on rdata while awaiting the dqs_bus pulses at
-- (2). For this reason, wait until the first match of the
-- training pattern, and continue reducing latency until it
-- TP no longer matches, then increase latency by one. In
-- this case, dqs_en_async_preset will have its latency
-- reduced by three until the training pattern is not matched,
-- then latency is increased by one.
--
--
--
--
-- Postamble calibration state
type t_poa_state is (
-- decrease poa enable latency by 1 cycle iteratively until 'correct' position found
s_poa_rewind_to_pass,
-- poa cal complete
s_poa_done
);
constant c_poa_lat_cmd_wait : natural := 10; -- Number of clock cycles to wait for lat_inc/lat_dec signal to take effect.
constant c_poa_max_lat : natural := 100; -- Maximum number of allowable latency changes.
signal sig_poa_adjust_count : integer range 0 to 2**8 - 1;
signal sig_poa_state : t_poa_state;
begin
poa_proc : process (clk, rst_n)
begin
if rst_n = '0' then
sig_poa_ack <= '0';
seq_poa_lat_dec_1x <= (others => '0');
seq_poa_lat_inc_1x <= (others => '0');
sig_poa_adjust_count <= 0;
sig_poa_state <= s_poa_rewind_to_pass;
elsif rising_edge(clk) then
sig_poa_ack <= '0';
seq_poa_lat_inc_1x <= (others => '0');
seq_poa_lat_dec_1x <= (others => '0');
if sig_dgrb_state = s_poa_cal then
case sig_poa_state is
when s_poa_rewind_to_pass =>
-- In postamble calibration
--
-- Normally, must wait for sig_dimm_driving_dq to be '1'
-- before reading, but by this point in calibration
-- rdata_valid is assumed to be set up properly. The
-- sig_poa_match_en (derived from rdata_valid) is used
-- here rather than sig_dimm_driving_dq.
if sig_poa_match_en = '1' then
if sig_poa_match = '1' then
sig_poa_state <= s_poa_done;
else
seq_poa_lat_dec_1x <= (others => '1');
end if;
sig_poa_adjust_count <= sig_poa_adjust_count + 1;
end if;
when s_poa_done =>
sig_poa_ack <= '1';
end case;
else
sig_poa_state <= s_poa_rewind_to_pass;
sig_poa_adjust_count <= 0;
end if;
assert sig_poa_adjust_count <= c_poa_max_lat
report dgrb_report_prefix & "Maximum number of postamble latency adjustments exceeded."
severity failure;
end if;
end process;
end block;
-- ------------------------------------------------------------------
-- code block for tracking signal generation
--
-- this is used for initial tracking setup (finding a reference window)
-- and periodic tracking operations (PVT compensation on rsc phase)
--
-- A slave trk state machine is described and implemented within the block
-- The mimic path is controlled within this block
-- ------------------------------------------------------------------
trk_block : block
type t_tracking_state is (
-- initialise variables out of reset
s_trk_init,
-- idle state
s_trk_idle,
-- sample data from the mimic path (build window)
s_trk_mimic_sample,
-- 'shift' mimic path phase
s_trk_next_phase,
-- calculate mimic window
s_trk_cdvw_calc,
s_trk_cdvw_wait, -- for results
-- calculate how much mimic window has moved (only entered in periodic tracking)
s_trk_cdvw_drift,
-- track rsc phase (only entered in periodic tracking)
s_trk_adjust_resync,
-- communicate command complete to the master state machine
s_trk_complete
);
signal sig_mmc_seq_done : std_logic;
signal sig_mmc_seq_done_1t : std_logic;
signal mmc_seq_value_r : std_logic;
signal sig_mmc_start : std_logic;
signal sig_trk_state : t_tracking_state;
signal sig_trk_last_state : t_tracking_state;
signal sig_rsc_drift : integer range -c_max_rsc_drift_in_phases to c_max_rsc_drift_in_phases; -- stores total change in rsc phase from first calibration
signal sig_req_rsc_shift : integer range -c_max_rsc_drift_in_phases to c_max_rsc_drift_in_phases; -- stores required shift in rsc phase instantaneously
signal sig_mimic_cdv_found : std_logic;
signal sig_mimic_cdv : integer range 0 to PLL_STEPS_PER_CYCLE; -- centre of data valid window calculated from first mimic-cycle
signal sig_mimic_delta : integer range -PLL_STEPS_PER_CYCLE to PLL_STEPS_PER_CYCLE;
signal sig_large_drift_seen : std_logic;
signal sig_remaining_samples : natural range 0 to 2**8 - 1;
begin
-- advertise the codvw phase shift
process (clk, rst_n)
variable v_length : integer;
begin
if rst_n = '0' then
codvw_trk_shift <= (others => '0');
elsif rising_edge(clk) then
if sig_mimic_cdv_found = '1' then
-- check range
v_length := codvw_trk_shift'length;
codvw_trk_shift <= std_logic_vector(to_signed(sig_rsc_drift, v_length));
else
codvw_trk_shift <= (others => '0');
end if;
end if;
end process;
-- request a mimic sample
mimic_sample_req : process (clk, rst_n)
variable seq_mmc_start_r : std_logic_vector(3 downto 0);
begin
if rst_n = '0' then
seq_mmc_start <= '0';
seq_mmc_start_r := "0000";
elsif rising_edge(clk) then
seq_mmc_start_r(3) := seq_mmc_start_r(2);
seq_mmc_start_r(2) := seq_mmc_start_r(1);
seq_mmc_start_r(1) := seq_mmc_start_r(0);
-- extend sig_mmc_start by one clock cycle
if sig_mmc_start = '1' then
seq_mmc_start <= '1';
seq_mmc_start_r(0) := '1';
elsif ( (seq_mmc_start_r(3) = '1') or (seq_mmc_start_r(2) = '1') or (seq_mmc_start_r(1) = '1') or (seq_mmc_start_r(0) = '1') ) then
seq_mmc_start <= '1';
seq_mmc_start_r(0) := '0';
else
seq_mmc_start <= '0';
end if;
end if;
end process;
-- metastability hardening of async mmc_seq_done signal
mmc_seq_req_sync : process (clk, rst_n)
variable v_mmc_seq_done_1r : std_logic;
variable v_mmc_seq_done_2r : std_logic;
variable v_mmc_seq_done_3r : std_logic;
begin
if rst_n = '0' then
sig_mmc_seq_done <= '0';
sig_mmc_seq_done_1t <= '0';
v_mmc_seq_done_1r := '0';
v_mmc_seq_done_2r := '0';
v_mmc_seq_done_3r := '0';
elsif rising_edge(clk) then
sig_mmc_seq_done_1t <= v_mmc_seq_done_3r;
sig_mmc_seq_done <= v_mmc_seq_done_2r;
mmc_seq_value_r <= mmc_seq_value;
v_mmc_seq_done_3r := v_mmc_seq_done_2r;
v_mmc_seq_done_2r := v_mmc_seq_done_1r;
v_mmc_seq_done_1r := mmc_seq_done;
end if;
end process;
-- collect mimic samples as they arrive
shift_in_mmc_seq_value : process (clk, rst_n)
begin
if rst_n = '0' then
sig_trk_cdvw_shift_in <= '0';
sig_trk_cdvw_phase <= '0';
elsif rising_edge(clk) then
sig_trk_cdvw_shift_in <= '0';
sig_trk_cdvw_phase <= '0';
if sig_mmc_seq_done_1t = '1' and sig_mmc_seq_done = '0' then
sig_trk_cdvw_shift_in <= '1';
sig_trk_cdvw_phase <= mmc_seq_value_r;
end if;
end if;
end process;
-- main tracking state machine
trk_proc : process (clk, rst_n)
begin
if rst_n = '0' then
sig_trk_state <= s_trk_init;
sig_trk_last_state <= s_trk_init;
sig_trk_result <= (others => '0');
sig_trk_err <= '0';
sig_mmc_start <= '0';
sig_trk_pll_select <= (others => '0');
sig_req_rsc_shift <= -c_max_rsc_drift_in_phases;
sig_rsc_drift <= -c_max_rsc_drift_in_phases;
sig_mimic_delta <= -PLL_STEPS_PER_CYCLE;
sig_mimic_cdv_found <= '0';
sig_mimic_cdv <= 0;
sig_large_drift_seen <= '0';
sig_trk_cdvw_calc <= '0';
sig_remaining_samples <= 0;
sig_trk_pll_start_reconfig <= '0';
sig_trk_pll_inc_dec_n <= c_pll_phs_inc;
sig_trk_ack <= '0';
elsif rising_edge(clk) then
sig_trk_pll_select <= pll_measure_clk_index;
sig_trk_pll_start_reconfig <= '0';
sig_trk_pll_inc_dec_n <= c_pll_phs_inc;
sig_large_drift_seen <= '0';
sig_trk_cdvw_calc <= '0';
sig_trk_ack <= '0';
sig_trk_err <= '0';
sig_trk_result <= (others => '0');
sig_mmc_start <= '0';
-- if no cdv found then reset tracking results
if sig_mimic_cdv_found = '0' then
sig_rsc_drift <= 0;
sig_req_rsc_shift <= 0;
sig_mimic_delta <= 0;
end if;
if sig_dgrb_state = s_track then
-- resync state machine
case sig_trk_state is
when s_trk_init =>
sig_trk_state <= s_trk_idle;
sig_mimic_cdv_found <= '0';
sig_rsc_drift <= 0;
sig_req_rsc_shift <= 0;
sig_mimic_delta <= 0;
when s_trk_idle =>
sig_remaining_samples <= PLL_STEPS_PER_CYCLE; -- ensure a 360 degrees sweep
sig_trk_state <= s_trk_mimic_sample;
when s_trk_mimic_sample =>
if sig_remaining_samples = 0 then
sig_trk_state <= s_trk_cdvw_calc;
else
if sig_trk_state /= sig_trk_last_state then
-- request a sample as soon as we arrive in this state.
-- the default value of sig_mmc_start is zero!
sig_mmc_start <= '1';
end if;
if sig_mmc_seq_done_1t = '1' and sig_mmc_seq_done = '0' then
-- a sample has been collected, go to next PLL phase
sig_remaining_samples <= sig_remaining_samples - 1;
sig_trk_state <= s_trk_next_phase;
end if;
end if;
when s_trk_next_phase =>
sig_trk_pll_start_reconfig <= '1';
sig_trk_pll_inc_dec_n <= c_pll_phs_inc;
if sig_phs_shft_start = '1' then
sig_trk_pll_start_reconfig <= '0';
end if;
if sig_phs_shft_end = '1' then
sig_trk_state <= s_trk_mimic_sample;
end if;
when s_trk_cdvw_calc =>
if sig_trk_state /= sig_trk_last_state then
-- reset variables we are interested in when we first arrive in this state
sig_trk_cdvw_calc <= '1';
report dgrb_report_prefix & "gathered mimic phase samples DGRB_MIMIC_SAMPLES: " & str(sig_cdvw_state.working_window(sig_cdvw_state.working_window'high downto sig_cdvw_state.working_window'length - PLL_STEPS_PER_CYCLE)) severity note;
else
sig_trk_state <= s_trk_cdvw_wait;
end if;
when s_trk_cdvw_wait =>
if sig_cdvw_state.status /= calculating then
if sig_cdvw_state.status = valid_result then
report dgrb_report_prefix & "mimic window successfully found." severity note;
if sig_mimic_cdv_found = '0' then -- first run of tracking operation
sig_mimic_cdv_found <= '1';
sig_mimic_cdv <= sig_cdvw_state.largest_window_centre;
sig_trk_state <= s_trk_complete;
else -- subsequent tracking operation runs
sig_mimic_delta <= sig_mimic_cdv - sig_cdvw_state.largest_window_centre;
sig_mimic_cdv <= sig_cdvw_state.largest_window_centre;
sig_trk_state <= s_trk_cdvw_drift;
end if;
else
report dgrb_report_prefix & "couldn't find a data-valid window for tracking." severity cal_fail_sev_level;
sig_trk_ack <= '1';
sig_trk_err <= '1';
sig_trk_state <= s_trk_idle;
-- set resync result code
case sig_cdvw_state.status is
when no_invalid_phases =>
sig_trk_result <= std_logic_vector(to_unsigned(C_ERR_RESYNC_NO_INVALID_PHASES, sig_trk_result'length));
when multiple_equal_windows =>
sig_trk_result <= std_logic_vector(to_unsigned(C_ERR_RESYNC_MULTIPLE_EQUAL_WINDOWS, sig_trk_result'length));
when no_valid_phases =>
sig_trk_result <= std_logic_vector(to_unsigned(C_ERR_RESYNC_NO_VALID_PHASES, sig_trk_result'length));
when others =>
sig_trk_result <= std_logic_vector(to_unsigned(C_ERR_CRITICAL, sig_trk_result'length));
end case;
end if;
end if;
when s_trk_cdvw_drift => -- calculate the drift in rsc phase
-- pipeline stage 1
if abs(sig_mimic_delta) > PLL_STEPS_PER_CYCLE/2 then
sig_large_drift_seen <= '1';
else
sig_large_drift_seen <= '0';
end if;
--pipeline stage 2
if sig_trk_state = sig_trk_last_state then
if sig_large_drift_seen = '1' then
if sig_mimic_delta < 0 then -- anti-clockwise movement
sig_req_rsc_shift <= sig_req_rsc_shift + sig_mimic_delta + PLL_STEPS_PER_CYCLE;
else -- clockwise movement
sig_req_rsc_shift <= sig_req_rsc_shift + sig_mimic_delta - PLL_STEPS_PER_CYCLE;
end if;
else
sig_req_rsc_shift <= sig_req_rsc_shift + sig_mimic_delta;
end if;
sig_trk_state <= s_trk_adjust_resync;
end if;
when s_trk_adjust_resync =>
sig_trk_pll_select <= pll_resync_clk_index;
sig_trk_pll_start_reconfig <= '1';
if sig_trk_state /= sig_trk_last_state then
if sig_req_rsc_shift < 0 then
sig_trk_pll_inc_dec_n <= c_pll_phs_inc;
sig_req_rsc_shift <= sig_req_rsc_shift + 1;
sig_rsc_drift <= sig_rsc_drift + 1;
elsif sig_req_rsc_shift > 0 then
sig_trk_pll_inc_dec_n <= c_pll_phs_dec;
sig_req_rsc_shift <= sig_req_rsc_shift - 1;
sig_rsc_drift <= sig_rsc_drift - 1;
else
sig_trk_state <= s_trk_complete;
sig_trk_pll_start_reconfig <= '0';
end if;
else
sig_trk_pll_inc_dec_n <= sig_trk_pll_inc_dec_n; -- maintain current value
end if;
if abs(sig_rsc_drift) = c_max_rsc_drift_in_phases then
report dgrb_report_prefix & " a maximum absolute change in resync_clk of " & integer'image(sig_rsc_drift) & " phases has " & LF &
" occurred (since read resynch phase calibration) during tracking" severity cal_fail_sev_level;
sig_trk_err <= '1';
sig_trk_result <= std_logic_vector(to_unsigned(C_ERR_MAX_TRK_SHFT_EXCEEDED, sig_trk_result'length));
end if;
if sig_phs_shft_start = '1' then
sig_trk_pll_start_reconfig <= '0';
end if;
if sig_phs_shft_end = '1' then
sig_trk_state <= s_trk_complete;
end if;
when s_trk_complete =>
sig_trk_ack <= '1';
end case;
sig_trk_last_state <= sig_trk_state;
else
sig_trk_state <= s_trk_idle;
sig_trk_last_state <= s_trk_idle;
end if;
end if;
end process;
rsc_drift: process (sig_rsc_drift)
begin
sig_trk_rsc_drift <= sig_rsc_drift; -- communicate tracking shift to rsc process
end process;
end block; -- tracking signals
-- ------------------------------------------------------------------
-- write-datapath (WDP) ` and on-chip-termination (OCT) signal
-- ------------------------------------------------------------------
wdp_oct : process(clk,rst_n)
begin
if rst_n = '0' then
seq_oct_value <= c_set_oct_to_rs;
dgrb_wdp_ovride <= '0';
elsif rising_edge(clk) then
if ((sig_dgrb_state = s_idle) or (EN_OCT = 0)) then
seq_oct_value <= c_set_oct_to_rs;
dgrb_wdp_ovride <= '0';
else
seq_oct_value <= c_set_oct_to_rt;
dgrb_wdp_ovride <= '1';
end if;
end if;
end process;
-- ------------------------------------------------------------------
-- handles muxing of error codes to the control block
-- ------------------------------------------------------------------
ac_handshake_proc : process(rst_n, clk)
begin
if rst_n = '0' then
dgrb_ctrl <= defaults;
elsif rising_edge(clk) then
dgrb_ctrl <= defaults;
if sig_dgrb_state = s_wait_admin and sig_dgrb_last_state = s_idle then
dgrb_ctrl.command_ack <= '1';
end if;
case sig_dgrb_state is
when s_seek_cdvw =>
dgrb_ctrl.command_err <= sig_rsc_err;
dgrb_ctrl.command_result <= sig_rsc_result;
when s_track =>
dgrb_ctrl.command_err <= sig_trk_err;
dgrb_ctrl.command_result <= sig_trk_result;
when others => -- from main state machine
dgrb_ctrl.command_err <= sig_cmd_err;
dgrb_ctrl.command_result <= sig_cmd_result;
end case;
if ctrl_dgrb_r.command = cmd_read_mtp then -- check against command because aligned with command done not command_err
dgrb_ctrl.command_err <= '0';
dgrb_ctrl.command_result <= std_logic_vector(to_unsigned(sig_cdvw_state.largest_window_size,dgrb_ctrl.command_result'length));
end if;
if sig_dgrb_state = s_idle and sig_dgrb_last_state = s_release_admin then
dgrb_ctrl.command_done <= '1';
end if;
end if;
end process;
-- ------------------------------------------------------------------
-- address/command state machine
-- process is commanded to begin reading training patterns.
--
-- implements the address/command slave state machine
-- issues read commands to the memory relative to given calibration
-- stage being implemented
-- burst length is dependent on memory type
-- ------------------------------------------------------------------
ac_block : block
-- override the calibration burst length for DDR3 device support
-- (requires BL8 / on the fly setting in MR in admin block)
function set_read_bl ( memtype: in string ) return natural is
begin
if memtype = "DDR3" then
return 8;
elsif memtype = "DDR" or memtype = "DDR2" then
return c_cal_burst_len;
else
report dgrb_report_prefix & " a calibration burst length choice has not been set for memory type " & memtype severity failure;
end if;
return 0;
end function;
-- parameterisation of the read algorithm by burst length
constant c_poa_addr_width : natural := 6;
constant c_cal_read_burst_len : natural := set_read_bl(MEM_IF_MEMTYPE);
constant c_bursts_per_btp : natural := c_cal_mtp_len / c_cal_read_burst_len;
constant c_read_burst_t : natural := c_cal_read_burst_len / DWIDTH_RATIO;
constant c_max_rdata_valid_lat : natural := 50*(c_cal_read_burst_len / DWIDTH_RATIO); -- maximum latency that rdata_valid can ever have with respect to doing_rd
constant c_rdv_ones_rd_clks : natural := (c_max_rdata_valid_lat + c_read_burst_t) / c_read_burst_t; -- number of cycles to read ones for before a pulse of zeros
-- array of burst training pattern addresses
-- here the MTP is used in this addressing
subtype t_btp_addr is natural range 0 to 2 ** MEM_IF_ADDR_WIDTH - 1;
type t_btp_addr_array is array (0 to c_bursts_per_btp - 1) of t_btp_addr;
-- default values
function defaults return t_btp_addr_array is
variable v_btp_array : t_btp_addr_array;
begin
for i in 0 to c_bursts_per_btp - 1 loop
v_btp_array(i) := 0;
end loop;
return v_btp_array;
end function;
-- load btp array addresses
-- Note: this scales to burst lengths of 2, 4 and 8
-- the settings here are specific to the choice of training pattern and need updating if the pattern changes
function set_btp_addr (mtp_almt : natural ) return t_btp_addr_array is
variable v_addr_array : t_btp_addr_array;
begin
for i in 0 to 8/c_cal_read_burst_len - 1 loop
-- set addresses for xF5 data
v_addr_array((c_bursts_per_btp - 1) - i) := MEM_IF_CAL_BASE_COL + c_cal_ofs_xF5 + i*c_cal_read_burst_len;
-- set addresses for x30 data (based on mtp alignment)
if mtp_almt = 0 then
v_addr_array((c_bursts_per_btp - 1) - (8/c_cal_read_burst_len + i)) := MEM_IF_CAL_BASE_COL + c_cal_ofs_x30_almt_0 + i*c_cal_read_burst_len;
else
v_addr_array((c_bursts_per_btp - 1) - (8/c_cal_read_burst_len + i)) := MEM_IF_CAL_BASE_COL + c_cal_ofs_x30_almt_1 + i*c_cal_read_burst_len;
end if;
end loop;
return v_addr_array;
end function;
function find_poa_cycle_period return natural is
-- Returns the period over which the postamble reads
-- repeat in c_read_burst_t units.
variable v_num_bursts : natural;
begin
v_num_bursts := 2 ** c_poa_addr_width / c_read_burst_t;
if v_num_bursts * c_read_burst_t < 2**c_poa_addr_width then
v_num_bursts := v_num_bursts + 1;
end if;
v_num_bursts := v_num_bursts + c_bursts_per_btp + 1;
return v_num_bursts;
end function;
function get_poa_burst_addr(burst_count : in natural; mtp_almt : in natural) return t_btp_addr is
variable v_addr : t_btp_addr;
begin
if burst_count = 0 then
if mtp_almt = 0 then
v_addr := c_cal_ofs_x30_almt_1;
elsif mtp_almt = 1 then
v_addr := c_cal_ofs_x30_almt_0;
else
report "Unsupported mtp_almt " & natural'image(mtp_almt) severity failure;
end if;
-- address gets incremented by four if in burst-length four.
v_addr := v_addr + (8 - c_cal_read_burst_len);
else
v_addr := c_cal_ofs_zeros;
end if;
return v_addr;
end function;
signal btp_addr_array : t_btp_addr_array; -- burst training pattern addresses
signal sig_addr_cmd_state : t_ac_state;
signal sig_addr_cmd_last_state : t_ac_state;
signal sig_doing_rd_count : integer range 0 to c_read_burst_t - 1;
signal sig_count : integer range 0 to 2**8 - 1;
signal sig_setup : integer range c_max_read_lat downto 0;
signal sig_burst_count : integer range 0 to c_read_burst_t;
begin
-- handles counts for when to begin burst-reads (sig_burst_count)
-- sets sig_dimm_driving_dq
-- sets dgrb_ac_access_req
dimm_driving_dq_proc : process(rst_n, clk)
begin
if rst_n = '0' then
sig_dimm_driving_dq <= '1';
sig_setup <= c_max_read_lat;
sig_burst_count <= 0;
dgrb_ac_access_req <= '0';
sig_ac_even <= '0';
elsif rising_edge(clk) then
sig_dimm_driving_dq <= '0';
if sig_addr_cmd_state /= s_ac_idle and sig_addr_cmd_state /= s_ac_relax then
dgrb_ac_access_req <= '1';
else
dgrb_ac_access_req <= '0';
end if;
case sig_addr_cmd_state is
when s_ac_read_mtp | s_ac_read_rdv | s_ac_read_wd_lat | s_ac_read_poa_mtp =>
sig_ac_even <= not sig_ac_even;
-- a counter that keeps track of when we are ready
-- to issue a burst read. Issue burst read eigvery
-- time we are at zero.
if sig_burst_count = 0 then
sig_burst_count <= c_read_burst_t - 1;
else
sig_burst_count <= sig_burst_count - 1;
end if;
if dgrb_ac_access_gnt /= '1' then
sig_setup <= c_max_read_lat;
else
-- primes reads
-- signal that dimms are driving dq pins after
-- at least c_max_read_lat clock cycles have passed.
--
if sig_setup = 0 then
sig_dimm_driving_dq <= '1';
elsif dgrb_ac_access_gnt = '1' then
sig_setup <= sig_setup - 1;
end if;
end if;
when s_ac_relax =>
sig_dimm_driving_dq <= '1';
sig_burst_count <= 0;
sig_ac_even <= '0';
when others =>
sig_burst_count <= 0;
sig_ac_even <= '0';
end case;
end if;
end process;
ac_proc : process(rst_n, clk)
begin
if rst_n = '0' then
sig_count <= 0;
sig_addr_cmd_state <= s_ac_idle;
sig_addr_cmd_last_state <= s_ac_idle;
sig_doing_rd_count <= 0;
sig_addr_cmd <= reset(c_seq_addr_cmd_config);
btp_addr_array <= defaults;
sig_doing_rd <= (others => '0');
elsif rising_edge(clk) then
assert c_cal_mtp_len mod c_cal_read_burst_len = 0 report dgrb_report_prefix & "burst-training pattern length must be a multiple of burst-length." severity failure;
assert MEM_IF_CAL_BANK < 2**MEM_IF_BANKADDR_WIDTH report dgrb_report_prefix & "MEM_IF_CAL_BANK out of range." severity failure;
assert MEM_IF_CAL_BASE_COL < 2**MEM_IF_ADDR_WIDTH - 1 - C_CAL_DATA_LEN report dgrb_report_prefix & "MEM_IF_CAL_BASE_COL out of range." severity failure;
sig_addr_cmd <= deselect(c_seq_addr_cmd_config, sig_addr_cmd);
if sig_ac_req /= sig_addr_cmd_state and sig_addr_cmd_state /= s_ac_idle then
-- and dgrb_ac_access_gnt = '1'
sig_addr_cmd_state <= s_ac_relax;
else
sig_addr_cmd_state <= sig_ac_req;
end if;
if sig_doing_rd_count /= 0 then
sig_doing_rd <= (others => '1');
sig_doing_rd_count <= sig_doing_rd_count - 1;
else
sig_doing_rd <= (others => '0');
end if;
case sig_addr_cmd_state is
when s_ac_idle =>
sig_addr_cmd <= defaults(c_seq_addr_cmd_config);
when s_ac_relax =>
-- waits at least c_max_read_lat before returning to s_ac_idle state
if sig_addr_cmd_state /= sig_addr_cmd_last_state then
sig_count <= c_max_read_lat;
else
if sig_count = 0 then
sig_addr_cmd_state <= s_ac_idle;
else
sig_count <= sig_count - 1;
end if;
end if;
when s_ac_read_mtp =>
-- reads 'more'-training pattern
-- issue read commands for proper addresses
-- set burst training pattern (mtp in this case) addresses
btp_addr_array <= set_btp_addr(current_mtp_almt);
if sig_addr_cmd_state /= sig_addr_cmd_last_state then
sig_count <= c_bursts_per_btp - 1; -- counts number of bursts in a training pattern
else
sig_doing_rd <= (others => '1');
-- issue a read command every c_read_burst_t clock cycles
if sig_burst_count = 0 then
-- decide which read command to issue
for i in 0 to c_bursts_per_btp - 1 loop
if sig_count = i then
sig_addr_cmd <= read(c_seq_addr_cmd_config, -- configuration
sig_addr_cmd, -- previous value
MEM_IF_CAL_BANK, -- bank
btp_addr_array(i), -- column address
2**current_cs, -- rank
c_cal_read_burst_len, -- burst length
false);
end if;
end loop;
-- Set next value of count
if sig_count = 0 then
sig_count <= c_bursts_per_btp - 1;
else
sig_count <= sig_count - 1;
end if;
end if;
end if;
when s_ac_read_poa_mtp =>
-- Postamble rdata/rdata_valid Activity:
--
--
-- (0) (1) (2)
-- ; ; ; ;
-- _________ __ ____________ _____________ _______ _________
-- \ / \ / \ \ \ / \ /
-- (a) rdata[0] 00000000 X 11 X 0000000000 / / 0000000000 X MTP X 00000000
-- _________/ \__/ \____________\ \____________/ \_______/ \_________
-- ; ; ; ;
-- ; ; ; ;
-- _________ / / _________
-- rdata_valid ____| |_____________\ \_____________| |__________
--
-- ;<- (b) ->;<------------(c)------------>; ;
-- ; ; ; ;
--
--
-- This block must issue reads and drive doing_rd to place the above pattern on
-- the rdata and rdata_valid ports. MTP will most likely come back corrupted but
-- the postamble block (poa_block) will make the necessary adjustments to improve
-- matters.
--
-- (a) Read zeros followed by two ones. The two will be at the end of a burst.
-- Assert rdata_valid only during the burst containing the ones.
-- (b) c_read_burst_t clock cycles.
-- (c) Must be greater than but NOT equal to maximum postamble latency clock
-- cycles. Another way: c_min = (max_poa_lat + 1) phy clock cycles. This
-- must also be long enough to allow the postamble block to respond to a
-- the seq_poa_lat_dec_1x signal, but this requirement is less stringent
-- than the first so that we can ignore it.
--
-- The find_poa_cycle_period function should return (b+c)/c_read_burst_t
-- rounded up to the next largest integer.
--
--
-- set burst training pattern (mtp in this case) addresses
btp_addr_array <= set_btp_addr(current_mtp_almt);
-- issue read commands for proper addresses
if sig_addr_cmd_state /= sig_addr_cmd_last_state then
sig_count <= find_poa_cycle_period - 1; -- length of read patter in bursts.
elsif dgrb_ac_access_gnt = '1' then
-- only begin operation once dgrb_ac_access_gnt has been issued
-- otherwise rdata_valid may be asserted when rdasta is not
-- valid.
--
-- *** WARNING: BE SAFE. DON'T LET THIS HAPPEN TO YOU: ***
--
-- ; ; ; ; ; ;
-- ; _______ ; ; _______ ; ; _______
-- XXXXX / \ XXXXXXXXX / \ XXXXXXXXX / \ XXXXXXXXX
-- addr/cmd XXXXXX READ XXXXXXXXXXX READ XXXXXXXXXXX READ XXXXXXXXXXX
-- XXXXX \_______/ XXXXXXXXX \_______/ XXXXXXXXX \_______/ XXXXXXXXX
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- ; ; ; ; ; ; _______
-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX / \
-- rdata XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX MTP X
-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX \_______/
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- _________ _________ _________
-- doing_rd ____| |_________| |_________| |__________
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- __________________________________________________
-- ac_accesss_gnt ______________|
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- _________ _________
-- rdata_valid __________________________________| |_________| |
-- ; ; ; ; ; ;
--
-- (0) (1) (2)
--
--
-- Cmmand and doing_rd issued at (0). The doing_rd signal enters the
-- rdata_valid pipe here so that it will return on rdata_valid with the
-- expected latency (at this point in calibration, rdata_valid and adv_rd_lat
-- should be properly calibrated). Unlike doing_rd, since ac_access_gnt is not
-- asserted the READ command at (0) is never actually issued. This results
-- in the situation at (2) where rdata is undefined yet rdata_valid indicates
-- valid data. The moral of this story is to wait for ac_access_gnt = '1'
-- before issuing commands when it is important that rdata_valid be accurate.
--
--
--
--
if sig_burst_count = 0 then
sig_addr_cmd <= read(c_seq_addr_cmd_config, -- configuration
sig_addr_cmd, -- previous value
MEM_IF_CAL_BANK, -- bank
get_poa_burst_addr(sig_count, current_mtp_almt),-- column address
2**current_cs, -- rank
c_cal_read_burst_len, -- burst length
false);
-- Set doing_rd
if sig_count = 0 then
sig_doing_rd <= (others => '1');
sig_doing_rd_count <= c_read_burst_t - 1; -- Extend doing_rd pulse by this many phy_clk cycles.
end if;
-- Set next value of count
if sig_count = 0 then
sig_count <= find_poa_cycle_period - 1; -- read for one period then relax (no read) for same time period
else
sig_count <= sig_count - 1;
end if;
end if;
end if;
when s_ac_read_rdv =>
assert c_max_rdata_valid_lat mod c_read_burst_t = 0 report dgrb_report_prefix & "c_max_rdata_valid_lat must be a multiple of c_read_burst_t." severity failure;
if sig_addr_cmd_state /= sig_addr_cmd_last_state then
sig_count <= c_rdv_ones_rd_clks - 1;
else
if sig_burst_count = 0 then
if sig_count = 0 then
-- expecting to read ZEROS
sig_addr_cmd <= read(c_seq_addr_cmd_config, -- configuration
sig_addr_cmd, -- previous valid
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_COL + C_CAL_OFS_ZEROS, -- column
2**current_cs, -- rank
c_cal_read_burst_len, -- burst length
false);
else
-- expecting to read ONES
sig_addr_cmd <= read(c_seq_addr_cmd_config, -- configuration
sig_addr_cmd, -- previous value
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_COL + C_CAL_OFS_ONES, -- column address
2**current_cs, -- rank
c_cal_read_burst_len, -- op length
false);
end if;
if sig_count = 0 then
sig_count <= c_rdv_ones_rd_clks - 1;
else
sig_count <= sig_count - 1;
end if;
end if;
if (sig_count = c_rdv_ones_rd_clks - 1 and sig_burst_count = 1) or
(sig_count = 0 and c_read_burst_t = 1) then
-- the last burst read- that was issued was supposed to read only zeros
-- a burst read command will be issued on the next clock cycle
--
-- A long (>= maximim rdata_valid latency) series of burst reads are
-- issued for ONES.
-- Into this stream a single burst read for ZEROs is issued. After
-- the ZERO read command is issued, rdata_valid needs to come back
-- high one clock cycle before the next read command (reading ONES
-- again) is issued. Since the rdata_valid is just a delayed
-- version of doing_rd, doing_rd needs to exhibit the same behaviour.
--
-- for FR (burst length 4): require that doing_rd high 1 clock cycle after cs_n is low
-- ____ ____ ____ ____ ____ ____ ____ ____ ____
-- clk ____| |____| |____| |____| |____| |____| |____| |____| |____|
--
-- ___ _______ _______ _______ _______
-- \ XXXXXXXXX / \ XXXXXXXXX / \ XXXXXXXXX / \ XXXXXXXXX / \ XXXX
-- addr XXXXXXXXXXX ONES XXXXXXXXXXX ONES XXXXXXXXXXX ZEROS XXXXXXXXXXX ONES XXXXX--> Repeat
-- ___/ XXXXXXXXX \_______/ XXXXXXXXX \_______/ XXXXXXXXX \_______/ XXXXXXXXX \_______/ XXXX
--
-- _________ _________ _________ _________ ____
-- cs_n ____| |_________| |_________| |_________| |_________|
--
-- _________
-- doing_rd ________________________________________________________________| |______________
--
--
-- for HR: require that doing_rd high in the same clock cycle as cs_n is low
--
sig_doing_rd(MEM_IF_DQS_WIDTH*(DWIDTH_RATIO/2-1)) <= '1';
end if;
end if;
when s_ac_read_wd_lat =>
-- continuously issues reads on the memory locations
-- containing write latency addr=[2*c_cal_burst_len - (3*c_cal_burst_len - 1)]
if sig_addr_cmd_state /= sig_addr_cmd_last_state then
-- no initialization required here. Must still wait
-- a clock cycle before beginning operations so that
-- we are properly synchronized with
-- dimm_driving_dq_proc.
else
if sig_burst_count = 0 then
if sig_dimm_driving_dq = '1' then
sig_doing_rd <= (others => '1');
end if;
sig_addr_cmd <= read(c_seq_addr_cmd_config, -- configuration
sig_addr_cmd, -- previous value
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_COL + c_cal_ofs_wd_lat, -- column
2**current_cs, -- rank
c_cal_read_burst_len,
false);
end if;
end if;
when others =>
report dgrb_report_prefix & "undefined state in addr_cmd_proc" severity error;
sig_addr_cmd_state <= s_ac_idle;
end case;
-- mask odt signal
for i in 0 to (DWIDTH_RATIO/2)-1 loop
sig_addr_cmd(i).odt <= odt_settings(current_cs).read;
end loop;
sig_addr_cmd_last_state <= sig_addr_cmd_state;
end if;
end process;
end block ac_block;
end architecture struct;
--
-- -----------------------------------------------------------------------------
-- Abstract : data gatherer (write bias) [dgwb] block for the non-levelling
-- AFI PHY sequencer
-- -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
-- The record package (alt_mem_phy_record_pkg) is used to combine command and status signals
-- (into records) to be passed between sequencer blocks. It also contains type and record definitions
-- for the stages of DRAM memory calibration.
--
use work.ddr3_int_phy_alt_mem_phy_record_pkg.all;
-- The address and command package (alt_mem_phy_addr_cmd_pkg) is used to combine DRAM address
-- and command signals in one record and unify the functions operating on this record.
--
use work.ddr3_int_phy_alt_mem_phy_addr_cmd_pkg.all;
--
entity ddr3_int_phy_alt_mem_phy_dgwb is
generic (
-- Physical IF width definitions
MEM_IF_DQS_WIDTH : natural;
MEM_IF_DQ_PER_DQS : natural;
MEM_IF_DWIDTH : natural;
MEM_IF_DM_WIDTH : natural;
DWIDTH_RATIO : natural;
MEM_IF_ADDR_WIDTH : natural;
MEM_IF_BANKADDR_WIDTH : natural;
MEM_IF_NUM_RANKS : natural; -- The sequencer outputs memory control signals of width num_ranks
MEM_IF_MEMTYPE : string;
ADV_LAT_WIDTH : natural;
MEM_IF_CAL_BANK : natural; -- Bank to which calibration data is written
-- Base column address to which calibration data is written.
-- Memory at MEM_IF_CAL_BASE_COL - MEM_IF_CAL_BASE_COL + C_CAL_DATA_LEN - 1
-- is assumed to contain the proper data.
MEM_IF_CAL_BASE_COL : natural
);
port (
-- CLK Reset
clk : in std_logic;
rst_n : in std_logic;
parameterisation_rec : in t_algm_paramaterisation;
-- Control interface :
dgwb_ctrl : out t_ctrl_stat;
ctrl_dgwb : in t_ctrl_command;
-- iRAM 'push' interface :
dgwb_iram : out t_iram_push;
iram_push_done : in std_logic;
-- Admin block req/gnt interface.
dgwb_ac_access_req : out std_logic;
dgwb_ac_access_gnt : in std_logic;
-- WDP interface
dgwb_dqs_burst : out std_logic_vector((DWIDTH_RATIO/2) * MEM_IF_DQS_WIDTH - 1 downto 0);
dgwb_wdata_valid : out std_logic_vector((DWIDTH_RATIO/2) * MEM_IF_DQS_WIDTH - 1 downto 0);
dgwb_wdata : out std_logic_vector( DWIDTH_RATIO * MEM_IF_DWIDTH - 1 downto 0);
dgwb_dm : out std_logic_vector( DWIDTH_RATIO * MEM_IF_DM_WIDTH - 1 downto 0);
dgwb_dqs : out std_logic_vector( DWIDTH_RATIO - 1 downto 0);
dgwb_wdp_ovride : out std_logic;
-- addr/cmd output for write commands.
dgwb_ac : out t_addr_cmd_vector(0 to (DWIDTH_RATIO/2)-1);
bypassed_rdata : in std_logic_vector(MEM_IF_DWIDTH-1 downto 0);
-- odt settings per chip select
odt_settings : in t_odt_array(0 to MEM_IF_NUM_RANKS-1)
);
end entity;
library work;
-- The constant package (alt_mem_phy_constants_pkg) contains global 'constants' which are fixed
-- thoughout the sequencer and will not change (for constants which may change between sequencer
-- instances generics are used)
--
use work.ddr3_int_phy_alt_mem_phy_constants_pkg.all;
--
architecture rtl of ddr3_int_phy_alt_mem_phy_dgwb is
type t_dgwb_state is (
s_idle,
s_wait_admin,
s_write_btp, -- Writes bit-training pattern
s_write_ones, -- Writes ones
s_write_zeros, -- Writes zeros
s_write_mtp, -- Write more training patterns (requires read to check allignment)
s_write_01_pairs, -- Writes 01 pairs
s_write_1100_step,-- Write step function (half zeros, half ones)
s_write_0011_step,-- Write reversed step function (half ones, half zeros)
s_write_wlat, -- Writes the write latency into a memory address.
s_release_admin
);
constant c_seq_addr_cmd_config : t_addr_cmd_config_rec := set_config_rec(MEM_IF_ADDR_WIDTH, MEM_IF_BANKADDR_WIDTH, MEM_IF_NUM_RANKS, DWIDTH_RATIO, MEM_IF_MEMTYPE);
-- a prefix for all report signals to identify phy and sequencer block
--
constant dgwb_report_prefix : string := "ddr3_int_phy_alt_mem_phy_seq (dgwb) : ";
function dqs_pattern return std_logic_vector is
variable dqs : std_logic_vector( DWIDTH_RATIO - 1 downto 0);
begin
if DWIDTH_RATIO = 2 then
dqs := "10";
elsif DWIDTH_RATIO = 4 then
dqs := "1100";
else
report dgwb_report_prefix & "unsupported DWIDTH_RATIO in function dqs_pattern." severity failure;
end if;
return dqs;
end;
signal sig_addr_cmd : t_addr_cmd_vector(0 to (DWIDTH_RATIO/2)-1);
signal sig_dgwb_state : t_dgwb_state;
signal sig_dgwb_last_state : t_dgwb_state;
signal access_complete : std_logic;
signal generate_wdata : std_logic; -- for s_write_wlat only
-- current chip select being processed
signal current_cs : natural range 0 to MEM_IF_NUM_RANKS-1;
begin
dgwb_ac <= sig_addr_cmd;
-- Set IRAM interface to defaults
dgwb_iram <= defaults;
-- Master state machine. Generates state transitions.
master_dgwb_state_block : if True generate
signal sig_ctrl_dgwb : t_ctrl_command; -- registers ctrl_dgwb input.
begin
-- generate the current_cs signal to track which cs accessed by PHY at any instance
current_cs_proc : process (clk, rst_n)
begin
if rst_n = '0' then
current_cs <= 0;
elsif rising_edge(clk) then
if sig_ctrl_dgwb.command_req = '1' then
current_cs <= sig_ctrl_dgwb.command_op.current_cs;
end if;
end if;
end process;
master_dgwb_state_proc : process(rst_n, clk)
begin
if rst_n = '0' then
sig_dgwb_state <= s_idle;
sig_dgwb_last_state <= s_idle;
sig_ctrl_dgwb <= defaults;
elsif rising_edge(clk) then
case sig_dgwb_state is
when s_idle =>
if sig_ctrl_dgwb.command_req = '1' then
if (curr_active_block(sig_ctrl_dgwb.command) = dgwb) then
sig_dgwb_state <= s_wait_admin;
end if;
end if;
when s_wait_admin =>
case sig_ctrl_dgwb.command is
when cmd_write_btp => sig_dgwb_state <= s_write_btp;
when cmd_write_mtp => sig_dgwb_state <= s_write_mtp;
when cmd_was => sig_dgwb_state <= s_write_wlat;
when others =>
report dgwb_report_prefix & "unknown command" severity error;
end case;
if dgwb_ac_access_gnt /= '1' then
sig_dgwb_state <= s_wait_admin;
end if;
when s_write_btp =>
sig_dgwb_state <= s_write_zeros;
when s_write_zeros =>
if sig_dgwb_state = sig_dgwb_last_state and access_complete = '1' then
sig_dgwb_state <= s_write_ones;
end if;
when s_write_ones =>
if sig_dgwb_state = sig_dgwb_last_state and access_complete = '1' then
sig_dgwb_state <= s_release_admin;
end if;
when s_write_mtp =>
sig_dgwb_state <= s_write_01_pairs;
when s_write_01_pairs =>
if sig_dgwb_state = sig_dgwb_last_state and access_complete = '1' then
sig_dgwb_state <= s_write_1100_step;
end if;
when s_write_1100_step =>
if sig_dgwb_state = sig_dgwb_last_state and access_complete = '1' then
sig_dgwb_state <= s_write_0011_step;
end if;
when s_write_0011_step =>
if sig_dgwb_state = sig_dgwb_last_state and access_complete = '1' then
sig_dgwb_state <= s_release_admin;
end if;
when s_write_wlat =>
if sig_dgwb_state = sig_dgwb_last_state and access_complete = '1' then
sig_dgwb_state <= s_release_admin;
end if;
when s_release_admin =>
if dgwb_ac_access_gnt = '0' then
sig_dgwb_state <= s_idle;
end if;
when others =>
report dgwb_report_prefix & "undefined state in addr_cmd_proc" severity error;
sig_dgwb_state <= s_idle;
end case;
sig_dgwb_last_state <= sig_dgwb_state;
sig_ctrl_dgwb <= ctrl_dgwb;
end if;
end process;
end generate;
-- Generates writes
ac_write_block : if True generate
constant C_BURST_T : natural := C_CAL_BURST_LEN / DWIDTH_RATIO; -- Number of phy-clock cycles per burst
constant C_MAX_WLAT : natural := 2**ADV_LAT_WIDTH-1; -- Maximum latency in clock cycles
constant C_MAX_COUNT : natural := C_MAX_WLAT + C_BURST_T + 4*12 - 1; -- up to 12 consecutive writes at 4 cycle intervals
-- The following function sets the width over which
-- write latency should be repeated on the dq bus
-- the default value is MEM_IF_DQ_PER_DQS
function set_wlat_dq_rep_width return natural is
begin
for i in 1 to MEM_IF_DWIDTH/MEM_IF_DQ_PER_DQS loop
if (i*MEM_IF_DQ_PER_DQS) >= ADV_LAT_WIDTH then
return i*MEM_IF_DQ_PER_DQS;
end if;
end loop;
report dgwb_report_prefix & "the specified maximum write latency cannot be fully represented in the given number of DQ pins" & LF &
"** NOTE: This may cause overflow when setting ctl_wlat signal" severity warning;
return MEM_IF_DQ_PER_DQS;
end function;
constant C_WLAT_DQ_REP_WIDTH : natural := set_wlat_dq_rep_width;
signal sig_count : natural range 0 to 2**8 - 1;
begin
ac_write_proc : process(rst_n, clk)
begin
if rst_n = '0' then
dgwb_wdp_ovride <= '0';
dgwb_dqs <= (others => '0');
dgwb_dm <= (others => '1');
dgwb_wdata <= (others => '0');
dgwb_dqs_burst <= (others => '0');
dgwb_wdata_valid <= (others => '0');
generate_wdata <= '0'; -- for s_write_wlat only
sig_count <= 0;
sig_addr_cmd <= int_pup_reset(c_seq_addr_cmd_config);
access_complete <= '0';
elsif rising_edge(clk) then
dgwb_wdp_ovride <= '0';
dgwb_dqs <= (others => '0');
dgwb_dm <= (others => '1');
dgwb_wdata <= (others => '0');
dgwb_dqs_burst <= (others => '0');
dgwb_wdata_valid <= (others => '0');
sig_addr_cmd <= deselect(c_seq_addr_cmd_config, sig_addr_cmd);
access_complete <= '0';
generate_wdata <= '0'; -- for s_write_wlat only
case sig_dgwb_state is
when s_idle =>
sig_addr_cmd <= defaults(c_seq_addr_cmd_config);
-- require ones in locations:
-- 1. c_cal_ofs_ones (8 locations)
-- 2. 2nd half of location c_cal_ofs_xF5 (4 locations)
when s_write_ones =>
dgwb_wdp_ovride <= '1';
dgwb_dqs <= dqs_pattern;
dgwb_dm <= (others => '0');
dgwb_dqs_burst <= (others => '1');
-- Write ONES to DQ pins
dgwb_wdata <= (others => '1');
dgwb_wdata_valid <= (others => '1');
-- Issue write command
if sig_dgwb_state /= sig_dgwb_last_state then
sig_count <= 0;
else
-- ensure safe intervals for DDRx memory writes (min 4 mem clk cycles between writes for BC4 DDR3)
if sig_count = 0 then
sig_addr_cmd <= write(c_seq_addr_cmd_config,
sig_addr_cmd,
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_COL + c_cal_ofs_ones, -- address
2**current_cs, -- rank
4, -- burst length (fixed at BC4)
false); -- auto-precharge
elsif sig_count = 4 then
sig_addr_cmd <= write(c_seq_addr_cmd_config,
sig_addr_cmd,
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_COL + c_cal_ofs_ones + 4, -- address
2**current_cs, -- rank
4, -- burst length (fixed at BC4)
false); -- auto-precharge
elsif sig_count = 8 then
sig_addr_cmd <= write(c_seq_addr_cmd_config,
sig_addr_cmd,
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_COL + c_cal_ofs_xF5 + 4, -- address
2**current_cs, -- rank
4, -- burst length (fixed at BC4)
false); -- auto-precharge
end if;
sig_count <= sig_count + 1;
end if;
if sig_count = C_MAX_COUNT - 1 then
access_complete <= '1';
end if;
-- require zeros in locations:
-- 1. c_cal_ofs_zeros (8 locations)
-- 2. 1st half of c_cal_ofs_x30_almt_0 (4 locations)
-- 3. 1st half of c_cal_ofs_x30_almt_1 (4 locations)
when s_write_zeros =>
dgwb_wdp_ovride <= '1';
dgwb_dqs <= dqs_pattern;
dgwb_dm <= (others => '0');
dgwb_dqs_burst <= (others => '1');
-- Write ZEROS to DQ pins
dgwb_wdata <= (others => '0');
dgwb_wdata_valid <= (others => '1');
-- Issue write command
if sig_dgwb_state /= sig_dgwb_last_state then
sig_count <= 0;
else
if sig_count = 0 then
sig_addr_cmd <= write(c_seq_addr_cmd_config,
sig_addr_cmd,
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_COL + c_cal_ofs_zeros, -- address
2**current_cs, -- rank
4, -- burst length (fixed at BC4)
false); -- auto-precharge
elsif sig_count = 4 then
sig_addr_cmd <= write(c_seq_addr_cmd_config,
sig_addr_cmd,
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_COL + c_cal_ofs_zeros + 4, -- address
2**current_cs, -- rank
4, -- burst length (fixed at BC4)
false); -- auto-precharge
elsif sig_count = 8 then
sig_addr_cmd <= write(c_seq_addr_cmd_config,
sig_addr_cmd,
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_COL + c_cal_ofs_x30_almt_0, -- address
2**current_cs, -- rank
4, -- burst length (fixed at BC4)
false); -- auto-precharge
elsif sig_count = 12 then
sig_addr_cmd <= write(c_seq_addr_cmd_config,
sig_addr_cmd,
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_COL + c_cal_ofs_x30_almt_1, -- address
2**current_cs, -- rank
4, -- burst length (fixed at BC4)
false); -- auto-precharge
end if;
sig_count <= sig_count + 1;
end if;
if sig_count = C_MAX_COUNT - 1 then
access_complete <= '1';
end if;
-- require 0101 pattern in locations:
-- 1. 1st half of location c_cal_ofs_xF5 (4 locations)
when s_write_01_pairs =>
dgwb_wdp_ovride <= '1';
dgwb_dqs <= dqs_pattern;
dgwb_dm <= (others => '0');
dgwb_dqs_burst <= (others => '1');
dgwb_wdata_valid <= (others => '1');
-- Issue write command
if sig_dgwb_state /= sig_dgwb_last_state then
sig_count <= 0;
else
if sig_count = 0 then
sig_addr_cmd <= write(c_seq_addr_cmd_config,
sig_addr_cmd,
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_COL + c_cal_ofs_xF5, -- address
2**current_cs, -- rank
4, -- burst length
false); -- auto-precharge
end if;
sig_count <= sig_count + 1;
end if;
if sig_count = C_MAX_COUNT - 1 then
access_complete <= '1';
end if;
-- Write 01 to pairs of memory addresses
for i in 0 to dgwb_wdata'length / MEM_IF_DWIDTH - 1 loop
if i mod 2 = 0 then
dgwb_wdata((i+1)*MEM_IF_DWIDTH - 1 downto i*MEM_IF_DWIDTH) <= (others => '1');
else
dgwb_wdata((i+1)*MEM_IF_DWIDTH - 1 downto i*MEM_IF_DWIDTH) <= (others => '0');
end if;
end loop;
-- require pattern "0011" (or "1100") in locations:
-- 1. 2nd half of c_cal_ofs_x30_almt_0 (4 locations)
when s_write_0011_step =>
dgwb_wdp_ovride <= '1';
dgwb_dqs <= dqs_pattern;
dgwb_dm <= (others => '0');
dgwb_dqs_burst <= (others => '1');
dgwb_wdata_valid <= (others => '1');
-- Issue write command
if sig_dgwb_state /= sig_dgwb_last_state then
sig_addr_cmd <= write(c_seq_addr_cmd_config,
sig_addr_cmd,
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_COL + c_cal_ofs_x30_almt_0 + 4, -- address
2**current_cs, -- rank
4, -- burst length
false); -- auto-precharge
sig_count <= 0;
else
sig_count <= sig_count + 1;
end if;
if sig_count = C_MAX_COUNT - 1 then
access_complete <= '1';
end if;
-- Write 0011 step to column addresses. Note that
-- it cannot be determined which at this point. The
-- strategy is to write both alignments and see which
-- one is correct later on.
-- this calculation has 2 parts:
-- a) sig_count mod C_BURST_T is a timewise iterator of repetition of the pattern
-- b) i represents the temporal iterator of the pattern
-- it is required to sum a and b and switch the pattern between 0 and 1 every 2 locations in each dimension
-- Note: the same formulae is used below for the 1100 pattern
for i in 0 to dgwb_wdata'length / MEM_IF_DWIDTH - 1 loop
if ((sig_count mod C_BURST_T) + (i/2)) mod 2 = 0 then
dgwb_wdata((i+1)*MEM_IF_DWIDTH - 1 downto i*MEM_IF_DWIDTH) <= (others => '0');
else
dgwb_wdata((i+1)*MEM_IF_DWIDTH - 1 downto i*MEM_IF_DWIDTH) <= (others => '1');
end if;
end loop;
-- require pattern "1100" (or "0011") in locations:
-- 1. 2nd half of c_cal_ofs_x30_almt_1 (4 locations)
when s_write_1100_step =>
dgwb_wdp_ovride <= '1';
dgwb_dqs <= dqs_pattern;
dgwb_dm <= (others => '0');
dgwb_dqs_burst <= (others => '1');
dgwb_wdata_valid <= (others => '1');
-- Issue write command
if sig_dgwb_state /= sig_dgwb_last_state then
sig_addr_cmd <= write(c_seq_addr_cmd_config,
sig_addr_cmd,
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_COL + c_cal_ofs_x30_almt_1 + 4, -- address
2**current_cs, -- rank
4, -- burst length
false); -- auto-precharge
sig_count <= 0;
else
sig_count <= sig_count + 1;
end if;
if sig_count = C_MAX_COUNT - 1 then
access_complete <= '1';
end if;
-- Write 1100 step to column addresses. Note that
-- it cannot be determined which at this point. The
-- strategy is to write both alignments and see which
-- one is correct later on.
for i in 0 to dgwb_wdata'length / MEM_IF_DWIDTH - 1 loop
if ((sig_count mod C_BURST_T) + (i/2)) mod 2 = 0 then
dgwb_wdata((i+1)*MEM_IF_DWIDTH - 1 downto i*MEM_IF_DWIDTH) <= (others => '1');
else
dgwb_wdata((i+1)*MEM_IF_DWIDTH - 1 downto i*MEM_IF_DWIDTH) <= (others => '0');
end if;
end loop;
when s_write_wlat =>
-- Effect:
-- *Writes the memory latency to an array formed
-- from memory addr=[2*C_CAL_BURST_LEN-(3*C_CAL_BURST_LEN-1)].
-- The write latency is written to pairs of addresses
-- across the given range.
--
-- Example
-- C_CAL_BURST_LEN = 4
-- addr 8 - 9 [WLAT] size = 2*MEM_IF_DWIDTH bits
-- addr 10 - 11 [WLAT] size = 2*MEM_IF_DWIDTH bits
--
dgwb_wdp_ovride <= '1';
dgwb_dqs <= dqs_pattern;
dgwb_dm <= (others => '0');
dgwb_wdata <= (others => '0');
dgwb_dqs_burst <= (others => '1');
dgwb_wdata_valid <= (others => '1');
if sig_dgwb_state /= sig_dgwb_last_state then
sig_addr_cmd <= write(c_seq_addr_cmd_config, -- A/C configuration
sig_addr_cmd,
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_COL + c_cal_ofs_wd_lat, -- address
2**current_cs, -- rank
8, -- burst length (8 for DDR3 and 4 for DDR/DDR2)
false); -- auto-precharge
sig_count <= 0;
else
-- hold wdata_valid and wdata 2 clock cycles
-- 1 - because ac signal registered at top level of sequencer
-- 2 - because want time to dqs_burst edge which occurs 1 cycle earlier
-- than wdata_valid in an AFI compliant controller
generate_wdata <= '1';
end if;
if generate_wdata = '1' then
for i in 0 to dgwb_wdata'length/C_WLAT_DQ_REP_WIDTH - 1 loop
dgwb_wdata((i+1)*C_WLAT_DQ_REP_WIDTH - 1 downto i*C_WLAT_DQ_REP_WIDTH) <= std_logic_vector(to_unsigned(sig_count, C_WLAT_DQ_REP_WIDTH));
end loop;
-- delay by 1 clock cycle to account for 1 cycle discrepancy
-- between dqs_burst and wdata_valid
if sig_count = C_MAX_COUNT then
access_complete <= '1';
end if;
sig_count <= sig_count + 1;
end if;
when others =>
null;
end case;
-- mask odt signal
for i in 0 to (DWIDTH_RATIO/2)-1 loop
sig_addr_cmd(i).odt <= odt_settings(current_cs).write;
end loop;
end if;
end process;
end generate;
-- Handles handshaking for access to address/command
ac_handshake_proc : process(rst_n, clk)
begin
if rst_n = '0' then
dgwb_ctrl <= defaults;
dgwb_ac_access_req <= '0';
elsif rising_edge(clk) then
dgwb_ctrl <= defaults;
dgwb_ac_access_req <= '0';
if sig_dgwb_state /= s_idle and sig_dgwb_state /= s_release_admin then
dgwb_ac_access_req <= '1';
elsif sig_dgwb_state = s_idle or sig_dgwb_state = s_release_admin then
dgwb_ac_access_req <= '0';
else
report dgwb_report_prefix & "unexpected state in ac_handshake_proc so haven't requested access to address/command." severity warning;
end if;
if sig_dgwb_state = s_wait_admin and sig_dgwb_last_state = s_idle then
dgwb_ctrl.command_ack <= '1';
end if;
if sig_dgwb_state = s_idle and sig_dgwb_last_state = s_release_admin then
dgwb_ctrl.command_done <= '1';
end if;
end if;
end process;
end architecture rtl;
--
-- -----------------------------------------------------------------------------
-- Abstract : ctrl block for the non-levelling AFI PHY sequencer
-- This block is the central control unit for the sequencer. The method
-- of control is to issue commands (prefixed cmd_) to each of the other
-- sequencer blocks to execute. Each command corresponds to a stage of
-- the AFI PHY calibaration stage, and in turn each state represents a
-- command or a supplimentary flow control operation. In addition to
-- controlling the sequencer this block also checks for time out
-- conditions which occur when a different system block is faulty.
-- -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
-- The record package (alt_mem_phy_record_pkg) is used to combine command and status signals
-- (into records) to be passed between sequencer blocks. It also contains type and record definitions
-- for the stages of DRAM memory calibration.
--
use work.ddr3_int_phy_alt_mem_phy_record_pkg.all;
-- The iram address package (alt_mem_phy_iram_addr_pkg) is used to define the base addresses used
-- for iram writes during calibration
--
use work.ddr3_int_phy_alt_mem_phy_iram_addr_pkg.all;
--
entity ddr3_int_phy_alt_mem_phy_ctrl is
generic (
FAMILYGROUP_ID : natural;
MEM_IF_DLL_LOCK_COUNT : natural;
MEM_IF_MEMTYPE : string;
DWIDTH_RATIO : natural;
IRAM_ADDRESSING : t_base_hdr_addresses;
MEM_IF_CLK_PS : natural;
TRACKING_INTERVAL_IN_MS : natural;
MEM_IF_NUM_RANKS : natural;
MEM_IF_DQS_WIDTH : natural;
GENERATE_ADDITIONAL_DBG_RTL : natural;
SIM_TIME_REDUCTIONS : natural; -- if 0 null, if 1 skip rrp, if 2 rrp for 1 dqs group and 1 cs
ACK_SEVERITY : severity_level
);
port (
-- clk / reset
clk : in std_logic;
rst_n : in std_logic;
-- calibration status and redo request
ctl_init_success : out std_logic;
ctl_init_fail : out std_logic;
ctl_recalibrate_req : in std_logic; -- acts as a synchronous reset
-- status signals from iram
iram_status : in t_iram_stat;
iram_push_done : in std_logic;
-- standard control signal to all blocks
ctrl_op_rec : out t_ctrl_command;
-- standardised response from all system blocks
admin_ctrl : in t_ctrl_stat;
dgrb_ctrl : in t_ctrl_stat;
dgwb_ctrl : in t_ctrl_stat;
-- mmi to ctrl interface
mmi_ctrl : in t_mmi_ctrl;
ctrl_mmi : out t_ctrl_mmi;
-- byte lane select
ctl_cal_byte_lanes : in std_logic_vector(MEM_IF_NUM_RANKS * MEM_IF_DQS_WIDTH - 1 downto 0);
-- signals to control the ac_nt setting
dgrb_ctrl_ac_nt_good : in std_logic;
int_ac_nt : out std_logic_vector(((DWIDTH_RATIO+2)/4) - 1 downto 0); -- width of 1 for DWIDTH_RATIO =2,4 and 2 for DWIDTH_RATIO = 8
-- the following signals are reserved for future use
ctrl_iram_push : out t_ctrl_iram
);
end entity;
library work;
-- The constant package (alt_mem_phy_constants_pkg) contains global 'constants' which are fixed
-- thoughout the sequencer and will not change (for constants which may change between sequencer
-- instances generics are used)
--
use work.ddr3_int_phy_alt_mem_phy_constants_pkg.all;
--
architecture struct of ddr3_int_phy_alt_mem_phy_ctrl is
-- a prefix for all report signals to identify phy and sequencer block
--
constant ctrl_report_prefix : string := "ddr3_int_phy_alt_mem_phy_seq (ctrl) : ";
-- decoder to find the relevant disable bit (from mmi registers) for a given state
function find_dis_bit
(
state : t_master_sm_state;
mmi_ctrl : t_mmi_ctrl
) return std_logic is
variable v_dis : std_logic;
begin
case state is
when s_phy_initialise => v_dis := mmi_ctrl.hl_css.phy_initialise_dis;
when s_init_dram |
s_prog_cal_mr => v_dis := mmi_ctrl.hl_css.init_dram_dis;
when s_write_ihi => v_dis := mmi_ctrl.hl_css.write_ihi_dis;
when s_cal => v_dis := mmi_ctrl.hl_css.cal_dis;
when s_write_btp => v_dis := mmi_ctrl.hl_css.write_btp_dis;
when s_write_mtp => v_dis := mmi_ctrl.hl_css.write_mtp_dis;
when s_read_mtp => v_dis := mmi_ctrl.hl_css.read_mtp_dis;
when s_rrp_reset => v_dis := mmi_ctrl.hl_css.rrp_reset_dis;
when s_rrp_sweep => v_dis := mmi_ctrl.hl_css.rrp_sweep_dis;
when s_rrp_seek => v_dis := mmi_ctrl.hl_css.rrp_seek_dis;
when s_rdv => v_dis := mmi_ctrl.hl_css.rdv_dis;
when s_poa => v_dis := mmi_ctrl.hl_css.poa_dis;
when s_was => v_dis := mmi_ctrl.hl_css.was_dis;
when s_adv_rd_lat => v_dis := mmi_ctrl.hl_css.adv_rd_lat_dis;
when s_adv_wr_lat => v_dis := mmi_ctrl.hl_css.adv_wr_lat_dis;
when s_prep_customer_mr_setup => v_dis := mmi_ctrl.hl_css.prep_customer_mr_setup_dis;
when s_tracking_setup |
s_tracking => v_dis := mmi_ctrl.hl_css.tracking_dis;
when others => v_dis := '1'; -- default change stage
end case;
return v_dis;
end function;
-- decoder to find the relevant command for a given state
function find_cmd
(
state : t_master_sm_state
) return t_ctrl_cmd_id is
begin
case state is
when s_phy_initialise => return cmd_phy_initialise;
when s_init_dram => return cmd_init_dram;
when s_prog_cal_mr => return cmd_prog_cal_mr;
when s_write_ihi => return cmd_write_ihi;
when s_cal => return cmd_idle;
when s_write_btp => return cmd_write_btp;
when s_write_mtp => return cmd_write_mtp;
when s_read_mtp => return cmd_read_mtp;
when s_rrp_reset => return cmd_rrp_reset;
when s_rrp_sweep => return cmd_rrp_sweep;
when s_rrp_seek => return cmd_rrp_seek;
when s_rdv => return cmd_rdv;
when s_poa => return cmd_poa;
when s_was => return cmd_was;
when s_adv_rd_lat => return cmd_prep_adv_rd_lat;
when s_adv_wr_lat => return cmd_prep_adv_wr_lat;
when s_prep_customer_mr_setup => return cmd_prep_customer_mr_setup;
when s_tracking_setup |
s_tracking => return cmd_tr_due;
when others => return cmd_idle;
end case;
end function;
function mcs_rw_state -- returns true for multiple cs read/write states
(
state : t_master_sm_state
) return boolean is
begin
case state is
when s_write_btp | s_write_mtp | s_rrp_sweep =>
return true;
when s_reset | s_phy_initialise | s_init_dram | s_prog_cal_mr | s_write_ihi | s_cal |
s_read_mtp | s_rrp_reset | s_rrp_seek | s_rdv | s_poa |
s_was | s_adv_rd_lat | s_adv_wr_lat | s_prep_customer_mr_setup |
s_tracking_setup | s_tracking | s_operational | s_non_operational =>
return false;
when others =>
--
return false;
end case;
end function;
-- timing parameters
constant c_done_timeout_count : natural := 32768;
constant c_ack_timeout_count : natural := 1000;
constant c_ticks_per_ms : natural := 1000000000/(MEM_IF_CLK_PS*(DWIDTH_RATIO/2));
constant c_ticks_per_10us : natural := 10000000 /(MEM_IF_CLK_PS*(DWIDTH_RATIO/2));
-- local copy of calibration fail/success signals
signal int_ctl_init_fail : std_logic;
signal int_ctl_init_success : std_logic;
-- state machine (master for sequencer)
signal state : t_master_sm_state;
signal last_state : t_master_sm_state;
-- flow control signals for state machine
signal dis_state : std_logic; -- disable state
signal hold_state : std_logic; -- hold in state for 1 clock cycle
signal master_ctrl_op_rec : t_ctrl_command; -- master command record to all sequencer blocks
signal master_ctrl_iram_push : t_ctrl_iram; -- record indicating control details for pushes
signal dll_lock_counter : natural range MEM_IF_DLL_LOCK_COUNT - 1 downto 0; -- to wait for dll to lock
signal iram_init_complete : std_logic;
-- timeout signals to check if a block has 'hung'
signal timeout_counter : natural range c_done_timeout_count - 1 downto 0;
signal timeout_counter_stop : std_logic;
signal timeout_counter_enable : std_logic;
signal timeout_counter_clear : std_logic;
signal cmd_req_asserted : std_logic; -- a command has been issued
signal flag_ack_timeout : std_logic; -- req -> ack timed out
signal flag_done_timeout : std_logic; -- reg -> done timed out
signal waiting_for_ack : std_logic; -- command issued
signal cmd_ack_seen : std_logic; -- command completed
signal curr_ctrl : t_ctrl_stat; -- response for current active block
signal curr_cmd : t_ctrl_cmd_id;
-- store state information based on issued command
signal int_ctrl_prev_stage : t_ctrl_cmd_id;
signal int_ctrl_current_stage : t_ctrl_cmd_id;
-- multiple chip select counter
signal cs_counter : natural range 0 to MEM_IF_NUM_RANKS - 1;
signal reissue_cmd_req : std_logic; -- reissue command request for multiple cs
signal cal_cs_enabled : std_logic_vector(MEM_IF_NUM_RANKS - 1 downto 0);
-- signals to check the ac_nt setting
signal ac_nt_almts_checked : natural range 0 to DWIDTH_RATIO/2-1;
signal ac_nt : std_logic_vector(((DWIDTH_RATIO+2)/4) - 1 downto 0);
-- track the mtp alignment setting
signal mtp_almts_checked : natural range 0 to 2;
signal mtp_correct_almt : natural range 0 to 1;
signal mtp_no_valid_almt : std_logic;
signal mtp_both_valid_almt : std_logic;
signal mtp_err : std_logic;
-- tracking timing
signal milisecond_tick_gen_count : natural range 0 to c_ticks_per_ms -1 := c_ticks_per_ms -1;
signal tracking_ms_counter : natural range 0 to 255;
signal tracking_update_due : std_logic;
begin -- architecture struct
-------------------------------------------------------------------------------
-- check if chip selects are enabled
-- this only effects reactive stages (i,e, those requiring memory reads)
-------------------------------------------------------------------------------
process(ctl_cal_byte_lanes)
variable v_cs_enabled : std_logic;
begin
for i in 0 to MEM_IF_NUM_RANKS - 1 loop
-- check if any bytes enabled
v_cs_enabled := '0';
for j in 0 to MEM_IF_DQS_WIDTH - 1 loop
v_cs_enabled := v_cs_enabled or ctl_cal_byte_lanes(i*MEM_IF_DQS_WIDTH + j);
end loop;
-- if any byte enabled set cs as enabled else not
cal_cs_enabled(i) <= v_cs_enabled;
-- sanity checking:
if i = 0 and v_cs_enabled = '0' then
report ctrl_report_prefix & " disabling of chip select 0 is unsupported by the sequencer," & LF &
"-> if this is your intention then please remap CS pins such that CS 0 is not disabled" severity failure;
end if;
end loop;
end process;
-- -----------------------------------------------------------------------------
-- dll lock counter
-- -----------------------------------------------------------------------------
process(clk, rst_n)
begin
if rst_n = '0' then
dll_lock_counter <= MEM_IF_DLL_LOCK_COUNT -1;
elsif rising_edge(clk) then
if ctl_recalibrate_req = '1' then
dll_lock_counter <= MEM_IF_DLL_LOCK_COUNT -1;
elsif dll_lock_counter /= 0 then
dll_lock_counter <= dll_lock_counter - 1;
end if;
end if;
end process;
-- -----------------------------------------------------------------------------
-- timeout counter : this counter is used to determine if an ack, or done has
-- not been received within the expected number of clock cycles of a req being
-- asserted.
-- -----------------------------------------------------------------------------
process(clk, rst_n)
begin
if rst_n = '0' then
timeout_counter <= c_done_timeout_count - 1;
elsif rising_edge(clk) then
if timeout_counter_clear = '1' then
timeout_counter <= c_done_timeout_count - 1;
elsif timeout_counter_enable = '1' and state /= s_init_dram then
if timeout_counter /= 0 then
timeout_counter <= timeout_counter - 1;
end if;
end if;
end if;
end process;
-- -----------------------------------------------------------------------------
-- register current ctrl signal based on current command
-- -----------------------------------------------------------------------------
process(clk, rst_n)
begin
if rst_n = '0' then
curr_ctrl <= defaults;
curr_cmd <= cmd_idle;
elsif rising_edge(clk) then
case curr_active_block(curr_cmd) is
when admin => curr_ctrl <= admin_ctrl;
when dgrb => curr_ctrl <= dgrb_ctrl;
when dgwb => curr_ctrl <= dgwb_ctrl;
when others => curr_ctrl <= defaults;
end case;
curr_cmd <= master_ctrl_op_rec.command;
end if;
end process;
-- -----------------------------------------------------------------------------
-- generation of cmd_ack_seen
-- -----------------------------------------------------------------------------
process (curr_ctrl)
begin
cmd_ack_seen <= curr_ctrl.command_ack;
end process;
-------------------------------------------------------------------------------
-- generation of waiting_for_ack flag (to determine whether ack has timed out)
-------------------------------------------------------------------------------
process(clk, rst_n)
begin
if rst_n = '0' then
waiting_for_ack <= '0';
elsif rising_edge(clk) then
if cmd_req_asserted = '1' then
waiting_for_ack <= '1';
elsif cmd_ack_seen = '1' then
waiting_for_ack <= '0';
end if;
end if;
end process;
-- -----------------------------------------------------------------------------
-- generation of timeout flags
-- -----------------------------------------------------------------------------
process(clk, rst_n)
begin
if rst_n = '0' then
flag_ack_timeout <= '0';
flag_done_timeout <= '0';
elsif rising_edge(clk) then
if mmi_ctrl.calibration_start = '1' or ctl_recalibrate_req = '1' then
flag_ack_timeout <= '0';
elsif timeout_counter = 0 and waiting_for_ack = '1' then
flag_ack_timeout <= '1';
end if;
if mmi_ctrl.calibration_start = '1' or ctl_recalibrate_req = '1' then
flag_done_timeout <= '0';
elsif timeout_counter = 0 and
state /= s_rrp_sweep and -- rrp can take enough cycles to overflow counter so don't timeout
state /= s_init_dram and -- init_dram takes about 200 us, so don't timeout
timeout_counter_clear /= '1' then -- check if currently clearing the timeout (i.e. command_done asserted for s_init_dram or s_rrp_sweep)
flag_done_timeout <= '1';
end if;
end if;
end process;
-- generation of timeout_counter_stop
timeout_counter_stop <= curr_ctrl.command_done;
-- -----------------------------------------------------------------------------
-- generation of timeout_counter_enable and timeout_counter_clear
-- -----------------------------------------------------------------------------
process(clk, rst_n)
begin
if rst_n = '0' then
timeout_counter_enable <= '0';
timeout_counter_clear <= '0';
elsif rising_edge(clk) then
if cmd_req_asserted = '1' then
timeout_counter_enable <= '1';
timeout_counter_clear <= '0';
elsif timeout_counter_stop = '1'
or state = s_operational
or state = s_non_operational
or state = s_reset then
timeout_counter_enable <= '0';
timeout_counter_clear <= '1';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- assignment to ctrl_mmi record
-------------------------------------------------------------------------------
process (clk, rst_n)
variable v_ctrl_mmi : t_ctrl_mmi;
begin
if rst_n = '0' then
v_ctrl_mmi := defaults;
ctrl_mmi <= defaults;
int_ctrl_prev_stage <= cmd_idle;
int_ctrl_current_stage <= cmd_idle;
elsif rising_edge(clk) then
ctrl_mmi <= v_ctrl_mmi;
v_ctrl_mmi.ctrl_calibration_success := '0';
v_ctrl_mmi.ctrl_calibration_fail := '0';
if (curr_ctrl.command_ack = '1') then
case state is
when s_init_dram => v_ctrl_mmi.ctrl_cal_stage_ack_seen.init_dram := '1';
when s_write_btp => v_ctrl_mmi.ctrl_cal_stage_ack_seen.write_btp := '1';
when s_write_mtp => v_ctrl_mmi.ctrl_cal_stage_ack_seen.write_mtp := '1';
when s_read_mtp => v_ctrl_mmi.ctrl_cal_stage_ack_seen.read_mtp := '1';
when s_rrp_reset => v_ctrl_mmi.ctrl_cal_stage_ack_seen.rrp_reset := '1';
when s_rrp_sweep => v_ctrl_mmi.ctrl_cal_stage_ack_seen.rrp_sweep := '1';
when s_rrp_seek => v_ctrl_mmi.ctrl_cal_stage_ack_seen.rrp_seek := '1';
when s_rdv => v_ctrl_mmi.ctrl_cal_stage_ack_seen.rdv := '1';
when s_poa => v_ctrl_mmi.ctrl_cal_stage_ack_seen.poa := '1';
when s_was => v_ctrl_mmi.ctrl_cal_stage_ack_seen.was := '1';
when s_adv_rd_lat => v_ctrl_mmi.ctrl_cal_stage_ack_seen.adv_rd_lat := '1';
when s_adv_wr_lat => v_ctrl_mmi.ctrl_cal_stage_ack_seen.adv_wr_lat := '1';
when s_prep_customer_mr_setup => v_ctrl_mmi.ctrl_cal_stage_ack_seen.prep_customer_mr_setup := '1';
when s_tracking_setup |
s_tracking => v_ctrl_mmi.ctrl_cal_stage_ack_seen.tracking_setup := '1';
when others => null;
end case;
end if;
-- special 'ack' (actually finished) triggers for phy_initialise, writing iram header info and s_cal
if state = s_phy_initialise then
if iram_status.init_done = '1' and dll_lock_counter = 0 then
v_ctrl_mmi.ctrl_cal_stage_ack_seen.phy_initialise := '1';
end if;
end if;
if state = s_write_ihi then
if iram_push_done = '1' then
v_ctrl_mmi.ctrl_cal_stage_ack_seen.write_ihi := '1';
end if;
end if;
if state = s_cal and find_dis_bit(state, mmi_ctrl) = '0' then -- if cal state and calibration not disabled acknowledge
v_ctrl_mmi.ctrl_cal_stage_ack_seen.cal := '1';
end if;
if state = s_operational then
v_ctrl_mmi.ctrl_calibration_success := '1';
end if;
if state = s_non_operational then
v_ctrl_mmi.ctrl_calibration_fail := '1';
end if;
if state /= s_non_operational then
v_ctrl_mmi.ctrl_current_active_block := master_ctrl_iram_push.active_block;
v_ctrl_mmi.ctrl_current_stage := master_ctrl_op_rec.command;
else
v_ctrl_mmi.ctrl_current_active_block := v_ctrl_mmi.ctrl_current_active_block;
v_ctrl_mmi.ctrl_current_stage := v_ctrl_mmi.ctrl_current_stage;
end if;
int_ctrl_prev_stage <= int_ctrl_current_stage;
int_ctrl_current_stage <= v_ctrl_mmi.ctrl_current_stage;
if int_ctrl_prev_stage /= int_ctrl_current_stage then
v_ctrl_mmi.ctrl_current_stage_done := '0';
else
if curr_ctrl.command_done = '1' then
v_ctrl_mmi.ctrl_current_stage_done := '1';
end if;
end if;
v_ctrl_mmi.master_state_r := last_state;
if mmi_ctrl.calibration_start = '1' or ctl_recalibrate_req = '1' then
v_ctrl_mmi := defaults;
ctrl_mmi <= defaults;
end if;
-- assert error codes here
if curr_ctrl.command_err = '1' then
v_ctrl_mmi.ctrl_err_code := curr_ctrl.command_result;
elsif flag_ack_timeout = '1' then
v_ctrl_mmi.ctrl_err_code := std_logic_vector(to_unsigned(c_err_ctrl_ack_timeout, v_ctrl_mmi.ctrl_err_code'length));
elsif flag_done_timeout = '1' then
v_ctrl_mmi.ctrl_err_code := std_logic_vector(to_unsigned(c_err_ctrl_done_timeout, v_ctrl_mmi.ctrl_err_code'length));
elsif mtp_err = '1' then
if mtp_no_valid_almt = '1' then
v_ctrl_mmi.ctrl_err_code := std_logic_vector(to_unsigned(C_ERR_READ_MTP_NO_VALID_ALMT, v_ctrl_mmi.ctrl_err_code'length));
elsif mtp_both_valid_almt = '1' then
v_ctrl_mmi.ctrl_err_code := std_logic_vector(to_unsigned(C_ERR_READ_MTP_BOTH_ALMT_PASS, v_ctrl_mmi.ctrl_err_code'length));
end if;
end if;
end if;
end process;
-- check if iram finished init
process(iram_status)
begin
if GENERATE_ADDITIONAL_DBG_RTL = 0 then
iram_init_complete <= '1';
else
iram_init_complete <= iram_status.init_done;
end if;
end process;
-- -----------------------------------------------------------------------------
-- master state machine
-- (this controls the operation of the entire sequencer)
-- the states are summarised as follows:
-- s_reset
-- s_phy_initialise - wait for dll lock and init done flag from iram
-- s_init_dram, -- dram initialisation - reset sequence
-- s_prog_cal_mr, -- dram initialisation - programming mode registers (once per chip select)
-- s_write_ihi - write header information in iRAM
-- s_cal - check if calibration to be executed
-- s_write_btp - write burst training pattern
-- s_write_mtp - write more training pattern
-- s_rrp_reset - read resync phase setup - reset initial conditions
-- s_rrp_sweep - read resync phase setup - sweep phases per chip select
-- s_read_mtp - read training patterns to find correct alignment for 1100 burst
-- (this is a special case of s_rrp_seek with no resych phase setting)
-- s_rrp_seek - read resync phase setup - seek correct alignment
-- s_rdv - read data valid setup
-- s_poa - calibrate the postamble
-- s_was - write datapath setup (ac to write data timing)
-- s_adv_rd_lat - advertise read latency
-- s_adv_wr_lat - advertise write latency
-- s_tracking_setup - perform tracking (1st pass to setup mimic window)
-- s_prep_customer_mr_setup - apply user mode register settings (in admin block)
-- s_tracking - perform tracking (subsequent passes in user mode)
-- s_operational - calibration successful and in user mode
-- s_non_operational - calibration unsuccessful and in user mode
-- -----------------------------------------------------------------------------
process(clk, rst_n)
variable v_seen_ack : boolean;
variable v_dis : std_logic; -- disable bit
begin
if rst_n = '0' then
state <= s_reset;
last_state <= s_reset;
int_ctl_init_success <= '0';
int_ctl_init_fail <= '0';
v_seen_ack := false;
hold_state <= '0';
cs_counter <= 0;
mtp_almts_checked <= 0;
ac_nt <= (others => '1');
ac_nt_almts_checked <= 0;
reissue_cmd_req <= '0';
dis_state <= '0';
elsif rising_edge(clk) then
last_state <= state;
-- check if state_tx required
if curr_ctrl.command_ack = '1' then
v_seen_ack := true;
end if;
-- find disable bit for current state (do once to avoid exit mid-state)
if state /= last_state then
dis_state <= find_dis_bit(state, mmi_ctrl);
end if;
-- Set special conditions:
if state = s_reset or
state = s_operational or
state = s_non_operational then
dis_state <= '1';
end if;
-- override to ensure execution of next state logic
if (state = s_cal) then
dis_state <= '1';
end if;
-- if header writing in iram check finished
if (state = s_write_ihi) then
if iram_push_done = '1' or mmi_ctrl.hl_css.write_ihi_dis = '1' then
dis_state <= '1';
else
dis_state <= '0';
end if;
end if;
-- Special condition for initialisation
if (state = s_phy_initialise) then
if ((dll_lock_counter = 0) and (iram_init_complete = '1')) or
(mmi_ctrl.hl_css.phy_initialise_dis = '1') then
dis_state <= '1';
else
dis_state <= '0';
end if;
end if;
if dis_state = '1' then
v_seen_ack := false;
elsif curr_ctrl.command_done = '1' then
if v_seen_ack = false then
report ctrl_report_prefix & "have not seen ack but have seen command done from " & t_ctrl_active_block'image(curr_active_block(master_ctrl_op_rec.command)) & "_block in state " & t_master_sm_state'image(state) severity warning;
end if;
v_seen_ack := false;
end if;
-- default do not reissue command request
reissue_cmd_req <= '0';
if (hold_state = '1') then
hold_state <= '0';
else
if ((dis_state = '1') or
(curr_ctrl.command_done = '1') or
((cal_cs_enabled(cs_counter) = '0') and (mcs_rw_state(state) = True))) then -- current chip select is disabled and read/write
hold_state <= '1';
-- Only reset the below if making state change
int_ctl_init_success <= '0';
int_ctl_init_fail <= '0';
-- default chip select counter gets reset to zero
cs_counter <= 0;
case state is
when s_reset => state <= s_phy_initialise;
ac_nt <= (others => '1');
mtp_almts_checked <= 0;
ac_nt_almts_checked <= 0;
when s_phy_initialise => state <= s_init_dram;
when s_init_dram => state <= s_prog_cal_mr;
when s_prog_cal_mr => if cs_counter = MEM_IF_NUM_RANKS - 1 then
-- if no debug interface don't write iram header
if GENERATE_ADDITIONAL_DBG_RTL = 1 then
state <= s_write_ihi;
else
state <= s_cal;
end if;
else
cs_counter <= cs_counter + 1;
reissue_cmd_req <= '1';
end if;
when s_write_ihi => state <= s_cal;
when s_cal => if mmi_ctrl.hl_css.cal_dis = '0' then
state <= s_write_btp;
else
state <= s_tracking_setup;
end if;
-- always enter s_cal before calibration so reset some variables here
mtp_almts_checked <= 0;
ac_nt_almts_checked <= 0;
when s_write_btp => if cs_counter = MEM_IF_NUM_RANKS-1 or
SIM_TIME_REDUCTIONS = 2 then
state <= s_write_mtp;
else
cs_counter <= cs_counter + 1;
-- only reissue command if current chip select enabled
if cal_cs_enabled(cs_counter + 1) = '1' then
reissue_cmd_req <= '1';
end if;
end if;
when s_write_mtp => if cs_counter = MEM_IF_NUM_RANKS - 1 or
SIM_TIME_REDUCTIONS = 2 then
if SIM_TIME_REDUCTIONS = 1 then
state <= s_rdv;
else
state <= s_rrp_reset;
end if;
else
cs_counter <= cs_counter + 1;
-- only reissue command if current chip select enabled
if cal_cs_enabled(cs_counter + 1) = '1' then
reissue_cmd_req <= '1';
end if;
end if;
when s_rrp_reset => state <= s_rrp_sweep;
when s_rrp_sweep => if cs_counter = MEM_IF_NUM_RANKS - 1 or
mtp_almts_checked /= 2 or
SIM_TIME_REDUCTIONS = 2 then
if mtp_almts_checked /= 2 then
state <= s_read_mtp;
else
state <= s_rrp_seek;
end if;
else
cs_counter <= cs_counter + 1;
-- only reissue command if current chip select enabled
if cal_cs_enabled(cs_counter + 1) = '1' then
reissue_cmd_req <= '1';
end if;
end if;
when s_read_mtp => if mtp_almts_checked /= 2 then
mtp_almts_checked <= mtp_almts_checked + 1;
end if;
state <= s_rrp_reset;
when s_rrp_seek => state <= s_rdv;
when s_rdv => state <= s_was;
when s_was => state <= s_adv_rd_lat;
when s_adv_rd_lat => state <= s_adv_wr_lat;
when s_adv_wr_lat => if dgrb_ctrl_ac_nt_good = '1' then
state <= s_poa;
else
if ac_nt_almts_checked = (DWIDTH_RATIO/2 - 1) then
state <= s_non_operational;
else
-- switch alignment and restart calibration
ac_nt <= std_logic_vector(unsigned(ac_nt) + 1);
ac_nt_almts_checked <= ac_nt_almts_checked + 1;
if SIM_TIME_REDUCTIONS = 1 then
state <= s_rdv;
else
state <= s_rrp_reset;
end if;
mtp_almts_checked <= 0;
end if;
end if;
when s_poa => state <= s_tracking_setup;
when s_tracking_setup => state <= s_prep_customer_mr_setup;
when s_prep_customer_mr_setup => if cs_counter = MEM_IF_NUM_RANKS - 1 then -- s_prep_customer_mr_setup is always performed over all cs
state <= s_operational;
else
cs_counter <= cs_counter + 1;
reissue_cmd_req <= '1';
end if;
when s_tracking => state <= s_operational;
int_ctl_init_success <= int_ctl_init_success;
int_ctl_init_fail <= int_ctl_init_fail;
when s_operational => int_ctl_init_success <= '1';
int_ctl_init_fail <= '0';
hold_state <= '0';
if tracking_update_due = '1' and mmi_ctrl.hl_css.tracking_dis = '0' then
state <= s_tracking;
hold_state <= '1';
end if;
when s_non_operational => int_ctl_init_success <= '0';
int_ctl_init_fail <= '1';
hold_state <= '0';
if last_state /= s_non_operational then -- print a warning on entering this state
report ctrl_report_prefix & "memory calibration has failed (output from ctrl block)" severity WARNING;
end if;
when others => state <= t_master_sm_state'succ(state);
end case;
end if;
end if;
if flag_done_timeout = '1' -- no done signal from current active block
or flag_ack_timeout = '1' -- or no ack signal from current active block
or curr_ctrl.command_err = '1' -- or an error from current active block
or mtp_err = '1' then -- or an error due to mtp alignment
state <= s_non_operational;
end if;
if mmi_ctrl.calibration_start = '1' then -- restart calibration process
state <= s_cal;
end if;
if ctl_recalibrate_req = '1' then -- restart all incl. initialisation
state <= s_reset;
end if;
end if;
end process;
-- generate output calibration fail/success signals
process(clk, rst_n)
begin
if rst_n = '0' then
ctl_init_fail <= '0';
ctl_init_success <= '0';
elsif rising_edge(clk) then
ctl_init_fail <= int_ctl_init_fail;
ctl_init_success <= int_ctl_init_success;
end if;
end process;
-- assign ac_nt to the output int_ac_nt
process(ac_nt)
begin
int_ac_nt <= ac_nt;
end process;
-- ------------------------------------------------------------------------------
-- find correct mtp_almt from returned data
-- ------------------------------------------------------------------------------
mtp_almt: block
signal dvw_size_a0 : natural range 0 to 255; -- maximum size of command result
signal dvw_size_a1 : natural range 0 to 255;
begin
process (clk, rst_n)
variable v_dvw_a0_small : boolean;
variable v_dvw_a1_small : boolean;
begin
if rst_n = '0' then
mtp_correct_almt <= 0;
dvw_size_a0 <= 0;
dvw_size_a1 <= 0;
mtp_no_valid_almt <= '0';
mtp_both_valid_almt <= '0';
mtp_err <= '0';
elsif rising_edge(clk) then
-- update the dvw sizes
if state = s_read_mtp then
if curr_ctrl.command_done = '1' then
if mtp_almts_checked = 0 then
dvw_size_a0 <= to_integer(unsigned(curr_ctrl.command_result));
else
dvw_size_a1 <= to_integer(unsigned(curr_ctrl.command_result));
end if;
end if;
end if;
-- check dvw size and set mtp almt
if dvw_size_a0 < dvw_size_a1 then
mtp_correct_almt <= 1;
else
mtp_correct_almt <= 0;
end if;
-- error conditions
if mtp_almts_checked = 2 and GENERATE_ADDITIONAL_DBG_RTL = 1 then -- if finished alignment checking (and GENERATE_ADDITIONAL_DBG_RTL set)
-- perform size checks once per dvw
if dvw_size_a0 < 3 then
v_dvw_a0_small := true;
else
v_dvw_a0_small := false;
end if;
if dvw_size_a1 < 3 then
v_dvw_a1_small := true;
else
v_dvw_a1_small := false;
end if;
if v_dvw_a0_small = true and v_dvw_a1_small = true then
mtp_no_valid_almt <= '1';
mtp_err <= '1';
end if;
if v_dvw_a0_small = false and v_dvw_a1_small = false then
mtp_both_valid_almt <= '1';
mtp_err <= '1';
end if;
else
mtp_no_valid_almt <= '0';
mtp_both_valid_almt <= '0';
mtp_err <= '0';
end if;
end if;
end process;
end block;
-- ------------------------------------------------------------------------------
-- process to generate command outputs, based on state, last_state and mmi_ctrl.
-- asynchronously
-- ------------------------------------------------------------------------------
process (state, last_state, mmi_ctrl, reissue_cmd_req, cs_counter, mtp_almts_checked, mtp_correct_almt)
begin
master_ctrl_op_rec <= defaults;
master_ctrl_iram_push <= defaults;
case state is
-- special condition states
when s_reset | s_phy_initialise | s_cal =>
null;
when s_write_ihi =>
if mmi_ctrl.hl_css.write_ihi_dis = '0' then
master_ctrl_op_rec.command <= find_cmd(state);
if state /= last_state then
master_ctrl_op_rec.command_req <= '1';
end if;
end if;
when s_operational | s_non_operational =>
master_ctrl_op_rec.command <= find_cmd(state);
when others => -- default condition for most states
if find_dis_bit(state, mmi_ctrl) = '0' then
master_ctrl_op_rec.command <= find_cmd(state);
if state /= last_state or reissue_cmd_req = '1' then
master_ctrl_op_rec.command_req <= '1';
end if;
else
if state = last_state then -- safe state exit if state disabled mid-calibration
master_ctrl_op_rec.command <= find_cmd(state);
end if;
end if;
end case;
-- for multiple chip select commands assign operand to cs_counter
master_ctrl_op_rec.command_op <= defaults;
master_ctrl_op_rec.command_op.current_cs <= cs_counter;
if state = s_rrp_sweep or state = s_read_mtp or state = s_poa then
if mtp_almts_checked /= 2 or SIM_TIME_REDUCTIONS = 2 then
master_ctrl_op_rec.command_op.single_bit <= '1';
end if;
if mtp_almts_checked /= 2 then
master_ctrl_op_rec.command_op.mtp_almt <= mtp_almts_checked;
else
master_ctrl_op_rec.command_op.mtp_almt <= mtp_correct_almt;
end if;
end if;
-- set write mode and packing mode for iram
if GENERATE_ADDITIONAL_DBG_RTL = 1 then
case state is
when s_rrp_sweep =>
master_ctrl_iram_push.write_mode <= overwrite_ram;
master_ctrl_iram_push.packing_mode <= dq_bitwise;
when s_rrp_seek |
s_read_mtp =>
master_ctrl_iram_push.write_mode <= overwrite_ram;
master_ctrl_iram_push.packing_mode <= dq_wordwise;
when others =>
null;
end case;
end if;
-- set current active block
master_ctrl_iram_push.active_block <= curr_active_block(find_cmd(state));
end process;
-- some concurc_read_burst_trent assignments to outputs
process (master_ctrl_iram_push, master_ctrl_op_rec)
begin
ctrl_iram_push <= master_ctrl_iram_push;
ctrl_op_rec <= master_ctrl_op_rec;
cmd_req_asserted <= master_ctrl_op_rec.command_req;
end process;
-- -----------------------------------------------------------------------------
-- tracking interval counter
-- -----------------------------------------------------------------------------
process(clk, rst_n)
begin
if rst_n = '0' then
milisecond_tick_gen_count <= c_ticks_per_ms -1;
tracking_ms_counter <= 0;
tracking_update_due <= '0';
elsif rising_edge(clk) then
if state = s_operational and last_state/= s_operational then
if mmi_ctrl.tracking_orvd_to_10ms = '1' then
milisecond_tick_gen_count <= c_ticks_per_10us -1;
else
milisecond_tick_gen_count <= c_ticks_per_ms -1;
end if;
tracking_ms_counter <= mmi_ctrl.tracking_period_ms;
elsif state = s_operational then
if milisecond_tick_gen_count = 0 and tracking_update_due /= '1' then
if tracking_ms_counter = 0 then
tracking_update_due <= '1';
else
tracking_ms_counter <= tracking_ms_counter -1;
end if;
if mmi_ctrl.tracking_orvd_to_10ms = '1' then
milisecond_tick_gen_count <= c_ticks_per_10us -1;
else
milisecond_tick_gen_count <= c_ticks_per_ms -1;
end if;
elsif milisecond_tick_gen_count /= 0 then
milisecond_tick_gen_count <= milisecond_tick_gen_count -1;
end if;
else
tracking_update_due <= '0';
end if;
end if;
end process;
end architecture struct;
--
-- -----------------------------------------------------------------------------
-- Abstract : top level for the non-levelling AFI PHY sequencer
-- The top level instances the sub-blocks of the AFI PHY
-- sequencer. In addition a number of multiplexing and high-
-- level control operations are performed. This includes the
-- multiplexing and generation of control signals for: the
-- address and command DRAM interface and pll, oct and datapath
-- latency control signals.
-- -----------------------------------------------------------------------------
--altera message_off 10036
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--
entity ddr3_int_phy_alt_mem_phy_seq IS
generic (
-- choice of FPGA device family and DRAM type
FAMILY : string;
MEM_IF_MEMTYPE : string;
SPEED_GRADE : string;
FAMILYGROUP_ID : natural;
-- physical interface width definitions
MEM_IF_DQS_WIDTH : natural;
MEM_IF_DWIDTH : natural;
MEM_IF_DM_WIDTH : natural;
MEM_IF_DQ_PER_DQS : natural;
DWIDTH_RATIO : natural;
CLOCK_INDEX_WIDTH : natural;
MEM_IF_CLK_PAIR_COUNT : natural;
MEM_IF_ADDR_WIDTH : natural;
MEM_IF_BANKADDR_WIDTH : natural;
MEM_IF_CS_WIDTH : natural;
MEM_IF_NUM_RANKS : natural;
MEM_IF_RANKS_PER_SLOT : natural;
ADV_LAT_WIDTH : natural;
RESYNCHRONISE_AVALON_DBG : natural; -- 0 = false, 1 = true
AV_IF_ADDR_WIDTH : natural;
-- Not used for non-levelled seq
CHIP_OR_DIMM : string;
RDIMM_CONFIG_BITS : string;
-- setup / algorithm information
NOM_DQS_PHASE_SETTING : natural;
SCAN_CLK_DIVIDE_BY : natural;
RDP_ADDR_WIDTH : natural;
PLL_STEPS_PER_CYCLE : natural;
IOE_PHASES_PER_TCK : natural;
IOE_DELAYS_PER_PHS : natural;
MEM_IF_CLK_PS : natural;
WRITE_DESKEW_T10 : natural;
WRITE_DESKEW_HC_T10 : natural;
WRITE_DESKEW_T9NI : natural;
WRITE_DESKEW_HC_T9NI : natural;
WRITE_DESKEW_T9I : natural;
WRITE_DESKEW_HC_T9I : natural;
WRITE_DESKEW_RANGE : natural;
-- initial mode register settings
PHY_DEF_MR_1ST : natural;
PHY_DEF_MR_2ND : natural;
PHY_DEF_MR_3RD : natural;
PHY_DEF_MR_4TH : natural;
MEM_IF_DQSN_EN : natural; -- default off for Cyclone-III
MEM_IF_DQS_CAPTURE_EN : natural;
GENERATE_ADDITIONAL_DBG_RTL : natural; -- 1 signals to include iram and mmi blocks and 0 not to include
SINGLE_DQS_DELAY_CONTROL_CODE : natural; -- reserved for future use
PRESET_RLAT : natural; -- reserved for future use
EN_OCT : natural; -- Does the sequencer use OCT during calibration.
OCT_LAT_WIDTH : natural;
SIM_TIME_REDUCTIONS : natural; -- if 0 null, if 2 rrp for 1 dqs group and 1 cs
FORCE_HC : natural; -- Use to force HardCopy in simulation.
CAPABILITIES : natural; -- advertise capabilities i.e. which ctrl block states to execute (default all on)
TINIT_TCK : natural;
TINIT_RST : natural;
GENERATE_TRACKING_PHASE_STORE : natural; -- reserved for future use
IP_BUILDNUM : natural
);
port (
-- clk / reset
clk : in std_logic;
rst_n : in std_logic;
-- calibration status and prompt
ctl_init_success : out std_logic;
ctl_init_fail : out std_logic;
ctl_init_warning : out std_logic; -- unused
ctl_recalibrate_req : in std_logic;
-- the following two signals are reserved for future use
mem_ac_swapped_ranks : in std_logic_vector(MEM_IF_NUM_RANKS - 1 downto 0);
ctl_cal_byte_lanes : in std_logic_vector(MEM_IF_NUM_RANKS * MEM_IF_DQS_WIDTH - 1 downto 0);
-- pll reconfiguration
seq_pll_inc_dec_n : out std_logic;
seq_pll_start_reconfig : out std_logic;
seq_pll_select : out std_logic_vector(CLOCK_INDEX_WIDTH - 1 downto 0);
seq_pll_phs_shift_busy : in std_logic;
pll_resync_clk_index : in std_logic_vector(CLOCK_INDEX_WIDTH - 1 downto 0); -- PLL phase used to select resync clock
pll_measure_clk_index : in std_logic_vector(CLOCK_INDEX_WIDTH - 1 downto 0); -- PLL phase used to select mimic/measure clock
-- scanchain associated signals (reserved for future use)
seq_scan_clk : out std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
seq_scan_enable_dqs_config : out std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
seq_scan_update : out std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
seq_scan_din : out std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
seq_scan_enable_ck : out std_logic_vector(MEM_IF_CLK_PAIR_COUNT - 1 downto 0);
seq_scan_enable_dqs : out std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
seq_scan_enable_dqsn : out std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
seq_scan_enable_dq : out std_logic_vector(MEM_IF_DWIDTH - 1 downto 0);
seq_scan_enable_dm : out std_logic_vector(MEM_IF_DM_WIDTH - 1 downto 0);
hr_rsc_clk : in std_logic;
-- address / command interface (note these are mapped internally to the seq_ac record)
seq_ac_addr : out std_logic_vector((DWIDTH_RATIO/2) * MEM_IF_ADDR_WIDTH - 1 downto 0);
seq_ac_ba : out std_logic_vector((DWIDTH_RATIO/2) * MEM_IF_BANKADDR_WIDTH - 1 downto 0);
seq_ac_cas_n : out std_logic_vector((DWIDTH_RATIO/2) - 1 downto 0);
seq_ac_ras_n : out std_logic_vector((DWIDTH_RATIO/2) - 1 downto 0);
seq_ac_we_n : out std_logic_vector((DWIDTH_RATIO/2) - 1 downto 0);
seq_ac_cke : out std_logic_vector((DWIDTH_RATIO/2) * MEM_IF_NUM_RANKS - 1 downto 0);
seq_ac_cs_n : out std_logic_vector((DWIDTH_RATIO/2) * MEM_IF_NUM_RANKS - 1 downto 0);
seq_ac_odt : out std_logic_vector((DWIDTH_RATIO/2) * MEM_IF_NUM_RANKS - 1 downto 0);
seq_ac_rst_n : out std_logic_vector((DWIDTH_RATIO/2) - 1 downto 0);
seq_ac_sel : out std_logic;
seq_mem_clk_disable : out std_logic;
-- additional datapath latency (reserved for future use)
seq_ac_add_1t_ac_lat_internal : out std_logic;
seq_ac_add_1t_odt_lat_internal : out std_logic;
seq_ac_add_2t : out std_logic;
-- read datapath interface
seq_rdp_reset_req_n : out std_logic;
seq_rdp_inc_read_lat_1x : out std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
seq_rdp_dec_read_lat_1x : out std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
rdata : in std_logic_vector( DWIDTH_RATIO * MEM_IF_DWIDTH - 1 downto 0);
-- read data valid (associated signals) interface
seq_rdv_doing_rd : out std_logic_vector(MEM_IF_DQS_WIDTH * DWIDTH_RATIO/2 - 1 downto 0);
rdata_valid : in std_logic_vector( DWIDTH_RATIO/2 - 1 downto 0);
seq_rdata_valid_lat_inc : out std_logic;
seq_rdata_valid_lat_dec : out std_logic;
seq_ctl_rlat : out std_logic_vector(ADV_LAT_WIDTH - 1 downto 0);
-- postamble interface (unused for Cyclone-III)
seq_poa_lat_dec_1x : out std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
seq_poa_lat_inc_1x : out std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
seq_poa_protection_override_1x : out std_logic;
-- OCT path control
seq_oct_oct_delay : out std_logic_vector(OCT_LAT_WIDTH - 1 downto 0);
seq_oct_oct_extend : out std_logic_vector(OCT_LAT_WIDTH - 1 downto 0);
seq_oct_value : out std_logic;
-- write data path interface
seq_wdp_dqs_burst : out std_logic_vector((DWIDTH_RATIO/2) * MEM_IF_DQS_WIDTH - 1 downto 0);
seq_wdp_wdata_valid : out std_logic_vector((DWIDTH_RATIO/2) * MEM_IF_DQS_WIDTH - 1 downto 0);
seq_wdp_wdata : out std_logic_vector( DWIDTH_RATIO * MEM_IF_DWIDTH - 1 downto 0);
seq_wdp_dm : out std_logic_vector( DWIDTH_RATIO * MEM_IF_DM_WIDTH - 1 downto 0);
seq_wdp_dqs : out std_logic_vector( DWIDTH_RATIO - 1 downto 0);
seq_wdp_ovride : out std_logic;
seq_dqs_add_2t_delay : out std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
seq_ctl_wlat : out std_logic_vector(ADV_LAT_WIDTH - 1 downto 0);
-- mimic path interface
seq_mmc_start : out std_logic;
mmc_seq_done : in std_logic;
mmc_seq_value : in std_logic;
-- parity signals (not used for non-levelled PHY)
mem_err_out_n : in std_logic;
parity_error_n : out std_logic;
--synchronous Avalon debug interface (internally re-synchronised to input clock (a generic option))
dbg_seq_clk : in std_logic;
dbg_seq_rst_n : in std_logic;
dbg_seq_addr : in std_logic_vector(AV_IF_ADDR_WIDTH - 1 downto 0);
dbg_seq_wr : in std_logic;
dbg_seq_rd : in std_logic;
dbg_seq_cs : in std_logic;
dbg_seq_wr_data : in std_logic_vector(31 downto 0);
seq_dbg_rd_data : out std_logic_vector(31 downto 0);
seq_dbg_waitrequest : out std_logic
);
end entity;
library work;
-- The record package (alt_mem_phy_record_pkg) is used to combine command and status signals
-- (into records) to be passed between sequencer blocks. It also contains type and record definitions
-- for the stages of DRAM memory calibration.
--
use work.ddr3_int_phy_alt_mem_phy_record_pkg.all;
-- The registers package (alt_mem_phy_regs_pkg) is used to combine the definition of the
-- registers for the mmi status registers and functions/procedures applied to the registers
--
use work.ddr3_int_phy_alt_mem_phy_regs_pkg.all;
-- The constant package (alt_mem_phy_constants_pkg) contains global 'constants' which are fixed
-- thoughout the sequencer and will not change (for constants which may change between sequencer
-- instances generics are used)
--
use work.ddr3_int_phy_alt_mem_phy_constants_pkg.all;
-- The iram address package (alt_mem_phy_iram_addr_pkg) is used to define the base addresses used
-- for iram writes during calibration
--
use work.ddr3_int_phy_alt_mem_phy_iram_addr_pkg.all;
-- The address and command package (alt_mem_phy_addr_cmd_pkg) is used to combine DRAM address
-- and command signals in one record and unify the functions operating on this record.
--
use work.ddr3_int_phy_alt_mem_phy_addr_cmd_pkg.all;
-- Individually include each of library files for the sub-blocks of the sequencer:
--
use work.ddr3_int_phy_alt_mem_phy_admin;
--
use work.ddr3_int_phy_alt_mem_phy_mmi;
--
use work.ddr3_int_phy_alt_mem_phy_iram;
--
use work.ddr3_int_phy_alt_mem_phy_dgrb;
--
use work.ddr3_int_phy_alt_mem_phy_dgwb;
--
use work.ddr3_int_phy_alt_mem_phy_ctrl;
--
architecture struct of ddr3_int_phy_alt_mem_phy_seq IS
attribute altera_attribute : string;
attribute altera_attribute of struct : architecture is "-name MESSAGE_DISABLE 18010";
-- debug signals (similar to those seen in the Quartus v8.0 DDR/DDR2 sequencer)
signal rsu_multiple_valid_latencies_err : std_logic; -- true if >2 valid latency values are detected
signal rsu_grt_one_dvw_err : std_logic; -- true if >1 data valid window is detected
signal rsu_no_dvw_err : std_logic; -- true if no data valid window is detected
signal rsu_codvw_phase : std_logic_vector(11 downto 0); -- set to the phase of the DVW detected if calibration is successful
signal rsu_codvw_size : std_logic_vector(11 downto 0); -- set to the phase of the DVW detected if calibration is successful
signal rsu_read_latency : std_logic_vector(ADV_LAT_WIDTH - 1 downto 0); -- set to the correct read latency if calibration is successful
-- outputs from the dgrb to generate the above rsu_codvw_* signals and report status to the mmi
signal dgrb_mmi : t_dgrb_mmi;
-- admin to mmi interface
signal regs_admin_ctrl_rec : t_admin_ctrl; -- mmi register settings information
signal admin_regs_status_rec : t_admin_stat; -- admin status information
-- odt enable from the admin block based on mr settings
signal enable_odt : std_logic;
-- iram status information (sent to the ctrl block)
signal iram_status : t_iram_stat;
-- dgrb iram write interface
signal dgrb_iram : t_iram_push;
-- ctrl to iram interface
signal ctrl_idib_top : natural; -- current write location in the iram
signal ctrl_active_block : t_ctrl_active_block;
signal ctrl_iram_push : t_ctrl_iram;
signal iram_push_done : std_logic;
signal ctrl_iram_ihi_write : std_logic;
-- local copies of calibration status
signal ctl_init_success_int : std_logic;
signal ctl_init_fail_int : std_logic;
-- refresh period failure flag
signal trefi_failure : std_logic;
-- unified ctrl signal broadcast to all blocks from the ctrl block
signal ctrl_broadcast : t_ctrl_command;
-- standardised status report per block to control block
signal admin_ctrl : t_ctrl_stat;
signal dgwb_ctrl : t_ctrl_stat;
signal dgrb_ctrl : t_ctrl_stat;
-- mmi and ctrl block interface
signal mmi_ctrl : t_mmi_ctrl;
signal ctrl_mmi : t_ctrl_mmi;
-- write datapath override signals
signal dgwb_wdp_override : std_logic;
signal dgrb_wdp_override : std_logic;
-- address/command access request and grant between the dgrb/dgwb blocks and the admin block
signal dgb_ac_access_gnt : std_logic;
signal dgb_ac_access_gnt_r : std_logic;
signal dgb_ac_access_req : std_logic;
signal dgwb_ac_access_req : std_logic;
signal dgrb_ac_access_req : std_logic;
-- per block address/command record (multiplexed in this entity)
signal admin_ac : t_addr_cmd_vector(0 to (DWIDTH_RATIO/2)-1);
signal dgwb_ac : t_addr_cmd_vector(0 to (DWIDTH_RATIO/2)-1);
signal dgrb_ac : t_addr_cmd_vector(0 to (DWIDTH_RATIO/2)-1);
-- doing read signal
signal seq_rdv_doing_rd_int : std_logic_vector(seq_rdv_doing_rd'range);
-- local copy of interface to inc/dec latency on rdata_valid and postamble
signal seq_rdata_valid_lat_dec_int : std_logic;
signal seq_rdata_valid_lat_inc_int : std_logic;
signal seq_poa_lat_inc_1x_int : std_logic_vector(MEM_IF_DQS_WIDTH -1 downto 0);
signal seq_poa_lat_dec_1x_int : std_logic_vector(MEM_IF_DQS_WIDTH -1 downto 0);
-- local copy of write/read latency
signal seq_ctl_wlat_int : std_logic_vector(seq_ctl_wlat'range);
signal seq_ctl_rlat_int : std_logic_vector(seq_ctl_rlat'range);
-- parameterisation of dgrb / dgwb / admin blocks from mmi register settings
signal parameterisation_rec : t_algm_paramaterisation;
-- PLL reconfig
signal seq_pll_phs_shift_busy_r : std_logic;
signal seq_pll_phs_shift_busy_ccd : std_logic;
signal dgrb_pll_inc_dec_n : std_logic;
signal dgrb_pll_start_reconfig : std_logic;
signal dgrb_pll_select : std_logic_vector(CLOCK_INDEX_WIDTH - 1 downto 0);
signal dgrb_phs_shft_busy : std_logic;
signal mmi_pll_inc_dec_n : std_logic;
signal mmi_pll_start_reconfig : std_logic;
signal mmi_pll_select : std_logic_vector(CLOCK_INDEX_WIDTH - 1 downto 0);
signal pll_mmi : t_pll_mmi;
signal mmi_pll : t_mmi_pll_reconfig;
-- address and command 1t setting (unused for Full Rate)
signal int_ac_nt : std_logic_vector(((DWIDTH_RATIO+2)/4) - 1 downto 0);
signal dgrb_ctrl_ac_nt_good : std_logic;
-- the following signals are reserved for future use
signal ctl_cal_byte_lanes_r : std_logic_vector(ctl_cal_byte_lanes'range);
signal mmi_setup : t_ctrl_cmd_id;
signal dgwb_iram : t_iram_push;
-- track number of poa / rdv adjustments (reporting only)
signal poa_adjustments : natural;
signal rdv_adjustments : natural;
-- convert input generics from natural to std_logic_vector
constant c_phy_def_mr_1st_sl_vector : std_logic_vector(15 downto 0) := std_logic_vector(to_unsigned(PHY_DEF_MR_1ST, 16));
constant c_phy_def_mr_2nd_sl_vector : std_logic_vector(15 downto 0) := std_logic_vector(to_unsigned(PHY_DEF_MR_2ND, 16));
constant c_phy_def_mr_3rd_sl_vector : std_logic_vector(15 downto 0) := std_logic_vector(to_unsigned(PHY_DEF_MR_3RD, 16));
constant c_phy_def_mr_4th_sl_vector : std_logic_vector(15 downto 0) := std_logic_vector(to_unsigned(PHY_DEF_MR_4TH, 16));
-- overrride on capabilities to speed up simulation time
function capabilities_override(capabilities : natural;
sim_time_reductions : natural) return natural is
begin
if sim_time_reductions = 1 then
return 2**c_hl_css_reg_cal_dis_bit; -- disable calibration completely
else
return capabilities;
end if;
end function;
-- set sequencer capabilities
constant c_capabilities_override : natural := capabilities_override(CAPABILITIES, SIM_TIME_REDUCTIONS);
constant c_capabilities : std_logic_vector(31 downto 0) := std_logic_vector(to_unsigned(c_capabilities_override,32));
-- setup for address/command interface
constant c_seq_addr_cmd_config : t_addr_cmd_config_rec := set_config_rec(MEM_IF_ADDR_WIDTH, MEM_IF_BANKADDR_WIDTH, MEM_IF_NUM_RANKS, DWIDTH_RATIO, MEM_IF_MEMTYPE);
-- setup for odt signals
-- odt setting as implemented in the altera high-performance controller for ddrx memories
constant c_odt_settings : t_odt_array(0 to MEM_IF_NUM_RANKS-1) := set_odt_values(MEM_IF_NUM_RANKS, MEM_IF_RANKS_PER_SLOT, MEM_IF_MEMTYPE);
-- a prefix for all report signals to identify phy and sequencer block
--
constant seq_report_prefix : string := "ddr3_int_phy_alt_mem_phy_seq (top) : ";
-- setup iram configuration
constant c_iram_addresses : t_base_hdr_addresses := calc_iram_addresses(DWIDTH_RATIO, PLL_STEPS_PER_CYCLE, MEM_IF_DWIDTH, MEM_IF_NUM_RANKS, MEM_IF_DQS_CAPTURE_EN);
constant c_int_iram_awidth : natural := c_iram_addresses.required_addr_bits;
constant c_preset_cal_setup : t_preset_cal := setup_instant_on(SIM_TIME_REDUCTIONS, FAMILYGROUP_ID, MEM_IF_MEMTYPE, DWIDTH_RATIO, PLL_STEPS_PER_CYCLE, c_phy_def_mr_1st_sl_vector, c_phy_def_mr_2nd_sl_vector, c_phy_def_mr_3rd_sl_vector);
constant c_preset_codvw_phase : natural := c_preset_cal_setup.codvw_phase;
constant c_preset_codvw_size : natural := c_preset_cal_setup.codvw_size;
constant c_tracking_interval_in_ms : natural := 128;
constant c_mem_if_cal_bank : natural := 0; -- location to calibrate to
constant c_mem_if_cal_base_col : natural := 0; -- default all zeros
constant c_mem_if_cal_base_row : natural := 0;
constant c_non_op_eval_md : string := "PIN_FINDER"; -- non_operational evaluation mode (used when GENERATE_ADDITIONAL_DBG_RTL = 1)
begin -- architecture struct
-- ---------------------------------------------------------------
-- tie off unused signals to default values
-- ---------------------------------------------------------------
-- scan chain associated signals
seq_scan_clk <= (others => '0');
seq_scan_enable_dqs_config <= (others => '0');
seq_scan_update <= (others => '0');
seq_scan_din <= (others => '0');
seq_scan_enable_ck <= (others => '0');
seq_scan_enable_dqs <= (others => '0');
seq_scan_enable_dqsn <= (others => '0');
seq_scan_enable_dq <= (others => '0');
seq_scan_enable_dm <= (others => '0');
seq_dqs_add_2t_delay <= (others => '0');
seq_rdp_inc_read_lat_1x <= (others => '0');
seq_rdp_dec_read_lat_1x <= (others => '0');
-- warning flag (not used in non-levelled sequencer)
ctl_init_warning <= '0';
-- parity error flag (not used in non-levelled sequencer)
parity_error_n <= '1';
--
admin: entity ddr3_int_phy_alt_mem_phy_admin
generic map
(
MEM_IF_DQS_WIDTH => MEM_IF_DQS_WIDTH,
MEM_IF_DWIDTH => MEM_IF_DWIDTH,
MEM_IF_DM_WIDTH => MEM_IF_DM_WIDTH,
MEM_IF_DQ_PER_DQS => MEM_IF_DQ_PER_DQS,
DWIDTH_RATIO => DWIDTH_RATIO,
CLOCK_INDEX_WIDTH => CLOCK_INDEX_WIDTH,
MEM_IF_CLK_PAIR_COUNT => MEM_IF_CLK_PAIR_COUNT,
MEM_IF_ADDR_WIDTH => MEM_IF_ADDR_WIDTH,
MEM_IF_BANKADDR_WIDTH => MEM_IF_BANKADDR_WIDTH,
MEM_IF_NUM_RANKS => MEM_IF_NUM_RANKS,
ADV_LAT_WIDTH => ADV_LAT_WIDTH,
MEM_IF_DQSN_EN => MEM_IF_DQSN_EN,
MEM_IF_MEMTYPE => MEM_IF_MEMTYPE,
MEM_IF_CAL_BANK => c_mem_if_cal_bank,
MEM_IF_CAL_BASE_ROW => c_mem_if_cal_base_row,
GENERATE_ADDITIONAL_DBG_RTL => GENERATE_ADDITIONAL_DBG_RTL,
NON_OP_EVAL_MD => c_non_op_eval_md,
MEM_IF_CLK_PS => MEM_IF_CLK_PS,
TINIT_TCK => TINIT_TCK,
TINIT_RST => TINIT_RST
)
port map
(
clk => clk,
rst_n => rst_n,
mem_ac_swapped_ranks => mem_ac_swapped_ranks,
ctl_cal_byte_lanes => ctl_cal_byte_lanes_r,
seq_ac => admin_ac,
seq_ac_sel => seq_ac_sel,
enable_odt => enable_odt,
regs_admin_ctrl_rec => regs_admin_ctrl_rec,
admin_regs_status_rec => admin_regs_status_rec,
trefi_failure => trefi_failure,
ctrl_admin => ctrl_broadcast,
admin_ctrl => admin_ctrl,
ac_access_req => dgb_ac_access_req,
ac_access_gnt => dgb_ac_access_gnt,
cal_fail => ctl_init_fail_int,
cal_success => ctl_init_success_int,
ctl_recalibrate_req => ctl_recalibrate_req
);
-- selectively include the debug i/f (iram and mmi blocks)
with_debug_if : if GENERATE_ADDITIONAL_DBG_RTL = 1 generate
signal mmi_iram : t_iram_ctrl;
signal mmi_iram_enable_writes : std_logic;
signal rrp_mem_loc : natural range 0 to 2 ** c_int_iram_awidth - 1;
signal command_req_r : std_logic;
signal ctrl_broadcast_r : t_ctrl_command;
begin
-- register ctrl_broadcast locally
process (clk, rst_n)
begin
if rst_n = '0' then
ctrl_broadcast_r <= defaults;
elsif rising_edge(clk) then
ctrl_broadcast_r <= ctrl_broadcast;
end if;
end process;
--
mmi : entity ddr3_int_phy_alt_mem_phy_mmi
generic map (
MEM_IF_DQS_WIDTH => MEM_IF_DQS_WIDTH,
MEM_IF_DWIDTH => MEM_IF_DWIDTH,
MEM_IF_DM_WIDTH => MEM_IF_DM_WIDTH,
MEM_IF_DQ_PER_DQS => MEM_IF_DQ_PER_DQS,
DWIDTH_RATIO => DWIDTH_RATIO,
CLOCK_INDEX_WIDTH => CLOCK_INDEX_WIDTH,
MEM_IF_CLK_PAIR_COUNT => MEM_IF_CLK_PAIR_COUNT,
MEM_IF_ADDR_WIDTH => MEM_IF_ADDR_WIDTH,
MEM_IF_BANKADDR_WIDTH => MEM_IF_BANKADDR_WIDTH,
MEM_IF_NUM_RANKS => MEM_IF_NUM_RANKS,
MEM_IF_DQS_CAPTURE => MEM_IF_DQS_CAPTURE_EN,
ADV_LAT_WIDTH => ADV_LAT_WIDTH,
RESYNCHRONISE_AVALON_DBG => RESYNCHRONISE_AVALON_DBG,
AV_IF_ADDR_WIDTH => AV_IF_ADDR_WIDTH,
NOM_DQS_PHASE_SETTING => NOM_DQS_PHASE_SETTING,
SCAN_CLK_DIVIDE_BY => SCAN_CLK_DIVIDE_BY,
RDP_ADDR_WIDTH => RDP_ADDR_WIDTH,
PLL_STEPS_PER_CYCLE => PLL_STEPS_PER_CYCLE,
IOE_PHASES_PER_TCK => IOE_PHASES_PER_TCK,
IOE_DELAYS_PER_PHS => IOE_DELAYS_PER_PHS,
MEM_IF_CLK_PS => MEM_IF_CLK_PS,
PHY_DEF_MR_1ST => c_phy_def_mr_1st_sl_vector,
PHY_DEF_MR_2ND => c_phy_def_mr_2nd_sl_vector,
PHY_DEF_MR_3RD => c_phy_def_mr_3rd_sl_vector,
PHY_DEF_MR_4TH => c_phy_def_mr_4th_sl_vector,
MEM_IF_MEMTYPE => MEM_IF_MEMTYPE,
PRESET_RLAT => PRESET_RLAT,
CAPABILITIES => c_capabilities_override,
USE_IRAM => '1', -- always use iram (generic is rfu)
IRAM_AWIDTH => c_int_iram_awidth,
TRACKING_INTERVAL_IN_MS => c_tracking_interval_in_ms,
READ_LAT_WIDTH => ADV_LAT_WIDTH
)
port map(
clk => clk,
rst_n => rst_n,
dbg_seq_clk => dbg_seq_clk,
dbg_seq_rst_n => dbg_seq_rst_n,
dbg_seq_addr => dbg_seq_addr,
dbg_seq_wr => dbg_seq_wr,
dbg_seq_rd => dbg_seq_rd,
dbg_seq_cs => dbg_seq_cs,
dbg_seq_wr_data => dbg_seq_wr_data,
seq_dbg_rd_data => seq_dbg_rd_data,
seq_dbg_waitrequest => seq_dbg_waitrequest,
regs_admin_ctrl => regs_admin_ctrl_rec,
admin_regs_status => admin_regs_status_rec,
mmi_iram => mmi_iram,
mmi_iram_enable_writes => mmi_iram_enable_writes,
iram_status => iram_status,
mmi_ctrl => mmi_ctrl,
ctrl_mmi => ctrl_mmi,
int_ac_1t => int_ac_nt(0),
invert_ac_1t => open,
trefi_failure => trefi_failure,
parameterisation_rec => parameterisation_rec,
pll_mmi => pll_mmi,
mmi_pll => mmi_pll,
dgrb_mmi => dgrb_mmi
);
--
iram : entity ddr3_int_phy_alt_mem_phy_iram
generic map(
MEM_IF_MEMTYPE => MEM_IF_MEMTYPE,
FAMILYGROUP_ID => FAMILYGROUP_ID,
MEM_IF_DQS_WIDTH => MEM_IF_DQS_WIDTH,
MEM_IF_DQ_PER_DQS => MEM_IF_DQ_PER_DQS,
MEM_IF_DWIDTH => MEM_IF_DWIDTH,
MEM_IF_DM_WIDTH => MEM_IF_DM_WIDTH,
MEM_IF_NUM_RANKS => MEM_IF_NUM_RANKS,
IRAM_AWIDTH => c_int_iram_awidth,
REFRESH_COUNT_INIT => 12,
PRESET_RLAT => PRESET_RLAT,
PLL_STEPS_PER_CYCLE => PLL_STEPS_PER_CYCLE,
CAPABILITIES => c_capabilities_override,
IP_BUILDNUM => IP_BUILDNUM
)
port map(
clk => clk,
rst_n => rst_n,
mmi_iram => mmi_iram,
mmi_iram_enable_writes => mmi_iram_enable_writes,
iram_status => iram_status,
iram_push_done => iram_push_done,
ctrl_iram => ctrl_broadcast_r,
dgrb_iram => dgrb_iram,
admin_regs_status_rec => admin_regs_status_rec,
ctrl_idib_top => ctrl_idib_top,
ctrl_iram_push => ctrl_iram_push,
dgwb_iram => dgwb_iram
);
-- calculate where current data should go in the iram
process (clk, rst_n)
variable v_words_req : natural range 0 to 2 * MEM_IF_DWIDTH * PLL_STEPS_PER_CYCLE * DWIDTH_RATIO - 1; -- how many words are required
begin
if rst_n = '0' then
ctrl_idib_top <= 0;
command_req_r <= '0';
rrp_mem_loc <= 0;
elsif rising_edge(clk) then
if command_req_r = '0' and ctrl_broadcast_r.command_req = '1' then -- execute once on each command_req assertion
-- default a 'safe location'
ctrl_idib_top <= c_iram_addresses.safe_dummy;
case ctrl_broadcast_r.command is
when cmd_write_ihi => -- reset pointers
rrp_mem_loc <= c_iram_addresses.rrp;
ctrl_idib_top <= 0; -- write header to zero location always
when cmd_rrp_sweep =>
-- add previous space requirement onto the current address
ctrl_idib_top <= rrp_mem_loc;
-- add the current space requirement to v_rrp_mem_loc
-- there are (DWIDTH_RATIO/2) * PLL_STEPS_PER_CYCLE phases swept packed into 32 bit words per pin
-- note: special case for single_bit calibration stages (e.g. read_mtp alignment)
if ctrl_broadcast_r.command_op.single_bit = '1' then
v_words_req := iram_wd_for_one_pin_rrp(DWIDTH_RATIO, PLL_STEPS_PER_CYCLE, MEM_IF_DWIDTH, MEM_IF_DQS_CAPTURE_EN);
else
v_words_req := iram_wd_for_full_rrp(DWIDTH_RATIO, PLL_STEPS_PER_CYCLE, MEM_IF_DWIDTH, MEM_IF_DQS_CAPTURE_EN);
end if;
v_words_req := v_words_req + 2; -- add 1 word location for header / footer information
rrp_mem_loc <= rrp_mem_loc + v_words_req;
when cmd_rrp_seek |
cmd_read_mtp =>
-- add previous space requirement onto the current address
ctrl_idib_top <= rrp_mem_loc;
-- require 3 words - header, result and footer
v_words_req := 3;
rrp_mem_loc <= rrp_mem_loc + v_words_req;
when others =>
null;
end case;
end if;
command_req_r <= ctrl_broadcast_r.command_req;
-- if recalibration request then reset iram address
if ctl_recalibrate_req = '1' or mmi_ctrl.calibration_start = '1' then
rrp_mem_loc <= c_iram_addresses.rrp;
end if;
end if;
end process;
end generate; -- with debug interface
-- if no debug interface (iram/mmi block) tie off relevant signals
without_debug_if : if GENERATE_ADDITIONAL_DBG_RTL = 0 generate
constant c_slv_hl_stage_enable : std_logic_vector(31 downto 0) := std_logic_vector(to_unsigned(c_capabilities_override, 32));
constant c_hl_stage_enable : std_logic_vector(c_hl_ccs_num_stages-1 downto 0) := c_slv_hl_stage_enable(c_hl_ccs_num_stages-1 downto 0);
constant c_pll_360_sweeps : natural := rrp_pll_phase_mult(DWIDTH_RATIO, MEM_IF_DQS_CAPTURE_EN);
signal mmi_regs : t_mmi_regs := defaults;
begin
-- avalon interface signals
seq_dbg_rd_data <= (others => '0');
seq_dbg_waitrequest <= '0';
-- The following registers are generated to simplify the assignments which follow
-- but will be optimised away in synthesis
mmi_regs.rw_regs <= defaults(c_phy_def_mr_1st_sl_vector,
c_phy_def_mr_2nd_sl_vector,
c_phy_def_mr_3rd_sl_vector,
c_phy_def_mr_4th_sl_vector,
NOM_DQS_PHASE_SETTING,
PLL_STEPS_PER_CYCLE,
c_pll_360_sweeps,
c_tracking_interval_in_ms,
c_hl_stage_enable);
mmi_regs.ro_regs <= defaults(dgrb_mmi,
ctrl_mmi,
pll_mmi,
mmi_regs.rw_regs.rw_if_test,
'0', -- do not use iram
MEM_IF_DQS_CAPTURE_EN,
int_ac_nt(0),
trefi_failure,
iram_status,
c_int_iram_awidth);
process(mmi_regs)
begin
-- debug parameterisation signals
regs_admin_ctrl_rec <= pack_record(mmi_regs.rw_regs);
parameterisation_rec <= pack_record(mmi_regs.rw_regs);
mmi_pll <= pack_record(mmi_regs.rw_regs);
mmi_ctrl <= pack_record(mmi_regs.rw_regs);
end process;
-- from the iram
iram_status <= defaults;
iram_push_done <= '0';
end generate; -- without debug interface
--
dgrb : entity ddr3_int_phy_alt_mem_phy_dgrb
generic map(
MEM_IF_DQS_WIDTH => MEM_IF_DQS_WIDTH,
MEM_IF_DQ_PER_DQS => MEM_IF_DQ_PER_DQS,
MEM_IF_DWIDTH => MEM_IF_DWIDTH,
MEM_IF_DM_WIDTH => MEM_IF_DM_WIDTH,
MEM_IF_DQS_CAPTURE => MEM_IF_DQS_CAPTURE_EN,
DWIDTH_RATIO => DWIDTH_RATIO,
CLOCK_INDEX_WIDTH => CLOCK_INDEX_WIDTH,
MEM_IF_ADDR_WIDTH => MEM_IF_ADDR_WIDTH,
MEM_IF_BANKADDR_WIDTH => MEM_IF_BANKADDR_WIDTH,
MEM_IF_NUM_RANKS => MEM_IF_NUM_RANKS,
MEM_IF_MEMTYPE => MEM_IF_MEMTYPE,
ADV_LAT_WIDTH => ADV_LAT_WIDTH,
PRESET_RLAT => PRESET_RLAT,
PLL_STEPS_PER_CYCLE => PLL_STEPS_PER_CYCLE,
SIM_TIME_REDUCTIONS => SIM_TIME_REDUCTIONS,
GENERATE_ADDITIONAL_DBG_RTL => GENERATE_ADDITIONAL_DBG_RTL,
PRESET_CODVW_PHASE => c_preset_codvw_phase,
PRESET_CODVW_SIZE => c_preset_codvw_size,
MEM_IF_CAL_BANK => c_mem_if_cal_bank,
MEM_IF_CAL_BASE_COL => c_mem_if_cal_base_col,
EN_OCT => EN_OCT
)
port map(
clk => clk,
rst_n => rst_n,
dgrb_ctrl => dgrb_ctrl,
ctrl_dgrb => ctrl_broadcast,
parameterisation_rec => parameterisation_rec,
phs_shft_busy => dgrb_phs_shft_busy,
seq_pll_inc_dec_n => dgrb_pll_inc_dec_n,
seq_pll_select => dgrb_pll_select,
seq_pll_start_reconfig => dgrb_pll_start_reconfig,
pll_resync_clk_index => pll_resync_clk_index,
pll_measure_clk_index => pll_measure_clk_index,
dgrb_iram => dgrb_iram,
iram_push_done => iram_push_done,
dgrb_ac => dgrb_ac,
dgrb_ac_access_req => dgrb_ac_access_req,
dgrb_ac_access_gnt => dgb_ac_access_gnt_r,
seq_rdata_valid_lat_inc => seq_rdata_valid_lat_inc_int,
seq_rdata_valid_lat_dec => seq_rdata_valid_lat_dec_int,
seq_poa_lat_dec_1x => seq_poa_lat_dec_1x_int,
seq_poa_lat_inc_1x => seq_poa_lat_inc_1x_int,
rdata_valid => rdata_valid,
rdata => rdata,
doing_rd => seq_rdv_doing_rd_int,
rd_lat => seq_ctl_rlat_int,
wd_lat => seq_ctl_wlat_int,
dgrb_wdp_ovride => dgrb_wdp_override,
seq_oct_value => seq_oct_value,
seq_mmc_start => seq_mmc_start,
mmc_seq_done => mmc_seq_done,
mmc_seq_value => mmc_seq_value,
ctl_cal_byte_lanes => ctl_cal_byte_lanes_r,
odt_settings => c_odt_settings,
dgrb_ctrl_ac_nt_good => dgrb_ctrl_ac_nt_good,
dgrb_mmi => dgrb_mmi
);
--
dgwb : entity ddr3_int_phy_alt_mem_phy_dgwb
generic map(
-- Physical IF width definitions
MEM_IF_DQS_WIDTH => MEM_IF_DQS_WIDTH,
MEM_IF_DQ_PER_DQS => MEM_IF_DQ_PER_DQS,
MEM_IF_DWIDTH => MEM_IF_DWIDTH,
MEM_IF_DM_WIDTH => MEM_IF_DM_WIDTH,
DWIDTH_RATIO => DWIDTH_RATIO,
MEM_IF_ADDR_WIDTH => MEM_IF_ADDR_WIDTH,
MEM_IF_BANKADDR_WIDTH => MEM_IF_BANKADDR_WIDTH,
MEM_IF_NUM_RANKS => MEM_IF_NUM_RANKS,
MEM_IF_MEMTYPE => MEM_IF_MEMTYPE,
ADV_LAT_WIDTH => ADV_LAT_WIDTH,
MEM_IF_CAL_BANK => c_mem_if_cal_bank,
MEM_IF_CAL_BASE_COL => c_mem_if_cal_base_col
)
port map(
clk => clk,
rst_n => rst_n,
parameterisation_rec => parameterisation_rec,
dgwb_ctrl => dgwb_ctrl,
ctrl_dgwb => ctrl_broadcast,
dgwb_iram => dgwb_iram,
iram_push_done => iram_push_done,
dgwb_ac_access_req => dgwb_ac_access_req,
dgwb_ac_access_gnt => dgb_ac_access_gnt_r,
dgwb_dqs_burst => seq_wdp_dqs_burst,
dgwb_wdata_valid => seq_wdp_wdata_valid,
dgwb_wdata => seq_wdp_wdata,
dgwb_dm => seq_wdp_dm,
dgwb_dqs => seq_wdp_dqs,
dgwb_wdp_ovride => dgwb_wdp_override,
dgwb_ac => dgwb_ac,
bypassed_rdata => rdata(DWIDTH_RATIO * MEM_IF_DWIDTH -1 downto (DWIDTH_RATIO-1) * MEM_IF_DWIDTH),
odt_settings => c_odt_settings
);
--
ctrl: entity ddr3_int_phy_alt_mem_phy_ctrl
generic map(
FAMILYGROUP_ID => FAMILYGROUP_ID,
MEM_IF_DLL_LOCK_COUNT => 1280/(DWIDTH_RATIO/2),
MEM_IF_MEMTYPE => MEM_IF_MEMTYPE,
DWIDTH_RATIO => DWIDTH_RATIO,
IRAM_ADDRESSING => c_iram_addresses,
MEM_IF_CLK_PS => MEM_IF_CLK_PS,
TRACKING_INTERVAL_IN_MS => c_tracking_interval_in_ms,
GENERATE_ADDITIONAL_DBG_RTL => GENERATE_ADDITIONAL_DBG_RTL,
MEM_IF_NUM_RANKS => MEM_IF_NUM_RANKS,
MEM_IF_DQS_WIDTH => MEM_IF_DQS_WIDTH,
SIM_TIME_REDUCTIONS => SIM_TIME_REDUCTIONS,
ACK_SEVERITY => warning
)
port map(
clk => clk,
rst_n => rst_n,
ctl_init_success => ctl_init_success_int,
ctl_init_fail => ctl_init_fail_int,
ctl_recalibrate_req => ctl_recalibrate_req,
iram_status => iram_status,
iram_push_done => iram_push_done,
ctrl_op_rec => ctrl_broadcast,
admin_ctrl => admin_ctrl,
dgrb_ctrl => dgrb_ctrl,
dgwb_ctrl => dgwb_ctrl,
ctrl_iram_push => ctrl_iram_push,
ctl_cal_byte_lanes => ctl_cal_byte_lanes_r,
dgrb_ctrl_ac_nt_good => dgrb_ctrl_ac_nt_good,
int_ac_nt => int_ac_nt,
mmi_ctrl => mmi_ctrl,
ctrl_mmi => ctrl_mmi
);
-- ------------------------------------------------------------------
-- generate legacy rsu signals
-- ------------------------------------------------------------------
process(rst_n, clk)
begin
if rst_n = '0' then
rsu_multiple_valid_latencies_err <= '0';
rsu_grt_one_dvw_err <= '0';
rsu_no_dvw_err <= '0';
rsu_codvw_phase <= (others => '0');
rsu_codvw_size <= (others => '0');
rsu_read_latency <= (others => '0');
elsif rising_edge(clk) then
if dgrb_ctrl.command_err = '1' then
case to_integer(unsigned(dgrb_ctrl.command_result)) is
when C_ERR_RESYNC_NO_VALID_PHASES =>
rsu_no_dvw_err <= '1';
when C_ERR_RESYNC_MULTIPLE_EQUAL_WINDOWS =>
rsu_multiple_valid_latencies_err <= '1';
when others => null;
end case;
end if;
rsu_codvw_phase(dgrb_mmi.cal_codvw_phase'range) <= dgrb_mmi.cal_codvw_phase;
rsu_codvw_size(dgrb_mmi.cal_codvw_size'range) <= dgrb_mmi.cal_codvw_size;
rsu_read_latency <= seq_ctl_rlat_int;
rsu_grt_one_dvw_err <= dgrb_mmi.codvw_grt_one_dvw;
-- Reset the flag on a recal request :
if ( ctl_recalibrate_req = '1') then
rsu_grt_one_dvw_err <= '0';
rsu_no_dvw_err <= '0';
rsu_multiple_valid_latencies_err <= '0';
end if;
end if;
end process;
-- ---------------------------------------------------------------
-- top level multiplexing and ctrl functionality
-- ---------------------------------------------------------------
oct_delay_block : block
constant DEFAULT_OCT_DELAY_CONST : integer := - 2; -- higher increases delay by one mem_clk cycle, lower decreases delay by one mem_clk cycle.
constant DEFAULT_OCT_EXTEND : natural := 3;
-- Returns additive latency extracted from mr0 as a natural number.
function decode_cl(mr0 : in std_logic_vector(12 downto 0))
return natural is
variable v_cl : natural range 0 to 2**4 - 1;
begin
if MEM_IF_MEMTYPE = "DDR" or MEM_IF_MEMTYPE = "DDR2" then
v_cl := to_integer(unsigned(mr0(6 downto 4)));
elsif MEM_IF_MEMTYPE = "DDR3" then
v_cl := to_integer(unsigned(mr0(6 downto 4))) + 4;
else
report "Unsupported memory type " & MEM_IF_MEMTYPE severity failure;
end if;
return v_cl;
end function;
-- Returns additive latency extracted from mr1 as a natural number.
function decode_al(mr1 : in std_logic_vector(12 downto 0))
return natural is
variable v_al : natural range 0 to 2**4 - 1;
begin
if MEM_IF_MEMTYPE = "DDR" or MEM_IF_MEMTYPE = "DDR2" then
v_al := to_integer(unsigned(mr1(5 downto 3)));
elsif MEM_IF_MEMTYPE = "DDR3" then
v_al := to_integer(unsigned(mr1(4 downto 3)));
else
report "Unsupported memory type " & MEM_IF_MEMTYPE severity failure;
end if;
return v_al;
end function;
-- Returns cas write latency extracted from mr2 as a natural number.
function decode_cwl(
mr0 : in std_logic_vector(12 downto 0);
mr2 : in std_logic_vector(12 downto 0)
)
return natural is
variable v_cwl : natural range 0 to 2**4 - 1;
begin
if MEM_IF_MEMTYPE = "DDR" then
v_cwl := 1;
elsif MEM_IF_MEMTYPE = "DDR2" then
v_cwl := decode_cl(mr0) - 1;
elsif MEM_IF_MEMTYPE = "DDR3" then
v_cwl := to_integer(unsigned(mr2(4 downto 3))) + 5;
else
report "Unsupported memory type " & MEM_IF_MEMTYPE severity failure;
end if;
return v_cwl;
end function;
begin
-- Process to work out timings for OCT extension and delay with respect to doing_read. NOTE that it is calculated on the basis of CL, CWL, ctl_wlat
oct_delay_proc : process(clk, rst_n)
variable v_cl : natural range 0 to 2**4 - 1; -- Total read latency.
variable v_cwl : natural range 0 to 2**4 - 1; -- Total write latency
variable oct_delay : natural range 0 to 2**OCT_LAT_WIDTH - 1;
variable v_wlat : natural range 0 to 2**ADV_LAT_WIDTH - 1;
begin
if rst_n = '0' then
seq_oct_oct_delay <= (others => '0');
seq_oct_oct_extend <= std_logic_vector(to_unsigned(DEFAULT_OCT_EXTEND, OCT_LAT_WIDTH));
elsif rising_edge(clk) then
if ctl_init_success_int = '1' then
seq_oct_oct_extend <= std_logic_vector(to_unsigned(DEFAULT_OCT_EXTEND, OCT_LAT_WIDTH));
v_cl := decode_cl(admin_regs_status_rec.mr0);
v_cwl := decode_cwl(admin_regs_status_rec.mr0, admin_regs_status_rec.mr2);
if SIM_TIME_REDUCTIONS = 1 then
v_wlat := c_preset_cal_setup.wlat;
else
v_wlat := to_integer(unsigned(seq_ctl_wlat_int));
end if;
oct_delay := DWIDTH_RATIO * v_wlat / 2 + (v_cl - v_cwl) + DEFAULT_OCT_DELAY_CONST;
if not (FAMILYGROUP_ID = 2) then -- CIII doesn't support OCT
seq_oct_oct_delay <= std_logic_vector(to_unsigned(oct_delay, OCT_LAT_WIDTH));
end if;
else
seq_oct_oct_delay <= (others => '0');
seq_oct_oct_extend <= std_logic_vector(to_unsigned(DEFAULT_OCT_EXTEND, OCT_LAT_WIDTH));
end if;
end if;
end process;
end block;
-- control postamble protection override signal (seq_poa_protection_override_1x)
process(clk, rst_n)
variable v_warning_given : std_logic;
begin
if rst_n = '0' then
seq_poa_protection_override_1x <= '0';
v_warning_given := '0';
elsif rising_edge(clk) then
case ctrl_broadcast.command is
when cmd_rdv |
cmd_rrp_sweep |
cmd_rrp_seek |
cmd_prep_adv_rd_lat |
cmd_prep_adv_wr_lat => seq_poa_protection_override_1x <= '1';
when others => seq_poa_protection_override_1x <= '0';
end case;
end if;
end process;
ac_mux : block
constant c_mem_clk_disable_pipe_len : natural := 3;
signal seen_phy_init_complete : std_logic;
signal mem_clk_disable : std_logic_vector(c_mem_clk_disable_pipe_len - 1 downto 0);
signal ctrl_broadcast_r : t_ctrl_command;
begin
-- register ctrl_broadcast locally
-- #for speed and to reduce fan out
process (clk, rst_n)
begin
if rst_n = '0' then
ctrl_broadcast_r <= defaults;
elsif rising_edge(clk) then
ctrl_broadcast_r <= ctrl_broadcast;
end if;
end process;
-- multiplex mem interface control between admin, dgrb and dgwb
process(clk, rst_n)
variable v_seq_ac_mux : t_addr_cmd_vector(0 to (DWIDTH_RATIO/2)-1);
begin
if rst_n = '0' then
seq_rdv_doing_rd <= (others => '0');
seq_mem_clk_disable <= '1';
mem_clk_disable <= (others => '1');
seen_phy_init_complete <= '0';
seq_ac_addr <= (others => '0');
seq_ac_ba <= (others => '0');
seq_ac_cas_n <= (others => '1');
seq_ac_ras_n <= (others => '1');
seq_ac_we_n <= (others => '1');
seq_ac_cke <= (others => '0');
seq_ac_cs_n <= (others => '1');
seq_ac_odt <= (others => '0');
seq_ac_rst_n <= (others => '0');
elsif rising_edge(clk) then
seq_rdv_doing_rd <= seq_rdv_doing_rd_int;
seq_mem_clk_disable <= mem_clk_disable(c_mem_clk_disable_pipe_len-1);
mem_clk_disable(c_mem_clk_disable_pipe_len-1 downto 1) <= mem_clk_disable(c_mem_clk_disable_pipe_len-2 downto 0);
if dgwb_ac_access_req = '1' and dgb_ac_access_gnt = '1' then
v_seq_ac_mux := dgwb_ac;
elsif dgrb_ac_access_req = '1' and dgb_ac_access_gnt = '1' then
v_seq_ac_mux := dgrb_ac;
else
v_seq_ac_mux := admin_ac;
end if;
if ctl_recalibrate_req = '1' then
mem_clk_disable(0) <= '1';
seen_phy_init_complete <= '0';
elsif ctrl_broadcast_r.command = cmd_init_dram and ctrl_broadcast_r.command_req = '1' then
mem_clk_disable(0) <= '0';
seen_phy_init_complete <= '1';
end if;
if seen_phy_init_complete /= '1' then -- if not initialised the phy hold in reset
seq_ac_addr <= (others => '0');
seq_ac_ba <= (others => '0');
seq_ac_cas_n <= (others => '1');
seq_ac_ras_n <= (others => '1');
seq_ac_we_n <= (others => '1');
seq_ac_cke <= (others => '0');
seq_ac_cs_n <= (others => '1');
seq_ac_odt <= (others => '0');
seq_ac_rst_n <= (others => '0');
else
if enable_odt = '0' then
v_seq_ac_mux := mask(c_seq_addr_cmd_config, v_seq_ac_mux, odt, '0');
end if;
unpack_addr_cmd_vector (
c_seq_addr_cmd_config,
v_seq_ac_mux,
seq_ac_addr,
seq_ac_ba,
seq_ac_cas_n,
seq_ac_ras_n,
seq_ac_we_n,
seq_ac_cke,
seq_ac_cs_n,
seq_ac_odt,
seq_ac_rst_n);
end if;
end if;
end process;
end block;
-- register dgb_ac_access_gnt signal to ensure ODT set correctly in dgrb and dgwb prior to a read or write operation
process(clk, rst_n)
begin
if rst_n = '0' then
dgb_ac_access_gnt_r <= '0';
elsif rising_edge(clk) then
dgb_ac_access_gnt_r <= dgb_ac_access_gnt;
end if;
end process;
-- multiplex access request from dgrb/dgwb to admin block with checking for multiple accesses
process (dgrb_ac_access_req, dgwb_ac_access_req)
begin
dgb_ac_access_req <= '0';
if dgwb_ac_access_req = '1' and dgrb_ac_access_req = '1' then
report seq_report_prefix & "multiple accesses attempted from DGRB and DGWB to admin block via signals dg.b_ac_access_reg " severity failure;
elsif dgwb_ac_access_req = '1' or dgrb_ac_access_req = '1' then
dgb_ac_access_req <= '1';
end if;
end process;
rdv_poa_blk : block
-- signals to control static setup of ctl_rdata_valid signal for instant on mode:
constant c_static_rdv_offset : integer := c_preset_cal_setup.rdv_lat; -- required change in RDV latency (should always be > 0)
signal static_rdv_offset : natural range 0 to abs(c_static_rdv_offset); -- signal to count # RDV shifts
constant c_dly_rdv_set : natural := 7; -- delay between RDV shifts
signal dly_rdv_inc_dec : std_logic; -- 1 = inc, 0 = dec
signal rdv_set_delay : natural range 0 to c_dly_rdv_set; -- signal to delay RDV shifts
-- same for poa protection
constant c_static_poa_offset : integer := c_preset_cal_setup.poa_lat;
signal static_poa_offset : natural range 0 to abs(c_static_poa_offset);
constant c_dly_poa_set : natural := 7;
signal dly_poa_inc_dec : std_logic;
signal poa_set_delay : natural range 0 to c_dly_poa_set;
-- function to abstract increment or decrement checking
function set_inc_dec(offset : integer) return std_logic is
begin
if offset < 0 then
return '1';
else
return '0';
end if;
end function;
begin
-- register postamble and rdata_valid latencies
-- note: postamble unused for Cyclone-III
-- RDV
process(clk, rst_n)
begin
if rst_n = '0' then
if SIM_TIME_REDUCTIONS = 1 then
-- setup offset calc
static_rdv_offset <= abs(c_static_rdv_offset);
dly_rdv_inc_dec <= set_inc_dec(c_static_rdv_offset);
rdv_set_delay <= c_dly_rdv_set;
end if;
seq_rdata_valid_lat_dec <= '0';
seq_rdata_valid_lat_inc <= '0';
elsif rising_edge(clk) then
if SIM_TIME_REDUCTIONS = 1 then -- perform static setup of RDV signal
if ctl_recalibrate_req = '1' then -- second reset condition
-- setup offset calc
static_rdv_offset <= abs(c_static_rdv_offset);
dly_rdv_inc_dec <= set_inc_dec(c_static_rdv_offset);
rdv_set_delay <= c_dly_rdv_set;
else
if static_rdv_offset /= 0 and
rdv_set_delay = 0 then
seq_rdata_valid_lat_dec <= not dly_rdv_inc_dec;
seq_rdata_valid_lat_inc <= dly_rdv_inc_dec;
static_rdv_offset <= static_rdv_offset - 1;
rdv_set_delay <= c_dly_rdv_set;
else -- once conplete pass through internal signals
seq_rdata_valid_lat_dec <= seq_rdata_valid_lat_dec_int;
seq_rdata_valid_lat_inc <= seq_rdata_valid_lat_inc_int;
end if;
if rdv_set_delay /= 0 then
rdv_set_delay <= rdv_set_delay - 1;
end if;
end if;
else -- no static setup
seq_rdata_valid_lat_dec <= seq_rdata_valid_lat_dec_int;
seq_rdata_valid_lat_inc <= seq_rdata_valid_lat_inc_int;
end if;
end if;
end process;
-- count number of RDV adjustments for debug
process(clk, rst_n)
begin
if rst_n = '0' then
rdv_adjustments <= 0;
elsif rising_edge(clk) then
if seq_rdata_valid_lat_dec_int = '1' then
rdv_adjustments <= rdv_adjustments + 1;
end if;
if seq_rdata_valid_lat_inc_int = '1' then
if rdv_adjustments = 0 then
report seq_report_prefix & " read data valid adjustment wrap around detected - more increments than decrements" severity failure;
else
rdv_adjustments <= rdv_adjustments - 1;
end if;
end if;
end if;
end process;
-- POA protection
process(clk, rst_n)
begin
if rst_n = '0' then
if SIM_TIME_REDUCTIONS = 1 then
-- setup offset calc
static_poa_offset <= abs(c_static_poa_offset);
dly_poa_inc_dec <= set_inc_dec(c_static_poa_offset);
poa_set_delay <= c_dly_poa_set;
end if;
seq_poa_lat_dec_1x <= (others => '0');
seq_poa_lat_inc_1x <= (others => '0');
elsif rising_edge(clk) then
if SIM_TIME_REDUCTIONS = 1 then -- static setup
if ctl_recalibrate_req = '1' then -- second reset condition
-- setup offset calc
static_poa_offset <= abs(c_static_poa_offset);
dly_poa_inc_dec <= set_inc_dec(c_static_poa_offset);
poa_set_delay <= c_dly_poa_set;
else
if static_poa_offset /= 0 and
poa_set_delay = 0 then
seq_poa_lat_dec_1x <= (others => not(dly_poa_inc_dec));
seq_poa_lat_inc_1x <= (others => dly_poa_inc_dec);
static_poa_offset <= static_poa_offset - 1;
poa_set_delay <= c_dly_poa_set;
else
seq_poa_lat_inc_1x <= seq_poa_lat_inc_1x_int;
seq_poa_lat_dec_1x <= seq_poa_lat_dec_1x_int;
end if;
if poa_set_delay /= 0 then
poa_set_delay <= poa_set_delay - 1;
end if;
end if;
else -- no static setup
seq_poa_lat_inc_1x <= seq_poa_lat_inc_1x_int;
seq_poa_lat_dec_1x <= seq_poa_lat_dec_1x_int;
end if;
end if;
end process;
-- count POA protection adjustments for debug
process(clk, rst_n)
begin
if rst_n = '0' then
poa_adjustments <= 0;
elsif rising_edge(clk) then
if seq_poa_lat_dec_1x_int(0) = '1' then
poa_adjustments <= poa_adjustments + 1;
end if;
if seq_poa_lat_inc_1x_int(0) = '1' then
if poa_adjustments = 0 then
report seq_report_prefix & " postamble adjustment wrap around detected - more increments than decrements" severity failure;
else
poa_adjustments <= poa_adjustments - 1;
end if;
end if;
end if;
end process;
end block;
-- register output fail/success signals - avoiding optimisation out
process(clk, rst_n)
begin
if rst_n = '0' then
ctl_init_fail <= '0';
ctl_init_success <= '0';
elsif rising_edge(clk) then
ctl_init_fail <= ctl_init_fail_int;
ctl_init_success <= ctl_init_success_int;
end if;
end process;
-- ctl_cal_byte_lanes register
-- seq_rdp_reset_req_n - when ctl_recalibrate_req issued
process(clk,rst_n)
begin
if rst_n = '0' then
seq_rdp_reset_req_n <= '0';
ctl_cal_byte_lanes_r <= (others => '1');
elsif rising_edge(clk) then
ctl_cal_byte_lanes_r <= not ctl_cal_byte_lanes;
if ctl_recalibrate_req = '1' then
seq_rdp_reset_req_n <= '0';
else
if ctrl_broadcast.command = cmd_rrp_sweep or
SIM_TIME_REDUCTIONS = 1 then
seq_rdp_reset_req_n <= '1';
end if;
end if;
end if;
end process;
-- register 1t addr/cmd and odt latency outputs
process(clk, rst_n)
begin
if rst_n = '0' then
seq_ac_add_1t_ac_lat_internal <= '0';
seq_ac_add_1t_odt_lat_internal <= '0';
seq_ac_add_2t <= '0';
elsif rising_edge(clk) then
if SIM_TIME_REDUCTIONS = 1 then
seq_ac_add_1t_ac_lat_internal <= c_preset_cal_setup.ac_1t;
seq_ac_add_1t_odt_lat_internal <= c_preset_cal_setup.ac_1t;
else
seq_ac_add_1t_ac_lat_internal <= int_ac_nt(0);
seq_ac_add_1t_odt_lat_internal <= int_ac_nt(0);
end if;
seq_ac_add_2t <= '0';
end if;
end process;
-- override write datapath signal generation
process(dgwb_wdp_override, dgrb_wdp_override, ctl_init_success_int, ctl_init_fail_int)
begin
if ctl_init_success_int = '0' and ctl_init_fail_int = '0' then -- if calibrating
seq_wdp_ovride <= dgwb_wdp_override or dgrb_wdp_override;
else
seq_wdp_ovride <= '0';
end if;
end process;
-- output write/read latency (override with preset values when sim time reductions equals 1
seq_ctl_wlat <= std_logic_vector(to_unsigned(c_preset_cal_setup.wlat,ADV_LAT_WIDTH)) when SIM_TIME_REDUCTIONS = 1 else seq_ctl_wlat_int;
seq_ctl_rlat <= std_logic_vector(to_unsigned(c_preset_cal_setup.rlat,ADV_LAT_WIDTH)) when SIM_TIME_REDUCTIONS = 1 else seq_ctl_rlat_int;
process (clk, rst_n)
begin
if rst_n = '0' then
seq_pll_phs_shift_busy_r <= '0';
seq_pll_phs_shift_busy_ccd <= '0';
elsif rising_edge(clk) then
seq_pll_phs_shift_busy_r <= seq_pll_phs_shift_busy;
seq_pll_phs_shift_busy_ccd <= seq_pll_phs_shift_busy_r;
end if;
end process;
pll_ctrl: block
-- static resync setup variables for sim time reductions
signal static_rst_offset : natural range 0 to 2*PLL_STEPS_PER_CYCLE;
signal phs_shft_busy_1r : std_logic;
signal pll_set_delay : natural range 100 downto 0; -- wait 100 clock cycles for clk to be stable before setting resync phase
-- pll signal generation
signal mmi_pll_active : boolean;
signal seq_pll_phs_shift_busy_ccd_1t : std_logic;
begin
-- multiplex ppl interface between dgrb and mmi blocks
-- plus static setup of rsc phase to a known 'good' condition
process(clk,rst_n)
begin
if rst_n = '0' then
seq_pll_inc_dec_n <= '0';
seq_pll_start_reconfig <= '0';
seq_pll_select <= (others => '0');
dgrb_phs_shft_busy <= '0';
-- static resync setup variables for sim time reductions
if SIM_TIME_REDUCTIONS = 1 then
static_rst_offset <= c_preset_codvw_phase;
else
static_rst_offset <= 0;
end if;
phs_shft_busy_1r <= '0';
pll_set_delay <= 100;
elsif rising_edge(clk) then
dgrb_phs_shft_busy <= '0';
if static_rst_offset /= 0 and -- not finished decrementing
pll_set_delay = 0 and -- initial reset period over
SIM_TIME_REDUCTIONS = 1 then -- in reduce sim time mode (optimse logic away when not in this mode)
seq_pll_inc_dec_n <= '1';
seq_pll_start_reconfig <= '1';
seq_pll_select <= pll_resync_clk_index;
if seq_pll_phs_shift_busy_ccd = '1' then -- no metastability hardening needed in simulation
-- PLL phase shift started - so stop requesting a shift
seq_pll_start_reconfig <= '0';
end if;
if seq_pll_phs_shift_busy_ccd = '0' and phs_shft_busy_1r = '1' then
-- PLL phase shift finished - so proceed to flush the datapath
static_rst_offset <= static_rst_offset - 1;
seq_pll_start_reconfig <= '0';
end if;
phs_shft_busy_1r <= seq_pll_phs_shift_busy_ccd;
else
if ctrl_iram_push.active_block = ret_dgrb then
seq_pll_inc_dec_n <= dgrb_pll_inc_dec_n;
seq_pll_start_reconfig <= dgrb_pll_start_reconfig;
seq_pll_select <= dgrb_pll_select;
dgrb_phs_shft_busy <= seq_pll_phs_shift_busy_ccd;
else
seq_pll_inc_dec_n <= mmi_pll_inc_dec_n;
seq_pll_start_reconfig <= mmi_pll_start_reconfig;
seq_pll_select <= mmi_pll_select;
end if;
end if;
if pll_set_delay /= 0 then
pll_set_delay <= pll_set_delay - 1;
end if;
if ctl_recalibrate_req = '1' then
pll_set_delay <= 100;
end if;
end if;
end process;
-- generate mmi pll signals
process (clk, rst_n)
begin
if rst_n = '0' then
pll_mmi.pll_busy <= '0';
pll_mmi.err <= (others => '0');
mmi_pll_inc_dec_n <= '0';
mmi_pll_start_reconfig <= '0';
mmi_pll_select <= (others => '0');
mmi_pll_active <= false;
seq_pll_phs_shift_busy_ccd_1t <= '0';
elsif rising_edge(clk) then
if mmi_pll_active = true then
pll_mmi.pll_busy <= '1';
else
pll_mmi.pll_busy <= mmi_pll.pll_phs_shft_up_wc or mmi_pll.pll_phs_shft_dn_wc;
end if;
if pll_mmi.err = "00" and dgrb_pll_start_reconfig = '1' then
pll_mmi.err <= "01";
elsif pll_mmi.err = "00" and mmi_pll_active = true then
pll_mmi.err <= "10";
elsif pll_mmi.err = "00" and dgrb_pll_start_reconfig = '1' and mmi_pll_active = true then
pll_mmi.err <= "11";
end if;
if mmi_pll.pll_phs_shft_up_wc = '1' and mmi_pll_active = false then
mmi_pll_inc_dec_n <= '1';
mmi_pll_select <= std_logic_vector(to_unsigned(mmi_pll.pll_phs_shft_phase_sel,mmi_pll_select'length));
mmi_pll_active <= true;
elsif mmi_pll.pll_phs_shft_dn_wc = '1' and mmi_pll_active = false then
mmi_pll_inc_dec_n <= '0';
mmi_pll_select <= std_logic_vector(to_unsigned(mmi_pll.pll_phs_shft_phase_sel,mmi_pll_select'length));
mmi_pll_active <= true;
elsif seq_pll_phs_shift_busy_ccd_1t = '1' and seq_pll_phs_shift_busy_ccd = '0' then
mmi_pll_start_reconfig <= '0';
mmi_pll_active <= false;
elsif mmi_pll_active = true and mmi_pll_start_reconfig = '0' and seq_pll_phs_shift_busy_ccd = '0' then
mmi_pll_start_reconfig <= '1';
elsif seq_pll_phs_shift_busy_ccd_1t = '0' and seq_pll_phs_shift_busy_ccd = '1' then
mmi_pll_start_reconfig <= '0';
end if;
seq_pll_phs_shift_busy_ccd_1t <= seq_pll_phs_shift_busy_ccd;
end if;
end process;
end block; -- pll_ctrl
--synopsys synthesis_off
reporting : block
function pass_or_fail_report( cal_success : in std_logic;
cal_fail : in std_logic
) return string is
begin
if cal_success = '1' and cal_fail = '1' then
return "unknown state cal_fail and cal_success both high";
end if;
if cal_success = '1' then
return "PASSED";
end if;
if cal_fail = '1' then
return "FAILED";
end if;
return "calibration report run whilst sequencer is still calibrating";
end function;
function is_stage_disabled ( stage_name : in string;
stage_dis : in std_logic
) return string is
begin
if stage_dis = '0' then
return "";
else
return stage_name & " stage is disabled" & LF;
end if;
end function;
function disabled_stages ( capabilities : in std_logic_vector
) return string is
begin
return is_stage_disabled("all calibration", c_capabilities(c_hl_css_reg_cal_dis_bit)) &
is_stage_disabled("initialisation", c_capabilities(c_hl_css_reg_phy_initialise_dis_bit)) &
is_stage_disabled("DRAM initialisation", c_capabilities(c_hl_css_reg_init_dram_dis_bit)) &
is_stage_disabled("iram header write", c_capabilities(c_hl_css_reg_write_ihi_dis_bit)) &
is_stage_disabled("burst training pattern write", c_capabilities(c_hl_css_reg_write_btp_dis_bit)) &
is_stage_disabled("more training pattern (MTP) write", c_capabilities(c_hl_css_reg_write_mtp_dis_bit)) &
is_stage_disabled("check MTP pattern alignment calculation", c_capabilities(c_hl_css_reg_read_mtp_dis_bit)) &
is_stage_disabled("read resynch phase reset stage", c_capabilities(c_hl_css_reg_rrp_reset_dis_bit)) &
is_stage_disabled("read resynch phase sweep stage", c_capabilities(c_hl_css_reg_rrp_sweep_dis_bit)) &
is_stage_disabled("read resynch phase seek stage (set phase)", c_capabilities(c_hl_css_reg_rrp_seek_dis_bit)) &
is_stage_disabled("read data valid window setup", c_capabilities(c_hl_css_reg_rdv_dis_bit)) &
is_stage_disabled("postamble calibration", c_capabilities(c_hl_css_reg_poa_dis_bit)) &
is_stage_disabled("write latency timing calc", c_capabilities(c_hl_css_reg_was_dis_bit)) &
is_stage_disabled("advertise read latency", c_capabilities(c_hl_css_reg_adv_rd_lat_dis_bit)) &
is_stage_disabled("advertise write latency", c_capabilities(c_hl_css_reg_adv_wr_lat_dis_bit)) &
is_stage_disabled("write customer mode register settings", c_capabilities(c_hl_css_reg_prep_customer_mr_setup_dis_bit)) &
is_stage_disabled("tracking", c_capabilities(c_hl_css_reg_tracking_dis_bit));
end function;
function ac_nt_report( ac_nt : in std_logic_vector;
dgrb_ctrl_ac_nt_good : in std_logic;
preset_cal_setup : in t_preset_cal) return string
is
variable v_ac_nt : std_logic_vector(0 downto 0);
begin
if SIM_TIME_REDUCTIONS = 1 then
v_ac_nt(0) := preset_cal_setup.ac_1t;
if v_ac_nt(0) = '1' then
return "-- statically set address and command 1T delay: add 1T delay" & LF;
else
return "-- statically set address and command 1T delay: no 1T delay" & LF;
end if;
else
v_ac_nt(0) := ac_nt(0);
if dgrb_ctrl_ac_nt_good = '1' then
if v_ac_nt(0) = '1' then
return "-- chosen address and command 1T delay: add 1T delay" & LF;
else
return "-- chosen address and command 1T delay: no 1T delay" & LF;
end if;
else
return "-- no valid address and command phase chosen (calibration FAILED)" & LF;
end if;
end if;
end function;
function read_resync_report ( codvw_phase : in std_logic_vector;
codvw_size : in std_logic_vector;
ctl_rlat : in std_logic_vector;
ctl_wlat : in std_logic_vector;
preset_cal_setup : in t_preset_cal) return string
is
begin
if SIM_TIME_REDUCTIONS = 1 then
return "-- read resynch phase static setup (no calibration run) report:" & LF &
" -- statically set centre of data valid window phase : " & natural'image(preset_cal_setup.codvw_phase) & LF &
" -- statically set centre of data valid window size : " & natural'image(preset_cal_setup.codvw_size) & LF &
" -- statically set read latency (ctl_rlat) : " & natural'image(preset_cal_setup.rlat) & LF &
" -- statically set write latency (ctl_wlat) : " & natural'image(preset_cal_setup.wlat) & LF &
" -- note: this mode only works for simulation and sets resync phase" & LF &
" to a known good operating condition for no test bench" & LF &
" delays on mem_dq signal" & LF;
else
return "-- PHY read latency (ctl_rlat) is : " & natural'image(to_integer(unsigned(ctl_rlat))) & LF &
"-- address/command to PHY write latency (ctl_wlat) is : " & natural'image(to_integer(unsigned(ctl_wlat))) & LF &
"-- read resynch phase calibration report:" & LF &
" -- calibrated centre of data valid window phase : " & natural'image(to_integer(unsigned(codvw_phase))) & LF &
" -- calibrated centre of data valid window size : " & natural'image(to_integer(unsigned(codvw_size))) & LF;
end if;
end function;
function poa_rdv_adjust_report( poa_adjust : in natural;
rdv_adjust : in natural;
preset_cal_setup : in t_preset_cal) return string
is
begin
if SIM_TIME_REDUCTIONS = 1 then
return "Statically set poa and rdv (adjustments from reset value):" & LF &
"poa 'dec' adjustments = " & natural'image(preset_cal_setup.poa_lat) & LF &
"rdv 'dec' adjustments = " & natural'image(preset_cal_setup.rdv_lat) & LF;
else
return "poa 'dec' adjustments = " & natural'image(poa_adjust) & LF &
"rdv 'dec' adjustments = " & natural'image(rdv_adjust) & LF;
end if;
end function;
function calibration_report ( capabilities : in std_logic_vector;
cal_success : in std_logic;
cal_fail : in std_logic;
ctl_rlat : in std_logic_vector;
ctl_wlat : in std_logic_vector;
codvw_phase : in std_logic_vector;
codvw_size : in std_logic_vector;
ac_nt : in std_logic_vector;
dgrb_ctrl_ac_nt_good : in std_logic;
preset_cal_setup : in t_preset_cal;
poa_adjust : in natural;
rdv_adjust : in natural) return string
is
begin
return seq_report_prefix & " report..." & LF &
"-----------------------------------------------------------------------" & LF &
"-- **** ALTMEMPHY CALIBRATION has completed ****" & LF &
"-- Status:" & LF &
"-- calibration has : " & pass_or_fail_report(cal_success, cal_fail) & LF &
read_resync_report(codvw_phase, codvw_size, ctl_rlat, ctl_wlat, preset_cal_setup) &
ac_nt_report(ac_nt, dgrb_ctrl_ac_nt_good, preset_cal_setup) &
poa_rdv_adjust_report(poa_adjust, rdv_adjust, preset_cal_setup) &
disabled_stages(capabilities) &
"-----------------------------------------------------------------------";
end function;
begin
-- -------------------------------------------------------
-- calibration result reporting
-- -------------------------------------------------------
process(rst_n, clk)
variable v_reports_written : std_logic;
variable v_cal_request_r : std_logic;
variable v_rewrite_report : std_logic;
begin
if rst_n = '0' then
v_reports_written := '0';
v_cal_request_r := '0';
v_rewrite_report := '0';
elsif Rising_Edge(clk) then
if v_reports_written = '0' then
if ctl_init_success_int = '1' or ctl_init_fail_int = '1' then
v_reports_written := '1';
report calibration_report(c_capabilities,
ctl_init_success_int,
ctl_init_fail_int,
seq_ctl_rlat_int,
seq_ctl_wlat_int,
dgrb_mmi.cal_codvw_phase,
dgrb_mmi.cal_codvw_size,
int_ac_nt,
dgrb_ctrl_ac_nt_good,
c_preset_cal_setup,
poa_adjustments,
rdv_adjustments
) severity note;
end if;
end if;
-- if recalibrate request triggered watch for cal success / fail going low and re-trigger report writing
if ctl_recalibrate_req = '1' and v_cal_request_r = '0' then
v_rewrite_report := '1';
end if;
if v_rewrite_report = '1' and ctl_init_success_int = '0' and ctl_init_fail_int = '0' then
v_reports_written := '0';
v_rewrite_report := '0';
end if;
v_cal_request_r := ctl_recalibrate_req;
end if;
end process;
-- -------------------------------------------------------
-- capabilities vector reporting and coarse PHY setup sanity checks
-- -------------------------------------------------------
process(rst_n, clk)
variable reports_written : std_logic;
begin
if rst_n = '0' then
reports_written := '0';
elsif Rising_Edge(clk) then
if reports_written = '0' then
reports_written := '1';
if MEM_IF_MEMTYPE="DDR" or MEM_IF_MEMTYPE="DDR2" or MEM_IF_MEMTYPE="DDR3" then
if DWIDTH_RATIO = 2 or DWIDTH_RATIO = 4 then
report disabled_stages(c_capabilities) severity note;
else
report seq_report_prefix & "unsupported rate for non-levelling AFI PHY sequencer - only full- or half-rate supported" severity warning;
end if;
else
report seq_report_prefix & "memory type " & MEM_IF_MEMTYPE & " is not supported in non-levelling AFI PHY sequencer" severity failure;
end if;
end if;
end if;
end process;
end block; -- reporting
--synopsys synthesis_on
end architecture struct;
| gpl-3.0 |
freecores/usb_fpga_1_2 | examples/usb-fpga-1.11/1.11a/intraffic/fpga/intraffic.vhd | 42 | 1939 | library ieee;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity intraffic is
port(
RESET : in std_logic;
CONT : in std_logic;
IFCLK : in std_logic;
FD : out std_logic_vector(15 downto 0);
SLOE : out std_logic;
SLRD : out std_logic;
SLWR : out std_logic;
FIFOADR0 : out std_logic;
FIFOADR1 : out std_logic;
PKTEND : out std_logic;
FLAGB : in std_logic
);
end intraffic;
architecture RTL of intraffic is
----------------------------
-- test pattern generator --
----------------------------
-- 30 bit counter
signal GEN_CNT : std_logic_vector(29 downto 0);
signal INT_CNT : std_logic_vector(6 downto 0);
signal FIFO_WORD : std_logic;
begin
SLOE <= '1';
SLRD <= '1';
FIFOADR0 <= '0';
FIFOADR1 <= '0';
PKTEND <= '1'; -- no data alignment
dpIFCLK: process (IFCLK, RESET)
begin
-- reset
if RESET = '1'
then
GEN_CNT <= ( others => '0' );
INT_CNT <= ( others => '0' );
FIFO_WORD <= '0';
SLWR <= '1';
-- IFCLK
elsif IFCLK'event and IFCLK = '1'
then
if CONT = '1' or FLAGB = '1'
then
if FIFO_WORD = '0'
then
FD(14 downto 0) <= GEN_CNT(14 downto 0);
else
FD(14 downto 0) <= GEN_CNT(29 downto 15);
end if;
FD(15) <= FIFO_WORD;
if FIFO_WORD = '1'
then
GEN_CNT <= GEN_CNT + '1';
if INT_CNT = conv_std_logic_vector(99,7)
then
INT_CNT <= ( others => '0' );
else
INT_CNT <= INT_CNT + '1';
end if;
end if;
FIFO_WORD <= not FIFO_WORD;
end if;
if ( INT_CNT >= conv_std_logic_vector(90,7) ) and ( CONT = '0' )
then
SLWR <= '1';
else
SLWR <= '0';
end if;
end if;
end process dpIFCLK;
end RTL;
| gpl-3.0 |
freecores/usb_fpga_1_2 | examples/usb-fpga-1.15/1.15d/intraffic/fpga/intraffic.vhd | 42 | 1939 | library ieee;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity intraffic is
port(
RESET : in std_logic;
CONT : in std_logic;
IFCLK : in std_logic;
FD : out std_logic_vector(15 downto 0);
SLOE : out std_logic;
SLRD : out std_logic;
SLWR : out std_logic;
FIFOADR0 : out std_logic;
FIFOADR1 : out std_logic;
PKTEND : out std_logic;
FLAGB : in std_logic
);
end intraffic;
architecture RTL of intraffic is
----------------------------
-- test pattern generator --
----------------------------
-- 30 bit counter
signal GEN_CNT : std_logic_vector(29 downto 0);
signal INT_CNT : std_logic_vector(6 downto 0);
signal FIFO_WORD : std_logic;
begin
SLOE <= '1';
SLRD <= '1';
FIFOADR0 <= '0';
FIFOADR1 <= '0';
PKTEND <= '1'; -- no data alignment
dpIFCLK: process (IFCLK, RESET)
begin
-- reset
if RESET = '1'
then
GEN_CNT <= ( others => '0' );
INT_CNT <= ( others => '0' );
FIFO_WORD <= '0';
SLWR <= '1';
-- IFCLK
elsif IFCLK'event and IFCLK = '1'
then
if CONT = '1' or FLAGB = '1'
then
if FIFO_WORD = '0'
then
FD(14 downto 0) <= GEN_CNT(14 downto 0);
else
FD(14 downto 0) <= GEN_CNT(29 downto 15);
end if;
FD(15) <= FIFO_WORD;
if FIFO_WORD = '1'
then
GEN_CNT <= GEN_CNT + '1';
if INT_CNT = conv_std_logic_vector(99,7)
then
INT_CNT <= ( others => '0' );
else
INT_CNT <= INT_CNT + '1';
end if;
end if;
FIFO_WORD <= not FIFO_WORD;
end if;
if ( INT_CNT >= conv_std_logic_vector(90,7) ) and ( CONT = '0' )
then
SLWR <= '1';
else
SLWR <= '0';
end if;
end if;
end process dpIFCLK;
end RTL;
| gpl-3.0 |
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