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// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_r0_p1_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd1;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_r0_p1 (
address0,
ce0,
q0,
we0,
d0,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input clk;
reg[DataWidth-1:0] q0;
wire[1 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[1 * AddressWidth - 1:0] mem_ra;
wire[1 - 1:0] mem_ce;
denoise_r0_p1_core #(
.READ_PORT_COUNT( 1 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_ra = {address0};
assign mem_ce = {ce0};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_r0_p2_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd1;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_r0_p2 (
address0,
ce0,
q0,
we0,
d0,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input clk;
reg[DataWidth-1:0] q0;
wire[1 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[1 * AddressWidth - 1:0] mem_ra;
wire[1 - 1:0] mem_ce;
denoise_r0_p2_core #(
.READ_PORT_COUNT( 1 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_ra = {address0};
assign mem_ce = {ce0};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_r0_p3_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd1;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_r0_p3 (
address0,
ce0,
q0,
we0,
d0,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input clk;
reg[DataWidth-1:0] q0;
wire[1 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[1 * AddressWidth - 1:0] mem_ra;
wire[1 - 1:0] mem_ce;
denoise_r0_p3_core #(
.READ_PORT_COUNT( 1 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_ra = {address0};
assign mem_ce = {ce0};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_r1_p0_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd1;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_r1_p0 (
address0,
ce0,
q0,
we0,
d0,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input clk;
reg[DataWidth-1:0] q0;
wire[1 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[1 * AddressWidth - 1:0] mem_ra;
wire[1 - 1:0] mem_ce;
denoise_r1_p0_core #(
.READ_PORT_COUNT( 1 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_ra = {address0};
assign mem_ce = {ce0};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_r1_p1_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd1;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_r1_p1 (
address0,
ce0,
q0,
we0,
d0,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input clk;
reg[DataWidth-1:0] q0;
wire[1 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[1 * AddressWidth - 1:0] mem_ra;
wire[1 - 1:0] mem_ce;
denoise_r1_p1_core #(
.READ_PORT_COUNT( 1 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_ra = {address0};
assign mem_ce = {ce0};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_r1_p2_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd1;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_r1_p2 (
address0,
ce0,
q0,
we0,
d0,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input clk;
reg[DataWidth-1:0] q0;
wire[1 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[1 * AddressWidth - 1:0] mem_ra;
wire[1 - 1:0] mem_ce;
denoise_r1_p2_core #(
.READ_PORT_COUNT( 1 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_ra = {address0};
assign mem_ce = {ce0};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_r1_p3_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd1;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_r1_p3 (
address0,
ce0,
q0,
we0,
d0,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input clk;
reg[DataWidth-1:0] q0;
wire[1 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[1 * AddressWidth - 1:0] mem_ra;
wire[1 - 1:0] mem_ce;
denoise_r1_p3_core #(
.READ_PORT_COUNT( 1 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_ra = {address0};
assign mem_ce = {ce0};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_sm0_p0_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd1;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_sm0_p0 (
address0,
ce0,
q0,
we0,
d0,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input clk;
reg[DataWidth-1:0] q0;
wire[1 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[1 * AddressWidth - 1:0] mem_ra;
wire[1 - 1:0] mem_ce;
denoise_sm0_p0_core #(
.READ_PORT_COUNT( 1 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_ra = {address0};
assign mem_ce = {ce0};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_sm0_p1_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd1;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_sm0_p1 (
address0,
ce0,
q0,
we0,
d0,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input clk;
reg[DataWidth-1:0] q0;
wire[1 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[1 * AddressWidth - 1:0] mem_ra;
wire[1 - 1:0] mem_ce;
denoise_sm0_p1_core #(
.READ_PORT_COUNT( 1 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_ra = {address0};
assign mem_ce = {ce0};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_sm0_p2_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd1;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_sm0_p2 (
address0,
ce0,
q0,
we0,
d0,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input clk;
reg[DataWidth-1:0] q0;
wire[1 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[1 * AddressWidth - 1:0] mem_ra;
wire[1 - 1:0] mem_ce;
denoise_sm0_p2_core #(
.READ_PORT_COUNT( 1 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_ra = {address0};
assign mem_ce = {ce0};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_sm0_p3_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd1;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_sm0_p3 (
address0,
ce0,
q0,
we0,
d0,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input clk;
reg[DataWidth-1:0] q0;
wire[1 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[1 * AddressWidth - 1:0] mem_ra;
wire[1 - 1:0] mem_ce;
denoise_sm0_p3_core #(
.READ_PORT_COUNT( 1 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_ra = {address0};
assign mem_ce = {ce0};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_sm1_p0_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd1;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_sm1_p0 (
address0,
ce0,
q0,
we0,
d0,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input clk;
reg[DataWidth-1:0] q0;
wire[1 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[1 * AddressWidth - 1:0] mem_ra;
wire[1 - 1:0] mem_ce;
denoise_sm1_p0_core #(
.READ_PORT_COUNT( 1 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_ra = {address0};
assign mem_ce = {ce0};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_sm1_p1_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd1;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_sm1_p1 (
address0,
ce0,
q0,
we0,
d0,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input clk;
reg[DataWidth-1:0] q0;
wire[1 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[1 * AddressWidth - 1:0] mem_ra;
wire[1 - 1:0] mem_ce;
denoise_sm1_p1_core #(
.READ_PORT_COUNT( 1 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_ra = {address0};
assign mem_ce = {ce0};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_sm1_p2_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd1;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_sm1_p2 (
address0,
ce0,
q0,
we0,
d0,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input clk;
reg[DataWidth-1:0] q0;
wire[1 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[1 * AddressWidth - 1:0] mem_ra;
wire[1 - 1:0] mem_ce;
denoise_sm1_p2_core #(
.READ_PORT_COUNT( 1 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_ra = {address0};
assign mem_ce = {ce0};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_sm1_p3_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd1;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_sm1_p3 (
address0,
ce0,
q0,
we0,
d0,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input clk;
reg[DataWidth-1:0] q0;
wire[1 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[1 * AddressWidth - 1:0] mem_ra;
wire[1 - 1:0] mem_ce;
denoise_sm1_p3_core #(
.READ_PORT_COUNT( 1 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_ra = {address0};
assign mem_ce = {ce0};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_sn0_p0_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd2;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or rai_reg[1] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_sn0_p0 (
address0,
ce0,
q0,
we0,
d0,
address1,
ce1,
q1,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input[AddressWidth-1:0] address1;
input ce1;
output[DataWidth-1:0] q1;
input clk;
reg[DataWidth-1:0] q0;
reg[DataWidth-1:0] q1;
wire[2 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[DataWidth - 1:0] mem_q1;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[2 * AddressWidth - 1:0] mem_ra;
wire[2 - 1:0] mem_ce;
denoise_sn0_p0_core #(
.READ_PORT_COUNT( 2 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[2 * DataWidth - 1 : 1 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_q1 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q1) begin
q1 = mem_q1;
end
assign mem_ra = {address0, address1};
assign mem_ce = {ce0, ce1};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_sn0_p1_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd1;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_sn0_p1 (
address0,
ce0,
q0,
we0,
d0,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input clk;
reg[DataWidth-1:0] q0;
wire[1 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[1 * AddressWidth - 1:0] mem_ra;
wire[1 - 1:0] mem_ce;
denoise_sn0_p1_core #(
.READ_PORT_COUNT( 1 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_ra = {address0};
assign mem_ce = {ce0};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_sn0_p2_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd1;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_sn0_p2 (
address0,
ce0,
q0,
we0,
d0,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input clk;
reg[DataWidth-1:0] q0;
wire[1 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[1 * AddressWidth - 1:0] mem_ra;
wire[1 - 1:0] mem_ce;
denoise_sn0_p2_core #(
.READ_PORT_COUNT( 1 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_ra = {address0};
assign mem_ce = {ce0};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_sn0_p3_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd1;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_sn0_p3 (
address0,
ce0,
q0,
we0,
d0,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input clk;
reg[DataWidth-1:0] q0;
wire[1 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[1 * AddressWidth - 1:0] mem_ra;
wire[1 - 1:0] mem_ce;
denoise_sn0_p3_core #(
.READ_PORT_COUNT( 1 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_ra = {address0};
assign mem_ce = {ce0};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_sn1_p0_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd2;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or rai_reg[1] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_sn1_p0 (
address0,
ce0,
q0,
we0,
d0,
address1,
ce1,
q1,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input[AddressWidth-1:0] address1;
input ce1;
output[DataWidth-1:0] q1;
input clk;
reg[DataWidth-1:0] q0;
reg[DataWidth-1:0] q1;
wire[2 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[DataWidth - 1:0] mem_q1;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[2 * AddressWidth - 1:0] mem_ra;
wire[2 - 1:0] mem_ce;
denoise_sn1_p0_core #(
.READ_PORT_COUNT( 2 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[2 * DataWidth - 1 : 1 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_q1 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q1) begin
q1 = mem_q1;
end
assign mem_ra = {address0, address1};
assign mem_ce = {ce0, ce1};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_sn1_p1_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd1;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_sn1_p1 (
address0,
ce0,
q0,
we0,
d0,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input clk;
reg[DataWidth-1:0] q0;
wire[1 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[1 * AddressWidth - 1:0] mem_ra;
wire[1 - 1:0] mem_ce;
denoise_sn1_p1_core #(
.READ_PORT_COUNT( 1 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_ra = {address0};
assign mem_ce = {ce0};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_sn1_p2_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd1;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_sn1_p2 (
address0,
ce0,
q0,
we0,
d0,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input clk;
reg[DataWidth-1:0] q0;
wire[1 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[1 * AddressWidth - 1:0] mem_ra;
wire[1 - 1:0] mem_ce;
denoise_sn1_p2_core #(
.READ_PORT_COUNT( 1 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_ra = {address0};
assign mem_ce = {ce0};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_sn1_p3_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd1;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_sn1_p3 (
address0,
ce0,
q0,
we0,
d0,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input clk;
reg[DataWidth-1:0] q0;
wire[1 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[1 * AddressWidth - 1:0] mem_ra;
wire[1 - 1:0] mem_ce;
denoise_sn1_p3_core #(
.READ_PORT_COUNT( 1 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_ra = {address0};
assign mem_ce = {ce0};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_sp0_p0_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd1;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_sp0_p0 (
address0,
ce0,
q0,
we0,
d0,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input clk;
reg[DataWidth-1:0] q0;
wire[1 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[1 * AddressWidth - 1:0] mem_ra;
wire[1 - 1:0] mem_ce;
denoise_sp0_p0_core #(
.READ_PORT_COUNT( 1 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_ra = {address0};
assign mem_ce = {ce0};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_sp0_p1_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd1;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_sp0_p1 (
address0,
ce0,
q0,
we0,
d0,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input clk;
reg[DataWidth-1:0] q0;
wire[1 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[1 * AddressWidth - 1:0] mem_ra;
wire[1 - 1:0] mem_ce;
denoise_sp0_p1_core #(
.READ_PORT_COUNT( 1 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_ra = {address0};
assign mem_ce = {ce0};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_sp0_p2_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd1;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_sp0_p2 (
address0,
ce0,
q0,
we0,
d0,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input clk;
reg[DataWidth-1:0] q0;
wire[1 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[1 * AddressWidth - 1:0] mem_ra;
wire[1 - 1:0] mem_ce;
denoise_sp0_p2_core #(
.READ_PORT_COUNT( 1 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_ra = {address0};
assign mem_ce = {ce0};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_sp0_p3_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd1;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_sp0_p3 (
address0,
ce0,
q0,
we0,
d0,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input clk;
reg[DataWidth-1:0] q0;
wire[1 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[1 * AddressWidth - 1:0] mem_ra;
wire[1 - 1:0] mem_ce;
denoise_sp0_p3_core #(
.READ_PORT_COUNT( 1 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_ra = {address0};
assign mem_ce = {ce0};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_sp1_p0_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd1;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_sp1_p0 (
address0,
ce0,
q0,
we0,
d0,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input clk;
reg[DataWidth-1:0] q0;
wire[1 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[1 * AddressWidth - 1:0] mem_ra;
wire[1 - 1:0] mem_ce;
denoise_sp1_p0_core #(
.READ_PORT_COUNT( 1 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_ra = {address0};
assign mem_ce = {ce0};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_sp1_p1_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd1;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_sp1_p1 (
address0,
ce0,
q0,
we0,
d0,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input clk;
reg[DataWidth-1:0] q0;
wire[1 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[1 * AddressWidth - 1:0] mem_ra;
wire[1 - 1:0] mem_ce;
denoise_sp1_p1_core #(
.READ_PORT_COUNT( 1 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_ra = {address0};
assign mem_ce = {ce0};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_sp1_p2_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd1;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_sp1_p2 (
address0,
ce0,
q0,
we0,
d0,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input clk;
reg[DataWidth-1:0] q0;
wire[1 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[1 * AddressWidth - 1:0] mem_ra;
wire[1 - 1:0] mem_ce;
denoise_sp1_p2_core #(
.READ_PORT_COUNT( 1 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_ra = {address0};
assign mem_ce = {ce0};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_sp1_p3_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd1;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_sp1_p3 (
address0,
ce0,
q0,
we0,
d0,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input clk;
reg[DataWidth-1:0] q0;
wire[1 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[1 * AddressWidth - 1:0] mem_ra;
wire[1 - 1:0] mem_ce;
denoise_sp1_p3_core #(
.READ_PORT_COUNT( 1 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_ra = {address0};
assign mem_ce = {ce0};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_sp2_p0_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd1;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_sp2_p0 (
address0,
ce0,
q0,
we0,
d0,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input clk;
reg[DataWidth-1:0] q0;
wire[1 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[1 * AddressWidth - 1:0] mem_ra;
wire[1 - 1:0] mem_ce;
denoise_sp2_p0_core #(
.READ_PORT_COUNT( 1 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_ra = {address0};
assign mem_ce = {ce0};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_sp2_p1_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd1;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_sp2_p1 (
address0,
ce0,
q0,
we0,
d0,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input clk;
reg[DataWidth-1:0] q0;
wire[1 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[1 * AddressWidth - 1:0] mem_ra;
wire[1 - 1:0] mem_ce;
denoise_sp2_p1_core #(
.READ_PORT_COUNT( 1 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_ra = {address0};
assign mem_ce = {ce0};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_sp2_p2_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd1;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_sp2_p2 (
address0,
ce0,
q0,
we0,
d0,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input clk;
reg[DataWidth-1:0] q0;
wire[1 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[1 * AddressWidth - 1:0] mem_ra;
wire[1 - 1:0] mem_ce;
denoise_sp2_p2_core #(
.READ_PORT_COUNT( 1 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_ra = {address0};
assign mem_ce = {ce0};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_sp2_p3_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd1;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_sp2_p3 (
address0,
ce0,
q0,
we0,
d0,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input clk;
reg[DataWidth-1:0] q0;
wire[1 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[1 * AddressWidth - 1:0] mem_ra;
wire[1 - 1:0] mem_ce;
denoise_sp2_p3_core #(
.READ_PORT_COUNT( 1 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_ra = {address0};
assign mem_ce = {ce0};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_u0_p0_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd1;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_u0_p0 (
address0,
ce0,
q0,
we0,
d0,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input clk;
reg[DataWidth-1:0] q0;
wire[1 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[1 * AddressWidth - 1:0] mem_ra;
wire[1 - 1:0] mem_ce;
denoise_u0_p0_core #(
.READ_PORT_COUNT( 1 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_ra = {address0};
assign mem_ce = {ce0};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_u0_p1_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd1;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_u0_p1 (
address0,
ce0,
q0,
we0,
d0,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input clk;
reg[DataWidth-1:0] q0;
wire[1 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[1 * AddressWidth - 1:0] mem_ra;
wire[1 - 1:0] mem_ce;
denoise_u0_p1_core #(
.READ_PORT_COUNT( 1 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_ra = {address0};
assign mem_ce = {ce0};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_u0_p2_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd1;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_u0_p2 (
address0,
ce0,
q0,
we0,
d0,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input clk;
reg[DataWidth-1:0] q0;
wire[1 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[1 * AddressWidth - 1:0] mem_ra;
wire[1 - 1:0] mem_ce;
denoise_u0_p2_core #(
.READ_PORT_COUNT( 1 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_ra = {address0};
assign mem_ce = {ce0};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_u0_p3_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd2;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or rai_reg[1] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_u0_p3 (
address0,
ce0,
q0,
we0,
d0,
address1,
ce1,
q1,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input[AddressWidth-1:0] address1;
input ce1;
output[DataWidth-1:0] q1;
input clk;
reg[DataWidth-1:0] q0;
reg[DataWidth-1:0] q1;
wire[2 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[DataWidth - 1:0] mem_q1;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[2 * AddressWidth - 1:0] mem_ra;
wire[2 - 1:0] mem_ce;
denoise_u0_p3_core #(
.READ_PORT_COUNT( 2 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[2 * DataWidth - 1 : 1 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_q1 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q1) begin
q1 = mem_q1;
end
assign mem_ra = {address0, address1};
assign mem_ce = {ce0, ce1};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_u1_p0_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd1;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_u1_p0 (
address0,
ce0,
q0,
we0,
d0,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input clk;
reg[DataWidth-1:0] q0;
wire[1 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[1 * AddressWidth - 1:0] mem_ra;
wire[1 - 1:0] mem_ce;
denoise_u1_p0_core #(
.READ_PORT_COUNT( 1 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_ra = {address0};
assign mem_ce = {ce0};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_u1_p1_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd1;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_u1_p1 (
address0,
ce0,
q0,
we0,
d0,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input clk;
reg[DataWidth-1:0] q0;
wire[1 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[1 * AddressWidth - 1:0] mem_ra;
wire[1 - 1:0] mem_ce;
denoise_u1_p1_core #(
.READ_PORT_COUNT( 1 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_ra = {address0};
assign mem_ce = {ce0};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_u1_p2_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd1;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_u1_p2 (
address0,
ce0,
q0,
we0,
d0,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input clk;
reg[DataWidth-1:0] q0;
wire[1 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[1 * AddressWidth - 1:0] mem_ra;
wire[1 - 1:0] mem_ce;
denoise_u1_p2_core #(
.READ_PORT_COUNT( 1 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_ra = {address0};
assign mem_ce = {ce0};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_u1_p3_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd2;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or rai_reg[1] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_u1_p3 (
address0,
ce0,
q0,
we0,
d0,
address1,
ce1,
q1,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input[AddressWidth-1:0] address1;
input ce1;
output[DataWidth-1:0] q1;
input clk;
reg[DataWidth-1:0] q0;
reg[DataWidth-1:0] q1;
wire[2 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[DataWidth - 1:0] mem_q1;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[2 * AddressWidth - 1:0] mem_ra;
wire[2 - 1:0] mem_ce;
denoise_u1_p3_core #(
.READ_PORT_COUNT( 2 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[2 * DataWidth - 1 : 1 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_q1 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q1) begin
q1 = mem_q1;
end
assign mem_ra = {address0, address1};
assign mem_ce = {ce0, ce1};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_u2_p0_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd1;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_u2_p0 (
address0,
ce0,
q0,
we0,
d0,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input clk;
reg[DataWidth-1:0] q0;
wire[1 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[1 * AddressWidth - 1:0] mem_ra;
wire[1 - 1:0] mem_ce;
denoise_u2_p0_core #(
.READ_PORT_COUNT( 1 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_ra = {address0};
assign mem_ce = {ce0};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_u2_p1_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd1;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_u2_p1 (
address0,
ce0,
q0,
we0,
d0,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input clk;
reg[DataWidth-1:0] q0;
wire[1 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[1 * AddressWidth - 1:0] mem_ra;
wire[1 - 1:0] mem_ce;
denoise_u2_p1_core #(
.READ_PORT_COUNT( 1 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_ra = {address0};
assign mem_ce = {ce0};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_u2_p2_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd1;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_u2_p2 (
address0,
ce0,
q0,
we0,
d0,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input clk;
reg[DataWidth-1:0] q0;
wire[1 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[1 * AddressWidth - 1:0] mem_ra;
wire[1 - 1:0] mem_ce;
denoise_u2_p2_core #(
.READ_PORT_COUNT( 1 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_ra = {address0};
assign mem_ce = {ce0};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_u2_p3_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd2;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or rai_reg[1] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_u2_p3 (
address0,
ce0,
q0,
we0,
d0,
address1,
ce1,
q1,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input[AddressWidth-1:0] address1;
input ce1;
output[DataWidth-1:0] q1;
input clk;
reg[DataWidth-1:0] q0;
reg[DataWidth-1:0] q1;
wire[2 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[DataWidth - 1:0] mem_q1;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[2 * AddressWidth - 1:0] mem_ra;
wire[2 - 1:0] mem_ce;
denoise_u2_p3_core #(
.READ_PORT_COUNT( 2 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[2 * DataWidth - 1 : 1 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_q1 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q1) begin
q1 = mem_q1;
end
assign mem_ra = {address0, address1};
assign mem_ce = {ce0, ce1};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_u3_p0_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd1;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_u3_p0 (
address0,
ce0,
q0,
we0,
d0,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input clk;
reg[DataWidth-1:0] q0;
wire[1 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[1 * AddressWidth - 1:0] mem_ra;
wire[1 - 1:0] mem_ce;
denoise_u3_p0_core #(
.READ_PORT_COUNT( 1 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_ra = {address0};
assign mem_ce = {ce0};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_u3_p1_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd1;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_u3_p1 (
address0,
ce0,
q0,
we0,
d0,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input clk;
reg[DataWidth-1:0] q0;
wire[1 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[1 * AddressWidth - 1:0] mem_ra;
wire[1 - 1:0] mem_ce;
denoise_u3_p1_core #(
.READ_PORT_COUNT( 1 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_ra = {address0};
assign mem_ce = {ce0};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_u3_p2_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd1;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_u3_p2 (
address0,
ce0,
q0,
we0,
d0,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input clk;
reg[DataWidth-1:0] q0;
wire[1 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[1 * AddressWidth - 1:0] mem_ra;
wire[1 - 1:0] mem_ce;
denoise_u3_p2_core #(
.READ_PORT_COUNT( 1 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_ra = {address0};
assign mem_ce = {ce0};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_u3_p3_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd2;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or rai_reg[1] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_u3_p3 (
address0,
ce0,
q0,
we0,
d0,
address1,
ce1,
q1,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input[AddressWidth-1:0] address1;
input ce1;
output[DataWidth-1:0] q1;
input clk;
reg[DataWidth-1:0] q0;
reg[DataWidth-1:0] q1;
wire[2 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[DataWidth - 1:0] mem_q1;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[2 * AddressWidth - 1:0] mem_ra;
wire[2 - 1:0] mem_ce;
denoise_u3_p3_core #(
.READ_PORT_COUNT( 2 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[2 * DataWidth - 1 : 1 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_q1 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q1) begin
q1 = mem_q1;
end
assign mem_ra = {address0, address1};
assign mem_ce = {ce0, ce1};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_u4_p0_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd1;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_u4_p0 (
address0,
ce0,
q0,
we0,
d0,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input clk;
reg[DataWidth-1:0] q0;
wire[1 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[1 * AddressWidth - 1:0] mem_ra;
wire[1 - 1:0] mem_ce;
denoise_u4_p0_core #(
.READ_PORT_COUNT( 1 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_ra = {address0};
assign mem_ce = {ce0};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_u4_p1_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd1;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_u4_p1 (
address0,
ce0,
q0,
we0,
d0,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input clk;
reg[DataWidth-1:0] q0;
wire[1 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[1 * AddressWidth - 1:0] mem_ra;
wire[1 - 1:0] mem_ce;
denoise_u4_p1_core #(
.READ_PORT_COUNT( 1 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_ra = {address0};
assign mem_ce = {ce0};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_u4_p2_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd1;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_u4_p2 (
address0,
ce0,
q0,
we0,
d0,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input clk;
reg[DataWidth-1:0] q0;
wire[1 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[1 * AddressWidth - 1:0] mem_ra;
wire[1 - 1:0] mem_ce;
denoise_u4_p2_core #(
.READ_PORT_COUNT( 1 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_ra = {address0};
assign mem_ce = {ce0};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_u4_p3_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd2;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or rai_reg[1] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_u4_p3 (
address0,
ce0,
q0,
we0,
d0,
address1,
ce1,
q1,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input[AddressWidth-1:0] address1;
input ce1;
output[DataWidth-1:0] q1;
input clk;
reg[DataWidth-1:0] q0;
reg[DataWidth-1:0] q1;
wire[2 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[DataWidth - 1:0] mem_q1;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[2 * AddressWidth - 1:0] mem_ra;
wire[2 - 1:0] mem_ce;
denoise_u4_p3_core #(
.READ_PORT_COUNT( 2 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[2 * DataWidth - 1 : 1 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_q1 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q1) begin
q1 = mem_q1;
end
assign mem_ra = {address0, address1};
assign mem_ce = {ce0, ce1};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_u5_p0_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd1;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_u5_p0 (
address0,
ce0,
q0,
we0,
d0,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input clk;
reg[DataWidth-1:0] q0;
wire[1 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[1 * AddressWidth - 1:0] mem_ra;
wire[1 - 1:0] mem_ce;
denoise_u5_p0_core #(
.READ_PORT_COUNT( 1 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_ra = {address0};
assign mem_ce = {ce0};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_u5_p1_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd1;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_u5_p1 (
address0,
ce0,
q0,
we0,
d0,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input clk;
reg[DataWidth-1:0] q0;
wire[1 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[1 * AddressWidth - 1:0] mem_ra;
wire[1 - 1:0] mem_ce;
denoise_u5_p1_core #(
.READ_PORT_COUNT( 1 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_ra = {address0};
assign mem_ce = {ce0};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_u5_p2_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd1;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_u5_p2 (
address0,
ce0,
q0,
we0,
d0,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input clk;
reg[DataWidth-1:0] q0;
wire[1 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[1 * AddressWidth - 1:0] mem_ra;
wire[1 - 1:0] mem_ce;
denoise_u5_p2_core #(
.READ_PORT_COUNT( 1 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_ra = {address0};
assign mem_ce = {ce0};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_u5_p3_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd2;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or rai_reg[1] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_u5_p3 (
address0,
ce0,
q0,
we0,
d0,
address1,
ce1,
q1,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input[AddressWidth-1:0] address1;
input ce1;
output[DataWidth-1:0] q1;
input clk;
reg[DataWidth-1:0] q0;
reg[DataWidth-1:0] q1;
wire[2 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[DataWidth - 1:0] mem_q1;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[2 * AddressWidth - 1:0] mem_ra;
wire[2 - 1:0] mem_ce;
denoise_u5_p3_core #(
.READ_PORT_COUNT( 2 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[2 * DataWidth - 1 : 1 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_q1 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q1) begin
q1 = mem_q1;
end
assign mem_ra = {address0, address1};
assign mem_ce = {ce0, ce1};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_u6_p0_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd1;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_u6_p0 (
address0,
ce0,
q0,
we0,
d0,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input clk;
reg[DataWidth-1:0] q0;
wire[1 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[1 * AddressWidth - 1:0] mem_ra;
wire[1 - 1:0] mem_ce;
denoise_u6_p0_core #(
.READ_PORT_COUNT( 1 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_ra = {address0};
assign mem_ce = {ce0};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_u6_p1_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd1;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_u6_p1 (
address0,
ce0,
q0,
we0,
d0,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input clk;
reg[DataWidth-1:0] q0;
wire[1 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[1 * AddressWidth - 1:0] mem_ra;
wire[1 - 1:0] mem_ce;
denoise_u6_p1_core #(
.READ_PORT_COUNT( 1 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_ra = {address0};
assign mem_ce = {ce0};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_u6_p2_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd1;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_u6_p2 (
address0,
ce0,
q0,
we0,
d0,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input clk;
reg[DataWidth-1:0] q0;
wire[1 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[1 * AddressWidth - 1:0] mem_ra;
wire[1 - 1:0] mem_ce;
denoise_u6_p2_core #(
.READ_PORT_COUNT( 1 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_ra = {address0};
assign mem_ce = {ce0};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_u6_p3_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd2;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or rai_reg[1] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_u6_p3 (
address0,
ce0,
q0,
we0,
d0,
address1,
ce1,
q1,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input[AddressWidth-1:0] address1;
input ce1;
output[DataWidth-1:0] q1;
input clk;
reg[DataWidth-1:0] q0;
reg[DataWidth-1:0] q1;
wire[2 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[DataWidth - 1:0] mem_q1;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[2 * AddressWidth - 1:0] mem_ra;
wire[2 - 1:0] mem_ce;
denoise_u6_p3_core #(
.READ_PORT_COUNT( 2 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[2 * DataWidth - 1 : 1 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_q1 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q1) begin
q1 = mem_q1;
end
assign mem_ra = {address0, address1};
assign mem_ce = {ce0, ce1};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_ug0_p0_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd2;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or rai_reg[1] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_ug0_p0 (
address0,
ce0,
q0,
we0,
d0,
address1,
ce1,
q1,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input[AddressWidth-1:0] address1;
input ce1;
output[DataWidth-1:0] q1;
input clk;
reg[DataWidth-1:0] q0;
reg[DataWidth-1:0] q1;
wire[2 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[DataWidth - 1:0] mem_q1;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[2 * AddressWidth - 1:0] mem_ra;
wire[2 - 1:0] mem_ce;
denoise_ug0_p0_core #(
.READ_PORT_COUNT( 2 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[2 * DataWidth - 1 : 1 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_q1 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q1) begin
q1 = mem_q1;
end
assign mem_ra = {address0, address1};
assign mem_ce = {ce0, ce1};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_ug0_p1_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd1;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_ug0_p1 (
address0,
ce0,
q0,
we0,
d0,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input clk;
reg[DataWidth-1:0] q0;
wire[1 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[1 * AddressWidth - 1:0] mem_ra;
wire[1 - 1:0] mem_ce;
denoise_ug0_p1_core #(
.READ_PORT_COUNT( 1 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_ra = {address0};
assign mem_ce = {ce0};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_ug0_p2_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd1;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_ug0_p2 (
address0,
ce0,
q0,
we0,
d0,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input clk;
reg[DataWidth-1:0] q0;
wire[1 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[1 * AddressWidth - 1:0] mem_ra;
wire[1 - 1:0] mem_ce;
denoise_ug0_p2_core #(
.READ_PORT_COUNT( 1 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_ra = {address0};
assign mem_ce = {ce0};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_ug0_p3_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd2;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or rai_reg[1] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_ug0_p3 (
address0,
ce0,
q0,
we0,
d0,
address1,
ce1,
q1,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input[AddressWidth-1:0] address1;
input ce1;
output[DataWidth-1:0] q1;
input clk;
reg[DataWidth-1:0] q0;
reg[DataWidth-1:0] q1;
wire[2 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[DataWidth - 1:0] mem_q1;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[2 * AddressWidth - 1:0] mem_ra;
wire[2 - 1:0] mem_ce;
denoise_ug0_p3_core #(
.READ_PORT_COUNT( 2 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[2 * DataWidth - 1 : 1 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_q1 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q1) begin
q1 = mem_q1;
end
assign mem_ra = {address0, address1};
assign mem_ce = {ce0, ce1};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_ug1_p0_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd2;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or rai_reg[1] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_ug1_p0 (
address0,
ce0,
q0,
we0,
d0,
address1,
ce1,
q1,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input[AddressWidth-1:0] address1;
input ce1;
output[DataWidth-1:0] q1;
input clk;
reg[DataWidth-1:0] q0;
reg[DataWidth-1:0] q1;
wire[2 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[DataWidth - 1:0] mem_q1;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[2 * AddressWidth - 1:0] mem_ra;
wire[2 - 1:0] mem_ce;
denoise_ug1_p0_core #(
.READ_PORT_COUNT( 2 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[2 * DataWidth - 1 : 1 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_q1 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q1) begin
q1 = mem_q1;
end
assign mem_ra = {address0, address1};
assign mem_ce = {ce0, ce1};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_ug1_p1_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd1;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_ug1_p1 (
address0,
ce0,
q0,
we0,
d0,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input clk;
reg[DataWidth-1:0] q0;
wire[1 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[1 * AddressWidth - 1:0] mem_ra;
wire[1 - 1:0] mem_ce;
denoise_ug1_p1_core #(
.READ_PORT_COUNT( 1 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_ra = {address0};
assign mem_ce = {ce0};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_ug1_p2_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd1;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_ug1_p2 (
address0,
ce0,
q0,
we0,
d0,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input clk;
reg[DataWidth-1:0] q0;
wire[1 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[1 * AddressWidth - 1:0] mem_ra;
wire[1 - 1:0] mem_ce;
denoise_ug1_p2_core #(
.READ_PORT_COUNT( 1 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_ra = {address0};
assign mem_ce = {ce0};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_ug1_p3_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd2;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or rai_reg[1] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_ug1_p3 (
address0,
ce0,
q0,
we0,
d0,
address1,
ce1,
q1,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input[AddressWidth-1:0] address1;
input ce1;
output[DataWidth-1:0] q1;
input clk;
reg[DataWidth-1:0] q0;
reg[DataWidth-1:0] q1;
wire[2 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[DataWidth - 1:0] mem_q1;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[2 * AddressWidth - 1:0] mem_ra;
wire[2 - 1:0] mem_ce;
denoise_ug1_p3_core #(
.READ_PORT_COUNT( 2 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[2 * DataWidth - 1 : 1 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_q1 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q1) begin
q1 = mem_q1;
end
assign mem_ra = {address0, address1};
assign mem_ce = {ce0, ce1};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_ug2_p0_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd2;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or rai_reg[1] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_ug2_p0 (
address0,
ce0,
q0,
we0,
d0,
address1,
ce1,
q1,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input[AddressWidth-1:0] address1;
input ce1;
output[DataWidth-1:0] q1;
input clk;
reg[DataWidth-1:0] q0;
reg[DataWidth-1:0] q1;
wire[2 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[DataWidth - 1:0] mem_q1;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[2 * AddressWidth - 1:0] mem_ra;
wire[2 - 1:0] mem_ce;
denoise_ug2_p0_core #(
.READ_PORT_COUNT( 2 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[2 * DataWidth - 1 : 1 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_q1 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q1) begin
q1 = mem_q1;
end
assign mem_ra = {address0, address1};
assign mem_ce = {ce0, ce1};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_ug2_p1_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd1;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_ug2_p1 (
address0,
ce0,
q0,
we0,
d0,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input clk;
reg[DataWidth-1:0] q0;
wire[1 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[1 * AddressWidth - 1:0] mem_ra;
wire[1 - 1:0] mem_ce;
denoise_ug2_p1_core #(
.READ_PORT_COUNT( 1 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_ra = {address0};
assign mem_ce = {ce0};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_ug2_p2_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd1;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_ug2_p2 (
address0,
ce0,
q0,
we0,
d0,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input clk;
reg[DataWidth-1:0] q0;
wire[1 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[1 * AddressWidth - 1:0] mem_ra;
wire[1 - 1:0] mem_ce;
denoise_ug2_p2_core #(
.READ_PORT_COUNT( 1 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_ra = {address0};
assign mem_ce = {ce0};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_ug2_p3_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd2;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or rai_reg[1] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_ug2_p3 (
address0,
ce0,
q0,
we0,
d0,
address1,
ce1,
q1,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input[AddressWidth-1:0] address1;
input ce1;
output[DataWidth-1:0] q1;
input clk;
reg[DataWidth-1:0] q0;
reg[DataWidth-1:0] q1;
wire[2 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[DataWidth - 1:0] mem_q1;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[2 * AddressWidth - 1:0] mem_ra;
wire[2 - 1:0] mem_ce;
denoise_ug2_p3_core #(
.READ_PORT_COUNT( 2 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[2 * DataWidth - 1 : 1 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_q1 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q1) begin
q1 = mem_q1;
end
assign mem_ra = {address0, address1};
assign mem_ce = {ce0, ce1};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_ug3_p0_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd2;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or rai_reg[1] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_ug3_p0 (
address0,
ce0,
q0,
we0,
d0,
address1,
ce1,
q1,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input[AddressWidth-1:0] address1;
input ce1;
output[DataWidth-1:0] q1;
input clk;
reg[DataWidth-1:0] q0;
reg[DataWidth-1:0] q1;
wire[2 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[DataWidth - 1:0] mem_q1;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[2 * AddressWidth - 1:0] mem_ra;
wire[2 - 1:0] mem_ce;
denoise_ug3_p0_core #(
.READ_PORT_COUNT( 2 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[2 * DataWidth - 1 : 1 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_q1 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q1) begin
q1 = mem_q1;
end
assign mem_ra = {address0, address1};
assign mem_ce = {ce0, ce1};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_ug3_p1_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd1;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_ug3_p1 (
address0,
ce0,
q0,
we0,
d0,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input clk;
reg[DataWidth-1:0] q0;
wire[1 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[1 * AddressWidth - 1:0] mem_ra;
wire[1 - 1:0] mem_ce;
denoise_ug3_p1_core #(
.READ_PORT_COUNT( 1 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_ra = {address0};
assign mem_ce = {ce0};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_ug3_p2_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd1;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_ug3_p2 (
address0,
ce0,
q0,
we0,
d0,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input clk;
reg[DataWidth-1:0] q0;
wire[1 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[1 * AddressWidth - 1:0] mem_ra;
wire[1 - 1:0] mem_ce;
denoise_ug3_p2_core #(
.READ_PORT_COUNT( 1 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_ra = {address0};
assign mem_ce = {ce0};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_ug3_p3_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd2;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or rai_reg[1] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_ug3_p3 (
address0,
ce0,
q0,
we0,
d0,
address1,
ce1,
q1,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input[AddressWidth-1:0] address1;
input ce1;
output[DataWidth-1:0] q1;
input clk;
reg[DataWidth-1:0] q0;
reg[DataWidth-1:0] q1;
wire[2 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[DataWidth - 1:0] mem_q1;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[2 * AddressWidth - 1:0] mem_ra;
wire[2 - 1:0] mem_ce;
denoise_ug3_p3_core #(
.READ_PORT_COUNT( 2 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[2 * DataWidth - 1 : 1 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_q1 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q1) begin
q1 = mem_q1;
end
assign mem_ra = {address0, address1};
assign mem_ce = {ce0, ce1};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// RTL generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ===========================================================
`timescale 1 ns / 1 ps
module fFetch_array (
ap_clk,
ap_rst,
ap_start,
ap_done,
ap_idle,
bus_r_req_din,
bus_r_req_full_n,
bus_r_req_write,
bus_r_rsp_dout,
bus_r_rsp_empty_n,
bus_r_rsp_read,
bus_r_address,
bus_r_datain,
bus_r_dataout,
bus_r_size,
data_p0_address0,
data_p0_ce0,
data_p0_we0,
data_p0_d0,
data_p1_address0,
data_p1_ce0,
data_p1_we0,
data_p1_d0,
data_p2_address0,
data_p2_ce0,
data_p2_we0,
data_p2_d0,
data_p3_address0,
data_p3_ce0,
data_p3_we0,
data_p3_d0
);
input ap_clk;
input ap_rst;
input ap_start;
output ap_done;
output ap_idle;
output bus_r_req_din;
input bus_r_req_full_n;
output bus_r_req_write;
input bus_r_rsp_dout;
input bus_r_rsp_empty_n;
output bus_r_rsp_read;
output [31:0] bus_r_address;
input [127:0] bus_r_datain;
output [127:0] bus_r_dataout;
output [31:0] bus_r_size;
output [7:0] data_p0_address0;
output data_p0_ce0;
output data_p0_we0;
output [31:0] data_p0_d0;
output [7:0] data_p1_address0;
output data_p1_ce0;
output data_p1_we0;
output [31:0] data_p1_d0;
output [7:0] data_p2_address0;
output data_p2_ce0;
output data_p2_we0;
output [31:0] data_p2_d0;
output [7:0] data_p3_address0;
output data_p3_ce0;
output data_p3_we0;
output [31:0] data_p3_d0;
reg ap_done;
reg ap_idle;
reg bus_r_req_write;
reg bus_r_rsp_read;
reg data_p0_ce0;
reg data_p0_we0;
reg data_p1_ce0;
reg data_p1_we0;
reg data_p2_ce0;
reg data_p2_we0;
reg data_p3_ce0;
reg data_p3_we0;
reg [1:0] ap_CS_fsm;
reg [31:0] fIndex;
reg [7:0] indvar_flatten_reg_128;
reg [5:0] i_reg_139;
reg [2:0] indvar_reg_150;
wire [0:0] exitcond_fu_162_p2;
reg [0:0] exitcond_reg_319;
reg ap_reg_ppiten_pp0_it0;
reg ap_sig_bdd_76;
reg ap_sig_bdd_81;
reg ap_reg_ppiten_pp0_it1;
reg ap_reg_ppiten_pp0_it2;
reg [0:0] ap_reg_ppstg_exitcond_reg_319_pp0_it1;
reg [7:0] indvar_next_reg_323;
wire [5:0] i_mid_fu_194_p3;
reg [5:0] i_mid_reg_328;
reg [7:0] data_p0_addr_reg_338;
reg [7:0] ap_reg_ppstg_data_p0_addr_reg_338_pp0_it1;
reg [2:0] indvar_next1_reg_343;
reg [31:0] Result1_reg_348;
reg [31:0] Result3_reg_353;
reg [31:0] Result2_reg_358;
reg [31:0] Result_reg_363;
reg [7:0] indvar_flatten_phi_fu_132_p4;
reg [5:0] i_phi_fu_143_p4;
reg [2:0] indvar_phi_fu_154_p4;
wire [31:0] data_p0_addr1_cast_fu_300_p1;
wire [63:0] tmp_fu_212_p1;
wire [7:0] exitcond_fu_162_p1;
wire [2:0] exitcond1_fu_180_p1;
wire [0:0] exitcond1_fu_180_p2;
wire [5:0] indvar_next6_dup_fu_174_p2;
wire [2:0] indvar_mid_fu_186_p3;
wire [3:0] indvar_cast_fu_202_p1;
wire [3:0] j_fu_206_p2;
wire [7:0] tmp4_trn_cast_fu_234_p1;
wire [7:0] p_shl_fu_238_p2;
wire [7:0] data_p0_addr_cast_fu_244_p2;
wire [7:0] tmp8_trn_cast_fu_230_p1;
reg [1:0] ap_NS_fsm;
parameter ap_const_logic_1 = 1'b1;
parameter ap_const_logic_0 = 1'b0;
parameter ap_ST_st0_fsm_0 = 2'b00;
parameter ap_ST_st1_fsm_1 = 2'b01;
parameter ap_ST_pp0_stg0_fsm_2 = 2'b10;
parameter ap_ST_st5_fsm_3 = 2'b11;
parameter ap_const_lv32_0 = 32'b00000000000000000000000000000000;
parameter ap_const_lv1_0 = 1'b0;
parameter ap_const_lv8_0 = 8'b00000000;
parameter ap_const_lv6_0 = 6'b000000;
parameter ap_const_lv3_0 = 3'b000;
parameter ap_const_lv8_F0 = 8'b11110000;
parameter ap_const_lv8_1 = 8'b00000001;
parameter ap_const_lv6_1 = 6'b000001;
parameter ap_const_lv3_4 = 3'b100;
parameter ap_const_lv4_2 = 4'b0010;
parameter ap_const_lv32_1 = 32'b00000000000000000000000000000001;
parameter ap_const_lv8_4 = 8'b00000100;
parameter ap_const_lv3_1 = 3'b001;
parameter ap_const_lv32_20 = 32'b00000000000000000000000000100000;
parameter ap_const_lv32_3F = 32'b00000000000000000000000000111111;
parameter ap_const_lv32_40 = 32'b00000000000000000000000001000000;
parameter ap_const_lv32_5F = 32'b00000000000000000000000001011111;
parameter ap_const_lv32_60 = 32'b00000000000000000000000001100000;
parameter ap_const_lv32_7F = 32'b00000000000000000000000001111111;
parameter ap_const_lv128_lc_1 = 128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_true = 1'b1;
/// ap_CS_fsm assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_CS_fsm
if (ap_rst == 1'b1) begin
ap_CS_fsm <= ap_ST_st0_fsm_0;
end else begin
ap_CS_fsm <= ap_NS_fsm;
end
end
/// ap_reg_ppiten_pp0_it0 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it0
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it0 <= ap_const_logic_0;
end else begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ap_sig_bdd_76) | (ap_sig_bdd_81 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))) & ~(exitcond_fu_162_p2 == ap_const_lv1_0))) begin
ap_reg_ppiten_pp0_it0 <= ap_const_logic_0;
end else if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it0 <= ap_const_logic_1;
end
end
end
/// ap_reg_ppiten_pp0_it1 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it1
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it1 <= ap_const_logic_0;
end else begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (exitcond_fu_162_p2 == ap_const_lv1_0) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ap_sig_bdd_76) | (ap_sig_bdd_81 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))))) begin
ap_reg_ppiten_pp0_it1 <= ap_const_logic_1;
end else if (((ap_ST_st1_fsm_1 == ap_CS_fsm) | ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ap_sig_bdd_76) | (ap_sig_bdd_81 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))) & ~(exitcond_fu_162_p2 == ap_const_lv1_0)))) begin
ap_reg_ppiten_pp0_it1 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp0_it2 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it2
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it2 <= ap_const_logic_0;
end else begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ap_sig_bdd_76) | (ap_sig_bdd_81 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))))) begin
ap_reg_ppiten_pp0_it2 <= ap_reg_ppiten_pp0_it1;
end else if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it2 <= ap_const_logic_0;
end
end
end
/// fIndex assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_fIndex
if (ap_rst == 1'b1) begin
fIndex <= ap_const_lv32_0;
end else begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_fu_162_p2 == ap_const_lv1_0) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ap_sig_bdd_76) | (ap_sig_bdd_81 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))))) begin
fIndex <= (fIndex + ap_const_lv32_1);
end
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (exitcond_reg_319 == ap_const_lv1_0) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ap_sig_bdd_76) | (ap_sig_bdd_81 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))))) begin
Result1_reg_348 <= bus_r_datain[31:0];
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (exitcond_reg_319 == ap_const_lv1_0) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ap_sig_bdd_76) | (ap_sig_bdd_81 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))))) begin
Result2_reg_358 <= {{bus_r_datain[ap_const_lv32_5F : ap_const_lv32_40]}};
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (exitcond_reg_319 == ap_const_lv1_0) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ap_sig_bdd_76) | (ap_sig_bdd_81 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))))) begin
Result3_reg_353 <= {{bus_r_datain[ap_const_lv32_3F : ap_const_lv32_20]}};
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (exitcond_reg_319 == ap_const_lv1_0) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ap_sig_bdd_76) | (ap_sig_bdd_81 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))))) begin
Result_reg_363 <= {{bus_r_datain[ap_const_lv32_7F : ap_const_lv32_60]}};
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ap_sig_bdd_76) | (ap_sig_bdd_81 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))))) begin
ap_reg_ppstg_data_p0_addr_reg_338_pp0_it1 <= data_p0_addr_reg_338;
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ap_sig_bdd_76) | (ap_sig_bdd_81 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))))) begin
ap_reg_ppstg_exitcond_reg_319_pp0_it1 <= exitcond_reg_319;
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_fu_162_p2 == ap_const_lv1_0) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ap_sig_bdd_76) | (ap_sig_bdd_81 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))))) begin
data_p0_addr_reg_338 <= (data_p0_addr_cast_fu_244_p2 + tmp8_trn_cast_fu_230_p1);
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ap_sig_bdd_76) | (ap_sig_bdd_81 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))))) begin
exitcond_reg_319 <= (indvar_flatten_phi_fu_132_p4 == exitcond_fu_162_p1? 1'b1: 1'b0);
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_fu_162_p2 == ap_const_lv1_0) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ap_sig_bdd_76) | (ap_sig_bdd_81 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))))) begin
if (exitcond1_fu_180_p2) begin
i_mid_reg_328 <= indvar_next6_dup_fu_174_p2;
end else begin
i_mid_reg_328 <= i_phi_fu_143_p4;
end
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (exitcond_reg_319 == ap_const_lv1_0) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ap_sig_bdd_76) | (ap_sig_bdd_81 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))))) begin
i_reg_139 <= i_mid_reg_328;
end else if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
i_reg_139 <= ap_const_lv6_0;
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (exitcond_reg_319 == ap_const_lv1_0) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ap_sig_bdd_76) | (ap_sig_bdd_81 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))))) begin
indvar_flatten_reg_128 <= indvar_next_reg_323;
end else if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
indvar_flatten_reg_128 <= ap_const_lv8_0;
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_fu_162_p2 == ap_const_lv1_0) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ap_sig_bdd_76) | (ap_sig_bdd_81 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))))) begin
indvar_next1_reg_343 <= (indvar_mid_fu_186_p3 + ap_const_lv3_1);
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ap_sig_bdd_76) | (ap_sig_bdd_81 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))))) begin
indvar_next_reg_323 <= (indvar_flatten_phi_fu_132_p4 + ap_const_lv8_1);
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (exitcond_reg_319 == ap_const_lv1_0) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ap_sig_bdd_76) | (ap_sig_bdd_81 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))))) begin
indvar_reg_150 <= indvar_next1_reg_343;
end else if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
indvar_reg_150 <= ap_const_lv3_0;
end
end
/// ap_NS_fsm assign process. ///
always @ (ap_start or ap_CS_fsm or exitcond_fu_162_p2 or ap_reg_ppiten_pp0_it0 or ap_sig_bdd_76 or ap_sig_bdd_81 or ap_reg_ppiten_pp0_it1 or ap_reg_ppiten_pp0_it2)
begin
if ((((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it2) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ap_sig_bdd_76) | (ap_sig_bdd_81 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))) & ~(ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ap_sig_bdd_76) | (ap_sig_bdd_81 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))) & ~(exitcond_fu_162_p2 == ap_const_lv1_0) & ~(ap_const_logic_1 == ap_reg_ppiten_pp0_it1)))) begin
ap_NS_fsm = ap_ST_st5_fsm_3;
end else if ((~(ap_const_logic_1 == ap_start) & (ap_ST_st5_fsm_3 == ap_CS_fsm))) begin
ap_NS_fsm = ap_ST_st0_fsm_0;
end else if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_pp0_stg0_fsm_2;
end else if ((((ap_ST_st0_fsm_0 == ap_CS_fsm) & (ap_const_logic_1 == ap_start)) | ((ap_const_logic_1 == ap_start) & (ap_ST_st5_fsm_3 == ap_CS_fsm)))) begin
ap_NS_fsm = ap_ST_st1_fsm_1;
end else begin
ap_NS_fsm = ap_CS_fsm;
end
end
/// ap_done assign process. ///
always @ (ap_CS_fsm)
begin
if (((ap_ST_st0_fsm_0 == ap_CS_fsm) | (ap_ST_st5_fsm_3 == ap_CS_fsm))) begin
ap_done = ap_const_logic_1;
end else begin
ap_done = ap_const_logic_0;
end
end
/// ap_idle assign process. ///
always @ (ap_CS_fsm)
begin
if ((ap_ST_st0_fsm_0 == ap_CS_fsm)) begin
ap_idle = ap_const_logic_1;
end else begin
ap_idle = ap_const_logic_0;
end
end
/// bus_r_req_write assign process. ///
always @ (ap_CS_fsm or exitcond_fu_162_p2 or ap_reg_ppiten_pp0_it0 or ap_sig_bdd_76 or ap_sig_bdd_81 or ap_reg_ppiten_pp0_it1)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_fu_162_p2 == ap_const_lv1_0) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ap_sig_bdd_76) | (ap_sig_bdd_81 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))))) begin
bus_r_req_write = ap_const_logic_1;
end else begin
bus_r_req_write = ap_const_logic_0;
end
end
/// bus_r_rsp_read assign process. ///
always @ (ap_CS_fsm or exitcond_reg_319 or ap_reg_ppiten_pp0_it0 or ap_sig_bdd_76 or ap_sig_bdd_81 or ap_reg_ppiten_pp0_it1)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (exitcond_reg_319 == ap_const_lv1_0) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ap_sig_bdd_76) | (ap_sig_bdd_81 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))))) begin
bus_r_rsp_read = ap_const_logic_1;
end else begin
bus_r_rsp_read = ap_const_logic_0;
end
end
/// data_p0_ce0 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp0_it0 or ap_sig_bdd_76 or ap_sig_bdd_81 or ap_reg_ppiten_pp0_it1 or ap_reg_ppiten_pp0_it2 or ap_reg_ppstg_exitcond_reg_319_pp0_it1)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it2) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ap_sig_bdd_76) | (ap_sig_bdd_81 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_319_pp0_it1))) begin
data_p0_ce0 = ap_const_logic_1;
end else begin
data_p0_ce0 = ap_const_logic_0;
end
end
/// data_p0_we0 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp0_it0 or ap_sig_bdd_76 or ap_sig_bdd_81 or ap_reg_ppiten_pp0_it1 or ap_reg_ppiten_pp0_it2 or ap_reg_ppstg_exitcond_reg_319_pp0_it1)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it2) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ap_sig_bdd_76) | (ap_sig_bdd_81 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_319_pp0_it1))) begin
data_p0_we0 = ap_const_logic_1;
end else begin
data_p0_we0 = ap_const_logic_0;
end
end
/// data_p1_ce0 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp0_it0 or ap_sig_bdd_76 or ap_sig_bdd_81 or ap_reg_ppiten_pp0_it1 or ap_reg_ppiten_pp0_it2 or ap_reg_ppstg_exitcond_reg_319_pp0_it1)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it2) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ap_sig_bdd_76) | (ap_sig_bdd_81 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_319_pp0_it1))) begin
data_p1_ce0 = ap_const_logic_1;
end else begin
data_p1_ce0 = ap_const_logic_0;
end
end
/// data_p1_we0 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp0_it0 or ap_sig_bdd_76 or ap_sig_bdd_81 or ap_reg_ppiten_pp0_it1 or ap_reg_ppiten_pp0_it2 or ap_reg_ppstg_exitcond_reg_319_pp0_it1)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it2) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ap_sig_bdd_76) | (ap_sig_bdd_81 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_319_pp0_it1))) begin
data_p1_we0 = ap_const_logic_1;
end else begin
data_p1_we0 = ap_const_logic_0;
end
end
/// data_p2_ce0 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp0_it0 or ap_sig_bdd_76 or ap_sig_bdd_81 or ap_reg_ppiten_pp0_it1 or ap_reg_ppiten_pp0_it2 or ap_reg_ppstg_exitcond_reg_319_pp0_it1)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it2) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ap_sig_bdd_76) | (ap_sig_bdd_81 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_319_pp0_it1))) begin
data_p2_ce0 = ap_const_logic_1;
end else begin
data_p2_ce0 = ap_const_logic_0;
end
end
/// data_p2_we0 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp0_it0 or ap_sig_bdd_76 or ap_sig_bdd_81 or ap_reg_ppiten_pp0_it1 or ap_reg_ppiten_pp0_it2 or ap_reg_ppstg_exitcond_reg_319_pp0_it1)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it2) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ap_sig_bdd_76) | (ap_sig_bdd_81 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_319_pp0_it1))) begin
data_p2_we0 = ap_const_logic_1;
end else begin
data_p2_we0 = ap_const_logic_0;
end
end
/// data_p3_ce0 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp0_it0 or ap_sig_bdd_76 or ap_sig_bdd_81 or ap_reg_ppiten_pp0_it1 or ap_reg_ppiten_pp0_it2 or ap_reg_ppstg_exitcond_reg_319_pp0_it1)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it2) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ap_sig_bdd_76) | (ap_sig_bdd_81 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_319_pp0_it1))) begin
data_p3_ce0 = ap_const_logic_1;
end else begin
data_p3_ce0 = ap_const_logic_0;
end
end
/// data_p3_we0 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp0_it0 or ap_sig_bdd_76 or ap_sig_bdd_81 or ap_reg_ppiten_pp0_it1 or ap_reg_ppiten_pp0_it2 or ap_reg_ppstg_exitcond_reg_319_pp0_it1)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it2) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ap_sig_bdd_76) | (ap_sig_bdd_81 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_319_pp0_it1))) begin
data_p3_we0 = ap_const_logic_1;
end else begin
data_p3_we0 = ap_const_logic_0;
end
end
/// i_phi_fu_143_p4 assign process. ///
always @ (ap_CS_fsm or i_reg_139 or exitcond_reg_319 or ap_reg_ppiten_pp0_it1 or i_mid_reg_328)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (exitcond_reg_319 == ap_const_lv1_0) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))) begin
i_phi_fu_143_p4 = i_mid_reg_328;
end else begin
i_phi_fu_143_p4 = i_reg_139;
end
end
/// indvar_flatten_phi_fu_132_p4 assign process. ///
always @ (ap_CS_fsm or indvar_flatten_reg_128 or exitcond_reg_319 or ap_reg_ppiten_pp0_it1 or indvar_next_reg_323)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (exitcond_reg_319 == ap_const_lv1_0) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))) begin
indvar_flatten_phi_fu_132_p4 = indvar_next_reg_323;
end else begin
indvar_flatten_phi_fu_132_p4 = indvar_flatten_reg_128;
end
end
/// indvar_phi_fu_154_p4 assign process. ///
always @ (ap_CS_fsm or indvar_reg_150 or exitcond_reg_319 or ap_reg_ppiten_pp0_it1 or indvar_next1_reg_343)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (exitcond_reg_319 == ap_const_lv1_0) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))) begin
indvar_phi_fu_154_p4 = indvar_next1_reg_343;
end else begin
indvar_phi_fu_154_p4 = indvar_reg_150;
end
end
/// ap_sig_bdd_76 assign process. ///
always @ (bus_r_req_full_n or exitcond_fu_162_p2)
begin
ap_sig_bdd_76 = ((bus_r_req_full_n == ap_const_logic_0) & (exitcond_fu_162_p2 == ap_const_lv1_0));
end
/// ap_sig_bdd_81 assign process. ///
always @ (bus_r_rsp_empty_n or exitcond_reg_319)
begin
ap_sig_bdd_81 = ((bus_r_rsp_empty_n == ap_const_logic_0) & (exitcond_reg_319 == ap_const_lv1_0));
end
assign bus_r_address = tmp_fu_212_p1;
assign bus_r_dataout = ap_const_lv128_lc_1;
assign bus_r_req_din = ap_const_logic_0;
assign bus_r_size = ap_const_lv32_0;
assign data_p0_addr1_cast_fu_300_p1 = {{24{1'b0}}, {ap_reg_ppstg_data_p0_addr_reg_338_pp0_it1}};
assign data_p0_addr_cast_fu_244_p2 = (p_shl_fu_238_p2 - tmp4_trn_cast_fu_234_p1);
assign data_p0_address0 = data_p0_addr1_cast_fu_300_p1;
assign data_p0_d0 = Result1_reg_348;
assign data_p1_address0 = data_p0_addr1_cast_fu_300_p1;
assign data_p1_d0 = Result3_reg_353;
assign data_p2_address0 = data_p0_addr1_cast_fu_300_p1;
assign data_p2_d0 = Result2_reg_358;
assign data_p3_address0 = data_p0_addr1_cast_fu_300_p1;
assign data_p3_d0 = Result_reg_363;
assign exitcond1_fu_180_p1 = ap_const_lv3_4;
assign exitcond1_fu_180_p2 = (indvar_phi_fu_154_p4 == exitcond1_fu_180_p1? 1'b1: 1'b0);
assign exitcond_fu_162_p1 = ap_const_lv8_F0;
assign exitcond_fu_162_p2 = (indvar_flatten_phi_fu_132_p4 == exitcond_fu_162_p1? 1'b1: 1'b0);
assign i_mid_fu_194_p3 = ((exitcond1_fu_180_p2)? indvar_next6_dup_fu_174_p2: i_phi_fu_143_p4);
assign indvar_cast_fu_202_p1 = {{1{1'b0}}, {indvar_mid_fu_186_p3}};
assign indvar_mid_fu_186_p3 = ((exitcond1_fu_180_p2)? ap_const_lv3_0: indvar_phi_fu_154_p4);
assign indvar_next6_dup_fu_174_p2 = (i_phi_fu_143_p4 + ap_const_lv6_1);
assign j_fu_206_p2 = indvar_cast_fu_202_p1 << ap_const_lv4_2;
assign p_shl_fu_238_p2 = tmp4_trn_cast_fu_234_p1 << ap_const_lv8_4;
assign tmp4_trn_cast_fu_234_p1 = {{2{1'b0}}, {i_mid_fu_194_p3}};
assign tmp8_trn_cast_fu_230_p1 = {{4{1'b0}}, {j_fu_206_p2}};
assign tmp_fu_212_p1 = {{32{fIndex[31]}}, {fIndex}};
endmodule //fFetch_array
|
// ==============================================================
// RTL generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ===========================================================
`timescale 1 ns / 1 ps
module uFetch_array (
ap_clk,
ap_rst,
ap_start,
ap_done,
ap_idle,
bus_r_req_din,
bus_r_req_full_n,
bus_r_req_write,
bus_r_rsp_dout,
bus_r_rsp_empty_n,
bus_r_rsp_read,
bus_r_address,
bus_r_datain,
bus_r_dataout,
bus_r_size,
data_p0_address0,
data_p0_ce0,
data_p0_we0,
data_p0_d0,
data_p1_address0,
data_p1_ce0,
data_p1_we0,
data_p1_d0,
data_p2_address0,
data_p2_ce0,
data_p2_we0,
data_p2_d0,
data_p3_address0,
data_p3_ce0,
data_p3_we0,
data_p3_d0
);
input ap_clk;
input ap_rst;
input ap_start;
output ap_done;
output ap_idle;
output bus_r_req_din;
input bus_r_req_full_n;
output bus_r_req_write;
input bus_r_rsp_dout;
input bus_r_rsp_empty_n;
output bus_r_rsp_read;
output [31:0] bus_r_address;
input [127:0] bus_r_datain;
output [127:0] bus_r_dataout;
output [31:0] bus_r_size;
output [7:0] data_p0_address0;
output data_p0_ce0;
output data_p0_we0;
output [31:0] data_p0_d0;
output [7:0] data_p1_address0;
output data_p1_ce0;
output data_p1_we0;
output [31:0] data_p1_d0;
output [7:0] data_p2_address0;
output data_p2_ce0;
output data_p2_we0;
output [31:0] data_p2_d0;
output [7:0] data_p3_address0;
output data_p3_ce0;
output data_p3_we0;
output [31:0] data_p3_d0;
reg ap_done;
reg ap_idle;
reg bus_r_req_write;
reg bus_r_rsp_read;
reg data_p0_ce0;
reg data_p0_we0;
reg data_p1_ce0;
reg data_p1_we0;
reg data_p2_ce0;
reg data_p2_we0;
reg data_p3_ce0;
reg data_p3_we0;
reg [1:0] ap_CS_fsm;
reg [31:0] uIndex;
reg [7:0] indvar_flatten_reg_128;
reg [5:0] i_reg_139;
reg [2:0] indvar_reg_150;
wire [0:0] exitcond_fu_162_p2;
reg [0:0] exitcond_reg_319;
reg ap_reg_ppiten_pp0_it0;
reg ap_sig_bdd_76;
reg ap_sig_bdd_81;
reg ap_reg_ppiten_pp0_it1;
reg ap_reg_ppiten_pp0_it2;
reg [0:0] ap_reg_ppstg_exitcond_reg_319_pp0_it1;
reg [7:0] indvar_next_reg_323;
wire [5:0] i_mid_fu_194_p3;
reg [5:0] i_mid_reg_328;
reg [7:0] data_p0_addr_reg_338;
reg [7:0] ap_reg_ppstg_data_p0_addr_reg_338_pp0_it1;
reg [2:0] indvar_next1_reg_343;
reg [31:0] Result1_reg_348;
reg [31:0] Result3_reg_353;
reg [31:0] Result2_reg_358;
reg [31:0] Result_reg_363;
reg [7:0] indvar_flatten_phi_fu_132_p4;
reg [5:0] i_phi_fu_143_p4;
reg [2:0] indvar_phi_fu_154_p4;
wire [31:0] data_p0_addr1_cast_fu_300_p1;
wire [63:0] tmp_fu_212_p1;
wire [7:0] exitcond_fu_162_p1;
wire [2:0] exitcond1_fu_180_p1;
wire [0:0] exitcond1_fu_180_p2;
wire [5:0] indvar_next6_dup_fu_174_p2;
wire [2:0] indvar_mid_fu_186_p3;
wire [3:0] indvar_cast_fu_202_p1;
wire [3:0] j_fu_206_p2;
wire [7:0] tmp4_trn_cast_fu_234_p1;
wire [7:0] p_shl_fu_238_p2;
wire [7:0] data_p0_addr_cast_fu_244_p2;
wire [7:0] tmp8_trn_cast_fu_230_p1;
reg [1:0] ap_NS_fsm;
parameter ap_const_logic_1 = 1'b1;
parameter ap_const_logic_0 = 1'b0;
parameter ap_ST_st0_fsm_0 = 2'b00;
parameter ap_ST_st1_fsm_1 = 2'b01;
parameter ap_ST_pp0_stg0_fsm_2 = 2'b10;
parameter ap_ST_st5_fsm_3 = 2'b11;
parameter ap_const_lv32_0 = 32'b00000000000000000000000000000000;
parameter ap_const_lv1_0 = 1'b0;
parameter ap_const_lv8_0 = 8'b00000000;
parameter ap_const_lv6_0 = 6'b000000;
parameter ap_const_lv3_0 = 3'b000;
parameter ap_const_lv8_F0 = 8'b11110000;
parameter ap_const_lv8_1 = 8'b00000001;
parameter ap_const_lv6_1 = 6'b000001;
parameter ap_const_lv3_4 = 3'b100;
parameter ap_const_lv4_2 = 4'b0010;
parameter ap_const_lv32_1 = 32'b00000000000000000000000000000001;
parameter ap_const_lv8_4 = 8'b00000100;
parameter ap_const_lv3_1 = 3'b001;
parameter ap_const_lv32_20 = 32'b00000000000000000000000000100000;
parameter ap_const_lv32_3F = 32'b00000000000000000000000000111111;
parameter ap_const_lv32_40 = 32'b00000000000000000000000001000000;
parameter ap_const_lv32_5F = 32'b00000000000000000000000001011111;
parameter ap_const_lv32_60 = 32'b00000000000000000000000001100000;
parameter ap_const_lv32_7F = 32'b00000000000000000000000001111111;
parameter ap_const_lv128_lc_1 = 128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_true = 1'b1;
/// ap_CS_fsm assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_CS_fsm
if (ap_rst == 1'b1) begin
ap_CS_fsm <= ap_ST_st0_fsm_0;
end else begin
ap_CS_fsm <= ap_NS_fsm;
end
end
/// ap_reg_ppiten_pp0_it0 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it0
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it0 <= ap_const_logic_0;
end else begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ap_sig_bdd_76) | (ap_sig_bdd_81 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))) & ~(exitcond_fu_162_p2 == ap_const_lv1_0))) begin
ap_reg_ppiten_pp0_it0 <= ap_const_logic_0;
end else if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it0 <= ap_const_logic_1;
end
end
end
/// ap_reg_ppiten_pp0_it1 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it1
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it1 <= ap_const_logic_0;
end else begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (exitcond_fu_162_p2 == ap_const_lv1_0) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ap_sig_bdd_76) | (ap_sig_bdd_81 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))))) begin
ap_reg_ppiten_pp0_it1 <= ap_const_logic_1;
end else if (((ap_ST_st1_fsm_1 == ap_CS_fsm) | ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ap_sig_bdd_76) | (ap_sig_bdd_81 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))) & ~(exitcond_fu_162_p2 == ap_const_lv1_0)))) begin
ap_reg_ppiten_pp0_it1 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp0_it2 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it2
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it2 <= ap_const_logic_0;
end else begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ap_sig_bdd_76) | (ap_sig_bdd_81 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))))) begin
ap_reg_ppiten_pp0_it2 <= ap_reg_ppiten_pp0_it1;
end else if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it2 <= ap_const_logic_0;
end
end
end
/// uIndex assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_uIndex
if (ap_rst == 1'b1) begin
uIndex <= ap_const_lv32_0;
end else begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_fu_162_p2 == ap_const_lv1_0) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ap_sig_bdd_76) | (ap_sig_bdd_81 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))))) begin
uIndex <= (uIndex + ap_const_lv32_1);
end
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (exitcond_reg_319 == ap_const_lv1_0) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ap_sig_bdd_76) | (ap_sig_bdd_81 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))))) begin
Result1_reg_348 <= bus_r_datain[31:0];
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (exitcond_reg_319 == ap_const_lv1_0) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ap_sig_bdd_76) | (ap_sig_bdd_81 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))))) begin
Result2_reg_358 <= {{bus_r_datain[ap_const_lv32_5F : ap_const_lv32_40]}};
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (exitcond_reg_319 == ap_const_lv1_0) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ap_sig_bdd_76) | (ap_sig_bdd_81 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))))) begin
Result3_reg_353 <= {{bus_r_datain[ap_const_lv32_3F : ap_const_lv32_20]}};
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (exitcond_reg_319 == ap_const_lv1_0) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ap_sig_bdd_76) | (ap_sig_bdd_81 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))))) begin
Result_reg_363 <= {{bus_r_datain[ap_const_lv32_7F : ap_const_lv32_60]}};
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ap_sig_bdd_76) | (ap_sig_bdd_81 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))))) begin
ap_reg_ppstg_data_p0_addr_reg_338_pp0_it1 <= data_p0_addr_reg_338;
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ap_sig_bdd_76) | (ap_sig_bdd_81 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))))) begin
ap_reg_ppstg_exitcond_reg_319_pp0_it1 <= exitcond_reg_319;
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_fu_162_p2 == ap_const_lv1_0) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ap_sig_bdd_76) | (ap_sig_bdd_81 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))))) begin
data_p0_addr_reg_338 <= (data_p0_addr_cast_fu_244_p2 + tmp8_trn_cast_fu_230_p1);
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ap_sig_bdd_76) | (ap_sig_bdd_81 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))))) begin
exitcond_reg_319 <= (indvar_flatten_phi_fu_132_p4 == exitcond_fu_162_p1? 1'b1: 1'b0);
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_fu_162_p2 == ap_const_lv1_0) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ap_sig_bdd_76) | (ap_sig_bdd_81 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))))) begin
if (exitcond1_fu_180_p2) begin
i_mid_reg_328 <= indvar_next6_dup_fu_174_p2;
end else begin
i_mid_reg_328 <= i_phi_fu_143_p4;
end
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (exitcond_reg_319 == ap_const_lv1_0) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ap_sig_bdd_76) | (ap_sig_bdd_81 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))))) begin
i_reg_139 <= i_mid_reg_328;
end else if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
i_reg_139 <= ap_const_lv6_0;
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (exitcond_reg_319 == ap_const_lv1_0) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ap_sig_bdd_76) | (ap_sig_bdd_81 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))))) begin
indvar_flatten_reg_128 <= indvar_next_reg_323;
end else if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
indvar_flatten_reg_128 <= ap_const_lv8_0;
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_fu_162_p2 == ap_const_lv1_0) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ap_sig_bdd_76) | (ap_sig_bdd_81 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))))) begin
indvar_next1_reg_343 <= (indvar_mid_fu_186_p3 + ap_const_lv3_1);
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ap_sig_bdd_76) | (ap_sig_bdd_81 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))))) begin
indvar_next_reg_323 <= (indvar_flatten_phi_fu_132_p4 + ap_const_lv8_1);
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (exitcond_reg_319 == ap_const_lv1_0) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ap_sig_bdd_76) | (ap_sig_bdd_81 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))))) begin
indvar_reg_150 <= indvar_next1_reg_343;
end else if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
indvar_reg_150 <= ap_const_lv3_0;
end
end
/// ap_NS_fsm assign process. ///
always @ (ap_start or ap_CS_fsm or exitcond_fu_162_p2 or ap_reg_ppiten_pp0_it0 or ap_sig_bdd_76 or ap_sig_bdd_81 or ap_reg_ppiten_pp0_it1 or ap_reg_ppiten_pp0_it2)
begin
if ((((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it2) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ap_sig_bdd_76) | (ap_sig_bdd_81 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))) & ~(ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ap_sig_bdd_76) | (ap_sig_bdd_81 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))) & ~(exitcond_fu_162_p2 == ap_const_lv1_0) & ~(ap_const_logic_1 == ap_reg_ppiten_pp0_it1)))) begin
ap_NS_fsm = ap_ST_st5_fsm_3;
end else if ((~(ap_const_logic_1 == ap_start) & (ap_ST_st5_fsm_3 == ap_CS_fsm))) begin
ap_NS_fsm = ap_ST_st0_fsm_0;
end else if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_pp0_stg0_fsm_2;
end else if ((((ap_ST_st0_fsm_0 == ap_CS_fsm) & (ap_const_logic_1 == ap_start)) | ((ap_const_logic_1 == ap_start) & (ap_ST_st5_fsm_3 == ap_CS_fsm)))) begin
ap_NS_fsm = ap_ST_st1_fsm_1;
end else begin
ap_NS_fsm = ap_CS_fsm;
end
end
/// ap_done assign process. ///
always @ (ap_CS_fsm)
begin
if (((ap_ST_st0_fsm_0 == ap_CS_fsm) | (ap_ST_st5_fsm_3 == ap_CS_fsm))) begin
ap_done = ap_const_logic_1;
end else begin
ap_done = ap_const_logic_0;
end
end
/// ap_idle assign process. ///
always @ (ap_CS_fsm)
begin
if ((ap_ST_st0_fsm_0 == ap_CS_fsm)) begin
ap_idle = ap_const_logic_1;
end else begin
ap_idle = ap_const_logic_0;
end
end
/// bus_r_req_write assign process. ///
always @ (ap_CS_fsm or exitcond_fu_162_p2 or ap_reg_ppiten_pp0_it0 or ap_sig_bdd_76 or ap_sig_bdd_81 or ap_reg_ppiten_pp0_it1)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_fu_162_p2 == ap_const_lv1_0) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ap_sig_bdd_76) | (ap_sig_bdd_81 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))))) begin
bus_r_req_write = ap_const_logic_1;
end else begin
bus_r_req_write = ap_const_logic_0;
end
end
/// bus_r_rsp_read assign process. ///
always @ (ap_CS_fsm or exitcond_reg_319 or ap_reg_ppiten_pp0_it0 or ap_sig_bdd_76 or ap_sig_bdd_81 or ap_reg_ppiten_pp0_it1)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (exitcond_reg_319 == ap_const_lv1_0) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ap_sig_bdd_76) | (ap_sig_bdd_81 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))))) begin
bus_r_rsp_read = ap_const_logic_1;
end else begin
bus_r_rsp_read = ap_const_logic_0;
end
end
/// data_p0_ce0 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp0_it0 or ap_sig_bdd_76 or ap_sig_bdd_81 or ap_reg_ppiten_pp0_it1 or ap_reg_ppiten_pp0_it2 or ap_reg_ppstg_exitcond_reg_319_pp0_it1)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it2) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ap_sig_bdd_76) | (ap_sig_bdd_81 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_319_pp0_it1))) begin
data_p0_ce0 = ap_const_logic_1;
end else begin
data_p0_ce0 = ap_const_logic_0;
end
end
/// data_p0_we0 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp0_it0 or ap_sig_bdd_76 or ap_sig_bdd_81 or ap_reg_ppiten_pp0_it1 or ap_reg_ppiten_pp0_it2 or ap_reg_ppstg_exitcond_reg_319_pp0_it1)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it2) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ap_sig_bdd_76) | (ap_sig_bdd_81 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_319_pp0_it1))) begin
data_p0_we0 = ap_const_logic_1;
end else begin
data_p0_we0 = ap_const_logic_0;
end
end
/// data_p1_ce0 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp0_it0 or ap_sig_bdd_76 or ap_sig_bdd_81 or ap_reg_ppiten_pp0_it1 or ap_reg_ppiten_pp0_it2 or ap_reg_ppstg_exitcond_reg_319_pp0_it1)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it2) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ap_sig_bdd_76) | (ap_sig_bdd_81 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_319_pp0_it1))) begin
data_p1_ce0 = ap_const_logic_1;
end else begin
data_p1_ce0 = ap_const_logic_0;
end
end
/// data_p1_we0 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp0_it0 or ap_sig_bdd_76 or ap_sig_bdd_81 or ap_reg_ppiten_pp0_it1 or ap_reg_ppiten_pp0_it2 or ap_reg_ppstg_exitcond_reg_319_pp0_it1)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it2) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ap_sig_bdd_76) | (ap_sig_bdd_81 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_319_pp0_it1))) begin
data_p1_we0 = ap_const_logic_1;
end else begin
data_p1_we0 = ap_const_logic_0;
end
end
/// data_p2_ce0 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp0_it0 or ap_sig_bdd_76 or ap_sig_bdd_81 or ap_reg_ppiten_pp0_it1 or ap_reg_ppiten_pp0_it2 or ap_reg_ppstg_exitcond_reg_319_pp0_it1)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it2) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ap_sig_bdd_76) | (ap_sig_bdd_81 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_319_pp0_it1))) begin
data_p2_ce0 = ap_const_logic_1;
end else begin
data_p2_ce0 = ap_const_logic_0;
end
end
/// data_p2_we0 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp0_it0 or ap_sig_bdd_76 or ap_sig_bdd_81 or ap_reg_ppiten_pp0_it1 or ap_reg_ppiten_pp0_it2 or ap_reg_ppstg_exitcond_reg_319_pp0_it1)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it2) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ap_sig_bdd_76) | (ap_sig_bdd_81 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_319_pp0_it1))) begin
data_p2_we0 = ap_const_logic_1;
end else begin
data_p2_we0 = ap_const_logic_0;
end
end
/// data_p3_ce0 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp0_it0 or ap_sig_bdd_76 or ap_sig_bdd_81 or ap_reg_ppiten_pp0_it1 or ap_reg_ppiten_pp0_it2 or ap_reg_ppstg_exitcond_reg_319_pp0_it1)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it2) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ap_sig_bdd_76) | (ap_sig_bdd_81 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_319_pp0_it1))) begin
data_p3_ce0 = ap_const_logic_1;
end else begin
data_p3_ce0 = ap_const_logic_0;
end
end
/// data_p3_we0 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp0_it0 or ap_sig_bdd_76 or ap_sig_bdd_81 or ap_reg_ppiten_pp0_it1 or ap_reg_ppiten_pp0_it2 or ap_reg_ppstg_exitcond_reg_319_pp0_it1)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it2) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ap_sig_bdd_76) | (ap_sig_bdd_81 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_319_pp0_it1))) begin
data_p3_we0 = ap_const_logic_1;
end else begin
data_p3_we0 = ap_const_logic_0;
end
end
/// i_phi_fu_143_p4 assign process. ///
always @ (ap_CS_fsm or i_reg_139 or exitcond_reg_319 or ap_reg_ppiten_pp0_it1 or i_mid_reg_328)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (exitcond_reg_319 == ap_const_lv1_0) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))) begin
i_phi_fu_143_p4 = i_mid_reg_328;
end else begin
i_phi_fu_143_p4 = i_reg_139;
end
end
/// indvar_flatten_phi_fu_132_p4 assign process. ///
always @ (ap_CS_fsm or indvar_flatten_reg_128 or exitcond_reg_319 or ap_reg_ppiten_pp0_it1 or indvar_next_reg_323)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (exitcond_reg_319 == ap_const_lv1_0) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))) begin
indvar_flatten_phi_fu_132_p4 = indvar_next_reg_323;
end else begin
indvar_flatten_phi_fu_132_p4 = indvar_flatten_reg_128;
end
end
/// indvar_phi_fu_154_p4 assign process. ///
always @ (ap_CS_fsm or indvar_reg_150 or exitcond_reg_319 or ap_reg_ppiten_pp0_it1 or indvar_next1_reg_343)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (exitcond_reg_319 == ap_const_lv1_0) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))) begin
indvar_phi_fu_154_p4 = indvar_next1_reg_343;
end else begin
indvar_phi_fu_154_p4 = indvar_reg_150;
end
end
/// ap_sig_bdd_76 assign process. ///
always @ (bus_r_req_full_n or exitcond_fu_162_p2)
begin
ap_sig_bdd_76 = ((bus_r_req_full_n == ap_const_logic_0) & (exitcond_fu_162_p2 == ap_const_lv1_0));
end
/// ap_sig_bdd_81 assign process. ///
always @ (bus_r_rsp_empty_n or exitcond_reg_319)
begin
ap_sig_bdd_81 = ((bus_r_rsp_empty_n == ap_const_logic_0) & (exitcond_reg_319 == ap_const_lv1_0));
end
assign bus_r_address = tmp_fu_212_p1;
assign bus_r_dataout = ap_const_lv128_lc_1;
assign bus_r_req_din = ap_const_logic_0;
assign bus_r_size = ap_const_lv32_0;
assign data_p0_addr1_cast_fu_300_p1 = {{24{1'b0}}, {ap_reg_ppstg_data_p0_addr_reg_338_pp0_it1}};
assign data_p0_addr_cast_fu_244_p2 = (p_shl_fu_238_p2 - tmp4_trn_cast_fu_234_p1);
assign data_p0_address0 = data_p0_addr1_cast_fu_300_p1;
assign data_p0_d0 = Result1_reg_348;
assign data_p1_address0 = data_p0_addr1_cast_fu_300_p1;
assign data_p1_d0 = Result3_reg_353;
assign data_p2_address0 = data_p0_addr1_cast_fu_300_p1;
assign data_p2_d0 = Result2_reg_358;
assign data_p3_address0 = data_p0_addr1_cast_fu_300_p1;
assign data_p3_d0 = Result_reg_363;
assign exitcond1_fu_180_p1 = ap_const_lv3_4;
assign exitcond1_fu_180_p2 = (indvar_phi_fu_154_p4 == exitcond1_fu_180_p1? 1'b1: 1'b0);
assign exitcond_fu_162_p1 = ap_const_lv8_F0;
assign exitcond_fu_162_p2 = (indvar_flatten_phi_fu_132_p4 == exitcond_fu_162_p1? 1'b1: 1'b0);
assign i_mid_fu_194_p3 = ((exitcond1_fu_180_p2)? indvar_next6_dup_fu_174_p2: i_phi_fu_143_p4);
assign indvar_cast_fu_202_p1 = {{1{1'b0}}, {indvar_mid_fu_186_p3}};
assign indvar_mid_fu_186_p3 = ((exitcond1_fu_180_p2)? ap_const_lv3_0: indvar_phi_fu_154_p4);
assign indvar_next6_dup_fu_174_p2 = (i_phi_fu_143_p4 + ap_const_lv6_1);
assign j_fu_206_p2 = indvar_cast_fu_202_p1 << ap_const_lv4_2;
assign p_shl_fu_238_p2 = tmp4_trn_cast_fu_234_p1 << ap_const_lv8_4;
assign tmp4_trn_cast_fu_234_p1 = {{2{1'b0}}, {i_mid_fu_194_p3}};
assign tmp8_trn_cast_fu_230_p1 = {{4{1'b0}}, {j_fu_206_p2}};
assign tmp_fu_212_p1 = {{32{uIndex[31]}}, {uIndex}};
endmodule //uFetch_array
|
// ==============================================================
// RTL generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ===========================================================
`timescale 1 ns / 1 ps
module write_array (
ap_clk,
ap_rst,
ap_start,
ap_done,
ap_idle,
bus_r_req_din,
bus_r_req_full_n,
bus_r_req_write,
bus_r_rsp_dout,
bus_r_rsp_empty_n,
bus_r_rsp_read,
bus_r_address,
bus_r_datain,
bus_r_dataout,
bus_r_size,
data_p0_address0,
data_p0_ce0,
data_p0_q0,
data_p1_address0,
data_p1_ce0,
data_p1_q0,
data_p2_address0,
data_p2_ce0,
data_p2_q0,
data_p3_address0,
data_p3_ce0,
data_p3_q0
);
input ap_clk;
input ap_rst;
input ap_start;
output ap_done;
output ap_idle;
output bus_r_req_din;
input bus_r_req_full_n;
output bus_r_req_write;
input bus_r_rsp_dout;
input bus_r_rsp_empty_n;
output bus_r_rsp_read;
output [31:0] bus_r_address;
input [127:0] bus_r_datain;
output [127:0] bus_r_dataout;
output [31:0] bus_r_size;
output [7:0] data_p0_address0;
output data_p0_ce0;
input [31:0] data_p0_q0;
output [7:0] data_p1_address0;
output data_p1_ce0;
input [31:0] data_p1_q0;
output [7:0] data_p2_address0;
output data_p2_ce0;
input [31:0] data_p2_q0;
output [7:0] data_p3_address0;
output data_p3_ce0;
input [31:0] data_p3_q0;
reg ap_done;
reg ap_idle;
reg bus_r_req_din;
reg bus_r_req_write;
reg data_p0_ce0;
reg data_p1_ce0;
reg data_p2_ce0;
reg data_p3_ce0;
reg [1:0] ap_CS_fsm;
reg [31:0] rIndex;
reg [7:0] indvar_flatten_reg_117;
reg [5:0] i_reg_128;
reg [2:0] indvar_reg_139;
wire [0:0] exitcond_fu_151_p2;
reg [0:0] exitcond_reg_284;
reg ap_reg_ppiten_pp0_it0;
reg ap_reg_ppiten_pp0_it1;
reg [0:0] ap_reg_ppstg_exitcond_reg_284_pp0_it1;
reg ap_sig_bdd_75;
reg ap_reg_ppiten_pp0_it2;
reg ap_reg_ppiten_pp0_it3;
reg [7:0] indvar_next_reg_288;
wire [5:0] i_mid_fu_183_p3;
reg [5:0] i_mid_reg_293;
reg [2:0] indvar_next1_reg_318;
reg [31:0] data_p0_load_reg_323;
reg [31:0] data_p1_load_reg_328;
reg [31:0] data_p2_load_reg_333;
reg [31:0] data_p3_load_reg_338;
reg [7:0] indvar_flatten_phi_fu_121_p4;
reg [5:0] i_phi_fu_132_p4;
reg [2:0] indvar_phi_fu_143_p4;
wire [31:0] data_p0_addr1_cast_fu_227_p1;
wire [63:0] tmp4_fu_266_p1;
wire [7:0] exitcond_fu_151_p1;
wire [2:0] exitcond1_fu_169_p1;
wire [0:0] exitcond1_fu_169_p2;
wire [5:0] indvar_next6_dup_fu_163_p2;
wire [2:0] indvar_mid_fu_175_p3;
wire [3:0] indvar_cast_fu_191_p1;
wire [3:0] j_fu_195_p2;
wire [7:0] tmp4_trn_cast_fu_205_p1;
wire [7:0] p_shl_fu_209_p2;
wire [7:0] data_p0_addr_cast_fu_215_p2;
wire [7:0] tmp6_trn_cast_fu_201_p1;
wire [7:0] data_p0_addr_fu_221_p2;
wire [31:0] empty_92_fu_253_p1;
wire [31:0] empty_92_fu_253_p2;
wire [31:0] empty_92_fu_253_p3;
wire [31:0] tmp3_fu_250_p1;
reg [1:0] ap_NS_fsm;
parameter ap_const_logic_1 = 1'b1;
parameter ap_const_logic_0 = 1'b0;
parameter ap_ST_st0_fsm_0 = 2'b00;
parameter ap_ST_st1_fsm_1 = 2'b01;
parameter ap_ST_pp0_stg0_fsm_2 = 2'b10;
parameter ap_ST_st6_fsm_3 = 2'b11;
parameter ap_const_lv32_0 = 32'b00000000000000000000000000000000;
parameter ap_const_lv1_0 = 1'b0;
parameter ap_const_lv8_0 = 8'b00000000;
parameter ap_const_lv6_0 = 6'b000000;
parameter ap_const_lv3_0 = 3'b000;
parameter ap_const_lv8_F0 = 8'b11110000;
parameter ap_const_lv8_1 = 8'b00000001;
parameter ap_const_lv6_1 = 6'b000001;
parameter ap_const_lv3_4 = 3'b100;
parameter ap_const_lv4_2 = 4'b0010;
parameter ap_const_lv8_4 = 8'b00000100;
parameter ap_const_lv3_1 = 3'b001;
parameter ap_const_lv32_1 = 32'b00000000000000000000000000000001;
parameter ap_true = 1'b1;
/// ap_CS_fsm assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_CS_fsm
if (ap_rst == 1'b1) begin
ap_CS_fsm <= ap_ST_st0_fsm_0;
end else begin
ap_CS_fsm <= ap_NS_fsm;
end
end
/// ap_reg_ppiten_pp0_it0 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it0
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it0 <= ap_const_logic_0;
end else begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & ~(ap_sig_bdd_75 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it2)) & ~(exitcond_fu_151_p2 == ap_const_lv1_0))) begin
ap_reg_ppiten_pp0_it0 <= ap_const_logic_0;
end else if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it0 <= ap_const_logic_1;
end
end
end
/// ap_reg_ppiten_pp0_it1 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it1
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it1 <= ap_const_logic_0;
end else begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & ~(ap_sig_bdd_75 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it2)) & (exitcond_fu_151_p2 == ap_const_lv1_0))) begin
ap_reg_ppiten_pp0_it1 <= ap_const_logic_1;
end else if (((ap_ST_st1_fsm_1 == ap_CS_fsm) | ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & ~(ap_sig_bdd_75 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it2)) & ~(exitcond_fu_151_p2 == ap_const_lv1_0)))) begin
ap_reg_ppiten_pp0_it1 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp0_it2 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it2
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it2 <= ap_const_logic_0;
end else begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & ~(ap_sig_bdd_75 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it2)))) begin
ap_reg_ppiten_pp0_it2 <= ap_reg_ppiten_pp0_it1;
end else if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it2 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp0_it3 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it3
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it3 <= ap_const_logic_0;
end else begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & ~(ap_sig_bdd_75 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it2)))) begin
ap_reg_ppiten_pp0_it3 <= ap_reg_ppiten_pp0_it2;
end else if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it3 <= ap_const_logic_0;
end
end
end
/// rIndex assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_rIndex
if (ap_rst == 1'b1) begin
rIndex <= ap_const_lv32_0;
end else begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_reg_ppstg_exitcond_reg_284_pp0_it1 == ap_const_lv1_0) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it2) & ~(ap_sig_bdd_75 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it2)))) begin
rIndex <= (rIndex + ap_const_lv32_1);
end
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & ~(ap_sig_bdd_75 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it2)))) begin
ap_reg_ppstg_exitcond_reg_284_pp0_it1 <= exitcond_reg_284;
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & ~(ap_sig_bdd_75 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it2)) & (exitcond_reg_284 == ap_const_lv1_0))) begin
data_p0_load_reg_323 <= data_p0_q0;
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & ~(ap_sig_bdd_75 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it2)) & (exitcond_reg_284 == ap_const_lv1_0))) begin
data_p1_load_reg_328 <= data_p1_q0;
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & ~(ap_sig_bdd_75 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it2)) & (exitcond_reg_284 == ap_const_lv1_0))) begin
data_p2_load_reg_333 <= data_p2_q0;
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & ~(ap_sig_bdd_75 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it2)) & (exitcond_reg_284 == ap_const_lv1_0))) begin
data_p3_load_reg_338 <= data_p3_q0;
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ~(ap_sig_bdd_75 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it2)))) begin
exitcond_reg_284 <= (indvar_flatten_phi_fu_121_p4 == exitcond_fu_151_p1? 1'b1: 1'b0);
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ~(ap_sig_bdd_75 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it2)) & (exitcond_fu_151_p2 == ap_const_lv1_0))) begin
if (exitcond1_fu_169_p2) begin
i_mid_reg_293 <= indvar_next6_dup_fu_163_p2;
end else begin
i_mid_reg_293 <= i_phi_fu_132_p4;
end
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & ~(ap_sig_bdd_75 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it2)) & (exitcond_reg_284 == ap_const_lv1_0))) begin
i_reg_128 <= i_mid_reg_293;
end else if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
i_reg_128 <= ap_const_lv6_0;
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & ~(ap_sig_bdd_75 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it2)) & (exitcond_reg_284 == ap_const_lv1_0))) begin
indvar_flatten_reg_117 <= indvar_next_reg_288;
end else if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
indvar_flatten_reg_117 <= ap_const_lv8_0;
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ~(ap_sig_bdd_75 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it2)) & (exitcond_fu_151_p2 == ap_const_lv1_0))) begin
indvar_next1_reg_318 <= (indvar_mid_fu_175_p3 + ap_const_lv3_1);
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ~(ap_sig_bdd_75 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it2)))) begin
indvar_next_reg_288 <= (indvar_flatten_phi_fu_121_p4 + ap_const_lv8_1);
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & ~(ap_sig_bdd_75 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it2)) & (exitcond_reg_284 == ap_const_lv1_0))) begin
indvar_reg_139 <= indvar_next1_reg_318;
end else if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
indvar_reg_139 <= ap_const_lv3_0;
end
end
/// ap_NS_fsm assign process. ///
always @ (ap_start or ap_CS_fsm or exitcond_fu_151_p2 or ap_reg_ppiten_pp0_it0 or ap_reg_ppiten_pp0_it1 or ap_sig_bdd_75 or ap_reg_ppiten_pp0_it2 or ap_reg_ppiten_pp0_it3)
begin
if ((((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it3) & ~(ap_sig_bdd_75 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it2)) & ~(ap_const_logic_1 == ap_reg_ppiten_pp0_it2)) | ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ~(ap_sig_bdd_75 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it2)) & ~(exitcond_fu_151_p2 == ap_const_lv1_0) & ~(ap_const_logic_1 == ap_reg_ppiten_pp0_it1)))) begin
ap_NS_fsm = ap_ST_st6_fsm_3;
end else if ((~(ap_const_logic_1 == ap_start) & (ap_ST_st6_fsm_3 == ap_CS_fsm))) begin
ap_NS_fsm = ap_ST_st0_fsm_0;
end else if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_pp0_stg0_fsm_2;
end else if ((((ap_ST_st0_fsm_0 == ap_CS_fsm) & (ap_const_logic_1 == ap_start)) | ((ap_const_logic_1 == ap_start) & (ap_ST_st6_fsm_3 == ap_CS_fsm)))) begin
ap_NS_fsm = ap_ST_st1_fsm_1;
end else begin
ap_NS_fsm = ap_CS_fsm;
end
end
/// ap_done assign process. ///
always @ (ap_CS_fsm)
begin
if (((ap_ST_st0_fsm_0 == ap_CS_fsm) | (ap_ST_st6_fsm_3 == ap_CS_fsm))) begin
ap_done = ap_const_logic_1;
end else begin
ap_done = ap_const_logic_0;
end
end
/// ap_idle assign process. ///
always @ (ap_CS_fsm)
begin
if ((ap_ST_st0_fsm_0 == ap_CS_fsm)) begin
ap_idle = ap_const_logic_1;
end else begin
ap_idle = ap_const_logic_0;
end
end
/// bus_r_req_din assign process. ///
always @ (ap_CS_fsm or ap_reg_ppstg_exitcond_reg_284_pp0_it1 or ap_sig_bdd_75 or ap_reg_ppiten_pp0_it2)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_reg_ppstg_exitcond_reg_284_pp0_it1 == ap_const_lv1_0) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it2) & ~(ap_sig_bdd_75 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it2)))) begin
bus_r_req_din = ap_const_logic_1;
end else begin
bus_r_req_din = ap_const_logic_0;
end
end
/// bus_r_req_write assign process. ///
always @ (ap_CS_fsm or ap_reg_ppstg_exitcond_reg_284_pp0_it1 or ap_sig_bdd_75 or ap_reg_ppiten_pp0_it2)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_reg_ppstg_exitcond_reg_284_pp0_it1 == ap_const_lv1_0) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it2) & ~(ap_sig_bdd_75 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it2)))) begin
bus_r_req_write = ap_const_logic_1;
end else begin
bus_r_req_write = ap_const_logic_0;
end
end
/// data_p0_ce0 assign process. ///
always @ (ap_CS_fsm or exitcond_fu_151_p2 or ap_reg_ppiten_pp0_it0 or ap_sig_bdd_75 or ap_reg_ppiten_pp0_it2)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ~(ap_sig_bdd_75 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it2)) & (exitcond_fu_151_p2 == ap_const_lv1_0))) begin
data_p0_ce0 = ap_const_logic_1;
end else begin
data_p0_ce0 = ap_const_logic_0;
end
end
/// data_p1_ce0 assign process. ///
always @ (ap_CS_fsm or exitcond_fu_151_p2 or ap_reg_ppiten_pp0_it0 or ap_sig_bdd_75 or ap_reg_ppiten_pp0_it2)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ~(ap_sig_bdd_75 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it2)) & (exitcond_fu_151_p2 == ap_const_lv1_0))) begin
data_p1_ce0 = ap_const_logic_1;
end else begin
data_p1_ce0 = ap_const_logic_0;
end
end
/// data_p2_ce0 assign process. ///
always @ (ap_CS_fsm or exitcond_fu_151_p2 or ap_reg_ppiten_pp0_it0 or ap_sig_bdd_75 or ap_reg_ppiten_pp0_it2)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ~(ap_sig_bdd_75 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it2)) & (exitcond_fu_151_p2 == ap_const_lv1_0))) begin
data_p2_ce0 = ap_const_logic_1;
end else begin
data_p2_ce0 = ap_const_logic_0;
end
end
/// data_p3_ce0 assign process. ///
always @ (ap_CS_fsm or exitcond_fu_151_p2 or ap_reg_ppiten_pp0_it0 or ap_sig_bdd_75 or ap_reg_ppiten_pp0_it2)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ~(ap_sig_bdd_75 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it2)) & (exitcond_fu_151_p2 == ap_const_lv1_0))) begin
data_p3_ce0 = ap_const_logic_1;
end else begin
data_p3_ce0 = ap_const_logic_0;
end
end
/// i_phi_fu_132_p4 assign process. ///
always @ (ap_CS_fsm or i_reg_128 or exitcond_reg_284 or ap_reg_ppiten_pp0_it1 or i_mid_reg_293)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (exitcond_reg_284 == ap_const_lv1_0))) begin
i_phi_fu_132_p4 = i_mid_reg_293;
end else begin
i_phi_fu_132_p4 = i_reg_128;
end
end
/// indvar_flatten_phi_fu_121_p4 assign process. ///
always @ (ap_CS_fsm or indvar_flatten_reg_117 or exitcond_reg_284 or ap_reg_ppiten_pp0_it1 or indvar_next_reg_288)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (exitcond_reg_284 == ap_const_lv1_0))) begin
indvar_flatten_phi_fu_121_p4 = indvar_next_reg_288;
end else begin
indvar_flatten_phi_fu_121_p4 = indvar_flatten_reg_117;
end
end
/// indvar_phi_fu_143_p4 assign process. ///
always @ (ap_CS_fsm or indvar_reg_139 or exitcond_reg_284 or ap_reg_ppiten_pp0_it1 or indvar_next1_reg_318)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (exitcond_reg_284 == ap_const_lv1_0))) begin
indvar_phi_fu_143_p4 = indvar_next1_reg_318;
end else begin
indvar_phi_fu_143_p4 = indvar_reg_139;
end
end
/// ap_sig_bdd_75 assign process. ///
always @ (bus_r_req_full_n or ap_reg_ppstg_exitcond_reg_284_pp0_it1)
begin
ap_sig_bdd_75 = ((bus_r_req_full_n == ap_const_logic_0) & (ap_reg_ppstg_exitcond_reg_284_pp0_it1 == ap_const_lv1_0));
end
assign bus_r_address = tmp4_fu_266_p1;
assign bus_r_dataout = {{{{{{empty_92_fu_253_p1}, {empty_92_fu_253_p2}}}, {empty_92_fu_253_p3}}}, {tmp3_fu_250_p1}};
assign bus_r_rsp_read = ap_const_logic_0;
assign bus_r_size = ap_const_lv32_0;
assign data_p0_addr1_cast_fu_227_p1 = {{24{1'b0}}, {data_p0_addr_fu_221_p2}};
assign data_p0_addr_cast_fu_215_p2 = (p_shl_fu_209_p2 - tmp4_trn_cast_fu_205_p1);
assign data_p0_addr_fu_221_p2 = (data_p0_addr_cast_fu_215_p2 + tmp6_trn_cast_fu_201_p1);
assign data_p0_address0 = data_p0_addr1_cast_fu_227_p1;
assign data_p1_address0 = data_p0_addr1_cast_fu_227_p1;
assign data_p2_address0 = data_p0_addr1_cast_fu_227_p1;
assign data_p3_address0 = data_p0_addr1_cast_fu_227_p1;
assign empty_92_fu_253_p1 = data_p0_load_reg_323;
assign empty_92_fu_253_p2 = data_p1_load_reg_328;
assign empty_92_fu_253_p3 = data_p2_load_reg_333;
assign exitcond1_fu_169_p1 = ap_const_lv3_4;
assign exitcond1_fu_169_p2 = (indvar_phi_fu_143_p4 == exitcond1_fu_169_p1? 1'b1: 1'b0);
assign exitcond_fu_151_p1 = ap_const_lv8_F0;
assign exitcond_fu_151_p2 = (indvar_flatten_phi_fu_121_p4 == exitcond_fu_151_p1? 1'b1: 1'b0);
assign i_mid_fu_183_p3 = ((exitcond1_fu_169_p2)? indvar_next6_dup_fu_163_p2: i_phi_fu_132_p4);
assign indvar_cast_fu_191_p1 = {{1{1'b0}}, {indvar_mid_fu_175_p3}};
assign indvar_mid_fu_175_p3 = ((exitcond1_fu_169_p2)? ap_const_lv3_0: indvar_phi_fu_143_p4);
assign indvar_next6_dup_fu_163_p2 = (i_phi_fu_132_p4 + ap_const_lv6_1);
assign j_fu_195_p2 = indvar_cast_fu_191_p1 << ap_const_lv4_2;
assign p_shl_fu_209_p2 = tmp4_trn_cast_fu_205_p1 << ap_const_lv8_4;
assign tmp3_fu_250_p1 = data_p3_load_reg_338;
assign tmp4_fu_266_p1 = {{32{rIndex[31]}}, {rIndex}};
assign tmp4_trn_cast_fu_205_p1 = {{2{1'b0}}, {i_mid_fu_183_p3}};
assign tmp6_trn_cast_fu_201_p1 = {{4{1'b0}}, {j_fu_195_p2}};
endmodule //write_array
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
/*-----------------------------------------------------------------------
-- AESL_FPSim_pkg.v:
-- Floating point simulation model for verilog.
--
-----------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Single precision units.
-- FAdd, FSub, FAddSub, FMul, FDiv, FSqrt
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Double precision units.
-- DAdd, DSub, DAddSub, DMul, DDiv, DSqrt
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Single precision units.
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Single precision Add.
-------------------------------------------------------------------------------
*/
`celldefine
module ACMP_fadd_comb(din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 32;
parameter din1_WIDTH = 32;
parameter dout_WIDTH = 32;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_FAdd #(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_FAdd_U (
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
`endcelldefine
`celldefine
module ACMP_fadd(clk, reset, ce, din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 32;
parameter din1_WIDTH = 32;
parameter dout_WIDTH = 32;
input clk, reset, ce;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_FAdd #(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_FAdd_U (
.clk(clk),
.reset(reset),
.ce(ce),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
`endcelldefine
/*
-------------------------------------------------------------------------------
-- Single precision Sub.
-------------------------------------------------------------------------------
*/
`celldefine
module ACMP_fsub_comb (din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 32;
parameter din1_WIDTH = 32;
parameter dout_WIDTH = 32;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_FSub #(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_FSub_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
`endcelldefine
`celldefine
module ACMP_fsub(clk, reset, ce, din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 32;
parameter din1_WIDTH = 32;
parameter dout_WIDTH = 32;
input clk, reset, ce;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_FSub #(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_FSub_U(
.clk(clk),
.reset(reset),
.ce(ce),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
`endcelldefine
/*
-------------------------------------------------------------------------------
-- Single precision AddSub.
-------------------------------------------------------------------------------
*/
`celldefine
module ACMP_faddfsub_comb(opcode, din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 32;
parameter din1_WIDTH = 32;
parameter dout_WIDTH = 32;
input[1:0] opcode;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_FAddFSub
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_FAddFSub_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.opcode(opcode),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
`endcelldefine
`celldefine
module ACMP_faddfsub(clk, reset, ce, opcode, din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 32;
parameter din1_WIDTH = 32;
parameter dout_WIDTH = 32;
input clk, reset, ce;
input[1:0] opcode;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_FAddFSub
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_FAddFSub_U(
.clk(clk),
.reset(reset),
.ce(ce),
.opcode(opcode),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
`endcelldefine
`celldefine
module ACMP_fmul_comb(din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 32;
parameter din1_WIDTH = 32;
parameter dout_WIDTH = 32;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_FMul
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_FMul_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
`endcelldefine
`celldefine
module ACMP_fmul(clk, reset, ce, din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 32;
parameter din1_WIDTH = 32;
parameter dout_WIDTH = 32;
input clk, reset, ce;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_FMul
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_FMul_U(
.clk(clk),
.reset(reset),
.ce(ce),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
`endcelldefine
`celldefine
module ACMP_fdiv_comb(din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 32;
parameter din1_WIDTH = 32;
parameter dout_WIDTH = 32;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_FDiv
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_FDiv_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
`endcelldefine
`celldefine
module ACMP_fdiv(clk, reset, ce, din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 32;
parameter din1_WIDTH = 32;
parameter dout_WIDTH = 32;
input clk, reset, ce;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_FDiv
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_FDiv_U(
.clk(clk),
.reset(reset),
.ce(ce),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
`endcelldefine
`celldefine
module ACMP_fsqrt_comb (din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 32;
parameter din1_WIDTH = 32;
parameter dout_WIDTH = 32;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_FSqrt
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_FSqrt_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
`endcelldefine
`celldefine
module ACMP_fsqrt(clk, reset, ce, din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 32;
parameter din1_WIDTH = 32;
parameter dout_WIDTH = 32;
input clk, reset, ce;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_FSqrt
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_FSqrt_U(
.clk(clk),
.reset(reset),
.ce(ce),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
`endcelldefine
/*
-------------------------------------------------------------------------------
-- Double precision
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Double precision ADD
-------------------------------------------------------------------------------
*/
`celldefine
module ACMP_dadd_comb(din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 64;
parameter din1_WIDTH = 64;
parameter dout_WIDTH = 64;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_DAdd
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_DAdd_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
`endcelldefine
`celldefine
module ACMP_dadd(clk, reset, ce, din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 64;
parameter din1_WIDTH = 64;
parameter dout_WIDTH = 64;
input clk, reset, ce;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_DAdd
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_DAdd_U(
.clk(clk),
.reset(reset),
.ce(ce),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
`endcelldefine
/*
-------------------------------------------------------------------------------
-- Double precision Sub
-------------------------------------------------------------------------------
*/
`celldefine
module ACMP_dsub_comb(din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 64;
parameter din1_WIDTH = 64;
parameter dout_WIDTH = 64;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_DSub
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_DSub_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
`endcelldefine
`celldefine
module ACMP_dsub(clk, reset, ce, din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 64;
parameter din1_WIDTH = 64;
parameter dout_WIDTH = 64;
input clk, reset, ce;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_DSub
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_DSub_U(
.clk(clk),
.reset(reset),
.ce(ce),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
`endcelldefine
/*
-------------------------------------------------------------------------------
-- Double precision AddSub
-------------------------------------------------------------------------------
*/
`celldefine
module ACMP_dadddsub_comb(opcode, din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 64;
parameter din1_WIDTH = 64;
parameter dout_WIDTH = 64;
input[1:0] opcode;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_DAddDSub
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_DAddDSub_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.opcode(opcode),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
`endcelldefine
`celldefine
module ACMP_dadddsub(clk, reset, ce, opcode, din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 64;
parameter din1_WIDTH = 64;
parameter dout_WIDTH = 64;
input clk, reset, ce;
input[1:0] opcode;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_DAddDSub
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_DAddDSub_U(
.clk(clk),
.reset(reset),
.ce(ce),
.opcode(opcode),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
`endcelldefine
`celldefine
module ACMP_dmul_comb(din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 64;
parameter din1_WIDTH = 64;
parameter dout_WIDTH = 64;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_DMul
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_DMul_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
`endcelldefine
`celldefine
module ACMP_dmul(clk, reset, ce, din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 64;
parameter din1_WIDTH = 64;
parameter dout_WIDTH = 64;
input clk, reset, ce;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_DMul
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_DMul_U(
.clk(clk),
.reset(reset),
.ce(ce),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
`endcelldefine
`celldefine
module ACMP_ddiv_comb(din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 64;
parameter din1_WIDTH = 64;
parameter dout_WIDTH = 64;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_DDiv
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_DDiv_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
`endcelldefine
`celldefine
module ACMP_ddiv(clk, reset, ce, din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 64;
parameter din1_WIDTH = 64;
parameter dout_WIDTH = 64;
input clk, reset, ce;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_DDiv
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_DDiv_U(
.clk(clk),
.reset(reset),
.ce(ce),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
`endcelldefine
`celldefine
module ACMP_dsqrt_comb(din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 64;
parameter din1_WIDTH = 64;
parameter dout_WIDTH = 64;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_DSqrt
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_DSqrt_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
`endcelldefine
`celldefine
module ACMP_dsqrt(clk, reset, ce, din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 64;
parameter din1_WIDTH = 64;
parameter dout_WIDTH = 64;
input clk, reset, ce;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_DSqrt
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_DSqrt_U(
.clk(clk),
.reset(reset),
.ce(ce),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
`endcelldefine
/*
-------------------------------------------------------------------------------
-- Single precision Cmp (Comparator)
-------------------------------------------------------------------------------
-- Predicate values:
-- FCMP_FALSE = 0, ///< 0 0 0 0 Always false (always folded)
-- FCMP_OEQ = 1, ///< 0 0 0 1 True if ordered and equal
-- FCMP_OGT = 2, ///< 0 0 1 0 True if ordered and greater than
-- FCMP_OGE = 3, ///< 0 0 1 1 True if ordered and greater than or equal
-- FCMP_OLT = 4, ///< 0 1 0 0 True if ordered and less than
-- FCMP_OLE = 5, ///< 0 1 0 1 True if ordered and less than or equal
-- FCMP_ONE = 6, ///< 0 1 1 0 True if ordered and operands are unequal
-- FCMP_ORD = 7, ///< 0 1 1 1 True if ordered (no nans)
-- FCMP_UNO = 8, ///< 1 0 0 0 True if unordered: isnan(X) | isnan(Y)
-- FCMP_UEQ = 9, ///< 1 0 0 1 True if unordered or equal
-- FCMP_UGT =10, ///< 1 0 1 0 True if unordered or greater than
-- FCMP_UGE =11, ///< 1 0 1 1 True if unordered, greater than, or equal
-- FCMP_ULT =12, ///< 1 1 0 0 True if unordered or less than
-- FCMP_ULE =13, ///< 1 1 0 1 True if unordered, less than, or equal
-- FCMP_UNE =14, ///< 1 1 1 0 True if unordered or not equal
-- FCMP_TRUE =15, ///< 1 1 1 1 Always true (always folded)
*/
`celldefine
module ACMP_fcmp_comb(opcode, din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 32;
parameter din1_WIDTH = 32;
parameter dout_WIDTH = 1;
input[4:0] opcode;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[0:0] dout;
AESL_WP_FCmp
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_FCmp_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.opcode(opcode),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
`endcelldefine
`celldefine
module ACMP_fcmp(clk, reset, ce, opcode, din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 32;
parameter din1_WIDTH = 32;
parameter dout_WIDTH = 1;
input clk;
input reset, ce;
input[4:0] opcode;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[0:0] dout;
AESL_WP_FCmp
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_FCmp_U(
.clk(clk),
.reset(reset),
.ce(ce),
.opcode(opcode),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
`endcelldefine
/*
-------------------------------------------------------------------------------
-- Double precision Cmp (Comparator)
-------------------------------------------------------------------------------
-- Predicate values:
-- FCMP_FALSE = 0, ///< 0 0 0 0 Always false (always folded)
-- FCMP_OEQ = 1, ///< 0 0 0 1 True if ordered and equal
-- FCMP_OGT = 2, ///< 0 0 1 0 True if ordered and greater than
-- FCMP_OGE = 3, ///< 0 0 1 1 True if ordered and greater than or equal
-- FCMP_OLT = 4, ///< 0 1 0 0 True if ordered and less than
-- FCMP_OLE = 5, ///< 0 1 0 1 True if ordered and less than or equal
-- FCMP_ONE = 6, ///< 0 1 1 0 True if ordered and operands are unequal
-- FCMP_ORD = 7, ///< 0 1 1 1 True if ordered (no nans)
-- FCMP_UNO = 8, ///< 1 0 0 0 True if unordered: isnan(X) | isnan(Y)
-- FCMP_UEQ = 9, ///< 1 0 0 1 True if unordered or equal
-- FCMP_UGT =10, ///< 1 0 1 0 True if unordered or greater than
-- FCMP_UGE =11, ///< 1 0 1 1 True if unordered, greater than, or equal
-- FCMP_ULT =12, ///< 1 1 0 0 True if unordered or less than
-- FCMP_ULE =13, ///< 1 1 0 1 True if unordered, less than, or equal
-- FCMP_UNE =14, ///< 1 1 1 0 True if unordered or not equal
-- FCMP_TRUE =15, ///< 1 1 1 1 Always true (always folded)
*/
`celldefine
module ACMP_dcmp_comb(opcode, din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 64;
parameter din1_WIDTH = 64;
parameter dout_WIDTH = 1;
input[4:0] opcode;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[0:0] dout;
AESL_WP_DCmp
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_DCmp_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.opcode(opcode),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
`endcelldefine
`celldefine
module ACMP_dcmp(clk, reset, ce, opcode, din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 64;
parameter din1_WIDTH = 64;
parameter dout_WIDTH = 1;
input clk;
input reset, ce;
input[4:0] opcode;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[0:0] dout;
AESL_WP_DCmp
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_DCmp_U(
.clk(clk),
.reset(reset),
.ce(ce),
.opcode(opcode),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
`endcelldefine
/*
-------------------------------------------------------------------------------
-- Single precision to int32
-------------------------------------------------------------------------------
*/
`celldefine
module ACMP_fptosi_comb(din0, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 32;
parameter dout_WIDTH = 32;
input[din0_WIDTH-1:0] din0;
output[dout_WIDTH-1:0] dout;
AESL_WP_SPToSI
#(NUM_STAGE, din0_WIDTH, dout_WIDTH)
ACMP_SPToSI_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.din0(din0),
.dout(dout));
endmodule
`endcelldefine
`celldefine
module ACMP_fptosi(clk, reset, ce, din0, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 32;
parameter dout_WIDTH = 32;
input clk;
input reset, ce;
input[din0_WIDTH-1:0] din0;
output[dout_WIDTH-1:0] dout;
AESL_WP_SPToSI
#(NUM_STAGE, din0_WIDTH, dout_WIDTH)
ACMP_SPToSI_U(
.clk(clk),
.reset(reset),
.ce(ce),
.din0(din0),
.dout(dout));
endmodule
`endcelldefine
/*
-------------------------------------------------------------------------------
-- Double precision to int32
-------------------------------------------------------------------------------
*/
`celldefine
module ACMP_dptosi_comb(din0, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 64;
parameter dout_WIDTH = 32;
input[din0_WIDTH-1:0] din0;
output[dout_WIDTH-1:0] dout;
AESL_WP_DPToSI
#(NUM_STAGE, din0_WIDTH, dout_WIDTH)
ACMP_DPToSI_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.din0(din0),
.dout(dout));
endmodule
`endcelldefine
`celldefine
module ACMP_dptosi(clk, reset, ce, din0, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 64;
parameter dout_WIDTH = 32;
input clk;
input reset, ce;
input[din0_WIDTH-1:0] din0;
output[dout_WIDTH-1:0] dout;
AESL_WP_DPToSI
#(NUM_STAGE, din0_WIDTH, dout_WIDTH)
ACMP_DPToSI_U(
.clk(clk),
.reset(reset),
.ce(ce),
.din0(din0),
.dout(dout));
endmodule
`endcelldefine
/*
-------------------------------------------------------------------------------
-- Int32 to single precision
-------------------------------------------------------------------------------
*/
`celldefine
module ACMP_sitofp_comb(din0, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 32;
parameter dout_WIDTH = 64;
input[din0_WIDTH-1:0] din0;
output[dout_WIDTH-1:0] dout;
AESL_WP_SIToSP
#(NUM_STAGE, din0_WIDTH, dout_WIDTH)
ACMP_SIToDP_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.din0(din0),
.dout(dout));
endmodule
`endcelldefine
`celldefine
module ACMP_sitofp(clk, reset, ce, din0, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 32;
parameter dout_WIDTH = 64;
input clk;
input reset, ce;
input[din0_WIDTH-1:0] din0;
output[dout_WIDTH-1:0] dout;
AESL_WP_SIToSP
#(NUM_STAGE, din0_WIDTH, dout_WIDTH)
ACMP_SIToDP_U(
.clk(clk),
.reset(reset),
.ce(ce),
.din0(din0),
.dout(dout));
endmodule
`endcelldefine
/*
-------------------------------------------------------------------------------
-- Int32 to double precision
-------------------------------------------------------------------------------
*/
`celldefine
module ACMP_sitodp_comb(din0, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 32;
parameter dout_WIDTH = 64;
input[din0_WIDTH-1:0] din0;
output[dout_WIDTH-1:0] dout;
AESL_WP_SIToDP
#(NUM_STAGE, din0_WIDTH, dout_WIDTH)
ACMP_SIToDP_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.din0(din0),
.dout(dout));
endmodule
`endcelldefine
`celldefine
module ACMP_sitodp(clk, reset, ce, din0, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 32;
parameter dout_WIDTH = 64;
input clk;
input reset, ce;
input[din0_WIDTH-1:0] din0;
output[dout_WIDTH-1:0] dout;
AESL_WP_SIToDP
#(NUM_STAGE, din0_WIDTH, dout_WIDTH)
ACMP_SIToDP_U(
.clk(clk),
.reset(reset),
.ce(ce),
.din0(din0),
.dout(dout));
endmodule
`endcelldefine
/*
-------------------------------------------------------------------------------
-- Single precision to uint32
-------------------------------------------------------------------------------
*/
`celldefine
module ACMP_fptoui_comb(din0, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 32;
parameter dout_WIDTH = 32;
input[din0_WIDTH-1:0] din0;
output[dout_WIDTH-1:0] dout;
AESL_WP_SPToUI
#(NUM_STAGE, din0_WIDTH, dout_WIDTH)
ACMP_SPToUI_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.din0(din0),
.dout(dout));
endmodule
`endcelldefine
`celldefine
module ACMP_fptoui(clk, reset, ce, din0, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 32;
parameter dout_WIDTH = 32;
input clk;
input reset, ce;
input[din0_WIDTH-1:0] din0;
output[dout_WIDTH-1:0] dout;
AESL_WP_SPToUI
#(NUM_STAGE, din0_WIDTH, dout_WIDTH)
ACMP_SPToUI_U(
.clk(clk),
.reset(reset),
.ce(ce),
.din0(din0),
.dout(dout));
endmodule
`endcelldefine
/*
-------------------------------------------------------------------------------
-- Double precision to uint32
-------------------------------------------------------------------------------
*/
`celldefine
module ACMP_dptoui_comb(din0, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 64;
parameter dout_WIDTH = 32;
input[din0_WIDTH-1:0] din0;
output[dout_WIDTH-1:0] dout;
AESL_WP_DPToUI
#(NUM_STAGE, din0_WIDTH, dout_WIDTH)
ACMP_DPToUI_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.din0(din0),
.dout(dout));
endmodule
`endcelldefine
`celldefine
module ACMP_dptoui(clk, reset, ce, din0, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 64;
parameter dout_WIDTH = 32;
input clk;
input reset, ce;
input[din0_WIDTH-1:0] din0;
output[dout_WIDTH-1:0] dout;
AESL_WP_DPToUI
#(NUM_STAGE, din0_WIDTH, dout_WIDTH)
ACMP_DPToUI_U(
.clk(clk),
.reset(reset),
.ce(ce),
.din0(din0),
.dout(dout));
endmodule
`endcelldefine
/*
-------------------------------------------------------------------------------
-- uInt32 to single precision
-------------------------------------------------------------------------------
*/
`celldefine
module ACMP_uitofp_comb(din0, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 32;
parameter dout_WIDTH = 64;
input[din0_WIDTH-1:0] din0;
output[dout_WIDTH-1:0] dout;
AESL_WP_UIToSP
#(NUM_STAGE, din0_WIDTH, dout_WIDTH)
ACMP_UIToSP_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.din0(din0),
.dout(dout));
endmodule
`endcelldefine
`celldefine
module ACMP_uitofp(clk, reset, ce, din0, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 32;
parameter dout_WIDTH = 64;
input clk;
input reset, ce;
input[din0_WIDTH-1:0] din0;
output[dout_WIDTH-1:0] dout;
AESL_WP_UIToSP
#(NUM_STAGE, din0_WIDTH, dout_WIDTH)
ACMP_UIToSP_U(
.clk(clk),
.reset(reset),
.ce(ce),
.din0(din0),
.dout(dout));
endmodule
`endcelldefine
/*
-------------------------------------------------------------------------------
-- uInt32 to double precision
-------------------------------------------------------------------------------
*/
`celldefine
module ACMP_uitodp_comb(din0, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 32;
parameter dout_WIDTH = 64;
input[din0_WIDTH-1:0] din0;
output[dout_WIDTH-1:0] dout;
AESL_WP_UIToDP
#(NUM_STAGE, din0_WIDTH, dout_WIDTH)
ACMP_UIToDP_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.din0(din0),
.dout(dout));
endmodule
`endcelldefine
`celldefine
module ACMP_uitodp(clk, reset, ce, din0, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 32;
parameter dout_WIDTH = 64;
input clk;
input reset, ce;
input[din0_WIDTH-1:0] din0;
output[dout_WIDTH-1:0] dout;
AESL_WP_UIToDP
#(NUM_STAGE, din0_WIDTH, dout_WIDTH)
ACMP_UIToDP_U(
.clk(clk),
.reset(reset),
.ce(ce),
.din0(din0),
.dout(dout));
endmodule
`endcelldefine
/*
-------------------------------------------------------------------------------
-- single to double precision
-------------------------------------------------------------------------------
*/
`celldefine
module ACMP_fpext_comb(din0, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 32;
parameter dout_WIDTH = 64;
input[din0_WIDTH-1:0] din0;
output[dout_WIDTH-1:0] dout;
AESL_WP_SPToDP
#(NUM_STAGE, din0_WIDTH, dout_WIDTH)
ACMP_fpext_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.din0(din0),
.dout(dout));
endmodule
`endcelldefine
`celldefine
module ACMP_fpext(clk, reset, ce, din0, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 32;
parameter dout_WIDTH = 64;
input clk;
input reset, ce;
input[din0_WIDTH-1:0] din0;
output[dout_WIDTH-1:0] dout;
AESL_WP_SPToDP
#(NUM_STAGE, din0_WIDTH, dout_WIDTH)
ACMP_fpext_U(
.clk(clk),
.reset(reset),
.ce(ce),
.din0(din0),
.dout(dout));
endmodule
`endcelldefine
/*
-------------------------------------------------------------------------------
-- double to single precision
-------------------------------------------------------------------------------
*/
`celldefine
module ACMP_fptrunc_comb(din0, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 32;
parameter dout_WIDTH = 64;
input[din0_WIDTH-1:0] din0;
output[dout_WIDTH-1:0] dout;
AESL_WP_DPToSP
#(NUM_STAGE, din0_WIDTH, dout_WIDTH)
ACMP_fptrunc_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.din0(din0),
.dout(dout));
endmodule
`endcelldefine
`celldefine
module ACMP_fptrunc(clk, reset, ce, din0, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 32;
parameter dout_WIDTH = 64;
input clk;
input reset, ce;
input[din0_WIDTH-1:0] din0;
output[dout_WIDTH-1:0] dout;
AESL_WP_DPToSP
#(NUM_STAGE, din0_WIDTH, dout_WIDTH)
ACMP_fptrunc_U(
.clk(clk),
.reset(reset),
.ce(ce),
.din0(din0),
.dout(dout));
endmodule
`endcelldefine
|
// ==============================================================
// RTL generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ===========================================================
`timescale 1 ns / 1 ps
module computeDiffSqr (
ap_clk,
ap_rst,
ap_start,
ap_done,
ap_idle,
sm_p0_address0,
sm_p0_ce0,
sm_p0_we0,
sm_p0_d0,
sm_p1_address0,
sm_p1_ce0,
sm_p1_we0,
sm_p1_d0,
sm_p2_address0,
sm_p2_ce0,
sm_p2_we0,
sm_p2_d0,
sm_p3_address0,
sm_p3_ce0,
sm_p3_we0,
sm_p3_d0,
sn_p0_address0,
sn_p0_ce0,
sn_p0_we0,
sn_p0_d0,
sn_p1_address0,
sn_p1_ce0,
sn_p1_we0,
sn_p1_d0,
sn_p2_address0,
sn_p2_ce0,
sn_p2_we0,
sn_p2_d0,
sn_p3_address0,
sn_p3_ce0,
sn_p3_we0,
sn_p3_d0,
sp_p0_address0,
sp_p0_ce0,
sp_p0_we0,
sp_p0_d0,
sp_p1_address0,
sp_p1_ce0,
sp_p1_we0,
sp_p1_d0,
sp_p2_address0,
sp_p2_ce0,
sp_p2_we0,
sp_p2_d0,
sp_p3_address0,
sp_p3_ce0,
sp_p3_we0,
sp_p3_d0,
u0_p0_address0,
u0_p0_ce0,
u0_p0_q0,
u0_p1_address0,
u0_p1_ce0,
u0_p1_q0,
u0_p2_address0,
u0_p2_ce0,
u0_p2_q0,
u0_p3_address0,
u0_p3_ce0,
u0_p3_q0,
u0_p3_address1,
u0_p3_ce1,
u0_p3_q1,
u1_p0_address0,
u1_p0_ce0,
u1_p0_q0,
u1_p1_address0,
u1_p1_ce0,
u1_p1_q0,
u1_p2_address0,
u1_p2_ce0,
u1_p2_q0,
u1_p3_address0,
u1_p3_ce0,
u1_p3_q0
);
input ap_clk;
input ap_rst;
input ap_start;
output ap_done;
output ap_idle;
output [7:0] sm_p0_address0;
output sm_p0_ce0;
output sm_p0_we0;
output [31:0] sm_p0_d0;
output [7:0] sm_p1_address0;
output sm_p1_ce0;
output sm_p1_we0;
output [31:0] sm_p1_d0;
output [7:0] sm_p2_address0;
output sm_p2_ce0;
output sm_p2_we0;
output [31:0] sm_p2_d0;
output [7:0] sm_p3_address0;
output sm_p3_ce0;
output sm_p3_we0;
output [31:0] sm_p3_d0;
output [7:0] sn_p0_address0;
output sn_p0_ce0;
output sn_p0_we0;
output [31:0] sn_p0_d0;
output [7:0] sn_p1_address0;
output sn_p1_ce0;
output sn_p1_we0;
output [31:0] sn_p1_d0;
output [7:0] sn_p2_address0;
output sn_p2_ce0;
output sn_p2_we0;
output [31:0] sn_p2_d0;
output [7:0] sn_p3_address0;
output sn_p3_ce0;
output sn_p3_we0;
output [31:0] sn_p3_d0;
output [7:0] sp_p0_address0;
output sp_p0_ce0;
output sp_p0_we0;
output [31:0] sp_p0_d0;
output [7:0] sp_p1_address0;
output sp_p1_ce0;
output sp_p1_we0;
output [31:0] sp_p1_d0;
output [7:0] sp_p2_address0;
output sp_p2_ce0;
output sp_p2_we0;
output [31:0] sp_p2_d0;
output [7:0] sp_p3_address0;
output sp_p3_ce0;
output sp_p3_we0;
output [31:0] sp_p3_d0;
output [7:0] u0_p0_address0;
output u0_p0_ce0;
input [31:0] u0_p0_q0;
output [7:0] u0_p1_address0;
output u0_p1_ce0;
input [31:0] u0_p1_q0;
output [7:0] u0_p2_address0;
output u0_p2_ce0;
input [31:0] u0_p2_q0;
output [7:0] u0_p3_address0;
output u0_p3_ce0;
input [31:0] u0_p3_q0;
output [7:0] u0_p3_address1;
output u0_p3_ce1;
input [31:0] u0_p3_q1;
output [7:0] u1_p0_address0;
output u1_p0_ce0;
input [31:0] u1_p0_q0;
output [7:0] u1_p1_address0;
output u1_p1_ce0;
input [31:0] u1_p1_q0;
output [7:0] u1_p2_address0;
output u1_p2_ce0;
input [31:0] u1_p2_q0;
output [7:0] u1_p3_address0;
output u1_p3_ce0;
input [31:0] u1_p3_q0;
reg ap_done;
reg ap_idle;
reg sm_p0_ce0;
reg sm_p0_we0;
reg sm_p1_ce0;
reg sm_p1_we0;
reg sm_p2_ce0;
reg sm_p2_we0;
reg sm_p3_ce0;
reg sm_p3_we0;
reg sn_p0_ce0;
reg sn_p0_we0;
reg sn_p1_ce0;
reg sn_p1_we0;
reg sn_p2_ce0;
reg sn_p2_we0;
reg sn_p3_ce0;
reg sn_p3_we0;
reg sp_p0_ce0;
reg sp_p0_we0;
reg sp_p1_ce0;
reg sp_p1_we0;
reg sp_p2_ce0;
reg sp_p2_we0;
reg sp_p3_ce0;
reg sp_p3_we0;
reg u0_p0_ce0;
reg u0_p1_ce0;
reg u0_p2_ce0;
reg u0_p3_ce0;
reg u0_p3_ce1;
reg u1_p0_ce0;
reg u1_p1_ce0;
reg u1_p2_ce0;
reg u1_p3_ce0;
reg [1:0] ap_CS_fsm;
reg [9:0] k_reg_327;
reg [31:0] j_reg_338;
reg [31:0] i_1_reg_349;
wire [0:0] exitcond_fu_433_p2;
reg [0:0] exitcond_reg_540;
reg ap_reg_ppiten_pp0_it0;
reg ap_reg_ppiten_pp0_it1;
reg ap_reg_ppiten_pp0_it2;
reg ap_reg_ppiten_pp0_it3;
reg ap_reg_ppiten_pp0_it4;
reg ap_reg_ppiten_pp0_it5;
reg ap_reg_ppiten_pp0_it6;
reg ap_reg_ppiten_pp0_it7;
reg ap_reg_ppiten_pp0_it8;
reg ap_reg_ppiten_pp0_it9;
reg [0:0] ap_reg_ppstg_exitcond_reg_540_pp0_it1;
reg [0:0] ap_reg_ppstg_exitcond_reg_540_pp0_it2;
reg [0:0] ap_reg_ppstg_exitcond_reg_540_pp0_it3;
reg [0:0] ap_reg_ppstg_exitcond_reg_540_pp0_it4;
reg [0:0] ap_reg_ppstg_exitcond_reg_540_pp0_it5;
reg [0:0] ap_reg_ppstg_exitcond_reg_540_pp0_it6;
reg [0:0] ap_reg_ppstg_exitcond_reg_540_pp0_it7;
reg [0:0] ap_reg_ppstg_exitcond_reg_540_pp0_it8;
reg [9:0] indvar_next_reg_544;
wire [31:0] u1_p0_addr52_cast_fu_471_p1;
reg [31:0] u1_p0_addr52_cast_reg_549;
reg [31:0] ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it1;
reg [31:0] ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it2;
reg [31:0] ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it3;
reg [31:0] ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it4;
reg [31:0] ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it5;
reg [31:0] ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it6;
reg [31:0] ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it7;
reg [31:0] ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it8;
reg [0:0] tmp13_reg_610;
reg [0:0] ap_reg_ppstg_tmp13_reg_610_pp0_it1;
reg [0:0] ap_reg_ppstg_tmp13_reg_610_pp0_it2;
reg [0:0] ap_reg_ppstg_tmp13_reg_610_pp0_it3;
reg [0:0] ap_reg_ppstg_tmp13_reg_610_pp0_it4;
reg [0:0] ap_reg_ppstg_tmp13_reg_610_pp0_it5;
reg [0:0] ap_reg_ppstg_tmp13_reg_610_pp0_it6;
reg [0:0] ap_reg_ppstg_tmp13_reg_610_pp0_it7;
reg [0:0] ap_reg_ppstg_tmp13_reg_610_pp0_it8;
reg [31:0] j_1_reg_614;
reg [31:0] i_reg_619;
reg [31:0] u1_p0_load_reg_624;
reg [31:0] u1_p1_load_reg_629;
reg [31:0] u1_p2_load_reg_634;
reg [31:0] u1_p3_load_reg_639;
reg [31:0] u0_p3_load_reg_644;
reg [31:0] u0_p0_load_reg_649;
reg [31:0] u0_p1_load_reg_656;
reg [31:0] u0_p2_load_reg_663;
reg [31:0] u0_p3_load_1_reg_670;
wire [31:0] grp_fu_361_p2;
reg [31:0] tmp1_reg_676;
wire [31:0] grp_fu_365_p2;
reg [31:0] tmp3_reg_682;
wire [31:0] grp_fu_369_p2;
reg [31:0] tmp5_reg_688;
wire [31:0] grp_fu_373_p2;
reg [31:0] tmp7_reg_694;
wire [31:0] grp_fu_377_p2;
reg [31:0] tmp9_reg_700;
wire [31:0] grp_fu_381_p2;
reg [31:0] tmp11_reg_706;
wire [31:0] grp_fu_385_p2;
reg [31:0] tmp14_reg_712;
wire [31:0] grp_fu_389_p2;
reg [31:0] tmp16_reg_718;
reg [9:0] k_phi_fu_331_p4;
reg [31:0] j_phi_fu_342_p4;
reg [31:0] i_1_phi_fu_353_p4;
wire [31:0] u0_p3_addr49_cast_fu_495_p1;
wire [31:0] grp_fu_393_p2;
wire [31:0] grp_fu_398_p2;
wire [31:0] grp_fu_403_p2;
wire [31:0] grp_fu_408_p2;
wire [31:0] grp_fu_413_p2;
wire [31:0] grp_fu_418_p2;
wire [31:0] grp_fu_423_p2;
wire [31:0] grp_fu_428_p2;
wire [31:0] grp_fu_361_p0;
wire [31:0] grp_fu_361_p1;
wire [31:0] grp_fu_365_p0;
wire [31:0] grp_fu_365_p1;
wire [31:0] grp_fu_369_p0;
wire [31:0] grp_fu_369_p1;
wire [31:0] grp_fu_373_p0;
wire [31:0] grp_fu_373_p1;
wire [31:0] grp_fu_377_p0;
wire [31:0] grp_fu_377_p1;
wire [31:0] grp_fu_381_p0;
wire [31:0] grp_fu_381_p1;
wire [31:0] grp_fu_385_p0;
wire [31:0] grp_fu_385_p1;
wire [31:0] grp_fu_389_p0;
wire [31:0] grp_fu_389_p1;
wire [31:0] grp_fu_393_p0;
wire [31:0] grp_fu_393_p1;
wire [31:0] grp_fu_398_p0;
wire [31:0] grp_fu_398_p1;
wire [31:0] grp_fu_403_p0;
wire [31:0] grp_fu_403_p1;
wire [31:0] grp_fu_408_p0;
wire [31:0] grp_fu_408_p1;
wire [31:0] grp_fu_413_p0;
wire [31:0] grp_fu_413_p1;
wire [31:0] grp_fu_418_p0;
wire [31:0] grp_fu_418_p1;
wire [31:0] grp_fu_423_p0;
wire [31:0] grp_fu_423_p1;
wire [31:0] grp_fu_428_p0;
wire [31:0] grp_fu_428_p1;
wire [9:0] exitcond_fu_433_p1;
wire [7:0] i_1_cast_fu_449_p1;
wire [7:0] p_shl_fu_453_p2;
wire [7:0] u1_p0_addr_cast_fu_459_p2;
wire [7:0] j_cast_fu_445_p1;
wire [7:0] u1_p0_addr_fu_465_p2;
wire [7:0] tmp_fu_483_p2;
wire [7:0] u0_p3_addr_fu_489_p2;
wire [31:0] tmp13_fu_500_p1;
wire [31:0] tmp18_fu_506_p2;
wire [31:0] tmp19_fu_512_p1;
wire [0:0] tmp19_fu_512_p2;
wire [31:0] tmp20_fu_518_p2;
wire grp_fu_361_ce;
wire grp_fu_365_ce;
wire grp_fu_369_ce;
wire grp_fu_373_ce;
wire grp_fu_377_ce;
wire grp_fu_381_ce;
wire grp_fu_385_ce;
wire grp_fu_389_ce;
wire grp_fu_393_ce;
wire grp_fu_398_ce;
wire grp_fu_403_ce;
wire grp_fu_408_ce;
wire grp_fu_413_ce;
wire grp_fu_418_ce;
wire grp_fu_423_ce;
wire grp_fu_428_ce;
reg [1:0] ap_NS_fsm;
parameter ap_const_logic_1 = 1'b1;
parameter ap_const_logic_0 = 1'b0;
parameter ap_ST_st0_fsm_0 = 2'b00;
parameter ap_ST_st1_fsm_1 = 2'b01;
parameter ap_ST_pp0_stg0_fsm_2 = 2'b10;
parameter ap_ST_st12_fsm_3 = 2'b11;
parameter ap_const_lv1_0 = 1'b0;
parameter ap_const_lv10_0 = 10'b0000000000;
parameter ap_const_lv32_1 = 32'b00000000000000000000000000000001;
parameter ap_const_lv32_0 = 32'b00000000000000000000000000000000;
parameter ap_const_lv10_375 = 10'b1101110101;
parameter ap_const_lv10_1 = 10'b0000000001;
parameter ap_const_lv8_4 = 8'b00000100;
parameter ap_const_lv8_FF = 8'b11111111;
parameter ap_const_lv32_38 = 32'b00000000000000000000000000111000;
parameter ap_const_lv32_4 = 32'b00000000000000000000000000000100;
parameter ap_const_lv32_3D = 32'b00000000000000000000000000111101;
parameter ap_true = 1'b1;
computeDiffSqr_grp_fu_361_ACMP_fsub_6 #(
.ID( 6 ),
.NUM_STAGE( 4 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
computeDiffSqr_grp_fu_361_ACMP_fsub_6_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_361_p0 ),
.din1( grp_fu_361_p1 ),
.ce( grp_fu_361_ce ),
.dout( grp_fu_361_p2 )
);
computeDiffSqr_grp_fu_365_ACMP_fsub_7 #(
.ID( 7 ),
.NUM_STAGE( 4 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
computeDiffSqr_grp_fu_365_ACMP_fsub_7_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_365_p0 ),
.din1( grp_fu_365_p1 ),
.ce( grp_fu_365_ce ),
.dout( grp_fu_365_p2 )
);
computeDiffSqr_grp_fu_369_ACMP_fsub_8 #(
.ID( 8 ),
.NUM_STAGE( 4 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
computeDiffSqr_grp_fu_369_ACMP_fsub_8_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_369_p0 ),
.din1( grp_fu_369_p1 ),
.ce( grp_fu_369_ce ),
.dout( grp_fu_369_p2 )
);
computeDiffSqr_grp_fu_373_ACMP_fsub_9 #(
.ID( 9 ),
.NUM_STAGE( 4 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
computeDiffSqr_grp_fu_373_ACMP_fsub_9_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_373_p0 ),
.din1( grp_fu_373_p1 ),
.ce( grp_fu_373_ce ),
.dout( grp_fu_373_p2 )
);
computeDiffSqr_grp_fu_377_ACMP_fsub_10 #(
.ID( 10 ),
.NUM_STAGE( 4 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
computeDiffSqr_grp_fu_377_ACMP_fsub_10_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_377_p0 ),
.din1( grp_fu_377_p1 ),
.ce( grp_fu_377_ce ),
.dout( grp_fu_377_p2 )
);
computeDiffSqr_grp_fu_381_ACMP_fsub_11 #(
.ID( 11 ),
.NUM_STAGE( 4 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
computeDiffSqr_grp_fu_381_ACMP_fsub_11_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_381_p0 ),
.din1( grp_fu_381_p1 ),
.ce( grp_fu_381_ce ),
.dout( grp_fu_381_p2 )
);
computeDiffSqr_grp_fu_385_ACMP_fsub_12 #(
.ID( 12 ),
.NUM_STAGE( 4 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
computeDiffSqr_grp_fu_385_ACMP_fsub_12_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_385_p0 ),
.din1( grp_fu_385_p1 ),
.ce( grp_fu_385_ce ),
.dout( grp_fu_385_p2 )
);
computeDiffSqr_grp_fu_389_ACMP_fsub_13 #(
.ID( 13 ),
.NUM_STAGE( 4 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
computeDiffSqr_grp_fu_389_ACMP_fsub_13_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_389_p0 ),
.din1( grp_fu_389_p1 ),
.ce( grp_fu_389_ce ),
.dout( grp_fu_389_p2 )
);
computeDiffSqr_grp_fu_393_ACMP_fmul_14 #(
.ID( 14 ),
.NUM_STAGE( 4 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
computeDiffSqr_grp_fu_393_ACMP_fmul_14_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_393_p0 ),
.din1( grp_fu_393_p1 ),
.ce( grp_fu_393_ce ),
.dout( grp_fu_393_p2 )
);
computeDiffSqr_grp_fu_398_ACMP_fmul_15 #(
.ID( 15 ),
.NUM_STAGE( 4 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
computeDiffSqr_grp_fu_398_ACMP_fmul_15_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_398_p0 ),
.din1( grp_fu_398_p1 ),
.ce( grp_fu_398_ce ),
.dout( grp_fu_398_p2 )
);
computeDiffSqr_grp_fu_403_ACMP_fmul_16 #(
.ID( 16 ),
.NUM_STAGE( 4 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
computeDiffSqr_grp_fu_403_ACMP_fmul_16_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_403_p0 ),
.din1( grp_fu_403_p1 ),
.ce( grp_fu_403_ce ),
.dout( grp_fu_403_p2 )
);
computeDiffSqr_grp_fu_408_ACMP_fmul_17 #(
.ID( 17 ),
.NUM_STAGE( 4 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
computeDiffSqr_grp_fu_408_ACMP_fmul_17_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_408_p0 ),
.din1( grp_fu_408_p1 ),
.ce( grp_fu_408_ce ),
.dout( grp_fu_408_p2 )
);
computeDiffSqr_grp_fu_413_ACMP_fmul_18 #(
.ID( 18 ),
.NUM_STAGE( 4 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
computeDiffSqr_grp_fu_413_ACMP_fmul_18_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_413_p0 ),
.din1( grp_fu_413_p1 ),
.ce( grp_fu_413_ce ),
.dout( grp_fu_413_p2 )
);
computeDiffSqr_grp_fu_418_ACMP_fmul_19 #(
.ID( 19 ),
.NUM_STAGE( 4 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
computeDiffSqr_grp_fu_418_ACMP_fmul_19_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_418_p0 ),
.din1( grp_fu_418_p1 ),
.ce( grp_fu_418_ce ),
.dout( grp_fu_418_p2 )
);
computeDiffSqr_grp_fu_423_ACMP_fmul_20 #(
.ID( 20 ),
.NUM_STAGE( 4 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
computeDiffSqr_grp_fu_423_ACMP_fmul_20_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_423_p0 ),
.din1( grp_fu_423_p1 ),
.ce( grp_fu_423_ce ),
.dout( grp_fu_423_p2 )
);
computeDiffSqr_grp_fu_428_ACMP_fmul_21 #(
.ID( 21 ),
.NUM_STAGE( 4 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
computeDiffSqr_grp_fu_428_ACMP_fmul_21_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_428_p0 ),
.din1( grp_fu_428_p1 ),
.ce( grp_fu_428_ce ),
.dout( grp_fu_428_p2 )
);
/// ap_CS_fsm assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_CS_fsm
if (ap_rst == 1'b1) begin
ap_CS_fsm <= ap_ST_st0_fsm_0;
end else begin
ap_CS_fsm <= ap_NS_fsm;
end
end
/// ap_reg_ppiten_pp0_it0 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it0
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it0 <= ap_const_logic_0;
end else begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & ~(exitcond_fu_433_p2 == ap_const_lv1_0))) begin
ap_reg_ppiten_pp0_it0 <= ap_const_logic_0;
end else if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it0 <= ap_const_logic_1;
end
end
end
/// ap_reg_ppiten_pp0_it1 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it1
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it1 <= ap_const_logic_0;
end else begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (exitcond_fu_433_p2 == ap_const_lv1_0))) begin
ap_reg_ppiten_pp0_it1 <= ap_const_logic_1;
end else if (((ap_ST_st1_fsm_1 == ap_CS_fsm) | ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & ~(exitcond_fu_433_p2 == ap_const_lv1_0)))) begin
ap_reg_ppiten_pp0_it1 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp0_it2 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it2
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it2 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it2 <= ap_reg_ppiten_pp0_it1;
end else if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it2 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp0_it3 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it3
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it3 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it3 <= ap_reg_ppiten_pp0_it2;
end else if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it3 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp0_it4 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it4
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it4 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it4 <= ap_reg_ppiten_pp0_it3;
end else if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it4 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp0_it5 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it5
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it5 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it5 <= ap_reg_ppiten_pp0_it4;
end else if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it5 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp0_it6 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it6
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it6 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it6 <= ap_reg_ppiten_pp0_it5;
end else if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it6 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp0_it7 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it7
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it7 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it7 <= ap_reg_ppiten_pp0_it6;
end else if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it7 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp0_it8 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it8
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it8 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it8 <= ap_reg_ppiten_pp0_it7;
end else if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it8 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp0_it9 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it9
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it9 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it9 <= ap_reg_ppiten_pp0_it8;
end else if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it9 <= ap_const_logic_0;
end
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond_reg_540_pp0_it1 <= exitcond_reg_540;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond_reg_540_pp0_it2 <= ap_reg_ppstg_exitcond_reg_540_pp0_it1;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond_reg_540_pp0_it3 <= ap_reg_ppstg_exitcond_reg_540_pp0_it2;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond_reg_540_pp0_it4 <= ap_reg_ppstg_exitcond_reg_540_pp0_it3;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond_reg_540_pp0_it5 <= ap_reg_ppstg_exitcond_reg_540_pp0_it4;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond_reg_540_pp0_it6 <= ap_reg_ppstg_exitcond_reg_540_pp0_it5;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond_reg_540_pp0_it7 <= ap_reg_ppstg_exitcond_reg_540_pp0_it6;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond_reg_540_pp0_it8 <= ap_reg_ppstg_exitcond_reg_540_pp0_it7;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp13_reg_610_pp0_it1 <= tmp13_reg_610;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp13_reg_610_pp0_it2 <= ap_reg_ppstg_tmp13_reg_610_pp0_it1;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp13_reg_610_pp0_it3 <= ap_reg_ppstg_tmp13_reg_610_pp0_it2;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp13_reg_610_pp0_it4 <= ap_reg_ppstg_tmp13_reg_610_pp0_it3;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp13_reg_610_pp0_it5 <= ap_reg_ppstg_tmp13_reg_610_pp0_it4;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp13_reg_610_pp0_it6 <= ap_reg_ppstg_tmp13_reg_610_pp0_it5;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp13_reg_610_pp0_it7 <= ap_reg_ppstg_tmp13_reg_610_pp0_it6;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp13_reg_610_pp0_it8 <= ap_reg_ppstg_tmp13_reg_610_pp0_it7;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it1[0] <= u1_p0_addr52_cast_reg_549[0];
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it1[1] <= u1_p0_addr52_cast_reg_549[1];
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it1[2] <= u1_p0_addr52_cast_reg_549[2];
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it1[3] <= u1_p0_addr52_cast_reg_549[3];
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it1[4] <= u1_p0_addr52_cast_reg_549[4];
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it1[5] <= u1_p0_addr52_cast_reg_549[5];
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it1[6] <= u1_p0_addr52_cast_reg_549[6];
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it1[7] <= u1_p0_addr52_cast_reg_549[7];
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it2[0] <= ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it1[0];
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it2[1] <= ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it1[1];
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it2[2] <= ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it1[2];
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it2[3] <= ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it1[3];
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it2[4] <= ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it1[4];
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it2[5] <= ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it1[5];
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it2[6] <= ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it1[6];
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it2[7] <= ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it1[7];
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it3[0] <= ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it2[0];
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it3[1] <= ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it2[1];
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it3[2] <= ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it2[2];
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it3[3] <= ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it2[3];
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it3[4] <= ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it2[4];
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it3[5] <= ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it2[5];
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it3[6] <= ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it2[6];
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it3[7] <= ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it2[7];
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it4[0] <= ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it3[0];
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it4[1] <= ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it3[1];
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it4[2] <= ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it3[2];
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it4[3] <= ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it3[3];
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it4[4] <= ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it3[4];
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it4[5] <= ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it3[5];
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it4[6] <= ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it3[6];
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it4[7] <= ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it3[7];
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it5[0] <= ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it4[0];
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it5[1] <= ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it4[1];
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it5[2] <= ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it4[2];
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it5[3] <= ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it4[3];
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it5[4] <= ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it4[4];
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it5[5] <= ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it4[5];
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it5[6] <= ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it4[6];
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it5[7] <= ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it4[7];
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it6[0] <= ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it5[0];
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it6[1] <= ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it5[1];
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it6[2] <= ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it5[2];
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it6[3] <= ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it5[3];
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it6[4] <= ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it5[4];
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it6[5] <= ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it5[5];
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it6[6] <= ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it5[6];
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it6[7] <= ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it5[7];
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it7[0] <= ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it6[0];
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it7[1] <= ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it6[1];
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it7[2] <= ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it6[2];
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it7[3] <= ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it6[3];
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it7[4] <= ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it6[4];
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it7[5] <= ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it6[5];
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it7[6] <= ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it6[6];
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it7[7] <= ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it6[7];
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it8[0] <= ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it7[0];
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it8[1] <= ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it7[1];
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it8[2] <= ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it7[2];
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it8[3] <= ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it7[3];
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it8[4] <= ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it7[4];
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it8[5] <= ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it7[5];
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it8[6] <= ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it7[6];
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it8[7] <= ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it7[7];
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0))) begin
exitcond_reg_540 <= (k_phi_fu_331_p4 == exitcond_fu_433_p1? 1'b1: 1'b0);
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (exitcond_reg_540 == ap_const_lv1_0))) begin
i_1_reg_349 <= i_reg_619;
end else if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
i_1_reg_349 <= ap_const_lv32_1;
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_fu_433_p2 == ap_const_lv1_0))) begin
if (tmp19_fu_512_p2) begin
i_reg_619 <= tmp20_fu_518_p2;
end else begin
i_reg_619 <= i_1_phi_fu_353_p4;
end
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0))) begin
indvar_next_reg_544 <= (k_phi_fu_331_p4 + ap_const_lv10_1);
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_fu_433_p2 == ap_const_lv1_0))) begin
if (tmp19_fu_512_p2) begin
j_1_reg_614 <= ap_const_lv32_1;
end else begin
j_1_reg_614 <= tmp18_fu_506_p2;
end
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (exitcond_reg_540 == ap_const_lv1_0))) begin
j_reg_338 <= j_1_reg_614;
end else if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
j_reg_338 <= ap_const_lv32_1;
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (exitcond_reg_540 == ap_const_lv1_0))) begin
k_reg_327 <= indvar_next_reg_544;
end else if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
k_reg_327 <= ap_const_lv10_0;
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it5) & (ap_reg_ppstg_exitcond_reg_540_pp0_it4 == ap_const_lv1_0))) begin
tmp11_reg_706 <= grp_fu_381_p2;
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_fu_433_p2 == ap_const_lv1_0))) begin
tmp13_reg_610 <= ($signed(j_phi_fu_342_p4) > $signed(tmp13_fu_500_p1)? 1'b1: 1'b0);
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it5) & (ap_reg_ppstg_exitcond_reg_540_pp0_it4 == ap_const_lv1_0) & (ap_const_lv1_0 == ap_reg_ppstg_tmp13_reg_610_pp0_it4))) begin
tmp14_reg_712 <= grp_fu_385_p2;
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it5) & (ap_reg_ppstg_exitcond_reg_540_pp0_it4 == ap_const_lv1_0) & (ap_const_lv1_0 == ap_reg_ppstg_tmp13_reg_610_pp0_it4))) begin
tmp16_reg_718 <= grp_fu_389_p2;
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it5) & (ap_reg_ppstg_exitcond_reg_540_pp0_it4 == ap_const_lv1_0))) begin
tmp1_reg_676 <= grp_fu_361_p2;
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it5) & (ap_reg_ppstg_exitcond_reg_540_pp0_it4 == ap_const_lv1_0))) begin
tmp3_reg_682 <= grp_fu_365_p2;
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it5) & (ap_reg_ppstg_exitcond_reg_540_pp0_it4 == ap_const_lv1_0))) begin
tmp5_reg_688 <= grp_fu_369_p2;
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it5) & (ap_reg_ppstg_exitcond_reg_540_pp0_it4 == ap_const_lv1_0))) begin
tmp7_reg_694 <= grp_fu_373_p2;
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it5) & (ap_reg_ppstg_exitcond_reg_540_pp0_it4 == ap_const_lv1_0))) begin
tmp9_reg_700 <= grp_fu_377_p2;
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (exitcond_reg_540 == ap_const_lv1_0))) begin
u0_p0_load_reg_649 <= u0_p0_q0;
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (exitcond_reg_540 == ap_const_lv1_0))) begin
u0_p1_load_reg_656 <= u0_p1_q0;
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (exitcond_reg_540 == ap_const_lv1_0))) begin
u0_p2_load_reg_663 <= u0_p2_q0;
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (exitcond_reg_540 == ap_const_lv1_0))) begin
u0_p3_load_1_reg_670 <= u0_p3_q1;
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (exitcond_reg_540 == ap_const_lv1_0))) begin
u0_p3_load_reg_644 <= u0_p3_q0;
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_fu_433_p2 == ap_const_lv1_0))) begin
u1_p0_addr52_cast_reg_549[0] <= u1_p0_addr52_cast_fu_471_p1[0];
u1_p0_addr52_cast_reg_549[1] <= u1_p0_addr52_cast_fu_471_p1[1];
u1_p0_addr52_cast_reg_549[2] <= u1_p0_addr52_cast_fu_471_p1[2];
u1_p0_addr52_cast_reg_549[3] <= u1_p0_addr52_cast_fu_471_p1[3];
u1_p0_addr52_cast_reg_549[4] <= u1_p0_addr52_cast_fu_471_p1[4];
u1_p0_addr52_cast_reg_549[5] <= u1_p0_addr52_cast_fu_471_p1[5];
u1_p0_addr52_cast_reg_549[6] <= u1_p0_addr52_cast_fu_471_p1[6];
u1_p0_addr52_cast_reg_549[7] <= u1_p0_addr52_cast_fu_471_p1[7];
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (exitcond_reg_540 == ap_const_lv1_0))) begin
u1_p0_load_reg_624 <= u1_p0_q0;
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (exitcond_reg_540 == ap_const_lv1_0))) begin
u1_p1_load_reg_629 <= u1_p1_q0;
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (exitcond_reg_540 == ap_const_lv1_0))) begin
u1_p2_load_reg_634 <= u1_p2_q0;
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (exitcond_reg_540 == ap_const_lv1_0))) begin
u1_p3_load_reg_639 <= u1_p3_q0;
end
end
/// ap_NS_fsm assign process. ///
always @ (ap_start or ap_CS_fsm or exitcond_fu_433_p2 or ap_reg_ppiten_pp0_it0 or ap_reg_ppiten_pp0_it1 or ap_reg_ppiten_pp0_it8 or ap_reg_ppiten_pp0_it9)
begin
if ((((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it9) & ~(ap_const_logic_1 == ap_reg_ppiten_pp0_it8)) | ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ~(exitcond_fu_433_p2 == ap_const_lv1_0) & ~(ap_const_logic_1 == ap_reg_ppiten_pp0_it1)))) begin
ap_NS_fsm = ap_ST_st12_fsm_3;
end else if ((~(ap_const_logic_1 == ap_start) & (ap_ST_st12_fsm_3 == ap_CS_fsm))) begin
ap_NS_fsm = ap_ST_st0_fsm_0;
end else if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_pp0_stg0_fsm_2;
end else if ((((ap_ST_st0_fsm_0 == ap_CS_fsm) & (ap_const_logic_1 == ap_start)) | ((ap_const_logic_1 == ap_start) & (ap_ST_st12_fsm_3 == ap_CS_fsm)))) begin
ap_NS_fsm = ap_ST_st1_fsm_1;
end else begin
ap_NS_fsm = ap_CS_fsm;
end
end
/// ap_done assign process. ///
always @ (ap_CS_fsm)
begin
if (((ap_ST_st0_fsm_0 == ap_CS_fsm) | (ap_ST_st12_fsm_3 == ap_CS_fsm))) begin
ap_done = ap_const_logic_1;
end else begin
ap_done = ap_const_logic_0;
end
end
/// ap_idle assign process. ///
always @ (ap_CS_fsm)
begin
if ((ap_ST_st0_fsm_0 == ap_CS_fsm)) begin
ap_idle = ap_const_logic_1;
end else begin
ap_idle = ap_const_logic_0;
end
end
/// i_1_phi_fu_353_p4 assign process. ///
always @ (ap_CS_fsm or i_1_reg_349 or exitcond_reg_540 or ap_reg_ppiten_pp0_it1 or i_reg_619)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (exitcond_reg_540 == ap_const_lv1_0))) begin
i_1_phi_fu_353_p4 = i_reg_619;
end else begin
i_1_phi_fu_353_p4 = i_1_reg_349;
end
end
/// j_phi_fu_342_p4 assign process. ///
always @ (ap_CS_fsm or j_reg_338 or exitcond_reg_540 or ap_reg_ppiten_pp0_it1 or j_1_reg_614)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (exitcond_reg_540 == ap_const_lv1_0))) begin
j_phi_fu_342_p4 = j_1_reg_614;
end else begin
j_phi_fu_342_p4 = j_reg_338;
end
end
/// k_phi_fu_331_p4 assign process. ///
always @ (ap_CS_fsm or k_reg_327 or exitcond_reg_540 or ap_reg_ppiten_pp0_it1 or indvar_next_reg_544)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (exitcond_reg_540 == ap_const_lv1_0))) begin
k_phi_fu_331_p4 = indvar_next_reg_544;
end else begin
k_phi_fu_331_p4 = k_reg_327;
end
end
/// sm_p0_ce0 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp0_it9 or ap_reg_ppstg_exitcond_reg_540_pp0_it8)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it9) & (ap_reg_ppstg_exitcond_reg_540_pp0_it8 == ap_const_lv1_0))) begin
sm_p0_ce0 = ap_const_logic_1;
end else begin
sm_p0_ce0 = ap_const_logic_0;
end
end
/// sm_p0_we0 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp0_it9 or ap_reg_ppstg_exitcond_reg_540_pp0_it8)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it9) & (ap_reg_ppstg_exitcond_reg_540_pp0_it8 == ap_const_lv1_0))) begin
sm_p0_we0 = ap_const_logic_1;
end else begin
sm_p0_we0 = ap_const_logic_0;
end
end
/// sm_p1_ce0 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp0_it9 or ap_reg_ppstg_exitcond_reg_540_pp0_it8)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it9) & (ap_reg_ppstg_exitcond_reg_540_pp0_it8 == ap_const_lv1_0))) begin
sm_p1_ce0 = ap_const_logic_1;
end else begin
sm_p1_ce0 = ap_const_logic_0;
end
end
/// sm_p1_we0 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp0_it9 or ap_reg_ppstg_exitcond_reg_540_pp0_it8)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it9) & (ap_reg_ppstg_exitcond_reg_540_pp0_it8 == ap_const_lv1_0))) begin
sm_p1_we0 = ap_const_logic_1;
end else begin
sm_p1_we0 = ap_const_logic_0;
end
end
/// sm_p2_ce0 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp0_it9 or ap_reg_ppstg_exitcond_reg_540_pp0_it8)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it9) & (ap_reg_ppstg_exitcond_reg_540_pp0_it8 == ap_const_lv1_0))) begin
sm_p2_ce0 = ap_const_logic_1;
end else begin
sm_p2_ce0 = ap_const_logic_0;
end
end
/// sm_p2_we0 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp0_it9 or ap_reg_ppstg_exitcond_reg_540_pp0_it8)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it9) & (ap_reg_ppstg_exitcond_reg_540_pp0_it8 == ap_const_lv1_0))) begin
sm_p2_we0 = ap_const_logic_1;
end else begin
sm_p2_we0 = ap_const_logic_0;
end
end
/// sm_p3_ce0 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp0_it9 or ap_reg_ppstg_exitcond_reg_540_pp0_it8 or ap_reg_ppstg_tmp13_reg_610_pp0_it8)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it9) & (ap_reg_ppstg_exitcond_reg_540_pp0_it8 == ap_const_lv1_0) & (ap_const_lv1_0 == ap_reg_ppstg_tmp13_reg_610_pp0_it8))) begin
sm_p3_ce0 = ap_const_logic_1;
end else begin
sm_p3_ce0 = ap_const_logic_0;
end
end
/// sm_p3_we0 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp0_it9 or ap_reg_ppstg_exitcond_reg_540_pp0_it8 or ap_reg_ppstg_tmp13_reg_610_pp0_it8)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it9) & (ap_reg_ppstg_exitcond_reg_540_pp0_it8 == ap_const_lv1_0) & (ap_const_lv1_0 == ap_reg_ppstg_tmp13_reg_610_pp0_it8))) begin
sm_p3_we0 = ap_const_logic_1;
end else begin
sm_p3_we0 = ap_const_logic_0;
end
end
/// sn_p0_ce0 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp0_it9 or ap_reg_ppstg_exitcond_reg_540_pp0_it8)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it9) & (ap_reg_ppstg_exitcond_reg_540_pp0_it8 == ap_const_lv1_0))) begin
sn_p0_ce0 = ap_const_logic_1;
end else begin
sn_p0_ce0 = ap_const_logic_0;
end
end
/// sn_p0_we0 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp0_it9 or ap_reg_ppstg_exitcond_reg_540_pp0_it8)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it9) & (ap_reg_ppstg_exitcond_reg_540_pp0_it8 == ap_const_lv1_0))) begin
sn_p0_we0 = ap_const_logic_1;
end else begin
sn_p0_we0 = ap_const_logic_0;
end
end
/// sn_p1_ce0 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp0_it9 or ap_reg_ppstg_exitcond_reg_540_pp0_it8)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it9) & (ap_reg_ppstg_exitcond_reg_540_pp0_it8 == ap_const_lv1_0))) begin
sn_p1_ce0 = ap_const_logic_1;
end else begin
sn_p1_ce0 = ap_const_logic_0;
end
end
/// sn_p1_we0 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp0_it9 or ap_reg_ppstg_exitcond_reg_540_pp0_it8)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it9) & (ap_reg_ppstg_exitcond_reg_540_pp0_it8 == ap_const_lv1_0))) begin
sn_p1_we0 = ap_const_logic_1;
end else begin
sn_p1_we0 = ap_const_logic_0;
end
end
/// sn_p2_ce0 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp0_it9 or ap_reg_ppstg_exitcond_reg_540_pp0_it8)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it9) & (ap_reg_ppstg_exitcond_reg_540_pp0_it8 == ap_const_lv1_0))) begin
sn_p2_ce0 = ap_const_logic_1;
end else begin
sn_p2_ce0 = ap_const_logic_0;
end
end
/// sn_p2_we0 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp0_it9 or ap_reg_ppstg_exitcond_reg_540_pp0_it8)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it9) & (ap_reg_ppstg_exitcond_reg_540_pp0_it8 == ap_const_lv1_0))) begin
sn_p2_we0 = ap_const_logic_1;
end else begin
sn_p2_we0 = ap_const_logic_0;
end
end
/// sn_p3_ce0 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp0_it9 or ap_reg_ppstg_exitcond_reg_540_pp0_it8 or ap_reg_ppstg_tmp13_reg_610_pp0_it8)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it9) & (ap_reg_ppstg_exitcond_reg_540_pp0_it8 == ap_const_lv1_0) & (ap_const_lv1_0 == ap_reg_ppstg_tmp13_reg_610_pp0_it8))) begin
sn_p3_ce0 = ap_const_logic_1;
end else begin
sn_p3_ce0 = ap_const_logic_0;
end
end
/// sn_p3_we0 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp0_it9 or ap_reg_ppstg_exitcond_reg_540_pp0_it8 or ap_reg_ppstg_tmp13_reg_610_pp0_it8)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it9) & (ap_reg_ppstg_exitcond_reg_540_pp0_it8 == ap_const_lv1_0) & (ap_const_lv1_0 == ap_reg_ppstg_tmp13_reg_610_pp0_it8))) begin
sn_p3_we0 = ap_const_logic_1;
end else begin
sn_p3_we0 = ap_const_logic_0;
end
end
/// sp_p0_ce0 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp0_it9 or ap_reg_ppstg_exitcond_reg_540_pp0_it8)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it9) & (ap_reg_ppstg_exitcond_reg_540_pp0_it8 == ap_const_lv1_0))) begin
sp_p0_ce0 = ap_const_logic_1;
end else begin
sp_p0_ce0 = ap_const_logic_0;
end
end
/// sp_p0_we0 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp0_it9 or ap_reg_ppstg_exitcond_reg_540_pp0_it8)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it9) & (ap_reg_ppstg_exitcond_reg_540_pp0_it8 == ap_const_lv1_0))) begin
sp_p0_we0 = ap_const_logic_1;
end else begin
sp_p0_we0 = ap_const_logic_0;
end
end
/// sp_p1_ce0 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp0_it9 or ap_reg_ppstg_exitcond_reg_540_pp0_it8)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it9) & (ap_reg_ppstg_exitcond_reg_540_pp0_it8 == ap_const_lv1_0))) begin
sp_p1_ce0 = ap_const_logic_1;
end else begin
sp_p1_ce0 = ap_const_logic_0;
end
end
/// sp_p1_we0 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp0_it9 or ap_reg_ppstg_exitcond_reg_540_pp0_it8)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it9) & (ap_reg_ppstg_exitcond_reg_540_pp0_it8 == ap_const_lv1_0))) begin
sp_p1_we0 = ap_const_logic_1;
end else begin
sp_p1_we0 = ap_const_logic_0;
end
end
/// sp_p2_ce0 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp0_it9 or ap_reg_ppstg_exitcond_reg_540_pp0_it8)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it9) & (ap_reg_ppstg_exitcond_reg_540_pp0_it8 == ap_const_lv1_0))) begin
sp_p2_ce0 = ap_const_logic_1;
end else begin
sp_p2_ce0 = ap_const_logic_0;
end
end
/// sp_p2_we0 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp0_it9 or ap_reg_ppstg_exitcond_reg_540_pp0_it8)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it9) & (ap_reg_ppstg_exitcond_reg_540_pp0_it8 == ap_const_lv1_0))) begin
sp_p2_we0 = ap_const_logic_1;
end else begin
sp_p2_we0 = ap_const_logic_0;
end
end
/// sp_p3_ce0 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp0_it9 or ap_reg_ppstg_exitcond_reg_540_pp0_it8 or ap_reg_ppstg_tmp13_reg_610_pp0_it8)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it9) & (ap_reg_ppstg_exitcond_reg_540_pp0_it8 == ap_const_lv1_0) & (ap_const_lv1_0 == ap_reg_ppstg_tmp13_reg_610_pp0_it8))) begin
sp_p3_ce0 = ap_const_logic_1;
end else begin
sp_p3_ce0 = ap_const_logic_0;
end
end
/// sp_p3_we0 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp0_it9 or ap_reg_ppstg_exitcond_reg_540_pp0_it8 or ap_reg_ppstg_tmp13_reg_610_pp0_it8)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it9) & (ap_reg_ppstg_exitcond_reg_540_pp0_it8 == ap_const_lv1_0) & (ap_const_lv1_0 == ap_reg_ppstg_tmp13_reg_610_pp0_it8))) begin
sp_p3_we0 = ap_const_logic_1;
end else begin
sp_p3_we0 = ap_const_logic_0;
end
end
/// u0_p0_ce0 assign process. ///
always @ (ap_CS_fsm or exitcond_fu_433_p2 or ap_reg_ppiten_pp0_it0)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_fu_433_p2 == ap_const_lv1_0))) begin
u0_p0_ce0 = ap_const_logic_1;
end else begin
u0_p0_ce0 = ap_const_logic_0;
end
end
/// u0_p1_ce0 assign process. ///
always @ (ap_CS_fsm or exitcond_fu_433_p2 or ap_reg_ppiten_pp0_it0)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_fu_433_p2 == ap_const_lv1_0))) begin
u0_p1_ce0 = ap_const_logic_1;
end else begin
u0_p1_ce0 = ap_const_logic_0;
end
end
/// u0_p2_ce0 assign process. ///
always @ (ap_CS_fsm or exitcond_fu_433_p2 or ap_reg_ppiten_pp0_it0)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_fu_433_p2 == ap_const_lv1_0))) begin
u0_p2_ce0 = ap_const_logic_1;
end else begin
u0_p2_ce0 = ap_const_logic_0;
end
end
/// u0_p3_ce0 assign process. ///
always @ (ap_CS_fsm or exitcond_fu_433_p2 or ap_reg_ppiten_pp0_it0)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_fu_433_p2 == ap_const_lv1_0))) begin
u0_p3_ce0 = ap_const_logic_1;
end else begin
u0_p3_ce0 = ap_const_logic_0;
end
end
/// u0_p3_ce1 assign process. ///
always @ (ap_CS_fsm or exitcond_fu_433_p2 or ap_reg_ppiten_pp0_it0)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_fu_433_p2 == ap_const_lv1_0))) begin
u0_p3_ce1 = ap_const_logic_1;
end else begin
u0_p3_ce1 = ap_const_logic_0;
end
end
/// u1_p0_ce0 assign process. ///
always @ (ap_CS_fsm or exitcond_fu_433_p2 or ap_reg_ppiten_pp0_it0)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_fu_433_p2 == ap_const_lv1_0))) begin
u1_p0_ce0 = ap_const_logic_1;
end else begin
u1_p0_ce0 = ap_const_logic_0;
end
end
/// u1_p1_ce0 assign process. ///
always @ (ap_CS_fsm or exitcond_fu_433_p2 or ap_reg_ppiten_pp0_it0)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_fu_433_p2 == ap_const_lv1_0))) begin
u1_p1_ce0 = ap_const_logic_1;
end else begin
u1_p1_ce0 = ap_const_logic_0;
end
end
/// u1_p2_ce0 assign process. ///
always @ (ap_CS_fsm or exitcond_fu_433_p2 or ap_reg_ppiten_pp0_it0)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_fu_433_p2 == ap_const_lv1_0))) begin
u1_p2_ce0 = ap_const_logic_1;
end else begin
u1_p2_ce0 = ap_const_logic_0;
end
end
/// u1_p3_ce0 assign process. ///
always @ (ap_CS_fsm or exitcond_fu_433_p2 or ap_reg_ppiten_pp0_it0)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_fu_433_p2 == ap_const_lv1_0))) begin
u1_p3_ce0 = ap_const_logic_1;
end else begin
u1_p3_ce0 = ap_const_logic_0;
end
end
assign exitcond_fu_433_p1 = ap_const_lv10_375;
assign exitcond_fu_433_p2 = (k_phi_fu_331_p4 == exitcond_fu_433_p1? 1'b1: 1'b0);
assign grp_fu_361_ce = ap_const_logic_1;
assign grp_fu_361_p0 = u0_p0_load_reg_649;
assign grp_fu_361_p1 = u0_p3_load_reg_644;
assign grp_fu_365_ce = ap_const_logic_1;
assign grp_fu_365_p0 = u0_p0_load_reg_649;
assign grp_fu_365_p1 = u1_p0_load_reg_624;
assign grp_fu_369_ce = ap_const_logic_1;
assign grp_fu_369_p0 = u0_p1_load_reg_656;
assign grp_fu_369_p1 = u0_p0_load_reg_649;
assign grp_fu_373_ce = ap_const_logic_1;
assign grp_fu_373_p0 = u0_p1_load_reg_656;
assign grp_fu_373_p1 = u1_p1_load_reg_629;
assign grp_fu_377_ce = ap_const_logic_1;
assign grp_fu_377_p0 = u0_p2_load_reg_663;
assign grp_fu_377_p1 = u0_p1_load_reg_656;
assign grp_fu_381_ce = ap_const_logic_1;
assign grp_fu_381_p0 = u0_p2_load_reg_663;
assign grp_fu_381_p1 = u1_p2_load_reg_634;
assign grp_fu_385_ce = ap_const_logic_1;
assign grp_fu_385_p0 = u0_p3_load_1_reg_670;
assign grp_fu_385_p1 = u0_p2_load_reg_663;
assign grp_fu_389_ce = ap_const_logic_1;
assign grp_fu_389_p0 = u0_p3_load_1_reg_670;
assign grp_fu_389_p1 = u1_p3_load_reg_639;
assign grp_fu_393_ce = ap_const_logic_1;
assign grp_fu_393_p0 = tmp1_reg_676;
assign grp_fu_393_p1 = tmp1_reg_676;
assign grp_fu_398_ce = ap_const_logic_1;
assign grp_fu_398_p0 = tmp3_reg_682;
assign grp_fu_398_p1 = tmp3_reg_682;
assign grp_fu_403_ce = ap_const_logic_1;
assign grp_fu_403_p0 = tmp5_reg_688;
assign grp_fu_403_p1 = tmp5_reg_688;
assign grp_fu_408_ce = ap_const_logic_1;
assign grp_fu_408_p0 = tmp7_reg_694;
assign grp_fu_408_p1 = tmp7_reg_694;
assign grp_fu_413_ce = ap_const_logic_1;
assign grp_fu_413_p0 = tmp9_reg_700;
assign grp_fu_413_p1 = tmp9_reg_700;
assign grp_fu_418_ce = ap_const_logic_1;
assign grp_fu_418_p0 = tmp11_reg_706;
assign grp_fu_418_p1 = tmp11_reg_706;
assign grp_fu_423_ce = ap_const_logic_1;
assign grp_fu_423_p0 = tmp14_reg_712;
assign grp_fu_423_p1 = tmp14_reg_712;
assign grp_fu_428_ce = ap_const_logic_1;
assign grp_fu_428_p0 = tmp16_reg_718;
assign grp_fu_428_p1 = tmp16_reg_718;
assign i_1_cast_fu_449_p1 = i_1_phi_fu_353_p4[7:0];
assign j_cast_fu_445_p1 = j_phi_fu_342_p4[7:0];
assign p_shl_fu_453_p2 = i_1_cast_fu_449_p1 << ap_const_lv8_4;
assign sm_p0_address0 = ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it8;
assign sm_p0_d0 = ap_const_lv32_0;
assign sm_p1_address0 = ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it8;
assign sm_p1_d0 = ap_const_lv32_0;
assign sm_p2_address0 = ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it8;
assign sm_p2_d0 = ap_const_lv32_0;
assign sm_p3_address0 = ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it8;
assign sm_p3_d0 = ap_const_lv32_0;
assign sn_p0_address0 = ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it8;
assign sn_p0_d0 = grp_fu_393_p2;
assign sn_p1_address0 = ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it8;
assign sn_p1_d0 = grp_fu_403_p2;
assign sn_p2_address0 = ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it8;
assign sn_p2_d0 = grp_fu_413_p2;
assign sn_p3_address0 = ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it8;
assign sn_p3_d0 = grp_fu_423_p2;
assign sp_p0_address0 = ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it8;
assign sp_p0_d0 = grp_fu_398_p2;
assign sp_p1_address0 = ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it8;
assign sp_p1_d0 = grp_fu_408_p2;
assign sp_p2_address0 = ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it8;
assign sp_p2_d0 = grp_fu_418_p2;
assign sp_p3_address0 = ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it8;
assign sp_p3_d0 = grp_fu_428_p2;
assign tmp13_fu_500_p1 = ap_const_lv32_38;
assign tmp18_fu_506_p2 = (j_phi_fu_342_p4 + ap_const_lv32_4);
assign tmp19_fu_512_p1 = ap_const_lv32_3D;
assign tmp19_fu_512_p2 = (tmp18_fu_506_p2 == tmp19_fu_512_p1? 1'b1: 1'b0);
assign tmp20_fu_518_p2 = (i_1_phi_fu_353_p4 + ap_const_lv32_1);
assign tmp_fu_483_p2 = (j_cast_fu_445_p1 + ap_const_lv8_FF);
assign u0_p0_address0 = u1_p0_addr52_cast_fu_471_p1;
assign u0_p1_address0 = u1_p0_addr52_cast_fu_471_p1;
assign u0_p2_address0 = u1_p0_addr52_cast_fu_471_p1;
assign u0_p3_addr49_cast_fu_495_p1 = {{24{1'b0}}, {u0_p3_addr_fu_489_p2}};
assign u0_p3_addr_fu_489_p2 = (u1_p0_addr_cast_fu_459_p2 + tmp_fu_483_p2);
assign u0_p3_address0 = u0_p3_addr49_cast_fu_495_p1;
assign u0_p3_address1 = u1_p0_addr52_cast_fu_471_p1;
assign u1_p0_addr52_cast_fu_471_p1 = {{24{1'b0}}, {u1_p0_addr_fu_465_p2}};
assign u1_p0_addr_cast_fu_459_p2 = (p_shl_fu_453_p2 - i_1_cast_fu_449_p1);
assign u1_p0_addr_fu_465_p2 = (u1_p0_addr_cast_fu_459_p2 + j_cast_fu_445_p1);
assign u1_p0_address0 = u1_p0_addr52_cast_fu_471_p1;
assign u1_p1_address0 = u1_p0_addr52_cast_fu_471_p1;
assign u1_p2_address0 = u1_p0_addr52_cast_fu_471_p1;
assign u1_p3_address0 = u1_p0_addr52_cast_fu_471_p1;
always @ (ap_clk)
begin
u1_p0_addr52_cast_reg_549[8] <= 1'b0;
u1_p0_addr52_cast_reg_549[9] <= 1'b0;
u1_p0_addr52_cast_reg_549[10] <= 1'b0;
u1_p0_addr52_cast_reg_549[11] <= 1'b0;
u1_p0_addr52_cast_reg_549[12] <= 1'b0;
u1_p0_addr52_cast_reg_549[13] <= 1'b0;
u1_p0_addr52_cast_reg_549[14] <= 1'b0;
u1_p0_addr52_cast_reg_549[15] <= 1'b0;
u1_p0_addr52_cast_reg_549[16] <= 1'b0;
u1_p0_addr52_cast_reg_549[17] <= 1'b0;
u1_p0_addr52_cast_reg_549[18] <= 1'b0;
u1_p0_addr52_cast_reg_549[19] <= 1'b0;
u1_p0_addr52_cast_reg_549[20] <= 1'b0;
u1_p0_addr52_cast_reg_549[21] <= 1'b0;
u1_p0_addr52_cast_reg_549[22] <= 1'b0;
u1_p0_addr52_cast_reg_549[23] <= 1'b0;
u1_p0_addr52_cast_reg_549[24] <= 1'b0;
u1_p0_addr52_cast_reg_549[25] <= 1'b0;
u1_p0_addr52_cast_reg_549[26] <= 1'b0;
u1_p0_addr52_cast_reg_549[27] <= 1'b0;
u1_p0_addr52_cast_reg_549[28] <= 1'b0;
u1_p0_addr52_cast_reg_549[29] <= 1'b0;
u1_p0_addr52_cast_reg_549[30] <= 1'b0;
u1_p0_addr52_cast_reg_549[31] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it1[8] <= 1'b0;
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it1[9] <= 1'b0;
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it1[10] <= 1'b0;
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it1[11] <= 1'b0;
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it1[12] <= 1'b0;
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it1[13] <= 1'b0;
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it1[14] <= 1'b0;
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it1[15] <= 1'b0;
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it1[16] <= 1'b0;
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it1[17] <= 1'b0;
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it1[18] <= 1'b0;
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it1[19] <= 1'b0;
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it1[20] <= 1'b0;
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it1[21] <= 1'b0;
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it1[22] <= 1'b0;
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it1[23] <= 1'b0;
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it1[24] <= 1'b0;
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it1[25] <= 1'b0;
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it1[26] <= 1'b0;
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it1[27] <= 1'b0;
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it1[28] <= 1'b0;
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it1[29] <= 1'b0;
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it1[30] <= 1'b0;
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it1[31] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it2[8] <= 1'b0;
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it2[9] <= 1'b0;
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it2[10] <= 1'b0;
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it2[11] <= 1'b0;
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it2[12] <= 1'b0;
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it2[13] <= 1'b0;
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it2[14] <= 1'b0;
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it2[15] <= 1'b0;
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it2[16] <= 1'b0;
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it2[17] <= 1'b0;
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it2[18] <= 1'b0;
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it2[19] <= 1'b0;
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it2[20] <= 1'b0;
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it2[21] <= 1'b0;
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it2[22] <= 1'b0;
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it2[23] <= 1'b0;
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it2[24] <= 1'b0;
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it2[25] <= 1'b0;
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it2[26] <= 1'b0;
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it2[27] <= 1'b0;
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it2[28] <= 1'b0;
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it2[29] <= 1'b0;
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it2[30] <= 1'b0;
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it2[31] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it3[8] <= 1'b0;
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it3[9] <= 1'b0;
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it3[10] <= 1'b0;
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it3[11] <= 1'b0;
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it3[12] <= 1'b0;
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it3[13] <= 1'b0;
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it3[14] <= 1'b0;
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it3[15] <= 1'b0;
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it3[16] <= 1'b0;
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it3[17] <= 1'b0;
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it3[18] <= 1'b0;
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it3[19] <= 1'b0;
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it3[20] <= 1'b0;
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it3[21] <= 1'b0;
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it3[22] <= 1'b0;
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it3[23] <= 1'b0;
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it3[24] <= 1'b0;
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it3[25] <= 1'b0;
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it3[26] <= 1'b0;
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it3[27] <= 1'b0;
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it3[28] <= 1'b0;
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it3[29] <= 1'b0;
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it3[30] <= 1'b0;
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it3[31] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it4[8] <= 1'b0;
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it4[9] <= 1'b0;
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it4[10] <= 1'b0;
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it4[11] <= 1'b0;
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it4[12] <= 1'b0;
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it4[13] <= 1'b0;
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it4[14] <= 1'b0;
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it4[15] <= 1'b0;
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it4[16] <= 1'b0;
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it4[17] <= 1'b0;
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it4[18] <= 1'b0;
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it4[19] <= 1'b0;
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it4[20] <= 1'b0;
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it4[21] <= 1'b0;
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it4[22] <= 1'b0;
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it4[23] <= 1'b0;
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it4[24] <= 1'b0;
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it4[25] <= 1'b0;
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it4[26] <= 1'b0;
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it4[27] <= 1'b0;
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it4[28] <= 1'b0;
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it4[29] <= 1'b0;
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it4[30] <= 1'b0;
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it4[31] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it5[8] <= 1'b0;
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it5[9] <= 1'b0;
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it5[10] <= 1'b0;
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it5[11] <= 1'b0;
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it5[12] <= 1'b0;
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it5[13] <= 1'b0;
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it5[14] <= 1'b0;
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it5[15] <= 1'b0;
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it5[16] <= 1'b0;
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it5[17] <= 1'b0;
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it5[18] <= 1'b0;
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it5[19] <= 1'b0;
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it5[20] <= 1'b0;
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it5[21] <= 1'b0;
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it5[22] <= 1'b0;
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it5[23] <= 1'b0;
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it5[24] <= 1'b0;
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it5[25] <= 1'b0;
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it5[26] <= 1'b0;
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it5[27] <= 1'b0;
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it5[28] <= 1'b0;
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it5[29] <= 1'b0;
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it5[30] <= 1'b0;
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it5[31] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it6[8] <= 1'b0;
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it6[9] <= 1'b0;
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it6[10] <= 1'b0;
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it6[11] <= 1'b0;
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it6[12] <= 1'b0;
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it6[13] <= 1'b0;
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it6[14] <= 1'b0;
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it6[15] <= 1'b0;
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it6[16] <= 1'b0;
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it6[17] <= 1'b0;
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it6[18] <= 1'b0;
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it6[19] <= 1'b0;
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it6[20] <= 1'b0;
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it6[21] <= 1'b0;
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it6[22] <= 1'b0;
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it6[23] <= 1'b0;
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it6[24] <= 1'b0;
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it6[25] <= 1'b0;
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it6[26] <= 1'b0;
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it6[27] <= 1'b0;
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it6[28] <= 1'b0;
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it6[29] <= 1'b0;
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it6[30] <= 1'b0;
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it6[31] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it7[8] <= 1'b0;
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it7[9] <= 1'b0;
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it7[10] <= 1'b0;
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it7[11] <= 1'b0;
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it7[12] <= 1'b0;
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it7[13] <= 1'b0;
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it7[14] <= 1'b0;
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it7[15] <= 1'b0;
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it7[16] <= 1'b0;
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it7[17] <= 1'b0;
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it7[18] <= 1'b0;
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it7[19] <= 1'b0;
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it7[20] <= 1'b0;
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it7[21] <= 1'b0;
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it7[22] <= 1'b0;
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it7[23] <= 1'b0;
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it7[24] <= 1'b0;
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it7[25] <= 1'b0;
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it7[26] <= 1'b0;
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it7[27] <= 1'b0;
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it7[28] <= 1'b0;
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it7[29] <= 1'b0;
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it7[30] <= 1'b0;
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it7[31] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it8[8] <= 1'b0;
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it8[9] <= 1'b0;
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it8[10] <= 1'b0;
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it8[11] <= 1'b0;
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it8[12] <= 1'b0;
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it8[13] <= 1'b0;
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it8[14] <= 1'b0;
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it8[15] <= 1'b0;
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it8[16] <= 1'b0;
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it8[17] <= 1'b0;
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it8[18] <= 1'b0;
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it8[19] <= 1'b0;
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it8[20] <= 1'b0;
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it8[21] <= 1'b0;
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it8[22] <= 1'b0;
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it8[23] <= 1'b0;
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it8[24] <= 1'b0;
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it8[25] <= 1'b0;
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it8[26] <= 1'b0;
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it8[27] <= 1'b0;
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it8[28] <= 1'b0;
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it8[29] <= 1'b0;
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it8[30] <= 1'b0;
ap_reg_ppstg_u1_p0_addr52_cast_reg_549_pp0_it8[31] <= 1'b0;
end
endmodule //computeDiffSqr
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
module computeDiffSqr_grp_fu_361_ACMP_fsub_6(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fsub #(
.ID( ID ),
.NUM_STAGE( 4 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fsub_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
module computeDiffSqr_grp_fu_365_ACMP_fsub_7(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fsub #(
.ID( ID ),
.NUM_STAGE( 4 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fsub_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
module computeDiffSqr_grp_fu_369_ACMP_fsub_8(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fsub #(
.ID( ID ),
.NUM_STAGE( 4 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fsub_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
module computeDiffSqr_grp_fu_373_ACMP_fsub_9(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fsub #(
.ID( ID ),
.NUM_STAGE( 4 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fsub_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
module computeDiffSqr_grp_fu_377_ACMP_fsub_10(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fsub #(
.ID( ID ),
.NUM_STAGE( 4 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fsub_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
module computeDiffSqr_grp_fu_381_ACMP_fsub_11(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fsub #(
.ID( ID ),
.NUM_STAGE( 4 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fsub_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
module computeDiffSqr_grp_fu_385_ACMP_fsub_12(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fsub #(
.ID( ID ),
.NUM_STAGE( 4 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fsub_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
module computeDiffSqr_grp_fu_389_ACMP_fsub_13(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fsub #(
.ID( ID ),
.NUM_STAGE( 4 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fsub_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
module computeDiffSqr_grp_fu_393_ACMP_fmul_14(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fmul #(
.ID( ID ),
.NUM_STAGE( 4 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fmul_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
module computeDiffSqr_grp_fu_398_ACMP_fmul_15(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fmul #(
.ID( ID ),
.NUM_STAGE( 4 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fmul_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
module computeDiffSqr_grp_fu_403_ACMP_fmul_16(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fmul #(
.ID( ID ),
.NUM_STAGE( 4 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fmul_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
module computeDiffSqr_grp_fu_408_ACMP_fmul_17(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fmul #(
.ID( ID ),
.NUM_STAGE( 4 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fmul_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
module computeDiffSqr_grp_fu_413_ACMP_fmul_18(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fmul #(
.ID( ID ),
.NUM_STAGE( 4 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fmul_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
module computeDiffSqr_grp_fu_418_ACMP_fmul_19(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fmul #(
.ID( ID ),
.NUM_STAGE( 4 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fmul_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
module computeDiffSqr_grp_fu_423_ACMP_fmul_20(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fmul #(
.ID( ID ),
.NUM_STAGE( 4 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fmul_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
module computeDiffSqr_grp_fu_428_ACMP_fmul_21(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fmul #(
.ID( ID ),
.NUM_STAGE( 4 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fmul_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
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