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// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
module computeGradient_grp_fu_419_ACMP_fadd_50(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fadd #(
.ID( ID ),
.NUM_STAGE( 4 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fadd_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
module computeGradient_grp_fu_423_ACMP_fadd_51(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fadd #(
.ID( ID ),
.NUM_STAGE( 4 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fadd_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
module computeGradient_grp_fu_427_ACMP_fadd_52(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fadd #(
.ID( ID ),
.NUM_STAGE( 4 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fadd_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
module computeGradient_grp_fu_431_ACMP_fadd_53(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fadd #(
.ID( ID ),
.NUM_STAGE( 4 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fadd_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
module computeGradient_grp_fu_435_ACMP_fadd_54(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fadd #(
.ID( ID ),
.NUM_STAGE( 4 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fadd_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
module computeGradient_grp_fu_439_ACMP_fadd_55(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fadd #(
.ID( ID ),
.NUM_STAGE( 4 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fadd_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
module computeGradient_grp_fu_443_ACMP_fadd_56(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fadd #(
.ID( ID ),
.NUM_STAGE( 4 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fadd_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
module computeGradient_grp_fu_447_ACMP_fadd_57(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fadd #(
.ID( ID ),
.NUM_STAGE( 4 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fadd_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
module computeGradient_grp_fu_451_ACMP_fadd_58(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fadd #(
.ID( ID ),
.NUM_STAGE( 4 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fadd_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
module computeGradient_grp_fu_455_ACMP_fadd_59(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fadd #(
.ID( ID ),
.NUM_STAGE( 4 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fadd_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
module computeGradient_grp_fu_459_ACMP_fadd_60(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fadd #(
.ID( ID ),
.NUM_STAGE( 4 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fadd_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
module computeGradient_grp_fu_463_ACMP_fadd_61(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fadd #(
.ID( ID ),
.NUM_STAGE( 4 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fadd_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
module computeGradient_grp_fu_467_ACMP_fadd_62(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fadd #(
.ID( ID ),
.NUM_STAGE( 4 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fadd_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
module computeGradient_grp_fu_471_ACMP_fadd_63(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fadd #(
.ID( ID ),
.NUM_STAGE( 4 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fadd_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
module computeGradient_grp_fu_475_ACMP_fadd_64(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fadd #(
.ID( ID ),
.NUM_STAGE( 4 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fadd_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
module computeGradient_grp_fu_479_ACMP_fadd_65(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fadd #(
.ID( ID ),
.NUM_STAGE( 4 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fadd_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
module computeGradient_grp_fu_483_ACMP_fsqrt_66(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fsqrt #(
.ID( ID ),
.NUM_STAGE( 8 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fsqrt_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
module computeGradient_grp_fu_488_ACMP_fsqrt_67(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fsqrt #(
.ID( ID ),
.NUM_STAGE( 8 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fsqrt_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
module computeGradient_grp_fu_493_ACMP_fsqrt_68(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fsqrt #(
.ID( ID ),
.NUM_STAGE( 8 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fsqrt_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
module computeGradient_grp_fu_498_ACMP_fsqrt_69(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fsqrt #(
.ID( ID ),
.NUM_STAGE( 8 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fsqrt_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// RTL generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ===========================================================
`timescale 1 ns / 1 ps
module computeResult (
ap_clk,
ap_rst,
ap_start,
ap_done,
ap_idle,
r_p0_address0,
r_p0_ce0,
r_p0_we0,
r_p0_d0,
r_p1_address0,
r_p1_ce0,
r_p1_we0,
r_p1_d0,
r_p2_address0,
r_p2_ce0,
r_p2_we0,
r_p2_d0,
r_p3_address0,
r_p3_ce0,
r_p3_we0,
r_p3_d0,
u_p0_address0,
u_p0_ce0,
u_p0_q0,
u_p1_address0,
u_p1_ce0,
u_p1_q0,
u_p2_address0,
u_p2_ce0,
u_p2_q0,
u_p3_address0,
u_p3_ce0,
u_p3_q0,
ug0_p0_address0,
ug0_p0_ce0,
ug0_p0_q0,
ug0_p1_address0,
ug0_p1_ce0,
ug0_p1_q0,
ug0_p2_address0,
ug0_p2_ce0,
ug0_p2_q0,
ug0_p3_address0,
ug0_p3_ce0,
ug0_p3_q0,
ug1_p0_address0,
ug1_p0_ce0,
ug1_p0_q0,
ug1_p0_address1,
ug1_p0_ce1,
ug1_p0_q1,
ug1_p1_address0,
ug1_p1_ce0,
ug1_p1_q0,
ug1_p2_address0,
ug1_p2_ce0,
ug1_p2_q0,
ug1_p3_address0,
ug1_p3_ce0,
ug1_p3_q0,
ug1_p3_address1,
ug1_p3_ce1,
ug1_p3_q1,
ug2_p0_address0,
ug2_p0_ce0,
ug2_p0_q0,
ug2_p1_address0,
ug2_p1_ce0,
ug2_p1_q0,
ug2_p2_address0,
ug2_p2_ce0,
ug2_p2_q0,
ug2_p3_address0,
ug2_p3_ce0,
ug2_p3_q0,
g0_p0_address0,
g0_p0_ce0,
g0_p0_q0,
g0_p1_address0,
g0_p1_ce0,
g0_p1_q0,
g0_p2_address0,
g0_p2_ce0,
g0_p2_q0,
g0_p3_address0,
g0_p3_ce0,
g0_p3_q0,
g1_p0_address0,
g1_p0_ce0,
g1_p0_q0,
g1_p0_address1,
g1_p0_ce1,
g1_p0_q1,
g1_p1_address0,
g1_p1_ce0,
g1_p1_q0,
g1_p2_address0,
g1_p2_ce0,
g1_p2_q0,
g1_p3_address0,
g1_p3_ce0,
g1_p3_q0,
g1_p3_address1,
g1_p3_ce1,
g1_p3_q1,
g2_p0_address0,
g2_p0_ce0,
g2_p0_q0,
g2_p1_address0,
g2_p1_ce0,
g2_p1_q0,
g2_p2_address0,
g2_p2_ce0,
g2_p2_q0,
g2_p3_address0,
g2_p3_ce0,
g2_p3_q0,
f_p0_address0,
f_p0_ce0,
f_p0_q0,
f_p1_address0,
f_p1_ce0,
f_p1_q0,
f_p2_address0,
f_p2_ce0,
f_p2_q0,
f_p3_address0,
f_p3_ce0,
f_p3_q0,
ap_return
);
input ap_clk;
input ap_rst;
input ap_start;
output ap_done;
output ap_idle;
output [7:0] r_p0_address0;
output r_p0_ce0;
output r_p0_we0;
output [31:0] r_p0_d0;
output [7:0] r_p1_address0;
output r_p1_ce0;
output r_p1_we0;
output [31:0] r_p1_d0;
output [7:0] r_p2_address0;
output r_p2_ce0;
output r_p2_we0;
output [31:0] r_p2_d0;
output [7:0] r_p3_address0;
output r_p3_ce0;
output r_p3_we0;
output [31:0] r_p3_d0;
output [7:0] u_p0_address0;
output u_p0_ce0;
input [31:0] u_p0_q0;
output [7:0] u_p1_address0;
output u_p1_ce0;
input [31:0] u_p1_q0;
output [7:0] u_p2_address0;
output u_p2_ce0;
input [31:0] u_p2_q0;
output [7:0] u_p3_address0;
output u_p3_ce0;
input [31:0] u_p3_q0;
output [7:0] ug0_p0_address0;
output ug0_p0_ce0;
input [31:0] ug0_p0_q0;
output [7:0] ug0_p1_address0;
output ug0_p1_ce0;
input [31:0] ug0_p1_q0;
output [7:0] ug0_p2_address0;
output ug0_p2_ce0;
input [31:0] ug0_p2_q0;
output [7:0] ug0_p3_address0;
output ug0_p3_ce0;
input [31:0] ug0_p3_q0;
output [7:0] ug1_p0_address0;
output ug1_p0_ce0;
input [31:0] ug1_p0_q0;
output [7:0] ug1_p0_address1;
output ug1_p0_ce1;
input [31:0] ug1_p0_q1;
output [7:0] ug1_p1_address0;
output ug1_p1_ce0;
input [31:0] ug1_p1_q0;
output [7:0] ug1_p2_address0;
output ug1_p2_ce0;
input [31:0] ug1_p2_q0;
output [7:0] ug1_p3_address0;
output ug1_p3_ce0;
input [31:0] ug1_p3_q0;
output [7:0] ug1_p3_address1;
output ug1_p3_ce1;
input [31:0] ug1_p3_q1;
output [7:0] ug2_p0_address0;
output ug2_p0_ce0;
input [31:0] ug2_p0_q0;
output [7:0] ug2_p1_address0;
output ug2_p1_ce0;
input [31:0] ug2_p1_q0;
output [7:0] ug2_p2_address0;
output ug2_p2_ce0;
input [31:0] ug2_p2_q0;
output [7:0] ug2_p3_address0;
output ug2_p3_ce0;
input [31:0] ug2_p3_q0;
output [7:0] g0_p0_address0;
output g0_p0_ce0;
input [31:0] g0_p0_q0;
output [7:0] g0_p1_address0;
output g0_p1_ce0;
input [31:0] g0_p1_q0;
output [7:0] g0_p2_address0;
output g0_p2_ce0;
input [31:0] g0_p2_q0;
output [7:0] g0_p3_address0;
output g0_p3_ce0;
input [31:0] g0_p3_q0;
output [7:0] g1_p0_address0;
output g1_p0_ce0;
input [31:0] g1_p0_q0;
output [7:0] g1_p0_address1;
output g1_p0_ce1;
input [31:0] g1_p0_q1;
output [7:0] g1_p1_address0;
output g1_p1_ce0;
input [31:0] g1_p1_q0;
output [7:0] g1_p2_address0;
output g1_p2_ce0;
input [31:0] g1_p2_q0;
output [7:0] g1_p3_address0;
output g1_p3_ce0;
input [31:0] g1_p3_q0;
output [7:0] g1_p3_address1;
output g1_p3_ce1;
input [31:0] g1_p3_q1;
output [7:0] g2_p0_address0;
output g2_p0_ce0;
input [31:0] g2_p0_q0;
output [7:0] g2_p1_address0;
output g2_p1_ce0;
input [31:0] g2_p1_q0;
output [7:0] g2_p2_address0;
output g2_p2_ce0;
input [31:0] g2_p2_q0;
output [7:0] g2_p3_address0;
output g2_p3_ce0;
input [31:0] g2_p3_q0;
output [7:0] f_p0_address0;
output f_p0_ce0;
input [31:0] f_p0_q0;
output [7:0] f_p1_address0;
output f_p1_ce0;
input [31:0] f_p1_q0;
output [7:0] f_p2_address0;
output f_p2_ce0;
input [31:0] f_p2_q0;
output [7:0] f_p3_address0;
output f_p3_ce0;
input [31:0] f_p3_q0;
output [0:0] ap_return;
reg ap_done;
reg ap_idle;
reg r_p0_ce0;
reg r_p0_we0;
reg r_p1_ce0;
reg r_p1_we0;
reg r_p2_ce0;
reg r_p2_we0;
reg r_p3_ce0;
reg r_p3_we0;
reg u_p0_ce0;
reg u_p1_ce0;
reg u_p2_ce0;
reg u_p3_ce0;
reg ug0_p0_ce0;
reg ug0_p1_ce0;
reg ug0_p2_ce0;
reg ug0_p3_ce0;
reg ug1_p0_ce0;
reg ug1_p0_ce1;
reg ug1_p1_ce0;
reg ug1_p2_ce0;
reg ug1_p3_ce0;
reg ug1_p3_ce1;
reg ug2_p0_ce0;
reg ug2_p1_ce0;
reg ug2_p2_ce0;
reg ug2_p3_ce0;
reg g0_p0_ce0;
reg g0_p1_ce0;
reg g0_p2_ce0;
reg g0_p3_ce0;
reg g1_p0_ce0;
reg g1_p0_ce1;
reg g1_p1_ce0;
reg g1_p2_ce0;
reg g1_p3_ce0;
reg g1_p3_ce1;
reg g2_p0_ce0;
reg g2_p1_ce0;
reg g2_p2_ce0;
reg g2_p3_ce0;
reg f_p0_ce0;
reg f_p1_ce0;
reg f_p2_ce0;
reg f_p3_ce0;
reg [1:0] ap_CS_fsm;
reg [9:0] k_reg_640;
reg [31:0] j_reg_651;
reg [31:0] i_1_reg_662;
reg [0:0] Convergence_reg_673;
wire [0:0] exitcond_fu_876_p2;
reg [0:0] exitcond_reg_1396;
reg ap_reg_ppiten_pp0_it0;
reg ap_reg_ppiten_pp0_it1;
reg ap_reg_ppiten_pp0_it2;
reg ap_reg_ppiten_pp0_it3;
reg ap_reg_ppiten_pp0_it4;
reg ap_reg_ppiten_pp0_it5;
reg ap_reg_ppiten_pp0_it6;
reg ap_reg_ppiten_pp0_it7;
reg ap_reg_ppiten_pp0_it8;
reg ap_reg_ppiten_pp0_it9;
reg ap_reg_ppiten_pp0_it10;
reg ap_reg_ppiten_pp0_it11;
reg ap_reg_ppiten_pp0_it12;
reg ap_reg_ppiten_pp0_it13;
reg ap_reg_ppiten_pp0_it14;
reg ap_reg_ppiten_pp0_it15;
reg ap_reg_ppiten_pp0_it16;
reg ap_reg_ppiten_pp0_it17;
reg ap_reg_ppiten_pp0_it18;
reg ap_reg_ppiten_pp0_it19;
reg ap_reg_ppiten_pp0_it20;
reg ap_reg_ppiten_pp0_it21;
reg ap_reg_ppiten_pp0_it22;
reg ap_reg_ppiten_pp0_it23;
reg ap_reg_ppiten_pp0_it24;
reg ap_reg_ppiten_pp0_it25;
reg ap_reg_ppiten_pp0_it26;
reg ap_reg_ppiten_pp0_it27;
reg ap_reg_ppiten_pp0_it28;
reg ap_reg_ppiten_pp0_it29;
reg ap_reg_ppiten_pp0_it30;
reg ap_reg_ppiten_pp0_it31;
reg ap_reg_ppiten_pp0_it32;
reg ap_reg_ppiten_pp0_it33;
reg ap_reg_ppiten_pp0_it34;
reg ap_reg_ppiten_pp0_it35;
reg ap_reg_ppiten_pp0_it36;
reg ap_reg_ppiten_pp0_it37;
reg ap_reg_ppiten_pp0_it38;
reg ap_reg_ppiten_pp0_it39;
reg ap_reg_ppiten_pp0_it40;
reg ap_reg_ppiten_pp0_it41;
reg ap_reg_ppiten_pp0_it42;
reg ap_reg_ppiten_pp0_it43;
reg ap_reg_ppiten_pp0_it44;
reg ap_reg_ppiten_pp0_it45;
reg ap_reg_ppiten_pp0_it46;
reg ap_reg_ppiten_pp0_it47;
reg ap_reg_ppiten_pp0_it48;
reg ap_reg_ppiten_pp0_it49;
reg ap_reg_ppiten_pp0_it50;
reg ap_reg_ppiten_pp0_it51;
reg ap_reg_ppiten_pp0_it52;
reg ap_reg_ppiten_pp0_it53;
reg ap_reg_ppiten_pp0_it54;
reg ap_reg_ppiten_pp0_it55;
reg ap_reg_ppiten_pp0_it56;
reg ap_reg_ppiten_pp0_it57;
reg ap_reg_ppiten_pp0_it58;
reg ap_reg_ppiten_pp0_it59;
reg ap_reg_ppiten_pp0_it60;
reg ap_reg_ppiten_pp0_it61;
reg ap_reg_ppiten_pp0_it62;
reg ap_reg_ppiten_pp0_it63;
reg ap_reg_ppiten_pp0_it64;
reg ap_reg_ppiten_pp0_it65;
reg ap_reg_ppiten_pp0_it66;
reg ap_reg_ppiten_pp0_it67;
reg ap_reg_ppiten_pp0_it68;
reg ap_reg_ppiten_pp0_it69;
reg ap_reg_ppiten_pp0_it70;
reg ap_reg_ppiten_pp0_it71;
reg ap_reg_ppiten_pp0_it72;
reg ap_reg_ppiten_pp0_it73;
reg ap_reg_ppiten_pp0_it74;
reg ap_reg_ppiten_pp0_it75;
reg ap_reg_ppiten_pp0_it76;
reg ap_reg_ppiten_pp0_it77;
reg [0:0] ap_reg_ppstg_exitcond_reg_1396_pp0_it1;
reg [0:0] ap_reg_ppstg_exitcond_reg_1396_pp0_it2;
reg [0:0] ap_reg_ppstg_exitcond_reg_1396_pp0_it3;
reg [0:0] ap_reg_ppstg_exitcond_reg_1396_pp0_it4;
reg [0:0] ap_reg_ppstg_exitcond_reg_1396_pp0_it5;
reg [0:0] ap_reg_ppstg_exitcond_reg_1396_pp0_it6;
reg [0:0] ap_reg_ppstg_exitcond_reg_1396_pp0_it7;
reg [0:0] ap_reg_ppstg_exitcond_reg_1396_pp0_it8;
reg [0:0] ap_reg_ppstg_exitcond_reg_1396_pp0_it9;
reg [0:0] ap_reg_ppstg_exitcond_reg_1396_pp0_it10;
reg [0:0] ap_reg_ppstg_exitcond_reg_1396_pp0_it11;
reg [0:0] ap_reg_ppstg_exitcond_reg_1396_pp0_it12;
reg [0:0] ap_reg_ppstg_exitcond_reg_1396_pp0_it13;
reg [0:0] ap_reg_ppstg_exitcond_reg_1396_pp0_it14;
reg [0:0] ap_reg_ppstg_exitcond_reg_1396_pp0_it15;
reg [0:0] ap_reg_ppstg_exitcond_reg_1396_pp0_it16;
reg [0:0] ap_reg_ppstg_exitcond_reg_1396_pp0_it17;
reg [0:0] ap_reg_ppstg_exitcond_reg_1396_pp0_it18;
reg [0:0] ap_reg_ppstg_exitcond_reg_1396_pp0_it19;
reg [0:0] ap_reg_ppstg_exitcond_reg_1396_pp0_it20;
reg [0:0] ap_reg_ppstg_exitcond_reg_1396_pp0_it21;
reg [0:0] ap_reg_ppstg_exitcond_reg_1396_pp0_it22;
reg [0:0] ap_reg_ppstg_exitcond_reg_1396_pp0_it23;
reg [0:0] ap_reg_ppstg_exitcond_reg_1396_pp0_it24;
reg [0:0] ap_reg_ppstg_exitcond_reg_1396_pp0_it25;
reg [0:0] ap_reg_ppstg_exitcond_reg_1396_pp0_it26;
reg [0:0] ap_reg_ppstg_exitcond_reg_1396_pp0_it27;
reg [0:0] ap_reg_ppstg_exitcond_reg_1396_pp0_it28;
reg [0:0] ap_reg_ppstg_exitcond_reg_1396_pp0_it29;
reg [0:0] ap_reg_ppstg_exitcond_reg_1396_pp0_it30;
reg [0:0] ap_reg_ppstg_exitcond_reg_1396_pp0_it31;
reg [0:0] ap_reg_ppstg_exitcond_reg_1396_pp0_it32;
reg [0:0] ap_reg_ppstg_exitcond_reg_1396_pp0_it33;
reg [0:0] ap_reg_ppstg_exitcond_reg_1396_pp0_it34;
reg [0:0] ap_reg_ppstg_exitcond_reg_1396_pp0_it35;
reg [0:0] ap_reg_ppstg_exitcond_reg_1396_pp0_it36;
reg [0:0] ap_reg_ppstg_exitcond_reg_1396_pp0_it37;
reg [0:0] ap_reg_ppstg_exitcond_reg_1396_pp0_it38;
reg [0:0] ap_reg_ppstg_exitcond_reg_1396_pp0_it39;
reg [0:0] ap_reg_ppstg_exitcond_reg_1396_pp0_it40;
reg [0:0] ap_reg_ppstg_exitcond_reg_1396_pp0_it41;
reg [0:0] ap_reg_ppstg_exitcond_reg_1396_pp0_it42;
reg [0:0] ap_reg_ppstg_exitcond_reg_1396_pp0_it43;
reg [0:0] ap_reg_ppstg_exitcond_reg_1396_pp0_it44;
reg [0:0] ap_reg_ppstg_exitcond_reg_1396_pp0_it45;
reg [0:0] ap_reg_ppstg_exitcond_reg_1396_pp0_it46;
reg [0:0] ap_reg_ppstg_exitcond_reg_1396_pp0_it47;
reg [0:0] ap_reg_ppstg_exitcond_reg_1396_pp0_it48;
reg [0:0] ap_reg_ppstg_exitcond_reg_1396_pp0_it49;
reg [0:0] ap_reg_ppstg_exitcond_reg_1396_pp0_it50;
reg [0:0] ap_reg_ppstg_exitcond_reg_1396_pp0_it51;
reg [0:0] ap_reg_ppstg_exitcond_reg_1396_pp0_it52;
reg [0:0] ap_reg_ppstg_exitcond_reg_1396_pp0_it53;
reg [0:0] ap_reg_ppstg_exitcond_reg_1396_pp0_it54;
reg [0:0] ap_reg_ppstg_exitcond_reg_1396_pp0_it55;
reg [0:0] ap_reg_ppstg_exitcond_reg_1396_pp0_it56;
reg [0:0] ap_reg_ppstg_exitcond_reg_1396_pp0_it57;
reg [0:0] ap_reg_ppstg_exitcond_reg_1396_pp0_it58;
reg [0:0] ap_reg_ppstg_exitcond_reg_1396_pp0_it59;
reg [0:0] ap_reg_ppstg_exitcond_reg_1396_pp0_it60;
reg [0:0] ap_reg_ppstg_exitcond_reg_1396_pp0_it61;
reg [0:0] ap_reg_ppstg_exitcond_reg_1396_pp0_it62;
reg [0:0] ap_reg_ppstg_exitcond_reg_1396_pp0_it63;
reg [0:0] ap_reg_ppstg_exitcond_reg_1396_pp0_it64;
reg [0:0] ap_reg_ppstg_exitcond_reg_1396_pp0_it65;
reg [0:0] ap_reg_ppstg_exitcond_reg_1396_pp0_it66;
reg [0:0] ap_reg_ppstg_exitcond_reg_1396_pp0_it67;
reg [0:0] ap_reg_ppstg_exitcond_reg_1396_pp0_it68;
reg [0:0] ap_reg_ppstg_exitcond_reg_1396_pp0_it69;
reg [0:0] ap_reg_ppstg_exitcond_reg_1396_pp0_it70;
reg [0:0] ap_reg_ppstg_exitcond_reg_1396_pp0_it71;
reg [0:0] ap_reg_ppstg_exitcond_reg_1396_pp0_it72;
reg [0:0] ap_reg_ppstg_exitcond_reg_1396_pp0_it73;
reg [0:0] ap_reg_ppstg_exitcond_reg_1396_pp0_it74;
reg [0:0] ap_reg_ppstg_exitcond_reg_1396_pp0_it75;
reg [0:0] ap_reg_ppstg_exitcond_reg_1396_pp0_it76;
reg [9:0] indvar_next_reg_1400;
wire [0:0] tmp_fu_888_p2;
reg [0:0] tmp_reg_1405;
reg [0:0] ap_reg_ppstg_tmp_reg_1405_pp0_it1;
reg [0:0] ap_reg_ppstg_tmp_reg_1405_pp0_it2;
reg [0:0] ap_reg_ppstg_tmp_reg_1405_pp0_it3;
reg [0:0] ap_reg_ppstg_tmp_reg_1405_pp0_it4;
reg [0:0] ap_reg_ppstg_tmp_reg_1405_pp0_it5;
reg [0:0] ap_reg_ppstg_tmp_reg_1405_pp0_it6;
reg [0:0] ap_reg_ppstg_tmp_reg_1405_pp0_it7;
reg [0:0] ap_reg_ppstg_tmp_reg_1405_pp0_it8;
reg [0:0] ap_reg_ppstg_tmp_reg_1405_pp0_it9;
reg [0:0] ap_reg_ppstg_tmp_reg_1405_pp0_it10;
reg [0:0] ap_reg_ppstg_tmp_reg_1405_pp0_it11;
reg [0:0] ap_reg_ppstg_tmp_reg_1405_pp0_it12;
reg [0:0] ap_reg_ppstg_tmp_reg_1405_pp0_it13;
reg [0:0] ap_reg_ppstg_tmp_reg_1405_pp0_it14;
reg [0:0] ap_reg_ppstg_tmp_reg_1405_pp0_it15;
reg [0:0] ap_reg_ppstg_tmp_reg_1405_pp0_it16;
reg [0:0] ap_reg_ppstg_tmp_reg_1405_pp0_it17;
reg [0:0] ap_reg_ppstg_tmp_reg_1405_pp0_it18;
reg [0:0] ap_reg_ppstg_tmp_reg_1405_pp0_it19;
reg [0:0] ap_reg_ppstg_tmp_reg_1405_pp0_it20;
reg [0:0] ap_reg_ppstg_tmp_reg_1405_pp0_it21;
reg [0:0] ap_reg_ppstg_tmp_reg_1405_pp0_it22;
reg [0:0] ap_reg_ppstg_tmp_reg_1405_pp0_it23;
reg [0:0] ap_reg_ppstg_tmp_reg_1405_pp0_it24;
reg [0:0] ap_reg_ppstg_tmp_reg_1405_pp0_it25;
reg [0:0] ap_reg_ppstg_tmp_reg_1405_pp0_it26;
reg [0:0] ap_reg_ppstg_tmp_reg_1405_pp0_it27;
reg [0:0] ap_reg_ppstg_tmp_reg_1405_pp0_it28;
reg [0:0] ap_reg_ppstg_tmp_reg_1405_pp0_it29;
reg [0:0] ap_reg_ppstg_tmp_reg_1405_pp0_it30;
reg [0:0] ap_reg_ppstg_tmp_reg_1405_pp0_it31;
reg [0:0] ap_reg_ppstg_tmp_reg_1405_pp0_it32;
reg [0:0] ap_reg_ppstg_tmp_reg_1405_pp0_it33;
reg [0:0] ap_reg_ppstg_tmp_reg_1405_pp0_it34;
reg [0:0] ap_reg_ppstg_tmp_reg_1405_pp0_it35;
reg [0:0] ap_reg_ppstg_tmp_reg_1405_pp0_it36;
reg [0:0] ap_reg_ppstg_tmp_reg_1405_pp0_it37;
reg [0:0] ap_reg_ppstg_tmp_reg_1405_pp0_it38;
reg [0:0] ap_reg_ppstg_tmp_reg_1405_pp0_it39;
reg [0:0] ap_reg_ppstg_tmp_reg_1405_pp0_it40;
reg [0:0] ap_reg_ppstg_tmp_reg_1405_pp0_it41;
reg [0:0] ap_reg_ppstg_tmp_reg_1405_pp0_it42;
reg [0:0] ap_reg_ppstg_tmp_reg_1405_pp0_it43;
reg [0:0] ap_reg_ppstg_tmp_reg_1405_pp0_it44;
reg [0:0] ap_reg_ppstg_tmp_reg_1405_pp0_it45;
reg [0:0] ap_reg_ppstg_tmp_reg_1405_pp0_it46;
reg [0:0] ap_reg_ppstg_tmp_reg_1405_pp0_it47;
reg [0:0] ap_reg_ppstg_tmp_reg_1405_pp0_it48;
reg [0:0] ap_reg_ppstg_tmp_reg_1405_pp0_it49;
reg [0:0] ap_reg_ppstg_tmp_reg_1405_pp0_it50;
reg [0:0] ap_reg_ppstg_tmp_reg_1405_pp0_it51;
reg [0:0] ap_reg_ppstg_tmp_reg_1405_pp0_it52;
reg [0:0] ap_reg_ppstg_tmp_reg_1405_pp0_it53;
reg [0:0] ap_reg_ppstg_tmp_reg_1405_pp0_it54;
reg [0:0] ap_reg_ppstg_tmp_reg_1405_pp0_it55;
reg [0:0] ap_reg_ppstg_tmp_reg_1405_pp0_it56;
reg [0:0] ap_reg_ppstg_tmp_reg_1405_pp0_it57;
reg [0:0] ap_reg_ppstg_tmp_reg_1405_pp0_it58;
reg [0:0] ap_reg_ppstg_tmp_reg_1405_pp0_it59;
reg [0:0] ap_reg_ppstg_tmp_reg_1405_pp0_it60;
reg [0:0] ap_reg_ppstg_tmp_reg_1405_pp0_it61;
reg [0:0] ap_reg_ppstg_tmp_reg_1405_pp0_it62;
reg [0:0] ap_reg_ppstg_tmp_reg_1405_pp0_it63;
reg [0:0] ap_reg_ppstg_tmp_reg_1405_pp0_it64;
reg [0:0] ap_reg_ppstg_tmp_reg_1405_pp0_it65;
reg [0:0] ap_reg_ppstg_tmp_reg_1405_pp0_it66;
reg [0:0] ap_reg_ppstg_tmp_reg_1405_pp0_it67;
reg [0:0] ap_reg_ppstg_tmp_reg_1405_pp0_it68;
reg [0:0] ap_reg_ppstg_tmp_reg_1405_pp0_it69;
reg [0:0] ap_reg_ppstg_tmp_reg_1405_pp0_it70;
reg [0:0] ap_reg_ppstg_tmp_reg_1405_pp0_it71;
reg [0:0] ap_reg_ppstg_tmp_reg_1405_pp0_it72;
reg [0:0] ap_reg_ppstg_tmp_reg_1405_pp0_it73;
reg [0:0] ap_reg_ppstg_tmp_reg_1405_pp0_it74;
reg [0:0] ap_reg_ppstg_tmp_reg_1405_pp0_it75;
reg [0:0] ap_reg_ppstg_tmp_reg_1405_pp0_it76;
wire [31:0] g2_p3_addr107_cast_fu_916_p1;
reg [31:0] g2_p3_addr107_cast_reg_1422;
reg [31:0] ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it1;
reg [31:0] ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it2;
reg [31:0] ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it3;
reg [31:0] ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it4;
reg [31:0] ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it5;
reg [31:0] ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it6;
reg [31:0] ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it7;
reg [31:0] ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it8;
reg [31:0] ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it9;
reg [31:0] ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it10;
reg [31:0] ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it11;
reg [31:0] ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it12;
reg [31:0] ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it13;
reg [31:0] ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it14;
reg [31:0] ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it15;
reg [31:0] ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it16;
reg [31:0] ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it17;
reg [31:0] ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it18;
reg [31:0] ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it19;
reg [31:0] ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it20;
reg [31:0] ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it21;
reg [31:0] ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it22;
reg [31:0] ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it23;
reg [31:0] ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it24;
reg [31:0] ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it25;
reg [31:0] ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it26;
reg [31:0] ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it27;
reg [31:0] ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it28;
reg [31:0] ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it29;
reg [31:0] ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it30;
reg [31:0] ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it31;
reg [31:0] ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it32;
reg [31:0] ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it33;
reg [31:0] ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it34;
reg [31:0] ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it35;
reg [31:0] ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it36;
reg [31:0] ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it37;
reg [31:0] ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it38;
reg [31:0] ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it39;
reg [31:0] ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it40;
reg [31:0] ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it41;
reg [31:0] ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it42;
reg [31:0] ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it43;
reg [31:0] ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it44;
reg [31:0] ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it45;
reg [31:0] ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it46;
reg [31:0] ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it47;
reg [31:0] ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it48;
reg [31:0] ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it49;
reg [31:0] ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it50;
reg [31:0] ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it51;
reg [31:0] ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it52;
reg [31:0] ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it53;
reg [31:0] ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it54;
reg [31:0] ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it55;
reg [31:0] ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it56;
reg [31:0] ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it57;
reg [31:0] ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it58;
reg [31:0] ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it59;
reg [31:0] ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it60;
reg [31:0] ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it61;
reg [31:0] ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it62;
reg [31:0] ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it63;
reg [31:0] ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it64;
reg [31:0] ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it65;
reg [31:0] ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it66;
reg [31:0] ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it67;
reg [31:0] ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it68;
reg [31:0] ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it69;
reg [31:0] j_1_reg_1610;
reg [31:0] i_reg_1615;
reg [31:0] u_Local_reg_1620;
reg [31:0] ap_reg_ppstg_u_Local_reg_1620_pp0_it2;
reg [31:0] ap_reg_ppstg_u_Local_reg_1620_pp0_it3;
reg [31:0] ap_reg_ppstg_u_Local_reg_1620_pp0_it4;
reg [31:0] ap_reg_ppstg_u_Local_reg_1620_pp0_it5;
reg [31:0] ap_reg_ppstg_u_Local_reg_1620_pp0_it6;
reg [31:0] ap_reg_ppstg_u_Local_reg_1620_pp0_it7;
reg [31:0] ap_reg_ppstg_u_Local_reg_1620_pp0_it8;
reg [31:0] ap_reg_ppstg_u_Local_reg_1620_pp0_it9;
reg [31:0] ap_reg_ppstg_u_Local_reg_1620_pp0_it10;
reg [31:0] ap_reg_ppstg_u_Local_reg_1620_pp0_it11;
reg [31:0] ap_reg_ppstg_u_Local_reg_1620_pp0_it12;
reg [31:0] ap_reg_ppstg_u_Local_reg_1620_pp0_it13;
reg [31:0] ap_reg_ppstg_u_Local_reg_1620_pp0_it14;
reg [31:0] ap_reg_ppstg_u_Local_reg_1620_pp0_it15;
reg [31:0] ap_reg_ppstg_u_Local_reg_1620_pp0_it16;
reg [31:0] ap_reg_ppstg_u_Local_reg_1620_pp0_it17;
reg [31:0] ap_reg_ppstg_u_Local_reg_1620_pp0_it18;
reg [31:0] ap_reg_ppstg_u_Local_reg_1620_pp0_it19;
reg [31:0] ap_reg_ppstg_u_Local_reg_1620_pp0_it20;
reg [31:0] ap_reg_ppstg_u_Local_reg_1620_pp0_it21;
reg [31:0] ap_reg_ppstg_u_Local_reg_1620_pp0_it22;
reg [31:0] ap_reg_ppstg_u_Local_reg_1620_pp0_it23;
reg [31:0] ap_reg_ppstg_u_Local_reg_1620_pp0_it24;
reg [31:0] ap_reg_ppstg_u_Local_reg_1620_pp0_it25;
reg [31:0] ap_reg_ppstg_u_Local_reg_1620_pp0_it26;
reg [31:0] ap_reg_ppstg_u_Local_reg_1620_pp0_it27;
reg [31:0] ap_reg_ppstg_u_Local_reg_1620_pp0_it28;
reg [31:0] ap_reg_ppstg_u_Local_reg_1620_pp0_it29;
reg [31:0] ap_reg_ppstg_u_Local_reg_1620_pp0_it30;
reg [31:0] ap_reg_ppstg_u_Local_reg_1620_pp0_it31;
reg [31:0] ap_reg_ppstg_u_Local_reg_1620_pp0_it32;
reg [31:0] ap_reg_ppstg_u_Local_reg_1620_pp0_it33;
reg [31:0] ap_reg_ppstg_u_Local_reg_1620_pp0_it34;
reg [31:0] ap_reg_ppstg_u_Local_reg_1620_pp0_it35;
reg [31:0] ap_reg_ppstg_u_Local_reg_1620_pp0_it36;
reg [31:0] ap_reg_ppstg_u_Local_reg_1620_pp0_it37;
reg [31:0] ap_reg_ppstg_u_Local_reg_1620_pp0_it38;
reg [31:0] ap_reg_ppstg_u_Local_reg_1620_pp0_it39;
reg [31:0] ap_reg_ppstg_u_Local_reg_1620_pp0_it40;
reg [31:0] ap_reg_ppstg_u_Local_reg_1620_pp0_it41;
reg [31:0] ap_reg_ppstg_u_Local_reg_1620_pp0_it42;
reg [31:0] ap_reg_ppstg_u_Local_reg_1620_pp0_it43;
reg [31:0] ap_reg_ppstg_u_Local_reg_1620_pp0_it44;
reg [31:0] ap_reg_ppstg_u_Local_reg_1620_pp0_it45;
reg [31:0] ap_reg_ppstg_u_Local_reg_1620_pp0_it46;
reg [31:0] ap_reg_ppstg_u_Local_reg_1620_pp0_it47;
reg [31:0] ap_reg_ppstg_u_Local_reg_1620_pp0_it48;
reg [31:0] ap_reg_ppstg_u_Local_reg_1620_pp0_it49;
reg [31:0] ap_reg_ppstg_u_Local_reg_1620_pp0_it50;
reg [31:0] ap_reg_ppstg_u_Local_reg_1620_pp0_it51;
reg [31:0] ap_reg_ppstg_u_Local_reg_1620_pp0_it52;
reg [31:0] ap_reg_ppstg_u_Local_reg_1620_pp0_it53;
reg [31:0] ap_reg_ppstg_u_Local_reg_1620_pp0_it54;
reg [31:0] ap_reg_ppstg_u_Local_reg_1620_pp0_it55;
reg [31:0] ap_reg_ppstg_u_Local_reg_1620_pp0_it56;
reg [31:0] ap_reg_ppstg_u_Local_reg_1620_pp0_it57;
reg [31:0] ap_reg_ppstg_u_Local_reg_1620_pp0_it58;
reg [31:0] ap_reg_ppstg_u_Local_reg_1620_pp0_it59;
reg [31:0] ap_reg_ppstg_u_Local_reg_1620_pp0_it60;
reg [31:0] ap_reg_ppstg_u_Local_reg_1620_pp0_it61;
reg [31:0] ap_reg_ppstg_u_Local_reg_1620_pp0_it62;
reg [31:0] ap_reg_ppstg_u_Local_reg_1620_pp0_it63;
reg [31:0] ap_reg_ppstg_u_Local_reg_1620_pp0_it64;
reg [31:0] ap_reg_ppstg_u_Local_reg_1620_pp0_it65;
reg [31:0] ap_reg_ppstg_u_Local_reg_1620_pp0_it66;
reg [31:0] ap_reg_ppstg_u_Local_reg_1620_pp0_it67;
reg [31:0] ap_reg_ppstg_u_Local_reg_1620_pp0_it68;
reg [31:0] ap_reg_ppstg_u_Local_reg_1620_pp0_it69;
reg [31:0] ap_reg_ppstg_u_Local_reg_1620_pp0_it70;
reg [31:0] u_p0_load_reg_1626;
reg [31:0] ap_reg_ppstg_u_p0_load_reg_1626_pp0_it2;
reg [31:0] ap_reg_ppstg_u_p0_load_reg_1626_pp0_it3;
reg [31:0] ap_reg_ppstg_u_p0_load_reg_1626_pp0_it4;
reg [31:0] ap_reg_ppstg_u_p0_load_reg_1626_pp0_it5;
reg [31:0] ap_reg_ppstg_u_p0_load_reg_1626_pp0_it6;
reg [31:0] ap_reg_ppstg_u_p0_load_reg_1626_pp0_it7;
reg [31:0] ap_reg_ppstg_u_p0_load_reg_1626_pp0_it8;
reg [31:0] ap_reg_ppstg_u_p0_load_reg_1626_pp0_it9;
reg [31:0] ap_reg_ppstg_u_p0_load_reg_1626_pp0_it10;
reg [31:0] ap_reg_ppstg_u_p0_load_reg_1626_pp0_it11;
reg [31:0] ap_reg_ppstg_u_p0_load_reg_1626_pp0_it12;
reg [31:0] ap_reg_ppstg_u_p0_load_reg_1626_pp0_it13;
reg [31:0] ap_reg_ppstg_u_p0_load_reg_1626_pp0_it14;
reg [31:0] ap_reg_ppstg_u_p0_load_reg_1626_pp0_it15;
reg [31:0] ap_reg_ppstg_u_p0_load_reg_1626_pp0_it16;
reg [31:0] ap_reg_ppstg_u_p0_load_reg_1626_pp0_it17;
reg [31:0] ap_reg_ppstg_u_p0_load_reg_1626_pp0_it18;
reg [31:0] ap_reg_ppstg_u_p0_load_reg_1626_pp0_it19;
reg [31:0] ap_reg_ppstg_u_p0_load_reg_1626_pp0_it20;
reg [31:0] ap_reg_ppstg_u_p0_load_reg_1626_pp0_it21;
reg [31:0] ap_reg_ppstg_u_p0_load_reg_1626_pp0_it22;
reg [31:0] ap_reg_ppstg_u_p0_load_reg_1626_pp0_it23;
reg [31:0] ap_reg_ppstg_u_p0_load_reg_1626_pp0_it24;
reg [31:0] ap_reg_ppstg_u_p0_load_reg_1626_pp0_it25;
reg [31:0] ap_reg_ppstg_u_p0_load_reg_1626_pp0_it26;
reg [31:0] ap_reg_ppstg_u_p0_load_reg_1626_pp0_it27;
reg [31:0] ap_reg_ppstg_u_p0_load_reg_1626_pp0_it28;
reg [31:0] ap_reg_ppstg_u_p0_load_reg_1626_pp0_it29;
reg [31:0] ap_reg_ppstg_u_p0_load_reg_1626_pp0_it30;
reg [31:0] ap_reg_ppstg_u_p0_load_reg_1626_pp0_it31;
reg [31:0] ap_reg_ppstg_u_p0_load_reg_1626_pp0_it32;
reg [31:0] ap_reg_ppstg_u_p0_load_reg_1626_pp0_it33;
reg [31:0] ap_reg_ppstg_u_p0_load_reg_1626_pp0_it34;
reg [31:0] ap_reg_ppstg_u_p0_load_reg_1626_pp0_it35;
reg [31:0] ap_reg_ppstg_u_p0_load_reg_1626_pp0_it36;
reg [31:0] ap_reg_ppstg_u_p0_load_reg_1626_pp0_it37;
reg [31:0] ap_reg_ppstg_u_p0_load_reg_1626_pp0_it38;
reg [31:0] ap_reg_ppstg_u_p0_load_reg_1626_pp0_it39;
reg [31:0] ap_reg_ppstg_u_p0_load_reg_1626_pp0_it40;
reg [31:0] ap_reg_ppstg_u_p0_load_reg_1626_pp0_it41;
reg [31:0] ap_reg_ppstg_u_p0_load_reg_1626_pp0_it42;
reg [31:0] ap_reg_ppstg_u_p0_load_reg_1626_pp0_it43;
reg [31:0] ap_reg_ppstg_u_p0_load_reg_1626_pp0_it44;
reg [31:0] ap_reg_ppstg_u_p0_load_reg_1626_pp0_it45;
reg [31:0] ap_reg_ppstg_u_p0_load_reg_1626_pp0_it46;
reg [31:0] ap_reg_ppstg_u_p0_load_reg_1626_pp0_it47;
reg [31:0] ap_reg_ppstg_u_p0_load_reg_1626_pp0_it48;
reg [31:0] ap_reg_ppstg_u_p0_load_reg_1626_pp0_it49;
reg [31:0] ap_reg_ppstg_u_p0_load_reg_1626_pp0_it50;
reg [31:0] ap_reg_ppstg_u_p0_load_reg_1626_pp0_it51;
reg [31:0] ap_reg_ppstg_u_p0_load_reg_1626_pp0_it52;
reg [31:0] ap_reg_ppstg_u_p0_load_reg_1626_pp0_it53;
reg [31:0] ap_reg_ppstg_u_p0_load_reg_1626_pp0_it54;
reg [31:0] ap_reg_ppstg_u_p0_load_reg_1626_pp0_it55;
reg [31:0] ap_reg_ppstg_u_p0_load_reg_1626_pp0_it56;
reg [31:0] ap_reg_ppstg_u_p0_load_reg_1626_pp0_it57;
reg [31:0] ap_reg_ppstg_u_p0_load_reg_1626_pp0_it58;
reg [31:0] ap_reg_ppstg_u_p0_load_reg_1626_pp0_it59;
reg [31:0] ap_reg_ppstg_u_p0_load_reg_1626_pp0_it60;
reg [31:0] ap_reg_ppstg_u_p0_load_reg_1626_pp0_it61;
reg [31:0] ap_reg_ppstg_u_p0_load_reg_1626_pp0_it62;
reg [31:0] ap_reg_ppstg_u_p0_load_reg_1626_pp0_it63;
reg [31:0] ap_reg_ppstg_u_p0_load_reg_1626_pp0_it64;
reg [31:0] ap_reg_ppstg_u_p0_load_reg_1626_pp0_it65;
reg [31:0] ap_reg_ppstg_u_p0_load_reg_1626_pp0_it66;
reg [31:0] ap_reg_ppstg_u_p0_load_reg_1626_pp0_it67;
reg [31:0] ap_reg_ppstg_u_p0_load_reg_1626_pp0_it68;
reg [31:0] ap_reg_ppstg_u_p0_load_reg_1626_pp0_it69;
reg [31:0] ap_reg_ppstg_u_p0_load_reg_1626_pp0_it70;
reg [31:0] u_p1_load_reg_1632;
reg [31:0] ap_reg_ppstg_u_p1_load_reg_1632_pp0_it2;
reg [31:0] ap_reg_ppstg_u_p1_load_reg_1632_pp0_it3;
reg [31:0] ap_reg_ppstg_u_p1_load_reg_1632_pp0_it4;
reg [31:0] ap_reg_ppstg_u_p1_load_reg_1632_pp0_it5;
reg [31:0] ap_reg_ppstg_u_p1_load_reg_1632_pp0_it6;
reg [31:0] ap_reg_ppstg_u_p1_load_reg_1632_pp0_it7;
reg [31:0] ap_reg_ppstg_u_p1_load_reg_1632_pp0_it8;
reg [31:0] ap_reg_ppstg_u_p1_load_reg_1632_pp0_it9;
reg [31:0] ap_reg_ppstg_u_p1_load_reg_1632_pp0_it10;
reg [31:0] ap_reg_ppstg_u_p1_load_reg_1632_pp0_it11;
reg [31:0] ap_reg_ppstg_u_p1_load_reg_1632_pp0_it12;
reg [31:0] ap_reg_ppstg_u_p1_load_reg_1632_pp0_it13;
reg [31:0] ap_reg_ppstg_u_p1_load_reg_1632_pp0_it14;
reg [31:0] ap_reg_ppstg_u_p1_load_reg_1632_pp0_it15;
reg [31:0] ap_reg_ppstg_u_p1_load_reg_1632_pp0_it16;
reg [31:0] ap_reg_ppstg_u_p1_load_reg_1632_pp0_it17;
reg [31:0] ap_reg_ppstg_u_p1_load_reg_1632_pp0_it18;
reg [31:0] ap_reg_ppstg_u_p1_load_reg_1632_pp0_it19;
reg [31:0] ap_reg_ppstg_u_p1_load_reg_1632_pp0_it20;
reg [31:0] ap_reg_ppstg_u_p1_load_reg_1632_pp0_it21;
reg [31:0] ap_reg_ppstg_u_p1_load_reg_1632_pp0_it22;
reg [31:0] ap_reg_ppstg_u_p1_load_reg_1632_pp0_it23;
reg [31:0] ap_reg_ppstg_u_p1_load_reg_1632_pp0_it24;
reg [31:0] ap_reg_ppstg_u_p1_load_reg_1632_pp0_it25;
reg [31:0] ap_reg_ppstg_u_p1_load_reg_1632_pp0_it26;
reg [31:0] ap_reg_ppstg_u_p1_load_reg_1632_pp0_it27;
reg [31:0] ap_reg_ppstg_u_p1_load_reg_1632_pp0_it28;
reg [31:0] ap_reg_ppstg_u_p1_load_reg_1632_pp0_it29;
reg [31:0] ap_reg_ppstg_u_p1_load_reg_1632_pp0_it30;
reg [31:0] ap_reg_ppstg_u_p1_load_reg_1632_pp0_it31;
reg [31:0] ap_reg_ppstg_u_p1_load_reg_1632_pp0_it32;
reg [31:0] ap_reg_ppstg_u_p1_load_reg_1632_pp0_it33;
reg [31:0] ap_reg_ppstg_u_p1_load_reg_1632_pp0_it34;
reg [31:0] ap_reg_ppstg_u_p1_load_reg_1632_pp0_it35;
reg [31:0] ap_reg_ppstg_u_p1_load_reg_1632_pp0_it36;
reg [31:0] ap_reg_ppstg_u_p1_load_reg_1632_pp0_it37;
reg [31:0] ap_reg_ppstg_u_p1_load_reg_1632_pp0_it38;
reg [31:0] ap_reg_ppstg_u_p1_load_reg_1632_pp0_it39;
reg [31:0] ap_reg_ppstg_u_p1_load_reg_1632_pp0_it40;
reg [31:0] ap_reg_ppstg_u_p1_load_reg_1632_pp0_it41;
reg [31:0] ap_reg_ppstg_u_p1_load_reg_1632_pp0_it42;
reg [31:0] ap_reg_ppstg_u_p1_load_reg_1632_pp0_it43;
reg [31:0] ap_reg_ppstg_u_p1_load_reg_1632_pp0_it44;
reg [31:0] ap_reg_ppstg_u_p1_load_reg_1632_pp0_it45;
reg [31:0] ap_reg_ppstg_u_p1_load_reg_1632_pp0_it46;
reg [31:0] ap_reg_ppstg_u_p1_load_reg_1632_pp0_it47;
reg [31:0] ap_reg_ppstg_u_p1_load_reg_1632_pp0_it48;
reg [31:0] ap_reg_ppstg_u_p1_load_reg_1632_pp0_it49;
reg [31:0] ap_reg_ppstg_u_p1_load_reg_1632_pp0_it50;
reg [31:0] ap_reg_ppstg_u_p1_load_reg_1632_pp0_it51;
reg [31:0] ap_reg_ppstg_u_p1_load_reg_1632_pp0_it52;
reg [31:0] ap_reg_ppstg_u_p1_load_reg_1632_pp0_it53;
reg [31:0] ap_reg_ppstg_u_p1_load_reg_1632_pp0_it54;
reg [31:0] ap_reg_ppstg_u_p1_load_reg_1632_pp0_it55;
reg [31:0] ap_reg_ppstg_u_p1_load_reg_1632_pp0_it56;
reg [31:0] ap_reg_ppstg_u_p1_load_reg_1632_pp0_it57;
reg [31:0] ap_reg_ppstg_u_p1_load_reg_1632_pp0_it58;
reg [31:0] ap_reg_ppstg_u_p1_load_reg_1632_pp0_it59;
reg [31:0] ap_reg_ppstg_u_p1_load_reg_1632_pp0_it60;
reg [31:0] ap_reg_ppstg_u_p1_load_reg_1632_pp0_it61;
reg [31:0] ap_reg_ppstg_u_p1_load_reg_1632_pp0_it62;
reg [31:0] ap_reg_ppstg_u_p1_load_reg_1632_pp0_it63;
reg [31:0] ap_reg_ppstg_u_p1_load_reg_1632_pp0_it64;
reg [31:0] ap_reg_ppstg_u_p1_load_reg_1632_pp0_it65;
reg [31:0] ap_reg_ppstg_u_p1_load_reg_1632_pp0_it66;
reg [31:0] ap_reg_ppstg_u_p1_load_reg_1632_pp0_it67;
reg [31:0] ap_reg_ppstg_u_p1_load_reg_1632_pp0_it68;
reg [31:0] ap_reg_ppstg_u_p1_load_reg_1632_pp0_it69;
reg [31:0] ap_reg_ppstg_u_p1_load_reg_1632_pp0_it70;
reg [31:0] u_p2_load_reg_1638;
reg [31:0] ap_reg_ppstg_u_p2_load_reg_1638_pp0_it2;
reg [31:0] ap_reg_ppstg_u_p2_load_reg_1638_pp0_it3;
reg [31:0] ap_reg_ppstg_u_p2_load_reg_1638_pp0_it4;
reg [31:0] ap_reg_ppstg_u_p2_load_reg_1638_pp0_it5;
reg [31:0] ap_reg_ppstg_u_p2_load_reg_1638_pp0_it6;
reg [31:0] ap_reg_ppstg_u_p2_load_reg_1638_pp0_it7;
reg [31:0] ap_reg_ppstg_u_p2_load_reg_1638_pp0_it8;
reg [31:0] ap_reg_ppstg_u_p2_load_reg_1638_pp0_it9;
reg [31:0] ap_reg_ppstg_u_p2_load_reg_1638_pp0_it10;
reg [31:0] ap_reg_ppstg_u_p2_load_reg_1638_pp0_it11;
reg [31:0] ap_reg_ppstg_u_p2_load_reg_1638_pp0_it12;
reg [31:0] ap_reg_ppstg_u_p2_load_reg_1638_pp0_it13;
reg [31:0] ap_reg_ppstg_u_p2_load_reg_1638_pp0_it14;
reg [31:0] ap_reg_ppstg_u_p2_load_reg_1638_pp0_it15;
reg [31:0] ap_reg_ppstg_u_p2_load_reg_1638_pp0_it16;
reg [31:0] ap_reg_ppstg_u_p2_load_reg_1638_pp0_it17;
reg [31:0] ap_reg_ppstg_u_p2_load_reg_1638_pp0_it18;
reg [31:0] ap_reg_ppstg_u_p2_load_reg_1638_pp0_it19;
reg [31:0] ap_reg_ppstg_u_p2_load_reg_1638_pp0_it20;
reg [31:0] ap_reg_ppstg_u_p2_load_reg_1638_pp0_it21;
reg [31:0] ap_reg_ppstg_u_p2_load_reg_1638_pp0_it22;
reg [31:0] ap_reg_ppstg_u_p2_load_reg_1638_pp0_it23;
reg [31:0] ap_reg_ppstg_u_p2_load_reg_1638_pp0_it24;
reg [31:0] ap_reg_ppstg_u_p2_load_reg_1638_pp0_it25;
reg [31:0] ap_reg_ppstg_u_p2_load_reg_1638_pp0_it26;
reg [31:0] ap_reg_ppstg_u_p2_load_reg_1638_pp0_it27;
reg [31:0] ap_reg_ppstg_u_p2_load_reg_1638_pp0_it28;
reg [31:0] ap_reg_ppstg_u_p2_load_reg_1638_pp0_it29;
reg [31:0] ap_reg_ppstg_u_p2_load_reg_1638_pp0_it30;
reg [31:0] ap_reg_ppstg_u_p2_load_reg_1638_pp0_it31;
reg [31:0] ap_reg_ppstg_u_p2_load_reg_1638_pp0_it32;
reg [31:0] ap_reg_ppstg_u_p2_load_reg_1638_pp0_it33;
reg [31:0] ap_reg_ppstg_u_p2_load_reg_1638_pp0_it34;
reg [31:0] ap_reg_ppstg_u_p2_load_reg_1638_pp0_it35;
reg [31:0] ap_reg_ppstg_u_p2_load_reg_1638_pp0_it36;
reg [31:0] ap_reg_ppstg_u_p2_load_reg_1638_pp0_it37;
reg [31:0] ap_reg_ppstg_u_p2_load_reg_1638_pp0_it38;
reg [31:0] ap_reg_ppstg_u_p2_load_reg_1638_pp0_it39;
reg [31:0] ap_reg_ppstg_u_p2_load_reg_1638_pp0_it40;
reg [31:0] ap_reg_ppstg_u_p2_load_reg_1638_pp0_it41;
reg [31:0] ap_reg_ppstg_u_p2_load_reg_1638_pp0_it42;
reg [31:0] ap_reg_ppstg_u_p2_load_reg_1638_pp0_it43;
reg [31:0] ap_reg_ppstg_u_p2_load_reg_1638_pp0_it44;
reg [31:0] ap_reg_ppstg_u_p2_load_reg_1638_pp0_it45;
reg [31:0] ap_reg_ppstg_u_p2_load_reg_1638_pp0_it46;
reg [31:0] ap_reg_ppstg_u_p2_load_reg_1638_pp0_it47;
reg [31:0] ap_reg_ppstg_u_p2_load_reg_1638_pp0_it48;
reg [31:0] ap_reg_ppstg_u_p2_load_reg_1638_pp0_it49;
reg [31:0] ap_reg_ppstg_u_p2_load_reg_1638_pp0_it50;
reg [31:0] ap_reg_ppstg_u_p2_load_reg_1638_pp0_it51;
reg [31:0] ap_reg_ppstg_u_p2_load_reg_1638_pp0_it52;
reg [31:0] ap_reg_ppstg_u_p2_load_reg_1638_pp0_it53;
reg [31:0] ap_reg_ppstg_u_p2_load_reg_1638_pp0_it54;
reg [31:0] ap_reg_ppstg_u_p2_load_reg_1638_pp0_it55;
reg [31:0] ap_reg_ppstg_u_p2_load_reg_1638_pp0_it56;
reg [31:0] ap_reg_ppstg_u_p2_load_reg_1638_pp0_it57;
reg [31:0] ap_reg_ppstg_u_p2_load_reg_1638_pp0_it58;
reg [31:0] ap_reg_ppstg_u_p2_load_reg_1638_pp0_it59;
reg [31:0] ap_reg_ppstg_u_p2_load_reg_1638_pp0_it60;
reg [31:0] ap_reg_ppstg_u_p2_load_reg_1638_pp0_it61;
reg [31:0] ap_reg_ppstg_u_p2_load_reg_1638_pp0_it62;
reg [31:0] ap_reg_ppstg_u_p2_load_reg_1638_pp0_it63;
reg [31:0] ap_reg_ppstg_u_p2_load_reg_1638_pp0_it64;
reg [31:0] ap_reg_ppstg_u_p2_load_reg_1638_pp0_it65;
reg [31:0] ap_reg_ppstg_u_p2_load_reg_1638_pp0_it66;
reg [31:0] ap_reg_ppstg_u_p2_load_reg_1638_pp0_it67;
reg [31:0] ap_reg_ppstg_u_p2_load_reg_1638_pp0_it68;
reg [31:0] ap_reg_ppstg_u_p2_load_reg_1638_pp0_it69;
reg [31:0] ap_reg_ppstg_u_p2_load_reg_1638_pp0_it70;
wire [31:0] grp_computeResultOne_fu_697_ap_return;
reg [31:0] tmp3_reg_1644;
wire [31:0] grp_computeResultOne_fu_730_ap_return;
reg [31:0] tmp6_reg_1649;
wire [31:0] grp_computeResultOne_fu_763_ap_return;
reg [31:0] tmp11_reg_1654;
wire [31:0] grp_computeResultOne_fu_794_ap_return;
reg [31:0] tmp14_reg_1659;
wire [31:0] grp_fu_856_p2;
reg [31:0] diff_reg_1664;
wire [31:0] grp_fu_860_p2;
reg [31:0] diff1_reg_1670;
wire [31:0] grp_fu_864_p2;
reg [31:0] diff2_reg_1676;
wire [31:0] grp_fu_868_p2;
reg [31:0] diff3_reg_1682;
wire [31:0] grp_computeResultOne_fu_697_u;
wire [31:0] grp_computeResultOne_fu_697_ug0;
wire [31:0] grp_computeResultOne_fu_697_ug1;
wire [31:0] grp_computeResultOne_fu_697_ug2;
wire [31:0] grp_computeResultOne_fu_697_ug3;
wire [31:0] grp_computeResultOne_fu_697_ug4;
wire [31:0] grp_computeResultOne_fu_697_ug5;
wire [31:0] grp_computeResultOne_fu_697_g0;
wire [31:0] grp_computeResultOne_fu_697_g1;
wire [31:0] grp_computeResultOne_fu_697_g2;
wire [31:0] grp_computeResultOne_fu_697_g3;
wire [31:0] grp_computeResultOne_fu_697_g4;
wire [31:0] grp_computeResultOne_fu_697_g5;
wire [31:0] grp_computeResultOne_fu_697_f;
reg grp_computeResultOne_fu_697_ap_ce;
wire [31:0] grp_computeResultOne_fu_730_u;
wire [31:0] grp_computeResultOne_fu_730_ug0;
wire [31:0] grp_computeResultOne_fu_730_ug1;
wire [31:0] grp_computeResultOne_fu_730_ug2;
wire [31:0] grp_computeResultOne_fu_730_ug3;
wire [31:0] grp_computeResultOne_fu_730_ug4;
wire [31:0] grp_computeResultOne_fu_730_ug5;
wire [31:0] grp_computeResultOne_fu_730_g0;
wire [31:0] grp_computeResultOne_fu_730_g1;
wire [31:0] grp_computeResultOne_fu_730_g2;
wire [31:0] grp_computeResultOne_fu_730_g3;
wire [31:0] grp_computeResultOne_fu_730_g4;
wire [31:0] grp_computeResultOne_fu_730_g5;
wire [31:0] grp_computeResultOne_fu_730_f;
reg grp_computeResultOne_fu_730_ap_ce;
wire [31:0] grp_computeResultOne_fu_763_u;
wire [31:0] grp_computeResultOne_fu_763_ug0;
wire [31:0] grp_computeResultOne_fu_763_ug1;
wire [31:0] grp_computeResultOne_fu_763_ug2;
wire [31:0] grp_computeResultOne_fu_763_ug3;
wire [31:0] grp_computeResultOne_fu_763_ug4;
wire [31:0] grp_computeResultOne_fu_763_ug5;
wire [31:0] grp_computeResultOne_fu_763_g0;
wire [31:0] grp_computeResultOne_fu_763_g1;
wire [31:0] grp_computeResultOne_fu_763_g2;
wire [31:0] grp_computeResultOne_fu_763_g3;
wire [31:0] grp_computeResultOne_fu_763_g4;
wire [31:0] grp_computeResultOne_fu_763_g5;
wire [31:0] grp_computeResultOne_fu_763_f;
reg grp_computeResultOne_fu_763_ap_ce;
wire [31:0] grp_computeResultOne_fu_794_u;
wire [31:0] grp_computeResultOne_fu_794_ug0;
wire [31:0] grp_computeResultOne_fu_794_ug1;
wire [31:0] grp_computeResultOne_fu_794_ug2;
wire [31:0] grp_computeResultOne_fu_794_ug3;
wire [31:0] grp_computeResultOne_fu_794_ug4;
wire [31:0] grp_computeResultOne_fu_794_ug5;
wire [31:0] grp_computeResultOne_fu_794_g0;
wire [31:0] grp_computeResultOne_fu_794_g1;
wire [31:0] grp_computeResultOne_fu_794_g2;
wire [31:0] grp_computeResultOne_fu_794_g3;
wire [31:0] grp_computeResultOne_fu_794_g4;
wire [31:0] grp_computeResultOne_fu_794_g5;
wire [31:0] grp_computeResultOne_fu_794_f;
reg grp_computeResultOne_fu_794_ap_ce;
reg [9:0] k_phi_fu_644_p4;
reg [31:0] j_phi_fu_655_p4;
reg [31:0] i_1_phi_fu_666_p4;
reg [0:0] Convergence_1_phi_fu_689_p4;
wire [0:0] tmp18_fu_1311_p2;
wire [0:0] tmp10_fu_1280_p2;
wire [31:0] g1_p3_addr95_cast_fu_972_p1;
wire [31:0] g1_p0_addr78_cast_fu_996_p1;
wire [31:0] g1_p3_addr91_cast_fu_1014_p1;
reg [31:0] g2_Local03_1_fu_112;
reg [31:0] g0_Local03_1_fu_116;
reg [31:0] g1_Local13_1_fu_120;
reg [31:0] g1_Local05_1_fu_124;
reg [31:0] g1_Local04_1_fu_128;
reg [31:0] g1_Localn13_1_fu_132;
reg [31:0] ug2_Local03_1_fu_136;
reg [31:0] ug0_Local03_1_fu_140;
reg [31:0] ug1_Local13_1_fu_144;
reg [31:0] ug1_Local05_1_fu_148;
reg [31:0] ug1_Local04_1_fu_152;
reg [31:0] ug1_Localn13_1_fu_156;
reg [31:0] u_Local03_1_fu_160;
wire [31:0] grp_fu_816_p0;
wire [31:0] grp_fu_816_p1;
wire [31:0] grp_fu_821_p0;
wire [31:0] grp_fu_821_p1;
wire [31:0] grp_fu_826_p0;
wire [31:0] grp_fu_826_p1;
wire [31:0] grp_fu_831_p0;
wire [31:0] grp_fu_831_p1;
wire [31:0] grp_fu_836_p0;
wire [31:0] grp_fu_836_p1;
wire [31:0] grp_fu_841_p0;
wire [31:0] grp_fu_841_p1;
wire [31:0] grp_fu_846_p0;
wire [31:0] grp_fu_846_p1;
wire [31:0] grp_fu_851_p0;
wire [31:0] grp_fu_851_p1;
wire [31:0] grp_fu_856_p0;
wire [31:0] grp_fu_856_p1;
wire [31:0] grp_fu_860_p0;
wire [31:0] grp_fu_860_p1;
wire [31:0] grp_fu_864_p0;
wire [31:0] grp_fu_864_p1;
wire [31:0] grp_fu_868_p0;
wire [31:0] grp_fu_868_p1;
wire [9:0] exitcond_fu_876_p1;
wire [31:0] tmp_fu_888_p1;
wire [7:0] i_1_cast_fu_894_p1;
wire [7:0] p_shl_fu_898_p2;
wire [7:0] g2_p3_addr_cast_fu_904_p2;
wire [7:0] j_cast_fu_872_p1;
wire [7:0] g2_p3_addr_fu_910_p2;
wire [31:0] tmp1_fu_944_p2;
wire [7:0] tmp42_cast_fu_950_p1;
wire [7:0] p_shl1_fu_954_p2;
wire [7:0] g1_p3_addr94_cast_fu_960_p2;
wire [7:0] g1_p3_addr_fu_966_p2;
wire [7:0] tmp2_fu_984_p2;
wire [7:0] g1_p0_addr_fu_990_p2;
wire [7:0] tmp48_cast_fu_1002_p2;
wire [7:0] g1_p3_addr1_fu_1008_p2;
wire [31:0] tmp19_fu_1020_p2;
wire [31:0] tmp20_fu_1026_p1;
wire [0:0] tmp20_fu_1026_p2;
wire [0:0] grp_fu_816_p2;
wire [0:0] grp_fu_821_p2;
wire [0:0] grp_fu_826_p2;
wire [0:0] grp_fu_831_p2;
wire [0:0] bothcond_fu_1256_p2;
wire [0:0] bothcond1_fu_1262_p2;
wire [0:0] tmp70_demorgan_fu_1268_p2;
wire [0:0] tmp9_fu_1274_p2;
wire [0:0] grp_fu_836_p2;
wire [0:0] grp_fu_841_p2;
wire [0:0] grp_fu_846_p2;
wire [0:0] grp_fu_851_p2;
wire [0:0] bothcond2_fu_1287_p2;
wire [0:0] bothcond3_fu_1293_p2;
wire [0:0] tmp71_demorgan_fu_1299_p2;
wire [0:0] tmp17_fu_1305_p2;
wire grp_fu_816_ce;
wire [4:0] grp_fu_816_opcode;
wire grp_fu_821_ce;
wire [4:0] grp_fu_821_opcode;
wire grp_fu_826_ce;
wire [4:0] grp_fu_826_opcode;
wire grp_fu_831_ce;
wire [4:0] grp_fu_831_opcode;
wire grp_fu_836_ce;
wire [4:0] grp_fu_836_opcode;
wire grp_fu_841_ce;
wire [4:0] grp_fu_841_opcode;
wire grp_fu_846_ce;
wire [4:0] grp_fu_846_opcode;
wire grp_fu_851_ce;
wire [4:0] grp_fu_851_opcode;
wire grp_fu_856_ce;
wire grp_fu_860_ce;
wire grp_fu_864_ce;
wire grp_fu_868_ce;
reg [1:0] ap_NS_fsm;
parameter ap_const_logic_1 = 1'b1;
parameter ap_const_logic_0 = 1'b0;
parameter ap_ST_st0_fsm_0 = 2'b00;
parameter ap_ST_st1_fsm_1 = 2'b01;
parameter ap_ST_pp0_stg0_fsm_2 = 2'b10;
parameter ap_ST_st80_fsm_3 = 2'b11;
parameter ap_const_lv1_0 = 1'b0;
parameter ap_const_lv10_0 = 10'b0000000000;
parameter ap_const_lv32_1 = 32'b00000000000000000000000000000001;
parameter ap_const_lv1_1 = 1'b1;
parameter ap_const_lv32_3B03126F = 32'b00111011000000110001001001101111;
parameter ap_const_lv32_BB03126F = 32'b10111011000000110001001001101111;
parameter ap_const_lv10_366 = 10'b1101100110;
parameter ap_const_lv10_1 = 10'b0000000001;
parameter ap_const_lv32_38 = 32'b00000000000000000000000000111000;
parameter ap_const_lv8_4 = 8'b00000100;
parameter ap_const_lv8_1 = 8'b00000001;
parameter ap_const_lv8_FF = 8'b11111111;
parameter ap_const_lv32_4 = 32'b00000000000000000000000000000100;
parameter ap_const_lv32_3D = 32'b00000000000000000000000000111101;
parameter ap_const_lv5_B = 5'b01011;
parameter ap_const_lv5_D = 5'b01101;
parameter ap_true = 1'b1;
computeResultOne grp_computeResultOne_fu_697(
.ap_clk( ap_clk ),
.ap_rst( ap_rst ),
.u( grp_computeResultOne_fu_697_u ),
.ug0( grp_computeResultOne_fu_697_ug0 ),
.ug1( grp_computeResultOne_fu_697_ug1 ),
.ug2( grp_computeResultOne_fu_697_ug2 ),
.ug3( grp_computeResultOne_fu_697_ug3 ),
.ug4( grp_computeResultOne_fu_697_ug4 ),
.ug5( grp_computeResultOne_fu_697_ug5 ),
.g0( grp_computeResultOne_fu_697_g0 ),
.g1( grp_computeResultOne_fu_697_g1 ),
.g2( grp_computeResultOne_fu_697_g2 ),
.g3( grp_computeResultOne_fu_697_g3 ),
.g4( grp_computeResultOne_fu_697_g4 ),
.g5( grp_computeResultOne_fu_697_g5 ),
.f( grp_computeResultOne_fu_697_f ),
.ap_return( grp_computeResultOne_fu_697_ap_return ),
.ap_ce( grp_computeResultOne_fu_697_ap_ce )
);
computeResultOne grp_computeResultOne_fu_730(
.ap_clk( ap_clk ),
.ap_rst( ap_rst ),
.u( grp_computeResultOne_fu_730_u ),
.ug0( grp_computeResultOne_fu_730_ug0 ),
.ug1( grp_computeResultOne_fu_730_ug1 ),
.ug2( grp_computeResultOne_fu_730_ug2 ),
.ug3( grp_computeResultOne_fu_730_ug3 ),
.ug4( grp_computeResultOne_fu_730_ug4 ),
.ug5( grp_computeResultOne_fu_730_ug5 ),
.g0( grp_computeResultOne_fu_730_g0 ),
.g1( grp_computeResultOne_fu_730_g1 ),
.g2( grp_computeResultOne_fu_730_g2 ),
.g3( grp_computeResultOne_fu_730_g3 ),
.g4( grp_computeResultOne_fu_730_g4 ),
.g5( grp_computeResultOne_fu_730_g5 ),
.f( grp_computeResultOne_fu_730_f ),
.ap_return( grp_computeResultOne_fu_730_ap_return ),
.ap_ce( grp_computeResultOne_fu_730_ap_ce )
);
computeResultOne grp_computeResultOne_fu_763(
.ap_clk( ap_clk ),
.ap_rst( ap_rst ),
.u( grp_computeResultOne_fu_763_u ),
.ug0( grp_computeResultOne_fu_763_ug0 ),
.ug1( grp_computeResultOne_fu_763_ug1 ),
.ug2( grp_computeResultOne_fu_763_ug2 ),
.ug3( grp_computeResultOne_fu_763_ug3 ),
.ug4( grp_computeResultOne_fu_763_ug4 ),
.ug5( grp_computeResultOne_fu_763_ug5 ),
.g0( grp_computeResultOne_fu_763_g0 ),
.g1( grp_computeResultOne_fu_763_g1 ),
.g2( grp_computeResultOne_fu_763_g2 ),
.g3( grp_computeResultOne_fu_763_g3 ),
.g4( grp_computeResultOne_fu_763_g4 ),
.g5( grp_computeResultOne_fu_763_g5 ),
.f( grp_computeResultOne_fu_763_f ),
.ap_return( grp_computeResultOne_fu_763_ap_return ),
.ap_ce( grp_computeResultOne_fu_763_ap_ce )
);
computeResultOne grp_computeResultOne_fu_794(
.ap_clk( ap_clk ),
.ap_rst( ap_rst ),
.u( grp_computeResultOne_fu_794_u ),
.ug0( grp_computeResultOne_fu_794_ug0 ),
.ug1( grp_computeResultOne_fu_794_ug1 ),
.ug2( grp_computeResultOne_fu_794_ug2 ),
.ug3( grp_computeResultOne_fu_794_ug3 ),
.ug4( grp_computeResultOne_fu_794_ug4 ),
.ug5( grp_computeResultOne_fu_794_ug5 ),
.g0( grp_computeResultOne_fu_794_g0 ),
.g1( grp_computeResultOne_fu_794_g1 ),
.g2( grp_computeResultOne_fu_794_g2 ),
.g3( grp_computeResultOne_fu_794_g3 ),
.g4( grp_computeResultOne_fu_794_g4 ),
.g5( grp_computeResultOne_fu_794_g5 ),
.f( grp_computeResultOne_fu_794_f ),
.ap_return( grp_computeResultOne_fu_794_ap_return ),
.ap_ce( grp_computeResultOne_fu_794_ap_ce )
);
computeResult_grp_fu_816_ACMP_fcmp_156 #(
.ID( 156 ),
.NUM_STAGE( 3 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 1 ))
computeResult_grp_fu_816_ACMP_fcmp_156_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_816_p0 ),
.din1( grp_fu_816_p1 ),
.ce( grp_fu_816_ce ),
.opcode( grp_fu_816_opcode ),
.dout( grp_fu_816_p2 )
);
computeResult_grp_fu_821_ACMP_fcmp_157 #(
.ID( 157 ),
.NUM_STAGE( 3 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 1 ))
computeResult_grp_fu_821_ACMP_fcmp_157_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_821_p0 ),
.din1( grp_fu_821_p1 ),
.ce( grp_fu_821_ce ),
.opcode( grp_fu_821_opcode ),
.dout( grp_fu_821_p2 )
);
computeResult_grp_fu_826_ACMP_fcmp_158 #(
.ID( 158 ),
.NUM_STAGE( 3 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 1 ))
computeResult_grp_fu_826_ACMP_fcmp_158_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_826_p0 ),
.din1( grp_fu_826_p1 ),
.ce( grp_fu_826_ce ),
.opcode( grp_fu_826_opcode ),
.dout( grp_fu_826_p2 )
);
computeResult_grp_fu_831_ACMP_fcmp_159 #(
.ID( 159 ),
.NUM_STAGE( 3 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 1 ))
computeResult_grp_fu_831_ACMP_fcmp_159_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_831_p0 ),
.din1( grp_fu_831_p1 ),
.ce( grp_fu_831_ce ),
.opcode( grp_fu_831_opcode ),
.dout( grp_fu_831_p2 )
);
computeResult_grp_fu_836_ACMP_fcmp_160 #(
.ID( 160 ),
.NUM_STAGE( 3 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 1 ))
computeResult_grp_fu_836_ACMP_fcmp_160_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_836_p0 ),
.din1( grp_fu_836_p1 ),
.ce( grp_fu_836_ce ),
.opcode( grp_fu_836_opcode ),
.dout( grp_fu_836_p2 )
);
computeResult_grp_fu_841_ACMP_fcmp_161 #(
.ID( 161 ),
.NUM_STAGE( 3 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 1 ))
computeResult_grp_fu_841_ACMP_fcmp_161_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_841_p0 ),
.din1( grp_fu_841_p1 ),
.ce( grp_fu_841_ce ),
.opcode( grp_fu_841_opcode ),
.dout( grp_fu_841_p2 )
);
computeResult_grp_fu_846_ACMP_fcmp_162 #(
.ID( 162 ),
.NUM_STAGE( 3 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 1 ))
computeResult_grp_fu_846_ACMP_fcmp_162_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_846_p0 ),
.din1( grp_fu_846_p1 ),
.ce( grp_fu_846_ce ),
.opcode( grp_fu_846_opcode ),
.dout( grp_fu_846_p2 )
);
computeResult_grp_fu_851_ACMP_fcmp_163 #(
.ID( 163 ),
.NUM_STAGE( 3 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 1 ))
computeResult_grp_fu_851_ACMP_fcmp_163_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_851_p0 ),
.din1( grp_fu_851_p1 ),
.ce( grp_fu_851_ce ),
.opcode( grp_fu_851_opcode ),
.dout( grp_fu_851_p2 )
);
computeResult_grp_fu_856_ACMP_fsub_164 #(
.ID( 164 ),
.NUM_STAGE( 4 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
computeResult_grp_fu_856_ACMP_fsub_164_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_856_p0 ),
.din1( grp_fu_856_p1 ),
.ce( grp_fu_856_ce ),
.dout( grp_fu_856_p2 )
);
computeResult_grp_fu_860_ACMP_fsub_165 #(
.ID( 165 ),
.NUM_STAGE( 4 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
computeResult_grp_fu_860_ACMP_fsub_165_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_860_p0 ),
.din1( grp_fu_860_p1 ),
.ce( grp_fu_860_ce ),
.dout( grp_fu_860_p2 )
);
computeResult_grp_fu_864_ACMP_fsub_166 #(
.ID( 166 ),
.NUM_STAGE( 4 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
computeResult_grp_fu_864_ACMP_fsub_166_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_864_p0 ),
.din1( grp_fu_864_p1 ),
.ce( grp_fu_864_ce ),
.dout( grp_fu_864_p2 )
);
computeResult_grp_fu_868_ACMP_fsub_167 #(
.ID( 167 ),
.NUM_STAGE( 4 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
computeResult_grp_fu_868_ACMP_fsub_167_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_868_p0 ),
.din1( grp_fu_868_p1 ),
.ce( grp_fu_868_ce ),
.dout( grp_fu_868_p2 )
);
/// ap_CS_fsm assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_CS_fsm
if (ap_rst == 1'b1) begin
ap_CS_fsm <= ap_ST_st0_fsm_0;
end else begin
ap_CS_fsm <= ap_NS_fsm;
end
end
/// ap_reg_ppiten_pp0_it0 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it0
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it0 <= ap_const_logic_0;
end else begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & ~(exitcond_fu_876_p2 == ap_const_lv1_0))) begin
ap_reg_ppiten_pp0_it0 <= ap_const_logic_0;
end else if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it0 <= ap_const_logic_1;
end
end
end
/// ap_reg_ppiten_pp0_it1 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it1
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it1 <= ap_const_logic_0;
end else begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (exitcond_fu_876_p2 == ap_const_lv1_0))) begin
ap_reg_ppiten_pp0_it1 <= ap_const_logic_1;
end else if (((ap_ST_st1_fsm_1 == ap_CS_fsm) | ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & ~(exitcond_fu_876_p2 == ap_const_lv1_0)))) begin
ap_reg_ppiten_pp0_it1 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp0_it10 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it10
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it10 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it10 <= ap_reg_ppiten_pp0_it9;
end else if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it10 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp0_it11 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it11
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it11 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it11 <= ap_reg_ppiten_pp0_it10;
end else if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it11 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp0_it12 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it12
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it12 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it12 <= ap_reg_ppiten_pp0_it11;
end else if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it12 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp0_it13 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it13
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it13 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it13 <= ap_reg_ppiten_pp0_it12;
end else if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it13 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp0_it14 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it14
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it14 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it14 <= ap_reg_ppiten_pp0_it13;
end else if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it14 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp0_it15 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it15
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it15 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it15 <= ap_reg_ppiten_pp0_it14;
end else if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it15 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp0_it16 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it16
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it16 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it16 <= ap_reg_ppiten_pp0_it15;
end else if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it16 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp0_it17 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it17
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it17 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it17 <= ap_reg_ppiten_pp0_it16;
end else if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it17 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp0_it18 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it18
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it18 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it18 <= ap_reg_ppiten_pp0_it17;
end else if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it18 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp0_it19 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it19
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it19 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it19 <= ap_reg_ppiten_pp0_it18;
end else if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it19 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp0_it2 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it2
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it2 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it2 <= ap_reg_ppiten_pp0_it1;
end else if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it2 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp0_it20 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it20
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it20 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it20 <= ap_reg_ppiten_pp0_it19;
end else if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it20 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp0_it21 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it21
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it21 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it21 <= ap_reg_ppiten_pp0_it20;
end else if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it21 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp0_it22 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it22
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it22 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it22 <= ap_reg_ppiten_pp0_it21;
end else if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it22 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp0_it23 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it23
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it23 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it23 <= ap_reg_ppiten_pp0_it22;
end else if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it23 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp0_it24 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it24
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it24 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it24 <= ap_reg_ppiten_pp0_it23;
end else if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it24 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp0_it25 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it25
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it25 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it25 <= ap_reg_ppiten_pp0_it24;
end else if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it25 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp0_it26 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it26
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it26 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it26 <= ap_reg_ppiten_pp0_it25;
end else if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it26 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp0_it27 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it27
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it27 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it27 <= ap_reg_ppiten_pp0_it26;
end else if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it27 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp0_it28 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it28
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it28 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it28 <= ap_reg_ppiten_pp0_it27;
end else if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it28 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp0_it29 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it29
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it29 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it29 <= ap_reg_ppiten_pp0_it28;
end else if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it29 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp0_it3 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it3
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it3 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it3 <= ap_reg_ppiten_pp0_it2;
end else if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it3 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp0_it30 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it30
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it30 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it30 <= ap_reg_ppiten_pp0_it29;
end else if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it30 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp0_it31 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it31
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it31 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it31 <= ap_reg_ppiten_pp0_it30;
end else if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it31 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp0_it32 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it32
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it32 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it32 <= ap_reg_ppiten_pp0_it31;
end else if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it32 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp0_it33 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it33
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it33 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it33 <= ap_reg_ppiten_pp0_it32;
end else if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it33 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp0_it34 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it34
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it34 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it34 <= ap_reg_ppiten_pp0_it33;
end else if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it34 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp0_it35 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it35
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it35 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it35 <= ap_reg_ppiten_pp0_it34;
end else if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it35 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp0_it36 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it36
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it36 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it36 <= ap_reg_ppiten_pp0_it35;
end else if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it36 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp0_it37 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it37
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it37 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it37 <= ap_reg_ppiten_pp0_it36;
end else if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it37 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp0_it38 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it38
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it38 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it38 <= ap_reg_ppiten_pp0_it37;
end else if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it38 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp0_it39 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it39
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it39 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it39 <= ap_reg_ppiten_pp0_it38;
end else if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it39 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp0_it4 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it4
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it4 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it4 <= ap_reg_ppiten_pp0_it3;
end else if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it4 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp0_it40 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it40
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it40 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it40 <= ap_reg_ppiten_pp0_it39;
end else if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it40 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp0_it41 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it41
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it41 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it41 <= ap_reg_ppiten_pp0_it40;
end else if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it41 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp0_it42 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it42
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it42 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it42 <= ap_reg_ppiten_pp0_it41;
end else if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it42 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp0_it43 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it43
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it43 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it43 <= ap_reg_ppiten_pp0_it42;
end else if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it43 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp0_it44 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it44
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it44 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it44 <= ap_reg_ppiten_pp0_it43;
end else if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it44 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp0_it45 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it45
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it45 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it45 <= ap_reg_ppiten_pp0_it44;
end else if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it45 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp0_it46 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it46
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it46 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it46 <= ap_reg_ppiten_pp0_it45;
end else if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it46 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp0_it47 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it47
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it47 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it47 <= ap_reg_ppiten_pp0_it46;
end else if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it47 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp0_it48 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it48
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it48 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it48 <= ap_reg_ppiten_pp0_it47;
end else if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it48 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp0_it49 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it49
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it49 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it49 <= ap_reg_ppiten_pp0_it48;
end else if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it49 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp0_it5 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it5
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it5 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it5 <= ap_reg_ppiten_pp0_it4;
end else if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it5 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp0_it50 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it50
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it50 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it50 <= ap_reg_ppiten_pp0_it49;
end else if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it50 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp0_it51 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it51
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it51 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it51 <= ap_reg_ppiten_pp0_it50;
end else if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it51 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp0_it52 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it52
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it52 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it52 <= ap_reg_ppiten_pp0_it51;
end else if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it52 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp0_it53 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it53
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it53 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it53 <= ap_reg_ppiten_pp0_it52;
end else if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it53 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp0_it54 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it54
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it54 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it54 <= ap_reg_ppiten_pp0_it53;
end else if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it54 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp0_it55 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it55
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it55 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it55 <= ap_reg_ppiten_pp0_it54;
end else if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it55 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp0_it56 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it56
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it56 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it56 <= ap_reg_ppiten_pp0_it55;
end else if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it56 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp0_it57 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it57
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it57 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it57 <= ap_reg_ppiten_pp0_it56;
end else if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it57 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp0_it58 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it58
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it58 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it58 <= ap_reg_ppiten_pp0_it57;
end else if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it58 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp0_it59 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it59
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it59 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it59 <= ap_reg_ppiten_pp0_it58;
end else if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it59 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp0_it6 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it6
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it6 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it6 <= ap_reg_ppiten_pp0_it5;
end else if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it6 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp0_it60 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it60
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it60 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it60 <= ap_reg_ppiten_pp0_it59;
end else if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it60 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp0_it61 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it61
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it61 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it61 <= ap_reg_ppiten_pp0_it60;
end else if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it61 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp0_it62 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it62
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it62 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it62 <= ap_reg_ppiten_pp0_it61;
end else if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it62 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp0_it63 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it63
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it63 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it63 <= ap_reg_ppiten_pp0_it62;
end else if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it63 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp0_it64 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it64
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it64 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it64 <= ap_reg_ppiten_pp0_it63;
end else if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it64 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp0_it65 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it65
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it65 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it65 <= ap_reg_ppiten_pp0_it64;
end else if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it65 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp0_it66 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it66
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it66 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it66 <= ap_reg_ppiten_pp0_it65;
end else if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it66 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp0_it67 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it67
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it67 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it67 <= ap_reg_ppiten_pp0_it66;
end else if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it67 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp0_it68 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it68
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it68 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it68 <= ap_reg_ppiten_pp0_it67;
end else if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it68 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp0_it69 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it69
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it69 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it69 <= ap_reg_ppiten_pp0_it68;
end else if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it69 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp0_it7 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it7
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it7 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it7 <= ap_reg_ppiten_pp0_it6;
end else if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it7 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp0_it70 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it70
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it70 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it70 <= ap_reg_ppiten_pp0_it69;
end else if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it70 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp0_it71 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it71
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it71 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it71 <= ap_reg_ppiten_pp0_it70;
end else if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it71 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp0_it72 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it72
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it72 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it72 <= ap_reg_ppiten_pp0_it71;
end else if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it72 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp0_it73 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it73
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it73 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it73 <= ap_reg_ppiten_pp0_it72;
end else if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it73 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp0_it74 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it74
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it74 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it74 <= ap_reg_ppiten_pp0_it73;
end else if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it74 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp0_it75 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it75
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it75 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it75 <= ap_reg_ppiten_pp0_it74;
end else if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it75 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp0_it76 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it76
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it76 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it76 <= ap_reg_ppiten_pp0_it75;
end else if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it76 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp0_it77 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it77
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it77 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it77 <= ap_reg_ppiten_pp0_it76;
end else if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it77 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp0_it8 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it8
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it8 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it8 <= ap_reg_ppiten_pp0_it7;
end else if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it8 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp0_it9 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it9
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it9 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it9 <= ap_reg_ppiten_pp0_it8;
end else if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it9 <= ap_const_logic_0;
end
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it77) & (ap_reg_ppstg_exitcond_reg_1396_pp0_it76 == ap_const_lv1_0))) begin
Convergence_reg_673 <= Convergence_1_phi_fu_689_p4;
end else if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
Convergence_reg_673 <= ap_const_lv1_1;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond_reg_1396_pp0_it1 <= exitcond_reg_1396;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond_reg_1396_pp0_it10 <= ap_reg_ppstg_exitcond_reg_1396_pp0_it9;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond_reg_1396_pp0_it11 <= ap_reg_ppstg_exitcond_reg_1396_pp0_it10;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond_reg_1396_pp0_it12 <= ap_reg_ppstg_exitcond_reg_1396_pp0_it11;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond_reg_1396_pp0_it13 <= ap_reg_ppstg_exitcond_reg_1396_pp0_it12;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond_reg_1396_pp0_it14 <= ap_reg_ppstg_exitcond_reg_1396_pp0_it13;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond_reg_1396_pp0_it15 <= ap_reg_ppstg_exitcond_reg_1396_pp0_it14;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond_reg_1396_pp0_it16 <= ap_reg_ppstg_exitcond_reg_1396_pp0_it15;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond_reg_1396_pp0_it17 <= ap_reg_ppstg_exitcond_reg_1396_pp0_it16;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond_reg_1396_pp0_it18 <= ap_reg_ppstg_exitcond_reg_1396_pp0_it17;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond_reg_1396_pp0_it19 <= ap_reg_ppstg_exitcond_reg_1396_pp0_it18;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond_reg_1396_pp0_it2 <= ap_reg_ppstg_exitcond_reg_1396_pp0_it1;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond_reg_1396_pp0_it20 <= ap_reg_ppstg_exitcond_reg_1396_pp0_it19;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond_reg_1396_pp0_it21 <= ap_reg_ppstg_exitcond_reg_1396_pp0_it20;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond_reg_1396_pp0_it22 <= ap_reg_ppstg_exitcond_reg_1396_pp0_it21;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond_reg_1396_pp0_it23 <= ap_reg_ppstg_exitcond_reg_1396_pp0_it22;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond_reg_1396_pp0_it24 <= ap_reg_ppstg_exitcond_reg_1396_pp0_it23;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond_reg_1396_pp0_it25 <= ap_reg_ppstg_exitcond_reg_1396_pp0_it24;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond_reg_1396_pp0_it26 <= ap_reg_ppstg_exitcond_reg_1396_pp0_it25;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond_reg_1396_pp0_it27 <= ap_reg_ppstg_exitcond_reg_1396_pp0_it26;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond_reg_1396_pp0_it28 <= ap_reg_ppstg_exitcond_reg_1396_pp0_it27;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond_reg_1396_pp0_it29 <= ap_reg_ppstg_exitcond_reg_1396_pp0_it28;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond_reg_1396_pp0_it3 <= ap_reg_ppstg_exitcond_reg_1396_pp0_it2;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond_reg_1396_pp0_it30 <= ap_reg_ppstg_exitcond_reg_1396_pp0_it29;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond_reg_1396_pp0_it31 <= ap_reg_ppstg_exitcond_reg_1396_pp0_it30;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond_reg_1396_pp0_it32 <= ap_reg_ppstg_exitcond_reg_1396_pp0_it31;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond_reg_1396_pp0_it33 <= ap_reg_ppstg_exitcond_reg_1396_pp0_it32;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond_reg_1396_pp0_it34 <= ap_reg_ppstg_exitcond_reg_1396_pp0_it33;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond_reg_1396_pp0_it35 <= ap_reg_ppstg_exitcond_reg_1396_pp0_it34;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond_reg_1396_pp0_it36 <= ap_reg_ppstg_exitcond_reg_1396_pp0_it35;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond_reg_1396_pp0_it37 <= ap_reg_ppstg_exitcond_reg_1396_pp0_it36;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond_reg_1396_pp0_it38 <= ap_reg_ppstg_exitcond_reg_1396_pp0_it37;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond_reg_1396_pp0_it39 <= ap_reg_ppstg_exitcond_reg_1396_pp0_it38;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond_reg_1396_pp0_it4 <= ap_reg_ppstg_exitcond_reg_1396_pp0_it3;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond_reg_1396_pp0_it40 <= ap_reg_ppstg_exitcond_reg_1396_pp0_it39;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond_reg_1396_pp0_it41 <= ap_reg_ppstg_exitcond_reg_1396_pp0_it40;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond_reg_1396_pp0_it42 <= ap_reg_ppstg_exitcond_reg_1396_pp0_it41;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond_reg_1396_pp0_it43 <= ap_reg_ppstg_exitcond_reg_1396_pp0_it42;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond_reg_1396_pp0_it44 <= ap_reg_ppstg_exitcond_reg_1396_pp0_it43;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond_reg_1396_pp0_it45 <= ap_reg_ppstg_exitcond_reg_1396_pp0_it44;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond_reg_1396_pp0_it46 <= ap_reg_ppstg_exitcond_reg_1396_pp0_it45;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond_reg_1396_pp0_it47 <= ap_reg_ppstg_exitcond_reg_1396_pp0_it46;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond_reg_1396_pp0_it48 <= ap_reg_ppstg_exitcond_reg_1396_pp0_it47;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond_reg_1396_pp0_it49 <= ap_reg_ppstg_exitcond_reg_1396_pp0_it48;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond_reg_1396_pp0_it5 <= ap_reg_ppstg_exitcond_reg_1396_pp0_it4;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond_reg_1396_pp0_it50 <= ap_reg_ppstg_exitcond_reg_1396_pp0_it49;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond_reg_1396_pp0_it51 <= ap_reg_ppstg_exitcond_reg_1396_pp0_it50;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond_reg_1396_pp0_it52 <= ap_reg_ppstg_exitcond_reg_1396_pp0_it51;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond_reg_1396_pp0_it53 <= ap_reg_ppstg_exitcond_reg_1396_pp0_it52;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond_reg_1396_pp0_it54 <= ap_reg_ppstg_exitcond_reg_1396_pp0_it53;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond_reg_1396_pp0_it55 <= ap_reg_ppstg_exitcond_reg_1396_pp0_it54;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond_reg_1396_pp0_it56 <= ap_reg_ppstg_exitcond_reg_1396_pp0_it55;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond_reg_1396_pp0_it57 <= ap_reg_ppstg_exitcond_reg_1396_pp0_it56;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond_reg_1396_pp0_it58 <= ap_reg_ppstg_exitcond_reg_1396_pp0_it57;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond_reg_1396_pp0_it59 <= ap_reg_ppstg_exitcond_reg_1396_pp0_it58;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond_reg_1396_pp0_it6 <= ap_reg_ppstg_exitcond_reg_1396_pp0_it5;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond_reg_1396_pp0_it60 <= ap_reg_ppstg_exitcond_reg_1396_pp0_it59;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond_reg_1396_pp0_it61 <= ap_reg_ppstg_exitcond_reg_1396_pp0_it60;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond_reg_1396_pp0_it62 <= ap_reg_ppstg_exitcond_reg_1396_pp0_it61;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond_reg_1396_pp0_it63 <= ap_reg_ppstg_exitcond_reg_1396_pp0_it62;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond_reg_1396_pp0_it64 <= ap_reg_ppstg_exitcond_reg_1396_pp0_it63;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond_reg_1396_pp0_it65 <= ap_reg_ppstg_exitcond_reg_1396_pp0_it64;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond_reg_1396_pp0_it66 <= ap_reg_ppstg_exitcond_reg_1396_pp0_it65;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond_reg_1396_pp0_it67 <= ap_reg_ppstg_exitcond_reg_1396_pp0_it66;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond_reg_1396_pp0_it68 <= ap_reg_ppstg_exitcond_reg_1396_pp0_it67;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond_reg_1396_pp0_it69 <= ap_reg_ppstg_exitcond_reg_1396_pp0_it68;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond_reg_1396_pp0_it7 <= ap_reg_ppstg_exitcond_reg_1396_pp0_it6;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond_reg_1396_pp0_it70 <= ap_reg_ppstg_exitcond_reg_1396_pp0_it69;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond_reg_1396_pp0_it71 <= ap_reg_ppstg_exitcond_reg_1396_pp0_it70;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond_reg_1396_pp0_it72 <= ap_reg_ppstg_exitcond_reg_1396_pp0_it71;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond_reg_1396_pp0_it73 <= ap_reg_ppstg_exitcond_reg_1396_pp0_it72;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond_reg_1396_pp0_it74 <= ap_reg_ppstg_exitcond_reg_1396_pp0_it73;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond_reg_1396_pp0_it75 <= ap_reg_ppstg_exitcond_reg_1396_pp0_it74;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond_reg_1396_pp0_it76 <= ap_reg_ppstg_exitcond_reg_1396_pp0_it75;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond_reg_1396_pp0_it8 <= ap_reg_ppstg_exitcond_reg_1396_pp0_it7;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond_reg_1396_pp0_it9 <= ap_reg_ppstg_exitcond_reg_1396_pp0_it8;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it1[0] <= g2_p3_addr107_cast_reg_1422[0];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it1[1] <= g2_p3_addr107_cast_reg_1422[1];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it1[2] <= g2_p3_addr107_cast_reg_1422[2];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it1[3] <= g2_p3_addr107_cast_reg_1422[3];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it1[4] <= g2_p3_addr107_cast_reg_1422[4];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it1[5] <= g2_p3_addr107_cast_reg_1422[5];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it1[6] <= g2_p3_addr107_cast_reg_1422[6];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it1[7] <= g2_p3_addr107_cast_reg_1422[7];
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it10[0] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it9[0];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it10[1] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it9[1];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it10[2] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it9[2];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it10[3] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it9[3];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it10[4] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it9[4];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it10[5] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it9[5];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it10[6] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it9[6];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it10[7] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it9[7];
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it11[0] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it10[0];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it11[1] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it10[1];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it11[2] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it10[2];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it11[3] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it10[3];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it11[4] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it10[4];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it11[5] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it10[5];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it11[6] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it10[6];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it11[7] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it10[7];
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it12[0] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it11[0];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it12[1] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it11[1];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it12[2] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it11[2];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it12[3] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it11[3];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it12[4] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it11[4];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it12[5] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it11[5];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it12[6] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it11[6];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it12[7] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it11[7];
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it13[0] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it12[0];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it13[1] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it12[1];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it13[2] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it12[2];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it13[3] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it12[3];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it13[4] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it12[4];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it13[5] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it12[5];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it13[6] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it12[6];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it13[7] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it12[7];
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it14[0] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it13[0];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it14[1] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it13[1];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it14[2] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it13[2];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it14[3] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it13[3];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it14[4] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it13[4];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it14[5] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it13[5];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it14[6] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it13[6];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it14[7] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it13[7];
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it15[0] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it14[0];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it15[1] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it14[1];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it15[2] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it14[2];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it15[3] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it14[3];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it15[4] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it14[4];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it15[5] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it14[5];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it15[6] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it14[6];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it15[7] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it14[7];
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it16[0] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it15[0];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it16[1] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it15[1];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it16[2] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it15[2];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it16[3] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it15[3];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it16[4] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it15[4];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it16[5] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it15[5];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it16[6] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it15[6];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it16[7] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it15[7];
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it17[0] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it16[0];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it17[1] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it16[1];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it17[2] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it16[2];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it17[3] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it16[3];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it17[4] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it16[4];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it17[5] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it16[5];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it17[6] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it16[6];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it17[7] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it16[7];
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it18[0] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it17[0];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it18[1] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it17[1];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it18[2] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it17[2];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it18[3] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it17[3];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it18[4] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it17[4];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it18[5] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it17[5];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it18[6] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it17[6];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it18[7] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it17[7];
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it19[0] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it18[0];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it19[1] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it18[1];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it19[2] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it18[2];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it19[3] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it18[3];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it19[4] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it18[4];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it19[5] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it18[5];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it19[6] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it18[6];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it19[7] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it18[7];
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it2[0] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it1[0];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it2[1] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it1[1];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it2[2] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it1[2];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it2[3] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it1[3];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it2[4] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it1[4];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it2[5] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it1[5];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it2[6] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it1[6];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it2[7] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it1[7];
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it20[0] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it19[0];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it20[1] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it19[1];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it20[2] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it19[2];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it20[3] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it19[3];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it20[4] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it19[4];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it20[5] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it19[5];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it20[6] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it19[6];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it20[7] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it19[7];
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it21[0] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it20[0];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it21[1] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it20[1];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it21[2] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it20[2];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it21[3] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it20[3];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it21[4] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it20[4];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it21[5] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it20[5];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it21[6] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it20[6];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it21[7] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it20[7];
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it22[0] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it21[0];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it22[1] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it21[1];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it22[2] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it21[2];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it22[3] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it21[3];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it22[4] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it21[4];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it22[5] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it21[5];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it22[6] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it21[6];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it22[7] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it21[7];
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it23[0] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it22[0];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it23[1] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it22[1];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it23[2] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it22[2];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it23[3] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it22[3];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it23[4] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it22[4];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it23[5] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it22[5];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it23[6] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it22[6];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it23[7] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it22[7];
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it24[0] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it23[0];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it24[1] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it23[1];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it24[2] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it23[2];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it24[3] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it23[3];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it24[4] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it23[4];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it24[5] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it23[5];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it24[6] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it23[6];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it24[7] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it23[7];
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it25[0] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it24[0];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it25[1] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it24[1];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it25[2] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it24[2];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it25[3] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it24[3];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it25[4] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it24[4];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it25[5] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it24[5];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it25[6] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it24[6];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it25[7] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it24[7];
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it26[0] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it25[0];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it26[1] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it25[1];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it26[2] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it25[2];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it26[3] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it25[3];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it26[4] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it25[4];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it26[5] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it25[5];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it26[6] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it25[6];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it26[7] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it25[7];
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it27[0] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it26[0];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it27[1] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it26[1];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it27[2] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it26[2];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it27[3] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it26[3];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it27[4] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it26[4];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it27[5] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it26[5];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it27[6] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it26[6];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it27[7] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it26[7];
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it28[0] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it27[0];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it28[1] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it27[1];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it28[2] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it27[2];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it28[3] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it27[3];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it28[4] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it27[4];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it28[5] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it27[5];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it28[6] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it27[6];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it28[7] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it27[7];
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it29[0] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it28[0];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it29[1] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it28[1];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it29[2] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it28[2];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it29[3] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it28[3];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it29[4] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it28[4];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it29[5] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it28[5];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it29[6] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it28[6];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it29[7] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it28[7];
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it3[0] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it2[0];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it3[1] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it2[1];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it3[2] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it2[2];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it3[3] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it2[3];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it3[4] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it2[4];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it3[5] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it2[5];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it3[6] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it2[6];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it3[7] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it2[7];
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it30[0] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it29[0];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it30[1] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it29[1];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it30[2] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it29[2];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it30[3] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it29[3];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it30[4] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it29[4];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it30[5] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it29[5];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it30[6] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it29[6];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it30[7] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it29[7];
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it31[0] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it30[0];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it31[1] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it30[1];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it31[2] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it30[2];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it31[3] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it30[3];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it31[4] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it30[4];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it31[5] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it30[5];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it31[6] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it30[6];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it31[7] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it30[7];
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it32[0] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it31[0];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it32[1] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it31[1];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it32[2] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it31[2];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it32[3] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it31[3];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it32[4] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it31[4];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it32[5] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it31[5];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it32[6] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it31[6];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it32[7] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it31[7];
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it33[0] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it32[0];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it33[1] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it32[1];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it33[2] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it32[2];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it33[3] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it32[3];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it33[4] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it32[4];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it33[5] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it32[5];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it33[6] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it32[6];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it33[7] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it32[7];
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it34[0] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it33[0];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it34[1] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it33[1];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it34[2] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it33[2];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it34[3] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it33[3];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it34[4] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it33[4];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it34[5] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it33[5];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it34[6] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it33[6];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it34[7] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it33[7];
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it35[0] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it34[0];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it35[1] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it34[1];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it35[2] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it34[2];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it35[3] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it34[3];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it35[4] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it34[4];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it35[5] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it34[5];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it35[6] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it34[6];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it35[7] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it34[7];
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it36[0] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it35[0];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it36[1] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it35[1];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it36[2] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it35[2];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it36[3] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it35[3];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it36[4] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it35[4];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it36[5] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it35[5];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it36[6] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it35[6];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it36[7] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it35[7];
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it37[0] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it36[0];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it37[1] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it36[1];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it37[2] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it36[2];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it37[3] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it36[3];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it37[4] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it36[4];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it37[5] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it36[5];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it37[6] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it36[6];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it37[7] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it36[7];
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it38[0] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it37[0];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it38[1] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it37[1];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it38[2] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it37[2];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it38[3] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it37[3];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it38[4] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it37[4];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it38[5] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it37[5];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it38[6] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it37[6];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it38[7] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it37[7];
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it39[0] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it38[0];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it39[1] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it38[1];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it39[2] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it38[2];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it39[3] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it38[3];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it39[4] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it38[4];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it39[5] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it38[5];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it39[6] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it38[6];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it39[7] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it38[7];
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it4[0] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it3[0];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it4[1] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it3[1];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it4[2] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it3[2];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it4[3] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it3[3];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it4[4] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it3[4];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it4[5] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it3[5];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it4[6] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it3[6];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it4[7] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it3[7];
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it40[0] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it39[0];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it40[1] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it39[1];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it40[2] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it39[2];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it40[3] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it39[3];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it40[4] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it39[4];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it40[5] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it39[5];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it40[6] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it39[6];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it40[7] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it39[7];
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it41[0] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it40[0];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it41[1] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it40[1];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it41[2] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it40[2];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it41[3] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it40[3];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it41[4] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it40[4];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it41[5] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it40[5];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it41[6] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it40[6];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it41[7] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it40[7];
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it42[0] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it41[0];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it42[1] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it41[1];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it42[2] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it41[2];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it42[3] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it41[3];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it42[4] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it41[4];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it42[5] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it41[5];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it42[6] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it41[6];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it42[7] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it41[7];
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it43[0] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it42[0];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it43[1] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it42[1];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it43[2] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it42[2];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it43[3] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it42[3];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it43[4] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it42[4];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it43[5] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it42[5];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it43[6] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it42[6];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it43[7] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it42[7];
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it44[0] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it43[0];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it44[1] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it43[1];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it44[2] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it43[2];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it44[3] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it43[3];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it44[4] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it43[4];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it44[5] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it43[5];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it44[6] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it43[6];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it44[7] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it43[7];
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it45[0] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it44[0];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it45[1] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it44[1];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it45[2] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it44[2];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it45[3] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it44[3];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it45[4] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it44[4];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it45[5] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it44[5];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it45[6] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it44[6];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it45[7] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it44[7];
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it46[0] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it45[0];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it46[1] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it45[1];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it46[2] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it45[2];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it46[3] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it45[3];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it46[4] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it45[4];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it46[5] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it45[5];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it46[6] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it45[6];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it46[7] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it45[7];
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it47[0] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it46[0];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it47[1] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it46[1];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it47[2] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it46[2];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it47[3] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it46[3];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it47[4] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it46[4];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it47[5] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it46[5];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it47[6] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it46[6];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it47[7] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it46[7];
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it48[0] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it47[0];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it48[1] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it47[1];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it48[2] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it47[2];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it48[3] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it47[3];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it48[4] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it47[4];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it48[5] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it47[5];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it48[6] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it47[6];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it48[7] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it47[7];
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it49[0] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it48[0];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it49[1] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it48[1];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it49[2] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it48[2];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it49[3] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it48[3];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it49[4] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it48[4];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it49[5] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it48[5];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it49[6] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it48[6];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it49[7] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it48[7];
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it5[0] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it4[0];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it5[1] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it4[1];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it5[2] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it4[2];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it5[3] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it4[3];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it5[4] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it4[4];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it5[5] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it4[5];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it5[6] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it4[6];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it5[7] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it4[7];
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it50[0] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it49[0];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it50[1] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it49[1];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it50[2] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it49[2];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it50[3] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it49[3];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it50[4] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it49[4];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it50[5] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it49[5];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it50[6] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it49[6];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it50[7] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it49[7];
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it51[0] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it50[0];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it51[1] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it50[1];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it51[2] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it50[2];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it51[3] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it50[3];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it51[4] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it50[4];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it51[5] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it50[5];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it51[6] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it50[6];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it51[7] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it50[7];
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it52[0] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it51[0];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it52[1] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it51[1];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it52[2] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it51[2];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it52[3] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it51[3];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it52[4] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it51[4];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it52[5] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it51[5];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it52[6] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it51[6];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it52[7] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it51[7];
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it53[0] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it52[0];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it53[1] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it52[1];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it53[2] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it52[2];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it53[3] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it52[3];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it53[4] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it52[4];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it53[5] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it52[5];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it53[6] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it52[6];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it53[7] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it52[7];
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it54[0] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it53[0];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it54[1] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it53[1];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it54[2] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it53[2];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it54[3] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it53[3];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it54[4] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it53[4];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it54[5] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it53[5];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it54[6] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it53[6];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it54[7] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it53[7];
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it55[0] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it54[0];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it55[1] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it54[1];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it55[2] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it54[2];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it55[3] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it54[3];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it55[4] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it54[4];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it55[5] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it54[5];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it55[6] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it54[6];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it55[7] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it54[7];
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it56[0] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it55[0];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it56[1] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it55[1];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it56[2] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it55[2];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it56[3] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it55[3];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it56[4] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it55[4];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it56[5] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it55[5];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it56[6] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it55[6];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it56[7] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it55[7];
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it57[0] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it56[0];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it57[1] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it56[1];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it57[2] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it56[2];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it57[3] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it56[3];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it57[4] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it56[4];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it57[5] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it56[5];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it57[6] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it56[6];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it57[7] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it56[7];
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it58[0] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it57[0];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it58[1] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it57[1];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it58[2] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it57[2];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it58[3] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it57[3];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it58[4] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it57[4];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it58[5] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it57[5];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it58[6] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it57[6];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it58[7] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it57[7];
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it59[0] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it58[0];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it59[1] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it58[1];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it59[2] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it58[2];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it59[3] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it58[3];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it59[4] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it58[4];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it59[5] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it58[5];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it59[6] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it58[6];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it59[7] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it58[7];
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it6[0] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it5[0];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it6[1] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it5[1];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it6[2] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it5[2];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it6[3] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it5[3];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it6[4] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it5[4];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it6[5] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it5[5];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it6[6] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it5[6];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it6[7] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it5[7];
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it60[0] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it59[0];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it60[1] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it59[1];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it60[2] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it59[2];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it60[3] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it59[3];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it60[4] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it59[4];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it60[5] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it59[5];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it60[6] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it59[6];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it60[7] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it59[7];
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it61[0] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it60[0];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it61[1] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it60[1];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it61[2] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it60[2];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it61[3] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it60[3];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it61[4] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it60[4];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it61[5] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it60[5];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it61[6] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it60[6];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it61[7] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it60[7];
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it62[0] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it61[0];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it62[1] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it61[1];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it62[2] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it61[2];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it62[3] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it61[3];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it62[4] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it61[4];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it62[5] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it61[5];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it62[6] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it61[6];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it62[7] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it61[7];
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it63[0] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it62[0];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it63[1] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it62[1];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it63[2] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it62[2];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it63[3] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it62[3];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it63[4] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it62[4];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it63[5] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it62[5];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it63[6] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it62[6];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it63[7] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it62[7];
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it64[0] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it63[0];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it64[1] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it63[1];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it64[2] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it63[2];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it64[3] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it63[3];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it64[4] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it63[4];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it64[5] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it63[5];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it64[6] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it63[6];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it64[7] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it63[7];
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it65[0] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it64[0];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it65[1] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it64[1];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it65[2] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it64[2];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it65[3] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it64[3];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it65[4] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it64[4];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it65[5] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it64[5];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it65[6] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it64[6];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it65[7] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it64[7];
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it66[0] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it65[0];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it66[1] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it65[1];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it66[2] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it65[2];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it66[3] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it65[3];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it66[4] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it65[4];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it66[5] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it65[5];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it66[6] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it65[6];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it66[7] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it65[7];
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it67[0] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it66[0];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it67[1] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it66[1];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it67[2] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it66[2];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it67[3] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it66[3];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it67[4] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it66[4];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it67[5] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it66[5];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it67[6] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it66[6];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it67[7] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it66[7];
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it68[0] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it67[0];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it68[1] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it67[1];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it68[2] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it67[2];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it68[3] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it67[3];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it68[4] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it67[4];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it68[5] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it67[5];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it68[6] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it67[6];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it68[7] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it67[7];
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it69[0] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it68[0];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it69[1] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it68[1];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it69[2] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it68[2];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it69[3] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it68[3];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it69[4] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it68[4];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it69[5] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it68[5];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it69[6] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it68[6];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it69[7] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it68[7];
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it7[0] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it6[0];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it7[1] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it6[1];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it7[2] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it6[2];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it7[3] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it6[3];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it7[4] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it6[4];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it7[5] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it6[5];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it7[6] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it6[6];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it7[7] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it6[7];
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it8[0] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it7[0];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it8[1] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it7[1];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it8[2] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it7[2];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it8[3] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it7[3];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it8[4] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it7[4];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it8[5] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it7[5];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it8[6] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it7[6];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it8[7] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it7[7];
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it9[0] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it8[0];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it9[1] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it8[1];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it9[2] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it8[2];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it9[3] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it8[3];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it9[4] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it8[4];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it9[5] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it8[5];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it9[6] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it8[6];
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it9[7] <= ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it8[7];
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_reg_1405_pp0_it1 <= tmp_reg_1405;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_reg_1405_pp0_it10 <= ap_reg_ppstg_tmp_reg_1405_pp0_it9;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_reg_1405_pp0_it11 <= ap_reg_ppstg_tmp_reg_1405_pp0_it10;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_reg_1405_pp0_it12 <= ap_reg_ppstg_tmp_reg_1405_pp0_it11;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_reg_1405_pp0_it13 <= ap_reg_ppstg_tmp_reg_1405_pp0_it12;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_reg_1405_pp0_it14 <= ap_reg_ppstg_tmp_reg_1405_pp0_it13;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_reg_1405_pp0_it15 <= ap_reg_ppstg_tmp_reg_1405_pp0_it14;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_reg_1405_pp0_it16 <= ap_reg_ppstg_tmp_reg_1405_pp0_it15;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_reg_1405_pp0_it17 <= ap_reg_ppstg_tmp_reg_1405_pp0_it16;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_reg_1405_pp0_it18 <= ap_reg_ppstg_tmp_reg_1405_pp0_it17;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_reg_1405_pp0_it19 <= ap_reg_ppstg_tmp_reg_1405_pp0_it18;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_reg_1405_pp0_it2 <= ap_reg_ppstg_tmp_reg_1405_pp0_it1;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_reg_1405_pp0_it20 <= ap_reg_ppstg_tmp_reg_1405_pp0_it19;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_reg_1405_pp0_it21 <= ap_reg_ppstg_tmp_reg_1405_pp0_it20;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_reg_1405_pp0_it22 <= ap_reg_ppstg_tmp_reg_1405_pp0_it21;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_reg_1405_pp0_it23 <= ap_reg_ppstg_tmp_reg_1405_pp0_it22;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_reg_1405_pp0_it24 <= ap_reg_ppstg_tmp_reg_1405_pp0_it23;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_reg_1405_pp0_it25 <= ap_reg_ppstg_tmp_reg_1405_pp0_it24;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_reg_1405_pp0_it26 <= ap_reg_ppstg_tmp_reg_1405_pp0_it25;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_reg_1405_pp0_it27 <= ap_reg_ppstg_tmp_reg_1405_pp0_it26;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_reg_1405_pp0_it28 <= ap_reg_ppstg_tmp_reg_1405_pp0_it27;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_reg_1405_pp0_it29 <= ap_reg_ppstg_tmp_reg_1405_pp0_it28;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_reg_1405_pp0_it3 <= ap_reg_ppstg_tmp_reg_1405_pp0_it2;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_reg_1405_pp0_it30 <= ap_reg_ppstg_tmp_reg_1405_pp0_it29;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_reg_1405_pp0_it31 <= ap_reg_ppstg_tmp_reg_1405_pp0_it30;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_reg_1405_pp0_it32 <= ap_reg_ppstg_tmp_reg_1405_pp0_it31;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_reg_1405_pp0_it33 <= ap_reg_ppstg_tmp_reg_1405_pp0_it32;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_reg_1405_pp0_it34 <= ap_reg_ppstg_tmp_reg_1405_pp0_it33;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_reg_1405_pp0_it35 <= ap_reg_ppstg_tmp_reg_1405_pp0_it34;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_reg_1405_pp0_it36 <= ap_reg_ppstg_tmp_reg_1405_pp0_it35;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_reg_1405_pp0_it37 <= ap_reg_ppstg_tmp_reg_1405_pp0_it36;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_reg_1405_pp0_it38 <= ap_reg_ppstg_tmp_reg_1405_pp0_it37;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_reg_1405_pp0_it39 <= ap_reg_ppstg_tmp_reg_1405_pp0_it38;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_reg_1405_pp0_it4 <= ap_reg_ppstg_tmp_reg_1405_pp0_it3;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_reg_1405_pp0_it40 <= ap_reg_ppstg_tmp_reg_1405_pp0_it39;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_reg_1405_pp0_it41 <= ap_reg_ppstg_tmp_reg_1405_pp0_it40;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_reg_1405_pp0_it42 <= ap_reg_ppstg_tmp_reg_1405_pp0_it41;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_reg_1405_pp0_it43 <= ap_reg_ppstg_tmp_reg_1405_pp0_it42;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_reg_1405_pp0_it44 <= ap_reg_ppstg_tmp_reg_1405_pp0_it43;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_reg_1405_pp0_it45 <= ap_reg_ppstg_tmp_reg_1405_pp0_it44;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_reg_1405_pp0_it46 <= ap_reg_ppstg_tmp_reg_1405_pp0_it45;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_reg_1405_pp0_it47 <= ap_reg_ppstg_tmp_reg_1405_pp0_it46;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_reg_1405_pp0_it48 <= ap_reg_ppstg_tmp_reg_1405_pp0_it47;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_reg_1405_pp0_it49 <= ap_reg_ppstg_tmp_reg_1405_pp0_it48;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_reg_1405_pp0_it5 <= ap_reg_ppstg_tmp_reg_1405_pp0_it4;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_reg_1405_pp0_it50 <= ap_reg_ppstg_tmp_reg_1405_pp0_it49;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_reg_1405_pp0_it51 <= ap_reg_ppstg_tmp_reg_1405_pp0_it50;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_reg_1405_pp0_it52 <= ap_reg_ppstg_tmp_reg_1405_pp0_it51;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_reg_1405_pp0_it53 <= ap_reg_ppstg_tmp_reg_1405_pp0_it52;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_reg_1405_pp0_it54 <= ap_reg_ppstg_tmp_reg_1405_pp0_it53;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_reg_1405_pp0_it55 <= ap_reg_ppstg_tmp_reg_1405_pp0_it54;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_reg_1405_pp0_it56 <= ap_reg_ppstg_tmp_reg_1405_pp0_it55;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_reg_1405_pp0_it57 <= ap_reg_ppstg_tmp_reg_1405_pp0_it56;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_reg_1405_pp0_it58 <= ap_reg_ppstg_tmp_reg_1405_pp0_it57;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_reg_1405_pp0_it59 <= ap_reg_ppstg_tmp_reg_1405_pp0_it58;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_reg_1405_pp0_it6 <= ap_reg_ppstg_tmp_reg_1405_pp0_it5;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_reg_1405_pp0_it60 <= ap_reg_ppstg_tmp_reg_1405_pp0_it59;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_reg_1405_pp0_it61 <= ap_reg_ppstg_tmp_reg_1405_pp0_it60;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_reg_1405_pp0_it62 <= ap_reg_ppstg_tmp_reg_1405_pp0_it61;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_reg_1405_pp0_it63 <= ap_reg_ppstg_tmp_reg_1405_pp0_it62;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_reg_1405_pp0_it64 <= ap_reg_ppstg_tmp_reg_1405_pp0_it63;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_reg_1405_pp0_it65 <= ap_reg_ppstg_tmp_reg_1405_pp0_it64;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_reg_1405_pp0_it66 <= ap_reg_ppstg_tmp_reg_1405_pp0_it65;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_reg_1405_pp0_it67 <= ap_reg_ppstg_tmp_reg_1405_pp0_it66;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_reg_1405_pp0_it68 <= ap_reg_ppstg_tmp_reg_1405_pp0_it67;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_reg_1405_pp0_it69 <= ap_reg_ppstg_tmp_reg_1405_pp0_it68;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_reg_1405_pp0_it7 <= ap_reg_ppstg_tmp_reg_1405_pp0_it6;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_reg_1405_pp0_it70 <= ap_reg_ppstg_tmp_reg_1405_pp0_it69;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_reg_1405_pp0_it71 <= ap_reg_ppstg_tmp_reg_1405_pp0_it70;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_reg_1405_pp0_it72 <= ap_reg_ppstg_tmp_reg_1405_pp0_it71;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_reg_1405_pp0_it73 <= ap_reg_ppstg_tmp_reg_1405_pp0_it72;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_reg_1405_pp0_it74 <= ap_reg_ppstg_tmp_reg_1405_pp0_it73;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_reg_1405_pp0_it75 <= ap_reg_ppstg_tmp_reg_1405_pp0_it74;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_reg_1405_pp0_it76 <= ap_reg_ppstg_tmp_reg_1405_pp0_it75;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_reg_1405_pp0_it8 <= ap_reg_ppstg_tmp_reg_1405_pp0_it7;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_reg_1405_pp0_it9 <= ap_reg_ppstg_tmp_reg_1405_pp0_it8;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_Local_reg_1620_pp0_it10 <= ap_reg_ppstg_u_Local_reg_1620_pp0_it9;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_Local_reg_1620_pp0_it11 <= ap_reg_ppstg_u_Local_reg_1620_pp0_it10;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_Local_reg_1620_pp0_it12 <= ap_reg_ppstg_u_Local_reg_1620_pp0_it11;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_Local_reg_1620_pp0_it13 <= ap_reg_ppstg_u_Local_reg_1620_pp0_it12;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_Local_reg_1620_pp0_it14 <= ap_reg_ppstg_u_Local_reg_1620_pp0_it13;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_Local_reg_1620_pp0_it15 <= ap_reg_ppstg_u_Local_reg_1620_pp0_it14;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_Local_reg_1620_pp0_it16 <= ap_reg_ppstg_u_Local_reg_1620_pp0_it15;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_Local_reg_1620_pp0_it17 <= ap_reg_ppstg_u_Local_reg_1620_pp0_it16;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_Local_reg_1620_pp0_it18 <= ap_reg_ppstg_u_Local_reg_1620_pp0_it17;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_Local_reg_1620_pp0_it19 <= ap_reg_ppstg_u_Local_reg_1620_pp0_it18;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_Local_reg_1620_pp0_it2 <= u_Local_reg_1620;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_Local_reg_1620_pp0_it20 <= ap_reg_ppstg_u_Local_reg_1620_pp0_it19;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_Local_reg_1620_pp0_it21 <= ap_reg_ppstg_u_Local_reg_1620_pp0_it20;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_Local_reg_1620_pp0_it22 <= ap_reg_ppstg_u_Local_reg_1620_pp0_it21;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_Local_reg_1620_pp0_it23 <= ap_reg_ppstg_u_Local_reg_1620_pp0_it22;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_Local_reg_1620_pp0_it24 <= ap_reg_ppstg_u_Local_reg_1620_pp0_it23;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_Local_reg_1620_pp0_it25 <= ap_reg_ppstg_u_Local_reg_1620_pp0_it24;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_Local_reg_1620_pp0_it26 <= ap_reg_ppstg_u_Local_reg_1620_pp0_it25;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_Local_reg_1620_pp0_it27 <= ap_reg_ppstg_u_Local_reg_1620_pp0_it26;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_Local_reg_1620_pp0_it28 <= ap_reg_ppstg_u_Local_reg_1620_pp0_it27;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_Local_reg_1620_pp0_it29 <= ap_reg_ppstg_u_Local_reg_1620_pp0_it28;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_Local_reg_1620_pp0_it3 <= ap_reg_ppstg_u_Local_reg_1620_pp0_it2;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_Local_reg_1620_pp0_it30 <= ap_reg_ppstg_u_Local_reg_1620_pp0_it29;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_Local_reg_1620_pp0_it31 <= ap_reg_ppstg_u_Local_reg_1620_pp0_it30;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_Local_reg_1620_pp0_it32 <= ap_reg_ppstg_u_Local_reg_1620_pp0_it31;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_Local_reg_1620_pp0_it33 <= ap_reg_ppstg_u_Local_reg_1620_pp0_it32;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_Local_reg_1620_pp0_it34 <= ap_reg_ppstg_u_Local_reg_1620_pp0_it33;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_Local_reg_1620_pp0_it35 <= ap_reg_ppstg_u_Local_reg_1620_pp0_it34;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_Local_reg_1620_pp0_it36 <= ap_reg_ppstg_u_Local_reg_1620_pp0_it35;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_Local_reg_1620_pp0_it37 <= ap_reg_ppstg_u_Local_reg_1620_pp0_it36;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_Local_reg_1620_pp0_it38 <= ap_reg_ppstg_u_Local_reg_1620_pp0_it37;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_Local_reg_1620_pp0_it39 <= ap_reg_ppstg_u_Local_reg_1620_pp0_it38;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_Local_reg_1620_pp0_it4 <= ap_reg_ppstg_u_Local_reg_1620_pp0_it3;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_Local_reg_1620_pp0_it40 <= ap_reg_ppstg_u_Local_reg_1620_pp0_it39;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_Local_reg_1620_pp0_it41 <= ap_reg_ppstg_u_Local_reg_1620_pp0_it40;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_Local_reg_1620_pp0_it42 <= ap_reg_ppstg_u_Local_reg_1620_pp0_it41;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_Local_reg_1620_pp0_it43 <= ap_reg_ppstg_u_Local_reg_1620_pp0_it42;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_Local_reg_1620_pp0_it44 <= ap_reg_ppstg_u_Local_reg_1620_pp0_it43;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_Local_reg_1620_pp0_it45 <= ap_reg_ppstg_u_Local_reg_1620_pp0_it44;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_Local_reg_1620_pp0_it46 <= ap_reg_ppstg_u_Local_reg_1620_pp0_it45;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_Local_reg_1620_pp0_it47 <= ap_reg_ppstg_u_Local_reg_1620_pp0_it46;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_Local_reg_1620_pp0_it48 <= ap_reg_ppstg_u_Local_reg_1620_pp0_it47;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_Local_reg_1620_pp0_it49 <= ap_reg_ppstg_u_Local_reg_1620_pp0_it48;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_Local_reg_1620_pp0_it5 <= ap_reg_ppstg_u_Local_reg_1620_pp0_it4;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_Local_reg_1620_pp0_it50 <= ap_reg_ppstg_u_Local_reg_1620_pp0_it49;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_Local_reg_1620_pp0_it51 <= ap_reg_ppstg_u_Local_reg_1620_pp0_it50;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_Local_reg_1620_pp0_it52 <= ap_reg_ppstg_u_Local_reg_1620_pp0_it51;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_Local_reg_1620_pp0_it53 <= ap_reg_ppstg_u_Local_reg_1620_pp0_it52;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_Local_reg_1620_pp0_it54 <= ap_reg_ppstg_u_Local_reg_1620_pp0_it53;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_Local_reg_1620_pp0_it55 <= ap_reg_ppstg_u_Local_reg_1620_pp0_it54;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_Local_reg_1620_pp0_it56 <= ap_reg_ppstg_u_Local_reg_1620_pp0_it55;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_Local_reg_1620_pp0_it57 <= ap_reg_ppstg_u_Local_reg_1620_pp0_it56;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_Local_reg_1620_pp0_it58 <= ap_reg_ppstg_u_Local_reg_1620_pp0_it57;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_Local_reg_1620_pp0_it59 <= ap_reg_ppstg_u_Local_reg_1620_pp0_it58;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_Local_reg_1620_pp0_it6 <= ap_reg_ppstg_u_Local_reg_1620_pp0_it5;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_Local_reg_1620_pp0_it60 <= ap_reg_ppstg_u_Local_reg_1620_pp0_it59;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_Local_reg_1620_pp0_it61 <= ap_reg_ppstg_u_Local_reg_1620_pp0_it60;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_Local_reg_1620_pp0_it62 <= ap_reg_ppstg_u_Local_reg_1620_pp0_it61;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_Local_reg_1620_pp0_it63 <= ap_reg_ppstg_u_Local_reg_1620_pp0_it62;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_Local_reg_1620_pp0_it64 <= ap_reg_ppstg_u_Local_reg_1620_pp0_it63;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_Local_reg_1620_pp0_it65 <= ap_reg_ppstg_u_Local_reg_1620_pp0_it64;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_Local_reg_1620_pp0_it66 <= ap_reg_ppstg_u_Local_reg_1620_pp0_it65;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_Local_reg_1620_pp0_it67 <= ap_reg_ppstg_u_Local_reg_1620_pp0_it66;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_Local_reg_1620_pp0_it68 <= ap_reg_ppstg_u_Local_reg_1620_pp0_it67;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_Local_reg_1620_pp0_it69 <= ap_reg_ppstg_u_Local_reg_1620_pp0_it68;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_Local_reg_1620_pp0_it7 <= ap_reg_ppstg_u_Local_reg_1620_pp0_it6;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_Local_reg_1620_pp0_it70 <= ap_reg_ppstg_u_Local_reg_1620_pp0_it69;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_Local_reg_1620_pp0_it8 <= ap_reg_ppstg_u_Local_reg_1620_pp0_it7;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_Local_reg_1620_pp0_it9 <= ap_reg_ppstg_u_Local_reg_1620_pp0_it8;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p0_load_reg_1626_pp0_it10 <= ap_reg_ppstg_u_p0_load_reg_1626_pp0_it9;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p0_load_reg_1626_pp0_it11 <= ap_reg_ppstg_u_p0_load_reg_1626_pp0_it10;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p0_load_reg_1626_pp0_it12 <= ap_reg_ppstg_u_p0_load_reg_1626_pp0_it11;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p0_load_reg_1626_pp0_it13 <= ap_reg_ppstg_u_p0_load_reg_1626_pp0_it12;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p0_load_reg_1626_pp0_it14 <= ap_reg_ppstg_u_p0_load_reg_1626_pp0_it13;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p0_load_reg_1626_pp0_it15 <= ap_reg_ppstg_u_p0_load_reg_1626_pp0_it14;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p0_load_reg_1626_pp0_it16 <= ap_reg_ppstg_u_p0_load_reg_1626_pp0_it15;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p0_load_reg_1626_pp0_it17 <= ap_reg_ppstg_u_p0_load_reg_1626_pp0_it16;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p0_load_reg_1626_pp0_it18 <= ap_reg_ppstg_u_p0_load_reg_1626_pp0_it17;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p0_load_reg_1626_pp0_it19 <= ap_reg_ppstg_u_p0_load_reg_1626_pp0_it18;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p0_load_reg_1626_pp0_it2 <= u_p0_load_reg_1626;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p0_load_reg_1626_pp0_it20 <= ap_reg_ppstg_u_p0_load_reg_1626_pp0_it19;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p0_load_reg_1626_pp0_it21 <= ap_reg_ppstg_u_p0_load_reg_1626_pp0_it20;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p0_load_reg_1626_pp0_it22 <= ap_reg_ppstg_u_p0_load_reg_1626_pp0_it21;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p0_load_reg_1626_pp0_it23 <= ap_reg_ppstg_u_p0_load_reg_1626_pp0_it22;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p0_load_reg_1626_pp0_it24 <= ap_reg_ppstg_u_p0_load_reg_1626_pp0_it23;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p0_load_reg_1626_pp0_it25 <= ap_reg_ppstg_u_p0_load_reg_1626_pp0_it24;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p0_load_reg_1626_pp0_it26 <= ap_reg_ppstg_u_p0_load_reg_1626_pp0_it25;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p0_load_reg_1626_pp0_it27 <= ap_reg_ppstg_u_p0_load_reg_1626_pp0_it26;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p0_load_reg_1626_pp0_it28 <= ap_reg_ppstg_u_p0_load_reg_1626_pp0_it27;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p0_load_reg_1626_pp0_it29 <= ap_reg_ppstg_u_p0_load_reg_1626_pp0_it28;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p0_load_reg_1626_pp0_it3 <= ap_reg_ppstg_u_p0_load_reg_1626_pp0_it2;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p0_load_reg_1626_pp0_it30 <= ap_reg_ppstg_u_p0_load_reg_1626_pp0_it29;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p0_load_reg_1626_pp0_it31 <= ap_reg_ppstg_u_p0_load_reg_1626_pp0_it30;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p0_load_reg_1626_pp0_it32 <= ap_reg_ppstg_u_p0_load_reg_1626_pp0_it31;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p0_load_reg_1626_pp0_it33 <= ap_reg_ppstg_u_p0_load_reg_1626_pp0_it32;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p0_load_reg_1626_pp0_it34 <= ap_reg_ppstg_u_p0_load_reg_1626_pp0_it33;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p0_load_reg_1626_pp0_it35 <= ap_reg_ppstg_u_p0_load_reg_1626_pp0_it34;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p0_load_reg_1626_pp0_it36 <= ap_reg_ppstg_u_p0_load_reg_1626_pp0_it35;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p0_load_reg_1626_pp0_it37 <= ap_reg_ppstg_u_p0_load_reg_1626_pp0_it36;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p0_load_reg_1626_pp0_it38 <= ap_reg_ppstg_u_p0_load_reg_1626_pp0_it37;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p0_load_reg_1626_pp0_it39 <= ap_reg_ppstg_u_p0_load_reg_1626_pp0_it38;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p0_load_reg_1626_pp0_it4 <= ap_reg_ppstg_u_p0_load_reg_1626_pp0_it3;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p0_load_reg_1626_pp0_it40 <= ap_reg_ppstg_u_p0_load_reg_1626_pp0_it39;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p0_load_reg_1626_pp0_it41 <= ap_reg_ppstg_u_p0_load_reg_1626_pp0_it40;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p0_load_reg_1626_pp0_it42 <= ap_reg_ppstg_u_p0_load_reg_1626_pp0_it41;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p0_load_reg_1626_pp0_it43 <= ap_reg_ppstg_u_p0_load_reg_1626_pp0_it42;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p0_load_reg_1626_pp0_it44 <= ap_reg_ppstg_u_p0_load_reg_1626_pp0_it43;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p0_load_reg_1626_pp0_it45 <= ap_reg_ppstg_u_p0_load_reg_1626_pp0_it44;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p0_load_reg_1626_pp0_it46 <= ap_reg_ppstg_u_p0_load_reg_1626_pp0_it45;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p0_load_reg_1626_pp0_it47 <= ap_reg_ppstg_u_p0_load_reg_1626_pp0_it46;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p0_load_reg_1626_pp0_it48 <= ap_reg_ppstg_u_p0_load_reg_1626_pp0_it47;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p0_load_reg_1626_pp0_it49 <= ap_reg_ppstg_u_p0_load_reg_1626_pp0_it48;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p0_load_reg_1626_pp0_it5 <= ap_reg_ppstg_u_p0_load_reg_1626_pp0_it4;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p0_load_reg_1626_pp0_it50 <= ap_reg_ppstg_u_p0_load_reg_1626_pp0_it49;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p0_load_reg_1626_pp0_it51 <= ap_reg_ppstg_u_p0_load_reg_1626_pp0_it50;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p0_load_reg_1626_pp0_it52 <= ap_reg_ppstg_u_p0_load_reg_1626_pp0_it51;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p0_load_reg_1626_pp0_it53 <= ap_reg_ppstg_u_p0_load_reg_1626_pp0_it52;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p0_load_reg_1626_pp0_it54 <= ap_reg_ppstg_u_p0_load_reg_1626_pp0_it53;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p0_load_reg_1626_pp0_it55 <= ap_reg_ppstg_u_p0_load_reg_1626_pp0_it54;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p0_load_reg_1626_pp0_it56 <= ap_reg_ppstg_u_p0_load_reg_1626_pp0_it55;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p0_load_reg_1626_pp0_it57 <= ap_reg_ppstg_u_p0_load_reg_1626_pp0_it56;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p0_load_reg_1626_pp0_it58 <= ap_reg_ppstg_u_p0_load_reg_1626_pp0_it57;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p0_load_reg_1626_pp0_it59 <= ap_reg_ppstg_u_p0_load_reg_1626_pp0_it58;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p0_load_reg_1626_pp0_it6 <= ap_reg_ppstg_u_p0_load_reg_1626_pp0_it5;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p0_load_reg_1626_pp0_it60 <= ap_reg_ppstg_u_p0_load_reg_1626_pp0_it59;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p0_load_reg_1626_pp0_it61 <= ap_reg_ppstg_u_p0_load_reg_1626_pp0_it60;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p0_load_reg_1626_pp0_it62 <= ap_reg_ppstg_u_p0_load_reg_1626_pp0_it61;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p0_load_reg_1626_pp0_it63 <= ap_reg_ppstg_u_p0_load_reg_1626_pp0_it62;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p0_load_reg_1626_pp0_it64 <= ap_reg_ppstg_u_p0_load_reg_1626_pp0_it63;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p0_load_reg_1626_pp0_it65 <= ap_reg_ppstg_u_p0_load_reg_1626_pp0_it64;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p0_load_reg_1626_pp0_it66 <= ap_reg_ppstg_u_p0_load_reg_1626_pp0_it65;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p0_load_reg_1626_pp0_it67 <= ap_reg_ppstg_u_p0_load_reg_1626_pp0_it66;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p0_load_reg_1626_pp0_it68 <= ap_reg_ppstg_u_p0_load_reg_1626_pp0_it67;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p0_load_reg_1626_pp0_it69 <= ap_reg_ppstg_u_p0_load_reg_1626_pp0_it68;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p0_load_reg_1626_pp0_it7 <= ap_reg_ppstg_u_p0_load_reg_1626_pp0_it6;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p0_load_reg_1626_pp0_it70 <= ap_reg_ppstg_u_p0_load_reg_1626_pp0_it69;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p0_load_reg_1626_pp0_it8 <= ap_reg_ppstg_u_p0_load_reg_1626_pp0_it7;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p0_load_reg_1626_pp0_it9 <= ap_reg_ppstg_u_p0_load_reg_1626_pp0_it8;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p1_load_reg_1632_pp0_it10 <= ap_reg_ppstg_u_p1_load_reg_1632_pp0_it9;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p1_load_reg_1632_pp0_it11 <= ap_reg_ppstg_u_p1_load_reg_1632_pp0_it10;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p1_load_reg_1632_pp0_it12 <= ap_reg_ppstg_u_p1_load_reg_1632_pp0_it11;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p1_load_reg_1632_pp0_it13 <= ap_reg_ppstg_u_p1_load_reg_1632_pp0_it12;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p1_load_reg_1632_pp0_it14 <= ap_reg_ppstg_u_p1_load_reg_1632_pp0_it13;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p1_load_reg_1632_pp0_it15 <= ap_reg_ppstg_u_p1_load_reg_1632_pp0_it14;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p1_load_reg_1632_pp0_it16 <= ap_reg_ppstg_u_p1_load_reg_1632_pp0_it15;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p1_load_reg_1632_pp0_it17 <= ap_reg_ppstg_u_p1_load_reg_1632_pp0_it16;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p1_load_reg_1632_pp0_it18 <= ap_reg_ppstg_u_p1_load_reg_1632_pp0_it17;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p1_load_reg_1632_pp0_it19 <= ap_reg_ppstg_u_p1_load_reg_1632_pp0_it18;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p1_load_reg_1632_pp0_it2 <= u_p1_load_reg_1632;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p1_load_reg_1632_pp0_it20 <= ap_reg_ppstg_u_p1_load_reg_1632_pp0_it19;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p1_load_reg_1632_pp0_it21 <= ap_reg_ppstg_u_p1_load_reg_1632_pp0_it20;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p1_load_reg_1632_pp0_it22 <= ap_reg_ppstg_u_p1_load_reg_1632_pp0_it21;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p1_load_reg_1632_pp0_it23 <= ap_reg_ppstg_u_p1_load_reg_1632_pp0_it22;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p1_load_reg_1632_pp0_it24 <= ap_reg_ppstg_u_p1_load_reg_1632_pp0_it23;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p1_load_reg_1632_pp0_it25 <= ap_reg_ppstg_u_p1_load_reg_1632_pp0_it24;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p1_load_reg_1632_pp0_it26 <= ap_reg_ppstg_u_p1_load_reg_1632_pp0_it25;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p1_load_reg_1632_pp0_it27 <= ap_reg_ppstg_u_p1_load_reg_1632_pp0_it26;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p1_load_reg_1632_pp0_it28 <= ap_reg_ppstg_u_p1_load_reg_1632_pp0_it27;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p1_load_reg_1632_pp0_it29 <= ap_reg_ppstg_u_p1_load_reg_1632_pp0_it28;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p1_load_reg_1632_pp0_it3 <= ap_reg_ppstg_u_p1_load_reg_1632_pp0_it2;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p1_load_reg_1632_pp0_it30 <= ap_reg_ppstg_u_p1_load_reg_1632_pp0_it29;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p1_load_reg_1632_pp0_it31 <= ap_reg_ppstg_u_p1_load_reg_1632_pp0_it30;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p1_load_reg_1632_pp0_it32 <= ap_reg_ppstg_u_p1_load_reg_1632_pp0_it31;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p1_load_reg_1632_pp0_it33 <= ap_reg_ppstg_u_p1_load_reg_1632_pp0_it32;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p1_load_reg_1632_pp0_it34 <= ap_reg_ppstg_u_p1_load_reg_1632_pp0_it33;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p1_load_reg_1632_pp0_it35 <= ap_reg_ppstg_u_p1_load_reg_1632_pp0_it34;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p1_load_reg_1632_pp0_it36 <= ap_reg_ppstg_u_p1_load_reg_1632_pp0_it35;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p1_load_reg_1632_pp0_it37 <= ap_reg_ppstg_u_p1_load_reg_1632_pp0_it36;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p1_load_reg_1632_pp0_it38 <= ap_reg_ppstg_u_p1_load_reg_1632_pp0_it37;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p1_load_reg_1632_pp0_it39 <= ap_reg_ppstg_u_p1_load_reg_1632_pp0_it38;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p1_load_reg_1632_pp0_it4 <= ap_reg_ppstg_u_p1_load_reg_1632_pp0_it3;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p1_load_reg_1632_pp0_it40 <= ap_reg_ppstg_u_p1_load_reg_1632_pp0_it39;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p1_load_reg_1632_pp0_it41 <= ap_reg_ppstg_u_p1_load_reg_1632_pp0_it40;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p1_load_reg_1632_pp0_it42 <= ap_reg_ppstg_u_p1_load_reg_1632_pp0_it41;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p1_load_reg_1632_pp0_it43 <= ap_reg_ppstg_u_p1_load_reg_1632_pp0_it42;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p1_load_reg_1632_pp0_it44 <= ap_reg_ppstg_u_p1_load_reg_1632_pp0_it43;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p1_load_reg_1632_pp0_it45 <= ap_reg_ppstg_u_p1_load_reg_1632_pp0_it44;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p1_load_reg_1632_pp0_it46 <= ap_reg_ppstg_u_p1_load_reg_1632_pp0_it45;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p1_load_reg_1632_pp0_it47 <= ap_reg_ppstg_u_p1_load_reg_1632_pp0_it46;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p1_load_reg_1632_pp0_it48 <= ap_reg_ppstg_u_p1_load_reg_1632_pp0_it47;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p1_load_reg_1632_pp0_it49 <= ap_reg_ppstg_u_p1_load_reg_1632_pp0_it48;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p1_load_reg_1632_pp0_it5 <= ap_reg_ppstg_u_p1_load_reg_1632_pp0_it4;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p1_load_reg_1632_pp0_it50 <= ap_reg_ppstg_u_p1_load_reg_1632_pp0_it49;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p1_load_reg_1632_pp0_it51 <= ap_reg_ppstg_u_p1_load_reg_1632_pp0_it50;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p1_load_reg_1632_pp0_it52 <= ap_reg_ppstg_u_p1_load_reg_1632_pp0_it51;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p1_load_reg_1632_pp0_it53 <= ap_reg_ppstg_u_p1_load_reg_1632_pp0_it52;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p1_load_reg_1632_pp0_it54 <= ap_reg_ppstg_u_p1_load_reg_1632_pp0_it53;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p1_load_reg_1632_pp0_it55 <= ap_reg_ppstg_u_p1_load_reg_1632_pp0_it54;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p1_load_reg_1632_pp0_it56 <= ap_reg_ppstg_u_p1_load_reg_1632_pp0_it55;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p1_load_reg_1632_pp0_it57 <= ap_reg_ppstg_u_p1_load_reg_1632_pp0_it56;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p1_load_reg_1632_pp0_it58 <= ap_reg_ppstg_u_p1_load_reg_1632_pp0_it57;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p1_load_reg_1632_pp0_it59 <= ap_reg_ppstg_u_p1_load_reg_1632_pp0_it58;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p1_load_reg_1632_pp0_it6 <= ap_reg_ppstg_u_p1_load_reg_1632_pp0_it5;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p1_load_reg_1632_pp0_it60 <= ap_reg_ppstg_u_p1_load_reg_1632_pp0_it59;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p1_load_reg_1632_pp0_it61 <= ap_reg_ppstg_u_p1_load_reg_1632_pp0_it60;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p1_load_reg_1632_pp0_it62 <= ap_reg_ppstg_u_p1_load_reg_1632_pp0_it61;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p1_load_reg_1632_pp0_it63 <= ap_reg_ppstg_u_p1_load_reg_1632_pp0_it62;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p1_load_reg_1632_pp0_it64 <= ap_reg_ppstg_u_p1_load_reg_1632_pp0_it63;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p1_load_reg_1632_pp0_it65 <= ap_reg_ppstg_u_p1_load_reg_1632_pp0_it64;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p1_load_reg_1632_pp0_it66 <= ap_reg_ppstg_u_p1_load_reg_1632_pp0_it65;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p1_load_reg_1632_pp0_it67 <= ap_reg_ppstg_u_p1_load_reg_1632_pp0_it66;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p1_load_reg_1632_pp0_it68 <= ap_reg_ppstg_u_p1_load_reg_1632_pp0_it67;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p1_load_reg_1632_pp0_it69 <= ap_reg_ppstg_u_p1_load_reg_1632_pp0_it68;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p1_load_reg_1632_pp0_it7 <= ap_reg_ppstg_u_p1_load_reg_1632_pp0_it6;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p1_load_reg_1632_pp0_it70 <= ap_reg_ppstg_u_p1_load_reg_1632_pp0_it69;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p1_load_reg_1632_pp0_it8 <= ap_reg_ppstg_u_p1_load_reg_1632_pp0_it7;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p1_load_reg_1632_pp0_it9 <= ap_reg_ppstg_u_p1_load_reg_1632_pp0_it8;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p2_load_reg_1638_pp0_it10 <= ap_reg_ppstg_u_p2_load_reg_1638_pp0_it9;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p2_load_reg_1638_pp0_it11 <= ap_reg_ppstg_u_p2_load_reg_1638_pp0_it10;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p2_load_reg_1638_pp0_it12 <= ap_reg_ppstg_u_p2_load_reg_1638_pp0_it11;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p2_load_reg_1638_pp0_it13 <= ap_reg_ppstg_u_p2_load_reg_1638_pp0_it12;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p2_load_reg_1638_pp0_it14 <= ap_reg_ppstg_u_p2_load_reg_1638_pp0_it13;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p2_load_reg_1638_pp0_it15 <= ap_reg_ppstg_u_p2_load_reg_1638_pp0_it14;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p2_load_reg_1638_pp0_it16 <= ap_reg_ppstg_u_p2_load_reg_1638_pp0_it15;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p2_load_reg_1638_pp0_it17 <= ap_reg_ppstg_u_p2_load_reg_1638_pp0_it16;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p2_load_reg_1638_pp0_it18 <= ap_reg_ppstg_u_p2_load_reg_1638_pp0_it17;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p2_load_reg_1638_pp0_it19 <= ap_reg_ppstg_u_p2_load_reg_1638_pp0_it18;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p2_load_reg_1638_pp0_it2 <= u_p2_load_reg_1638;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p2_load_reg_1638_pp0_it20 <= ap_reg_ppstg_u_p2_load_reg_1638_pp0_it19;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p2_load_reg_1638_pp0_it21 <= ap_reg_ppstg_u_p2_load_reg_1638_pp0_it20;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p2_load_reg_1638_pp0_it22 <= ap_reg_ppstg_u_p2_load_reg_1638_pp0_it21;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p2_load_reg_1638_pp0_it23 <= ap_reg_ppstg_u_p2_load_reg_1638_pp0_it22;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p2_load_reg_1638_pp0_it24 <= ap_reg_ppstg_u_p2_load_reg_1638_pp0_it23;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p2_load_reg_1638_pp0_it25 <= ap_reg_ppstg_u_p2_load_reg_1638_pp0_it24;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p2_load_reg_1638_pp0_it26 <= ap_reg_ppstg_u_p2_load_reg_1638_pp0_it25;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p2_load_reg_1638_pp0_it27 <= ap_reg_ppstg_u_p2_load_reg_1638_pp0_it26;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p2_load_reg_1638_pp0_it28 <= ap_reg_ppstg_u_p2_load_reg_1638_pp0_it27;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p2_load_reg_1638_pp0_it29 <= ap_reg_ppstg_u_p2_load_reg_1638_pp0_it28;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p2_load_reg_1638_pp0_it3 <= ap_reg_ppstg_u_p2_load_reg_1638_pp0_it2;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p2_load_reg_1638_pp0_it30 <= ap_reg_ppstg_u_p2_load_reg_1638_pp0_it29;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p2_load_reg_1638_pp0_it31 <= ap_reg_ppstg_u_p2_load_reg_1638_pp0_it30;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p2_load_reg_1638_pp0_it32 <= ap_reg_ppstg_u_p2_load_reg_1638_pp0_it31;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p2_load_reg_1638_pp0_it33 <= ap_reg_ppstg_u_p2_load_reg_1638_pp0_it32;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p2_load_reg_1638_pp0_it34 <= ap_reg_ppstg_u_p2_load_reg_1638_pp0_it33;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p2_load_reg_1638_pp0_it35 <= ap_reg_ppstg_u_p2_load_reg_1638_pp0_it34;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p2_load_reg_1638_pp0_it36 <= ap_reg_ppstg_u_p2_load_reg_1638_pp0_it35;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p2_load_reg_1638_pp0_it37 <= ap_reg_ppstg_u_p2_load_reg_1638_pp0_it36;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p2_load_reg_1638_pp0_it38 <= ap_reg_ppstg_u_p2_load_reg_1638_pp0_it37;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p2_load_reg_1638_pp0_it39 <= ap_reg_ppstg_u_p2_load_reg_1638_pp0_it38;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p2_load_reg_1638_pp0_it4 <= ap_reg_ppstg_u_p2_load_reg_1638_pp0_it3;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p2_load_reg_1638_pp0_it40 <= ap_reg_ppstg_u_p2_load_reg_1638_pp0_it39;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p2_load_reg_1638_pp0_it41 <= ap_reg_ppstg_u_p2_load_reg_1638_pp0_it40;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p2_load_reg_1638_pp0_it42 <= ap_reg_ppstg_u_p2_load_reg_1638_pp0_it41;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p2_load_reg_1638_pp0_it43 <= ap_reg_ppstg_u_p2_load_reg_1638_pp0_it42;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p2_load_reg_1638_pp0_it44 <= ap_reg_ppstg_u_p2_load_reg_1638_pp0_it43;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p2_load_reg_1638_pp0_it45 <= ap_reg_ppstg_u_p2_load_reg_1638_pp0_it44;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p2_load_reg_1638_pp0_it46 <= ap_reg_ppstg_u_p2_load_reg_1638_pp0_it45;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p2_load_reg_1638_pp0_it47 <= ap_reg_ppstg_u_p2_load_reg_1638_pp0_it46;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p2_load_reg_1638_pp0_it48 <= ap_reg_ppstg_u_p2_load_reg_1638_pp0_it47;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p2_load_reg_1638_pp0_it49 <= ap_reg_ppstg_u_p2_load_reg_1638_pp0_it48;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p2_load_reg_1638_pp0_it5 <= ap_reg_ppstg_u_p2_load_reg_1638_pp0_it4;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p2_load_reg_1638_pp0_it50 <= ap_reg_ppstg_u_p2_load_reg_1638_pp0_it49;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p2_load_reg_1638_pp0_it51 <= ap_reg_ppstg_u_p2_load_reg_1638_pp0_it50;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p2_load_reg_1638_pp0_it52 <= ap_reg_ppstg_u_p2_load_reg_1638_pp0_it51;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p2_load_reg_1638_pp0_it53 <= ap_reg_ppstg_u_p2_load_reg_1638_pp0_it52;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p2_load_reg_1638_pp0_it54 <= ap_reg_ppstg_u_p2_load_reg_1638_pp0_it53;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p2_load_reg_1638_pp0_it55 <= ap_reg_ppstg_u_p2_load_reg_1638_pp0_it54;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p2_load_reg_1638_pp0_it56 <= ap_reg_ppstg_u_p2_load_reg_1638_pp0_it55;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p2_load_reg_1638_pp0_it57 <= ap_reg_ppstg_u_p2_load_reg_1638_pp0_it56;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p2_load_reg_1638_pp0_it58 <= ap_reg_ppstg_u_p2_load_reg_1638_pp0_it57;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p2_load_reg_1638_pp0_it59 <= ap_reg_ppstg_u_p2_load_reg_1638_pp0_it58;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p2_load_reg_1638_pp0_it6 <= ap_reg_ppstg_u_p2_load_reg_1638_pp0_it5;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p2_load_reg_1638_pp0_it60 <= ap_reg_ppstg_u_p2_load_reg_1638_pp0_it59;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p2_load_reg_1638_pp0_it61 <= ap_reg_ppstg_u_p2_load_reg_1638_pp0_it60;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p2_load_reg_1638_pp0_it62 <= ap_reg_ppstg_u_p2_load_reg_1638_pp0_it61;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p2_load_reg_1638_pp0_it63 <= ap_reg_ppstg_u_p2_load_reg_1638_pp0_it62;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p2_load_reg_1638_pp0_it64 <= ap_reg_ppstg_u_p2_load_reg_1638_pp0_it63;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p2_load_reg_1638_pp0_it65 <= ap_reg_ppstg_u_p2_load_reg_1638_pp0_it64;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p2_load_reg_1638_pp0_it66 <= ap_reg_ppstg_u_p2_load_reg_1638_pp0_it65;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p2_load_reg_1638_pp0_it67 <= ap_reg_ppstg_u_p2_load_reg_1638_pp0_it66;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p2_load_reg_1638_pp0_it68 <= ap_reg_ppstg_u_p2_load_reg_1638_pp0_it67;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p2_load_reg_1638_pp0_it69 <= ap_reg_ppstg_u_p2_load_reg_1638_pp0_it68;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p2_load_reg_1638_pp0_it7 <= ap_reg_ppstg_u_p2_load_reg_1638_pp0_it6;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p2_load_reg_1638_pp0_it70 <= ap_reg_ppstg_u_p2_load_reg_1638_pp0_it69;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p2_load_reg_1638_pp0_it8 <= ap_reg_ppstg_u_p2_load_reg_1638_pp0_it7;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p2_load_reg_1638_pp0_it9 <= ap_reg_ppstg_u_p2_load_reg_1638_pp0_it8;
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it74) & (ap_reg_ppstg_exitcond_reg_1396_pp0_it73 == ap_const_lv1_0))) begin
diff1_reg_1670 <= grp_fu_860_p2;
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it74) & (ap_reg_ppstg_exitcond_reg_1396_pp0_it73 == ap_const_lv1_0) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_reg_1405_pp0_it73))) begin
diff2_reg_1676 <= grp_fu_864_p2;
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it74) & (ap_reg_ppstg_exitcond_reg_1396_pp0_it73 == ap_const_lv1_0) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_reg_1405_pp0_it73))) begin
diff3_reg_1682 <= grp_fu_868_p2;
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it74) & (ap_reg_ppstg_exitcond_reg_1396_pp0_it73 == ap_const_lv1_0))) begin
diff_reg_1664 <= grp_fu_856_p2;
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0))) begin
exitcond_reg_1396 <= (k_phi_fu_644_p4 == exitcond_fu_876_p1? 1'b1: 1'b0);
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (exitcond_reg_1396 == ap_const_lv1_0))) begin
if (tmp_reg_1405) begin
g0_Local03_1_fu_116 <= g0_Local03_1_fu_116;
end else begin
g0_Local03_1_fu_116 <= g0_p3_q0;
end
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (exitcond_reg_1396 == ap_const_lv1_0))) begin
if (tmp_reg_1405) begin
g1_Local04_1_fu_128 <= g1_Local04_1_fu_128;
end else begin
g1_Local04_1_fu_128 <= g1_p3_q0;
end
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (exitcond_reg_1396 == ap_const_lv1_0))) begin
if (tmp_reg_1405) begin
g1_Local05_1_fu_124 <= g1_Local05_1_fu_124;
end else begin
g1_Local05_1_fu_124 <= g1_p0_q1;
end
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (exitcond_reg_1396 == ap_const_lv1_0))) begin
if (tmp_reg_1405) begin
g1_Local13_1_fu_120 <= g1_Local13_1_fu_120;
end else begin
g1_Local13_1_fu_120 <= g1_p3_q0;
end
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (exitcond_reg_1396 == ap_const_lv1_0))) begin
if (tmp_reg_1405) begin
g1_Localn13_1_fu_132 <= g1_Localn13_1_fu_132;
end else begin
g1_Localn13_1_fu_132 <= g1_p3_q0;
end
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (exitcond_reg_1396 == ap_const_lv1_0))) begin
if (tmp_reg_1405) begin
g2_Local03_1_fu_112 <= g2_Local03_1_fu_112;
end else begin
g2_Local03_1_fu_112 <= g2_p3_q0;
end
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_fu_876_p2 == ap_const_lv1_0))) begin
g2_p3_addr107_cast_reg_1422[0] <= g2_p3_addr107_cast_fu_916_p1[0];
g2_p3_addr107_cast_reg_1422[1] <= g2_p3_addr107_cast_fu_916_p1[1];
g2_p3_addr107_cast_reg_1422[2] <= g2_p3_addr107_cast_fu_916_p1[2];
g2_p3_addr107_cast_reg_1422[3] <= g2_p3_addr107_cast_fu_916_p1[3];
g2_p3_addr107_cast_reg_1422[4] <= g2_p3_addr107_cast_fu_916_p1[4];
g2_p3_addr107_cast_reg_1422[5] <= g2_p3_addr107_cast_fu_916_p1[5];
g2_p3_addr107_cast_reg_1422[6] <= g2_p3_addr107_cast_fu_916_p1[6];
g2_p3_addr107_cast_reg_1422[7] <= g2_p3_addr107_cast_fu_916_p1[7];
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (exitcond_reg_1396 == ap_const_lv1_0))) begin
i_1_reg_662 <= i_reg_1615;
end else if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
i_1_reg_662 <= ap_const_lv32_1;
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_fu_876_p2 == ap_const_lv1_0))) begin
if (tmp20_fu_1026_p2) begin
i_reg_1615 <= tmp1_fu_944_p2;
end else begin
i_reg_1615 <= i_1_phi_fu_666_p4;
end
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0))) begin
indvar_next_reg_1400 <= (k_phi_fu_644_p4 + ap_const_lv10_1);
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_fu_876_p2 == ap_const_lv1_0))) begin
if (tmp20_fu_1026_p2) begin
j_1_reg_1610 <= ap_const_lv32_1;
end else begin
j_1_reg_1610 <= tmp19_fu_1020_p2;
end
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (exitcond_reg_1396 == ap_const_lv1_0))) begin
j_reg_651 <= j_1_reg_1610;
end else if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
j_reg_651 <= ap_const_lv32_1;
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (exitcond_reg_1396 == ap_const_lv1_0))) begin
k_reg_640 <= indvar_next_reg_1400;
end else if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
k_reg_640 <= ap_const_lv10_0;
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it70) & (ap_reg_ppstg_exitcond_reg_1396_pp0_it69 == ap_const_lv1_0) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_reg_1405_pp0_it69))) begin
tmp11_reg_1654 <= grp_computeResultOne_fu_763_ap_return;
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it70) & (ap_reg_ppstg_exitcond_reg_1396_pp0_it69 == ap_const_lv1_0) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_reg_1405_pp0_it69))) begin
tmp14_reg_1659 <= grp_computeResultOne_fu_794_ap_return;
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it70) & (ap_reg_ppstg_exitcond_reg_1396_pp0_it69 == ap_const_lv1_0))) begin
tmp3_reg_1644 <= grp_computeResultOne_fu_697_ap_return;
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it70) & (ap_reg_ppstg_exitcond_reg_1396_pp0_it69 == ap_const_lv1_0))) begin
tmp6_reg_1649 <= grp_computeResultOne_fu_730_ap_return;
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_fu_876_p2 == ap_const_lv1_0))) begin
tmp_reg_1405 <= ($signed(j_phi_fu_655_p4) > $signed(tmp_fu_888_p1)? 1'b1: 1'b0);
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (exitcond_reg_1396 == ap_const_lv1_0))) begin
if (tmp_reg_1405) begin
u_Local03_1_fu_160 <= u_Local03_1_fu_160;
end else begin
u_Local03_1_fu_160 <= u_p3_q0;
end
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (exitcond_reg_1396 == ap_const_lv1_0))) begin
if (tmp_reg_1405) begin
u_Local_reg_1620 <= u_Local03_1_fu_160;
end else begin
u_Local_reg_1620 <= u_p3_q0;
end
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (exitcond_reg_1396 == ap_const_lv1_0))) begin
u_p0_load_reg_1626 <= u_p0_q0;
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (exitcond_reg_1396 == ap_const_lv1_0))) begin
u_p1_load_reg_1632 <= u_p1_q0;
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (exitcond_reg_1396 == ap_const_lv1_0))) begin
u_p2_load_reg_1638 <= u_p2_q0;
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (exitcond_reg_1396 == ap_const_lv1_0))) begin
if (tmp_reg_1405) begin
ug0_Local03_1_fu_140 <= ug0_Local03_1_fu_140;
end else begin
ug0_Local03_1_fu_140 <= ug0_p3_q0;
end
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (exitcond_reg_1396 == ap_const_lv1_0))) begin
if (tmp_reg_1405) begin
ug1_Local04_1_fu_152 <= ug1_Local04_1_fu_152;
end else begin
ug1_Local04_1_fu_152 <= ug1_p3_q0;
end
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (exitcond_reg_1396 == ap_const_lv1_0))) begin
if (tmp_reg_1405) begin
ug1_Local05_1_fu_148 <= ug1_Local05_1_fu_148;
end else begin
ug1_Local05_1_fu_148 <= ug1_p0_q1;
end
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (exitcond_reg_1396 == ap_const_lv1_0))) begin
if (tmp_reg_1405) begin
ug1_Local13_1_fu_144 <= ug1_Local13_1_fu_144;
end else begin
ug1_Local13_1_fu_144 <= ug1_p3_q0;
end
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (exitcond_reg_1396 == ap_const_lv1_0))) begin
if (tmp_reg_1405) begin
ug1_Localn13_1_fu_156 <= ug1_Localn13_1_fu_156;
end else begin
ug1_Localn13_1_fu_156 <= ug1_p3_q0;
end
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (exitcond_reg_1396 == ap_const_lv1_0))) begin
if (tmp_reg_1405) begin
ug2_Local03_1_fu_136 <= ug2_Local03_1_fu_136;
end else begin
ug2_Local03_1_fu_136 <= ug2_p3_q0;
end
end
end
/// Convergence_1_phi_fu_689_p4 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp0_it77 or ap_reg_ppstg_exitcond_reg_1396_pp0_it76 or ap_reg_ppstg_tmp_reg_1405_pp0_it76 or tmp18_fu_1311_p2 or tmp10_fu_1280_p2)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it77) & (ap_reg_ppstg_exitcond_reg_1396_pp0_it76 == ap_const_lv1_0) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_reg_1405_pp0_it76))) begin
Convergence_1_phi_fu_689_p4 = tmp10_fu_1280_p2;
end else if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it77) & (ap_reg_ppstg_exitcond_reg_1396_pp0_it76 == ap_const_lv1_0) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_reg_1405_pp0_it76))) begin
Convergence_1_phi_fu_689_p4 = tmp18_fu_1311_p2;
end else begin
Convergence_1_phi_fu_689_p4 = ap_const_lv1_0;
end
end
/// ap_NS_fsm assign process. ///
always @ (ap_start or ap_CS_fsm or exitcond_fu_876_p2 or ap_reg_ppiten_pp0_it0 or ap_reg_ppiten_pp0_it1 or ap_reg_ppiten_pp0_it76 or ap_reg_ppiten_pp0_it77)
begin
if ((((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it77) & ~(ap_const_logic_1 == ap_reg_ppiten_pp0_it76)) | ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ~(exitcond_fu_876_p2 == ap_const_lv1_0) & ~(ap_const_logic_1 == ap_reg_ppiten_pp0_it1)))) begin
ap_NS_fsm = ap_ST_st80_fsm_3;
end else if (((ap_ST_st80_fsm_3 == ap_CS_fsm) & ~(ap_const_logic_1 == ap_start))) begin
ap_NS_fsm = ap_ST_st0_fsm_0;
end else if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_pp0_stg0_fsm_2;
end else if ((((ap_ST_st0_fsm_0 == ap_CS_fsm) & (ap_const_logic_1 == ap_start)) | ((ap_ST_st80_fsm_3 == ap_CS_fsm) & (ap_const_logic_1 == ap_start)))) begin
ap_NS_fsm = ap_ST_st1_fsm_1;
end else begin
ap_NS_fsm = ap_CS_fsm;
end
end
/// ap_done assign process. ///
always @ (ap_CS_fsm)
begin
if (((ap_ST_st0_fsm_0 == ap_CS_fsm) | (ap_ST_st80_fsm_3 == ap_CS_fsm))) begin
ap_done = ap_const_logic_1;
end else begin
ap_done = ap_const_logic_0;
end
end
/// ap_idle assign process. ///
always @ (ap_CS_fsm)
begin
if ((ap_ST_st0_fsm_0 == ap_CS_fsm)) begin
ap_idle = ap_const_logic_1;
end else begin
ap_idle = ap_const_logic_0;
end
end
/// f_p0_ce0 assign process. ///
always @ (ap_CS_fsm or exitcond_fu_876_p2 or ap_reg_ppiten_pp0_it0)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_fu_876_p2 == ap_const_lv1_0))) begin
f_p0_ce0 = ap_const_logic_1;
end else begin
f_p0_ce0 = ap_const_logic_0;
end
end
/// f_p1_ce0 assign process. ///
always @ (ap_CS_fsm or exitcond_fu_876_p2 or ap_reg_ppiten_pp0_it0)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_fu_876_p2 == ap_const_lv1_0))) begin
f_p1_ce0 = ap_const_logic_1;
end else begin
f_p1_ce0 = ap_const_logic_0;
end
end
/// f_p2_ce0 assign process. ///
always @ (ap_CS_fsm or exitcond_fu_876_p2 or ap_reg_ppiten_pp0_it0 or tmp_fu_888_p2)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_fu_876_p2 == ap_const_lv1_0) & (tmp_fu_888_p2 == ap_const_lv1_0))) begin
f_p2_ce0 = ap_const_logic_1;
end else begin
f_p2_ce0 = ap_const_logic_0;
end
end
/// f_p3_ce0 assign process. ///
always @ (ap_CS_fsm or exitcond_fu_876_p2 or ap_reg_ppiten_pp0_it0 or tmp_fu_888_p2)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_fu_876_p2 == ap_const_lv1_0) & (tmp_fu_888_p2 == ap_const_lv1_0))) begin
f_p3_ce0 = ap_const_logic_1;
end else begin
f_p3_ce0 = ap_const_logic_0;
end
end
/// g0_p0_ce0 assign process. ///
always @ (ap_CS_fsm or exitcond_fu_876_p2 or ap_reg_ppiten_pp0_it0)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_fu_876_p2 == ap_const_lv1_0))) begin
g0_p0_ce0 = ap_const_logic_1;
end else begin
g0_p0_ce0 = ap_const_logic_0;
end
end
/// g0_p1_ce0 assign process. ///
always @ (ap_CS_fsm or exitcond_fu_876_p2 or ap_reg_ppiten_pp0_it0)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_fu_876_p2 == ap_const_lv1_0))) begin
g0_p1_ce0 = ap_const_logic_1;
end else begin
g0_p1_ce0 = ap_const_logic_0;
end
end
/// g0_p2_ce0 assign process. ///
always @ (ap_CS_fsm or exitcond_fu_876_p2 or ap_reg_ppiten_pp0_it0)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_fu_876_p2 == ap_const_lv1_0))) begin
g0_p2_ce0 = ap_const_logic_1;
end else begin
g0_p2_ce0 = ap_const_logic_0;
end
end
/// g0_p3_ce0 assign process. ///
always @ (ap_CS_fsm or exitcond_fu_876_p2 or ap_reg_ppiten_pp0_it0)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_fu_876_p2 == ap_const_lv1_0))) begin
g0_p3_ce0 = ap_const_logic_1;
end else begin
g0_p3_ce0 = ap_const_logic_0;
end
end
/// g1_p0_ce0 assign process. ///
always @ (ap_CS_fsm or exitcond_fu_876_p2 or ap_reg_ppiten_pp0_it0)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_fu_876_p2 == ap_const_lv1_0))) begin
g1_p0_ce0 = ap_const_logic_1;
end else begin
g1_p0_ce0 = ap_const_logic_0;
end
end
/// g1_p0_ce1 assign process. ///
always @ (ap_CS_fsm or exitcond_fu_876_p2 or ap_reg_ppiten_pp0_it0)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_fu_876_p2 == ap_const_lv1_0))) begin
g1_p0_ce1 = ap_const_logic_1;
end else begin
g1_p0_ce1 = ap_const_logic_0;
end
end
/// g1_p1_ce0 assign process. ///
always @ (ap_CS_fsm or exitcond_fu_876_p2 or ap_reg_ppiten_pp0_it0)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_fu_876_p2 == ap_const_lv1_0))) begin
g1_p1_ce0 = ap_const_logic_1;
end else begin
g1_p1_ce0 = ap_const_logic_0;
end
end
/// g1_p2_ce0 assign process. ///
always @ (ap_CS_fsm or exitcond_fu_876_p2 or ap_reg_ppiten_pp0_it0)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_fu_876_p2 == ap_const_lv1_0))) begin
g1_p2_ce0 = ap_const_logic_1;
end else begin
g1_p2_ce0 = ap_const_logic_0;
end
end
/// g1_p3_ce0 assign process. ///
always @ (ap_CS_fsm or exitcond_fu_876_p2 or ap_reg_ppiten_pp0_it0)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_fu_876_p2 == ap_const_lv1_0))) begin
g1_p3_ce0 = ap_const_logic_1;
end else begin
g1_p3_ce0 = ap_const_logic_0;
end
end
/// g1_p3_ce1 assign process. ///
always @ (ap_CS_fsm or exitcond_fu_876_p2 or ap_reg_ppiten_pp0_it0)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_fu_876_p2 == ap_const_lv1_0))) begin
g1_p3_ce1 = ap_const_logic_1;
end else begin
g1_p3_ce1 = ap_const_logic_0;
end
end
/// g2_p0_ce0 assign process. ///
always @ (ap_CS_fsm or exitcond_fu_876_p2 or ap_reg_ppiten_pp0_it0)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_fu_876_p2 == ap_const_lv1_0))) begin
g2_p0_ce0 = ap_const_logic_1;
end else begin
g2_p0_ce0 = ap_const_logic_0;
end
end
/// g2_p1_ce0 assign process. ///
always @ (ap_CS_fsm or exitcond_fu_876_p2 or ap_reg_ppiten_pp0_it0)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_fu_876_p2 == ap_const_lv1_0))) begin
g2_p1_ce0 = ap_const_logic_1;
end else begin
g2_p1_ce0 = ap_const_logic_0;
end
end
/// g2_p2_ce0 assign process. ///
always @ (ap_CS_fsm or exitcond_fu_876_p2 or ap_reg_ppiten_pp0_it0)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_fu_876_p2 == ap_const_lv1_0))) begin
g2_p2_ce0 = ap_const_logic_1;
end else begin
g2_p2_ce0 = ap_const_logic_0;
end
end
/// g2_p3_ce0 assign process. ///
always @ (ap_CS_fsm or exitcond_fu_876_p2 or ap_reg_ppiten_pp0_it0)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_fu_876_p2 == ap_const_lv1_0))) begin
g2_p3_ce0 = ap_const_logic_1;
end else begin
g2_p3_ce0 = ap_const_logic_0;
end
end
/// grp_computeResultOne_fu_697_ap_ce assign process. ///
always @ (ap_CS_fsm or exitcond_reg_1396 or ap_reg_ppstg_exitcond_reg_1396_pp0_it1 or ap_reg_ppstg_exitcond_reg_1396_pp0_it2 or ap_reg_ppstg_exitcond_reg_1396_pp0_it3 or ap_reg_ppstg_exitcond_reg_1396_pp0_it4 or ap_reg_ppstg_exitcond_reg_1396_pp0_it5 or ap_reg_ppstg_exitcond_reg_1396_pp0_it6 or ap_reg_ppstg_exitcond_reg_1396_pp0_it7 or ap_reg_ppstg_exitcond_reg_1396_pp0_it8 or ap_reg_ppstg_exitcond_reg_1396_pp0_it9 or ap_reg_ppstg_exitcond_reg_1396_pp0_it10 or ap_reg_ppstg_exitcond_reg_1396_pp0_it11 or ap_reg_ppstg_exitcond_reg_1396_pp0_it12 or ap_reg_ppstg_exitcond_reg_1396_pp0_it13 or ap_reg_ppstg_exitcond_reg_1396_pp0_it14 or ap_reg_ppstg_exitcond_reg_1396_pp0_it15 or ap_reg_ppstg_exitcond_reg_1396_pp0_it16 or ap_reg_ppstg_exitcond_reg_1396_pp0_it17 or ap_reg_ppstg_exitcond_reg_1396_pp0_it18 or ap_reg_ppstg_exitcond_reg_1396_pp0_it19 or ap_reg_ppstg_exitcond_reg_1396_pp0_it20 or ap_reg_ppstg_exitcond_reg_1396_pp0_it21 or ap_reg_ppstg_exitcond_reg_1396_pp0_it22 or ap_reg_ppstg_exitcond_reg_1396_pp0_it23 or ap_reg_ppstg_exitcond_reg_1396_pp0_it24 or ap_reg_ppstg_exitcond_reg_1396_pp0_it25 or ap_reg_ppstg_exitcond_reg_1396_pp0_it26 or ap_reg_ppstg_exitcond_reg_1396_pp0_it27 or ap_reg_ppstg_exitcond_reg_1396_pp0_it28 or ap_reg_ppstg_exitcond_reg_1396_pp0_it29 or ap_reg_ppstg_exitcond_reg_1396_pp0_it30 or ap_reg_ppstg_exitcond_reg_1396_pp0_it31 or ap_reg_ppstg_exitcond_reg_1396_pp0_it32 or ap_reg_ppstg_exitcond_reg_1396_pp0_it33 or ap_reg_ppstg_exitcond_reg_1396_pp0_it34 or ap_reg_ppstg_exitcond_reg_1396_pp0_it35 or ap_reg_ppstg_exitcond_reg_1396_pp0_it36 or ap_reg_ppstg_exitcond_reg_1396_pp0_it37 or ap_reg_ppstg_exitcond_reg_1396_pp0_it38 or ap_reg_ppstg_exitcond_reg_1396_pp0_it39 or ap_reg_ppstg_exitcond_reg_1396_pp0_it40 or ap_reg_ppstg_exitcond_reg_1396_pp0_it41 or ap_reg_ppstg_exitcond_reg_1396_pp0_it42 or ap_reg_ppstg_exitcond_reg_1396_pp0_it43 or ap_reg_ppstg_exitcond_reg_1396_pp0_it44 or ap_reg_ppstg_exitcond_reg_1396_pp0_it45 or ap_reg_ppstg_exitcond_reg_1396_pp0_it46 or ap_reg_ppstg_exitcond_reg_1396_pp0_it47 or ap_reg_ppstg_exitcond_reg_1396_pp0_it48 or ap_reg_ppstg_exitcond_reg_1396_pp0_it49 or ap_reg_ppstg_exitcond_reg_1396_pp0_it50 or ap_reg_ppstg_exitcond_reg_1396_pp0_it51 or ap_reg_ppstg_exitcond_reg_1396_pp0_it52 or ap_reg_ppstg_exitcond_reg_1396_pp0_it53 or ap_reg_ppstg_exitcond_reg_1396_pp0_it54 or ap_reg_ppstg_exitcond_reg_1396_pp0_it55 or ap_reg_ppstg_exitcond_reg_1396_pp0_it56 or ap_reg_ppstg_exitcond_reg_1396_pp0_it57 or ap_reg_ppstg_exitcond_reg_1396_pp0_it58 or ap_reg_ppstg_exitcond_reg_1396_pp0_it59 or ap_reg_ppstg_exitcond_reg_1396_pp0_it60 or ap_reg_ppstg_exitcond_reg_1396_pp0_it61 or ap_reg_ppstg_exitcond_reg_1396_pp0_it62 or ap_reg_ppstg_exitcond_reg_1396_pp0_it63 or ap_reg_ppstg_exitcond_reg_1396_pp0_it64 or ap_reg_ppstg_exitcond_reg_1396_pp0_it65 or ap_reg_ppstg_exitcond_reg_1396_pp0_it66 or ap_reg_ppstg_exitcond_reg_1396_pp0_it67 or ap_reg_ppstg_exitcond_reg_1396_pp0_it68 or ap_reg_ppstg_exitcond_reg_1396_pp0_it69)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & ((exitcond_reg_1396 == ap_const_lv1_0) | (ap_reg_ppstg_exitcond_reg_1396_pp0_it69 == ap_const_lv1_0) | (ap_reg_ppstg_exitcond_reg_1396_pp0_it1 == ap_const_lv1_0) | (ap_reg_ppstg_exitcond_reg_1396_pp0_it2 == ap_const_lv1_0) | (ap_reg_ppstg_exitcond_reg_1396_pp0_it3 == ap_const_lv1_0) | (ap_reg_ppstg_exitcond_reg_1396_pp0_it4 == ap_const_lv1_0) | (ap_reg_ppstg_exitcond_reg_1396_pp0_it5 == ap_const_lv1_0) | (ap_reg_ppstg_exitcond_reg_1396_pp0_it6 == ap_const_lv1_0) | (ap_reg_ppstg_exitcond_reg_1396_pp0_it7 == ap_const_lv1_0) | (ap_reg_ppstg_exitcond_reg_1396_pp0_it8 == ap_const_lv1_0) | (ap_reg_ppstg_exitcond_reg_1396_pp0_it9 == ap_const_lv1_0) | (ap_reg_ppstg_exitcond_reg_1396_pp0_it10 == ap_const_lv1_0) | (ap_reg_ppstg_exitcond_reg_1396_pp0_it11 == ap_const_lv1_0) | (ap_reg_ppstg_exitcond_reg_1396_pp0_it12 == ap_const_lv1_0) | (ap_reg_ppstg_exitcond_reg_1396_pp0_it13 == ap_const_lv1_0) | (ap_reg_ppstg_exitcond_reg_1396_pp0_it14 == ap_const_lv1_0) | (ap_reg_ppstg_exitcond_reg_1396_pp0_it15 == ap_const_lv1_0) | (ap_reg_ppstg_exitcond_reg_1396_pp0_it16 == ap_const_lv1_0) | (ap_reg_ppstg_exitcond_reg_1396_pp0_it17 == ap_const_lv1_0) | (ap_reg_ppstg_exitcond_reg_1396_pp0_it18 == ap_const_lv1_0) | (ap_reg_ppstg_exitcond_reg_1396_pp0_it19 == ap_const_lv1_0) | (ap_reg_ppstg_exitcond_reg_1396_pp0_it20 == ap_const_lv1_0) | (ap_reg_ppstg_exitcond_reg_1396_pp0_it21 == ap_const_lv1_0) | (ap_reg_ppstg_exitcond_reg_1396_pp0_it22 == ap_const_lv1_0) | (ap_reg_ppstg_exitcond_reg_1396_pp0_it23 == ap_const_lv1_0) | (ap_reg_ppstg_exitcond_reg_1396_pp0_it24 == ap_const_lv1_0) | (ap_reg_ppstg_exitcond_reg_1396_pp0_it25 == ap_const_lv1_0) | (ap_reg_ppstg_exitcond_reg_1396_pp0_it26 == ap_const_lv1_0) | (ap_reg_ppstg_exitcond_reg_1396_pp0_it27 == ap_const_lv1_0) | (ap_reg_ppstg_exitcond_reg_1396_pp0_it28 == ap_const_lv1_0) | (ap_reg_ppstg_exitcond_reg_1396_pp0_it29 == ap_const_lv1_0) | (ap_reg_ppstg_exitcond_reg_1396_pp0_it30 == ap_const_lv1_0) | (ap_reg_ppstg_exitcond_reg_1396_pp0_it31 == ap_const_lv1_0) | (ap_reg_ppstg_exitcond_reg_1396_pp0_it32 == ap_const_lv1_0) | (ap_reg_ppstg_exitcond_reg_1396_pp0_it33 == ap_const_lv1_0) | (ap_reg_ppstg_exitcond_reg_1396_pp0_it34 == ap_const_lv1_0) | (ap_reg_ppstg_exitcond_reg_1396_pp0_it35 == ap_const_lv1_0) | (ap_reg_ppstg_exitcond_reg_1396_pp0_it36 == ap_const_lv1_0) | (ap_reg_ppstg_exitcond_reg_1396_pp0_it37 == ap_const_lv1_0) | (ap_reg_ppstg_exitcond_reg_1396_pp0_it38 == ap_const_lv1_0) | (ap_reg_ppstg_exitcond_reg_1396_pp0_it39 == ap_const_lv1_0) | (ap_reg_ppstg_exitcond_reg_1396_pp0_it40 == ap_const_lv1_0) | (ap_reg_ppstg_exitcond_reg_1396_pp0_it41 == ap_const_lv1_0) | (ap_reg_ppstg_exitcond_reg_1396_pp0_it42 == ap_const_lv1_0) | (ap_reg_ppstg_exitcond_reg_1396_pp0_it43 == ap_const_lv1_0) | (ap_reg_ppstg_exitcond_reg_1396_pp0_it44 == ap_const_lv1_0) | (ap_reg_ppstg_exitcond_reg_1396_pp0_it45 == ap_const_lv1_0) | (ap_reg_ppstg_exitcond_reg_1396_pp0_it46 == ap_const_lv1_0) | (ap_reg_ppstg_exitcond_reg_1396_pp0_it47 == ap_const_lv1_0) | (ap_reg_ppstg_exitcond_reg_1396_pp0_it48 == ap_const_lv1_0) | (ap_reg_ppstg_exitcond_reg_1396_pp0_it49 == ap_const_lv1_0) | (ap_reg_ppstg_exitcond_reg_1396_pp0_it50 == ap_const_lv1_0) | (ap_reg_ppstg_exitcond_reg_1396_pp0_it51 == ap_const_lv1_0) | (ap_reg_ppstg_exitcond_reg_1396_pp0_it52 == ap_const_lv1_0) | (ap_reg_ppstg_exitcond_reg_1396_pp0_it53 == ap_const_lv1_0) | (ap_reg_ppstg_exitcond_reg_1396_pp0_it54 == ap_const_lv1_0) | (ap_reg_ppstg_exitcond_reg_1396_pp0_it55 == ap_const_lv1_0) | (ap_reg_ppstg_exitcond_reg_1396_pp0_it56 == ap_const_lv1_0) | (ap_reg_ppstg_exitcond_reg_1396_pp0_it57 == ap_const_lv1_0) | (ap_reg_ppstg_exitcond_reg_1396_pp0_it58 == ap_const_lv1_0) | (ap_reg_ppstg_exitcond_reg_1396_pp0_it59 == ap_const_lv1_0) | (ap_reg_ppstg_exitcond_reg_1396_pp0_it60 == ap_const_lv1_0) | (ap_reg_ppstg_exitcond_reg_1396_pp0_it61 == ap_const_lv1_0) | (ap_reg_ppstg_exitcond_reg_1396_pp0_it62 == ap_const_lv1_0) | (ap_reg_ppstg_exitcond_reg_1396_pp0_it63 == ap_const_lv1_0) | (ap_reg_ppstg_exitcond_reg_1396_pp0_it64 == ap_const_lv1_0) | (ap_reg_ppstg_exitcond_reg_1396_pp0_it65 == ap_const_lv1_0) | (ap_reg_ppstg_exitcond_reg_1396_pp0_it66 == ap_const_lv1_0) | (ap_reg_ppstg_exitcond_reg_1396_pp0_it67 == ap_const_lv1_0) | (ap_reg_ppstg_exitcond_reg_1396_pp0_it68 == ap_const_lv1_0)))) begin
grp_computeResultOne_fu_697_ap_ce = ap_const_logic_1;
end else begin
grp_computeResultOne_fu_697_ap_ce = ap_const_logic_0;
end
end
/// grp_computeResultOne_fu_730_ap_ce assign process. ///
always @ (ap_CS_fsm or exitcond_reg_1396 or ap_reg_ppstg_exitcond_reg_1396_pp0_it1 or ap_reg_ppstg_exitcond_reg_1396_pp0_it2 or ap_reg_ppstg_exitcond_reg_1396_pp0_it3 or ap_reg_ppstg_exitcond_reg_1396_pp0_it4 or ap_reg_ppstg_exitcond_reg_1396_pp0_it5 or ap_reg_ppstg_exitcond_reg_1396_pp0_it6 or ap_reg_ppstg_exitcond_reg_1396_pp0_it7 or ap_reg_ppstg_exitcond_reg_1396_pp0_it8 or ap_reg_ppstg_exitcond_reg_1396_pp0_it9 or ap_reg_ppstg_exitcond_reg_1396_pp0_it10 or ap_reg_ppstg_exitcond_reg_1396_pp0_it11 or ap_reg_ppstg_exitcond_reg_1396_pp0_it12 or ap_reg_ppstg_exitcond_reg_1396_pp0_it13 or ap_reg_ppstg_exitcond_reg_1396_pp0_it14 or ap_reg_ppstg_exitcond_reg_1396_pp0_it15 or ap_reg_ppstg_exitcond_reg_1396_pp0_it16 or ap_reg_ppstg_exitcond_reg_1396_pp0_it17 or ap_reg_ppstg_exitcond_reg_1396_pp0_it18 or ap_reg_ppstg_exitcond_reg_1396_pp0_it19 or ap_reg_ppstg_exitcond_reg_1396_pp0_it20 or ap_reg_ppstg_exitcond_reg_1396_pp0_it21 or ap_reg_ppstg_exitcond_reg_1396_pp0_it22 or ap_reg_ppstg_exitcond_reg_1396_pp0_it23 or ap_reg_ppstg_exitcond_reg_1396_pp0_it24 or ap_reg_ppstg_exitcond_reg_1396_pp0_it25 or ap_reg_ppstg_exitcond_reg_1396_pp0_it26 or ap_reg_ppstg_exitcond_reg_1396_pp0_it27 or ap_reg_ppstg_exitcond_reg_1396_pp0_it28 or ap_reg_ppstg_exitcond_reg_1396_pp0_it29 or ap_reg_ppstg_exitcond_reg_1396_pp0_it30 or ap_reg_ppstg_exitcond_reg_1396_pp0_it31 or ap_reg_ppstg_exitcond_reg_1396_pp0_it32 or ap_reg_ppstg_exitcond_reg_1396_pp0_it33 or ap_reg_ppstg_exitcond_reg_1396_pp0_it34 or ap_reg_ppstg_exitcond_reg_1396_pp0_it35 or ap_reg_ppstg_exitcond_reg_1396_pp0_it36 or ap_reg_ppstg_exitcond_reg_1396_pp0_it37 or ap_reg_ppstg_exitcond_reg_1396_pp0_it38 or ap_reg_ppstg_exitcond_reg_1396_pp0_it39 or ap_reg_ppstg_exitcond_reg_1396_pp0_it40 or ap_reg_ppstg_exitcond_reg_1396_pp0_it41 or ap_reg_ppstg_exitcond_reg_1396_pp0_it42 or ap_reg_ppstg_exitcond_reg_1396_pp0_it43 or ap_reg_ppstg_exitcond_reg_1396_pp0_it44 or ap_reg_ppstg_exitcond_reg_1396_pp0_it45 or ap_reg_ppstg_exitcond_reg_1396_pp0_it46 or ap_reg_ppstg_exitcond_reg_1396_pp0_it47 or ap_reg_ppstg_exitcond_reg_1396_pp0_it48 or ap_reg_ppstg_exitcond_reg_1396_pp0_it49 or ap_reg_ppstg_exitcond_reg_1396_pp0_it50 or ap_reg_ppstg_exitcond_reg_1396_pp0_it51 or ap_reg_ppstg_exitcond_reg_1396_pp0_it52 or ap_reg_ppstg_exitcond_reg_1396_pp0_it53 or ap_reg_ppstg_exitcond_reg_1396_pp0_it54 or ap_reg_ppstg_exitcond_reg_1396_pp0_it55 or ap_reg_ppstg_exitcond_reg_1396_pp0_it56 or ap_reg_ppstg_exitcond_reg_1396_pp0_it57 or ap_reg_ppstg_exitcond_reg_1396_pp0_it58 or ap_reg_ppstg_exitcond_reg_1396_pp0_it59 or ap_reg_ppstg_exitcond_reg_1396_pp0_it60 or ap_reg_ppstg_exitcond_reg_1396_pp0_it61 or ap_reg_ppstg_exitcond_reg_1396_pp0_it62 or ap_reg_ppstg_exitcond_reg_1396_pp0_it63 or ap_reg_ppstg_exitcond_reg_1396_pp0_it64 or ap_reg_ppstg_exitcond_reg_1396_pp0_it65 or ap_reg_ppstg_exitcond_reg_1396_pp0_it66 or ap_reg_ppstg_exitcond_reg_1396_pp0_it67 or ap_reg_ppstg_exitcond_reg_1396_pp0_it68 or ap_reg_ppstg_exitcond_reg_1396_pp0_it69)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & ((exitcond_reg_1396 == ap_const_lv1_0) | (ap_reg_ppstg_exitcond_reg_1396_pp0_it69 == ap_const_lv1_0) | (ap_reg_ppstg_exitcond_reg_1396_pp0_it1 == ap_const_lv1_0) | (ap_reg_ppstg_exitcond_reg_1396_pp0_it2 == ap_const_lv1_0) | (ap_reg_ppstg_exitcond_reg_1396_pp0_it3 == ap_const_lv1_0) | (ap_reg_ppstg_exitcond_reg_1396_pp0_it4 == ap_const_lv1_0) | (ap_reg_ppstg_exitcond_reg_1396_pp0_it5 == ap_const_lv1_0) | (ap_reg_ppstg_exitcond_reg_1396_pp0_it6 == ap_const_lv1_0) | (ap_reg_ppstg_exitcond_reg_1396_pp0_it7 == ap_const_lv1_0) | (ap_reg_ppstg_exitcond_reg_1396_pp0_it8 == ap_const_lv1_0) | (ap_reg_ppstg_exitcond_reg_1396_pp0_it9 == ap_const_lv1_0) | (ap_reg_ppstg_exitcond_reg_1396_pp0_it10 == ap_const_lv1_0) | (ap_reg_ppstg_exitcond_reg_1396_pp0_it11 == ap_const_lv1_0) | (ap_reg_ppstg_exitcond_reg_1396_pp0_it12 == ap_const_lv1_0) | (ap_reg_ppstg_exitcond_reg_1396_pp0_it13 == ap_const_lv1_0) | (ap_reg_ppstg_exitcond_reg_1396_pp0_it14 == ap_const_lv1_0) | (ap_reg_ppstg_exitcond_reg_1396_pp0_it15 == ap_const_lv1_0) | (ap_reg_ppstg_exitcond_reg_1396_pp0_it16 == ap_const_lv1_0) | (ap_reg_ppstg_exitcond_reg_1396_pp0_it17 == ap_const_lv1_0) | (ap_reg_ppstg_exitcond_reg_1396_pp0_it18 == ap_const_lv1_0) | (ap_reg_ppstg_exitcond_reg_1396_pp0_it19 == ap_const_lv1_0) | (ap_reg_ppstg_exitcond_reg_1396_pp0_it20 == ap_const_lv1_0) | (ap_reg_ppstg_exitcond_reg_1396_pp0_it21 == ap_const_lv1_0) | (ap_reg_ppstg_exitcond_reg_1396_pp0_it22 == ap_const_lv1_0) | (ap_reg_ppstg_exitcond_reg_1396_pp0_it23 == ap_const_lv1_0) | (ap_reg_ppstg_exitcond_reg_1396_pp0_it24 == ap_const_lv1_0) | (ap_reg_ppstg_exitcond_reg_1396_pp0_it25 == ap_const_lv1_0) | (ap_reg_ppstg_exitcond_reg_1396_pp0_it26 == ap_const_lv1_0) | (ap_reg_ppstg_exitcond_reg_1396_pp0_it27 == ap_const_lv1_0) | (ap_reg_ppstg_exitcond_reg_1396_pp0_it28 == ap_const_lv1_0) | (ap_reg_ppstg_exitcond_reg_1396_pp0_it29 == ap_const_lv1_0) | (ap_reg_ppstg_exitcond_reg_1396_pp0_it30 == ap_const_lv1_0) | (ap_reg_ppstg_exitcond_reg_1396_pp0_it31 == ap_const_lv1_0) | (ap_reg_ppstg_exitcond_reg_1396_pp0_it32 == ap_const_lv1_0) | (ap_reg_ppstg_exitcond_reg_1396_pp0_it33 == ap_const_lv1_0) | (ap_reg_ppstg_exitcond_reg_1396_pp0_it34 == ap_const_lv1_0) | (ap_reg_ppstg_exitcond_reg_1396_pp0_it35 == ap_const_lv1_0) | (ap_reg_ppstg_exitcond_reg_1396_pp0_it36 == ap_const_lv1_0) | (ap_reg_ppstg_exitcond_reg_1396_pp0_it37 == ap_const_lv1_0) | (ap_reg_ppstg_exitcond_reg_1396_pp0_it38 == ap_const_lv1_0) | (ap_reg_ppstg_exitcond_reg_1396_pp0_it39 == ap_const_lv1_0) | (ap_reg_ppstg_exitcond_reg_1396_pp0_it40 == ap_const_lv1_0) | (ap_reg_ppstg_exitcond_reg_1396_pp0_it41 == ap_const_lv1_0) | (ap_reg_ppstg_exitcond_reg_1396_pp0_it42 == ap_const_lv1_0) | (ap_reg_ppstg_exitcond_reg_1396_pp0_it43 == ap_const_lv1_0) | (ap_reg_ppstg_exitcond_reg_1396_pp0_it44 == ap_const_lv1_0) | (ap_reg_ppstg_exitcond_reg_1396_pp0_it45 == ap_const_lv1_0) | (ap_reg_ppstg_exitcond_reg_1396_pp0_it46 == ap_const_lv1_0) | (ap_reg_ppstg_exitcond_reg_1396_pp0_it47 == ap_const_lv1_0) | (ap_reg_ppstg_exitcond_reg_1396_pp0_it48 == ap_const_lv1_0) | (ap_reg_ppstg_exitcond_reg_1396_pp0_it49 == ap_const_lv1_0) | (ap_reg_ppstg_exitcond_reg_1396_pp0_it50 == ap_const_lv1_0) | (ap_reg_ppstg_exitcond_reg_1396_pp0_it51 == ap_const_lv1_0) | (ap_reg_ppstg_exitcond_reg_1396_pp0_it52 == ap_const_lv1_0) | (ap_reg_ppstg_exitcond_reg_1396_pp0_it53 == ap_const_lv1_0) | (ap_reg_ppstg_exitcond_reg_1396_pp0_it54 == ap_const_lv1_0) | (ap_reg_ppstg_exitcond_reg_1396_pp0_it55 == ap_const_lv1_0) | (ap_reg_ppstg_exitcond_reg_1396_pp0_it56 == ap_const_lv1_0) | (ap_reg_ppstg_exitcond_reg_1396_pp0_it57 == ap_const_lv1_0) | (ap_reg_ppstg_exitcond_reg_1396_pp0_it58 == ap_const_lv1_0) | (ap_reg_ppstg_exitcond_reg_1396_pp0_it59 == ap_const_lv1_0) | (ap_reg_ppstg_exitcond_reg_1396_pp0_it60 == ap_const_lv1_0) | (ap_reg_ppstg_exitcond_reg_1396_pp0_it61 == ap_const_lv1_0) | (ap_reg_ppstg_exitcond_reg_1396_pp0_it62 == ap_const_lv1_0) | (ap_reg_ppstg_exitcond_reg_1396_pp0_it63 == ap_const_lv1_0) | (ap_reg_ppstg_exitcond_reg_1396_pp0_it64 == ap_const_lv1_0) | (ap_reg_ppstg_exitcond_reg_1396_pp0_it65 == ap_const_lv1_0) | (ap_reg_ppstg_exitcond_reg_1396_pp0_it66 == ap_const_lv1_0) | (ap_reg_ppstg_exitcond_reg_1396_pp0_it67 == ap_const_lv1_0) | (ap_reg_ppstg_exitcond_reg_1396_pp0_it68 == ap_const_lv1_0)))) begin
grp_computeResultOne_fu_730_ap_ce = ap_const_logic_1;
end else begin
grp_computeResultOne_fu_730_ap_ce = ap_const_logic_0;
end
end
/// grp_computeResultOne_fu_763_ap_ce assign process. ///
always @ (ap_CS_fsm or exitcond_reg_1396 or ap_reg_ppstg_exitcond_reg_1396_pp0_it1 or ap_reg_ppstg_exitcond_reg_1396_pp0_it2 or ap_reg_ppstg_exitcond_reg_1396_pp0_it3 or ap_reg_ppstg_exitcond_reg_1396_pp0_it4 or ap_reg_ppstg_exitcond_reg_1396_pp0_it5 or ap_reg_ppstg_exitcond_reg_1396_pp0_it6 or ap_reg_ppstg_exitcond_reg_1396_pp0_it7 or ap_reg_ppstg_exitcond_reg_1396_pp0_it8 or ap_reg_ppstg_exitcond_reg_1396_pp0_it9 or ap_reg_ppstg_exitcond_reg_1396_pp0_it10 or ap_reg_ppstg_exitcond_reg_1396_pp0_it11 or ap_reg_ppstg_exitcond_reg_1396_pp0_it12 or ap_reg_ppstg_exitcond_reg_1396_pp0_it13 or ap_reg_ppstg_exitcond_reg_1396_pp0_it14 or ap_reg_ppstg_exitcond_reg_1396_pp0_it15 or ap_reg_ppstg_exitcond_reg_1396_pp0_it16 or ap_reg_ppstg_exitcond_reg_1396_pp0_it17 or ap_reg_ppstg_exitcond_reg_1396_pp0_it18 or ap_reg_ppstg_exitcond_reg_1396_pp0_it19 or ap_reg_ppstg_exitcond_reg_1396_pp0_it20 or ap_reg_ppstg_exitcond_reg_1396_pp0_it21 or ap_reg_ppstg_exitcond_reg_1396_pp0_it22 or ap_reg_ppstg_exitcond_reg_1396_pp0_it23 or ap_reg_ppstg_exitcond_reg_1396_pp0_it24 or ap_reg_ppstg_exitcond_reg_1396_pp0_it25 or ap_reg_ppstg_exitcond_reg_1396_pp0_it26 or ap_reg_ppstg_exitcond_reg_1396_pp0_it27 or ap_reg_ppstg_exitcond_reg_1396_pp0_it28 or ap_reg_ppstg_exitcond_reg_1396_pp0_it29 or ap_reg_ppstg_exitcond_reg_1396_pp0_it30 or ap_reg_ppstg_exitcond_reg_1396_pp0_it31 or ap_reg_ppstg_exitcond_reg_1396_pp0_it32 or ap_reg_ppstg_exitcond_reg_1396_pp0_it33 or ap_reg_ppstg_exitcond_reg_1396_pp0_it34 or ap_reg_ppstg_exitcond_reg_1396_pp0_it35 or ap_reg_ppstg_exitcond_reg_1396_pp0_it36 or ap_reg_ppstg_exitcond_reg_1396_pp0_it37 or ap_reg_ppstg_exitcond_reg_1396_pp0_it38 or ap_reg_ppstg_exitcond_reg_1396_pp0_it39 or ap_reg_ppstg_exitcond_reg_1396_pp0_it40 or ap_reg_ppstg_exitcond_reg_1396_pp0_it41 or ap_reg_ppstg_exitcond_reg_1396_pp0_it42 or ap_reg_ppstg_exitcond_reg_1396_pp0_it43 or ap_reg_ppstg_exitcond_reg_1396_pp0_it44 or ap_reg_ppstg_exitcond_reg_1396_pp0_it45 or ap_reg_ppstg_exitcond_reg_1396_pp0_it46 or ap_reg_ppstg_exitcond_reg_1396_pp0_it47 or ap_reg_ppstg_exitcond_reg_1396_pp0_it48 or ap_reg_ppstg_exitcond_reg_1396_pp0_it49 or ap_reg_ppstg_exitcond_reg_1396_pp0_it50 or ap_reg_ppstg_exitcond_reg_1396_pp0_it51 or ap_reg_ppstg_exitcond_reg_1396_pp0_it52 or ap_reg_ppstg_exitcond_reg_1396_pp0_it53 or ap_reg_ppstg_exitcond_reg_1396_pp0_it54 or ap_reg_ppstg_exitcond_reg_1396_pp0_it55 or ap_reg_ppstg_exitcond_reg_1396_pp0_it56 or ap_reg_ppstg_exitcond_reg_1396_pp0_it57 or ap_reg_ppstg_exitcond_reg_1396_pp0_it58 or ap_reg_ppstg_exitcond_reg_1396_pp0_it59 or ap_reg_ppstg_exitcond_reg_1396_pp0_it60 or ap_reg_ppstg_exitcond_reg_1396_pp0_it61 or ap_reg_ppstg_exitcond_reg_1396_pp0_it62 or ap_reg_ppstg_exitcond_reg_1396_pp0_it63 or ap_reg_ppstg_exitcond_reg_1396_pp0_it64 or ap_reg_ppstg_exitcond_reg_1396_pp0_it65 or ap_reg_ppstg_exitcond_reg_1396_pp0_it66 or ap_reg_ppstg_exitcond_reg_1396_pp0_it67 or ap_reg_ppstg_exitcond_reg_1396_pp0_it68 or ap_reg_ppstg_exitcond_reg_1396_pp0_it69 or tmp_reg_1405 or ap_reg_ppstg_tmp_reg_1405_pp0_it1 or ap_reg_ppstg_tmp_reg_1405_pp0_it2 or ap_reg_ppstg_tmp_reg_1405_pp0_it3 or ap_reg_ppstg_tmp_reg_1405_pp0_it4 or ap_reg_ppstg_tmp_reg_1405_pp0_it5 or ap_reg_ppstg_tmp_reg_1405_pp0_it6 or ap_reg_ppstg_tmp_reg_1405_pp0_it7 or ap_reg_ppstg_tmp_reg_1405_pp0_it8 or ap_reg_ppstg_tmp_reg_1405_pp0_it9 or ap_reg_ppstg_tmp_reg_1405_pp0_it10 or ap_reg_ppstg_tmp_reg_1405_pp0_it11 or ap_reg_ppstg_tmp_reg_1405_pp0_it12 or ap_reg_ppstg_tmp_reg_1405_pp0_it13 or ap_reg_ppstg_tmp_reg_1405_pp0_it14 or ap_reg_ppstg_tmp_reg_1405_pp0_it15 or ap_reg_ppstg_tmp_reg_1405_pp0_it16 or ap_reg_ppstg_tmp_reg_1405_pp0_it17 or ap_reg_ppstg_tmp_reg_1405_pp0_it18 or ap_reg_ppstg_tmp_reg_1405_pp0_it19 or ap_reg_ppstg_tmp_reg_1405_pp0_it20 or ap_reg_ppstg_tmp_reg_1405_pp0_it21 or ap_reg_ppstg_tmp_reg_1405_pp0_it22 or ap_reg_ppstg_tmp_reg_1405_pp0_it23 or ap_reg_ppstg_tmp_reg_1405_pp0_it24 or ap_reg_ppstg_tmp_reg_1405_pp0_it25 or ap_reg_ppstg_tmp_reg_1405_pp0_it26 or ap_reg_ppstg_tmp_reg_1405_pp0_it27 or ap_reg_ppstg_tmp_reg_1405_pp0_it28 or ap_reg_ppstg_tmp_reg_1405_pp0_it29 or ap_reg_ppstg_tmp_reg_1405_pp0_it30 or ap_reg_ppstg_tmp_reg_1405_pp0_it31 or ap_reg_ppstg_tmp_reg_1405_pp0_it32 or ap_reg_ppstg_tmp_reg_1405_pp0_it33 or ap_reg_ppstg_tmp_reg_1405_pp0_it34 or ap_reg_ppstg_tmp_reg_1405_pp0_it35 or ap_reg_ppstg_tmp_reg_1405_pp0_it36 or ap_reg_ppstg_tmp_reg_1405_pp0_it37 or ap_reg_ppstg_tmp_reg_1405_pp0_it38 or ap_reg_ppstg_tmp_reg_1405_pp0_it39 or ap_reg_ppstg_tmp_reg_1405_pp0_it40 or ap_reg_ppstg_tmp_reg_1405_pp0_it41 or ap_reg_ppstg_tmp_reg_1405_pp0_it42 or ap_reg_ppstg_tmp_reg_1405_pp0_it43 or ap_reg_ppstg_tmp_reg_1405_pp0_it44 or ap_reg_ppstg_tmp_reg_1405_pp0_it45 or ap_reg_ppstg_tmp_reg_1405_pp0_it46 or ap_reg_ppstg_tmp_reg_1405_pp0_it47 or ap_reg_ppstg_tmp_reg_1405_pp0_it48 or ap_reg_ppstg_tmp_reg_1405_pp0_it49 or ap_reg_ppstg_tmp_reg_1405_pp0_it50 or ap_reg_ppstg_tmp_reg_1405_pp0_it51 or ap_reg_ppstg_tmp_reg_1405_pp0_it52 or ap_reg_ppstg_tmp_reg_1405_pp0_it53 or ap_reg_ppstg_tmp_reg_1405_pp0_it54 or ap_reg_ppstg_tmp_reg_1405_pp0_it55 or ap_reg_ppstg_tmp_reg_1405_pp0_it56 or ap_reg_ppstg_tmp_reg_1405_pp0_it57 or ap_reg_ppstg_tmp_reg_1405_pp0_it58 or ap_reg_ppstg_tmp_reg_1405_pp0_it59 or ap_reg_ppstg_tmp_reg_1405_pp0_it60 or ap_reg_ppstg_tmp_reg_1405_pp0_it61 or ap_reg_ppstg_tmp_reg_1405_pp0_it62 or ap_reg_ppstg_tmp_reg_1405_pp0_it63 or ap_reg_ppstg_tmp_reg_1405_pp0_it64 or ap_reg_ppstg_tmp_reg_1405_pp0_it65 or ap_reg_ppstg_tmp_reg_1405_pp0_it66 or ap_reg_ppstg_tmp_reg_1405_pp0_it67 or ap_reg_ppstg_tmp_reg_1405_pp0_it68 or ap_reg_ppstg_tmp_reg_1405_pp0_it69)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (((ap_reg_ppstg_exitcond_reg_1396_pp0_it69 == ap_const_lv1_0) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_reg_1405_pp0_it69)) | ((exitcond_reg_1396 == ap_const_lv1_0) & (tmp_reg_1405 == ap_const_lv1_0)) | ((ap_reg_ppstg_exitcond_reg_1396_pp0_it1 == ap_const_lv1_0) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_reg_1405_pp0_it1)) | ((ap_reg_ppstg_exitcond_reg_1396_pp0_it2 == ap_const_lv1_0) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_reg_1405_pp0_it2)) | ((ap_reg_ppstg_exitcond_reg_1396_pp0_it3 == ap_const_lv1_0) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_reg_1405_pp0_it3)) | ((ap_reg_ppstg_exitcond_reg_1396_pp0_it4 == ap_const_lv1_0) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_reg_1405_pp0_it4)) | ((ap_reg_ppstg_exitcond_reg_1396_pp0_it5 == ap_const_lv1_0) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_reg_1405_pp0_it5)) | ((ap_reg_ppstg_exitcond_reg_1396_pp0_it6 == ap_const_lv1_0) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_reg_1405_pp0_it6)) | ((ap_reg_ppstg_exitcond_reg_1396_pp0_it7 == ap_const_lv1_0) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_reg_1405_pp0_it7)) | ((ap_reg_ppstg_exitcond_reg_1396_pp0_it8 == ap_const_lv1_0) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_reg_1405_pp0_it8)) | ((ap_reg_ppstg_exitcond_reg_1396_pp0_it9 == ap_const_lv1_0) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_reg_1405_pp0_it9)) | ((ap_reg_ppstg_exitcond_reg_1396_pp0_it10 == ap_const_lv1_0) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_reg_1405_pp0_it10)) | ((ap_reg_ppstg_exitcond_reg_1396_pp0_it11 == ap_const_lv1_0) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_reg_1405_pp0_it11)) | ((ap_reg_ppstg_exitcond_reg_1396_pp0_it12 == ap_const_lv1_0) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_reg_1405_pp0_it12)) | ((ap_reg_ppstg_exitcond_reg_1396_pp0_it13 == ap_const_lv1_0) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_reg_1405_pp0_it13)) | ((ap_reg_ppstg_exitcond_reg_1396_pp0_it14 == ap_const_lv1_0) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_reg_1405_pp0_it14)) | ((ap_reg_ppstg_exitcond_reg_1396_pp0_it15 == ap_const_lv1_0) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_reg_1405_pp0_it15)) | ((ap_reg_ppstg_exitcond_reg_1396_pp0_it16 == ap_const_lv1_0) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_reg_1405_pp0_it16)) | ((ap_reg_ppstg_exitcond_reg_1396_pp0_it17 == ap_const_lv1_0) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_reg_1405_pp0_it17)) | ((ap_reg_ppstg_exitcond_reg_1396_pp0_it18 == ap_const_lv1_0) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_reg_1405_pp0_it18)) | ((ap_reg_ppstg_exitcond_reg_1396_pp0_it19 == ap_const_lv1_0) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_reg_1405_pp0_it19)) | ((ap_reg_ppstg_exitcond_reg_1396_pp0_it20 == ap_const_lv1_0) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_reg_1405_pp0_it20)) | ((ap_reg_ppstg_exitcond_reg_1396_pp0_it21 == ap_const_lv1_0) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_reg_1405_pp0_it21)) | ((ap_reg_ppstg_exitcond_reg_1396_pp0_it22 == ap_const_lv1_0) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_reg_1405_pp0_it22)) | ((ap_reg_ppstg_exitcond_reg_1396_pp0_it23 == ap_const_lv1_0) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_reg_1405_pp0_it23)) | ((ap_reg_ppstg_exitcond_reg_1396_pp0_it24 == ap_const_lv1_0) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_reg_1405_pp0_it24)) | ((ap_reg_ppstg_exitcond_reg_1396_pp0_it25 == ap_const_lv1_0) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_reg_1405_pp0_it25)) | ((ap_reg_ppstg_exitcond_reg_1396_pp0_it26 == ap_const_lv1_0) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_reg_1405_pp0_it26)) | ((ap_reg_ppstg_exitcond_reg_1396_pp0_it27 == ap_const_lv1_0) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_reg_1405_pp0_it27)) | ((ap_reg_ppstg_exitcond_reg_1396_pp0_it28 == ap_const_lv1_0) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_reg_1405_pp0_it28)) | ((ap_reg_ppstg_exitcond_reg_1396_pp0_it29 == ap_const_lv1_0) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_reg_1405_pp0_it29)) | ((ap_reg_ppstg_exitcond_reg_1396_pp0_it30 == ap_const_lv1_0) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_reg_1405_pp0_it30)) | ((ap_reg_ppstg_exitcond_reg_1396_pp0_it31 == ap_const_lv1_0) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_reg_1405_pp0_it31)) | ((ap_reg_ppstg_exitcond_reg_1396_pp0_it32 == ap_const_lv1_0) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_reg_1405_pp0_it32)) | ((ap_reg_ppstg_exitcond_reg_1396_pp0_it33 == ap_const_lv1_0) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_reg_1405_pp0_it33)) | ((ap_reg_ppstg_exitcond_reg_1396_pp0_it34 == ap_const_lv1_0) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_reg_1405_pp0_it34)) | ((ap_reg_ppstg_exitcond_reg_1396_pp0_it35 == ap_const_lv1_0) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_reg_1405_pp0_it35)) | ((ap_reg_ppstg_exitcond_reg_1396_pp0_it36 == ap_const_lv1_0) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_reg_1405_pp0_it36)) | ((ap_reg_ppstg_exitcond_reg_1396_pp0_it37 == ap_const_lv1_0) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_reg_1405_pp0_it37)) | ((ap_reg_ppstg_exitcond_reg_1396_pp0_it38 == ap_const_lv1_0) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_reg_1405_pp0_it38)) | ((ap_reg_ppstg_exitcond_reg_1396_pp0_it39 == ap_const_lv1_0) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_reg_1405_pp0_it39)) | ((ap_reg_ppstg_exitcond_reg_1396_pp0_it40 == ap_const_lv1_0) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_reg_1405_pp0_it40)) | ((ap_reg_ppstg_exitcond_reg_1396_pp0_it41 == ap_const_lv1_0) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_reg_1405_pp0_it41)) | ((ap_reg_ppstg_exitcond_reg_1396_pp0_it42 == ap_const_lv1_0) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_reg_1405_pp0_it42)) | ((ap_reg_ppstg_exitcond_reg_1396_pp0_it43 == ap_const_lv1_0) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_reg_1405_pp0_it43)) | ((ap_reg_ppstg_exitcond_reg_1396_pp0_it44 == ap_const_lv1_0) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_reg_1405_pp0_it44)) | ((ap_reg_ppstg_exitcond_reg_1396_pp0_it45 == ap_const_lv1_0) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_reg_1405_pp0_it45)) | ((ap_reg_ppstg_exitcond_reg_1396_pp0_it46 == ap_const_lv1_0) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_reg_1405_pp0_it46)) | ((ap_reg_ppstg_exitcond_reg_1396_pp0_it47 == ap_const_lv1_0) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_reg_1405_pp0_it47)) | ((ap_reg_ppstg_exitcond_reg_1396_pp0_it48 == ap_const_lv1_0) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_reg_1405_pp0_it48)) | ((ap_reg_ppstg_exitcond_reg_1396_pp0_it49 == ap_const_lv1_0) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_reg_1405_pp0_it49)) | ((ap_reg_ppstg_exitcond_reg_1396_pp0_it50 == ap_const_lv1_0) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_reg_1405_pp0_it50)) | ((ap_reg_ppstg_exitcond_reg_1396_pp0_it51 == ap_const_lv1_0) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_reg_1405_pp0_it51)) | ((ap_reg_ppstg_exitcond_reg_1396_pp0_it52 == ap_const_lv1_0) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_reg_1405_pp0_it52)) | ((ap_reg_ppstg_exitcond_reg_1396_pp0_it53 == ap_const_lv1_0) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_reg_1405_pp0_it53)) | ((ap_reg_ppstg_exitcond_reg_1396_pp0_it54 == ap_const_lv1_0) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_reg_1405_pp0_it54)) | ((ap_reg_ppstg_exitcond_reg_1396_pp0_it55 == ap_const_lv1_0) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_reg_1405_pp0_it55)) | ((ap_reg_ppstg_exitcond_reg_1396_pp0_it56 == ap_const_lv1_0) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_reg_1405_pp0_it56)) | ((ap_reg_ppstg_exitcond_reg_1396_pp0_it57 == ap_const_lv1_0) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_reg_1405_pp0_it57)) | ((ap_reg_ppstg_exitcond_reg_1396_pp0_it58 == ap_const_lv1_0) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_reg_1405_pp0_it58)) | ((ap_reg_ppstg_exitcond_reg_1396_pp0_it59 == ap_const_lv1_0) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_reg_1405_pp0_it59)) | ((ap_reg_ppstg_exitcond_reg_1396_pp0_it60 == ap_const_lv1_0) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_reg_1405_pp0_it60)) | ((ap_reg_ppstg_exitcond_reg_1396_pp0_it61 == ap_const_lv1_0) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_reg_1405_pp0_it61)) | ((ap_reg_ppstg_exitcond_reg_1396_pp0_it62 == ap_const_lv1_0) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_reg_1405_pp0_it62)) | ((ap_reg_ppstg_exitcond_reg_1396_pp0_it63 == ap_const_lv1_0) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_reg_1405_pp0_it63)) | ((ap_reg_ppstg_exitcond_reg_1396_pp0_it64 == ap_const_lv1_0) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_reg_1405_pp0_it64)) | ((ap_reg_ppstg_exitcond_reg_1396_pp0_it65 == ap_const_lv1_0) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_reg_1405_pp0_it65)) | ((ap_reg_ppstg_exitcond_reg_1396_pp0_it66 == ap_const_lv1_0) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_reg_1405_pp0_it66)) | ((ap_reg_ppstg_exitcond_reg_1396_pp0_it67 == ap_const_lv1_0) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_reg_1405_pp0_it67)) | ((ap_reg_ppstg_exitcond_reg_1396_pp0_it68 == ap_const_lv1_0) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_reg_1405_pp0_it68))))) begin
grp_computeResultOne_fu_763_ap_ce = ap_const_logic_1;
end else begin
grp_computeResultOne_fu_763_ap_ce = ap_const_logic_0;
end
end
/// grp_computeResultOne_fu_794_ap_ce assign process. ///
always @ (ap_CS_fsm or exitcond_reg_1396 or ap_reg_ppstg_exitcond_reg_1396_pp0_it1 or ap_reg_ppstg_exitcond_reg_1396_pp0_it2 or ap_reg_ppstg_exitcond_reg_1396_pp0_it3 or ap_reg_ppstg_exitcond_reg_1396_pp0_it4 or ap_reg_ppstg_exitcond_reg_1396_pp0_it5 or ap_reg_ppstg_exitcond_reg_1396_pp0_it6 or ap_reg_ppstg_exitcond_reg_1396_pp0_it7 or ap_reg_ppstg_exitcond_reg_1396_pp0_it8 or ap_reg_ppstg_exitcond_reg_1396_pp0_it9 or ap_reg_ppstg_exitcond_reg_1396_pp0_it10 or ap_reg_ppstg_exitcond_reg_1396_pp0_it11 or ap_reg_ppstg_exitcond_reg_1396_pp0_it12 or ap_reg_ppstg_exitcond_reg_1396_pp0_it13 or ap_reg_ppstg_exitcond_reg_1396_pp0_it14 or ap_reg_ppstg_exitcond_reg_1396_pp0_it15 or ap_reg_ppstg_exitcond_reg_1396_pp0_it16 or ap_reg_ppstg_exitcond_reg_1396_pp0_it17 or ap_reg_ppstg_exitcond_reg_1396_pp0_it18 or ap_reg_ppstg_exitcond_reg_1396_pp0_it19 or ap_reg_ppstg_exitcond_reg_1396_pp0_it20 or ap_reg_ppstg_exitcond_reg_1396_pp0_it21 or ap_reg_ppstg_exitcond_reg_1396_pp0_it22 or ap_reg_ppstg_exitcond_reg_1396_pp0_it23 or ap_reg_ppstg_exitcond_reg_1396_pp0_it24 or ap_reg_ppstg_exitcond_reg_1396_pp0_it25 or ap_reg_ppstg_exitcond_reg_1396_pp0_it26 or ap_reg_ppstg_exitcond_reg_1396_pp0_it27 or ap_reg_ppstg_exitcond_reg_1396_pp0_it28 or ap_reg_ppstg_exitcond_reg_1396_pp0_it29 or ap_reg_ppstg_exitcond_reg_1396_pp0_it30 or ap_reg_ppstg_exitcond_reg_1396_pp0_it31 or ap_reg_ppstg_exitcond_reg_1396_pp0_it32 or ap_reg_ppstg_exitcond_reg_1396_pp0_it33 or ap_reg_ppstg_exitcond_reg_1396_pp0_it34 or ap_reg_ppstg_exitcond_reg_1396_pp0_it35 or ap_reg_ppstg_exitcond_reg_1396_pp0_it36 or ap_reg_ppstg_exitcond_reg_1396_pp0_it37 or ap_reg_ppstg_exitcond_reg_1396_pp0_it38 or ap_reg_ppstg_exitcond_reg_1396_pp0_it39 or ap_reg_ppstg_exitcond_reg_1396_pp0_it40 or ap_reg_ppstg_exitcond_reg_1396_pp0_it41 or ap_reg_ppstg_exitcond_reg_1396_pp0_it42 or ap_reg_ppstg_exitcond_reg_1396_pp0_it43 or ap_reg_ppstg_exitcond_reg_1396_pp0_it44 or ap_reg_ppstg_exitcond_reg_1396_pp0_it45 or ap_reg_ppstg_exitcond_reg_1396_pp0_it46 or ap_reg_ppstg_exitcond_reg_1396_pp0_it47 or ap_reg_ppstg_exitcond_reg_1396_pp0_it48 or ap_reg_ppstg_exitcond_reg_1396_pp0_it49 or ap_reg_ppstg_exitcond_reg_1396_pp0_it50 or ap_reg_ppstg_exitcond_reg_1396_pp0_it51 or ap_reg_ppstg_exitcond_reg_1396_pp0_it52 or ap_reg_ppstg_exitcond_reg_1396_pp0_it53 or ap_reg_ppstg_exitcond_reg_1396_pp0_it54 or ap_reg_ppstg_exitcond_reg_1396_pp0_it55 or ap_reg_ppstg_exitcond_reg_1396_pp0_it56 or ap_reg_ppstg_exitcond_reg_1396_pp0_it57 or ap_reg_ppstg_exitcond_reg_1396_pp0_it58 or ap_reg_ppstg_exitcond_reg_1396_pp0_it59 or ap_reg_ppstg_exitcond_reg_1396_pp0_it60 or ap_reg_ppstg_exitcond_reg_1396_pp0_it61 or ap_reg_ppstg_exitcond_reg_1396_pp0_it62 or ap_reg_ppstg_exitcond_reg_1396_pp0_it63 or ap_reg_ppstg_exitcond_reg_1396_pp0_it64 or ap_reg_ppstg_exitcond_reg_1396_pp0_it65 or ap_reg_ppstg_exitcond_reg_1396_pp0_it66 or ap_reg_ppstg_exitcond_reg_1396_pp0_it67 or ap_reg_ppstg_exitcond_reg_1396_pp0_it68 or ap_reg_ppstg_exitcond_reg_1396_pp0_it69 or tmp_reg_1405 or ap_reg_ppstg_tmp_reg_1405_pp0_it1 or ap_reg_ppstg_tmp_reg_1405_pp0_it2 or ap_reg_ppstg_tmp_reg_1405_pp0_it3 or ap_reg_ppstg_tmp_reg_1405_pp0_it4 or ap_reg_ppstg_tmp_reg_1405_pp0_it5 or ap_reg_ppstg_tmp_reg_1405_pp0_it6 or ap_reg_ppstg_tmp_reg_1405_pp0_it7 or ap_reg_ppstg_tmp_reg_1405_pp0_it8 or ap_reg_ppstg_tmp_reg_1405_pp0_it9 or ap_reg_ppstg_tmp_reg_1405_pp0_it10 or ap_reg_ppstg_tmp_reg_1405_pp0_it11 or ap_reg_ppstg_tmp_reg_1405_pp0_it12 or ap_reg_ppstg_tmp_reg_1405_pp0_it13 or ap_reg_ppstg_tmp_reg_1405_pp0_it14 or ap_reg_ppstg_tmp_reg_1405_pp0_it15 or ap_reg_ppstg_tmp_reg_1405_pp0_it16 or ap_reg_ppstg_tmp_reg_1405_pp0_it17 or ap_reg_ppstg_tmp_reg_1405_pp0_it18 or ap_reg_ppstg_tmp_reg_1405_pp0_it19 or ap_reg_ppstg_tmp_reg_1405_pp0_it20 or ap_reg_ppstg_tmp_reg_1405_pp0_it21 or ap_reg_ppstg_tmp_reg_1405_pp0_it22 or ap_reg_ppstg_tmp_reg_1405_pp0_it23 or ap_reg_ppstg_tmp_reg_1405_pp0_it24 or ap_reg_ppstg_tmp_reg_1405_pp0_it25 or ap_reg_ppstg_tmp_reg_1405_pp0_it26 or ap_reg_ppstg_tmp_reg_1405_pp0_it27 or ap_reg_ppstg_tmp_reg_1405_pp0_it28 or ap_reg_ppstg_tmp_reg_1405_pp0_it29 or ap_reg_ppstg_tmp_reg_1405_pp0_it30 or ap_reg_ppstg_tmp_reg_1405_pp0_it31 or ap_reg_ppstg_tmp_reg_1405_pp0_it32 or ap_reg_ppstg_tmp_reg_1405_pp0_it33 or ap_reg_ppstg_tmp_reg_1405_pp0_it34 or ap_reg_ppstg_tmp_reg_1405_pp0_it35 or ap_reg_ppstg_tmp_reg_1405_pp0_it36 or ap_reg_ppstg_tmp_reg_1405_pp0_it37 or ap_reg_ppstg_tmp_reg_1405_pp0_it38 or ap_reg_ppstg_tmp_reg_1405_pp0_it39 or ap_reg_ppstg_tmp_reg_1405_pp0_it40 or ap_reg_ppstg_tmp_reg_1405_pp0_it41 or ap_reg_ppstg_tmp_reg_1405_pp0_it42 or ap_reg_ppstg_tmp_reg_1405_pp0_it43 or ap_reg_ppstg_tmp_reg_1405_pp0_it44 or ap_reg_ppstg_tmp_reg_1405_pp0_it45 or ap_reg_ppstg_tmp_reg_1405_pp0_it46 or ap_reg_ppstg_tmp_reg_1405_pp0_it47 or ap_reg_ppstg_tmp_reg_1405_pp0_it48 or ap_reg_ppstg_tmp_reg_1405_pp0_it49 or ap_reg_ppstg_tmp_reg_1405_pp0_it50 or ap_reg_ppstg_tmp_reg_1405_pp0_it51 or ap_reg_ppstg_tmp_reg_1405_pp0_it52 or ap_reg_ppstg_tmp_reg_1405_pp0_it53 or ap_reg_ppstg_tmp_reg_1405_pp0_it54 or ap_reg_ppstg_tmp_reg_1405_pp0_it55 or ap_reg_ppstg_tmp_reg_1405_pp0_it56 or ap_reg_ppstg_tmp_reg_1405_pp0_it57 or ap_reg_ppstg_tmp_reg_1405_pp0_it58 or ap_reg_ppstg_tmp_reg_1405_pp0_it59 or ap_reg_ppstg_tmp_reg_1405_pp0_it60 or ap_reg_ppstg_tmp_reg_1405_pp0_it61 or ap_reg_ppstg_tmp_reg_1405_pp0_it62 or ap_reg_ppstg_tmp_reg_1405_pp0_it63 or ap_reg_ppstg_tmp_reg_1405_pp0_it64 or ap_reg_ppstg_tmp_reg_1405_pp0_it65 or ap_reg_ppstg_tmp_reg_1405_pp0_it66 or ap_reg_ppstg_tmp_reg_1405_pp0_it67 or ap_reg_ppstg_tmp_reg_1405_pp0_it68 or ap_reg_ppstg_tmp_reg_1405_pp0_it69)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (((ap_reg_ppstg_exitcond_reg_1396_pp0_it69 == ap_const_lv1_0) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_reg_1405_pp0_it69)) | ((exitcond_reg_1396 == ap_const_lv1_0) & (tmp_reg_1405 == ap_const_lv1_0)) | ((ap_reg_ppstg_exitcond_reg_1396_pp0_it1 == ap_const_lv1_0) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_reg_1405_pp0_it1)) | ((ap_reg_ppstg_exitcond_reg_1396_pp0_it2 == ap_const_lv1_0) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_reg_1405_pp0_it2)) | ((ap_reg_ppstg_exitcond_reg_1396_pp0_it3 == ap_const_lv1_0) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_reg_1405_pp0_it3)) | ((ap_reg_ppstg_exitcond_reg_1396_pp0_it4 == ap_const_lv1_0) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_reg_1405_pp0_it4)) | ((ap_reg_ppstg_exitcond_reg_1396_pp0_it5 == ap_const_lv1_0) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_reg_1405_pp0_it5)) | ((ap_reg_ppstg_exitcond_reg_1396_pp0_it6 == ap_const_lv1_0) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_reg_1405_pp0_it6)) | ((ap_reg_ppstg_exitcond_reg_1396_pp0_it7 == ap_const_lv1_0) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_reg_1405_pp0_it7)) | ((ap_reg_ppstg_exitcond_reg_1396_pp0_it8 == ap_const_lv1_0) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_reg_1405_pp0_it8)) | ((ap_reg_ppstg_exitcond_reg_1396_pp0_it9 == ap_const_lv1_0) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_reg_1405_pp0_it9)) | ((ap_reg_ppstg_exitcond_reg_1396_pp0_it10 == ap_const_lv1_0) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_reg_1405_pp0_it10)) | ((ap_reg_ppstg_exitcond_reg_1396_pp0_it11 == ap_const_lv1_0) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_reg_1405_pp0_it11)) | ((ap_reg_ppstg_exitcond_reg_1396_pp0_it12 == ap_const_lv1_0) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_reg_1405_pp0_it12)) | ((ap_reg_ppstg_exitcond_reg_1396_pp0_it13 == ap_const_lv1_0) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_reg_1405_pp0_it13)) | ((ap_reg_ppstg_exitcond_reg_1396_pp0_it14 == ap_const_lv1_0) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_reg_1405_pp0_it14)) | ((ap_reg_ppstg_exitcond_reg_1396_pp0_it15 == ap_const_lv1_0) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_reg_1405_pp0_it15)) | ((ap_reg_ppstg_exitcond_reg_1396_pp0_it16 == ap_const_lv1_0) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_reg_1405_pp0_it16)) | ((ap_reg_ppstg_exitcond_reg_1396_pp0_it17 == ap_const_lv1_0) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_reg_1405_pp0_it17)) | ((ap_reg_ppstg_exitcond_reg_1396_pp0_it18 == ap_const_lv1_0) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_reg_1405_pp0_it18)) | ((ap_reg_ppstg_exitcond_reg_1396_pp0_it19 == ap_const_lv1_0) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_reg_1405_pp0_it19)) | ((ap_reg_ppstg_exitcond_reg_1396_pp0_it20 == ap_const_lv1_0) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_reg_1405_pp0_it20)) | ((ap_reg_ppstg_exitcond_reg_1396_pp0_it21 == ap_const_lv1_0) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_reg_1405_pp0_it21)) | ((ap_reg_ppstg_exitcond_reg_1396_pp0_it22 == ap_const_lv1_0) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_reg_1405_pp0_it22)) | ((ap_reg_ppstg_exitcond_reg_1396_pp0_it23 == ap_const_lv1_0) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_reg_1405_pp0_it23)) | ((ap_reg_ppstg_exitcond_reg_1396_pp0_it24 == ap_const_lv1_0) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_reg_1405_pp0_it24)) | ((ap_reg_ppstg_exitcond_reg_1396_pp0_it25 == ap_const_lv1_0) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_reg_1405_pp0_it25)) | ((ap_reg_ppstg_exitcond_reg_1396_pp0_it26 == ap_const_lv1_0) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_reg_1405_pp0_it26)) | ((ap_reg_ppstg_exitcond_reg_1396_pp0_it27 == ap_const_lv1_0) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_reg_1405_pp0_it27)) | ((ap_reg_ppstg_exitcond_reg_1396_pp0_it28 == ap_const_lv1_0) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_reg_1405_pp0_it28)) | ((ap_reg_ppstg_exitcond_reg_1396_pp0_it29 == ap_const_lv1_0) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_reg_1405_pp0_it29)) | ((ap_reg_ppstg_exitcond_reg_1396_pp0_it30 == ap_const_lv1_0) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_reg_1405_pp0_it30)) | ((ap_reg_ppstg_exitcond_reg_1396_pp0_it31 == ap_const_lv1_0) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_reg_1405_pp0_it31)) | ((ap_reg_ppstg_exitcond_reg_1396_pp0_it32 == ap_const_lv1_0) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_reg_1405_pp0_it32)) | ((ap_reg_ppstg_exitcond_reg_1396_pp0_it33 == ap_const_lv1_0) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_reg_1405_pp0_it33)) | ((ap_reg_ppstg_exitcond_reg_1396_pp0_it34 == ap_const_lv1_0) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_reg_1405_pp0_it34)) | ((ap_reg_ppstg_exitcond_reg_1396_pp0_it35 == ap_const_lv1_0) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_reg_1405_pp0_it35)) | ((ap_reg_ppstg_exitcond_reg_1396_pp0_it36 == ap_const_lv1_0) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_reg_1405_pp0_it36)) | ((ap_reg_ppstg_exitcond_reg_1396_pp0_it37 == ap_const_lv1_0) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_reg_1405_pp0_it37)) | ((ap_reg_ppstg_exitcond_reg_1396_pp0_it38 == ap_const_lv1_0) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_reg_1405_pp0_it38)) | ((ap_reg_ppstg_exitcond_reg_1396_pp0_it39 == ap_const_lv1_0) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_reg_1405_pp0_it39)) | ((ap_reg_ppstg_exitcond_reg_1396_pp0_it40 == ap_const_lv1_0) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_reg_1405_pp0_it40)) | ((ap_reg_ppstg_exitcond_reg_1396_pp0_it41 == ap_const_lv1_0) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_reg_1405_pp0_it41)) | ((ap_reg_ppstg_exitcond_reg_1396_pp0_it42 == ap_const_lv1_0) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_reg_1405_pp0_it42)) | ((ap_reg_ppstg_exitcond_reg_1396_pp0_it43 == ap_const_lv1_0) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_reg_1405_pp0_it43)) | ((ap_reg_ppstg_exitcond_reg_1396_pp0_it44 == ap_const_lv1_0) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_reg_1405_pp0_it44)) | ((ap_reg_ppstg_exitcond_reg_1396_pp0_it45 == ap_const_lv1_0) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_reg_1405_pp0_it45)) | ((ap_reg_ppstg_exitcond_reg_1396_pp0_it46 == ap_const_lv1_0) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_reg_1405_pp0_it46)) | ((ap_reg_ppstg_exitcond_reg_1396_pp0_it47 == ap_const_lv1_0) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_reg_1405_pp0_it47)) | ((ap_reg_ppstg_exitcond_reg_1396_pp0_it48 == ap_const_lv1_0) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_reg_1405_pp0_it48)) | ((ap_reg_ppstg_exitcond_reg_1396_pp0_it49 == ap_const_lv1_0) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_reg_1405_pp0_it49)) | ((ap_reg_ppstg_exitcond_reg_1396_pp0_it50 == ap_const_lv1_0) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_reg_1405_pp0_it50)) | ((ap_reg_ppstg_exitcond_reg_1396_pp0_it51 == ap_const_lv1_0) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_reg_1405_pp0_it51)) | ((ap_reg_ppstg_exitcond_reg_1396_pp0_it52 == ap_const_lv1_0) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_reg_1405_pp0_it52)) | ((ap_reg_ppstg_exitcond_reg_1396_pp0_it53 == ap_const_lv1_0) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_reg_1405_pp0_it53)) | ((ap_reg_ppstg_exitcond_reg_1396_pp0_it54 == ap_const_lv1_0) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_reg_1405_pp0_it54)) | ((ap_reg_ppstg_exitcond_reg_1396_pp0_it55 == ap_const_lv1_0) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_reg_1405_pp0_it55)) | ((ap_reg_ppstg_exitcond_reg_1396_pp0_it56 == ap_const_lv1_0) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_reg_1405_pp0_it56)) | ((ap_reg_ppstg_exitcond_reg_1396_pp0_it57 == ap_const_lv1_0) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_reg_1405_pp0_it57)) | ((ap_reg_ppstg_exitcond_reg_1396_pp0_it58 == ap_const_lv1_0) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_reg_1405_pp0_it58)) | ((ap_reg_ppstg_exitcond_reg_1396_pp0_it59 == ap_const_lv1_0) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_reg_1405_pp0_it59)) | ((ap_reg_ppstg_exitcond_reg_1396_pp0_it60 == ap_const_lv1_0) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_reg_1405_pp0_it60)) | ((ap_reg_ppstg_exitcond_reg_1396_pp0_it61 == ap_const_lv1_0) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_reg_1405_pp0_it61)) | ((ap_reg_ppstg_exitcond_reg_1396_pp0_it62 == ap_const_lv1_0) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_reg_1405_pp0_it62)) | ((ap_reg_ppstg_exitcond_reg_1396_pp0_it63 == ap_const_lv1_0) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_reg_1405_pp0_it63)) | ((ap_reg_ppstg_exitcond_reg_1396_pp0_it64 == ap_const_lv1_0) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_reg_1405_pp0_it64)) | ((ap_reg_ppstg_exitcond_reg_1396_pp0_it65 == ap_const_lv1_0) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_reg_1405_pp0_it65)) | ((ap_reg_ppstg_exitcond_reg_1396_pp0_it66 == ap_const_lv1_0) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_reg_1405_pp0_it66)) | ((ap_reg_ppstg_exitcond_reg_1396_pp0_it67 == ap_const_lv1_0) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_reg_1405_pp0_it67)) | ((ap_reg_ppstg_exitcond_reg_1396_pp0_it68 == ap_const_lv1_0) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_reg_1405_pp0_it68))))) begin
grp_computeResultOne_fu_794_ap_ce = ap_const_logic_1;
end else begin
grp_computeResultOne_fu_794_ap_ce = ap_const_logic_0;
end
end
/// i_1_phi_fu_666_p4 assign process. ///
always @ (ap_CS_fsm or i_1_reg_662 or exitcond_reg_1396 or ap_reg_ppiten_pp0_it1 or i_reg_1615)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (exitcond_reg_1396 == ap_const_lv1_0))) begin
i_1_phi_fu_666_p4 = i_reg_1615;
end else begin
i_1_phi_fu_666_p4 = i_1_reg_662;
end
end
/// j_phi_fu_655_p4 assign process. ///
always @ (ap_CS_fsm or j_reg_651 or exitcond_reg_1396 or ap_reg_ppiten_pp0_it1 or j_1_reg_1610)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (exitcond_reg_1396 == ap_const_lv1_0))) begin
j_phi_fu_655_p4 = j_1_reg_1610;
end else begin
j_phi_fu_655_p4 = j_reg_651;
end
end
/// k_phi_fu_644_p4 assign process. ///
always @ (ap_CS_fsm or k_reg_640 or exitcond_reg_1396 or ap_reg_ppiten_pp0_it1 or indvar_next_reg_1400)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (exitcond_reg_1396 == ap_const_lv1_0))) begin
k_phi_fu_644_p4 = indvar_next_reg_1400;
end else begin
k_phi_fu_644_p4 = k_reg_640;
end
end
/// r_p0_ce0 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp0_it70 or ap_reg_ppstg_exitcond_reg_1396_pp0_it69)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it70) & (ap_reg_ppstg_exitcond_reg_1396_pp0_it69 == ap_const_lv1_0))) begin
r_p0_ce0 = ap_const_logic_1;
end else begin
r_p0_ce0 = ap_const_logic_0;
end
end
/// r_p0_we0 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp0_it70 or ap_reg_ppstg_exitcond_reg_1396_pp0_it69)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it70) & (ap_reg_ppstg_exitcond_reg_1396_pp0_it69 == ap_const_lv1_0))) begin
r_p0_we0 = ap_const_logic_1;
end else begin
r_p0_we0 = ap_const_logic_0;
end
end
/// r_p1_ce0 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp0_it70 or ap_reg_ppstg_exitcond_reg_1396_pp0_it69)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it70) & (ap_reg_ppstg_exitcond_reg_1396_pp0_it69 == ap_const_lv1_0))) begin
r_p1_ce0 = ap_const_logic_1;
end else begin
r_p1_ce0 = ap_const_logic_0;
end
end
/// r_p1_we0 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp0_it70 or ap_reg_ppstg_exitcond_reg_1396_pp0_it69)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it70) & (ap_reg_ppstg_exitcond_reg_1396_pp0_it69 == ap_const_lv1_0))) begin
r_p1_we0 = ap_const_logic_1;
end else begin
r_p1_we0 = ap_const_logic_0;
end
end
/// r_p2_ce0 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp0_it70 or ap_reg_ppstg_exitcond_reg_1396_pp0_it69 or ap_reg_ppstg_tmp_reg_1405_pp0_it69)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it70) & (ap_reg_ppstg_exitcond_reg_1396_pp0_it69 == ap_const_lv1_0) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_reg_1405_pp0_it69))) begin
r_p2_ce0 = ap_const_logic_1;
end else begin
r_p2_ce0 = ap_const_logic_0;
end
end
/// r_p2_we0 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp0_it70 or ap_reg_ppstg_exitcond_reg_1396_pp0_it69 or ap_reg_ppstg_tmp_reg_1405_pp0_it69)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it70) & (ap_reg_ppstg_exitcond_reg_1396_pp0_it69 == ap_const_lv1_0) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_reg_1405_pp0_it69))) begin
r_p2_we0 = ap_const_logic_1;
end else begin
r_p2_we0 = ap_const_logic_0;
end
end
/// r_p3_ce0 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp0_it70 or ap_reg_ppstg_exitcond_reg_1396_pp0_it69 or ap_reg_ppstg_tmp_reg_1405_pp0_it69)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it70) & (ap_reg_ppstg_exitcond_reg_1396_pp0_it69 == ap_const_lv1_0) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_reg_1405_pp0_it69))) begin
r_p3_ce0 = ap_const_logic_1;
end else begin
r_p3_ce0 = ap_const_logic_0;
end
end
/// r_p3_we0 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp0_it70 or ap_reg_ppstg_exitcond_reg_1396_pp0_it69 or ap_reg_ppstg_tmp_reg_1405_pp0_it69)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it70) & (ap_reg_ppstg_exitcond_reg_1396_pp0_it69 == ap_const_lv1_0) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_reg_1405_pp0_it69))) begin
r_p3_we0 = ap_const_logic_1;
end else begin
r_p3_we0 = ap_const_logic_0;
end
end
/// u_p0_ce0 assign process. ///
always @ (ap_CS_fsm or exitcond_fu_876_p2 or ap_reg_ppiten_pp0_it0)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_fu_876_p2 == ap_const_lv1_0))) begin
u_p0_ce0 = ap_const_logic_1;
end else begin
u_p0_ce0 = ap_const_logic_0;
end
end
/// u_p1_ce0 assign process. ///
always @ (ap_CS_fsm or exitcond_fu_876_p2 or ap_reg_ppiten_pp0_it0)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_fu_876_p2 == ap_const_lv1_0))) begin
u_p1_ce0 = ap_const_logic_1;
end else begin
u_p1_ce0 = ap_const_logic_0;
end
end
/// u_p2_ce0 assign process. ///
always @ (ap_CS_fsm or exitcond_fu_876_p2 or ap_reg_ppiten_pp0_it0)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_fu_876_p2 == ap_const_lv1_0))) begin
u_p2_ce0 = ap_const_logic_1;
end else begin
u_p2_ce0 = ap_const_logic_0;
end
end
/// u_p3_ce0 assign process. ///
always @ (ap_CS_fsm or exitcond_fu_876_p2 or ap_reg_ppiten_pp0_it0)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_fu_876_p2 == ap_const_lv1_0))) begin
u_p3_ce0 = ap_const_logic_1;
end else begin
u_p3_ce0 = ap_const_logic_0;
end
end
/// ug0_p0_ce0 assign process. ///
always @ (ap_CS_fsm or exitcond_fu_876_p2 or ap_reg_ppiten_pp0_it0)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_fu_876_p2 == ap_const_lv1_0))) begin
ug0_p0_ce0 = ap_const_logic_1;
end else begin
ug0_p0_ce0 = ap_const_logic_0;
end
end
/// ug0_p1_ce0 assign process. ///
always @ (ap_CS_fsm or exitcond_fu_876_p2 or ap_reg_ppiten_pp0_it0)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_fu_876_p2 == ap_const_lv1_0))) begin
ug0_p1_ce0 = ap_const_logic_1;
end else begin
ug0_p1_ce0 = ap_const_logic_0;
end
end
/// ug0_p2_ce0 assign process. ///
always @ (ap_CS_fsm or exitcond_fu_876_p2 or ap_reg_ppiten_pp0_it0)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_fu_876_p2 == ap_const_lv1_0))) begin
ug0_p2_ce0 = ap_const_logic_1;
end else begin
ug0_p2_ce0 = ap_const_logic_0;
end
end
/// ug0_p3_ce0 assign process. ///
always @ (ap_CS_fsm or exitcond_fu_876_p2 or ap_reg_ppiten_pp0_it0)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_fu_876_p2 == ap_const_lv1_0))) begin
ug0_p3_ce0 = ap_const_logic_1;
end else begin
ug0_p3_ce0 = ap_const_logic_0;
end
end
/// ug1_p0_ce0 assign process. ///
always @ (ap_CS_fsm or exitcond_fu_876_p2 or ap_reg_ppiten_pp0_it0)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_fu_876_p2 == ap_const_lv1_0))) begin
ug1_p0_ce0 = ap_const_logic_1;
end else begin
ug1_p0_ce0 = ap_const_logic_0;
end
end
/// ug1_p0_ce1 assign process. ///
always @ (ap_CS_fsm or exitcond_fu_876_p2 or ap_reg_ppiten_pp0_it0)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_fu_876_p2 == ap_const_lv1_0))) begin
ug1_p0_ce1 = ap_const_logic_1;
end else begin
ug1_p0_ce1 = ap_const_logic_0;
end
end
/// ug1_p1_ce0 assign process. ///
always @ (ap_CS_fsm or exitcond_fu_876_p2 or ap_reg_ppiten_pp0_it0)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_fu_876_p2 == ap_const_lv1_0))) begin
ug1_p1_ce0 = ap_const_logic_1;
end else begin
ug1_p1_ce0 = ap_const_logic_0;
end
end
/// ug1_p2_ce0 assign process. ///
always @ (ap_CS_fsm or exitcond_fu_876_p2 or ap_reg_ppiten_pp0_it0)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_fu_876_p2 == ap_const_lv1_0))) begin
ug1_p2_ce0 = ap_const_logic_1;
end else begin
ug1_p2_ce0 = ap_const_logic_0;
end
end
/// ug1_p3_ce0 assign process. ///
always @ (ap_CS_fsm or exitcond_fu_876_p2 or ap_reg_ppiten_pp0_it0)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_fu_876_p2 == ap_const_lv1_0))) begin
ug1_p3_ce0 = ap_const_logic_1;
end else begin
ug1_p3_ce0 = ap_const_logic_0;
end
end
/// ug1_p3_ce1 assign process. ///
always @ (ap_CS_fsm or exitcond_fu_876_p2 or ap_reg_ppiten_pp0_it0)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_fu_876_p2 == ap_const_lv1_0))) begin
ug1_p3_ce1 = ap_const_logic_1;
end else begin
ug1_p3_ce1 = ap_const_logic_0;
end
end
/// ug2_p0_ce0 assign process. ///
always @ (ap_CS_fsm or exitcond_fu_876_p2 or ap_reg_ppiten_pp0_it0)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_fu_876_p2 == ap_const_lv1_0))) begin
ug2_p0_ce0 = ap_const_logic_1;
end else begin
ug2_p0_ce0 = ap_const_logic_0;
end
end
/// ug2_p1_ce0 assign process. ///
always @ (ap_CS_fsm or exitcond_fu_876_p2 or ap_reg_ppiten_pp0_it0)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_fu_876_p2 == ap_const_lv1_0))) begin
ug2_p1_ce0 = ap_const_logic_1;
end else begin
ug2_p1_ce0 = ap_const_logic_0;
end
end
/// ug2_p2_ce0 assign process. ///
always @ (ap_CS_fsm or exitcond_fu_876_p2 or ap_reg_ppiten_pp0_it0)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_fu_876_p2 == ap_const_lv1_0))) begin
ug2_p2_ce0 = ap_const_logic_1;
end else begin
ug2_p2_ce0 = ap_const_logic_0;
end
end
/// ug2_p3_ce0 assign process. ///
always @ (ap_CS_fsm or exitcond_fu_876_p2 or ap_reg_ppiten_pp0_it0)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_fu_876_p2 == ap_const_lv1_0))) begin
ug2_p3_ce0 = ap_const_logic_1;
end else begin
ug2_p3_ce0 = ap_const_logic_0;
end
end
assign ap_return = Convergence_reg_673;
assign bothcond1_fu_1262_p2 = (grp_fu_826_p2 | grp_fu_831_p2);
assign bothcond2_fu_1287_p2 = (grp_fu_836_p2 | grp_fu_841_p2);
assign bothcond3_fu_1293_p2 = (grp_fu_846_p2 | grp_fu_851_p2);
assign bothcond_fu_1256_p2 = (grp_fu_816_p2 | grp_fu_821_p2);
assign exitcond_fu_876_p1 = ap_const_lv10_366;
assign exitcond_fu_876_p2 = (k_phi_fu_644_p4 == exitcond_fu_876_p1? 1'b1: 1'b0);
assign f_p0_address0 = g2_p3_addr107_cast_fu_916_p1;
assign f_p1_address0 = g2_p3_addr107_cast_fu_916_p1;
assign f_p2_address0 = g2_p3_addr107_cast_fu_916_p1;
assign f_p3_address0 = g2_p3_addr107_cast_fu_916_p1;
assign g0_p0_address0 = g2_p3_addr107_cast_fu_916_p1;
assign g0_p1_address0 = g2_p3_addr107_cast_fu_916_p1;
assign g0_p2_address0 = g2_p3_addr107_cast_fu_916_p1;
assign g0_p3_address0 = g2_p3_addr107_cast_fu_916_p1;
assign g1_p0_addr78_cast_fu_996_p1 = {{24{1'b0}}, {g1_p0_addr_fu_990_p2}};
assign g1_p0_addr_fu_990_p2 = (g2_p3_addr_cast_fu_904_p2 + tmp2_fu_984_p2);
assign g1_p0_address0 = g1_p3_addr95_cast_fu_972_p1;
assign g1_p0_address1 = g1_p0_addr78_cast_fu_996_p1;
assign g1_p1_address0 = g1_p3_addr95_cast_fu_972_p1;
assign g1_p2_address0 = g1_p3_addr95_cast_fu_972_p1;
assign g1_p3_addr1_fu_1008_p2 = (g2_p3_addr_cast_fu_904_p2 + tmp48_cast_fu_1002_p2);
assign g1_p3_addr91_cast_fu_1014_p1 = {{24{1'b0}}, {g1_p3_addr1_fu_1008_p2}};
assign g1_p3_addr94_cast_fu_960_p2 = (p_shl1_fu_954_p2 - tmp42_cast_fu_950_p1);
assign g1_p3_addr95_cast_fu_972_p1 = {{24{1'b0}}, {g1_p3_addr_fu_966_p2}};
assign g1_p3_addr_fu_966_p2 = (g1_p3_addr94_cast_fu_960_p2 + j_cast_fu_872_p1);
assign g1_p3_address0 = g1_p3_addr95_cast_fu_972_p1;
assign g1_p3_address1 = g1_p3_addr91_cast_fu_1014_p1;
assign g2_p0_address0 = g2_p3_addr107_cast_fu_916_p1;
assign g2_p1_address0 = g2_p3_addr107_cast_fu_916_p1;
assign g2_p2_address0 = g2_p3_addr107_cast_fu_916_p1;
assign g2_p3_addr107_cast_fu_916_p1 = {{24{1'b0}}, {g2_p3_addr_fu_910_p2}};
assign g2_p3_addr_cast_fu_904_p2 = (p_shl_fu_898_p2 - i_1_cast_fu_894_p1);
assign g2_p3_addr_fu_910_p2 = (g2_p3_addr_cast_fu_904_p2 + j_cast_fu_872_p1);
assign g2_p3_address0 = g2_p3_addr107_cast_fu_916_p1;
assign grp_computeResultOne_fu_697_f = f_p0_q0;
assign grp_computeResultOne_fu_697_g0 = g1_p0_q0;
assign grp_computeResultOne_fu_697_g1 = g1_p0_q0;
assign grp_computeResultOne_fu_697_g2 = g1_p3_q1;
assign grp_computeResultOne_fu_697_g3 = g1_p1_q0;
assign grp_computeResultOne_fu_697_g4 = g0_p0_q0;
assign grp_computeResultOne_fu_697_g5 = g2_p0_q0;
assign grp_computeResultOne_fu_697_u = u_p0_q0;
assign grp_computeResultOne_fu_697_ug0 = ug1_p0_q0;
assign grp_computeResultOne_fu_697_ug1 = ug1_p0_q0;
assign grp_computeResultOne_fu_697_ug2 = ug1_p3_q1;
assign grp_computeResultOne_fu_697_ug3 = ug1_p1_q0;
assign grp_computeResultOne_fu_697_ug4 = ug0_p0_q0;
assign grp_computeResultOne_fu_697_ug5 = ug2_p0_q0;
assign grp_computeResultOne_fu_730_f = f_p1_q0;
assign grp_computeResultOne_fu_730_g0 = g1_p1_q0;
assign grp_computeResultOne_fu_730_g1 = g1_p1_q0;
assign grp_computeResultOne_fu_730_g2 = g1_p0_q0;
assign grp_computeResultOne_fu_730_g3 = g1_p2_q0;
assign grp_computeResultOne_fu_730_g4 = g0_p1_q0;
assign grp_computeResultOne_fu_730_g5 = g2_p1_q0;
assign grp_computeResultOne_fu_730_u = u_p1_q0;
assign grp_computeResultOne_fu_730_ug0 = ug1_p1_q0;
assign grp_computeResultOne_fu_730_ug1 = ug1_p1_q0;
assign grp_computeResultOne_fu_730_ug2 = ug1_p0_q0;
assign grp_computeResultOne_fu_730_ug3 = ug1_p2_q0;
assign grp_computeResultOne_fu_730_ug4 = ug0_p1_q0;
assign grp_computeResultOne_fu_730_ug5 = ug2_p1_q0;
assign grp_computeResultOne_fu_763_f = f_p2_q0;
assign grp_computeResultOne_fu_763_g0 = g1_p2_q0;
assign grp_computeResultOne_fu_763_g1 = g1_p2_q0;
assign grp_computeResultOne_fu_763_g2 = g1_p1_q0;
assign grp_computeResultOne_fu_763_g3 = ((tmp_reg_1405)? g1_Local04_1_fu_128: g1_p3_q0);
assign grp_computeResultOne_fu_763_g4 = g0_p2_q0;
assign grp_computeResultOne_fu_763_g5 = g2_p2_q0;
assign grp_computeResultOne_fu_763_u = u_p2_q0;
assign grp_computeResultOne_fu_763_ug0 = ug1_p2_q0;
assign grp_computeResultOne_fu_763_ug1 = ug1_p2_q0;
assign grp_computeResultOne_fu_763_ug2 = ug1_p1_q0;
assign grp_computeResultOne_fu_763_ug3 = ((tmp_reg_1405)? ug1_Local04_1_fu_152: ug1_p3_q0);
assign grp_computeResultOne_fu_763_ug4 = ug0_p2_q0;
assign grp_computeResultOne_fu_763_ug5 = ug2_p2_q0;
assign grp_computeResultOne_fu_794_f = f_p3_q0;
assign grp_computeResultOne_fu_794_g0 = ((tmp_reg_1405)? g1_Localn13_1_fu_132: g1_p3_q0);
assign grp_computeResultOne_fu_794_g1 = ((tmp_reg_1405)? g1_Local13_1_fu_120: g1_p3_q0);
assign grp_computeResultOne_fu_794_g2 = g1_p2_q0;
assign grp_computeResultOne_fu_794_g3 = ((tmp_reg_1405)? g1_Local05_1_fu_124: g1_p0_q1);
assign grp_computeResultOne_fu_794_g4 = ((tmp_reg_1405)? g0_Local03_1_fu_116: g0_p3_q0);
assign grp_computeResultOne_fu_794_g5 = ((tmp_reg_1405)? g2_Local03_1_fu_112: g2_p3_q0);
assign grp_computeResultOne_fu_794_u = ((tmp_reg_1405)? u_Local03_1_fu_160: u_p3_q0);
assign grp_computeResultOne_fu_794_ug0 = ((tmp_reg_1405)? ug1_Localn13_1_fu_156: ug1_p3_q0);
assign grp_computeResultOne_fu_794_ug1 = ((tmp_reg_1405)? ug1_Local13_1_fu_144: ug1_p3_q0);
assign grp_computeResultOne_fu_794_ug2 = ug1_p2_q0;
assign grp_computeResultOne_fu_794_ug3 = ((tmp_reg_1405)? ug1_Local05_1_fu_148: ug1_p0_q1);
assign grp_computeResultOne_fu_794_ug4 = ((tmp_reg_1405)? ug0_Local03_1_fu_140: ug0_p3_q0);
assign grp_computeResultOne_fu_794_ug5 = ((tmp_reg_1405)? ug2_Local03_1_fu_136: ug2_p3_q0);
assign grp_fu_816_ce = ap_const_logic_1;
assign grp_fu_816_opcode = ap_const_lv5_B;
assign grp_fu_816_p0 = diff_reg_1664;
assign grp_fu_816_p1 = ap_const_lv32_3B03126F;
assign grp_fu_821_ce = ap_const_logic_1;
assign grp_fu_821_opcode = ap_const_lv5_D;
assign grp_fu_821_p0 = diff_reg_1664;
assign grp_fu_821_p1 = ap_const_lv32_BB03126F;
assign grp_fu_826_ce = ap_const_logic_1;
assign grp_fu_826_opcode = ap_const_lv5_B;
assign grp_fu_826_p0 = diff1_reg_1670;
assign grp_fu_826_p1 = ap_const_lv32_3B03126F;
assign grp_fu_831_ce = ap_const_logic_1;
assign grp_fu_831_opcode = ap_const_lv5_D;
assign grp_fu_831_p0 = diff1_reg_1670;
assign grp_fu_831_p1 = ap_const_lv32_BB03126F;
assign grp_fu_836_ce = ap_const_logic_1;
assign grp_fu_836_opcode = ap_const_lv5_B;
assign grp_fu_836_p0 = diff2_reg_1676;
assign grp_fu_836_p1 = ap_const_lv32_3B03126F;
assign grp_fu_841_ce = ap_const_logic_1;
assign grp_fu_841_opcode = ap_const_lv5_D;
assign grp_fu_841_p0 = diff2_reg_1676;
assign grp_fu_841_p1 = ap_const_lv32_BB03126F;
assign grp_fu_846_ce = ap_const_logic_1;
assign grp_fu_846_opcode = ap_const_lv5_B;
assign grp_fu_846_p0 = diff3_reg_1682;
assign grp_fu_846_p1 = ap_const_lv32_3B03126F;
assign grp_fu_851_ce = ap_const_logic_1;
assign grp_fu_851_opcode = ap_const_lv5_D;
assign grp_fu_851_p0 = diff3_reg_1682;
assign grp_fu_851_p1 = ap_const_lv32_BB03126F;
assign grp_fu_856_ce = ap_const_logic_1;
assign grp_fu_856_p0 = ap_reg_ppstg_u_p0_load_reg_1626_pp0_it70;
assign grp_fu_856_p1 = tmp3_reg_1644;
assign grp_fu_860_ce = ap_const_logic_1;
assign grp_fu_860_p0 = ap_reg_ppstg_u_p1_load_reg_1632_pp0_it70;
assign grp_fu_860_p1 = tmp6_reg_1649;
assign grp_fu_864_ce = ap_const_logic_1;
assign grp_fu_864_p0 = ap_reg_ppstg_u_p2_load_reg_1638_pp0_it70;
assign grp_fu_864_p1 = tmp11_reg_1654;
assign grp_fu_868_ce = ap_const_logic_1;
assign grp_fu_868_p0 = ap_reg_ppstg_u_Local_reg_1620_pp0_it70;
assign grp_fu_868_p1 = tmp14_reg_1659;
assign i_1_cast_fu_894_p1 = i_1_phi_fu_666_p4[7:0];
assign j_cast_fu_872_p1 = j_phi_fu_655_p4[7:0];
assign p_shl1_fu_954_p2 = tmp42_cast_fu_950_p1 << ap_const_lv8_4;
assign p_shl_fu_898_p2 = i_1_cast_fu_894_p1 << ap_const_lv8_4;
assign r_p0_address0 = ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it69;
assign r_p0_d0 = grp_computeResultOne_fu_697_ap_return;
assign r_p1_address0 = ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it69;
assign r_p1_d0 = grp_computeResultOne_fu_730_ap_return;
assign r_p2_address0 = ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it69;
assign r_p2_d0 = grp_computeResultOne_fu_763_ap_return;
assign r_p3_address0 = ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it69;
assign r_p3_d0 = grp_computeResultOne_fu_794_ap_return;
assign tmp10_fu_1280_p2 = (Convergence_reg_673 & tmp9_fu_1274_p2);
assign tmp17_fu_1305_p2 = (tmp71_demorgan_fu_1299_p2 ^ ap_const_lv1_1);
assign tmp18_fu_1311_p2 = (tmp10_fu_1280_p2 & tmp17_fu_1305_p2);
assign tmp19_fu_1020_p2 = (j_phi_fu_655_p4 + ap_const_lv32_4);
assign tmp1_fu_944_p2 = (i_1_phi_fu_666_p4 + ap_const_lv32_1);
assign tmp20_fu_1026_p1 = ap_const_lv32_3D;
assign tmp20_fu_1026_p2 = (tmp19_fu_1020_p2 == tmp20_fu_1026_p1? 1'b1: 1'b0);
assign tmp2_fu_984_p2 = (j_cast_fu_872_p1 + ap_const_lv8_1);
assign tmp42_cast_fu_950_p1 = tmp1_fu_944_p2[7:0];
assign tmp48_cast_fu_1002_p2 = (j_cast_fu_872_p1 + ap_const_lv8_FF);
assign tmp70_demorgan_fu_1268_p2 = (bothcond_fu_1256_p2 | bothcond1_fu_1262_p2);
assign tmp71_demorgan_fu_1299_p2 = (bothcond2_fu_1287_p2 | bothcond3_fu_1293_p2);
assign tmp9_fu_1274_p2 = (tmp70_demorgan_fu_1268_p2 ^ ap_const_lv1_1);
assign tmp_fu_888_p1 = ap_const_lv32_38;
assign tmp_fu_888_p2 = ($signed(j_phi_fu_655_p4) > $signed(tmp_fu_888_p1)? 1'b1: 1'b0);
assign u_p0_address0 = g2_p3_addr107_cast_fu_916_p1;
assign u_p1_address0 = g2_p3_addr107_cast_fu_916_p1;
assign u_p2_address0 = g2_p3_addr107_cast_fu_916_p1;
assign u_p3_address0 = g2_p3_addr107_cast_fu_916_p1;
assign ug0_p0_address0 = g2_p3_addr107_cast_fu_916_p1;
assign ug0_p1_address0 = g2_p3_addr107_cast_fu_916_p1;
assign ug0_p2_address0 = g2_p3_addr107_cast_fu_916_p1;
assign ug0_p3_address0 = g2_p3_addr107_cast_fu_916_p1;
assign ug1_p0_address0 = g1_p3_addr95_cast_fu_972_p1;
assign ug1_p0_address1 = g1_p0_addr78_cast_fu_996_p1;
assign ug1_p1_address0 = g1_p3_addr95_cast_fu_972_p1;
assign ug1_p2_address0 = g1_p3_addr95_cast_fu_972_p1;
assign ug1_p3_address0 = g1_p3_addr95_cast_fu_972_p1;
assign ug1_p3_address1 = g1_p3_addr91_cast_fu_1014_p1;
assign ug2_p0_address0 = g2_p3_addr107_cast_fu_916_p1;
assign ug2_p1_address0 = g2_p3_addr107_cast_fu_916_p1;
assign ug2_p2_address0 = g2_p3_addr107_cast_fu_916_p1;
assign ug2_p3_address0 = g2_p3_addr107_cast_fu_916_p1;
always @ (ap_clk)
begin
g2_p3_addr107_cast_reg_1422[8] <= 1'b0;
g2_p3_addr107_cast_reg_1422[9] <= 1'b0;
g2_p3_addr107_cast_reg_1422[10] <= 1'b0;
g2_p3_addr107_cast_reg_1422[11] <= 1'b0;
g2_p3_addr107_cast_reg_1422[12] <= 1'b0;
g2_p3_addr107_cast_reg_1422[13] <= 1'b0;
g2_p3_addr107_cast_reg_1422[14] <= 1'b0;
g2_p3_addr107_cast_reg_1422[15] <= 1'b0;
g2_p3_addr107_cast_reg_1422[16] <= 1'b0;
g2_p3_addr107_cast_reg_1422[17] <= 1'b0;
g2_p3_addr107_cast_reg_1422[18] <= 1'b0;
g2_p3_addr107_cast_reg_1422[19] <= 1'b0;
g2_p3_addr107_cast_reg_1422[20] <= 1'b0;
g2_p3_addr107_cast_reg_1422[21] <= 1'b0;
g2_p3_addr107_cast_reg_1422[22] <= 1'b0;
g2_p3_addr107_cast_reg_1422[23] <= 1'b0;
g2_p3_addr107_cast_reg_1422[24] <= 1'b0;
g2_p3_addr107_cast_reg_1422[25] <= 1'b0;
g2_p3_addr107_cast_reg_1422[26] <= 1'b0;
g2_p3_addr107_cast_reg_1422[27] <= 1'b0;
g2_p3_addr107_cast_reg_1422[28] <= 1'b0;
g2_p3_addr107_cast_reg_1422[29] <= 1'b0;
g2_p3_addr107_cast_reg_1422[30] <= 1'b0;
g2_p3_addr107_cast_reg_1422[31] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it1[8] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it1[9] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it1[10] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it1[11] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it1[12] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it1[13] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it1[14] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it1[15] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it1[16] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it1[17] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it1[18] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it1[19] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it1[20] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it1[21] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it1[22] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it1[23] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it1[24] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it1[25] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it1[26] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it1[27] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it1[28] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it1[29] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it1[30] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it1[31] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it2[8] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it2[9] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it2[10] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it2[11] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it2[12] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it2[13] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it2[14] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it2[15] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it2[16] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it2[17] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it2[18] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it2[19] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it2[20] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it2[21] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it2[22] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it2[23] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it2[24] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it2[25] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it2[26] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it2[27] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it2[28] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it2[29] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it2[30] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it2[31] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it3[8] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it3[9] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it3[10] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it3[11] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it3[12] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it3[13] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it3[14] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it3[15] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it3[16] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it3[17] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it3[18] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it3[19] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it3[20] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it3[21] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it3[22] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it3[23] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it3[24] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it3[25] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it3[26] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it3[27] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it3[28] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it3[29] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it3[30] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it3[31] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it4[8] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it4[9] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it4[10] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it4[11] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it4[12] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it4[13] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it4[14] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it4[15] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it4[16] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it4[17] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it4[18] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it4[19] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it4[20] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it4[21] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it4[22] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it4[23] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it4[24] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it4[25] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it4[26] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it4[27] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it4[28] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it4[29] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it4[30] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it4[31] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it5[8] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it5[9] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it5[10] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it5[11] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it5[12] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it5[13] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it5[14] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it5[15] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it5[16] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it5[17] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it5[18] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it5[19] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it5[20] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it5[21] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it5[22] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it5[23] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it5[24] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it5[25] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it5[26] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it5[27] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it5[28] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it5[29] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it5[30] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it5[31] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it6[8] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it6[9] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it6[10] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it6[11] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it6[12] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it6[13] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it6[14] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it6[15] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it6[16] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it6[17] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it6[18] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it6[19] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it6[20] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it6[21] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it6[22] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it6[23] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it6[24] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it6[25] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it6[26] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it6[27] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it6[28] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it6[29] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it6[30] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it6[31] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it7[8] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it7[9] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it7[10] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it7[11] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it7[12] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it7[13] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it7[14] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it7[15] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it7[16] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it7[17] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it7[18] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it7[19] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it7[20] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it7[21] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it7[22] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it7[23] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it7[24] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it7[25] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it7[26] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it7[27] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it7[28] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it7[29] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it7[30] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it7[31] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it8[8] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it8[9] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it8[10] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it8[11] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it8[12] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it8[13] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it8[14] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it8[15] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it8[16] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it8[17] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it8[18] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it8[19] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it8[20] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it8[21] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it8[22] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it8[23] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it8[24] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it8[25] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it8[26] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it8[27] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it8[28] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it8[29] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it8[30] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it8[31] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it9[8] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it9[9] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it9[10] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it9[11] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it9[12] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it9[13] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it9[14] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it9[15] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it9[16] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it9[17] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it9[18] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it9[19] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it9[20] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it9[21] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it9[22] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it9[23] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it9[24] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it9[25] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it9[26] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it9[27] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it9[28] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it9[29] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it9[30] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it9[31] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it10[8] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it10[9] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it10[10] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it10[11] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it10[12] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it10[13] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it10[14] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it10[15] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it10[16] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it10[17] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it10[18] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it10[19] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it10[20] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it10[21] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it10[22] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it10[23] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it10[24] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it10[25] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it10[26] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it10[27] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it10[28] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it10[29] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it10[30] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it10[31] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it11[8] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it11[9] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it11[10] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it11[11] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it11[12] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it11[13] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it11[14] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it11[15] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it11[16] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it11[17] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it11[18] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it11[19] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it11[20] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it11[21] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it11[22] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it11[23] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it11[24] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it11[25] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it11[26] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it11[27] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it11[28] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it11[29] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it11[30] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it11[31] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it12[8] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it12[9] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it12[10] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it12[11] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it12[12] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it12[13] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it12[14] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it12[15] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it12[16] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it12[17] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it12[18] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it12[19] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it12[20] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it12[21] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it12[22] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it12[23] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it12[24] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it12[25] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it12[26] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it12[27] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it12[28] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it12[29] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it12[30] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it12[31] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it13[8] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it13[9] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it13[10] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it13[11] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it13[12] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it13[13] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it13[14] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it13[15] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it13[16] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it13[17] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it13[18] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it13[19] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it13[20] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it13[21] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it13[22] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it13[23] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it13[24] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it13[25] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it13[26] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it13[27] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it13[28] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it13[29] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it13[30] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it13[31] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it14[8] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it14[9] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it14[10] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it14[11] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it14[12] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it14[13] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it14[14] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it14[15] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it14[16] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it14[17] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it14[18] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it14[19] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it14[20] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it14[21] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it14[22] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it14[23] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it14[24] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it14[25] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it14[26] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it14[27] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it14[28] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it14[29] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it14[30] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it14[31] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it15[8] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it15[9] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it15[10] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it15[11] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it15[12] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it15[13] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it15[14] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it15[15] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it15[16] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it15[17] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it15[18] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it15[19] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it15[20] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it15[21] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it15[22] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it15[23] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it15[24] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it15[25] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it15[26] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it15[27] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it15[28] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it15[29] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it15[30] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it15[31] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it16[8] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it16[9] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it16[10] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it16[11] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it16[12] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it16[13] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it16[14] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it16[15] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it16[16] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it16[17] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it16[18] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it16[19] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it16[20] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it16[21] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it16[22] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it16[23] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it16[24] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it16[25] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it16[26] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it16[27] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it16[28] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it16[29] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it16[30] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it16[31] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it17[8] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it17[9] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it17[10] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it17[11] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it17[12] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it17[13] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it17[14] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it17[15] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it17[16] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it17[17] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it17[18] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it17[19] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it17[20] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it17[21] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it17[22] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it17[23] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it17[24] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it17[25] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it17[26] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it17[27] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it17[28] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it17[29] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it17[30] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it17[31] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it18[8] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it18[9] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it18[10] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it18[11] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it18[12] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it18[13] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it18[14] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it18[15] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it18[16] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it18[17] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it18[18] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it18[19] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it18[20] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it18[21] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it18[22] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it18[23] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it18[24] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it18[25] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it18[26] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it18[27] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it18[28] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it18[29] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it18[30] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it18[31] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it19[8] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it19[9] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it19[10] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it19[11] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it19[12] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it19[13] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it19[14] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it19[15] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it19[16] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it19[17] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it19[18] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it19[19] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it19[20] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it19[21] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it19[22] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it19[23] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it19[24] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it19[25] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it19[26] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it19[27] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it19[28] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it19[29] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it19[30] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it19[31] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it20[8] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it20[9] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it20[10] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it20[11] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it20[12] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it20[13] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it20[14] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it20[15] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it20[16] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it20[17] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it20[18] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it20[19] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it20[20] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it20[21] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it20[22] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it20[23] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it20[24] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it20[25] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it20[26] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it20[27] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it20[28] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it20[29] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it20[30] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it20[31] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it21[8] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it21[9] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it21[10] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it21[11] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it21[12] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it21[13] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it21[14] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it21[15] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it21[16] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it21[17] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it21[18] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it21[19] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it21[20] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it21[21] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it21[22] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it21[23] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it21[24] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it21[25] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it21[26] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it21[27] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it21[28] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it21[29] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it21[30] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it21[31] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it22[8] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it22[9] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it22[10] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it22[11] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it22[12] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it22[13] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it22[14] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it22[15] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it22[16] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it22[17] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it22[18] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it22[19] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it22[20] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it22[21] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it22[22] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it22[23] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it22[24] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it22[25] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it22[26] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it22[27] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it22[28] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it22[29] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it22[30] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it22[31] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it23[8] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it23[9] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it23[10] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it23[11] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it23[12] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it23[13] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it23[14] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it23[15] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it23[16] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it23[17] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it23[18] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it23[19] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it23[20] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it23[21] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it23[22] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it23[23] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it23[24] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it23[25] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it23[26] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it23[27] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it23[28] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it23[29] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it23[30] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it23[31] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it24[8] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it24[9] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it24[10] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it24[11] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it24[12] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it24[13] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it24[14] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it24[15] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it24[16] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it24[17] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it24[18] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it24[19] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it24[20] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it24[21] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it24[22] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it24[23] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it24[24] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it24[25] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it24[26] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it24[27] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it24[28] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it24[29] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it24[30] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it24[31] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it25[8] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it25[9] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it25[10] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it25[11] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it25[12] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it25[13] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it25[14] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it25[15] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it25[16] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it25[17] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it25[18] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it25[19] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it25[20] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it25[21] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it25[22] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it25[23] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it25[24] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it25[25] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it25[26] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it25[27] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it25[28] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it25[29] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it25[30] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it25[31] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it26[8] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it26[9] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it26[10] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it26[11] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it26[12] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it26[13] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it26[14] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it26[15] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it26[16] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it26[17] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it26[18] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it26[19] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it26[20] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it26[21] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it26[22] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it26[23] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it26[24] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it26[25] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it26[26] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it26[27] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it26[28] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it26[29] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it26[30] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it26[31] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it27[8] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it27[9] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it27[10] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it27[11] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it27[12] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it27[13] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it27[14] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it27[15] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it27[16] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it27[17] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it27[18] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it27[19] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it27[20] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it27[21] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it27[22] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it27[23] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it27[24] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it27[25] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it27[26] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it27[27] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it27[28] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it27[29] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it27[30] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it27[31] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it28[8] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it28[9] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it28[10] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it28[11] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it28[12] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it28[13] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it28[14] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it28[15] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it28[16] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it28[17] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it28[18] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it28[19] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it28[20] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it28[21] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it28[22] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it28[23] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it28[24] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it28[25] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it28[26] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it28[27] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it28[28] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it28[29] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it28[30] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it28[31] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it29[8] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it29[9] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it29[10] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it29[11] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it29[12] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it29[13] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it29[14] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it29[15] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it29[16] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it29[17] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it29[18] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it29[19] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it29[20] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it29[21] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it29[22] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it29[23] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it29[24] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it29[25] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it29[26] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it29[27] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it29[28] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it29[29] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it29[30] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it29[31] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it30[8] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it30[9] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it30[10] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it30[11] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it30[12] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it30[13] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it30[14] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it30[15] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it30[16] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it30[17] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it30[18] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it30[19] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it30[20] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it30[21] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it30[22] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it30[23] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it30[24] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it30[25] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it30[26] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it30[27] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it30[28] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it30[29] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it30[30] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it30[31] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it31[8] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it31[9] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it31[10] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it31[11] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it31[12] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it31[13] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it31[14] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it31[15] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it31[16] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it31[17] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it31[18] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it31[19] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it31[20] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it31[21] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it31[22] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it31[23] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it31[24] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it31[25] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it31[26] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it31[27] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it31[28] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it31[29] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it31[30] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it31[31] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it32[8] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it32[9] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it32[10] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it32[11] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it32[12] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it32[13] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it32[14] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it32[15] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it32[16] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it32[17] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it32[18] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it32[19] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it32[20] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it32[21] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it32[22] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it32[23] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it32[24] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it32[25] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it32[26] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it32[27] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it32[28] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it32[29] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it32[30] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it32[31] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it33[8] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it33[9] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it33[10] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it33[11] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it33[12] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it33[13] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it33[14] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it33[15] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it33[16] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it33[17] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it33[18] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it33[19] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it33[20] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it33[21] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it33[22] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it33[23] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it33[24] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it33[25] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it33[26] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it33[27] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it33[28] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it33[29] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it33[30] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it33[31] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it34[8] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it34[9] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it34[10] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it34[11] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it34[12] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it34[13] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it34[14] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it34[15] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it34[16] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it34[17] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it34[18] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it34[19] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it34[20] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it34[21] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it34[22] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it34[23] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it34[24] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it34[25] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it34[26] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it34[27] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it34[28] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it34[29] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it34[30] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it34[31] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it35[8] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it35[9] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it35[10] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it35[11] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it35[12] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it35[13] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it35[14] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it35[15] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it35[16] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it35[17] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it35[18] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it35[19] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it35[20] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it35[21] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it35[22] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it35[23] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it35[24] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it35[25] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it35[26] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it35[27] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it35[28] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it35[29] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it35[30] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it35[31] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it36[8] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it36[9] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it36[10] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it36[11] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it36[12] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it36[13] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it36[14] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it36[15] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it36[16] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it36[17] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it36[18] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it36[19] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it36[20] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it36[21] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it36[22] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it36[23] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it36[24] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it36[25] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it36[26] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it36[27] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it36[28] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it36[29] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it36[30] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it36[31] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it37[8] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it37[9] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it37[10] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it37[11] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it37[12] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it37[13] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it37[14] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it37[15] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it37[16] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it37[17] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it37[18] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it37[19] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it37[20] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it37[21] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it37[22] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it37[23] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it37[24] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it37[25] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it37[26] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it37[27] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it37[28] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it37[29] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it37[30] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it37[31] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it38[8] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it38[9] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it38[10] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it38[11] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it38[12] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it38[13] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it38[14] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it38[15] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it38[16] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it38[17] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it38[18] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it38[19] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it38[20] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it38[21] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it38[22] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it38[23] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it38[24] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it38[25] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it38[26] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it38[27] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it38[28] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it38[29] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it38[30] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it38[31] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it39[8] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it39[9] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it39[10] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it39[11] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it39[12] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it39[13] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it39[14] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it39[15] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it39[16] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it39[17] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it39[18] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it39[19] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it39[20] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it39[21] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it39[22] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it39[23] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it39[24] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it39[25] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it39[26] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it39[27] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it39[28] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it39[29] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it39[30] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it39[31] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it40[8] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it40[9] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it40[10] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it40[11] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it40[12] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it40[13] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it40[14] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it40[15] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it40[16] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it40[17] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it40[18] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it40[19] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it40[20] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it40[21] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it40[22] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it40[23] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it40[24] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it40[25] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it40[26] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it40[27] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it40[28] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it40[29] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it40[30] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it40[31] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it41[8] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it41[9] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it41[10] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it41[11] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it41[12] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it41[13] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it41[14] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it41[15] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it41[16] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it41[17] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it41[18] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it41[19] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it41[20] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it41[21] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it41[22] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it41[23] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it41[24] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it41[25] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it41[26] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it41[27] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it41[28] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it41[29] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it41[30] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it41[31] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it42[8] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it42[9] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it42[10] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it42[11] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it42[12] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it42[13] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it42[14] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it42[15] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it42[16] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it42[17] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it42[18] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it42[19] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it42[20] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it42[21] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it42[22] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it42[23] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it42[24] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it42[25] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it42[26] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it42[27] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it42[28] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it42[29] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it42[30] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it42[31] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it43[8] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it43[9] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it43[10] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it43[11] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it43[12] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it43[13] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it43[14] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it43[15] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it43[16] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it43[17] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it43[18] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it43[19] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it43[20] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it43[21] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it43[22] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it43[23] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it43[24] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it43[25] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it43[26] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it43[27] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it43[28] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it43[29] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it43[30] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it43[31] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it44[8] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it44[9] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it44[10] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it44[11] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it44[12] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it44[13] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it44[14] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it44[15] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it44[16] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it44[17] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it44[18] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it44[19] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it44[20] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it44[21] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it44[22] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it44[23] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it44[24] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it44[25] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it44[26] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it44[27] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it44[28] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it44[29] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it44[30] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it44[31] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it45[8] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it45[9] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it45[10] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it45[11] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it45[12] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it45[13] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it45[14] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it45[15] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it45[16] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it45[17] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it45[18] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it45[19] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it45[20] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it45[21] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it45[22] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it45[23] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it45[24] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it45[25] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it45[26] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it45[27] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it45[28] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it45[29] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it45[30] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it45[31] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it46[8] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it46[9] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it46[10] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it46[11] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it46[12] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it46[13] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it46[14] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it46[15] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it46[16] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it46[17] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it46[18] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it46[19] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it46[20] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it46[21] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it46[22] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it46[23] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it46[24] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it46[25] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it46[26] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it46[27] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it46[28] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it46[29] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it46[30] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it46[31] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it47[8] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it47[9] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it47[10] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it47[11] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it47[12] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it47[13] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it47[14] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it47[15] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it47[16] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it47[17] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it47[18] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it47[19] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it47[20] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it47[21] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it47[22] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it47[23] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it47[24] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it47[25] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it47[26] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it47[27] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it47[28] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it47[29] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it47[30] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it47[31] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it48[8] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it48[9] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it48[10] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it48[11] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it48[12] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it48[13] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it48[14] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it48[15] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it48[16] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it48[17] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it48[18] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it48[19] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it48[20] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it48[21] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it48[22] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it48[23] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it48[24] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it48[25] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it48[26] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it48[27] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it48[28] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it48[29] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it48[30] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it48[31] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it49[8] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it49[9] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it49[10] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it49[11] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it49[12] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it49[13] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it49[14] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it49[15] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it49[16] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it49[17] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it49[18] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it49[19] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it49[20] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it49[21] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it49[22] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it49[23] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it49[24] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it49[25] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it49[26] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it49[27] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it49[28] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it49[29] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it49[30] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it49[31] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it50[8] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it50[9] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it50[10] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it50[11] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it50[12] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it50[13] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it50[14] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it50[15] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it50[16] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it50[17] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it50[18] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it50[19] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it50[20] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it50[21] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it50[22] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it50[23] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it50[24] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it50[25] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it50[26] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it50[27] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it50[28] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it50[29] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it50[30] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it50[31] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it51[8] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it51[9] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it51[10] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it51[11] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it51[12] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it51[13] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it51[14] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it51[15] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it51[16] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it51[17] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it51[18] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it51[19] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it51[20] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it51[21] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it51[22] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it51[23] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it51[24] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it51[25] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it51[26] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it51[27] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it51[28] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it51[29] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it51[30] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it51[31] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it52[8] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it52[9] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it52[10] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it52[11] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it52[12] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it52[13] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it52[14] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it52[15] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it52[16] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it52[17] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it52[18] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it52[19] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it52[20] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it52[21] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it52[22] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it52[23] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it52[24] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it52[25] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it52[26] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it52[27] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it52[28] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it52[29] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it52[30] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it52[31] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it53[8] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it53[9] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it53[10] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it53[11] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it53[12] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it53[13] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it53[14] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it53[15] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it53[16] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it53[17] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it53[18] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it53[19] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it53[20] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it53[21] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it53[22] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it53[23] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it53[24] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it53[25] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it53[26] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it53[27] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it53[28] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it53[29] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it53[30] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it53[31] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it54[8] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it54[9] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it54[10] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it54[11] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it54[12] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it54[13] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it54[14] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it54[15] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it54[16] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it54[17] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it54[18] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it54[19] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it54[20] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it54[21] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it54[22] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it54[23] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it54[24] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it54[25] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it54[26] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it54[27] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it54[28] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it54[29] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it54[30] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it54[31] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it55[8] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it55[9] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it55[10] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it55[11] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it55[12] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it55[13] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it55[14] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it55[15] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it55[16] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it55[17] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it55[18] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it55[19] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it55[20] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it55[21] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it55[22] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it55[23] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it55[24] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it55[25] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it55[26] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it55[27] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it55[28] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it55[29] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it55[30] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it55[31] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it56[8] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it56[9] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it56[10] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it56[11] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it56[12] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it56[13] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it56[14] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it56[15] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it56[16] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it56[17] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it56[18] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it56[19] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it56[20] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it56[21] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it56[22] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it56[23] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it56[24] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it56[25] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it56[26] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it56[27] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it56[28] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it56[29] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it56[30] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it56[31] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it57[8] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it57[9] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it57[10] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it57[11] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it57[12] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it57[13] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it57[14] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it57[15] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it57[16] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it57[17] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it57[18] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it57[19] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it57[20] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it57[21] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it57[22] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it57[23] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it57[24] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it57[25] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it57[26] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it57[27] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it57[28] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it57[29] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it57[30] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it57[31] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it58[8] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it58[9] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it58[10] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it58[11] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it58[12] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it58[13] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it58[14] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it58[15] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it58[16] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it58[17] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it58[18] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it58[19] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it58[20] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it58[21] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it58[22] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it58[23] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it58[24] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it58[25] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it58[26] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it58[27] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it58[28] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it58[29] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it58[30] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it58[31] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it59[8] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it59[9] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it59[10] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it59[11] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it59[12] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it59[13] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it59[14] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it59[15] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it59[16] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it59[17] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it59[18] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it59[19] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it59[20] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it59[21] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it59[22] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it59[23] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it59[24] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it59[25] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it59[26] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it59[27] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it59[28] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it59[29] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it59[30] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it59[31] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it60[8] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it60[9] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it60[10] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it60[11] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it60[12] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it60[13] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it60[14] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it60[15] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it60[16] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it60[17] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it60[18] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it60[19] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it60[20] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it60[21] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it60[22] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it60[23] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it60[24] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it60[25] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it60[26] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it60[27] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it60[28] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it60[29] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it60[30] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it60[31] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it61[8] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it61[9] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it61[10] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it61[11] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it61[12] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it61[13] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it61[14] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it61[15] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it61[16] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it61[17] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it61[18] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it61[19] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it61[20] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it61[21] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it61[22] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it61[23] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it61[24] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it61[25] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it61[26] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it61[27] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it61[28] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it61[29] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it61[30] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it61[31] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it62[8] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it62[9] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it62[10] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it62[11] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it62[12] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it62[13] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it62[14] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it62[15] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it62[16] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it62[17] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it62[18] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it62[19] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it62[20] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it62[21] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it62[22] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it62[23] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it62[24] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it62[25] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it62[26] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it62[27] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it62[28] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it62[29] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it62[30] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it62[31] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it63[8] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it63[9] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it63[10] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it63[11] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it63[12] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it63[13] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it63[14] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it63[15] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it63[16] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it63[17] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it63[18] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it63[19] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it63[20] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it63[21] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it63[22] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it63[23] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it63[24] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it63[25] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it63[26] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it63[27] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it63[28] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it63[29] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it63[30] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it63[31] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it64[8] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it64[9] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it64[10] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it64[11] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it64[12] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it64[13] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it64[14] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it64[15] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it64[16] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it64[17] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it64[18] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it64[19] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it64[20] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it64[21] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it64[22] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it64[23] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it64[24] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it64[25] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it64[26] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it64[27] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it64[28] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it64[29] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it64[30] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it64[31] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it65[8] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it65[9] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it65[10] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it65[11] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it65[12] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it65[13] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it65[14] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it65[15] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it65[16] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it65[17] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it65[18] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it65[19] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it65[20] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it65[21] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it65[22] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it65[23] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it65[24] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it65[25] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it65[26] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it65[27] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it65[28] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it65[29] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it65[30] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it65[31] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it66[8] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it66[9] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it66[10] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it66[11] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it66[12] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it66[13] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it66[14] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it66[15] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it66[16] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it66[17] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it66[18] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it66[19] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it66[20] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it66[21] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it66[22] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it66[23] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it66[24] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it66[25] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it66[26] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it66[27] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it66[28] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it66[29] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it66[30] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it66[31] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it67[8] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it67[9] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it67[10] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it67[11] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it67[12] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it67[13] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it67[14] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it67[15] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it67[16] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it67[17] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it67[18] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it67[19] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it67[20] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it67[21] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it67[22] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it67[23] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it67[24] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it67[25] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it67[26] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it67[27] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it67[28] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it67[29] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it67[30] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it67[31] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it68[8] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it68[9] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it68[10] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it68[11] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it68[12] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it68[13] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it68[14] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it68[15] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it68[16] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it68[17] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it68[18] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it68[19] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it68[20] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it68[21] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it68[22] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it68[23] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it68[24] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it68[25] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it68[26] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it68[27] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it68[28] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it68[29] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it68[30] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it68[31] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it69[8] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it69[9] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it69[10] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it69[11] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it69[12] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it69[13] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it69[14] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it69[15] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it69[16] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it69[17] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it69[18] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it69[19] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it69[20] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it69[21] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it69[22] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it69[23] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it69[24] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it69[25] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it69[26] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it69[27] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it69[28] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it69[29] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it69[30] <= 1'b0;
ap_reg_ppstg_g2_p3_addr107_cast_reg_1422_pp0_it69[31] <= 1'b0;
end
endmodule //computeResult
|
// ==============================================================
// RTL generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ===========================================================
`timescale 1 ns / 1 ps
module computeResultOne (
ap_clk,
ap_rst,
u,
ug0,
ug1,
ug2,
ug3,
ug4,
ug5,
g0,
g1,
g2,
g3,
g4,
g5,
f,
ap_return,
ap_ce
);
input ap_clk;
input ap_rst;
input [31:0] u;
input [31:0] ug0;
input [31:0] ug1;
input [31:0] ug2;
input [31:0] ug3;
input [31:0] ug4;
input [31:0] ug5;
input [31:0] g0;
input [31:0] g1;
input [31:0] g2;
input [31:0] g3;
input [31:0] g4;
input [31:0] g5;
input [31:0] f;
output [31:0] ap_return;
input ap_ce;
reg [31:0] f_read_reg_270;
reg [31:0] ap_reg_ppstg_f_read_reg_270_pp0_it1;
reg [31:0] ap_reg_ppstg_f_read_reg_270_pp0_it2;
reg [31:0] ap_reg_ppstg_f_read_reg_270_pp0_it3;
reg [31:0] ap_reg_ppstg_f_read_reg_270_pp0_it4;
reg [31:0] ap_reg_ppstg_f_read_reg_270_pp0_it5;
reg [31:0] ap_reg_ppstg_f_read_reg_270_pp0_it6;
reg [31:0] ap_reg_ppstg_f_read_reg_270_pp0_it7;
reg [31:0] ap_reg_ppstg_f_read_reg_270_pp0_it8;
reg [31:0] ap_reg_ppstg_f_read_reg_270_pp0_it9;
reg [31:0] ap_reg_ppstg_f_read_reg_270_pp0_it10;
reg [31:0] ap_reg_ppstg_f_read_reg_270_pp0_it11;
reg [31:0] ap_reg_ppstg_f_read_reg_270_pp0_it12;
reg [31:0] ap_reg_ppstg_f_read_reg_270_pp0_it13;
reg [31:0] ap_reg_ppstg_f_read_reg_270_pp0_it14;
reg [31:0] ap_reg_ppstg_f_read_reg_270_pp0_it15;
reg [31:0] ap_reg_ppstg_f_read_reg_270_pp0_it16;
reg [31:0] ap_reg_ppstg_f_read_reg_270_pp0_it17;
reg [31:0] ap_reg_ppstg_f_read_reg_270_pp0_it18;
reg [31:0] ap_reg_ppstg_f_read_reg_270_pp0_it19;
reg [31:0] ap_reg_ppstg_f_read_reg_270_pp0_it20;
reg [31:0] ap_reg_ppstg_f_read_reg_270_pp0_it21;
reg [31:0] ap_reg_ppstg_f_read_reg_270_pp0_it22;
reg [31:0] ap_reg_ppstg_f_read_reg_270_pp0_it23;
reg [31:0] ap_reg_ppstg_f_read_reg_270_pp0_it24;
reg [31:0] ap_reg_ppstg_f_read_reg_270_pp0_it25;
reg [31:0] ap_reg_ppstg_f_read_reg_270_pp0_it26;
reg [31:0] ap_reg_ppstg_f_read_reg_270_pp0_it27;
reg [31:0] ap_reg_ppstg_f_read_reg_270_pp0_it28;
reg [31:0] ap_reg_ppstg_f_read_reg_270_pp0_it29;
reg [31:0] ap_reg_ppstg_f_read_reg_270_pp0_it30;
reg [31:0] ap_reg_ppstg_f_read_reg_270_pp0_it31;
reg [31:0] ap_reg_ppstg_f_read_reg_270_pp0_it32;
reg [31:0] ap_reg_ppstg_f_read_reg_270_pp0_it33;
reg [31:0] ap_reg_ppstg_f_read_reg_270_pp0_it34;
reg [31:0] ap_reg_ppstg_f_read_reg_270_pp0_it35;
reg [31:0] ap_reg_ppstg_f_read_reg_270_pp0_it36;
reg [31:0] ap_reg_ppstg_f_read_reg_270_pp0_it37;
reg [31:0] ap_reg_ppstg_f_read_reg_270_pp0_it38;
reg [31:0] ap_reg_ppstg_f_read_reg_270_pp0_it39;
reg [31:0] g5_read_reg_276;
reg [31:0] ap_reg_ppstg_g5_read_reg_276_pp0_it1;
reg [31:0] ap_reg_ppstg_g5_read_reg_276_pp0_it2;
reg [31:0] ap_reg_ppstg_g5_read_reg_276_pp0_it3;
reg [31:0] ap_reg_ppstg_g5_read_reg_276_pp0_it4;
reg [31:0] ap_reg_ppstg_g5_read_reg_276_pp0_it5;
reg [31:0] ap_reg_ppstg_g5_read_reg_276_pp0_it6;
reg [31:0] ap_reg_ppstg_g5_read_reg_276_pp0_it7;
reg [31:0] ap_reg_ppstg_g5_read_reg_276_pp0_it8;
reg [31:0] ap_reg_ppstg_g5_read_reg_276_pp0_it9;
reg [31:0] ap_reg_ppstg_g5_read_reg_276_pp0_it10;
reg [31:0] ap_reg_ppstg_g5_read_reg_276_pp0_it11;
reg [31:0] ap_reg_ppstg_g5_read_reg_276_pp0_it12;
reg [31:0] ap_reg_ppstg_g5_read_reg_276_pp0_it13;
reg [31:0] ap_reg_ppstg_g5_read_reg_276_pp0_it14;
reg [31:0] ap_reg_ppstg_g5_read_reg_276_pp0_it15;
reg [31:0] ap_reg_ppstg_g5_read_reg_276_pp0_it16;
reg [31:0] g4_read_reg_281;
reg [31:0] ap_reg_ppstg_g4_read_reg_281_pp0_it1;
reg [31:0] ap_reg_ppstg_g4_read_reg_281_pp0_it2;
reg [31:0] ap_reg_ppstg_g4_read_reg_281_pp0_it3;
reg [31:0] ap_reg_ppstg_g4_read_reg_281_pp0_it4;
reg [31:0] ap_reg_ppstg_g4_read_reg_281_pp0_it5;
reg [31:0] ap_reg_ppstg_g4_read_reg_281_pp0_it6;
reg [31:0] ap_reg_ppstg_g4_read_reg_281_pp0_it7;
reg [31:0] ap_reg_ppstg_g4_read_reg_281_pp0_it8;
reg [31:0] ap_reg_ppstg_g4_read_reg_281_pp0_it9;
reg [31:0] ap_reg_ppstg_g4_read_reg_281_pp0_it10;
reg [31:0] ap_reg_ppstg_g4_read_reg_281_pp0_it11;
reg [31:0] ap_reg_ppstg_g4_read_reg_281_pp0_it12;
reg [31:0] g3_read_reg_286;
reg [31:0] ap_reg_ppstg_g3_read_reg_286_pp0_it1;
reg [31:0] ap_reg_ppstg_g3_read_reg_286_pp0_it2;
reg [31:0] ap_reg_ppstg_g3_read_reg_286_pp0_it3;
reg [31:0] ap_reg_ppstg_g3_read_reg_286_pp0_it4;
reg [31:0] ap_reg_ppstg_g3_read_reg_286_pp0_it5;
reg [31:0] ap_reg_ppstg_g3_read_reg_286_pp0_it6;
reg [31:0] ap_reg_ppstg_g3_read_reg_286_pp0_it7;
reg [31:0] ap_reg_ppstg_g3_read_reg_286_pp0_it8;
reg [31:0] g2_read_reg_291;
reg [31:0] ap_reg_ppstg_g2_read_reg_291_pp0_it1;
reg [31:0] ap_reg_ppstg_g2_read_reg_291_pp0_it2;
reg [31:0] ap_reg_ppstg_g2_read_reg_291_pp0_it3;
reg [31:0] ap_reg_ppstg_g2_read_reg_291_pp0_it4;
reg [31:0] g1_read_reg_296;
reg [31:0] g0_read_reg_301;
reg [31:0] ug5_read_reg_306;
reg [31:0] ap_reg_ppstg_ug5_read_reg_306_pp0_it1;
reg [31:0] ap_reg_ppstg_ug5_read_reg_306_pp0_it2;
reg [31:0] ap_reg_ppstg_ug5_read_reg_306_pp0_it3;
reg [31:0] ap_reg_ppstg_ug5_read_reg_306_pp0_it4;
reg [31:0] ap_reg_ppstg_ug5_read_reg_306_pp0_it5;
reg [31:0] ap_reg_ppstg_ug5_read_reg_306_pp0_it6;
reg [31:0] ap_reg_ppstg_ug5_read_reg_306_pp0_it7;
reg [31:0] ap_reg_ppstg_ug5_read_reg_306_pp0_it8;
reg [31:0] ap_reg_ppstg_ug5_read_reg_306_pp0_it9;
reg [31:0] ap_reg_ppstg_ug5_read_reg_306_pp0_it10;
reg [31:0] ap_reg_ppstg_ug5_read_reg_306_pp0_it11;
reg [31:0] ap_reg_ppstg_ug5_read_reg_306_pp0_it12;
reg [31:0] ap_reg_ppstg_ug5_read_reg_306_pp0_it13;
reg [31:0] ap_reg_ppstg_ug5_read_reg_306_pp0_it14;
reg [31:0] ap_reg_ppstg_ug5_read_reg_306_pp0_it15;
reg [31:0] ap_reg_ppstg_ug5_read_reg_306_pp0_it16;
reg [31:0] ug4_read_reg_311;
reg [31:0] ap_reg_ppstg_ug4_read_reg_311_pp0_it1;
reg [31:0] ap_reg_ppstg_ug4_read_reg_311_pp0_it2;
reg [31:0] ap_reg_ppstg_ug4_read_reg_311_pp0_it3;
reg [31:0] ap_reg_ppstg_ug4_read_reg_311_pp0_it4;
reg [31:0] ap_reg_ppstg_ug4_read_reg_311_pp0_it5;
reg [31:0] ap_reg_ppstg_ug4_read_reg_311_pp0_it6;
reg [31:0] ap_reg_ppstg_ug4_read_reg_311_pp0_it7;
reg [31:0] ap_reg_ppstg_ug4_read_reg_311_pp0_it8;
reg [31:0] ap_reg_ppstg_ug4_read_reg_311_pp0_it9;
reg [31:0] ap_reg_ppstg_ug4_read_reg_311_pp0_it10;
reg [31:0] ap_reg_ppstg_ug4_read_reg_311_pp0_it11;
reg [31:0] ap_reg_ppstg_ug4_read_reg_311_pp0_it12;
reg [31:0] ug3_read_reg_316;
reg [31:0] ap_reg_ppstg_ug3_read_reg_316_pp0_it1;
reg [31:0] ap_reg_ppstg_ug3_read_reg_316_pp0_it2;
reg [31:0] ap_reg_ppstg_ug3_read_reg_316_pp0_it3;
reg [31:0] ap_reg_ppstg_ug3_read_reg_316_pp0_it4;
reg [31:0] ap_reg_ppstg_ug3_read_reg_316_pp0_it5;
reg [31:0] ap_reg_ppstg_ug3_read_reg_316_pp0_it6;
reg [31:0] ap_reg_ppstg_ug3_read_reg_316_pp0_it7;
reg [31:0] ap_reg_ppstg_ug3_read_reg_316_pp0_it8;
reg [31:0] ug2_read_reg_321;
reg [31:0] ap_reg_ppstg_ug2_read_reg_321_pp0_it1;
reg [31:0] ap_reg_ppstg_ug2_read_reg_321_pp0_it2;
reg [31:0] ap_reg_ppstg_ug2_read_reg_321_pp0_it3;
reg [31:0] ap_reg_ppstg_ug2_read_reg_321_pp0_it4;
reg [31:0] ug1_read_reg_326;
reg [31:0] ug0_read_reg_331;
reg [31:0] u_read_reg_336;
reg [31:0] ap_reg_ppstg_u_read_reg_336_pp0_it1;
reg [31:0] ap_reg_ppstg_u_read_reg_336_pp0_it2;
reg [31:0] ap_reg_ppstg_u_read_reg_336_pp0_it3;
reg [31:0] ap_reg_ppstg_u_read_reg_336_pp0_it4;
reg [31:0] ap_reg_ppstg_u_read_reg_336_pp0_it5;
reg [31:0] ap_reg_ppstg_u_read_reg_336_pp0_it6;
reg [31:0] ap_reg_ppstg_u_read_reg_336_pp0_it7;
reg [31:0] ap_reg_ppstg_u_read_reg_336_pp0_it8;
reg [31:0] ap_reg_ppstg_u_read_reg_336_pp0_it9;
reg [31:0] ap_reg_ppstg_u_read_reg_336_pp0_it10;
reg [31:0] ap_reg_ppstg_u_read_reg_336_pp0_it11;
reg [31:0] ap_reg_ppstg_u_read_reg_336_pp0_it12;
reg [31:0] ap_reg_ppstg_u_read_reg_336_pp0_it13;
reg [31:0] ap_reg_ppstg_u_read_reg_336_pp0_it14;
reg [31:0] ap_reg_ppstg_u_read_reg_336_pp0_it15;
reg [31:0] ap_reg_ppstg_u_read_reg_336_pp0_it16;
reg [31:0] ap_reg_ppstg_u_read_reg_336_pp0_it17;
reg [31:0] ap_reg_ppstg_u_read_reg_336_pp0_it18;
reg [31:0] ap_reg_ppstg_u_read_reg_336_pp0_it19;
reg [31:0] ap_reg_ppstg_u_read_reg_336_pp0_it20;
reg [31:0] ap_reg_ppstg_u_read_reg_336_pp0_it21;
reg [31:0] ap_reg_ppstg_u_read_reg_336_pp0_it22;
reg [31:0] ap_reg_ppstg_u_read_reg_336_pp0_it23;
reg [31:0] ap_reg_ppstg_u_read_reg_336_pp0_it24;
reg [31:0] ap_reg_ppstg_u_read_reg_336_pp0_it25;
reg [31:0] ap_reg_ppstg_u_read_reg_336_pp0_it26;
reg [31:0] ap_reg_ppstg_u_read_reg_336_pp0_it27;
reg [31:0] ap_reg_ppstg_u_read_reg_336_pp0_it28;
reg [31:0] ap_reg_ppstg_u_read_reg_336_pp0_it29;
reg [31:0] ap_reg_ppstg_u_read_reg_336_pp0_it30;
reg [31:0] ap_reg_ppstg_u_read_reg_336_pp0_it31;
reg [31:0] ap_reg_ppstg_u_read_reg_336_pp0_it32;
reg [31:0] ap_reg_ppstg_u_read_reg_336_pp0_it33;
reg [31:0] ap_reg_ppstg_u_read_reg_336_pp0_it34;
reg [31:0] ap_reg_ppstg_u_read_reg_336_pp0_it35;
reg [31:0] ap_reg_ppstg_u_read_reg_336_pp0_it36;
reg [31:0] ap_reg_ppstg_u_read_reg_336_pp0_it37;
reg [31:0] ap_reg_ppstg_u_read_reg_336_pp0_it38;
reg [31:0] ap_reg_ppstg_u_read_reg_336_pp0_it39;
reg [31:0] ap_reg_ppstg_u_read_reg_336_pp0_it40;
reg [31:0] ap_reg_ppstg_u_read_reg_336_pp0_it41;
reg [31:0] ap_reg_ppstg_u_read_reg_336_pp0_it42;
reg [31:0] ap_reg_ppstg_u_read_reg_336_pp0_it43;
reg [31:0] ap_reg_ppstg_u_read_reg_336_pp0_it44;
reg [31:0] ap_reg_ppstg_u_read_reg_336_pp0_it45;
reg [31:0] ap_reg_ppstg_u_read_reg_336_pp0_it46;
reg [31:0] ap_reg_ppstg_u_read_reg_336_pp0_it47;
reg [31:0] ap_reg_ppstg_u_read_reg_336_pp0_it48;
reg [31:0] ap_reg_ppstg_u_read_reg_336_pp0_it49;
reg [31:0] ap_reg_ppstg_u_read_reg_336_pp0_it50;
reg [31:0] ap_reg_ppstg_u_read_reg_336_pp0_it51;
reg [31:0] ap_reg_ppstg_u_read_reg_336_pp0_it52;
reg [31:0] ap_reg_ppstg_u_read_reg_336_pp0_it53;
reg [31:0] ap_reg_ppstg_u_read_reg_336_pp0_it54;
reg [31:0] ap_reg_ppstg_u_read_reg_336_pp0_it55;
wire [31:0] grp_fu_229_p2;
reg [31:0] tmp_reg_342;
wire [31:0] grp_fu_146_p2;
reg [31:0] tmp10_reg_347;
wire [31:0] grp_fu_150_p2;
reg [31:0] tmp20_reg_352;
wire [31:0] grp_fu_154_p2;
reg [31:0] tmp11_reg_357;
wire [31:0] grp_fu_158_p2;
reg [31:0] tmp21_reg_362;
wire [31:0] grp_fu_162_p2;
reg [31:0] tmp12_reg_367;
wire [31:0] grp_fu_166_p2;
reg [31:0] tmp22_reg_372;
wire [31:0] grp_fu_133_p2;
reg [31:0] r_reg_377;
reg [31:0] ap_reg_ppstg_r_reg_377_pp0_it14;
reg [31:0] ap_reg_ppstg_r_reg_377_pp0_it15;
reg [31:0] ap_reg_ppstg_r_reg_377_pp0_it16;
reg [31:0] ap_reg_ppstg_r_reg_377_pp0_it17;
reg [31:0] ap_reg_ppstg_r_reg_377_pp0_it18;
reg [31:0] ap_reg_ppstg_r_reg_377_pp0_it19;
reg [31:0] ap_reg_ppstg_r_reg_377_pp0_it20;
reg [31:0] ap_reg_ppstg_r_reg_377_pp0_it21;
reg [31:0] ap_reg_ppstg_r_reg_377_pp0_it22;
reg [31:0] ap_reg_ppstg_r_reg_377_pp0_it23;
reg [31:0] ap_reg_ppstg_r_reg_377_pp0_it24;
reg [31:0] ap_reg_ppstg_r_reg_377_pp0_it25;
reg [31:0] ap_reg_ppstg_r_reg_377_pp0_it26;
reg [31:0] ap_reg_ppstg_r_reg_377_pp0_it27;
reg [31:0] ap_reg_ppstg_r_reg_377_pp0_it28;
reg [31:0] ap_reg_ppstg_r_reg_377_pp0_it29;
wire [31:0] grp_fu_170_p2;
reg [31:0] tmp13_reg_387;
wire [31:0] grp_fu_174_p2;
reg [31:0] tmp23_reg_392;
wire [31:0] grp_fu_178_p2;
reg [31:0] tmp5_reg_397;
wire [31:0] grp_fu_183_p2;
reg [31:0] tmp14_reg_402;
reg [31:0] ap_reg_ppstg_tmp14_reg_402_pp0_it21;
reg [31:0] ap_reg_ppstg_tmp14_reg_402_pp0_it22;
reg [31:0] ap_reg_ppstg_tmp14_reg_402_pp0_it23;
reg [31:0] ap_reg_ppstg_tmp14_reg_402_pp0_it24;
reg [31:0] ap_reg_ppstg_tmp14_reg_402_pp0_it25;
reg [31:0] ap_reg_ppstg_tmp14_reg_402_pp0_it26;
reg [31:0] ap_reg_ppstg_tmp14_reg_402_pp0_it27;
reg [31:0] ap_reg_ppstg_tmp14_reg_402_pp0_it28;
reg [31:0] ap_reg_ppstg_tmp14_reg_402_pp0_it29;
reg [31:0] ap_reg_ppstg_tmp14_reg_402_pp0_it30;
reg [31:0] ap_reg_ppstg_tmp14_reg_402_pp0_it31;
reg [31:0] ap_reg_ppstg_tmp14_reg_402_pp0_it32;
reg [31:0] ap_reg_ppstg_tmp14_reg_402_pp0_it33;
reg [31:0] ap_reg_ppstg_tmp14_reg_402_pp0_it34;
reg [31:0] ap_reg_ppstg_tmp14_reg_402_pp0_it35;
reg [31:0] ap_reg_ppstg_tmp14_reg_402_pp0_it36;
reg [31:0] ap_reg_ppstg_tmp14_reg_402_pp0_it37;
reg [31:0] ap_reg_ppstg_tmp14_reg_402_pp0_it38;
reg [31:0] ap_reg_ppstg_tmp14_reg_402_pp0_it39;
reg [31:0] ap_reg_ppstg_tmp14_reg_402_pp0_it40;
reg [31:0] ap_reg_ppstg_tmp14_reg_402_pp0_it41;
reg [31:0] ap_reg_ppstg_tmp14_reg_402_pp0_it42;
reg [31:0] ap_reg_ppstg_tmp14_reg_402_pp0_it43;
reg [31:0] ap_reg_ppstg_tmp14_reg_402_pp0_it44;
reg [31:0] ap_reg_ppstg_tmp14_reg_402_pp0_it45;
reg [31:0] ap_reg_ppstg_tmp14_reg_402_pp0_it46;
reg [31:0] ap_reg_ppstg_tmp14_reg_402_pp0_it47;
wire [31:0] grp_fu_187_p2;
reg [31:0] tmp24_reg_407;
reg [31:0] ap_reg_ppstg_tmp24_reg_407_pp0_it21;
reg [31:0] ap_reg_ppstg_tmp24_reg_407_pp0_it22;
reg [31:0] ap_reg_ppstg_tmp24_reg_407_pp0_it23;
reg [31:0] ap_reg_ppstg_tmp24_reg_407_pp0_it24;
reg [31:0] ap_reg_ppstg_tmp24_reg_407_pp0_it25;
reg [31:0] ap_reg_ppstg_tmp24_reg_407_pp0_it26;
reg [31:0] ap_reg_ppstg_tmp24_reg_407_pp0_it27;
reg [31:0] ap_reg_ppstg_tmp24_reg_407_pp0_it28;
reg [31:0] ap_reg_ppstg_tmp24_reg_407_pp0_it29;
reg [31:0] ap_reg_ppstg_tmp24_reg_407_pp0_it30;
reg [31:0] ap_reg_ppstg_tmp24_reg_407_pp0_it31;
reg [31:0] ap_reg_ppstg_tmp24_reg_407_pp0_it32;
reg [31:0] ap_reg_ppstg_tmp24_reg_407_pp0_it33;
reg [31:0] ap_reg_ppstg_tmp24_reg_407_pp0_it34;
reg [31:0] ap_reg_ppstg_tmp24_reg_407_pp0_it35;
reg [31:0] ap_reg_ppstg_tmp24_reg_407_pp0_it36;
reg [31:0] ap_reg_ppstg_tmp24_reg_407_pp0_it37;
reg [31:0] ap_reg_ppstg_tmp24_reg_407_pp0_it38;
reg [31:0] ap_reg_ppstg_tmp24_reg_407_pp0_it39;
reg [31:0] ap_reg_ppstg_tmp24_reg_407_pp0_it40;
reg [31:0] ap_reg_ppstg_tmp24_reg_407_pp0_it41;
reg [31:0] ap_reg_ppstg_tmp24_reg_407_pp0_it42;
reg [31:0] ap_reg_ppstg_tmp24_reg_407_pp0_it43;
reg [31:0] ap_reg_ppstg_tmp24_reg_407_pp0_it44;
reg [31:0] ap_reg_ppstg_tmp24_reg_407_pp0_it45;
reg [31:0] ap_reg_ppstg_tmp24_reg_407_pp0_it46;
reg [31:0] ap_reg_ppstg_tmp24_reg_407_pp0_it47;
wire [31:0] grp_fu_191_p2;
reg [31:0] tmp1_reg_412;
wire [31:0] grp_fu_235_p2;
reg [31:0] tmp6_reg_417;
wire [31:0] grp_fu_239_p2;
reg [31:0] tmp2_reg_422;
wire [31:0] grp_fu_196_p2;
reg [31:0] tmp7_reg_427;
wire [31:0] grp_fu_201_p2;
reg [31:0] tmp3_reg_432;
wire [31:0] grp_fu_243_p2;
reg [31:0] tmp8_reg_437;
wire [31:0] grp_fu_247_p2;
reg [31:0] tmp4_reg_442;
wire [31:0] grp_fu_206_p2;
reg [31:0] tmp9_reg_447;
wire [31:0] grp_fu_138_p2;
reg [31:0] r1_reg_452;
wire [31:0] grp_fu_251_p2;
reg [31:0] tmp15_reg_457;
wire [31:0] grp_fu_256_p2;
reg [31:0] tmp16_reg_462;
wire [31:0] grp_fu_211_p2;
reg [31:0] tmp17_reg_467;
wire [31:0] grp_fu_215_p2;
reg [31:0] tmp25_reg_472;
wire [31:0] grp_fu_260_p2;
reg [31:0] tmp18_reg_477;
wire [31:0] grp_fu_265_p2;
reg [31:0] tmp26_reg_482;
wire [31:0] grp_fu_220_p2;
reg [31:0] tmp19_reg_487;
wire [31:0] grp_fu_224_p2;
reg [31:0] tmp27_reg_492;
wire [31:0] grp_fu_133_p0;
wire [31:0] grp_fu_133_p1;
wire [31:0] grp_fu_138_p0;
wire [31:0] grp_fu_138_p1;
wire [31:0] grp_fu_142_p0;
wire [31:0] grp_fu_142_p1;
wire [31:0] grp_fu_146_p0;
wire [31:0] grp_fu_146_p1;
wire [31:0] grp_fu_150_p0;
wire [31:0] grp_fu_150_p1;
wire [31:0] grp_fu_154_p0;
wire [31:0] grp_fu_154_p1;
wire [31:0] grp_fu_158_p0;
wire [31:0] grp_fu_158_p1;
wire [31:0] grp_fu_162_p0;
wire [31:0] grp_fu_162_p1;
wire [31:0] grp_fu_166_p0;
wire [31:0] grp_fu_166_p1;
wire [31:0] grp_fu_170_p0;
wire [31:0] grp_fu_170_p1;
wire [31:0] grp_fu_174_p0;
wire [31:0] grp_fu_174_p1;
wire [31:0] grp_fu_178_p0;
wire [31:0] grp_fu_178_p1;
wire [31:0] grp_fu_183_p0;
wire [31:0] grp_fu_183_p1;
wire [31:0] grp_fu_187_p0;
wire [31:0] grp_fu_187_p1;
wire [31:0] grp_fu_191_p0;
wire [31:0] grp_fu_191_p1;
wire [31:0] grp_fu_196_p0;
wire [31:0] grp_fu_196_p1;
wire [31:0] grp_fu_201_p0;
wire [31:0] grp_fu_201_p1;
wire [31:0] grp_fu_206_p0;
wire [31:0] grp_fu_206_p1;
wire [31:0] grp_fu_211_p0;
wire [31:0] grp_fu_211_p1;
wire [31:0] grp_fu_215_p0;
wire [31:0] grp_fu_215_p1;
wire [31:0] grp_fu_220_p0;
wire [31:0] grp_fu_220_p1;
wire [31:0] grp_fu_224_p0;
wire [31:0] grp_fu_224_p1;
wire [31:0] grp_fu_229_p0;
wire [31:0] grp_fu_229_p1;
wire [31:0] grp_fu_235_p0;
wire [31:0] grp_fu_235_p1;
wire [31:0] grp_fu_239_p0;
wire [31:0] grp_fu_239_p1;
wire [31:0] grp_fu_243_p0;
wire [31:0] grp_fu_243_p1;
wire [31:0] grp_fu_247_p0;
wire [31:0] grp_fu_247_p1;
wire [31:0] grp_fu_251_p0;
wire [31:0] grp_fu_251_p1;
wire [31:0] grp_fu_256_p0;
wire [31:0] grp_fu_256_p1;
wire [31:0] grp_fu_260_p0;
wire [31:0] grp_fu_260_p1;
wire [31:0] grp_fu_265_p0;
wire [31:0] grp_fu_265_p1;
reg grp_fu_133_ce;
reg grp_fu_138_ce;
wire [31:0] grp_fu_142_p2;
reg grp_fu_142_ce;
reg grp_fu_146_ce;
reg grp_fu_150_ce;
reg grp_fu_154_ce;
reg grp_fu_158_ce;
reg grp_fu_162_ce;
reg grp_fu_166_ce;
reg grp_fu_170_ce;
reg grp_fu_174_ce;
reg grp_fu_178_ce;
reg grp_fu_183_ce;
reg grp_fu_187_ce;
reg grp_fu_191_ce;
reg grp_fu_196_ce;
reg grp_fu_201_ce;
reg grp_fu_206_ce;
reg grp_fu_211_ce;
reg grp_fu_215_ce;
reg grp_fu_220_ce;
reg grp_fu_224_ce;
reg grp_fu_229_ce;
reg grp_fu_235_ce;
reg grp_fu_239_ce;
reg grp_fu_243_ce;
reg grp_fu_247_ce;
reg grp_fu_251_ce;
reg grp_fu_256_ce;
reg grp_fu_260_ce;
reg grp_fu_265_ce;
parameter ap_const_logic_1 = 1'b1;
parameter ap_const_logic_0 = 1'b0;
parameter ap_const_lv32_3E64F766 = 32'b00111110011001001111011101100110;
parameter ap_const_lv32_3FBEA3AD = 32'b00111111101111101010001110101101;
parameter ap_const_lv32_3F7335A0 = 32'b00111111011100110011010110100000;
parameter ap_const_lv32_4024D384 = 32'b01000000001001001101001110000100;
parameter ap_const_lv32_4018EC96 = 32'b01000000000110001110110010010110;
parameter ap_const_lv32_4094E686 = 32'b01000000100101001110011010000110;
parameter ap_const_lv32_3E94D6A1 = 32'b00111110100101001101011010100001;
parameter ap_const_lv32_3F800000 = 32'b00111111100000000000000000000000;
parameter ap_const_lv32_40A00000 = 32'b01000000101000000000000000000000;
parameter ap_true = 1'b1;
computeResultOne_grp_fu_133_ACMP_fdiv_111 #(
.ID( 111 ),
.NUM_STAGE( 10 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
computeResultOne_grp_fu_133_ACMP_fdiv_111_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_133_p0 ),
.din1( grp_fu_133_p1 ),
.ce( grp_fu_133_ce ),
.dout( grp_fu_133_p2 )
);
computeResultOne_grp_fu_138_ACMP_fdiv_112 #(
.ID( 112 ),
.NUM_STAGE( 10 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
computeResultOne_grp_fu_138_ACMP_fdiv_112_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_138_p0 ),
.din1( grp_fu_138_p1 ),
.ce( grp_fu_138_ce ),
.dout( grp_fu_138_p2 )
);
computeResultOne_grp_fu_142_ACMP_fdiv_113 #(
.ID( 113 ),
.NUM_STAGE( 10 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
computeResultOne_grp_fu_142_ACMP_fdiv_113_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_142_p0 ),
.din1( grp_fu_142_p1 ),
.ce( grp_fu_142_ce ),
.dout( grp_fu_142_p2 )
);
computeResultOne_grp_fu_146_ACMP_fadd_114 #(
.ID( 114 ),
.NUM_STAGE( 4 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
computeResultOne_grp_fu_146_ACMP_fadd_114_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_146_p0 ),
.din1( grp_fu_146_p1 ),
.ce( grp_fu_146_ce ),
.dout( grp_fu_146_p2 )
);
computeResultOne_grp_fu_150_ACMP_fadd_115 #(
.ID( 115 ),
.NUM_STAGE( 4 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
computeResultOne_grp_fu_150_ACMP_fadd_115_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_150_p0 ),
.din1( grp_fu_150_p1 ),
.ce( grp_fu_150_ce ),
.dout( grp_fu_150_p2 )
);
computeResultOne_grp_fu_154_ACMP_fadd_116 #(
.ID( 116 ),
.NUM_STAGE( 4 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
computeResultOne_grp_fu_154_ACMP_fadd_116_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_154_p0 ),
.din1( grp_fu_154_p1 ),
.ce( grp_fu_154_ce ),
.dout( grp_fu_154_p2 )
);
computeResultOne_grp_fu_158_ACMP_fadd_117 #(
.ID( 117 ),
.NUM_STAGE( 4 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
computeResultOne_grp_fu_158_ACMP_fadd_117_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_158_p0 ),
.din1( grp_fu_158_p1 ),
.ce( grp_fu_158_ce ),
.dout( grp_fu_158_p2 )
);
computeResultOne_grp_fu_162_ACMP_fadd_118 #(
.ID( 118 ),
.NUM_STAGE( 4 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
computeResultOne_grp_fu_162_ACMP_fadd_118_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_162_p0 ),
.din1( grp_fu_162_p1 ),
.ce( grp_fu_162_ce ),
.dout( grp_fu_162_p2 )
);
computeResultOne_grp_fu_166_ACMP_fadd_119 #(
.ID( 119 ),
.NUM_STAGE( 4 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
computeResultOne_grp_fu_166_ACMP_fadd_119_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_166_p0 ),
.din1( grp_fu_166_p1 ),
.ce( grp_fu_166_ce ),
.dout( grp_fu_166_p2 )
);
computeResultOne_grp_fu_170_ACMP_fadd_120 #(
.ID( 120 ),
.NUM_STAGE( 4 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
computeResultOne_grp_fu_170_ACMP_fadd_120_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_170_p0 ),
.din1( grp_fu_170_p1 ),
.ce( grp_fu_170_ce ),
.dout( grp_fu_170_p2 )
);
computeResultOne_grp_fu_174_ACMP_fadd_121 #(
.ID( 121 ),
.NUM_STAGE( 4 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
computeResultOne_grp_fu_174_ACMP_fadd_121_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_174_p0 ),
.din1( grp_fu_174_p1 ),
.ce( grp_fu_174_ce ),
.dout( grp_fu_174_p2 )
);
computeResultOne_grp_fu_178_ACMP_fadd_122 #(
.ID( 122 ),
.NUM_STAGE( 4 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
computeResultOne_grp_fu_178_ACMP_fadd_122_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_178_p0 ),
.din1( grp_fu_178_p1 ),
.ce( grp_fu_178_ce ),
.dout( grp_fu_178_p2 )
);
computeResultOne_grp_fu_183_ACMP_fadd_123 #(
.ID( 123 ),
.NUM_STAGE( 4 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
computeResultOne_grp_fu_183_ACMP_fadd_123_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_183_p0 ),
.din1( grp_fu_183_p1 ),
.ce( grp_fu_183_ce ),
.dout( grp_fu_183_p2 )
);
computeResultOne_grp_fu_187_ACMP_fadd_124 #(
.ID( 124 ),
.NUM_STAGE( 4 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
computeResultOne_grp_fu_187_ACMP_fadd_124_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_187_p0 ),
.din1( grp_fu_187_p1 ),
.ce( grp_fu_187_ce ),
.dout( grp_fu_187_p2 )
);
computeResultOne_grp_fu_191_ACMP_fadd_125 #(
.ID( 125 ),
.NUM_STAGE( 4 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
computeResultOne_grp_fu_191_ACMP_fadd_125_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_191_p0 ),
.din1( grp_fu_191_p1 ),
.ce( grp_fu_191_ce ),
.dout( grp_fu_191_p2 )
);
computeResultOne_grp_fu_196_ACMP_fadd_126 #(
.ID( 126 ),
.NUM_STAGE( 4 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
computeResultOne_grp_fu_196_ACMP_fadd_126_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_196_p0 ),
.din1( grp_fu_196_p1 ),
.ce( grp_fu_196_ce ),
.dout( grp_fu_196_p2 )
);
computeResultOne_grp_fu_201_ACMP_fadd_127 #(
.ID( 127 ),
.NUM_STAGE( 4 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
computeResultOne_grp_fu_201_ACMP_fadd_127_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_201_p0 ),
.din1( grp_fu_201_p1 ),
.ce( grp_fu_201_ce ),
.dout( grp_fu_201_p2 )
);
computeResultOne_grp_fu_206_ACMP_fadd_128 #(
.ID( 128 ),
.NUM_STAGE( 4 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
computeResultOne_grp_fu_206_ACMP_fadd_128_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_206_p0 ),
.din1( grp_fu_206_p1 ),
.ce( grp_fu_206_ce ),
.dout( grp_fu_206_p2 )
);
computeResultOne_grp_fu_211_ACMP_fadd_129 #(
.ID( 129 ),
.NUM_STAGE( 4 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
computeResultOne_grp_fu_211_ACMP_fadd_129_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_211_p0 ),
.din1( grp_fu_211_p1 ),
.ce( grp_fu_211_ce ),
.dout( grp_fu_211_p2 )
);
computeResultOne_grp_fu_215_ACMP_fadd_130 #(
.ID( 130 ),
.NUM_STAGE( 4 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
computeResultOne_grp_fu_215_ACMP_fadd_130_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_215_p0 ),
.din1( grp_fu_215_p1 ),
.ce( grp_fu_215_ce ),
.dout( grp_fu_215_p2 )
);
computeResultOne_grp_fu_220_ACMP_fadd_131 #(
.ID( 131 ),
.NUM_STAGE( 4 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
computeResultOne_grp_fu_220_ACMP_fadd_131_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_220_p0 ),
.din1( grp_fu_220_p1 ),
.ce( grp_fu_220_ce ),
.dout( grp_fu_220_p2 )
);
computeResultOne_grp_fu_224_ACMP_fadd_132 #(
.ID( 132 ),
.NUM_STAGE( 4 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
computeResultOne_grp_fu_224_ACMP_fadd_132_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_224_p0 ),
.din1( grp_fu_224_p1 ),
.ce( grp_fu_224_ce ),
.dout( grp_fu_224_p2 )
);
computeResultOne_grp_fu_229_ACMP_fmul_133 #(
.ID( 133 ),
.NUM_STAGE( 4 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
computeResultOne_grp_fu_229_ACMP_fmul_133_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_229_p0 ),
.din1( grp_fu_229_p1 ),
.ce( grp_fu_229_ce ),
.dout( grp_fu_229_p2 )
);
computeResultOne_grp_fu_235_ACMP_fmul_134 #(
.ID( 134 ),
.NUM_STAGE( 4 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
computeResultOne_grp_fu_235_ACMP_fmul_134_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_235_p0 ),
.din1( grp_fu_235_p1 ),
.ce( grp_fu_235_ce ),
.dout( grp_fu_235_p2 )
);
computeResultOne_grp_fu_239_ACMP_fmul_135 #(
.ID( 135 ),
.NUM_STAGE( 4 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
computeResultOne_grp_fu_239_ACMP_fmul_135_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_239_p0 ),
.din1( grp_fu_239_p1 ),
.ce( grp_fu_239_ce ),
.dout( grp_fu_239_p2 )
);
computeResultOne_grp_fu_243_ACMP_fmul_136 #(
.ID( 136 ),
.NUM_STAGE( 4 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
computeResultOne_grp_fu_243_ACMP_fmul_136_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_243_p0 ),
.din1( grp_fu_243_p1 ),
.ce( grp_fu_243_ce ),
.dout( grp_fu_243_p2 )
);
computeResultOne_grp_fu_247_ACMP_fmul_137 #(
.ID( 137 ),
.NUM_STAGE( 4 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
computeResultOne_grp_fu_247_ACMP_fmul_137_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_247_p0 ),
.din1( grp_fu_247_p1 ),
.ce( grp_fu_247_ce ),
.dout( grp_fu_247_p2 )
);
computeResultOne_grp_fu_251_ACMP_fmul_138 #(
.ID( 138 ),
.NUM_STAGE( 4 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
computeResultOne_grp_fu_251_ACMP_fmul_138_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_251_p0 ),
.din1( grp_fu_251_p1 ),
.ce( grp_fu_251_ce ),
.dout( grp_fu_251_p2 )
);
computeResultOne_grp_fu_256_ACMP_fmul_139 #(
.ID( 139 ),
.NUM_STAGE( 4 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
computeResultOne_grp_fu_256_ACMP_fmul_139_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_256_p0 ),
.din1( grp_fu_256_p1 ),
.ce( grp_fu_256_ce ),
.dout( grp_fu_256_p2 )
);
computeResultOne_grp_fu_260_ACMP_fmul_140 #(
.ID( 140 ),
.NUM_STAGE( 4 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
computeResultOne_grp_fu_260_ACMP_fmul_140_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_260_p0 ),
.din1( grp_fu_260_p1 ),
.ce( grp_fu_260_ce ),
.dout( grp_fu_260_p2 )
);
computeResultOne_grp_fu_265_ACMP_fmul_141 #(
.ID( 141 ),
.NUM_STAGE( 4 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
computeResultOne_grp_fu_265_ACMP_fmul_141_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_265_p0 ),
.din1( grp_fu_265_p1 ),
.ce( grp_fu_265_ce ),
.dout( grp_fu_265_p2 )
);
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_f_read_reg_270_pp0_it1 <= f_read_reg_270;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_f_read_reg_270_pp0_it10 <= ap_reg_ppstg_f_read_reg_270_pp0_it9;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_f_read_reg_270_pp0_it11 <= ap_reg_ppstg_f_read_reg_270_pp0_it10;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_f_read_reg_270_pp0_it12 <= ap_reg_ppstg_f_read_reg_270_pp0_it11;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_f_read_reg_270_pp0_it13 <= ap_reg_ppstg_f_read_reg_270_pp0_it12;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_f_read_reg_270_pp0_it14 <= ap_reg_ppstg_f_read_reg_270_pp0_it13;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_f_read_reg_270_pp0_it15 <= ap_reg_ppstg_f_read_reg_270_pp0_it14;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_f_read_reg_270_pp0_it16 <= ap_reg_ppstg_f_read_reg_270_pp0_it15;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_f_read_reg_270_pp0_it17 <= ap_reg_ppstg_f_read_reg_270_pp0_it16;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_f_read_reg_270_pp0_it18 <= ap_reg_ppstg_f_read_reg_270_pp0_it17;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_f_read_reg_270_pp0_it19 <= ap_reg_ppstg_f_read_reg_270_pp0_it18;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_f_read_reg_270_pp0_it2 <= ap_reg_ppstg_f_read_reg_270_pp0_it1;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_f_read_reg_270_pp0_it20 <= ap_reg_ppstg_f_read_reg_270_pp0_it19;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_f_read_reg_270_pp0_it21 <= ap_reg_ppstg_f_read_reg_270_pp0_it20;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_f_read_reg_270_pp0_it22 <= ap_reg_ppstg_f_read_reg_270_pp0_it21;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_f_read_reg_270_pp0_it23 <= ap_reg_ppstg_f_read_reg_270_pp0_it22;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_f_read_reg_270_pp0_it24 <= ap_reg_ppstg_f_read_reg_270_pp0_it23;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_f_read_reg_270_pp0_it25 <= ap_reg_ppstg_f_read_reg_270_pp0_it24;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_f_read_reg_270_pp0_it26 <= ap_reg_ppstg_f_read_reg_270_pp0_it25;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_f_read_reg_270_pp0_it27 <= ap_reg_ppstg_f_read_reg_270_pp0_it26;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_f_read_reg_270_pp0_it28 <= ap_reg_ppstg_f_read_reg_270_pp0_it27;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_f_read_reg_270_pp0_it29 <= ap_reg_ppstg_f_read_reg_270_pp0_it28;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_f_read_reg_270_pp0_it3 <= ap_reg_ppstg_f_read_reg_270_pp0_it2;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_f_read_reg_270_pp0_it30 <= ap_reg_ppstg_f_read_reg_270_pp0_it29;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_f_read_reg_270_pp0_it31 <= ap_reg_ppstg_f_read_reg_270_pp0_it30;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_f_read_reg_270_pp0_it32 <= ap_reg_ppstg_f_read_reg_270_pp0_it31;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_f_read_reg_270_pp0_it33 <= ap_reg_ppstg_f_read_reg_270_pp0_it32;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_f_read_reg_270_pp0_it34 <= ap_reg_ppstg_f_read_reg_270_pp0_it33;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_f_read_reg_270_pp0_it35 <= ap_reg_ppstg_f_read_reg_270_pp0_it34;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_f_read_reg_270_pp0_it36 <= ap_reg_ppstg_f_read_reg_270_pp0_it35;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_f_read_reg_270_pp0_it37 <= ap_reg_ppstg_f_read_reg_270_pp0_it36;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_f_read_reg_270_pp0_it38 <= ap_reg_ppstg_f_read_reg_270_pp0_it37;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_f_read_reg_270_pp0_it39 <= ap_reg_ppstg_f_read_reg_270_pp0_it38;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_f_read_reg_270_pp0_it4 <= ap_reg_ppstg_f_read_reg_270_pp0_it3;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_f_read_reg_270_pp0_it5 <= ap_reg_ppstg_f_read_reg_270_pp0_it4;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_f_read_reg_270_pp0_it6 <= ap_reg_ppstg_f_read_reg_270_pp0_it5;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_f_read_reg_270_pp0_it7 <= ap_reg_ppstg_f_read_reg_270_pp0_it6;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_f_read_reg_270_pp0_it8 <= ap_reg_ppstg_f_read_reg_270_pp0_it7;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_f_read_reg_270_pp0_it9 <= ap_reg_ppstg_f_read_reg_270_pp0_it8;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_g2_read_reg_291_pp0_it1 <= g2_read_reg_291;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_g2_read_reg_291_pp0_it2 <= ap_reg_ppstg_g2_read_reg_291_pp0_it1;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_g2_read_reg_291_pp0_it3 <= ap_reg_ppstg_g2_read_reg_291_pp0_it2;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_g2_read_reg_291_pp0_it4 <= ap_reg_ppstg_g2_read_reg_291_pp0_it3;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_g3_read_reg_286_pp0_it1 <= g3_read_reg_286;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_g3_read_reg_286_pp0_it2 <= ap_reg_ppstg_g3_read_reg_286_pp0_it1;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_g3_read_reg_286_pp0_it3 <= ap_reg_ppstg_g3_read_reg_286_pp0_it2;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_g3_read_reg_286_pp0_it4 <= ap_reg_ppstg_g3_read_reg_286_pp0_it3;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_g3_read_reg_286_pp0_it5 <= ap_reg_ppstg_g3_read_reg_286_pp0_it4;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_g3_read_reg_286_pp0_it6 <= ap_reg_ppstg_g3_read_reg_286_pp0_it5;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_g3_read_reg_286_pp0_it7 <= ap_reg_ppstg_g3_read_reg_286_pp0_it6;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_g3_read_reg_286_pp0_it8 <= ap_reg_ppstg_g3_read_reg_286_pp0_it7;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_g4_read_reg_281_pp0_it1 <= g4_read_reg_281;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_g4_read_reg_281_pp0_it10 <= ap_reg_ppstg_g4_read_reg_281_pp0_it9;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_g4_read_reg_281_pp0_it11 <= ap_reg_ppstg_g4_read_reg_281_pp0_it10;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_g4_read_reg_281_pp0_it12 <= ap_reg_ppstg_g4_read_reg_281_pp0_it11;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_g4_read_reg_281_pp0_it2 <= ap_reg_ppstg_g4_read_reg_281_pp0_it1;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_g4_read_reg_281_pp0_it3 <= ap_reg_ppstg_g4_read_reg_281_pp0_it2;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_g4_read_reg_281_pp0_it4 <= ap_reg_ppstg_g4_read_reg_281_pp0_it3;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_g4_read_reg_281_pp0_it5 <= ap_reg_ppstg_g4_read_reg_281_pp0_it4;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_g4_read_reg_281_pp0_it6 <= ap_reg_ppstg_g4_read_reg_281_pp0_it5;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_g4_read_reg_281_pp0_it7 <= ap_reg_ppstg_g4_read_reg_281_pp0_it6;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_g4_read_reg_281_pp0_it8 <= ap_reg_ppstg_g4_read_reg_281_pp0_it7;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_g4_read_reg_281_pp0_it9 <= ap_reg_ppstg_g4_read_reg_281_pp0_it8;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_g5_read_reg_276_pp0_it1 <= g5_read_reg_276;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_g5_read_reg_276_pp0_it10 <= ap_reg_ppstg_g5_read_reg_276_pp0_it9;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_g5_read_reg_276_pp0_it11 <= ap_reg_ppstg_g5_read_reg_276_pp0_it10;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_g5_read_reg_276_pp0_it12 <= ap_reg_ppstg_g5_read_reg_276_pp0_it11;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_g5_read_reg_276_pp0_it13 <= ap_reg_ppstg_g5_read_reg_276_pp0_it12;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_g5_read_reg_276_pp0_it14 <= ap_reg_ppstg_g5_read_reg_276_pp0_it13;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_g5_read_reg_276_pp0_it15 <= ap_reg_ppstg_g5_read_reg_276_pp0_it14;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_g5_read_reg_276_pp0_it16 <= ap_reg_ppstg_g5_read_reg_276_pp0_it15;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_g5_read_reg_276_pp0_it2 <= ap_reg_ppstg_g5_read_reg_276_pp0_it1;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_g5_read_reg_276_pp0_it3 <= ap_reg_ppstg_g5_read_reg_276_pp0_it2;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_g5_read_reg_276_pp0_it4 <= ap_reg_ppstg_g5_read_reg_276_pp0_it3;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_g5_read_reg_276_pp0_it5 <= ap_reg_ppstg_g5_read_reg_276_pp0_it4;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_g5_read_reg_276_pp0_it6 <= ap_reg_ppstg_g5_read_reg_276_pp0_it5;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_g5_read_reg_276_pp0_it7 <= ap_reg_ppstg_g5_read_reg_276_pp0_it6;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_g5_read_reg_276_pp0_it8 <= ap_reg_ppstg_g5_read_reg_276_pp0_it7;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_g5_read_reg_276_pp0_it9 <= ap_reg_ppstg_g5_read_reg_276_pp0_it8;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_r_reg_377_pp0_it14 <= r_reg_377;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_r_reg_377_pp0_it15 <= ap_reg_ppstg_r_reg_377_pp0_it14;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_r_reg_377_pp0_it16 <= ap_reg_ppstg_r_reg_377_pp0_it15;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_r_reg_377_pp0_it17 <= ap_reg_ppstg_r_reg_377_pp0_it16;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_r_reg_377_pp0_it18 <= ap_reg_ppstg_r_reg_377_pp0_it17;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_r_reg_377_pp0_it19 <= ap_reg_ppstg_r_reg_377_pp0_it18;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_r_reg_377_pp0_it20 <= ap_reg_ppstg_r_reg_377_pp0_it19;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_r_reg_377_pp0_it21 <= ap_reg_ppstg_r_reg_377_pp0_it20;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_r_reg_377_pp0_it22 <= ap_reg_ppstg_r_reg_377_pp0_it21;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_r_reg_377_pp0_it23 <= ap_reg_ppstg_r_reg_377_pp0_it22;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_r_reg_377_pp0_it24 <= ap_reg_ppstg_r_reg_377_pp0_it23;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_r_reg_377_pp0_it25 <= ap_reg_ppstg_r_reg_377_pp0_it24;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_r_reg_377_pp0_it26 <= ap_reg_ppstg_r_reg_377_pp0_it25;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_r_reg_377_pp0_it27 <= ap_reg_ppstg_r_reg_377_pp0_it26;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_r_reg_377_pp0_it28 <= ap_reg_ppstg_r_reg_377_pp0_it27;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_r_reg_377_pp0_it29 <= ap_reg_ppstg_r_reg_377_pp0_it28;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_tmp14_reg_402_pp0_it21 <= tmp14_reg_402;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_tmp14_reg_402_pp0_it22 <= ap_reg_ppstg_tmp14_reg_402_pp0_it21;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_tmp14_reg_402_pp0_it23 <= ap_reg_ppstg_tmp14_reg_402_pp0_it22;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_tmp14_reg_402_pp0_it24 <= ap_reg_ppstg_tmp14_reg_402_pp0_it23;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_tmp14_reg_402_pp0_it25 <= ap_reg_ppstg_tmp14_reg_402_pp0_it24;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_tmp14_reg_402_pp0_it26 <= ap_reg_ppstg_tmp14_reg_402_pp0_it25;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_tmp14_reg_402_pp0_it27 <= ap_reg_ppstg_tmp14_reg_402_pp0_it26;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_tmp14_reg_402_pp0_it28 <= ap_reg_ppstg_tmp14_reg_402_pp0_it27;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_tmp14_reg_402_pp0_it29 <= ap_reg_ppstg_tmp14_reg_402_pp0_it28;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_tmp14_reg_402_pp0_it30 <= ap_reg_ppstg_tmp14_reg_402_pp0_it29;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_tmp14_reg_402_pp0_it31 <= ap_reg_ppstg_tmp14_reg_402_pp0_it30;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_tmp14_reg_402_pp0_it32 <= ap_reg_ppstg_tmp14_reg_402_pp0_it31;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_tmp14_reg_402_pp0_it33 <= ap_reg_ppstg_tmp14_reg_402_pp0_it32;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_tmp14_reg_402_pp0_it34 <= ap_reg_ppstg_tmp14_reg_402_pp0_it33;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_tmp14_reg_402_pp0_it35 <= ap_reg_ppstg_tmp14_reg_402_pp0_it34;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_tmp14_reg_402_pp0_it36 <= ap_reg_ppstg_tmp14_reg_402_pp0_it35;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_tmp14_reg_402_pp0_it37 <= ap_reg_ppstg_tmp14_reg_402_pp0_it36;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_tmp14_reg_402_pp0_it38 <= ap_reg_ppstg_tmp14_reg_402_pp0_it37;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_tmp14_reg_402_pp0_it39 <= ap_reg_ppstg_tmp14_reg_402_pp0_it38;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_tmp14_reg_402_pp0_it40 <= ap_reg_ppstg_tmp14_reg_402_pp0_it39;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_tmp14_reg_402_pp0_it41 <= ap_reg_ppstg_tmp14_reg_402_pp0_it40;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_tmp14_reg_402_pp0_it42 <= ap_reg_ppstg_tmp14_reg_402_pp0_it41;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_tmp14_reg_402_pp0_it43 <= ap_reg_ppstg_tmp14_reg_402_pp0_it42;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_tmp14_reg_402_pp0_it44 <= ap_reg_ppstg_tmp14_reg_402_pp0_it43;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_tmp14_reg_402_pp0_it45 <= ap_reg_ppstg_tmp14_reg_402_pp0_it44;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_tmp14_reg_402_pp0_it46 <= ap_reg_ppstg_tmp14_reg_402_pp0_it45;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_tmp14_reg_402_pp0_it47 <= ap_reg_ppstg_tmp14_reg_402_pp0_it46;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_tmp24_reg_407_pp0_it21 <= tmp24_reg_407;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_tmp24_reg_407_pp0_it22 <= ap_reg_ppstg_tmp24_reg_407_pp0_it21;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_tmp24_reg_407_pp0_it23 <= ap_reg_ppstg_tmp24_reg_407_pp0_it22;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_tmp24_reg_407_pp0_it24 <= ap_reg_ppstg_tmp24_reg_407_pp0_it23;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_tmp24_reg_407_pp0_it25 <= ap_reg_ppstg_tmp24_reg_407_pp0_it24;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_tmp24_reg_407_pp0_it26 <= ap_reg_ppstg_tmp24_reg_407_pp0_it25;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_tmp24_reg_407_pp0_it27 <= ap_reg_ppstg_tmp24_reg_407_pp0_it26;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_tmp24_reg_407_pp0_it28 <= ap_reg_ppstg_tmp24_reg_407_pp0_it27;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_tmp24_reg_407_pp0_it29 <= ap_reg_ppstg_tmp24_reg_407_pp0_it28;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_tmp24_reg_407_pp0_it30 <= ap_reg_ppstg_tmp24_reg_407_pp0_it29;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_tmp24_reg_407_pp0_it31 <= ap_reg_ppstg_tmp24_reg_407_pp0_it30;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_tmp24_reg_407_pp0_it32 <= ap_reg_ppstg_tmp24_reg_407_pp0_it31;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_tmp24_reg_407_pp0_it33 <= ap_reg_ppstg_tmp24_reg_407_pp0_it32;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_tmp24_reg_407_pp0_it34 <= ap_reg_ppstg_tmp24_reg_407_pp0_it33;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_tmp24_reg_407_pp0_it35 <= ap_reg_ppstg_tmp24_reg_407_pp0_it34;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_tmp24_reg_407_pp0_it36 <= ap_reg_ppstg_tmp24_reg_407_pp0_it35;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_tmp24_reg_407_pp0_it37 <= ap_reg_ppstg_tmp24_reg_407_pp0_it36;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_tmp24_reg_407_pp0_it38 <= ap_reg_ppstg_tmp24_reg_407_pp0_it37;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_tmp24_reg_407_pp0_it39 <= ap_reg_ppstg_tmp24_reg_407_pp0_it38;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_tmp24_reg_407_pp0_it40 <= ap_reg_ppstg_tmp24_reg_407_pp0_it39;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_tmp24_reg_407_pp0_it41 <= ap_reg_ppstg_tmp24_reg_407_pp0_it40;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_tmp24_reg_407_pp0_it42 <= ap_reg_ppstg_tmp24_reg_407_pp0_it41;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_tmp24_reg_407_pp0_it43 <= ap_reg_ppstg_tmp24_reg_407_pp0_it42;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_tmp24_reg_407_pp0_it44 <= ap_reg_ppstg_tmp24_reg_407_pp0_it43;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_tmp24_reg_407_pp0_it45 <= ap_reg_ppstg_tmp24_reg_407_pp0_it44;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_tmp24_reg_407_pp0_it46 <= ap_reg_ppstg_tmp24_reg_407_pp0_it45;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_tmp24_reg_407_pp0_it47 <= ap_reg_ppstg_tmp24_reg_407_pp0_it46;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_u_read_reg_336_pp0_it1 <= u_read_reg_336;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_u_read_reg_336_pp0_it10 <= ap_reg_ppstg_u_read_reg_336_pp0_it9;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_u_read_reg_336_pp0_it11 <= ap_reg_ppstg_u_read_reg_336_pp0_it10;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_u_read_reg_336_pp0_it12 <= ap_reg_ppstg_u_read_reg_336_pp0_it11;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_u_read_reg_336_pp0_it13 <= ap_reg_ppstg_u_read_reg_336_pp0_it12;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_u_read_reg_336_pp0_it14 <= ap_reg_ppstg_u_read_reg_336_pp0_it13;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_u_read_reg_336_pp0_it15 <= ap_reg_ppstg_u_read_reg_336_pp0_it14;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_u_read_reg_336_pp0_it16 <= ap_reg_ppstg_u_read_reg_336_pp0_it15;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_u_read_reg_336_pp0_it17 <= ap_reg_ppstg_u_read_reg_336_pp0_it16;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_u_read_reg_336_pp0_it18 <= ap_reg_ppstg_u_read_reg_336_pp0_it17;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_u_read_reg_336_pp0_it19 <= ap_reg_ppstg_u_read_reg_336_pp0_it18;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_u_read_reg_336_pp0_it2 <= ap_reg_ppstg_u_read_reg_336_pp0_it1;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_u_read_reg_336_pp0_it20 <= ap_reg_ppstg_u_read_reg_336_pp0_it19;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_u_read_reg_336_pp0_it21 <= ap_reg_ppstg_u_read_reg_336_pp0_it20;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_u_read_reg_336_pp0_it22 <= ap_reg_ppstg_u_read_reg_336_pp0_it21;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_u_read_reg_336_pp0_it23 <= ap_reg_ppstg_u_read_reg_336_pp0_it22;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_u_read_reg_336_pp0_it24 <= ap_reg_ppstg_u_read_reg_336_pp0_it23;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_u_read_reg_336_pp0_it25 <= ap_reg_ppstg_u_read_reg_336_pp0_it24;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_u_read_reg_336_pp0_it26 <= ap_reg_ppstg_u_read_reg_336_pp0_it25;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_u_read_reg_336_pp0_it27 <= ap_reg_ppstg_u_read_reg_336_pp0_it26;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_u_read_reg_336_pp0_it28 <= ap_reg_ppstg_u_read_reg_336_pp0_it27;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_u_read_reg_336_pp0_it29 <= ap_reg_ppstg_u_read_reg_336_pp0_it28;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_u_read_reg_336_pp0_it3 <= ap_reg_ppstg_u_read_reg_336_pp0_it2;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_u_read_reg_336_pp0_it30 <= ap_reg_ppstg_u_read_reg_336_pp0_it29;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_u_read_reg_336_pp0_it31 <= ap_reg_ppstg_u_read_reg_336_pp0_it30;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_u_read_reg_336_pp0_it32 <= ap_reg_ppstg_u_read_reg_336_pp0_it31;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_u_read_reg_336_pp0_it33 <= ap_reg_ppstg_u_read_reg_336_pp0_it32;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_u_read_reg_336_pp0_it34 <= ap_reg_ppstg_u_read_reg_336_pp0_it33;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_u_read_reg_336_pp0_it35 <= ap_reg_ppstg_u_read_reg_336_pp0_it34;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_u_read_reg_336_pp0_it36 <= ap_reg_ppstg_u_read_reg_336_pp0_it35;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_u_read_reg_336_pp0_it37 <= ap_reg_ppstg_u_read_reg_336_pp0_it36;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_u_read_reg_336_pp0_it38 <= ap_reg_ppstg_u_read_reg_336_pp0_it37;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_u_read_reg_336_pp0_it39 <= ap_reg_ppstg_u_read_reg_336_pp0_it38;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_u_read_reg_336_pp0_it4 <= ap_reg_ppstg_u_read_reg_336_pp0_it3;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_u_read_reg_336_pp0_it40 <= ap_reg_ppstg_u_read_reg_336_pp0_it39;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_u_read_reg_336_pp0_it41 <= ap_reg_ppstg_u_read_reg_336_pp0_it40;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_u_read_reg_336_pp0_it42 <= ap_reg_ppstg_u_read_reg_336_pp0_it41;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_u_read_reg_336_pp0_it43 <= ap_reg_ppstg_u_read_reg_336_pp0_it42;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_u_read_reg_336_pp0_it44 <= ap_reg_ppstg_u_read_reg_336_pp0_it43;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_u_read_reg_336_pp0_it45 <= ap_reg_ppstg_u_read_reg_336_pp0_it44;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_u_read_reg_336_pp0_it46 <= ap_reg_ppstg_u_read_reg_336_pp0_it45;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_u_read_reg_336_pp0_it47 <= ap_reg_ppstg_u_read_reg_336_pp0_it46;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_u_read_reg_336_pp0_it48 <= ap_reg_ppstg_u_read_reg_336_pp0_it47;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_u_read_reg_336_pp0_it49 <= ap_reg_ppstg_u_read_reg_336_pp0_it48;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_u_read_reg_336_pp0_it5 <= ap_reg_ppstg_u_read_reg_336_pp0_it4;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_u_read_reg_336_pp0_it50 <= ap_reg_ppstg_u_read_reg_336_pp0_it49;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_u_read_reg_336_pp0_it51 <= ap_reg_ppstg_u_read_reg_336_pp0_it50;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_u_read_reg_336_pp0_it52 <= ap_reg_ppstg_u_read_reg_336_pp0_it51;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_u_read_reg_336_pp0_it53 <= ap_reg_ppstg_u_read_reg_336_pp0_it52;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_u_read_reg_336_pp0_it54 <= ap_reg_ppstg_u_read_reg_336_pp0_it53;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_u_read_reg_336_pp0_it55 <= ap_reg_ppstg_u_read_reg_336_pp0_it54;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_u_read_reg_336_pp0_it6 <= ap_reg_ppstg_u_read_reg_336_pp0_it5;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_u_read_reg_336_pp0_it7 <= ap_reg_ppstg_u_read_reg_336_pp0_it6;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_u_read_reg_336_pp0_it8 <= ap_reg_ppstg_u_read_reg_336_pp0_it7;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_u_read_reg_336_pp0_it9 <= ap_reg_ppstg_u_read_reg_336_pp0_it8;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_ug2_read_reg_321_pp0_it1 <= ug2_read_reg_321;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_ug2_read_reg_321_pp0_it2 <= ap_reg_ppstg_ug2_read_reg_321_pp0_it1;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_ug2_read_reg_321_pp0_it3 <= ap_reg_ppstg_ug2_read_reg_321_pp0_it2;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_ug2_read_reg_321_pp0_it4 <= ap_reg_ppstg_ug2_read_reg_321_pp0_it3;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_ug3_read_reg_316_pp0_it1 <= ug3_read_reg_316;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_ug3_read_reg_316_pp0_it2 <= ap_reg_ppstg_ug3_read_reg_316_pp0_it1;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_ug3_read_reg_316_pp0_it3 <= ap_reg_ppstg_ug3_read_reg_316_pp0_it2;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_ug3_read_reg_316_pp0_it4 <= ap_reg_ppstg_ug3_read_reg_316_pp0_it3;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_ug3_read_reg_316_pp0_it5 <= ap_reg_ppstg_ug3_read_reg_316_pp0_it4;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_ug3_read_reg_316_pp0_it6 <= ap_reg_ppstg_ug3_read_reg_316_pp0_it5;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_ug3_read_reg_316_pp0_it7 <= ap_reg_ppstg_ug3_read_reg_316_pp0_it6;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_ug3_read_reg_316_pp0_it8 <= ap_reg_ppstg_ug3_read_reg_316_pp0_it7;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_ug4_read_reg_311_pp0_it1 <= ug4_read_reg_311;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_ug4_read_reg_311_pp0_it10 <= ap_reg_ppstg_ug4_read_reg_311_pp0_it9;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_ug4_read_reg_311_pp0_it11 <= ap_reg_ppstg_ug4_read_reg_311_pp0_it10;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_ug4_read_reg_311_pp0_it12 <= ap_reg_ppstg_ug4_read_reg_311_pp0_it11;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_ug4_read_reg_311_pp0_it2 <= ap_reg_ppstg_ug4_read_reg_311_pp0_it1;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_ug4_read_reg_311_pp0_it3 <= ap_reg_ppstg_ug4_read_reg_311_pp0_it2;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_ug4_read_reg_311_pp0_it4 <= ap_reg_ppstg_ug4_read_reg_311_pp0_it3;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_ug4_read_reg_311_pp0_it5 <= ap_reg_ppstg_ug4_read_reg_311_pp0_it4;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_ug4_read_reg_311_pp0_it6 <= ap_reg_ppstg_ug4_read_reg_311_pp0_it5;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_ug4_read_reg_311_pp0_it7 <= ap_reg_ppstg_ug4_read_reg_311_pp0_it6;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_ug4_read_reg_311_pp0_it8 <= ap_reg_ppstg_ug4_read_reg_311_pp0_it7;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_ug4_read_reg_311_pp0_it9 <= ap_reg_ppstg_ug4_read_reg_311_pp0_it8;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_ug5_read_reg_306_pp0_it1 <= ug5_read_reg_306;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_ug5_read_reg_306_pp0_it10 <= ap_reg_ppstg_ug5_read_reg_306_pp0_it9;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_ug5_read_reg_306_pp0_it11 <= ap_reg_ppstg_ug5_read_reg_306_pp0_it10;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_ug5_read_reg_306_pp0_it12 <= ap_reg_ppstg_ug5_read_reg_306_pp0_it11;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_ug5_read_reg_306_pp0_it13 <= ap_reg_ppstg_ug5_read_reg_306_pp0_it12;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_ug5_read_reg_306_pp0_it14 <= ap_reg_ppstg_ug5_read_reg_306_pp0_it13;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_ug5_read_reg_306_pp0_it15 <= ap_reg_ppstg_ug5_read_reg_306_pp0_it14;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_ug5_read_reg_306_pp0_it16 <= ap_reg_ppstg_ug5_read_reg_306_pp0_it15;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_ug5_read_reg_306_pp0_it2 <= ap_reg_ppstg_ug5_read_reg_306_pp0_it1;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_ug5_read_reg_306_pp0_it3 <= ap_reg_ppstg_ug5_read_reg_306_pp0_it2;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_ug5_read_reg_306_pp0_it4 <= ap_reg_ppstg_ug5_read_reg_306_pp0_it3;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_ug5_read_reg_306_pp0_it5 <= ap_reg_ppstg_ug5_read_reg_306_pp0_it4;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_ug5_read_reg_306_pp0_it6 <= ap_reg_ppstg_ug5_read_reg_306_pp0_it5;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_ug5_read_reg_306_pp0_it7 <= ap_reg_ppstg_ug5_read_reg_306_pp0_it6;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_ug5_read_reg_306_pp0_it8 <= ap_reg_ppstg_ug5_read_reg_306_pp0_it7;
end
if ((ap_const_logic_1 == ap_ce)) begin
ap_reg_ppstg_ug5_read_reg_306_pp0_it9 <= ap_reg_ppstg_ug5_read_reg_306_pp0_it8;
end
if ((ap_const_logic_1 == ap_ce)) begin
f_read_reg_270 <= f;
end
if ((ap_const_logic_1 == ap_ce)) begin
g0_read_reg_301 <= g0;
end
if ((ap_const_logic_1 == ap_ce)) begin
g1_read_reg_296 <= g1;
end
if ((ap_const_logic_1 == ap_ce)) begin
g2_read_reg_291 <= g2;
end
if ((ap_const_logic_1 == ap_ce)) begin
g3_read_reg_286 <= g3;
end
if ((ap_const_logic_1 == ap_ce)) begin
g4_read_reg_281 <= g4;
end
if ((ap_const_logic_1 == ap_ce)) begin
g5_read_reg_276 <= g5;
end
if ((ap_const_logic_1 == ap_ce)) begin
r1_reg_452 <= grp_fu_138_p2;
end
if ((ap_const_logic_1 == ap_ce)) begin
r_reg_377 <= grp_fu_133_p2;
end
if ((ap_const_logic_1 == ap_ce)) begin
tmp10_reg_347 <= grp_fu_146_p2;
end
if ((ap_const_logic_1 == ap_ce)) begin
tmp11_reg_357 <= grp_fu_154_p2;
end
if ((ap_const_logic_1 == ap_ce)) begin
tmp12_reg_367 <= grp_fu_162_p2;
end
if ((ap_const_logic_1 == ap_ce)) begin
tmp13_reg_387 <= grp_fu_170_p2;
end
if ((ap_const_logic_1 == ap_ce)) begin
tmp14_reg_402 <= grp_fu_183_p2;
end
if ((ap_const_logic_1 == ap_ce)) begin
tmp15_reg_457 <= grp_fu_251_p2;
end
if ((ap_const_logic_1 == ap_ce)) begin
tmp16_reg_462 <= grp_fu_256_p2;
end
if ((ap_const_logic_1 == ap_ce)) begin
tmp17_reg_467 <= grp_fu_211_p2;
end
if ((ap_const_logic_1 == ap_ce)) begin
tmp18_reg_477 <= grp_fu_260_p2;
end
if ((ap_const_logic_1 == ap_ce)) begin
tmp19_reg_487 <= grp_fu_220_p2;
end
if ((ap_const_logic_1 == ap_ce)) begin
tmp1_reg_412 <= grp_fu_191_p2;
end
if ((ap_const_logic_1 == ap_ce)) begin
tmp20_reg_352 <= grp_fu_150_p2;
end
if ((ap_const_logic_1 == ap_ce)) begin
tmp21_reg_362 <= grp_fu_158_p2;
end
if ((ap_const_logic_1 == ap_ce)) begin
tmp22_reg_372 <= grp_fu_166_p2;
end
if ((ap_const_logic_1 == ap_ce)) begin
tmp23_reg_392 <= grp_fu_174_p2;
end
if ((ap_const_logic_1 == ap_ce)) begin
tmp24_reg_407 <= grp_fu_187_p2;
end
if ((ap_const_logic_1 == ap_ce)) begin
tmp25_reg_472 <= grp_fu_215_p2;
end
if ((ap_const_logic_1 == ap_ce)) begin
tmp26_reg_482 <= grp_fu_265_p2;
end
if ((ap_const_logic_1 == ap_ce)) begin
tmp27_reg_492 <= grp_fu_224_p2;
end
if ((ap_const_logic_1 == ap_ce)) begin
tmp2_reg_422 <= grp_fu_239_p2;
end
if ((ap_const_logic_1 == ap_ce)) begin
tmp3_reg_432 <= grp_fu_201_p2;
end
if ((ap_const_logic_1 == ap_ce)) begin
tmp4_reg_442 <= grp_fu_247_p2;
end
if ((ap_const_logic_1 == ap_ce)) begin
tmp5_reg_397 <= grp_fu_178_p2;
end
if ((ap_const_logic_1 == ap_ce)) begin
tmp6_reg_417 <= grp_fu_235_p2;
end
if ((ap_const_logic_1 == ap_ce)) begin
tmp7_reg_427 <= grp_fu_196_p2;
end
if ((ap_const_logic_1 == ap_ce)) begin
tmp8_reg_437 <= grp_fu_243_p2;
end
if ((ap_const_logic_1 == ap_ce)) begin
tmp9_reg_447 <= grp_fu_206_p2;
end
if ((ap_const_logic_1 == ap_ce)) begin
tmp_reg_342 <= grp_fu_229_p2;
end
if ((ap_const_logic_1 == ap_ce)) begin
u_read_reg_336 <= u;
end
if ((ap_const_logic_1 == ap_ce)) begin
ug0_read_reg_331 <= ug0;
end
if ((ap_const_logic_1 == ap_ce)) begin
ug1_read_reg_326 <= ug1;
end
if ((ap_const_logic_1 == ap_ce)) begin
ug2_read_reg_321 <= ug2;
end
if ((ap_const_logic_1 == ap_ce)) begin
ug3_read_reg_316 <= ug3;
end
if ((ap_const_logic_1 == ap_ce)) begin
ug4_read_reg_311 <= ug4;
end
if ((ap_const_logic_1 == ap_ce)) begin
ug5_read_reg_306 <= ug5;
end
end
/// grp_fu_133_ce assign process. ///
always @ (ap_ce)
begin
if ((ap_const_logic_1 == ap_ce)) begin
grp_fu_133_ce = ap_const_logic_1;
end else begin
grp_fu_133_ce = ap_const_logic_0;
end
end
/// grp_fu_138_ce assign process. ///
always @ (ap_ce)
begin
if ((ap_const_logic_1 == ap_ce)) begin
grp_fu_138_ce = ap_const_logic_1;
end else begin
grp_fu_138_ce = ap_const_logic_0;
end
end
/// grp_fu_142_ce assign process. ///
always @ (ap_ce)
begin
if ((ap_const_logic_1 == ap_ce)) begin
grp_fu_142_ce = ap_const_logic_1;
end else begin
grp_fu_142_ce = ap_const_logic_0;
end
end
/// grp_fu_146_ce assign process. ///
always @ (ap_ce)
begin
if ((ap_const_logic_1 == ap_ce)) begin
grp_fu_146_ce = ap_const_logic_1;
end else begin
grp_fu_146_ce = ap_const_logic_0;
end
end
/// grp_fu_150_ce assign process. ///
always @ (ap_ce)
begin
if ((ap_const_logic_1 == ap_ce)) begin
grp_fu_150_ce = ap_const_logic_1;
end else begin
grp_fu_150_ce = ap_const_logic_0;
end
end
/// grp_fu_154_ce assign process. ///
always @ (ap_ce)
begin
if ((ap_const_logic_1 == ap_ce)) begin
grp_fu_154_ce = ap_const_logic_1;
end else begin
grp_fu_154_ce = ap_const_logic_0;
end
end
/// grp_fu_158_ce assign process. ///
always @ (ap_ce)
begin
if ((ap_const_logic_1 == ap_ce)) begin
grp_fu_158_ce = ap_const_logic_1;
end else begin
grp_fu_158_ce = ap_const_logic_0;
end
end
/// grp_fu_162_ce assign process. ///
always @ (ap_ce)
begin
if ((ap_const_logic_1 == ap_ce)) begin
grp_fu_162_ce = ap_const_logic_1;
end else begin
grp_fu_162_ce = ap_const_logic_0;
end
end
/// grp_fu_166_ce assign process. ///
always @ (ap_ce)
begin
if ((ap_const_logic_1 == ap_ce)) begin
grp_fu_166_ce = ap_const_logic_1;
end else begin
grp_fu_166_ce = ap_const_logic_0;
end
end
/// grp_fu_170_ce assign process. ///
always @ (ap_ce)
begin
if ((ap_const_logic_1 == ap_ce)) begin
grp_fu_170_ce = ap_const_logic_1;
end else begin
grp_fu_170_ce = ap_const_logic_0;
end
end
/// grp_fu_174_ce assign process. ///
always @ (ap_ce)
begin
if ((ap_const_logic_1 == ap_ce)) begin
grp_fu_174_ce = ap_const_logic_1;
end else begin
grp_fu_174_ce = ap_const_logic_0;
end
end
/// grp_fu_178_ce assign process. ///
always @ (ap_ce)
begin
if ((ap_const_logic_1 == ap_ce)) begin
grp_fu_178_ce = ap_const_logic_1;
end else begin
grp_fu_178_ce = ap_const_logic_0;
end
end
/// grp_fu_183_ce assign process. ///
always @ (ap_ce)
begin
if ((ap_const_logic_1 == ap_ce)) begin
grp_fu_183_ce = ap_const_logic_1;
end else begin
grp_fu_183_ce = ap_const_logic_0;
end
end
/// grp_fu_187_ce assign process. ///
always @ (ap_ce)
begin
if ((ap_const_logic_1 == ap_ce)) begin
grp_fu_187_ce = ap_const_logic_1;
end else begin
grp_fu_187_ce = ap_const_logic_0;
end
end
/// grp_fu_191_ce assign process. ///
always @ (ap_ce)
begin
if ((ap_const_logic_1 == ap_ce)) begin
grp_fu_191_ce = ap_const_logic_1;
end else begin
grp_fu_191_ce = ap_const_logic_0;
end
end
/// grp_fu_196_ce assign process. ///
always @ (ap_ce)
begin
if ((ap_const_logic_1 == ap_ce)) begin
grp_fu_196_ce = ap_const_logic_1;
end else begin
grp_fu_196_ce = ap_const_logic_0;
end
end
/// grp_fu_201_ce assign process. ///
always @ (ap_ce)
begin
if ((ap_const_logic_1 == ap_ce)) begin
grp_fu_201_ce = ap_const_logic_1;
end else begin
grp_fu_201_ce = ap_const_logic_0;
end
end
/// grp_fu_206_ce assign process. ///
always @ (ap_ce)
begin
if ((ap_const_logic_1 == ap_ce)) begin
grp_fu_206_ce = ap_const_logic_1;
end else begin
grp_fu_206_ce = ap_const_logic_0;
end
end
/// grp_fu_211_ce assign process. ///
always @ (ap_ce)
begin
if ((ap_const_logic_1 == ap_ce)) begin
grp_fu_211_ce = ap_const_logic_1;
end else begin
grp_fu_211_ce = ap_const_logic_0;
end
end
/// grp_fu_215_ce assign process. ///
always @ (ap_ce)
begin
if ((ap_const_logic_1 == ap_ce)) begin
grp_fu_215_ce = ap_const_logic_1;
end else begin
grp_fu_215_ce = ap_const_logic_0;
end
end
/// grp_fu_220_ce assign process. ///
always @ (ap_ce)
begin
if ((ap_const_logic_1 == ap_ce)) begin
grp_fu_220_ce = ap_const_logic_1;
end else begin
grp_fu_220_ce = ap_const_logic_0;
end
end
/// grp_fu_224_ce assign process. ///
always @ (ap_ce)
begin
if ((ap_const_logic_1 == ap_ce)) begin
grp_fu_224_ce = ap_const_logic_1;
end else begin
grp_fu_224_ce = ap_const_logic_0;
end
end
/// grp_fu_229_ce assign process. ///
always @ (ap_ce)
begin
if ((ap_const_logic_1 == ap_ce)) begin
grp_fu_229_ce = ap_const_logic_1;
end else begin
grp_fu_229_ce = ap_const_logic_0;
end
end
/// grp_fu_235_ce assign process. ///
always @ (ap_ce)
begin
if ((ap_const_logic_1 == ap_ce)) begin
grp_fu_235_ce = ap_const_logic_1;
end else begin
grp_fu_235_ce = ap_const_logic_0;
end
end
/// grp_fu_239_ce assign process. ///
always @ (ap_ce)
begin
if ((ap_const_logic_1 == ap_ce)) begin
grp_fu_239_ce = ap_const_logic_1;
end else begin
grp_fu_239_ce = ap_const_logic_0;
end
end
/// grp_fu_243_ce assign process. ///
always @ (ap_ce)
begin
if ((ap_const_logic_1 == ap_ce)) begin
grp_fu_243_ce = ap_const_logic_1;
end else begin
grp_fu_243_ce = ap_const_logic_0;
end
end
/// grp_fu_247_ce assign process. ///
always @ (ap_ce)
begin
if ((ap_const_logic_1 == ap_ce)) begin
grp_fu_247_ce = ap_const_logic_1;
end else begin
grp_fu_247_ce = ap_const_logic_0;
end
end
/// grp_fu_251_ce assign process. ///
always @ (ap_ce)
begin
if ((ap_const_logic_1 == ap_ce)) begin
grp_fu_251_ce = ap_const_logic_1;
end else begin
grp_fu_251_ce = ap_const_logic_0;
end
end
/// grp_fu_256_ce assign process. ///
always @ (ap_ce)
begin
if ((ap_const_logic_1 == ap_ce)) begin
grp_fu_256_ce = ap_const_logic_1;
end else begin
grp_fu_256_ce = ap_const_logic_0;
end
end
/// grp_fu_260_ce assign process. ///
always @ (ap_ce)
begin
if ((ap_const_logic_1 == ap_ce)) begin
grp_fu_260_ce = ap_const_logic_1;
end else begin
grp_fu_260_ce = ap_const_logic_0;
end
end
/// grp_fu_265_ce assign process. ///
always @ (ap_ce)
begin
if ((ap_const_logic_1 == ap_ce)) begin
grp_fu_265_ce = ap_const_logic_1;
end else begin
grp_fu_265_ce = ap_const_logic_0;
end
end
assign ap_return = grp_fu_142_p2;
assign grp_fu_133_p0 = tmp_reg_342;
assign grp_fu_133_p1 = ap_const_lv32_3E64F766;
assign grp_fu_138_p0 = tmp4_reg_442;
assign grp_fu_138_p1 = tmp9_reg_447;
assign grp_fu_142_p0 = tmp19_reg_487;
assign grp_fu_142_p1 = tmp27_reg_492;
assign grp_fu_146_p0 = ug0_read_reg_331;
assign grp_fu_146_p1 = ug1_read_reg_326;
assign grp_fu_150_p0 = g0_read_reg_301;
assign grp_fu_150_p1 = g1_read_reg_296;
assign grp_fu_154_p0 = tmp10_reg_347;
assign grp_fu_154_p1 = ap_reg_ppstg_ug2_read_reg_321_pp0_it4;
assign grp_fu_158_p0 = tmp20_reg_352;
assign grp_fu_158_p1 = ap_reg_ppstg_g2_read_reg_291_pp0_it4;
assign grp_fu_162_p0 = tmp11_reg_357;
assign grp_fu_162_p1 = ap_reg_ppstg_ug3_read_reg_316_pp0_it8;
assign grp_fu_166_p0 = tmp21_reg_362;
assign grp_fu_166_p1 = ap_reg_ppstg_g3_read_reg_286_pp0_it8;
assign grp_fu_170_p0 = tmp12_reg_367;
assign grp_fu_170_p1 = ap_reg_ppstg_ug4_read_reg_311_pp0_it12;
assign grp_fu_174_p0 = tmp22_reg_372;
assign grp_fu_174_p1 = ap_reg_ppstg_g4_read_reg_281_pp0_it12;
assign grp_fu_178_p0 = r_reg_377;
assign grp_fu_178_p1 = ap_const_lv32_3FBEA3AD;
assign grp_fu_183_p0 = tmp13_reg_387;
assign grp_fu_183_p1 = ap_reg_ppstg_ug5_read_reg_306_pp0_it16;
assign grp_fu_187_p0 = tmp23_reg_392;
assign grp_fu_187_p1 = ap_reg_ppstg_g5_read_reg_276_pp0_it16;
assign grp_fu_191_p0 = ap_reg_ppstg_r_reg_377_pp0_it17;
assign grp_fu_191_p1 = ap_const_lv32_3F7335A0;
assign grp_fu_196_p0 = tmp6_reg_417;
assign grp_fu_196_p1 = ap_const_lv32_4024D384;
assign grp_fu_201_p0 = tmp2_reg_422;
assign grp_fu_201_p1 = ap_const_lv32_4018EC96;
assign grp_fu_206_p0 = tmp8_reg_437;
assign grp_fu_206_p1 = ap_const_lv32_4094E686;
assign grp_fu_211_p0 = ap_reg_ppstg_tmp14_reg_402_pp0_it47;
assign grp_fu_211_p1 = tmp16_reg_462;
assign grp_fu_215_p0 = ap_reg_ppstg_tmp24_reg_407_pp0_it47;
assign grp_fu_215_p1 = ap_const_lv32_3E94D6A1;
assign grp_fu_220_p0 = tmp18_reg_477;
assign grp_fu_220_p1 = ap_reg_ppstg_u_read_reg_336_pp0_it55;
assign grp_fu_224_p0 = tmp26_reg_482;
assign grp_fu_224_p1 = ap_const_lv32_3F800000;
assign grp_fu_229_p0 = u;
assign grp_fu_229_p1 = f;
assign grp_fu_235_p0 = tmp5_reg_397;
assign grp_fu_235_p1 = ap_reg_ppstg_r_reg_377_pp0_it17;
assign grp_fu_239_p0 = tmp1_reg_412;
assign grp_fu_239_p1 = ap_reg_ppstg_r_reg_377_pp0_it21;
assign grp_fu_243_p0 = tmp7_reg_427;
assign grp_fu_243_p1 = ap_reg_ppstg_r_reg_377_pp0_it25;
assign grp_fu_247_p0 = tmp3_reg_432;
assign grp_fu_247_p1 = ap_reg_ppstg_r_reg_377_pp0_it29;
assign grp_fu_251_p0 = ap_reg_ppstg_f_read_reg_270_pp0_it39;
assign grp_fu_251_p1 = ap_const_lv32_3E94D6A1;
assign grp_fu_256_p0 = tmp15_reg_457;
assign grp_fu_256_p1 = r1_reg_452;
assign grp_fu_260_p0 = tmp17_reg_467;
assign grp_fu_260_p1 = ap_const_lv32_40A00000;
assign grp_fu_265_p0 = tmp25_reg_472;
assign grp_fu_265_p1 = ap_const_lv32_40A00000;
endmodule //computeResultOne
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
module computeResultOne_grp_fu_133_ACMP_fdiv_111(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fdiv #(
.ID( ID ),
.NUM_STAGE( 10 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fdiv_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
module computeResultOne_grp_fu_138_ACMP_fdiv_112(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fdiv #(
.ID( ID ),
.NUM_STAGE( 10 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fdiv_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
module computeResultOne_grp_fu_142_ACMP_fdiv_113(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fdiv #(
.ID( ID ),
.NUM_STAGE( 10 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fdiv_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
module computeResultOne_grp_fu_146_ACMP_fadd_114(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fadd #(
.ID( ID ),
.NUM_STAGE( 4 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fadd_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
module computeResultOne_grp_fu_150_ACMP_fadd_115(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fadd #(
.ID( ID ),
.NUM_STAGE( 4 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fadd_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
module computeResultOne_grp_fu_154_ACMP_fadd_116(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fadd #(
.ID( ID ),
.NUM_STAGE( 4 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fadd_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
module computeResultOne_grp_fu_158_ACMP_fadd_117(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fadd #(
.ID( ID ),
.NUM_STAGE( 4 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fadd_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
module computeResultOne_grp_fu_162_ACMP_fadd_118(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fadd #(
.ID( ID ),
.NUM_STAGE( 4 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fadd_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
module computeResultOne_grp_fu_166_ACMP_fadd_119(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fadd #(
.ID( ID ),
.NUM_STAGE( 4 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fadd_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
module computeResultOne_grp_fu_170_ACMP_fadd_120(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fadd #(
.ID( ID ),
.NUM_STAGE( 4 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fadd_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
module computeResultOne_grp_fu_174_ACMP_fadd_121(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fadd #(
.ID( ID ),
.NUM_STAGE( 4 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fadd_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
module computeResultOne_grp_fu_178_ACMP_fadd_122(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fadd #(
.ID( ID ),
.NUM_STAGE( 4 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fadd_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
module computeResultOne_grp_fu_183_ACMP_fadd_123(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fadd #(
.ID( ID ),
.NUM_STAGE( 4 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fadd_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
module computeResultOne_grp_fu_187_ACMP_fadd_124(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fadd #(
.ID( ID ),
.NUM_STAGE( 4 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fadd_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
module computeResultOne_grp_fu_191_ACMP_fadd_125(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fadd #(
.ID( ID ),
.NUM_STAGE( 4 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fadd_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
module computeResultOne_grp_fu_196_ACMP_fadd_126(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fadd #(
.ID( ID ),
.NUM_STAGE( 4 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fadd_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
module computeResultOne_grp_fu_201_ACMP_fadd_127(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fadd #(
.ID( ID ),
.NUM_STAGE( 4 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fadd_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
module computeResultOne_grp_fu_206_ACMP_fadd_128(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fadd #(
.ID( ID ),
.NUM_STAGE( 4 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fadd_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
module computeResultOne_grp_fu_211_ACMP_fadd_129(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fadd #(
.ID( ID ),
.NUM_STAGE( 4 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fadd_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
module computeResultOne_grp_fu_215_ACMP_fadd_130(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fadd #(
.ID( ID ),
.NUM_STAGE( 4 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fadd_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
module computeResultOne_grp_fu_220_ACMP_fadd_131(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fadd #(
.ID( ID ),
.NUM_STAGE( 4 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fadd_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
module computeResultOne_grp_fu_224_ACMP_fadd_132(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fadd #(
.ID( ID ),
.NUM_STAGE( 4 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fadd_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
module computeResultOne_grp_fu_229_ACMP_fmul_133(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fmul #(
.ID( ID ),
.NUM_STAGE( 4 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fmul_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
module computeResultOne_grp_fu_235_ACMP_fmul_134(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fmul #(
.ID( ID ),
.NUM_STAGE( 4 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fmul_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
module computeResultOne_grp_fu_239_ACMP_fmul_135(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fmul #(
.ID( ID ),
.NUM_STAGE( 4 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fmul_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
module computeResultOne_grp_fu_243_ACMP_fmul_136(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fmul #(
.ID( ID ),
.NUM_STAGE( 4 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fmul_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
module computeResultOne_grp_fu_247_ACMP_fmul_137(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fmul #(
.ID( ID ),
.NUM_STAGE( 4 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fmul_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
module computeResultOne_grp_fu_251_ACMP_fmul_138(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fmul #(
.ID( ID ),
.NUM_STAGE( 4 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fmul_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
module computeResultOne_grp_fu_256_ACMP_fmul_139(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fmul #(
.ID( ID ),
.NUM_STAGE( 4 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fmul_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
module computeResultOne_grp_fu_260_ACMP_fmul_140(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fmul #(
.ID( ID ),
.NUM_STAGE( 4 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fmul_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
module computeResultOne_grp_fu_265_ACMP_fmul_141(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fmul #(
.ID( ID ),
.NUM_STAGE( 4 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fmul_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
module computeResult_grp_fu_816_ACMP_fcmp_156(
clk,
reset,
ce,
din0,
din1,
opcode,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
input[5 - 1:0] opcode;
output[dout_WIDTH - 1:0] dout;
ACMP_fcmp #(
.ID( ID ),
.NUM_STAGE( 3 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fcmp_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ),
.opcode( opcode ));
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
module computeResult_grp_fu_821_ACMP_fcmp_157(
clk,
reset,
ce,
din0,
din1,
opcode,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
input[5 - 1:0] opcode;
output[dout_WIDTH - 1:0] dout;
ACMP_fcmp #(
.ID( ID ),
.NUM_STAGE( 3 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fcmp_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ),
.opcode( opcode ));
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
module computeResult_grp_fu_826_ACMP_fcmp_158(
clk,
reset,
ce,
din0,
din1,
opcode,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
input[5 - 1:0] opcode;
output[dout_WIDTH - 1:0] dout;
ACMP_fcmp #(
.ID( ID ),
.NUM_STAGE( 3 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fcmp_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ),
.opcode( opcode ));
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
module computeResult_grp_fu_831_ACMP_fcmp_159(
clk,
reset,
ce,
din0,
din1,
opcode,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
input[5 - 1:0] opcode;
output[dout_WIDTH - 1:0] dout;
ACMP_fcmp #(
.ID( ID ),
.NUM_STAGE( 3 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fcmp_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ),
.opcode( opcode ));
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
module computeResult_grp_fu_836_ACMP_fcmp_160(
clk,
reset,
ce,
din0,
din1,
opcode,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
input[5 - 1:0] opcode;
output[dout_WIDTH - 1:0] dout;
ACMP_fcmp #(
.ID( ID ),
.NUM_STAGE( 3 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fcmp_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ),
.opcode( opcode ));
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
module computeResult_grp_fu_841_ACMP_fcmp_161(
clk,
reset,
ce,
din0,
din1,
opcode,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
input[5 - 1:0] opcode;
output[dout_WIDTH - 1:0] dout;
ACMP_fcmp #(
.ID( ID ),
.NUM_STAGE( 3 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fcmp_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ),
.opcode( opcode ));
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
module computeResult_grp_fu_846_ACMP_fcmp_162(
clk,
reset,
ce,
din0,
din1,
opcode,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
input[5 - 1:0] opcode;
output[dout_WIDTH - 1:0] dout;
ACMP_fcmp #(
.ID( ID ),
.NUM_STAGE( 3 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fcmp_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ),
.opcode( opcode ));
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
module computeResult_grp_fu_851_ACMP_fcmp_163(
clk,
reset,
ce,
din0,
din1,
opcode,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
input[5 - 1:0] opcode;
output[dout_WIDTH - 1:0] dout;
ACMP_fcmp #(
.ID( ID ),
.NUM_STAGE( 3 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fcmp_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ),
.opcode( opcode ));
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
module computeResult_grp_fu_856_ACMP_fsub_164(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fsub #(
.ID( ID ),
.NUM_STAGE( 4 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fsub_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
module computeResult_grp_fu_860_ACMP_fsub_165(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fsub #(
.ID( ID ),
.NUM_STAGE( 4 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fsub_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
module computeResult_grp_fu_864_ACMP_fsub_166(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fsub #(
.ID( ID ),
.NUM_STAGE( 4 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fsub_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
module computeResult_grp_fu_868_ACMP_fsub_167(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fsub #(
.ID( ID ),
.NUM_STAGE( 4 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fsub_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// RTL generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ===========================================================
`timescale 1 ns / 1 ps
module computeUG (
ap_clk,
ap_rst,
ap_start,
ap_done,
ap_idle,
ug_p0_address0,
ug_p0_ce0,
ug_p0_we0,
ug_p0_d0,
ug_p1_address0,
ug_p1_ce0,
ug_p1_we0,
ug_p1_d0,
ug_p2_address0,
ug_p2_ce0,
ug_p2_we0,
ug_p2_d0,
ug_p3_address0,
ug_p3_ce0,
ug_p3_we0,
ug_p3_d0,
u_p0_address0,
u_p0_ce0,
u_p0_q0,
u_p1_address0,
u_p1_ce0,
u_p1_q0,
u_p2_address0,
u_p2_ce0,
u_p2_q0,
u_p3_address0,
u_p3_ce0,
u_p3_q0,
g_p0_address0,
g_p0_ce0,
g_p0_q0,
g_p1_address0,
g_p1_ce0,
g_p1_q0,
g_p2_address0,
g_p2_ce0,
g_p2_q0,
g_p3_address0,
g_p3_ce0,
g_p3_q0
);
input ap_clk;
input ap_rst;
input ap_start;
output ap_done;
output ap_idle;
output [7:0] ug_p0_address0;
output ug_p0_ce0;
output ug_p0_we0;
output [31:0] ug_p0_d0;
output [7:0] ug_p1_address0;
output ug_p1_ce0;
output ug_p1_we0;
output [31:0] ug_p1_d0;
output [7:0] ug_p2_address0;
output ug_p2_ce0;
output ug_p2_we0;
output [31:0] ug_p2_d0;
output [7:0] ug_p3_address0;
output ug_p3_ce0;
output ug_p3_we0;
output [31:0] ug_p3_d0;
output [7:0] u_p0_address0;
output u_p0_ce0;
input [31:0] u_p0_q0;
output [7:0] u_p1_address0;
output u_p1_ce0;
input [31:0] u_p1_q0;
output [7:0] u_p2_address0;
output u_p2_ce0;
input [31:0] u_p2_q0;
output [7:0] u_p3_address0;
output u_p3_ce0;
input [31:0] u_p3_q0;
output [7:0] g_p0_address0;
output g_p0_ce0;
input [31:0] g_p0_q0;
output [7:0] g_p1_address0;
output g_p1_ce0;
input [31:0] g_p1_q0;
output [7:0] g_p2_address0;
output g_p2_ce0;
input [31:0] g_p2_q0;
output [7:0] g_p3_address0;
output g_p3_ce0;
input [31:0] g_p3_q0;
reg ap_done;
reg ap_idle;
reg ug_p0_ce0;
reg ug_p0_we0;
reg ug_p1_ce0;
reg ug_p1_we0;
reg ug_p2_ce0;
reg ug_p2_we0;
reg ug_p3_ce0;
reg ug_p3_we0;
reg u_p0_ce0;
reg u_p1_ce0;
reg u_p2_ce0;
reg u_p3_ce0;
reg g_p0_ce0;
reg g_p1_ce0;
reg g_p2_ce0;
reg g_p3_ce0;
reg [1:0] ap_CS_fsm;
reg [9:0] k_reg_208;
reg [31:0] j_reg_219;
reg [31:0] i_1_reg_230;
wire [0:0] exitcond_fu_267_p2;
reg [0:0] exitcond_reg_415;
reg ap_reg_ppiten_pp0_it0;
reg ap_reg_ppiten_pp0_it1;
reg ap_reg_ppiten_pp0_it2;
reg ap_reg_ppiten_pp0_it3;
reg ap_reg_ppiten_pp0_it4;
reg ap_reg_ppiten_pp0_it5;
reg [0:0] ap_reg_ppstg_exitcond_reg_415_pp0_it1;
reg [0:0] ap_reg_ppstg_exitcond_reg_415_pp0_it2;
reg [0:0] ap_reg_ppstg_exitcond_reg_415_pp0_it3;
reg [0:0] ap_reg_ppstg_exitcond_reg_415_pp0_it4;
reg [9:0] indvar_next_reg_419;
reg [0:0] tmp_reg_424;
reg [0:0] ap_reg_ppstg_tmp_reg_424_pp0_it1;
reg [0:0] ap_reg_ppstg_tmp_reg_424_pp0_it2;
reg [0:0] ap_reg_ppstg_tmp_reg_424_pp0_it3;
reg [0:0] ap_reg_ppstg_tmp_reg_424_pp0_it4;
wire [31:0] u_p1_addr16_cast_fu_311_p1;
reg [31:0] u_p1_addr16_cast_reg_431;
reg [31:0] ap_reg_ppstg_u_p1_addr16_cast_reg_431_pp0_it1;
reg [31:0] ap_reg_ppstg_u_p1_addr16_cast_reg_431_pp0_it2;
reg [31:0] ap_reg_ppstg_u_p1_addr16_cast_reg_431_pp0_it3;
reg [31:0] ap_reg_ppstg_u_p1_addr16_cast_reg_431_pp0_it4;
reg [31:0] j_1_reg_459;
reg [31:0] i_reg_464;
reg [31:0] u_Local_reg_469;
reg [31:0] u_Local1_reg_474;
reg [31:0] u_Local2_reg_479;
reg [9:0] k_phi_fu_212_p4;
reg [31:0] j_phi_fu_223_p4;
reg [31:0] i_1_phi_fu_234_p4;
reg [31:0] u_Local03_1_fu_52;
reg [31:0] u_Local02_1_fu_56;
reg [31:0] u_Local01_1_fu_60;
wire [31:0] grp_fu_242_p2;
wire [31:0] grp_fu_249_p2;
wire [31:0] grp_fu_255_p2;
wire [31:0] grp_fu_261_p2;
wire [31:0] grp_fu_242_p0;
wire [31:0] grp_fu_242_p1;
wire [31:0] grp_fu_249_p0;
wire [31:0] grp_fu_249_p1;
wire [31:0] grp_fu_255_p0;
wire [31:0] grp_fu_255_p1;
wire [31:0] grp_fu_261_p0;
wire [31:0] grp_fu_261_p1;
wire [9:0] exitcond_fu_267_p1;
wire [31:0] tmp_fu_283_p1;
wire [7:0] i_1_cast_fu_289_p1;
wire [7:0] p_shl_fu_293_p2;
wire [7:0] u_p1_addr_cast_fu_299_p2;
wire [7:0] j_cast_fu_279_p1;
wire [7:0] u_p1_addr_fu_305_p2;
wire [31:0] tmp5_fu_318_p2;
wire [31:0] tmp6_fu_324_p1;
wire [0:0] tmp6_fu_324_p2;
wire [31:0] tmp7_fu_330_p2;
wire grp_fu_242_ce;
wire grp_fu_249_ce;
wire grp_fu_255_ce;
wire grp_fu_261_ce;
reg [1:0] ap_NS_fsm;
parameter ap_const_logic_1 = 1'b1;
parameter ap_const_logic_0 = 1'b0;
parameter ap_ST_st0_fsm_0 = 2'b00;
parameter ap_ST_st1_fsm_1 = 2'b01;
parameter ap_ST_pp0_stg0_fsm_2 = 2'b10;
parameter ap_ST_st8_fsm_3 = 2'b11;
parameter ap_const_lv1_0 = 1'b0;
parameter ap_const_lv10_0 = 10'b0000000000;
parameter ap_const_lv32_0 = 32'b00000000000000000000000000000000;
parameter ap_const_lv32_1 = 32'b00000000000000000000000000000001;
parameter ap_const_lv10_384 = 10'b1110000100;
parameter ap_const_lv10_1 = 10'b0000000001;
parameter ap_const_lv32_3B = 32'b00000000000000000000000000111011;
parameter ap_const_lv8_4 = 8'b00000100;
parameter ap_const_lv32_4 = 32'b00000000000000000000000000000100;
parameter ap_const_lv32_3C = 32'b00000000000000000000000000111100;
parameter ap_true = 1'b1;
computeUG_grp_fu_242_ACMP_fmul_90 #(
.ID( 90 ),
.NUM_STAGE( 4 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
computeUG_grp_fu_242_ACMP_fmul_90_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_242_p0 ),
.din1( grp_fu_242_p1 ),
.ce( grp_fu_242_ce ),
.dout( grp_fu_242_p2 )
);
computeUG_grp_fu_249_ACMP_fmul_91 #(
.ID( 91 ),
.NUM_STAGE( 4 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
computeUG_grp_fu_249_ACMP_fmul_91_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_249_p0 ),
.din1( grp_fu_249_p1 ),
.ce( grp_fu_249_ce ),
.dout( grp_fu_249_p2 )
);
computeUG_grp_fu_255_ACMP_fmul_92 #(
.ID( 92 ),
.NUM_STAGE( 4 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
computeUG_grp_fu_255_ACMP_fmul_92_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_255_p0 ),
.din1( grp_fu_255_p1 ),
.ce( grp_fu_255_ce ),
.dout( grp_fu_255_p2 )
);
computeUG_grp_fu_261_ACMP_fmul_93 #(
.ID( 93 ),
.NUM_STAGE( 4 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
computeUG_grp_fu_261_ACMP_fmul_93_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_261_p0 ),
.din1( grp_fu_261_p1 ),
.ce( grp_fu_261_ce ),
.dout( grp_fu_261_p2 )
);
/// ap_CS_fsm assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_CS_fsm
if (ap_rst == 1'b1) begin
ap_CS_fsm <= ap_ST_st0_fsm_0;
end else begin
ap_CS_fsm <= ap_NS_fsm;
end
end
/// ap_reg_ppiten_pp0_it0 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it0
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it0 <= ap_const_logic_0;
end else begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & ~(exitcond_fu_267_p2 == ap_const_lv1_0))) begin
ap_reg_ppiten_pp0_it0 <= ap_const_logic_0;
end else if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it0 <= ap_const_logic_1;
end
end
end
/// ap_reg_ppiten_pp0_it1 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it1
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it1 <= ap_const_logic_0;
end else begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (exitcond_fu_267_p2 == ap_const_lv1_0))) begin
ap_reg_ppiten_pp0_it1 <= ap_const_logic_1;
end else if (((ap_ST_st1_fsm_1 == ap_CS_fsm) | ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & ~(exitcond_fu_267_p2 == ap_const_lv1_0)))) begin
ap_reg_ppiten_pp0_it1 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp0_it2 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it2
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it2 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it2 <= ap_reg_ppiten_pp0_it1;
end else if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it2 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp0_it3 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it3
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it3 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it3 <= ap_reg_ppiten_pp0_it2;
end else if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it3 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp0_it4 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it4
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it4 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it4 <= ap_reg_ppiten_pp0_it3;
end else if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it4 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp0_it5 assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it5
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it5 <= ap_const_logic_0;
end else begin
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it5 <= ap_reg_ppiten_pp0_it4;
end else if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
ap_reg_ppiten_pp0_it5 <= ap_const_logic_0;
end
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond_reg_415_pp0_it1 <= exitcond_reg_415;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond_reg_415_pp0_it2 <= ap_reg_ppstg_exitcond_reg_415_pp0_it1;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond_reg_415_pp0_it3 <= ap_reg_ppstg_exitcond_reg_415_pp0_it2;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_exitcond_reg_415_pp0_it4 <= ap_reg_ppstg_exitcond_reg_415_pp0_it3;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_reg_424_pp0_it1 <= tmp_reg_424;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_reg_424_pp0_it2 <= ap_reg_ppstg_tmp_reg_424_pp0_it1;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_reg_424_pp0_it3 <= ap_reg_ppstg_tmp_reg_424_pp0_it2;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_tmp_reg_424_pp0_it4 <= ap_reg_ppstg_tmp_reg_424_pp0_it3;
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p1_addr16_cast_reg_431_pp0_it1[0] <= u_p1_addr16_cast_reg_431[0];
ap_reg_ppstg_u_p1_addr16_cast_reg_431_pp0_it1[1] <= u_p1_addr16_cast_reg_431[1];
ap_reg_ppstg_u_p1_addr16_cast_reg_431_pp0_it1[2] <= u_p1_addr16_cast_reg_431[2];
ap_reg_ppstg_u_p1_addr16_cast_reg_431_pp0_it1[3] <= u_p1_addr16_cast_reg_431[3];
ap_reg_ppstg_u_p1_addr16_cast_reg_431_pp0_it1[4] <= u_p1_addr16_cast_reg_431[4];
ap_reg_ppstg_u_p1_addr16_cast_reg_431_pp0_it1[5] <= u_p1_addr16_cast_reg_431[5];
ap_reg_ppstg_u_p1_addr16_cast_reg_431_pp0_it1[6] <= u_p1_addr16_cast_reg_431[6];
ap_reg_ppstg_u_p1_addr16_cast_reg_431_pp0_it1[7] <= u_p1_addr16_cast_reg_431[7];
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p1_addr16_cast_reg_431_pp0_it2[0] <= ap_reg_ppstg_u_p1_addr16_cast_reg_431_pp0_it1[0];
ap_reg_ppstg_u_p1_addr16_cast_reg_431_pp0_it2[1] <= ap_reg_ppstg_u_p1_addr16_cast_reg_431_pp0_it1[1];
ap_reg_ppstg_u_p1_addr16_cast_reg_431_pp0_it2[2] <= ap_reg_ppstg_u_p1_addr16_cast_reg_431_pp0_it1[2];
ap_reg_ppstg_u_p1_addr16_cast_reg_431_pp0_it2[3] <= ap_reg_ppstg_u_p1_addr16_cast_reg_431_pp0_it1[3];
ap_reg_ppstg_u_p1_addr16_cast_reg_431_pp0_it2[4] <= ap_reg_ppstg_u_p1_addr16_cast_reg_431_pp0_it1[4];
ap_reg_ppstg_u_p1_addr16_cast_reg_431_pp0_it2[5] <= ap_reg_ppstg_u_p1_addr16_cast_reg_431_pp0_it1[5];
ap_reg_ppstg_u_p1_addr16_cast_reg_431_pp0_it2[6] <= ap_reg_ppstg_u_p1_addr16_cast_reg_431_pp0_it1[6];
ap_reg_ppstg_u_p1_addr16_cast_reg_431_pp0_it2[7] <= ap_reg_ppstg_u_p1_addr16_cast_reg_431_pp0_it1[7];
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p1_addr16_cast_reg_431_pp0_it3[0] <= ap_reg_ppstg_u_p1_addr16_cast_reg_431_pp0_it2[0];
ap_reg_ppstg_u_p1_addr16_cast_reg_431_pp0_it3[1] <= ap_reg_ppstg_u_p1_addr16_cast_reg_431_pp0_it2[1];
ap_reg_ppstg_u_p1_addr16_cast_reg_431_pp0_it3[2] <= ap_reg_ppstg_u_p1_addr16_cast_reg_431_pp0_it2[2];
ap_reg_ppstg_u_p1_addr16_cast_reg_431_pp0_it3[3] <= ap_reg_ppstg_u_p1_addr16_cast_reg_431_pp0_it2[3];
ap_reg_ppstg_u_p1_addr16_cast_reg_431_pp0_it3[4] <= ap_reg_ppstg_u_p1_addr16_cast_reg_431_pp0_it2[4];
ap_reg_ppstg_u_p1_addr16_cast_reg_431_pp0_it3[5] <= ap_reg_ppstg_u_p1_addr16_cast_reg_431_pp0_it2[5];
ap_reg_ppstg_u_p1_addr16_cast_reg_431_pp0_it3[6] <= ap_reg_ppstg_u_p1_addr16_cast_reg_431_pp0_it2[6];
ap_reg_ppstg_u_p1_addr16_cast_reg_431_pp0_it3[7] <= ap_reg_ppstg_u_p1_addr16_cast_reg_431_pp0_it2[7];
end
if ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm)) begin
ap_reg_ppstg_u_p1_addr16_cast_reg_431_pp0_it4[0] <= ap_reg_ppstg_u_p1_addr16_cast_reg_431_pp0_it3[0];
ap_reg_ppstg_u_p1_addr16_cast_reg_431_pp0_it4[1] <= ap_reg_ppstg_u_p1_addr16_cast_reg_431_pp0_it3[1];
ap_reg_ppstg_u_p1_addr16_cast_reg_431_pp0_it4[2] <= ap_reg_ppstg_u_p1_addr16_cast_reg_431_pp0_it3[2];
ap_reg_ppstg_u_p1_addr16_cast_reg_431_pp0_it4[3] <= ap_reg_ppstg_u_p1_addr16_cast_reg_431_pp0_it3[3];
ap_reg_ppstg_u_p1_addr16_cast_reg_431_pp0_it4[4] <= ap_reg_ppstg_u_p1_addr16_cast_reg_431_pp0_it3[4];
ap_reg_ppstg_u_p1_addr16_cast_reg_431_pp0_it4[5] <= ap_reg_ppstg_u_p1_addr16_cast_reg_431_pp0_it3[5];
ap_reg_ppstg_u_p1_addr16_cast_reg_431_pp0_it4[6] <= ap_reg_ppstg_u_p1_addr16_cast_reg_431_pp0_it3[6];
ap_reg_ppstg_u_p1_addr16_cast_reg_431_pp0_it4[7] <= ap_reg_ppstg_u_p1_addr16_cast_reg_431_pp0_it3[7];
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0))) begin
exitcond_reg_415 <= (k_phi_fu_212_p4 == exitcond_fu_267_p1? 1'b1: 1'b0);
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (exitcond_reg_415 == ap_const_lv1_0))) begin
i_1_reg_230 <= i_reg_464;
end else if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
i_1_reg_230 <= ap_const_lv32_0;
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_fu_267_p2 == ap_const_lv1_0))) begin
if (tmp6_fu_324_p2) begin
i_reg_464 <= tmp7_fu_330_p2;
end else begin
i_reg_464 <= i_1_phi_fu_234_p4;
end
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0))) begin
indvar_next_reg_419 <= (k_phi_fu_212_p4 + ap_const_lv10_1);
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_fu_267_p2 == ap_const_lv1_0))) begin
if (tmp6_fu_324_p2) begin
j_1_reg_459 <= ap_const_lv32_0;
end else begin
j_1_reg_459 <= tmp5_fu_318_p2;
end
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (exitcond_reg_415 == ap_const_lv1_0))) begin
j_reg_219 <= j_1_reg_459;
end else if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
j_reg_219 <= ap_const_lv32_0;
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (exitcond_reg_415 == ap_const_lv1_0))) begin
k_reg_208 <= indvar_next_reg_419;
end else if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
k_reg_208 <= ap_const_lv10_0;
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_fu_267_p2 == ap_const_lv1_0))) begin
tmp_reg_424 <= ($signed(j_phi_fu_223_p4) > $signed(tmp_fu_283_p1)? 1'b1: 1'b0);
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (exitcond_reg_415 == ap_const_lv1_0))) begin
if (tmp_reg_424) begin
u_Local01_1_fu_60 <= u_Local01_1_fu_60;
end else begin
u_Local01_1_fu_60 <= u_p1_q0;
end
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (exitcond_reg_415 == ap_const_lv1_0))) begin
if (tmp_reg_424) begin
u_Local02_1_fu_56 <= u_Local02_1_fu_56;
end else begin
u_Local02_1_fu_56 <= u_p2_q0;
end
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (exitcond_reg_415 == ap_const_lv1_0))) begin
if (tmp_reg_424) begin
u_Local03_1_fu_52 <= u_Local03_1_fu_52;
end else begin
u_Local03_1_fu_52 <= u_p3_q0;
end
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (exitcond_reg_415 == ap_const_lv1_0))) begin
if (tmp_reg_424) begin
u_Local1_reg_474 <= u_Local02_1_fu_56;
end else begin
u_Local1_reg_474 <= u_p2_q0;
end
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (exitcond_reg_415 == ap_const_lv1_0))) begin
if (tmp_reg_424) begin
u_Local2_reg_479 <= u_Local03_1_fu_52;
end else begin
u_Local2_reg_479 <= u_p3_q0;
end
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (exitcond_reg_415 == ap_const_lv1_0))) begin
if (tmp_reg_424) begin
u_Local_reg_469 <= u_Local01_1_fu_60;
end else begin
u_Local_reg_469 <= u_p1_q0;
end
end
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_fu_267_p2 == ap_const_lv1_0))) begin
u_p1_addr16_cast_reg_431[0] <= u_p1_addr16_cast_fu_311_p1[0];
u_p1_addr16_cast_reg_431[1] <= u_p1_addr16_cast_fu_311_p1[1];
u_p1_addr16_cast_reg_431[2] <= u_p1_addr16_cast_fu_311_p1[2];
u_p1_addr16_cast_reg_431[3] <= u_p1_addr16_cast_fu_311_p1[3];
u_p1_addr16_cast_reg_431[4] <= u_p1_addr16_cast_fu_311_p1[4];
u_p1_addr16_cast_reg_431[5] <= u_p1_addr16_cast_fu_311_p1[5];
u_p1_addr16_cast_reg_431[6] <= u_p1_addr16_cast_fu_311_p1[6];
u_p1_addr16_cast_reg_431[7] <= u_p1_addr16_cast_fu_311_p1[7];
end
end
/// ap_NS_fsm assign process. ///
always @ (ap_start or ap_CS_fsm or exitcond_fu_267_p2 or ap_reg_ppiten_pp0_it0 or ap_reg_ppiten_pp0_it1 or ap_reg_ppiten_pp0_it4 or ap_reg_ppiten_pp0_it5)
begin
if ((((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it5) & ~(ap_const_logic_1 == ap_reg_ppiten_pp0_it4)) | ((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ~(exitcond_fu_267_p2 == ap_const_lv1_0) & ~(ap_const_logic_1 == ap_reg_ppiten_pp0_it1)))) begin
ap_NS_fsm = ap_ST_st8_fsm_3;
end else if ((~(ap_const_logic_1 == ap_start) & (ap_ST_st8_fsm_3 == ap_CS_fsm))) begin
ap_NS_fsm = ap_ST_st0_fsm_0;
end else if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_pp0_stg0_fsm_2;
end else if ((((ap_ST_st0_fsm_0 == ap_CS_fsm) & (ap_const_logic_1 == ap_start)) | ((ap_const_logic_1 == ap_start) & (ap_ST_st8_fsm_3 == ap_CS_fsm)))) begin
ap_NS_fsm = ap_ST_st1_fsm_1;
end else begin
ap_NS_fsm = ap_CS_fsm;
end
end
/// ap_done assign process. ///
always @ (ap_CS_fsm)
begin
if (((ap_ST_st0_fsm_0 == ap_CS_fsm) | (ap_ST_st8_fsm_3 == ap_CS_fsm))) begin
ap_done = ap_const_logic_1;
end else begin
ap_done = ap_const_logic_0;
end
end
/// ap_idle assign process. ///
always @ (ap_CS_fsm)
begin
if ((ap_ST_st0_fsm_0 == ap_CS_fsm)) begin
ap_idle = ap_const_logic_1;
end else begin
ap_idle = ap_const_logic_0;
end
end
/// g_p0_ce0 assign process. ///
always @ (ap_CS_fsm or exitcond_reg_415 or ap_reg_ppiten_pp0_it1 or tmp_reg_424)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (exitcond_reg_415 == ap_const_lv1_0) & (tmp_reg_424 == ap_const_lv1_0))) begin
g_p0_ce0 = ap_const_logic_1;
end else begin
g_p0_ce0 = ap_const_logic_0;
end
end
/// g_p1_ce0 assign process. ///
always @ (ap_CS_fsm or exitcond_reg_415 or ap_reg_ppiten_pp0_it1 or tmp_reg_424)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (exitcond_reg_415 == ap_const_lv1_0) & (tmp_reg_424 == ap_const_lv1_0))) begin
g_p1_ce0 = ap_const_logic_1;
end else begin
g_p1_ce0 = ap_const_logic_0;
end
end
/// g_p2_ce0 assign process. ///
always @ (ap_CS_fsm or exitcond_reg_415 or ap_reg_ppiten_pp0_it1 or tmp_reg_424)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (exitcond_reg_415 == ap_const_lv1_0) & (tmp_reg_424 == ap_const_lv1_0))) begin
g_p2_ce0 = ap_const_logic_1;
end else begin
g_p2_ce0 = ap_const_logic_0;
end
end
/// g_p3_ce0 assign process. ///
always @ (ap_CS_fsm or exitcond_reg_415 or ap_reg_ppiten_pp0_it1 or tmp_reg_424)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (exitcond_reg_415 == ap_const_lv1_0) & (tmp_reg_424 == ap_const_lv1_0))) begin
g_p3_ce0 = ap_const_logic_1;
end else begin
g_p3_ce0 = ap_const_logic_0;
end
end
/// i_1_phi_fu_234_p4 assign process. ///
always @ (ap_CS_fsm or i_1_reg_230 or exitcond_reg_415 or ap_reg_ppiten_pp0_it1 or i_reg_464)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (exitcond_reg_415 == ap_const_lv1_0))) begin
i_1_phi_fu_234_p4 = i_reg_464;
end else begin
i_1_phi_fu_234_p4 = i_1_reg_230;
end
end
/// j_phi_fu_223_p4 assign process. ///
always @ (ap_CS_fsm or j_reg_219 or exitcond_reg_415 or ap_reg_ppiten_pp0_it1 or j_1_reg_459)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (exitcond_reg_415 == ap_const_lv1_0))) begin
j_phi_fu_223_p4 = j_1_reg_459;
end else begin
j_phi_fu_223_p4 = j_reg_219;
end
end
/// k_phi_fu_212_p4 assign process. ///
always @ (ap_CS_fsm or k_reg_208 or exitcond_reg_415 or ap_reg_ppiten_pp0_it1 or indvar_next_reg_419)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (exitcond_reg_415 == ap_const_lv1_0))) begin
k_phi_fu_212_p4 = indvar_next_reg_419;
end else begin
k_phi_fu_212_p4 = k_reg_208;
end
end
/// u_p0_ce0 assign process. ///
always @ (ap_CS_fsm or exitcond_reg_415 or ap_reg_ppiten_pp0_it1 or tmp_reg_424)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (exitcond_reg_415 == ap_const_lv1_0) & (tmp_reg_424 == ap_const_lv1_0))) begin
u_p0_ce0 = ap_const_logic_1;
end else begin
u_p0_ce0 = ap_const_logic_0;
end
end
/// u_p1_ce0 assign process. ///
always @ (ap_CS_fsm or exitcond_fu_267_p2 or ap_reg_ppiten_pp0_it0)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_fu_267_p2 == ap_const_lv1_0))) begin
u_p1_ce0 = ap_const_logic_1;
end else begin
u_p1_ce0 = ap_const_logic_0;
end
end
/// u_p2_ce0 assign process. ///
always @ (ap_CS_fsm or exitcond_fu_267_p2 or ap_reg_ppiten_pp0_it0)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_fu_267_p2 == ap_const_lv1_0))) begin
u_p2_ce0 = ap_const_logic_1;
end else begin
u_p2_ce0 = ap_const_logic_0;
end
end
/// u_p3_ce0 assign process. ///
always @ (ap_CS_fsm or exitcond_fu_267_p2 or ap_reg_ppiten_pp0_it0)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond_fu_267_p2 == ap_const_lv1_0))) begin
u_p3_ce0 = ap_const_logic_1;
end else begin
u_p3_ce0 = ap_const_logic_0;
end
end
/// ug_p0_ce0 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp0_it5 or ap_reg_ppstg_exitcond_reg_415_pp0_it4 or ap_reg_ppstg_tmp_reg_424_pp0_it4)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it5) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_reg_424_pp0_it4) & (ap_reg_ppstg_exitcond_reg_415_pp0_it4 == ap_const_lv1_0))) begin
ug_p0_ce0 = ap_const_logic_1;
end else begin
ug_p0_ce0 = ap_const_logic_0;
end
end
/// ug_p0_we0 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp0_it5 or ap_reg_ppstg_exitcond_reg_415_pp0_it4 or ap_reg_ppstg_tmp_reg_424_pp0_it4)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it5) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_reg_424_pp0_it4) & (ap_reg_ppstg_exitcond_reg_415_pp0_it4 == ap_const_lv1_0))) begin
ug_p0_we0 = ap_const_logic_1;
end else begin
ug_p0_we0 = ap_const_logic_0;
end
end
/// ug_p1_ce0 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp0_it5 or ap_reg_ppstg_exitcond_reg_415_pp0_it4 or ap_reg_ppstg_tmp_reg_424_pp0_it4)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it5) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_reg_424_pp0_it4) & (ap_reg_ppstg_exitcond_reg_415_pp0_it4 == ap_const_lv1_0))) begin
ug_p1_ce0 = ap_const_logic_1;
end else begin
ug_p1_ce0 = ap_const_logic_0;
end
end
/// ug_p1_we0 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp0_it5 or ap_reg_ppstg_exitcond_reg_415_pp0_it4 or ap_reg_ppstg_tmp_reg_424_pp0_it4)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it5) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_reg_424_pp0_it4) & (ap_reg_ppstg_exitcond_reg_415_pp0_it4 == ap_const_lv1_0))) begin
ug_p1_we0 = ap_const_logic_1;
end else begin
ug_p1_we0 = ap_const_logic_0;
end
end
/// ug_p2_ce0 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp0_it5 or ap_reg_ppstg_exitcond_reg_415_pp0_it4 or ap_reg_ppstg_tmp_reg_424_pp0_it4)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it5) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_reg_424_pp0_it4) & (ap_reg_ppstg_exitcond_reg_415_pp0_it4 == ap_const_lv1_0))) begin
ug_p2_ce0 = ap_const_logic_1;
end else begin
ug_p2_ce0 = ap_const_logic_0;
end
end
/// ug_p2_we0 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp0_it5 or ap_reg_ppstg_exitcond_reg_415_pp0_it4 or ap_reg_ppstg_tmp_reg_424_pp0_it4)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it5) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_reg_424_pp0_it4) & (ap_reg_ppstg_exitcond_reg_415_pp0_it4 == ap_const_lv1_0))) begin
ug_p2_we0 = ap_const_logic_1;
end else begin
ug_p2_we0 = ap_const_logic_0;
end
end
/// ug_p3_ce0 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp0_it5 or ap_reg_ppstg_exitcond_reg_415_pp0_it4 or ap_reg_ppstg_tmp_reg_424_pp0_it4)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it5) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_reg_424_pp0_it4) & (ap_reg_ppstg_exitcond_reg_415_pp0_it4 == ap_const_lv1_0))) begin
ug_p3_ce0 = ap_const_logic_1;
end else begin
ug_p3_ce0 = ap_const_logic_0;
end
end
/// ug_p3_we0 assign process. ///
always @ (ap_CS_fsm or ap_reg_ppiten_pp0_it5 or ap_reg_ppstg_exitcond_reg_415_pp0_it4 or ap_reg_ppstg_tmp_reg_424_pp0_it4)
begin
if (((ap_ST_pp0_stg0_fsm_2 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it5) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_reg_424_pp0_it4) & (ap_reg_ppstg_exitcond_reg_415_pp0_it4 == ap_const_lv1_0))) begin
ug_p3_we0 = ap_const_logic_1;
end else begin
ug_p3_we0 = ap_const_logic_0;
end
end
assign exitcond_fu_267_p1 = ap_const_lv10_384;
assign exitcond_fu_267_p2 = (k_phi_fu_212_p4 == exitcond_fu_267_p1? 1'b1: 1'b0);
assign g_p0_address0 = u_p1_addr16_cast_reg_431;
assign g_p1_address0 = u_p1_addr16_cast_reg_431;
assign g_p2_address0 = u_p1_addr16_cast_reg_431;
assign g_p3_address0 = u_p1_addr16_cast_reg_431;
assign grp_fu_242_ce = ap_const_logic_1;
assign grp_fu_242_p0 = g_p0_q0;
assign grp_fu_242_p1 = u_p0_q0;
assign grp_fu_249_ce = ap_const_logic_1;
assign grp_fu_249_p0 = g_p1_q0;
assign grp_fu_249_p1 = u_Local_reg_469;
assign grp_fu_255_ce = ap_const_logic_1;
assign grp_fu_255_p0 = g_p2_q0;
assign grp_fu_255_p1 = u_Local1_reg_474;
assign grp_fu_261_ce = ap_const_logic_1;
assign grp_fu_261_p0 = g_p3_q0;
assign grp_fu_261_p1 = u_Local2_reg_479;
assign i_1_cast_fu_289_p1 = i_1_phi_fu_234_p4[7:0];
assign j_cast_fu_279_p1 = j_phi_fu_223_p4[7:0];
assign p_shl_fu_293_p2 = i_1_cast_fu_289_p1 << ap_const_lv8_4;
assign tmp5_fu_318_p2 = (j_phi_fu_223_p4 + ap_const_lv32_4);
assign tmp6_fu_324_p1 = ap_const_lv32_3C;
assign tmp6_fu_324_p2 = (tmp5_fu_318_p2 == tmp6_fu_324_p1? 1'b1: 1'b0);
assign tmp7_fu_330_p2 = (i_1_phi_fu_234_p4 + ap_const_lv32_1);
assign tmp_fu_283_p1 = ap_const_lv32_3B;
assign u_p0_address0 = u_p1_addr16_cast_reg_431;
assign u_p1_addr16_cast_fu_311_p1 = {{24{1'b0}}, {u_p1_addr_fu_305_p2}};
assign u_p1_addr_cast_fu_299_p2 = (p_shl_fu_293_p2 - i_1_cast_fu_289_p1);
assign u_p1_addr_fu_305_p2 = (u_p1_addr_cast_fu_299_p2 + j_cast_fu_279_p1);
assign u_p1_address0 = u_p1_addr16_cast_fu_311_p1;
assign u_p2_address0 = u_p1_addr16_cast_fu_311_p1;
assign u_p3_address0 = u_p1_addr16_cast_fu_311_p1;
assign ug_p0_address0 = ap_reg_ppstg_u_p1_addr16_cast_reg_431_pp0_it4;
assign ug_p0_d0 = grp_fu_242_p2;
assign ug_p1_address0 = ap_reg_ppstg_u_p1_addr16_cast_reg_431_pp0_it4;
assign ug_p1_d0 = grp_fu_249_p2;
assign ug_p2_address0 = ap_reg_ppstg_u_p1_addr16_cast_reg_431_pp0_it4;
assign ug_p2_d0 = grp_fu_255_p2;
assign ug_p3_address0 = ap_reg_ppstg_u_p1_addr16_cast_reg_431_pp0_it4;
assign ug_p3_d0 = grp_fu_261_p2;
always @ (ap_clk)
begin
u_p1_addr16_cast_reg_431[8] <= 1'b0;
u_p1_addr16_cast_reg_431[9] <= 1'b0;
u_p1_addr16_cast_reg_431[10] <= 1'b0;
u_p1_addr16_cast_reg_431[11] <= 1'b0;
u_p1_addr16_cast_reg_431[12] <= 1'b0;
u_p1_addr16_cast_reg_431[13] <= 1'b0;
u_p1_addr16_cast_reg_431[14] <= 1'b0;
u_p1_addr16_cast_reg_431[15] <= 1'b0;
u_p1_addr16_cast_reg_431[16] <= 1'b0;
u_p1_addr16_cast_reg_431[17] <= 1'b0;
u_p1_addr16_cast_reg_431[18] <= 1'b0;
u_p1_addr16_cast_reg_431[19] <= 1'b0;
u_p1_addr16_cast_reg_431[20] <= 1'b0;
u_p1_addr16_cast_reg_431[21] <= 1'b0;
u_p1_addr16_cast_reg_431[22] <= 1'b0;
u_p1_addr16_cast_reg_431[23] <= 1'b0;
u_p1_addr16_cast_reg_431[24] <= 1'b0;
u_p1_addr16_cast_reg_431[25] <= 1'b0;
u_p1_addr16_cast_reg_431[26] <= 1'b0;
u_p1_addr16_cast_reg_431[27] <= 1'b0;
u_p1_addr16_cast_reg_431[28] <= 1'b0;
u_p1_addr16_cast_reg_431[29] <= 1'b0;
u_p1_addr16_cast_reg_431[30] <= 1'b0;
u_p1_addr16_cast_reg_431[31] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_u_p1_addr16_cast_reg_431_pp0_it1[8] <= 1'b0;
ap_reg_ppstg_u_p1_addr16_cast_reg_431_pp0_it1[9] <= 1'b0;
ap_reg_ppstg_u_p1_addr16_cast_reg_431_pp0_it1[10] <= 1'b0;
ap_reg_ppstg_u_p1_addr16_cast_reg_431_pp0_it1[11] <= 1'b0;
ap_reg_ppstg_u_p1_addr16_cast_reg_431_pp0_it1[12] <= 1'b0;
ap_reg_ppstg_u_p1_addr16_cast_reg_431_pp0_it1[13] <= 1'b0;
ap_reg_ppstg_u_p1_addr16_cast_reg_431_pp0_it1[14] <= 1'b0;
ap_reg_ppstg_u_p1_addr16_cast_reg_431_pp0_it1[15] <= 1'b0;
ap_reg_ppstg_u_p1_addr16_cast_reg_431_pp0_it1[16] <= 1'b0;
ap_reg_ppstg_u_p1_addr16_cast_reg_431_pp0_it1[17] <= 1'b0;
ap_reg_ppstg_u_p1_addr16_cast_reg_431_pp0_it1[18] <= 1'b0;
ap_reg_ppstg_u_p1_addr16_cast_reg_431_pp0_it1[19] <= 1'b0;
ap_reg_ppstg_u_p1_addr16_cast_reg_431_pp0_it1[20] <= 1'b0;
ap_reg_ppstg_u_p1_addr16_cast_reg_431_pp0_it1[21] <= 1'b0;
ap_reg_ppstg_u_p1_addr16_cast_reg_431_pp0_it1[22] <= 1'b0;
ap_reg_ppstg_u_p1_addr16_cast_reg_431_pp0_it1[23] <= 1'b0;
ap_reg_ppstg_u_p1_addr16_cast_reg_431_pp0_it1[24] <= 1'b0;
ap_reg_ppstg_u_p1_addr16_cast_reg_431_pp0_it1[25] <= 1'b0;
ap_reg_ppstg_u_p1_addr16_cast_reg_431_pp0_it1[26] <= 1'b0;
ap_reg_ppstg_u_p1_addr16_cast_reg_431_pp0_it1[27] <= 1'b0;
ap_reg_ppstg_u_p1_addr16_cast_reg_431_pp0_it1[28] <= 1'b0;
ap_reg_ppstg_u_p1_addr16_cast_reg_431_pp0_it1[29] <= 1'b0;
ap_reg_ppstg_u_p1_addr16_cast_reg_431_pp0_it1[30] <= 1'b0;
ap_reg_ppstg_u_p1_addr16_cast_reg_431_pp0_it1[31] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_u_p1_addr16_cast_reg_431_pp0_it2[8] <= 1'b0;
ap_reg_ppstg_u_p1_addr16_cast_reg_431_pp0_it2[9] <= 1'b0;
ap_reg_ppstg_u_p1_addr16_cast_reg_431_pp0_it2[10] <= 1'b0;
ap_reg_ppstg_u_p1_addr16_cast_reg_431_pp0_it2[11] <= 1'b0;
ap_reg_ppstg_u_p1_addr16_cast_reg_431_pp0_it2[12] <= 1'b0;
ap_reg_ppstg_u_p1_addr16_cast_reg_431_pp0_it2[13] <= 1'b0;
ap_reg_ppstg_u_p1_addr16_cast_reg_431_pp0_it2[14] <= 1'b0;
ap_reg_ppstg_u_p1_addr16_cast_reg_431_pp0_it2[15] <= 1'b0;
ap_reg_ppstg_u_p1_addr16_cast_reg_431_pp0_it2[16] <= 1'b0;
ap_reg_ppstg_u_p1_addr16_cast_reg_431_pp0_it2[17] <= 1'b0;
ap_reg_ppstg_u_p1_addr16_cast_reg_431_pp0_it2[18] <= 1'b0;
ap_reg_ppstg_u_p1_addr16_cast_reg_431_pp0_it2[19] <= 1'b0;
ap_reg_ppstg_u_p1_addr16_cast_reg_431_pp0_it2[20] <= 1'b0;
ap_reg_ppstg_u_p1_addr16_cast_reg_431_pp0_it2[21] <= 1'b0;
ap_reg_ppstg_u_p1_addr16_cast_reg_431_pp0_it2[22] <= 1'b0;
ap_reg_ppstg_u_p1_addr16_cast_reg_431_pp0_it2[23] <= 1'b0;
ap_reg_ppstg_u_p1_addr16_cast_reg_431_pp0_it2[24] <= 1'b0;
ap_reg_ppstg_u_p1_addr16_cast_reg_431_pp0_it2[25] <= 1'b0;
ap_reg_ppstg_u_p1_addr16_cast_reg_431_pp0_it2[26] <= 1'b0;
ap_reg_ppstg_u_p1_addr16_cast_reg_431_pp0_it2[27] <= 1'b0;
ap_reg_ppstg_u_p1_addr16_cast_reg_431_pp0_it2[28] <= 1'b0;
ap_reg_ppstg_u_p1_addr16_cast_reg_431_pp0_it2[29] <= 1'b0;
ap_reg_ppstg_u_p1_addr16_cast_reg_431_pp0_it2[30] <= 1'b0;
ap_reg_ppstg_u_p1_addr16_cast_reg_431_pp0_it2[31] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_u_p1_addr16_cast_reg_431_pp0_it3[8] <= 1'b0;
ap_reg_ppstg_u_p1_addr16_cast_reg_431_pp0_it3[9] <= 1'b0;
ap_reg_ppstg_u_p1_addr16_cast_reg_431_pp0_it3[10] <= 1'b0;
ap_reg_ppstg_u_p1_addr16_cast_reg_431_pp0_it3[11] <= 1'b0;
ap_reg_ppstg_u_p1_addr16_cast_reg_431_pp0_it3[12] <= 1'b0;
ap_reg_ppstg_u_p1_addr16_cast_reg_431_pp0_it3[13] <= 1'b0;
ap_reg_ppstg_u_p1_addr16_cast_reg_431_pp0_it3[14] <= 1'b0;
ap_reg_ppstg_u_p1_addr16_cast_reg_431_pp0_it3[15] <= 1'b0;
ap_reg_ppstg_u_p1_addr16_cast_reg_431_pp0_it3[16] <= 1'b0;
ap_reg_ppstg_u_p1_addr16_cast_reg_431_pp0_it3[17] <= 1'b0;
ap_reg_ppstg_u_p1_addr16_cast_reg_431_pp0_it3[18] <= 1'b0;
ap_reg_ppstg_u_p1_addr16_cast_reg_431_pp0_it3[19] <= 1'b0;
ap_reg_ppstg_u_p1_addr16_cast_reg_431_pp0_it3[20] <= 1'b0;
ap_reg_ppstg_u_p1_addr16_cast_reg_431_pp0_it3[21] <= 1'b0;
ap_reg_ppstg_u_p1_addr16_cast_reg_431_pp0_it3[22] <= 1'b0;
ap_reg_ppstg_u_p1_addr16_cast_reg_431_pp0_it3[23] <= 1'b0;
ap_reg_ppstg_u_p1_addr16_cast_reg_431_pp0_it3[24] <= 1'b0;
ap_reg_ppstg_u_p1_addr16_cast_reg_431_pp0_it3[25] <= 1'b0;
ap_reg_ppstg_u_p1_addr16_cast_reg_431_pp0_it3[26] <= 1'b0;
ap_reg_ppstg_u_p1_addr16_cast_reg_431_pp0_it3[27] <= 1'b0;
ap_reg_ppstg_u_p1_addr16_cast_reg_431_pp0_it3[28] <= 1'b0;
ap_reg_ppstg_u_p1_addr16_cast_reg_431_pp0_it3[29] <= 1'b0;
ap_reg_ppstg_u_p1_addr16_cast_reg_431_pp0_it3[30] <= 1'b0;
ap_reg_ppstg_u_p1_addr16_cast_reg_431_pp0_it3[31] <= 1'b0;
end
always @ (ap_clk)
begin
ap_reg_ppstg_u_p1_addr16_cast_reg_431_pp0_it4[8] <= 1'b0;
ap_reg_ppstg_u_p1_addr16_cast_reg_431_pp0_it4[9] <= 1'b0;
ap_reg_ppstg_u_p1_addr16_cast_reg_431_pp0_it4[10] <= 1'b0;
ap_reg_ppstg_u_p1_addr16_cast_reg_431_pp0_it4[11] <= 1'b0;
ap_reg_ppstg_u_p1_addr16_cast_reg_431_pp0_it4[12] <= 1'b0;
ap_reg_ppstg_u_p1_addr16_cast_reg_431_pp0_it4[13] <= 1'b0;
ap_reg_ppstg_u_p1_addr16_cast_reg_431_pp0_it4[14] <= 1'b0;
ap_reg_ppstg_u_p1_addr16_cast_reg_431_pp0_it4[15] <= 1'b0;
ap_reg_ppstg_u_p1_addr16_cast_reg_431_pp0_it4[16] <= 1'b0;
ap_reg_ppstg_u_p1_addr16_cast_reg_431_pp0_it4[17] <= 1'b0;
ap_reg_ppstg_u_p1_addr16_cast_reg_431_pp0_it4[18] <= 1'b0;
ap_reg_ppstg_u_p1_addr16_cast_reg_431_pp0_it4[19] <= 1'b0;
ap_reg_ppstg_u_p1_addr16_cast_reg_431_pp0_it4[20] <= 1'b0;
ap_reg_ppstg_u_p1_addr16_cast_reg_431_pp0_it4[21] <= 1'b0;
ap_reg_ppstg_u_p1_addr16_cast_reg_431_pp0_it4[22] <= 1'b0;
ap_reg_ppstg_u_p1_addr16_cast_reg_431_pp0_it4[23] <= 1'b0;
ap_reg_ppstg_u_p1_addr16_cast_reg_431_pp0_it4[24] <= 1'b0;
ap_reg_ppstg_u_p1_addr16_cast_reg_431_pp0_it4[25] <= 1'b0;
ap_reg_ppstg_u_p1_addr16_cast_reg_431_pp0_it4[26] <= 1'b0;
ap_reg_ppstg_u_p1_addr16_cast_reg_431_pp0_it4[27] <= 1'b0;
ap_reg_ppstg_u_p1_addr16_cast_reg_431_pp0_it4[28] <= 1'b0;
ap_reg_ppstg_u_p1_addr16_cast_reg_431_pp0_it4[29] <= 1'b0;
ap_reg_ppstg_u_p1_addr16_cast_reg_431_pp0_it4[30] <= 1'b0;
ap_reg_ppstg_u_p1_addr16_cast_reg_431_pp0_it4[31] <= 1'b0;
end
endmodule //computeUG
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
module computeUG_grp_fu_242_ACMP_fmul_90(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fmul #(
.ID( ID ),
.NUM_STAGE( 4 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fmul_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
module computeUG_grp_fu_249_ACMP_fmul_91(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fmul #(
.ID( ID ),
.NUM_STAGE( 4 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fmul_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
module computeUG_grp_fu_255_ACMP_fmul_92(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fmul #(
.ID( ID ),
.NUM_STAGE( 4 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fmul_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
module computeUG_grp_fu_261_ACMP_fmul_93(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
ACMP_fmul #(
.ID( ID ),
.NUM_STAGE( 4 ),
.din0_WIDTH( din0_WIDTH ),
.din1_WIDTH( din1_WIDTH ),
.dout_WIDTH( dout_WIDTH ))
ACMP_fmul_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.din0( din0 ),
.din1( din1 ),
.dout( dout ));
endmodule
|
// ==============================================================
// RTL generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ===========================================================
`timescale 1 ns / 1 ps
module denoise (
ap_clk,
ap_rst,
ap_start,
ap_done,
ap_idle,
uReadBus_req_din,
uReadBus_req_full_n,
uReadBus_req_write,
uReadBus_rsp_dout,
uReadBus_rsp_empty_n,
uReadBus_rsp_read,
uReadBus_address,
uReadBus_datain,
uReadBus_dataout,
uReadBus_size,
fReadBus_req_din,
fReadBus_req_full_n,
fReadBus_req_write,
fReadBus_rsp_dout,
fReadBus_rsp_empty_n,
fReadBus_rsp_read,
fReadBus_address,
fReadBus_datain,
fReadBus_dataout,
fReadBus_size,
writeBus_req_din,
writeBus_req_full_n,
writeBus_req_write,
writeBus_rsp_dout,
writeBus_rsp_empty_n,
writeBus_rsp_read,
writeBus_address,
writeBus_datain,
writeBus_dataout,
writeBus_size,
ap_return
);
input ap_clk;
input ap_rst;
input ap_start;
output ap_done;
output ap_idle;
output uReadBus_req_din;
input uReadBus_req_full_n;
output uReadBus_req_write;
input uReadBus_rsp_dout;
input uReadBus_rsp_empty_n;
output uReadBus_rsp_read;
output [31:0] uReadBus_address;
input [127:0] uReadBus_datain;
output [127:0] uReadBus_dataout;
output [31:0] uReadBus_size;
output fReadBus_req_din;
input fReadBus_req_full_n;
output fReadBus_req_write;
input fReadBus_rsp_dout;
input fReadBus_rsp_empty_n;
output fReadBus_rsp_read;
output [31:0] fReadBus_address;
input [127:0] fReadBus_datain;
output [127:0] fReadBus_dataout;
output [31:0] fReadBus_size;
output writeBus_req_din;
input writeBus_req_full_n;
output writeBus_req_write;
input writeBus_rsp_dout;
input writeBus_rsp_empty_n;
output writeBus_rsp_read;
output [31:0] writeBus_address;
input [127:0] writeBus_datain;
output [127:0] writeBus_dataout;
output [31:0] writeBus_size;
output [0:0] ap_return;
reg ap_done;
reg ap_idle;
reg [7:0] ap_CS_fsm;
wire [0:0] grp_computeResult_fu_467_ap_return;
reg [0:0] empty_2_reg_900;
wire grp_uFetch_array_fu_583_ap_done;
wire grp_computeDiffSqr_fu_531_ap_done;
wire grp_computeGradient_fu_507_ap_done;
wire grp_computeUG_fu_555_ap_done;
wire grp_computeResult_fu_467_ap_done;
reg [0:0] empty_3_reg_905;
wire grp_write_array_fu_571_ap_done;
wire grp_fFetch_array_fu_599_ap_done;
reg [0:0] tmp1_reg_910;
reg [0:0] empty_5_reg_915;
reg [0:0] tmp2_reg_920;
reg [0:0] empty_7_reg_925;
reg [0:0] tmp5_reg_930;
reg [0:0] empty_9_reg_935;
reg [0:0] empty_10_reg_940;
reg [0:0] tmp7_reg_945;
reg [0:0] empty_12_reg_950;
reg [0:0] tmp8_reg_955;
reg [0:0] empty_14_reg_960;
reg [0:0] tmp12_reg_965;
reg [0:0] empty_16_reg_970;
reg [0:0] empty_17_reg_975;
reg [0:0] tmp14_reg_980;
reg [0:0] empty_19_reg_985;
reg [0:0] tmp15_reg_990;
reg [0:0] empty_21_reg_995;
reg [0:0] tmp18_reg_1000;
reg [0:0] empty_23_reg_1005;
reg [0:0] tmp19_reg_1010;
reg [0:0] empty_25_reg_1015;
reg [0:0] tmp21_reg_1020;
reg [0:0] empty_27_reg_1025;
reg [0:0] tmp22_reg_1030;
reg [0:0] empty_29_reg_1035;
reg [0:0] tmp27_reg_1040;
reg [0:0] empty_31_reg_1045;
reg [0:0] empty_32_reg_1050;
reg [0:0] tmp29_reg_1055;
reg [0:0] empty_34_reg_1060;
reg [0:0] tmp30_reg_1065;
reg [0:0] empty_36_reg_1070;
reg [0:0] tmp33_reg_1075;
reg [0:0] empty_38_reg_1080;
reg [0:0] empty_39_reg_1085;
reg [0:0] tmp35_reg_1090;
reg [0:0] empty_41_reg_1095;
reg [0:0] tmp36_reg_1100;
reg [0:0] empty_43_reg_1105;
reg [0:0] tmp40_reg_1110;
reg [0:0] empty_45_reg_1115;
reg [0:0] empty_46_reg_1120;
reg [0:0] tmp42_reg_1125;
reg [0:0] empty_48_reg_1130;
reg [0:0] tmp43_reg_1135;
reg [0:0] empty_50_reg_1140;
reg [0:0] tmp46_reg_1145;
reg [0:0] empty_52_reg_1150;
reg [0:0] tmp47_reg_1155;
reg [0:0] empty_54_reg_1160;
reg [0:0] tmp49_reg_1165;
reg [0:0] empty_56_reg_1170;
reg [0:0] tmp50_reg_1175;
reg [0:0] empty_58_reg_1180;
reg [0:0] Convergence_assign_58_reg_1185;
reg [7:0] r1_p3_address0;
reg r1_p3_ce0;
reg r1_p3_we0;
wire [31:0] r1_p3_d0;
wire [31:0] r1_p3_q0;
reg [7:0] r1_p2_address0;
reg r1_p2_ce0;
reg r1_p2_we0;
wire [31:0] r1_p2_d0;
wire [31:0] r1_p2_q0;
reg [7:0] r1_p1_address0;
reg r1_p1_ce0;
reg r1_p1_we0;
wire [31:0] r1_p1_d0;
wire [31:0] r1_p1_q0;
reg [7:0] r1_p0_address0;
reg r1_p0_ce0;
reg r1_p0_we0;
wire [31:0] r1_p0_d0;
wire [31:0] r1_p0_q0;
reg [7:0] r0_p3_address0;
reg r0_p3_ce0;
reg r0_p3_we0;
wire [31:0] r0_p3_d0;
wire [31:0] r0_p3_q0;
reg [7:0] r0_p2_address0;
reg r0_p2_ce0;
reg r0_p2_we0;
wire [31:0] r0_p2_d0;
wire [31:0] r0_p2_q0;
reg [7:0] r0_p1_address0;
reg r0_p1_ce0;
reg r0_p1_we0;
wire [31:0] r0_p1_d0;
wire [31:0] r0_p1_q0;
reg [7:0] r0_p0_address0;
reg r0_p0_ce0;
reg r0_p0_we0;
wire [31:0] r0_p0_d0;
wire [31:0] r0_p0_q0;
reg [7:0] f1_p3_address0;
reg f1_p3_ce0;
reg f1_p3_we0;
wire [31:0] f1_p3_d0;
wire [31:0] f1_p3_q0;
reg [7:0] f1_p2_address0;
reg f1_p2_ce0;
reg f1_p2_we0;
wire [31:0] f1_p2_d0;
wire [31:0] f1_p2_q0;
reg [7:0] f1_p1_address0;
reg f1_p1_ce0;
reg f1_p1_we0;
wire [31:0] f1_p1_d0;
wire [31:0] f1_p1_q0;
reg [7:0] f1_p0_address0;
reg f1_p0_ce0;
reg f1_p0_we0;
wire [31:0] f1_p0_d0;
wire [31:0] f1_p0_q0;
reg [7:0] f0_p3_address0;
reg f0_p3_ce0;
reg f0_p3_we0;
wire [31:0] f0_p3_d0;
wire [31:0] f0_p3_q0;
reg [7:0] f0_p2_address0;
reg f0_p2_ce0;
reg f0_p2_we0;
wire [31:0] f0_p2_d0;
wire [31:0] f0_p2_q0;
reg [7:0] f0_p1_address0;
reg f0_p1_ce0;
reg f0_p1_we0;
wire [31:0] f0_p1_d0;
wire [31:0] f0_p1_q0;
reg [7:0] f0_p0_address0;
reg f0_p0_ce0;
reg f0_p0_we0;
wire [31:0] f0_p0_d0;
wire [31:0] f0_p0_q0;
reg [7:0] g4_p3_address0;
reg g4_p3_ce0;
reg g4_p3_we0;
wire [31:0] g4_p3_d0;
wire [31:0] g4_p3_q0;
wire [7:0] g4_p3_address1;
reg g4_p3_ce1;
wire [31:0] g4_p3_q1;
reg [7:0] g4_p2_address0;
reg g4_p2_ce0;
reg g4_p2_we0;
wire [31:0] g4_p2_d0;
wire [31:0] g4_p2_q0;
reg [7:0] g4_p1_address0;
reg g4_p1_ce0;
reg g4_p1_we0;
wire [31:0] g4_p1_d0;
wire [31:0] g4_p1_q0;
reg [7:0] g4_p0_address0;
reg g4_p0_ce0;
reg g4_p0_we0;
wire [31:0] g4_p0_d0;
wire [31:0] g4_p0_q0;
wire [7:0] g4_p0_address1;
reg g4_p0_ce1;
wire [31:0] g4_p0_q1;
reg [7:0] g3_p3_address0;
reg g3_p3_ce0;
reg g3_p3_we0;
wire [31:0] g3_p3_d0;
wire [31:0] g3_p3_q0;
wire [7:0] g3_p3_address1;
reg g3_p3_ce1;
wire [31:0] g3_p3_q1;
reg [7:0] g3_p2_address0;
reg g3_p2_ce0;
reg g3_p2_we0;
wire [31:0] g3_p2_d0;
wire [31:0] g3_p2_q0;
reg [7:0] g3_p1_address0;
reg g3_p1_ce0;
reg g3_p1_we0;
wire [31:0] g3_p1_d0;
wire [31:0] g3_p1_q0;
reg [7:0] g3_p0_address0;
reg g3_p0_ce0;
reg g3_p0_we0;
wire [31:0] g3_p0_d0;
wire [31:0] g3_p0_q0;
wire [7:0] g3_p0_address1;
reg g3_p0_ce1;
wire [31:0] g3_p0_q1;
reg [7:0] g2_p3_address0;
reg g2_p3_ce0;
reg g2_p3_we0;
wire [31:0] g2_p3_d0;
wire [31:0] g2_p3_q0;
wire [7:0] g2_p3_address1;
reg g2_p3_ce1;
wire [31:0] g2_p3_q1;
reg [7:0] g2_p2_address0;
reg g2_p2_ce0;
reg g2_p2_we0;
wire [31:0] g2_p2_d0;
wire [31:0] g2_p2_q0;
reg [7:0] g2_p1_address0;
reg g2_p1_ce0;
reg g2_p1_we0;
wire [31:0] g2_p1_d0;
wire [31:0] g2_p1_q0;
reg [7:0] g2_p0_address0;
reg g2_p0_ce0;
reg g2_p0_we0;
wire [31:0] g2_p0_d0;
wire [31:0] g2_p0_q0;
wire [7:0] g2_p0_address1;
reg g2_p0_ce1;
wire [31:0] g2_p0_q1;
reg [7:0] g1_p3_address0;
reg g1_p3_ce0;
reg g1_p3_we0;
wire [31:0] g1_p3_d0;
wire [31:0] g1_p3_q0;
wire [7:0] g1_p3_address1;
reg g1_p3_ce1;
wire [31:0] g1_p3_q1;
reg [7:0] g1_p2_address0;
reg g1_p2_ce0;
reg g1_p2_we0;
wire [31:0] g1_p2_d0;
wire [31:0] g1_p2_q0;
reg [7:0] g1_p1_address0;
reg g1_p1_ce0;
reg g1_p1_we0;
wire [31:0] g1_p1_d0;
wire [31:0] g1_p1_q0;
reg [7:0] g1_p0_address0;
reg g1_p0_ce0;
reg g1_p0_we0;
wire [31:0] g1_p0_d0;
wire [31:0] g1_p0_q0;
wire [7:0] g1_p0_address1;
reg g1_p0_ce1;
wire [31:0] g1_p0_q1;
reg [7:0] g0_p3_address0;
reg g0_p3_ce0;
reg g0_p3_we0;
wire [31:0] g0_p3_d0;
wire [31:0] g0_p3_q0;
wire [7:0] g0_p3_address1;
reg g0_p3_ce1;
wire [31:0] g0_p3_q1;
reg [7:0] g0_p2_address0;
reg g0_p2_ce0;
reg g0_p2_we0;
wire [31:0] g0_p2_d0;
wire [31:0] g0_p2_q0;
reg [7:0] g0_p1_address0;
reg g0_p1_ce0;
reg g0_p1_we0;
wire [31:0] g0_p1_d0;
wire [31:0] g0_p1_q0;
reg [7:0] g0_p0_address0;
reg g0_p0_ce0;
reg g0_p0_we0;
wire [31:0] g0_p0_d0;
wire [31:0] g0_p0_q0;
wire [7:0] g0_p0_address1;
reg g0_p0_ce1;
wire [31:0] g0_p0_q1;
reg [7:0] ug3_p3_address0;
reg ug3_p3_ce0;
reg ug3_p3_we0;
wire [31:0] ug3_p3_d0;
wire [31:0] ug3_p3_q0;
wire [7:0] ug3_p3_address1;
reg ug3_p3_ce1;
wire [31:0] ug3_p3_q1;
reg [7:0] ug3_p2_address0;
reg ug3_p2_ce0;
reg ug3_p2_we0;
wire [31:0] ug3_p2_d0;
wire [31:0] ug3_p2_q0;
reg [7:0] ug3_p1_address0;
reg ug3_p1_ce0;
reg ug3_p1_we0;
wire [31:0] ug3_p1_d0;
wire [31:0] ug3_p1_q0;
reg [7:0] ug3_p0_address0;
reg ug3_p0_ce0;
reg ug3_p0_we0;
wire [31:0] ug3_p0_d0;
wire [31:0] ug3_p0_q0;
wire [7:0] ug3_p0_address1;
reg ug3_p0_ce1;
wire [31:0] ug3_p0_q1;
reg [7:0] ug2_p3_address0;
reg ug2_p3_ce0;
reg ug2_p3_we0;
wire [31:0] ug2_p3_d0;
wire [31:0] ug2_p3_q0;
wire [7:0] ug2_p3_address1;
reg ug2_p3_ce1;
wire [31:0] ug2_p3_q1;
reg [7:0] ug2_p2_address0;
reg ug2_p2_ce0;
reg ug2_p2_we0;
wire [31:0] ug2_p2_d0;
wire [31:0] ug2_p2_q0;
reg [7:0] ug2_p1_address0;
reg ug2_p1_ce0;
reg ug2_p1_we0;
wire [31:0] ug2_p1_d0;
wire [31:0] ug2_p1_q0;
reg [7:0] ug2_p0_address0;
reg ug2_p0_ce0;
reg ug2_p0_we0;
wire [31:0] ug2_p0_d0;
wire [31:0] ug2_p0_q0;
wire [7:0] ug2_p0_address1;
reg ug2_p0_ce1;
wire [31:0] ug2_p0_q1;
reg [7:0] ug1_p3_address0;
reg ug1_p3_ce0;
reg ug1_p3_we0;
wire [31:0] ug1_p3_d0;
wire [31:0] ug1_p3_q0;
wire [7:0] ug1_p3_address1;
reg ug1_p3_ce1;
wire [31:0] ug1_p3_q1;
reg [7:0] ug1_p2_address0;
reg ug1_p2_ce0;
reg ug1_p2_we0;
wire [31:0] ug1_p2_d0;
wire [31:0] ug1_p2_q0;
reg [7:0] ug1_p1_address0;
reg ug1_p1_ce0;
reg ug1_p1_we0;
wire [31:0] ug1_p1_d0;
wire [31:0] ug1_p1_q0;
reg [7:0] ug1_p0_address0;
reg ug1_p0_ce0;
reg ug1_p0_we0;
wire [31:0] ug1_p0_d0;
wire [31:0] ug1_p0_q0;
wire [7:0] ug1_p0_address1;
reg ug1_p0_ce1;
wire [31:0] ug1_p0_q1;
reg [7:0] ug0_p3_address0;
reg ug0_p3_ce0;
reg ug0_p3_we0;
wire [31:0] ug0_p3_d0;
wire [31:0] ug0_p3_q0;
wire [7:0] ug0_p3_address1;
reg ug0_p3_ce1;
wire [31:0] ug0_p3_q1;
reg [7:0] ug0_p2_address0;
reg ug0_p2_ce0;
reg ug0_p2_we0;
wire [31:0] ug0_p2_d0;
wire [31:0] ug0_p2_q0;
reg [7:0] ug0_p1_address0;
reg ug0_p1_ce0;
reg ug0_p1_we0;
wire [31:0] ug0_p1_d0;
wire [31:0] ug0_p1_q0;
reg [7:0] ug0_p0_address0;
reg ug0_p0_ce0;
reg ug0_p0_we0;
wire [31:0] ug0_p0_d0;
wire [31:0] ug0_p0_q0;
wire [7:0] ug0_p0_address1;
reg ug0_p0_ce1;
wire [31:0] ug0_p0_q1;
reg [7:0] sp2_p3_address0;
reg sp2_p3_ce0;
reg sp2_p3_we0;
wire [31:0] sp2_p3_d0;
wire [31:0] sp2_p3_q0;
reg [7:0] sp2_p2_address0;
reg sp2_p2_ce0;
reg sp2_p2_we0;
wire [31:0] sp2_p2_d0;
wire [31:0] sp2_p2_q0;
reg [7:0] sp2_p1_address0;
reg sp2_p1_ce0;
reg sp2_p1_we0;
wire [31:0] sp2_p1_d0;
wire [31:0] sp2_p1_q0;
reg [7:0] sp2_p0_address0;
reg sp2_p0_ce0;
reg sp2_p0_we0;
wire [31:0] sp2_p0_d0;
wire [31:0] sp2_p0_q0;
reg [7:0] sp1_p3_address0;
reg sp1_p3_ce0;
reg sp1_p3_we0;
wire [31:0] sp1_p3_d0;
wire [31:0] sp1_p3_q0;
reg [7:0] sp1_p2_address0;
reg sp1_p2_ce0;
reg sp1_p2_we0;
wire [31:0] sp1_p2_d0;
wire [31:0] sp1_p2_q0;
reg [7:0] sp1_p1_address0;
reg sp1_p1_ce0;
reg sp1_p1_we0;
wire [31:0] sp1_p1_d0;
wire [31:0] sp1_p1_q0;
reg [7:0] sp1_p0_address0;
reg sp1_p0_ce0;
reg sp1_p0_we0;
wire [31:0] sp1_p0_d0;
wire [31:0] sp1_p0_q0;
reg [7:0] sp0_p3_address0;
reg sp0_p3_ce0;
reg sp0_p3_we0;
wire [31:0] sp0_p3_d0;
wire [31:0] sp0_p3_q0;
reg [7:0] sp0_p2_address0;
reg sp0_p2_ce0;
reg sp0_p2_we0;
wire [31:0] sp0_p2_d0;
wire [31:0] sp0_p2_q0;
reg [7:0] sp0_p1_address0;
reg sp0_p1_ce0;
reg sp0_p1_we0;
wire [31:0] sp0_p1_d0;
wire [31:0] sp0_p1_q0;
reg [7:0] sp0_p0_address0;
reg sp0_p0_ce0;
reg sp0_p0_we0;
wire [31:0] sp0_p0_d0;
wire [31:0] sp0_p0_q0;
reg [7:0] sn1_p3_address0;
reg sn1_p3_ce0;
reg sn1_p3_we0;
wire [31:0] sn1_p3_d0;
wire [31:0] sn1_p3_q0;
reg [7:0] sn1_p2_address0;
reg sn1_p2_ce0;
reg sn1_p2_we0;
wire [31:0] sn1_p2_d0;
wire [31:0] sn1_p2_q0;
reg [7:0] sn1_p1_address0;
reg sn1_p1_ce0;
reg sn1_p1_we0;
wire [31:0] sn1_p1_d0;
wire [31:0] sn1_p1_q0;
reg [7:0] sn1_p0_address0;
reg sn1_p0_ce0;
reg sn1_p0_we0;
wire [31:0] sn1_p0_d0;
wire [31:0] sn1_p0_q0;
wire [7:0] sn1_p0_address1;
reg sn1_p0_ce1;
wire [31:0] sn1_p0_q1;
reg [7:0] sn0_p3_address0;
reg sn0_p3_ce0;
reg sn0_p3_we0;
wire [31:0] sn0_p3_d0;
wire [31:0] sn0_p3_q0;
reg [7:0] sn0_p2_address0;
reg sn0_p2_ce0;
reg sn0_p2_we0;
wire [31:0] sn0_p2_d0;
wire [31:0] sn0_p2_q0;
reg [7:0] sn0_p1_address0;
reg sn0_p1_ce0;
reg sn0_p1_we0;
wire [31:0] sn0_p1_d0;
wire [31:0] sn0_p1_q0;
reg [7:0] sn0_p0_address0;
reg sn0_p0_ce0;
reg sn0_p0_we0;
wire [31:0] sn0_p0_d0;
wire [31:0] sn0_p0_q0;
wire [7:0] sn0_p0_address1;
reg sn0_p0_ce1;
wire [31:0] sn0_p0_q1;
reg [7:0] sm1_p3_address0;
reg sm1_p3_ce0;
reg sm1_p3_we0;
wire [31:0] sm1_p3_d0;
wire [31:0] sm1_p3_q0;
reg [7:0] sm1_p2_address0;
reg sm1_p2_ce0;
reg sm1_p2_we0;
wire [31:0] sm1_p2_d0;
wire [31:0] sm1_p2_q0;
reg [7:0] sm1_p1_address0;
reg sm1_p1_ce0;
reg sm1_p1_we0;
wire [31:0] sm1_p1_d0;
wire [31:0] sm1_p1_q0;
reg [7:0] sm1_p0_address0;
reg sm1_p0_ce0;
reg sm1_p0_we0;
wire [31:0] sm1_p0_d0;
wire [31:0] sm1_p0_q0;
reg [7:0] sm0_p3_address0;
reg sm0_p3_ce0;
reg sm0_p3_we0;
wire [31:0] sm0_p3_d0;
wire [31:0] sm0_p3_q0;
reg [7:0] sm0_p2_address0;
reg sm0_p2_ce0;
reg sm0_p2_we0;
wire [31:0] sm0_p2_d0;
wire [31:0] sm0_p2_q0;
reg [7:0] sm0_p1_address0;
reg sm0_p1_ce0;
reg sm0_p1_we0;
wire [31:0] sm0_p1_d0;
wire [31:0] sm0_p1_q0;
reg [7:0] sm0_p0_address0;
reg sm0_p0_ce0;
reg sm0_p0_we0;
wire [31:0] sm0_p0_d0;
wire [31:0] sm0_p0_q0;
reg [7:0] u6_p3_address0;
reg u6_p3_ce0;
reg u6_p3_we0;
wire [31:0] u6_p3_d0;
wire [31:0] u6_p3_q0;
wire [7:0] u6_p3_address1;
reg u6_p3_ce1;
wire [31:0] u6_p3_q1;
reg [7:0] u6_p2_address0;
reg u6_p2_ce0;
reg u6_p2_we0;
wire [31:0] u6_p2_d0;
wire [31:0] u6_p2_q0;
reg [7:0] u6_p1_address0;
reg u6_p1_ce0;
reg u6_p1_we0;
wire [31:0] u6_p1_d0;
wire [31:0] u6_p1_q0;
reg [7:0] u6_p0_address0;
reg u6_p0_ce0;
reg u6_p0_we0;
wire [31:0] u6_p0_d0;
wire [31:0] u6_p0_q0;
reg [7:0] u5_p3_address0;
reg u5_p3_ce0;
reg u5_p3_we0;
wire [31:0] u5_p3_d0;
wire [31:0] u5_p3_q0;
wire [7:0] u5_p3_address1;
reg u5_p3_ce1;
wire [31:0] u5_p3_q1;
reg [7:0] u5_p2_address0;
reg u5_p2_ce0;
reg u5_p2_we0;
wire [31:0] u5_p2_d0;
wire [31:0] u5_p2_q0;
reg [7:0] u5_p1_address0;
reg u5_p1_ce0;
reg u5_p1_we0;
wire [31:0] u5_p1_d0;
wire [31:0] u5_p1_q0;
reg [7:0] u5_p0_address0;
reg u5_p0_ce0;
reg u5_p0_we0;
wire [31:0] u5_p0_d0;
wire [31:0] u5_p0_q0;
reg [7:0] u4_p3_address0;
reg u4_p3_ce0;
reg u4_p3_we0;
wire [31:0] u4_p3_d0;
wire [31:0] u4_p3_q0;
wire [7:0] u4_p3_address1;
reg u4_p3_ce1;
wire [31:0] u4_p3_q1;
reg [7:0] u4_p2_address0;
reg u4_p2_ce0;
reg u4_p2_we0;
wire [31:0] u4_p2_d0;
wire [31:0] u4_p2_q0;
reg [7:0] u4_p1_address0;
reg u4_p1_ce0;
reg u4_p1_we0;
wire [31:0] u4_p1_d0;
wire [31:0] u4_p1_q0;
reg [7:0] u4_p0_address0;
reg u4_p0_ce0;
reg u4_p0_we0;
wire [31:0] u4_p0_d0;
wire [31:0] u4_p0_q0;
reg [7:0] u3_p3_address0;
reg u3_p3_ce0;
reg u3_p3_we0;
wire [31:0] u3_p3_d0;
wire [31:0] u3_p3_q0;
wire [7:0] u3_p3_address1;
reg u3_p3_ce1;
wire [31:0] u3_p3_q1;
reg [7:0] u3_p2_address0;
reg u3_p2_ce0;
reg u3_p2_we0;
wire [31:0] u3_p2_d0;
wire [31:0] u3_p2_q0;
reg [7:0] u3_p1_address0;
reg u3_p1_ce0;
reg u3_p1_we0;
wire [31:0] u3_p1_d0;
wire [31:0] u3_p1_q0;
reg [7:0] u3_p0_address0;
reg u3_p0_ce0;
reg u3_p0_we0;
wire [31:0] u3_p0_d0;
wire [31:0] u3_p0_q0;
reg [7:0] u2_p3_address0;
reg u2_p3_ce0;
reg u2_p3_we0;
wire [31:0] u2_p3_d0;
wire [31:0] u2_p3_q0;
wire [7:0] u2_p3_address1;
reg u2_p3_ce1;
wire [31:0] u2_p3_q1;
reg [7:0] u2_p2_address0;
reg u2_p2_ce0;
reg u2_p2_we0;
wire [31:0] u2_p2_d0;
wire [31:0] u2_p2_q0;
reg [7:0] u2_p1_address0;
reg u2_p1_ce0;
reg u2_p1_we0;
wire [31:0] u2_p1_d0;
wire [31:0] u2_p1_q0;
reg [7:0] u2_p0_address0;
reg u2_p0_ce0;
reg u2_p0_we0;
wire [31:0] u2_p0_d0;
wire [31:0] u2_p0_q0;
reg [7:0] u1_p3_address0;
reg u1_p3_ce0;
reg u1_p3_we0;
wire [31:0] u1_p3_d0;
wire [31:0] u1_p3_q0;
wire [7:0] u1_p3_address1;
reg u1_p3_ce1;
wire [31:0] u1_p3_q1;
reg [7:0] u1_p2_address0;
reg u1_p2_ce0;
reg u1_p2_we0;
wire [31:0] u1_p2_d0;
wire [31:0] u1_p2_q0;
reg [7:0] u1_p1_address0;
reg u1_p1_ce0;
reg u1_p1_we0;
wire [31:0] u1_p1_d0;
wire [31:0] u1_p1_q0;
reg [7:0] u1_p0_address0;
reg u1_p0_ce0;
reg u1_p0_we0;
wire [31:0] u1_p0_d0;
wire [31:0] u1_p0_q0;
reg [7:0] u0_p3_address0;
reg u0_p3_ce0;
reg u0_p3_we0;
wire [31:0] u0_p3_d0;
wire [31:0] u0_p3_q0;
wire [7:0] u0_p3_address1;
reg u0_p3_ce1;
wire [31:0] u0_p3_q1;
reg [7:0] u0_p2_address0;
reg u0_p2_ce0;
reg u0_p2_we0;
wire [31:0] u0_p2_d0;
wire [31:0] u0_p2_q0;
reg [7:0] u0_p1_address0;
reg u0_p1_ce0;
reg u0_p1_we0;
wire [31:0] u0_p1_d0;
wire [31:0] u0_p1_q0;
reg [7:0] u0_p0_address0;
reg u0_p0_ce0;
reg u0_p0_we0;
wire [31:0] u0_p0_d0;
wire [31:0] u0_p0_q0;
reg grp_computeResult_fu_467_ap_start;
wire grp_computeResult_fu_467_ap_idle;
wire [7:0] grp_computeResult_fu_467_r_p0_address0;
wire grp_computeResult_fu_467_r_p0_ce0;
wire grp_computeResult_fu_467_r_p0_we0;
wire [31:0] grp_computeResult_fu_467_r_p0_d0;
wire [7:0] grp_computeResult_fu_467_r_p1_address0;
wire grp_computeResult_fu_467_r_p1_ce0;
wire grp_computeResult_fu_467_r_p1_we0;
wire [31:0] grp_computeResult_fu_467_r_p1_d0;
wire [7:0] grp_computeResult_fu_467_r_p2_address0;
wire grp_computeResult_fu_467_r_p2_ce0;
wire grp_computeResult_fu_467_r_p2_we0;
wire [31:0] grp_computeResult_fu_467_r_p2_d0;
wire [7:0] grp_computeResult_fu_467_r_p3_address0;
wire grp_computeResult_fu_467_r_p3_ce0;
wire grp_computeResult_fu_467_r_p3_we0;
wire [31:0] grp_computeResult_fu_467_r_p3_d0;
wire [7:0] grp_computeResult_fu_467_u_p0_address0;
wire grp_computeResult_fu_467_u_p0_ce0;
reg [31:0] grp_computeResult_fu_467_u_p0_q0;
wire [7:0] grp_computeResult_fu_467_u_p1_address0;
wire grp_computeResult_fu_467_u_p1_ce0;
reg [31:0] grp_computeResult_fu_467_u_p1_q0;
wire [7:0] grp_computeResult_fu_467_u_p2_address0;
wire grp_computeResult_fu_467_u_p2_ce0;
reg [31:0] grp_computeResult_fu_467_u_p2_q0;
wire [7:0] grp_computeResult_fu_467_u_p3_address0;
wire grp_computeResult_fu_467_u_p3_ce0;
reg [31:0] grp_computeResult_fu_467_u_p3_q0;
wire [7:0] grp_computeResult_fu_467_ug0_p0_address0;
wire grp_computeResult_fu_467_ug0_p0_ce0;
reg [31:0] grp_computeResult_fu_467_ug0_p0_q0;
wire [7:0] grp_computeResult_fu_467_ug0_p1_address0;
wire grp_computeResult_fu_467_ug0_p1_ce0;
reg [31:0] grp_computeResult_fu_467_ug0_p1_q0;
wire [7:0] grp_computeResult_fu_467_ug0_p2_address0;
wire grp_computeResult_fu_467_ug0_p2_ce0;
reg [31:0] grp_computeResult_fu_467_ug0_p2_q0;
wire [7:0] grp_computeResult_fu_467_ug0_p3_address0;
wire grp_computeResult_fu_467_ug0_p3_ce0;
reg [31:0] grp_computeResult_fu_467_ug0_p3_q0;
wire [7:0] grp_computeResult_fu_467_ug1_p0_address0;
wire grp_computeResult_fu_467_ug1_p0_ce0;
reg [31:0] grp_computeResult_fu_467_ug1_p0_q0;
wire [7:0] grp_computeResult_fu_467_ug1_p0_address1;
wire grp_computeResult_fu_467_ug1_p0_ce1;
reg [31:0] grp_computeResult_fu_467_ug1_p0_q1;
wire [7:0] grp_computeResult_fu_467_ug1_p1_address0;
wire grp_computeResult_fu_467_ug1_p1_ce0;
reg [31:0] grp_computeResult_fu_467_ug1_p1_q0;
wire [7:0] grp_computeResult_fu_467_ug1_p2_address0;
wire grp_computeResult_fu_467_ug1_p2_ce0;
reg [31:0] grp_computeResult_fu_467_ug1_p2_q0;
wire [7:0] grp_computeResult_fu_467_ug1_p3_address0;
wire grp_computeResult_fu_467_ug1_p3_ce0;
reg [31:0] grp_computeResult_fu_467_ug1_p3_q0;
wire [7:0] grp_computeResult_fu_467_ug1_p3_address1;
wire grp_computeResult_fu_467_ug1_p3_ce1;
reg [31:0] grp_computeResult_fu_467_ug1_p3_q1;
wire [7:0] grp_computeResult_fu_467_ug2_p0_address0;
wire grp_computeResult_fu_467_ug2_p0_ce0;
reg [31:0] grp_computeResult_fu_467_ug2_p0_q0;
wire [7:0] grp_computeResult_fu_467_ug2_p1_address0;
wire grp_computeResult_fu_467_ug2_p1_ce0;
reg [31:0] grp_computeResult_fu_467_ug2_p1_q0;
wire [7:0] grp_computeResult_fu_467_ug2_p2_address0;
wire grp_computeResult_fu_467_ug2_p2_ce0;
reg [31:0] grp_computeResult_fu_467_ug2_p2_q0;
wire [7:0] grp_computeResult_fu_467_ug2_p3_address0;
wire grp_computeResult_fu_467_ug2_p3_ce0;
reg [31:0] grp_computeResult_fu_467_ug2_p3_q0;
wire [7:0] grp_computeResult_fu_467_g0_p0_address0;
wire grp_computeResult_fu_467_g0_p0_ce0;
reg [31:0] grp_computeResult_fu_467_g0_p0_q0;
wire [7:0] grp_computeResult_fu_467_g0_p1_address0;
wire grp_computeResult_fu_467_g0_p1_ce0;
reg [31:0] grp_computeResult_fu_467_g0_p1_q0;
wire [7:0] grp_computeResult_fu_467_g0_p2_address0;
wire grp_computeResult_fu_467_g0_p2_ce0;
reg [31:0] grp_computeResult_fu_467_g0_p2_q0;
wire [7:0] grp_computeResult_fu_467_g0_p3_address0;
wire grp_computeResult_fu_467_g0_p3_ce0;
reg [31:0] grp_computeResult_fu_467_g0_p3_q0;
wire [7:0] grp_computeResult_fu_467_g1_p0_address0;
wire grp_computeResult_fu_467_g1_p0_ce0;
reg [31:0] grp_computeResult_fu_467_g1_p0_q0;
wire [7:0] grp_computeResult_fu_467_g1_p0_address1;
wire grp_computeResult_fu_467_g1_p0_ce1;
reg [31:0] grp_computeResult_fu_467_g1_p0_q1;
wire [7:0] grp_computeResult_fu_467_g1_p1_address0;
wire grp_computeResult_fu_467_g1_p1_ce0;
reg [31:0] grp_computeResult_fu_467_g1_p1_q0;
wire [7:0] grp_computeResult_fu_467_g1_p2_address0;
wire grp_computeResult_fu_467_g1_p2_ce0;
reg [31:0] grp_computeResult_fu_467_g1_p2_q0;
wire [7:0] grp_computeResult_fu_467_g1_p3_address0;
wire grp_computeResult_fu_467_g1_p3_ce0;
reg [31:0] grp_computeResult_fu_467_g1_p3_q0;
wire [7:0] grp_computeResult_fu_467_g1_p3_address1;
wire grp_computeResult_fu_467_g1_p3_ce1;
reg [31:0] grp_computeResult_fu_467_g1_p3_q1;
wire [7:0] grp_computeResult_fu_467_g2_p0_address0;
wire grp_computeResult_fu_467_g2_p0_ce0;
reg [31:0] grp_computeResult_fu_467_g2_p0_q0;
wire [7:0] grp_computeResult_fu_467_g2_p1_address0;
wire grp_computeResult_fu_467_g2_p1_ce0;
reg [31:0] grp_computeResult_fu_467_g2_p1_q0;
wire [7:0] grp_computeResult_fu_467_g2_p2_address0;
wire grp_computeResult_fu_467_g2_p2_ce0;
reg [31:0] grp_computeResult_fu_467_g2_p2_q0;
wire [7:0] grp_computeResult_fu_467_g2_p3_address0;
wire grp_computeResult_fu_467_g2_p3_ce0;
reg [31:0] grp_computeResult_fu_467_g2_p3_q0;
wire [7:0] grp_computeResult_fu_467_f_p0_address0;
wire grp_computeResult_fu_467_f_p0_ce0;
reg [31:0] grp_computeResult_fu_467_f_p0_q0;
wire [7:0] grp_computeResult_fu_467_f_p1_address0;
wire grp_computeResult_fu_467_f_p1_ce0;
reg [31:0] grp_computeResult_fu_467_f_p1_q0;
wire [7:0] grp_computeResult_fu_467_f_p2_address0;
wire grp_computeResult_fu_467_f_p2_ce0;
reg [31:0] grp_computeResult_fu_467_f_p2_q0;
wire [7:0] grp_computeResult_fu_467_f_p3_address0;
wire grp_computeResult_fu_467_f_p3_ce0;
reg [31:0] grp_computeResult_fu_467_f_p3_q0;
reg grp_computeGradient_fu_507_ap_start;
wire grp_computeGradient_fu_507_ap_idle;
wire [7:0] grp_computeGradient_fu_507_g_p0_address0;
wire grp_computeGradient_fu_507_g_p0_ce0;
wire grp_computeGradient_fu_507_g_p0_we0;
wire [31:0] grp_computeGradient_fu_507_g_p0_d0;
wire [7:0] grp_computeGradient_fu_507_g_p1_address0;
wire grp_computeGradient_fu_507_g_p1_ce0;
wire grp_computeGradient_fu_507_g_p1_we0;
wire [31:0] grp_computeGradient_fu_507_g_p1_d0;
wire [7:0] grp_computeGradient_fu_507_g_p2_address0;
wire grp_computeGradient_fu_507_g_p2_ce0;
wire grp_computeGradient_fu_507_g_p2_we0;
wire [31:0] grp_computeGradient_fu_507_g_p2_d0;
wire [7:0] grp_computeGradient_fu_507_g_p3_address0;
wire grp_computeGradient_fu_507_g_p3_ce0;
wire grp_computeGradient_fu_507_g_p3_we0;
wire [31:0] grp_computeGradient_fu_507_g_p3_d0;
wire [7:0] grp_computeGradient_fu_507_sm0_p0_address0;
wire grp_computeGradient_fu_507_sm0_p0_ce0;
reg [31:0] grp_computeGradient_fu_507_sm0_p0_q0;
wire [7:0] grp_computeGradient_fu_507_sm0_p1_address0;
wire grp_computeGradient_fu_507_sm0_p1_ce0;
reg [31:0] grp_computeGradient_fu_507_sm0_p1_q0;
wire [7:0] grp_computeGradient_fu_507_sm0_p2_address0;
wire grp_computeGradient_fu_507_sm0_p2_ce0;
reg [31:0] grp_computeGradient_fu_507_sm0_p2_q0;
wire [7:0] grp_computeGradient_fu_507_sm0_p3_address0;
wire grp_computeGradient_fu_507_sm0_p3_ce0;
reg [31:0] grp_computeGradient_fu_507_sm0_p3_q0;
wire [7:0] grp_computeGradient_fu_507_sn0_p0_address0;
wire grp_computeGradient_fu_507_sn0_p0_ce0;
reg [31:0] grp_computeGradient_fu_507_sn0_p0_q0;
wire [7:0] grp_computeGradient_fu_507_sn0_p0_address1;
wire grp_computeGradient_fu_507_sn0_p0_ce1;
reg [31:0] grp_computeGradient_fu_507_sn0_p0_q1;
wire [7:0] grp_computeGradient_fu_507_sn0_p1_address0;
wire grp_computeGradient_fu_507_sn0_p1_ce0;
reg [31:0] grp_computeGradient_fu_507_sn0_p1_q0;
wire [7:0] grp_computeGradient_fu_507_sn0_p2_address0;
wire grp_computeGradient_fu_507_sn0_p2_ce0;
reg [31:0] grp_computeGradient_fu_507_sn0_p2_q0;
wire [7:0] grp_computeGradient_fu_507_sn0_p3_address0;
wire grp_computeGradient_fu_507_sn0_p3_ce0;
reg [31:0] grp_computeGradient_fu_507_sn0_p3_q0;
wire [7:0] grp_computeGradient_fu_507_sp0_p0_address0;
wire grp_computeGradient_fu_507_sp0_p0_ce0;
reg [31:0] grp_computeGradient_fu_507_sp0_p0_q0;
wire [7:0] grp_computeGradient_fu_507_sp0_p1_address0;
wire grp_computeGradient_fu_507_sp0_p1_ce0;
reg [31:0] grp_computeGradient_fu_507_sp0_p1_q0;
wire [7:0] grp_computeGradient_fu_507_sp0_p2_address0;
wire grp_computeGradient_fu_507_sp0_p2_ce0;
reg [31:0] grp_computeGradient_fu_507_sp0_p2_q0;
wire [7:0] grp_computeGradient_fu_507_sp0_p3_address0;
wire grp_computeGradient_fu_507_sp0_p3_ce0;
reg [31:0] grp_computeGradient_fu_507_sp0_p3_q0;
wire [7:0] grp_computeGradient_fu_507_sp1_p0_address0;
wire grp_computeGradient_fu_507_sp1_p0_ce0;
reg [31:0] grp_computeGradient_fu_507_sp1_p0_q0;
wire [7:0] grp_computeGradient_fu_507_sp1_p1_address0;
wire grp_computeGradient_fu_507_sp1_p1_ce0;
reg [31:0] grp_computeGradient_fu_507_sp1_p1_q0;
wire [7:0] grp_computeGradient_fu_507_sp1_p2_address0;
wire grp_computeGradient_fu_507_sp1_p2_ce0;
reg [31:0] grp_computeGradient_fu_507_sp1_p2_q0;
wire [7:0] grp_computeGradient_fu_507_sp1_p3_address0;
wire grp_computeGradient_fu_507_sp1_p3_ce0;
reg [31:0] grp_computeGradient_fu_507_sp1_p3_q0;
reg grp_computeDiffSqr_fu_531_ap_start;
wire grp_computeDiffSqr_fu_531_ap_idle;
wire [7:0] grp_computeDiffSqr_fu_531_sm_p0_address0;
wire grp_computeDiffSqr_fu_531_sm_p0_ce0;
wire grp_computeDiffSqr_fu_531_sm_p0_we0;
wire [31:0] grp_computeDiffSqr_fu_531_sm_p0_d0;
wire [7:0] grp_computeDiffSqr_fu_531_sm_p1_address0;
wire grp_computeDiffSqr_fu_531_sm_p1_ce0;
wire grp_computeDiffSqr_fu_531_sm_p1_we0;
wire [31:0] grp_computeDiffSqr_fu_531_sm_p1_d0;
wire [7:0] grp_computeDiffSqr_fu_531_sm_p2_address0;
wire grp_computeDiffSqr_fu_531_sm_p2_ce0;
wire grp_computeDiffSqr_fu_531_sm_p2_we0;
wire [31:0] grp_computeDiffSqr_fu_531_sm_p2_d0;
wire [7:0] grp_computeDiffSqr_fu_531_sm_p3_address0;
wire grp_computeDiffSqr_fu_531_sm_p3_ce0;
wire grp_computeDiffSqr_fu_531_sm_p3_we0;
wire [31:0] grp_computeDiffSqr_fu_531_sm_p3_d0;
wire [7:0] grp_computeDiffSqr_fu_531_sn_p0_address0;
wire grp_computeDiffSqr_fu_531_sn_p0_ce0;
wire grp_computeDiffSqr_fu_531_sn_p0_we0;
wire [31:0] grp_computeDiffSqr_fu_531_sn_p0_d0;
wire [7:0] grp_computeDiffSqr_fu_531_sn_p1_address0;
wire grp_computeDiffSqr_fu_531_sn_p1_ce0;
wire grp_computeDiffSqr_fu_531_sn_p1_we0;
wire [31:0] grp_computeDiffSqr_fu_531_sn_p1_d0;
wire [7:0] grp_computeDiffSqr_fu_531_sn_p2_address0;
wire grp_computeDiffSqr_fu_531_sn_p2_ce0;
wire grp_computeDiffSqr_fu_531_sn_p2_we0;
wire [31:0] grp_computeDiffSqr_fu_531_sn_p2_d0;
wire [7:0] grp_computeDiffSqr_fu_531_sn_p3_address0;
wire grp_computeDiffSqr_fu_531_sn_p3_ce0;
wire grp_computeDiffSqr_fu_531_sn_p3_we0;
wire [31:0] grp_computeDiffSqr_fu_531_sn_p3_d0;
wire [7:0] grp_computeDiffSqr_fu_531_sp_p0_address0;
wire grp_computeDiffSqr_fu_531_sp_p0_ce0;
wire grp_computeDiffSqr_fu_531_sp_p0_we0;
wire [31:0] grp_computeDiffSqr_fu_531_sp_p0_d0;
wire [7:0] grp_computeDiffSqr_fu_531_sp_p1_address0;
wire grp_computeDiffSqr_fu_531_sp_p1_ce0;
wire grp_computeDiffSqr_fu_531_sp_p1_we0;
wire [31:0] grp_computeDiffSqr_fu_531_sp_p1_d0;
wire [7:0] grp_computeDiffSqr_fu_531_sp_p2_address0;
wire grp_computeDiffSqr_fu_531_sp_p2_ce0;
wire grp_computeDiffSqr_fu_531_sp_p2_we0;
wire [31:0] grp_computeDiffSqr_fu_531_sp_p2_d0;
wire [7:0] grp_computeDiffSqr_fu_531_sp_p3_address0;
wire grp_computeDiffSqr_fu_531_sp_p3_ce0;
wire grp_computeDiffSqr_fu_531_sp_p3_we0;
wire [31:0] grp_computeDiffSqr_fu_531_sp_p3_d0;
wire [7:0] grp_computeDiffSqr_fu_531_u0_p0_address0;
wire grp_computeDiffSqr_fu_531_u0_p0_ce0;
reg [31:0] grp_computeDiffSqr_fu_531_u0_p0_q0;
wire [7:0] grp_computeDiffSqr_fu_531_u0_p1_address0;
wire grp_computeDiffSqr_fu_531_u0_p1_ce0;
reg [31:0] grp_computeDiffSqr_fu_531_u0_p1_q0;
wire [7:0] grp_computeDiffSqr_fu_531_u0_p2_address0;
wire grp_computeDiffSqr_fu_531_u0_p2_ce0;
reg [31:0] grp_computeDiffSqr_fu_531_u0_p2_q0;
wire [7:0] grp_computeDiffSqr_fu_531_u0_p3_address0;
wire grp_computeDiffSqr_fu_531_u0_p3_ce0;
reg [31:0] grp_computeDiffSqr_fu_531_u0_p3_q0;
wire [7:0] grp_computeDiffSqr_fu_531_u0_p3_address1;
wire grp_computeDiffSqr_fu_531_u0_p3_ce1;
reg [31:0] grp_computeDiffSqr_fu_531_u0_p3_q1;
wire [7:0] grp_computeDiffSqr_fu_531_u1_p0_address0;
wire grp_computeDiffSqr_fu_531_u1_p0_ce0;
reg [31:0] grp_computeDiffSqr_fu_531_u1_p0_q0;
wire [7:0] grp_computeDiffSqr_fu_531_u1_p1_address0;
wire grp_computeDiffSqr_fu_531_u1_p1_ce0;
reg [31:0] grp_computeDiffSqr_fu_531_u1_p1_q0;
wire [7:0] grp_computeDiffSqr_fu_531_u1_p2_address0;
wire grp_computeDiffSqr_fu_531_u1_p2_ce0;
reg [31:0] grp_computeDiffSqr_fu_531_u1_p2_q0;
wire [7:0] grp_computeDiffSqr_fu_531_u1_p3_address0;
wire grp_computeDiffSqr_fu_531_u1_p3_ce0;
reg [31:0] grp_computeDiffSqr_fu_531_u1_p3_q0;
reg grp_computeUG_fu_555_ap_start;
wire grp_computeUG_fu_555_ap_idle;
wire [7:0] grp_computeUG_fu_555_ug_p0_address0;
wire grp_computeUG_fu_555_ug_p0_ce0;
wire grp_computeUG_fu_555_ug_p0_we0;
wire [31:0] grp_computeUG_fu_555_ug_p0_d0;
wire [7:0] grp_computeUG_fu_555_ug_p1_address0;
wire grp_computeUG_fu_555_ug_p1_ce0;
wire grp_computeUG_fu_555_ug_p1_we0;
wire [31:0] grp_computeUG_fu_555_ug_p1_d0;
wire [7:0] grp_computeUG_fu_555_ug_p2_address0;
wire grp_computeUG_fu_555_ug_p2_ce0;
wire grp_computeUG_fu_555_ug_p2_we0;
wire [31:0] grp_computeUG_fu_555_ug_p2_d0;
wire [7:0] grp_computeUG_fu_555_ug_p3_address0;
wire grp_computeUG_fu_555_ug_p3_ce0;
wire grp_computeUG_fu_555_ug_p3_we0;
wire [31:0] grp_computeUG_fu_555_ug_p3_d0;
wire [7:0] grp_computeUG_fu_555_u_p0_address0;
wire grp_computeUG_fu_555_u_p0_ce0;
reg [31:0] grp_computeUG_fu_555_u_p0_q0;
wire [7:0] grp_computeUG_fu_555_u_p1_address0;
wire grp_computeUG_fu_555_u_p1_ce0;
reg [31:0] grp_computeUG_fu_555_u_p1_q0;
wire [7:0] grp_computeUG_fu_555_u_p2_address0;
wire grp_computeUG_fu_555_u_p2_ce0;
reg [31:0] grp_computeUG_fu_555_u_p2_q0;
wire [7:0] grp_computeUG_fu_555_u_p3_address0;
wire grp_computeUG_fu_555_u_p3_ce0;
reg [31:0] grp_computeUG_fu_555_u_p3_q0;
wire [7:0] grp_computeUG_fu_555_g_p0_address0;
wire grp_computeUG_fu_555_g_p0_ce0;
reg [31:0] grp_computeUG_fu_555_g_p0_q0;
wire [7:0] grp_computeUG_fu_555_g_p1_address0;
wire grp_computeUG_fu_555_g_p1_ce0;
reg [31:0] grp_computeUG_fu_555_g_p1_q0;
wire [7:0] grp_computeUG_fu_555_g_p2_address0;
wire grp_computeUG_fu_555_g_p2_ce0;
reg [31:0] grp_computeUG_fu_555_g_p2_q0;
wire [7:0] grp_computeUG_fu_555_g_p3_address0;
wire grp_computeUG_fu_555_g_p3_ce0;
reg [31:0] grp_computeUG_fu_555_g_p3_q0;
reg grp_write_array_fu_571_ap_start;
wire grp_write_array_fu_571_ap_idle;
wire grp_write_array_fu_571_bus_r_req_din;
wire grp_write_array_fu_571_bus_r_req_full_n;
wire grp_write_array_fu_571_bus_r_req_write;
wire grp_write_array_fu_571_bus_r_rsp_dout;
wire grp_write_array_fu_571_bus_r_rsp_empty_n;
wire grp_write_array_fu_571_bus_r_rsp_read;
wire [31:0] grp_write_array_fu_571_bus_r_address;
wire [127:0] grp_write_array_fu_571_bus_r_datain;
wire [127:0] grp_write_array_fu_571_bus_r_dataout;
wire [31:0] grp_write_array_fu_571_bus_r_size;
wire [7:0] grp_write_array_fu_571_data_p0_address0;
wire grp_write_array_fu_571_data_p0_ce0;
reg [31:0] grp_write_array_fu_571_data_p0_q0;
wire [7:0] grp_write_array_fu_571_data_p1_address0;
wire grp_write_array_fu_571_data_p1_ce0;
reg [31:0] grp_write_array_fu_571_data_p1_q0;
wire [7:0] grp_write_array_fu_571_data_p2_address0;
wire grp_write_array_fu_571_data_p2_ce0;
reg [31:0] grp_write_array_fu_571_data_p2_q0;
wire [7:0] grp_write_array_fu_571_data_p3_address0;
wire grp_write_array_fu_571_data_p3_ce0;
reg [31:0] grp_write_array_fu_571_data_p3_q0;
reg grp_uFetch_array_fu_583_ap_start;
wire grp_uFetch_array_fu_583_ap_idle;
wire grp_uFetch_array_fu_583_bus_r_req_din;
wire grp_uFetch_array_fu_583_bus_r_req_full_n;
wire grp_uFetch_array_fu_583_bus_r_req_write;
wire grp_uFetch_array_fu_583_bus_r_rsp_dout;
wire grp_uFetch_array_fu_583_bus_r_rsp_empty_n;
wire grp_uFetch_array_fu_583_bus_r_rsp_read;
wire [31:0] grp_uFetch_array_fu_583_bus_r_address;
wire [127:0] grp_uFetch_array_fu_583_bus_r_datain;
wire [127:0] grp_uFetch_array_fu_583_bus_r_dataout;
wire [31:0] grp_uFetch_array_fu_583_bus_r_size;
wire [7:0] grp_uFetch_array_fu_583_data_p0_address0;
wire grp_uFetch_array_fu_583_data_p0_ce0;
wire grp_uFetch_array_fu_583_data_p0_we0;
wire [31:0] grp_uFetch_array_fu_583_data_p0_d0;
wire [7:0] grp_uFetch_array_fu_583_data_p1_address0;
wire grp_uFetch_array_fu_583_data_p1_ce0;
wire grp_uFetch_array_fu_583_data_p1_we0;
wire [31:0] grp_uFetch_array_fu_583_data_p1_d0;
wire [7:0] grp_uFetch_array_fu_583_data_p2_address0;
wire grp_uFetch_array_fu_583_data_p2_ce0;
wire grp_uFetch_array_fu_583_data_p2_we0;
wire [31:0] grp_uFetch_array_fu_583_data_p2_d0;
wire [7:0] grp_uFetch_array_fu_583_data_p3_address0;
wire grp_uFetch_array_fu_583_data_p3_ce0;
wire grp_uFetch_array_fu_583_data_p3_we0;
wire [31:0] grp_uFetch_array_fu_583_data_p3_d0;
reg grp_fFetch_array_fu_599_ap_start;
wire grp_fFetch_array_fu_599_ap_idle;
wire grp_fFetch_array_fu_599_bus_r_req_din;
wire grp_fFetch_array_fu_599_bus_r_req_full_n;
wire grp_fFetch_array_fu_599_bus_r_req_write;
wire grp_fFetch_array_fu_599_bus_r_rsp_dout;
wire grp_fFetch_array_fu_599_bus_r_rsp_empty_n;
wire grp_fFetch_array_fu_599_bus_r_rsp_read;
wire [31:0] grp_fFetch_array_fu_599_bus_r_address;
wire [127:0] grp_fFetch_array_fu_599_bus_r_datain;
wire [127:0] grp_fFetch_array_fu_599_bus_r_dataout;
wire [31:0] grp_fFetch_array_fu_599_bus_r_size;
wire [7:0] grp_fFetch_array_fu_599_data_p0_address0;
wire grp_fFetch_array_fu_599_data_p0_ce0;
wire grp_fFetch_array_fu_599_data_p0_we0;
wire [31:0] grp_fFetch_array_fu_599_data_p0_d0;
wire [7:0] grp_fFetch_array_fu_599_data_p1_address0;
wire grp_fFetch_array_fu_599_data_p1_ce0;
wire grp_fFetch_array_fu_599_data_p1_we0;
wire [31:0] grp_fFetch_array_fu_599_data_p1_d0;
wire [7:0] grp_fFetch_array_fu_599_data_p2_address0;
wire grp_fFetch_array_fu_599_data_p2_ce0;
wire grp_fFetch_array_fu_599_data_p2_we0;
wire [31:0] grp_fFetch_array_fu_599_data_p2_d0;
wire [7:0] grp_fFetch_array_fu_599_data_p3_address0;
wire grp_fFetch_array_fu_599_data_p3_ce0;
wire grp_fFetch_array_fu_599_data_p3_we0;
wire [31:0] grp_fFetch_array_fu_599_data_p3_d0;
wire [0:0] tmp_fu_615_p2;
wire [0:0] tmp3_fu_630_p2;
wire [0:0] tmp4_fu_635_p2;
wire [0:0] tmp6_fu_645_p2;
wire [0:0] tmp9_fu_660_p2;
wire [0:0] tmp10_fu_665_p2;
wire [0:0] tmp11_fu_670_p2;
wire [0:0] tmp13_fu_680_p2;
wire [0:0] tmp16_fu_695_p2;
wire [0:0] tmp17_fu_700_p2;
wire [0:0] tmp20_fu_715_p2;
wire [0:0] tmp23_fu_730_p2;
wire [0:0] tmp24_fu_735_p2;
wire [0:0] tmp25_fu_740_p2;
wire [0:0] tmp26_fu_745_p2;
wire [0:0] tmp28_fu_755_p2;
wire [0:0] tmp31_fu_770_p2;
wire [0:0] tmp32_fu_775_p2;
wire [0:0] tmp34_fu_785_p2;
wire [0:0] tmp37_fu_800_p2;
wire [0:0] tmp38_fu_805_p2;
wire [0:0] tmp39_fu_810_p2;
wire [0:0] tmp41_fu_820_p2;
wire [0:0] tmp44_fu_835_p2;
wire [0:0] tmp45_fu_840_p2;
wire [0:0] tmp48_fu_855_p2;
wire [0:0] tmp51_fu_870_p2;
wire [0:0] tmp52_fu_875_p2;
wire [0:0] tmp53_fu_880_p2;
wire [0:0] tmp54_fu_885_p2;
wire [0:0] tmp55_fu_890_p2;
reg [7:0] ap_NS_fsm;
parameter ap_const_logic_1 = 1'b1;
parameter ap_const_logic_0 = 1'b0;
parameter ap_ST_st0_fsm_0 = 8'b00000000;
parameter ap_ST_st1_fsm_1 = 8'b00000001;
parameter ap_ST_st2_fsm_2 = 8'b00000010;
parameter ap_ST_st3_fsm_3 = 8'b00000011;
parameter ap_ST_st4_fsm_4 = 8'b00000100;
parameter ap_ST_st5_fsm_5 = 8'b00000101;
parameter ap_ST_st6_fsm_6 = 8'b00000110;
parameter ap_ST_st7_fsm_7 = 8'b00000111;
parameter ap_ST_st8_fsm_8 = 8'b00001000;
parameter ap_ST_st9_fsm_9 = 8'b00001001;
parameter ap_ST_st10_fsm_10 = 8'b00001010;
parameter ap_ST_st11_fsm_11 = 8'b00001011;
parameter ap_ST_st12_fsm_12 = 8'b00001100;
parameter ap_ST_st13_fsm_13 = 8'b00001101;
parameter ap_ST_st14_fsm_14 = 8'b00001110;
parameter ap_ST_st15_fsm_15 = 8'b00001111;
parameter ap_ST_st16_fsm_16 = 8'b00010000;
parameter ap_ST_st17_fsm_17 = 8'b00010001;
parameter ap_ST_st18_fsm_18 = 8'b00010010;
parameter ap_ST_st19_fsm_19 = 8'b00010011;
parameter ap_ST_st20_fsm_20 = 8'b00010100;
parameter ap_ST_st21_fsm_21 = 8'b00010101;
parameter ap_ST_st22_fsm_22 = 8'b00010110;
parameter ap_ST_st23_fsm_23 = 8'b00010111;
parameter ap_ST_st24_fsm_24 = 8'b00011000;
parameter ap_ST_st25_fsm_25 = 8'b00011001;
parameter ap_ST_st26_fsm_26 = 8'b00011010;
parameter ap_ST_st27_fsm_27 = 8'b00011011;
parameter ap_ST_st28_fsm_28 = 8'b00011100;
parameter ap_ST_st29_fsm_29 = 8'b00011101;
parameter ap_ST_st30_fsm_30 = 8'b00011110;
parameter ap_ST_st31_fsm_31 = 8'b00011111;
parameter ap_ST_st32_fsm_32 = 8'b00100000;
parameter ap_ST_st33_fsm_33 = 8'b00100001;
parameter ap_ST_st34_fsm_34 = 8'b00100010;
parameter ap_ST_st35_fsm_35 = 8'b00100011;
parameter ap_ST_st36_fsm_36 = 8'b00100100;
parameter ap_ST_st37_fsm_37 = 8'b00100101;
parameter ap_ST_st38_fsm_38 = 8'b00100110;
parameter ap_ST_st39_fsm_39 = 8'b00100111;
parameter ap_ST_st40_fsm_40 = 8'b00101000;
parameter ap_ST_st41_fsm_41 = 8'b00101001;
parameter ap_ST_st42_fsm_42 = 8'b00101010;
parameter ap_ST_st43_fsm_43 = 8'b00101011;
parameter ap_ST_st44_fsm_44 = 8'b00101100;
parameter ap_ST_st45_fsm_45 = 8'b00101101;
parameter ap_ST_st46_fsm_46 = 8'b00101110;
parameter ap_ST_st47_fsm_47 = 8'b00101111;
parameter ap_ST_st48_fsm_48 = 8'b00110000;
parameter ap_ST_st49_fsm_49 = 8'b00110001;
parameter ap_ST_st50_fsm_50 = 8'b00110010;
parameter ap_ST_st51_fsm_51 = 8'b00110011;
parameter ap_ST_st52_fsm_52 = 8'b00110100;
parameter ap_ST_st53_fsm_53 = 8'b00110101;
parameter ap_ST_st54_fsm_54 = 8'b00110110;
parameter ap_ST_st55_fsm_55 = 8'b00110111;
parameter ap_ST_st56_fsm_56 = 8'b00111000;
parameter ap_ST_st57_fsm_57 = 8'b00111001;
parameter ap_ST_st58_fsm_58 = 8'b00111010;
parameter ap_ST_st59_fsm_59 = 8'b00111011;
parameter ap_ST_st60_fsm_60 = 8'b00111100;
parameter ap_ST_st61_fsm_61 = 8'b00111101;
parameter ap_ST_st62_fsm_62 = 8'b00111110;
parameter ap_ST_st63_fsm_63 = 8'b00111111;
parameter ap_ST_st64_fsm_64 = 8'b01000000;
parameter ap_ST_st65_fsm_65 = 8'b01000001;
parameter ap_ST_st66_fsm_66 = 8'b01000010;
parameter ap_ST_st67_fsm_67 = 8'b01000011;
parameter ap_ST_st68_fsm_68 = 8'b01000100;
parameter ap_ST_st69_fsm_69 = 8'b01000101;
parameter ap_ST_st70_fsm_70 = 8'b01000110;
parameter ap_ST_st71_fsm_71 = 8'b01000111;
parameter ap_ST_st72_fsm_72 = 8'b01001000;
parameter ap_ST_st73_fsm_73 = 8'b01001001;
parameter ap_ST_st74_fsm_74 = 8'b01001010;
parameter ap_ST_st75_fsm_75 = 8'b01001011;
parameter ap_ST_st76_fsm_76 = 8'b01001100;
parameter ap_ST_st77_fsm_77 = 8'b01001101;
parameter ap_ST_st78_fsm_78 = 8'b01001110;
parameter ap_ST_st79_fsm_79 = 8'b01001111;
parameter ap_ST_st80_fsm_80 = 8'b01010000;
parameter ap_ST_st81_fsm_81 = 8'b01010001;
parameter ap_ST_st82_fsm_82 = 8'b01010010;
parameter ap_ST_st83_fsm_83 = 8'b01010011;
parameter ap_ST_st84_fsm_84 = 8'b01010100;
parameter ap_ST_st85_fsm_85 = 8'b01010101;
parameter ap_ST_st86_fsm_86 = 8'b01010110;
parameter ap_ST_st87_fsm_87 = 8'b01010111;
parameter ap_ST_st88_fsm_88 = 8'b01011000;
parameter ap_ST_st89_fsm_89 = 8'b01011001;
parameter ap_ST_st90_fsm_90 = 8'b01011010;
parameter ap_ST_st91_fsm_91 = 8'b01011011;
parameter ap_ST_st92_fsm_92 = 8'b01011100;
parameter ap_ST_st93_fsm_93 = 8'b01011101;
parameter ap_ST_st94_fsm_94 = 8'b01011110;
parameter ap_ST_st95_fsm_95 = 8'b01011111;
parameter ap_ST_st96_fsm_96 = 8'b01100000;
parameter ap_ST_st97_fsm_97 = 8'b01100001;
parameter ap_ST_st98_fsm_98 = 8'b01100010;
parameter ap_ST_st99_fsm_99 = 8'b01100011;
parameter ap_ST_st100_fsm_100 = 8'b01100100;
parameter ap_ST_st101_fsm_101 = 8'b01100101;
parameter ap_ST_st102_fsm_102 = 8'b01100110;
parameter ap_ST_st103_fsm_103 = 8'b01100111;
parameter ap_ST_st104_fsm_104 = 8'b01101000;
parameter ap_ST_st105_fsm_105 = 8'b01101001;
parameter ap_ST_st106_fsm_106 = 8'b01101010;
parameter ap_ST_st107_fsm_107 = 8'b01101011;
parameter ap_ST_st108_fsm_108 = 8'b01101100;
parameter ap_ST_st109_fsm_109 = 8'b01101101;
parameter ap_ST_st110_fsm_110 = 8'b01101110;
parameter ap_ST_st111_fsm_111 = 8'b01101111;
parameter ap_ST_st112_fsm_112 = 8'b01110000;
parameter ap_ST_st113_fsm_113 = 8'b01110001;
parameter ap_ST_st114_fsm_114 = 8'b01110010;
parameter ap_ST_st115_fsm_115 = 8'b01110011;
parameter ap_ST_st116_fsm_116 = 8'b01110100;
parameter ap_ST_st117_fsm_117 = 8'b01110101;
parameter ap_ST_st118_fsm_118 = 8'b01110110;
parameter ap_ST_st119_fsm_119 = 8'b01110111;
parameter ap_ST_st120_fsm_120 = 8'b01111000;
parameter ap_ST_st121_fsm_121 = 8'b01111001;
parameter ap_ST_st122_fsm_122 = 8'b01111010;
parameter ap_ST_st123_fsm_123 = 8'b01111011;
parameter ap_ST_st124_fsm_124 = 8'b01111100;
parameter ap_ST_st125_fsm_125 = 8'b01111101;
parameter ap_ST_st126_fsm_126 = 8'b01111110;
parameter ap_ST_st127_fsm_127 = 8'b01111111;
parameter ap_ST_st128_fsm_128 = 8'b10000000;
parameter ap_ST_st129_fsm_129 = 8'b10000001;
parameter ap_ST_st130_fsm_130 = 8'b10000010;
parameter ap_ST_st131_fsm_131 = 8'b10000011;
parameter ap_ST_st132_fsm_132 = 8'b10000100;
parameter ap_true = 1'b1;
denoise_r1_p3 #(
.DataWidth( 32 ),
.AddressRange( 225 ),
.AddressWidth( 8 ))
r1_p3_U(
.clk( ap_clk ),
.address0( r1_p3_address0 ),
.ce0( r1_p3_ce0 ),
.we0( r1_p3_we0 ),
.d0( r1_p3_d0 ),
.q0( r1_p3_q0 )
);
denoise_r1_p2 #(
.DataWidth( 32 ),
.AddressRange( 225 ),
.AddressWidth( 8 ))
r1_p2_U(
.clk( ap_clk ),
.address0( r1_p2_address0 ),
.ce0( r1_p2_ce0 ),
.we0( r1_p2_we0 ),
.d0( r1_p2_d0 ),
.q0( r1_p2_q0 )
);
denoise_r1_p1 #(
.DataWidth( 32 ),
.AddressRange( 225 ),
.AddressWidth( 8 ))
r1_p1_U(
.clk( ap_clk ),
.address0( r1_p1_address0 ),
.ce0( r1_p1_ce0 ),
.we0( r1_p1_we0 ),
.d0( r1_p1_d0 ),
.q0( r1_p1_q0 )
);
denoise_r1_p0 #(
.DataWidth( 32 ),
.AddressRange( 225 ),
.AddressWidth( 8 ))
r1_p0_U(
.clk( ap_clk ),
.address0( r1_p0_address0 ),
.ce0( r1_p0_ce0 ),
.we0( r1_p0_we0 ),
.d0( r1_p0_d0 ),
.q0( r1_p0_q0 )
);
denoise_r0_p3 #(
.DataWidth( 32 ),
.AddressRange( 225 ),
.AddressWidth( 8 ))
r0_p3_U(
.clk( ap_clk ),
.address0( r0_p3_address0 ),
.ce0( r0_p3_ce0 ),
.we0( r0_p3_we0 ),
.d0( r0_p3_d0 ),
.q0( r0_p3_q0 )
);
denoise_r0_p2 #(
.DataWidth( 32 ),
.AddressRange( 225 ),
.AddressWidth( 8 ))
r0_p2_U(
.clk( ap_clk ),
.address0( r0_p2_address0 ),
.ce0( r0_p2_ce0 ),
.we0( r0_p2_we0 ),
.d0( r0_p2_d0 ),
.q0( r0_p2_q0 )
);
denoise_r0_p1 #(
.DataWidth( 32 ),
.AddressRange( 225 ),
.AddressWidth( 8 ))
r0_p1_U(
.clk( ap_clk ),
.address0( r0_p1_address0 ),
.ce0( r0_p1_ce0 ),
.we0( r0_p1_we0 ),
.d0( r0_p1_d0 ),
.q0( r0_p1_q0 )
);
denoise_r0_p0 #(
.DataWidth( 32 ),
.AddressRange( 225 ),
.AddressWidth( 8 ))
r0_p0_U(
.clk( ap_clk ),
.address0( r0_p0_address0 ),
.ce0( r0_p0_ce0 ),
.we0( r0_p0_we0 ),
.d0( r0_p0_d0 ),
.q0( r0_p0_q0 )
);
denoise_f1_p3 #(
.DataWidth( 32 ),
.AddressRange( 225 ),
.AddressWidth( 8 ))
f1_p3_U(
.clk( ap_clk ),
.address0( f1_p3_address0 ),
.ce0( f1_p3_ce0 ),
.we0( f1_p3_we0 ),
.d0( f1_p3_d0 ),
.q0( f1_p3_q0 )
);
denoise_f1_p2 #(
.DataWidth( 32 ),
.AddressRange( 225 ),
.AddressWidth( 8 ))
f1_p2_U(
.clk( ap_clk ),
.address0( f1_p2_address0 ),
.ce0( f1_p2_ce0 ),
.we0( f1_p2_we0 ),
.d0( f1_p2_d0 ),
.q0( f1_p2_q0 )
);
denoise_f1_p1 #(
.DataWidth( 32 ),
.AddressRange( 225 ),
.AddressWidth( 8 ))
f1_p1_U(
.clk( ap_clk ),
.address0( f1_p1_address0 ),
.ce0( f1_p1_ce0 ),
.we0( f1_p1_we0 ),
.d0( f1_p1_d0 ),
.q0( f1_p1_q0 )
);
denoise_f1_p0 #(
.DataWidth( 32 ),
.AddressRange( 225 ),
.AddressWidth( 8 ))
f1_p0_U(
.clk( ap_clk ),
.address0( f1_p0_address0 ),
.ce0( f1_p0_ce0 ),
.we0( f1_p0_we0 ),
.d0( f1_p0_d0 ),
.q0( f1_p0_q0 )
);
denoise_f0_p3 #(
.DataWidth( 32 ),
.AddressRange( 225 ),
.AddressWidth( 8 ))
f0_p3_U(
.clk( ap_clk ),
.address0( f0_p3_address0 ),
.ce0( f0_p3_ce0 ),
.we0( f0_p3_we0 ),
.d0( f0_p3_d0 ),
.q0( f0_p3_q0 )
);
denoise_f0_p2 #(
.DataWidth( 32 ),
.AddressRange( 225 ),
.AddressWidth( 8 ))
f0_p2_U(
.clk( ap_clk ),
.address0( f0_p2_address0 ),
.ce0( f0_p2_ce0 ),
.we0( f0_p2_we0 ),
.d0( f0_p2_d0 ),
.q0( f0_p2_q0 )
);
denoise_f0_p1 #(
.DataWidth( 32 ),
.AddressRange( 225 ),
.AddressWidth( 8 ))
f0_p1_U(
.clk( ap_clk ),
.address0( f0_p1_address0 ),
.ce0( f0_p1_ce0 ),
.we0( f0_p1_we0 ),
.d0( f0_p1_d0 ),
.q0( f0_p1_q0 )
);
denoise_f0_p0 #(
.DataWidth( 32 ),
.AddressRange( 225 ),
.AddressWidth( 8 ))
f0_p0_U(
.clk( ap_clk ),
.address0( f0_p0_address0 ),
.ce0( f0_p0_ce0 ),
.we0( f0_p0_we0 ),
.d0( f0_p0_d0 ),
.q0( f0_p0_q0 )
);
denoise_g4_p3 #(
.DataWidth( 32 ),
.AddressRange( 225 ),
.AddressWidth( 8 ))
g4_p3_U(
.clk( ap_clk ),
.address0( g4_p3_address0 ),
.ce0( g4_p3_ce0 ),
.we0( g4_p3_we0 ),
.d0( g4_p3_d0 ),
.q0( g4_p3_q0 ),
.address1( g4_p3_address1 ),
.ce1( g4_p3_ce1 ),
.q1( g4_p3_q1 )
);
denoise_g4_p2 #(
.DataWidth( 32 ),
.AddressRange( 225 ),
.AddressWidth( 8 ))
g4_p2_U(
.clk( ap_clk ),
.address0( g4_p2_address0 ),
.ce0( g4_p2_ce0 ),
.we0( g4_p2_we0 ),
.d0( g4_p2_d0 ),
.q0( g4_p2_q0 )
);
denoise_g4_p1 #(
.DataWidth( 32 ),
.AddressRange( 225 ),
.AddressWidth( 8 ))
g4_p1_U(
.clk( ap_clk ),
.address0( g4_p1_address0 ),
.ce0( g4_p1_ce0 ),
.we0( g4_p1_we0 ),
.d0( g4_p1_d0 ),
.q0( g4_p1_q0 )
);
denoise_g4_p0 #(
.DataWidth( 32 ),
.AddressRange( 225 ),
.AddressWidth( 8 ))
g4_p0_U(
.clk( ap_clk ),
.address0( g4_p0_address0 ),
.ce0( g4_p0_ce0 ),
.we0( g4_p0_we0 ),
.d0( g4_p0_d0 ),
.q0( g4_p0_q0 ),
.address1( g4_p0_address1 ),
.ce1( g4_p0_ce1 ),
.q1( g4_p0_q1 )
);
denoise_g3_p3 #(
.DataWidth( 32 ),
.AddressRange( 225 ),
.AddressWidth( 8 ))
g3_p3_U(
.clk( ap_clk ),
.address0( g3_p3_address0 ),
.ce0( g3_p3_ce0 ),
.we0( g3_p3_we0 ),
.d0( g3_p3_d0 ),
.q0( g3_p3_q0 ),
.address1( g3_p3_address1 ),
.ce1( g3_p3_ce1 ),
.q1( g3_p3_q1 )
);
denoise_g3_p2 #(
.DataWidth( 32 ),
.AddressRange( 225 ),
.AddressWidth( 8 ))
g3_p2_U(
.clk( ap_clk ),
.address0( g3_p2_address0 ),
.ce0( g3_p2_ce0 ),
.we0( g3_p2_we0 ),
.d0( g3_p2_d0 ),
.q0( g3_p2_q0 )
);
denoise_g3_p1 #(
.DataWidth( 32 ),
.AddressRange( 225 ),
.AddressWidth( 8 ))
g3_p1_U(
.clk( ap_clk ),
.address0( g3_p1_address0 ),
.ce0( g3_p1_ce0 ),
.we0( g3_p1_we0 ),
.d0( g3_p1_d0 ),
.q0( g3_p1_q0 )
);
denoise_g3_p0 #(
.DataWidth( 32 ),
.AddressRange( 225 ),
.AddressWidth( 8 ))
g3_p0_U(
.clk( ap_clk ),
.address0( g3_p0_address0 ),
.ce0( g3_p0_ce0 ),
.we0( g3_p0_we0 ),
.d0( g3_p0_d0 ),
.q0( g3_p0_q0 ),
.address1( g3_p0_address1 ),
.ce1( g3_p0_ce1 ),
.q1( g3_p0_q1 )
);
denoise_g2_p3 #(
.DataWidth( 32 ),
.AddressRange( 225 ),
.AddressWidth( 8 ))
g2_p3_U(
.clk( ap_clk ),
.address0( g2_p3_address0 ),
.ce0( g2_p3_ce0 ),
.we0( g2_p3_we0 ),
.d0( g2_p3_d0 ),
.q0( g2_p3_q0 ),
.address1( g2_p3_address1 ),
.ce1( g2_p3_ce1 ),
.q1( g2_p3_q1 )
);
denoise_g2_p2 #(
.DataWidth( 32 ),
.AddressRange( 225 ),
.AddressWidth( 8 ))
g2_p2_U(
.clk( ap_clk ),
.address0( g2_p2_address0 ),
.ce0( g2_p2_ce0 ),
.we0( g2_p2_we0 ),
.d0( g2_p2_d0 ),
.q0( g2_p2_q0 )
);
denoise_g2_p1 #(
.DataWidth( 32 ),
.AddressRange( 225 ),
.AddressWidth( 8 ))
g2_p1_U(
.clk( ap_clk ),
.address0( g2_p1_address0 ),
.ce0( g2_p1_ce0 ),
.we0( g2_p1_we0 ),
.d0( g2_p1_d0 ),
.q0( g2_p1_q0 )
);
denoise_g2_p0 #(
.DataWidth( 32 ),
.AddressRange( 225 ),
.AddressWidth( 8 ))
g2_p0_U(
.clk( ap_clk ),
.address0( g2_p0_address0 ),
.ce0( g2_p0_ce0 ),
.we0( g2_p0_we0 ),
.d0( g2_p0_d0 ),
.q0( g2_p0_q0 ),
.address1( g2_p0_address1 ),
.ce1( g2_p0_ce1 ),
.q1( g2_p0_q1 )
);
denoise_g1_p3 #(
.DataWidth( 32 ),
.AddressRange( 225 ),
.AddressWidth( 8 ))
g1_p3_U(
.clk( ap_clk ),
.address0( g1_p3_address0 ),
.ce0( g1_p3_ce0 ),
.we0( g1_p3_we0 ),
.d0( g1_p3_d0 ),
.q0( g1_p3_q0 ),
.address1( g1_p3_address1 ),
.ce1( g1_p3_ce1 ),
.q1( g1_p3_q1 )
);
denoise_g1_p2 #(
.DataWidth( 32 ),
.AddressRange( 225 ),
.AddressWidth( 8 ))
g1_p2_U(
.clk( ap_clk ),
.address0( g1_p2_address0 ),
.ce0( g1_p2_ce0 ),
.we0( g1_p2_we0 ),
.d0( g1_p2_d0 ),
.q0( g1_p2_q0 )
);
denoise_g1_p1 #(
.DataWidth( 32 ),
.AddressRange( 225 ),
.AddressWidth( 8 ))
g1_p1_U(
.clk( ap_clk ),
.address0( g1_p1_address0 ),
.ce0( g1_p1_ce0 ),
.we0( g1_p1_we0 ),
.d0( g1_p1_d0 ),
.q0( g1_p1_q0 )
);
denoise_g1_p0 #(
.DataWidth( 32 ),
.AddressRange( 225 ),
.AddressWidth( 8 ))
g1_p0_U(
.clk( ap_clk ),
.address0( g1_p0_address0 ),
.ce0( g1_p0_ce0 ),
.we0( g1_p0_we0 ),
.d0( g1_p0_d0 ),
.q0( g1_p0_q0 ),
.address1( g1_p0_address1 ),
.ce1( g1_p0_ce1 ),
.q1( g1_p0_q1 )
);
denoise_g0_p3 #(
.DataWidth( 32 ),
.AddressRange( 225 ),
.AddressWidth( 8 ))
g0_p3_U(
.clk( ap_clk ),
.address0( g0_p3_address0 ),
.ce0( g0_p3_ce0 ),
.we0( g0_p3_we0 ),
.d0( g0_p3_d0 ),
.q0( g0_p3_q0 ),
.address1( g0_p3_address1 ),
.ce1( g0_p3_ce1 ),
.q1( g0_p3_q1 )
);
denoise_g0_p2 #(
.DataWidth( 32 ),
.AddressRange( 225 ),
.AddressWidth( 8 ))
g0_p2_U(
.clk( ap_clk ),
.address0( g0_p2_address0 ),
.ce0( g0_p2_ce0 ),
.we0( g0_p2_we0 ),
.d0( g0_p2_d0 ),
.q0( g0_p2_q0 )
);
denoise_g0_p1 #(
.DataWidth( 32 ),
.AddressRange( 225 ),
.AddressWidth( 8 ))
g0_p1_U(
.clk( ap_clk ),
.address0( g0_p1_address0 ),
.ce0( g0_p1_ce0 ),
.we0( g0_p1_we0 ),
.d0( g0_p1_d0 ),
.q0( g0_p1_q0 )
);
denoise_g0_p0 #(
.DataWidth( 32 ),
.AddressRange( 225 ),
.AddressWidth( 8 ))
g0_p0_U(
.clk( ap_clk ),
.address0( g0_p0_address0 ),
.ce0( g0_p0_ce0 ),
.we0( g0_p0_we0 ),
.d0( g0_p0_d0 ),
.q0( g0_p0_q0 ),
.address1( g0_p0_address1 ),
.ce1( g0_p0_ce1 ),
.q1( g0_p0_q1 )
);
denoise_ug3_p3 #(
.DataWidth( 32 ),
.AddressRange( 225 ),
.AddressWidth( 8 ))
ug3_p3_U(
.clk( ap_clk ),
.address0( ug3_p3_address0 ),
.ce0( ug3_p3_ce0 ),
.we0( ug3_p3_we0 ),
.d0( ug3_p3_d0 ),
.q0( ug3_p3_q0 ),
.address1( ug3_p3_address1 ),
.ce1( ug3_p3_ce1 ),
.q1( ug3_p3_q1 )
);
denoise_ug3_p2 #(
.DataWidth( 32 ),
.AddressRange( 225 ),
.AddressWidth( 8 ))
ug3_p2_U(
.clk( ap_clk ),
.address0( ug3_p2_address0 ),
.ce0( ug3_p2_ce0 ),
.we0( ug3_p2_we0 ),
.d0( ug3_p2_d0 ),
.q0( ug3_p2_q0 )
);
denoise_ug3_p1 #(
.DataWidth( 32 ),
.AddressRange( 225 ),
.AddressWidth( 8 ))
ug3_p1_U(
.clk( ap_clk ),
.address0( ug3_p1_address0 ),
.ce0( ug3_p1_ce0 ),
.we0( ug3_p1_we0 ),
.d0( ug3_p1_d0 ),
.q0( ug3_p1_q0 )
);
denoise_ug3_p0 #(
.DataWidth( 32 ),
.AddressRange( 225 ),
.AddressWidth( 8 ))
ug3_p0_U(
.clk( ap_clk ),
.address0( ug3_p0_address0 ),
.ce0( ug3_p0_ce0 ),
.we0( ug3_p0_we0 ),
.d0( ug3_p0_d0 ),
.q0( ug3_p0_q0 ),
.address1( ug3_p0_address1 ),
.ce1( ug3_p0_ce1 ),
.q1( ug3_p0_q1 )
);
denoise_ug2_p3 #(
.DataWidth( 32 ),
.AddressRange( 225 ),
.AddressWidth( 8 ))
ug2_p3_U(
.clk( ap_clk ),
.address0( ug2_p3_address0 ),
.ce0( ug2_p3_ce0 ),
.we0( ug2_p3_we0 ),
.d0( ug2_p3_d0 ),
.q0( ug2_p3_q0 ),
.address1( ug2_p3_address1 ),
.ce1( ug2_p3_ce1 ),
.q1( ug2_p3_q1 )
);
denoise_ug2_p2 #(
.DataWidth( 32 ),
.AddressRange( 225 ),
.AddressWidth( 8 ))
ug2_p2_U(
.clk( ap_clk ),
.address0( ug2_p2_address0 ),
.ce0( ug2_p2_ce0 ),
.we0( ug2_p2_we0 ),
.d0( ug2_p2_d0 ),
.q0( ug2_p2_q0 )
);
denoise_ug2_p1 #(
.DataWidth( 32 ),
.AddressRange( 225 ),
.AddressWidth( 8 ))
ug2_p1_U(
.clk( ap_clk ),
.address0( ug2_p1_address0 ),
.ce0( ug2_p1_ce0 ),
.we0( ug2_p1_we0 ),
.d0( ug2_p1_d0 ),
.q0( ug2_p1_q0 )
);
denoise_ug2_p0 #(
.DataWidth( 32 ),
.AddressRange( 225 ),
.AddressWidth( 8 ))
ug2_p0_U(
.clk( ap_clk ),
.address0( ug2_p0_address0 ),
.ce0( ug2_p0_ce0 ),
.we0( ug2_p0_we0 ),
.d0( ug2_p0_d0 ),
.q0( ug2_p0_q0 ),
.address1( ug2_p0_address1 ),
.ce1( ug2_p0_ce1 ),
.q1( ug2_p0_q1 )
);
denoise_ug1_p3 #(
.DataWidth( 32 ),
.AddressRange( 225 ),
.AddressWidth( 8 ))
ug1_p3_U(
.clk( ap_clk ),
.address0( ug1_p3_address0 ),
.ce0( ug1_p3_ce0 ),
.we0( ug1_p3_we0 ),
.d0( ug1_p3_d0 ),
.q0( ug1_p3_q0 ),
.address1( ug1_p3_address1 ),
.ce1( ug1_p3_ce1 ),
.q1( ug1_p3_q1 )
);
denoise_ug1_p2 #(
.DataWidth( 32 ),
.AddressRange( 225 ),
.AddressWidth( 8 ))
ug1_p2_U(
.clk( ap_clk ),
.address0( ug1_p2_address0 ),
.ce0( ug1_p2_ce0 ),
.we0( ug1_p2_we0 ),
.d0( ug1_p2_d0 ),
.q0( ug1_p2_q0 )
);
denoise_ug1_p1 #(
.DataWidth( 32 ),
.AddressRange( 225 ),
.AddressWidth( 8 ))
ug1_p1_U(
.clk( ap_clk ),
.address0( ug1_p1_address0 ),
.ce0( ug1_p1_ce0 ),
.we0( ug1_p1_we0 ),
.d0( ug1_p1_d0 ),
.q0( ug1_p1_q0 )
);
denoise_ug1_p0 #(
.DataWidth( 32 ),
.AddressRange( 225 ),
.AddressWidth( 8 ))
ug1_p0_U(
.clk( ap_clk ),
.address0( ug1_p0_address0 ),
.ce0( ug1_p0_ce0 ),
.we0( ug1_p0_we0 ),
.d0( ug1_p0_d0 ),
.q0( ug1_p0_q0 ),
.address1( ug1_p0_address1 ),
.ce1( ug1_p0_ce1 ),
.q1( ug1_p0_q1 )
);
denoise_ug0_p3 #(
.DataWidth( 32 ),
.AddressRange( 225 ),
.AddressWidth( 8 ))
ug0_p3_U(
.clk( ap_clk ),
.address0( ug0_p3_address0 ),
.ce0( ug0_p3_ce0 ),
.we0( ug0_p3_we0 ),
.d0( ug0_p3_d0 ),
.q0( ug0_p3_q0 ),
.address1( ug0_p3_address1 ),
.ce1( ug0_p3_ce1 ),
.q1( ug0_p3_q1 )
);
denoise_ug0_p2 #(
.DataWidth( 32 ),
.AddressRange( 225 ),
.AddressWidth( 8 ))
ug0_p2_U(
.clk( ap_clk ),
.address0( ug0_p2_address0 ),
.ce0( ug0_p2_ce0 ),
.we0( ug0_p2_we0 ),
.d0( ug0_p2_d0 ),
.q0( ug0_p2_q0 )
);
denoise_ug0_p1 #(
.DataWidth( 32 ),
.AddressRange( 225 ),
.AddressWidth( 8 ))
ug0_p1_U(
.clk( ap_clk ),
.address0( ug0_p1_address0 ),
.ce0( ug0_p1_ce0 ),
.we0( ug0_p1_we0 ),
.d0( ug0_p1_d0 ),
.q0( ug0_p1_q0 )
);
denoise_ug0_p0 #(
.DataWidth( 32 ),
.AddressRange( 225 ),
.AddressWidth( 8 ))
ug0_p0_U(
.clk( ap_clk ),
.address0( ug0_p0_address0 ),
.ce0( ug0_p0_ce0 ),
.we0( ug0_p0_we0 ),
.d0( ug0_p0_d0 ),
.q0( ug0_p0_q0 ),
.address1( ug0_p0_address1 ),
.ce1( ug0_p0_ce1 ),
.q1( ug0_p0_q1 )
);
denoise_sp2_p3 #(
.DataWidth( 32 ),
.AddressRange( 225 ),
.AddressWidth( 8 ))
sp2_p3_U(
.clk( ap_clk ),
.address0( sp2_p3_address0 ),
.ce0( sp2_p3_ce0 ),
.we0( sp2_p3_we0 ),
.d0( sp2_p3_d0 ),
.q0( sp2_p3_q0 )
);
denoise_sp2_p2 #(
.DataWidth( 32 ),
.AddressRange( 225 ),
.AddressWidth( 8 ))
sp2_p2_U(
.clk( ap_clk ),
.address0( sp2_p2_address0 ),
.ce0( sp2_p2_ce0 ),
.we0( sp2_p2_we0 ),
.d0( sp2_p2_d0 ),
.q0( sp2_p2_q0 )
);
denoise_sp2_p1 #(
.DataWidth( 32 ),
.AddressRange( 225 ),
.AddressWidth( 8 ))
sp2_p1_U(
.clk( ap_clk ),
.address0( sp2_p1_address0 ),
.ce0( sp2_p1_ce0 ),
.we0( sp2_p1_we0 ),
.d0( sp2_p1_d0 ),
.q0( sp2_p1_q0 )
);
denoise_sp2_p0 #(
.DataWidth( 32 ),
.AddressRange( 225 ),
.AddressWidth( 8 ))
sp2_p0_U(
.clk( ap_clk ),
.address0( sp2_p0_address0 ),
.ce0( sp2_p0_ce0 ),
.we0( sp2_p0_we0 ),
.d0( sp2_p0_d0 ),
.q0( sp2_p0_q0 )
);
denoise_sp1_p3 #(
.DataWidth( 32 ),
.AddressRange( 225 ),
.AddressWidth( 8 ))
sp1_p3_U(
.clk( ap_clk ),
.address0( sp1_p3_address0 ),
.ce0( sp1_p3_ce0 ),
.we0( sp1_p3_we0 ),
.d0( sp1_p3_d0 ),
.q0( sp1_p3_q0 )
);
denoise_sp1_p2 #(
.DataWidth( 32 ),
.AddressRange( 225 ),
.AddressWidth( 8 ))
sp1_p2_U(
.clk( ap_clk ),
.address0( sp1_p2_address0 ),
.ce0( sp1_p2_ce0 ),
.we0( sp1_p2_we0 ),
.d0( sp1_p2_d0 ),
.q0( sp1_p2_q0 )
);
denoise_sp1_p1 #(
.DataWidth( 32 ),
.AddressRange( 225 ),
.AddressWidth( 8 ))
sp1_p1_U(
.clk( ap_clk ),
.address0( sp1_p1_address0 ),
.ce0( sp1_p1_ce0 ),
.we0( sp1_p1_we0 ),
.d0( sp1_p1_d0 ),
.q0( sp1_p1_q0 )
);
denoise_sp1_p0 #(
.DataWidth( 32 ),
.AddressRange( 225 ),
.AddressWidth( 8 ))
sp1_p0_U(
.clk( ap_clk ),
.address0( sp1_p0_address0 ),
.ce0( sp1_p0_ce0 ),
.we0( sp1_p0_we0 ),
.d0( sp1_p0_d0 ),
.q0( sp1_p0_q0 )
);
denoise_sp0_p3 #(
.DataWidth( 32 ),
.AddressRange( 225 ),
.AddressWidth( 8 ))
sp0_p3_U(
.clk( ap_clk ),
.address0( sp0_p3_address0 ),
.ce0( sp0_p3_ce0 ),
.we0( sp0_p3_we0 ),
.d0( sp0_p3_d0 ),
.q0( sp0_p3_q0 )
);
denoise_sp0_p2 #(
.DataWidth( 32 ),
.AddressRange( 225 ),
.AddressWidth( 8 ))
sp0_p2_U(
.clk( ap_clk ),
.address0( sp0_p2_address0 ),
.ce0( sp0_p2_ce0 ),
.we0( sp0_p2_we0 ),
.d0( sp0_p2_d0 ),
.q0( sp0_p2_q0 )
);
denoise_sp0_p1 #(
.DataWidth( 32 ),
.AddressRange( 225 ),
.AddressWidth( 8 ))
sp0_p1_U(
.clk( ap_clk ),
.address0( sp0_p1_address0 ),
.ce0( sp0_p1_ce0 ),
.we0( sp0_p1_we0 ),
.d0( sp0_p1_d0 ),
.q0( sp0_p1_q0 )
);
denoise_sp0_p0 #(
.DataWidth( 32 ),
.AddressRange( 225 ),
.AddressWidth( 8 ))
sp0_p0_U(
.clk( ap_clk ),
.address0( sp0_p0_address0 ),
.ce0( sp0_p0_ce0 ),
.we0( sp0_p0_we0 ),
.d0( sp0_p0_d0 ),
.q0( sp0_p0_q0 )
);
denoise_sn1_p3 #(
.DataWidth( 32 ),
.AddressRange( 225 ),
.AddressWidth( 8 ))
sn1_p3_U(
.clk( ap_clk ),
.address0( sn1_p3_address0 ),
.ce0( sn1_p3_ce0 ),
.we0( sn1_p3_we0 ),
.d0( sn1_p3_d0 ),
.q0( sn1_p3_q0 )
);
denoise_sn1_p2 #(
.DataWidth( 32 ),
.AddressRange( 225 ),
.AddressWidth( 8 ))
sn1_p2_U(
.clk( ap_clk ),
.address0( sn1_p2_address0 ),
.ce0( sn1_p2_ce0 ),
.we0( sn1_p2_we0 ),
.d0( sn1_p2_d0 ),
.q0( sn1_p2_q0 )
);
denoise_sn1_p1 #(
.DataWidth( 32 ),
.AddressRange( 225 ),
.AddressWidth( 8 ))
sn1_p1_U(
.clk( ap_clk ),
.address0( sn1_p1_address0 ),
.ce0( sn1_p1_ce0 ),
.we0( sn1_p1_we0 ),
.d0( sn1_p1_d0 ),
.q0( sn1_p1_q0 )
);
denoise_sn1_p0 #(
.DataWidth( 32 ),
.AddressRange( 225 ),
.AddressWidth( 8 ))
sn1_p0_U(
.clk( ap_clk ),
.address0( sn1_p0_address0 ),
.ce0( sn1_p0_ce0 ),
.we0( sn1_p0_we0 ),
.d0( sn1_p0_d0 ),
.q0( sn1_p0_q0 ),
.address1( sn1_p0_address1 ),
.ce1( sn1_p0_ce1 ),
.q1( sn1_p0_q1 )
);
denoise_sn0_p3 #(
.DataWidth( 32 ),
.AddressRange( 225 ),
.AddressWidth( 8 ))
sn0_p3_U(
.clk( ap_clk ),
.address0( sn0_p3_address0 ),
.ce0( sn0_p3_ce0 ),
.we0( sn0_p3_we0 ),
.d0( sn0_p3_d0 ),
.q0( sn0_p3_q0 )
);
denoise_sn0_p2 #(
.DataWidth( 32 ),
.AddressRange( 225 ),
.AddressWidth( 8 ))
sn0_p2_U(
.clk( ap_clk ),
.address0( sn0_p2_address0 ),
.ce0( sn0_p2_ce0 ),
.we0( sn0_p2_we0 ),
.d0( sn0_p2_d0 ),
.q0( sn0_p2_q0 )
);
denoise_sn0_p1 #(
.DataWidth( 32 ),
.AddressRange( 225 ),
.AddressWidth( 8 ))
sn0_p1_U(
.clk( ap_clk ),
.address0( sn0_p1_address0 ),
.ce0( sn0_p1_ce0 ),
.we0( sn0_p1_we0 ),
.d0( sn0_p1_d0 ),
.q0( sn0_p1_q0 )
);
denoise_sn0_p0 #(
.DataWidth( 32 ),
.AddressRange( 225 ),
.AddressWidth( 8 ))
sn0_p0_U(
.clk( ap_clk ),
.address0( sn0_p0_address0 ),
.ce0( sn0_p0_ce0 ),
.we0( sn0_p0_we0 ),
.d0( sn0_p0_d0 ),
.q0( sn0_p0_q0 ),
.address1( sn0_p0_address1 ),
.ce1( sn0_p0_ce1 ),
.q1( sn0_p0_q1 )
);
denoise_sm1_p3 #(
.DataWidth( 32 ),
.AddressRange( 225 ),
.AddressWidth( 8 ))
sm1_p3_U(
.clk( ap_clk ),
.address0( sm1_p3_address0 ),
.ce0( sm1_p3_ce0 ),
.we0( sm1_p3_we0 ),
.d0( sm1_p3_d0 ),
.q0( sm1_p3_q0 )
);
denoise_sm1_p2 #(
.DataWidth( 32 ),
.AddressRange( 225 ),
.AddressWidth( 8 ))
sm1_p2_U(
.clk( ap_clk ),
.address0( sm1_p2_address0 ),
.ce0( sm1_p2_ce0 ),
.we0( sm1_p2_we0 ),
.d0( sm1_p2_d0 ),
.q0( sm1_p2_q0 )
);
denoise_sm1_p1 #(
.DataWidth( 32 ),
.AddressRange( 225 ),
.AddressWidth( 8 ))
sm1_p1_U(
.clk( ap_clk ),
.address0( sm1_p1_address0 ),
.ce0( sm1_p1_ce0 ),
.we0( sm1_p1_we0 ),
.d0( sm1_p1_d0 ),
.q0( sm1_p1_q0 )
);
denoise_sm1_p0 #(
.DataWidth( 32 ),
.AddressRange( 225 ),
.AddressWidth( 8 ))
sm1_p0_U(
.clk( ap_clk ),
.address0( sm1_p0_address0 ),
.ce0( sm1_p0_ce0 ),
.we0( sm1_p0_we0 ),
.d0( sm1_p0_d0 ),
.q0( sm1_p0_q0 )
);
denoise_sm0_p3 #(
.DataWidth( 32 ),
.AddressRange( 225 ),
.AddressWidth( 8 ))
sm0_p3_U(
.clk( ap_clk ),
.address0( sm0_p3_address0 ),
.ce0( sm0_p3_ce0 ),
.we0( sm0_p3_we0 ),
.d0( sm0_p3_d0 ),
.q0( sm0_p3_q0 )
);
denoise_sm0_p2 #(
.DataWidth( 32 ),
.AddressRange( 225 ),
.AddressWidth( 8 ))
sm0_p2_U(
.clk( ap_clk ),
.address0( sm0_p2_address0 ),
.ce0( sm0_p2_ce0 ),
.we0( sm0_p2_we0 ),
.d0( sm0_p2_d0 ),
.q0( sm0_p2_q0 )
);
denoise_sm0_p1 #(
.DataWidth( 32 ),
.AddressRange( 225 ),
.AddressWidth( 8 ))
sm0_p1_U(
.clk( ap_clk ),
.address0( sm0_p1_address0 ),
.ce0( sm0_p1_ce0 ),
.we0( sm0_p1_we0 ),
.d0( sm0_p1_d0 ),
.q0( sm0_p1_q0 )
);
denoise_sm0_p0 #(
.DataWidth( 32 ),
.AddressRange( 225 ),
.AddressWidth( 8 ))
sm0_p0_U(
.clk( ap_clk ),
.address0( sm0_p0_address0 ),
.ce0( sm0_p0_ce0 ),
.we0( sm0_p0_we0 ),
.d0( sm0_p0_d0 ),
.q0( sm0_p0_q0 )
);
denoise_u6_p3 #(
.DataWidth( 32 ),
.AddressRange( 225 ),
.AddressWidth( 8 ))
u6_p3_U(
.clk( ap_clk ),
.address0( u6_p3_address0 ),
.ce0( u6_p3_ce0 ),
.we0( u6_p3_we0 ),
.d0( u6_p3_d0 ),
.q0( u6_p3_q0 ),
.address1( u6_p3_address1 ),
.ce1( u6_p3_ce1 ),
.q1( u6_p3_q1 )
);
denoise_u6_p2 #(
.DataWidth( 32 ),
.AddressRange( 225 ),
.AddressWidth( 8 ))
u6_p2_U(
.clk( ap_clk ),
.address0( u6_p2_address0 ),
.ce0( u6_p2_ce0 ),
.we0( u6_p2_we0 ),
.d0( u6_p2_d0 ),
.q0( u6_p2_q0 )
);
denoise_u6_p1 #(
.DataWidth( 32 ),
.AddressRange( 225 ),
.AddressWidth( 8 ))
u6_p1_U(
.clk( ap_clk ),
.address0( u6_p1_address0 ),
.ce0( u6_p1_ce0 ),
.we0( u6_p1_we0 ),
.d0( u6_p1_d0 ),
.q0( u6_p1_q0 )
);
denoise_u6_p0 #(
.DataWidth( 32 ),
.AddressRange( 225 ),
.AddressWidth( 8 ))
u6_p0_U(
.clk( ap_clk ),
.address0( u6_p0_address0 ),
.ce0( u6_p0_ce0 ),
.we0( u6_p0_we0 ),
.d0( u6_p0_d0 ),
.q0( u6_p0_q0 )
);
denoise_u5_p3 #(
.DataWidth( 32 ),
.AddressRange( 225 ),
.AddressWidth( 8 ))
u5_p3_U(
.clk( ap_clk ),
.address0( u5_p3_address0 ),
.ce0( u5_p3_ce0 ),
.we0( u5_p3_we0 ),
.d0( u5_p3_d0 ),
.q0( u5_p3_q0 ),
.address1( u5_p3_address1 ),
.ce1( u5_p3_ce1 ),
.q1( u5_p3_q1 )
);
denoise_u5_p2 #(
.DataWidth( 32 ),
.AddressRange( 225 ),
.AddressWidth( 8 ))
u5_p2_U(
.clk( ap_clk ),
.address0( u5_p2_address0 ),
.ce0( u5_p2_ce0 ),
.we0( u5_p2_we0 ),
.d0( u5_p2_d0 ),
.q0( u5_p2_q0 )
);
denoise_u5_p1 #(
.DataWidth( 32 ),
.AddressRange( 225 ),
.AddressWidth( 8 ))
u5_p1_U(
.clk( ap_clk ),
.address0( u5_p1_address0 ),
.ce0( u5_p1_ce0 ),
.we0( u5_p1_we0 ),
.d0( u5_p1_d0 ),
.q0( u5_p1_q0 )
);
denoise_u5_p0 #(
.DataWidth( 32 ),
.AddressRange( 225 ),
.AddressWidth( 8 ))
u5_p0_U(
.clk( ap_clk ),
.address0( u5_p0_address0 ),
.ce0( u5_p0_ce0 ),
.we0( u5_p0_we0 ),
.d0( u5_p0_d0 ),
.q0( u5_p0_q0 )
);
denoise_u4_p3 #(
.DataWidth( 32 ),
.AddressRange( 225 ),
.AddressWidth( 8 ))
u4_p3_U(
.clk( ap_clk ),
.address0( u4_p3_address0 ),
.ce0( u4_p3_ce0 ),
.we0( u4_p3_we0 ),
.d0( u4_p3_d0 ),
.q0( u4_p3_q0 ),
.address1( u4_p3_address1 ),
.ce1( u4_p3_ce1 ),
.q1( u4_p3_q1 )
);
denoise_u4_p2 #(
.DataWidth( 32 ),
.AddressRange( 225 ),
.AddressWidth( 8 ))
u4_p2_U(
.clk( ap_clk ),
.address0( u4_p2_address0 ),
.ce0( u4_p2_ce0 ),
.we0( u4_p2_we0 ),
.d0( u4_p2_d0 ),
.q0( u4_p2_q0 )
);
denoise_u4_p1 #(
.DataWidth( 32 ),
.AddressRange( 225 ),
.AddressWidth( 8 ))
u4_p1_U(
.clk( ap_clk ),
.address0( u4_p1_address0 ),
.ce0( u4_p1_ce0 ),
.we0( u4_p1_we0 ),
.d0( u4_p1_d0 ),
.q0( u4_p1_q0 )
);
denoise_u4_p0 #(
.DataWidth( 32 ),
.AddressRange( 225 ),
.AddressWidth( 8 ))
u4_p0_U(
.clk( ap_clk ),
.address0( u4_p0_address0 ),
.ce0( u4_p0_ce0 ),
.we0( u4_p0_we0 ),
.d0( u4_p0_d0 ),
.q0( u4_p0_q0 )
);
denoise_u3_p3 #(
.DataWidth( 32 ),
.AddressRange( 225 ),
.AddressWidth( 8 ))
u3_p3_U(
.clk( ap_clk ),
.address0( u3_p3_address0 ),
.ce0( u3_p3_ce0 ),
.we0( u3_p3_we0 ),
.d0( u3_p3_d0 ),
.q0( u3_p3_q0 ),
.address1( u3_p3_address1 ),
.ce1( u3_p3_ce1 ),
.q1( u3_p3_q1 )
);
denoise_u3_p2 #(
.DataWidth( 32 ),
.AddressRange( 225 ),
.AddressWidth( 8 ))
u3_p2_U(
.clk( ap_clk ),
.address0( u3_p2_address0 ),
.ce0( u3_p2_ce0 ),
.we0( u3_p2_we0 ),
.d0( u3_p2_d0 ),
.q0( u3_p2_q0 )
);
denoise_u3_p1 #(
.DataWidth( 32 ),
.AddressRange( 225 ),
.AddressWidth( 8 ))
u3_p1_U(
.clk( ap_clk ),
.address0( u3_p1_address0 ),
.ce0( u3_p1_ce0 ),
.we0( u3_p1_we0 ),
.d0( u3_p1_d0 ),
.q0( u3_p1_q0 )
);
denoise_u3_p0 #(
.DataWidth( 32 ),
.AddressRange( 225 ),
.AddressWidth( 8 ))
u3_p0_U(
.clk( ap_clk ),
.address0( u3_p0_address0 ),
.ce0( u3_p0_ce0 ),
.we0( u3_p0_we0 ),
.d0( u3_p0_d0 ),
.q0( u3_p0_q0 )
);
denoise_u2_p3 #(
.DataWidth( 32 ),
.AddressRange( 225 ),
.AddressWidth( 8 ))
u2_p3_U(
.clk( ap_clk ),
.address0( u2_p3_address0 ),
.ce0( u2_p3_ce0 ),
.we0( u2_p3_we0 ),
.d0( u2_p3_d0 ),
.q0( u2_p3_q0 ),
.address1( u2_p3_address1 ),
.ce1( u2_p3_ce1 ),
.q1( u2_p3_q1 )
);
denoise_u2_p2 #(
.DataWidth( 32 ),
.AddressRange( 225 ),
.AddressWidth( 8 ))
u2_p2_U(
.clk( ap_clk ),
.address0( u2_p2_address0 ),
.ce0( u2_p2_ce0 ),
.we0( u2_p2_we0 ),
.d0( u2_p2_d0 ),
.q0( u2_p2_q0 )
);
denoise_u2_p1 #(
.DataWidth( 32 ),
.AddressRange( 225 ),
.AddressWidth( 8 ))
u2_p1_U(
.clk( ap_clk ),
.address0( u2_p1_address0 ),
.ce0( u2_p1_ce0 ),
.we0( u2_p1_we0 ),
.d0( u2_p1_d0 ),
.q0( u2_p1_q0 )
);
denoise_u2_p0 #(
.DataWidth( 32 ),
.AddressRange( 225 ),
.AddressWidth( 8 ))
u2_p0_U(
.clk( ap_clk ),
.address0( u2_p0_address0 ),
.ce0( u2_p0_ce0 ),
.we0( u2_p0_we0 ),
.d0( u2_p0_d0 ),
.q0( u2_p0_q0 )
);
denoise_u1_p3 #(
.DataWidth( 32 ),
.AddressRange( 225 ),
.AddressWidth( 8 ))
u1_p3_U(
.clk( ap_clk ),
.address0( u1_p3_address0 ),
.ce0( u1_p3_ce0 ),
.we0( u1_p3_we0 ),
.d0( u1_p3_d0 ),
.q0( u1_p3_q0 ),
.address1( u1_p3_address1 ),
.ce1( u1_p3_ce1 ),
.q1( u1_p3_q1 )
);
denoise_u1_p2 #(
.DataWidth( 32 ),
.AddressRange( 225 ),
.AddressWidth( 8 ))
u1_p2_U(
.clk( ap_clk ),
.address0( u1_p2_address0 ),
.ce0( u1_p2_ce0 ),
.we0( u1_p2_we0 ),
.d0( u1_p2_d0 ),
.q0( u1_p2_q0 )
);
denoise_u1_p1 #(
.DataWidth( 32 ),
.AddressRange( 225 ),
.AddressWidth( 8 ))
u1_p1_U(
.clk( ap_clk ),
.address0( u1_p1_address0 ),
.ce0( u1_p1_ce0 ),
.we0( u1_p1_we0 ),
.d0( u1_p1_d0 ),
.q0( u1_p1_q0 )
);
denoise_u1_p0 #(
.DataWidth( 32 ),
.AddressRange( 225 ),
.AddressWidth( 8 ))
u1_p0_U(
.clk( ap_clk ),
.address0( u1_p0_address0 ),
.ce0( u1_p0_ce0 ),
.we0( u1_p0_we0 ),
.d0( u1_p0_d0 ),
.q0( u1_p0_q0 )
);
denoise_u0_p3 #(
.DataWidth( 32 ),
.AddressRange( 225 ),
.AddressWidth( 8 ))
u0_p3_U(
.clk( ap_clk ),
.address0( u0_p3_address0 ),
.ce0( u0_p3_ce0 ),
.we0( u0_p3_we0 ),
.d0( u0_p3_d0 ),
.q0( u0_p3_q0 ),
.address1( u0_p3_address1 ),
.ce1( u0_p3_ce1 ),
.q1( u0_p3_q1 )
);
denoise_u0_p2 #(
.DataWidth( 32 ),
.AddressRange( 225 ),
.AddressWidth( 8 ))
u0_p2_U(
.clk( ap_clk ),
.address0( u0_p2_address0 ),
.ce0( u0_p2_ce0 ),
.we0( u0_p2_we0 ),
.d0( u0_p2_d0 ),
.q0( u0_p2_q0 )
);
denoise_u0_p1 #(
.DataWidth( 32 ),
.AddressRange( 225 ),
.AddressWidth( 8 ))
u0_p1_U(
.clk( ap_clk ),
.address0( u0_p1_address0 ),
.ce0( u0_p1_ce0 ),
.we0( u0_p1_we0 ),
.d0( u0_p1_d0 ),
.q0( u0_p1_q0 )
);
denoise_u0_p0 #(
.DataWidth( 32 ),
.AddressRange( 225 ),
.AddressWidth( 8 ))
u0_p0_U(
.clk( ap_clk ),
.address0( u0_p0_address0 ),
.ce0( u0_p0_ce0 ),
.we0( u0_p0_we0 ),
.d0( u0_p0_d0 ),
.q0( u0_p0_q0 )
);
computeResult grp_computeResult_fu_467(
.ap_clk( ap_clk ),
.ap_rst( ap_rst ),
.ap_start( grp_computeResult_fu_467_ap_start ),
.ap_done( grp_computeResult_fu_467_ap_done ),
.ap_idle( grp_computeResult_fu_467_ap_idle ),
.r_p0_address0( grp_computeResult_fu_467_r_p0_address0 ),
.r_p0_ce0( grp_computeResult_fu_467_r_p0_ce0 ),
.r_p0_we0( grp_computeResult_fu_467_r_p0_we0 ),
.r_p0_d0( grp_computeResult_fu_467_r_p0_d0 ),
.r_p1_address0( grp_computeResult_fu_467_r_p1_address0 ),
.r_p1_ce0( grp_computeResult_fu_467_r_p1_ce0 ),
.r_p1_we0( grp_computeResult_fu_467_r_p1_we0 ),
.r_p1_d0( grp_computeResult_fu_467_r_p1_d0 ),
.r_p2_address0( grp_computeResult_fu_467_r_p2_address0 ),
.r_p2_ce0( grp_computeResult_fu_467_r_p2_ce0 ),
.r_p2_we0( grp_computeResult_fu_467_r_p2_we0 ),
.r_p2_d0( grp_computeResult_fu_467_r_p2_d0 ),
.r_p3_address0( grp_computeResult_fu_467_r_p3_address0 ),
.r_p3_ce0( grp_computeResult_fu_467_r_p3_ce0 ),
.r_p3_we0( grp_computeResult_fu_467_r_p3_we0 ),
.r_p3_d0( grp_computeResult_fu_467_r_p3_d0 ),
.u_p0_address0( grp_computeResult_fu_467_u_p0_address0 ),
.u_p0_ce0( grp_computeResult_fu_467_u_p0_ce0 ),
.u_p0_q0( grp_computeResult_fu_467_u_p0_q0 ),
.u_p1_address0( grp_computeResult_fu_467_u_p1_address0 ),
.u_p1_ce0( grp_computeResult_fu_467_u_p1_ce0 ),
.u_p1_q0( grp_computeResult_fu_467_u_p1_q0 ),
.u_p2_address0( grp_computeResult_fu_467_u_p2_address0 ),
.u_p2_ce0( grp_computeResult_fu_467_u_p2_ce0 ),
.u_p2_q0( grp_computeResult_fu_467_u_p2_q0 ),
.u_p3_address0( grp_computeResult_fu_467_u_p3_address0 ),
.u_p3_ce0( grp_computeResult_fu_467_u_p3_ce0 ),
.u_p3_q0( grp_computeResult_fu_467_u_p3_q0 ),
.ug0_p0_address0( grp_computeResult_fu_467_ug0_p0_address0 ),
.ug0_p0_ce0( grp_computeResult_fu_467_ug0_p0_ce0 ),
.ug0_p0_q0( grp_computeResult_fu_467_ug0_p0_q0 ),
.ug0_p1_address0( grp_computeResult_fu_467_ug0_p1_address0 ),
.ug0_p1_ce0( grp_computeResult_fu_467_ug0_p1_ce0 ),
.ug0_p1_q0( grp_computeResult_fu_467_ug0_p1_q0 ),
.ug0_p2_address0( grp_computeResult_fu_467_ug0_p2_address0 ),
.ug0_p2_ce0( grp_computeResult_fu_467_ug0_p2_ce0 ),
.ug0_p2_q0( grp_computeResult_fu_467_ug0_p2_q0 ),
.ug0_p3_address0( grp_computeResult_fu_467_ug0_p3_address0 ),
.ug0_p3_ce0( grp_computeResult_fu_467_ug0_p3_ce0 ),
.ug0_p3_q0( grp_computeResult_fu_467_ug0_p3_q0 ),
.ug1_p0_address0( grp_computeResult_fu_467_ug1_p0_address0 ),
.ug1_p0_ce0( grp_computeResult_fu_467_ug1_p0_ce0 ),
.ug1_p0_q0( grp_computeResult_fu_467_ug1_p0_q0 ),
.ug1_p0_address1( grp_computeResult_fu_467_ug1_p0_address1 ),
.ug1_p0_ce1( grp_computeResult_fu_467_ug1_p0_ce1 ),
.ug1_p0_q1( grp_computeResult_fu_467_ug1_p0_q1 ),
.ug1_p1_address0( grp_computeResult_fu_467_ug1_p1_address0 ),
.ug1_p1_ce0( grp_computeResult_fu_467_ug1_p1_ce0 ),
.ug1_p1_q0( grp_computeResult_fu_467_ug1_p1_q0 ),
.ug1_p2_address0( grp_computeResult_fu_467_ug1_p2_address0 ),
.ug1_p2_ce0( grp_computeResult_fu_467_ug1_p2_ce0 ),
.ug1_p2_q0( grp_computeResult_fu_467_ug1_p2_q0 ),
.ug1_p3_address0( grp_computeResult_fu_467_ug1_p3_address0 ),
.ug1_p3_ce0( grp_computeResult_fu_467_ug1_p3_ce0 ),
.ug1_p3_q0( grp_computeResult_fu_467_ug1_p3_q0 ),
.ug1_p3_address1( grp_computeResult_fu_467_ug1_p3_address1 ),
.ug1_p3_ce1( grp_computeResult_fu_467_ug1_p3_ce1 ),
.ug1_p3_q1( grp_computeResult_fu_467_ug1_p3_q1 ),
.ug2_p0_address0( grp_computeResult_fu_467_ug2_p0_address0 ),
.ug2_p0_ce0( grp_computeResult_fu_467_ug2_p0_ce0 ),
.ug2_p0_q0( grp_computeResult_fu_467_ug2_p0_q0 ),
.ug2_p1_address0( grp_computeResult_fu_467_ug2_p1_address0 ),
.ug2_p1_ce0( grp_computeResult_fu_467_ug2_p1_ce0 ),
.ug2_p1_q0( grp_computeResult_fu_467_ug2_p1_q0 ),
.ug2_p2_address0( grp_computeResult_fu_467_ug2_p2_address0 ),
.ug2_p2_ce0( grp_computeResult_fu_467_ug2_p2_ce0 ),
.ug2_p2_q0( grp_computeResult_fu_467_ug2_p2_q0 ),
.ug2_p3_address0( grp_computeResult_fu_467_ug2_p3_address0 ),
.ug2_p3_ce0( grp_computeResult_fu_467_ug2_p3_ce0 ),
.ug2_p3_q0( grp_computeResult_fu_467_ug2_p3_q0 ),
.g0_p0_address0( grp_computeResult_fu_467_g0_p0_address0 ),
.g0_p0_ce0( grp_computeResult_fu_467_g0_p0_ce0 ),
.g0_p0_q0( grp_computeResult_fu_467_g0_p0_q0 ),
.g0_p1_address0( grp_computeResult_fu_467_g0_p1_address0 ),
.g0_p1_ce0( grp_computeResult_fu_467_g0_p1_ce0 ),
.g0_p1_q0( grp_computeResult_fu_467_g0_p1_q0 ),
.g0_p2_address0( grp_computeResult_fu_467_g0_p2_address0 ),
.g0_p2_ce0( grp_computeResult_fu_467_g0_p2_ce0 ),
.g0_p2_q0( grp_computeResult_fu_467_g0_p2_q0 ),
.g0_p3_address0( grp_computeResult_fu_467_g0_p3_address0 ),
.g0_p3_ce0( grp_computeResult_fu_467_g0_p3_ce0 ),
.g0_p3_q0( grp_computeResult_fu_467_g0_p3_q0 ),
.g1_p0_address0( grp_computeResult_fu_467_g1_p0_address0 ),
.g1_p0_ce0( grp_computeResult_fu_467_g1_p0_ce0 ),
.g1_p0_q0( grp_computeResult_fu_467_g1_p0_q0 ),
.g1_p0_address1( grp_computeResult_fu_467_g1_p0_address1 ),
.g1_p0_ce1( grp_computeResult_fu_467_g1_p0_ce1 ),
.g1_p0_q1( grp_computeResult_fu_467_g1_p0_q1 ),
.g1_p1_address0( grp_computeResult_fu_467_g1_p1_address0 ),
.g1_p1_ce0( grp_computeResult_fu_467_g1_p1_ce0 ),
.g1_p1_q0( grp_computeResult_fu_467_g1_p1_q0 ),
.g1_p2_address0( grp_computeResult_fu_467_g1_p2_address0 ),
.g1_p2_ce0( grp_computeResult_fu_467_g1_p2_ce0 ),
.g1_p2_q0( grp_computeResult_fu_467_g1_p2_q0 ),
.g1_p3_address0( grp_computeResult_fu_467_g1_p3_address0 ),
.g1_p3_ce0( grp_computeResult_fu_467_g1_p3_ce0 ),
.g1_p3_q0( grp_computeResult_fu_467_g1_p3_q0 ),
.g1_p3_address1( grp_computeResult_fu_467_g1_p3_address1 ),
.g1_p3_ce1( grp_computeResult_fu_467_g1_p3_ce1 ),
.g1_p3_q1( grp_computeResult_fu_467_g1_p3_q1 ),
.g2_p0_address0( grp_computeResult_fu_467_g2_p0_address0 ),
.g2_p0_ce0( grp_computeResult_fu_467_g2_p0_ce0 ),
.g2_p0_q0( grp_computeResult_fu_467_g2_p0_q0 ),
.g2_p1_address0( grp_computeResult_fu_467_g2_p1_address0 ),
.g2_p1_ce0( grp_computeResult_fu_467_g2_p1_ce0 ),
.g2_p1_q0( grp_computeResult_fu_467_g2_p1_q0 ),
.g2_p2_address0( grp_computeResult_fu_467_g2_p2_address0 ),
.g2_p2_ce0( grp_computeResult_fu_467_g2_p2_ce0 ),
.g2_p2_q0( grp_computeResult_fu_467_g2_p2_q0 ),
.g2_p3_address0( grp_computeResult_fu_467_g2_p3_address0 ),
.g2_p3_ce0( grp_computeResult_fu_467_g2_p3_ce0 ),
.g2_p3_q0( grp_computeResult_fu_467_g2_p3_q0 ),
.f_p0_address0( grp_computeResult_fu_467_f_p0_address0 ),
.f_p0_ce0( grp_computeResult_fu_467_f_p0_ce0 ),
.f_p0_q0( grp_computeResult_fu_467_f_p0_q0 ),
.f_p1_address0( grp_computeResult_fu_467_f_p1_address0 ),
.f_p1_ce0( grp_computeResult_fu_467_f_p1_ce0 ),
.f_p1_q0( grp_computeResult_fu_467_f_p1_q0 ),
.f_p2_address0( grp_computeResult_fu_467_f_p2_address0 ),
.f_p2_ce0( grp_computeResult_fu_467_f_p2_ce0 ),
.f_p2_q0( grp_computeResult_fu_467_f_p2_q0 ),
.f_p3_address0( grp_computeResult_fu_467_f_p3_address0 ),
.f_p3_ce0( grp_computeResult_fu_467_f_p3_ce0 ),
.f_p3_q0( grp_computeResult_fu_467_f_p3_q0 ),
.ap_return( grp_computeResult_fu_467_ap_return )
);
computeGradient grp_computeGradient_fu_507(
.ap_clk( ap_clk ),
.ap_rst( ap_rst ),
.ap_start( grp_computeGradient_fu_507_ap_start ),
.ap_done( grp_computeGradient_fu_507_ap_done ),
.ap_idle( grp_computeGradient_fu_507_ap_idle ),
.g_p0_address0( grp_computeGradient_fu_507_g_p0_address0 ),
.g_p0_ce0( grp_computeGradient_fu_507_g_p0_ce0 ),
.g_p0_we0( grp_computeGradient_fu_507_g_p0_we0 ),
.g_p0_d0( grp_computeGradient_fu_507_g_p0_d0 ),
.g_p1_address0( grp_computeGradient_fu_507_g_p1_address0 ),
.g_p1_ce0( grp_computeGradient_fu_507_g_p1_ce0 ),
.g_p1_we0( grp_computeGradient_fu_507_g_p1_we0 ),
.g_p1_d0( grp_computeGradient_fu_507_g_p1_d0 ),
.g_p2_address0( grp_computeGradient_fu_507_g_p2_address0 ),
.g_p2_ce0( grp_computeGradient_fu_507_g_p2_ce0 ),
.g_p2_we0( grp_computeGradient_fu_507_g_p2_we0 ),
.g_p2_d0( grp_computeGradient_fu_507_g_p2_d0 ),
.g_p3_address0( grp_computeGradient_fu_507_g_p3_address0 ),
.g_p3_ce0( grp_computeGradient_fu_507_g_p3_ce0 ),
.g_p3_we0( grp_computeGradient_fu_507_g_p3_we0 ),
.g_p3_d0( grp_computeGradient_fu_507_g_p3_d0 ),
.sm0_p0_address0( grp_computeGradient_fu_507_sm0_p0_address0 ),
.sm0_p0_ce0( grp_computeGradient_fu_507_sm0_p0_ce0 ),
.sm0_p0_q0( grp_computeGradient_fu_507_sm0_p0_q0 ),
.sm0_p1_address0( grp_computeGradient_fu_507_sm0_p1_address0 ),
.sm0_p1_ce0( grp_computeGradient_fu_507_sm0_p1_ce0 ),
.sm0_p1_q0( grp_computeGradient_fu_507_sm0_p1_q0 ),
.sm0_p2_address0( grp_computeGradient_fu_507_sm0_p2_address0 ),
.sm0_p2_ce0( grp_computeGradient_fu_507_sm0_p2_ce0 ),
.sm0_p2_q0( grp_computeGradient_fu_507_sm0_p2_q0 ),
.sm0_p3_address0( grp_computeGradient_fu_507_sm0_p3_address0 ),
.sm0_p3_ce0( grp_computeGradient_fu_507_sm0_p3_ce0 ),
.sm0_p3_q0( grp_computeGradient_fu_507_sm0_p3_q0 ),
.sn0_p0_address0( grp_computeGradient_fu_507_sn0_p0_address0 ),
.sn0_p0_ce0( grp_computeGradient_fu_507_sn0_p0_ce0 ),
.sn0_p0_q0( grp_computeGradient_fu_507_sn0_p0_q0 ),
.sn0_p0_address1( grp_computeGradient_fu_507_sn0_p0_address1 ),
.sn0_p0_ce1( grp_computeGradient_fu_507_sn0_p0_ce1 ),
.sn0_p0_q1( grp_computeGradient_fu_507_sn0_p0_q1 ),
.sn0_p1_address0( grp_computeGradient_fu_507_sn0_p1_address0 ),
.sn0_p1_ce0( grp_computeGradient_fu_507_sn0_p1_ce0 ),
.sn0_p1_q0( grp_computeGradient_fu_507_sn0_p1_q0 ),
.sn0_p2_address0( grp_computeGradient_fu_507_sn0_p2_address0 ),
.sn0_p2_ce0( grp_computeGradient_fu_507_sn0_p2_ce0 ),
.sn0_p2_q0( grp_computeGradient_fu_507_sn0_p2_q0 ),
.sn0_p3_address0( grp_computeGradient_fu_507_sn0_p3_address0 ),
.sn0_p3_ce0( grp_computeGradient_fu_507_sn0_p3_ce0 ),
.sn0_p3_q0( grp_computeGradient_fu_507_sn0_p3_q0 ),
.sp0_p0_address0( grp_computeGradient_fu_507_sp0_p0_address0 ),
.sp0_p0_ce0( grp_computeGradient_fu_507_sp0_p0_ce0 ),
.sp0_p0_q0( grp_computeGradient_fu_507_sp0_p0_q0 ),
.sp0_p1_address0( grp_computeGradient_fu_507_sp0_p1_address0 ),
.sp0_p1_ce0( grp_computeGradient_fu_507_sp0_p1_ce0 ),
.sp0_p1_q0( grp_computeGradient_fu_507_sp0_p1_q0 ),
.sp0_p2_address0( grp_computeGradient_fu_507_sp0_p2_address0 ),
.sp0_p2_ce0( grp_computeGradient_fu_507_sp0_p2_ce0 ),
.sp0_p2_q0( grp_computeGradient_fu_507_sp0_p2_q0 ),
.sp0_p3_address0( grp_computeGradient_fu_507_sp0_p3_address0 ),
.sp0_p3_ce0( grp_computeGradient_fu_507_sp0_p3_ce0 ),
.sp0_p3_q0( grp_computeGradient_fu_507_sp0_p3_q0 ),
.sp1_p0_address0( grp_computeGradient_fu_507_sp1_p0_address0 ),
.sp1_p0_ce0( grp_computeGradient_fu_507_sp1_p0_ce0 ),
.sp1_p0_q0( grp_computeGradient_fu_507_sp1_p0_q0 ),
.sp1_p1_address0( grp_computeGradient_fu_507_sp1_p1_address0 ),
.sp1_p1_ce0( grp_computeGradient_fu_507_sp1_p1_ce0 ),
.sp1_p1_q0( grp_computeGradient_fu_507_sp1_p1_q0 ),
.sp1_p2_address0( grp_computeGradient_fu_507_sp1_p2_address0 ),
.sp1_p2_ce0( grp_computeGradient_fu_507_sp1_p2_ce0 ),
.sp1_p2_q0( grp_computeGradient_fu_507_sp1_p2_q0 ),
.sp1_p3_address0( grp_computeGradient_fu_507_sp1_p3_address0 ),
.sp1_p3_ce0( grp_computeGradient_fu_507_sp1_p3_ce0 ),
.sp1_p3_q0( grp_computeGradient_fu_507_sp1_p3_q0 )
);
computeDiffSqr grp_computeDiffSqr_fu_531(
.ap_clk( ap_clk ),
.ap_rst( ap_rst ),
.ap_start( grp_computeDiffSqr_fu_531_ap_start ),
.ap_done( grp_computeDiffSqr_fu_531_ap_done ),
.ap_idle( grp_computeDiffSqr_fu_531_ap_idle ),
.sm_p0_address0( grp_computeDiffSqr_fu_531_sm_p0_address0 ),
.sm_p0_ce0( grp_computeDiffSqr_fu_531_sm_p0_ce0 ),
.sm_p0_we0( grp_computeDiffSqr_fu_531_sm_p0_we0 ),
.sm_p0_d0( grp_computeDiffSqr_fu_531_sm_p0_d0 ),
.sm_p1_address0( grp_computeDiffSqr_fu_531_sm_p1_address0 ),
.sm_p1_ce0( grp_computeDiffSqr_fu_531_sm_p1_ce0 ),
.sm_p1_we0( grp_computeDiffSqr_fu_531_sm_p1_we0 ),
.sm_p1_d0( grp_computeDiffSqr_fu_531_sm_p1_d0 ),
.sm_p2_address0( grp_computeDiffSqr_fu_531_sm_p2_address0 ),
.sm_p2_ce0( grp_computeDiffSqr_fu_531_sm_p2_ce0 ),
.sm_p2_we0( grp_computeDiffSqr_fu_531_sm_p2_we0 ),
.sm_p2_d0( grp_computeDiffSqr_fu_531_sm_p2_d0 ),
.sm_p3_address0( grp_computeDiffSqr_fu_531_sm_p3_address0 ),
.sm_p3_ce0( grp_computeDiffSqr_fu_531_sm_p3_ce0 ),
.sm_p3_we0( grp_computeDiffSqr_fu_531_sm_p3_we0 ),
.sm_p3_d0( grp_computeDiffSqr_fu_531_sm_p3_d0 ),
.sn_p0_address0( grp_computeDiffSqr_fu_531_sn_p0_address0 ),
.sn_p0_ce0( grp_computeDiffSqr_fu_531_sn_p0_ce0 ),
.sn_p0_we0( grp_computeDiffSqr_fu_531_sn_p0_we0 ),
.sn_p0_d0( grp_computeDiffSqr_fu_531_sn_p0_d0 ),
.sn_p1_address0( grp_computeDiffSqr_fu_531_sn_p1_address0 ),
.sn_p1_ce0( grp_computeDiffSqr_fu_531_sn_p1_ce0 ),
.sn_p1_we0( grp_computeDiffSqr_fu_531_sn_p1_we0 ),
.sn_p1_d0( grp_computeDiffSqr_fu_531_sn_p1_d0 ),
.sn_p2_address0( grp_computeDiffSqr_fu_531_sn_p2_address0 ),
.sn_p2_ce0( grp_computeDiffSqr_fu_531_sn_p2_ce0 ),
.sn_p2_we0( grp_computeDiffSqr_fu_531_sn_p2_we0 ),
.sn_p2_d0( grp_computeDiffSqr_fu_531_sn_p2_d0 ),
.sn_p3_address0( grp_computeDiffSqr_fu_531_sn_p3_address0 ),
.sn_p3_ce0( grp_computeDiffSqr_fu_531_sn_p3_ce0 ),
.sn_p3_we0( grp_computeDiffSqr_fu_531_sn_p3_we0 ),
.sn_p3_d0( grp_computeDiffSqr_fu_531_sn_p3_d0 ),
.sp_p0_address0( grp_computeDiffSqr_fu_531_sp_p0_address0 ),
.sp_p0_ce0( grp_computeDiffSqr_fu_531_sp_p0_ce0 ),
.sp_p0_we0( grp_computeDiffSqr_fu_531_sp_p0_we0 ),
.sp_p0_d0( grp_computeDiffSqr_fu_531_sp_p0_d0 ),
.sp_p1_address0( grp_computeDiffSqr_fu_531_sp_p1_address0 ),
.sp_p1_ce0( grp_computeDiffSqr_fu_531_sp_p1_ce0 ),
.sp_p1_we0( grp_computeDiffSqr_fu_531_sp_p1_we0 ),
.sp_p1_d0( grp_computeDiffSqr_fu_531_sp_p1_d0 ),
.sp_p2_address0( grp_computeDiffSqr_fu_531_sp_p2_address0 ),
.sp_p2_ce0( grp_computeDiffSqr_fu_531_sp_p2_ce0 ),
.sp_p2_we0( grp_computeDiffSqr_fu_531_sp_p2_we0 ),
.sp_p2_d0( grp_computeDiffSqr_fu_531_sp_p2_d0 ),
.sp_p3_address0( grp_computeDiffSqr_fu_531_sp_p3_address0 ),
.sp_p3_ce0( grp_computeDiffSqr_fu_531_sp_p3_ce0 ),
.sp_p3_we0( grp_computeDiffSqr_fu_531_sp_p3_we0 ),
.sp_p3_d0( grp_computeDiffSqr_fu_531_sp_p3_d0 ),
.u0_p0_address0( grp_computeDiffSqr_fu_531_u0_p0_address0 ),
.u0_p0_ce0( grp_computeDiffSqr_fu_531_u0_p0_ce0 ),
.u0_p0_q0( grp_computeDiffSqr_fu_531_u0_p0_q0 ),
.u0_p1_address0( grp_computeDiffSqr_fu_531_u0_p1_address0 ),
.u0_p1_ce0( grp_computeDiffSqr_fu_531_u0_p1_ce0 ),
.u0_p1_q0( grp_computeDiffSqr_fu_531_u0_p1_q0 ),
.u0_p2_address0( grp_computeDiffSqr_fu_531_u0_p2_address0 ),
.u0_p2_ce0( grp_computeDiffSqr_fu_531_u0_p2_ce0 ),
.u0_p2_q0( grp_computeDiffSqr_fu_531_u0_p2_q0 ),
.u0_p3_address0( grp_computeDiffSqr_fu_531_u0_p3_address0 ),
.u0_p3_ce0( grp_computeDiffSqr_fu_531_u0_p3_ce0 ),
.u0_p3_q0( grp_computeDiffSqr_fu_531_u0_p3_q0 ),
.u0_p3_address1( grp_computeDiffSqr_fu_531_u0_p3_address1 ),
.u0_p3_ce1( grp_computeDiffSqr_fu_531_u0_p3_ce1 ),
.u0_p3_q1( grp_computeDiffSqr_fu_531_u0_p3_q1 ),
.u1_p0_address0( grp_computeDiffSqr_fu_531_u1_p0_address0 ),
.u1_p0_ce0( grp_computeDiffSqr_fu_531_u1_p0_ce0 ),
.u1_p0_q0( grp_computeDiffSqr_fu_531_u1_p0_q0 ),
.u1_p1_address0( grp_computeDiffSqr_fu_531_u1_p1_address0 ),
.u1_p1_ce0( grp_computeDiffSqr_fu_531_u1_p1_ce0 ),
.u1_p1_q0( grp_computeDiffSqr_fu_531_u1_p1_q0 ),
.u1_p2_address0( grp_computeDiffSqr_fu_531_u1_p2_address0 ),
.u1_p2_ce0( grp_computeDiffSqr_fu_531_u1_p2_ce0 ),
.u1_p2_q0( grp_computeDiffSqr_fu_531_u1_p2_q0 ),
.u1_p3_address0( grp_computeDiffSqr_fu_531_u1_p3_address0 ),
.u1_p3_ce0( grp_computeDiffSqr_fu_531_u1_p3_ce0 ),
.u1_p3_q0( grp_computeDiffSqr_fu_531_u1_p3_q0 )
);
computeUG grp_computeUG_fu_555(
.ap_clk( ap_clk ),
.ap_rst( ap_rst ),
.ap_start( grp_computeUG_fu_555_ap_start ),
.ap_done( grp_computeUG_fu_555_ap_done ),
.ap_idle( grp_computeUG_fu_555_ap_idle ),
.ug_p0_address0( grp_computeUG_fu_555_ug_p0_address0 ),
.ug_p0_ce0( grp_computeUG_fu_555_ug_p0_ce0 ),
.ug_p0_we0( grp_computeUG_fu_555_ug_p0_we0 ),
.ug_p0_d0( grp_computeUG_fu_555_ug_p0_d0 ),
.ug_p1_address0( grp_computeUG_fu_555_ug_p1_address0 ),
.ug_p1_ce0( grp_computeUG_fu_555_ug_p1_ce0 ),
.ug_p1_we0( grp_computeUG_fu_555_ug_p1_we0 ),
.ug_p1_d0( grp_computeUG_fu_555_ug_p1_d0 ),
.ug_p2_address0( grp_computeUG_fu_555_ug_p2_address0 ),
.ug_p2_ce0( grp_computeUG_fu_555_ug_p2_ce0 ),
.ug_p2_we0( grp_computeUG_fu_555_ug_p2_we0 ),
.ug_p2_d0( grp_computeUG_fu_555_ug_p2_d0 ),
.ug_p3_address0( grp_computeUG_fu_555_ug_p3_address0 ),
.ug_p3_ce0( grp_computeUG_fu_555_ug_p3_ce0 ),
.ug_p3_we0( grp_computeUG_fu_555_ug_p3_we0 ),
.ug_p3_d0( grp_computeUG_fu_555_ug_p3_d0 ),
.u_p0_address0( grp_computeUG_fu_555_u_p0_address0 ),
.u_p0_ce0( grp_computeUG_fu_555_u_p0_ce0 ),
.u_p0_q0( grp_computeUG_fu_555_u_p0_q0 ),
.u_p1_address0( grp_computeUG_fu_555_u_p1_address0 ),
.u_p1_ce0( grp_computeUG_fu_555_u_p1_ce0 ),
.u_p1_q0( grp_computeUG_fu_555_u_p1_q0 ),
.u_p2_address0( grp_computeUG_fu_555_u_p2_address0 ),
.u_p2_ce0( grp_computeUG_fu_555_u_p2_ce0 ),
.u_p2_q0( grp_computeUG_fu_555_u_p2_q0 ),
.u_p3_address0( grp_computeUG_fu_555_u_p3_address0 ),
.u_p3_ce0( grp_computeUG_fu_555_u_p3_ce0 ),
.u_p3_q0( grp_computeUG_fu_555_u_p3_q0 ),
.g_p0_address0( grp_computeUG_fu_555_g_p0_address0 ),
.g_p0_ce0( grp_computeUG_fu_555_g_p0_ce0 ),
.g_p0_q0( grp_computeUG_fu_555_g_p0_q0 ),
.g_p1_address0( grp_computeUG_fu_555_g_p1_address0 ),
.g_p1_ce0( grp_computeUG_fu_555_g_p1_ce0 ),
.g_p1_q0( grp_computeUG_fu_555_g_p1_q0 ),
.g_p2_address0( grp_computeUG_fu_555_g_p2_address0 ),
.g_p2_ce0( grp_computeUG_fu_555_g_p2_ce0 ),
.g_p2_q0( grp_computeUG_fu_555_g_p2_q0 ),
.g_p3_address0( grp_computeUG_fu_555_g_p3_address0 ),
.g_p3_ce0( grp_computeUG_fu_555_g_p3_ce0 ),
.g_p3_q0( grp_computeUG_fu_555_g_p3_q0 )
);
write_array grp_write_array_fu_571(
.ap_clk( ap_clk ),
.ap_rst( ap_rst ),
.ap_start( grp_write_array_fu_571_ap_start ),
.ap_done( grp_write_array_fu_571_ap_done ),
.ap_idle( grp_write_array_fu_571_ap_idle ),
.bus_r_req_din( grp_write_array_fu_571_bus_r_req_din ),
.bus_r_req_full_n( grp_write_array_fu_571_bus_r_req_full_n ),
.bus_r_req_write( grp_write_array_fu_571_bus_r_req_write ),
.bus_r_rsp_dout( grp_write_array_fu_571_bus_r_rsp_dout ),
.bus_r_rsp_empty_n( grp_write_array_fu_571_bus_r_rsp_empty_n ),
.bus_r_rsp_read( grp_write_array_fu_571_bus_r_rsp_read ),
.bus_r_address( grp_write_array_fu_571_bus_r_address ),
.bus_r_datain( grp_write_array_fu_571_bus_r_datain ),
.bus_r_dataout( grp_write_array_fu_571_bus_r_dataout ),
.bus_r_size( grp_write_array_fu_571_bus_r_size ),
.data_p0_address0( grp_write_array_fu_571_data_p0_address0 ),
.data_p0_ce0( grp_write_array_fu_571_data_p0_ce0 ),
.data_p0_q0( grp_write_array_fu_571_data_p0_q0 ),
.data_p1_address0( grp_write_array_fu_571_data_p1_address0 ),
.data_p1_ce0( grp_write_array_fu_571_data_p1_ce0 ),
.data_p1_q0( grp_write_array_fu_571_data_p1_q0 ),
.data_p2_address0( grp_write_array_fu_571_data_p2_address0 ),
.data_p2_ce0( grp_write_array_fu_571_data_p2_ce0 ),
.data_p2_q0( grp_write_array_fu_571_data_p2_q0 ),
.data_p3_address0( grp_write_array_fu_571_data_p3_address0 ),
.data_p3_ce0( grp_write_array_fu_571_data_p3_ce0 ),
.data_p3_q0( grp_write_array_fu_571_data_p3_q0 )
);
uFetch_array grp_uFetch_array_fu_583(
.ap_clk( ap_clk ),
.ap_rst( ap_rst ),
.ap_start( grp_uFetch_array_fu_583_ap_start ),
.ap_done( grp_uFetch_array_fu_583_ap_done ),
.ap_idle( grp_uFetch_array_fu_583_ap_idle ),
.bus_r_req_din( grp_uFetch_array_fu_583_bus_r_req_din ),
.bus_r_req_full_n( grp_uFetch_array_fu_583_bus_r_req_full_n ),
.bus_r_req_write( grp_uFetch_array_fu_583_bus_r_req_write ),
.bus_r_rsp_dout( grp_uFetch_array_fu_583_bus_r_rsp_dout ),
.bus_r_rsp_empty_n( grp_uFetch_array_fu_583_bus_r_rsp_empty_n ),
.bus_r_rsp_read( grp_uFetch_array_fu_583_bus_r_rsp_read ),
.bus_r_address( grp_uFetch_array_fu_583_bus_r_address ),
.bus_r_datain( grp_uFetch_array_fu_583_bus_r_datain ),
.bus_r_dataout( grp_uFetch_array_fu_583_bus_r_dataout ),
.bus_r_size( grp_uFetch_array_fu_583_bus_r_size ),
.data_p0_address0( grp_uFetch_array_fu_583_data_p0_address0 ),
.data_p0_ce0( grp_uFetch_array_fu_583_data_p0_ce0 ),
.data_p0_we0( grp_uFetch_array_fu_583_data_p0_we0 ),
.data_p0_d0( grp_uFetch_array_fu_583_data_p0_d0 ),
.data_p1_address0( grp_uFetch_array_fu_583_data_p1_address0 ),
.data_p1_ce0( grp_uFetch_array_fu_583_data_p1_ce0 ),
.data_p1_we0( grp_uFetch_array_fu_583_data_p1_we0 ),
.data_p1_d0( grp_uFetch_array_fu_583_data_p1_d0 ),
.data_p2_address0( grp_uFetch_array_fu_583_data_p2_address0 ),
.data_p2_ce0( grp_uFetch_array_fu_583_data_p2_ce0 ),
.data_p2_we0( grp_uFetch_array_fu_583_data_p2_we0 ),
.data_p2_d0( grp_uFetch_array_fu_583_data_p2_d0 ),
.data_p3_address0( grp_uFetch_array_fu_583_data_p3_address0 ),
.data_p3_ce0( grp_uFetch_array_fu_583_data_p3_ce0 ),
.data_p3_we0( grp_uFetch_array_fu_583_data_p3_we0 ),
.data_p3_d0( grp_uFetch_array_fu_583_data_p3_d0 )
);
fFetch_array grp_fFetch_array_fu_599(
.ap_clk( ap_clk ),
.ap_rst( ap_rst ),
.ap_start( grp_fFetch_array_fu_599_ap_start ),
.ap_done( grp_fFetch_array_fu_599_ap_done ),
.ap_idle( grp_fFetch_array_fu_599_ap_idle ),
.bus_r_req_din( grp_fFetch_array_fu_599_bus_r_req_din ),
.bus_r_req_full_n( grp_fFetch_array_fu_599_bus_r_req_full_n ),
.bus_r_req_write( grp_fFetch_array_fu_599_bus_r_req_write ),
.bus_r_rsp_dout( grp_fFetch_array_fu_599_bus_r_rsp_dout ),
.bus_r_rsp_empty_n( grp_fFetch_array_fu_599_bus_r_rsp_empty_n ),
.bus_r_rsp_read( grp_fFetch_array_fu_599_bus_r_rsp_read ),
.bus_r_address( grp_fFetch_array_fu_599_bus_r_address ),
.bus_r_datain( grp_fFetch_array_fu_599_bus_r_datain ),
.bus_r_dataout( grp_fFetch_array_fu_599_bus_r_dataout ),
.bus_r_size( grp_fFetch_array_fu_599_bus_r_size ),
.data_p0_address0( grp_fFetch_array_fu_599_data_p0_address0 ),
.data_p0_ce0( grp_fFetch_array_fu_599_data_p0_ce0 ),
.data_p0_we0( grp_fFetch_array_fu_599_data_p0_we0 ),
.data_p0_d0( grp_fFetch_array_fu_599_data_p0_d0 ),
.data_p1_address0( grp_fFetch_array_fu_599_data_p1_address0 ),
.data_p1_ce0( grp_fFetch_array_fu_599_data_p1_ce0 ),
.data_p1_we0( grp_fFetch_array_fu_599_data_p1_we0 ),
.data_p1_d0( grp_fFetch_array_fu_599_data_p1_d0 ),
.data_p2_address0( grp_fFetch_array_fu_599_data_p2_address0 ),
.data_p2_ce0( grp_fFetch_array_fu_599_data_p2_ce0 ),
.data_p2_we0( grp_fFetch_array_fu_599_data_p2_we0 ),
.data_p2_d0( grp_fFetch_array_fu_599_data_p2_d0 ),
.data_p3_address0( grp_fFetch_array_fu_599_data_p3_address0 ),
.data_p3_ce0( grp_fFetch_array_fu_599_data_p3_ce0 ),
.data_p3_we0( grp_fFetch_array_fu_599_data_p3_we0 ),
.data_p3_d0( grp_fFetch_array_fu_599_data_p3_d0 )
);
/// ap_CS_fsm assign process. ///
always @ (posedge ap_rst or posedge ap_clk)
begin : ap_ret_ap_CS_fsm
if (ap_rst == 1'b1) begin
ap_CS_fsm <= ap_ST_st0_fsm_0;
end else begin
ap_CS_fsm <= ap_NS_fsm;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st130_fsm_130 == ap_CS_fsm) & ~((ap_const_logic_0 == grp_computeResult_fu_467_ap_done) | (ap_const_logic_0 == grp_write_array_fu_571_ap_done)))) begin
Convergence_assign_58_reg_1185 <= (tmp55_fu_890_p2 & tmp27_reg_1040);
end
if ((~((ap_const_logic_0 == grp_uFetch_array_fu_583_ap_done) | (ap_const_logic_0 == grp_computeDiffSqr_fu_531_ap_done) | (ap_const_logic_0 == grp_computeGradient_fu_507_ap_done) | (ap_const_logic_0 == grp_computeUG_fu_555_ap_done) | (ap_const_logic_0 == grp_computeResult_fu_467_ap_done) | (ap_const_logic_0 == grp_write_array_fu_571_ap_done) | (ap_const_logic_0 == grp_fFetch_array_fu_599_ap_done)) & (ap_ST_st32_fsm_32 == ap_CS_fsm))) begin
empty_10_reg_940 <= grp_computeResult_fu_467_ap_return;
end
if ((~((ap_const_logic_0 == grp_uFetch_array_fu_583_ap_done) | (ap_const_logic_0 == grp_computeDiffSqr_fu_531_ap_done) | (ap_const_logic_0 == grp_computeGradient_fu_507_ap_done) | (ap_const_logic_0 == grp_computeUG_fu_555_ap_done) | (ap_const_logic_0 == grp_computeResult_fu_467_ap_done) | (ap_const_logic_0 == grp_write_array_fu_571_ap_done) | (ap_const_logic_0 == grp_fFetch_array_fu_599_ap_done)) & (ap_ST_st36_fsm_36 == ap_CS_fsm))) begin
empty_12_reg_950 <= grp_computeResult_fu_467_ap_return;
end
if ((~((ap_const_logic_0 == grp_uFetch_array_fu_583_ap_done) | (ap_const_logic_0 == grp_computeDiffSqr_fu_531_ap_done) | (ap_const_logic_0 == grp_computeGradient_fu_507_ap_done) | (ap_const_logic_0 == grp_computeUG_fu_555_ap_done) | (ap_const_logic_0 == grp_computeResult_fu_467_ap_done) | (ap_const_logic_0 == grp_write_array_fu_571_ap_done) | (ap_const_logic_0 == grp_fFetch_array_fu_599_ap_done)) & (ap_ST_st40_fsm_40 == ap_CS_fsm))) begin
empty_14_reg_960 <= grp_computeResult_fu_467_ap_return;
end
if ((~((ap_const_logic_0 == grp_uFetch_array_fu_583_ap_done) | (ap_const_logic_0 == grp_computeDiffSqr_fu_531_ap_done) | (ap_const_logic_0 == grp_computeGradient_fu_507_ap_done) | (ap_const_logic_0 == grp_computeUG_fu_555_ap_done) | (ap_const_logic_0 == grp_computeResult_fu_467_ap_done) | (ap_const_logic_0 == grp_write_array_fu_571_ap_done) | (ap_const_logic_0 == grp_fFetch_array_fu_599_ap_done)) & (ap_ST_st44_fsm_44 == ap_CS_fsm))) begin
empty_16_reg_970 <= grp_computeResult_fu_467_ap_return;
end
if ((~((ap_const_logic_0 == grp_uFetch_array_fu_583_ap_done) | (ap_const_logic_0 == grp_computeDiffSqr_fu_531_ap_done) | (ap_const_logic_0 == grp_computeGradient_fu_507_ap_done) | (ap_const_logic_0 == grp_computeUG_fu_555_ap_done) | (ap_const_logic_0 == grp_computeResult_fu_467_ap_done) | (ap_const_logic_0 == grp_write_array_fu_571_ap_done) | (ap_const_logic_0 == grp_fFetch_array_fu_599_ap_done)) & (ap_ST_st46_fsm_46 == ap_CS_fsm))) begin
empty_17_reg_975 <= grp_computeResult_fu_467_ap_return;
end
if ((~((ap_const_logic_0 == grp_uFetch_array_fu_583_ap_done) | (ap_const_logic_0 == grp_computeDiffSqr_fu_531_ap_done) | (ap_const_logic_0 == grp_computeGradient_fu_507_ap_done) | (ap_const_logic_0 == grp_computeUG_fu_555_ap_done) | (ap_const_logic_0 == grp_computeResult_fu_467_ap_done) | (ap_const_logic_0 == grp_write_array_fu_571_ap_done) | (ap_const_logic_0 == grp_fFetch_array_fu_599_ap_done)) & (ap_ST_st50_fsm_50 == ap_CS_fsm))) begin
empty_19_reg_985 <= grp_computeResult_fu_467_ap_return;
end
if ((~((ap_const_logic_0 == grp_uFetch_array_fu_583_ap_done) | (ap_const_logic_0 == grp_computeDiffSqr_fu_531_ap_done) | (ap_const_logic_0 == grp_computeGradient_fu_507_ap_done) | (ap_const_logic_0 == grp_computeUG_fu_555_ap_done) | (ap_const_logic_0 == grp_computeResult_fu_467_ap_done) | (ap_const_logic_0 == grp_write_array_fu_571_ap_done) | (ap_const_logic_0 == grp_fFetch_array_fu_599_ap_done)) & (ap_ST_st54_fsm_54 == ap_CS_fsm))) begin
empty_21_reg_995 <= grp_computeResult_fu_467_ap_return;
end
if ((~((ap_const_logic_0 == grp_uFetch_array_fu_583_ap_done) | (ap_const_logic_0 == grp_computeDiffSqr_fu_531_ap_done) | (ap_const_logic_0 == grp_computeGradient_fu_507_ap_done) | (ap_const_logic_0 == grp_computeUG_fu_555_ap_done) | (ap_const_logic_0 == grp_computeResult_fu_467_ap_done) | (ap_const_logic_0 == grp_write_array_fu_571_ap_done) | (ap_const_logic_0 == grp_fFetch_array_fu_599_ap_done)) & (ap_ST_st58_fsm_58 == ap_CS_fsm))) begin
empty_23_reg_1005 <= grp_computeResult_fu_467_ap_return;
end
if ((~((ap_const_logic_0 == grp_uFetch_array_fu_583_ap_done) | (ap_const_logic_0 == grp_computeDiffSqr_fu_531_ap_done) | (ap_const_logic_0 == grp_computeGradient_fu_507_ap_done) | (ap_const_logic_0 == grp_computeUG_fu_555_ap_done) | (ap_const_logic_0 == grp_computeResult_fu_467_ap_done) | (ap_const_logic_0 == grp_write_array_fu_571_ap_done) | (ap_const_logic_0 == grp_fFetch_array_fu_599_ap_done)) & (ap_ST_st62_fsm_62 == ap_CS_fsm))) begin
empty_25_reg_1015 <= grp_computeResult_fu_467_ap_return;
end
if ((~((ap_const_logic_0 == grp_uFetch_array_fu_583_ap_done) | (ap_const_logic_0 == grp_computeDiffSqr_fu_531_ap_done) | (ap_const_logic_0 == grp_computeGradient_fu_507_ap_done) | (ap_const_logic_0 == grp_computeUG_fu_555_ap_done) | (ap_const_logic_0 == grp_computeResult_fu_467_ap_done) | (ap_const_logic_0 == grp_write_array_fu_571_ap_done) | (ap_const_logic_0 == grp_fFetch_array_fu_599_ap_done)) & (ap_ST_st66_fsm_66 == ap_CS_fsm))) begin
empty_27_reg_1025 <= grp_computeResult_fu_467_ap_return;
end
if ((~((ap_const_logic_0 == grp_uFetch_array_fu_583_ap_done) | (ap_const_logic_0 == grp_computeDiffSqr_fu_531_ap_done) | (ap_const_logic_0 == grp_computeGradient_fu_507_ap_done) | (ap_const_logic_0 == grp_computeUG_fu_555_ap_done) | (ap_const_logic_0 == grp_computeResult_fu_467_ap_done) | (ap_const_logic_0 == grp_write_array_fu_571_ap_done) | (ap_const_logic_0 == grp_fFetch_array_fu_599_ap_done)) & (ap_ST_st70_fsm_70 == ap_CS_fsm))) begin
empty_29_reg_1035 <= grp_computeResult_fu_467_ap_return;
end
if (((ap_ST_st16_fsm_16 == ap_CS_fsm) & ~((ap_const_logic_0 == grp_uFetch_array_fu_583_ap_done) | (ap_const_logic_0 == grp_computeDiffSqr_fu_531_ap_done) | (ap_const_logic_0 == grp_computeGradient_fu_507_ap_done) | (ap_const_logic_0 == grp_computeUG_fu_555_ap_done) | (ap_const_logic_0 == grp_computeResult_fu_467_ap_done)))) begin
empty_2_reg_900 <= grp_computeResult_fu_467_ap_return;
end
if ((~((ap_const_logic_0 == grp_uFetch_array_fu_583_ap_done) | (ap_const_logic_0 == grp_computeDiffSqr_fu_531_ap_done) | (ap_const_logic_0 == grp_computeGradient_fu_507_ap_done) | (ap_const_logic_0 == grp_computeUG_fu_555_ap_done) | (ap_const_logic_0 == grp_computeResult_fu_467_ap_done) | (ap_const_logic_0 == grp_write_array_fu_571_ap_done) | (ap_const_logic_0 == grp_fFetch_array_fu_599_ap_done)) & (ap_ST_st74_fsm_74 == ap_CS_fsm))) begin
empty_31_reg_1045 <= grp_computeResult_fu_467_ap_return;
end
if ((~((ap_const_logic_0 == grp_uFetch_array_fu_583_ap_done) | (ap_const_logic_0 == grp_computeDiffSqr_fu_531_ap_done) | (ap_const_logic_0 == grp_computeGradient_fu_507_ap_done) | (ap_const_logic_0 == grp_computeUG_fu_555_ap_done) | (ap_const_logic_0 == grp_computeResult_fu_467_ap_done) | (ap_const_logic_0 == grp_write_array_fu_571_ap_done) | (ap_const_logic_0 == grp_fFetch_array_fu_599_ap_done)) & (ap_ST_st76_fsm_76 == ap_CS_fsm))) begin
empty_32_reg_1050 <= grp_computeResult_fu_467_ap_return;
end
if ((~((ap_const_logic_0 == grp_uFetch_array_fu_583_ap_done) | (ap_const_logic_0 == grp_computeDiffSqr_fu_531_ap_done) | (ap_const_logic_0 == grp_computeGradient_fu_507_ap_done) | (ap_const_logic_0 == grp_computeUG_fu_555_ap_done) | (ap_const_logic_0 == grp_computeResult_fu_467_ap_done) | (ap_const_logic_0 == grp_write_array_fu_571_ap_done) | (ap_const_logic_0 == grp_fFetch_array_fu_599_ap_done)) & (ap_ST_st80_fsm_80 == ap_CS_fsm))) begin
empty_34_reg_1060 <= grp_computeResult_fu_467_ap_return;
end
if ((~((ap_const_logic_0 == grp_uFetch_array_fu_583_ap_done) | (ap_const_logic_0 == grp_computeDiffSqr_fu_531_ap_done) | (ap_const_logic_0 == grp_computeGradient_fu_507_ap_done) | (ap_const_logic_0 == grp_computeUG_fu_555_ap_done) | (ap_const_logic_0 == grp_computeResult_fu_467_ap_done) | (ap_const_logic_0 == grp_write_array_fu_571_ap_done) | (ap_const_logic_0 == grp_fFetch_array_fu_599_ap_done)) & (ap_ST_st84_fsm_84 == ap_CS_fsm))) begin
empty_36_reg_1070 <= grp_computeResult_fu_467_ap_return;
end
if ((~((ap_const_logic_0 == grp_uFetch_array_fu_583_ap_done) | (ap_const_logic_0 == grp_computeDiffSqr_fu_531_ap_done) | (ap_const_logic_0 == grp_computeGradient_fu_507_ap_done) | (ap_const_logic_0 == grp_computeUG_fu_555_ap_done) | (ap_const_logic_0 == grp_computeResult_fu_467_ap_done) | (ap_const_logic_0 == grp_write_array_fu_571_ap_done) | (ap_const_logic_0 == grp_fFetch_array_fu_599_ap_done)) & (ap_ST_st88_fsm_88 == ap_CS_fsm))) begin
empty_38_reg_1080 <= grp_computeResult_fu_467_ap_return;
end
if ((~((ap_const_logic_0 == grp_uFetch_array_fu_583_ap_done) | (ap_const_logic_0 == grp_computeDiffSqr_fu_531_ap_done) | (ap_const_logic_0 == grp_computeGradient_fu_507_ap_done) | (ap_const_logic_0 == grp_computeUG_fu_555_ap_done) | (ap_const_logic_0 == grp_computeResult_fu_467_ap_done) | (ap_const_logic_0 == grp_write_array_fu_571_ap_done) | (ap_const_logic_0 == grp_fFetch_array_fu_599_ap_done)) & (ap_ST_st90_fsm_90 == ap_CS_fsm))) begin
empty_39_reg_1085 <= grp_computeResult_fu_467_ap_return;
end
if (((ap_ST_st18_fsm_18 == ap_CS_fsm) & ~((ap_const_logic_0 == grp_uFetch_array_fu_583_ap_done) | (ap_const_logic_0 == grp_computeDiffSqr_fu_531_ap_done) | (ap_const_logic_0 == grp_computeGradient_fu_507_ap_done) | (ap_const_logic_0 == grp_computeUG_fu_555_ap_done) | (ap_const_logic_0 == grp_computeResult_fu_467_ap_done) | (ap_const_logic_0 == grp_write_array_fu_571_ap_done) | (ap_const_logic_0 == grp_fFetch_array_fu_599_ap_done)))) begin
empty_3_reg_905 <= grp_computeResult_fu_467_ap_return;
end
if ((~((ap_const_logic_0 == grp_uFetch_array_fu_583_ap_done) | (ap_const_logic_0 == grp_computeDiffSqr_fu_531_ap_done) | (ap_const_logic_0 == grp_computeGradient_fu_507_ap_done) | (ap_const_logic_0 == grp_computeUG_fu_555_ap_done) | (ap_const_logic_0 == grp_computeResult_fu_467_ap_done) | (ap_const_logic_0 == grp_write_array_fu_571_ap_done) | (ap_const_logic_0 == grp_fFetch_array_fu_599_ap_done)) & (ap_ST_st94_fsm_94 == ap_CS_fsm))) begin
empty_41_reg_1095 <= grp_computeResult_fu_467_ap_return;
end
if ((~((ap_const_logic_0 == grp_uFetch_array_fu_583_ap_done) | (ap_const_logic_0 == grp_computeDiffSqr_fu_531_ap_done) | (ap_const_logic_0 == grp_computeGradient_fu_507_ap_done) | (ap_const_logic_0 == grp_computeUG_fu_555_ap_done) | (ap_const_logic_0 == grp_computeResult_fu_467_ap_done) | (ap_const_logic_0 == grp_write_array_fu_571_ap_done) | (ap_const_logic_0 == grp_fFetch_array_fu_599_ap_done)) & (ap_ST_st98_fsm_98 == ap_CS_fsm))) begin
empty_43_reg_1105 <= grp_computeResult_fu_467_ap_return;
end
if ((~((ap_const_logic_0 == grp_uFetch_array_fu_583_ap_done) | (ap_const_logic_0 == grp_computeDiffSqr_fu_531_ap_done) | (ap_const_logic_0 == grp_computeGradient_fu_507_ap_done) | (ap_const_logic_0 == grp_computeUG_fu_555_ap_done) | (ap_const_logic_0 == grp_computeResult_fu_467_ap_done) | (ap_const_logic_0 == grp_write_array_fu_571_ap_done) | (ap_const_logic_0 == grp_fFetch_array_fu_599_ap_done)) & (ap_ST_st102_fsm_102 == ap_CS_fsm))) begin
empty_45_reg_1115 <= grp_computeResult_fu_467_ap_return;
end
if ((~((ap_const_logic_0 == grp_uFetch_array_fu_583_ap_done) | (ap_const_logic_0 == grp_computeDiffSqr_fu_531_ap_done) | (ap_const_logic_0 == grp_computeGradient_fu_507_ap_done) | (ap_const_logic_0 == grp_computeUG_fu_555_ap_done) | (ap_const_logic_0 == grp_computeResult_fu_467_ap_done) | (ap_const_logic_0 == grp_write_array_fu_571_ap_done) | (ap_const_logic_0 == grp_fFetch_array_fu_599_ap_done)) & (ap_ST_st104_fsm_104 == ap_CS_fsm))) begin
empty_46_reg_1120 <= grp_computeResult_fu_467_ap_return;
end
if ((~((ap_const_logic_0 == grp_uFetch_array_fu_583_ap_done) | (ap_const_logic_0 == grp_computeDiffSqr_fu_531_ap_done) | (ap_const_logic_0 == grp_computeGradient_fu_507_ap_done) | (ap_const_logic_0 == grp_computeUG_fu_555_ap_done) | (ap_const_logic_0 == grp_computeResult_fu_467_ap_done) | (ap_const_logic_0 == grp_write_array_fu_571_ap_done) | (ap_const_logic_0 == grp_fFetch_array_fu_599_ap_done)) & (ap_ST_st108_fsm_108 == ap_CS_fsm))) begin
empty_48_reg_1130 <= grp_computeResult_fu_467_ap_return;
end
if ((~((ap_const_logic_0 == grp_uFetch_array_fu_583_ap_done) | (ap_const_logic_0 == grp_computeDiffSqr_fu_531_ap_done) | (ap_const_logic_0 == grp_computeGradient_fu_507_ap_done) | (ap_const_logic_0 == grp_computeUG_fu_555_ap_done) | (ap_const_logic_0 == grp_computeResult_fu_467_ap_done) | (ap_const_logic_0 == grp_write_array_fu_571_ap_done) | (ap_const_logic_0 == grp_fFetch_array_fu_599_ap_done)) & (ap_ST_st112_fsm_112 == ap_CS_fsm))) begin
empty_50_reg_1140 <= grp_computeResult_fu_467_ap_return;
end
if ((~((ap_const_logic_0 == grp_uFetch_array_fu_583_ap_done) | (ap_const_logic_0 == grp_computeDiffSqr_fu_531_ap_done) | (ap_const_logic_0 == grp_computeGradient_fu_507_ap_done) | (ap_const_logic_0 == grp_computeUG_fu_555_ap_done) | (ap_const_logic_0 == grp_computeResult_fu_467_ap_done) | (ap_const_logic_0 == grp_write_array_fu_571_ap_done) | (ap_const_logic_0 == grp_fFetch_array_fu_599_ap_done)) & (ap_ST_st116_fsm_116 == ap_CS_fsm))) begin
empty_52_reg_1150 <= grp_computeResult_fu_467_ap_return;
end
if ((~((ap_const_logic_0 == grp_uFetch_array_fu_583_ap_done) | (ap_const_logic_0 == grp_computeDiffSqr_fu_531_ap_done) | (ap_const_logic_0 == grp_computeGradient_fu_507_ap_done) | (ap_const_logic_0 == grp_computeUG_fu_555_ap_done) | (ap_const_logic_0 == grp_computeResult_fu_467_ap_done) | (ap_const_logic_0 == grp_write_array_fu_571_ap_done) | (ap_const_logic_0 == grp_fFetch_array_fu_599_ap_done)) & (ap_ST_st120_fsm_120 == ap_CS_fsm))) begin
empty_54_reg_1160 <= grp_computeResult_fu_467_ap_return;
end
if (((ap_ST_st124_fsm_124 == ap_CS_fsm) & ~((ap_const_logic_0 == grp_computeGradient_fu_507_ap_done) | (ap_const_logic_0 == grp_computeUG_fu_555_ap_done) | (ap_const_logic_0 == grp_computeResult_fu_467_ap_done) | (ap_const_logic_0 == grp_write_array_fu_571_ap_done) | (ap_const_logic_0 == grp_fFetch_array_fu_599_ap_done)))) begin
empty_56_reg_1170 <= grp_computeResult_fu_467_ap_return;
end
if (((ap_ST_st128_fsm_128 == ap_CS_fsm) & ~((ap_const_logic_0 == grp_computeUG_fu_555_ap_done) | (ap_const_logic_0 == grp_computeResult_fu_467_ap_done) | (ap_const_logic_0 == grp_write_array_fu_571_ap_done)))) begin
empty_58_reg_1180 <= grp_computeResult_fu_467_ap_return;
end
if ((~((ap_const_logic_0 == grp_uFetch_array_fu_583_ap_done) | (ap_const_logic_0 == grp_computeDiffSqr_fu_531_ap_done) | (ap_const_logic_0 == grp_computeGradient_fu_507_ap_done) | (ap_const_logic_0 == grp_computeUG_fu_555_ap_done) | (ap_const_logic_0 == grp_computeResult_fu_467_ap_done) | (ap_const_logic_0 == grp_write_array_fu_571_ap_done) | (ap_const_logic_0 == grp_fFetch_array_fu_599_ap_done)) & (ap_ST_st22_fsm_22 == ap_CS_fsm))) begin
empty_5_reg_915 <= grp_computeResult_fu_467_ap_return;
end
if ((~((ap_const_logic_0 == grp_uFetch_array_fu_583_ap_done) | (ap_const_logic_0 == grp_computeDiffSqr_fu_531_ap_done) | (ap_const_logic_0 == grp_computeGradient_fu_507_ap_done) | (ap_const_logic_0 == grp_computeUG_fu_555_ap_done) | (ap_const_logic_0 == grp_computeResult_fu_467_ap_done) | (ap_const_logic_0 == grp_write_array_fu_571_ap_done) | (ap_const_logic_0 == grp_fFetch_array_fu_599_ap_done)) & (ap_ST_st26_fsm_26 == ap_CS_fsm))) begin
empty_7_reg_925 <= grp_computeResult_fu_467_ap_return;
end
if ((~((ap_const_logic_0 == grp_uFetch_array_fu_583_ap_done) | (ap_const_logic_0 == grp_computeDiffSqr_fu_531_ap_done) | (ap_const_logic_0 == grp_computeGradient_fu_507_ap_done) | (ap_const_logic_0 == grp_computeUG_fu_555_ap_done) | (ap_const_logic_0 == grp_computeResult_fu_467_ap_done) | (ap_const_logic_0 == grp_write_array_fu_571_ap_done) | (ap_const_logic_0 == grp_fFetch_array_fu_599_ap_done)) & (ap_ST_st30_fsm_30 == ap_CS_fsm))) begin
empty_9_reg_935 <= grp_computeResult_fu_467_ap_return;
end
if ((~((ap_const_logic_0 == grp_uFetch_array_fu_583_ap_done) | (ap_const_logic_0 == grp_computeDiffSqr_fu_531_ap_done) | (ap_const_logic_0 == grp_computeGradient_fu_507_ap_done) | (ap_const_logic_0 == grp_computeUG_fu_555_ap_done) | (ap_const_logic_0 == grp_computeResult_fu_467_ap_done) | (ap_const_logic_0 == grp_write_array_fu_571_ap_done) | (ap_const_logic_0 == grp_fFetch_array_fu_599_ap_done)) & (ap_ST_st42_fsm_42 == ap_CS_fsm))) begin
tmp12_reg_965 <= (tmp11_fu_670_p2 & tmp5_reg_930);
end
if ((~((ap_const_logic_0 == grp_uFetch_array_fu_583_ap_done) | (ap_const_logic_0 == grp_computeDiffSqr_fu_531_ap_done) | (ap_const_logic_0 == grp_computeGradient_fu_507_ap_done) | (ap_const_logic_0 == grp_computeUG_fu_555_ap_done) | (ap_const_logic_0 == grp_computeResult_fu_467_ap_done) | (ap_const_logic_0 == grp_write_array_fu_571_ap_done) | (ap_const_logic_0 == grp_fFetch_array_fu_599_ap_done)) & (ap_ST_st48_fsm_48 == ap_CS_fsm))) begin
tmp14_reg_980 <= (tmp13_fu_680_p2 & empty_16_reg_970);
end
if ((~((ap_const_logic_0 == grp_uFetch_array_fu_583_ap_done) | (ap_const_logic_0 == grp_computeDiffSqr_fu_531_ap_done) | (ap_const_logic_0 == grp_computeGradient_fu_507_ap_done) | (ap_const_logic_0 == grp_computeUG_fu_555_ap_done) | (ap_const_logic_0 == grp_computeResult_fu_467_ap_done) | (ap_const_logic_0 == grp_write_array_fu_571_ap_done) | (ap_const_logic_0 == grp_fFetch_array_fu_599_ap_done)) & (ap_ST_st52_fsm_52 == ap_CS_fsm))) begin
tmp15_reg_990 <= (empty_19_reg_985 & grp_computeResult_fu_467_ap_return);
end
if ((~((ap_const_logic_0 == grp_uFetch_array_fu_583_ap_done) | (ap_const_logic_0 == grp_computeDiffSqr_fu_531_ap_done) | (ap_const_logic_0 == grp_computeGradient_fu_507_ap_done) | (ap_const_logic_0 == grp_computeUG_fu_555_ap_done) | (ap_const_logic_0 == grp_computeResult_fu_467_ap_done) | (ap_const_logic_0 == grp_write_array_fu_571_ap_done) | (ap_const_logic_0 == grp_fFetch_array_fu_599_ap_done)) & (ap_ST_st56_fsm_56 == ap_CS_fsm))) begin
tmp18_reg_1000 <= (tmp17_fu_700_p2 & tmp14_reg_980);
end
if ((~((ap_const_logic_0 == grp_uFetch_array_fu_583_ap_done) | (ap_const_logic_0 == grp_computeDiffSqr_fu_531_ap_done) | (ap_const_logic_0 == grp_computeGradient_fu_507_ap_done) | (ap_const_logic_0 == grp_computeUG_fu_555_ap_done) | (ap_const_logic_0 == grp_computeResult_fu_467_ap_done) | (ap_const_logic_0 == grp_write_array_fu_571_ap_done) | (ap_const_logic_0 == grp_fFetch_array_fu_599_ap_done)) & (ap_ST_st60_fsm_60 == ap_CS_fsm))) begin
tmp19_reg_1010 <= (empty_23_reg_1005 & grp_computeResult_fu_467_ap_return);
end
if ((~((ap_const_logic_0 == grp_uFetch_array_fu_583_ap_done) | (ap_const_logic_0 == grp_computeDiffSqr_fu_531_ap_done) | (ap_const_logic_0 == grp_computeGradient_fu_507_ap_done) | (ap_const_logic_0 == grp_computeUG_fu_555_ap_done) | (ap_const_logic_0 == grp_computeResult_fu_467_ap_done) | (ap_const_logic_0 == grp_write_array_fu_571_ap_done) | (ap_const_logic_0 == grp_fFetch_array_fu_599_ap_done)) & (ap_ST_st20_fsm_20 == ap_CS_fsm))) begin
tmp1_reg_910 <= (tmp_fu_615_p2 & empty_3_reg_905);
end
if ((~((ap_const_logic_0 == grp_uFetch_array_fu_583_ap_done) | (ap_const_logic_0 == grp_computeDiffSqr_fu_531_ap_done) | (ap_const_logic_0 == grp_computeGradient_fu_507_ap_done) | (ap_const_logic_0 == grp_computeUG_fu_555_ap_done) | (ap_const_logic_0 == grp_computeResult_fu_467_ap_done) | (ap_const_logic_0 == grp_write_array_fu_571_ap_done) | (ap_const_logic_0 == grp_fFetch_array_fu_599_ap_done)) & (ap_ST_st64_fsm_64 == ap_CS_fsm))) begin
tmp21_reg_1020 <= (tmp20_fu_715_p2 & tmp19_reg_1010);
end
if ((~((ap_const_logic_0 == grp_uFetch_array_fu_583_ap_done) | (ap_const_logic_0 == grp_computeDiffSqr_fu_531_ap_done) | (ap_const_logic_0 == grp_computeGradient_fu_507_ap_done) | (ap_const_logic_0 == grp_computeUG_fu_555_ap_done) | (ap_const_logic_0 == grp_computeResult_fu_467_ap_done) | (ap_const_logic_0 == grp_write_array_fu_571_ap_done) | (ap_const_logic_0 == grp_fFetch_array_fu_599_ap_done)) & (ap_ST_st68_fsm_68 == ap_CS_fsm))) begin
tmp22_reg_1030 <= (empty_27_reg_1025 & grp_computeResult_fu_467_ap_return);
end
if ((~((ap_const_logic_0 == grp_uFetch_array_fu_583_ap_done) | (ap_const_logic_0 == grp_computeDiffSqr_fu_531_ap_done) | (ap_const_logic_0 == grp_computeGradient_fu_507_ap_done) | (ap_const_logic_0 == grp_computeUG_fu_555_ap_done) | (ap_const_logic_0 == grp_computeResult_fu_467_ap_done) | (ap_const_logic_0 == grp_write_array_fu_571_ap_done) | (ap_const_logic_0 == grp_fFetch_array_fu_599_ap_done)) & (ap_ST_st72_fsm_72 == ap_CS_fsm))) begin
tmp27_reg_1040 <= (tmp26_fu_745_p2 & tmp12_reg_965);
end
if ((~((ap_const_logic_0 == grp_uFetch_array_fu_583_ap_done) | (ap_const_logic_0 == grp_computeDiffSqr_fu_531_ap_done) | (ap_const_logic_0 == grp_computeGradient_fu_507_ap_done) | (ap_const_logic_0 == grp_computeUG_fu_555_ap_done) | (ap_const_logic_0 == grp_computeResult_fu_467_ap_done) | (ap_const_logic_0 == grp_write_array_fu_571_ap_done) | (ap_const_logic_0 == grp_fFetch_array_fu_599_ap_done)) & (ap_ST_st78_fsm_78 == ap_CS_fsm))) begin
tmp29_reg_1055 <= (tmp28_fu_755_p2 & empty_31_reg_1045);
end
if ((~((ap_const_logic_0 == grp_uFetch_array_fu_583_ap_done) | (ap_const_logic_0 == grp_computeDiffSqr_fu_531_ap_done) | (ap_const_logic_0 == grp_computeGradient_fu_507_ap_done) | (ap_const_logic_0 == grp_computeUG_fu_555_ap_done) | (ap_const_logic_0 == grp_computeResult_fu_467_ap_done) | (ap_const_logic_0 == grp_write_array_fu_571_ap_done) | (ap_const_logic_0 == grp_fFetch_array_fu_599_ap_done)) & (ap_ST_st24_fsm_24 == ap_CS_fsm))) begin
tmp2_reg_920 <= (empty_5_reg_915 & grp_computeResult_fu_467_ap_return);
end
if ((~((ap_const_logic_0 == grp_uFetch_array_fu_583_ap_done) | (ap_const_logic_0 == grp_computeDiffSqr_fu_531_ap_done) | (ap_const_logic_0 == grp_computeGradient_fu_507_ap_done) | (ap_const_logic_0 == grp_computeUG_fu_555_ap_done) | (ap_const_logic_0 == grp_computeResult_fu_467_ap_done) | (ap_const_logic_0 == grp_write_array_fu_571_ap_done) | (ap_const_logic_0 == grp_fFetch_array_fu_599_ap_done)) & (ap_ST_st82_fsm_82 == ap_CS_fsm))) begin
tmp30_reg_1065 <= (empty_34_reg_1060 & grp_computeResult_fu_467_ap_return);
end
if ((~((ap_const_logic_0 == grp_uFetch_array_fu_583_ap_done) | (ap_const_logic_0 == grp_computeDiffSqr_fu_531_ap_done) | (ap_const_logic_0 == grp_computeGradient_fu_507_ap_done) | (ap_const_logic_0 == grp_computeUG_fu_555_ap_done) | (ap_const_logic_0 == grp_computeResult_fu_467_ap_done) | (ap_const_logic_0 == grp_write_array_fu_571_ap_done) | (ap_const_logic_0 == grp_fFetch_array_fu_599_ap_done)) & (ap_ST_st86_fsm_86 == ap_CS_fsm))) begin
tmp33_reg_1075 <= (tmp32_fu_775_p2 & tmp29_reg_1055);
end
if ((~((ap_const_logic_0 == grp_uFetch_array_fu_583_ap_done) | (ap_const_logic_0 == grp_computeDiffSqr_fu_531_ap_done) | (ap_const_logic_0 == grp_computeGradient_fu_507_ap_done) | (ap_const_logic_0 == grp_computeUG_fu_555_ap_done) | (ap_const_logic_0 == grp_computeResult_fu_467_ap_done) | (ap_const_logic_0 == grp_write_array_fu_571_ap_done) | (ap_const_logic_0 == grp_fFetch_array_fu_599_ap_done)) & (ap_ST_st92_fsm_92 == ap_CS_fsm))) begin
tmp35_reg_1090 <= (tmp34_fu_785_p2 & empty_38_reg_1080);
end
if ((~((ap_const_logic_0 == grp_uFetch_array_fu_583_ap_done) | (ap_const_logic_0 == grp_computeDiffSqr_fu_531_ap_done) | (ap_const_logic_0 == grp_computeGradient_fu_507_ap_done) | (ap_const_logic_0 == grp_computeUG_fu_555_ap_done) | (ap_const_logic_0 == grp_computeResult_fu_467_ap_done) | (ap_const_logic_0 == grp_write_array_fu_571_ap_done) | (ap_const_logic_0 == grp_fFetch_array_fu_599_ap_done)) & (ap_ST_st96_fsm_96 == ap_CS_fsm))) begin
tmp36_reg_1100 <= (empty_41_reg_1095 & grp_computeResult_fu_467_ap_return);
end
if ((~((ap_const_logic_0 == grp_uFetch_array_fu_583_ap_done) | (ap_const_logic_0 == grp_computeDiffSqr_fu_531_ap_done) | (ap_const_logic_0 == grp_computeGradient_fu_507_ap_done) | (ap_const_logic_0 == grp_computeUG_fu_555_ap_done) | (ap_const_logic_0 == grp_computeResult_fu_467_ap_done) | (ap_const_logic_0 == grp_write_array_fu_571_ap_done) | (ap_const_logic_0 == grp_fFetch_array_fu_599_ap_done)) & (ap_ST_st100_fsm_100 == ap_CS_fsm))) begin
tmp40_reg_1110 <= (tmp39_fu_810_p2 & tmp33_reg_1075);
end
if ((~((ap_const_logic_0 == grp_uFetch_array_fu_583_ap_done) | (ap_const_logic_0 == grp_computeDiffSqr_fu_531_ap_done) | (ap_const_logic_0 == grp_computeGradient_fu_507_ap_done) | (ap_const_logic_0 == grp_computeUG_fu_555_ap_done) | (ap_const_logic_0 == grp_computeResult_fu_467_ap_done) | (ap_const_logic_0 == grp_write_array_fu_571_ap_done) | (ap_const_logic_0 == grp_fFetch_array_fu_599_ap_done)) & (ap_ST_st106_fsm_106 == ap_CS_fsm))) begin
tmp42_reg_1125 <= (tmp41_fu_820_p2 & empty_45_reg_1115);
end
if ((~((ap_const_logic_0 == grp_uFetch_array_fu_583_ap_done) | (ap_const_logic_0 == grp_computeDiffSqr_fu_531_ap_done) | (ap_const_logic_0 == grp_computeGradient_fu_507_ap_done) | (ap_const_logic_0 == grp_computeUG_fu_555_ap_done) | (ap_const_logic_0 == grp_computeResult_fu_467_ap_done) | (ap_const_logic_0 == grp_write_array_fu_571_ap_done) | (ap_const_logic_0 == grp_fFetch_array_fu_599_ap_done)) & (ap_ST_st110_fsm_110 == ap_CS_fsm))) begin
tmp43_reg_1135 <= (empty_48_reg_1130 & grp_computeResult_fu_467_ap_return);
end
if ((~((ap_const_logic_0 == grp_uFetch_array_fu_583_ap_done) | (ap_const_logic_0 == grp_computeDiffSqr_fu_531_ap_done) | (ap_const_logic_0 == grp_computeGradient_fu_507_ap_done) | (ap_const_logic_0 == grp_computeUG_fu_555_ap_done) | (ap_const_logic_0 == grp_computeResult_fu_467_ap_done) | (ap_const_logic_0 == grp_write_array_fu_571_ap_done) | (ap_const_logic_0 == grp_fFetch_array_fu_599_ap_done)) & (ap_ST_st114_fsm_114 == ap_CS_fsm))) begin
tmp46_reg_1145 <= (tmp45_fu_840_p2 & tmp42_reg_1125);
end
if ((~((ap_const_logic_0 == grp_uFetch_array_fu_583_ap_done) | (ap_const_logic_0 == grp_computeDiffSqr_fu_531_ap_done) | (ap_const_logic_0 == grp_computeGradient_fu_507_ap_done) | (ap_const_logic_0 == grp_computeUG_fu_555_ap_done) | (ap_const_logic_0 == grp_computeResult_fu_467_ap_done) | (ap_const_logic_0 == grp_write_array_fu_571_ap_done) | (ap_const_logic_0 == grp_fFetch_array_fu_599_ap_done)) & (ap_ST_st118_fsm_118 == ap_CS_fsm))) begin
tmp47_reg_1155 <= (empty_52_reg_1150 & grp_computeResult_fu_467_ap_return);
end
if (((ap_ST_st122_fsm_122 == ap_CS_fsm) & ~((ap_const_logic_0 == grp_computeDiffSqr_fu_531_ap_done) | (ap_const_logic_0 == grp_computeGradient_fu_507_ap_done) | (ap_const_logic_0 == grp_computeUG_fu_555_ap_done) | (ap_const_logic_0 == grp_computeResult_fu_467_ap_done) | (ap_const_logic_0 == grp_write_array_fu_571_ap_done) | (ap_const_logic_0 == grp_fFetch_array_fu_599_ap_done)))) begin
tmp49_reg_1165 <= (tmp48_fu_855_p2 & tmp47_reg_1155);
end
if (((ap_ST_st126_fsm_126 == ap_CS_fsm) & ~((ap_const_logic_0 == grp_computeUG_fu_555_ap_done) | (ap_const_logic_0 == grp_computeResult_fu_467_ap_done) | (ap_const_logic_0 == grp_write_array_fu_571_ap_done) | (ap_const_logic_0 == grp_fFetch_array_fu_599_ap_done)))) begin
tmp50_reg_1175 <= (empty_56_reg_1170 & grp_computeResult_fu_467_ap_return);
end
if ((~((ap_const_logic_0 == grp_uFetch_array_fu_583_ap_done) | (ap_const_logic_0 == grp_computeDiffSqr_fu_531_ap_done) | (ap_const_logic_0 == grp_computeGradient_fu_507_ap_done) | (ap_const_logic_0 == grp_computeUG_fu_555_ap_done) | (ap_const_logic_0 == grp_computeResult_fu_467_ap_done) | (ap_const_logic_0 == grp_write_array_fu_571_ap_done) | (ap_const_logic_0 == grp_fFetch_array_fu_599_ap_done)) & (ap_ST_st28_fsm_28 == ap_CS_fsm))) begin
tmp5_reg_930 <= (tmp4_fu_635_p2 & tmp1_reg_910);
end
if ((~((ap_const_logic_0 == grp_uFetch_array_fu_583_ap_done) | (ap_const_logic_0 == grp_computeDiffSqr_fu_531_ap_done) | (ap_const_logic_0 == grp_computeGradient_fu_507_ap_done) | (ap_const_logic_0 == grp_computeUG_fu_555_ap_done) | (ap_const_logic_0 == grp_computeResult_fu_467_ap_done) | (ap_const_logic_0 == grp_write_array_fu_571_ap_done) | (ap_const_logic_0 == grp_fFetch_array_fu_599_ap_done)) & (ap_ST_st34_fsm_34 == ap_CS_fsm))) begin
tmp7_reg_945 <= (tmp6_fu_645_p2 & empty_9_reg_935);
end
if ((~((ap_const_logic_0 == grp_uFetch_array_fu_583_ap_done) | (ap_const_logic_0 == grp_computeDiffSqr_fu_531_ap_done) | (ap_const_logic_0 == grp_computeGradient_fu_507_ap_done) | (ap_const_logic_0 == grp_computeUG_fu_555_ap_done) | (ap_const_logic_0 == grp_computeResult_fu_467_ap_done) | (ap_const_logic_0 == grp_write_array_fu_571_ap_done) | (ap_const_logic_0 == grp_fFetch_array_fu_599_ap_done)) & (ap_ST_st38_fsm_38 == ap_CS_fsm))) begin
tmp8_reg_955 <= (empty_12_reg_950 & grp_computeResult_fu_467_ap_return);
end
end
/// ap_NS_fsm assign process. ///
always @ (ap_start or ap_CS_fsm or grp_uFetch_array_fu_583_ap_done or grp_computeDiffSqr_fu_531_ap_done or grp_computeGradient_fu_507_ap_done or grp_computeUG_fu_555_ap_done or grp_computeResult_fu_467_ap_done or grp_write_array_fu_571_ap_done or grp_fFetch_array_fu_599_ap_done)
begin
if (((ap_ST_st132_fsm_132 == ap_CS_fsm) & ~(ap_const_logic_0 == grp_write_array_fu_571_ap_done) & ~(ap_const_logic_1 == ap_start))) begin
ap_NS_fsm = ap_ST_st0_fsm_0;
end else if ((ap_ST_st131_fsm_131 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st132_fsm_132;
end else if (((ap_ST_st130_fsm_130 == ap_CS_fsm) & ~((ap_const_logic_0 == grp_computeResult_fu_467_ap_done) | (ap_const_logic_0 == grp_write_array_fu_571_ap_done)))) begin
ap_NS_fsm = ap_ST_st131_fsm_131;
end else if ((ap_ST_st129_fsm_129 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st130_fsm_130;
end else if (((ap_ST_st128_fsm_128 == ap_CS_fsm) & ~((ap_const_logic_0 == grp_computeUG_fu_555_ap_done) | (ap_const_logic_0 == grp_computeResult_fu_467_ap_done) | (ap_const_logic_0 == grp_write_array_fu_571_ap_done)))) begin
ap_NS_fsm = ap_ST_st129_fsm_129;
end else if ((ap_ST_st127_fsm_127 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st128_fsm_128;
end else if (((ap_ST_st126_fsm_126 == ap_CS_fsm) & ~((ap_const_logic_0 == grp_computeUG_fu_555_ap_done) | (ap_const_logic_0 == grp_computeResult_fu_467_ap_done) | (ap_const_logic_0 == grp_write_array_fu_571_ap_done) | (ap_const_logic_0 == grp_fFetch_array_fu_599_ap_done)))) begin
ap_NS_fsm = ap_ST_st127_fsm_127;
end else if ((ap_ST_st125_fsm_125 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st126_fsm_126;
end else if (((ap_ST_st124_fsm_124 == ap_CS_fsm) & ~((ap_const_logic_0 == grp_computeGradient_fu_507_ap_done) | (ap_const_logic_0 == grp_computeUG_fu_555_ap_done) | (ap_const_logic_0 == grp_computeResult_fu_467_ap_done) | (ap_const_logic_0 == grp_write_array_fu_571_ap_done) | (ap_const_logic_0 == grp_fFetch_array_fu_599_ap_done)))) begin
ap_NS_fsm = ap_ST_st125_fsm_125;
end else if ((ap_ST_st123_fsm_123 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st124_fsm_124;
end else if (((ap_ST_st122_fsm_122 == ap_CS_fsm) & ~((ap_const_logic_0 == grp_computeDiffSqr_fu_531_ap_done) | (ap_const_logic_0 == grp_computeGradient_fu_507_ap_done) | (ap_const_logic_0 == grp_computeUG_fu_555_ap_done) | (ap_const_logic_0 == grp_computeResult_fu_467_ap_done) | (ap_const_logic_0 == grp_write_array_fu_571_ap_done) | (ap_const_logic_0 == grp_fFetch_array_fu_599_ap_done)))) begin
ap_NS_fsm = ap_ST_st123_fsm_123;
end else if ((ap_ST_st121_fsm_121 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st122_fsm_122;
end else if ((~((ap_const_logic_0 == grp_uFetch_array_fu_583_ap_done) | (ap_const_logic_0 == grp_computeDiffSqr_fu_531_ap_done) | (ap_const_logic_0 == grp_computeGradient_fu_507_ap_done) | (ap_const_logic_0 == grp_computeUG_fu_555_ap_done) | (ap_const_logic_0 == grp_computeResult_fu_467_ap_done) | (ap_const_logic_0 == grp_write_array_fu_571_ap_done) | (ap_const_logic_0 == grp_fFetch_array_fu_599_ap_done)) & (ap_ST_st120_fsm_120 == ap_CS_fsm))) begin
ap_NS_fsm = ap_ST_st121_fsm_121;
end else if ((ap_ST_st119_fsm_119 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st120_fsm_120;
end else if ((~((ap_const_logic_0 == grp_uFetch_array_fu_583_ap_done) | (ap_const_logic_0 == grp_computeDiffSqr_fu_531_ap_done) | (ap_const_logic_0 == grp_computeGradient_fu_507_ap_done) | (ap_const_logic_0 == grp_computeUG_fu_555_ap_done) | (ap_const_logic_0 == grp_computeResult_fu_467_ap_done) | (ap_const_logic_0 == grp_write_array_fu_571_ap_done) | (ap_const_logic_0 == grp_fFetch_array_fu_599_ap_done)) & (ap_ST_st118_fsm_118 == ap_CS_fsm))) begin
ap_NS_fsm = ap_ST_st119_fsm_119;
end else if ((ap_ST_st117_fsm_117 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st118_fsm_118;
end else if ((~((ap_const_logic_0 == grp_uFetch_array_fu_583_ap_done) | (ap_const_logic_0 == grp_computeDiffSqr_fu_531_ap_done) | (ap_const_logic_0 == grp_computeGradient_fu_507_ap_done) | (ap_const_logic_0 == grp_computeUG_fu_555_ap_done) | (ap_const_logic_0 == grp_computeResult_fu_467_ap_done) | (ap_const_logic_0 == grp_write_array_fu_571_ap_done) | (ap_const_logic_0 == grp_fFetch_array_fu_599_ap_done)) & (ap_ST_st116_fsm_116 == ap_CS_fsm))) begin
ap_NS_fsm = ap_ST_st117_fsm_117;
end else if ((ap_ST_st115_fsm_115 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st116_fsm_116;
end else if ((~((ap_const_logic_0 == grp_uFetch_array_fu_583_ap_done) | (ap_const_logic_0 == grp_computeDiffSqr_fu_531_ap_done) | (ap_const_logic_0 == grp_computeGradient_fu_507_ap_done) | (ap_const_logic_0 == grp_computeUG_fu_555_ap_done) | (ap_const_logic_0 == grp_computeResult_fu_467_ap_done) | (ap_const_logic_0 == grp_write_array_fu_571_ap_done) | (ap_const_logic_0 == grp_fFetch_array_fu_599_ap_done)) & (ap_ST_st114_fsm_114 == ap_CS_fsm))) begin
ap_NS_fsm = ap_ST_st115_fsm_115;
end else if ((ap_ST_st113_fsm_113 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st114_fsm_114;
end else if ((~((ap_const_logic_0 == grp_uFetch_array_fu_583_ap_done) | (ap_const_logic_0 == grp_computeDiffSqr_fu_531_ap_done) | (ap_const_logic_0 == grp_computeGradient_fu_507_ap_done) | (ap_const_logic_0 == grp_computeUG_fu_555_ap_done) | (ap_const_logic_0 == grp_computeResult_fu_467_ap_done) | (ap_const_logic_0 == grp_write_array_fu_571_ap_done) | (ap_const_logic_0 == grp_fFetch_array_fu_599_ap_done)) & (ap_ST_st112_fsm_112 == ap_CS_fsm))) begin
ap_NS_fsm = ap_ST_st113_fsm_113;
end else if ((ap_ST_st111_fsm_111 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st112_fsm_112;
end else if ((~((ap_const_logic_0 == grp_uFetch_array_fu_583_ap_done) | (ap_const_logic_0 == grp_computeDiffSqr_fu_531_ap_done) | (ap_const_logic_0 == grp_computeGradient_fu_507_ap_done) | (ap_const_logic_0 == grp_computeUG_fu_555_ap_done) | (ap_const_logic_0 == grp_computeResult_fu_467_ap_done) | (ap_const_logic_0 == grp_write_array_fu_571_ap_done) | (ap_const_logic_0 == grp_fFetch_array_fu_599_ap_done)) & (ap_ST_st110_fsm_110 == ap_CS_fsm))) begin
ap_NS_fsm = ap_ST_st111_fsm_111;
end else if ((ap_ST_st109_fsm_109 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st110_fsm_110;
end else if ((~((ap_const_logic_0 == grp_uFetch_array_fu_583_ap_done) | (ap_const_logic_0 == grp_computeDiffSqr_fu_531_ap_done) | (ap_const_logic_0 == grp_computeGradient_fu_507_ap_done) | (ap_const_logic_0 == grp_computeUG_fu_555_ap_done) | (ap_const_logic_0 == grp_computeResult_fu_467_ap_done) | (ap_const_logic_0 == grp_write_array_fu_571_ap_done) | (ap_const_logic_0 == grp_fFetch_array_fu_599_ap_done)) & (ap_ST_st108_fsm_108 == ap_CS_fsm))) begin
ap_NS_fsm = ap_ST_st109_fsm_109;
end else if ((ap_ST_st107_fsm_107 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st108_fsm_108;
end else if ((~((ap_const_logic_0 == grp_uFetch_array_fu_583_ap_done) | (ap_const_logic_0 == grp_computeDiffSqr_fu_531_ap_done) | (ap_const_logic_0 == grp_computeGradient_fu_507_ap_done) | (ap_const_logic_0 == grp_computeUG_fu_555_ap_done) | (ap_const_logic_0 == grp_computeResult_fu_467_ap_done) | (ap_const_logic_0 == grp_write_array_fu_571_ap_done) | (ap_const_logic_0 == grp_fFetch_array_fu_599_ap_done)) & (ap_ST_st106_fsm_106 == ap_CS_fsm))) begin
ap_NS_fsm = ap_ST_st107_fsm_107;
end else if ((ap_ST_st105_fsm_105 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st106_fsm_106;
end else if ((~((ap_const_logic_0 == grp_uFetch_array_fu_583_ap_done) | (ap_const_logic_0 == grp_computeDiffSqr_fu_531_ap_done) | (ap_const_logic_0 == grp_computeGradient_fu_507_ap_done) | (ap_const_logic_0 == grp_computeUG_fu_555_ap_done) | (ap_const_logic_0 == grp_computeResult_fu_467_ap_done) | (ap_const_logic_0 == grp_write_array_fu_571_ap_done) | (ap_const_logic_0 == grp_fFetch_array_fu_599_ap_done)) & (ap_ST_st104_fsm_104 == ap_CS_fsm))) begin
ap_NS_fsm = ap_ST_st105_fsm_105;
end else if ((ap_ST_st103_fsm_103 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st104_fsm_104;
end else if ((~((ap_const_logic_0 == grp_uFetch_array_fu_583_ap_done) | (ap_const_logic_0 == grp_computeDiffSqr_fu_531_ap_done) | (ap_const_logic_0 == grp_computeGradient_fu_507_ap_done) | (ap_const_logic_0 == grp_computeUG_fu_555_ap_done) | (ap_const_logic_0 == grp_computeResult_fu_467_ap_done) | (ap_const_logic_0 == grp_write_array_fu_571_ap_done) | (ap_const_logic_0 == grp_fFetch_array_fu_599_ap_done)) & (ap_ST_st102_fsm_102 == ap_CS_fsm))) begin
ap_NS_fsm = ap_ST_st103_fsm_103;
end else if ((ap_ST_st101_fsm_101 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st102_fsm_102;
end else if ((~((ap_const_logic_0 == grp_uFetch_array_fu_583_ap_done) | (ap_const_logic_0 == grp_computeDiffSqr_fu_531_ap_done) | (ap_const_logic_0 == grp_computeGradient_fu_507_ap_done) | (ap_const_logic_0 == grp_computeUG_fu_555_ap_done) | (ap_const_logic_0 == grp_computeResult_fu_467_ap_done) | (ap_const_logic_0 == grp_write_array_fu_571_ap_done) | (ap_const_logic_0 == grp_fFetch_array_fu_599_ap_done)) & (ap_ST_st100_fsm_100 == ap_CS_fsm))) begin
ap_NS_fsm = ap_ST_st101_fsm_101;
end else if ((ap_ST_st99_fsm_99 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st100_fsm_100;
end else if ((~((ap_const_logic_0 == grp_uFetch_array_fu_583_ap_done) | (ap_const_logic_0 == grp_computeDiffSqr_fu_531_ap_done) | (ap_const_logic_0 == grp_computeGradient_fu_507_ap_done) | (ap_const_logic_0 == grp_computeUG_fu_555_ap_done) | (ap_const_logic_0 == grp_computeResult_fu_467_ap_done) | (ap_const_logic_0 == grp_write_array_fu_571_ap_done) | (ap_const_logic_0 == grp_fFetch_array_fu_599_ap_done)) & (ap_ST_st98_fsm_98 == ap_CS_fsm))) begin
ap_NS_fsm = ap_ST_st99_fsm_99;
end else if ((ap_ST_st97_fsm_97 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st98_fsm_98;
end else if ((~((ap_const_logic_0 == grp_uFetch_array_fu_583_ap_done) | (ap_const_logic_0 == grp_computeDiffSqr_fu_531_ap_done) | (ap_const_logic_0 == grp_computeGradient_fu_507_ap_done) | (ap_const_logic_0 == grp_computeUG_fu_555_ap_done) | (ap_const_logic_0 == grp_computeResult_fu_467_ap_done) | (ap_const_logic_0 == grp_write_array_fu_571_ap_done) | (ap_const_logic_0 == grp_fFetch_array_fu_599_ap_done)) & (ap_ST_st96_fsm_96 == ap_CS_fsm))) begin
ap_NS_fsm = ap_ST_st97_fsm_97;
end else if ((ap_ST_st95_fsm_95 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st96_fsm_96;
end else if ((~((ap_const_logic_0 == grp_uFetch_array_fu_583_ap_done) | (ap_const_logic_0 == grp_computeDiffSqr_fu_531_ap_done) | (ap_const_logic_0 == grp_computeGradient_fu_507_ap_done) | (ap_const_logic_0 == grp_computeUG_fu_555_ap_done) | (ap_const_logic_0 == grp_computeResult_fu_467_ap_done) | (ap_const_logic_0 == grp_write_array_fu_571_ap_done) | (ap_const_logic_0 == grp_fFetch_array_fu_599_ap_done)) & (ap_ST_st94_fsm_94 == ap_CS_fsm))) begin
ap_NS_fsm = ap_ST_st95_fsm_95;
end else if ((ap_ST_st93_fsm_93 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st94_fsm_94;
end else if ((~((ap_const_logic_0 == grp_uFetch_array_fu_583_ap_done) | (ap_const_logic_0 == grp_computeDiffSqr_fu_531_ap_done) | (ap_const_logic_0 == grp_computeGradient_fu_507_ap_done) | (ap_const_logic_0 == grp_computeUG_fu_555_ap_done) | (ap_const_logic_0 == grp_computeResult_fu_467_ap_done) | (ap_const_logic_0 == grp_write_array_fu_571_ap_done) | (ap_const_logic_0 == grp_fFetch_array_fu_599_ap_done)) & (ap_ST_st92_fsm_92 == ap_CS_fsm))) begin
ap_NS_fsm = ap_ST_st93_fsm_93;
end else if ((ap_ST_st91_fsm_91 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st92_fsm_92;
end else if ((~((ap_const_logic_0 == grp_uFetch_array_fu_583_ap_done) | (ap_const_logic_0 == grp_computeDiffSqr_fu_531_ap_done) | (ap_const_logic_0 == grp_computeGradient_fu_507_ap_done) | (ap_const_logic_0 == grp_computeUG_fu_555_ap_done) | (ap_const_logic_0 == grp_computeResult_fu_467_ap_done) | (ap_const_logic_0 == grp_write_array_fu_571_ap_done) | (ap_const_logic_0 == grp_fFetch_array_fu_599_ap_done)) & (ap_ST_st90_fsm_90 == ap_CS_fsm))) begin
ap_NS_fsm = ap_ST_st91_fsm_91;
end else if ((ap_ST_st89_fsm_89 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st90_fsm_90;
end else if ((~((ap_const_logic_0 == grp_uFetch_array_fu_583_ap_done) | (ap_const_logic_0 == grp_computeDiffSqr_fu_531_ap_done) | (ap_const_logic_0 == grp_computeGradient_fu_507_ap_done) | (ap_const_logic_0 == grp_computeUG_fu_555_ap_done) | (ap_const_logic_0 == grp_computeResult_fu_467_ap_done) | (ap_const_logic_0 == grp_write_array_fu_571_ap_done) | (ap_const_logic_0 == grp_fFetch_array_fu_599_ap_done)) & (ap_ST_st88_fsm_88 == ap_CS_fsm))) begin
ap_NS_fsm = ap_ST_st89_fsm_89;
end else if ((ap_ST_st87_fsm_87 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st88_fsm_88;
end else if ((~((ap_const_logic_0 == grp_uFetch_array_fu_583_ap_done) | (ap_const_logic_0 == grp_computeDiffSqr_fu_531_ap_done) | (ap_const_logic_0 == grp_computeGradient_fu_507_ap_done) | (ap_const_logic_0 == grp_computeUG_fu_555_ap_done) | (ap_const_logic_0 == grp_computeResult_fu_467_ap_done) | (ap_const_logic_0 == grp_write_array_fu_571_ap_done) | (ap_const_logic_0 == grp_fFetch_array_fu_599_ap_done)) & (ap_ST_st86_fsm_86 == ap_CS_fsm))) begin
ap_NS_fsm = ap_ST_st87_fsm_87;
end else if ((ap_ST_st85_fsm_85 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st86_fsm_86;
end else if ((~((ap_const_logic_0 == grp_uFetch_array_fu_583_ap_done) | (ap_const_logic_0 == grp_computeDiffSqr_fu_531_ap_done) | (ap_const_logic_0 == grp_computeGradient_fu_507_ap_done) | (ap_const_logic_0 == grp_computeUG_fu_555_ap_done) | (ap_const_logic_0 == grp_computeResult_fu_467_ap_done) | (ap_const_logic_0 == grp_write_array_fu_571_ap_done) | (ap_const_logic_0 == grp_fFetch_array_fu_599_ap_done)) & (ap_ST_st84_fsm_84 == ap_CS_fsm))) begin
ap_NS_fsm = ap_ST_st85_fsm_85;
end else if ((ap_ST_st83_fsm_83 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st84_fsm_84;
end else if ((~((ap_const_logic_0 == grp_uFetch_array_fu_583_ap_done) | (ap_const_logic_0 == grp_computeDiffSqr_fu_531_ap_done) | (ap_const_logic_0 == grp_computeGradient_fu_507_ap_done) | (ap_const_logic_0 == grp_computeUG_fu_555_ap_done) | (ap_const_logic_0 == grp_computeResult_fu_467_ap_done) | (ap_const_logic_0 == grp_write_array_fu_571_ap_done) | (ap_const_logic_0 == grp_fFetch_array_fu_599_ap_done)) & (ap_ST_st82_fsm_82 == ap_CS_fsm))) begin
ap_NS_fsm = ap_ST_st83_fsm_83;
end else if ((ap_ST_st81_fsm_81 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st82_fsm_82;
end else if ((~((ap_const_logic_0 == grp_uFetch_array_fu_583_ap_done) | (ap_const_logic_0 == grp_computeDiffSqr_fu_531_ap_done) | (ap_const_logic_0 == grp_computeGradient_fu_507_ap_done) | (ap_const_logic_0 == grp_computeUG_fu_555_ap_done) | (ap_const_logic_0 == grp_computeResult_fu_467_ap_done) | (ap_const_logic_0 == grp_write_array_fu_571_ap_done) | (ap_const_logic_0 == grp_fFetch_array_fu_599_ap_done)) & (ap_ST_st80_fsm_80 == ap_CS_fsm))) begin
ap_NS_fsm = ap_ST_st81_fsm_81;
end else if ((ap_ST_st79_fsm_79 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st80_fsm_80;
end else if ((~((ap_const_logic_0 == grp_uFetch_array_fu_583_ap_done) | (ap_const_logic_0 == grp_computeDiffSqr_fu_531_ap_done) | (ap_const_logic_0 == grp_computeGradient_fu_507_ap_done) | (ap_const_logic_0 == grp_computeUG_fu_555_ap_done) | (ap_const_logic_0 == grp_computeResult_fu_467_ap_done) | (ap_const_logic_0 == grp_write_array_fu_571_ap_done) | (ap_const_logic_0 == grp_fFetch_array_fu_599_ap_done)) & (ap_ST_st78_fsm_78 == ap_CS_fsm))) begin
ap_NS_fsm = ap_ST_st79_fsm_79;
end else if ((ap_ST_st77_fsm_77 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st78_fsm_78;
end else if ((~((ap_const_logic_0 == grp_uFetch_array_fu_583_ap_done) | (ap_const_logic_0 == grp_computeDiffSqr_fu_531_ap_done) | (ap_const_logic_0 == grp_computeGradient_fu_507_ap_done) | (ap_const_logic_0 == grp_computeUG_fu_555_ap_done) | (ap_const_logic_0 == grp_computeResult_fu_467_ap_done) | (ap_const_logic_0 == grp_write_array_fu_571_ap_done) | (ap_const_logic_0 == grp_fFetch_array_fu_599_ap_done)) & (ap_ST_st76_fsm_76 == ap_CS_fsm))) begin
ap_NS_fsm = ap_ST_st77_fsm_77;
end else if ((ap_ST_st75_fsm_75 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st76_fsm_76;
end else if ((~((ap_const_logic_0 == grp_uFetch_array_fu_583_ap_done) | (ap_const_logic_0 == grp_computeDiffSqr_fu_531_ap_done) | (ap_const_logic_0 == grp_computeGradient_fu_507_ap_done) | (ap_const_logic_0 == grp_computeUG_fu_555_ap_done) | (ap_const_logic_0 == grp_computeResult_fu_467_ap_done) | (ap_const_logic_0 == grp_write_array_fu_571_ap_done) | (ap_const_logic_0 == grp_fFetch_array_fu_599_ap_done)) & (ap_ST_st74_fsm_74 == ap_CS_fsm))) begin
ap_NS_fsm = ap_ST_st75_fsm_75;
end else if ((ap_ST_st73_fsm_73 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st74_fsm_74;
end else if ((~((ap_const_logic_0 == grp_uFetch_array_fu_583_ap_done) | (ap_const_logic_0 == grp_computeDiffSqr_fu_531_ap_done) | (ap_const_logic_0 == grp_computeGradient_fu_507_ap_done) | (ap_const_logic_0 == grp_computeUG_fu_555_ap_done) | (ap_const_logic_0 == grp_computeResult_fu_467_ap_done) | (ap_const_logic_0 == grp_write_array_fu_571_ap_done) | (ap_const_logic_0 == grp_fFetch_array_fu_599_ap_done)) & (ap_ST_st72_fsm_72 == ap_CS_fsm))) begin
ap_NS_fsm = ap_ST_st73_fsm_73;
end else if ((ap_ST_st71_fsm_71 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st72_fsm_72;
end else if ((~((ap_const_logic_0 == grp_uFetch_array_fu_583_ap_done) | (ap_const_logic_0 == grp_computeDiffSqr_fu_531_ap_done) | (ap_const_logic_0 == grp_computeGradient_fu_507_ap_done) | (ap_const_logic_0 == grp_computeUG_fu_555_ap_done) | (ap_const_logic_0 == grp_computeResult_fu_467_ap_done) | (ap_const_logic_0 == grp_write_array_fu_571_ap_done) | (ap_const_logic_0 == grp_fFetch_array_fu_599_ap_done)) & (ap_ST_st70_fsm_70 == ap_CS_fsm))) begin
ap_NS_fsm = ap_ST_st71_fsm_71;
end else if ((ap_ST_st69_fsm_69 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st70_fsm_70;
end else if ((~((ap_const_logic_0 == grp_uFetch_array_fu_583_ap_done) | (ap_const_logic_0 == grp_computeDiffSqr_fu_531_ap_done) | (ap_const_logic_0 == grp_computeGradient_fu_507_ap_done) | (ap_const_logic_0 == grp_computeUG_fu_555_ap_done) | (ap_const_logic_0 == grp_computeResult_fu_467_ap_done) | (ap_const_logic_0 == grp_write_array_fu_571_ap_done) | (ap_const_logic_0 == grp_fFetch_array_fu_599_ap_done)) & (ap_ST_st68_fsm_68 == ap_CS_fsm))) begin
ap_NS_fsm = ap_ST_st69_fsm_69;
end else if ((ap_ST_st67_fsm_67 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st68_fsm_68;
end else if ((~((ap_const_logic_0 == grp_uFetch_array_fu_583_ap_done) | (ap_const_logic_0 == grp_computeDiffSqr_fu_531_ap_done) | (ap_const_logic_0 == grp_computeGradient_fu_507_ap_done) | (ap_const_logic_0 == grp_computeUG_fu_555_ap_done) | (ap_const_logic_0 == grp_computeResult_fu_467_ap_done) | (ap_const_logic_0 == grp_write_array_fu_571_ap_done) | (ap_const_logic_0 == grp_fFetch_array_fu_599_ap_done)) & (ap_ST_st66_fsm_66 == ap_CS_fsm))) begin
ap_NS_fsm = ap_ST_st67_fsm_67;
end else if ((ap_ST_st65_fsm_65 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st66_fsm_66;
end else if ((~((ap_const_logic_0 == grp_uFetch_array_fu_583_ap_done) | (ap_const_logic_0 == grp_computeDiffSqr_fu_531_ap_done) | (ap_const_logic_0 == grp_computeGradient_fu_507_ap_done) | (ap_const_logic_0 == grp_computeUG_fu_555_ap_done) | (ap_const_logic_0 == grp_computeResult_fu_467_ap_done) | (ap_const_logic_0 == grp_write_array_fu_571_ap_done) | (ap_const_logic_0 == grp_fFetch_array_fu_599_ap_done)) & (ap_ST_st64_fsm_64 == ap_CS_fsm))) begin
ap_NS_fsm = ap_ST_st65_fsm_65;
end else if ((ap_ST_st63_fsm_63 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st64_fsm_64;
end else if ((~((ap_const_logic_0 == grp_uFetch_array_fu_583_ap_done) | (ap_const_logic_0 == grp_computeDiffSqr_fu_531_ap_done) | (ap_const_logic_0 == grp_computeGradient_fu_507_ap_done) | (ap_const_logic_0 == grp_computeUG_fu_555_ap_done) | (ap_const_logic_0 == grp_computeResult_fu_467_ap_done) | (ap_const_logic_0 == grp_write_array_fu_571_ap_done) | (ap_const_logic_0 == grp_fFetch_array_fu_599_ap_done)) & (ap_ST_st62_fsm_62 == ap_CS_fsm))) begin
ap_NS_fsm = ap_ST_st63_fsm_63;
end else if ((ap_ST_st61_fsm_61 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st62_fsm_62;
end else if ((~((ap_const_logic_0 == grp_uFetch_array_fu_583_ap_done) | (ap_const_logic_0 == grp_computeDiffSqr_fu_531_ap_done) | (ap_const_logic_0 == grp_computeGradient_fu_507_ap_done) | (ap_const_logic_0 == grp_computeUG_fu_555_ap_done) | (ap_const_logic_0 == grp_computeResult_fu_467_ap_done) | (ap_const_logic_0 == grp_write_array_fu_571_ap_done) | (ap_const_logic_0 == grp_fFetch_array_fu_599_ap_done)) & (ap_ST_st60_fsm_60 == ap_CS_fsm))) begin
ap_NS_fsm = ap_ST_st61_fsm_61;
end else if ((ap_ST_st59_fsm_59 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st60_fsm_60;
end else if ((~((ap_const_logic_0 == grp_uFetch_array_fu_583_ap_done) | (ap_const_logic_0 == grp_computeDiffSqr_fu_531_ap_done) | (ap_const_logic_0 == grp_computeGradient_fu_507_ap_done) | (ap_const_logic_0 == grp_computeUG_fu_555_ap_done) | (ap_const_logic_0 == grp_computeResult_fu_467_ap_done) | (ap_const_logic_0 == grp_write_array_fu_571_ap_done) | (ap_const_logic_0 == grp_fFetch_array_fu_599_ap_done)) & (ap_ST_st58_fsm_58 == ap_CS_fsm))) begin
ap_NS_fsm = ap_ST_st59_fsm_59;
end else if ((ap_ST_st57_fsm_57 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st58_fsm_58;
end else if ((~((ap_const_logic_0 == grp_uFetch_array_fu_583_ap_done) | (ap_const_logic_0 == grp_computeDiffSqr_fu_531_ap_done) | (ap_const_logic_0 == grp_computeGradient_fu_507_ap_done) | (ap_const_logic_0 == grp_computeUG_fu_555_ap_done) | (ap_const_logic_0 == grp_computeResult_fu_467_ap_done) | (ap_const_logic_0 == grp_write_array_fu_571_ap_done) | (ap_const_logic_0 == grp_fFetch_array_fu_599_ap_done)) & (ap_ST_st56_fsm_56 == ap_CS_fsm))) begin
ap_NS_fsm = ap_ST_st57_fsm_57;
end else if ((ap_ST_st55_fsm_55 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st56_fsm_56;
end else if ((~((ap_const_logic_0 == grp_uFetch_array_fu_583_ap_done) | (ap_const_logic_0 == grp_computeDiffSqr_fu_531_ap_done) | (ap_const_logic_0 == grp_computeGradient_fu_507_ap_done) | (ap_const_logic_0 == grp_computeUG_fu_555_ap_done) | (ap_const_logic_0 == grp_computeResult_fu_467_ap_done) | (ap_const_logic_0 == grp_write_array_fu_571_ap_done) | (ap_const_logic_0 == grp_fFetch_array_fu_599_ap_done)) & (ap_ST_st54_fsm_54 == ap_CS_fsm))) begin
ap_NS_fsm = ap_ST_st55_fsm_55;
end else if ((ap_ST_st53_fsm_53 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st54_fsm_54;
end else if ((~((ap_const_logic_0 == grp_uFetch_array_fu_583_ap_done) | (ap_const_logic_0 == grp_computeDiffSqr_fu_531_ap_done) | (ap_const_logic_0 == grp_computeGradient_fu_507_ap_done) | (ap_const_logic_0 == grp_computeUG_fu_555_ap_done) | (ap_const_logic_0 == grp_computeResult_fu_467_ap_done) | (ap_const_logic_0 == grp_write_array_fu_571_ap_done) | (ap_const_logic_0 == grp_fFetch_array_fu_599_ap_done)) & (ap_ST_st52_fsm_52 == ap_CS_fsm))) begin
ap_NS_fsm = ap_ST_st53_fsm_53;
end else if ((ap_ST_st51_fsm_51 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st52_fsm_52;
end else if ((~((ap_const_logic_0 == grp_uFetch_array_fu_583_ap_done) | (ap_const_logic_0 == grp_computeDiffSqr_fu_531_ap_done) | (ap_const_logic_0 == grp_computeGradient_fu_507_ap_done) | (ap_const_logic_0 == grp_computeUG_fu_555_ap_done) | (ap_const_logic_0 == grp_computeResult_fu_467_ap_done) | (ap_const_logic_0 == grp_write_array_fu_571_ap_done) | (ap_const_logic_0 == grp_fFetch_array_fu_599_ap_done)) & (ap_ST_st50_fsm_50 == ap_CS_fsm))) begin
ap_NS_fsm = ap_ST_st51_fsm_51;
end else if ((ap_ST_st49_fsm_49 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st50_fsm_50;
end else if ((~((ap_const_logic_0 == grp_uFetch_array_fu_583_ap_done) | (ap_const_logic_0 == grp_computeDiffSqr_fu_531_ap_done) | (ap_const_logic_0 == grp_computeGradient_fu_507_ap_done) | (ap_const_logic_0 == grp_computeUG_fu_555_ap_done) | (ap_const_logic_0 == grp_computeResult_fu_467_ap_done) | (ap_const_logic_0 == grp_write_array_fu_571_ap_done) | (ap_const_logic_0 == grp_fFetch_array_fu_599_ap_done)) & (ap_ST_st48_fsm_48 == ap_CS_fsm))) begin
ap_NS_fsm = ap_ST_st49_fsm_49;
end else if ((ap_ST_st47_fsm_47 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st48_fsm_48;
end else if ((~((ap_const_logic_0 == grp_uFetch_array_fu_583_ap_done) | (ap_const_logic_0 == grp_computeDiffSqr_fu_531_ap_done) | (ap_const_logic_0 == grp_computeGradient_fu_507_ap_done) | (ap_const_logic_0 == grp_computeUG_fu_555_ap_done) | (ap_const_logic_0 == grp_computeResult_fu_467_ap_done) | (ap_const_logic_0 == grp_write_array_fu_571_ap_done) | (ap_const_logic_0 == grp_fFetch_array_fu_599_ap_done)) & (ap_ST_st46_fsm_46 == ap_CS_fsm))) begin
ap_NS_fsm = ap_ST_st47_fsm_47;
end else if ((ap_ST_st45_fsm_45 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st46_fsm_46;
end else if ((~((ap_const_logic_0 == grp_uFetch_array_fu_583_ap_done) | (ap_const_logic_0 == grp_computeDiffSqr_fu_531_ap_done) | (ap_const_logic_0 == grp_computeGradient_fu_507_ap_done) | (ap_const_logic_0 == grp_computeUG_fu_555_ap_done) | (ap_const_logic_0 == grp_computeResult_fu_467_ap_done) | (ap_const_logic_0 == grp_write_array_fu_571_ap_done) | (ap_const_logic_0 == grp_fFetch_array_fu_599_ap_done)) & (ap_ST_st44_fsm_44 == ap_CS_fsm))) begin
ap_NS_fsm = ap_ST_st45_fsm_45;
end else if ((ap_ST_st43_fsm_43 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st44_fsm_44;
end else if ((~((ap_const_logic_0 == grp_uFetch_array_fu_583_ap_done) | (ap_const_logic_0 == grp_computeDiffSqr_fu_531_ap_done) | (ap_const_logic_0 == grp_computeGradient_fu_507_ap_done) | (ap_const_logic_0 == grp_computeUG_fu_555_ap_done) | (ap_const_logic_0 == grp_computeResult_fu_467_ap_done) | (ap_const_logic_0 == grp_write_array_fu_571_ap_done) | (ap_const_logic_0 == grp_fFetch_array_fu_599_ap_done)) & (ap_ST_st42_fsm_42 == ap_CS_fsm))) begin
ap_NS_fsm = ap_ST_st43_fsm_43;
end else if ((ap_ST_st41_fsm_41 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st42_fsm_42;
end else if ((~((ap_const_logic_0 == grp_uFetch_array_fu_583_ap_done) | (ap_const_logic_0 == grp_computeDiffSqr_fu_531_ap_done) | (ap_const_logic_0 == grp_computeGradient_fu_507_ap_done) | (ap_const_logic_0 == grp_computeUG_fu_555_ap_done) | (ap_const_logic_0 == grp_computeResult_fu_467_ap_done) | (ap_const_logic_0 == grp_write_array_fu_571_ap_done) | (ap_const_logic_0 == grp_fFetch_array_fu_599_ap_done)) & (ap_ST_st40_fsm_40 == ap_CS_fsm))) begin
ap_NS_fsm = ap_ST_st41_fsm_41;
end else if ((ap_ST_st39_fsm_39 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st40_fsm_40;
end else if ((~((ap_const_logic_0 == grp_uFetch_array_fu_583_ap_done) | (ap_const_logic_0 == grp_computeDiffSqr_fu_531_ap_done) | (ap_const_logic_0 == grp_computeGradient_fu_507_ap_done) | (ap_const_logic_0 == grp_computeUG_fu_555_ap_done) | (ap_const_logic_0 == grp_computeResult_fu_467_ap_done) | (ap_const_logic_0 == grp_write_array_fu_571_ap_done) | (ap_const_logic_0 == grp_fFetch_array_fu_599_ap_done)) & (ap_ST_st38_fsm_38 == ap_CS_fsm))) begin
ap_NS_fsm = ap_ST_st39_fsm_39;
end else if ((ap_ST_st37_fsm_37 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st38_fsm_38;
end else if ((~((ap_const_logic_0 == grp_uFetch_array_fu_583_ap_done) | (ap_const_logic_0 == grp_computeDiffSqr_fu_531_ap_done) | (ap_const_logic_0 == grp_computeGradient_fu_507_ap_done) | (ap_const_logic_0 == grp_computeUG_fu_555_ap_done) | (ap_const_logic_0 == grp_computeResult_fu_467_ap_done) | (ap_const_logic_0 == grp_write_array_fu_571_ap_done) | (ap_const_logic_0 == grp_fFetch_array_fu_599_ap_done)) & (ap_ST_st36_fsm_36 == ap_CS_fsm))) begin
ap_NS_fsm = ap_ST_st37_fsm_37;
end else if ((ap_ST_st35_fsm_35 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st36_fsm_36;
end else if ((~((ap_const_logic_0 == grp_uFetch_array_fu_583_ap_done) | (ap_const_logic_0 == grp_computeDiffSqr_fu_531_ap_done) | (ap_const_logic_0 == grp_computeGradient_fu_507_ap_done) | (ap_const_logic_0 == grp_computeUG_fu_555_ap_done) | (ap_const_logic_0 == grp_computeResult_fu_467_ap_done) | (ap_const_logic_0 == grp_write_array_fu_571_ap_done) | (ap_const_logic_0 == grp_fFetch_array_fu_599_ap_done)) & (ap_ST_st34_fsm_34 == ap_CS_fsm))) begin
ap_NS_fsm = ap_ST_st35_fsm_35;
end else if ((ap_ST_st33_fsm_33 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st34_fsm_34;
end else if ((~((ap_const_logic_0 == grp_uFetch_array_fu_583_ap_done) | (ap_const_logic_0 == grp_computeDiffSqr_fu_531_ap_done) | (ap_const_logic_0 == grp_computeGradient_fu_507_ap_done) | (ap_const_logic_0 == grp_computeUG_fu_555_ap_done) | (ap_const_logic_0 == grp_computeResult_fu_467_ap_done) | (ap_const_logic_0 == grp_write_array_fu_571_ap_done) | (ap_const_logic_0 == grp_fFetch_array_fu_599_ap_done)) & (ap_ST_st32_fsm_32 == ap_CS_fsm))) begin
ap_NS_fsm = ap_ST_st33_fsm_33;
end else if ((ap_ST_st31_fsm_31 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st32_fsm_32;
end else if ((~((ap_const_logic_0 == grp_uFetch_array_fu_583_ap_done) | (ap_const_logic_0 == grp_computeDiffSqr_fu_531_ap_done) | (ap_const_logic_0 == grp_computeGradient_fu_507_ap_done) | (ap_const_logic_0 == grp_computeUG_fu_555_ap_done) | (ap_const_logic_0 == grp_computeResult_fu_467_ap_done) | (ap_const_logic_0 == grp_write_array_fu_571_ap_done) | (ap_const_logic_0 == grp_fFetch_array_fu_599_ap_done)) & (ap_ST_st30_fsm_30 == ap_CS_fsm))) begin
ap_NS_fsm = ap_ST_st31_fsm_31;
end else if ((ap_ST_st29_fsm_29 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st30_fsm_30;
end else if ((~((ap_const_logic_0 == grp_uFetch_array_fu_583_ap_done) | (ap_const_logic_0 == grp_computeDiffSqr_fu_531_ap_done) | (ap_const_logic_0 == grp_computeGradient_fu_507_ap_done) | (ap_const_logic_0 == grp_computeUG_fu_555_ap_done) | (ap_const_logic_0 == grp_computeResult_fu_467_ap_done) | (ap_const_logic_0 == grp_write_array_fu_571_ap_done) | (ap_const_logic_0 == grp_fFetch_array_fu_599_ap_done)) & (ap_ST_st28_fsm_28 == ap_CS_fsm))) begin
ap_NS_fsm = ap_ST_st29_fsm_29;
end else if ((ap_ST_st27_fsm_27 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st28_fsm_28;
end else if ((~((ap_const_logic_0 == grp_uFetch_array_fu_583_ap_done) | (ap_const_logic_0 == grp_computeDiffSqr_fu_531_ap_done) | (ap_const_logic_0 == grp_computeGradient_fu_507_ap_done) | (ap_const_logic_0 == grp_computeUG_fu_555_ap_done) | (ap_const_logic_0 == grp_computeResult_fu_467_ap_done) | (ap_const_logic_0 == grp_write_array_fu_571_ap_done) | (ap_const_logic_0 == grp_fFetch_array_fu_599_ap_done)) & (ap_ST_st26_fsm_26 == ap_CS_fsm))) begin
ap_NS_fsm = ap_ST_st27_fsm_27;
end else if ((ap_ST_st25_fsm_25 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st26_fsm_26;
end else if ((~((ap_const_logic_0 == grp_uFetch_array_fu_583_ap_done) | (ap_const_logic_0 == grp_computeDiffSqr_fu_531_ap_done) | (ap_const_logic_0 == grp_computeGradient_fu_507_ap_done) | (ap_const_logic_0 == grp_computeUG_fu_555_ap_done) | (ap_const_logic_0 == grp_computeResult_fu_467_ap_done) | (ap_const_logic_0 == grp_write_array_fu_571_ap_done) | (ap_const_logic_0 == grp_fFetch_array_fu_599_ap_done)) & (ap_ST_st24_fsm_24 == ap_CS_fsm))) begin
ap_NS_fsm = ap_ST_st25_fsm_25;
end else if ((ap_ST_st23_fsm_23 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st24_fsm_24;
end else if ((~((ap_const_logic_0 == grp_uFetch_array_fu_583_ap_done) | (ap_const_logic_0 == grp_computeDiffSqr_fu_531_ap_done) | (ap_const_logic_0 == grp_computeGradient_fu_507_ap_done) | (ap_const_logic_0 == grp_computeUG_fu_555_ap_done) | (ap_const_logic_0 == grp_computeResult_fu_467_ap_done) | (ap_const_logic_0 == grp_write_array_fu_571_ap_done) | (ap_const_logic_0 == grp_fFetch_array_fu_599_ap_done)) & (ap_ST_st22_fsm_22 == ap_CS_fsm))) begin
ap_NS_fsm = ap_ST_st23_fsm_23;
end else if ((ap_ST_st21_fsm_21 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st22_fsm_22;
end else if ((~((ap_const_logic_0 == grp_uFetch_array_fu_583_ap_done) | (ap_const_logic_0 == grp_computeDiffSqr_fu_531_ap_done) | (ap_const_logic_0 == grp_computeGradient_fu_507_ap_done) | (ap_const_logic_0 == grp_computeUG_fu_555_ap_done) | (ap_const_logic_0 == grp_computeResult_fu_467_ap_done) | (ap_const_logic_0 == grp_write_array_fu_571_ap_done) | (ap_const_logic_0 == grp_fFetch_array_fu_599_ap_done)) & (ap_ST_st20_fsm_20 == ap_CS_fsm))) begin
ap_NS_fsm = ap_ST_st21_fsm_21;
end else if ((ap_ST_st19_fsm_19 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st20_fsm_20;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) & ~((ap_const_logic_0 == grp_uFetch_array_fu_583_ap_done) | (ap_const_logic_0 == grp_computeDiffSqr_fu_531_ap_done) | (ap_const_logic_0 == grp_computeGradient_fu_507_ap_done) | (ap_const_logic_0 == grp_computeUG_fu_555_ap_done) | (ap_const_logic_0 == grp_computeResult_fu_467_ap_done) | (ap_const_logic_0 == grp_write_array_fu_571_ap_done) | (ap_const_logic_0 == grp_fFetch_array_fu_599_ap_done)))) begin
ap_NS_fsm = ap_ST_st19_fsm_19;
end else if ((ap_ST_st17_fsm_17 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st18_fsm_18;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) & ~((ap_const_logic_0 == grp_uFetch_array_fu_583_ap_done) | (ap_const_logic_0 == grp_computeDiffSqr_fu_531_ap_done) | (ap_const_logic_0 == grp_computeGradient_fu_507_ap_done) | (ap_const_logic_0 == grp_computeUG_fu_555_ap_done) | (ap_const_logic_0 == grp_computeResult_fu_467_ap_done)))) begin
ap_NS_fsm = ap_ST_st17_fsm_17;
end else if ((ap_ST_st15_fsm_15 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st16_fsm_16;
end else if (((ap_ST_st14_fsm_14 == ap_CS_fsm) & ~((ap_const_logic_0 == grp_uFetch_array_fu_583_ap_done) | (ap_const_logic_0 == grp_computeDiffSqr_fu_531_ap_done) | (ap_const_logic_0 == grp_computeGradient_fu_507_ap_done) | (ap_const_logic_0 == grp_computeUG_fu_555_ap_done)))) begin
ap_NS_fsm = ap_ST_st15_fsm_15;
end else if ((ap_ST_st13_fsm_13 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st14_fsm_14;
end else if (((ap_ST_st12_fsm_12 == ap_CS_fsm) & ~((ap_const_logic_0 == grp_uFetch_array_fu_583_ap_done) | (ap_const_logic_0 == grp_computeDiffSqr_fu_531_ap_done) | (ap_const_logic_0 == grp_computeGradient_fu_507_ap_done) | (ap_const_logic_0 == grp_computeUG_fu_555_ap_done)))) begin
ap_NS_fsm = ap_ST_st13_fsm_13;
end else if ((ap_ST_st11_fsm_11 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st12_fsm_12;
end else if (((ap_ST_st10_fsm_10 == ap_CS_fsm) & ~((ap_const_logic_0 == grp_uFetch_array_fu_583_ap_done) | (ap_const_logic_0 == grp_computeDiffSqr_fu_531_ap_done) | (ap_const_logic_0 == grp_computeGradient_fu_507_ap_done)))) begin
ap_NS_fsm = ap_ST_st11_fsm_11;
end else if ((ap_ST_st9_fsm_9 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st10_fsm_10;
end else if (((ap_ST_st8_fsm_8 == ap_CS_fsm) & ~((ap_const_logic_0 == grp_uFetch_array_fu_583_ap_done) | (ap_const_logic_0 == grp_computeDiffSqr_fu_531_ap_done)))) begin
ap_NS_fsm = ap_ST_st9_fsm_9;
end else if ((ap_ST_st7_fsm_7 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st8_fsm_8;
end else if (((ap_ST_st6_fsm_6 == ap_CS_fsm) & ~((ap_const_logic_0 == grp_uFetch_array_fu_583_ap_done) | (ap_const_logic_0 == grp_computeDiffSqr_fu_531_ap_done) | (ap_const_logic_0 == grp_fFetch_array_fu_599_ap_done)))) begin
ap_NS_fsm = ap_ST_st7_fsm_7;
end else if ((ap_ST_st5_fsm_5 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st6_fsm_6;
end else if (((ap_ST_st4_fsm_4 == ap_CS_fsm) & ~((ap_const_logic_0 == grp_uFetch_array_fu_583_ap_done) | (ap_const_logic_0 == grp_fFetch_array_fu_599_ap_done)))) begin
ap_NS_fsm = ap_ST_st5_fsm_5;
end else if ((ap_ST_st3_fsm_3 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st4_fsm_4;
end else if (((ap_ST_st2_fsm_2 == ap_CS_fsm) & ~((ap_const_logic_0 == grp_uFetch_array_fu_583_ap_done) | (ap_const_logic_0 == grp_fFetch_array_fu_599_ap_done)))) begin
ap_NS_fsm = ap_ST_st3_fsm_3;
end else if ((ap_ST_st1_fsm_1 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st2_fsm_2;
end else if ((((ap_ST_st0_fsm_0 == ap_CS_fsm) & (ap_const_logic_1 == ap_start)) | ((ap_ST_st132_fsm_132 == ap_CS_fsm) & ~(ap_const_logic_0 == grp_write_array_fu_571_ap_done) & (ap_const_logic_1 == ap_start)))) begin
ap_NS_fsm = ap_ST_st1_fsm_1;
end else begin
ap_NS_fsm = ap_CS_fsm;
end
end
/// ap_done assign process. ///
always @ (ap_CS_fsm or grp_write_array_fu_571_ap_done)
begin
if (((ap_ST_st132_fsm_132 == ap_CS_fsm) & ~(ap_const_logic_0 == grp_write_array_fu_571_ap_done))) begin
ap_done = ap_const_logic_1;
end else begin
ap_done = ap_const_logic_0;
end
end
/// ap_idle assign process. ///
always @ (ap_CS_fsm)
begin
if ((ap_ST_st0_fsm_0 == ap_CS_fsm)) begin
ap_idle = ap_const_logic_1;
end else begin
ap_idle = ap_const_logic_0;
end
end
/// f0_p0_address0 assign process. ///
always @ (ap_CS_fsm or grp_computeResult_fu_467_f_p0_address0 or grp_fFetch_array_fu_599_data_p0_address0)
begin
if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st126_fsm_126 == ap_CS_fsm) | (ap_ST_st4_fsm_4 == ap_CS_fsm))) begin
f0_p0_address0 = grp_fFetch_array_fu_599_data_p0_address0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm) | (ap_ST_st128_fsm_128 == ap_CS_fsm))) begin
f0_p0_address0 = grp_computeResult_fu_467_f_p0_address0;
end else begin
f0_p0_address0 = grp_fFetch_array_fu_599_data_p0_address0;
end
end
/// f0_p0_ce0 assign process. ///
always @ (ap_CS_fsm or grp_computeResult_fu_467_f_p0_ce0 or grp_fFetch_array_fu_599_data_p0_ce0)
begin
if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st126_fsm_126 == ap_CS_fsm) | (ap_ST_st4_fsm_4 == ap_CS_fsm))) begin
f0_p0_ce0 = grp_fFetch_array_fu_599_data_p0_ce0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm) | (ap_ST_st128_fsm_128 == ap_CS_fsm))) begin
f0_p0_ce0 = grp_computeResult_fu_467_f_p0_ce0;
end else begin
f0_p0_ce0 = ap_const_logic_0;
end
end
/// f0_p0_we0 assign process. ///
always @ (ap_CS_fsm or grp_fFetch_array_fu_599_data_p0_we0)
begin
if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st126_fsm_126 == ap_CS_fsm) | (ap_ST_st4_fsm_4 == ap_CS_fsm))) begin
f0_p0_we0 = grp_fFetch_array_fu_599_data_p0_we0;
end else begin
f0_p0_we0 = ap_const_logic_0;
end
end
/// f0_p1_address0 assign process. ///
always @ (ap_CS_fsm or grp_computeResult_fu_467_f_p1_address0 or grp_fFetch_array_fu_599_data_p1_address0)
begin
if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st126_fsm_126 == ap_CS_fsm) | (ap_ST_st4_fsm_4 == ap_CS_fsm))) begin
f0_p1_address0 = grp_fFetch_array_fu_599_data_p1_address0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm) | (ap_ST_st128_fsm_128 == ap_CS_fsm))) begin
f0_p1_address0 = grp_computeResult_fu_467_f_p1_address0;
end else begin
f0_p1_address0 = grp_fFetch_array_fu_599_data_p1_address0;
end
end
/// f0_p1_ce0 assign process. ///
always @ (ap_CS_fsm or grp_computeResult_fu_467_f_p1_ce0 or grp_fFetch_array_fu_599_data_p1_ce0)
begin
if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st126_fsm_126 == ap_CS_fsm) | (ap_ST_st4_fsm_4 == ap_CS_fsm))) begin
f0_p1_ce0 = grp_fFetch_array_fu_599_data_p1_ce0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm) | (ap_ST_st128_fsm_128 == ap_CS_fsm))) begin
f0_p1_ce0 = grp_computeResult_fu_467_f_p1_ce0;
end else begin
f0_p1_ce0 = ap_const_logic_0;
end
end
/// f0_p1_we0 assign process. ///
always @ (ap_CS_fsm or grp_fFetch_array_fu_599_data_p1_we0)
begin
if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st126_fsm_126 == ap_CS_fsm) | (ap_ST_st4_fsm_4 == ap_CS_fsm))) begin
f0_p1_we0 = grp_fFetch_array_fu_599_data_p1_we0;
end else begin
f0_p1_we0 = ap_const_logic_0;
end
end
/// f0_p2_address0 assign process. ///
always @ (ap_CS_fsm or grp_computeResult_fu_467_f_p2_address0 or grp_fFetch_array_fu_599_data_p2_address0)
begin
if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st126_fsm_126 == ap_CS_fsm) | (ap_ST_st4_fsm_4 == ap_CS_fsm))) begin
f0_p2_address0 = grp_fFetch_array_fu_599_data_p2_address0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm) | (ap_ST_st128_fsm_128 == ap_CS_fsm))) begin
f0_p2_address0 = grp_computeResult_fu_467_f_p2_address0;
end else begin
f0_p2_address0 = grp_fFetch_array_fu_599_data_p2_address0;
end
end
/// f0_p2_ce0 assign process. ///
always @ (ap_CS_fsm or grp_computeResult_fu_467_f_p2_ce0 or grp_fFetch_array_fu_599_data_p2_ce0)
begin
if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st126_fsm_126 == ap_CS_fsm) | (ap_ST_st4_fsm_4 == ap_CS_fsm))) begin
f0_p2_ce0 = grp_fFetch_array_fu_599_data_p2_ce0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm) | (ap_ST_st128_fsm_128 == ap_CS_fsm))) begin
f0_p2_ce0 = grp_computeResult_fu_467_f_p2_ce0;
end else begin
f0_p2_ce0 = ap_const_logic_0;
end
end
/// f0_p2_we0 assign process. ///
always @ (ap_CS_fsm or grp_fFetch_array_fu_599_data_p2_we0)
begin
if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st126_fsm_126 == ap_CS_fsm) | (ap_ST_st4_fsm_4 == ap_CS_fsm))) begin
f0_p2_we0 = grp_fFetch_array_fu_599_data_p2_we0;
end else begin
f0_p2_we0 = ap_const_logic_0;
end
end
/// f0_p3_address0 assign process. ///
always @ (ap_CS_fsm or grp_computeResult_fu_467_f_p3_address0 or grp_fFetch_array_fu_599_data_p3_address0)
begin
if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st126_fsm_126 == ap_CS_fsm) | (ap_ST_st4_fsm_4 == ap_CS_fsm))) begin
f0_p3_address0 = grp_fFetch_array_fu_599_data_p3_address0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm) | (ap_ST_st128_fsm_128 == ap_CS_fsm))) begin
f0_p3_address0 = grp_computeResult_fu_467_f_p3_address0;
end else begin
f0_p3_address0 = grp_fFetch_array_fu_599_data_p3_address0;
end
end
/// f0_p3_ce0 assign process. ///
always @ (ap_CS_fsm or grp_computeResult_fu_467_f_p3_ce0 or grp_fFetch_array_fu_599_data_p3_ce0)
begin
if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st126_fsm_126 == ap_CS_fsm) | (ap_ST_st4_fsm_4 == ap_CS_fsm))) begin
f0_p3_ce0 = grp_fFetch_array_fu_599_data_p3_ce0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm) | (ap_ST_st128_fsm_128 == ap_CS_fsm))) begin
f0_p3_ce0 = grp_computeResult_fu_467_f_p3_ce0;
end else begin
f0_p3_ce0 = ap_const_logic_0;
end
end
/// f0_p3_we0 assign process. ///
always @ (ap_CS_fsm or grp_fFetch_array_fu_599_data_p3_we0)
begin
if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st126_fsm_126 == ap_CS_fsm) | (ap_ST_st4_fsm_4 == ap_CS_fsm))) begin
f0_p3_we0 = grp_fFetch_array_fu_599_data_p3_we0;
end else begin
f0_p3_we0 = ap_const_logic_0;
end
end
/// f1_p0_address0 assign process. ///
always @ (ap_CS_fsm or grp_computeResult_fu_467_f_p0_address0 or grp_fFetch_array_fu_599_data_p0_address0)
begin
if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm) | (ap_ST_st6_fsm_6 == ap_CS_fsm) | (ap_ST_st2_fsm_2 == ap_CS_fsm))) begin
f1_p0_address0 = grp_fFetch_array_fu_599_data_p0_address0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st126_fsm_126 == ap_CS_fsm) | (ap_ST_st130_fsm_130 == ap_CS_fsm))) begin
f1_p0_address0 = grp_computeResult_fu_467_f_p0_address0;
end else begin
f1_p0_address0 = grp_fFetch_array_fu_599_data_p0_address0;
end
end
/// f1_p0_ce0 assign process. ///
always @ (ap_CS_fsm or grp_computeResult_fu_467_f_p0_ce0 or grp_fFetch_array_fu_599_data_p0_ce0)
begin
if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm) | (ap_ST_st6_fsm_6 == ap_CS_fsm) | (ap_ST_st2_fsm_2 == ap_CS_fsm))) begin
f1_p0_ce0 = grp_fFetch_array_fu_599_data_p0_ce0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st126_fsm_126 == ap_CS_fsm) | (ap_ST_st130_fsm_130 == ap_CS_fsm))) begin
f1_p0_ce0 = grp_computeResult_fu_467_f_p0_ce0;
end else begin
f1_p0_ce0 = ap_const_logic_0;
end
end
/// f1_p0_we0 assign process. ///
always @ (ap_CS_fsm or grp_fFetch_array_fu_599_data_p0_we0)
begin
if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm) | (ap_ST_st6_fsm_6 == ap_CS_fsm) | (ap_ST_st2_fsm_2 == ap_CS_fsm))) begin
f1_p0_we0 = grp_fFetch_array_fu_599_data_p0_we0;
end else begin
f1_p0_we0 = ap_const_logic_0;
end
end
/// f1_p1_address0 assign process. ///
always @ (ap_CS_fsm or grp_computeResult_fu_467_f_p1_address0 or grp_fFetch_array_fu_599_data_p1_address0)
begin
if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm) | (ap_ST_st6_fsm_6 == ap_CS_fsm) | (ap_ST_st2_fsm_2 == ap_CS_fsm))) begin
f1_p1_address0 = grp_fFetch_array_fu_599_data_p1_address0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st126_fsm_126 == ap_CS_fsm) | (ap_ST_st130_fsm_130 == ap_CS_fsm))) begin
f1_p1_address0 = grp_computeResult_fu_467_f_p1_address0;
end else begin
f1_p1_address0 = grp_fFetch_array_fu_599_data_p1_address0;
end
end
/// f1_p1_ce0 assign process. ///
always @ (ap_CS_fsm or grp_computeResult_fu_467_f_p1_ce0 or grp_fFetch_array_fu_599_data_p1_ce0)
begin
if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm) | (ap_ST_st6_fsm_6 == ap_CS_fsm) | (ap_ST_st2_fsm_2 == ap_CS_fsm))) begin
f1_p1_ce0 = grp_fFetch_array_fu_599_data_p1_ce0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st126_fsm_126 == ap_CS_fsm) | (ap_ST_st130_fsm_130 == ap_CS_fsm))) begin
f1_p1_ce0 = grp_computeResult_fu_467_f_p1_ce0;
end else begin
f1_p1_ce0 = ap_const_logic_0;
end
end
/// f1_p1_we0 assign process. ///
always @ (ap_CS_fsm or grp_fFetch_array_fu_599_data_p1_we0)
begin
if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm) | (ap_ST_st6_fsm_6 == ap_CS_fsm) | (ap_ST_st2_fsm_2 == ap_CS_fsm))) begin
f1_p1_we0 = grp_fFetch_array_fu_599_data_p1_we0;
end else begin
f1_p1_we0 = ap_const_logic_0;
end
end
/// f1_p2_address0 assign process. ///
always @ (ap_CS_fsm or grp_computeResult_fu_467_f_p2_address0 or grp_fFetch_array_fu_599_data_p2_address0)
begin
if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm) | (ap_ST_st6_fsm_6 == ap_CS_fsm) | (ap_ST_st2_fsm_2 == ap_CS_fsm))) begin
f1_p2_address0 = grp_fFetch_array_fu_599_data_p2_address0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st126_fsm_126 == ap_CS_fsm) | (ap_ST_st130_fsm_130 == ap_CS_fsm))) begin
f1_p2_address0 = grp_computeResult_fu_467_f_p2_address0;
end else begin
f1_p2_address0 = grp_fFetch_array_fu_599_data_p2_address0;
end
end
/// f1_p2_ce0 assign process. ///
always @ (ap_CS_fsm or grp_computeResult_fu_467_f_p2_ce0 or grp_fFetch_array_fu_599_data_p2_ce0)
begin
if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm) | (ap_ST_st6_fsm_6 == ap_CS_fsm) | (ap_ST_st2_fsm_2 == ap_CS_fsm))) begin
f1_p2_ce0 = grp_fFetch_array_fu_599_data_p2_ce0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st126_fsm_126 == ap_CS_fsm) | (ap_ST_st130_fsm_130 == ap_CS_fsm))) begin
f1_p2_ce0 = grp_computeResult_fu_467_f_p2_ce0;
end else begin
f1_p2_ce0 = ap_const_logic_0;
end
end
/// f1_p2_we0 assign process. ///
always @ (ap_CS_fsm or grp_fFetch_array_fu_599_data_p2_we0)
begin
if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm) | (ap_ST_st6_fsm_6 == ap_CS_fsm) | (ap_ST_st2_fsm_2 == ap_CS_fsm))) begin
f1_p2_we0 = grp_fFetch_array_fu_599_data_p2_we0;
end else begin
f1_p2_we0 = ap_const_logic_0;
end
end
/// f1_p3_address0 assign process. ///
always @ (ap_CS_fsm or grp_computeResult_fu_467_f_p3_address0 or grp_fFetch_array_fu_599_data_p3_address0)
begin
if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm) | (ap_ST_st6_fsm_6 == ap_CS_fsm) | (ap_ST_st2_fsm_2 == ap_CS_fsm))) begin
f1_p3_address0 = grp_fFetch_array_fu_599_data_p3_address0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st126_fsm_126 == ap_CS_fsm) | (ap_ST_st130_fsm_130 == ap_CS_fsm))) begin
f1_p3_address0 = grp_computeResult_fu_467_f_p3_address0;
end else begin
f1_p3_address0 = grp_fFetch_array_fu_599_data_p3_address0;
end
end
/// f1_p3_ce0 assign process. ///
always @ (ap_CS_fsm or grp_computeResult_fu_467_f_p3_ce0 or grp_fFetch_array_fu_599_data_p3_ce0)
begin
if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm) | (ap_ST_st6_fsm_6 == ap_CS_fsm) | (ap_ST_st2_fsm_2 == ap_CS_fsm))) begin
f1_p3_ce0 = grp_fFetch_array_fu_599_data_p3_ce0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st126_fsm_126 == ap_CS_fsm) | (ap_ST_st130_fsm_130 == ap_CS_fsm))) begin
f1_p3_ce0 = grp_computeResult_fu_467_f_p3_ce0;
end else begin
f1_p3_ce0 = ap_const_logic_0;
end
end
/// f1_p3_we0 assign process. ///
always @ (ap_CS_fsm or grp_fFetch_array_fu_599_data_p3_we0)
begin
if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm) | (ap_ST_st6_fsm_6 == ap_CS_fsm) | (ap_ST_st2_fsm_2 == ap_CS_fsm))) begin
f1_p3_we0 = grp_fFetch_array_fu_599_data_p3_we0;
end else begin
f1_p3_we0 = ap_const_logic_0;
end
end
/// g0_p0_address0 assign process. ///
always @ (ap_CS_fsm or grp_computeResult_fu_467_g0_p0_address0 or grp_computeResult_fu_467_g1_p0_address0 or grp_computeResult_fu_467_g2_p0_address0 or grp_computeGradient_fu_507_g_p0_address0 or grp_computeUG_fu_555_g_p0_address0)
begin
if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm))) begin
g0_p0_address0 = grp_computeUG_fu_555_g_p0_address0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm))) begin
g0_p0_address0 = grp_computeGradient_fu_507_g_p0_address0;
end else if (((ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm))) begin
g0_p0_address0 = grp_computeResult_fu_467_g2_p0_address0;
end else if (((ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm))) begin
g0_p0_address0 = grp_computeResult_fu_467_g1_p0_address0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st126_fsm_126 == ap_CS_fsm))) begin
g0_p0_address0 = grp_computeResult_fu_467_g0_p0_address0;
end else begin
g0_p0_address0 = grp_computeUG_fu_555_g_p0_address0;
end
end
/// g0_p0_ce0 assign process. ///
always @ (ap_CS_fsm or grp_computeResult_fu_467_g0_p0_ce0 or grp_computeResult_fu_467_g1_p0_ce0 or grp_computeResult_fu_467_g2_p0_ce0 or grp_computeGradient_fu_507_g_p0_ce0 or grp_computeUG_fu_555_g_p0_ce0)
begin
if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm))) begin
g0_p0_ce0 = grp_computeUG_fu_555_g_p0_ce0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm))) begin
g0_p0_ce0 = grp_computeGradient_fu_507_g_p0_ce0;
end else if (((ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm))) begin
g0_p0_ce0 = grp_computeResult_fu_467_g2_p0_ce0;
end else if (((ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm))) begin
g0_p0_ce0 = grp_computeResult_fu_467_g1_p0_ce0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st126_fsm_126 == ap_CS_fsm))) begin
g0_p0_ce0 = grp_computeResult_fu_467_g0_p0_ce0;
end else begin
g0_p0_ce0 = ap_const_logic_0;
end
end
/// g0_p0_ce1 assign process. ///
always @ (ap_CS_fsm or grp_computeResult_fu_467_g1_p0_ce1)
begin
if (((ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm))) begin
g0_p0_ce1 = grp_computeResult_fu_467_g1_p0_ce1;
end else begin
g0_p0_ce1 = ap_const_logic_0;
end
end
/// g0_p0_we0 assign process. ///
always @ (ap_CS_fsm or grp_computeGradient_fu_507_g_p0_we0)
begin
if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm))) begin
g0_p0_we0 = grp_computeGradient_fu_507_g_p0_we0;
end else begin
g0_p0_we0 = ap_const_logic_0;
end
end
/// g0_p1_address0 assign process. ///
always @ (ap_CS_fsm or grp_computeResult_fu_467_g0_p1_address0 or grp_computeResult_fu_467_g1_p1_address0 or grp_computeResult_fu_467_g2_p1_address0 or grp_computeGradient_fu_507_g_p1_address0 or grp_computeUG_fu_555_g_p1_address0)
begin
if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm))) begin
g0_p1_address0 = grp_computeUG_fu_555_g_p1_address0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm))) begin
g0_p1_address0 = grp_computeGradient_fu_507_g_p1_address0;
end else if (((ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm))) begin
g0_p1_address0 = grp_computeResult_fu_467_g2_p1_address0;
end else if (((ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm))) begin
g0_p1_address0 = grp_computeResult_fu_467_g1_p1_address0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st126_fsm_126 == ap_CS_fsm))) begin
g0_p1_address0 = grp_computeResult_fu_467_g0_p1_address0;
end else begin
g0_p1_address0 = grp_computeUG_fu_555_g_p1_address0;
end
end
/// g0_p1_ce0 assign process. ///
always @ (ap_CS_fsm or grp_computeResult_fu_467_g0_p1_ce0 or grp_computeResult_fu_467_g1_p1_ce0 or grp_computeResult_fu_467_g2_p1_ce0 or grp_computeGradient_fu_507_g_p1_ce0 or grp_computeUG_fu_555_g_p1_ce0)
begin
if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm))) begin
g0_p1_ce0 = grp_computeUG_fu_555_g_p1_ce0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm))) begin
g0_p1_ce0 = grp_computeGradient_fu_507_g_p1_ce0;
end else if (((ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm))) begin
g0_p1_ce0 = grp_computeResult_fu_467_g2_p1_ce0;
end else if (((ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm))) begin
g0_p1_ce0 = grp_computeResult_fu_467_g1_p1_ce0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st126_fsm_126 == ap_CS_fsm))) begin
g0_p1_ce0 = grp_computeResult_fu_467_g0_p1_ce0;
end else begin
g0_p1_ce0 = ap_const_logic_0;
end
end
/// g0_p1_we0 assign process. ///
always @ (ap_CS_fsm or grp_computeGradient_fu_507_g_p1_we0)
begin
if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm))) begin
g0_p1_we0 = grp_computeGradient_fu_507_g_p1_we0;
end else begin
g0_p1_we0 = ap_const_logic_0;
end
end
/// g0_p2_address0 assign process. ///
always @ (ap_CS_fsm or grp_computeResult_fu_467_g0_p2_address0 or grp_computeResult_fu_467_g1_p2_address0 or grp_computeResult_fu_467_g2_p2_address0 or grp_computeGradient_fu_507_g_p2_address0 or grp_computeUG_fu_555_g_p2_address0)
begin
if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm))) begin
g0_p2_address0 = grp_computeUG_fu_555_g_p2_address0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm))) begin
g0_p2_address0 = grp_computeGradient_fu_507_g_p2_address0;
end else if (((ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm))) begin
g0_p2_address0 = grp_computeResult_fu_467_g2_p2_address0;
end else if (((ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm))) begin
g0_p2_address0 = grp_computeResult_fu_467_g1_p2_address0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st126_fsm_126 == ap_CS_fsm))) begin
g0_p2_address0 = grp_computeResult_fu_467_g0_p2_address0;
end else begin
g0_p2_address0 = grp_computeUG_fu_555_g_p2_address0;
end
end
/// g0_p2_ce0 assign process. ///
always @ (ap_CS_fsm or grp_computeResult_fu_467_g0_p2_ce0 or grp_computeResult_fu_467_g1_p2_ce0 or grp_computeResult_fu_467_g2_p2_ce0 or grp_computeGradient_fu_507_g_p2_ce0 or grp_computeUG_fu_555_g_p2_ce0)
begin
if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm))) begin
g0_p2_ce0 = grp_computeUG_fu_555_g_p2_ce0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm))) begin
g0_p2_ce0 = grp_computeGradient_fu_507_g_p2_ce0;
end else if (((ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm))) begin
g0_p2_ce0 = grp_computeResult_fu_467_g2_p2_ce0;
end else if (((ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm))) begin
g0_p2_ce0 = grp_computeResult_fu_467_g1_p2_ce0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st126_fsm_126 == ap_CS_fsm))) begin
g0_p2_ce0 = grp_computeResult_fu_467_g0_p2_ce0;
end else begin
g0_p2_ce0 = ap_const_logic_0;
end
end
/// g0_p2_we0 assign process. ///
always @ (ap_CS_fsm or grp_computeGradient_fu_507_g_p2_we0)
begin
if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm))) begin
g0_p2_we0 = grp_computeGradient_fu_507_g_p2_we0;
end else begin
g0_p2_we0 = ap_const_logic_0;
end
end
/// g0_p3_address0 assign process. ///
always @ (ap_CS_fsm or grp_computeResult_fu_467_g0_p3_address0 or grp_computeResult_fu_467_g1_p3_address0 or grp_computeResult_fu_467_g2_p3_address0 or grp_computeGradient_fu_507_g_p3_address0 or grp_computeUG_fu_555_g_p3_address0)
begin
if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm))) begin
g0_p3_address0 = grp_computeUG_fu_555_g_p3_address0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm))) begin
g0_p3_address0 = grp_computeGradient_fu_507_g_p3_address0;
end else if (((ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm))) begin
g0_p3_address0 = grp_computeResult_fu_467_g2_p3_address0;
end else if (((ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm))) begin
g0_p3_address0 = grp_computeResult_fu_467_g1_p3_address0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st126_fsm_126 == ap_CS_fsm))) begin
g0_p3_address0 = grp_computeResult_fu_467_g0_p3_address0;
end else begin
g0_p3_address0 = grp_computeUG_fu_555_g_p3_address0;
end
end
/// g0_p3_ce0 assign process. ///
always @ (ap_CS_fsm or grp_computeResult_fu_467_g0_p3_ce0 or grp_computeResult_fu_467_g1_p3_ce0 or grp_computeResult_fu_467_g2_p3_ce0 or grp_computeGradient_fu_507_g_p3_ce0 or grp_computeUG_fu_555_g_p3_ce0)
begin
if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm))) begin
g0_p3_ce0 = grp_computeUG_fu_555_g_p3_ce0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm))) begin
g0_p3_ce0 = grp_computeGradient_fu_507_g_p3_ce0;
end else if (((ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm))) begin
g0_p3_ce0 = grp_computeResult_fu_467_g2_p3_ce0;
end else if (((ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm))) begin
g0_p3_ce0 = grp_computeResult_fu_467_g1_p3_ce0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st126_fsm_126 == ap_CS_fsm))) begin
g0_p3_ce0 = grp_computeResult_fu_467_g0_p3_ce0;
end else begin
g0_p3_ce0 = ap_const_logic_0;
end
end
/// g0_p3_ce1 assign process. ///
always @ (ap_CS_fsm or grp_computeResult_fu_467_g1_p3_ce1)
begin
if (((ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm))) begin
g0_p3_ce1 = grp_computeResult_fu_467_g1_p3_ce1;
end else begin
g0_p3_ce1 = ap_const_logic_0;
end
end
/// g0_p3_we0 assign process. ///
always @ (ap_CS_fsm or grp_computeGradient_fu_507_g_p3_we0)
begin
if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm))) begin
g0_p3_we0 = grp_computeGradient_fu_507_g_p3_we0;
end else begin
g0_p3_we0 = ap_const_logic_0;
end
end
/// g1_p0_address0 assign process. ///
always @ (ap_CS_fsm or grp_computeResult_fu_467_g0_p0_address0 or grp_computeResult_fu_467_g1_p0_address0 or grp_computeResult_fu_467_g2_p0_address0 or grp_computeGradient_fu_507_g_p0_address0 or grp_computeUG_fu_555_g_p0_address0)
begin
if (((ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st12_fsm_12 == ap_CS_fsm))) begin
g1_p0_address0 = grp_computeUG_fu_555_g_p0_address0;
end else if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st10_fsm_10 == ap_CS_fsm))) begin
g1_p0_address0 = grp_computeGradient_fu_507_g_p0_address0;
end else if (((ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm))) begin
g1_p0_address0 = grp_computeResult_fu_467_g2_p0_address0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st126_fsm_126 == ap_CS_fsm))) begin
g1_p0_address0 = grp_computeResult_fu_467_g1_p0_address0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st128_fsm_128 == ap_CS_fsm))) begin
g1_p0_address0 = grp_computeResult_fu_467_g0_p0_address0;
end else begin
g1_p0_address0 = grp_computeUG_fu_555_g_p0_address0;
end
end
/// g1_p0_ce0 assign process. ///
always @ (ap_CS_fsm or grp_computeResult_fu_467_g0_p0_ce0 or grp_computeResult_fu_467_g1_p0_ce0 or grp_computeResult_fu_467_g2_p0_ce0 or grp_computeGradient_fu_507_g_p0_ce0 or grp_computeUG_fu_555_g_p0_ce0)
begin
if (((ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st12_fsm_12 == ap_CS_fsm))) begin
g1_p0_ce0 = grp_computeUG_fu_555_g_p0_ce0;
end else if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st10_fsm_10 == ap_CS_fsm))) begin
g1_p0_ce0 = grp_computeGradient_fu_507_g_p0_ce0;
end else if (((ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm))) begin
g1_p0_ce0 = grp_computeResult_fu_467_g2_p0_ce0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st126_fsm_126 == ap_CS_fsm))) begin
g1_p0_ce0 = grp_computeResult_fu_467_g1_p0_ce0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st128_fsm_128 == ap_CS_fsm))) begin
g1_p0_ce0 = grp_computeResult_fu_467_g0_p0_ce0;
end else begin
g1_p0_ce0 = ap_const_logic_0;
end
end
/// g1_p0_ce1 assign process. ///
always @ (ap_CS_fsm or grp_computeResult_fu_467_g1_p0_ce1)
begin
if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st126_fsm_126 == ap_CS_fsm))) begin
g1_p0_ce1 = grp_computeResult_fu_467_g1_p0_ce1;
end else begin
g1_p0_ce1 = ap_const_logic_0;
end
end
/// g1_p0_we0 assign process. ///
always @ (ap_CS_fsm or grp_computeGradient_fu_507_g_p0_we0)
begin
if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st10_fsm_10 == ap_CS_fsm))) begin
g1_p0_we0 = grp_computeGradient_fu_507_g_p0_we0;
end else begin
g1_p0_we0 = ap_const_logic_0;
end
end
/// g1_p1_address0 assign process. ///
always @ (ap_CS_fsm or grp_computeResult_fu_467_g0_p1_address0 or grp_computeResult_fu_467_g1_p1_address0 or grp_computeResult_fu_467_g2_p1_address0 or grp_computeGradient_fu_507_g_p1_address0 or grp_computeUG_fu_555_g_p1_address0)
begin
if (((ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st12_fsm_12 == ap_CS_fsm))) begin
g1_p1_address0 = grp_computeUG_fu_555_g_p1_address0;
end else if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st10_fsm_10 == ap_CS_fsm))) begin
g1_p1_address0 = grp_computeGradient_fu_507_g_p1_address0;
end else if (((ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm))) begin
g1_p1_address0 = grp_computeResult_fu_467_g2_p1_address0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st126_fsm_126 == ap_CS_fsm))) begin
g1_p1_address0 = grp_computeResult_fu_467_g1_p1_address0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st128_fsm_128 == ap_CS_fsm))) begin
g1_p1_address0 = grp_computeResult_fu_467_g0_p1_address0;
end else begin
g1_p1_address0 = grp_computeUG_fu_555_g_p1_address0;
end
end
/// g1_p1_ce0 assign process. ///
always @ (ap_CS_fsm or grp_computeResult_fu_467_g0_p1_ce0 or grp_computeResult_fu_467_g1_p1_ce0 or grp_computeResult_fu_467_g2_p1_ce0 or grp_computeGradient_fu_507_g_p1_ce0 or grp_computeUG_fu_555_g_p1_ce0)
begin
if (((ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st12_fsm_12 == ap_CS_fsm))) begin
g1_p1_ce0 = grp_computeUG_fu_555_g_p1_ce0;
end else if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st10_fsm_10 == ap_CS_fsm))) begin
g1_p1_ce0 = grp_computeGradient_fu_507_g_p1_ce0;
end else if (((ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm))) begin
g1_p1_ce0 = grp_computeResult_fu_467_g2_p1_ce0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st126_fsm_126 == ap_CS_fsm))) begin
g1_p1_ce0 = grp_computeResult_fu_467_g1_p1_ce0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st128_fsm_128 == ap_CS_fsm))) begin
g1_p1_ce0 = grp_computeResult_fu_467_g0_p1_ce0;
end else begin
g1_p1_ce0 = ap_const_logic_0;
end
end
/// g1_p1_we0 assign process. ///
always @ (ap_CS_fsm or grp_computeGradient_fu_507_g_p1_we0)
begin
if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st10_fsm_10 == ap_CS_fsm))) begin
g1_p1_we0 = grp_computeGradient_fu_507_g_p1_we0;
end else begin
g1_p1_we0 = ap_const_logic_0;
end
end
/// g1_p2_address0 assign process. ///
always @ (ap_CS_fsm or grp_computeResult_fu_467_g0_p2_address0 or grp_computeResult_fu_467_g1_p2_address0 or grp_computeResult_fu_467_g2_p2_address0 or grp_computeGradient_fu_507_g_p2_address0 or grp_computeUG_fu_555_g_p2_address0)
begin
if (((ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st12_fsm_12 == ap_CS_fsm))) begin
g1_p2_address0 = grp_computeUG_fu_555_g_p2_address0;
end else if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st10_fsm_10 == ap_CS_fsm))) begin
g1_p2_address0 = grp_computeGradient_fu_507_g_p2_address0;
end else if (((ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm))) begin
g1_p2_address0 = grp_computeResult_fu_467_g2_p2_address0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st126_fsm_126 == ap_CS_fsm))) begin
g1_p2_address0 = grp_computeResult_fu_467_g1_p2_address0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st128_fsm_128 == ap_CS_fsm))) begin
g1_p2_address0 = grp_computeResult_fu_467_g0_p2_address0;
end else begin
g1_p2_address0 = grp_computeUG_fu_555_g_p2_address0;
end
end
/// g1_p2_ce0 assign process. ///
always @ (ap_CS_fsm or grp_computeResult_fu_467_g0_p2_ce0 or grp_computeResult_fu_467_g1_p2_ce0 or grp_computeResult_fu_467_g2_p2_ce0 or grp_computeGradient_fu_507_g_p2_ce0 or grp_computeUG_fu_555_g_p2_ce0)
begin
if (((ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st12_fsm_12 == ap_CS_fsm))) begin
g1_p2_ce0 = grp_computeUG_fu_555_g_p2_ce0;
end else if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st10_fsm_10 == ap_CS_fsm))) begin
g1_p2_ce0 = grp_computeGradient_fu_507_g_p2_ce0;
end else if (((ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm))) begin
g1_p2_ce0 = grp_computeResult_fu_467_g2_p2_ce0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st126_fsm_126 == ap_CS_fsm))) begin
g1_p2_ce0 = grp_computeResult_fu_467_g1_p2_ce0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st128_fsm_128 == ap_CS_fsm))) begin
g1_p2_ce0 = grp_computeResult_fu_467_g0_p2_ce0;
end else begin
g1_p2_ce0 = ap_const_logic_0;
end
end
/// g1_p2_we0 assign process. ///
always @ (ap_CS_fsm or grp_computeGradient_fu_507_g_p2_we0)
begin
if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st10_fsm_10 == ap_CS_fsm))) begin
g1_p2_we0 = grp_computeGradient_fu_507_g_p2_we0;
end else begin
g1_p2_we0 = ap_const_logic_0;
end
end
/// g1_p3_address0 assign process. ///
always @ (ap_CS_fsm or grp_computeResult_fu_467_g0_p3_address0 or grp_computeResult_fu_467_g1_p3_address0 or grp_computeResult_fu_467_g2_p3_address0 or grp_computeGradient_fu_507_g_p3_address0 or grp_computeUG_fu_555_g_p3_address0)
begin
if (((ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st12_fsm_12 == ap_CS_fsm))) begin
g1_p3_address0 = grp_computeUG_fu_555_g_p3_address0;
end else if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st10_fsm_10 == ap_CS_fsm))) begin
g1_p3_address0 = grp_computeGradient_fu_507_g_p3_address0;
end else if (((ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm))) begin
g1_p3_address0 = grp_computeResult_fu_467_g2_p3_address0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st126_fsm_126 == ap_CS_fsm))) begin
g1_p3_address0 = grp_computeResult_fu_467_g1_p3_address0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st128_fsm_128 == ap_CS_fsm))) begin
g1_p3_address0 = grp_computeResult_fu_467_g0_p3_address0;
end else begin
g1_p3_address0 = grp_computeUG_fu_555_g_p3_address0;
end
end
/// g1_p3_ce0 assign process. ///
always @ (ap_CS_fsm or grp_computeResult_fu_467_g0_p3_ce0 or grp_computeResult_fu_467_g1_p3_ce0 or grp_computeResult_fu_467_g2_p3_ce0 or grp_computeGradient_fu_507_g_p3_ce0 or grp_computeUG_fu_555_g_p3_ce0)
begin
if (((ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st12_fsm_12 == ap_CS_fsm))) begin
g1_p3_ce0 = grp_computeUG_fu_555_g_p3_ce0;
end else if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st10_fsm_10 == ap_CS_fsm))) begin
g1_p3_ce0 = grp_computeGradient_fu_507_g_p3_ce0;
end else if (((ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm))) begin
g1_p3_ce0 = grp_computeResult_fu_467_g2_p3_ce0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st126_fsm_126 == ap_CS_fsm))) begin
g1_p3_ce0 = grp_computeResult_fu_467_g1_p3_ce0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st128_fsm_128 == ap_CS_fsm))) begin
g1_p3_ce0 = grp_computeResult_fu_467_g0_p3_ce0;
end else begin
g1_p3_ce0 = ap_const_logic_0;
end
end
/// g1_p3_ce1 assign process. ///
always @ (ap_CS_fsm or grp_computeResult_fu_467_g1_p3_ce1)
begin
if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st126_fsm_126 == ap_CS_fsm))) begin
g1_p3_ce1 = grp_computeResult_fu_467_g1_p3_ce1;
end else begin
g1_p3_ce1 = ap_const_logic_0;
end
end
/// g1_p3_we0 assign process. ///
always @ (ap_CS_fsm or grp_computeGradient_fu_507_g_p3_we0)
begin
if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st10_fsm_10 == ap_CS_fsm))) begin
g1_p3_we0 = grp_computeGradient_fu_507_g_p3_we0;
end else begin
g1_p3_we0 = ap_const_logic_0;
end
end
/// g2_p0_address0 assign process. ///
always @ (ap_CS_fsm or grp_computeResult_fu_467_g0_p0_address0 or grp_computeResult_fu_467_g1_p0_address0 or grp_computeResult_fu_467_g2_p0_address0 or grp_computeGradient_fu_507_g_p0_address0 or grp_computeUG_fu_555_g_p0_address0)
begin
if (((ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm) | (ap_ST_st14_fsm_14 == ap_CS_fsm))) begin
g2_p0_address0 = grp_computeUG_fu_555_g_p0_address0;
end else if (((ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st12_fsm_12 == ap_CS_fsm))) begin
g2_p0_address0 = grp_computeGradient_fu_507_g_p0_address0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st126_fsm_126 == ap_CS_fsm))) begin
g2_p0_address0 = grp_computeResult_fu_467_g2_p0_address0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st128_fsm_128 == ap_CS_fsm))) begin
g2_p0_address0 = grp_computeResult_fu_467_g1_p0_address0;
end else if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st130_fsm_130 == ap_CS_fsm))) begin
g2_p0_address0 = grp_computeResult_fu_467_g0_p0_address0;
end else begin
g2_p0_address0 = grp_computeUG_fu_555_g_p0_address0;
end
end
/// g2_p0_ce0 assign process. ///
always @ (ap_CS_fsm or grp_computeResult_fu_467_g0_p0_ce0 or grp_computeResult_fu_467_g1_p0_ce0 or grp_computeResult_fu_467_g2_p0_ce0 or grp_computeGradient_fu_507_g_p0_ce0 or grp_computeUG_fu_555_g_p0_ce0)
begin
if (((ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm) | (ap_ST_st14_fsm_14 == ap_CS_fsm))) begin
g2_p0_ce0 = grp_computeUG_fu_555_g_p0_ce0;
end else if (((ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st12_fsm_12 == ap_CS_fsm))) begin
g2_p0_ce0 = grp_computeGradient_fu_507_g_p0_ce0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st126_fsm_126 == ap_CS_fsm))) begin
g2_p0_ce0 = grp_computeResult_fu_467_g2_p0_ce0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st128_fsm_128 == ap_CS_fsm))) begin
g2_p0_ce0 = grp_computeResult_fu_467_g1_p0_ce0;
end else if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st130_fsm_130 == ap_CS_fsm))) begin
g2_p0_ce0 = grp_computeResult_fu_467_g0_p0_ce0;
end else begin
g2_p0_ce0 = ap_const_logic_0;
end
end
/// g2_p0_ce1 assign process. ///
always @ (ap_CS_fsm or grp_computeResult_fu_467_g1_p0_ce1)
begin
if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st128_fsm_128 == ap_CS_fsm))) begin
g2_p0_ce1 = grp_computeResult_fu_467_g1_p0_ce1;
end else begin
g2_p0_ce1 = ap_const_logic_0;
end
end
/// g2_p0_we0 assign process. ///
always @ (ap_CS_fsm or grp_computeGradient_fu_507_g_p0_we0)
begin
if (((ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st12_fsm_12 == ap_CS_fsm))) begin
g2_p0_we0 = grp_computeGradient_fu_507_g_p0_we0;
end else begin
g2_p0_we0 = ap_const_logic_0;
end
end
/// g2_p1_address0 assign process. ///
always @ (ap_CS_fsm or grp_computeResult_fu_467_g0_p1_address0 or grp_computeResult_fu_467_g1_p1_address0 or grp_computeResult_fu_467_g2_p1_address0 or grp_computeGradient_fu_507_g_p1_address0 or grp_computeUG_fu_555_g_p1_address0)
begin
if (((ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm) | (ap_ST_st14_fsm_14 == ap_CS_fsm))) begin
g2_p1_address0 = grp_computeUG_fu_555_g_p1_address0;
end else if (((ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st12_fsm_12 == ap_CS_fsm))) begin
g2_p1_address0 = grp_computeGradient_fu_507_g_p1_address0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st126_fsm_126 == ap_CS_fsm))) begin
g2_p1_address0 = grp_computeResult_fu_467_g2_p1_address0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st128_fsm_128 == ap_CS_fsm))) begin
g2_p1_address0 = grp_computeResult_fu_467_g1_p1_address0;
end else if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st130_fsm_130 == ap_CS_fsm))) begin
g2_p1_address0 = grp_computeResult_fu_467_g0_p1_address0;
end else begin
g2_p1_address0 = grp_computeUG_fu_555_g_p1_address0;
end
end
/// g2_p1_ce0 assign process. ///
always @ (ap_CS_fsm or grp_computeResult_fu_467_g0_p1_ce0 or grp_computeResult_fu_467_g1_p1_ce0 or grp_computeResult_fu_467_g2_p1_ce0 or grp_computeGradient_fu_507_g_p1_ce0 or grp_computeUG_fu_555_g_p1_ce0)
begin
if (((ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm) | (ap_ST_st14_fsm_14 == ap_CS_fsm))) begin
g2_p1_ce0 = grp_computeUG_fu_555_g_p1_ce0;
end else if (((ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st12_fsm_12 == ap_CS_fsm))) begin
g2_p1_ce0 = grp_computeGradient_fu_507_g_p1_ce0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st126_fsm_126 == ap_CS_fsm))) begin
g2_p1_ce0 = grp_computeResult_fu_467_g2_p1_ce0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st128_fsm_128 == ap_CS_fsm))) begin
g2_p1_ce0 = grp_computeResult_fu_467_g1_p1_ce0;
end else if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st130_fsm_130 == ap_CS_fsm))) begin
g2_p1_ce0 = grp_computeResult_fu_467_g0_p1_ce0;
end else begin
g2_p1_ce0 = ap_const_logic_0;
end
end
/// g2_p1_we0 assign process. ///
always @ (ap_CS_fsm or grp_computeGradient_fu_507_g_p1_we0)
begin
if (((ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st12_fsm_12 == ap_CS_fsm))) begin
g2_p1_we0 = grp_computeGradient_fu_507_g_p1_we0;
end else begin
g2_p1_we0 = ap_const_logic_0;
end
end
/// g2_p2_address0 assign process. ///
always @ (ap_CS_fsm or grp_computeResult_fu_467_g0_p2_address0 or grp_computeResult_fu_467_g1_p2_address0 or grp_computeResult_fu_467_g2_p2_address0 or grp_computeGradient_fu_507_g_p2_address0 or grp_computeUG_fu_555_g_p2_address0)
begin
if (((ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm) | (ap_ST_st14_fsm_14 == ap_CS_fsm))) begin
g2_p2_address0 = grp_computeUG_fu_555_g_p2_address0;
end else if (((ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st12_fsm_12 == ap_CS_fsm))) begin
g2_p2_address0 = grp_computeGradient_fu_507_g_p2_address0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st126_fsm_126 == ap_CS_fsm))) begin
g2_p2_address0 = grp_computeResult_fu_467_g2_p2_address0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st128_fsm_128 == ap_CS_fsm))) begin
g2_p2_address0 = grp_computeResult_fu_467_g1_p2_address0;
end else if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st130_fsm_130 == ap_CS_fsm))) begin
g2_p2_address0 = grp_computeResult_fu_467_g0_p2_address0;
end else begin
g2_p2_address0 = grp_computeUG_fu_555_g_p2_address0;
end
end
/// g2_p2_ce0 assign process. ///
always @ (ap_CS_fsm or grp_computeResult_fu_467_g0_p2_ce0 or grp_computeResult_fu_467_g1_p2_ce0 or grp_computeResult_fu_467_g2_p2_ce0 or grp_computeGradient_fu_507_g_p2_ce0 or grp_computeUG_fu_555_g_p2_ce0)
begin
if (((ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm) | (ap_ST_st14_fsm_14 == ap_CS_fsm))) begin
g2_p2_ce0 = grp_computeUG_fu_555_g_p2_ce0;
end else if (((ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st12_fsm_12 == ap_CS_fsm))) begin
g2_p2_ce0 = grp_computeGradient_fu_507_g_p2_ce0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st126_fsm_126 == ap_CS_fsm))) begin
g2_p2_ce0 = grp_computeResult_fu_467_g2_p2_ce0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st128_fsm_128 == ap_CS_fsm))) begin
g2_p2_ce0 = grp_computeResult_fu_467_g1_p2_ce0;
end else if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st130_fsm_130 == ap_CS_fsm))) begin
g2_p2_ce0 = grp_computeResult_fu_467_g0_p2_ce0;
end else begin
g2_p2_ce0 = ap_const_logic_0;
end
end
/// g2_p2_we0 assign process. ///
always @ (ap_CS_fsm or grp_computeGradient_fu_507_g_p2_we0)
begin
if (((ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st12_fsm_12 == ap_CS_fsm))) begin
g2_p2_we0 = grp_computeGradient_fu_507_g_p2_we0;
end else begin
g2_p2_we0 = ap_const_logic_0;
end
end
/// g2_p3_address0 assign process. ///
always @ (ap_CS_fsm or grp_computeResult_fu_467_g0_p3_address0 or grp_computeResult_fu_467_g1_p3_address0 or grp_computeResult_fu_467_g2_p3_address0 or grp_computeGradient_fu_507_g_p3_address0 or grp_computeUG_fu_555_g_p3_address0)
begin
if (((ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm) | (ap_ST_st14_fsm_14 == ap_CS_fsm))) begin
g2_p3_address0 = grp_computeUG_fu_555_g_p3_address0;
end else if (((ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st12_fsm_12 == ap_CS_fsm))) begin
g2_p3_address0 = grp_computeGradient_fu_507_g_p3_address0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st126_fsm_126 == ap_CS_fsm))) begin
g2_p3_address0 = grp_computeResult_fu_467_g2_p3_address0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st128_fsm_128 == ap_CS_fsm))) begin
g2_p3_address0 = grp_computeResult_fu_467_g1_p3_address0;
end else if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st130_fsm_130 == ap_CS_fsm))) begin
g2_p3_address0 = grp_computeResult_fu_467_g0_p3_address0;
end else begin
g2_p3_address0 = grp_computeUG_fu_555_g_p3_address0;
end
end
/// g2_p3_ce0 assign process. ///
always @ (ap_CS_fsm or grp_computeResult_fu_467_g0_p3_ce0 or grp_computeResult_fu_467_g1_p3_ce0 or grp_computeResult_fu_467_g2_p3_ce0 or grp_computeGradient_fu_507_g_p3_ce0 or grp_computeUG_fu_555_g_p3_ce0)
begin
if (((ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm) | (ap_ST_st14_fsm_14 == ap_CS_fsm))) begin
g2_p3_ce0 = grp_computeUG_fu_555_g_p3_ce0;
end else if (((ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st12_fsm_12 == ap_CS_fsm))) begin
g2_p3_ce0 = grp_computeGradient_fu_507_g_p3_ce0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st126_fsm_126 == ap_CS_fsm))) begin
g2_p3_ce0 = grp_computeResult_fu_467_g2_p3_ce0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st128_fsm_128 == ap_CS_fsm))) begin
g2_p3_ce0 = grp_computeResult_fu_467_g1_p3_ce0;
end else if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st130_fsm_130 == ap_CS_fsm))) begin
g2_p3_ce0 = grp_computeResult_fu_467_g0_p3_ce0;
end else begin
g2_p3_ce0 = ap_const_logic_0;
end
end
/// g2_p3_ce1 assign process. ///
always @ (ap_CS_fsm or grp_computeResult_fu_467_g1_p3_ce1)
begin
if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st128_fsm_128 == ap_CS_fsm))) begin
g2_p3_ce1 = grp_computeResult_fu_467_g1_p3_ce1;
end else begin
g2_p3_ce1 = ap_const_logic_0;
end
end
/// g2_p3_we0 assign process. ///
always @ (ap_CS_fsm or grp_computeGradient_fu_507_g_p3_we0)
begin
if (((ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st12_fsm_12 == ap_CS_fsm))) begin
g2_p3_we0 = grp_computeGradient_fu_507_g_p3_we0;
end else begin
g2_p3_we0 = ap_const_logic_0;
end
end
/// g3_p0_address0 assign process. ///
always @ (ap_CS_fsm or grp_computeResult_fu_467_g0_p0_address0 or grp_computeResult_fu_467_g1_p0_address0 or grp_computeResult_fu_467_g2_p0_address0 or grp_computeGradient_fu_507_g_p0_address0 or grp_computeUG_fu_555_g_p0_address0)
begin
if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st126_fsm_126 == ap_CS_fsm))) begin
g3_p0_address0 = grp_computeUG_fu_555_g_p0_address0;
end else if (((ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm) | (ap_ST_st14_fsm_14 == ap_CS_fsm))) begin
g3_p0_address0 = grp_computeGradient_fu_507_g_p0_address0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st128_fsm_128 == ap_CS_fsm))) begin
g3_p0_address0 = grp_computeResult_fu_467_g2_p0_address0;
end else if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st130_fsm_130 == ap_CS_fsm))) begin
g3_p0_address0 = grp_computeResult_fu_467_g1_p0_address0;
end else if (((ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm))) begin
g3_p0_address0 = grp_computeResult_fu_467_g0_p0_address0;
end else begin
g3_p0_address0 = grp_computeUG_fu_555_g_p0_address0;
end
end
/// g3_p0_ce0 assign process. ///
always @ (ap_CS_fsm or grp_computeResult_fu_467_g0_p0_ce0 or grp_computeResult_fu_467_g1_p0_ce0 or grp_computeResult_fu_467_g2_p0_ce0 or grp_computeGradient_fu_507_g_p0_ce0 or grp_computeUG_fu_555_g_p0_ce0)
begin
if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st126_fsm_126 == ap_CS_fsm))) begin
g3_p0_ce0 = grp_computeUG_fu_555_g_p0_ce0;
end else if (((ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm) | (ap_ST_st14_fsm_14 == ap_CS_fsm))) begin
g3_p0_ce0 = grp_computeGradient_fu_507_g_p0_ce0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st128_fsm_128 == ap_CS_fsm))) begin
g3_p0_ce0 = grp_computeResult_fu_467_g2_p0_ce0;
end else if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st130_fsm_130 == ap_CS_fsm))) begin
g3_p0_ce0 = grp_computeResult_fu_467_g1_p0_ce0;
end else if (((ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm))) begin
g3_p0_ce0 = grp_computeResult_fu_467_g0_p0_ce0;
end else begin
g3_p0_ce0 = ap_const_logic_0;
end
end
/// g3_p0_ce1 assign process. ///
always @ (ap_CS_fsm or grp_computeResult_fu_467_g1_p0_ce1)
begin
if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st130_fsm_130 == ap_CS_fsm))) begin
g3_p0_ce1 = grp_computeResult_fu_467_g1_p0_ce1;
end else begin
g3_p0_ce1 = ap_const_logic_0;
end
end
/// g3_p0_we0 assign process. ///
always @ (ap_CS_fsm or grp_computeGradient_fu_507_g_p0_we0)
begin
if (((ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm) | (ap_ST_st14_fsm_14 == ap_CS_fsm))) begin
g3_p0_we0 = grp_computeGradient_fu_507_g_p0_we0;
end else begin
g3_p0_we0 = ap_const_logic_0;
end
end
/// g3_p1_address0 assign process. ///
always @ (ap_CS_fsm or grp_computeResult_fu_467_g0_p1_address0 or grp_computeResult_fu_467_g1_p1_address0 or grp_computeResult_fu_467_g2_p1_address0 or grp_computeGradient_fu_507_g_p1_address0 or grp_computeUG_fu_555_g_p1_address0)
begin
if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st126_fsm_126 == ap_CS_fsm))) begin
g3_p1_address0 = grp_computeUG_fu_555_g_p1_address0;
end else if (((ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm) | (ap_ST_st14_fsm_14 == ap_CS_fsm))) begin
g3_p1_address0 = grp_computeGradient_fu_507_g_p1_address0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st128_fsm_128 == ap_CS_fsm))) begin
g3_p1_address0 = grp_computeResult_fu_467_g2_p1_address0;
end else if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st130_fsm_130 == ap_CS_fsm))) begin
g3_p1_address0 = grp_computeResult_fu_467_g1_p1_address0;
end else if (((ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm))) begin
g3_p1_address0 = grp_computeResult_fu_467_g0_p1_address0;
end else begin
g3_p1_address0 = grp_computeUG_fu_555_g_p1_address0;
end
end
/// g3_p1_ce0 assign process. ///
always @ (ap_CS_fsm or grp_computeResult_fu_467_g0_p1_ce0 or grp_computeResult_fu_467_g1_p1_ce0 or grp_computeResult_fu_467_g2_p1_ce0 or grp_computeGradient_fu_507_g_p1_ce0 or grp_computeUG_fu_555_g_p1_ce0)
begin
if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st126_fsm_126 == ap_CS_fsm))) begin
g3_p1_ce0 = grp_computeUG_fu_555_g_p1_ce0;
end else if (((ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm) | (ap_ST_st14_fsm_14 == ap_CS_fsm))) begin
g3_p1_ce0 = grp_computeGradient_fu_507_g_p1_ce0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st128_fsm_128 == ap_CS_fsm))) begin
g3_p1_ce0 = grp_computeResult_fu_467_g2_p1_ce0;
end else if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st130_fsm_130 == ap_CS_fsm))) begin
g3_p1_ce0 = grp_computeResult_fu_467_g1_p1_ce0;
end else if (((ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm))) begin
g3_p1_ce0 = grp_computeResult_fu_467_g0_p1_ce0;
end else begin
g3_p1_ce0 = ap_const_logic_0;
end
end
/// g3_p1_we0 assign process. ///
always @ (ap_CS_fsm or grp_computeGradient_fu_507_g_p1_we0)
begin
if (((ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm) | (ap_ST_st14_fsm_14 == ap_CS_fsm))) begin
g3_p1_we0 = grp_computeGradient_fu_507_g_p1_we0;
end else begin
g3_p1_we0 = ap_const_logic_0;
end
end
/// g3_p2_address0 assign process. ///
always @ (ap_CS_fsm or grp_computeResult_fu_467_g0_p2_address0 or grp_computeResult_fu_467_g1_p2_address0 or grp_computeResult_fu_467_g2_p2_address0 or grp_computeGradient_fu_507_g_p2_address0 or grp_computeUG_fu_555_g_p2_address0)
begin
if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st126_fsm_126 == ap_CS_fsm))) begin
g3_p2_address0 = grp_computeUG_fu_555_g_p2_address0;
end else if (((ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm) | (ap_ST_st14_fsm_14 == ap_CS_fsm))) begin
g3_p2_address0 = grp_computeGradient_fu_507_g_p2_address0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st128_fsm_128 == ap_CS_fsm))) begin
g3_p2_address0 = grp_computeResult_fu_467_g2_p2_address0;
end else if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st130_fsm_130 == ap_CS_fsm))) begin
g3_p2_address0 = grp_computeResult_fu_467_g1_p2_address0;
end else if (((ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm))) begin
g3_p2_address0 = grp_computeResult_fu_467_g0_p2_address0;
end else begin
g3_p2_address0 = grp_computeUG_fu_555_g_p2_address0;
end
end
/// g3_p2_ce0 assign process. ///
always @ (ap_CS_fsm or grp_computeResult_fu_467_g0_p2_ce0 or grp_computeResult_fu_467_g1_p2_ce0 or grp_computeResult_fu_467_g2_p2_ce0 or grp_computeGradient_fu_507_g_p2_ce0 or grp_computeUG_fu_555_g_p2_ce0)
begin
if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st126_fsm_126 == ap_CS_fsm))) begin
g3_p2_ce0 = grp_computeUG_fu_555_g_p2_ce0;
end else if (((ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm) | (ap_ST_st14_fsm_14 == ap_CS_fsm))) begin
g3_p2_ce0 = grp_computeGradient_fu_507_g_p2_ce0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st128_fsm_128 == ap_CS_fsm))) begin
g3_p2_ce0 = grp_computeResult_fu_467_g2_p2_ce0;
end else if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st130_fsm_130 == ap_CS_fsm))) begin
g3_p2_ce0 = grp_computeResult_fu_467_g1_p2_ce0;
end else if (((ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm))) begin
g3_p2_ce0 = grp_computeResult_fu_467_g0_p2_ce0;
end else begin
g3_p2_ce0 = ap_const_logic_0;
end
end
/// g3_p2_we0 assign process. ///
always @ (ap_CS_fsm or grp_computeGradient_fu_507_g_p2_we0)
begin
if (((ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm) | (ap_ST_st14_fsm_14 == ap_CS_fsm))) begin
g3_p2_we0 = grp_computeGradient_fu_507_g_p2_we0;
end else begin
g3_p2_we0 = ap_const_logic_0;
end
end
/// g3_p3_address0 assign process. ///
always @ (ap_CS_fsm or grp_computeResult_fu_467_g0_p3_address0 or grp_computeResult_fu_467_g1_p3_address0 or grp_computeResult_fu_467_g2_p3_address0 or grp_computeGradient_fu_507_g_p3_address0 or grp_computeUG_fu_555_g_p3_address0)
begin
if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st126_fsm_126 == ap_CS_fsm))) begin
g3_p3_address0 = grp_computeUG_fu_555_g_p3_address0;
end else if (((ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm) | (ap_ST_st14_fsm_14 == ap_CS_fsm))) begin
g3_p3_address0 = grp_computeGradient_fu_507_g_p3_address0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st128_fsm_128 == ap_CS_fsm))) begin
g3_p3_address0 = grp_computeResult_fu_467_g2_p3_address0;
end else if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st130_fsm_130 == ap_CS_fsm))) begin
g3_p3_address0 = grp_computeResult_fu_467_g1_p3_address0;
end else if (((ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm))) begin
g3_p3_address0 = grp_computeResult_fu_467_g0_p3_address0;
end else begin
g3_p3_address0 = grp_computeUG_fu_555_g_p3_address0;
end
end
/// g3_p3_ce0 assign process. ///
always @ (ap_CS_fsm or grp_computeResult_fu_467_g0_p3_ce0 or grp_computeResult_fu_467_g1_p3_ce0 or grp_computeResult_fu_467_g2_p3_ce0 or grp_computeGradient_fu_507_g_p3_ce0 or grp_computeUG_fu_555_g_p3_ce0)
begin
if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st126_fsm_126 == ap_CS_fsm))) begin
g3_p3_ce0 = grp_computeUG_fu_555_g_p3_ce0;
end else if (((ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm) | (ap_ST_st14_fsm_14 == ap_CS_fsm))) begin
g3_p3_ce0 = grp_computeGradient_fu_507_g_p3_ce0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st128_fsm_128 == ap_CS_fsm))) begin
g3_p3_ce0 = grp_computeResult_fu_467_g2_p3_ce0;
end else if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st130_fsm_130 == ap_CS_fsm))) begin
g3_p3_ce0 = grp_computeResult_fu_467_g1_p3_ce0;
end else if (((ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm))) begin
g3_p3_ce0 = grp_computeResult_fu_467_g0_p3_ce0;
end else begin
g3_p3_ce0 = ap_const_logic_0;
end
end
/// g3_p3_ce1 assign process. ///
always @ (ap_CS_fsm or grp_computeResult_fu_467_g1_p3_ce1)
begin
if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st130_fsm_130 == ap_CS_fsm))) begin
g3_p3_ce1 = grp_computeResult_fu_467_g1_p3_ce1;
end else begin
g3_p3_ce1 = ap_const_logic_0;
end
end
/// g3_p3_we0 assign process. ///
always @ (ap_CS_fsm or grp_computeGradient_fu_507_g_p3_we0)
begin
if (((ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm) | (ap_ST_st14_fsm_14 == ap_CS_fsm))) begin
g3_p3_we0 = grp_computeGradient_fu_507_g_p3_we0;
end else begin
g3_p3_we0 = ap_const_logic_0;
end
end
/// g4_p0_address0 assign process. ///
always @ (ap_CS_fsm or grp_computeResult_fu_467_g0_p0_address0 or grp_computeResult_fu_467_g1_p0_address0 or grp_computeResult_fu_467_g2_p0_address0 or grp_computeGradient_fu_507_g_p0_address0 or grp_computeUG_fu_555_g_p0_address0)
begin
if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st128_fsm_128 == ap_CS_fsm))) begin
g4_p0_address0 = grp_computeUG_fu_555_g_p0_address0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm))) begin
g4_p0_address0 = grp_computeGradient_fu_507_g_p0_address0;
end else if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st130_fsm_130 == ap_CS_fsm))) begin
g4_p0_address0 = grp_computeResult_fu_467_g2_p0_address0;
end else if (((ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm))) begin
g4_p0_address0 = grp_computeResult_fu_467_g1_p0_address0;
end else if (((ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm))) begin
g4_p0_address0 = grp_computeResult_fu_467_g0_p0_address0;
end else begin
g4_p0_address0 = grp_computeUG_fu_555_g_p0_address0;
end
end
/// g4_p0_ce0 assign process. ///
always @ (ap_CS_fsm or grp_computeResult_fu_467_g0_p0_ce0 or grp_computeResult_fu_467_g1_p0_ce0 or grp_computeResult_fu_467_g2_p0_ce0 or grp_computeGradient_fu_507_g_p0_ce0 or grp_computeUG_fu_555_g_p0_ce0)
begin
if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st128_fsm_128 == ap_CS_fsm))) begin
g4_p0_ce0 = grp_computeUG_fu_555_g_p0_ce0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm))) begin
g4_p0_ce0 = grp_computeGradient_fu_507_g_p0_ce0;
end else if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st130_fsm_130 == ap_CS_fsm))) begin
g4_p0_ce0 = grp_computeResult_fu_467_g2_p0_ce0;
end else if (((ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm))) begin
g4_p0_ce0 = grp_computeResult_fu_467_g1_p0_ce0;
end else if (((ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm))) begin
g4_p0_ce0 = grp_computeResult_fu_467_g0_p0_ce0;
end else begin
g4_p0_ce0 = ap_const_logic_0;
end
end
/// g4_p0_ce1 assign process. ///
always @ (ap_CS_fsm or grp_computeResult_fu_467_g1_p0_ce1)
begin
if (((ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm))) begin
g4_p0_ce1 = grp_computeResult_fu_467_g1_p0_ce1;
end else begin
g4_p0_ce1 = ap_const_logic_0;
end
end
/// g4_p0_we0 assign process. ///
always @ (ap_CS_fsm or grp_computeGradient_fu_507_g_p0_we0)
begin
if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm))) begin
g4_p0_we0 = grp_computeGradient_fu_507_g_p0_we0;
end else begin
g4_p0_we0 = ap_const_logic_0;
end
end
/// g4_p1_address0 assign process. ///
always @ (ap_CS_fsm or grp_computeResult_fu_467_g0_p1_address0 or grp_computeResult_fu_467_g1_p1_address0 or grp_computeResult_fu_467_g2_p1_address0 or grp_computeGradient_fu_507_g_p1_address0 or grp_computeUG_fu_555_g_p1_address0)
begin
if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st128_fsm_128 == ap_CS_fsm))) begin
g4_p1_address0 = grp_computeUG_fu_555_g_p1_address0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm))) begin
g4_p1_address0 = grp_computeGradient_fu_507_g_p1_address0;
end else if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st130_fsm_130 == ap_CS_fsm))) begin
g4_p1_address0 = grp_computeResult_fu_467_g2_p1_address0;
end else if (((ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm))) begin
g4_p1_address0 = grp_computeResult_fu_467_g1_p1_address0;
end else if (((ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm))) begin
g4_p1_address0 = grp_computeResult_fu_467_g0_p1_address0;
end else begin
g4_p1_address0 = grp_computeUG_fu_555_g_p1_address0;
end
end
/// g4_p1_ce0 assign process. ///
always @ (ap_CS_fsm or grp_computeResult_fu_467_g0_p1_ce0 or grp_computeResult_fu_467_g1_p1_ce0 or grp_computeResult_fu_467_g2_p1_ce0 or grp_computeGradient_fu_507_g_p1_ce0 or grp_computeUG_fu_555_g_p1_ce0)
begin
if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st128_fsm_128 == ap_CS_fsm))) begin
g4_p1_ce0 = grp_computeUG_fu_555_g_p1_ce0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm))) begin
g4_p1_ce0 = grp_computeGradient_fu_507_g_p1_ce0;
end else if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st130_fsm_130 == ap_CS_fsm))) begin
g4_p1_ce0 = grp_computeResult_fu_467_g2_p1_ce0;
end else if (((ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm))) begin
g4_p1_ce0 = grp_computeResult_fu_467_g1_p1_ce0;
end else if (((ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm))) begin
g4_p1_ce0 = grp_computeResult_fu_467_g0_p1_ce0;
end else begin
g4_p1_ce0 = ap_const_logic_0;
end
end
/// g4_p1_we0 assign process. ///
always @ (ap_CS_fsm or grp_computeGradient_fu_507_g_p1_we0)
begin
if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm))) begin
g4_p1_we0 = grp_computeGradient_fu_507_g_p1_we0;
end else begin
g4_p1_we0 = ap_const_logic_0;
end
end
/// g4_p2_address0 assign process. ///
always @ (ap_CS_fsm or grp_computeResult_fu_467_g0_p2_address0 or grp_computeResult_fu_467_g1_p2_address0 or grp_computeResult_fu_467_g2_p2_address0 or grp_computeGradient_fu_507_g_p2_address0 or grp_computeUG_fu_555_g_p2_address0)
begin
if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st128_fsm_128 == ap_CS_fsm))) begin
g4_p2_address0 = grp_computeUG_fu_555_g_p2_address0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm))) begin
g4_p2_address0 = grp_computeGradient_fu_507_g_p2_address0;
end else if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st130_fsm_130 == ap_CS_fsm))) begin
g4_p2_address0 = grp_computeResult_fu_467_g2_p2_address0;
end else if (((ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm))) begin
g4_p2_address0 = grp_computeResult_fu_467_g1_p2_address0;
end else if (((ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm))) begin
g4_p2_address0 = grp_computeResult_fu_467_g0_p2_address0;
end else begin
g4_p2_address0 = grp_computeUG_fu_555_g_p2_address0;
end
end
/// g4_p2_ce0 assign process. ///
always @ (ap_CS_fsm or grp_computeResult_fu_467_g0_p2_ce0 or grp_computeResult_fu_467_g1_p2_ce0 or grp_computeResult_fu_467_g2_p2_ce0 or grp_computeGradient_fu_507_g_p2_ce0 or grp_computeUG_fu_555_g_p2_ce0)
begin
if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st128_fsm_128 == ap_CS_fsm))) begin
g4_p2_ce0 = grp_computeUG_fu_555_g_p2_ce0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm))) begin
g4_p2_ce0 = grp_computeGradient_fu_507_g_p2_ce0;
end else if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st130_fsm_130 == ap_CS_fsm))) begin
g4_p2_ce0 = grp_computeResult_fu_467_g2_p2_ce0;
end else if (((ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm))) begin
g4_p2_ce0 = grp_computeResult_fu_467_g1_p2_ce0;
end else if (((ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm))) begin
g4_p2_ce0 = grp_computeResult_fu_467_g0_p2_ce0;
end else begin
g4_p2_ce0 = ap_const_logic_0;
end
end
/// g4_p2_we0 assign process. ///
always @ (ap_CS_fsm or grp_computeGradient_fu_507_g_p2_we0)
begin
if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm))) begin
g4_p2_we0 = grp_computeGradient_fu_507_g_p2_we0;
end else begin
g4_p2_we0 = ap_const_logic_0;
end
end
/// g4_p3_address0 assign process. ///
always @ (ap_CS_fsm or grp_computeResult_fu_467_g0_p3_address0 or grp_computeResult_fu_467_g1_p3_address0 or grp_computeResult_fu_467_g2_p3_address0 or grp_computeGradient_fu_507_g_p3_address0 or grp_computeUG_fu_555_g_p3_address0)
begin
if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st128_fsm_128 == ap_CS_fsm))) begin
g4_p3_address0 = grp_computeUG_fu_555_g_p3_address0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm))) begin
g4_p3_address0 = grp_computeGradient_fu_507_g_p3_address0;
end else if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st130_fsm_130 == ap_CS_fsm))) begin
g4_p3_address0 = grp_computeResult_fu_467_g2_p3_address0;
end else if (((ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm))) begin
g4_p3_address0 = grp_computeResult_fu_467_g1_p3_address0;
end else if (((ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm))) begin
g4_p3_address0 = grp_computeResult_fu_467_g0_p3_address0;
end else begin
g4_p3_address0 = grp_computeUG_fu_555_g_p3_address0;
end
end
/// g4_p3_ce0 assign process. ///
always @ (ap_CS_fsm or grp_computeResult_fu_467_g0_p3_ce0 or grp_computeResult_fu_467_g1_p3_ce0 or grp_computeResult_fu_467_g2_p3_ce0 or grp_computeGradient_fu_507_g_p3_ce0 or grp_computeUG_fu_555_g_p3_ce0)
begin
if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st128_fsm_128 == ap_CS_fsm))) begin
g4_p3_ce0 = grp_computeUG_fu_555_g_p3_ce0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm))) begin
g4_p3_ce0 = grp_computeGradient_fu_507_g_p3_ce0;
end else if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st130_fsm_130 == ap_CS_fsm))) begin
g4_p3_ce0 = grp_computeResult_fu_467_g2_p3_ce0;
end else if (((ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm))) begin
g4_p3_ce0 = grp_computeResult_fu_467_g1_p3_ce0;
end else if (((ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm))) begin
g4_p3_ce0 = grp_computeResult_fu_467_g0_p3_ce0;
end else begin
g4_p3_ce0 = ap_const_logic_0;
end
end
/// g4_p3_ce1 assign process. ///
always @ (ap_CS_fsm or grp_computeResult_fu_467_g1_p3_ce1)
begin
if (((ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm))) begin
g4_p3_ce1 = grp_computeResult_fu_467_g1_p3_ce1;
end else begin
g4_p3_ce1 = ap_const_logic_0;
end
end
/// g4_p3_we0 assign process. ///
always @ (ap_CS_fsm or grp_computeGradient_fu_507_g_p3_we0)
begin
if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm))) begin
g4_p3_we0 = grp_computeGradient_fu_507_g_p3_we0;
end else begin
g4_p3_we0 = ap_const_logic_0;
end
end
/// grp_computeDiffSqr_fu_531_ap_start assign process. ///
always @ (ap_CS_fsm)
begin
if (((ap_ST_st15_fsm_15 == ap_CS_fsm) | (ap_ST_st17_fsm_17 == ap_CS_fsm) | (ap_ST_st19_fsm_19 == ap_CS_fsm) | (ap_ST_st21_fsm_21 == ap_CS_fsm) | (ap_ST_st23_fsm_23 == ap_CS_fsm) | (ap_ST_st25_fsm_25 == ap_CS_fsm) | (ap_ST_st27_fsm_27 == ap_CS_fsm) | (ap_ST_st29_fsm_29 == ap_CS_fsm) | (ap_ST_st31_fsm_31 == ap_CS_fsm) | (ap_ST_st33_fsm_33 == ap_CS_fsm) | (ap_ST_st35_fsm_35 == ap_CS_fsm) | (ap_ST_st37_fsm_37 == ap_CS_fsm) | (ap_ST_st39_fsm_39 == ap_CS_fsm) | (ap_ST_st41_fsm_41 == ap_CS_fsm) | (ap_ST_st43_fsm_43 == ap_CS_fsm) | (ap_ST_st45_fsm_45 == ap_CS_fsm) | (ap_ST_st47_fsm_47 == ap_CS_fsm) | (ap_ST_st49_fsm_49 == ap_CS_fsm) | (ap_ST_st51_fsm_51 == ap_CS_fsm) | (ap_ST_st53_fsm_53 == ap_CS_fsm) | (ap_ST_st55_fsm_55 == ap_CS_fsm) | (ap_ST_st57_fsm_57 == ap_CS_fsm) | (ap_ST_st59_fsm_59 == ap_CS_fsm) | (ap_ST_st61_fsm_61 == ap_CS_fsm) | (ap_ST_st63_fsm_63 == ap_CS_fsm) | (ap_ST_st65_fsm_65 == ap_CS_fsm) | (ap_ST_st67_fsm_67 == ap_CS_fsm) | (ap_ST_st69_fsm_69 == ap_CS_fsm) | (ap_ST_st71_fsm_71 == ap_CS_fsm) | (ap_ST_st73_fsm_73 == ap_CS_fsm) | (ap_ST_st75_fsm_75 == ap_CS_fsm) | (ap_ST_st77_fsm_77 == ap_CS_fsm) | (ap_ST_st79_fsm_79 == ap_CS_fsm) | (ap_ST_st81_fsm_81 == ap_CS_fsm) | (ap_ST_st83_fsm_83 == ap_CS_fsm) | (ap_ST_st85_fsm_85 == ap_CS_fsm) | (ap_ST_st87_fsm_87 == ap_CS_fsm) | (ap_ST_st89_fsm_89 == ap_CS_fsm) | (ap_ST_st91_fsm_91 == ap_CS_fsm) | (ap_ST_st93_fsm_93 == ap_CS_fsm) | (ap_ST_st95_fsm_95 == ap_CS_fsm) | (ap_ST_st97_fsm_97 == ap_CS_fsm) | (ap_ST_st99_fsm_99 == ap_CS_fsm) | (ap_ST_st101_fsm_101 == ap_CS_fsm) | (ap_ST_st103_fsm_103 == ap_CS_fsm) | (ap_ST_st105_fsm_105 == ap_CS_fsm) | (ap_ST_st107_fsm_107 == ap_CS_fsm) | (ap_ST_st109_fsm_109 == ap_CS_fsm) | (ap_ST_st111_fsm_111 == ap_CS_fsm) | (ap_ST_st113_fsm_113 == ap_CS_fsm) | (ap_ST_st115_fsm_115 == ap_CS_fsm) | (ap_ST_st117_fsm_117 == ap_CS_fsm) | (ap_ST_st119_fsm_119 == ap_CS_fsm) | (ap_ST_st121_fsm_121 == ap_CS_fsm) | (ap_ST_st9_fsm_9 == ap_CS_fsm) | (ap_ST_st11_fsm_11 == ap_CS_fsm) | (ap_ST_st13_fsm_13 == ap_CS_fsm) | (ap_ST_st5_fsm_5 == ap_CS_fsm) | (ap_ST_st7_fsm_7 == ap_CS_fsm))) begin
grp_computeDiffSqr_fu_531_ap_start = ap_const_logic_1;
end else begin
grp_computeDiffSqr_fu_531_ap_start = ap_const_logic_0;
end
end
/// grp_computeDiffSqr_fu_531_u0_p0_q0 assign process. ///
always @ (ap_CS_fsm or u6_p0_q0 or u5_p0_q0 or u4_p0_q0 or u3_p0_q0 or u2_p0_q0 or u1_p0_q0 or u0_p0_q0)
begin
if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm))) begin
grp_computeDiffSqr_fu_531_u0_p0_q0 = u6_p0_q0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm))) begin
grp_computeDiffSqr_fu_531_u0_p0_q0 = u5_p0_q0;
end else if (((ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st14_fsm_14 == ap_CS_fsm))) begin
grp_computeDiffSqr_fu_531_u0_p0_q0 = u4_p0_q0;
end else if (((ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st12_fsm_12 == ap_CS_fsm))) begin
grp_computeDiffSqr_fu_531_u0_p0_q0 = u3_p0_q0;
end else if (((ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st10_fsm_10 == ap_CS_fsm))) begin
grp_computeDiffSqr_fu_531_u0_p0_q0 = u2_p0_q0;
end else if (((ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st8_fsm_8 == ap_CS_fsm))) begin
grp_computeDiffSqr_fu_531_u0_p0_q0 = u1_p0_q0;
end else if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st6_fsm_6 == ap_CS_fsm))) begin
grp_computeDiffSqr_fu_531_u0_p0_q0 = u0_p0_q0;
end else begin
grp_computeDiffSqr_fu_531_u0_p0_q0 = u0_p0_q0;
end
end
/// grp_computeDiffSqr_fu_531_u0_p1_q0 assign process. ///
always @ (ap_CS_fsm or u6_p1_q0 or u5_p1_q0 or u4_p1_q0 or u3_p1_q0 or u2_p1_q0 or u1_p1_q0 or u0_p1_q0)
begin
if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm))) begin
grp_computeDiffSqr_fu_531_u0_p1_q0 = u6_p1_q0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm))) begin
grp_computeDiffSqr_fu_531_u0_p1_q0 = u5_p1_q0;
end else if (((ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st14_fsm_14 == ap_CS_fsm))) begin
grp_computeDiffSqr_fu_531_u0_p1_q0 = u4_p1_q0;
end else if (((ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st12_fsm_12 == ap_CS_fsm))) begin
grp_computeDiffSqr_fu_531_u0_p1_q0 = u3_p1_q0;
end else if (((ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st10_fsm_10 == ap_CS_fsm))) begin
grp_computeDiffSqr_fu_531_u0_p1_q0 = u2_p1_q0;
end else if (((ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st8_fsm_8 == ap_CS_fsm))) begin
grp_computeDiffSqr_fu_531_u0_p1_q0 = u1_p1_q0;
end else if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st6_fsm_6 == ap_CS_fsm))) begin
grp_computeDiffSqr_fu_531_u0_p1_q0 = u0_p1_q0;
end else begin
grp_computeDiffSqr_fu_531_u0_p1_q0 = u0_p1_q0;
end
end
/// grp_computeDiffSqr_fu_531_u0_p2_q0 assign process. ///
always @ (ap_CS_fsm or u6_p2_q0 or u5_p2_q0 or u4_p2_q0 or u3_p2_q0 or u2_p2_q0 or u1_p2_q0 or u0_p2_q0)
begin
if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm))) begin
grp_computeDiffSqr_fu_531_u0_p2_q0 = u6_p2_q0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm))) begin
grp_computeDiffSqr_fu_531_u0_p2_q0 = u5_p2_q0;
end else if (((ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st14_fsm_14 == ap_CS_fsm))) begin
grp_computeDiffSqr_fu_531_u0_p2_q0 = u4_p2_q0;
end else if (((ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st12_fsm_12 == ap_CS_fsm))) begin
grp_computeDiffSqr_fu_531_u0_p2_q0 = u3_p2_q0;
end else if (((ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st10_fsm_10 == ap_CS_fsm))) begin
grp_computeDiffSqr_fu_531_u0_p2_q0 = u2_p2_q0;
end else if (((ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st8_fsm_8 == ap_CS_fsm))) begin
grp_computeDiffSqr_fu_531_u0_p2_q0 = u1_p2_q0;
end else if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st6_fsm_6 == ap_CS_fsm))) begin
grp_computeDiffSqr_fu_531_u0_p2_q0 = u0_p2_q0;
end else begin
grp_computeDiffSqr_fu_531_u0_p2_q0 = u0_p2_q0;
end
end
/// grp_computeDiffSqr_fu_531_u0_p3_q0 assign process. ///
always @ (ap_CS_fsm or u6_p3_q0 or u5_p3_q0 or u4_p3_q0 or u3_p3_q0 or u2_p3_q0 or u1_p3_q0 or u0_p3_q0)
begin
if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm))) begin
grp_computeDiffSqr_fu_531_u0_p3_q0 = u6_p3_q0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm))) begin
grp_computeDiffSqr_fu_531_u0_p3_q0 = u5_p3_q0;
end else if (((ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st14_fsm_14 == ap_CS_fsm))) begin
grp_computeDiffSqr_fu_531_u0_p3_q0 = u4_p3_q0;
end else if (((ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st12_fsm_12 == ap_CS_fsm))) begin
grp_computeDiffSqr_fu_531_u0_p3_q0 = u3_p3_q0;
end else if (((ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st10_fsm_10 == ap_CS_fsm))) begin
grp_computeDiffSqr_fu_531_u0_p3_q0 = u2_p3_q0;
end else if (((ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st8_fsm_8 == ap_CS_fsm))) begin
grp_computeDiffSqr_fu_531_u0_p3_q0 = u1_p3_q0;
end else if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st6_fsm_6 == ap_CS_fsm))) begin
grp_computeDiffSqr_fu_531_u0_p3_q0 = u0_p3_q0;
end else begin
grp_computeDiffSqr_fu_531_u0_p3_q0 = u0_p3_q0;
end
end
/// grp_computeDiffSqr_fu_531_u0_p3_q1 assign process. ///
always @ (ap_CS_fsm or u6_p3_q1 or u5_p3_q1 or u4_p3_q1 or u3_p3_q1 or u2_p3_q1 or u1_p3_q1 or u0_p3_q1)
begin
if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm))) begin
grp_computeDiffSqr_fu_531_u0_p3_q1 = u6_p3_q1;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm))) begin
grp_computeDiffSqr_fu_531_u0_p3_q1 = u5_p3_q1;
end else if (((ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st14_fsm_14 == ap_CS_fsm))) begin
grp_computeDiffSqr_fu_531_u0_p3_q1 = u4_p3_q1;
end else if (((ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st12_fsm_12 == ap_CS_fsm))) begin
grp_computeDiffSqr_fu_531_u0_p3_q1 = u3_p3_q1;
end else if (((ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st10_fsm_10 == ap_CS_fsm))) begin
grp_computeDiffSqr_fu_531_u0_p3_q1 = u2_p3_q1;
end else if (((ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st8_fsm_8 == ap_CS_fsm))) begin
grp_computeDiffSqr_fu_531_u0_p3_q1 = u1_p3_q1;
end else if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st6_fsm_6 == ap_CS_fsm))) begin
grp_computeDiffSqr_fu_531_u0_p3_q1 = u0_p3_q1;
end else begin
grp_computeDiffSqr_fu_531_u0_p3_q1 = u0_p3_q1;
end
end
/// grp_computeDiffSqr_fu_531_u1_p0_q0 assign process. ///
always @ (ap_CS_fsm or u6_p0_q0 or u5_p0_q0 or u4_p0_q0 or u3_p0_q0 or u2_p0_q0 or u1_p0_q0 or u0_p0_q0)
begin
if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm))) begin
grp_computeDiffSqr_fu_531_u1_p0_q0 = u0_p0_q0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm))) begin
grp_computeDiffSqr_fu_531_u1_p0_q0 = u6_p0_q0;
end else if (((ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st14_fsm_14 == ap_CS_fsm))) begin
grp_computeDiffSqr_fu_531_u1_p0_q0 = u5_p0_q0;
end else if (((ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st12_fsm_12 == ap_CS_fsm))) begin
grp_computeDiffSqr_fu_531_u1_p0_q0 = u4_p0_q0;
end else if (((ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st10_fsm_10 == ap_CS_fsm))) begin
grp_computeDiffSqr_fu_531_u1_p0_q0 = u3_p0_q0;
end else if (((ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st8_fsm_8 == ap_CS_fsm))) begin
grp_computeDiffSqr_fu_531_u1_p0_q0 = u2_p0_q0;
end else if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st6_fsm_6 == ap_CS_fsm))) begin
grp_computeDiffSqr_fu_531_u1_p0_q0 = u1_p0_q0;
end else begin
grp_computeDiffSqr_fu_531_u1_p0_q0 = u0_p0_q0;
end
end
/// grp_computeDiffSqr_fu_531_u1_p1_q0 assign process. ///
always @ (ap_CS_fsm or u6_p1_q0 or u5_p1_q0 or u4_p1_q0 or u3_p1_q0 or u2_p1_q0 or u1_p1_q0 or u0_p1_q0)
begin
if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm))) begin
grp_computeDiffSqr_fu_531_u1_p1_q0 = u0_p1_q0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm))) begin
grp_computeDiffSqr_fu_531_u1_p1_q0 = u6_p1_q0;
end else if (((ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st14_fsm_14 == ap_CS_fsm))) begin
grp_computeDiffSqr_fu_531_u1_p1_q0 = u5_p1_q0;
end else if (((ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st12_fsm_12 == ap_CS_fsm))) begin
grp_computeDiffSqr_fu_531_u1_p1_q0 = u4_p1_q0;
end else if (((ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st10_fsm_10 == ap_CS_fsm))) begin
grp_computeDiffSqr_fu_531_u1_p1_q0 = u3_p1_q0;
end else if (((ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st8_fsm_8 == ap_CS_fsm))) begin
grp_computeDiffSqr_fu_531_u1_p1_q0 = u2_p1_q0;
end else if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st6_fsm_6 == ap_CS_fsm))) begin
grp_computeDiffSqr_fu_531_u1_p1_q0 = u1_p1_q0;
end else begin
grp_computeDiffSqr_fu_531_u1_p1_q0 = u0_p1_q0;
end
end
/// grp_computeDiffSqr_fu_531_u1_p2_q0 assign process. ///
always @ (ap_CS_fsm or u6_p2_q0 or u5_p2_q0 or u4_p2_q0 or u3_p2_q0 or u2_p2_q0 or u1_p2_q0 or u0_p2_q0)
begin
if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm))) begin
grp_computeDiffSqr_fu_531_u1_p2_q0 = u0_p2_q0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm))) begin
grp_computeDiffSqr_fu_531_u1_p2_q0 = u6_p2_q0;
end else if (((ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st14_fsm_14 == ap_CS_fsm))) begin
grp_computeDiffSqr_fu_531_u1_p2_q0 = u5_p2_q0;
end else if (((ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st12_fsm_12 == ap_CS_fsm))) begin
grp_computeDiffSqr_fu_531_u1_p2_q0 = u4_p2_q0;
end else if (((ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st10_fsm_10 == ap_CS_fsm))) begin
grp_computeDiffSqr_fu_531_u1_p2_q0 = u3_p2_q0;
end else if (((ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st8_fsm_8 == ap_CS_fsm))) begin
grp_computeDiffSqr_fu_531_u1_p2_q0 = u2_p2_q0;
end else if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st6_fsm_6 == ap_CS_fsm))) begin
grp_computeDiffSqr_fu_531_u1_p2_q0 = u1_p2_q0;
end else begin
grp_computeDiffSqr_fu_531_u1_p2_q0 = u0_p2_q0;
end
end
/// grp_computeDiffSqr_fu_531_u1_p3_q0 assign process. ///
always @ (ap_CS_fsm or u6_p3_q0 or u5_p3_q0 or u4_p3_q0 or u3_p3_q0 or u2_p3_q0 or u1_p3_q0 or u0_p3_q0)
begin
if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm))) begin
grp_computeDiffSqr_fu_531_u1_p3_q0 = u0_p3_q0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm))) begin
grp_computeDiffSqr_fu_531_u1_p3_q0 = u6_p3_q0;
end else if (((ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st14_fsm_14 == ap_CS_fsm))) begin
grp_computeDiffSqr_fu_531_u1_p3_q0 = u5_p3_q0;
end else if (((ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st12_fsm_12 == ap_CS_fsm))) begin
grp_computeDiffSqr_fu_531_u1_p3_q0 = u4_p3_q0;
end else if (((ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st10_fsm_10 == ap_CS_fsm))) begin
grp_computeDiffSqr_fu_531_u1_p3_q0 = u3_p3_q0;
end else if (((ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st8_fsm_8 == ap_CS_fsm))) begin
grp_computeDiffSqr_fu_531_u1_p3_q0 = u2_p3_q0;
end else if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st6_fsm_6 == ap_CS_fsm))) begin
grp_computeDiffSqr_fu_531_u1_p3_q0 = u1_p3_q0;
end else begin
grp_computeDiffSqr_fu_531_u1_p3_q0 = u0_p3_q0;
end
end
/// grp_computeGradient_fu_507_ap_start assign process. ///
always @ (ap_CS_fsm)
begin
if (((ap_ST_st15_fsm_15 == ap_CS_fsm) | (ap_ST_st17_fsm_17 == ap_CS_fsm) | (ap_ST_st19_fsm_19 == ap_CS_fsm) | (ap_ST_st21_fsm_21 == ap_CS_fsm) | (ap_ST_st23_fsm_23 == ap_CS_fsm) | (ap_ST_st25_fsm_25 == ap_CS_fsm) | (ap_ST_st27_fsm_27 == ap_CS_fsm) | (ap_ST_st29_fsm_29 == ap_CS_fsm) | (ap_ST_st31_fsm_31 == ap_CS_fsm) | (ap_ST_st33_fsm_33 == ap_CS_fsm) | (ap_ST_st35_fsm_35 == ap_CS_fsm) | (ap_ST_st37_fsm_37 == ap_CS_fsm) | (ap_ST_st39_fsm_39 == ap_CS_fsm) | (ap_ST_st41_fsm_41 == ap_CS_fsm) | (ap_ST_st43_fsm_43 == ap_CS_fsm) | (ap_ST_st45_fsm_45 == ap_CS_fsm) | (ap_ST_st47_fsm_47 == ap_CS_fsm) | (ap_ST_st49_fsm_49 == ap_CS_fsm) | (ap_ST_st51_fsm_51 == ap_CS_fsm) | (ap_ST_st53_fsm_53 == ap_CS_fsm) | (ap_ST_st55_fsm_55 == ap_CS_fsm) | (ap_ST_st57_fsm_57 == ap_CS_fsm) | (ap_ST_st59_fsm_59 == ap_CS_fsm) | (ap_ST_st61_fsm_61 == ap_CS_fsm) | (ap_ST_st63_fsm_63 == ap_CS_fsm) | (ap_ST_st65_fsm_65 == ap_CS_fsm) | (ap_ST_st67_fsm_67 == ap_CS_fsm) | (ap_ST_st69_fsm_69 == ap_CS_fsm) | (ap_ST_st71_fsm_71 == ap_CS_fsm) | (ap_ST_st73_fsm_73 == ap_CS_fsm) | (ap_ST_st75_fsm_75 == ap_CS_fsm) | (ap_ST_st77_fsm_77 == ap_CS_fsm) | (ap_ST_st79_fsm_79 == ap_CS_fsm) | (ap_ST_st81_fsm_81 == ap_CS_fsm) | (ap_ST_st83_fsm_83 == ap_CS_fsm) | (ap_ST_st85_fsm_85 == ap_CS_fsm) | (ap_ST_st87_fsm_87 == ap_CS_fsm) | (ap_ST_st89_fsm_89 == ap_CS_fsm) | (ap_ST_st91_fsm_91 == ap_CS_fsm) | (ap_ST_st93_fsm_93 == ap_CS_fsm) | (ap_ST_st95_fsm_95 == ap_CS_fsm) | (ap_ST_st97_fsm_97 == ap_CS_fsm) | (ap_ST_st99_fsm_99 == ap_CS_fsm) | (ap_ST_st101_fsm_101 == ap_CS_fsm) | (ap_ST_st103_fsm_103 == ap_CS_fsm) | (ap_ST_st105_fsm_105 == ap_CS_fsm) | (ap_ST_st107_fsm_107 == ap_CS_fsm) | (ap_ST_st109_fsm_109 == ap_CS_fsm) | (ap_ST_st111_fsm_111 == ap_CS_fsm) | (ap_ST_st113_fsm_113 == ap_CS_fsm) | (ap_ST_st115_fsm_115 == ap_CS_fsm) | (ap_ST_st117_fsm_117 == ap_CS_fsm) | (ap_ST_st119_fsm_119 == ap_CS_fsm) | (ap_ST_st121_fsm_121 == ap_CS_fsm) | (ap_ST_st123_fsm_123 == ap_CS_fsm) | (ap_ST_st9_fsm_9 == ap_CS_fsm) | (ap_ST_st11_fsm_11 == ap_CS_fsm) | (ap_ST_st13_fsm_13 == ap_CS_fsm))) begin
grp_computeGradient_fu_507_ap_start = ap_const_logic_1;
end else begin
grp_computeGradient_fu_507_ap_start = ap_const_logic_0;
end
end
/// grp_computeGradient_fu_507_sm0_p0_q0 assign process. ///
always @ (ap_CS_fsm or sm1_p0_q0 or sm0_p0_q0)
begin
if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm) | (ap_ST_st12_fsm_12 == ap_CS_fsm))) begin
grp_computeGradient_fu_507_sm0_p0_q0 = sm0_p0_q0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st10_fsm_10 == ap_CS_fsm) | (ap_ST_st14_fsm_14 == ap_CS_fsm))) begin
grp_computeGradient_fu_507_sm0_p0_q0 = sm1_p0_q0;
end else begin
grp_computeGradient_fu_507_sm0_p0_q0 = sm0_p0_q0;
end
end
/// grp_computeGradient_fu_507_sm0_p1_q0 assign process. ///
always @ (ap_CS_fsm or sm1_p1_q0 or sm0_p1_q0)
begin
if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm) | (ap_ST_st12_fsm_12 == ap_CS_fsm))) begin
grp_computeGradient_fu_507_sm0_p1_q0 = sm0_p1_q0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st10_fsm_10 == ap_CS_fsm) | (ap_ST_st14_fsm_14 == ap_CS_fsm))) begin
grp_computeGradient_fu_507_sm0_p1_q0 = sm1_p1_q0;
end else begin
grp_computeGradient_fu_507_sm0_p1_q0 = sm0_p1_q0;
end
end
/// grp_computeGradient_fu_507_sm0_p2_q0 assign process. ///
always @ (ap_CS_fsm or sm1_p2_q0 or sm0_p2_q0)
begin
if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm) | (ap_ST_st12_fsm_12 == ap_CS_fsm))) begin
grp_computeGradient_fu_507_sm0_p2_q0 = sm0_p2_q0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st10_fsm_10 == ap_CS_fsm) | (ap_ST_st14_fsm_14 == ap_CS_fsm))) begin
grp_computeGradient_fu_507_sm0_p2_q0 = sm1_p2_q0;
end else begin
grp_computeGradient_fu_507_sm0_p2_q0 = sm0_p2_q0;
end
end
/// grp_computeGradient_fu_507_sm0_p3_q0 assign process. ///
always @ (ap_CS_fsm or sm1_p3_q0 or sm0_p3_q0)
begin
if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm) | (ap_ST_st12_fsm_12 == ap_CS_fsm))) begin
grp_computeGradient_fu_507_sm0_p3_q0 = sm0_p3_q0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st10_fsm_10 == ap_CS_fsm) | (ap_ST_st14_fsm_14 == ap_CS_fsm))) begin
grp_computeGradient_fu_507_sm0_p3_q0 = sm1_p3_q0;
end else begin
grp_computeGradient_fu_507_sm0_p3_q0 = sm0_p3_q0;
end
end
/// grp_computeGradient_fu_507_sn0_p0_q0 assign process. ///
always @ (ap_CS_fsm or sn1_p0_q0 or sn0_p0_q0)
begin
if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm) | (ap_ST_st12_fsm_12 == ap_CS_fsm))) begin
grp_computeGradient_fu_507_sn0_p0_q0 = sn0_p0_q0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st10_fsm_10 == ap_CS_fsm) | (ap_ST_st14_fsm_14 == ap_CS_fsm))) begin
grp_computeGradient_fu_507_sn0_p0_q0 = sn1_p0_q0;
end else begin
grp_computeGradient_fu_507_sn0_p0_q0 = sn0_p0_q0;
end
end
/// grp_computeGradient_fu_507_sn0_p0_q1 assign process. ///
always @ (ap_CS_fsm or sn1_p0_q1 or sn0_p0_q1)
begin
if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm) | (ap_ST_st12_fsm_12 == ap_CS_fsm))) begin
grp_computeGradient_fu_507_sn0_p0_q1 = sn0_p0_q1;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st10_fsm_10 == ap_CS_fsm) | (ap_ST_st14_fsm_14 == ap_CS_fsm))) begin
grp_computeGradient_fu_507_sn0_p0_q1 = sn1_p0_q1;
end else begin
grp_computeGradient_fu_507_sn0_p0_q1 = sn0_p0_q1;
end
end
/// grp_computeGradient_fu_507_sn0_p1_q0 assign process. ///
always @ (ap_CS_fsm or sn1_p1_q0 or sn0_p1_q0)
begin
if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm) | (ap_ST_st12_fsm_12 == ap_CS_fsm))) begin
grp_computeGradient_fu_507_sn0_p1_q0 = sn0_p1_q0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st10_fsm_10 == ap_CS_fsm) | (ap_ST_st14_fsm_14 == ap_CS_fsm))) begin
grp_computeGradient_fu_507_sn0_p1_q0 = sn1_p1_q0;
end else begin
grp_computeGradient_fu_507_sn0_p1_q0 = sn0_p1_q0;
end
end
/// grp_computeGradient_fu_507_sn0_p2_q0 assign process. ///
always @ (ap_CS_fsm or sn1_p2_q0 or sn0_p2_q0)
begin
if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm) | (ap_ST_st12_fsm_12 == ap_CS_fsm))) begin
grp_computeGradient_fu_507_sn0_p2_q0 = sn0_p2_q0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st10_fsm_10 == ap_CS_fsm) | (ap_ST_st14_fsm_14 == ap_CS_fsm))) begin
grp_computeGradient_fu_507_sn0_p2_q0 = sn1_p2_q0;
end else begin
grp_computeGradient_fu_507_sn0_p2_q0 = sn0_p2_q0;
end
end
/// grp_computeGradient_fu_507_sn0_p3_q0 assign process. ///
always @ (ap_CS_fsm or sn1_p3_q0 or sn0_p3_q0)
begin
if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm) | (ap_ST_st12_fsm_12 == ap_CS_fsm))) begin
grp_computeGradient_fu_507_sn0_p3_q0 = sn0_p3_q0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st10_fsm_10 == ap_CS_fsm) | (ap_ST_st14_fsm_14 == ap_CS_fsm))) begin
grp_computeGradient_fu_507_sn0_p3_q0 = sn1_p3_q0;
end else begin
grp_computeGradient_fu_507_sn0_p3_q0 = sn0_p3_q0;
end
end
/// grp_computeGradient_fu_507_sp0_p0_q0 assign process. ///
always @ (ap_CS_fsm or sp2_p0_q0 or sp1_p0_q0 or sp0_p0_q0)
begin
if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st14_fsm_14 == ap_CS_fsm))) begin
grp_computeGradient_fu_507_sp0_p0_q0 = sp2_p0_q0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st12_fsm_12 == ap_CS_fsm))) begin
grp_computeGradient_fu_507_sp0_p0_q0 = sp1_p0_q0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm) | (ap_ST_st10_fsm_10 == ap_CS_fsm))) begin
grp_computeGradient_fu_507_sp0_p0_q0 = sp0_p0_q0;
end else begin
grp_computeGradient_fu_507_sp0_p0_q0 = sp0_p0_q0;
end
end
/// grp_computeGradient_fu_507_sp0_p1_q0 assign process. ///
always @ (ap_CS_fsm or sp2_p1_q0 or sp1_p1_q0 or sp0_p1_q0)
begin
if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st14_fsm_14 == ap_CS_fsm))) begin
grp_computeGradient_fu_507_sp0_p1_q0 = sp2_p1_q0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st12_fsm_12 == ap_CS_fsm))) begin
grp_computeGradient_fu_507_sp0_p1_q0 = sp1_p1_q0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm) | (ap_ST_st10_fsm_10 == ap_CS_fsm))) begin
grp_computeGradient_fu_507_sp0_p1_q0 = sp0_p1_q0;
end else begin
grp_computeGradient_fu_507_sp0_p1_q0 = sp0_p1_q0;
end
end
/// grp_computeGradient_fu_507_sp0_p2_q0 assign process. ///
always @ (ap_CS_fsm or sp2_p2_q0 or sp1_p2_q0 or sp0_p2_q0)
begin
if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st14_fsm_14 == ap_CS_fsm))) begin
grp_computeGradient_fu_507_sp0_p2_q0 = sp2_p2_q0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st12_fsm_12 == ap_CS_fsm))) begin
grp_computeGradient_fu_507_sp0_p2_q0 = sp1_p2_q0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm) | (ap_ST_st10_fsm_10 == ap_CS_fsm))) begin
grp_computeGradient_fu_507_sp0_p2_q0 = sp0_p2_q0;
end else begin
grp_computeGradient_fu_507_sp0_p2_q0 = sp0_p2_q0;
end
end
/// grp_computeGradient_fu_507_sp0_p3_q0 assign process. ///
always @ (ap_CS_fsm or sp2_p3_q0 or sp1_p3_q0 or sp0_p3_q0)
begin
if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st14_fsm_14 == ap_CS_fsm))) begin
grp_computeGradient_fu_507_sp0_p3_q0 = sp2_p3_q0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st12_fsm_12 == ap_CS_fsm))) begin
grp_computeGradient_fu_507_sp0_p3_q0 = sp1_p3_q0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm) | (ap_ST_st10_fsm_10 == ap_CS_fsm))) begin
grp_computeGradient_fu_507_sp0_p3_q0 = sp0_p3_q0;
end else begin
grp_computeGradient_fu_507_sp0_p3_q0 = sp0_p3_q0;
end
end
/// grp_computeGradient_fu_507_sp1_p0_q0 assign process. ///
always @ (ap_CS_fsm or sp2_p0_q0 or sp1_p0_q0 or sp0_p0_q0)
begin
if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st14_fsm_14 == ap_CS_fsm))) begin
grp_computeGradient_fu_507_sp1_p0_q0 = sp0_p0_q0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st12_fsm_12 == ap_CS_fsm))) begin
grp_computeGradient_fu_507_sp1_p0_q0 = sp2_p0_q0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm) | (ap_ST_st10_fsm_10 == ap_CS_fsm))) begin
grp_computeGradient_fu_507_sp1_p0_q0 = sp1_p0_q0;
end else begin
grp_computeGradient_fu_507_sp1_p0_q0 = sp0_p0_q0;
end
end
/// grp_computeGradient_fu_507_sp1_p1_q0 assign process. ///
always @ (ap_CS_fsm or sp2_p1_q0 or sp1_p1_q0 or sp0_p1_q0)
begin
if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st14_fsm_14 == ap_CS_fsm))) begin
grp_computeGradient_fu_507_sp1_p1_q0 = sp0_p1_q0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st12_fsm_12 == ap_CS_fsm))) begin
grp_computeGradient_fu_507_sp1_p1_q0 = sp2_p1_q0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm) | (ap_ST_st10_fsm_10 == ap_CS_fsm))) begin
grp_computeGradient_fu_507_sp1_p1_q0 = sp1_p1_q0;
end else begin
grp_computeGradient_fu_507_sp1_p1_q0 = sp0_p1_q0;
end
end
/// grp_computeGradient_fu_507_sp1_p2_q0 assign process. ///
always @ (ap_CS_fsm or sp2_p2_q0 or sp1_p2_q0 or sp0_p2_q0)
begin
if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st14_fsm_14 == ap_CS_fsm))) begin
grp_computeGradient_fu_507_sp1_p2_q0 = sp0_p2_q0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st12_fsm_12 == ap_CS_fsm))) begin
grp_computeGradient_fu_507_sp1_p2_q0 = sp2_p2_q0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm) | (ap_ST_st10_fsm_10 == ap_CS_fsm))) begin
grp_computeGradient_fu_507_sp1_p2_q0 = sp1_p2_q0;
end else begin
grp_computeGradient_fu_507_sp1_p2_q0 = sp0_p2_q0;
end
end
/// grp_computeGradient_fu_507_sp1_p3_q0 assign process. ///
always @ (ap_CS_fsm or sp2_p3_q0 or sp1_p3_q0 or sp0_p3_q0)
begin
if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st14_fsm_14 == ap_CS_fsm))) begin
grp_computeGradient_fu_507_sp1_p3_q0 = sp0_p3_q0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st12_fsm_12 == ap_CS_fsm))) begin
grp_computeGradient_fu_507_sp1_p3_q0 = sp2_p3_q0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm) | (ap_ST_st10_fsm_10 == ap_CS_fsm))) begin
grp_computeGradient_fu_507_sp1_p3_q0 = sp1_p3_q0;
end else begin
grp_computeGradient_fu_507_sp1_p3_q0 = sp0_p3_q0;
end
end
/// grp_computeResult_fu_467_ap_start assign process. ///
always @ (ap_CS_fsm)
begin
if (((ap_ST_st15_fsm_15 == ap_CS_fsm) | (ap_ST_st17_fsm_17 == ap_CS_fsm) | (ap_ST_st19_fsm_19 == ap_CS_fsm) | (ap_ST_st21_fsm_21 == ap_CS_fsm) | (ap_ST_st23_fsm_23 == ap_CS_fsm) | (ap_ST_st25_fsm_25 == ap_CS_fsm) | (ap_ST_st27_fsm_27 == ap_CS_fsm) | (ap_ST_st29_fsm_29 == ap_CS_fsm) | (ap_ST_st31_fsm_31 == ap_CS_fsm) | (ap_ST_st33_fsm_33 == ap_CS_fsm) | (ap_ST_st35_fsm_35 == ap_CS_fsm) | (ap_ST_st37_fsm_37 == ap_CS_fsm) | (ap_ST_st39_fsm_39 == ap_CS_fsm) | (ap_ST_st41_fsm_41 == ap_CS_fsm) | (ap_ST_st43_fsm_43 == ap_CS_fsm) | (ap_ST_st45_fsm_45 == ap_CS_fsm) | (ap_ST_st47_fsm_47 == ap_CS_fsm) | (ap_ST_st49_fsm_49 == ap_CS_fsm) | (ap_ST_st51_fsm_51 == ap_CS_fsm) | (ap_ST_st53_fsm_53 == ap_CS_fsm) | (ap_ST_st55_fsm_55 == ap_CS_fsm) | (ap_ST_st57_fsm_57 == ap_CS_fsm) | (ap_ST_st59_fsm_59 == ap_CS_fsm) | (ap_ST_st61_fsm_61 == ap_CS_fsm) | (ap_ST_st63_fsm_63 == ap_CS_fsm) | (ap_ST_st65_fsm_65 == ap_CS_fsm) | (ap_ST_st67_fsm_67 == ap_CS_fsm) | (ap_ST_st69_fsm_69 == ap_CS_fsm) | (ap_ST_st71_fsm_71 == ap_CS_fsm) | (ap_ST_st73_fsm_73 == ap_CS_fsm) | (ap_ST_st75_fsm_75 == ap_CS_fsm) | (ap_ST_st77_fsm_77 == ap_CS_fsm) | (ap_ST_st79_fsm_79 == ap_CS_fsm) | (ap_ST_st81_fsm_81 == ap_CS_fsm) | (ap_ST_st83_fsm_83 == ap_CS_fsm) | (ap_ST_st85_fsm_85 == ap_CS_fsm) | (ap_ST_st87_fsm_87 == ap_CS_fsm) | (ap_ST_st89_fsm_89 == ap_CS_fsm) | (ap_ST_st91_fsm_91 == ap_CS_fsm) | (ap_ST_st93_fsm_93 == ap_CS_fsm) | (ap_ST_st95_fsm_95 == ap_CS_fsm) | (ap_ST_st97_fsm_97 == ap_CS_fsm) | (ap_ST_st99_fsm_99 == ap_CS_fsm) | (ap_ST_st101_fsm_101 == ap_CS_fsm) | (ap_ST_st103_fsm_103 == ap_CS_fsm) | (ap_ST_st105_fsm_105 == ap_CS_fsm) | (ap_ST_st107_fsm_107 == ap_CS_fsm) | (ap_ST_st109_fsm_109 == ap_CS_fsm) | (ap_ST_st111_fsm_111 == ap_CS_fsm) | (ap_ST_st113_fsm_113 == ap_CS_fsm) | (ap_ST_st115_fsm_115 == ap_CS_fsm) | (ap_ST_st117_fsm_117 == ap_CS_fsm) | (ap_ST_st119_fsm_119 == ap_CS_fsm) | (ap_ST_st121_fsm_121 == ap_CS_fsm) | (ap_ST_st123_fsm_123 == ap_CS_fsm) | (ap_ST_st125_fsm_125 == ap_CS_fsm) | (ap_ST_st127_fsm_127 == ap_CS_fsm) | (ap_ST_st129_fsm_129 == ap_CS_fsm))) begin
grp_computeResult_fu_467_ap_start = ap_const_logic_1;
end else begin
grp_computeResult_fu_467_ap_start = ap_const_logic_0;
end
end
/// grp_computeResult_fu_467_f_p0_q0 assign process. ///
always @ (ap_CS_fsm or f1_p0_q0 or f0_p0_q0)
begin
if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st126_fsm_126 == ap_CS_fsm) | (ap_ST_st130_fsm_130 == ap_CS_fsm))) begin
grp_computeResult_fu_467_f_p0_q0 = f1_p0_q0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm) | (ap_ST_st128_fsm_128 == ap_CS_fsm))) begin
grp_computeResult_fu_467_f_p0_q0 = f0_p0_q0;
end else begin
grp_computeResult_fu_467_f_p0_q0 = f0_p0_q0;
end
end
/// grp_computeResult_fu_467_f_p1_q0 assign process. ///
always @ (ap_CS_fsm or f1_p1_q0 or f0_p1_q0)
begin
if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st126_fsm_126 == ap_CS_fsm) | (ap_ST_st130_fsm_130 == ap_CS_fsm))) begin
grp_computeResult_fu_467_f_p1_q0 = f1_p1_q0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm) | (ap_ST_st128_fsm_128 == ap_CS_fsm))) begin
grp_computeResult_fu_467_f_p1_q0 = f0_p1_q0;
end else begin
grp_computeResult_fu_467_f_p1_q0 = f0_p1_q0;
end
end
/// grp_computeResult_fu_467_f_p2_q0 assign process. ///
always @ (ap_CS_fsm or f1_p2_q0 or f0_p2_q0)
begin
if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st126_fsm_126 == ap_CS_fsm) | (ap_ST_st130_fsm_130 == ap_CS_fsm))) begin
grp_computeResult_fu_467_f_p2_q0 = f1_p2_q0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm) | (ap_ST_st128_fsm_128 == ap_CS_fsm))) begin
grp_computeResult_fu_467_f_p2_q0 = f0_p2_q0;
end else begin
grp_computeResult_fu_467_f_p2_q0 = f0_p2_q0;
end
end
/// grp_computeResult_fu_467_f_p3_q0 assign process. ///
always @ (ap_CS_fsm or f1_p3_q0 or f0_p3_q0)
begin
if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st126_fsm_126 == ap_CS_fsm) | (ap_ST_st130_fsm_130 == ap_CS_fsm))) begin
grp_computeResult_fu_467_f_p3_q0 = f1_p3_q0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm) | (ap_ST_st128_fsm_128 == ap_CS_fsm))) begin
grp_computeResult_fu_467_f_p3_q0 = f0_p3_q0;
end else begin
grp_computeResult_fu_467_f_p3_q0 = f0_p3_q0;
end
end
/// grp_computeResult_fu_467_g0_p0_q0 assign process. ///
always @ (ap_CS_fsm or g4_p0_q0 or g3_p0_q0 or g2_p0_q0 or g1_p0_q0 or g0_p0_q0)
begin
if (((ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm))) begin
grp_computeResult_fu_467_g0_p0_q0 = g4_p0_q0;
end else if (((ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm))) begin
grp_computeResult_fu_467_g0_p0_q0 = g3_p0_q0;
end else if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st130_fsm_130 == ap_CS_fsm))) begin
grp_computeResult_fu_467_g0_p0_q0 = g2_p0_q0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st128_fsm_128 == ap_CS_fsm))) begin
grp_computeResult_fu_467_g0_p0_q0 = g1_p0_q0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st126_fsm_126 == ap_CS_fsm))) begin
grp_computeResult_fu_467_g0_p0_q0 = g0_p0_q0;
end else begin
grp_computeResult_fu_467_g0_p0_q0 = g0_p0_q0;
end
end
/// grp_computeResult_fu_467_g0_p1_q0 assign process. ///
always @ (ap_CS_fsm or g4_p1_q0 or g3_p1_q0 or g2_p1_q0 or g1_p1_q0 or g0_p1_q0)
begin
if (((ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm))) begin
grp_computeResult_fu_467_g0_p1_q0 = g4_p1_q0;
end else if (((ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm))) begin
grp_computeResult_fu_467_g0_p1_q0 = g3_p1_q0;
end else if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st130_fsm_130 == ap_CS_fsm))) begin
grp_computeResult_fu_467_g0_p1_q0 = g2_p1_q0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st128_fsm_128 == ap_CS_fsm))) begin
grp_computeResult_fu_467_g0_p1_q0 = g1_p1_q0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st126_fsm_126 == ap_CS_fsm))) begin
grp_computeResult_fu_467_g0_p1_q0 = g0_p1_q0;
end else begin
grp_computeResult_fu_467_g0_p1_q0 = g0_p1_q0;
end
end
/// grp_computeResult_fu_467_g0_p2_q0 assign process. ///
always @ (ap_CS_fsm or g4_p2_q0 or g3_p2_q0 or g2_p2_q0 or g1_p2_q0 or g0_p2_q0)
begin
if (((ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm))) begin
grp_computeResult_fu_467_g0_p2_q0 = g4_p2_q0;
end else if (((ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm))) begin
grp_computeResult_fu_467_g0_p2_q0 = g3_p2_q0;
end else if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st130_fsm_130 == ap_CS_fsm))) begin
grp_computeResult_fu_467_g0_p2_q0 = g2_p2_q0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st128_fsm_128 == ap_CS_fsm))) begin
grp_computeResult_fu_467_g0_p2_q0 = g1_p2_q0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st126_fsm_126 == ap_CS_fsm))) begin
grp_computeResult_fu_467_g0_p2_q0 = g0_p2_q0;
end else begin
grp_computeResult_fu_467_g0_p2_q0 = g0_p2_q0;
end
end
/// grp_computeResult_fu_467_g0_p3_q0 assign process. ///
always @ (ap_CS_fsm or g4_p3_q0 or g3_p3_q0 or g2_p3_q0 or g1_p3_q0 or g0_p3_q0)
begin
if (((ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm))) begin
grp_computeResult_fu_467_g0_p3_q0 = g4_p3_q0;
end else if (((ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm))) begin
grp_computeResult_fu_467_g0_p3_q0 = g3_p3_q0;
end else if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st130_fsm_130 == ap_CS_fsm))) begin
grp_computeResult_fu_467_g0_p3_q0 = g2_p3_q0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st128_fsm_128 == ap_CS_fsm))) begin
grp_computeResult_fu_467_g0_p3_q0 = g1_p3_q0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st126_fsm_126 == ap_CS_fsm))) begin
grp_computeResult_fu_467_g0_p3_q0 = g0_p3_q0;
end else begin
grp_computeResult_fu_467_g0_p3_q0 = g0_p3_q0;
end
end
/// grp_computeResult_fu_467_g1_p0_q0 assign process. ///
always @ (ap_CS_fsm or g4_p0_q0 or g3_p0_q0 or g2_p0_q0 or g1_p0_q0 or g0_p0_q0)
begin
if (((ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm))) begin
grp_computeResult_fu_467_g1_p0_q0 = g0_p0_q0;
end else if (((ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm))) begin
grp_computeResult_fu_467_g1_p0_q0 = g4_p0_q0;
end else if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st130_fsm_130 == ap_CS_fsm))) begin
grp_computeResult_fu_467_g1_p0_q0 = g3_p0_q0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st128_fsm_128 == ap_CS_fsm))) begin
grp_computeResult_fu_467_g1_p0_q0 = g2_p0_q0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st126_fsm_126 == ap_CS_fsm))) begin
grp_computeResult_fu_467_g1_p0_q0 = g1_p0_q0;
end else begin
grp_computeResult_fu_467_g1_p0_q0 = g0_p0_q0;
end
end
/// grp_computeResult_fu_467_g1_p0_q1 assign process. ///
always @ (ap_CS_fsm or g4_p0_q1 or g3_p0_q1 or g2_p0_q1 or g1_p0_q1 or g0_p0_q1)
begin
if (((ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm))) begin
grp_computeResult_fu_467_g1_p0_q1 = g0_p0_q1;
end else if (((ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm))) begin
grp_computeResult_fu_467_g1_p0_q1 = g4_p0_q1;
end else if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st130_fsm_130 == ap_CS_fsm))) begin
grp_computeResult_fu_467_g1_p0_q1 = g3_p0_q1;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st128_fsm_128 == ap_CS_fsm))) begin
grp_computeResult_fu_467_g1_p0_q1 = g2_p0_q1;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st126_fsm_126 == ap_CS_fsm))) begin
grp_computeResult_fu_467_g1_p0_q1 = g1_p0_q1;
end else begin
grp_computeResult_fu_467_g1_p0_q1 = g0_p0_q1;
end
end
/// grp_computeResult_fu_467_g1_p1_q0 assign process. ///
always @ (ap_CS_fsm or g4_p1_q0 or g3_p1_q0 or g2_p1_q0 or g1_p1_q0 or g0_p1_q0)
begin
if (((ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm))) begin
grp_computeResult_fu_467_g1_p1_q0 = g0_p1_q0;
end else if (((ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm))) begin
grp_computeResult_fu_467_g1_p1_q0 = g4_p1_q0;
end else if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st130_fsm_130 == ap_CS_fsm))) begin
grp_computeResult_fu_467_g1_p1_q0 = g3_p1_q0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st128_fsm_128 == ap_CS_fsm))) begin
grp_computeResult_fu_467_g1_p1_q0 = g2_p1_q0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st126_fsm_126 == ap_CS_fsm))) begin
grp_computeResult_fu_467_g1_p1_q0 = g1_p1_q0;
end else begin
grp_computeResult_fu_467_g1_p1_q0 = g0_p1_q0;
end
end
/// grp_computeResult_fu_467_g1_p2_q0 assign process. ///
always @ (ap_CS_fsm or g4_p2_q0 or g3_p2_q0 or g2_p2_q0 or g1_p2_q0 or g0_p2_q0)
begin
if (((ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm))) begin
grp_computeResult_fu_467_g1_p2_q0 = g0_p2_q0;
end else if (((ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm))) begin
grp_computeResult_fu_467_g1_p2_q0 = g4_p2_q0;
end else if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st130_fsm_130 == ap_CS_fsm))) begin
grp_computeResult_fu_467_g1_p2_q0 = g3_p2_q0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st128_fsm_128 == ap_CS_fsm))) begin
grp_computeResult_fu_467_g1_p2_q0 = g2_p2_q0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st126_fsm_126 == ap_CS_fsm))) begin
grp_computeResult_fu_467_g1_p2_q0 = g1_p2_q0;
end else begin
grp_computeResult_fu_467_g1_p2_q0 = g0_p2_q0;
end
end
/// grp_computeResult_fu_467_g1_p3_q0 assign process. ///
always @ (ap_CS_fsm or g4_p3_q0 or g3_p3_q0 or g2_p3_q0 or g1_p3_q0 or g0_p3_q0)
begin
if (((ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm))) begin
grp_computeResult_fu_467_g1_p3_q0 = g0_p3_q0;
end else if (((ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm))) begin
grp_computeResult_fu_467_g1_p3_q0 = g4_p3_q0;
end else if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st130_fsm_130 == ap_CS_fsm))) begin
grp_computeResult_fu_467_g1_p3_q0 = g3_p3_q0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st128_fsm_128 == ap_CS_fsm))) begin
grp_computeResult_fu_467_g1_p3_q0 = g2_p3_q0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st126_fsm_126 == ap_CS_fsm))) begin
grp_computeResult_fu_467_g1_p3_q0 = g1_p3_q0;
end else begin
grp_computeResult_fu_467_g1_p3_q0 = g0_p3_q0;
end
end
/// grp_computeResult_fu_467_g1_p3_q1 assign process. ///
always @ (ap_CS_fsm or g4_p3_q1 or g3_p3_q1 or g2_p3_q1 or g1_p3_q1 or g0_p3_q1)
begin
if (((ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm))) begin
grp_computeResult_fu_467_g1_p3_q1 = g0_p3_q1;
end else if (((ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm))) begin
grp_computeResult_fu_467_g1_p3_q1 = g4_p3_q1;
end else if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st130_fsm_130 == ap_CS_fsm))) begin
grp_computeResult_fu_467_g1_p3_q1 = g3_p3_q1;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st128_fsm_128 == ap_CS_fsm))) begin
grp_computeResult_fu_467_g1_p3_q1 = g2_p3_q1;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st126_fsm_126 == ap_CS_fsm))) begin
grp_computeResult_fu_467_g1_p3_q1 = g1_p3_q1;
end else begin
grp_computeResult_fu_467_g1_p3_q1 = g0_p3_q1;
end
end
/// grp_computeResult_fu_467_g2_p0_q0 assign process. ///
always @ (ap_CS_fsm or g4_p0_q0 or g3_p0_q0 or g2_p0_q0 or g1_p0_q0 or g0_p0_q0)
begin
if (((ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm))) begin
grp_computeResult_fu_467_g2_p0_q0 = g1_p0_q0;
end else if (((ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm))) begin
grp_computeResult_fu_467_g2_p0_q0 = g0_p0_q0;
end else if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st130_fsm_130 == ap_CS_fsm))) begin
grp_computeResult_fu_467_g2_p0_q0 = g4_p0_q0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st128_fsm_128 == ap_CS_fsm))) begin
grp_computeResult_fu_467_g2_p0_q0 = g3_p0_q0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st126_fsm_126 == ap_CS_fsm))) begin
grp_computeResult_fu_467_g2_p0_q0 = g2_p0_q0;
end else begin
grp_computeResult_fu_467_g2_p0_q0 = g0_p0_q0;
end
end
/// grp_computeResult_fu_467_g2_p1_q0 assign process. ///
always @ (ap_CS_fsm or g4_p1_q0 or g3_p1_q0 or g2_p1_q0 or g1_p1_q0 or g0_p1_q0)
begin
if (((ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm))) begin
grp_computeResult_fu_467_g2_p1_q0 = g1_p1_q0;
end else if (((ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm))) begin
grp_computeResult_fu_467_g2_p1_q0 = g0_p1_q0;
end else if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st130_fsm_130 == ap_CS_fsm))) begin
grp_computeResult_fu_467_g2_p1_q0 = g4_p1_q0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st128_fsm_128 == ap_CS_fsm))) begin
grp_computeResult_fu_467_g2_p1_q0 = g3_p1_q0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st126_fsm_126 == ap_CS_fsm))) begin
grp_computeResult_fu_467_g2_p1_q0 = g2_p1_q0;
end else begin
grp_computeResult_fu_467_g2_p1_q0 = g0_p1_q0;
end
end
/// grp_computeResult_fu_467_g2_p2_q0 assign process. ///
always @ (ap_CS_fsm or g4_p2_q0 or g3_p2_q0 or g2_p2_q0 or g1_p2_q0 or g0_p2_q0)
begin
if (((ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm))) begin
grp_computeResult_fu_467_g2_p2_q0 = g1_p2_q0;
end else if (((ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm))) begin
grp_computeResult_fu_467_g2_p2_q0 = g0_p2_q0;
end else if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st130_fsm_130 == ap_CS_fsm))) begin
grp_computeResult_fu_467_g2_p2_q0 = g4_p2_q0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st128_fsm_128 == ap_CS_fsm))) begin
grp_computeResult_fu_467_g2_p2_q0 = g3_p2_q0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st126_fsm_126 == ap_CS_fsm))) begin
grp_computeResult_fu_467_g2_p2_q0 = g2_p2_q0;
end else begin
grp_computeResult_fu_467_g2_p2_q0 = g0_p2_q0;
end
end
/// grp_computeResult_fu_467_g2_p3_q0 assign process. ///
always @ (ap_CS_fsm or g4_p3_q0 or g3_p3_q0 or g2_p3_q0 or g1_p3_q0 or g0_p3_q0)
begin
if (((ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm))) begin
grp_computeResult_fu_467_g2_p3_q0 = g1_p3_q0;
end else if (((ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm))) begin
grp_computeResult_fu_467_g2_p3_q0 = g0_p3_q0;
end else if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st130_fsm_130 == ap_CS_fsm))) begin
grp_computeResult_fu_467_g2_p3_q0 = g4_p3_q0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st128_fsm_128 == ap_CS_fsm))) begin
grp_computeResult_fu_467_g2_p3_q0 = g3_p3_q0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st126_fsm_126 == ap_CS_fsm))) begin
grp_computeResult_fu_467_g2_p3_q0 = g2_p3_q0;
end else begin
grp_computeResult_fu_467_g2_p3_q0 = g0_p3_q0;
end
end
/// grp_computeResult_fu_467_u_p0_q0 assign process. ///
always @ (ap_CS_fsm or u6_p0_q0 or u5_p0_q0 or u4_p0_q0 or u3_p0_q0 or u2_p0_q0 or u1_p0_q0 or u0_p0_q0)
begin
if (((ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st126_fsm_126 == ap_CS_fsm))) begin
grp_computeResult_fu_467_u_p0_q0 = u0_p0_q0;
end else if (((ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm))) begin
grp_computeResult_fu_467_u_p0_q0 = u6_p0_q0;
end else if (((ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm))) begin
grp_computeResult_fu_467_u_p0_q0 = u5_p0_q0;
end else if (((ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm))) begin
grp_computeResult_fu_467_u_p0_q0 = u4_p0_q0;
end else if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm))) begin
grp_computeResult_fu_467_u_p0_q0 = u3_p0_q0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st130_fsm_130 == ap_CS_fsm))) begin
grp_computeResult_fu_467_u_p0_q0 = u2_p0_q0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st128_fsm_128 == ap_CS_fsm))) begin
grp_computeResult_fu_467_u_p0_q0 = u1_p0_q0;
end else begin
grp_computeResult_fu_467_u_p0_q0 = u0_p0_q0;
end
end
/// grp_computeResult_fu_467_u_p1_q0 assign process. ///
always @ (ap_CS_fsm or u6_p1_q0 or u5_p1_q0 or u4_p1_q0 or u3_p1_q0 or u2_p1_q0 or u1_p1_q0 or u0_p1_q0)
begin
if (((ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st126_fsm_126 == ap_CS_fsm))) begin
grp_computeResult_fu_467_u_p1_q0 = u0_p1_q0;
end else if (((ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm))) begin
grp_computeResult_fu_467_u_p1_q0 = u6_p1_q0;
end else if (((ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm))) begin
grp_computeResult_fu_467_u_p1_q0 = u5_p1_q0;
end else if (((ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm))) begin
grp_computeResult_fu_467_u_p1_q0 = u4_p1_q0;
end else if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm))) begin
grp_computeResult_fu_467_u_p1_q0 = u3_p1_q0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st130_fsm_130 == ap_CS_fsm))) begin
grp_computeResult_fu_467_u_p1_q0 = u2_p1_q0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st128_fsm_128 == ap_CS_fsm))) begin
grp_computeResult_fu_467_u_p1_q0 = u1_p1_q0;
end else begin
grp_computeResult_fu_467_u_p1_q0 = u0_p1_q0;
end
end
/// grp_computeResult_fu_467_u_p2_q0 assign process. ///
always @ (ap_CS_fsm or u6_p2_q0 or u5_p2_q0 or u4_p2_q0 or u3_p2_q0 or u2_p2_q0 or u1_p2_q0 or u0_p2_q0)
begin
if (((ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st126_fsm_126 == ap_CS_fsm))) begin
grp_computeResult_fu_467_u_p2_q0 = u0_p2_q0;
end else if (((ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm))) begin
grp_computeResult_fu_467_u_p2_q0 = u6_p2_q0;
end else if (((ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm))) begin
grp_computeResult_fu_467_u_p2_q0 = u5_p2_q0;
end else if (((ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm))) begin
grp_computeResult_fu_467_u_p2_q0 = u4_p2_q0;
end else if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm))) begin
grp_computeResult_fu_467_u_p2_q0 = u3_p2_q0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st130_fsm_130 == ap_CS_fsm))) begin
grp_computeResult_fu_467_u_p2_q0 = u2_p2_q0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st128_fsm_128 == ap_CS_fsm))) begin
grp_computeResult_fu_467_u_p2_q0 = u1_p2_q0;
end else begin
grp_computeResult_fu_467_u_p2_q0 = u0_p2_q0;
end
end
/// grp_computeResult_fu_467_u_p3_q0 assign process. ///
always @ (ap_CS_fsm or u6_p3_q0 or u5_p3_q0 or u4_p3_q0 or u3_p3_q0 or u2_p3_q0 or u1_p3_q0 or u0_p3_q0)
begin
if (((ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st126_fsm_126 == ap_CS_fsm))) begin
grp_computeResult_fu_467_u_p3_q0 = u0_p3_q0;
end else if (((ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm))) begin
grp_computeResult_fu_467_u_p3_q0 = u6_p3_q0;
end else if (((ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm))) begin
grp_computeResult_fu_467_u_p3_q0 = u5_p3_q0;
end else if (((ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm))) begin
grp_computeResult_fu_467_u_p3_q0 = u4_p3_q0;
end else if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm))) begin
grp_computeResult_fu_467_u_p3_q0 = u3_p3_q0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st130_fsm_130 == ap_CS_fsm))) begin
grp_computeResult_fu_467_u_p3_q0 = u2_p3_q0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st128_fsm_128 == ap_CS_fsm))) begin
grp_computeResult_fu_467_u_p3_q0 = u1_p3_q0;
end else begin
grp_computeResult_fu_467_u_p3_q0 = u0_p3_q0;
end
end
/// grp_computeResult_fu_467_ug0_p0_q0 assign process. ///
always @ (ap_CS_fsm or ug3_p0_q0 or ug2_p0_q0 or ug1_p0_q0 or ug0_p0_q0)
begin
if (((ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st126_fsm_126 == ap_CS_fsm))) begin
grp_computeResult_fu_467_ug0_p0_q0 = ug3_p0_q0;
end else if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm))) begin
grp_computeResult_fu_467_ug0_p0_q0 = ug2_p0_q0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st130_fsm_130 == ap_CS_fsm))) begin
grp_computeResult_fu_467_ug0_p0_q0 = ug1_p0_q0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st128_fsm_128 == ap_CS_fsm))) begin
grp_computeResult_fu_467_ug0_p0_q0 = ug0_p0_q0;
end else begin
grp_computeResult_fu_467_ug0_p0_q0 = ug0_p0_q0;
end
end
/// grp_computeResult_fu_467_ug0_p1_q0 assign process. ///
always @ (ap_CS_fsm or ug3_p1_q0 or ug2_p1_q0 or ug1_p1_q0 or ug0_p1_q0)
begin
if (((ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st126_fsm_126 == ap_CS_fsm))) begin
grp_computeResult_fu_467_ug0_p1_q0 = ug3_p1_q0;
end else if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm))) begin
grp_computeResult_fu_467_ug0_p1_q0 = ug2_p1_q0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st130_fsm_130 == ap_CS_fsm))) begin
grp_computeResult_fu_467_ug0_p1_q0 = ug1_p1_q0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st128_fsm_128 == ap_CS_fsm))) begin
grp_computeResult_fu_467_ug0_p1_q0 = ug0_p1_q0;
end else begin
grp_computeResult_fu_467_ug0_p1_q0 = ug0_p1_q0;
end
end
/// grp_computeResult_fu_467_ug0_p2_q0 assign process. ///
always @ (ap_CS_fsm or ug3_p2_q0 or ug2_p2_q0 or ug1_p2_q0 or ug0_p2_q0)
begin
if (((ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st126_fsm_126 == ap_CS_fsm))) begin
grp_computeResult_fu_467_ug0_p2_q0 = ug3_p2_q0;
end else if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm))) begin
grp_computeResult_fu_467_ug0_p2_q0 = ug2_p2_q0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st130_fsm_130 == ap_CS_fsm))) begin
grp_computeResult_fu_467_ug0_p2_q0 = ug1_p2_q0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st128_fsm_128 == ap_CS_fsm))) begin
grp_computeResult_fu_467_ug0_p2_q0 = ug0_p2_q0;
end else begin
grp_computeResult_fu_467_ug0_p2_q0 = ug0_p2_q0;
end
end
/// grp_computeResult_fu_467_ug0_p3_q0 assign process. ///
always @ (ap_CS_fsm or ug3_p3_q0 or ug2_p3_q0 or ug1_p3_q0 or ug0_p3_q0)
begin
if (((ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st126_fsm_126 == ap_CS_fsm))) begin
grp_computeResult_fu_467_ug0_p3_q0 = ug3_p3_q0;
end else if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm))) begin
grp_computeResult_fu_467_ug0_p3_q0 = ug2_p3_q0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st130_fsm_130 == ap_CS_fsm))) begin
grp_computeResult_fu_467_ug0_p3_q0 = ug1_p3_q0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st128_fsm_128 == ap_CS_fsm))) begin
grp_computeResult_fu_467_ug0_p3_q0 = ug0_p3_q0;
end else begin
grp_computeResult_fu_467_ug0_p3_q0 = ug0_p3_q0;
end
end
/// grp_computeResult_fu_467_ug1_p0_q0 assign process. ///
always @ (ap_CS_fsm or ug3_p0_q0 or ug2_p0_q0 or ug1_p0_q0 or ug0_p0_q0)
begin
if (((ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st126_fsm_126 == ap_CS_fsm))) begin
grp_computeResult_fu_467_ug1_p0_q0 = ug0_p0_q0;
end else if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm))) begin
grp_computeResult_fu_467_ug1_p0_q0 = ug3_p0_q0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st130_fsm_130 == ap_CS_fsm))) begin
grp_computeResult_fu_467_ug1_p0_q0 = ug2_p0_q0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st128_fsm_128 == ap_CS_fsm))) begin
grp_computeResult_fu_467_ug1_p0_q0 = ug1_p0_q0;
end else begin
grp_computeResult_fu_467_ug1_p0_q0 = ug0_p0_q0;
end
end
/// grp_computeResult_fu_467_ug1_p0_q1 assign process. ///
always @ (ap_CS_fsm or ug3_p0_q1 or ug2_p0_q1 or ug1_p0_q1 or ug0_p0_q1)
begin
if (((ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st126_fsm_126 == ap_CS_fsm))) begin
grp_computeResult_fu_467_ug1_p0_q1 = ug0_p0_q1;
end else if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm))) begin
grp_computeResult_fu_467_ug1_p0_q1 = ug3_p0_q1;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st130_fsm_130 == ap_CS_fsm))) begin
grp_computeResult_fu_467_ug1_p0_q1 = ug2_p0_q1;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st128_fsm_128 == ap_CS_fsm))) begin
grp_computeResult_fu_467_ug1_p0_q1 = ug1_p0_q1;
end else begin
grp_computeResult_fu_467_ug1_p0_q1 = ug0_p0_q1;
end
end
/// grp_computeResult_fu_467_ug1_p1_q0 assign process. ///
always @ (ap_CS_fsm or ug3_p1_q0 or ug2_p1_q0 or ug1_p1_q0 or ug0_p1_q0)
begin
if (((ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st126_fsm_126 == ap_CS_fsm))) begin
grp_computeResult_fu_467_ug1_p1_q0 = ug0_p1_q0;
end else if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm))) begin
grp_computeResult_fu_467_ug1_p1_q0 = ug3_p1_q0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st130_fsm_130 == ap_CS_fsm))) begin
grp_computeResult_fu_467_ug1_p1_q0 = ug2_p1_q0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st128_fsm_128 == ap_CS_fsm))) begin
grp_computeResult_fu_467_ug1_p1_q0 = ug1_p1_q0;
end else begin
grp_computeResult_fu_467_ug1_p1_q0 = ug0_p1_q0;
end
end
/// grp_computeResult_fu_467_ug1_p2_q0 assign process. ///
always @ (ap_CS_fsm or ug3_p2_q0 or ug2_p2_q0 or ug1_p2_q0 or ug0_p2_q0)
begin
if (((ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st126_fsm_126 == ap_CS_fsm))) begin
grp_computeResult_fu_467_ug1_p2_q0 = ug0_p2_q0;
end else if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm))) begin
grp_computeResult_fu_467_ug1_p2_q0 = ug3_p2_q0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st130_fsm_130 == ap_CS_fsm))) begin
grp_computeResult_fu_467_ug1_p2_q0 = ug2_p2_q0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st128_fsm_128 == ap_CS_fsm))) begin
grp_computeResult_fu_467_ug1_p2_q0 = ug1_p2_q0;
end else begin
grp_computeResult_fu_467_ug1_p2_q0 = ug0_p2_q0;
end
end
/// grp_computeResult_fu_467_ug1_p3_q0 assign process. ///
always @ (ap_CS_fsm or ug3_p3_q0 or ug2_p3_q0 or ug1_p3_q0 or ug0_p3_q0)
begin
if (((ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st126_fsm_126 == ap_CS_fsm))) begin
grp_computeResult_fu_467_ug1_p3_q0 = ug0_p3_q0;
end else if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm))) begin
grp_computeResult_fu_467_ug1_p3_q0 = ug3_p3_q0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st130_fsm_130 == ap_CS_fsm))) begin
grp_computeResult_fu_467_ug1_p3_q0 = ug2_p3_q0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st128_fsm_128 == ap_CS_fsm))) begin
grp_computeResult_fu_467_ug1_p3_q0 = ug1_p3_q0;
end else begin
grp_computeResult_fu_467_ug1_p3_q0 = ug0_p3_q0;
end
end
/// grp_computeResult_fu_467_ug1_p3_q1 assign process. ///
always @ (ap_CS_fsm or ug3_p3_q1 or ug2_p3_q1 or ug1_p3_q1 or ug0_p3_q1)
begin
if (((ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st126_fsm_126 == ap_CS_fsm))) begin
grp_computeResult_fu_467_ug1_p3_q1 = ug0_p3_q1;
end else if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm))) begin
grp_computeResult_fu_467_ug1_p3_q1 = ug3_p3_q1;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st130_fsm_130 == ap_CS_fsm))) begin
grp_computeResult_fu_467_ug1_p3_q1 = ug2_p3_q1;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st128_fsm_128 == ap_CS_fsm))) begin
grp_computeResult_fu_467_ug1_p3_q1 = ug1_p3_q1;
end else begin
grp_computeResult_fu_467_ug1_p3_q1 = ug0_p3_q1;
end
end
/// grp_computeResult_fu_467_ug2_p0_q0 assign process. ///
always @ (ap_CS_fsm or ug3_p0_q0 or ug2_p0_q0 or ug1_p0_q0 or ug0_p0_q0)
begin
if (((ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st126_fsm_126 == ap_CS_fsm))) begin
grp_computeResult_fu_467_ug2_p0_q0 = ug1_p0_q0;
end else if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm))) begin
grp_computeResult_fu_467_ug2_p0_q0 = ug0_p0_q0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st130_fsm_130 == ap_CS_fsm))) begin
grp_computeResult_fu_467_ug2_p0_q0 = ug3_p0_q0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st128_fsm_128 == ap_CS_fsm))) begin
grp_computeResult_fu_467_ug2_p0_q0 = ug2_p0_q0;
end else begin
grp_computeResult_fu_467_ug2_p0_q0 = ug0_p0_q0;
end
end
/// grp_computeResult_fu_467_ug2_p1_q0 assign process. ///
always @ (ap_CS_fsm or ug3_p1_q0 or ug2_p1_q0 or ug1_p1_q0 or ug0_p1_q0)
begin
if (((ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st126_fsm_126 == ap_CS_fsm))) begin
grp_computeResult_fu_467_ug2_p1_q0 = ug1_p1_q0;
end else if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm))) begin
grp_computeResult_fu_467_ug2_p1_q0 = ug0_p1_q0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st130_fsm_130 == ap_CS_fsm))) begin
grp_computeResult_fu_467_ug2_p1_q0 = ug3_p1_q0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st128_fsm_128 == ap_CS_fsm))) begin
grp_computeResult_fu_467_ug2_p1_q0 = ug2_p1_q0;
end else begin
grp_computeResult_fu_467_ug2_p1_q0 = ug0_p1_q0;
end
end
/// grp_computeResult_fu_467_ug2_p2_q0 assign process. ///
always @ (ap_CS_fsm or ug3_p2_q0 or ug2_p2_q0 or ug1_p2_q0 or ug0_p2_q0)
begin
if (((ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st126_fsm_126 == ap_CS_fsm))) begin
grp_computeResult_fu_467_ug2_p2_q0 = ug1_p2_q0;
end else if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm))) begin
grp_computeResult_fu_467_ug2_p2_q0 = ug0_p2_q0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st130_fsm_130 == ap_CS_fsm))) begin
grp_computeResult_fu_467_ug2_p2_q0 = ug3_p2_q0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st128_fsm_128 == ap_CS_fsm))) begin
grp_computeResult_fu_467_ug2_p2_q0 = ug2_p2_q0;
end else begin
grp_computeResult_fu_467_ug2_p2_q0 = ug0_p2_q0;
end
end
/// grp_computeResult_fu_467_ug2_p3_q0 assign process. ///
always @ (ap_CS_fsm or ug3_p3_q0 or ug2_p3_q0 or ug1_p3_q0 or ug0_p3_q0)
begin
if (((ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st126_fsm_126 == ap_CS_fsm))) begin
grp_computeResult_fu_467_ug2_p3_q0 = ug1_p3_q0;
end else if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm))) begin
grp_computeResult_fu_467_ug2_p3_q0 = ug0_p3_q0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st130_fsm_130 == ap_CS_fsm))) begin
grp_computeResult_fu_467_ug2_p3_q0 = ug3_p3_q0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st128_fsm_128 == ap_CS_fsm))) begin
grp_computeResult_fu_467_ug2_p3_q0 = ug2_p3_q0;
end else begin
grp_computeResult_fu_467_ug2_p3_q0 = ug0_p3_q0;
end
end
/// grp_computeUG_fu_555_ap_start assign process. ///
always @ (ap_CS_fsm)
begin
if (((ap_ST_st15_fsm_15 == ap_CS_fsm) | (ap_ST_st17_fsm_17 == ap_CS_fsm) | (ap_ST_st19_fsm_19 == ap_CS_fsm) | (ap_ST_st21_fsm_21 == ap_CS_fsm) | (ap_ST_st23_fsm_23 == ap_CS_fsm) | (ap_ST_st25_fsm_25 == ap_CS_fsm) | (ap_ST_st27_fsm_27 == ap_CS_fsm) | (ap_ST_st29_fsm_29 == ap_CS_fsm) | (ap_ST_st31_fsm_31 == ap_CS_fsm) | (ap_ST_st33_fsm_33 == ap_CS_fsm) | (ap_ST_st35_fsm_35 == ap_CS_fsm) | (ap_ST_st37_fsm_37 == ap_CS_fsm) | (ap_ST_st39_fsm_39 == ap_CS_fsm) | (ap_ST_st41_fsm_41 == ap_CS_fsm) | (ap_ST_st43_fsm_43 == ap_CS_fsm) | (ap_ST_st45_fsm_45 == ap_CS_fsm) | (ap_ST_st47_fsm_47 == ap_CS_fsm) | (ap_ST_st49_fsm_49 == ap_CS_fsm) | (ap_ST_st51_fsm_51 == ap_CS_fsm) | (ap_ST_st53_fsm_53 == ap_CS_fsm) | (ap_ST_st55_fsm_55 == ap_CS_fsm) | (ap_ST_st57_fsm_57 == ap_CS_fsm) | (ap_ST_st59_fsm_59 == ap_CS_fsm) | (ap_ST_st61_fsm_61 == ap_CS_fsm) | (ap_ST_st63_fsm_63 == ap_CS_fsm) | (ap_ST_st65_fsm_65 == ap_CS_fsm) | (ap_ST_st67_fsm_67 == ap_CS_fsm) | (ap_ST_st69_fsm_69 == ap_CS_fsm) | (ap_ST_st71_fsm_71 == ap_CS_fsm) | (ap_ST_st73_fsm_73 == ap_CS_fsm) | (ap_ST_st75_fsm_75 == ap_CS_fsm) | (ap_ST_st77_fsm_77 == ap_CS_fsm) | (ap_ST_st79_fsm_79 == ap_CS_fsm) | (ap_ST_st81_fsm_81 == ap_CS_fsm) | (ap_ST_st83_fsm_83 == ap_CS_fsm) | (ap_ST_st85_fsm_85 == ap_CS_fsm) | (ap_ST_st87_fsm_87 == ap_CS_fsm) | (ap_ST_st89_fsm_89 == ap_CS_fsm) | (ap_ST_st91_fsm_91 == ap_CS_fsm) | (ap_ST_st93_fsm_93 == ap_CS_fsm) | (ap_ST_st95_fsm_95 == ap_CS_fsm) | (ap_ST_st97_fsm_97 == ap_CS_fsm) | (ap_ST_st99_fsm_99 == ap_CS_fsm) | (ap_ST_st101_fsm_101 == ap_CS_fsm) | (ap_ST_st103_fsm_103 == ap_CS_fsm) | (ap_ST_st105_fsm_105 == ap_CS_fsm) | (ap_ST_st107_fsm_107 == ap_CS_fsm) | (ap_ST_st109_fsm_109 == ap_CS_fsm) | (ap_ST_st111_fsm_111 == ap_CS_fsm) | (ap_ST_st113_fsm_113 == ap_CS_fsm) | (ap_ST_st115_fsm_115 == ap_CS_fsm) | (ap_ST_st117_fsm_117 == ap_CS_fsm) | (ap_ST_st119_fsm_119 == ap_CS_fsm) | (ap_ST_st121_fsm_121 == ap_CS_fsm) | (ap_ST_st123_fsm_123 == ap_CS_fsm) | (ap_ST_st125_fsm_125 == ap_CS_fsm) | (ap_ST_st127_fsm_127 == ap_CS_fsm) | (ap_ST_st11_fsm_11 == ap_CS_fsm) | (ap_ST_st13_fsm_13 == ap_CS_fsm))) begin
grp_computeUG_fu_555_ap_start = ap_const_logic_1;
end else begin
grp_computeUG_fu_555_ap_start = ap_const_logic_0;
end
end
/// grp_computeUG_fu_555_g_p0_q0 assign process. ///
always @ (ap_CS_fsm or g4_p0_q0 or g3_p0_q0 or g2_p0_q0 or g1_p0_q0 or g0_p0_q0)
begin
if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm))) begin
grp_computeUG_fu_555_g_p0_q0 = g0_p0_q0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st128_fsm_128 == ap_CS_fsm))) begin
grp_computeUG_fu_555_g_p0_q0 = g4_p0_q0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st126_fsm_126 == ap_CS_fsm))) begin
grp_computeUG_fu_555_g_p0_q0 = g3_p0_q0;
end else if (((ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm) | (ap_ST_st14_fsm_14 == ap_CS_fsm))) begin
grp_computeUG_fu_555_g_p0_q0 = g2_p0_q0;
end else if (((ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st12_fsm_12 == ap_CS_fsm))) begin
grp_computeUG_fu_555_g_p0_q0 = g1_p0_q0;
end else begin
grp_computeUG_fu_555_g_p0_q0 = g0_p0_q0;
end
end
/// grp_computeUG_fu_555_g_p1_q0 assign process. ///
always @ (ap_CS_fsm or g4_p1_q0 or g3_p1_q0 or g2_p1_q0 or g1_p1_q0 or g0_p1_q0)
begin
if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm))) begin
grp_computeUG_fu_555_g_p1_q0 = g0_p1_q0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st128_fsm_128 == ap_CS_fsm))) begin
grp_computeUG_fu_555_g_p1_q0 = g4_p1_q0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st126_fsm_126 == ap_CS_fsm))) begin
grp_computeUG_fu_555_g_p1_q0 = g3_p1_q0;
end else if (((ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm) | (ap_ST_st14_fsm_14 == ap_CS_fsm))) begin
grp_computeUG_fu_555_g_p1_q0 = g2_p1_q0;
end else if (((ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st12_fsm_12 == ap_CS_fsm))) begin
grp_computeUG_fu_555_g_p1_q0 = g1_p1_q0;
end else begin
grp_computeUG_fu_555_g_p1_q0 = g0_p1_q0;
end
end
/// grp_computeUG_fu_555_g_p2_q0 assign process. ///
always @ (ap_CS_fsm or g4_p2_q0 or g3_p2_q0 or g2_p2_q0 or g1_p2_q0 or g0_p2_q0)
begin
if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm))) begin
grp_computeUG_fu_555_g_p2_q0 = g0_p2_q0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st128_fsm_128 == ap_CS_fsm))) begin
grp_computeUG_fu_555_g_p2_q0 = g4_p2_q0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st126_fsm_126 == ap_CS_fsm))) begin
grp_computeUG_fu_555_g_p2_q0 = g3_p2_q0;
end else if (((ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm) | (ap_ST_st14_fsm_14 == ap_CS_fsm))) begin
grp_computeUG_fu_555_g_p2_q0 = g2_p2_q0;
end else if (((ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st12_fsm_12 == ap_CS_fsm))) begin
grp_computeUG_fu_555_g_p2_q0 = g1_p2_q0;
end else begin
grp_computeUG_fu_555_g_p2_q0 = g0_p2_q0;
end
end
/// grp_computeUG_fu_555_g_p3_q0 assign process. ///
always @ (ap_CS_fsm or g4_p3_q0 or g3_p3_q0 or g2_p3_q0 or g1_p3_q0 or g0_p3_q0)
begin
if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm))) begin
grp_computeUG_fu_555_g_p3_q0 = g0_p3_q0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st128_fsm_128 == ap_CS_fsm))) begin
grp_computeUG_fu_555_g_p3_q0 = g4_p3_q0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st126_fsm_126 == ap_CS_fsm))) begin
grp_computeUG_fu_555_g_p3_q0 = g3_p3_q0;
end else if (((ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm) | (ap_ST_st14_fsm_14 == ap_CS_fsm))) begin
grp_computeUG_fu_555_g_p3_q0 = g2_p3_q0;
end else if (((ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st12_fsm_12 == ap_CS_fsm))) begin
grp_computeUG_fu_555_g_p3_q0 = g1_p3_q0;
end else begin
grp_computeUG_fu_555_g_p3_q0 = g0_p3_q0;
end
end
/// grp_computeUG_fu_555_u_p0_q0 assign process. ///
always @ (ap_CS_fsm or u6_p0_q0 or u5_p0_q0 or u4_p0_q0 or u3_p0_q0 or u2_p0_q0 or u1_p0_q0 or u0_p0_q0)
begin
if (((ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm))) begin
grp_computeUG_fu_555_u_p0_q0 = u0_p0_q0;
end else if (((ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm))) begin
grp_computeUG_fu_555_u_p0_q0 = u6_p0_q0;
end else if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm))) begin
grp_computeUG_fu_555_u_p0_q0 = u5_p0_q0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm))) begin
grp_computeUG_fu_555_u_p0_q0 = u4_p0_q0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st128_fsm_128 == ap_CS_fsm))) begin
grp_computeUG_fu_555_u_p0_q0 = u3_p0_q0;
end else if (((ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st126_fsm_126 == ap_CS_fsm) | (ap_ST_st14_fsm_14 == ap_CS_fsm))) begin
grp_computeUG_fu_555_u_p0_q0 = u2_p0_q0;
end else if (((ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm) | (ap_ST_st12_fsm_12 == ap_CS_fsm))) begin
grp_computeUG_fu_555_u_p0_q0 = u1_p0_q0;
end else begin
grp_computeUG_fu_555_u_p0_q0 = u0_p0_q0;
end
end
/// grp_computeUG_fu_555_u_p1_q0 assign process. ///
always @ (ap_CS_fsm or u6_p1_q0 or u5_p1_q0 or u4_p1_q0 or u3_p1_q0 or u2_p1_q0 or u1_p1_q0 or u0_p1_q0)
begin
if (((ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm))) begin
grp_computeUG_fu_555_u_p1_q0 = u0_p1_q0;
end else if (((ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm))) begin
grp_computeUG_fu_555_u_p1_q0 = u6_p1_q0;
end else if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm))) begin
grp_computeUG_fu_555_u_p1_q0 = u5_p1_q0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm))) begin
grp_computeUG_fu_555_u_p1_q0 = u4_p1_q0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st128_fsm_128 == ap_CS_fsm))) begin
grp_computeUG_fu_555_u_p1_q0 = u3_p1_q0;
end else if (((ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st126_fsm_126 == ap_CS_fsm) | (ap_ST_st14_fsm_14 == ap_CS_fsm))) begin
grp_computeUG_fu_555_u_p1_q0 = u2_p1_q0;
end else if (((ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm) | (ap_ST_st12_fsm_12 == ap_CS_fsm))) begin
grp_computeUG_fu_555_u_p1_q0 = u1_p1_q0;
end else begin
grp_computeUG_fu_555_u_p1_q0 = u0_p1_q0;
end
end
/// grp_computeUG_fu_555_u_p2_q0 assign process. ///
always @ (ap_CS_fsm or u6_p2_q0 or u5_p2_q0 or u4_p2_q0 or u3_p2_q0 or u2_p2_q0 or u1_p2_q0 or u0_p2_q0)
begin
if (((ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm))) begin
grp_computeUG_fu_555_u_p2_q0 = u0_p2_q0;
end else if (((ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm))) begin
grp_computeUG_fu_555_u_p2_q0 = u6_p2_q0;
end else if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm))) begin
grp_computeUG_fu_555_u_p2_q0 = u5_p2_q0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm))) begin
grp_computeUG_fu_555_u_p2_q0 = u4_p2_q0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st128_fsm_128 == ap_CS_fsm))) begin
grp_computeUG_fu_555_u_p2_q0 = u3_p2_q0;
end else if (((ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st126_fsm_126 == ap_CS_fsm) | (ap_ST_st14_fsm_14 == ap_CS_fsm))) begin
grp_computeUG_fu_555_u_p2_q0 = u2_p2_q0;
end else if (((ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm) | (ap_ST_st12_fsm_12 == ap_CS_fsm))) begin
grp_computeUG_fu_555_u_p2_q0 = u1_p2_q0;
end else begin
grp_computeUG_fu_555_u_p2_q0 = u0_p2_q0;
end
end
/// grp_computeUG_fu_555_u_p3_q0 assign process. ///
always @ (ap_CS_fsm or u6_p3_q0 or u5_p3_q0 or u4_p3_q0 or u3_p3_q0 or u2_p3_q0 or u1_p3_q0 or u0_p3_q0)
begin
if (((ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm))) begin
grp_computeUG_fu_555_u_p3_q0 = u0_p3_q0;
end else if (((ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm))) begin
grp_computeUG_fu_555_u_p3_q0 = u6_p3_q0;
end else if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm))) begin
grp_computeUG_fu_555_u_p3_q0 = u5_p3_q0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm))) begin
grp_computeUG_fu_555_u_p3_q0 = u4_p3_q0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st128_fsm_128 == ap_CS_fsm))) begin
grp_computeUG_fu_555_u_p3_q0 = u3_p3_q0;
end else if (((ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st126_fsm_126 == ap_CS_fsm) | (ap_ST_st14_fsm_14 == ap_CS_fsm))) begin
grp_computeUG_fu_555_u_p3_q0 = u2_p3_q0;
end else if (((ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm) | (ap_ST_st12_fsm_12 == ap_CS_fsm))) begin
grp_computeUG_fu_555_u_p3_q0 = u1_p3_q0;
end else begin
grp_computeUG_fu_555_u_p3_q0 = u0_p3_q0;
end
end
/// grp_fFetch_array_fu_599_ap_start assign process. ///
always @ (ap_CS_fsm)
begin
if (((ap_ST_st17_fsm_17 == ap_CS_fsm) | (ap_ST_st19_fsm_19 == ap_CS_fsm) | (ap_ST_st21_fsm_21 == ap_CS_fsm) | (ap_ST_st23_fsm_23 == ap_CS_fsm) | (ap_ST_st25_fsm_25 == ap_CS_fsm) | (ap_ST_st27_fsm_27 == ap_CS_fsm) | (ap_ST_st29_fsm_29 == ap_CS_fsm) | (ap_ST_st31_fsm_31 == ap_CS_fsm) | (ap_ST_st33_fsm_33 == ap_CS_fsm) | (ap_ST_st35_fsm_35 == ap_CS_fsm) | (ap_ST_st37_fsm_37 == ap_CS_fsm) | (ap_ST_st39_fsm_39 == ap_CS_fsm) | (ap_ST_st41_fsm_41 == ap_CS_fsm) | (ap_ST_st43_fsm_43 == ap_CS_fsm) | (ap_ST_st45_fsm_45 == ap_CS_fsm) | (ap_ST_st47_fsm_47 == ap_CS_fsm) | (ap_ST_st49_fsm_49 == ap_CS_fsm) | (ap_ST_st51_fsm_51 == ap_CS_fsm) | (ap_ST_st53_fsm_53 == ap_CS_fsm) | (ap_ST_st55_fsm_55 == ap_CS_fsm) | (ap_ST_st57_fsm_57 == ap_CS_fsm) | (ap_ST_st59_fsm_59 == ap_CS_fsm) | (ap_ST_st61_fsm_61 == ap_CS_fsm) | (ap_ST_st63_fsm_63 == ap_CS_fsm) | (ap_ST_st65_fsm_65 == ap_CS_fsm) | (ap_ST_st67_fsm_67 == ap_CS_fsm) | (ap_ST_st69_fsm_69 == ap_CS_fsm) | (ap_ST_st71_fsm_71 == ap_CS_fsm) | (ap_ST_st73_fsm_73 == ap_CS_fsm) | (ap_ST_st75_fsm_75 == ap_CS_fsm) | (ap_ST_st77_fsm_77 == ap_CS_fsm) | (ap_ST_st79_fsm_79 == ap_CS_fsm) | (ap_ST_st81_fsm_81 == ap_CS_fsm) | (ap_ST_st83_fsm_83 == ap_CS_fsm) | (ap_ST_st85_fsm_85 == ap_CS_fsm) | (ap_ST_st87_fsm_87 == ap_CS_fsm) | (ap_ST_st89_fsm_89 == ap_CS_fsm) | (ap_ST_st91_fsm_91 == ap_CS_fsm) | (ap_ST_st93_fsm_93 == ap_CS_fsm) | (ap_ST_st95_fsm_95 == ap_CS_fsm) | (ap_ST_st97_fsm_97 == ap_CS_fsm) | (ap_ST_st99_fsm_99 == ap_CS_fsm) | (ap_ST_st101_fsm_101 == ap_CS_fsm) | (ap_ST_st103_fsm_103 == ap_CS_fsm) | (ap_ST_st105_fsm_105 == ap_CS_fsm) | (ap_ST_st107_fsm_107 == ap_CS_fsm) | (ap_ST_st109_fsm_109 == ap_CS_fsm) | (ap_ST_st111_fsm_111 == ap_CS_fsm) | (ap_ST_st113_fsm_113 == ap_CS_fsm) | (ap_ST_st115_fsm_115 == ap_CS_fsm) | (ap_ST_st117_fsm_117 == ap_CS_fsm) | (ap_ST_st119_fsm_119 == ap_CS_fsm) | (ap_ST_st121_fsm_121 == ap_CS_fsm) | (ap_ST_st123_fsm_123 == ap_CS_fsm) | (ap_ST_st125_fsm_125 == ap_CS_fsm) | (ap_ST_st5_fsm_5 == ap_CS_fsm) | (ap_ST_st1_fsm_1 == ap_CS_fsm) | (ap_ST_st3_fsm_3 == ap_CS_fsm))) begin
grp_fFetch_array_fu_599_ap_start = ap_const_logic_1;
end else begin
grp_fFetch_array_fu_599_ap_start = ap_const_logic_0;
end
end
/// grp_uFetch_array_fu_583_ap_start assign process. ///
always @ (ap_CS_fsm)
begin
if (((ap_ST_st15_fsm_15 == ap_CS_fsm) | (ap_ST_st17_fsm_17 == ap_CS_fsm) | (ap_ST_st19_fsm_19 == ap_CS_fsm) | (ap_ST_st21_fsm_21 == ap_CS_fsm) | (ap_ST_st23_fsm_23 == ap_CS_fsm) | (ap_ST_st25_fsm_25 == ap_CS_fsm) | (ap_ST_st27_fsm_27 == ap_CS_fsm) | (ap_ST_st29_fsm_29 == ap_CS_fsm) | (ap_ST_st31_fsm_31 == ap_CS_fsm) | (ap_ST_st33_fsm_33 == ap_CS_fsm) | (ap_ST_st35_fsm_35 == ap_CS_fsm) | (ap_ST_st37_fsm_37 == ap_CS_fsm) | (ap_ST_st39_fsm_39 == ap_CS_fsm) | (ap_ST_st41_fsm_41 == ap_CS_fsm) | (ap_ST_st43_fsm_43 == ap_CS_fsm) | (ap_ST_st45_fsm_45 == ap_CS_fsm) | (ap_ST_st47_fsm_47 == ap_CS_fsm) | (ap_ST_st49_fsm_49 == ap_CS_fsm) | (ap_ST_st51_fsm_51 == ap_CS_fsm) | (ap_ST_st53_fsm_53 == ap_CS_fsm) | (ap_ST_st55_fsm_55 == ap_CS_fsm) | (ap_ST_st57_fsm_57 == ap_CS_fsm) | (ap_ST_st59_fsm_59 == ap_CS_fsm) | (ap_ST_st61_fsm_61 == ap_CS_fsm) | (ap_ST_st63_fsm_63 == ap_CS_fsm) | (ap_ST_st65_fsm_65 == ap_CS_fsm) | (ap_ST_st67_fsm_67 == ap_CS_fsm) | (ap_ST_st69_fsm_69 == ap_CS_fsm) | (ap_ST_st71_fsm_71 == ap_CS_fsm) | (ap_ST_st73_fsm_73 == ap_CS_fsm) | (ap_ST_st75_fsm_75 == ap_CS_fsm) | (ap_ST_st77_fsm_77 == ap_CS_fsm) | (ap_ST_st79_fsm_79 == ap_CS_fsm) | (ap_ST_st81_fsm_81 == ap_CS_fsm) | (ap_ST_st83_fsm_83 == ap_CS_fsm) | (ap_ST_st85_fsm_85 == ap_CS_fsm) | (ap_ST_st87_fsm_87 == ap_CS_fsm) | (ap_ST_st89_fsm_89 == ap_CS_fsm) | (ap_ST_st91_fsm_91 == ap_CS_fsm) | (ap_ST_st93_fsm_93 == ap_CS_fsm) | (ap_ST_st95_fsm_95 == ap_CS_fsm) | (ap_ST_st97_fsm_97 == ap_CS_fsm) | (ap_ST_st99_fsm_99 == ap_CS_fsm) | (ap_ST_st101_fsm_101 == ap_CS_fsm) | (ap_ST_st103_fsm_103 == ap_CS_fsm) | (ap_ST_st105_fsm_105 == ap_CS_fsm) | (ap_ST_st107_fsm_107 == ap_CS_fsm) | (ap_ST_st109_fsm_109 == ap_CS_fsm) | (ap_ST_st111_fsm_111 == ap_CS_fsm) | (ap_ST_st113_fsm_113 == ap_CS_fsm) | (ap_ST_st115_fsm_115 == ap_CS_fsm) | (ap_ST_st117_fsm_117 == ap_CS_fsm) | (ap_ST_st119_fsm_119 == ap_CS_fsm) | (ap_ST_st9_fsm_9 == ap_CS_fsm) | (ap_ST_st11_fsm_11 == ap_CS_fsm) | (ap_ST_st13_fsm_13 == ap_CS_fsm) | (ap_ST_st5_fsm_5 == ap_CS_fsm) | (ap_ST_st7_fsm_7 == ap_CS_fsm) | (ap_ST_st1_fsm_1 == ap_CS_fsm) | (ap_ST_st3_fsm_3 == ap_CS_fsm))) begin
grp_uFetch_array_fu_583_ap_start = ap_const_logic_1;
end else begin
grp_uFetch_array_fu_583_ap_start = ap_const_logic_0;
end
end
/// grp_write_array_fu_571_ap_start assign process. ///
always @ (ap_CS_fsm)
begin
if (((ap_ST_st17_fsm_17 == ap_CS_fsm) | (ap_ST_st19_fsm_19 == ap_CS_fsm) | (ap_ST_st21_fsm_21 == ap_CS_fsm) | (ap_ST_st23_fsm_23 == ap_CS_fsm) | (ap_ST_st25_fsm_25 == ap_CS_fsm) | (ap_ST_st27_fsm_27 == ap_CS_fsm) | (ap_ST_st29_fsm_29 == ap_CS_fsm) | (ap_ST_st31_fsm_31 == ap_CS_fsm) | (ap_ST_st33_fsm_33 == ap_CS_fsm) | (ap_ST_st35_fsm_35 == ap_CS_fsm) | (ap_ST_st37_fsm_37 == ap_CS_fsm) | (ap_ST_st39_fsm_39 == ap_CS_fsm) | (ap_ST_st41_fsm_41 == ap_CS_fsm) | (ap_ST_st43_fsm_43 == ap_CS_fsm) | (ap_ST_st45_fsm_45 == ap_CS_fsm) | (ap_ST_st47_fsm_47 == ap_CS_fsm) | (ap_ST_st49_fsm_49 == ap_CS_fsm) | (ap_ST_st51_fsm_51 == ap_CS_fsm) | (ap_ST_st53_fsm_53 == ap_CS_fsm) | (ap_ST_st55_fsm_55 == ap_CS_fsm) | (ap_ST_st57_fsm_57 == ap_CS_fsm) | (ap_ST_st59_fsm_59 == ap_CS_fsm) | (ap_ST_st61_fsm_61 == ap_CS_fsm) | (ap_ST_st63_fsm_63 == ap_CS_fsm) | (ap_ST_st65_fsm_65 == ap_CS_fsm) | (ap_ST_st67_fsm_67 == ap_CS_fsm) | (ap_ST_st69_fsm_69 == ap_CS_fsm) | (ap_ST_st71_fsm_71 == ap_CS_fsm) | (ap_ST_st73_fsm_73 == ap_CS_fsm) | (ap_ST_st75_fsm_75 == ap_CS_fsm) | (ap_ST_st77_fsm_77 == ap_CS_fsm) | (ap_ST_st79_fsm_79 == ap_CS_fsm) | (ap_ST_st81_fsm_81 == ap_CS_fsm) | (ap_ST_st83_fsm_83 == ap_CS_fsm) | (ap_ST_st85_fsm_85 == ap_CS_fsm) | (ap_ST_st87_fsm_87 == ap_CS_fsm) | (ap_ST_st89_fsm_89 == ap_CS_fsm) | (ap_ST_st91_fsm_91 == ap_CS_fsm) | (ap_ST_st93_fsm_93 == ap_CS_fsm) | (ap_ST_st95_fsm_95 == ap_CS_fsm) | (ap_ST_st97_fsm_97 == ap_CS_fsm) | (ap_ST_st99_fsm_99 == ap_CS_fsm) | (ap_ST_st101_fsm_101 == ap_CS_fsm) | (ap_ST_st103_fsm_103 == ap_CS_fsm) | (ap_ST_st105_fsm_105 == ap_CS_fsm) | (ap_ST_st107_fsm_107 == ap_CS_fsm) | (ap_ST_st109_fsm_109 == ap_CS_fsm) | (ap_ST_st111_fsm_111 == ap_CS_fsm) | (ap_ST_st113_fsm_113 == ap_CS_fsm) | (ap_ST_st115_fsm_115 == ap_CS_fsm) | (ap_ST_st117_fsm_117 == ap_CS_fsm) | (ap_ST_st119_fsm_119 == ap_CS_fsm) | (ap_ST_st121_fsm_121 == ap_CS_fsm) | (ap_ST_st123_fsm_123 == ap_CS_fsm) | (ap_ST_st125_fsm_125 == ap_CS_fsm) | (ap_ST_st127_fsm_127 == ap_CS_fsm) | (ap_ST_st129_fsm_129 == ap_CS_fsm) | (ap_ST_st131_fsm_131 == ap_CS_fsm))) begin
grp_write_array_fu_571_ap_start = ap_const_logic_1;
end else begin
grp_write_array_fu_571_ap_start = ap_const_logic_0;
end
end
/// grp_write_array_fu_571_data_p0_q0 assign process. ///
always @ (ap_CS_fsm or r1_p0_q0 or r0_p0_q0)
begin
if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm) | (ap_ST_st128_fsm_128 == ap_CS_fsm) | (ap_ST_st132_fsm_132 == ap_CS_fsm))) begin
grp_write_array_fu_571_data_p0_q0 = r0_p0_q0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st126_fsm_126 == ap_CS_fsm) | (ap_ST_st130_fsm_130 == ap_CS_fsm))) begin
grp_write_array_fu_571_data_p0_q0 = r1_p0_q0;
end else begin
grp_write_array_fu_571_data_p0_q0 = r0_p0_q0;
end
end
/// grp_write_array_fu_571_data_p1_q0 assign process. ///
always @ (ap_CS_fsm or r1_p1_q0 or r0_p1_q0)
begin
if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm) | (ap_ST_st128_fsm_128 == ap_CS_fsm) | (ap_ST_st132_fsm_132 == ap_CS_fsm))) begin
grp_write_array_fu_571_data_p1_q0 = r0_p1_q0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st126_fsm_126 == ap_CS_fsm) | (ap_ST_st130_fsm_130 == ap_CS_fsm))) begin
grp_write_array_fu_571_data_p1_q0 = r1_p1_q0;
end else begin
grp_write_array_fu_571_data_p1_q0 = r0_p1_q0;
end
end
/// grp_write_array_fu_571_data_p2_q0 assign process. ///
always @ (ap_CS_fsm or r1_p2_q0 or r0_p2_q0)
begin
if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm) | (ap_ST_st128_fsm_128 == ap_CS_fsm) | (ap_ST_st132_fsm_132 == ap_CS_fsm))) begin
grp_write_array_fu_571_data_p2_q0 = r0_p2_q0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st126_fsm_126 == ap_CS_fsm) | (ap_ST_st130_fsm_130 == ap_CS_fsm))) begin
grp_write_array_fu_571_data_p2_q0 = r1_p2_q0;
end else begin
grp_write_array_fu_571_data_p2_q0 = r0_p2_q0;
end
end
/// grp_write_array_fu_571_data_p3_q0 assign process. ///
always @ (ap_CS_fsm or r1_p3_q0 or r0_p3_q0)
begin
if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm) | (ap_ST_st128_fsm_128 == ap_CS_fsm) | (ap_ST_st132_fsm_132 == ap_CS_fsm))) begin
grp_write_array_fu_571_data_p3_q0 = r0_p3_q0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st126_fsm_126 == ap_CS_fsm) | (ap_ST_st130_fsm_130 == ap_CS_fsm))) begin
grp_write_array_fu_571_data_p3_q0 = r1_p3_q0;
end else begin
grp_write_array_fu_571_data_p3_q0 = r0_p3_q0;
end
end
/// r0_p0_address0 assign process. ///
always @ (ap_CS_fsm or grp_computeResult_fu_467_r_p0_address0 or grp_write_array_fu_571_data_p0_address0)
begin
if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm) | (ap_ST_st128_fsm_128 == ap_CS_fsm) | (ap_ST_st132_fsm_132 == ap_CS_fsm))) begin
r0_p0_address0 = grp_write_array_fu_571_data_p0_address0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st126_fsm_126 == ap_CS_fsm) | (ap_ST_st130_fsm_130 == ap_CS_fsm))) begin
r0_p0_address0 = grp_computeResult_fu_467_r_p0_address0;
end else begin
r0_p0_address0 = grp_write_array_fu_571_data_p0_address0;
end
end
/// r0_p0_ce0 assign process. ///
always @ (ap_CS_fsm or grp_computeResult_fu_467_r_p0_ce0 or grp_write_array_fu_571_data_p0_ce0)
begin
if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm) | (ap_ST_st128_fsm_128 == ap_CS_fsm) | (ap_ST_st132_fsm_132 == ap_CS_fsm))) begin
r0_p0_ce0 = grp_write_array_fu_571_data_p0_ce0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st126_fsm_126 == ap_CS_fsm) | (ap_ST_st130_fsm_130 == ap_CS_fsm))) begin
r0_p0_ce0 = grp_computeResult_fu_467_r_p0_ce0;
end else begin
r0_p0_ce0 = ap_const_logic_0;
end
end
/// r0_p0_we0 assign process. ///
always @ (ap_CS_fsm or grp_computeResult_fu_467_r_p0_we0)
begin
if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st126_fsm_126 == ap_CS_fsm) | (ap_ST_st130_fsm_130 == ap_CS_fsm))) begin
r0_p0_we0 = grp_computeResult_fu_467_r_p0_we0;
end else begin
r0_p0_we0 = ap_const_logic_0;
end
end
/// r0_p1_address0 assign process. ///
always @ (ap_CS_fsm or grp_computeResult_fu_467_r_p1_address0 or grp_write_array_fu_571_data_p1_address0)
begin
if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm) | (ap_ST_st128_fsm_128 == ap_CS_fsm) | (ap_ST_st132_fsm_132 == ap_CS_fsm))) begin
r0_p1_address0 = grp_write_array_fu_571_data_p1_address0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st126_fsm_126 == ap_CS_fsm) | (ap_ST_st130_fsm_130 == ap_CS_fsm))) begin
r0_p1_address0 = grp_computeResult_fu_467_r_p1_address0;
end else begin
r0_p1_address0 = grp_write_array_fu_571_data_p1_address0;
end
end
/// r0_p1_ce0 assign process. ///
always @ (ap_CS_fsm or grp_computeResult_fu_467_r_p1_ce0 or grp_write_array_fu_571_data_p1_ce0)
begin
if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm) | (ap_ST_st128_fsm_128 == ap_CS_fsm) | (ap_ST_st132_fsm_132 == ap_CS_fsm))) begin
r0_p1_ce0 = grp_write_array_fu_571_data_p1_ce0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st126_fsm_126 == ap_CS_fsm) | (ap_ST_st130_fsm_130 == ap_CS_fsm))) begin
r0_p1_ce0 = grp_computeResult_fu_467_r_p1_ce0;
end else begin
r0_p1_ce0 = ap_const_logic_0;
end
end
/// r0_p1_we0 assign process. ///
always @ (ap_CS_fsm or grp_computeResult_fu_467_r_p1_we0)
begin
if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st126_fsm_126 == ap_CS_fsm) | (ap_ST_st130_fsm_130 == ap_CS_fsm))) begin
r0_p1_we0 = grp_computeResult_fu_467_r_p1_we0;
end else begin
r0_p1_we0 = ap_const_logic_0;
end
end
/// r0_p2_address0 assign process. ///
always @ (ap_CS_fsm or grp_computeResult_fu_467_r_p2_address0 or grp_write_array_fu_571_data_p2_address0)
begin
if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm) | (ap_ST_st128_fsm_128 == ap_CS_fsm) | (ap_ST_st132_fsm_132 == ap_CS_fsm))) begin
r0_p2_address0 = grp_write_array_fu_571_data_p2_address0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st126_fsm_126 == ap_CS_fsm) | (ap_ST_st130_fsm_130 == ap_CS_fsm))) begin
r0_p2_address0 = grp_computeResult_fu_467_r_p2_address0;
end else begin
r0_p2_address0 = grp_write_array_fu_571_data_p2_address0;
end
end
/// r0_p2_ce0 assign process. ///
always @ (ap_CS_fsm or grp_computeResult_fu_467_r_p2_ce0 or grp_write_array_fu_571_data_p2_ce0)
begin
if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm) | (ap_ST_st128_fsm_128 == ap_CS_fsm) | (ap_ST_st132_fsm_132 == ap_CS_fsm))) begin
r0_p2_ce0 = grp_write_array_fu_571_data_p2_ce0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st126_fsm_126 == ap_CS_fsm) | (ap_ST_st130_fsm_130 == ap_CS_fsm))) begin
r0_p2_ce0 = grp_computeResult_fu_467_r_p2_ce0;
end else begin
r0_p2_ce0 = ap_const_logic_0;
end
end
/// r0_p2_we0 assign process. ///
always @ (ap_CS_fsm or grp_computeResult_fu_467_r_p2_we0)
begin
if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st126_fsm_126 == ap_CS_fsm) | (ap_ST_st130_fsm_130 == ap_CS_fsm))) begin
r0_p2_we0 = grp_computeResult_fu_467_r_p2_we0;
end else begin
r0_p2_we0 = ap_const_logic_0;
end
end
/// r0_p3_address0 assign process. ///
always @ (ap_CS_fsm or grp_computeResult_fu_467_r_p3_address0 or grp_write_array_fu_571_data_p3_address0)
begin
if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm) | (ap_ST_st128_fsm_128 == ap_CS_fsm) | (ap_ST_st132_fsm_132 == ap_CS_fsm))) begin
r0_p3_address0 = grp_write_array_fu_571_data_p3_address0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st126_fsm_126 == ap_CS_fsm) | (ap_ST_st130_fsm_130 == ap_CS_fsm))) begin
r0_p3_address0 = grp_computeResult_fu_467_r_p3_address0;
end else begin
r0_p3_address0 = grp_write_array_fu_571_data_p3_address0;
end
end
/// r0_p3_ce0 assign process. ///
always @ (ap_CS_fsm or grp_computeResult_fu_467_r_p3_ce0 or grp_write_array_fu_571_data_p3_ce0)
begin
if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm) | (ap_ST_st128_fsm_128 == ap_CS_fsm) | (ap_ST_st132_fsm_132 == ap_CS_fsm))) begin
r0_p3_ce0 = grp_write_array_fu_571_data_p3_ce0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st126_fsm_126 == ap_CS_fsm) | (ap_ST_st130_fsm_130 == ap_CS_fsm))) begin
r0_p3_ce0 = grp_computeResult_fu_467_r_p3_ce0;
end else begin
r0_p3_ce0 = ap_const_logic_0;
end
end
/// r0_p3_we0 assign process. ///
always @ (ap_CS_fsm or grp_computeResult_fu_467_r_p3_we0)
begin
if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st126_fsm_126 == ap_CS_fsm) | (ap_ST_st130_fsm_130 == ap_CS_fsm))) begin
r0_p3_we0 = grp_computeResult_fu_467_r_p3_we0;
end else begin
r0_p3_we0 = ap_const_logic_0;
end
end
/// r1_p0_address0 assign process. ///
always @ (ap_CS_fsm or grp_computeResult_fu_467_r_p0_address0 or grp_write_array_fu_571_data_p0_address0)
begin
if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st126_fsm_126 == ap_CS_fsm) | (ap_ST_st130_fsm_130 == ap_CS_fsm))) begin
r1_p0_address0 = grp_write_array_fu_571_data_p0_address0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm) | (ap_ST_st128_fsm_128 == ap_CS_fsm))) begin
r1_p0_address0 = grp_computeResult_fu_467_r_p0_address0;
end else begin
r1_p0_address0 = grp_write_array_fu_571_data_p0_address0;
end
end
/// r1_p0_ce0 assign process. ///
always @ (ap_CS_fsm or grp_computeResult_fu_467_r_p0_ce0 or grp_write_array_fu_571_data_p0_ce0)
begin
if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st126_fsm_126 == ap_CS_fsm) | (ap_ST_st130_fsm_130 == ap_CS_fsm))) begin
r1_p0_ce0 = grp_write_array_fu_571_data_p0_ce0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm) | (ap_ST_st128_fsm_128 == ap_CS_fsm))) begin
r1_p0_ce0 = grp_computeResult_fu_467_r_p0_ce0;
end else begin
r1_p0_ce0 = ap_const_logic_0;
end
end
/// r1_p0_we0 assign process. ///
always @ (ap_CS_fsm or grp_computeResult_fu_467_r_p0_we0)
begin
if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm) | (ap_ST_st128_fsm_128 == ap_CS_fsm))) begin
r1_p0_we0 = grp_computeResult_fu_467_r_p0_we0;
end else begin
r1_p0_we0 = ap_const_logic_0;
end
end
/// r1_p1_address0 assign process. ///
always @ (ap_CS_fsm or grp_computeResult_fu_467_r_p1_address0 or grp_write_array_fu_571_data_p1_address0)
begin
if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st126_fsm_126 == ap_CS_fsm) | (ap_ST_st130_fsm_130 == ap_CS_fsm))) begin
r1_p1_address0 = grp_write_array_fu_571_data_p1_address0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm) | (ap_ST_st128_fsm_128 == ap_CS_fsm))) begin
r1_p1_address0 = grp_computeResult_fu_467_r_p1_address0;
end else begin
r1_p1_address0 = grp_write_array_fu_571_data_p1_address0;
end
end
/// r1_p1_ce0 assign process. ///
always @ (ap_CS_fsm or grp_computeResult_fu_467_r_p1_ce0 or grp_write_array_fu_571_data_p1_ce0)
begin
if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st126_fsm_126 == ap_CS_fsm) | (ap_ST_st130_fsm_130 == ap_CS_fsm))) begin
r1_p1_ce0 = grp_write_array_fu_571_data_p1_ce0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm) | (ap_ST_st128_fsm_128 == ap_CS_fsm))) begin
r1_p1_ce0 = grp_computeResult_fu_467_r_p1_ce0;
end else begin
r1_p1_ce0 = ap_const_logic_0;
end
end
/// r1_p1_we0 assign process. ///
always @ (ap_CS_fsm or grp_computeResult_fu_467_r_p1_we0)
begin
if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm) | (ap_ST_st128_fsm_128 == ap_CS_fsm))) begin
r1_p1_we0 = grp_computeResult_fu_467_r_p1_we0;
end else begin
r1_p1_we0 = ap_const_logic_0;
end
end
/// r1_p2_address0 assign process. ///
always @ (ap_CS_fsm or grp_computeResult_fu_467_r_p2_address0 or grp_write_array_fu_571_data_p2_address0)
begin
if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st126_fsm_126 == ap_CS_fsm) | (ap_ST_st130_fsm_130 == ap_CS_fsm))) begin
r1_p2_address0 = grp_write_array_fu_571_data_p2_address0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm) | (ap_ST_st128_fsm_128 == ap_CS_fsm))) begin
r1_p2_address0 = grp_computeResult_fu_467_r_p2_address0;
end else begin
r1_p2_address0 = grp_write_array_fu_571_data_p2_address0;
end
end
/// r1_p2_ce0 assign process. ///
always @ (ap_CS_fsm or grp_computeResult_fu_467_r_p2_ce0 or grp_write_array_fu_571_data_p2_ce0)
begin
if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st126_fsm_126 == ap_CS_fsm) | (ap_ST_st130_fsm_130 == ap_CS_fsm))) begin
r1_p2_ce0 = grp_write_array_fu_571_data_p2_ce0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm) | (ap_ST_st128_fsm_128 == ap_CS_fsm))) begin
r1_p2_ce0 = grp_computeResult_fu_467_r_p2_ce0;
end else begin
r1_p2_ce0 = ap_const_logic_0;
end
end
/// r1_p2_we0 assign process. ///
always @ (ap_CS_fsm or grp_computeResult_fu_467_r_p2_we0)
begin
if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm) | (ap_ST_st128_fsm_128 == ap_CS_fsm))) begin
r1_p2_we0 = grp_computeResult_fu_467_r_p2_we0;
end else begin
r1_p2_we0 = ap_const_logic_0;
end
end
/// r1_p3_address0 assign process. ///
always @ (ap_CS_fsm or grp_computeResult_fu_467_r_p3_address0 or grp_write_array_fu_571_data_p3_address0)
begin
if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st126_fsm_126 == ap_CS_fsm) | (ap_ST_st130_fsm_130 == ap_CS_fsm))) begin
r1_p3_address0 = grp_write_array_fu_571_data_p3_address0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm) | (ap_ST_st128_fsm_128 == ap_CS_fsm))) begin
r1_p3_address0 = grp_computeResult_fu_467_r_p3_address0;
end else begin
r1_p3_address0 = grp_write_array_fu_571_data_p3_address0;
end
end
/// r1_p3_ce0 assign process. ///
always @ (ap_CS_fsm or grp_computeResult_fu_467_r_p3_ce0 or grp_write_array_fu_571_data_p3_ce0)
begin
if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st126_fsm_126 == ap_CS_fsm) | (ap_ST_st130_fsm_130 == ap_CS_fsm))) begin
r1_p3_ce0 = grp_write_array_fu_571_data_p3_ce0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm) | (ap_ST_st128_fsm_128 == ap_CS_fsm))) begin
r1_p3_ce0 = grp_computeResult_fu_467_r_p3_ce0;
end else begin
r1_p3_ce0 = ap_const_logic_0;
end
end
/// r1_p3_we0 assign process. ///
always @ (ap_CS_fsm or grp_computeResult_fu_467_r_p3_we0)
begin
if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm) | (ap_ST_st128_fsm_128 == ap_CS_fsm))) begin
r1_p3_we0 = grp_computeResult_fu_467_r_p3_we0;
end else begin
r1_p3_we0 = ap_const_logic_0;
end
end
/// sm0_p0_address0 assign process. ///
always @ (ap_CS_fsm or grp_computeGradient_fu_507_sm0_p0_address0 or grp_computeDiffSqr_fu_531_sm_p0_address0)
begin
if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st10_fsm_10 == ap_CS_fsm) | (ap_ST_st14_fsm_14 == ap_CS_fsm) | (ap_ST_st6_fsm_6 == ap_CS_fsm))) begin
sm0_p0_address0 = grp_computeDiffSqr_fu_531_sm_p0_address0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm) | (ap_ST_st12_fsm_12 == ap_CS_fsm))) begin
sm0_p0_address0 = grp_computeGradient_fu_507_sm0_p0_address0;
end else begin
sm0_p0_address0 = grp_computeDiffSqr_fu_531_sm_p0_address0;
end
end
/// sm0_p0_ce0 assign process. ///
always @ (ap_CS_fsm or grp_computeGradient_fu_507_sm0_p0_ce0 or grp_computeDiffSqr_fu_531_sm_p0_ce0)
begin
if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st10_fsm_10 == ap_CS_fsm) | (ap_ST_st14_fsm_14 == ap_CS_fsm) | (ap_ST_st6_fsm_6 == ap_CS_fsm))) begin
sm0_p0_ce0 = grp_computeDiffSqr_fu_531_sm_p0_ce0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm) | (ap_ST_st12_fsm_12 == ap_CS_fsm))) begin
sm0_p0_ce0 = grp_computeGradient_fu_507_sm0_p0_ce0;
end else begin
sm0_p0_ce0 = ap_const_logic_0;
end
end
/// sm0_p0_we0 assign process. ///
always @ (ap_CS_fsm or grp_computeDiffSqr_fu_531_sm_p0_we0)
begin
if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st10_fsm_10 == ap_CS_fsm) | (ap_ST_st14_fsm_14 == ap_CS_fsm) | (ap_ST_st6_fsm_6 == ap_CS_fsm))) begin
sm0_p0_we0 = grp_computeDiffSqr_fu_531_sm_p0_we0;
end else begin
sm0_p0_we0 = ap_const_logic_0;
end
end
/// sm0_p1_address0 assign process. ///
always @ (ap_CS_fsm or grp_computeGradient_fu_507_sm0_p1_address0 or grp_computeDiffSqr_fu_531_sm_p1_address0)
begin
if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st10_fsm_10 == ap_CS_fsm) | (ap_ST_st14_fsm_14 == ap_CS_fsm) | (ap_ST_st6_fsm_6 == ap_CS_fsm))) begin
sm0_p1_address0 = grp_computeDiffSqr_fu_531_sm_p1_address0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm) | (ap_ST_st12_fsm_12 == ap_CS_fsm))) begin
sm0_p1_address0 = grp_computeGradient_fu_507_sm0_p1_address0;
end else begin
sm0_p1_address0 = grp_computeDiffSqr_fu_531_sm_p1_address0;
end
end
/// sm0_p1_ce0 assign process. ///
always @ (ap_CS_fsm or grp_computeGradient_fu_507_sm0_p1_ce0 or grp_computeDiffSqr_fu_531_sm_p1_ce0)
begin
if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st10_fsm_10 == ap_CS_fsm) | (ap_ST_st14_fsm_14 == ap_CS_fsm) | (ap_ST_st6_fsm_6 == ap_CS_fsm))) begin
sm0_p1_ce0 = grp_computeDiffSqr_fu_531_sm_p1_ce0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm) | (ap_ST_st12_fsm_12 == ap_CS_fsm))) begin
sm0_p1_ce0 = grp_computeGradient_fu_507_sm0_p1_ce0;
end else begin
sm0_p1_ce0 = ap_const_logic_0;
end
end
/// sm0_p1_we0 assign process. ///
always @ (ap_CS_fsm or grp_computeDiffSqr_fu_531_sm_p1_we0)
begin
if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st10_fsm_10 == ap_CS_fsm) | (ap_ST_st14_fsm_14 == ap_CS_fsm) | (ap_ST_st6_fsm_6 == ap_CS_fsm))) begin
sm0_p1_we0 = grp_computeDiffSqr_fu_531_sm_p1_we0;
end else begin
sm0_p1_we0 = ap_const_logic_0;
end
end
/// sm0_p2_address0 assign process. ///
always @ (ap_CS_fsm or grp_computeGradient_fu_507_sm0_p2_address0 or grp_computeDiffSqr_fu_531_sm_p2_address0)
begin
if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st10_fsm_10 == ap_CS_fsm) | (ap_ST_st14_fsm_14 == ap_CS_fsm) | (ap_ST_st6_fsm_6 == ap_CS_fsm))) begin
sm0_p2_address0 = grp_computeDiffSqr_fu_531_sm_p2_address0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm) | (ap_ST_st12_fsm_12 == ap_CS_fsm))) begin
sm0_p2_address0 = grp_computeGradient_fu_507_sm0_p2_address0;
end else begin
sm0_p2_address0 = grp_computeDiffSqr_fu_531_sm_p2_address0;
end
end
/// sm0_p2_ce0 assign process. ///
always @ (ap_CS_fsm or grp_computeGradient_fu_507_sm0_p2_ce0 or grp_computeDiffSqr_fu_531_sm_p2_ce0)
begin
if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st10_fsm_10 == ap_CS_fsm) | (ap_ST_st14_fsm_14 == ap_CS_fsm) | (ap_ST_st6_fsm_6 == ap_CS_fsm))) begin
sm0_p2_ce0 = grp_computeDiffSqr_fu_531_sm_p2_ce0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm) | (ap_ST_st12_fsm_12 == ap_CS_fsm))) begin
sm0_p2_ce0 = grp_computeGradient_fu_507_sm0_p2_ce0;
end else begin
sm0_p2_ce0 = ap_const_logic_0;
end
end
/// sm0_p2_we0 assign process. ///
always @ (ap_CS_fsm or grp_computeDiffSqr_fu_531_sm_p2_we0)
begin
if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st10_fsm_10 == ap_CS_fsm) | (ap_ST_st14_fsm_14 == ap_CS_fsm) | (ap_ST_st6_fsm_6 == ap_CS_fsm))) begin
sm0_p2_we0 = grp_computeDiffSqr_fu_531_sm_p2_we0;
end else begin
sm0_p2_we0 = ap_const_logic_0;
end
end
/// sm0_p3_address0 assign process. ///
always @ (ap_CS_fsm or grp_computeGradient_fu_507_sm0_p3_address0 or grp_computeDiffSqr_fu_531_sm_p3_address0)
begin
if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st10_fsm_10 == ap_CS_fsm) | (ap_ST_st14_fsm_14 == ap_CS_fsm) | (ap_ST_st6_fsm_6 == ap_CS_fsm))) begin
sm0_p3_address0 = grp_computeDiffSqr_fu_531_sm_p3_address0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm) | (ap_ST_st12_fsm_12 == ap_CS_fsm))) begin
sm0_p3_address0 = grp_computeGradient_fu_507_sm0_p3_address0;
end else begin
sm0_p3_address0 = grp_computeDiffSqr_fu_531_sm_p3_address0;
end
end
/// sm0_p3_ce0 assign process. ///
always @ (ap_CS_fsm or grp_computeGradient_fu_507_sm0_p3_ce0 or grp_computeDiffSqr_fu_531_sm_p3_ce0)
begin
if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st10_fsm_10 == ap_CS_fsm) | (ap_ST_st14_fsm_14 == ap_CS_fsm) | (ap_ST_st6_fsm_6 == ap_CS_fsm))) begin
sm0_p3_ce0 = grp_computeDiffSqr_fu_531_sm_p3_ce0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm) | (ap_ST_st12_fsm_12 == ap_CS_fsm))) begin
sm0_p3_ce0 = grp_computeGradient_fu_507_sm0_p3_ce0;
end else begin
sm0_p3_ce0 = ap_const_logic_0;
end
end
/// sm0_p3_we0 assign process. ///
always @ (ap_CS_fsm or grp_computeDiffSqr_fu_531_sm_p3_we0)
begin
if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st10_fsm_10 == ap_CS_fsm) | (ap_ST_st14_fsm_14 == ap_CS_fsm) | (ap_ST_st6_fsm_6 == ap_CS_fsm))) begin
sm0_p3_we0 = grp_computeDiffSqr_fu_531_sm_p3_we0;
end else begin
sm0_p3_we0 = ap_const_logic_0;
end
end
/// sm1_p0_address0 assign process. ///
always @ (ap_CS_fsm or grp_computeGradient_fu_507_sm0_p0_address0 or grp_computeDiffSqr_fu_531_sm_p0_address0)
begin
if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st12_fsm_12 == ap_CS_fsm) | (ap_ST_st8_fsm_8 == ap_CS_fsm))) begin
sm1_p0_address0 = grp_computeDiffSqr_fu_531_sm_p0_address0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st10_fsm_10 == ap_CS_fsm) | (ap_ST_st14_fsm_14 == ap_CS_fsm))) begin
sm1_p0_address0 = grp_computeGradient_fu_507_sm0_p0_address0;
end else begin
sm1_p0_address0 = grp_computeDiffSqr_fu_531_sm_p0_address0;
end
end
/// sm1_p0_ce0 assign process. ///
always @ (ap_CS_fsm or grp_computeGradient_fu_507_sm0_p0_ce0 or grp_computeDiffSqr_fu_531_sm_p0_ce0)
begin
if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st12_fsm_12 == ap_CS_fsm) | (ap_ST_st8_fsm_8 == ap_CS_fsm))) begin
sm1_p0_ce0 = grp_computeDiffSqr_fu_531_sm_p0_ce0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st10_fsm_10 == ap_CS_fsm) | (ap_ST_st14_fsm_14 == ap_CS_fsm))) begin
sm1_p0_ce0 = grp_computeGradient_fu_507_sm0_p0_ce0;
end else begin
sm1_p0_ce0 = ap_const_logic_0;
end
end
/// sm1_p0_we0 assign process. ///
always @ (ap_CS_fsm or grp_computeDiffSqr_fu_531_sm_p0_we0)
begin
if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st12_fsm_12 == ap_CS_fsm) | (ap_ST_st8_fsm_8 == ap_CS_fsm))) begin
sm1_p0_we0 = grp_computeDiffSqr_fu_531_sm_p0_we0;
end else begin
sm1_p0_we0 = ap_const_logic_0;
end
end
/// sm1_p1_address0 assign process. ///
always @ (ap_CS_fsm or grp_computeGradient_fu_507_sm0_p1_address0 or grp_computeDiffSqr_fu_531_sm_p1_address0)
begin
if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st12_fsm_12 == ap_CS_fsm) | (ap_ST_st8_fsm_8 == ap_CS_fsm))) begin
sm1_p1_address0 = grp_computeDiffSqr_fu_531_sm_p1_address0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st10_fsm_10 == ap_CS_fsm) | (ap_ST_st14_fsm_14 == ap_CS_fsm))) begin
sm1_p1_address0 = grp_computeGradient_fu_507_sm0_p1_address0;
end else begin
sm1_p1_address0 = grp_computeDiffSqr_fu_531_sm_p1_address0;
end
end
/// sm1_p1_ce0 assign process. ///
always @ (ap_CS_fsm or grp_computeGradient_fu_507_sm0_p1_ce0 or grp_computeDiffSqr_fu_531_sm_p1_ce0)
begin
if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st12_fsm_12 == ap_CS_fsm) | (ap_ST_st8_fsm_8 == ap_CS_fsm))) begin
sm1_p1_ce0 = grp_computeDiffSqr_fu_531_sm_p1_ce0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st10_fsm_10 == ap_CS_fsm) | (ap_ST_st14_fsm_14 == ap_CS_fsm))) begin
sm1_p1_ce0 = grp_computeGradient_fu_507_sm0_p1_ce0;
end else begin
sm1_p1_ce0 = ap_const_logic_0;
end
end
/// sm1_p1_we0 assign process. ///
always @ (ap_CS_fsm or grp_computeDiffSqr_fu_531_sm_p1_we0)
begin
if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st12_fsm_12 == ap_CS_fsm) | (ap_ST_st8_fsm_8 == ap_CS_fsm))) begin
sm1_p1_we0 = grp_computeDiffSqr_fu_531_sm_p1_we0;
end else begin
sm1_p1_we0 = ap_const_logic_0;
end
end
/// sm1_p2_address0 assign process. ///
always @ (ap_CS_fsm or grp_computeGradient_fu_507_sm0_p2_address0 or grp_computeDiffSqr_fu_531_sm_p2_address0)
begin
if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st12_fsm_12 == ap_CS_fsm) | (ap_ST_st8_fsm_8 == ap_CS_fsm))) begin
sm1_p2_address0 = grp_computeDiffSqr_fu_531_sm_p2_address0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st10_fsm_10 == ap_CS_fsm) | (ap_ST_st14_fsm_14 == ap_CS_fsm))) begin
sm1_p2_address0 = grp_computeGradient_fu_507_sm0_p2_address0;
end else begin
sm1_p2_address0 = grp_computeDiffSqr_fu_531_sm_p2_address0;
end
end
/// sm1_p2_ce0 assign process. ///
always @ (ap_CS_fsm or grp_computeGradient_fu_507_sm0_p2_ce0 or grp_computeDiffSqr_fu_531_sm_p2_ce0)
begin
if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st12_fsm_12 == ap_CS_fsm) | (ap_ST_st8_fsm_8 == ap_CS_fsm))) begin
sm1_p2_ce0 = grp_computeDiffSqr_fu_531_sm_p2_ce0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st10_fsm_10 == ap_CS_fsm) | (ap_ST_st14_fsm_14 == ap_CS_fsm))) begin
sm1_p2_ce0 = grp_computeGradient_fu_507_sm0_p2_ce0;
end else begin
sm1_p2_ce0 = ap_const_logic_0;
end
end
/// sm1_p2_we0 assign process. ///
always @ (ap_CS_fsm or grp_computeDiffSqr_fu_531_sm_p2_we0)
begin
if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st12_fsm_12 == ap_CS_fsm) | (ap_ST_st8_fsm_8 == ap_CS_fsm))) begin
sm1_p2_we0 = grp_computeDiffSqr_fu_531_sm_p2_we0;
end else begin
sm1_p2_we0 = ap_const_logic_0;
end
end
/// sm1_p3_address0 assign process. ///
always @ (ap_CS_fsm or grp_computeGradient_fu_507_sm0_p3_address0 or grp_computeDiffSqr_fu_531_sm_p3_address0)
begin
if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st12_fsm_12 == ap_CS_fsm) | (ap_ST_st8_fsm_8 == ap_CS_fsm))) begin
sm1_p3_address0 = grp_computeDiffSqr_fu_531_sm_p3_address0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st10_fsm_10 == ap_CS_fsm) | (ap_ST_st14_fsm_14 == ap_CS_fsm))) begin
sm1_p3_address0 = grp_computeGradient_fu_507_sm0_p3_address0;
end else begin
sm1_p3_address0 = grp_computeDiffSqr_fu_531_sm_p3_address0;
end
end
/// sm1_p3_ce0 assign process. ///
always @ (ap_CS_fsm or grp_computeGradient_fu_507_sm0_p3_ce0 or grp_computeDiffSqr_fu_531_sm_p3_ce0)
begin
if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st12_fsm_12 == ap_CS_fsm) | (ap_ST_st8_fsm_8 == ap_CS_fsm))) begin
sm1_p3_ce0 = grp_computeDiffSqr_fu_531_sm_p3_ce0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st10_fsm_10 == ap_CS_fsm) | (ap_ST_st14_fsm_14 == ap_CS_fsm))) begin
sm1_p3_ce0 = grp_computeGradient_fu_507_sm0_p3_ce0;
end else begin
sm1_p3_ce0 = ap_const_logic_0;
end
end
/// sm1_p3_we0 assign process. ///
always @ (ap_CS_fsm or grp_computeDiffSqr_fu_531_sm_p3_we0)
begin
if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st12_fsm_12 == ap_CS_fsm) | (ap_ST_st8_fsm_8 == ap_CS_fsm))) begin
sm1_p3_we0 = grp_computeDiffSqr_fu_531_sm_p3_we0;
end else begin
sm1_p3_we0 = ap_const_logic_0;
end
end
/// sn0_p0_address0 assign process. ///
always @ (ap_CS_fsm or grp_computeGradient_fu_507_sn0_p0_address0 or grp_computeDiffSqr_fu_531_sn_p0_address0)
begin
if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st10_fsm_10 == ap_CS_fsm) | (ap_ST_st14_fsm_14 == ap_CS_fsm) | (ap_ST_st6_fsm_6 == ap_CS_fsm))) begin
sn0_p0_address0 = grp_computeDiffSqr_fu_531_sn_p0_address0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm) | (ap_ST_st12_fsm_12 == ap_CS_fsm))) begin
sn0_p0_address0 = grp_computeGradient_fu_507_sn0_p0_address0;
end else begin
sn0_p0_address0 = grp_computeDiffSqr_fu_531_sn_p0_address0;
end
end
/// sn0_p0_ce0 assign process. ///
always @ (ap_CS_fsm or grp_computeGradient_fu_507_sn0_p0_ce0 or grp_computeDiffSqr_fu_531_sn_p0_ce0)
begin
if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st10_fsm_10 == ap_CS_fsm) | (ap_ST_st14_fsm_14 == ap_CS_fsm) | (ap_ST_st6_fsm_6 == ap_CS_fsm))) begin
sn0_p0_ce0 = grp_computeDiffSqr_fu_531_sn_p0_ce0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm) | (ap_ST_st12_fsm_12 == ap_CS_fsm))) begin
sn0_p0_ce0 = grp_computeGradient_fu_507_sn0_p0_ce0;
end else begin
sn0_p0_ce0 = ap_const_logic_0;
end
end
/// sn0_p0_ce1 assign process. ///
always @ (ap_CS_fsm or grp_computeGradient_fu_507_sn0_p0_ce1)
begin
if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm) | (ap_ST_st12_fsm_12 == ap_CS_fsm))) begin
sn0_p0_ce1 = grp_computeGradient_fu_507_sn0_p0_ce1;
end else begin
sn0_p0_ce1 = ap_const_logic_0;
end
end
/// sn0_p0_we0 assign process. ///
always @ (ap_CS_fsm or grp_computeDiffSqr_fu_531_sn_p0_we0)
begin
if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st10_fsm_10 == ap_CS_fsm) | (ap_ST_st14_fsm_14 == ap_CS_fsm) | (ap_ST_st6_fsm_6 == ap_CS_fsm))) begin
sn0_p0_we0 = grp_computeDiffSqr_fu_531_sn_p0_we0;
end else begin
sn0_p0_we0 = ap_const_logic_0;
end
end
/// sn0_p1_address0 assign process. ///
always @ (ap_CS_fsm or grp_computeGradient_fu_507_sn0_p1_address0 or grp_computeDiffSqr_fu_531_sn_p1_address0)
begin
if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st10_fsm_10 == ap_CS_fsm) | (ap_ST_st14_fsm_14 == ap_CS_fsm) | (ap_ST_st6_fsm_6 == ap_CS_fsm))) begin
sn0_p1_address0 = grp_computeDiffSqr_fu_531_sn_p1_address0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm) | (ap_ST_st12_fsm_12 == ap_CS_fsm))) begin
sn0_p1_address0 = grp_computeGradient_fu_507_sn0_p1_address0;
end else begin
sn0_p1_address0 = grp_computeDiffSqr_fu_531_sn_p1_address0;
end
end
/// sn0_p1_ce0 assign process. ///
always @ (ap_CS_fsm or grp_computeGradient_fu_507_sn0_p1_ce0 or grp_computeDiffSqr_fu_531_sn_p1_ce0)
begin
if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st10_fsm_10 == ap_CS_fsm) | (ap_ST_st14_fsm_14 == ap_CS_fsm) | (ap_ST_st6_fsm_6 == ap_CS_fsm))) begin
sn0_p1_ce0 = grp_computeDiffSqr_fu_531_sn_p1_ce0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm) | (ap_ST_st12_fsm_12 == ap_CS_fsm))) begin
sn0_p1_ce0 = grp_computeGradient_fu_507_sn0_p1_ce0;
end else begin
sn0_p1_ce0 = ap_const_logic_0;
end
end
/// sn0_p1_we0 assign process. ///
always @ (ap_CS_fsm or grp_computeDiffSqr_fu_531_sn_p1_we0)
begin
if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st10_fsm_10 == ap_CS_fsm) | (ap_ST_st14_fsm_14 == ap_CS_fsm) | (ap_ST_st6_fsm_6 == ap_CS_fsm))) begin
sn0_p1_we0 = grp_computeDiffSqr_fu_531_sn_p1_we0;
end else begin
sn0_p1_we0 = ap_const_logic_0;
end
end
/// sn0_p2_address0 assign process. ///
always @ (ap_CS_fsm or grp_computeGradient_fu_507_sn0_p2_address0 or grp_computeDiffSqr_fu_531_sn_p2_address0)
begin
if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st10_fsm_10 == ap_CS_fsm) | (ap_ST_st14_fsm_14 == ap_CS_fsm) | (ap_ST_st6_fsm_6 == ap_CS_fsm))) begin
sn0_p2_address0 = grp_computeDiffSqr_fu_531_sn_p2_address0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm) | (ap_ST_st12_fsm_12 == ap_CS_fsm))) begin
sn0_p2_address0 = grp_computeGradient_fu_507_sn0_p2_address0;
end else begin
sn0_p2_address0 = grp_computeDiffSqr_fu_531_sn_p2_address0;
end
end
/// sn0_p2_ce0 assign process. ///
always @ (ap_CS_fsm or grp_computeGradient_fu_507_sn0_p2_ce0 or grp_computeDiffSqr_fu_531_sn_p2_ce0)
begin
if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st10_fsm_10 == ap_CS_fsm) | (ap_ST_st14_fsm_14 == ap_CS_fsm) | (ap_ST_st6_fsm_6 == ap_CS_fsm))) begin
sn0_p2_ce0 = grp_computeDiffSqr_fu_531_sn_p2_ce0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm) | (ap_ST_st12_fsm_12 == ap_CS_fsm))) begin
sn0_p2_ce0 = grp_computeGradient_fu_507_sn0_p2_ce0;
end else begin
sn0_p2_ce0 = ap_const_logic_0;
end
end
/// sn0_p2_we0 assign process. ///
always @ (ap_CS_fsm or grp_computeDiffSqr_fu_531_sn_p2_we0)
begin
if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st10_fsm_10 == ap_CS_fsm) | (ap_ST_st14_fsm_14 == ap_CS_fsm) | (ap_ST_st6_fsm_6 == ap_CS_fsm))) begin
sn0_p2_we0 = grp_computeDiffSqr_fu_531_sn_p2_we0;
end else begin
sn0_p2_we0 = ap_const_logic_0;
end
end
/// sn0_p3_address0 assign process. ///
always @ (ap_CS_fsm or grp_computeGradient_fu_507_sn0_p3_address0 or grp_computeDiffSqr_fu_531_sn_p3_address0)
begin
if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st10_fsm_10 == ap_CS_fsm) | (ap_ST_st14_fsm_14 == ap_CS_fsm) | (ap_ST_st6_fsm_6 == ap_CS_fsm))) begin
sn0_p3_address0 = grp_computeDiffSqr_fu_531_sn_p3_address0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm) | (ap_ST_st12_fsm_12 == ap_CS_fsm))) begin
sn0_p3_address0 = grp_computeGradient_fu_507_sn0_p3_address0;
end else begin
sn0_p3_address0 = grp_computeDiffSqr_fu_531_sn_p3_address0;
end
end
/// sn0_p3_ce0 assign process. ///
always @ (ap_CS_fsm or grp_computeGradient_fu_507_sn0_p3_ce0 or grp_computeDiffSqr_fu_531_sn_p3_ce0)
begin
if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st10_fsm_10 == ap_CS_fsm) | (ap_ST_st14_fsm_14 == ap_CS_fsm) | (ap_ST_st6_fsm_6 == ap_CS_fsm))) begin
sn0_p3_ce0 = grp_computeDiffSqr_fu_531_sn_p3_ce0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm) | (ap_ST_st12_fsm_12 == ap_CS_fsm))) begin
sn0_p3_ce0 = grp_computeGradient_fu_507_sn0_p3_ce0;
end else begin
sn0_p3_ce0 = ap_const_logic_0;
end
end
/// sn0_p3_we0 assign process. ///
always @ (ap_CS_fsm or grp_computeDiffSqr_fu_531_sn_p3_we0)
begin
if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st10_fsm_10 == ap_CS_fsm) | (ap_ST_st14_fsm_14 == ap_CS_fsm) | (ap_ST_st6_fsm_6 == ap_CS_fsm))) begin
sn0_p3_we0 = grp_computeDiffSqr_fu_531_sn_p3_we0;
end else begin
sn0_p3_we0 = ap_const_logic_0;
end
end
/// sn1_p0_address0 assign process. ///
always @ (ap_CS_fsm or grp_computeGradient_fu_507_sn0_p0_address0 or grp_computeDiffSqr_fu_531_sn_p0_address0)
begin
if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st12_fsm_12 == ap_CS_fsm) | (ap_ST_st8_fsm_8 == ap_CS_fsm))) begin
sn1_p0_address0 = grp_computeDiffSqr_fu_531_sn_p0_address0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st10_fsm_10 == ap_CS_fsm) | (ap_ST_st14_fsm_14 == ap_CS_fsm))) begin
sn1_p0_address0 = grp_computeGradient_fu_507_sn0_p0_address0;
end else begin
sn1_p0_address0 = grp_computeDiffSqr_fu_531_sn_p0_address0;
end
end
/// sn1_p0_ce0 assign process. ///
always @ (ap_CS_fsm or grp_computeGradient_fu_507_sn0_p0_ce0 or grp_computeDiffSqr_fu_531_sn_p0_ce0)
begin
if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st12_fsm_12 == ap_CS_fsm) | (ap_ST_st8_fsm_8 == ap_CS_fsm))) begin
sn1_p0_ce0 = grp_computeDiffSqr_fu_531_sn_p0_ce0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st10_fsm_10 == ap_CS_fsm) | (ap_ST_st14_fsm_14 == ap_CS_fsm))) begin
sn1_p0_ce0 = grp_computeGradient_fu_507_sn0_p0_ce0;
end else begin
sn1_p0_ce0 = ap_const_logic_0;
end
end
/// sn1_p0_ce1 assign process. ///
always @ (ap_CS_fsm or grp_computeGradient_fu_507_sn0_p0_ce1)
begin
if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st10_fsm_10 == ap_CS_fsm) | (ap_ST_st14_fsm_14 == ap_CS_fsm))) begin
sn1_p0_ce1 = grp_computeGradient_fu_507_sn0_p0_ce1;
end else begin
sn1_p0_ce1 = ap_const_logic_0;
end
end
/// sn1_p0_we0 assign process. ///
always @ (ap_CS_fsm or grp_computeDiffSqr_fu_531_sn_p0_we0)
begin
if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st12_fsm_12 == ap_CS_fsm) | (ap_ST_st8_fsm_8 == ap_CS_fsm))) begin
sn1_p0_we0 = grp_computeDiffSqr_fu_531_sn_p0_we0;
end else begin
sn1_p0_we0 = ap_const_logic_0;
end
end
/// sn1_p1_address0 assign process. ///
always @ (ap_CS_fsm or grp_computeGradient_fu_507_sn0_p1_address0 or grp_computeDiffSqr_fu_531_sn_p1_address0)
begin
if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st12_fsm_12 == ap_CS_fsm) | (ap_ST_st8_fsm_8 == ap_CS_fsm))) begin
sn1_p1_address0 = grp_computeDiffSqr_fu_531_sn_p1_address0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st10_fsm_10 == ap_CS_fsm) | (ap_ST_st14_fsm_14 == ap_CS_fsm))) begin
sn1_p1_address0 = grp_computeGradient_fu_507_sn0_p1_address0;
end else begin
sn1_p1_address0 = grp_computeDiffSqr_fu_531_sn_p1_address0;
end
end
/// sn1_p1_ce0 assign process. ///
always @ (ap_CS_fsm or grp_computeGradient_fu_507_sn0_p1_ce0 or grp_computeDiffSqr_fu_531_sn_p1_ce0)
begin
if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st12_fsm_12 == ap_CS_fsm) | (ap_ST_st8_fsm_8 == ap_CS_fsm))) begin
sn1_p1_ce0 = grp_computeDiffSqr_fu_531_sn_p1_ce0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st10_fsm_10 == ap_CS_fsm) | (ap_ST_st14_fsm_14 == ap_CS_fsm))) begin
sn1_p1_ce0 = grp_computeGradient_fu_507_sn0_p1_ce0;
end else begin
sn1_p1_ce0 = ap_const_logic_0;
end
end
/// sn1_p1_we0 assign process. ///
always @ (ap_CS_fsm or grp_computeDiffSqr_fu_531_sn_p1_we0)
begin
if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st12_fsm_12 == ap_CS_fsm) | (ap_ST_st8_fsm_8 == ap_CS_fsm))) begin
sn1_p1_we0 = grp_computeDiffSqr_fu_531_sn_p1_we0;
end else begin
sn1_p1_we0 = ap_const_logic_0;
end
end
/// sn1_p2_address0 assign process. ///
always @ (ap_CS_fsm or grp_computeGradient_fu_507_sn0_p2_address0 or grp_computeDiffSqr_fu_531_sn_p2_address0)
begin
if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st12_fsm_12 == ap_CS_fsm) | (ap_ST_st8_fsm_8 == ap_CS_fsm))) begin
sn1_p2_address0 = grp_computeDiffSqr_fu_531_sn_p2_address0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st10_fsm_10 == ap_CS_fsm) | (ap_ST_st14_fsm_14 == ap_CS_fsm))) begin
sn1_p2_address0 = grp_computeGradient_fu_507_sn0_p2_address0;
end else begin
sn1_p2_address0 = grp_computeDiffSqr_fu_531_sn_p2_address0;
end
end
/// sn1_p2_ce0 assign process. ///
always @ (ap_CS_fsm or grp_computeGradient_fu_507_sn0_p2_ce0 or grp_computeDiffSqr_fu_531_sn_p2_ce0)
begin
if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st12_fsm_12 == ap_CS_fsm) | (ap_ST_st8_fsm_8 == ap_CS_fsm))) begin
sn1_p2_ce0 = grp_computeDiffSqr_fu_531_sn_p2_ce0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st10_fsm_10 == ap_CS_fsm) | (ap_ST_st14_fsm_14 == ap_CS_fsm))) begin
sn1_p2_ce0 = grp_computeGradient_fu_507_sn0_p2_ce0;
end else begin
sn1_p2_ce0 = ap_const_logic_0;
end
end
/// sn1_p2_we0 assign process. ///
always @ (ap_CS_fsm or grp_computeDiffSqr_fu_531_sn_p2_we0)
begin
if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st12_fsm_12 == ap_CS_fsm) | (ap_ST_st8_fsm_8 == ap_CS_fsm))) begin
sn1_p2_we0 = grp_computeDiffSqr_fu_531_sn_p2_we0;
end else begin
sn1_p2_we0 = ap_const_logic_0;
end
end
/// sn1_p3_address0 assign process. ///
always @ (ap_CS_fsm or grp_computeGradient_fu_507_sn0_p3_address0 or grp_computeDiffSqr_fu_531_sn_p3_address0)
begin
if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st12_fsm_12 == ap_CS_fsm) | (ap_ST_st8_fsm_8 == ap_CS_fsm))) begin
sn1_p3_address0 = grp_computeDiffSqr_fu_531_sn_p3_address0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st10_fsm_10 == ap_CS_fsm) | (ap_ST_st14_fsm_14 == ap_CS_fsm))) begin
sn1_p3_address0 = grp_computeGradient_fu_507_sn0_p3_address0;
end else begin
sn1_p3_address0 = grp_computeDiffSqr_fu_531_sn_p3_address0;
end
end
/// sn1_p3_ce0 assign process. ///
always @ (ap_CS_fsm or grp_computeGradient_fu_507_sn0_p3_ce0 or grp_computeDiffSqr_fu_531_sn_p3_ce0)
begin
if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st12_fsm_12 == ap_CS_fsm) | (ap_ST_st8_fsm_8 == ap_CS_fsm))) begin
sn1_p3_ce0 = grp_computeDiffSqr_fu_531_sn_p3_ce0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st10_fsm_10 == ap_CS_fsm) | (ap_ST_st14_fsm_14 == ap_CS_fsm))) begin
sn1_p3_ce0 = grp_computeGradient_fu_507_sn0_p3_ce0;
end else begin
sn1_p3_ce0 = ap_const_logic_0;
end
end
/// sn1_p3_we0 assign process. ///
always @ (ap_CS_fsm or grp_computeDiffSqr_fu_531_sn_p3_we0)
begin
if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st12_fsm_12 == ap_CS_fsm) | (ap_ST_st8_fsm_8 == ap_CS_fsm))) begin
sn1_p3_we0 = grp_computeDiffSqr_fu_531_sn_p3_we0;
end else begin
sn1_p3_we0 = ap_const_logic_0;
end
end
/// sp0_p0_address0 assign process. ///
always @ (ap_CS_fsm or grp_computeGradient_fu_507_sp0_p0_address0 or grp_computeGradient_fu_507_sp1_p0_address0 or grp_computeDiffSqr_fu_531_sp_p0_address0)
begin
if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st12_fsm_12 == ap_CS_fsm) | (ap_ST_st6_fsm_6 == ap_CS_fsm))) begin
sp0_p0_address0 = grp_computeDiffSqr_fu_531_sp_p0_address0;
end else if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st14_fsm_14 == ap_CS_fsm))) begin
sp0_p0_address0 = grp_computeGradient_fu_507_sp1_p0_address0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm) | (ap_ST_st10_fsm_10 == ap_CS_fsm))) begin
sp0_p0_address0 = grp_computeGradient_fu_507_sp0_p0_address0;
end else begin
sp0_p0_address0 = grp_computeDiffSqr_fu_531_sp_p0_address0;
end
end
/// sp0_p0_ce0 assign process. ///
always @ (ap_CS_fsm or grp_computeGradient_fu_507_sp0_p0_ce0 or grp_computeGradient_fu_507_sp1_p0_ce0 or grp_computeDiffSqr_fu_531_sp_p0_ce0)
begin
if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st12_fsm_12 == ap_CS_fsm) | (ap_ST_st6_fsm_6 == ap_CS_fsm))) begin
sp0_p0_ce0 = grp_computeDiffSqr_fu_531_sp_p0_ce0;
end else if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st14_fsm_14 == ap_CS_fsm))) begin
sp0_p0_ce0 = grp_computeGradient_fu_507_sp1_p0_ce0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm) | (ap_ST_st10_fsm_10 == ap_CS_fsm))) begin
sp0_p0_ce0 = grp_computeGradient_fu_507_sp0_p0_ce0;
end else begin
sp0_p0_ce0 = ap_const_logic_0;
end
end
/// sp0_p0_we0 assign process. ///
always @ (ap_CS_fsm or grp_computeDiffSqr_fu_531_sp_p0_we0)
begin
if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st12_fsm_12 == ap_CS_fsm) | (ap_ST_st6_fsm_6 == ap_CS_fsm))) begin
sp0_p0_we0 = grp_computeDiffSqr_fu_531_sp_p0_we0;
end else begin
sp0_p0_we0 = ap_const_logic_0;
end
end
/// sp0_p1_address0 assign process. ///
always @ (ap_CS_fsm or grp_computeGradient_fu_507_sp0_p1_address0 or grp_computeGradient_fu_507_sp1_p1_address0 or grp_computeDiffSqr_fu_531_sp_p1_address0)
begin
if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st12_fsm_12 == ap_CS_fsm) | (ap_ST_st6_fsm_6 == ap_CS_fsm))) begin
sp0_p1_address0 = grp_computeDiffSqr_fu_531_sp_p1_address0;
end else if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st14_fsm_14 == ap_CS_fsm))) begin
sp0_p1_address0 = grp_computeGradient_fu_507_sp1_p1_address0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm) | (ap_ST_st10_fsm_10 == ap_CS_fsm))) begin
sp0_p1_address0 = grp_computeGradient_fu_507_sp0_p1_address0;
end else begin
sp0_p1_address0 = grp_computeDiffSqr_fu_531_sp_p1_address0;
end
end
/// sp0_p1_ce0 assign process. ///
always @ (ap_CS_fsm or grp_computeGradient_fu_507_sp0_p1_ce0 or grp_computeGradient_fu_507_sp1_p1_ce0 or grp_computeDiffSqr_fu_531_sp_p1_ce0)
begin
if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st12_fsm_12 == ap_CS_fsm) | (ap_ST_st6_fsm_6 == ap_CS_fsm))) begin
sp0_p1_ce0 = grp_computeDiffSqr_fu_531_sp_p1_ce0;
end else if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st14_fsm_14 == ap_CS_fsm))) begin
sp0_p1_ce0 = grp_computeGradient_fu_507_sp1_p1_ce0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm) | (ap_ST_st10_fsm_10 == ap_CS_fsm))) begin
sp0_p1_ce0 = grp_computeGradient_fu_507_sp0_p1_ce0;
end else begin
sp0_p1_ce0 = ap_const_logic_0;
end
end
/// sp0_p1_we0 assign process. ///
always @ (ap_CS_fsm or grp_computeDiffSqr_fu_531_sp_p1_we0)
begin
if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st12_fsm_12 == ap_CS_fsm) | (ap_ST_st6_fsm_6 == ap_CS_fsm))) begin
sp0_p1_we0 = grp_computeDiffSqr_fu_531_sp_p1_we0;
end else begin
sp0_p1_we0 = ap_const_logic_0;
end
end
/// sp0_p2_address0 assign process. ///
always @ (ap_CS_fsm or grp_computeGradient_fu_507_sp0_p2_address0 or grp_computeGradient_fu_507_sp1_p2_address0 or grp_computeDiffSqr_fu_531_sp_p2_address0)
begin
if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st12_fsm_12 == ap_CS_fsm) | (ap_ST_st6_fsm_6 == ap_CS_fsm))) begin
sp0_p2_address0 = grp_computeDiffSqr_fu_531_sp_p2_address0;
end else if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st14_fsm_14 == ap_CS_fsm))) begin
sp0_p2_address0 = grp_computeGradient_fu_507_sp1_p2_address0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm) | (ap_ST_st10_fsm_10 == ap_CS_fsm))) begin
sp0_p2_address0 = grp_computeGradient_fu_507_sp0_p2_address0;
end else begin
sp0_p2_address0 = grp_computeDiffSqr_fu_531_sp_p2_address0;
end
end
/// sp0_p2_ce0 assign process. ///
always @ (ap_CS_fsm or grp_computeGradient_fu_507_sp0_p2_ce0 or grp_computeGradient_fu_507_sp1_p2_ce0 or grp_computeDiffSqr_fu_531_sp_p2_ce0)
begin
if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st12_fsm_12 == ap_CS_fsm) | (ap_ST_st6_fsm_6 == ap_CS_fsm))) begin
sp0_p2_ce0 = grp_computeDiffSqr_fu_531_sp_p2_ce0;
end else if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st14_fsm_14 == ap_CS_fsm))) begin
sp0_p2_ce0 = grp_computeGradient_fu_507_sp1_p2_ce0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm) | (ap_ST_st10_fsm_10 == ap_CS_fsm))) begin
sp0_p2_ce0 = grp_computeGradient_fu_507_sp0_p2_ce0;
end else begin
sp0_p2_ce0 = ap_const_logic_0;
end
end
/// sp0_p2_we0 assign process. ///
always @ (ap_CS_fsm or grp_computeDiffSqr_fu_531_sp_p2_we0)
begin
if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st12_fsm_12 == ap_CS_fsm) | (ap_ST_st6_fsm_6 == ap_CS_fsm))) begin
sp0_p2_we0 = grp_computeDiffSqr_fu_531_sp_p2_we0;
end else begin
sp0_p2_we0 = ap_const_logic_0;
end
end
/// sp0_p3_address0 assign process. ///
always @ (ap_CS_fsm or grp_computeGradient_fu_507_sp0_p3_address0 or grp_computeGradient_fu_507_sp1_p3_address0 or grp_computeDiffSqr_fu_531_sp_p3_address0)
begin
if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st12_fsm_12 == ap_CS_fsm) | (ap_ST_st6_fsm_6 == ap_CS_fsm))) begin
sp0_p3_address0 = grp_computeDiffSqr_fu_531_sp_p3_address0;
end else if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st14_fsm_14 == ap_CS_fsm))) begin
sp0_p3_address0 = grp_computeGradient_fu_507_sp1_p3_address0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm) | (ap_ST_st10_fsm_10 == ap_CS_fsm))) begin
sp0_p3_address0 = grp_computeGradient_fu_507_sp0_p3_address0;
end else begin
sp0_p3_address0 = grp_computeDiffSqr_fu_531_sp_p3_address0;
end
end
/// sp0_p3_ce0 assign process. ///
always @ (ap_CS_fsm or grp_computeGradient_fu_507_sp0_p3_ce0 or grp_computeGradient_fu_507_sp1_p3_ce0 or grp_computeDiffSqr_fu_531_sp_p3_ce0)
begin
if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st12_fsm_12 == ap_CS_fsm) | (ap_ST_st6_fsm_6 == ap_CS_fsm))) begin
sp0_p3_ce0 = grp_computeDiffSqr_fu_531_sp_p3_ce0;
end else if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st14_fsm_14 == ap_CS_fsm))) begin
sp0_p3_ce0 = grp_computeGradient_fu_507_sp1_p3_ce0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm) | (ap_ST_st10_fsm_10 == ap_CS_fsm))) begin
sp0_p3_ce0 = grp_computeGradient_fu_507_sp0_p3_ce0;
end else begin
sp0_p3_ce0 = ap_const_logic_0;
end
end
/// sp0_p3_we0 assign process. ///
always @ (ap_CS_fsm or grp_computeDiffSqr_fu_531_sp_p3_we0)
begin
if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st12_fsm_12 == ap_CS_fsm) | (ap_ST_st6_fsm_6 == ap_CS_fsm))) begin
sp0_p3_we0 = grp_computeDiffSqr_fu_531_sp_p3_we0;
end else begin
sp0_p3_we0 = ap_const_logic_0;
end
end
/// sp1_p0_address0 assign process. ///
always @ (ap_CS_fsm or grp_computeGradient_fu_507_sp0_p0_address0 or grp_computeGradient_fu_507_sp1_p0_address0 or grp_computeDiffSqr_fu_531_sp_p0_address0)
begin
if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st14_fsm_14 == ap_CS_fsm) | (ap_ST_st8_fsm_8 == ap_CS_fsm))) begin
sp1_p0_address0 = grp_computeDiffSqr_fu_531_sp_p0_address0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm) | (ap_ST_st10_fsm_10 == ap_CS_fsm))) begin
sp1_p0_address0 = grp_computeGradient_fu_507_sp1_p0_address0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st12_fsm_12 == ap_CS_fsm))) begin
sp1_p0_address0 = grp_computeGradient_fu_507_sp0_p0_address0;
end else begin
sp1_p0_address0 = grp_computeDiffSqr_fu_531_sp_p0_address0;
end
end
/// sp1_p0_ce0 assign process. ///
always @ (ap_CS_fsm or grp_computeGradient_fu_507_sp0_p0_ce0 or grp_computeGradient_fu_507_sp1_p0_ce0 or grp_computeDiffSqr_fu_531_sp_p0_ce0)
begin
if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st14_fsm_14 == ap_CS_fsm) | (ap_ST_st8_fsm_8 == ap_CS_fsm))) begin
sp1_p0_ce0 = grp_computeDiffSqr_fu_531_sp_p0_ce0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm) | (ap_ST_st10_fsm_10 == ap_CS_fsm))) begin
sp1_p0_ce0 = grp_computeGradient_fu_507_sp1_p0_ce0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st12_fsm_12 == ap_CS_fsm))) begin
sp1_p0_ce0 = grp_computeGradient_fu_507_sp0_p0_ce0;
end else begin
sp1_p0_ce0 = ap_const_logic_0;
end
end
/// sp1_p0_we0 assign process. ///
always @ (ap_CS_fsm or grp_computeDiffSqr_fu_531_sp_p0_we0)
begin
if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st14_fsm_14 == ap_CS_fsm) | (ap_ST_st8_fsm_8 == ap_CS_fsm))) begin
sp1_p0_we0 = grp_computeDiffSqr_fu_531_sp_p0_we0;
end else begin
sp1_p0_we0 = ap_const_logic_0;
end
end
/// sp1_p1_address0 assign process. ///
always @ (ap_CS_fsm or grp_computeGradient_fu_507_sp0_p1_address0 or grp_computeGradient_fu_507_sp1_p1_address0 or grp_computeDiffSqr_fu_531_sp_p1_address0)
begin
if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st14_fsm_14 == ap_CS_fsm) | (ap_ST_st8_fsm_8 == ap_CS_fsm))) begin
sp1_p1_address0 = grp_computeDiffSqr_fu_531_sp_p1_address0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm) | (ap_ST_st10_fsm_10 == ap_CS_fsm))) begin
sp1_p1_address0 = grp_computeGradient_fu_507_sp1_p1_address0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st12_fsm_12 == ap_CS_fsm))) begin
sp1_p1_address0 = grp_computeGradient_fu_507_sp0_p1_address0;
end else begin
sp1_p1_address0 = grp_computeDiffSqr_fu_531_sp_p1_address0;
end
end
/// sp1_p1_ce0 assign process. ///
always @ (ap_CS_fsm or grp_computeGradient_fu_507_sp0_p1_ce0 or grp_computeGradient_fu_507_sp1_p1_ce0 or grp_computeDiffSqr_fu_531_sp_p1_ce0)
begin
if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st14_fsm_14 == ap_CS_fsm) | (ap_ST_st8_fsm_8 == ap_CS_fsm))) begin
sp1_p1_ce0 = grp_computeDiffSqr_fu_531_sp_p1_ce0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm) | (ap_ST_st10_fsm_10 == ap_CS_fsm))) begin
sp1_p1_ce0 = grp_computeGradient_fu_507_sp1_p1_ce0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st12_fsm_12 == ap_CS_fsm))) begin
sp1_p1_ce0 = grp_computeGradient_fu_507_sp0_p1_ce0;
end else begin
sp1_p1_ce0 = ap_const_logic_0;
end
end
/// sp1_p1_we0 assign process. ///
always @ (ap_CS_fsm or grp_computeDiffSqr_fu_531_sp_p1_we0)
begin
if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st14_fsm_14 == ap_CS_fsm) | (ap_ST_st8_fsm_8 == ap_CS_fsm))) begin
sp1_p1_we0 = grp_computeDiffSqr_fu_531_sp_p1_we0;
end else begin
sp1_p1_we0 = ap_const_logic_0;
end
end
/// sp1_p2_address0 assign process. ///
always @ (ap_CS_fsm or grp_computeGradient_fu_507_sp0_p2_address0 or grp_computeGradient_fu_507_sp1_p2_address0 or grp_computeDiffSqr_fu_531_sp_p2_address0)
begin
if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st14_fsm_14 == ap_CS_fsm) | (ap_ST_st8_fsm_8 == ap_CS_fsm))) begin
sp1_p2_address0 = grp_computeDiffSqr_fu_531_sp_p2_address0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm) | (ap_ST_st10_fsm_10 == ap_CS_fsm))) begin
sp1_p2_address0 = grp_computeGradient_fu_507_sp1_p2_address0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st12_fsm_12 == ap_CS_fsm))) begin
sp1_p2_address0 = grp_computeGradient_fu_507_sp0_p2_address0;
end else begin
sp1_p2_address0 = grp_computeDiffSqr_fu_531_sp_p2_address0;
end
end
/// sp1_p2_ce0 assign process. ///
always @ (ap_CS_fsm or grp_computeGradient_fu_507_sp0_p2_ce0 or grp_computeGradient_fu_507_sp1_p2_ce0 or grp_computeDiffSqr_fu_531_sp_p2_ce0)
begin
if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st14_fsm_14 == ap_CS_fsm) | (ap_ST_st8_fsm_8 == ap_CS_fsm))) begin
sp1_p2_ce0 = grp_computeDiffSqr_fu_531_sp_p2_ce0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm) | (ap_ST_st10_fsm_10 == ap_CS_fsm))) begin
sp1_p2_ce0 = grp_computeGradient_fu_507_sp1_p2_ce0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st12_fsm_12 == ap_CS_fsm))) begin
sp1_p2_ce0 = grp_computeGradient_fu_507_sp0_p2_ce0;
end else begin
sp1_p2_ce0 = ap_const_logic_0;
end
end
/// sp1_p2_we0 assign process. ///
always @ (ap_CS_fsm or grp_computeDiffSqr_fu_531_sp_p2_we0)
begin
if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st14_fsm_14 == ap_CS_fsm) | (ap_ST_st8_fsm_8 == ap_CS_fsm))) begin
sp1_p2_we0 = grp_computeDiffSqr_fu_531_sp_p2_we0;
end else begin
sp1_p2_we0 = ap_const_logic_0;
end
end
/// sp1_p3_address0 assign process. ///
always @ (ap_CS_fsm or grp_computeGradient_fu_507_sp0_p3_address0 or grp_computeGradient_fu_507_sp1_p3_address0 or grp_computeDiffSqr_fu_531_sp_p3_address0)
begin
if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st14_fsm_14 == ap_CS_fsm) | (ap_ST_st8_fsm_8 == ap_CS_fsm))) begin
sp1_p3_address0 = grp_computeDiffSqr_fu_531_sp_p3_address0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm) | (ap_ST_st10_fsm_10 == ap_CS_fsm))) begin
sp1_p3_address0 = grp_computeGradient_fu_507_sp1_p3_address0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st12_fsm_12 == ap_CS_fsm))) begin
sp1_p3_address0 = grp_computeGradient_fu_507_sp0_p3_address0;
end else begin
sp1_p3_address0 = grp_computeDiffSqr_fu_531_sp_p3_address0;
end
end
/// sp1_p3_ce0 assign process. ///
always @ (ap_CS_fsm or grp_computeGradient_fu_507_sp0_p3_ce0 or grp_computeGradient_fu_507_sp1_p3_ce0 or grp_computeDiffSqr_fu_531_sp_p3_ce0)
begin
if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st14_fsm_14 == ap_CS_fsm) | (ap_ST_st8_fsm_8 == ap_CS_fsm))) begin
sp1_p3_ce0 = grp_computeDiffSqr_fu_531_sp_p3_ce0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm) | (ap_ST_st10_fsm_10 == ap_CS_fsm))) begin
sp1_p3_ce0 = grp_computeGradient_fu_507_sp1_p3_ce0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st12_fsm_12 == ap_CS_fsm))) begin
sp1_p3_ce0 = grp_computeGradient_fu_507_sp0_p3_ce0;
end else begin
sp1_p3_ce0 = ap_const_logic_0;
end
end
/// sp1_p3_we0 assign process. ///
always @ (ap_CS_fsm or grp_computeDiffSqr_fu_531_sp_p3_we0)
begin
if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st14_fsm_14 == ap_CS_fsm) | (ap_ST_st8_fsm_8 == ap_CS_fsm))) begin
sp1_p3_we0 = grp_computeDiffSqr_fu_531_sp_p3_we0;
end else begin
sp1_p3_we0 = ap_const_logic_0;
end
end
/// sp2_p0_address0 assign process. ///
always @ (ap_CS_fsm or grp_computeGradient_fu_507_sp0_p0_address0 or grp_computeGradient_fu_507_sp1_p0_address0 or grp_computeDiffSqr_fu_531_sp_p0_address0)
begin
if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st10_fsm_10 == ap_CS_fsm))) begin
sp2_p0_address0 = grp_computeDiffSqr_fu_531_sp_p0_address0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st12_fsm_12 == ap_CS_fsm))) begin
sp2_p0_address0 = grp_computeGradient_fu_507_sp1_p0_address0;
end else if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st14_fsm_14 == ap_CS_fsm))) begin
sp2_p0_address0 = grp_computeGradient_fu_507_sp0_p0_address0;
end else begin
sp2_p0_address0 = grp_computeDiffSqr_fu_531_sp_p0_address0;
end
end
/// sp2_p0_ce0 assign process. ///
always @ (ap_CS_fsm or grp_computeGradient_fu_507_sp0_p0_ce0 or grp_computeGradient_fu_507_sp1_p0_ce0 or grp_computeDiffSqr_fu_531_sp_p0_ce0)
begin
if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st10_fsm_10 == ap_CS_fsm))) begin
sp2_p0_ce0 = grp_computeDiffSqr_fu_531_sp_p0_ce0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st12_fsm_12 == ap_CS_fsm))) begin
sp2_p0_ce0 = grp_computeGradient_fu_507_sp1_p0_ce0;
end else if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st14_fsm_14 == ap_CS_fsm))) begin
sp2_p0_ce0 = grp_computeGradient_fu_507_sp0_p0_ce0;
end else begin
sp2_p0_ce0 = ap_const_logic_0;
end
end
/// sp2_p0_we0 assign process. ///
always @ (ap_CS_fsm or grp_computeDiffSqr_fu_531_sp_p0_we0)
begin
if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st10_fsm_10 == ap_CS_fsm))) begin
sp2_p0_we0 = grp_computeDiffSqr_fu_531_sp_p0_we0;
end else begin
sp2_p0_we0 = ap_const_logic_0;
end
end
/// sp2_p1_address0 assign process. ///
always @ (ap_CS_fsm or grp_computeGradient_fu_507_sp0_p1_address0 or grp_computeGradient_fu_507_sp1_p1_address0 or grp_computeDiffSqr_fu_531_sp_p1_address0)
begin
if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st10_fsm_10 == ap_CS_fsm))) begin
sp2_p1_address0 = grp_computeDiffSqr_fu_531_sp_p1_address0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st12_fsm_12 == ap_CS_fsm))) begin
sp2_p1_address0 = grp_computeGradient_fu_507_sp1_p1_address0;
end else if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st14_fsm_14 == ap_CS_fsm))) begin
sp2_p1_address0 = grp_computeGradient_fu_507_sp0_p1_address0;
end else begin
sp2_p1_address0 = grp_computeDiffSqr_fu_531_sp_p1_address0;
end
end
/// sp2_p1_ce0 assign process. ///
always @ (ap_CS_fsm or grp_computeGradient_fu_507_sp0_p1_ce0 or grp_computeGradient_fu_507_sp1_p1_ce0 or grp_computeDiffSqr_fu_531_sp_p1_ce0)
begin
if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st10_fsm_10 == ap_CS_fsm))) begin
sp2_p1_ce0 = grp_computeDiffSqr_fu_531_sp_p1_ce0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st12_fsm_12 == ap_CS_fsm))) begin
sp2_p1_ce0 = grp_computeGradient_fu_507_sp1_p1_ce0;
end else if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st14_fsm_14 == ap_CS_fsm))) begin
sp2_p1_ce0 = grp_computeGradient_fu_507_sp0_p1_ce0;
end else begin
sp2_p1_ce0 = ap_const_logic_0;
end
end
/// sp2_p1_we0 assign process. ///
always @ (ap_CS_fsm or grp_computeDiffSqr_fu_531_sp_p1_we0)
begin
if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st10_fsm_10 == ap_CS_fsm))) begin
sp2_p1_we0 = grp_computeDiffSqr_fu_531_sp_p1_we0;
end else begin
sp2_p1_we0 = ap_const_logic_0;
end
end
/// sp2_p2_address0 assign process. ///
always @ (ap_CS_fsm or grp_computeGradient_fu_507_sp0_p2_address0 or grp_computeGradient_fu_507_sp1_p2_address0 or grp_computeDiffSqr_fu_531_sp_p2_address0)
begin
if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st10_fsm_10 == ap_CS_fsm))) begin
sp2_p2_address0 = grp_computeDiffSqr_fu_531_sp_p2_address0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st12_fsm_12 == ap_CS_fsm))) begin
sp2_p2_address0 = grp_computeGradient_fu_507_sp1_p2_address0;
end else if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st14_fsm_14 == ap_CS_fsm))) begin
sp2_p2_address0 = grp_computeGradient_fu_507_sp0_p2_address0;
end else begin
sp2_p2_address0 = grp_computeDiffSqr_fu_531_sp_p2_address0;
end
end
/// sp2_p2_ce0 assign process. ///
always @ (ap_CS_fsm or grp_computeGradient_fu_507_sp0_p2_ce0 or grp_computeGradient_fu_507_sp1_p2_ce0 or grp_computeDiffSqr_fu_531_sp_p2_ce0)
begin
if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st10_fsm_10 == ap_CS_fsm))) begin
sp2_p2_ce0 = grp_computeDiffSqr_fu_531_sp_p2_ce0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st12_fsm_12 == ap_CS_fsm))) begin
sp2_p2_ce0 = grp_computeGradient_fu_507_sp1_p2_ce0;
end else if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st14_fsm_14 == ap_CS_fsm))) begin
sp2_p2_ce0 = grp_computeGradient_fu_507_sp0_p2_ce0;
end else begin
sp2_p2_ce0 = ap_const_logic_0;
end
end
/// sp2_p2_we0 assign process. ///
always @ (ap_CS_fsm or grp_computeDiffSqr_fu_531_sp_p2_we0)
begin
if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st10_fsm_10 == ap_CS_fsm))) begin
sp2_p2_we0 = grp_computeDiffSqr_fu_531_sp_p2_we0;
end else begin
sp2_p2_we0 = ap_const_logic_0;
end
end
/// sp2_p3_address0 assign process. ///
always @ (ap_CS_fsm or grp_computeGradient_fu_507_sp0_p3_address0 or grp_computeGradient_fu_507_sp1_p3_address0 or grp_computeDiffSqr_fu_531_sp_p3_address0)
begin
if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st10_fsm_10 == ap_CS_fsm))) begin
sp2_p3_address0 = grp_computeDiffSqr_fu_531_sp_p3_address0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st12_fsm_12 == ap_CS_fsm))) begin
sp2_p3_address0 = grp_computeGradient_fu_507_sp1_p3_address0;
end else if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st14_fsm_14 == ap_CS_fsm))) begin
sp2_p3_address0 = grp_computeGradient_fu_507_sp0_p3_address0;
end else begin
sp2_p3_address0 = grp_computeDiffSqr_fu_531_sp_p3_address0;
end
end
/// sp2_p3_ce0 assign process. ///
always @ (ap_CS_fsm or grp_computeGradient_fu_507_sp0_p3_ce0 or grp_computeGradient_fu_507_sp1_p3_ce0 or grp_computeDiffSqr_fu_531_sp_p3_ce0)
begin
if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st10_fsm_10 == ap_CS_fsm))) begin
sp2_p3_ce0 = grp_computeDiffSqr_fu_531_sp_p3_ce0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st12_fsm_12 == ap_CS_fsm))) begin
sp2_p3_ce0 = grp_computeGradient_fu_507_sp1_p3_ce0;
end else if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st14_fsm_14 == ap_CS_fsm))) begin
sp2_p3_ce0 = grp_computeGradient_fu_507_sp0_p3_ce0;
end else begin
sp2_p3_ce0 = ap_const_logic_0;
end
end
/// sp2_p3_we0 assign process. ///
always @ (ap_CS_fsm or grp_computeDiffSqr_fu_531_sp_p3_we0)
begin
if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st10_fsm_10 == ap_CS_fsm))) begin
sp2_p3_we0 = grp_computeDiffSqr_fu_531_sp_p3_we0;
end else begin
sp2_p3_we0 = ap_const_logic_0;
end
end
/// u0_p0_address0 assign process. ///
always @ (ap_CS_fsm or grp_computeResult_fu_467_u_p0_address0 or grp_computeDiffSqr_fu_531_u0_p0_address0 or grp_computeDiffSqr_fu_531_u1_p0_address0 or grp_computeUG_fu_555_u_p0_address0 or grp_uFetch_array_fu_583_data_p0_address0)
begin
if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st2_fsm_2 == ap_CS_fsm))) begin
u0_p0_address0 = grp_uFetch_array_fu_583_data_p0_address0;
end else if (((ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm))) begin
u0_p0_address0 = grp_computeUG_fu_555_u_p0_address0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm))) begin
u0_p0_address0 = grp_computeDiffSqr_fu_531_u1_p0_address0;
end else if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st6_fsm_6 == ap_CS_fsm))) begin
u0_p0_address0 = grp_computeDiffSqr_fu_531_u0_p0_address0;
end else if (((ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st126_fsm_126 == ap_CS_fsm))) begin
u0_p0_address0 = grp_computeResult_fu_467_u_p0_address0;
end else begin
u0_p0_address0 = grp_uFetch_array_fu_583_data_p0_address0;
end
end
/// u0_p0_ce0 assign process. ///
always @ (ap_CS_fsm or grp_computeResult_fu_467_u_p0_ce0 or grp_computeDiffSqr_fu_531_u0_p0_ce0 or grp_computeDiffSqr_fu_531_u1_p0_ce0 or grp_computeUG_fu_555_u_p0_ce0 or grp_uFetch_array_fu_583_data_p0_ce0)
begin
if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st2_fsm_2 == ap_CS_fsm))) begin
u0_p0_ce0 = grp_uFetch_array_fu_583_data_p0_ce0;
end else if (((ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm))) begin
u0_p0_ce0 = grp_computeUG_fu_555_u_p0_ce0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm))) begin
u0_p0_ce0 = grp_computeDiffSqr_fu_531_u1_p0_ce0;
end else if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st6_fsm_6 == ap_CS_fsm))) begin
u0_p0_ce0 = grp_computeDiffSqr_fu_531_u0_p0_ce0;
end else if (((ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st126_fsm_126 == ap_CS_fsm))) begin
u0_p0_ce0 = grp_computeResult_fu_467_u_p0_ce0;
end else begin
u0_p0_ce0 = ap_const_logic_0;
end
end
/// u0_p0_we0 assign process. ///
always @ (ap_CS_fsm or grp_uFetch_array_fu_583_data_p0_we0)
begin
if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st2_fsm_2 == ap_CS_fsm))) begin
u0_p0_we0 = grp_uFetch_array_fu_583_data_p0_we0;
end else begin
u0_p0_we0 = ap_const_logic_0;
end
end
/// u0_p1_address0 assign process. ///
always @ (ap_CS_fsm or grp_computeResult_fu_467_u_p1_address0 or grp_computeDiffSqr_fu_531_u0_p1_address0 or grp_computeDiffSqr_fu_531_u1_p1_address0 or grp_computeUG_fu_555_u_p1_address0 or grp_uFetch_array_fu_583_data_p1_address0)
begin
if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st2_fsm_2 == ap_CS_fsm))) begin
u0_p1_address0 = grp_uFetch_array_fu_583_data_p1_address0;
end else if (((ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm))) begin
u0_p1_address0 = grp_computeUG_fu_555_u_p1_address0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm))) begin
u0_p1_address0 = grp_computeDiffSqr_fu_531_u1_p1_address0;
end else if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st6_fsm_6 == ap_CS_fsm))) begin
u0_p1_address0 = grp_computeDiffSqr_fu_531_u0_p1_address0;
end else if (((ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st126_fsm_126 == ap_CS_fsm))) begin
u0_p1_address0 = grp_computeResult_fu_467_u_p1_address0;
end else begin
u0_p1_address0 = grp_uFetch_array_fu_583_data_p1_address0;
end
end
/// u0_p1_ce0 assign process. ///
always @ (ap_CS_fsm or grp_computeResult_fu_467_u_p1_ce0 or grp_computeDiffSqr_fu_531_u0_p1_ce0 or grp_computeDiffSqr_fu_531_u1_p1_ce0 or grp_computeUG_fu_555_u_p1_ce0 or grp_uFetch_array_fu_583_data_p1_ce0)
begin
if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st2_fsm_2 == ap_CS_fsm))) begin
u0_p1_ce0 = grp_uFetch_array_fu_583_data_p1_ce0;
end else if (((ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm))) begin
u0_p1_ce0 = grp_computeUG_fu_555_u_p1_ce0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm))) begin
u0_p1_ce0 = grp_computeDiffSqr_fu_531_u1_p1_ce0;
end else if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st6_fsm_6 == ap_CS_fsm))) begin
u0_p1_ce0 = grp_computeDiffSqr_fu_531_u0_p1_ce0;
end else if (((ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st126_fsm_126 == ap_CS_fsm))) begin
u0_p1_ce0 = grp_computeResult_fu_467_u_p1_ce0;
end else begin
u0_p1_ce0 = ap_const_logic_0;
end
end
/// u0_p1_we0 assign process. ///
always @ (ap_CS_fsm or grp_uFetch_array_fu_583_data_p1_we0)
begin
if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st2_fsm_2 == ap_CS_fsm))) begin
u0_p1_we0 = grp_uFetch_array_fu_583_data_p1_we0;
end else begin
u0_p1_we0 = ap_const_logic_0;
end
end
/// u0_p2_address0 assign process. ///
always @ (ap_CS_fsm or grp_computeResult_fu_467_u_p2_address0 or grp_computeDiffSqr_fu_531_u0_p2_address0 or grp_computeDiffSqr_fu_531_u1_p2_address0 or grp_computeUG_fu_555_u_p2_address0 or grp_uFetch_array_fu_583_data_p2_address0)
begin
if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st2_fsm_2 == ap_CS_fsm))) begin
u0_p2_address0 = grp_uFetch_array_fu_583_data_p2_address0;
end else if (((ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm))) begin
u0_p2_address0 = grp_computeUG_fu_555_u_p2_address0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm))) begin
u0_p2_address0 = grp_computeDiffSqr_fu_531_u1_p2_address0;
end else if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st6_fsm_6 == ap_CS_fsm))) begin
u0_p2_address0 = grp_computeDiffSqr_fu_531_u0_p2_address0;
end else if (((ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st126_fsm_126 == ap_CS_fsm))) begin
u0_p2_address0 = grp_computeResult_fu_467_u_p2_address0;
end else begin
u0_p2_address0 = grp_uFetch_array_fu_583_data_p2_address0;
end
end
/// u0_p2_ce0 assign process. ///
always @ (ap_CS_fsm or grp_computeResult_fu_467_u_p2_ce0 or grp_computeDiffSqr_fu_531_u0_p2_ce0 or grp_computeDiffSqr_fu_531_u1_p2_ce0 or grp_computeUG_fu_555_u_p2_ce0 or grp_uFetch_array_fu_583_data_p2_ce0)
begin
if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st2_fsm_2 == ap_CS_fsm))) begin
u0_p2_ce0 = grp_uFetch_array_fu_583_data_p2_ce0;
end else if (((ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm))) begin
u0_p2_ce0 = grp_computeUG_fu_555_u_p2_ce0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm))) begin
u0_p2_ce0 = grp_computeDiffSqr_fu_531_u1_p2_ce0;
end else if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st6_fsm_6 == ap_CS_fsm))) begin
u0_p2_ce0 = grp_computeDiffSqr_fu_531_u0_p2_ce0;
end else if (((ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st126_fsm_126 == ap_CS_fsm))) begin
u0_p2_ce0 = grp_computeResult_fu_467_u_p2_ce0;
end else begin
u0_p2_ce0 = ap_const_logic_0;
end
end
/// u0_p2_we0 assign process. ///
always @ (ap_CS_fsm or grp_uFetch_array_fu_583_data_p2_we0)
begin
if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st2_fsm_2 == ap_CS_fsm))) begin
u0_p2_we0 = grp_uFetch_array_fu_583_data_p2_we0;
end else begin
u0_p2_we0 = ap_const_logic_0;
end
end
/// u0_p3_address0 assign process. ///
always @ (ap_CS_fsm or grp_computeResult_fu_467_u_p3_address0 or grp_computeDiffSqr_fu_531_u0_p3_address0 or grp_computeDiffSqr_fu_531_u1_p3_address0 or grp_computeUG_fu_555_u_p3_address0 or grp_uFetch_array_fu_583_data_p3_address0)
begin
if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st2_fsm_2 == ap_CS_fsm))) begin
u0_p3_address0 = grp_uFetch_array_fu_583_data_p3_address0;
end else if (((ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm))) begin
u0_p3_address0 = grp_computeUG_fu_555_u_p3_address0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm))) begin
u0_p3_address0 = grp_computeDiffSqr_fu_531_u1_p3_address0;
end else if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st6_fsm_6 == ap_CS_fsm))) begin
u0_p3_address0 = grp_computeDiffSqr_fu_531_u0_p3_address0;
end else if (((ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st126_fsm_126 == ap_CS_fsm))) begin
u0_p3_address0 = grp_computeResult_fu_467_u_p3_address0;
end else begin
u0_p3_address0 = grp_uFetch_array_fu_583_data_p3_address0;
end
end
/// u0_p3_ce0 assign process. ///
always @ (ap_CS_fsm or grp_computeResult_fu_467_u_p3_ce0 or grp_computeDiffSqr_fu_531_u0_p3_ce0 or grp_computeDiffSqr_fu_531_u1_p3_ce0 or grp_computeUG_fu_555_u_p3_ce0 or grp_uFetch_array_fu_583_data_p3_ce0)
begin
if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st2_fsm_2 == ap_CS_fsm))) begin
u0_p3_ce0 = grp_uFetch_array_fu_583_data_p3_ce0;
end else if (((ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm))) begin
u0_p3_ce0 = grp_computeUG_fu_555_u_p3_ce0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm))) begin
u0_p3_ce0 = grp_computeDiffSqr_fu_531_u1_p3_ce0;
end else if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st6_fsm_6 == ap_CS_fsm))) begin
u0_p3_ce0 = grp_computeDiffSqr_fu_531_u0_p3_ce0;
end else if (((ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st126_fsm_126 == ap_CS_fsm))) begin
u0_p3_ce0 = grp_computeResult_fu_467_u_p3_ce0;
end else begin
u0_p3_ce0 = ap_const_logic_0;
end
end
/// u0_p3_ce1 assign process. ///
always @ (ap_CS_fsm or grp_computeDiffSqr_fu_531_u0_p3_ce1)
begin
if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st6_fsm_6 == ap_CS_fsm))) begin
u0_p3_ce1 = grp_computeDiffSqr_fu_531_u0_p3_ce1;
end else begin
u0_p3_ce1 = ap_const_logic_0;
end
end
/// u0_p3_we0 assign process. ///
always @ (ap_CS_fsm or grp_uFetch_array_fu_583_data_p3_we0)
begin
if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st2_fsm_2 == ap_CS_fsm))) begin
u0_p3_we0 = grp_uFetch_array_fu_583_data_p3_we0;
end else begin
u0_p3_we0 = ap_const_logic_0;
end
end
/// u1_p0_address0 assign process. ///
always @ (ap_CS_fsm or grp_computeResult_fu_467_u_p0_address0 or grp_computeDiffSqr_fu_531_u0_p0_address0 or grp_computeDiffSqr_fu_531_u1_p0_address0 or grp_computeUG_fu_555_u_p0_address0 or grp_uFetch_array_fu_583_data_p0_address0)
begin
if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st4_fsm_4 == ap_CS_fsm))) begin
u1_p0_address0 = grp_uFetch_array_fu_583_data_p0_address0;
end else if (((ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm) | (ap_ST_st12_fsm_12 == ap_CS_fsm))) begin
u1_p0_address0 = grp_computeUG_fu_555_u_p0_address0;
end else if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st6_fsm_6 == ap_CS_fsm))) begin
u1_p0_address0 = grp_computeDiffSqr_fu_531_u1_p0_address0;
end else if (((ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st8_fsm_8 == ap_CS_fsm))) begin
u1_p0_address0 = grp_computeDiffSqr_fu_531_u0_p0_address0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st128_fsm_128 == ap_CS_fsm))) begin
u1_p0_address0 = grp_computeResult_fu_467_u_p0_address0;
end else begin
u1_p0_address0 = grp_uFetch_array_fu_583_data_p0_address0;
end
end
/// u1_p0_ce0 assign process. ///
always @ (ap_CS_fsm or grp_computeResult_fu_467_u_p0_ce0 or grp_computeDiffSqr_fu_531_u0_p0_ce0 or grp_computeDiffSqr_fu_531_u1_p0_ce0 or grp_computeUG_fu_555_u_p0_ce0 or grp_uFetch_array_fu_583_data_p0_ce0)
begin
if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st4_fsm_4 == ap_CS_fsm))) begin
u1_p0_ce0 = grp_uFetch_array_fu_583_data_p0_ce0;
end else if (((ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm) | (ap_ST_st12_fsm_12 == ap_CS_fsm))) begin
u1_p0_ce0 = grp_computeUG_fu_555_u_p0_ce0;
end else if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st6_fsm_6 == ap_CS_fsm))) begin
u1_p0_ce0 = grp_computeDiffSqr_fu_531_u1_p0_ce0;
end else if (((ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st8_fsm_8 == ap_CS_fsm))) begin
u1_p0_ce0 = grp_computeDiffSqr_fu_531_u0_p0_ce0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st128_fsm_128 == ap_CS_fsm))) begin
u1_p0_ce0 = grp_computeResult_fu_467_u_p0_ce0;
end else begin
u1_p0_ce0 = ap_const_logic_0;
end
end
/// u1_p0_we0 assign process. ///
always @ (ap_CS_fsm or grp_uFetch_array_fu_583_data_p0_we0)
begin
if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st4_fsm_4 == ap_CS_fsm))) begin
u1_p0_we0 = grp_uFetch_array_fu_583_data_p0_we0;
end else begin
u1_p0_we0 = ap_const_logic_0;
end
end
/// u1_p1_address0 assign process. ///
always @ (ap_CS_fsm or grp_computeResult_fu_467_u_p1_address0 or grp_computeDiffSqr_fu_531_u0_p1_address0 or grp_computeDiffSqr_fu_531_u1_p1_address0 or grp_computeUG_fu_555_u_p1_address0 or grp_uFetch_array_fu_583_data_p1_address0)
begin
if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st4_fsm_4 == ap_CS_fsm))) begin
u1_p1_address0 = grp_uFetch_array_fu_583_data_p1_address0;
end else if (((ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm) | (ap_ST_st12_fsm_12 == ap_CS_fsm))) begin
u1_p1_address0 = grp_computeUG_fu_555_u_p1_address0;
end else if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st6_fsm_6 == ap_CS_fsm))) begin
u1_p1_address0 = grp_computeDiffSqr_fu_531_u1_p1_address0;
end else if (((ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st8_fsm_8 == ap_CS_fsm))) begin
u1_p1_address0 = grp_computeDiffSqr_fu_531_u0_p1_address0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st128_fsm_128 == ap_CS_fsm))) begin
u1_p1_address0 = grp_computeResult_fu_467_u_p1_address0;
end else begin
u1_p1_address0 = grp_uFetch_array_fu_583_data_p1_address0;
end
end
/// u1_p1_ce0 assign process. ///
always @ (ap_CS_fsm or grp_computeResult_fu_467_u_p1_ce0 or grp_computeDiffSqr_fu_531_u0_p1_ce0 or grp_computeDiffSqr_fu_531_u1_p1_ce0 or grp_computeUG_fu_555_u_p1_ce0 or grp_uFetch_array_fu_583_data_p1_ce0)
begin
if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st4_fsm_4 == ap_CS_fsm))) begin
u1_p1_ce0 = grp_uFetch_array_fu_583_data_p1_ce0;
end else if (((ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm) | (ap_ST_st12_fsm_12 == ap_CS_fsm))) begin
u1_p1_ce0 = grp_computeUG_fu_555_u_p1_ce0;
end else if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st6_fsm_6 == ap_CS_fsm))) begin
u1_p1_ce0 = grp_computeDiffSqr_fu_531_u1_p1_ce0;
end else if (((ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st8_fsm_8 == ap_CS_fsm))) begin
u1_p1_ce0 = grp_computeDiffSqr_fu_531_u0_p1_ce0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st128_fsm_128 == ap_CS_fsm))) begin
u1_p1_ce0 = grp_computeResult_fu_467_u_p1_ce0;
end else begin
u1_p1_ce0 = ap_const_logic_0;
end
end
/// u1_p1_we0 assign process. ///
always @ (ap_CS_fsm or grp_uFetch_array_fu_583_data_p1_we0)
begin
if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st4_fsm_4 == ap_CS_fsm))) begin
u1_p1_we0 = grp_uFetch_array_fu_583_data_p1_we0;
end else begin
u1_p1_we0 = ap_const_logic_0;
end
end
/// u1_p2_address0 assign process. ///
always @ (ap_CS_fsm or grp_computeResult_fu_467_u_p2_address0 or grp_computeDiffSqr_fu_531_u0_p2_address0 or grp_computeDiffSqr_fu_531_u1_p2_address0 or grp_computeUG_fu_555_u_p2_address0 or grp_uFetch_array_fu_583_data_p2_address0)
begin
if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st4_fsm_4 == ap_CS_fsm))) begin
u1_p2_address0 = grp_uFetch_array_fu_583_data_p2_address0;
end else if (((ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm) | (ap_ST_st12_fsm_12 == ap_CS_fsm))) begin
u1_p2_address0 = grp_computeUG_fu_555_u_p2_address0;
end else if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st6_fsm_6 == ap_CS_fsm))) begin
u1_p2_address0 = grp_computeDiffSqr_fu_531_u1_p2_address0;
end else if (((ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st8_fsm_8 == ap_CS_fsm))) begin
u1_p2_address0 = grp_computeDiffSqr_fu_531_u0_p2_address0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st128_fsm_128 == ap_CS_fsm))) begin
u1_p2_address0 = grp_computeResult_fu_467_u_p2_address0;
end else begin
u1_p2_address0 = grp_uFetch_array_fu_583_data_p2_address0;
end
end
/// u1_p2_ce0 assign process. ///
always @ (ap_CS_fsm or grp_computeResult_fu_467_u_p2_ce0 or grp_computeDiffSqr_fu_531_u0_p2_ce0 or grp_computeDiffSqr_fu_531_u1_p2_ce0 or grp_computeUG_fu_555_u_p2_ce0 or grp_uFetch_array_fu_583_data_p2_ce0)
begin
if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st4_fsm_4 == ap_CS_fsm))) begin
u1_p2_ce0 = grp_uFetch_array_fu_583_data_p2_ce0;
end else if (((ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm) | (ap_ST_st12_fsm_12 == ap_CS_fsm))) begin
u1_p2_ce0 = grp_computeUG_fu_555_u_p2_ce0;
end else if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st6_fsm_6 == ap_CS_fsm))) begin
u1_p2_ce0 = grp_computeDiffSqr_fu_531_u1_p2_ce0;
end else if (((ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st8_fsm_8 == ap_CS_fsm))) begin
u1_p2_ce0 = grp_computeDiffSqr_fu_531_u0_p2_ce0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st128_fsm_128 == ap_CS_fsm))) begin
u1_p2_ce0 = grp_computeResult_fu_467_u_p2_ce0;
end else begin
u1_p2_ce0 = ap_const_logic_0;
end
end
/// u1_p2_we0 assign process. ///
always @ (ap_CS_fsm or grp_uFetch_array_fu_583_data_p2_we0)
begin
if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st4_fsm_4 == ap_CS_fsm))) begin
u1_p2_we0 = grp_uFetch_array_fu_583_data_p2_we0;
end else begin
u1_p2_we0 = ap_const_logic_0;
end
end
/// u1_p3_address0 assign process. ///
always @ (ap_CS_fsm or grp_computeResult_fu_467_u_p3_address0 or grp_computeDiffSqr_fu_531_u0_p3_address0 or grp_computeDiffSqr_fu_531_u1_p3_address0 or grp_computeUG_fu_555_u_p3_address0 or grp_uFetch_array_fu_583_data_p3_address0)
begin
if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st4_fsm_4 == ap_CS_fsm))) begin
u1_p3_address0 = grp_uFetch_array_fu_583_data_p3_address0;
end else if (((ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm) | (ap_ST_st12_fsm_12 == ap_CS_fsm))) begin
u1_p3_address0 = grp_computeUG_fu_555_u_p3_address0;
end else if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st6_fsm_6 == ap_CS_fsm))) begin
u1_p3_address0 = grp_computeDiffSqr_fu_531_u1_p3_address0;
end else if (((ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st8_fsm_8 == ap_CS_fsm))) begin
u1_p3_address0 = grp_computeDiffSqr_fu_531_u0_p3_address0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st128_fsm_128 == ap_CS_fsm))) begin
u1_p3_address0 = grp_computeResult_fu_467_u_p3_address0;
end else begin
u1_p3_address0 = grp_uFetch_array_fu_583_data_p3_address0;
end
end
/// u1_p3_ce0 assign process. ///
always @ (ap_CS_fsm or grp_computeResult_fu_467_u_p3_ce0 or grp_computeDiffSqr_fu_531_u0_p3_ce0 or grp_computeDiffSqr_fu_531_u1_p3_ce0 or grp_computeUG_fu_555_u_p3_ce0 or grp_uFetch_array_fu_583_data_p3_ce0)
begin
if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st4_fsm_4 == ap_CS_fsm))) begin
u1_p3_ce0 = grp_uFetch_array_fu_583_data_p3_ce0;
end else if (((ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm) | (ap_ST_st12_fsm_12 == ap_CS_fsm))) begin
u1_p3_ce0 = grp_computeUG_fu_555_u_p3_ce0;
end else if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st6_fsm_6 == ap_CS_fsm))) begin
u1_p3_ce0 = grp_computeDiffSqr_fu_531_u1_p3_ce0;
end else if (((ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st8_fsm_8 == ap_CS_fsm))) begin
u1_p3_ce0 = grp_computeDiffSqr_fu_531_u0_p3_ce0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st128_fsm_128 == ap_CS_fsm))) begin
u1_p3_ce0 = grp_computeResult_fu_467_u_p3_ce0;
end else begin
u1_p3_ce0 = ap_const_logic_0;
end
end
/// u1_p3_ce1 assign process. ///
always @ (ap_CS_fsm or grp_computeDiffSqr_fu_531_u0_p3_ce1)
begin
if (((ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st8_fsm_8 == ap_CS_fsm))) begin
u1_p3_ce1 = grp_computeDiffSqr_fu_531_u0_p3_ce1;
end else begin
u1_p3_ce1 = ap_const_logic_0;
end
end
/// u1_p3_we0 assign process. ///
always @ (ap_CS_fsm or grp_uFetch_array_fu_583_data_p3_we0)
begin
if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st4_fsm_4 == ap_CS_fsm))) begin
u1_p3_we0 = grp_uFetch_array_fu_583_data_p3_we0;
end else begin
u1_p3_we0 = ap_const_logic_0;
end
end
/// u2_p0_address0 assign process. ///
always @ (ap_CS_fsm or grp_computeResult_fu_467_u_p0_address0 or grp_computeDiffSqr_fu_531_u0_p0_address0 or grp_computeDiffSqr_fu_531_u1_p0_address0 or grp_computeUG_fu_555_u_p0_address0 or grp_uFetch_array_fu_583_data_p0_address0)
begin
if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st6_fsm_6 == ap_CS_fsm))) begin
u2_p0_address0 = grp_uFetch_array_fu_583_data_p0_address0;
end else if (((ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st126_fsm_126 == ap_CS_fsm) | (ap_ST_st14_fsm_14 == ap_CS_fsm))) begin
u2_p0_address0 = grp_computeUG_fu_555_u_p0_address0;
end else if (((ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st8_fsm_8 == ap_CS_fsm))) begin
u2_p0_address0 = grp_computeDiffSqr_fu_531_u1_p0_address0;
end else if (((ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st10_fsm_10 == ap_CS_fsm))) begin
u2_p0_address0 = grp_computeDiffSqr_fu_531_u0_p0_address0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st130_fsm_130 == ap_CS_fsm))) begin
u2_p0_address0 = grp_computeResult_fu_467_u_p0_address0;
end else begin
u2_p0_address0 = grp_uFetch_array_fu_583_data_p0_address0;
end
end
/// u2_p0_ce0 assign process. ///
always @ (ap_CS_fsm or grp_computeResult_fu_467_u_p0_ce0 or grp_computeDiffSqr_fu_531_u0_p0_ce0 or grp_computeDiffSqr_fu_531_u1_p0_ce0 or grp_computeUG_fu_555_u_p0_ce0 or grp_uFetch_array_fu_583_data_p0_ce0)
begin
if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st6_fsm_6 == ap_CS_fsm))) begin
u2_p0_ce0 = grp_uFetch_array_fu_583_data_p0_ce0;
end else if (((ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st126_fsm_126 == ap_CS_fsm) | (ap_ST_st14_fsm_14 == ap_CS_fsm))) begin
u2_p0_ce0 = grp_computeUG_fu_555_u_p0_ce0;
end else if (((ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st8_fsm_8 == ap_CS_fsm))) begin
u2_p0_ce0 = grp_computeDiffSqr_fu_531_u1_p0_ce0;
end else if (((ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st10_fsm_10 == ap_CS_fsm))) begin
u2_p0_ce0 = grp_computeDiffSqr_fu_531_u0_p0_ce0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st130_fsm_130 == ap_CS_fsm))) begin
u2_p0_ce0 = grp_computeResult_fu_467_u_p0_ce0;
end else begin
u2_p0_ce0 = ap_const_logic_0;
end
end
/// u2_p0_we0 assign process. ///
always @ (ap_CS_fsm or grp_uFetch_array_fu_583_data_p0_we0)
begin
if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st6_fsm_6 == ap_CS_fsm))) begin
u2_p0_we0 = grp_uFetch_array_fu_583_data_p0_we0;
end else begin
u2_p0_we0 = ap_const_logic_0;
end
end
/// u2_p1_address0 assign process. ///
always @ (ap_CS_fsm or grp_computeResult_fu_467_u_p1_address0 or grp_computeDiffSqr_fu_531_u0_p1_address0 or grp_computeDiffSqr_fu_531_u1_p1_address0 or grp_computeUG_fu_555_u_p1_address0 or grp_uFetch_array_fu_583_data_p1_address0)
begin
if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st6_fsm_6 == ap_CS_fsm))) begin
u2_p1_address0 = grp_uFetch_array_fu_583_data_p1_address0;
end else if (((ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st126_fsm_126 == ap_CS_fsm) | (ap_ST_st14_fsm_14 == ap_CS_fsm))) begin
u2_p1_address0 = grp_computeUG_fu_555_u_p1_address0;
end else if (((ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st8_fsm_8 == ap_CS_fsm))) begin
u2_p1_address0 = grp_computeDiffSqr_fu_531_u1_p1_address0;
end else if (((ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st10_fsm_10 == ap_CS_fsm))) begin
u2_p1_address0 = grp_computeDiffSqr_fu_531_u0_p1_address0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st130_fsm_130 == ap_CS_fsm))) begin
u2_p1_address0 = grp_computeResult_fu_467_u_p1_address0;
end else begin
u2_p1_address0 = grp_uFetch_array_fu_583_data_p1_address0;
end
end
/// u2_p1_ce0 assign process. ///
always @ (ap_CS_fsm or grp_computeResult_fu_467_u_p1_ce0 or grp_computeDiffSqr_fu_531_u0_p1_ce0 or grp_computeDiffSqr_fu_531_u1_p1_ce0 or grp_computeUG_fu_555_u_p1_ce0 or grp_uFetch_array_fu_583_data_p1_ce0)
begin
if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st6_fsm_6 == ap_CS_fsm))) begin
u2_p1_ce0 = grp_uFetch_array_fu_583_data_p1_ce0;
end else if (((ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st126_fsm_126 == ap_CS_fsm) | (ap_ST_st14_fsm_14 == ap_CS_fsm))) begin
u2_p1_ce0 = grp_computeUG_fu_555_u_p1_ce0;
end else if (((ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st8_fsm_8 == ap_CS_fsm))) begin
u2_p1_ce0 = grp_computeDiffSqr_fu_531_u1_p1_ce0;
end else if (((ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st10_fsm_10 == ap_CS_fsm))) begin
u2_p1_ce0 = grp_computeDiffSqr_fu_531_u0_p1_ce0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st130_fsm_130 == ap_CS_fsm))) begin
u2_p1_ce0 = grp_computeResult_fu_467_u_p1_ce0;
end else begin
u2_p1_ce0 = ap_const_logic_0;
end
end
/// u2_p1_we0 assign process. ///
always @ (ap_CS_fsm or grp_uFetch_array_fu_583_data_p1_we0)
begin
if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st6_fsm_6 == ap_CS_fsm))) begin
u2_p1_we0 = grp_uFetch_array_fu_583_data_p1_we0;
end else begin
u2_p1_we0 = ap_const_logic_0;
end
end
/// u2_p2_address0 assign process. ///
always @ (ap_CS_fsm or grp_computeResult_fu_467_u_p2_address0 or grp_computeDiffSqr_fu_531_u0_p2_address0 or grp_computeDiffSqr_fu_531_u1_p2_address0 or grp_computeUG_fu_555_u_p2_address0 or grp_uFetch_array_fu_583_data_p2_address0)
begin
if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st6_fsm_6 == ap_CS_fsm))) begin
u2_p2_address0 = grp_uFetch_array_fu_583_data_p2_address0;
end else if (((ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st126_fsm_126 == ap_CS_fsm) | (ap_ST_st14_fsm_14 == ap_CS_fsm))) begin
u2_p2_address0 = grp_computeUG_fu_555_u_p2_address0;
end else if (((ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st8_fsm_8 == ap_CS_fsm))) begin
u2_p2_address0 = grp_computeDiffSqr_fu_531_u1_p2_address0;
end else if (((ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st10_fsm_10 == ap_CS_fsm))) begin
u2_p2_address0 = grp_computeDiffSqr_fu_531_u0_p2_address0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st130_fsm_130 == ap_CS_fsm))) begin
u2_p2_address0 = grp_computeResult_fu_467_u_p2_address0;
end else begin
u2_p2_address0 = grp_uFetch_array_fu_583_data_p2_address0;
end
end
/// u2_p2_ce0 assign process. ///
always @ (ap_CS_fsm or grp_computeResult_fu_467_u_p2_ce0 or grp_computeDiffSqr_fu_531_u0_p2_ce0 or grp_computeDiffSqr_fu_531_u1_p2_ce0 or grp_computeUG_fu_555_u_p2_ce0 or grp_uFetch_array_fu_583_data_p2_ce0)
begin
if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st6_fsm_6 == ap_CS_fsm))) begin
u2_p2_ce0 = grp_uFetch_array_fu_583_data_p2_ce0;
end else if (((ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st126_fsm_126 == ap_CS_fsm) | (ap_ST_st14_fsm_14 == ap_CS_fsm))) begin
u2_p2_ce0 = grp_computeUG_fu_555_u_p2_ce0;
end else if (((ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st8_fsm_8 == ap_CS_fsm))) begin
u2_p2_ce0 = grp_computeDiffSqr_fu_531_u1_p2_ce0;
end else if (((ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st10_fsm_10 == ap_CS_fsm))) begin
u2_p2_ce0 = grp_computeDiffSqr_fu_531_u0_p2_ce0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st130_fsm_130 == ap_CS_fsm))) begin
u2_p2_ce0 = grp_computeResult_fu_467_u_p2_ce0;
end else begin
u2_p2_ce0 = ap_const_logic_0;
end
end
/// u2_p2_we0 assign process. ///
always @ (ap_CS_fsm or grp_uFetch_array_fu_583_data_p2_we0)
begin
if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st6_fsm_6 == ap_CS_fsm))) begin
u2_p2_we0 = grp_uFetch_array_fu_583_data_p2_we0;
end else begin
u2_p2_we0 = ap_const_logic_0;
end
end
/// u2_p3_address0 assign process. ///
always @ (ap_CS_fsm or grp_computeResult_fu_467_u_p3_address0 or grp_computeDiffSqr_fu_531_u0_p3_address0 or grp_computeDiffSqr_fu_531_u1_p3_address0 or grp_computeUG_fu_555_u_p3_address0 or grp_uFetch_array_fu_583_data_p3_address0)
begin
if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st6_fsm_6 == ap_CS_fsm))) begin
u2_p3_address0 = grp_uFetch_array_fu_583_data_p3_address0;
end else if (((ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st126_fsm_126 == ap_CS_fsm) | (ap_ST_st14_fsm_14 == ap_CS_fsm))) begin
u2_p3_address0 = grp_computeUG_fu_555_u_p3_address0;
end else if (((ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st8_fsm_8 == ap_CS_fsm))) begin
u2_p3_address0 = grp_computeDiffSqr_fu_531_u1_p3_address0;
end else if (((ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st10_fsm_10 == ap_CS_fsm))) begin
u2_p3_address0 = grp_computeDiffSqr_fu_531_u0_p3_address0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st130_fsm_130 == ap_CS_fsm))) begin
u2_p3_address0 = grp_computeResult_fu_467_u_p3_address0;
end else begin
u2_p3_address0 = grp_uFetch_array_fu_583_data_p3_address0;
end
end
/// u2_p3_ce0 assign process. ///
always @ (ap_CS_fsm or grp_computeResult_fu_467_u_p3_ce0 or grp_computeDiffSqr_fu_531_u0_p3_ce0 or grp_computeDiffSqr_fu_531_u1_p3_ce0 or grp_computeUG_fu_555_u_p3_ce0 or grp_uFetch_array_fu_583_data_p3_ce0)
begin
if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st6_fsm_6 == ap_CS_fsm))) begin
u2_p3_ce0 = grp_uFetch_array_fu_583_data_p3_ce0;
end else if (((ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st126_fsm_126 == ap_CS_fsm) | (ap_ST_st14_fsm_14 == ap_CS_fsm))) begin
u2_p3_ce0 = grp_computeUG_fu_555_u_p3_ce0;
end else if (((ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st8_fsm_8 == ap_CS_fsm))) begin
u2_p3_ce0 = grp_computeDiffSqr_fu_531_u1_p3_ce0;
end else if (((ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st10_fsm_10 == ap_CS_fsm))) begin
u2_p3_ce0 = grp_computeDiffSqr_fu_531_u0_p3_ce0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st130_fsm_130 == ap_CS_fsm))) begin
u2_p3_ce0 = grp_computeResult_fu_467_u_p3_ce0;
end else begin
u2_p3_ce0 = ap_const_logic_0;
end
end
/// u2_p3_ce1 assign process. ///
always @ (ap_CS_fsm or grp_computeDiffSqr_fu_531_u0_p3_ce1)
begin
if (((ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st10_fsm_10 == ap_CS_fsm))) begin
u2_p3_ce1 = grp_computeDiffSqr_fu_531_u0_p3_ce1;
end else begin
u2_p3_ce1 = ap_const_logic_0;
end
end
/// u2_p3_we0 assign process. ///
always @ (ap_CS_fsm or grp_uFetch_array_fu_583_data_p3_we0)
begin
if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st6_fsm_6 == ap_CS_fsm))) begin
u2_p3_we0 = grp_uFetch_array_fu_583_data_p3_we0;
end else begin
u2_p3_we0 = ap_const_logic_0;
end
end
/// u3_p0_address0 assign process. ///
always @ (ap_CS_fsm or grp_computeResult_fu_467_u_p0_address0 or grp_computeDiffSqr_fu_531_u0_p0_address0 or grp_computeDiffSqr_fu_531_u1_p0_address0 or grp_computeUG_fu_555_u_p0_address0 or grp_uFetch_array_fu_583_data_p0_address0)
begin
if (((ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st8_fsm_8 == ap_CS_fsm))) begin
u3_p0_address0 = grp_uFetch_array_fu_583_data_p0_address0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st128_fsm_128 == ap_CS_fsm))) begin
u3_p0_address0 = grp_computeUG_fu_555_u_p0_address0;
end else if (((ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st10_fsm_10 == ap_CS_fsm))) begin
u3_p0_address0 = grp_computeDiffSqr_fu_531_u1_p0_address0;
end else if (((ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st12_fsm_12 == ap_CS_fsm))) begin
u3_p0_address0 = grp_computeDiffSqr_fu_531_u0_p0_address0;
end else if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm))) begin
u3_p0_address0 = grp_computeResult_fu_467_u_p0_address0;
end else begin
u3_p0_address0 = grp_uFetch_array_fu_583_data_p0_address0;
end
end
/// u3_p0_ce0 assign process. ///
always @ (ap_CS_fsm or grp_computeResult_fu_467_u_p0_ce0 or grp_computeDiffSqr_fu_531_u0_p0_ce0 or grp_computeDiffSqr_fu_531_u1_p0_ce0 or grp_computeUG_fu_555_u_p0_ce0 or grp_uFetch_array_fu_583_data_p0_ce0)
begin
if (((ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st8_fsm_8 == ap_CS_fsm))) begin
u3_p0_ce0 = grp_uFetch_array_fu_583_data_p0_ce0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st128_fsm_128 == ap_CS_fsm))) begin
u3_p0_ce0 = grp_computeUG_fu_555_u_p0_ce0;
end else if (((ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st10_fsm_10 == ap_CS_fsm))) begin
u3_p0_ce0 = grp_computeDiffSqr_fu_531_u1_p0_ce0;
end else if (((ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st12_fsm_12 == ap_CS_fsm))) begin
u3_p0_ce0 = grp_computeDiffSqr_fu_531_u0_p0_ce0;
end else if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm))) begin
u3_p0_ce0 = grp_computeResult_fu_467_u_p0_ce0;
end else begin
u3_p0_ce0 = ap_const_logic_0;
end
end
/// u3_p0_we0 assign process. ///
always @ (ap_CS_fsm or grp_uFetch_array_fu_583_data_p0_we0)
begin
if (((ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st8_fsm_8 == ap_CS_fsm))) begin
u3_p0_we0 = grp_uFetch_array_fu_583_data_p0_we0;
end else begin
u3_p0_we0 = ap_const_logic_0;
end
end
/// u3_p1_address0 assign process. ///
always @ (ap_CS_fsm or grp_computeResult_fu_467_u_p1_address0 or grp_computeDiffSqr_fu_531_u0_p1_address0 or grp_computeDiffSqr_fu_531_u1_p1_address0 or grp_computeUG_fu_555_u_p1_address0 or grp_uFetch_array_fu_583_data_p1_address0)
begin
if (((ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st8_fsm_8 == ap_CS_fsm))) begin
u3_p1_address0 = grp_uFetch_array_fu_583_data_p1_address0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st128_fsm_128 == ap_CS_fsm))) begin
u3_p1_address0 = grp_computeUG_fu_555_u_p1_address0;
end else if (((ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st10_fsm_10 == ap_CS_fsm))) begin
u3_p1_address0 = grp_computeDiffSqr_fu_531_u1_p1_address0;
end else if (((ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st12_fsm_12 == ap_CS_fsm))) begin
u3_p1_address0 = grp_computeDiffSqr_fu_531_u0_p1_address0;
end else if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm))) begin
u3_p1_address0 = grp_computeResult_fu_467_u_p1_address0;
end else begin
u3_p1_address0 = grp_uFetch_array_fu_583_data_p1_address0;
end
end
/// u3_p1_ce0 assign process. ///
always @ (ap_CS_fsm or grp_computeResult_fu_467_u_p1_ce0 or grp_computeDiffSqr_fu_531_u0_p1_ce0 or grp_computeDiffSqr_fu_531_u1_p1_ce0 or grp_computeUG_fu_555_u_p1_ce0 or grp_uFetch_array_fu_583_data_p1_ce0)
begin
if (((ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st8_fsm_8 == ap_CS_fsm))) begin
u3_p1_ce0 = grp_uFetch_array_fu_583_data_p1_ce0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st128_fsm_128 == ap_CS_fsm))) begin
u3_p1_ce0 = grp_computeUG_fu_555_u_p1_ce0;
end else if (((ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st10_fsm_10 == ap_CS_fsm))) begin
u3_p1_ce0 = grp_computeDiffSqr_fu_531_u1_p1_ce0;
end else if (((ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st12_fsm_12 == ap_CS_fsm))) begin
u3_p1_ce0 = grp_computeDiffSqr_fu_531_u0_p1_ce0;
end else if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm))) begin
u3_p1_ce0 = grp_computeResult_fu_467_u_p1_ce0;
end else begin
u3_p1_ce0 = ap_const_logic_0;
end
end
/// u3_p1_we0 assign process. ///
always @ (ap_CS_fsm or grp_uFetch_array_fu_583_data_p1_we0)
begin
if (((ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st8_fsm_8 == ap_CS_fsm))) begin
u3_p1_we0 = grp_uFetch_array_fu_583_data_p1_we0;
end else begin
u3_p1_we0 = ap_const_logic_0;
end
end
/// u3_p2_address0 assign process. ///
always @ (ap_CS_fsm or grp_computeResult_fu_467_u_p2_address0 or grp_computeDiffSqr_fu_531_u0_p2_address0 or grp_computeDiffSqr_fu_531_u1_p2_address0 or grp_computeUG_fu_555_u_p2_address0 or grp_uFetch_array_fu_583_data_p2_address0)
begin
if (((ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st8_fsm_8 == ap_CS_fsm))) begin
u3_p2_address0 = grp_uFetch_array_fu_583_data_p2_address0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st128_fsm_128 == ap_CS_fsm))) begin
u3_p2_address0 = grp_computeUG_fu_555_u_p2_address0;
end else if (((ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st10_fsm_10 == ap_CS_fsm))) begin
u3_p2_address0 = grp_computeDiffSqr_fu_531_u1_p2_address0;
end else if (((ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st12_fsm_12 == ap_CS_fsm))) begin
u3_p2_address0 = grp_computeDiffSqr_fu_531_u0_p2_address0;
end else if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm))) begin
u3_p2_address0 = grp_computeResult_fu_467_u_p2_address0;
end else begin
u3_p2_address0 = grp_uFetch_array_fu_583_data_p2_address0;
end
end
/// u3_p2_ce0 assign process. ///
always @ (ap_CS_fsm or grp_computeResult_fu_467_u_p2_ce0 or grp_computeDiffSqr_fu_531_u0_p2_ce0 or grp_computeDiffSqr_fu_531_u1_p2_ce0 or grp_computeUG_fu_555_u_p2_ce0 or grp_uFetch_array_fu_583_data_p2_ce0)
begin
if (((ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st8_fsm_8 == ap_CS_fsm))) begin
u3_p2_ce0 = grp_uFetch_array_fu_583_data_p2_ce0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st128_fsm_128 == ap_CS_fsm))) begin
u3_p2_ce0 = grp_computeUG_fu_555_u_p2_ce0;
end else if (((ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st10_fsm_10 == ap_CS_fsm))) begin
u3_p2_ce0 = grp_computeDiffSqr_fu_531_u1_p2_ce0;
end else if (((ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st12_fsm_12 == ap_CS_fsm))) begin
u3_p2_ce0 = grp_computeDiffSqr_fu_531_u0_p2_ce0;
end else if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm))) begin
u3_p2_ce0 = grp_computeResult_fu_467_u_p2_ce0;
end else begin
u3_p2_ce0 = ap_const_logic_0;
end
end
/// u3_p2_we0 assign process. ///
always @ (ap_CS_fsm or grp_uFetch_array_fu_583_data_p2_we0)
begin
if (((ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st8_fsm_8 == ap_CS_fsm))) begin
u3_p2_we0 = grp_uFetch_array_fu_583_data_p2_we0;
end else begin
u3_p2_we0 = ap_const_logic_0;
end
end
/// u3_p3_address0 assign process. ///
always @ (ap_CS_fsm or grp_computeResult_fu_467_u_p3_address0 or grp_computeDiffSqr_fu_531_u0_p3_address0 or grp_computeDiffSqr_fu_531_u1_p3_address0 or grp_computeUG_fu_555_u_p3_address0 or grp_uFetch_array_fu_583_data_p3_address0)
begin
if (((ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st8_fsm_8 == ap_CS_fsm))) begin
u3_p3_address0 = grp_uFetch_array_fu_583_data_p3_address0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st128_fsm_128 == ap_CS_fsm))) begin
u3_p3_address0 = grp_computeUG_fu_555_u_p3_address0;
end else if (((ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st10_fsm_10 == ap_CS_fsm))) begin
u3_p3_address0 = grp_computeDiffSqr_fu_531_u1_p3_address0;
end else if (((ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st12_fsm_12 == ap_CS_fsm))) begin
u3_p3_address0 = grp_computeDiffSqr_fu_531_u0_p3_address0;
end else if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm))) begin
u3_p3_address0 = grp_computeResult_fu_467_u_p3_address0;
end else begin
u3_p3_address0 = grp_uFetch_array_fu_583_data_p3_address0;
end
end
/// u3_p3_ce0 assign process. ///
always @ (ap_CS_fsm or grp_computeResult_fu_467_u_p3_ce0 or grp_computeDiffSqr_fu_531_u0_p3_ce0 or grp_computeDiffSqr_fu_531_u1_p3_ce0 or grp_computeUG_fu_555_u_p3_ce0 or grp_uFetch_array_fu_583_data_p3_ce0)
begin
if (((ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st8_fsm_8 == ap_CS_fsm))) begin
u3_p3_ce0 = grp_uFetch_array_fu_583_data_p3_ce0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st128_fsm_128 == ap_CS_fsm))) begin
u3_p3_ce0 = grp_computeUG_fu_555_u_p3_ce0;
end else if (((ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st10_fsm_10 == ap_CS_fsm))) begin
u3_p3_ce0 = grp_computeDiffSqr_fu_531_u1_p3_ce0;
end else if (((ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st12_fsm_12 == ap_CS_fsm))) begin
u3_p3_ce0 = grp_computeDiffSqr_fu_531_u0_p3_ce0;
end else if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm))) begin
u3_p3_ce0 = grp_computeResult_fu_467_u_p3_ce0;
end else begin
u3_p3_ce0 = ap_const_logic_0;
end
end
/// u3_p3_ce1 assign process. ///
always @ (ap_CS_fsm or grp_computeDiffSqr_fu_531_u0_p3_ce1)
begin
if (((ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st12_fsm_12 == ap_CS_fsm))) begin
u3_p3_ce1 = grp_computeDiffSqr_fu_531_u0_p3_ce1;
end else begin
u3_p3_ce1 = ap_const_logic_0;
end
end
/// u3_p3_we0 assign process. ///
always @ (ap_CS_fsm or grp_uFetch_array_fu_583_data_p3_we0)
begin
if (((ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st8_fsm_8 == ap_CS_fsm))) begin
u3_p3_we0 = grp_uFetch_array_fu_583_data_p3_we0;
end else begin
u3_p3_we0 = ap_const_logic_0;
end
end
/// u4_p0_address0 assign process. ///
always @ (ap_CS_fsm or grp_computeResult_fu_467_u_p0_address0 or grp_computeDiffSqr_fu_531_u0_p0_address0 or grp_computeDiffSqr_fu_531_u1_p0_address0 or grp_computeUG_fu_555_u_p0_address0 or grp_uFetch_array_fu_583_data_p0_address0)
begin
if (((ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st10_fsm_10 == ap_CS_fsm))) begin
u4_p0_address0 = grp_uFetch_array_fu_583_data_p0_address0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm))) begin
u4_p0_address0 = grp_computeUG_fu_555_u_p0_address0;
end else if (((ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st12_fsm_12 == ap_CS_fsm))) begin
u4_p0_address0 = grp_computeDiffSqr_fu_531_u1_p0_address0;
end else if (((ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st14_fsm_14 == ap_CS_fsm))) begin
u4_p0_address0 = grp_computeDiffSqr_fu_531_u0_p0_address0;
end else if (((ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm))) begin
u4_p0_address0 = grp_computeResult_fu_467_u_p0_address0;
end else begin
u4_p0_address0 = grp_uFetch_array_fu_583_data_p0_address0;
end
end
/// u4_p0_ce0 assign process. ///
always @ (ap_CS_fsm or grp_computeResult_fu_467_u_p0_ce0 or grp_computeDiffSqr_fu_531_u0_p0_ce0 or grp_computeDiffSqr_fu_531_u1_p0_ce0 or grp_computeUG_fu_555_u_p0_ce0 or grp_uFetch_array_fu_583_data_p0_ce0)
begin
if (((ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st10_fsm_10 == ap_CS_fsm))) begin
u4_p0_ce0 = grp_uFetch_array_fu_583_data_p0_ce0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm))) begin
u4_p0_ce0 = grp_computeUG_fu_555_u_p0_ce0;
end else if (((ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st12_fsm_12 == ap_CS_fsm))) begin
u4_p0_ce0 = grp_computeDiffSqr_fu_531_u1_p0_ce0;
end else if (((ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st14_fsm_14 == ap_CS_fsm))) begin
u4_p0_ce0 = grp_computeDiffSqr_fu_531_u0_p0_ce0;
end else if (((ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm))) begin
u4_p0_ce0 = grp_computeResult_fu_467_u_p0_ce0;
end else begin
u4_p0_ce0 = ap_const_logic_0;
end
end
/// u4_p0_we0 assign process. ///
always @ (ap_CS_fsm or grp_uFetch_array_fu_583_data_p0_we0)
begin
if (((ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st10_fsm_10 == ap_CS_fsm))) begin
u4_p0_we0 = grp_uFetch_array_fu_583_data_p0_we0;
end else begin
u4_p0_we0 = ap_const_logic_0;
end
end
/// u4_p1_address0 assign process. ///
always @ (ap_CS_fsm or grp_computeResult_fu_467_u_p1_address0 or grp_computeDiffSqr_fu_531_u0_p1_address0 or grp_computeDiffSqr_fu_531_u1_p1_address0 or grp_computeUG_fu_555_u_p1_address0 or grp_uFetch_array_fu_583_data_p1_address0)
begin
if (((ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st10_fsm_10 == ap_CS_fsm))) begin
u4_p1_address0 = grp_uFetch_array_fu_583_data_p1_address0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm))) begin
u4_p1_address0 = grp_computeUG_fu_555_u_p1_address0;
end else if (((ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st12_fsm_12 == ap_CS_fsm))) begin
u4_p1_address0 = grp_computeDiffSqr_fu_531_u1_p1_address0;
end else if (((ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st14_fsm_14 == ap_CS_fsm))) begin
u4_p1_address0 = grp_computeDiffSqr_fu_531_u0_p1_address0;
end else if (((ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm))) begin
u4_p1_address0 = grp_computeResult_fu_467_u_p1_address0;
end else begin
u4_p1_address0 = grp_uFetch_array_fu_583_data_p1_address0;
end
end
/// u4_p1_ce0 assign process. ///
always @ (ap_CS_fsm or grp_computeResult_fu_467_u_p1_ce0 or grp_computeDiffSqr_fu_531_u0_p1_ce0 or grp_computeDiffSqr_fu_531_u1_p1_ce0 or grp_computeUG_fu_555_u_p1_ce0 or grp_uFetch_array_fu_583_data_p1_ce0)
begin
if (((ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st10_fsm_10 == ap_CS_fsm))) begin
u4_p1_ce0 = grp_uFetch_array_fu_583_data_p1_ce0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm))) begin
u4_p1_ce0 = grp_computeUG_fu_555_u_p1_ce0;
end else if (((ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st12_fsm_12 == ap_CS_fsm))) begin
u4_p1_ce0 = grp_computeDiffSqr_fu_531_u1_p1_ce0;
end else if (((ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st14_fsm_14 == ap_CS_fsm))) begin
u4_p1_ce0 = grp_computeDiffSqr_fu_531_u0_p1_ce0;
end else if (((ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm))) begin
u4_p1_ce0 = grp_computeResult_fu_467_u_p1_ce0;
end else begin
u4_p1_ce0 = ap_const_logic_0;
end
end
/// u4_p1_we0 assign process. ///
always @ (ap_CS_fsm or grp_uFetch_array_fu_583_data_p1_we0)
begin
if (((ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st10_fsm_10 == ap_CS_fsm))) begin
u4_p1_we0 = grp_uFetch_array_fu_583_data_p1_we0;
end else begin
u4_p1_we0 = ap_const_logic_0;
end
end
/// u4_p2_address0 assign process. ///
always @ (ap_CS_fsm or grp_computeResult_fu_467_u_p2_address0 or grp_computeDiffSqr_fu_531_u0_p2_address0 or grp_computeDiffSqr_fu_531_u1_p2_address0 or grp_computeUG_fu_555_u_p2_address0 or grp_uFetch_array_fu_583_data_p2_address0)
begin
if (((ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st10_fsm_10 == ap_CS_fsm))) begin
u4_p2_address0 = grp_uFetch_array_fu_583_data_p2_address0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm))) begin
u4_p2_address0 = grp_computeUG_fu_555_u_p2_address0;
end else if (((ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st12_fsm_12 == ap_CS_fsm))) begin
u4_p2_address0 = grp_computeDiffSqr_fu_531_u1_p2_address0;
end else if (((ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st14_fsm_14 == ap_CS_fsm))) begin
u4_p2_address0 = grp_computeDiffSqr_fu_531_u0_p2_address0;
end else if (((ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm))) begin
u4_p2_address0 = grp_computeResult_fu_467_u_p2_address0;
end else begin
u4_p2_address0 = grp_uFetch_array_fu_583_data_p2_address0;
end
end
/// u4_p2_ce0 assign process. ///
always @ (ap_CS_fsm or grp_computeResult_fu_467_u_p2_ce0 or grp_computeDiffSqr_fu_531_u0_p2_ce0 or grp_computeDiffSqr_fu_531_u1_p2_ce0 or grp_computeUG_fu_555_u_p2_ce0 or grp_uFetch_array_fu_583_data_p2_ce0)
begin
if (((ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st10_fsm_10 == ap_CS_fsm))) begin
u4_p2_ce0 = grp_uFetch_array_fu_583_data_p2_ce0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm))) begin
u4_p2_ce0 = grp_computeUG_fu_555_u_p2_ce0;
end else if (((ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st12_fsm_12 == ap_CS_fsm))) begin
u4_p2_ce0 = grp_computeDiffSqr_fu_531_u1_p2_ce0;
end else if (((ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st14_fsm_14 == ap_CS_fsm))) begin
u4_p2_ce0 = grp_computeDiffSqr_fu_531_u0_p2_ce0;
end else if (((ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm))) begin
u4_p2_ce0 = grp_computeResult_fu_467_u_p2_ce0;
end else begin
u4_p2_ce0 = ap_const_logic_0;
end
end
/// u4_p2_we0 assign process. ///
always @ (ap_CS_fsm or grp_uFetch_array_fu_583_data_p2_we0)
begin
if (((ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st10_fsm_10 == ap_CS_fsm))) begin
u4_p2_we0 = grp_uFetch_array_fu_583_data_p2_we0;
end else begin
u4_p2_we0 = ap_const_logic_0;
end
end
/// u4_p3_address0 assign process. ///
always @ (ap_CS_fsm or grp_computeResult_fu_467_u_p3_address0 or grp_computeDiffSqr_fu_531_u0_p3_address0 or grp_computeDiffSqr_fu_531_u1_p3_address0 or grp_computeUG_fu_555_u_p3_address0 or grp_uFetch_array_fu_583_data_p3_address0)
begin
if (((ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st10_fsm_10 == ap_CS_fsm))) begin
u4_p3_address0 = grp_uFetch_array_fu_583_data_p3_address0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm))) begin
u4_p3_address0 = grp_computeUG_fu_555_u_p3_address0;
end else if (((ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st12_fsm_12 == ap_CS_fsm))) begin
u4_p3_address0 = grp_computeDiffSqr_fu_531_u1_p3_address0;
end else if (((ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st14_fsm_14 == ap_CS_fsm))) begin
u4_p3_address0 = grp_computeDiffSqr_fu_531_u0_p3_address0;
end else if (((ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm))) begin
u4_p3_address0 = grp_computeResult_fu_467_u_p3_address0;
end else begin
u4_p3_address0 = grp_uFetch_array_fu_583_data_p3_address0;
end
end
/// u4_p3_ce0 assign process. ///
always @ (ap_CS_fsm or grp_computeResult_fu_467_u_p3_ce0 or grp_computeDiffSqr_fu_531_u0_p3_ce0 or grp_computeDiffSqr_fu_531_u1_p3_ce0 or grp_computeUG_fu_555_u_p3_ce0 or grp_uFetch_array_fu_583_data_p3_ce0)
begin
if (((ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st10_fsm_10 == ap_CS_fsm))) begin
u4_p3_ce0 = grp_uFetch_array_fu_583_data_p3_ce0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm))) begin
u4_p3_ce0 = grp_computeUG_fu_555_u_p3_ce0;
end else if (((ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st12_fsm_12 == ap_CS_fsm))) begin
u4_p3_ce0 = grp_computeDiffSqr_fu_531_u1_p3_ce0;
end else if (((ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st14_fsm_14 == ap_CS_fsm))) begin
u4_p3_ce0 = grp_computeDiffSqr_fu_531_u0_p3_ce0;
end else if (((ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm))) begin
u4_p3_ce0 = grp_computeResult_fu_467_u_p3_ce0;
end else begin
u4_p3_ce0 = ap_const_logic_0;
end
end
/// u4_p3_ce1 assign process. ///
always @ (ap_CS_fsm or grp_computeDiffSqr_fu_531_u0_p3_ce1)
begin
if (((ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st14_fsm_14 == ap_CS_fsm))) begin
u4_p3_ce1 = grp_computeDiffSqr_fu_531_u0_p3_ce1;
end else begin
u4_p3_ce1 = ap_const_logic_0;
end
end
/// u4_p3_we0 assign process. ///
always @ (ap_CS_fsm or grp_uFetch_array_fu_583_data_p3_we0)
begin
if (((ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st10_fsm_10 == ap_CS_fsm))) begin
u4_p3_we0 = grp_uFetch_array_fu_583_data_p3_we0;
end else begin
u4_p3_we0 = ap_const_logic_0;
end
end
/// u5_p0_address0 assign process. ///
always @ (ap_CS_fsm or grp_computeResult_fu_467_u_p0_address0 or grp_computeDiffSqr_fu_531_u0_p0_address0 or grp_computeDiffSqr_fu_531_u1_p0_address0 or grp_computeUG_fu_555_u_p0_address0 or grp_uFetch_array_fu_583_data_p0_address0)
begin
if (((ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st12_fsm_12 == ap_CS_fsm))) begin
u5_p0_address0 = grp_uFetch_array_fu_583_data_p0_address0;
end else if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm))) begin
u5_p0_address0 = grp_computeUG_fu_555_u_p0_address0;
end else if (((ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st14_fsm_14 == ap_CS_fsm))) begin
u5_p0_address0 = grp_computeDiffSqr_fu_531_u1_p0_address0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm))) begin
u5_p0_address0 = grp_computeDiffSqr_fu_531_u0_p0_address0;
end else if (((ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm))) begin
u5_p0_address0 = grp_computeResult_fu_467_u_p0_address0;
end else begin
u5_p0_address0 = grp_uFetch_array_fu_583_data_p0_address0;
end
end
/// u5_p0_ce0 assign process. ///
always @ (ap_CS_fsm or grp_computeResult_fu_467_u_p0_ce0 or grp_computeDiffSqr_fu_531_u0_p0_ce0 or grp_computeDiffSqr_fu_531_u1_p0_ce0 or grp_computeUG_fu_555_u_p0_ce0 or grp_uFetch_array_fu_583_data_p0_ce0)
begin
if (((ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st12_fsm_12 == ap_CS_fsm))) begin
u5_p0_ce0 = grp_uFetch_array_fu_583_data_p0_ce0;
end else if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm))) begin
u5_p0_ce0 = grp_computeUG_fu_555_u_p0_ce0;
end else if (((ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st14_fsm_14 == ap_CS_fsm))) begin
u5_p0_ce0 = grp_computeDiffSqr_fu_531_u1_p0_ce0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm))) begin
u5_p0_ce0 = grp_computeDiffSqr_fu_531_u0_p0_ce0;
end else if (((ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm))) begin
u5_p0_ce0 = grp_computeResult_fu_467_u_p0_ce0;
end else begin
u5_p0_ce0 = ap_const_logic_0;
end
end
/// u5_p0_we0 assign process. ///
always @ (ap_CS_fsm or grp_uFetch_array_fu_583_data_p0_we0)
begin
if (((ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st12_fsm_12 == ap_CS_fsm))) begin
u5_p0_we0 = grp_uFetch_array_fu_583_data_p0_we0;
end else begin
u5_p0_we0 = ap_const_logic_0;
end
end
/// u5_p1_address0 assign process. ///
always @ (ap_CS_fsm or grp_computeResult_fu_467_u_p1_address0 or grp_computeDiffSqr_fu_531_u0_p1_address0 or grp_computeDiffSqr_fu_531_u1_p1_address0 or grp_computeUG_fu_555_u_p1_address0 or grp_uFetch_array_fu_583_data_p1_address0)
begin
if (((ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st12_fsm_12 == ap_CS_fsm))) begin
u5_p1_address0 = grp_uFetch_array_fu_583_data_p1_address0;
end else if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm))) begin
u5_p1_address0 = grp_computeUG_fu_555_u_p1_address0;
end else if (((ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st14_fsm_14 == ap_CS_fsm))) begin
u5_p1_address0 = grp_computeDiffSqr_fu_531_u1_p1_address0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm))) begin
u5_p1_address0 = grp_computeDiffSqr_fu_531_u0_p1_address0;
end else if (((ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm))) begin
u5_p1_address0 = grp_computeResult_fu_467_u_p1_address0;
end else begin
u5_p1_address0 = grp_uFetch_array_fu_583_data_p1_address0;
end
end
/// u5_p1_ce0 assign process. ///
always @ (ap_CS_fsm or grp_computeResult_fu_467_u_p1_ce0 or grp_computeDiffSqr_fu_531_u0_p1_ce0 or grp_computeDiffSqr_fu_531_u1_p1_ce0 or grp_computeUG_fu_555_u_p1_ce0 or grp_uFetch_array_fu_583_data_p1_ce0)
begin
if (((ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st12_fsm_12 == ap_CS_fsm))) begin
u5_p1_ce0 = grp_uFetch_array_fu_583_data_p1_ce0;
end else if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm))) begin
u5_p1_ce0 = grp_computeUG_fu_555_u_p1_ce0;
end else if (((ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st14_fsm_14 == ap_CS_fsm))) begin
u5_p1_ce0 = grp_computeDiffSqr_fu_531_u1_p1_ce0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm))) begin
u5_p1_ce0 = grp_computeDiffSqr_fu_531_u0_p1_ce0;
end else if (((ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm))) begin
u5_p1_ce0 = grp_computeResult_fu_467_u_p1_ce0;
end else begin
u5_p1_ce0 = ap_const_logic_0;
end
end
/// u5_p1_we0 assign process. ///
always @ (ap_CS_fsm or grp_uFetch_array_fu_583_data_p1_we0)
begin
if (((ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st12_fsm_12 == ap_CS_fsm))) begin
u5_p1_we0 = grp_uFetch_array_fu_583_data_p1_we0;
end else begin
u5_p1_we0 = ap_const_logic_0;
end
end
/// u5_p2_address0 assign process. ///
always @ (ap_CS_fsm or grp_computeResult_fu_467_u_p2_address0 or grp_computeDiffSqr_fu_531_u0_p2_address0 or grp_computeDiffSqr_fu_531_u1_p2_address0 or grp_computeUG_fu_555_u_p2_address0 or grp_uFetch_array_fu_583_data_p2_address0)
begin
if (((ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st12_fsm_12 == ap_CS_fsm))) begin
u5_p2_address0 = grp_uFetch_array_fu_583_data_p2_address0;
end else if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm))) begin
u5_p2_address0 = grp_computeUG_fu_555_u_p2_address0;
end else if (((ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st14_fsm_14 == ap_CS_fsm))) begin
u5_p2_address0 = grp_computeDiffSqr_fu_531_u1_p2_address0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm))) begin
u5_p2_address0 = grp_computeDiffSqr_fu_531_u0_p2_address0;
end else if (((ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm))) begin
u5_p2_address0 = grp_computeResult_fu_467_u_p2_address0;
end else begin
u5_p2_address0 = grp_uFetch_array_fu_583_data_p2_address0;
end
end
/// u5_p2_ce0 assign process. ///
always @ (ap_CS_fsm or grp_computeResult_fu_467_u_p2_ce0 or grp_computeDiffSqr_fu_531_u0_p2_ce0 or grp_computeDiffSqr_fu_531_u1_p2_ce0 or grp_computeUG_fu_555_u_p2_ce0 or grp_uFetch_array_fu_583_data_p2_ce0)
begin
if (((ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st12_fsm_12 == ap_CS_fsm))) begin
u5_p2_ce0 = grp_uFetch_array_fu_583_data_p2_ce0;
end else if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm))) begin
u5_p2_ce0 = grp_computeUG_fu_555_u_p2_ce0;
end else if (((ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st14_fsm_14 == ap_CS_fsm))) begin
u5_p2_ce0 = grp_computeDiffSqr_fu_531_u1_p2_ce0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm))) begin
u5_p2_ce0 = grp_computeDiffSqr_fu_531_u0_p2_ce0;
end else if (((ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm))) begin
u5_p2_ce0 = grp_computeResult_fu_467_u_p2_ce0;
end else begin
u5_p2_ce0 = ap_const_logic_0;
end
end
/// u5_p2_we0 assign process. ///
always @ (ap_CS_fsm or grp_uFetch_array_fu_583_data_p2_we0)
begin
if (((ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st12_fsm_12 == ap_CS_fsm))) begin
u5_p2_we0 = grp_uFetch_array_fu_583_data_p2_we0;
end else begin
u5_p2_we0 = ap_const_logic_0;
end
end
/// u5_p3_address0 assign process. ///
always @ (ap_CS_fsm or grp_computeResult_fu_467_u_p3_address0 or grp_computeDiffSqr_fu_531_u0_p3_address0 or grp_computeDiffSqr_fu_531_u1_p3_address0 or grp_computeUG_fu_555_u_p3_address0 or grp_uFetch_array_fu_583_data_p3_address0)
begin
if (((ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st12_fsm_12 == ap_CS_fsm))) begin
u5_p3_address0 = grp_uFetch_array_fu_583_data_p3_address0;
end else if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm))) begin
u5_p3_address0 = grp_computeUG_fu_555_u_p3_address0;
end else if (((ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st14_fsm_14 == ap_CS_fsm))) begin
u5_p3_address0 = grp_computeDiffSqr_fu_531_u1_p3_address0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm))) begin
u5_p3_address0 = grp_computeDiffSqr_fu_531_u0_p3_address0;
end else if (((ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm))) begin
u5_p3_address0 = grp_computeResult_fu_467_u_p3_address0;
end else begin
u5_p3_address0 = grp_uFetch_array_fu_583_data_p3_address0;
end
end
/// u5_p3_ce0 assign process. ///
always @ (ap_CS_fsm or grp_computeResult_fu_467_u_p3_ce0 or grp_computeDiffSqr_fu_531_u0_p3_ce0 or grp_computeDiffSqr_fu_531_u1_p3_ce0 or grp_computeUG_fu_555_u_p3_ce0 or grp_uFetch_array_fu_583_data_p3_ce0)
begin
if (((ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st12_fsm_12 == ap_CS_fsm))) begin
u5_p3_ce0 = grp_uFetch_array_fu_583_data_p3_ce0;
end else if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm))) begin
u5_p3_ce0 = grp_computeUG_fu_555_u_p3_ce0;
end else if (((ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st14_fsm_14 == ap_CS_fsm))) begin
u5_p3_ce0 = grp_computeDiffSqr_fu_531_u1_p3_ce0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm))) begin
u5_p3_ce0 = grp_computeDiffSqr_fu_531_u0_p3_ce0;
end else if (((ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm))) begin
u5_p3_ce0 = grp_computeResult_fu_467_u_p3_ce0;
end else begin
u5_p3_ce0 = ap_const_logic_0;
end
end
/// u5_p3_ce1 assign process. ///
always @ (ap_CS_fsm or grp_computeDiffSqr_fu_531_u0_p3_ce1)
begin
if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm))) begin
u5_p3_ce1 = grp_computeDiffSqr_fu_531_u0_p3_ce1;
end else begin
u5_p3_ce1 = ap_const_logic_0;
end
end
/// u5_p3_we0 assign process. ///
always @ (ap_CS_fsm or grp_uFetch_array_fu_583_data_p3_we0)
begin
if (((ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st12_fsm_12 == ap_CS_fsm))) begin
u5_p3_we0 = grp_uFetch_array_fu_583_data_p3_we0;
end else begin
u5_p3_we0 = ap_const_logic_0;
end
end
/// u6_p0_address0 assign process. ///
always @ (ap_CS_fsm or grp_computeResult_fu_467_u_p0_address0 or grp_computeDiffSqr_fu_531_u0_p0_address0 or grp_computeDiffSqr_fu_531_u1_p0_address0 or grp_computeUG_fu_555_u_p0_address0 or grp_uFetch_array_fu_583_data_p0_address0)
begin
if (((ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st14_fsm_14 == ap_CS_fsm))) begin
u6_p0_address0 = grp_uFetch_array_fu_583_data_p0_address0;
end else if (((ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm))) begin
u6_p0_address0 = grp_computeUG_fu_555_u_p0_address0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm))) begin
u6_p0_address0 = grp_computeDiffSqr_fu_531_u1_p0_address0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm))) begin
u6_p0_address0 = grp_computeDiffSqr_fu_531_u0_p0_address0;
end else if (((ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm))) begin
u6_p0_address0 = grp_computeResult_fu_467_u_p0_address0;
end else begin
u6_p0_address0 = grp_uFetch_array_fu_583_data_p0_address0;
end
end
/// u6_p0_ce0 assign process. ///
always @ (ap_CS_fsm or grp_computeResult_fu_467_u_p0_ce0 or grp_computeDiffSqr_fu_531_u0_p0_ce0 or grp_computeDiffSqr_fu_531_u1_p0_ce0 or grp_computeUG_fu_555_u_p0_ce0 or grp_uFetch_array_fu_583_data_p0_ce0)
begin
if (((ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st14_fsm_14 == ap_CS_fsm))) begin
u6_p0_ce0 = grp_uFetch_array_fu_583_data_p0_ce0;
end else if (((ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm))) begin
u6_p0_ce0 = grp_computeUG_fu_555_u_p0_ce0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm))) begin
u6_p0_ce0 = grp_computeDiffSqr_fu_531_u1_p0_ce0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm))) begin
u6_p0_ce0 = grp_computeDiffSqr_fu_531_u0_p0_ce0;
end else if (((ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm))) begin
u6_p0_ce0 = grp_computeResult_fu_467_u_p0_ce0;
end else begin
u6_p0_ce0 = ap_const_logic_0;
end
end
/// u6_p0_we0 assign process. ///
always @ (ap_CS_fsm or grp_uFetch_array_fu_583_data_p0_we0)
begin
if (((ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st14_fsm_14 == ap_CS_fsm))) begin
u6_p0_we0 = grp_uFetch_array_fu_583_data_p0_we0;
end else begin
u6_p0_we0 = ap_const_logic_0;
end
end
/// u6_p1_address0 assign process. ///
always @ (ap_CS_fsm or grp_computeResult_fu_467_u_p1_address0 or grp_computeDiffSqr_fu_531_u0_p1_address0 or grp_computeDiffSqr_fu_531_u1_p1_address0 or grp_computeUG_fu_555_u_p1_address0 or grp_uFetch_array_fu_583_data_p1_address0)
begin
if (((ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st14_fsm_14 == ap_CS_fsm))) begin
u6_p1_address0 = grp_uFetch_array_fu_583_data_p1_address0;
end else if (((ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm))) begin
u6_p1_address0 = grp_computeUG_fu_555_u_p1_address0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm))) begin
u6_p1_address0 = grp_computeDiffSqr_fu_531_u1_p1_address0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm))) begin
u6_p1_address0 = grp_computeDiffSqr_fu_531_u0_p1_address0;
end else if (((ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm))) begin
u6_p1_address0 = grp_computeResult_fu_467_u_p1_address0;
end else begin
u6_p1_address0 = grp_uFetch_array_fu_583_data_p1_address0;
end
end
/// u6_p1_ce0 assign process. ///
always @ (ap_CS_fsm or grp_computeResult_fu_467_u_p1_ce0 or grp_computeDiffSqr_fu_531_u0_p1_ce0 or grp_computeDiffSqr_fu_531_u1_p1_ce0 or grp_computeUG_fu_555_u_p1_ce0 or grp_uFetch_array_fu_583_data_p1_ce0)
begin
if (((ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st14_fsm_14 == ap_CS_fsm))) begin
u6_p1_ce0 = grp_uFetch_array_fu_583_data_p1_ce0;
end else if (((ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm))) begin
u6_p1_ce0 = grp_computeUG_fu_555_u_p1_ce0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm))) begin
u6_p1_ce0 = grp_computeDiffSqr_fu_531_u1_p1_ce0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm))) begin
u6_p1_ce0 = grp_computeDiffSqr_fu_531_u0_p1_ce0;
end else if (((ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm))) begin
u6_p1_ce0 = grp_computeResult_fu_467_u_p1_ce0;
end else begin
u6_p1_ce0 = ap_const_logic_0;
end
end
/// u6_p1_we0 assign process. ///
always @ (ap_CS_fsm or grp_uFetch_array_fu_583_data_p1_we0)
begin
if (((ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st14_fsm_14 == ap_CS_fsm))) begin
u6_p1_we0 = grp_uFetch_array_fu_583_data_p1_we0;
end else begin
u6_p1_we0 = ap_const_logic_0;
end
end
/// u6_p2_address0 assign process. ///
always @ (ap_CS_fsm or grp_computeResult_fu_467_u_p2_address0 or grp_computeDiffSqr_fu_531_u0_p2_address0 or grp_computeDiffSqr_fu_531_u1_p2_address0 or grp_computeUG_fu_555_u_p2_address0 or grp_uFetch_array_fu_583_data_p2_address0)
begin
if (((ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st14_fsm_14 == ap_CS_fsm))) begin
u6_p2_address0 = grp_uFetch_array_fu_583_data_p2_address0;
end else if (((ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm))) begin
u6_p2_address0 = grp_computeUG_fu_555_u_p2_address0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm))) begin
u6_p2_address0 = grp_computeDiffSqr_fu_531_u1_p2_address0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm))) begin
u6_p2_address0 = grp_computeDiffSqr_fu_531_u0_p2_address0;
end else if (((ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm))) begin
u6_p2_address0 = grp_computeResult_fu_467_u_p2_address0;
end else begin
u6_p2_address0 = grp_uFetch_array_fu_583_data_p2_address0;
end
end
/// u6_p2_ce0 assign process. ///
always @ (ap_CS_fsm or grp_computeResult_fu_467_u_p2_ce0 or grp_computeDiffSqr_fu_531_u0_p2_ce0 or grp_computeDiffSqr_fu_531_u1_p2_ce0 or grp_computeUG_fu_555_u_p2_ce0 or grp_uFetch_array_fu_583_data_p2_ce0)
begin
if (((ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st14_fsm_14 == ap_CS_fsm))) begin
u6_p2_ce0 = grp_uFetch_array_fu_583_data_p2_ce0;
end else if (((ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm))) begin
u6_p2_ce0 = grp_computeUG_fu_555_u_p2_ce0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm))) begin
u6_p2_ce0 = grp_computeDiffSqr_fu_531_u1_p2_ce0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm))) begin
u6_p2_ce0 = grp_computeDiffSqr_fu_531_u0_p2_ce0;
end else if (((ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm))) begin
u6_p2_ce0 = grp_computeResult_fu_467_u_p2_ce0;
end else begin
u6_p2_ce0 = ap_const_logic_0;
end
end
/// u6_p2_we0 assign process. ///
always @ (ap_CS_fsm or grp_uFetch_array_fu_583_data_p2_we0)
begin
if (((ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st14_fsm_14 == ap_CS_fsm))) begin
u6_p2_we0 = grp_uFetch_array_fu_583_data_p2_we0;
end else begin
u6_p2_we0 = ap_const_logic_0;
end
end
/// u6_p3_address0 assign process. ///
always @ (ap_CS_fsm or grp_computeResult_fu_467_u_p3_address0 or grp_computeDiffSqr_fu_531_u0_p3_address0 or grp_computeDiffSqr_fu_531_u1_p3_address0 or grp_computeUG_fu_555_u_p3_address0 or grp_uFetch_array_fu_583_data_p3_address0)
begin
if (((ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st14_fsm_14 == ap_CS_fsm))) begin
u6_p3_address0 = grp_uFetch_array_fu_583_data_p3_address0;
end else if (((ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm))) begin
u6_p3_address0 = grp_computeUG_fu_555_u_p3_address0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm))) begin
u6_p3_address0 = grp_computeDiffSqr_fu_531_u1_p3_address0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm))) begin
u6_p3_address0 = grp_computeDiffSqr_fu_531_u0_p3_address0;
end else if (((ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm))) begin
u6_p3_address0 = grp_computeResult_fu_467_u_p3_address0;
end else begin
u6_p3_address0 = grp_uFetch_array_fu_583_data_p3_address0;
end
end
/// u6_p3_ce0 assign process. ///
always @ (ap_CS_fsm or grp_computeResult_fu_467_u_p3_ce0 or grp_computeDiffSqr_fu_531_u0_p3_ce0 or grp_computeDiffSqr_fu_531_u1_p3_ce0 or grp_computeUG_fu_555_u_p3_ce0 or grp_uFetch_array_fu_583_data_p3_ce0)
begin
if (((ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st14_fsm_14 == ap_CS_fsm))) begin
u6_p3_ce0 = grp_uFetch_array_fu_583_data_p3_ce0;
end else if (((ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm))) begin
u6_p3_ce0 = grp_computeUG_fu_555_u_p3_ce0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm))) begin
u6_p3_ce0 = grp_computeDiffSqr_fu_531_u1_p3_ce0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm))) begin
u6_p3_ce0 = grp_computeDiffSqr_fu_531_u0_p3_ce0;
end else if (((ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm))) begin
u6_p3_ce0 = grp_computeResult_fu_467_u_p3_ce0;
end else begin
u6_p3_ce0 = ap_const_logic_0;
end
end
/// u6_p3_ce1 assign process. ///
always @ (ap_CS_fsm or grp_computeDiffSqr_fu_531_u0_p3_ce1)
begin
if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm))) begin
u6_p3_ce1 = grp_computeDiffSqr_fu_531_u0_p3_ce1;
end else begin
u6_p3_ce1 = ap_const_logic_0;
end
end
/// u6_p3_we0 assign process. ///
always @ (ap_CS_fsm or grp_uFetch_array_fu_583_data_p3_we0)
begin
if (((ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st14_fsm_14 == ap_CS_fsm))) begin
u6_p3_we0 = grp_uFetch_array_fu_583_data_p3_we0;
end else begin
u6_p3_we0 = ap_const_logic_0;
end
end
/// ug0_p0_address0 assign process. ///
always @ (ap_CS_fsm or grp_computeResult_fu_467_ug0_p0_address0 or grp_computeResult_fu_467_ug1_p0_address0 or grp_computeResult_fu_467_ug2_p0_address0 or grp_computeUG_fu_555_ug_p0_address0)
begin
if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm))) begin
ug0_p0_address0 = grp_computeUG_fu_555_ug_p0_address0;
end else if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm))) begin
ug0_p0_address0 = grp_computeResult_fu_467_ug2_p0_address0;
end else if (((ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st126_fsm_126 == ap_CS_fsm))) begin
ug0_p0_address0 = grp_computeResult_fu_467_ug1_p0_address0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st128_fsm_128 == ap_CS_fsm))) begin
ug0_p0_address0 = grp_computeResult_fu_467_ug0_p0_address0;
end else begin
ug0_p0_address0 = grp_computeUG_fu_555_ug_p0_address0;
end
end
/// ug0_p0_ce0 assign process. ///
always @ (ap_CS_fsm or grp_computeResult_fu_467_ug0_p0_ce0 or grp_computeResult_fu_467_ug1_p0_ce0 or grp_computeResult_fu_467_ug2_p0_ce0 or grp_computeUG_fu_555_ug_p0_ce0)
begin
if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm))) begin
ug0_p0_ce0 = grp_computeUG_fu_555_ug_p0_ce0;
end else if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm))) begin
ug0_p0_ce0 = grp_computeResult_fu_467_ug2_p0_ce0;
end else if (((ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st126_fsm_126 == ap_CS_fsm))) begin
ug0_p0_ce0 = grp_computeResult_fu_467_ug1_p0_ce0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st128_fsm_128 == ap_CS_fsm))) begin
ug0_p0_ce0 = grp_computeResult_fu_467_ug0_p0_ce0;
end else begin
ug0_p0_ce0 = ap_const_logic_0;
end
end
/// ug0_p0_ce1 assign process. ///
always @ (ap_CS_fsm or grp_computeResult_fu_467_ug1_p0_ce1)
begin
if (((ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st126_fsm_126 == ap_CS_fsm))) begin
ug0_p0_ce1 = grp_computeResult_fu_467_ug1_p0_ce1;
end else begin
ug0_p0_ce1 = ap_const_logic_0;
end
end
/// ug0_p0_we0 assign process. ///
always @ (ap_CS_fsm or grp_computeUG_fu_555_ug_p0_we0)
begin
if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm))) begin
ug0_p0_we0 = grp_computeUG_fu_555_ug_p0_we0;
end else begin
ug0_p0_we0 = ap_const_logic_0;
end
end
/// ug0_p1_address0 assign process. ///
always @ (ap_CS_fsm or grp_computeResult_fu_467_ug0_p1_address0 or grp_computeResult_fu_467_ug1_p1_address0 or grp_computeResult_fu_467_ug2_p1_address0 or grp_computeUG_fu_555_ug_p1_address0)
begin
if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm))) begin
ug0_p1_address0 = grp_computeUG_fu_555_ug_p1_address0;
end else if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm))) begin
ug0_p1_address0 = grp_computeResult_fu_467_ug2_p1_address0;
end else if (((ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st126_fsm_126 == ap_CS_fsm))) begin
ug0_p1_address0 = grp_computeResult_fu_467_ug1_p1_address0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st128_fsm_128 == ap_CS_fsm))) begin
ug0_p1_address0 = grp_computeResult_fu_467_ug0_p1_address0;
end else begin
ug0_p1_address0 = grp_computeUG_fu_555_ug_p1_address0;
end
end
/// ug0_p1_ce0 assign process. ///
always @ (ap_CS_fsm or grp_computeResult_fu_467_ug0_p1_ce0 or grp_computeResult_fu_467_ug1_p1_ce0 or grp_computeResult_fu_467_ug2_p1_ce0 or grp_computeUG_fu_555_ug_p1_ce0)
begin
if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm))) begin
ug0_p1_ce0 = grp_computeUG_fu_555_ug_p1_ce0;
end else if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm))) begin
ug0_p1_ce0 = grp_computeResult_fu_467_ug2_p1_ce0;
end else if (((ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st126_fsm_126 == ap_CS_fsm))) begin
ug0_p1_ce0 = grp_computeResult_fu_467_ug1_p1_ce0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st128_fsm_128 == ap_CS_fsm))) begin
ug0_p1_ce0 = grp_computeResult_fu_467_ug0_p1_ce0;
end else begin
ug0_p1_ce0 = ap_const_logic_0;
end
end
/// ug0_p1_we0 assign process. ///
always @ (ap_CS_fsm or grp_computeUG_fu_555_ug_p1_we0)
begin
if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm))) begin
ug0_p1_we0 = grp_computeUG_fu_555_ug_p1_we0;
end else begin
ug0_p1_we0 = ap_const_logic_0;
end
end
/// ug0_p2_address0 assign process. ///
always @ (ap_CS_fsm or grp_computeResult_fu_467_ug0_p2_address0 or grp_computeResult_fu_467_ug1_p2_address0 or grp_computeResult_fu_467_ug2_p2_address0 or grp_computeUG_fu_555_ug_p2_address0)
begin
if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm))) begin
ug0_p2_address0 = grp_computeUG_fu_555_ug_p2_address0;
end else if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm))) begin
ug0_p2_address0 = grp_computeResult_fu_467_ug2_p2_address0;
end else if (((ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st126_fsm_126 == ap_CS_fsm))) begin
ug0_p2_address0 = grp_computeResult_fu_467_ug1_p2_address0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st128_fsm_128 == ap_CS_fsm))) begin
ug0_p2_address0 = grp_computeResult_fu_467_ug0_p2_address0;
end else begin
ug0_p2_address0 = grp_computeUG_fu_555_ug_p2_address0;
end
end
/// ug0_p2_ce0 assign process. ///
always @ (ap_CS_fsm or grp_computeResult_fu_467_ug0_p2_ce0 or grp_computeResult_fu_467_ug1_p2_ce0 or grp_computeResult_fu_467_ug2_p2_ce0 or grp_computeUG_fu_555_ug_p2_ce0)
begin
if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm))) begin
ug0_p2_ce0 = grp_computeUG_fu_555_ug_p2_ce0;
end else if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm))) begin
ug0_p2_ce0 = grp_computeResult_fu_467_ug2_p2_ce0;
end else if (((ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st126_fsm_126 == ap_CS_fsm))) begin
ug0_p2_ce0 = grp_computeResult_fu_467_ug1_p2_ce0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st128_fsm_128 == ap_CS_fsm))) begin
ug0_p2_ce0 = grp_computeResult_fu_467_ug0_p2_ce0;
end else begin
ug0_p2_ce0 = ap_const_logic_0;
end
end
/// ug0_p2_we0 assign process. ///
always @ (ap_CS_fsm or grp_computeUG_fu_555_ug_p2_we0)
begin
if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm))) begin
ug0_p2_we0 = grp_computeUG_fu_555_ug_p2_we0;
end else begin
ug0_p2_we0 = ap_const_logic_0;
end
end
/// ug0_p3_address0 assign process. ///
always @ (ap_CS_fsm or grp_computeResult_fu_467_ug0_p3_address0 or grp_computeResult_fu_467_ug1_p3_address0 or grp_computeResult_fu_467_ug2_p3_address0 or grp_computeUG_fu_555_ug_p3_address0)
begin
if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm))) begin
ug0_p3_address0 = grp_computeUG_fu_555_ug_p3_address0;
end else if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm))) begin
ug0_p3_address0 = grp_computeResult_fu_467_ug2_p3_address0;
end else if (((ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st126_fsm_126 == ap_CS_fsm))) begin
ug0_p3_address0 = grp_computeResult_fu_467_ug1_p3_address0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st128_fsm_128 == ap_CS_fsm))) begin
ug0_p3_address0 = grp_computeResult_fu_467_ug0_p3_address0;
end else begin
ug0_p3_address0 = grp_computeUG_fu_555_ug_p3_address0;
end
end
/// ug0_p3_ce0 assign process. ///
always @ (ap_CS_fsm or grp_computeResult_fu_467_ug0_p3_ce0 or grp_computeResult_fu_467_ug1_p3_ce0 or grp_computeResult_fu_467_ug2_p3_ce0 or grp_computeUG_fu_555_ug_p3_ce0)
begin
if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm))) begin
ug0_p3_ce0 = grp_computeUG_fu_555_ug_p3_ce0;
end else if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm))) begin
ug0_p3_ce0 = grp_computeResult_fu_467_ug2_p3_ce0;
end else if (((ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st126_fsm_126 == ap_CS_fsm))) begin
ug0_p3_ce0 = grp_computeResult_fu_467_ug1_p3_ce0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st128_fsm_128 == ap_CS_fsm))) begin
ug0_p3_ce0 = grp_computeResult_fu_467_ug0_p3_ce0;
end else begin
ug0_p3_ce0 = ap_const_logic_0;
end
end
/// ug0_p3_ce1 assign process. ///
always @ (ap_CS_fsm or grp_computeResult_fu_467_ug1_p3_ce1)
begin
if (((ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st126_fsm_126 == ap_CS_fsm))) begin
ug0_p3_ce1 = grp_computeResult_fu_467_ug1_p3_ce1;
end else begin
ug0_p3_ce1 = ap_const_logic_0;
end
end
/// ug0_p3_we0 assign process. ///
always @ (ap_CS_fsm or grp_computeUG_fu_555_ug_p3_we0)
begin
if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm))) begin
ug0_p3_we0 = grp_computeUG_fu_555_ug_p3_we0;
end else begin
ug0_p3_we0 = ap_const_logic_0;
end
end
/// ug1_p0_address0 assign process. ///
always @ (ap_CS_fsm or grp_computeResult_fu_467_ug0_p0_address0 or grp_computeResult_fu_467_ug1_p0_address0 or grp_computeResult_fu_467_ug2_p0_address0 or grp_computeUG_fu_555_ug_p0_address0)
begin
if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm) | (ap_ST_st12_fsm_12 == ap_CS_fsm))) begin
ug1_p0_address0 = grp_computeUG_fu_555_ug_p0_address0;
end else if (((ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st126_fsm_126 == ap_CS_fsm))) begin
ug1_p0_address0 = grp_computeResult_fu_467_ug2_p0_address0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st128_fsm_128 == ap_CS_fsm))) begin
ug1_p0_address0 = grp_computeResult_fu_467_ug1_p0_address0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st130_fsm_130 == ap_CS_fsm))) begin
ug1_p0_address0 = grp_computeResult_fu_467_ug0_p0_address0;
end else begin
ug1_p0_address0 = grp_computeUG_fu_555_ug_p0_address0;
end
end
/// ug1_p0_ce0 assign process. ///
always @ (ap_CS_fsm or grp_computeResult_fu_467_ug0_p0_ce0 or grp_computeResult_fu_467_ug1_p0_ce0 or grp_computeResult_fu_467_ug2_p0_ce0 or grp_computeUG_fu_555_ug_p0_ce0)
begin
if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm) | (ap_ST_st12_fsm_12 == ap_CS_fsm))) begin
ug1_p0_ce0 = grp_computeUG_fu_555_ug_p0_ce0;
end else if (((ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st126_fsm_126 == ap_CS_fsm))) begin
ug1_p0_ce0 = grp_computeResult_fu_467_ug2_p0_ce0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st128_fsm_128 == ap_CS_fsm))) begin
ug1_p0_ce0 = grp_computeResult_fu_467_ug1_p0_ce0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st130_fsm_130 == ap_CS_fsm))) begin
ug1_p0_ce0 = grp_computeResult_fu_467_ug0_p0_ce0;
end else begin
ug1_p0_ce0 = ap_const_logic_0;
end
end
/// ug1_p0_ce1 assign process. ///
always @ (ap_CS_fsm or grp_computeResult_fu_467_ug1_p0_ce1)
begin
if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st128_fsm_128 == ap_CS_fsm))) begin
ug1_p0_ce1 = grp_computeResult_fu_467_ug1_p0_ce1;
end else begin
ug1_p0_ce1 = ap_const_logic_0;
end
end
/// ug1_p0_we0 assign process. ///
always @ (ap_CS_fsm or grp_computeUG_fu_555_ug_p0_we0)
begin
if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm) | (ap_ST_st12_fsm_12 == ap_CS_fsm))) begin
ug1_p0_we0 = grp_computeUG_fu_555_ug_p0_we0;
end else begin
ug1_p0_we0 = ap_const_logic_0;
end
end
/// ug1_p1_address0 assign process. ///
always @ (ap_CS_fsm or grp_computeResult_fu_467_ug0_p1_address0 or grp_computeResult_fu_467_ug1_p1_address0 or grp_computeResult_fu_467_ug2_p1_address0 or grp_computeUG_fu_555_ug_p1_address0)
begin
if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm) | (ap_ST_st12_fsm_12 == ap_CS_fsm))) begin
ug1_p1_address0 = grp_computeUG_fu_555_ug_p1_address0;
end else if (((ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st126_fsm_126 == ap_CS_fsm))) begin
ug1_p1_address0 = grp_computeResult_fu_467_ug2_p1_address0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st128_fsm_128 == ap_CS_fsm))) begin
ug1_p1_address0 = grp_computeResult_fu_467_ug1_p1_address0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st130_fsm_130 == ap_CS_fsm))) begin
ug1_p1_address0 = grp_computeResult_fu_467_ug0_p1_address0;
end else begin
ug1_p1_address0 = grp_computeUG_fu_555_ug_p1_address0;
end
end
/// ug1_p1_ce0 assign process. ///
always @ (ap_CS_fsm or grp_computeResult_fu_467_ug0_p1_ce0 or grp_computeResult_fu_467_ug1_p1_ce0 or grp_computeResult_fu_467_ug2_p1_ce0 or grp_computeUG_fu_555_ug_p1_ce0)
begin
if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm) | (ap_ST_st12_fsm_12 == ap_CS_fsm))) begin
ug1_p1_ce0 = grp_computeUG_fu_555_ug_p1_ce0;
end else if (((ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st126_fsm_126 == ap_CS_fsm))) begin
ug1_p1_ce0 = grp_computeResult_fu_467_ug2_p1_ce0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st128_fsm_128 == ap_CS_fsm))) begin
ug1_p1_ce0 = grp_computeResult_fu_467_ug1_p1_ce0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st130_fsm_130 == ap_CS_fsm))) begin
ug1_p1_ce0 = grp_computeResult_fu_467_ug0_p1_ce0;
end else begin
ug1_p1_ce0 = ap_const_logic_0;
end
end
/// ug1_p1_we0 assign process. ///
always @ (ap_CS_fsm or grp_computeUG_fu_555_ug_p1_we0)
begin
if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm) | (ap_ST_st12_fsm_12 == ap_CS_fsm))) begin
ug1_p1_we0 = grp_computeUG_fu_555_ug_p1_we0;
end else begin
ug1_p1_we0 = ap_const_logic_0;
end
end
/// ug1_p2_address0 assign process. ///
always @ (ap_CS_fsm or grp_computeResult_fu_467_ug0_p2_address0 or grp_computeResult_fu_467_ug1_p2_address0 or grp_computeResult_fu_467_ug2_p2_address0 or grp_computeUG_fu_555_ug_p2_address0)
begin
if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm) | (ap_ST_st12_fsm_12 == ap_CS_fsm))) begin
ug1_p2_address0 = grp_computeUG_fu_555_ug_p2_address0;
end else if (((ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st126_fsm_126 == ap_CS_fsm))) begin
ug1_p2_address0 = grp_computeResult_fu_467_ug2_p2_address0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st128_fsm_128 == ap_CS_fsm))) begin
ug1_p2_address0 = grp_computeResult_fu_467_ug1_p2_address0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st130_fsm_130 == ap_CS_fsm))) begin
ug1_p2_address0 = grp_computeResult_fu_467_ug0_p2_address0;
end else begin
ug1_p2_address0 = grp_computeUG_fu_555_ug_p2_address0;
end
end
/// ug1_p2_ce0 assign process. ///
always @ (ap_CS_fsm or grp_computeResult_fu_467_ug0_p2_ce0 or grp_computeResult_fu_467_ug1_p2_ce0 or grp_computeResult_fu_467_ug2_p2_ce0 or grp_computeUG_fu_555_ug_p2_ce0)
begin
if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm) | (ap_ST_st12_fsm_12 == ap_CS_fsm))) begin
ug1_p2_ce0 = grp_computeUG_fu_555_ug_p2_ce0;
end else if (((ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st126_fsm_126 == ap_CS_fsm))) begin
ug1_p2_ce0 = grp_computeResult_fu_467_ug2_p2_ce0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st128_fsm_128 == ap_CS_fsm))) begin
ug1_p2_ce0 = grp_computeResult_fu_467_ug1_p2_ce0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st130_fsm_130 == ap_CS_fsm))) begin
ug1_p2_ce0 = grp_computeResult_fu_467_ug0_p2_ce0;
end else begin
ug1_p2_ce0 = ap_const_logic_0;
end
end
/// ug1_p2_we0 assign process. ///
always @ (ap_CS_fsm or grp_computeUG_fu_555_ug_p2_we0)
begin
if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm) | (ap_ST_st12_fsm_12 == ap_CS_fsm))) begin
ug1_p2_we0 = grp_computeUG_fu_555_ug_p2_we0;
end else begin
ug1_p2_we0 = ap_const_logic_0;
end
end
/// ug1_p3_address0 assign process. ///
always @ (ap_CS_fsm or grp_computeResult_fu_467_ug0_p3_address0 or grp_computeResult_fu_467_ug1_p3_address0 or grp_computeResult_fu_467_ug2_p3_address0 or grp_computeUG_fu_555_ug_p3_address0)
begin
if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm) | (ap_ST_st12_fsm_12 == ap_CS_fsm))) begin
ug1_p3_address0 = grp_computeUG_fu_555_ug_p3_address0;
end else if (((ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st126_fsm_126 == ap_CS_fsm))) begin
ug1_p3_address0 = grp_computeResult_fu_467_ug2_p3_address0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st128_fsm_128 == ap_CS_fsm))) begin
ug1_p3_address0 = grp_computeResult_fu_467_ug1_p3_address0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st130_fsm_130 == ap_CS_fsm))) begin
ug1_p3_address0 = grp_computeResult_fu_467_ug0_p3_address0;
end else begin
ug1_p3_address0 = grp_computeUG_fu_555_ug_p3_address0;
end
end
/// ug1_p3_ce0 assign process. ///
always @ (ap_CS_fsm or grp_computeResult_fu_467_ug0_p3_ce0 or grp_computeResult_fu_467_ug1_p3_ce0 or grp_computeResult_fu_467_ug2_p3_ce0 or grp_computeUG_fu_555_ug_p3_ce0)
begin
if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm) | (ap_ST_st12_fsm_12 == ap_CS_fsm))) begin
ug1_p3_ce0 = grp_computeUG_fu_555_ug_p3_ce0;
end else if (((ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st126_fsm_126 == ap_CS_fsm))) begin
ug1_p3_ce0 = grp_computeResult_fu_467_ug2_p3_ce0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st128_fsm_128 == ap_CS_fsm))) begin
ug1_p3_ce0 = grp_computeResult_fu_467_ug1_p3_ce0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st130_fsm_130 == ap_CS_fsm))) begin
ug1_p3_ce0 = grp_computeResult_fu_467_ug0_p3_ce0;
end else begin
ug1_p3_ce0 = ap_const_logic_0;
end
end
/// ug1_p3_ce1 assign process. ///
always @ (ap_CS_fsm or grp_computeResult_fu_467_ug1_p3_ce1)
begin
if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st128_fsm_128 == ap_CS_fsm))) begin
ug1_p3_ce1 = grp_computeResult_fu_467_ug1_p3_ce1;
end else begin
ug1_p3_ce1 = ap_const_logic_0;
end
end
/// ug1_p3_we0 assign process. ///
always @ (ap_CS_fsm or grp_computeUG_fu_555_ug_p3_we0)
begin
if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm) | (ap_ST_st12_fsm_12 == ap_CS_fsm))) begin
ug1_p3_we0 = grp_computeUG_fu_555_ug_p3_we0;
end else begin
ug1_p3_we0 = ap_const_logic_0;
end
end
/// ug2_p0_address0 assign process. ///
always @ (ap_CS_fsm or grp_computeResult_fu_467_ug0_p0_address0 or grp_computeResult_fu_467_ug1_p0_address0 or grp_computeResult_fu_467_ug2_p0_address0 or grp_computeUG_fu_555_ug_p0_address0)
begin
if (((ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st126_fsm_126 == ap_CS_fsm) | (ap_ST_st14_fsm_14 == ap_CS_fsm))) begin
ug2_p0_address0 = grp_computeUG_fu_555_ug_p0_address0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st128_fsm_128 == ap_CS_fsm))) begin
ug2_p0_address0 = grp_computeResult_fu_467_ug2_p0_address0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st130_fsm_130 == ap_CS_fsm))) begin
ug2_p0_address0 = grp_computeResult_fu_467_ug1_p0_address0;
end else if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm))) begin
ug2_p0_address0 = grp_computeResult_fu_467_ug0_p0_address0;
end else begin
ug2_p0_address0 = grp_computeUG_fu_555_ug_p0_address0;
end
end
/// ug2_p0_ce0 assign process. ///
always @ (ap_CS_fsm or grp_computeResult_fu_467_ug0_p0_ce0 or grp_computeResult_fu_467_ug1_p0_ce0 or grp_computeResult_fu_467_ug2_p0_ce0 or grp_computeUG_fu_555_ug_p0_ce0)
begin
if (((ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st126_fsm_126 == ap_CS_fsm) | (ap_ST_st14_fsm_14 == ap_CS_fsm))) begin
ug2_p0_ce0 = grp_computeUG_fu_555_ug_p0_ce0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st128_fsm_128 == ap_CS_fsm))) begin
ug2_p0_ce0 = grp_computeResult_fu_467_ug2_p0_ce0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st130_fsm_130 == ap_CS_fsm))) begin
ug2_p0_ce0 = grp_computeResult_fu_467_ug1_p0_ce0;
end else if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm))) begin
ug2_p0_ce0 = grp_computeResult_fu_467_ug0_p0_ce0;
end else begin
ug2_p0_ce0 = ap_const_logic_0;
end
end
/// ug2_p0_ce1 assign process. ///
always @ (ap_CS_fsm or grp_computeResult_fu_467_ug1_p0_ce1)
begin
if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st130_fsm_130 == ap_CS_fsm))) begin
ug2_p0_ce1 = grp_computeResult_fu_467_ug1_p0_ce1;
end else begin
ug2_p0_ce1 = ap_const_logic_0;
end
end
/// ug2_p0_we0 assign process. ///
always @ (ap_CS_fsm or grp_computeUG_fu_555_ug_p0_we0)
begin
if (((ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st126_fsm_126 == ap_CS_fsm) | (ap_ST_st14_fsm_14 == ap_CS_fsm))) begin
ug2_p0_we0 = grp_computeUG_fu_555_ug_p0_we0;
end else begin
ug2_p0_we0 = ap_const_logic_0;
end
end
/// ug2_p1_address0 assign process. ///
always @ (ap_CS_fsm or grp_computeResult_fu_467_ug0_p1_address0 or grp_computeResult_fu_467_ug1_p1_address0 or grp_computeResult_fu_467_ug2_p1_address0 or grp_computeUG_fu_555_ug_p1_address0)
begin
if (((ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st126_fsm_126 == ap_CS_fsm) | (ap_ST_st14_fsm_14 == ap_CS_fsm))) begin
ug2_p1_address0 = grp_computeUG_fu_555_ug_p1_address0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st128_fsm_128 == ap_CS_fsm))) begin
ug2_p1_address0 = grp_computeResult_fu_467_ug2_p1_address0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st130_fsm_130 == ap_CS_fsm))) begin
ug2_p1_address0 = grp_computeResult_fu_467_ug1_p1_address0;
end else if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm))) begin
ug2_p1_address0 = grp_computeResult_fu_467_ug0_p1_address0;
end else begin
ug2_p1_address0 = grp_computeUG_fu_555_ug_p1_address0;
end
end
/// ug2_p1_ce0 assign process. ///
always @ (ap_CS_fsm or grp_computeResult_fu_467_ug0_p1_ce0 or grp_computeResult_fu_467_ug1_p1_ce0 or grp_computeResult_fu_467_ug2_p1_ce0 or grp_computeUG_fu_555_ug_p1_ce0)
begin
if (((ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st126_fsm_126 == ap_CS_fsm) | (ap_ST_st14_fsm_14 == ap_CS_fsm))) begin
ug2_p1_ce0 = grp_computeUG_fu_555_ug_p1_ce0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st128_fsm_128 == ap_CS_fsm))) begin
ug2_p1_ce0 = grp_computeResult_fu_467_ug2_p1_ce0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st130_fsm_130 == ap_CS_fsm))) begin
ug2_p1_ce0 = grp_computeResult_fu_467_ug1_p1_ce0;
end else if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm))) begin
ug2_p1_ce0 = grp_computeResult_fu_467_ug0_p1_ce0;
end else begin
ug2_p1_ce0 = ap_const_logic_0;
end
end
/// ug2_p1_we0 assign process. ///
always @ (ap_CS_fsm or grp_computeUG_fu_555_ug_p1_we0)
begin
if (((ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st126_fsm_126 == ap_CS_fsm) | (ap_ST_st14_fsm_14 == ap_CS_fsm))) begin
ug2_p1_we0 = grp_computeUG_fu_555_ug_p1_we0;
end else begin
ug2_p1_we0 = ap_const_logic_0;
end
end
/// ug2_p2_address0 assign process. ///
always @ (ap_CS_fsm or grp_computeResult_fu_467_ug0_p2_address0 or grp_computeResult_fu_467_ug1_p2_address0 or grp_computeResult_fu_467_ug2_p2_address0 or grp_computeUG_fu_555_ug_p2_address0)
begin
if (((ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st126_fsm_126 == ap_CS_fsm) | (ap_ST_st14_fsm_14 == ap_CS_fsm))) begin
ug2_p2_address0 = grp_computeUG_fu_555_ug_p2_address0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st128_fsm_128 == ap_CS_fsm))) begin
ug2_p2_address0 = grp_computeResult_fu_467_ug2_p2_address0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st130_fsm_130 == ap_CS_fsm))) begin
ug2_p2_address0 = grp_computeResult_fu_467_ug1_p2_address0;
end else if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm))) begin
ug2_p2_address0 = grp_computeResult_fu_467_ug0_p2_address0;
end else begin
ug2_p2_address0 = grp_computeUG_fu_555_ug_p2_address0;
end
end
/// ug2_p2_ce0 assign process. ///
always @ (ap_CS_fsm or grp_computeResult_fu_467_ug0_p2_ce0 or grp_computeResult_fu_467_ug1_p2_ce0 or grp_computeResult_fu_467_ug2_p2_ce0 or grp_computeUG_fu_555_ug_p2_ce0)
begin
if (((ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st126_fsm_126 == ap_CS_fsm) | (ap_ST_st14_fsm_14 == ap_CS_fsm))) begin
ug2_p2_ce0 = grp_computeUG_fu_555_ug_p2_ce0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st128_fsm_128 == ap_CS_fsm))) begin
ug2_p2_ce0 = grp_computeResult_fu_467_ug2_p2_ce0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st130_fsm_130 == ap_CS_fsm))) begin
ug2_p2_ce0 = grp_computeResult_fu_467_ug1_p2_ce0;
end else if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm))) begin
ug2_p2_ce0 = grp_computeResult_fu_467_ug0_p2_ce0;
end else begin
ug2_p2_ce0 = ap_const_logic_0;
end
end
/// ug2_p2_we0 assign process. ///
always @ (ap_CS_fsm or grp_computeUG_fu_555_ug_p2_we0)
begin
if (((ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st126_fsm_126 == ap_CS_fsm) | (ap_ST_st14_fsm_14 == ap_CS_fsm))) begin
ug2_p2_we0 = grp_computeUG_fu_555_ug_p2_we0;
end else begin
ug2_p2_we0 = ap_const_logic_0;
end
end
/// ug2_p3_address0 assign process. ///
always @ (ap_CS_fsm or grp_computeResult_fu_467_ug0_p3_address0 or grp_computeResult_fu_467_ug1_p3_address0 or grp_computeResult_fu_467_ug2_p3_address0 or grp_computeUG_fu_555_ug_p3_address0)
begin
if (((ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st126_fsm_126 == ap_CS_fsm) | (ap_ST_st14_fsm_14 == ap_CS_fsm))) begin
ug2_p3_address0 = grp_computeUG_fu_555_ug_p3_address0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st128_fsm_128 == ap_CS_fsm))) begin
ug2_p3_address0 = grp_computeResult_fu_467_ug2_p3_address0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st130_fsm_130 == ap_CS_fsm))) begin
ug2_p3_address0 = grp_computeResult_fu_467_ug1_p3_address0;
end else if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm))) begin
ug2_p3_address0 = grp_computeResult_fu_467_ug0_p3_address0;
end else begin
ug2_p3_address0 = grp_computeUG_fu_555_ug_p3_address0;
end
end
/// ug2_p3_ce0 assign process. ///
always @ (ap_CS_fsm or grp_computeResult_fu_467_ug0_p3_ce0 or grp_computeResult_fu_467_ug1_p3_ce0 or grp_computeResult_fu_467_ug2_p3_ce0 or grp_computeUG_fu_555_ug_p3_ce0)
begin
if (((ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st126_fsm_126 == ap_CS_fsm) | (ap_ST_st14_fsm_14 == ap_CS_fsm))) begin
ug2_p3_ce0 = grp_computeUG_fu_555_ug_p3_ce0;
end else if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st128_fsm_128 == ap_CS_fsm))) begin
ug2_p3_ce0 = grp_computeResult_fu_467_ug2_p3_ce0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st130_fsm_130 == ap_CS_fsm))) begin
ug2_p3_ce0 = grp_computeResult_fu_467_ug1_p3_ce0;
end else if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm))) begin
ug2_p3_ce0 = grp_computeResult_fu_467_ug0_p3_ce0;
end else begin
ug2_p3_ce0 = ap_const_logic_0;
end
end
/// ug2_p3_ce1 assign process. ///
always @ (ap_CS_fsm or grp_computeResult_fu_467_ug1_p3_ce1)
begin
if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st130_fsm_130 == ap_CS_fsm))) begin
ug2_p3_ce1 = grp_computeResult_fu_467_ug1_p3_ce1;
end else begin
ug2_p3_ce1 = ap_const_logic_0;
end
end
/// ug2_p3_we0 assign process. ///
always @ (ap_CS_fsm or grp_computeUG_fu_555_ug_p3_we0)
begin
if (((ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st126_fsm_126 == ap_CS_fsm) | (ap_ST_st14_fsm_14 == ap_CS_fsm))) begin
ug2_p3_we0 = grp_computeUG_fu_555_ug_p3_we0;
end else begin
ug2_p3_we0 = ap_const_logic_0;
end
end
/// ug3_p0_address0 assign process. ///
always @ (ap_CS_fsm or grp_computeResult_fu_467_ug0_p0_address0 or grp_computeResult_fu_467_ug1_p0_address0 or grp_computeResult_fu_467_ug2_p0_address0 or grp_computeUG_fu_555_ug_p0_address0)
begin
if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st128_fsm_128 == ap_CS_fsm))) begin
ug3_p0_address0 = grp_computeUG_fu_555_ug_p0_address0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st130_fsm_130 == ap_CS_fsm))) begin
ug3_p0_address0 = grp_computeResult_fu_467_ug2_p0_address0;
end else if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm))) begin
ug3_p0_address0 = grp_computeResult_fu_467_ug1_p0_address0;
end else if (((ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st126_fsm_126 == ap_CS_fsm))) begin
ug3_p0_address0 = grp_computeResult_fu_467_ug0_p0_address0;
end else begin
ug3_p0_address0 = grp_computeUG_fu_555_ug_p0_address0;
end
end
/// ug3_p0_ce0 assign process. ///
always @ (ap_CS_fsm or grp_computeResult_fu_467_ug0_p0_ce0 or grp_computeResult_fu_467_ug1_p0_ce0 or grp_computeResult_fu_467_ug2_p0_ce0 or grp_computeUG_fu_555_ug_p0_ce0)
begin
if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st128_fsm_128 == ap_CS_fsm))) begin
ug3_p0_ce0 = grp_computeUG_fu_555_ug_p0_ce0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st130_fsm_130 == ap_CS_fsm))) begin
ug3_p0_ce0 = grp_computeResult_fu_467_ug2_p0_ce0;
end else if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm))) begin
ug3_p0_ce0 = grp_computeResult_fu_467_ug1_p0_ce0;
end else if (((ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st126_fsm_126 == ap_CS_fsm))) begin
ug3_p0_ce0 = grp_computeResult_fu_467_ug0_p0_ce0;
end else begin
ug3_p0_ce0 = ap_const_logic_0;
end
end
/// ug3_p0_ce1 assign process. ///
always @ (ap_CS_fsm or grp_computeResult_fu_467_ug1_p0_ce1)
begin
if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm))) begin
ug3_p0_ce1 = grp_computeResult_fu_467_ug1_p0_ce1;
end else begin
ug3_p0_ce1 = ap_const_logic_0;
end
end
/// ug3_p0_we0 assign process. ///
always @ (ap_CS_fsm or grp_computeUG_fu_555_ug_p0_we0)
begin
if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st128_fsm_128 == ap_CS_fsm))) begin
ug3_p0_we0 = grp_computeUG_fu_555_ug_p0_we0;
end else begin
ug3_p0_we0 = ap_const_logic_0;
end
end
/// ug3_p1_address0 assign process. ///
always @ (ap_CS_fsm or grp_computeResult_fu_467_ug0_p1_address0 or grp_computeResult_fu_467_ug1_p1_address0 or grp_computeResult_fu_467_ug2_p1_address0 or grp_computeUG_fu_555_ug_p1_address0)
begin
if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st128_fsm_128 == ap_CS_fsm))) begin
ug3_p1_address0 = grp_computeUG_fu_555_ug_p1_address0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st130_fsm_130 == ap_CS_fsm))) begin
ug3_p1_address0 = grp_computeResult_fu_467_ug2_p1_address0;
end else if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm))) begin
ug3_p1_address0 = grp_computeResult_fu_467_ug1_p1_address0;
end else if (((ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st126_fsm_126 == ap_CS_fsm))) begin
ug3_p1_address0 = grp_computeResult_fu_467_ug0_p1_address0;
end else begin
ug3_p1_address0 = grp_computeUG_fu_555_ug_p1_address0;
end
end
/// ug3_p1_ce0 assign process. ///
always @ (ap_CS_fsm or grp_computeResult_fu_467_ug0_p1_ce0 or grp_computeResult_fu_467_ug1_p1_ce0 or grp_computeResult_fu_467_ug2_p1_ce0 or grp_computeUG_fu_555_ug_p1_ce0)
begin
if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st128_fsm_128 == ap_CS_fsm))) begin
ug3_p1_ce0 = grp_computeUG_fu_555_ug_p1_ce0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st130_fsm_130 == ap_CS_fsm))) begin
ug3_p1_ce0 = grp_computeResult_fu_467_ug2_p1_ce0;
end else if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm))) begin
ug3_p1_ce0 = grp_computeResult_fu_467_ug1_p1_ce0;
end else if (((ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st126_fsm_126 == ap_CS_fsm))) begin
ug3_p1_ce0 = grp_computeResult_fu_467_ug0_p1_ce0;
end else begin
ug3_p1_ce0 = ap_const_logic_0;
end
end
/// ug3_p1_we0 assign process. ///
always @ (ap_CS_fsm or grp_computeUG_fu_555_ug_p1_we0)
begin
if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st128_fsm_128 == ap_CS_fsm))) begin
ug3_p1_we0 = grp_computeUG_fu_555_ug_p1_we0;
end else begin
ug3_p1_we0 = ap_const_logic_0;
end
end
/// ug3_p2_address0 assign process. ///
always @ (ap_CS_fsm or grp_computeResult_fu_467_ug0_p2_address0 or grp_computeResult_fu_467_ug1_p2_address0 or grp_computeResult_fu_467_ug2_p2_address0 or grp_computeUG_fu_555_ug_p2_address0)
begin
if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st128_fsm_128 == ap_CS_fsm))) begin
ug3_p2_address0 = grp_computeUG_fu_555_ug_p2_address0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st130_fsm_130 == ap_CS_fsm))) begin
ug3_p2_address0 = grp_computeResult_fu_467_ug2_p2_address0;
end else if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm))) begin
ug3_p2_address0 = grp_computeResult_fu_467_ug1_p2_address0;
end else if (((ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st126_fsm_126 == ap_CS_fsm))) begin
ug3_p2_address0 = grp_computeResult_fu_467_ug0_p2_address0;
end else begin
ug3_p2_address0 = grp_computeUG_fu_555_ug_p2_address0;
end
end
/// ug3_p2_ce0 assign process. ///
always @ (ap_CS_fsm or grp_computeResult_fu_467_ug0_p2_ce0 or grp_computeResult_fu_467_ug1_p2_ce0 or grp_computeResult_fu_467_ug2_p2_ce0 or grp_computeUG_fu_555_ug_p2_ce0)
begin
if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st128_fsm_128 == ap_CS_fsm))) begin
ug3_p2_ce0 = grp_computeUG_fu_555_ug_p2_ce0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st130_fsm_130 == ap_CS_fsm))) begin
ug3_p2_ce0 = grp_computeResult_fu_467_ug2_p2_ce0;
end else if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm))) begin
ug3_p2_ce0 = grp_computeResult_fu_467_ug1_p2_ce0;
end else if (((ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st126_fsm_126 == ap_CS_fsm))) begin
ug3_p2_ce0 = grp_computeResult_fu_467_ug0_p2_ce0;
end else begin
ug3_p2_ce0 = ap_const_logic_0;
end
end
/// ug3_p2_we0 assign process. ///
always @ (ap_CS_fsm or grp_computeUG_fu_555_ug_p2_we0)
begin
if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st128_fsm_128 == ap_CS_fsm))) begin
ug3_p2_we0 = grp_computeUG_fu_555_ug_p2_we0;
end else begin
ug3_p2_we0 = ap_const_logic_0;
end
end
/// ug3_p3_address0 assign process. ///
always @ (ap_CS_fsm or grp_computeResult_fu_467_ug0_p3_address0 or grp_computeResult_fu_467_ug1_p3_address0 or grp_computeResult_fu_467_ug2_p3_address0 or grp_computeUG_fu_555_ug_p3_address0)
begin
if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st128_fsm_128 == ap_CS_fsm))) begin
ug3_p3_address0 = grp_computeUG_fu_555_ug_p3_address0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st130_fsm_130 == ap_CS_fsm))) begin
ug3_p3_address0 = grp_computeResult_fu_467_ug2_p3_address0;
end else if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm))) begin
ug3_p3_address0 = grp_computeResult_fu_467_ug1_p3_address0;
end else if (((ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st126_fsm_126 == ap_CS_fsm))) begin
ug3_p3_address0 = grp_computeResult_fu_467_ug0_p3_address0;
end else begin
ug3_p3_address0 = grp_computeUG_fu_555_ug_p3_address0;
end
end
/// ug3_p3_ce0 assign process. ///
always @ (ap_CS_fsm or grp_computeResult_fu_467_ug0_p3_ce0 or grp_computeResult_fu_467_ug1_p3_ce0 or grp_computeResult_fu_467_ug2_p3_ce0 or grp_computeUG_fu_555_ug_p3_ce0)
begin
if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st128_fsm_128 == ap_CS_fsm))) begin
ug3_p3_ce0 = grp_computeUG_fu_555_ug_p3_ce0;
end else if (((ap_ST_st18_fsm_18 == ap_CS_fsm) | (ap_ST_st26_fsm_26 == ap_CS_fsm) | (ap_ST_st34_fsm_34 == ap_CS_fsm) | (ap_ST_st42_fsm_42 == ap_CS_fsm) | (ap_ST_st50_fsm_50 == ap_CS_fsm) | (ap_ST_st58_fsm_58 == ap_CS_fsm) | (ap_ST_st66_fsm_66 == ap_CS_fsm) | (ap_ST_st74_fsm_74 == ap_CS_fsm) | (ap_ST_st82_fsm_82 == ap_CS_fsm) | (ap_ST_st90_fsm_90 == ap_CS_fsm) | (ap_ST_st98_fsm_98 == ap_CS_fsm) | (ap_ST_st106_fsm_106 == ap_CS_fsm) | (ap_ST_st114_fsm_114 == ap_CS_fsm) | (ap_ST_st122_fsm_122 == ap_CS_fsm) | (ap_ST_st130_fsm_130 == ap_CS_fsm))) begin
ug3_p3_ce0 = grp_computeResult_fu_467_ug2_p3_ce0;
end else if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm))) begin
ug3_p3_ce0 = grp_computeResult_fu_467_ug1_p3_ce0;
end else if (((ap_ST_st22_fsm_22 == ap_CS_fsm) | (ap_ST_st30_fsm_30 == ap_CS_fsm) | (ap_ST_st38_fsm_38 == ap_CS_fsm) | (ap_ST_st46_fsm_46 == ap_CS_fsm) | (ap_ST_st54_fsm_54 == ap_CS_fsm) | (ap_ST_st62_fsm_62 == ap_CS_fsm) | (ap_ST_st70_fsm_70 == ap_CS_fsm) | (ap_ST_st78_fsm_78 == ap_CS_fsm) | (ap_ST_st86_fsm_86 == ap_CS_fsm) | (ap_ST_st94_fsm_94 == ap_CS_fsm) | (ap_ST_st102_fsm_102 == ap_CS_fsm) | (ap_ST_st110_fsm_110 == ap_CS_fsm) | (ap_ST_st118_fsm_118 == ap_CS_fsm) | (ap_ST_st126_fsm_126 == ap_CS_fsm))) begin
ug3_p3_ce0 = grp_computeResult_fu_467_ug0_p3_ce0;
end else begin
ug3_p3_ce0 = ap_const_logic_0;
end
end
/// ug3_p3_ce1 assign process. ///
always @ (ap_CS_fsm or grp_computeResult_fu_467_ug1_p3_ce1)
begin
if (((ap_ST_st20_fsm_20 == ap_CS_fsm) | (ap_ST_st28_fsm_28 == ap_CS_fsm) | (ap_ST_st36_fsm_36 == ap_CS_fsm) | (ap_ST_st44_fsm_44 == ap_CS_fsm) | (ap_ST_st52_fsm_52 == ap_CS_fsm) | (ap_ST_st60_fsm_60 == ap_CS_fsm) | (ap_ST_st68_fsm_68 == ap_CS_fsm) | (ap_ST_st76_fsm_76 == ap_CS_fsm) | (ap_ST_st84_fsm_84 == ap_CS_fsm) | (ap_ST_st92_fsm_92 == ap_CS_fsm) | (ap_ST_st100_fsm_100 == ap_CS_fsm) | (ap_ST_st108_fsm_108 == ap_CS_fsm) | (ap_ST_st116_fsm_116 == ap_CS_fsm) | (ap_ST_st124_fsm_124 == ap_CS_fsm))) begin
ug3_p3_ce1 = grp_computeResult_fu_467_ug1_p3_ce1;
end else begin
ug3_p3_ce1 = ap_const_logic_0;
end
end
/// ug3_p3_we0 assign process. ///
always @ (ap_CS_fsm or grp_computeUG_fu_555_ug_p3_we0)
begin
if (((ap_ST_st16_fsm_16 == ap_CS_fsm) | (ap_ST_st24_fsm_24 == ap_CS_fsm) | (ap_ST_st32_fsm_32 == ap_CS_fsm) | (ap_ST_st40_fsm_40 == ap_CS_fsm) | (ap_ST_st48_fsm_48 == ap_CS_fsm) | (ap_ST_st56_fsm_56 == ap_CS_fsm) | (ap_ST_st64_fsm_64 == ap_CS_fsm) | (ap_ST_st72_fsm_72 == ap_CS_fsm) | (ap_ST_st80_fsm_80 == ap_CS_fsm) | (ap_ST_st88_fsm_88 == ap_CS_fsm) | (ap_ST_st96_fsm_96 == ap_CS_fsm) | (ap_ST_st104_fsm_104 == ap_CS_fsm) | (ap_ST_st112_fsm_112 == ap_CS_fsm) | (ap_ST_st120_fsm_120 == ap_CS_fsm) | (ap_ST_st128_fsm_128 == ap_CS_fsm))) begin
ug3_p3_we0 = grp_computeUG_fu_555_ug_p3_we0;
end else begin
ug3_p3_we0 = ap_const_logic_0;
end
end
assign ap_return = Convergence_assign_58_reg_1185;
assign f0_p0_d0 = grp_fFetch_array_fu_599_data_p0_d0;
assign f0_p1_d0 = grp_fFetch_array_fu_599_data_p1_d0;
assign f0_p2_d0 = grp_fFetch_array_fu_599_data_p2_d0;
assign f0_p3_d0 = grp_fFetch_array_fu_599_data_p3_d0;
assign f1_p0_d0 = grp_fFetch_array_fu_599_data_p0_d0;
assign f1_p1_d0 = grp_fFetch_array_fu_599_data_p1_d0;
assign f1_p2_d0 = grp_fFetch_array_fu_599_data_p2_d0;
assign f1_p3_d0 = grp_fFetch_array_fu_599_data_p3_d0;
assign fReadBus_address = grp_fFetch_array_fu_599_bus_r_address;
assign fReadBus_dataout = grp_fFetch_array_fu_599_bus_r_dataout;
assign fReadBus_req_din = grp_fFetch_array_fu_599_bus_r_req_din;
assign fReadBus_req_write = grp_fFetch_array_fu_599_bus_r_req_write;
assign fReadBus_rsp_read = grp_fFetch_array_fu_599_bus_r_rsp_read;
assign fReadBus_size = grp_fFetch_array_fu_599_bus_r_size;
assign g0_p0_address1 = grp_computeResult_fu_467_g1_p0_address1;
assign g0_p0_d0 = grp_computeGradient_fu_507_g_p0_d0;
assign g0_p1_d0 = grp_computeGradient_fu_507_g_p1_d0;
assign g0_p2_d0 = grp_computeGradient_fu_507_g_p2_d0;
assign g0_p3_address1 = grp_computeResult_fu_467_g1_p3_address1;
assign g0_p3_d0 = grp_computeGradient_fu_507_g_p3_d0;
assign g1_p0_address1 = grp_computeResult_fu_467_g1_p0_address1;
assign g1_p0_d0 = grp_computeGradient_fu_507_g_p0_d0;
assign g1_p1_d0 = grp_computeGradient_fu_507_g_p1_d0;
assign g1_p2_d0 = grp_computeGradient_fu_507_g_p2_d0;
assign g1_p3_address1 = grp_computeResult_fu_467_g1_p3_address1;
assign g1_p3_d0 = grp_computeGradient_fu_507_g_p3_d0;
assign g2_p0_address1 = grp_computeResult_fu_467_g1_p0_address1;
assign g2_p0_d0 = grp_computeGradient_fu_507_g_p0_d0;
assign g2_p1_d0 = grp_computeGradient_fu_507_g_p1_d0;
assign g2_p2_d0 = grp_computeGradient_fu_507_g_p2_d0;
assign g2_p3_address1 = grp_computeResult_fu_467_g1_p3_address1;
assign g2_p3_d0 = grp_computeGradient_fu_507_g_p3_d0;
assign g3_p0_address1 = grp_computeResult_fu_467_g1_p0_address1;
assign g3_p0_d0 = grp_computeGradient_fu_507_g_p0_d0;
assign g3_p1_d0 = grp_computeGradient_fu_507_g_p1_d0;
assign g3_p2_d0 = grp_computeGradient_fu_507_g_p2_d0;
assign g3_p3_address1 = grp_computeResult_fu_467_g1_p3_address1;
assign g3_p3_d0 = grp_computeGradient_fu_507_g_p3_d0;
assign g4_p0_address1 = grp_computeResult_fu_467_g1_p0_address1;
assign g4_p0_d0 = grp_computeGradient_fu_507_g_p0_d0;
assign g4_p1_d0 = grp_computeGradient_fu_507_g_p1_d0;
assign g4_p2_d0 = grp_computeGradient_fu_507_g_p2_d0;
assign g4_p3_address1 = grp_computeResult_fu_467_g1_p3_address1;
assign g4_p3_d0 = grp_computeGradient_fu_507_g_p3_d0;
assign grp_fFetch_array_fu_599_bus_r_datain = fReadBus_datain;
assign grp_fFetch_array_fu_599_bus_r_req_full_n = fReadBus_req_full_n;
assign grp_fFetch_array_fu_599_bus_r_rsp_dout = fReadBus_rsp_dout;
assign grp_fFetch_array_fu_599_bus_r_rsp_empty_n = fReadBus_rsp_empty_n;
assign grp_uFetch_array_fu_583_bus_r_datain = uReadBus_datain;
assign grp_uFetch_array_fu_583_bus_r_req_full_n = uReadBus_req_full_n;
assign grp_uFetch_array_fu_583_bus_r_rsp_dout = uReadBus_rsp_dout;
assign grp_uFetch_array_fu_583_bus_r_rsp_empty_n = uReadBus_rsp_empty_n;
assign grp_write_array_fu_571_bus_r_datain = writeBus_datain;
assign grp_write_array_fu_571_bus_r_req_full_n = writeBus_req_full_n;
assign grp_write_array_fu_571_bus_r_rsp_dout = writeBus_rsp_dout;
assign grp_write_array_fu_571_bus_r_rsp_empty_n = writeBus_rsp_empty_n;
assign r0_p0_d0 = grp_computeResult_fu_467_r_p0_d0;
assign r0_p1_d0 = grp_computeResult_fu_467_r_p1_d0;
assign r0_p2_d0 = grp_computeResult_fu_467_r_p2_d0;
assign r0_p3_d0 = grp_computeResult_fu_467_r_p3_d0;
assign r1_p0_d0 = grp_computeResult_fu_467_r_p0_d0;
assign r1_p1_d0 = grp_computeResult_fu_467_r_p1_d0;
assign r1_p2_d0 = grp_computeResult_fu_467_r_p2_d0;
assign r1_p3_d0 = grp_computeResult_fu_467_r_p3_d0;
assign sm0_p0_d0 = grp_computeDiffSqr_fu_531_sm_p0_d0;
assign sm0_p1_d0 = grp_computeDiffSqr_fu_531_sm_p1_d0;
assign sm0_p2_d0 = grp_computeDiffSqr_fu_531_sm_p2_d0;
assign sm0_p3_d0 = grp_computeDiffSqr_fu_531_sm_p3_d0;
assign sm1_p0_d0 = grp_computeDiffSqr_fu_531_sm_p0_d0;
assign sm1_p1_d0 = grp_computeDiffSqr_fu_531_sm_p1_d0;
assign sm1_p2_d0 = grp_computeDiffSqr_fu_531_sm_p2_d0;
assign sm1_p3_d0 = grp_computeDiffSqr_fu_531_sm_p3_d0;
assign sn0_p0_address1 = grp_computeGradient_fu_507_sn0_p0_address1;
assign sn0_p0_d0 = grp_computeDiffSqr_fu_531_sn_p0_d0;
assign sn0_p1_d0 = grp_computeDiffSqr_fu_531_sn_p1_d0;
assign sn0_p2_d0 = grp_computeDiffSqr_fu_531_sn_p2_d0;
assign sn0_p3_d0 = grp_computeDiffSqr_fu_531_sn_p3_d0;
assign sn1_p0_address1 = grp_computeGradient_fu_507_sn0_p0_address1;
assign sn1_p0_d0 = grp_computeDiffSqr_fu_531_sn_p0_d0;
assign sn1_p1_d0 = grp_computeDiffSqr_fu_531_sn_p1_d0;
assign sn1_p2_d0 = grp_computeDiffSqr_fu_531_sn_p2_d0;
assign sn1_p3_d0 = grp_computeDiffSqr_fu_531_sn_p3_d0;
assign sp0_p0_d0 = grp_computeDiffSqr_fu_531_sp_p0_d0;
assign sp0_p1_d0 = grp_computeDiffSqr_fu_531_sp_p1_d0;
assign sp0_p2_d0 = grp_computeDiffSqr_fu_531_sp_p2_d0;
assign sp0_p3_d0 = grp_computeDiffSqr_fu_531_sp_p3_d0;
assign sp1_p0_d0 = grp_computeDiffSqr_fu_531_sp_p0_d0;
assign sp1_p1_d0 = grp_computeDiffSqr_fu_531_sp_p1_d0;
assign sp1_p2_d0 = grp_computeDiffSqr_fu_531_sp_p2_d0;
assign sp1_p3_d0 = grp_computeDiffSqr_fu_531_sp_p3_d0;
assign sp2_p0_d0 = grp_computeDiffSqr_fu_531_sp_p0_d0;
assign sp2_p1_d0 = grp_computeDiffSqr_fu_531_sp_p1_d0;
assign sp2_p2_d0 = grp_computeDiffSqr_fu_531_sp_p2_d0;
assign sp2_p3_d0 = grp_computeDiffSqr_fu_531_sp_p3_d0;
assign tmp10_fu_665_p2 = (tmp9_fu_660_p2 & tmp8_reg_955);
assign tmp11_fu_670_p2 = (tmp10_fu_665_p2 & tmp7_reg_945);
assign tmp13_fu_680_p2 = (empty_17_reg_975 & grp_computeResult_fu_467_ap_return);
assign tmp16_fu_695_p2 = (empty_21_reg_995 & grp_computeResult_fu_467_ap_return);
assign tmp17_fu_700_p2 = (tmp16_fu_695_p2 & tmp15_reg_990);
assign tmp20_fu_715_p2 = (empty_25_reg_1015 & grp_computeResult_fu_467_ap_return);
assign tmp23_fu_730_p2 = (empty_29_reg_1035 & grp_computeResult_fu_467_ap_return);
assign tmp24_fu_735_p2 = (tmp23_fu_730_p2 & tmp22_reg_1030);
assign tmp25_fu_740_p2 = (tmp24_fu_735_p2 & tmp21_reg_1020);
assign tmp26_fu_745_p2 = (tmp25_fu_740_p2 & tmp18_reg_1000);
assign tmp28_fu_755_p2 = (empty_32_reg_1050 & grp_computeResult_fu_467_ap_return);
assign tmp31_fu_770_p2 = (empty_36_reg_1070 & grp_computeResult_fu_467_ap_return);
assign tmp32_fu_775_p2 = (tmp31_fu_770_p2 & tmp30_reg_1065);
assign tmp34_fu_785_p2 = (empty_39_reg_1085 & grp_computeResult_fu_467_ap_return);
assign tmp37_fu_800_p2 = (empty_43_reg_1105 & grp_computeResult_fu_467_ap_return);
assign tmp38_fu_805_p2 = (tmp37_fu_800_p2 & tmp36_reg_1100);
assign tmp39_fu_810_p2 = (tmp38_fu_805_p2 & tmp35_reg_1090);
assign tmp3_fu_630_p2 = (empty_7_reg_925 & grp_computeResult_fu_467_ap_return);
assign tmp41_fu_820_p2 = (empty_46_reg_1120 & grp_computeResult_fu_467_ap_return);
assign tmp44_fu_835_p2 = (empty_50_reg_1140 & grp_computeResult_fu_467_ap_return);
assign tmp45_fu_840_p2 = (tmp44_fu_835_p2 & tmp43_reg_1135);
assign tmp48_fu_855_p2 = (empty_54_reg_1160 & grp_computeResult_fu_467_ap_return);
assign tmp4_fu_635_p2 = (tmp3_fu_630_p2 & tmp2_reg_920);
assign tmp51_fu_870_p2 = (empty_58_reg_1180 & grp_computeResult_fu_467_ap_return);
assign tmp52_fu_875_p2 = (tmp51_fu_870_p2 & tmp50_reg_1175);
assign tmp53_fu_880_p2 = (tmp52_fu_875_p2 & tmp49_reg_1165);
assign tmp54_fu_885_p2 = (tmp53_fu_880_p2 & tmp46_reg_1145);
assign tmp55_fu_890_p2 = (tmp54_fu_885_p2 & tmp40_reg_1110);
assign tmp6_fu_645_p2 = (empty_10_reg_940 & grp_computeResult_fu_467_ap_return);
assign tmp9_fu_660_p2 = (empty_14_reg_960 & grp_computeResult_fu_467_ap_return);
assign tmp_fu_615_p2 = (empty_2_reg_900 & grp_computeResult_fu_467_ap_return);
assign u0_p0_d0 = grp_uFetch_array_fu_583_data_p0_d0;
assign u0_p1_d0 = grp_uFetch_array_fu_583_data_p1_d0;
assign u0_p2_d0 = grp_uFetch_array_fu_583_data_p2_d0;
assign u0_p3_address1 = grp_computeDiffSqr_fu_531_u0_p3_address1;
assign u0_p3_d0 = grp_uFetch_array_fu_583_data_p3_d0;
assign u1_p0_d0 = grp_uFetch_array_fu_583_data_p0_d0;
assign u1_p1_d0 = grp_uFetch_array_fu_583_data_p1_d0;
assign u1_p2_d0 = grp_uFetch_array_fu_583_data_p2_d0;
assign u1_p3_address1 = grp_computeDiffSqr_fu_531_u0_p3_address1;
assign u1_p3_d0 = grp_uFetch_array_fu_583_data_p3_d0;
assign u2_p0_d0 = grp_uFetch_array_fu_583_data_p0_d0;
assign u2_p1_d0 = grp_uFetch_array_fu_583_data_p1_d0;
assign u2_p2_d0 = grp_uFetch_array_fu_583_data_p2_d0;
assign u2_p3_address1 = grp_computeDiffSqr_fu_531_u0_p3_address1;
assign u2_p3_d0 = grp_uFetch_array_fu_583_data_p3_d0;
assign u3_p0_d0 = grp_uFetch_array_fu_583_data_p0_d0;
assign u3_p1_d0 = grp_uFetch_array_fu_583_data_p1_d0;
assign u3_p2_d0 = grp_uFetch_array_fu_583_data_p2_d0;
assign u3_p3_address1 = grp_computeDiffSqr_fu_531_u0_p3_address1;
assign u3_p3_d0 = grp_uFetch_array_fu_583_data_p3_d0;
assign u4_p0_d0 = grp_uFetch_array_fu_583_data_p0_d0;
assign u4_p1_d0 = grp_uFetch_array_fu_583_data_p1_d0;
assign u4_p2_d0 = grp_uFetch_array_fu_583_data_p2_d0;
assign u4_p3_address1 = grp_computeDiffSqr_fu_531_u0_p3_address1;
assign u4_p3_d0 = grp_uFetch_array_fu_583_data_p3_d0;
assign u5_p0_d0 = grp_uFetch_array_fu_583_data_p0_d0;
assign u5_p1_d0 = grp_uFetch_array_fu_583_data_p1_d0;
assign u5_p2_d0 = grp_uFetch_array_fu_583_data_p2_d0;
assign u5_p3_address1 = grp_computeDiffSqr_fu_531_u0_p3_address1;
assign u5_p3_d0 = grp_uFetch_array_fu_583_data_p3_d0;
assign u6_p0_d0 = grp_uFetch_array_fu_583_data_p0_d0;
assign u6_p1_d0 = grp_uFetch_array_fu_583_data_p1_d0;
assign u6_p2_d0 = grp_uFetch_array_fu_583_data_p2_d0;
assign u6_p3_address1 = grp_computeDiffSqr_fu_531_u0_p3_address1;
assign u6_p3_d0 = grp_uFetch_array_fu_583_data_p3_d0;
assign uReadBus_address = grp_uFetch_array_fu_583_bus_r_address;
assign uReadBus_dataout = grp_uFetch_array_fu_583_bus_r_dataout;
assign uReadBus_req_din = grp_uFetch_array_fu_583_bus_r_req_din;
assign uReadBus_req_write = grp_uFetch_array_fu_583_bus_r_req_write;
assign uReadBus_rsp_read = grp_uFetch_array_fu_583_bus_r_rsp_read;
assign uReadBus_size = grp_uFetch_array_fu_583_bus_r_size;
assign ug0_p0_address1 = grp_computeResult_fu_467_ug1_p0_address1;
assign ug0_p0_d0 = grp_computeUG_fu_555_ug_p0_d0;
assign ug0_p1_d0 = grp_computeUG_fu_555_ug_p1_d0;
assign ug0_p2_d0 = grp_computeUG_fu_555_ug_p2_d0;
assign ug0_p3_address1 = grp_computeResult_fu_467_ug1_p3_address1;
assign ug0_p3_d0 = grp_computeUG_fu_555_ug_p3_d0;
assign ug1_p0_address1 = grp_computeResult_fu_467_ug1_p0_address1;
assign ug1_p0_d0 = grp_computeUG_fu_555_ug_p0_d0;
assign ug1_p1_d0 = grp_computeUG_fu_555_ug_p1_d0;
assign ug1_p2_d0 = grp_computeUG_fu_555_ug_p2_d0;
assign ug1_p3_address1 = grp_computeResult_fu_467_ug1_p3_address1;
assign ug1_p3_d0 = grp_computeUG_fu_555_ug_p3_d0;
assign ug2_p0_address1 = grp_computeResult_fu_467_ug1_p0_address1;
assign ug2_p0_d0 = grp_computeUG_fu_555_ug_p0_d0;
assign ug2_p1_d0 = grp_computeUG_fu_555_ug_p1_d0;
assign ug2_p2_d0 = grp_computeUG_fu_555_ug_p2_d0;
assign ug2_p3_address1 = grp_computeResult_fu_467_ug1_p3_address1;
assign ug2_p3_d0 = grp_computeUG_fu_555_ug_p3_d0;
assign ug3_p0_address1 = grp_computeResult_fu_467_ug1_p0_address1;
assign ug3_p0_d0 = grp_computeUG_fu_555_ug_p0_d0;
assign ug3_p1_d0 = grp_computeUG_fu_555_ug_p1_d0;
assign ug3_p2_d0 = grp_computeUG_fu_555_ug_p2_d0;
assign ug3_p3_address1 = grp_computeResult_fu_467_ug1_p3_address1;
assign ug3_p3_d0 = grp_computeUG_fu_555_ug_p3_d0;
assign writeBus_address = grp_write_array_fu_571_bus_r_address;
assign writeBus_dataout = grp_write_array_fu_571_bus_r_dataout;
assign writeBus_req_din = grp_write_array_fu_571_bus_r_req_din;
assign writeBus_req_write = grp_write_array_fu_571_bus_r_req_write;
assign writeBus_rsp_read = grp_write_array_fu_571_bus_r_rsp_read;
assign writeBus_size = grp_write_array_fu_571_bus_r_size;
endmodule //denoise
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_f0_p0_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd1;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_f0_p0 (
address0,
ce0,
q0,
we0,
d0,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input clk;
reg[DataWidth-1:0] q0;
wire[1 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[1 * AddressWidth - 1:0] mem_ra;
wire[1 - 1:0] mem_ce;
denoise_f0_p0_core #(
.READ_PORT_COUNT( 1 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_ra = {address0};
assign mem_ce = {ce0};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_f0_p1_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd1;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_f0_p1 (
address0,
ce0,
q0,
we0,
d0,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input clk;
reg[DataWidth-1:0] q0;
wire[1 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[1 * AddressWidth - 1:0] mem_ra;
wire[1 - 1:0] mem_ce;
denoise_f0_p1_core #(
.READ_PORT_COUNT( 1 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_ra = {address0};
assign mem_ce = {ce0};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_f0_p2_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd1;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_f0_p2 (
address0,
ce0,
q0,
we0,
d0,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input clk;
reg[DataWidth-1:0] q0;
wire[1 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[1 * AddressWidth - 1:0] mem_ra;
wire[1 - 1:0] mem_ce;
denoise_f0_p2_core #(
.READ_PORT_COUNT( 1 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_ra = {address0};
assign mem_ce = {ce0};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_f0_p3_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd1;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_f0_p3 (
address0,
ce0,
q0,
we0,
d0,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input clk;
reg[DataWidth-1:0] q0;
wire[1 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[1 * AddressWidth - 1:0] mem_ra;
wire[1 - 1:0] mem_ce;
denoise_f0_p3_core #(
.READ_PORT_COUNT( 1 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_ra = {address0};
assign mem_ce = {ce0};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_f1_p0_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd1;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_f1_p0 (
address0,
ce0,
q0,
we0,
d0,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input clk;
reg[DataWidth-1:0] q0;
wire[1 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[1 * AddressWidth - 1:0] mem_ra;
wire[1 - 1:0] mem_ce;
denoise_f1_p0_core #(
.READ_PORT_COUNT( 1 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_ra = {address0};
assign mem_ce = {ce0};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_f1_p1_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd1;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_f1_p1 (
address0,
ce0,
q0,
we0,
d0,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input clk;
reg[DataWidth-1:0] q0;
wire[1 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[1 * AddressWidth - 1:0] mem_ra;
wire[1 - 1:0] mem_ce;
denoise_f1_p1_core #(
.READ_PORT_COUNT( 1 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_ra = {address0};
assign mem_ce = {ce0};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_f1_p2_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd1;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_f1_p2 (
address0,
ce0,
q0,
we0,
d0,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input clk;
reg[DataWidth-1:0] q0;
wire[1 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[1 * AddressWidth - 1:0] mem_ra;
wire[1 - 1:0] mem_ce;
denoise_f1_p2_core #(
.READ_PORT_COUNT( 1 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_ra = {address0};
assign mem_ce = {ce0};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_f1_p3_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd1;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_f1_p3 (
address0,
ce0,
q0,
we0,
d0,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input clk;
reg[DataWidth-1:0] q0;
wire[1 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[1 * AddressWidth - 1:0] mem_ra;
wire[1 - 1:0] mem_ce;
denoise_f1_p3_core #(
.READ_PORT_COUNT( 1 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_ra = {address0};
assign mem_ce = {ce0};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_g0_p0_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd2;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or rai_reg[1] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_g0_p0 (
address0,
ce0,
q0,
we0,
d0,
address1,
ce1,
q1,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input[AddressWidth-1:0] address1;
input ce1;
output[DataWidth-1:0] q1;
input clk;
reg[DataWidth-1:0] q0;
reg[DataWidth-1:0] q1;
wire[2 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[DataWidth - 1:0] mem_q1;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[2 * AddressWidth - 1:0] mem_ra;
wire[2 - 1:0] mem_ce;
denoise_g0_p0_core #(
.READ_PORT_COUNT( 2 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[2 * DataWidth - 1 : 1 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_q1 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q1) begin
q1 = mem_q1;
end
assign mem_ra = {address0, address1};
assign mem_ce = {ce0, ce1};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_g0_p1_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd1;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_g0_p1 (
address0,
ce0,
q0,
we0,
d0,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input clk;
reg[DataWidth-1:0] q0;
wire[1 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[1 * AddressWidth - 1:0] mem_ra;
wire[1 - 1:0] mem_ce;
denoise_g0_p1_core #(
.READ_PORT_COUNT( 1 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_ra = {address0};
assign mem_ce = {ce0};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_g0_p2_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd1;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_g0_p2 (
address0,
ce0,
q0,
we0,
d0,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input clk;
reg[DataWidth-1:0] q0;
wire[1 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[1 * AddressWidth - 1:0] mem_ra;
wire[1 - 1:0] mem_ce;
denoise_g0_p2_core #(
.READ_PORT_COUNT( 1 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_ra = {address0};
assign mem_ce = {ce0};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_g0_p3_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd2;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or rai_reg[1] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_g0_p3 (
address0,
ce0,
q0,
we0,
d0,
address1,
ce1,
q1,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input[AddressWidth-1:0] address1;
input ce1;
output[DataWidth-1:0] q1;
input clk;
reg[DataWidth-1:0] q0;
reg[DataWidth-1:0] q1;
wire[2 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[DataWidth - 1:0] mem_q1;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[2 * AddressWidth - 1:0] mem_ra;
wire[2 - 1:0] mem_ce;
denoise_g0_p3_core #(
.READ_PORT_COUNT( 2 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[2 * DataWidth - 1 : 1 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_q1 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q1) begin
q1 = mem_q1;
end
assign mem_ra = {address0, address1};
assign mem_ce = {ce0, ce1};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_g1_p0_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd2;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or rai_reg[1] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_g1_p0 (
address0,
ce0,
q0,
we0,
d0,
address1,
ce1,
q1,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input[AddressWidth-1:0] address1;
input ce1;
output[DataWidth-1:0] q1;
input clk;
reg[DataWidth-1:0] q0;
reg[DataWidth-1:0] q1;
wire[2 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[DataWidth - 1:0] mem_q1;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[2 * AddressWidth - 1:0] mem_ra;
wire[2 - 1:0] mem_ce;
denoise_g1_p0_core #(
.READ_PORT_COUNT( 2 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[2 * DataWidth - 1 : 1 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_q1 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q1) begin
q1 = mem_q1;
end
assign mem_ra = {address0, address1};
assign mem_ce = {ce0, ce1};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_g1_p1_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd1;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_g1_p1 (
address0,
ce0,
q0,
we0,
d0,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input clk;
reg[DataWidth-1:0] q0;
wire[1 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[1 * AddressWidth - 1:0] mem_ra;
wire[1 - 1:0] mem_ce;
denoise_g1_p1_core #(
.READ_PORT_COUNT( 1 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_ra = {address0};
assign mem_ce = {ce0};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_g1_p2_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd1;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_g1_p2 (
address0,
ce0,
q0,
we0,
d0,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input clk;
reg[DataWidth-1:0] q0;
wire[1 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[1 * AddressWidth - 1:0] mem_ra;
wire[1 - 1:0] mem_ce;
denoise_g1_p2_core #(
.READ_PORT_COUNT( 1 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_ra = {address0};
assign mem_ce = {ce0};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_g1_p3_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd2;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or rai_reg[1] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_g1_p3 (
address0,
ce0,
q0,
we0,
d0,
address1,
ce1,
q1,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input[AddressWidth-1:0] address1;
input ce1;
output[DataWidth-1:0] q1;
input clk;
reg[DataWidth-1:0] q0;
reg[DataWidth-1:0] q1;
wire[2 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[DataWidth - 1:0] mem_q1;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[2 * AddressWidth - 1:0] mem_ra;
wire[2 - 1:0] mem_ce;
denoise_g1_p3_core #(
.READ_PORT_COUNT( 2 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[2 * DataWidth - 1 : 1 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_q1 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q1) begin
q1 = mem_q1;
end
assign mem_ra = {address0, address1};
assign mem_ce = {ce0, ce1};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_g2_p0_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd2;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or rai_reg[1] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_g2_p0 (
address0,
ce0,
q0,
we0,
d0,
address1,
ce1,
q1,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input[AddressWidth-1:0] address1;
input ce1;
output[DataWidth-1:0] q1;
input clk;
reg[DataWidth-1:0] q0;
reg[DataWidth-1:0] q1;
wire[2 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[DataWidth - 1:0] mem_q1;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[2 * AddressWidth - 1:0] mem_ra;
wire[2 - 1:0] mem_ce;
denoise_g2_p0_core #(
.READ_PORT_COUNT( 2 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[2 * DataWidth - 1 : 1 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_q1 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q1) begin
q1 = mem_q1;
end
assign mem_ra = {address0, address1};
assign mem_ce = {ce0, ce1};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_g2_p1_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd1;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_g2_p1 (
address0,
ce0,
q0,
we0,
d0,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input clk;
reg[DataWidth-1:0] q0;
wire[1 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[1 * AddressWidth - 1:0] mem_ra;
wire[1 - 1:0] mem_ce;
denoise_g2_p1_core #(
.READ_PORT_COUNT( 1 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_ra = {address0};
assign mem_ce = {ce0};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_g2_p2_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd1;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_g2_p2 (
address0,
ce0,
q0,
we0,
d0,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input clk;
reg[DataWidth-1:0] q0;
wire[1 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[1 * AddressWidth - 1:0] mem_ra;
wire[1 - 1:0] mem_ce;
denoise_g2_p2_core #(
.READ_PORT_COUNT( 1 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_ra = {address0};
assign mem_ce = {ce0};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_g2_p3_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd2;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or rai_reg[1] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_g2_p3 (
address0,
ce0,
q0,
we0,
d0,
address1,
ce1,
q1,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input[AddressWidth-1:0] address1;
input ce1;
output[DataWidth-1:0] q1;
input clk;
reg[DataWidth-1:0] q0;
reg[DataWidth-1:0] q1;
wire[2 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[DataWidth - 1:0] mem_q1;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[2 * AddressWidth - 1:0] mem_ra;
wire[2 - 1:0] mem_ce;
denoise_g2_p3_core #(
.READ_PORT_COUNT( 2 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[2 * DataWidth - 1 : 1 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_q1 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q1) begin
q1 = mem_q1;
end
assign mem_ra = {address0, address1};
assign mem_ce = {ce0, ce1};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_g3_p0_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd2;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or rai_reg[1] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_g3_p0 (
address0,
ce0,
q0,
we0,
d0,
address1,
ce1,
q1,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input[AddressWidth-1:0] address1;
input ce1;
output[DataWidth-1:0] q1;
input clk;
reg[DataWidth-1:0] q0;
reg[DataWidth-1:0] q1;
wire[2 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[DataWidth - 1:0] mem_q1;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[2 * AddressWidth - 1:0] mem_ra;
wire[2 - 1:0] mem_ce;
denoise_g3_p0_core #(
.READ_PORT_COUNT( 2 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[2 * DataWidth - 1 : 1 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_q1 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q1) begin
q1 = mem_q1;
end
assign mem_ra = {address0, address1};
assign mem_ce = {ce0, ce1};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_g3_p1_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd1;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_g3_p1 (
address0,
ce0,
q0,
we0,
d0,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input clk;
reg[DataWidth-1:0] q0;
wire[1 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[1 * AddressWidth - 1:0] mem_ra;
wire[1 - 1:0] mem_ce;
denoise_g3_p1_core #(
.READ_PORT_COUNT( 1 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_ra = {address0};
assign mem_ce = {ce0};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_g3_p2_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd1;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_g3_p2 (
address0,
ce0,
q0,
we0,
d0,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input clk;
reg[DataWidth-1:0] q0;
wire[1 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[1 * AddressWidth - 1:0] mem_ra;
wire[1 - 1:0] mem_ce;
denoise_g3_p2_core #(
.READ_PORT_COUNT( 1 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_ra = {address0};
assign mem_ce = {ce0};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_g3_p3_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd2;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or rai_reg[1] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_g3_p3 (
address0,
ce0,
q0,
we0,
d0,
address1,
ce1,
q1,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input[AddressWidth-1:0] address1;
input ce1;
output[DataWidth-1:0] q1;
input clk;
reg[DataWidth-1:0] q0;
reg[DataWidth-1:0] q1;
wire[2 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[DataWidth - 1:0] mem_q1;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[2 * AddressWidth - 1:0] mem_ra;
wire[2 - 1:0] mem_ce;
denoise_g3_p3_core #(
.READ_PORT_COUNT( 2 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[2 * DataWidth - 1 : 1 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_q1 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q1) begin
q1 = mem_q1;
end
assign mem_ra = {address0, address1};
assign mem_ce = {ce0, ce1};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_g4_p0_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd2;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or rai_reg[1] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_g4_p0 (
address0,
ce0,
q0,
we0,
d0,
address1,
ce1,
q1,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input[AddressWidth-1:0] address1;
input ce1;
output[DataWidth-1:0] q1;
input clk;
reg[DataWidth-1:0] q0;
reg[DataWidth-1:0] q1;
wire[2 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[DataWidth - 1:0] mem_q1;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[2 * AddressWidth - 1:0] mem_ra;
wire[2 - 1:0] mem_ce;
denoise_g4_p0_core #(
.READ_PORT_COUNT( 2 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[2 * DataWidth - 1 : 1 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_q1 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q1) begin
q1 = mem_q1;
end
assign mem_ra = {address0, address1};
assign mem_ce = {ce0, ce1};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_g4_p1_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd1;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_g4_p1 (
address0,
ce0,
q0,
we0,
d0,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input clk;
reg[DataWidth-1:0] q0;
wire[1 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[1 * AddressWidth - 1:0] mem_ra;
wire[1 - 1:0] mem_ce;
denoise_g4_p1_core #(
.READ_PORT_COUNT( 1 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_ra = {address0};
assign mem_ce = {ce0};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_g4_p2_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd1;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_g4_p2 (
address0,
ce0,
q0,
we0,
d0,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input clk;
reg[DataWidth-1:0] q0;
wire[1 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[1 * AddressWidth - 1:0] mem_ra;
wire[1 - 1:0] mem_ce;
denoise_g4_p2_core #(
.READ_PORT_COUNT( 1 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_ra = {address0};
assign mem_ce = {ce0};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_g4_p3_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd2;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or rai_reg[1] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_g4_p3 (
address0,
ce0,
q0,
we0,
d0,
address1,
ce1,
q1,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input[AddressWidth-1:0] address1;
input ce1;
output[DataWidth-1:0] q1;
input clk;
reg[DataWidth-1:0] q0;
reg[DataWidth-1:0] q1;
wire[2 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[DataWidth - 1:0] mem_q1;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[2 * AddressWidth - 1:0] mem_ra;
wire[2 - 1:0] mem_ce;
denoise_g4_p3_core #(
.READ_PORT_COUNT( 2 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[2 * DataWidth - 1 : 1 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_q1 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q1) begin
q1 = mem_q1;
end
assign mem_ra = {address0, address1};
assign mem_ce = {ce0, ce1};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
// ==============================================================
// File generated by AutoPilot - High-Level Synthesis System (C, C++, SystemC)
// Version: 2010.a.3
// Copyright (C) :2006-2010 AutoESL Design Technologies, Inc.
//
// ==============================================================
`timescale 1 ns / 1 ps
`celldefine
module denoise_r0_p0_core (q, ra, ce, clk, d, wa, we);
parameter READ_PORT_COUNT=32'd1;
parameter WRITE_PORT_COUNT=32'd1;
parameter DATA_WIDTH=32'd32;
parameter ADDRESS_WIDTH=32'd8;
parameter WORD_COUNT=32'd225;
output [READ_PORT_COUNT*DATA_WIDTH-1:0] q;
input [READ_PORT_COUNT*ADDRESS_WIDTH-1:0] ra;
input [READ_PORT_COUNT-1:0] ce;
input [WRITE_PORT_COUNT*DATA_WIDTH-1:0] d;
input [WRITE_PORT_COUNT*ADDRESS_WIDTH-1:0] wa;
input [WRITE_PORT_COUNT-1:0] we;
input clk;
integer i,j,k;
reg [DATA_WIDTH-1:0] mem [0:WORD_COUNT-1];
reg [ADDRESS_WIDTH-1:0] rat;
reg [ADDRESS_WIDTH-1:0] rai [READ_PORT_COUNT-1:0];
reg [ADDRESS_WIDTH-1:0] rai_reg [READ_PORT_COUNT-1:0];
reg [READ_PORT_COUNT*DATA_WIDTH-1:0] qi;
reg [DATA_WIDTH-1:0] qt;
reg [DATA_WIDTH-1:0] di [WRITE_PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] dt;
reg [ADDRESS_WIDTH-1:0] wat;
reg [ADDRESS_WIDTH-1:0] wai [WRITE_PORT_COUNT-1:0];
// Split input data
always @ (d) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
dt[j]=d[i*DATA_WIDTH+j];
end
di[i]=dt;
end
end
// Split write addresses
always @ (wa) begin
for (i=0;i<WRITE_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
wat[j]=wa[i*ADDRESS_WIDTH+j];
end
wai[i]=wat;
end
end
// Write memory
always @ (posedge clk) begin
for (j=0;j<WRITE_PORT_COUNT;j=j+1) begin
if (we[j]) begin
mem[wai[j]] <= di[j];
end
end
end
// Split read addresses
always @ (ra) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
for (j=0;j<ADDRESS_WIDTH;j=j+1) begin
rat[j]=ra[i*ADDRESS_WIDTH+j];
end
rai[i]=rat;
end
end
// guide read addresses using CE
always @ (posedge clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if ( ce[i] ) begin
rai_reg[i] <= rai[i];
end
end
end
// Memory read
always @ (rai_reg[0] or clk) begin
for (i=0;i<READ_PORT_COUNT;i=i+1) begin
if (rai_reg[i] >= WORD_COUNT) begin
qt={DATA_WIDTH {1'b0}};
end else begin
qt=mem[rai_reg[i]];
end
for (j=0;j<DATA_WIDTH;j=j+1) begin
qi[i*DATA_WIDTH+j]=qt[j];
end
end
end
assign q=qi;
endmodule
`endcelldefine
module denoise_r0_p0 (
address0,
ce0,
q0,
we0,
d0,
clk);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd225;
parameter AddressWidth = 32'd8;
input[AddressWidth-1:0] address0;
input ce0;
output[DataWidth-1:0] q0;
input we0;
input[DataWidth-1:0] d0;
input clk;
reg[DataWidth-1:0] q0;
wire[1 * DataWidth - 1:0] mem_q;
wire[DataWidth - 1:0] mem_q0;
wire[1 - 1:0] mem_we;
wire[1 * DataWidth - 1:0] mem_d;
wire[1 * AddressWidth - 1:0] mem_wa;
wire[1 * AddressWidth - 1:0] mem_ra;
wire[1 - 1:0] mem_ce;
denoise_r0_p0_core #(
.READ_PORT_COUNT( 1 ),
.WRITE_PORT_COUNT( 1 ),
.DATA_WIDTH( DataWidth ),
.ADDRESS_WIDTH( AddressWidth ),
.WORD_COUNT( AddressRange ))
core_inst (
.q( mem_q ),
.ra( mem_ra ),
.ce( mem_ce ),
.d( mem_d ),
.wa( mem_wa ),
.we( mem_we ),
.clk( clk ));
assign mem_q0 = mem_q[1 * DataWidth - 1 : 0 * DataWidth];
always @ (mem_q0) begin
q0 = mem_q0;
end
assign mem_ra = {address0};
assign mem_ce = {ce0};
assign mem_we[0] = we0;
assign mem_d = {d0};
assign mem_wa = {address0};
endmodule
|
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