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`timescale 1ns / 1ps
/* Flit Queue
* FlitQueue.v
*
* Models a single 2-VC FlitQueue without credit channels
*
* Configuration path
* config_in -> FQCtrl -> config_out
*/
`include "const.v"
module FlitQueue_NC (
clock,
reset,
enable,
sim_time,
error,
is_quiescent,
latency, // For FQ to have access to the latency
config_in,
config_in_valid,
config_out,
config_out_valid,
flit_full,
flit_in_valid,
flit_in,
nexthop_in,
flit_ack,
flit_out,
flit_out_valid,
dequeue
);
`include "util.v"
parameter [`A_WIDTH-1:0] HADDR = 1; // 8-bit global node ID + 3-bit port ID
parameter LOG_NVCS = 1;
localparam NVCS = 1 << LOG_NVCS;
input clock;
input reset;
input enable;
input [`TS_WIDTH-1:0] sim_time;
output error;
output is_quiescent;
output [`LAT_WIDTH-1:0] latency;
// Config interface
input [15: 0] config_in;
input config_in_valid;
output [15: 0] config_out;
output config_out_valid;
// Flit interface (1 in, NVCS out)
output [NVCS-1: 0] flit_full;
input flit_in_valid;
input [`FLIT_WIDTH-1:0] flit_in;
input [`A_FQID] nexthop_in;
output flit_ack;
output [NVCS*`FLIT_WIDTH-1:0] flit_out; // One out interface per VC
output [NVCS-1: 0] flit_out_valid;
input [NVCS-1: 0] dequeue;
// Wires
wire [`LAT_WIDTH-1:0] w_latency;
wire w_flit_in_valid;
wire [`TS_WIDTH-1:0] w_flit_in_ts;
wire [`TS_WIDTH-1:0] w_flit_new_ts;
wire w_flit_in_vc;
wire [`FLIT_WIDTH-1:0] w_flit_to_enqueue;
wire [NVCS*`FLIT_WIDTH-1:0] w_flit_out;
wire w_flit_enqueue;
wire w_flit_dequeue;
wire [NVCS-1: 0] w_flit_full;
wire [NVCS-1: 0] w_flit_empty;
wire w_flit_error;
wire [NVCS-1: 0] w_flit_has_data;
wire w_ram_read;
wire w_ram_write;
genvar i;
// Output
assign error = w_flit_error;
assign is_quiescent = &w_flit_empty;
assign latency = w_latency;
assign flit_full = w_flit_full;
assign flit_ack = w_ram_write;
assign flit_out = w_flit_out;
assign w_ram_read = enable & w_flit_dequeue;
assign w_ram_write = enable & w_flit_enqueue;
// Simulation stuff
`ifdef SIMULATION
always @(posedge clock)
begin
if (w_ram_write)
$display ("T %x FQ (%x) recvs flit %x", sim_time, HADDR, flit_in);
end
generate
for (i = 0; i < NVCS; i = i + 1)
begin : sim_display
always @(posedge clock)
begin
if (dequeue[i])
$display ("T %x FQ (%x) sends flit %x (VC %d)", sim_time, HADDR, flit_out[(i+1)*`FLIT_WIDTH-1:i*`FLIT_WIDTH], flit_out[i*`FLIT_WIDTH]);
end
end
endgenerate
`endif
// FQ control unit (1 per context)
assign w_flit_in_valid = (nexthop_in == HADDR[`A_FQID]) ? (enable & flit_in_valid) : 1'b0;
assign w_flit_in_ts = flit_in[`F_TS];
FQCtrl ctrl (
.clock (clock),
.reset (reset),
.in_ready (w_flit_in_valid),
.in_timestamp (w_flit_in_ts),
.out_timestamp (w_flit_new_ts),
.config_in (config_in),
.config_in_valid (config_in_valid),
.config_out (config_out),
.config_out_valid (config_out_valid),
.bandwidth (),
.latency (w_latency));
// Flit FIFO (64 deep)
assign w_flit_in_vc = flit_vc (flit_in);
assign w_flit_to_enqueue = update_flit_ts (flit_in, w_flit_new_ts);
generate
if (LOG_NVCS == 0)
begin
assign w_flit_enqueue = w_flit_in_valid & ~w_flit_full;
assign w_flit_dequeue = dequeue;
assign w_flit_error = 1'b0;
RAMFIFO_single_slow #(.WIDTH(`FLIT_WIDTH), .LOG_DEP(6)) fq (
.clock (clock),
.reset (reset),
.enable (enable),
.data_in (w_flit_to_enqueue),
.data_out (w_flit_out),
.write (w_ram_write),
.read (w_ram_read),
.full (w_flit_full),
.empty (w_flit_empty),
.has_data (w_flit_has_data));
end
else
begin
wire [LOG_NVCS-1: 0] w_flit_dequeue_ccid;
wire w_flit_fifo_full;
assign w_flit_enqueue = w_flit_in_valid & ~w_flit_fifo_full;
mux_Nto1 #(.WIDTH(1), .SIZE(NVCS)) enqueue_mux (
.in (w_flit_full),
.sel (w_flit_in_vc),
.out (w_flit_fifo_full));
//RAMFIFO #(.WIDTH(`FLIT_WIDTH), .LOG_DEP(6), .LOG_CTX(LOG_NVCS)) fq (
RAMFIFO_slow #(.WIDTH(`FLIT_WIDTH), .LOG_DEP(6), .LOG_CTX(LOG_NVCS)) fq (
.clock (clock),
.reset (reset),
.enable (enable),
.rcc_id (w_flit_dequeue_ccid),
.wcc_id (w_flit_in_vc),
.data_in (w_flit_to_enqueue),
.data_out (w_flit_out),
.write (w_ram_write),
.read (w_ram_read),
.full (w_flit_full),
.empty (w_flit_empty),
.has_data (w_flit_has_data),
.error (w_flit_error));
encoder_N #(.SIZE(NVCS)) dequeue_encoder (
.decoded (dequeue),
.encoded (w_flit_dequeue_ccid),
.valid (w_flit_dequeue));
end
endgenerate
// Flit out interface
generate
for (i = 0; i < NVCS; i = i + 1)
begin : fout
wire [`TS_WIDTH-1:0] w_flit_out_ts;
assign w_flit_out_ts = flit_ts (w_flit_out[(i+1)*`FLIT_WIDTH-1:i*`FLIT_WIDTH]);
flit_out_inf inf (
.clock (clock),
.reset (reset),
.dequeue (dequeue[i]),
.flit_valid (w_flit_has_data[i]),
.flit_timestamp (w_flit_out_ts),
.sim_time (sim_time),
.ready (flit_out_valid[i]));
end
endgenerate
endmodule
|
`timescale 1 ns/100 ps // time unit = 1ns; precision = 1/10 ns
`include "const.v"
/* Flit Out Interface
* flit_out_inf.v
*
* Given timestamp of a flit, generate the ready signals.
* Since we only use 4-bit time differences, a flit that arrives at the output
* of the FQ more than 8 steps late will be considered a "future" flit due to
* timestamp overflow. However, this should not happen because incoming flits to
* the FQ should never be late.
* A flit may wait at the output of the FQ for more than 8 steps after its timestamp
* if the downstream Router cannot route this flit. In this case, the r_valid bi-modal
* state machine will keep the ready signal high even when timestamp overflows.
*/
module flit_out_inf (
input clock,
input reset,
input dequeue,
input flit_valid,
input [`TS_WIDTH-1:0] flit_timestamp,
input [`TS_WIDTH-1:0] sim_time,
output ready // ready when flit_timestamp <= sim_time
);
parameter WIDTH = `TS_WIDTH; // Number of bits to use to compute time difference
wire [WIDTH-1: 0] w_timestamp_diff;
wire w_valid;
reg r_valid;
// Ready
assign w_timestamp_diff = sim_time[WIDTH-1:0] - flit_timestamp[WIDTH-1:0];
assign w_valid = ~w_timestamp_diff[WIDTH-1] & flit_valid;
assign ready = w_valid | r_valid;
always @(posedge clock)
begin
if (reset)
r_valid <= 0;
else if (~r_valid)
r_valid <= w_valid & ~dequeue;
else if (dequeue)
r_valid <= 0;
end
endmodule
|
`timescale 1ns / 1ps
/* FQCtrl.v
* Bandwidth control unit for FQ. One per FQ. The path from in_ready to
* out_timestamp completes in 1 cycle.
*
* Config path
* config_in -> {bandwidth, latency} -> config_out
*/
`include "const.v"
module FQCtrl(
clock,
reset,
in_ready,
in_timestamp,
out_timestamp,
config_in,
config_in_valid,
config_out,
config_out_valid,
bandwidth,
latency
);
localparam RESET = 0, COUNT = 1;
input clock;
input reset;
input in_ready;
input [`TS_WIDTH-1:0] in_timestamp;
output [`TS_WIDTH-1:0] out_timestamp;
// Config ports
input config_in_valid;
input [15: 0] config_in;
output config_out_valid;
output [15: 0] config_out;
// Exposing parameters
output [`BW_WIDTH-1:0] bandwidth;
output [`LAT_WIDTH-1:0] latency;
// Internal states
reg [`BW_WIDTH-1:0] bandwidth;
reg [`LAT_WIDTH-1:0] latency;
reg [`BW_WIDTH-1:0] count;
reg [`TS_WIDTH-1:0] last_ts;
// Wires
reg [`BW_WIDTH-1:0] w_count;
reg [`TS_WIDTH-1:0] w_ts_bw_component;
// Output
assign config_out_valid = config_in_valid;
assign config_out = {bandwidth, latency};
assign out_timestamp = w_ts_bw_component + {2'b00, latency};
//
// Configuration logic
//
always @(posedge clock)
begin
if (reset)
{bandwidth, latency} <= {(`BW_WIDTH+`LAT_WIDTH){1'b0}};
else if (config_in_valid)
{bandwidth, latency} <= config_in;
end
//
// FQ Control
//
wire w_in_timestamp_gt_last_ts;
wire [`TS_WIDTH-1:0] w_ts_diff;
assign w_ts_diff = last_ts - in_timestamp;
assign w_in_timestamp_gt_last_ts = w_ts_diff[`TS_WIDTH-1];
always @(*)
begin
w_count = count;
w_ts_bw_component = in_timestamp;
if (in_ready)
begin
if (count == bandwidth || w_in_timestamp_gt_last_ts == 1'b1)
w_count = 1;
else
w_count = count + 1;
// Huge area...
if (w_in_timestamp_gt_last_ts)
w_ts_bw_component = in_timestamp;
else if (count == bandwidth)
w_ts_bw_component = last_ts + 1;
else
w_ts_bw_component = last_ts;
end
end
always @(posedge clock)
begin
if (reset)
begin
last_ts <= 0;
count <= 0;
end
else if (in_ready)
begin
last_ts <= w_ts_bw_component;
count <= w_count;
end
end
endmodule
|
`timescale 1ns / 1ps
/* FQCtrlFSM.v
* Bandwidth control unit for FQ. One per FQ. The path from in_ready to
* out_timestamp completes in 1 cycle.
*
* Config path
* config_in -> {bandwidth, latency} -> config_out
*/
//TODO: Not finished. Use FQCtrl.v instead.
`include "const.v"
module FQCtrlFSM(
clock,
reset,
sim_time,
sim_time_tick,
in_ready,
in_timestamp,
out_timestamp,
config_in,
config_in_valid,
config_out,
config_out_valid
);
localparam RESET = 0, COUNT = 1;
input clock;
input reset;
input [`TS_WIDTH-1:0] sim_time;
input sim_time_tick;
input in_ready;
input [`TS_WIDTH-1:0] in_timestamp;
output [`TS_WIDTH-1:0] out_timestamp;
// Config ports
input config_in_valid;
input [15: 0] config_in;
output config_out_valid;
output [15: 0] config_out;
// Internal states
reg [`BW_WIDTH-1:0] bandwidth;
reg [ 7: 0] latency;
reg [`BW_WIDTH-1:0] count;
reg [`TS_WIDTH-1:0] last_ts;
reg [`TS_WIDTH-1:0] reset_when;
reg state;
reg next_state;
// Wires
reg [ 1: 0] w_count_sel;
reg [`TS_WIDTH-1:0] w_ts_bw_component;
wire in_ts_is_newer;
// Output
assign config_out_valid = config_in_valid;
assign config_out = {bandwidth, latency};
assign out_timestamp = w_ts_bw_component + latency;
// Wires
assign in_ts_is_newer = (in_timestamp > last_ts) ? 1'b1 : 1'b0;
//
// Configuration logic
//
always @(posedge clock or posedge reset)
begin
if (reset)
{bandwidth, latency} <= {(`BW_WIDTH+8){1'b0}};
else if (config_in_valid)
{bandwidth, latency} <= config_in;
end
//
// FSM
//
always @(posedge clock or posedge reset)
begin
if (reset)
state <= 2'b00;
else
state <= next_state;
end
// FSM state transition
always @(*)
begin
next_state = state;
w_count_sel = 2; // Keep old count value
case (state)
RESET:
begin
if (in_ready)
begin
next_state = COUNT;
w_count_sel = 1; // Set count to 1
end
end
COUNT:
begin
if (in_ready)
begin
if (count == bandwidth || in_ts_is_newer == 1'b1)
w_count_sel = 1; // Set count to 1
else
w_count_sel = 3; // Increment count
end
/*else if (sim_time_tick == 1'b1 && reset_when == sim_time)
begin
next_state = RESET;
w_count_sel = 0; // Set count to 0
end*/
end
endcase
end
always @(posedge clock or posedge reset)
begin
if (reset)
begin
count <= {(`BW_WIDTH){1'b0}};
last_ts <= {(`TS_WIDTH){1'b0}};
reset_when <= {(`TS_WIDTH){1'b0}};
end
else
begin
if (w_count_sel[1] == 1'b0)
count <= {{(`BW_WIDTH-1){1'b0}}, w_count_sel[0]};
else
count <= count + {{(`BW_WIDTH-1){1'b0}}, w_count_sel[0]};
last_ts <= w_ts_bw_component;
if (w_count_sel == 0) // Reset counter
reset_when <= reset_when + 1;
else
reset_when <= out_timestamp;
end
end
always @(*)
begin
if (w_count_sel == 2'b1)
w_ts_bw_component = in_timestamp;
else
w_ts_bw_component = last_ts + 1;
end
endmodule
|
`timescale 1ns / 1ps
/* FQCtrl_test.v
* Wrapper module to test the critical path of FQCtrl
*/
`include "const.v"
module FQCtrl_wrapper(
clock,
reset,
in_ready,
in_timestamp,
config_in,
config_in_valid,
out
);
input clock;
input reset;
input in_ready;
input [`TS_WIDTH-1:0] in_timestamp;
output [15:0] out;
// Config ports
input config_in_valid;
input [15: 0] config_in;
reg r_in_ready;
reg [`TS_WIDTH-1:0] r_in_timestamp;
reg [15: 0] r_config_in;
reg r_config_in_valid;
reg [`TS_WIDTH-1:0] r_out_timestamp;
reg [15: 0] r_config_out;
reg r_config_out_valid;
wire [`TS_WIDTH-1:0] w_out_timestamp;
wire [15: 0] w_config_out;
wire w_config_out_valid;
assign out = (r_config_out_valid) ? r_config_out : r_out_timestamp;
always @(posedge clock or posedge reset)
begin
if (reset)
begin
r_in_ready <= 0;
r_in_timestamp <= 0;
r_config_in <= 0;
r_config_in_valid <= 0;
r_out_timestamp <= 0;
r_config_out <= 0;
r_config_out_valid <= 0;
end
else
begin
r_in_ready <= in_ready;
r_in_timestamp <= in_timestamp;
r_config_in <= config_in;
r_config_in_valid <= config_in_valid;
r_out_timestamp <= w_out_timestamp;
r_config_out <= w_config_out;
r_config_out_valid <= w_config_out_valid;
end
end
FQCtrl ut (
.clock (clock),
.reset (reset),
.in_ready (r_in_ready),
.in_timestamp (r_in_timestamp),
.out_timestamp (w_out_timestamp),
.config_in (r_config_in),
.config_in_valid (r_config_in_valid),
.config_out (w_config_out),
.config_out_valid (w_config_out_valid));
endmodule
|
`timescale 1 ns/100 ps // time unit = 1ns; precision = 1/10 ns
/* Interconnect Destination Side Partition
* ICDestPart.v
*/
`include "const.v"
module ICDestPart #(
parameter PID = 3'b000, // Partition ID
parameter NSP = 8, // Number of source partitions
parameter WIDTH = `FLIT_WIDTH // Data width
)
(
// Global interface
input clock,
input reset,
input enable,
output error,
// Stage 1 interface
input [NSP-1:0] src_s1_valid, // Stage 1 ready signals from all partitions
input [NSP-1:0] src_s1_valid_urgent, // Stage 1 urgent ready signals
input [NSP*`A_WIDTH-1:0] src_s1_nexthop_in, // Stage 1 nexthops
output [NSP-1:0] src_s1_part_sel, // Decoded source partition select
// Stage 2 input
input [NSP*WIDTH-1:0] src_s2_data_in, // Stage 2 data values
input [NSP*`A_WIDTH-1:0] src_s2_nexthop_in, // Stage 2 nexthop values
// Destination side interface
input dequeue, // Ack from node
output [WIDTH-1:0] s3_data_out, // Stage 3 data
output [`A_FQID] s3_nexthop_out, // Stage 3 nexthop (Node ID and port ID only)
output s3_data_valid
);
`include "math.v"
localparam PIPE_WIDTH = WIDTH + `A_FQID; // Data + (local node ID (4) + port ID (3))
// Internal stages
reg [CLogB2(NSP-1)-1:0] r_sel;
reg r_sel_valid; // A valid data was selected
reg [PIPE_WIDTH-1: 0] r_dest_bus_out;
reg r_dest_bus_valid;
reg r_error;
// Wires
wire [NSP-1:0] w_s1_dest_check;
wire [NSP-1:0] w_s1_valid;
wire [NSP-1:0] w_s1_valid_urgent;
wire [NSP-1:0] w_s1_sel;
wire w_s1_sel_valid;
wire [CLogB2(NSP-1)-1:0] w_s1_sel_encoded;
wire [NSP*PIPE_WIDTH-1:0] w_s2_mux_in;
wire [PIPE_WIDTH-1:0] w_s2_mux_out;
// Output
assign error = r_error;
assign src_s1_part_sel = (enable) ? w_s1_sel : {(NSP){1'b0}};
assign {s3_data_out, s3_nexthop_out} = r_dest_bus_out;
assign s3_data_valid = r_dest_bus_valid;
// Reorder input signals to connect to the MUX
genvar i;
generate
for (i = 0; i < NSP; i = i + 1)
begin : src_s2
wire [WIDTH-1:0] data;
wire [`A_WIDTH-1:0] nexthop; // 4-bit local node ID + 3-bit port ID
assign data = src_s2_data_in[(i+1)*WIDTH-1:i*WIDTH];
assign nexthop = src_s2_nexthop_in[(i+1)*`A_WIDTH-1:i*`A_WIDTH];
assign w_s2_mux_in[(i+1)*PIPE_WIDTH-1:i*PIPE_WIDTH] = {data, nexthop[`A_FQID]};
end
endgenerate
// Figure out which of the incoming datas are for this destination
check_dest #(.N(NSP), .PID(PID)) cd (
.src_nexthop_in (src_s1_nexthop_in),
.valid (w_s1_dest_check));
assign w_s1_valid = src_s1_valid & w_s1_dest_check;
assign w_s1_valid_urgent = src_s1_valid_urgent & w_s1_dest_check;
// Select a ready source part (pick an urgent one if applicable) among the 8
select_ready #(.N(NSP)) arb_src (
.ready (w_s1_valid),
.ready_urgent (w_s1_valid_urgent),
.sel (w_s1_sel),
.sel_valid (w_s1_sel_valid),
.sel_valid_urgent ());
encoder_N #(.SIZE(NSP)) src_sel_encode (
.decoded (w_s1_sel),
.encoded (w_s1_sel_encoded),
.valid ());
// Destination MUX (this is part of stage 2)
mux_Nto1 #(.WIDTH(PIPE_WIDTH), .SIZE(NSP)) dest_mux (
.in (w_s2_mux_in),
.sel (r_sel),
.out (w_s2_mux_out));
// Pipeline registers
always @(posedge clock)
begin
if (reset)
begin
r_sel <= 3'b000;
r_sel_valid <= 1'b0;
end
else if (enable)
begin
r_sel <= w_s1_sel_encoded;
r_sel_valid <= w_s1_sel_valid;
end
end
// Stage 2 FIFO registers (note this "FIFO" will never have more than 1 element)
always @(posedge clock)
begin
if (reset)
begin
r_dest_bus_valid <= 1'b0;
r_dest_bus_out <= {(72){1'b0}};
end
else if (enable)
begin
r_dest_bus_valid <= r_sel_valid;
r_dest_bus_out <= w_s2_mux_out;
end
end
// Errors
always @(posedge clock)
begin
if (reset)
begin
r_error <= 1'b0;
end
else if (r_dest_bus_valid & (~dequeue) & enable)
begin
r_error <= 1'b1; // Last data was valid, but not acknowledged
end
end
endmodule
|
`timescale 1 ns/100 ps // time unit = 1ns; precision = 1/10 ns
/* Interconnect Source Partition
* ICSourcePart.v
*
* Connects Routers to FQ/TGs. Does not stall the simulator.
*/
`include "const.v"
module ICSourcePart #(
parameter N = 2, // Number of nodes connected to this partition
parameter WIDTH = `FLIT_WIDTH
)
(
// Global interface
input clock,
input reset,
input enable,
// Partition control
input select, // This source partition is selected for stage 2
output can_increment,
// Source node interface
input [N-1:0] src_data_valid,
input [N-1:0] src_data_valid_urgent,
input [N*WIDTH-1:0] src_data_in,
input [N*`ADDR_WIDTH-1:0] src_nexthop_in,
output [N-1:0] src_dequeue,
// Stage 1 output
output [`ADDR_WIDTH-1:0] s1_nexthop_out,
output s1_valid,
output s1_valid_urgent,
// Stage 2 output
output [WIDTH-1:0] s2_data_out,
output [`ADDR_WIDTH-1:0] s2_nexthop_out
);
`include "math.v"
// Internal stages
reg [WIDTH-1:0] r_pipe_data;
reg [`ADDR_WIDTH-1:0] r_pipe_nexthop;
// Wires
wire [WIDTH-1:0] w_s1_data;
wire [`ADDR_WIDTH-1:0] w_s1_nexthop;
wire [N-1:0] w_s1_sel;
wire w_s1_valid;
wire w_s1_valid_urgent;
// Output
assign can_increment = ~w_s1_valid_urgent;
assign src_dequeue = (select & w_s1_valid) ? w_s1_sel : {(N){1'b0}};
assign s1_nexthop_out = w_s1_nexthop;
assign s1_valid = w_s1_valid;
assign s1_valid_urgent = w_s1_valid_urgent;
assign s2_data_out = r_pipe_data;
assign s2_nexthop_out = r_pipe_nexthop;
genvar i;
generate
// Only one node is connected to this SourcePart
if (N == 1)
begin
assign w_s1_sel = 1'b1;
assign w_s1_valid = src_data_valid;
assign w_s1_valid_urgent = src_data_valid_urgent;
assign w_s1_data = src_data_in;
assign w_s1_nexthop = src_nexthop_in;
end
// More than one node is connected to this SourcePart
else
begin
wire [N*(WIDTH+`ADDR_WIDTH)-1:0] w_source_mux_in;
// Scramble the input bits to generate the MUX in signals
for (i = 0; i < N; i = i + 1)
begin : in
wire [WIDTH-1: 0] data;
wire [`ADDR_WIDTH-1: 0] nexthop;
assign data = src_data_in[(i+1)*WIDTH-1:i*WIDTH];
assign nexthop = src_nexthop_in[(i+1)*`ADDR_WIDTH-1:i*`ADDR_WIDTH];
assign w_source_mux_in[(i+1)*(WIDTH+`ADDR_WIDTH)-1:i*(WIDTH+`ADDR_WIDTH)] = {data, nexthop};
end
// Source partition arbiter
select_ready #(.N(N)) arb_input (
.ready (src_data_valid),
.ready_urgent (src_data_valid_urgent),
.sel (w_s1_sel),
.sel_valid (w_s1_valid),
.sel_valid_urgent (w_s1_valid_urgent));
// Source partition MUX
mux_Nto1_decoded #(.WIDTH(WIDTH + `ADDR_WIDTH), .SIZE(N)) source_mux (
.in(w_source_mux_in),
.sel (w_s1_sel),
.out ({w_s1_data, w_s1_nexthop}));
end
endgenerate
// Pipeline registers for this partition
always @(posedge clock)
begin
if (reset)
begin
r_pipe_data <= {(WIDTH){1'b0}};
r_pipe_nexthop <= {(`ADDR_WIDTH){1'b0}};
end
else if (enable)
begin
r_pipe_data <= w_s1_data;
r_pipe_nexthop <= w_s1_nexthop;
end
end
endmodule
|
`timescale 1ns/100 ps // time unit = 1ns; precision = 1/10 ns
/* Router
* Router.v
*
* Single N-port Router. NPORTS x NVCS input ports, 1 output port
*
* Configuration path:
* config_in -> CreditCounter_0 -> ... -> CreditCounter_N (N = nports * nvc) -> config_out
* ram_config_in -> Input RouterPortLookup -> Output RouterPortLookup -> ram_config_out
*/
`include "const.v"
module InputVCState #(
parameter VC_WIDTH = 1,
NINPUTS = 10
)
(
input clock,
input reset,
input [VC_WIDTH-1:0] allocated_vc,
input allocate_enable,
input [NINPUTS-1:0] ivc_sel,
output [VC_WIDTH-1:0] assigned_vc
);
`include "math.v"
localparam LOG_NINPUTS = CLogB2(NINPUTS-1);
// Assigned output VC for each input VC
reg [VC_WIDTH*NINPUTS-1:0] assigned_ovc;
genvar i;
generate
for (i = 0; i < NINPUTS; i = i + 1)
begin : ivc
always @(posedge clock)
begin
if (reset)
begin
assigned_ovc[(i+1)*VC_WIDTH-1:i*VC_WIDTH] <= 0;
end
else if (allocate_enable & ivc_sel[i])
begin
assigned_ovc[(i+1)*VC_WIDTH-1:i*VC_WIDTH] <= allocated_vc;
end
end
end
endgenerate
// Select the output VC
mux_Nto1_decoded #(.WIDTH(VC_WIDTH), .SIZE(NINPUTS)) vc_mux (
.in (assigned_ovc),
.sel (ivc_sel),
.out (assigned_vc));
endmodule
|
`timescale 1ns / 1ps
module is_greater_than (
a,
b,
a_gt_b
);
parameter N = 32;
input [N-1:0] a;
input [N-1:0] b;
output a_gt_b;
wire [N-1:0] diff;
assign diff = b - a;
assign a_gt_b = diff[N-1];
endmodule
|
`timescale 1ns / 1ps
module is_less_than (
a,
b,
a_lt_b
);
parameter N = 32;
input [N-1:0] a;
input [N-1:0] b;
output a_lt_b;
wire [N-1:0] diff;
assign diff = a - b;
assign a_lt_b = diff[N-1];
endmodule
|
`timescale 1ns / 1ps
/* LFSR3_9.v
* Linear Feedback Shift Register (any length between 3 to 9 bits)
*/
module LFSR3_9(
clock,
reset,
enable,
dout,
dout_next
);
parameter LENGTH = 6;
parameter FULL_CYCLE = 1;
input clock;
input reset;
input enable;
output [LENGTH-1: 0] dout;
output [LENGTH-1: 0] dout_next;
// Shift register
reg [LENGTH-1: 0] dout;
// Feedback signal
wire din;
wire lockup;
// Output
assign dout_next = {dout[LENGTH-2:0], din};
// Maximal period
generate
if (LENGTH == 3 || LENGTH == 4 || LENGTH == 6 || LENGTH == 7)
assign din = dout[LENGTH-1] ^ dout[LENGTH-2] ^ lockup;
else if (LENGTH == 5)
assign din = dout[4] ^ dout[2] ^ lockup;
else if (LENGTH == 8)
assign din = dout[7] ^ dout[5] ^ dout[4] ^ dout[3] ^ lockup;
else if (LENGTH == 9)
assign din = dout[8] ^ dout[4] ^ lockup;
else
begin
//$display ("LFSR Error: Don't know what to do with length %d", LENGTH);
assign din = dout[0];
end
// Lock-up state detection
if (FULL_CYCLE == 1)
assign lockup = ~|(dout[LENGTH-2:0]);
else
assign lockup = 1'b0;
endgenerate
always @(posedge clock)
begin
if (reset)
dout <= {(LENGTH){1'b1}};
else if (enable)
dout <= dout_next;
end
endmodule
|
// Ceil of log base 2
function integer CLogB2;
input [31:0] size;
integer i;
begin
i = size;
for (CLogB2 = 0; i > 0; CLogB2 = CLogB2 + 1)
i = i >> 1;
end
endfunction
|
`timescale 1 ns/100 ps // time unit = 1ns; precision = 1/10 ns
/* max2
* max2.v
*
* Combinational logic to select the larger signal of the two
*/
module max2 (
a,
b,
out
);
parameter WIDTH = 10;
input [WIDTH-1:0] a;
input [WIDTH-1:0] b;
output [WIDTH-1:0] out;
wire [WIDTH-1:0] diff = b-a;
assign out = (diff[WIDTH-1]) ? a : b;
endmodule
|
`timescale 1ns / 1ps
/* mux_Nto1.v
* N-to-1 mux with encoded select
* N has to be a power of 2
*/
module mux_Nto1 (
in,
sel,
out
);
`include "math.v"
parameter WIDTH = 1;
parameter SIZE = 10;
input [WIDTH*SIZE-1:0] in;
input [CLogB2(SIZE-1)-1:0] sel;
output [WIDTH-1:0] out;
// MUX function
genvar i, j;
generate
for (i = 0; i < WIDTH; i = i + 1)
begin : scramble
wire [SIZE-1:0] din;
for (j = 0; j < SIZE; j = j + 1)
begin : in_inf
assign din[j] = in[j*WIDTH + i];
end
assign out[i] = din[sel];
end
endgenerate
endmodule
|
`timescale 1ns / 1ps
/* mux_Nto1.v
* N-to-1 mux with decoded select
* N has to be a power of 2
*/
module mux_Nto1_decoded (
in,
sel,
out
);
parameter WIDTH = 4;
parameter SIZE = 4;
input [WIDTH*SIZE-1:0] in;
input [SIZE-1:0] sel;
output [WIDTH-1:0] out;
genvar i, j;
generate
for (i = 0; i < WIDTH; i = i + 1)
begin : scramble
wire [SIZE-1:0] din;
for (j = 0; j < SIZE; j = j + 1)
begin : in_inf
assign din[j] = in[j*WIDTH + i];
end
assign out[i] = |(din & sel);
end
endgenerate
endmodule
|
`timescale 1ns / 1ps
/* mux_Nto1_wrapper.v
* Wrapper for mux_Nto1 module to test Fmax
*/
module mux_Nto1_wrapper(
clock,
reset,
in,
sel,
out
);
parameter WIDTH = 4;
parameter SIZE = 8;
localparam LOG_SIZE = CLogB2(SIZE-1);
input clock;
input reset;
input [WIDTH*SIZE-1:0] in;
input [LOG_SIZE-1:0] sel;
output out;
reg [WIDTH*SIZE-1:0] r_in;
reg [LOG_SIZE-1:0] r_sel_e;
reg [WIDTH-1:0] r_out_e;
reg [SIZE-1:0] r_sel_d;
reg [WIDTH-1:0] r_out_d;
wire [WIDTH-1:0] w_out_e;
wire [WIDTH-1:0] w_out_d;
wire [SIZE-1:0] w_sel_d;
assign out = |(r_out_e ^ r_out_d);
// Ceil of log base 2
function integer CLogB2;
input [31:0] size;
integer i;
begin
i = size;
for (CLogB2 = 0; i > 0; CLogB2 = CLogB2 + 1)
i = i >> 1;
end
endfunction
mux_Nto1 #(.WIDTH(WIDTH), .SIZE(SIZE)) ute (
.in (r_in),
.sel (r_sel_e),
.out (w_out_e));
mux_Nto1_decoded #(.WIDTH(WIDTH), .SIZE(SIZE)) utd (
.in (r_in),
.sel (r_sel_d),
.out (w_out_d));
decoder_N #(.LOG_SIZE (LOG_SIZE)) dec (
.encoded (sel),
.decoded (w_sel_d));
always @(posedge clock or posedge reset)
begin
if (reset)
begin
r_in <= 0;
r_sel_e <= 0;
r_out_e <= 0;
r_sel_d <= 0;
r_out_d <= 0;
end
else
begin
r_in <= in;
r_sel_e <= sel;
r_out_e <= w_out_e;
r_sel_d <= w_sel_d;
r_out_d <= w_out_d;
end
end
endmodule
|
`timescale 1ns / 1ps
/* Test the UART rx and tx modules by first receiving 100 words
* from UART, store into RAM and send them back
*/
module myuart_fifotest (
input SYSTEM_CLOCK,
input SW_0,
input SW_1,
input SW_3,
input RS232_RX_DATA,
output RS232_TX_DATA,
output LED_0,
output LED_1,
output LED_2,
output LED_3
);
wire clock_fb;
wire dcm_locked;
wire clock;
wire reset;
wire error;
wire rx_error;
wire tx_error;
reg [3:0] led_out;
wire [15:0] to_fifo_data;
wire to_fifo_valid;
wire [15:0] from_fifo_data;
wire fifo_empty;
wire fifo_read;
assign {LED_3, LED_2, LED_1, LED_0} = ~led_out;
always @(*)
begin
case ({SW_1, SW_0})
2'b00: led_out = {reset, rx_error, tx_error, dcm_locked};
2'b01: led_out = {2'b00, ~RS232_RX_DATA, ~RS232_TX_DATA};
default: led_out = 4'b0000;
endcase
end
assign reset = SW_3;
DCM #(
.SIM_MODE("SAFE"), // Simulation: "SAFE" vs. "FAST", see "Synthesis and Simulation Design Guide" for details
.CLKDV_DIVIDE(2.0), // Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
// 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
.CLKFX_DIVIDE(1), // Can be any integer from 1 to 32
.CLKFX_MULTIPLY(4), // Can be any integer from 2 to 32
.CLKIN_DIVIDE_BY_2("FALSE"), // TRUE/FALSE to enable CLKIN divide by two feature
.CLKIN_PERIOD(0.0), // Specify period of input clock
.CLKOUT_PHASE_SHIFT("NONE"), // Specify phase shift of NONE, FIXED or VARIABLE
.CLK_FEEDBACK("1X"),// Specify clock feedback of NONE, 1X or 2X
.DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), // SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
// an integer from 0 to 15
.DFS_FREQUENCY_MODE("LOW"), // HIGH or LOW frequency mode for frequency synthesis
.DLL_FREQUENCY_MODE("LOW"), // HIGH or LOW frequency mode for DLL
.DUTY_CYCLE_CORRECTION("TRUE"), // Duty cycle correction, TRUE or FALSE
.FACTORY_JF(16'hC080), // FACTORY JF values
.PHASE_SHIFT(0), // Amount of fixed phase shift from -255 to 255
.STARTUP_WAIT("FALSE") // Delay configuration DONE until DCM LOCK, TRUE/FALSE
) DCM_inst (
.CLK0(clock_fb), // 0 degree DCM CLK output
.CLK180(), // 180 degree DCM CLK output
.CLK270(), // 270 degree DCM CLK output
.CLK2X(), // 2X DCM CLK output
.CLK2X180(), // 2X, 180 degree DCM CLK out
.CLK90(), // 90 degree DCM CLK output
.CLKDV(clock), // Divided DCM CLK out (CLKDV_DIVIDE)
.CLKFX(), // DCM CLK synthesis out (M/D)
.CLKFX180(), // 180 degree CLK synthesis out
.LOCKED(dcm_locked), // DCM LOCK status output
.PSDONE(), // Dynamic phase adjust done output
.STATUS(), // 8-bit DCM status bits output
.CLKFB(clock_fb), // DCM clock feedback
.CLKIN(SYSTEM_CLOCK), // Clock input (from IBUFG, BUFG or DCM)
.PSCLK(1'b0), // Dynamic phase adjust clock input
.PSEN(1'b0), // Dynamic phase adjust enable input
.PSINCDEC(0), // Dynamic phase adjust increment/decrement
.RST(reset) // DCM asynchronous reset input
);
// DART UART port (user data width = 16)
dartport #(.WIDTH(16)) dartio (
.clock (clock),
.reset (reset),
.enable (dcm_locked),
.rx_error (rx_error),
.tx_error (tx_error),
.RS232_RX_DATA (RS232_RX_DATA),
.RS232_TX_DATA (RS232_TX_DATA),
.rx_data (to_fifo_data),
.rx_valid (to_fifo_valid),
.tx_data (from_fifo_data),
.tx_valid (~fifo_empty),
.tx_ack (fifo_read));
// Data FIFO
fifo buffer (
.clk (clock),
.rst (reset),
.din (to_fifo_data),
.wr_en (to_fifo_valid & dcm_locked),
.dout (from_fifo_data),
.rd_en (fifo_read & dcm_locked),
.empty (fifo_empty),
.full ());
endmodule
|
`timescale 1ns / 1ps
/* Simple UART RX module (9600 baud rate)
*/
module myuart_rx #(
parameter BAUD_RATE = 9600
)
(
input clock,
input reset,
input enable,
output error,
input rx_data_in,
output [7:0] data_out,
output data_out_valid
);
localparam RX_IDLE = 0,
RX_START = 1,
RX_STOP = 2,
RX_ERROR = 3;
// Internal States
reg [ 8: 0] rx_word; // MSB = parity
reg rx_word_valid;
reg [ 3: 0] rx_bit_count; // Count the number of bits received
reg [ 1: 0] rx_state;
// Wires
reg [ 1: 0] next_rx_state;
reg [ 8: 0] next_rx_word; // MSB = parity
reg next_rx_word_valid;
reg [ 3: 0] next_rx_bit_count;
wire rx_tick;
reg rx_start; // Indicate a start bit is detected
wire parity; // odd parity
// Output
assign data_out = rx_word;
assign data_out_valid = rx_word_valid;
assign error = (rx_state == RX_ERROR) ? 1'b1 : 1'b0;
assign parity = ~(rx_word[0]^rx_word[1]^rx_word[2]^rx_word[3]^rx_word[4]^rx_word[5]^rx_word[6]^rx_word[7]);
// Baud tick generator
baud_gen #(.BAUD_RATE(BAUD_RATE)) rx_tick_gen (
.clock (clock),
.reset (reset),
.start (rx_start),
.baud_tick (rx_tick));
// RX register
always @(posedge clock)
begin
if (reset)
begin
rx_word <= 8'h00;
rx_word_valid <= 1'b0;
rx_bit_count <= 4'h0;
end
else if (enable)
begin
rx_word <= next_rx_word;
rx_word_valid <= next_rx_word_valid;
rx_bit_count <= next_rx_bit_count;
end
end
// RX state machine
always @(posedge clock)
begin
if (reset)
rx_state <= RX_IDLE;
else if (enable)
rx_state <= next_rx_state;
end
always @(*)
begin
rx_start = 1'b0;
next_rx_state = rx_state;
next_rx_word = rx_word;
next_rx_word_valid = 1'b0;
next_rx_bit_count = rx_bit_count;
case (rx_state)
RX_IDLE:
begin
if (~rx_data_in)
begin
next_rx_state = RX_START;
rx_start = 1'b1;
end
next_rx_bit_count = 4'h0;
end
RX_START:
begin
if (rx_tick)
begin
//next_rx_word = {rx_data_in, rx_word[7:1]}; // Shift right
next_rx_word = {rx_data_in, rx_word[8:1]}; // Shift right
next_rx_bit_count = rx_bit_count + 4'h1; // Count # of bits
//if (rx_bit_count == 4'h8)
if (rx_bit_count == 4'h9) // 8 bits + 1 bit odd parity
begin
next_rx_state = RX_STOP;
end
end
end
RX_STOP:
begin
if (rx_tick)
begin
if (~rx_data_in || (rx_word[8] != parity))
// Missing stop bit 1'b1 or incorrect parity
next_rx_state = RX_ERROR;
else
begin
next_rx_state = RX_IDLE;
next_rx_word_valid = 1'b1;
end
end
end
endcase
end
endmodule
|
`timescale 1ns / 1ps
/* Simple UART TX module (9600 baud rate)
*/
module myuart_tx # (
parameter BAUD_RATE = 9600
)
(
input clock,
input reset,
input enable,
output error,
input [7:0] data_in,
input tx_start,
output tx_ready,
output tx_data_out
);
localparam TX_IDLE = 0,
TX_START = 1,
TX_STOP = 2,
TX_ERROR = 3;
// Internal States
reg tx_bit;
reg [ 8: 0] tx_word;
reg [ 3: 0] tx_bit_count; // Count the number of bits sent
reg [ 1: 0] tx_state;
// Wires
reg [ 1: 0] next_tx_state;
reg next_tx_bit;
reg [ 3: 0] next_tx_bit_count;
reg [ 8: 0] next_tx_word;
wire tx_tick;
wire parity; // odd parity
// Output
assign tx_data_out = tx_bit;
assign tx_ready = (tx_state == TX_IDLE) ? 1'b1 : 1'b0;
assign error = (tx_state == TX_ERROR) ? 1'b1 : 1'b0;
assign parity = ~(data_in[0]^data_in[1]^data_in[2]^data_in[3]^data_in[4]^data_in[5]^data_in[6]^data_in[7]);
// Baud tick generator
baud_gen #(.BAUD_RATE(BAUD_RATE)) tx_tick_gen (
.clock (clock),
.reset (tx_start),
.start (tx_start),
.baud_tick (tx_tick));
// TX registers
always @(posedge clock)
begin
if (reset)
begin
tx_bit <= 1'b1;
tx_bit_count <= 4'h0;
tx_word <= 8'h00;
end
else if (enable)
begin
if (tx_start)
tx_word <= {parity, data_in};
else
tx_word <= next_tx_word;
tx_bit <= next_tx_bit;
tx_bit_count <= next_tx_bit_count;
end
end
// TX state machine
always @(posedge clock)
begin
if (reset)
tx_state <= TX_IDLE;
else if (enable)
tx_state <= next_tx_state;
end
always @(*)
begin
next_tx_state = tx_state;
next_tx_bit = tx_bit;
next_tx_bit_count = tx_bit_count;
next_tx_word = tx_word;
case (tx_state)
TX_IDLE:
begin
if (tx_start)
begin
next_tx_bit = 1'b0; // Start bit
next_tx_state = TX_START;
end
next_tx_bit_count = 4'h0;
end
TX_START:
begin
if (tx_start)
begin
next_tx_state = TX_ERROR;
end
else if (tx_tick)
begin
{next_tx_word, next_tx_bit} = {1'b1, tx_word}; // Right shift out the bits
next_tx_bit_count = tx_bit_count + 4'h1;
//if (tx_bit_count == 4'h8)
if (tx_bit_count == 4'h9) // 8 bits data + 1 bit parity
next_tx_state = TX_STOP;
end
end
TX_STOP:
begin
if (tx_tick)
next_tx_state = TX_IDLE;
end
endcase
end
endmodule
|
`timescale 1 ns/100 ps // time unit = 1ns; precision = 1/10 ns
/* Node = Router + (NPORTS-1) * FQs + TG
* A single network node with the host switch.
* 1 input interface (broadcast to all nodes) and 1 output interface (from the Router)
*
* Configuration chain:
* in -> Router -> TG -> (NPORTS-1) x FQ -> out
*
* RAM config chain:
* ram_config_in -> Router -> ram_config_out
*
* Stats chain:
* in -> TG -> out
*/
`include "const.v"
module Node (
clock,
reset,
enable,
stop_injection,
measure,
sim_time,
sim_time_tick,
error,
is_quiescent,
can_increment,
// Configuration and Stats interfaces
config_in_valid,
config_in,
config_out_valid,
config_out,
ram_config_in_valid,
ram_config_in,
ram_config_out_valid,
ram_config_out,
stats_shift,
stats_in,
stats_out,
// Flit interface
flit_in_valid,
flit_in,
nexthop_in,
flit_ack,
flit_out_valid,
flit_out,
nexthop_out,
dequeue,
// Credit interface
credit_in_valid,
credit_in,
credit_in_nexthop,
credit_ack,
credit_out_valid,
credit_out,
credit_out_nexthop,
credit_dequeue,
rtable_dest,
rtable_oport
);
`include "math.v"
`include "util.v"
parameter [`ADDR_WIDTH-1:0] HADDR = 0; // 8-bit global node ID
parameter NPORTS = 5; // Number of ports on the Router
parameter NVCS = 2;
localparam NINPUTS = NPORTS * NVCS;
localparam LOG_NPORTS = CLogB2(NPORTS-1);
localparam LOG_NVCS = CLogB2(NVCS-1);
// Global interfaces
input clock;
input reset;
input enable;
input stop_injection;
input measure;
input [`TS_WIDTH-1:0] sim_time;
input sim_time_tick;
output error;
output is_quiescent;
output can_increment;
// Configuration and Stats interfaces
input config_in_valid;
input [15: 0] config_in;
output config_out_valid;
output [15: 0] config_out;
input ram_config_in_valid;
input [15: 0] ram_config_in;
output ram_config_out_valid;
output [15: 0] ram_config_out;
input stats_shift;
input [15: 0] stats_in;
output [15: 0] stats_out;
// Flit interface
input flit_in_valid;
input [`FLIT_WIDTH-1:0] flit_in;
input [`A_FQID] nexthop_in;
output flit_ack;
output flit_out_valid;
output [`FLIT_WIDTH-1:0] flit_out;
output [`A_WIDTH-1:0] nexthop_out;
input dequeue;
// Credit interface
input credit_in_valid;
input [`CREDIT_WIDTH-1:0] credit_in;
input [`A_FQID] credit_in_nexthop;
output credit_ack;
output credit_out_valid;
output [`CREDIT_WIDTH-1:0] credit_out;
output [`A_WIDTH-1:0] credit_out_nexthop;
input credit_dequeue;
output [`ADDR_WIDTH-1:0] rtable_dest;
input [LOG_NPORTS-1:0] rtable_oport;
wire w_rt_error;
wire w_rt_quiescent;
wire w_rt_can_increment;
wire [NPORTS-1:0] w_port_error;
wire [NPORTS-1:0] w_port_quiescent;
wire [NPORTS-1:0] w_port_flit_ack;
wire [NPORTS-1:0] w_port_credit_ack;
wire [15: 0] w_port_config_in[NPORTS:0];
wire [NPORTS:0] w_port_config_in_valid;
// FQ/TG -> Router interface
wire [NINPUTS*`FLIT_WIDTH-1:0] w_rt_flit_in;
wire [NINPUTS-1:0] w_rt_flit_in_valid;
wire [NINPUTS-1:0] w_rt_flit_ack;
wire [NPORTS*`CREDIT_WIDTH-1:0] w_rt_credit_in;
wire [NPORTS-1:0] w_rt_credit_in_valid;
wire [NPORTS-1:0] w_rt_credit_ack;
// Output
assign error = w_rt_error | (|w_port_error);
assign is_quiescent = w_rt_quiescent & (&w_port_quiescent);
assign can_increment = w_rt_can_increment;
assign config_out_valid = w_port_config_in_valid[NPORTS];
assign config_out = w_port_config_in[NPORTS];
assign flit_ack = |w_port_flit_ack;
assign credit_ack = |w_port_credit_ack;
Router #(.HADDR(HADDR), .NPORTS(NPORTS)) rt (
.clock (clock),
.reset (reset),
.enable (enable),
.sim_time (sim_time),
.sim_time_tick (sim_time_tick),
.error (w_rt_error),
.is_quiescent (w_rt_quiescent),
.can_increment (w_rt_can_increment),
.ram_config_in (ram_config_in),
.ram_config_in_valid (ram_config_in_valid),
.ram_config_out (ram_config_out),
.ram_config_out_valid (ram_config_out_valid),
.config_in (config_in),
.config_in_valid (config_in_valid),
.config_out (w_port_config_in[0]),
.config_out_valid (w_port_config_in_valid[0]),
.flit_in (w_rt_flit_in),
.flit_in_valid (w_rt_flit_in_valid),
.flit_ack (w_rt_flit_ack),
.flit_out (flit_out),
.flit_out_valid (flit_out_valid),
.nexthop_out (nexthop_out),
.dequeue (dequeue),
.credit_in (w_rt_credit_in),
.credit_in_valid (w_rt_credit_in_valid),
.credit_ack (w_rt_credit_ack),
.credit_out (credit_out),
.credit_out_valid (credit_out_valid),
.credit_out_nexthop (credit_out_nexthop),
.credit_dequeue (credit_dequeue),
.rtable_dest (rtable_dest),
.rtable_oport (rtable_oport));
// Host TG is on Port 0 (no credit interface for now)
assign w_port_credit_ack[0] = 1'b1; // TG always acks Router's credit
TrafficGen #(.HADDR({HADDR, 3'b000}), .LOG_NVCS(LOG_NVCS)) tg (
.clock (clock),
.reset (reset),
.enable (enable),
.stop_injection (stop_injection),
.sim_time (sim_time),
.error (w_port_error[0]),
.measure (measure),
.is_quiescent (w_port_quiescent[0]),
.config_in (w_port_config_in[0]),
.config_in_valid (w_port_config_in_valid[0]),
.config_out (w_port_config_in[1]),
.config_out_valid (w_port_config_in_valid[1]),
.stats_shift (stats_shift),
.stats_in (stats_in),
.stats_out (stats_out),
// From DestPart
.flit_in (flit_in),
.flit_in_valid (flit_in_valid),
.nexthop_in (nexthop_in),
.flit_ack (w_port_flit_ack[0]),
.flit_full (),
// To Router
.flit_out (w_rt_flit_in[NVCS*`FLIT_WIDTH-1:0]),
.flit_out_valid (w_rt_flit_in_valid[NVCS-1:0]),
.dequeue (w_rt_flit_ack[NVCS-1:0]),
.credit_out (w_rt_credit_in[`CREDIT_WIDTH-1:0]),
.credit_out_valid (w_rt_credit_in_valid[0]));
// Port 1..N
genvar i;
generate
for (i = 1; i < NPORTS; i = i + 1)
begin : port
FlitQueue #(.NPID({HADDR, 3'b000}|i), .LOG_NVCS(LOG_NVCS)) fq (
.clock (clock),
.reset (reset),
.enable (enable),
.sim_time (sim_time),
.error (w_port_error[i]),
.is_quiescent (w_port_quiescent[i]),
.config_in (w_port_config_in[i]),
.config_in_valid (w_port_config_in_valid[i]),
.config_out (w_port_config_in[i+1]),
.config_out_valid (w_port_config_in_valid[i+1]),
// DestPart facing interface
.flit_full (),
.flit_in (flit_in),
.flit_in_valid (flit_in_valid),
.nexthop_in (nexthop_in),
.flit_ack (w_port_flit_ack[i]),
.credit_full (),
.credit_in (credit_in),
.credit_in_valid (credit_in_valid),
.credit_in_nexthop (credit_in_nexthop),
.credit_ack (w_port_credit_ack[i]),
// Router Port j interface
.flit_out (w_rt_flit_in[(i+1)*NVCS*`FLIT_WIDTH-1:i*NVCS*`FLIT_WIDTH]),
.flit_out_valid (w_rt_flit_in_valid[(i+1)*NVCS-1:i*NVCS]),
.dequeue (w_rt_flit_ack[(i+1)*NVCS-1:i*NVCS]),
.credit_out (w_rt_credit_in[(i+1)*`CREDIT_WIDTH-1:i*`CREDIT_WIDTH]),
.credit_out_valid (w_rt_credit_in_valid[i]),
.credit_dequeue (w_rt_credit_ack[i]));
end
endgenerate
endmodule
|
`timescale 1ns / 1ps
/* one_hot_detect.v
*
* Drives 0 if there are more than one 1s in the input and 1 otherwise
*/
module one_hot_detect (
in,
is_one_hot
);
parameter WIDTH = 10;
input [WIDTH-1: 0] in;
output is_one_hot;
reg out;
assign is_one_hot = out;
// For now this only works for 10-bit
// psl ERROR_unsupported_1hot_detect_size: assert always {WIDTH == 10};
always @(*)
begin
case (in)
10'b00_0000_0001: out = 1'b1;
10'b00_0000_0010: out = 1'b1;
10'b00_0000_0100: out = 1'b1;
10'b00_0000_1000: out = 1'b1;
10'b00_0001_0000: out = 1'b1;
10'b00_0010_0000: out = 1'b1;
10'b00_0100_0000: out = 1'b1;
10'b00_1000_0000: out = 1'b1;
10'b01_0000_0000: out = 1'b1;
10'b10_0000_0000: out = 1'b1;
10'b00_0000_0000: out = 1'b1;
default: out = 1'b0;
endcase
end
endmodule
|
`timescale 1ns / 1ps
/* Packed FIFO
* Multiple FIFO packed into 1 block RAM
* 2-cycle latency
*/
module PackedFIFO #(
parameter logN = 2,
parameter WIDTH = 36,
parameter logDEPTH = 6
)
(
input clock,
input reset,
input [logN-1:0] wid,
input [logN-1:0] rid,
input write,
input read,
input [WIDTH-1:0] data_in,
output [(1<<logN)*WIDTH-1:0] data_out,
output [(1<<logN)-1:0] full,
output [(1<<logN)-1:0] empty,
output [(1<<logN)-1:0] has_data,
output error
);
localparam N = 1<<logN;
localparam DEPTH = 1 << logDEPTH;
reg r_read_busy;
reg [N*WIDTH-1:0] r_dout;
reg [N-1:0] r_dout_valid;
reg [N-1:0] r_load_dout;
wire [N-1:0] w_read_request;
wire [N-1:0] w_write_request;
wire [N-1:0] w_wid_decoded;
wire [N-1:0] w_rid_decoded;
reg [N-1:0] w_fifo_enable;
reg [N-1:0] w_fifo_write;
reg [N-1:0] w_fifo_read;
wire [N-1:0] w_fifo_full;
wire [N-1:0] w_fifo_empty;
wire [N-1:0] w_fifo_wen;
wire [N*logDEPTH-1:0] w_fifo_waddr;
wire [N*logDEPTH-1:0] w_fifo_raddr;
reg [N-1:0] w_load_din; // Tell r_dout[i] to load the value of data_in
reg [N-1:0] w_load_dout; // Tell r_dout[i] to load the value of ram_dout
wire w_ram_wen;
wire [logN+logDEPTH-1:0] w_ram_waddr;
wire [logN+logDEPTH-1:0] w_ram_raddr;
wire [WIDTH-1:0] w_ram_dout;
// Output
assign data_out = r_dout;
assign full = w_fifo_full;
assign empty = w_fifo_empty & (~r_dout_valid);
assign error = 1'b1;
decoder_N #(.SIZE(N)) wid_decode (
.encoded (wid),
.decoded (w_wid_decoded));
decoder_N #(.SIZE(N)) rid_decode (
.encoded (rid),
.decoded (w_rid_decoded));
assign w_write_request = (write == 1'b1) ? w_wid_decoded : 0;
assign w_read_request = (read == 1'b1 && r_read_busy == 1'b0) ? w_rid_decoded : 0;
// FIFO controls
genvar i;
generate
for (i = 0; i < N; i = i + 1)
begin : fifo
// FIFO control
RAMFIFO_ctrl_lfsr #(.LOG_DEP(logDEPTH)) ctrl (
.clock (clock),
.reset (reset),
.enable (w_fifo_enable[i]),
.write (w_fifo_write[i]),
.read (w_fifo_read[i]),
.full (w_fifo_full[i]),
.empty (w_fifo_empty[i]),
.ram_wen (w_fifo_wen[i]),
.ram_waddr (w_fifo_waddr[(i+1)*logDEPTH-1:i*logDEPTH]),
.ram_raddr (w_fifo_raddr[(i+1)*logDEPTH-1:i*logDEPTH]),
.ram_raddr_next ());
always @(*)
begin
w_fifo_read[i] = 0;
w_fifo_write[i] = 0;
w_fifo_enable[i] = 0;
w_load_din[i] = 0;
w_load_dout[i] = 0;
if (w_read_request[i] & ~w_write_request[i])
begin
// Read from FIFO and no write
if (~w_fifo_empty[i])
begin
w_fifo_enable[i] = 1;
w_fifo_read[i] = 1;
w_load_dout[i] = 1;
end
end
else if (~w_read_request[i] & w_write_request[i])
begin
// Write to FIFO and no read
if (~r_dout_valid[i])
begin
// dout is invalid => FIFO is empty. Write to dout directly
w_load_din[i] = 1;
end
else
begin
// Something is already in dout. Write to FIFO.
w_fifo_enable[i] = 1;
w_fifo_write[i] = 1;
end
end
else if (w_read_request[i] & w_write_request[i])
begin
// Reading and writing simultaneously
if (w_fifo_empty[i])
begin
// FIFO in RAM is empty and dout is being read. Write data_in to dout
w_load_din[i] = 1;
end
else
begin
// Write to FIFO and read from FIFO
w_fifo_enable[i] = 1;
w_fifo_write[i] = 1;
w_fifo_read[i] = 1;
w_load_dout[i] = 1;
end
end
end
// Output register
assign has_data[i] = (r_read_busy & r_load_dout[i]) ? 0 : ~empty[i];
always @(posedge clock)
begin
if (reset)
r_dout[(i+1)*WIDTH-1:i*WIDTH] <= 0;
else if (w_load_din[i])
r_dout[(i+1)*WIDTH-1:i*WIDTH] <= data_in;
else if (r_load_dout[i])
r_dout[(i+1)*WIDTH-1:i*WIDTH] <= w_ram_dout;
end
always @(posedge clock)
begin
if (reset)
r_dout_valid[i] <= 1'b0;
else if (w_load_din[i] | w_load_dout[i])
r_dout_valid[i] <= 1'b1;
else if (w_read_request[i] & ~w_load_din[i] & ~w_load_dout[i])
r_dout_valid[i] <= 1'b0;
end
always @(posedge clock)
begin
if (reset)
r_load_dout[i] <= 0;
else
r_load_dout[i] <= w_load_dout[i];
end
end
endgenerate
always @(posedge clock)
begin
if (reset)
r_read_busy <= 0;
else if (read == 1 && w_load_dout != 0)
// Allow 1 cycle to load data from RAM
r_read_busy <= 1;
else if (r_read_busy == 1)
r_read_busy <= 0;
end
// Block RAM
DualBRAM #(.WIDTH(WIDTH), .LOG_DEP(logN+logDEPTH)) ram (
.clock (clock),
.wen (w_ram_wen),
.waddr (w_ram_waddr),
.raddr (w_ram_raddr),
.din (data_in),
.dout (w_ram_dout),
.wdout ());
assign w_ram_waddr[logDEPTH+logN-1:logDEPTH] = wid;
mux_Nto1 #(.WIDTH(logDEPTH), .SIZE(N)) waddr_mux (
.in (w_fifo_waddr),
.sel (wid),
.out (w_ram_waddr[logDEPTH-1:0]));
assign w_ram_raddr[logDEPTH+logN-1:logDEPTH] = rid;
mux_Nto1 #(.WIDTH(logDEPTH), .SIZE(N)) raddr_mux (
.in (w_fifo_raddr),
.sel (rid),
.out (w_ram_raddr[logDEPTH-1:0]));
assign w_ram_wen = |w_fifo_wen;
endmodule
|
`timescale 1ns / 1ps
/* Packet Buffer
*
* Buffer for packet descriptors before they are injected to the corresponding
* PacketPlayer unit. Packets are stored in FIFO order for each PP. The buffer
* address spaces is divided statically between the PPs.
*
* Parameter:
* PID Partition ID for this buffer (for now set to 3 bits)
* N Number of PPs that share this buffer
* WIDTH Width of the packet descriptor
* K Number of packet buffer space per PP (should be a power of 2)
*
* Interface:
* in_valid I Host-facing
* in_packet [W-1:0] I
* in_ack O
*
* rd_select [N-1:0] I PP/DART-facing
* rd_packet [W-1:0] O
* rd_ready [N-1:0] O
*/
`include "const.v"
module PacketBuffer (
clock,
reset,
enable,
// Host-facing interface
in_valid,
in_packet,
in_ack,
// PP/DART-facing
rd_select,
rd_packet,
rd_ready
);
`include "math.v"
parameter [2:0] PID = 0;
parameter N = 4; // # of TGs in this partition
parameter WIDTH = 32;
parameter K = 128; // # of entries per TG
parameter logPBPARTS = 3; // log(# of PlaybackBuffer Partitions globally)
localparam logN = CLogB2(N-1);
localparam logK = CLogB2(K-1);
localparam logBUF = logN + logK;
input clock;
input reset;
input enable;
input in_valid;
input [WIDTH-1:0] in_packet;
output in_ack;
input [N-1:0] rd_select;
output [WIDTH-1:0] rd_packet;
output [N-1:0] rd_ready;
// FIFO controls
wire [logK-1:0] w_fifo_waddr;
wire [logK-1:0] w_fifo_raddr;
wire w_fifo_wen;
wire [N*logK-1:0] w_fifo_waddr_all;
wire [N*logK-1:0] w_fifo_raddr_all;
wire [N-1:0] w_fifo_empty_all;
wire [N-1:0] w_fifo_wen_all;
wire [logN-1:0] w_fifo_wid;
wire [logN-1:0] w_fifo_rid;
wire [N-1:0] w_fifo_wid_decoded;
wire [N-1:0] w_fifo_rid_decoded;
// Big buffer for the packets
wire w_ram_wen;
wire [logBUF-1:0] w_ram_waddr;
wire [logBUF-1:0] w_ram_raddr;
wire [WIDTH-1:0] w_ram_dout;
wire [7:0] w_in_packet_src;
// Output
assign in_ack = w_fifo_wen;
assign rd_packet = w_ram_dout;
assign rd_ready = ~w_fifo_empty_all;
assign w_in_packet_src = in_packet[`P_SRC];
assign w_ram_wen = ((w_in_packet_src[logN+logPBPARTS:logN] == PID) && (enable == 1'b1) && (in_valid == 1'b1)) ? 1'b1 : 1'b0;
// Context-selection logic
assign w_fifo_wid = w_in_packet_src[logN-1:0]; // Incoming packet's Node ID selects write context
decoder_N #(.SIZE(N)) wid_decode (
.encoded (w_fifo_wid),
.decoded (w_fifo_wid_decoded));
// Controller read Node ID selects read context
encoder_N #(.SIZE(N)) rid_encode (
.decoded (rd_select),
.encoded (w_fifo_rid),
.valid ());
assign w_fifo_rid_decoded = rd_select;
// FIFO controllers
genvar i;
generate
for (i = 0; i < N; i = i + 1)
begin : ctrl
RAMFIFO_ctrl_lfsr #(.LOG_DEP(logK)) candy (
.clock (clock),
.reset (reset),
.enable (enable),
.write (w_fifo_wid_decoded[i] & w_ram_wen),
.read (w_fifo_rid_decoded),
.full (),
.empty (w_fifo_empty_all[i]),
.ram_wen (w_fifo_wen_all[i]), // FIFO control indicate if really should write
.ram_waddr (w_fifo_waddr_all[(i+1)*logK-1:i*logK]),
.ram_raddr (w_fifo_raddr_all[(i+1)*logK-1:i*logK]),
.ram_raddr_next ());
end
endgenerate
mux_Nto1 #(.WIDTH(logK), .SIZE(N)) fifo_waddr_mux (
.in (w_fifo_waddr_all),
.sel (w_fifo_wid),
.out (w_fifo_waddr));
mux_Nto1 #(.WIDTH(logK), .SIZE(N)) fifo_raddr_mux (
.in (w_fifo_raddr_all),
.sel (w_fifo_rid),
.out (w_fifo_raddr));
assign w_fifo_wen = |w_fifo_wen_all; // By design only 1 of the FIFO will allow write at a time
// Big buffer
assign w_ram_waddr = {w_fifo_wid, w_fifo_waddr};
assign w_ram_raddr = {w_fifo_rid, w_fifo_raddr};
DualBRAM #(.WIDTH(WIDTH), .LOG_DEP(logBUF)) buffer (
.clock (clock),
.wen (w_fifo_wen),
.waddr (w_ram_waddr),
.raddr (w_ram_raddr),
.din (in_packet),
.dout (w_ram_dout),
.wdout ());
endmodule
|
`timescale 1ns / 1ps
/* Packet Playback Control
*
* Input:
* ready [N-1:0]
* request [N-1:0]
*
* Output:
* select [N-1:0] Select is always valid
*
* State:
* ~Round-robin priority
*/
module PacketPBControl #(
parameter N = 4
)
(
input clock,
input reset,
input enable,
input [N-1:0] ready,
input [N-1:0] request,
output [N-1:0] select
);
`include "math.v"
reg [N-1:0] r_prio;
wire [N-1:0] w_available;
wire [N-1:0] w_select;
// Output
assign select = w_select;
// Only those TGs that are requesting a new packet and also have a new
// packet available can be chosen from
assign w_available = (enable == 1'b1) ? (ready & request & r_prio) : {(N){1'b0}};
// Select a node according to the priority
rr_prio_x4 rr_select (
.ready (w_available),
.prio (r_prio),
.select (w_select));
// Update the priority so the selected node has the lowest priority in next round
always @(posedge clock)
begin
if (reset)
r_prio <= 1;
else if (|w_select)
r_prio <= {w_select[N-2:0], w_select[N-1]};
end
endmodule
|
`timescale 1ns / 1ps
/* PacketPlayer.v
* Receives packet descriptor from PacketPBControl and injects flits into the network.
* Contains the injection and ejection queues.
*/
`include "const.v"
module PacketPlayer #(
parameter [`A_WIDTH-1:0] HADDR = 0,
parameter NVCS = 2
)
(
// Global interface
input clock,
input reset,
input enable,
input [`TS_WIDTH-1:0] sim_time,
output error,
output is_quiescent,
// Config interface
input [15:0] config_in,
input config_in_valid,
output [15:0] config_out,
output config_out_valid,
// Stats interface
input stats_shift,
input [15:0] stats_in,
output [15:0] stats_out,
// PacketPBControl interface
input [31:0] packet_in,
input packet_in_valid,
output packet_request,
// DestPart interface
input [`FLIT_WIDTH-1:0] flit_in,
input flit_in_valid,
input [`A_FQID] nexthop_in,
output flit_ack,
// SourcePart interface
output [NVCS*`FLIT_WIDTH-1:0] flit_out,
output [NVCS-1:0] flit_out_valid,
input [NVCS-1:0] dequeue,
// SourcePart credit interface
output [`CREDIT_WIDTH-1:0] credit_out,
output credit_out_valid
);
`include "math.v"
localparam logNVCS = CLogB2(NVCS-1);
// Internal states
reg [15: 0] stats_nreceived;
reg [63: 0] stats_sum_latency;
reg r_error;
reg [NVCS-1: 0] r_prio;
// Wires
wire w_recv_flit;
wire w_iq_error;
wire w_iq_is_quiescent;
wire w_oq_error;
wire w_oq_is_quiescent;
wire [15: 0] w_iq_config_out;
wire w_iq_config_out_valid;
wire [15: 0] w_oq_config_out;
wire w_oq_config_out_valid;
wire [NVCS*`FLIT_WIDTH-1:0] w_iq_flit_out;
wire [NVCS-1:0] w_iq_flit_out_valid;
wire [NVCS*`FLIT_WIDTH-1:0] w_oq_flit_out;
wire [NVCS-1:0] w_oq_flit_out_valid;
wire [NVCS-1:0] w_oq_flit_full;
wire [NVCS-1:0] w_oq_flit_dequeue;
wire [`FLIT_WIDTH-1:0] w_tg_flit_out;
wire w_tg_flit_out_valid;
wire [NVCS-1: 0] w_iq_flit_dequeue;
wire [`TS_WIDTH-1:0] w_recv_flit_latency;
wire [`FLIT_WIDTH-1:0] w_received_flit;
// Output
assign error = r_error;
assign is_quiescent = w_iq_is_quiescent & w_oq_is_quiescent;
assign config_out = w_oq_config_out;
assign config_out_valid = w_oq_config_out_valid;
assign stats_out = stats_nreceived;
assign flit_out = w_oq_flit_out;
assign flit_out_valid = w_oq_flit_out_valid;
assign credit_out = {flit_in[`F_OVC], sim_time};
assign credit_out_valid = flit_in_valid;
// Simulation stuff
`ifdef SIMULATION
always @(posedge clock)
begin
if (dequeue)
$display ("T %x TG (%x) sends flit %x", sim_time, HADDR, flit_out);
if (w_recv_flit)
$display ("T %x TG (%x) recvs flit %x", sim_time, HADDR, w_received_flit);
if (enable & error)
$display ("ATTENTION: TG (%x) has an error", HADDR);
end
`endif
// Error
always @(posedge clock)
begin
if (reset)
r_error <= 1'b0;
else if (enable)
r_error <= w_iq_error | w_oq_error | (w_recv_flit == 1'b1 && w_received_flit[`F_DEST] != HADDR);
end
// Stats counters
assign w_recv_flit = |w_iq_flit_dequeue;
assign w_recv_flit_latency = w_received_flit[`F_TS] - w_received_flit[`F_SRC_INJ];
always @(posedge clock)
begin
if (reset)
begin
stats_nreceived <= 0;
stats_sum_latency <= 0;
end
else if (stats_shift)
begin
stats_sum_latency <= {stats_in, stats_sum_latency[63:16]};
stats_nreceived <= stats_sum_latency[15:0];
end
else if (w_recv_flit & w_received_flit[`F_TAIL] & w_received_flit[`F_MEASURE])
begin
// Collect stats on tail flit injected during measurement
stats_nreceived <= stats_nreceived + 1;
stats_sum_latency <= stats_sum_latency + {w_recv_flit_latency[`TS_WIDTH-1], {(64-`TS_WIDTH){1'b0}}, w_recv_flit_latency[`TS_WIDTH-2:0]};
end
end
// Input queues
FlitQueue_NC #(.NPID(HADDR[`A_FQID]), .LOG_NVCS(logNVCS)) iq (
.clock (clock),
.reset (reset),
.enable (enable),
.sim_time (sim_time),
.error (w_iq_error),
.is_quiescent (w_iq_is_quiescent),
.latency (),
.config_in (config_in),
.config_in_valid (config_in_valid),
.config_out (w_iq_config_out),
.config_out_valid (w_iq_config_out_valid),
.flit_full (),
.flit_in_valid (flit_in_valid),
.flit_in (flit_in),
.nexthop_in (nexthop_in),
.flit_ack (flit_ack),
.flit_out (w_iq_flit_out),
.flit_out_valid (w_iq_flit_out_valid),
.dequeue (w_iq_flit_dequeue));
// Round-robin priority encoder to figure out which input VC to dequeue
rr_prio #(.N(NVCS)) iq_sel (
.ready (w_iq_flit_out_valid),
.prio (r_prio),
.select (w_iq_flit_dequeue));
always @(posedge clock)
begin
if (reset)
r_prio <= 1;
else if (enable)
r_prio <= {r_prio[NVCS-2:0], r_prio[NVCS-1]};
end
// Select received flit
mux_Nto1_decoded #(.WIDTH(`FLIT_WIDTH), .SIZE(NVCS)) iq_flit_mux (
.in (w_iq_flit_out),
.sel (w_iq_flit_dequeue),
.out (w_received_flit));
// Packet injection process
TGPacketFSM #(.HADDR(HADDR), .NVCS(NVCS)) tg (
.clock (clock),
.reset (reset),
.enable (enable),
.sim_time (sim_time),
.packet_in (packet_in),
.packet_in_valid (packet_in_valid),
.packet_request (packet_request),
.obuf_full (w_oq_flit_full),
.flit_out (w_tg_flit_out),
.flit_out_valid (w_tg_flit_out_valid));
wire [NVCS*`FLIT_WIDTH-1:0] w_oq_flit_in;
wire [NVCS-1:0] w_oq_flit_in_valid;
assign w_oq_flit_in_valid = (w_tg_flit_out[0] == 1'b1) ? {1'b0, w_tg_flit_out_valid} : {w_tg_flit_out_valid, 1'b0};
assign w_oq_flit_in = {w_tg_flit_out, w_tg_flit_out};
// Output queue
assign w_oq_flit_dequeue = dequeue;
FlitQueue_NC #(.NPID(HADDR[`A_FQID]), .LOG_NVCS(logNVCS)) oq (
.clock (clock),
.reset (reset),
.enable (enable),
.sim_time (sim_time),
.error (w_oq_error),
.is_quiescent (w_oq_is_quiescent),
.latency (),
.config_in (w_iq_config_out),
.config_in_valid (w_iq_config_out_valid),
.config_out (w_oq_config_out),
.config_out_valid (w_oq_config_out_valid),
.flit_full (w_oq_flit_full),
.flit_in_valid (w_tg_flit_out_valid),
.flit_in (w_tg_flit_out),
.nexthop_in (HADDR[`A_FQID]),
.flit_ack (),
.flit_out (w_oq_flit_out),
.flit_out_valid (w_oq_flit_out_valid),
.dequeue (w_oq_flit_dequeue));
endmodule
|
`timescale 1 ns/100 ps // time unit = 1ns; precision = 1/10 ns
/* Partition of Nodes.
*
* Configuration chain:
* config_in -> 2 x 2 x Node -> config_out
*
* RAM config chain:
* in -> 2 x 2 x Routers -> 2 x RoutingTable -> out
*
* Stats chain:
* in -> 2 x 2 x node -> out
*/
`include "const.v"
module Partition (
clock,
reset,
enable,
stop_injection,
measure,
sim_time,
sim_time_tick,
error,
is_quiescent,
can_increment,
// Configuration and Stats interfaces
config_in_valid,
config_in,
config_out_valid,
config_out,
ram_config_in_valid,
ram_config_in,
ram_config_out_valid,
ram_config_out,
stats_shift,
stats_in,
stats_out,
// ICSourcePart interface (x2)
fsp_vec_valid,
fsp_vec_valid_urgent,
fsp_vec_data,
fsp_vec_nexthop,
fsp_vec_dequeue,
csp_vec_valid,
csp_vec_valid_urgent,
csp_vec_data,
csp_vec_nexthop,
csp_vec_dequeue,
// ICDestPart interface 0
fdp_valid,
fdp_data,
fdp_nexthop,
fdp_ack,
cdp_valid,
cdp_data,
cdp_nexthop,
cdp_ack
);
`include "math.v"
`include "util.v"
parameter [3:0] DPID = 1; // 4-bit DestPart ID
parameter N = 2; // Number of Nodes in this Partition
parameter NPORTS = 5;
localparam NTBL = (N+1)/2; // Number of RoutingTables needed
localparam LOG_NPORTS = CLogB2(NPORTS-1);
// Global interfaces
input clock;
input reset;
input enable;
input stop_injection;
input measure;
input [`TS_WIDTH-1:0] sim_time;
input sim_time_tick;
output error;
output is_quiescent;
output can_increment;
// Configuration and Stats interfaces
input config_in_valid;
input [15: 0] config_in;
output config_out_valid;
output [15: 0] config_out;
input ram_config_in_valid;
input [15: 0] ram_config_in;
output ram_config_out_valid;
output [15: 0] ram_config_out;
input stats_shift;
input [15: 0] stats_in;
output [15: 0] stats_out;
// ICSourcePart interface (x2)
output [N-1: 0] fsp_vec_valid;
output [N-1: 0] fsp_vec_valid_urgent;
output [N*`FLIT_WIDTH-1:0] fsp_vec_data;
output [N*`A_WIDTH-1:0] fsp_vec_nexthop;
input [N-1: 0] fsp_vec_dequeue;
output [N-1: 0] csp_vec_valid;
output [N-1: 0] csp_vec_valid_urgent;
output [N*`CREDIT_WIDTH-1:0] csp_vec_data;
output [N*`A_WIDTH-1:0] csp_vec_nexthop;
input [N-1:0] csp_vec_dequeue;
// ICDestPart interface 0
input fdp_valid;
input [`FLIT_WIDTH-1:0] fdp_data;
input [`A_FQID] fdp_nexthop;
output fdp_ack;
input cdp_valid;
input [`CREDIT_WIDTH-1:0] cdp_data;
input [`A_FQID] cdp_nexthop;
output cdp_ack;
wire [N-1:0] rt_error;
wire [N-1:0] rt_quiescent;
wire [N-1:0] rt_can_increment;
wire [15:0] rt_config_in [N:0];
wire [N:0] rt_config_in_valid;
wire [15:0] rt_ram_config_in [N:0];
wire [N:0] rt_ram_config_in_valid;
wire [15:0] rtable_ram_config_in [NTBL:0];
wire [NTBL:0] rtable_ram_config_in_valid;
wire [15:0] rt_stats_in [N:0];
wire [N-1:0] rt_flit_ack;
wire [N-1:0] rt_credit_ack;
wire [`ADDR_WIDTH-1:0] rtable_dest [N-1:0];
wire [LOG_NPORTS-1:0] rtable_oport [N-1:0];
assign error = |rt_error;
assign is_quiescent = &rt_quiescent;
assign can_increment = &rt_can_increment;
assign config_out_valid = rt_config_in_valid[N];
assign config_out = rt_config_in[N];
assign ram_config_out_valid = rtable_ram_config_in_valid[NTBL];
assign ram_config_out = rtable_ram_config_in[NTBL];
assign stats_out = rt_stats_in[N];
assign fdp_ack = |rt_flit_ack;
assign cdp_ack = |rt_credit_ack;
assign rt_config_in_valid[0] = config_in_valid;
assign rt_config_in[0] = config_in;
assign rt_ram_config_in_valid[0] = ram_config_in_valid;
assign rt_ram_config_in[0] = ram_config_in;
assign rt_stats_in[0] = stats_in;
genvar i;
generate
for (i = 0; i < N; i = i + 1)
begin : node
wire [`FLIT_WIDTH-1:0] w_flit_out;
wire [`CREDIT_WIDTH-1:0] w_credit_out;
wire [`TS_WIDTH-1:0] w_flit_ts;
wire [`TS_WIDTH-1:0] w_credit_ts;
assign w_flit_ts = flit_ts (w_flit_out);
assign fsp_vec_data[(i+1)*`FLIT_WIDTH-1:i*`FLIT_WIDTH] = w_flit_out;
assign fsp_vec_valid_urgent[i] = (w_flit_ts[2:0] == sim_time[2:0]) ? fsp_vec_valid[i] : 1'b0;
assign w_credit_ts = credit_ts (w_credit_out);
assign csp_vec_data[(i+1)*`CREDIT_WIDTH-1:i*`CREDIT_WIDTH] = w_credit_out;
assign csp_vec_valid_urgent[i] = (w_credit_ts[2:0] == sim_time[2:0]) ? csp_vec_valid[i] : 1'b0;
Node #(.HADDR({DPID, 4'h0}|i), .NPORTS(NPORTS)) n (
.clock (clock),
.reset (reset),
.enable (enable),
.stop_injection (stop_injection),
.measure (measure),
.sim_time (sim_time),
.sim_time_tick (sim_time_tick),
.error (rt_error[i]),
.is_quiescent (rt_quiescent[i]),
.can_increment (rt_can_increment[i]),
.config_in_valid (rt_config_in_valid[i]),
.config_in (rt_config_in[i]),
.config_out_valid (rt_config_in_valid[i+1]),
.config_out (rt_config_in[i+1]),
.ram_config_in_valid (rt_ram_config_in_valid[i]),
.ram_config_in (rt_ram_config_in[i]),
.ram_config_out_valid (rt_ram_config_in_valid[i+1]),
.ram_config_out (rt_ram_config_in[i+1]),
.stats_shift (stats_shift),
.stats_in (rt_stats_in[i]),
.stats_out (rt_stats_in[i+1]),
// DestPart interface
.flit_in_valid (fdp_valid),
.flit_in (fdp_data),
.nexthop_in (fdp_nexthop),
.flit_ack (rt_flit_ack[i]),
.credit_in_valid (cdp_valid),
.credit_in (cdp_data),
.credit_in_nexthop (cdp_nexthop),
.credit_ack (rt_credit_ack[i]),
// SourcePart interface
.flit_out_valid (fsp_vec_valid[i]),
.flit_out (w_flit_out),
.nexthop_out (fsp_vec_nexthop[(i+1)*`A_WIDTH-1:i*`A_WIDTH]),
.dequeue (fsp_vec_dequeue[i]),
.credit_out_valid (csp_vec_valid[i]),
.credit_out (w_credit_out),
.credit_out_nexthop (csp_vec_nexthop[(i+1)*`A_WIDTH-1:i*`A_WIDTH]),
.credit_dequeue (csp_vec_dequeue[i]),
// RoutingTable interface
.rtable_dest (rtable_dest[i]),
.rtable_oport (rtable_oport[i]));
end
endgenerate
// Every two nodes share a RoutingTable.
// Multi-context nodes can use multi-context routing tables (not implemented now TODO)
assign rtable_ram_config_in[0] = rt_ram_config_in[N];
assign rtable_ram_config_in_valid[0] = rt_ram_config_in_valid[N];
generate
for (i = 0; i < N; i = i + 2)
begin : rtable
wire [5:0] w_temp_a;
wire [5:0] w_temp_b;
if (i + 1 < N)
begin
RoutingTable_single rt (
.clock (clock),
.reset (reset),
.enable (enable | rtable_ram_config_in_valid[i/2]),
.ram_config_in (rtable_ram_config_in[i/2]),
.ram_config_in_valid (rtable_ram_config_in_valid[i/2]),
.ram_config_out_valid (rtable_ram_config_in_valid[i/2+1]),
.ram_config_out (rtable_ram_config_in[i/2+1]),
.dest_ina (rtable_dest[i]),
.nexthop_outa ({w_temp_a, rtable_oport[i]}),
.dest_inb (rtable_dest[i+1]),
.nexthop_outb ({w_temp_b, rtable_oport[i+1]}));
end
else
begin
RoutingTable_single rt (
.clock (clock),
.reset (reset),
.enable (enable | rtable_ram_config_in_valid[i/2]),
.ram_config_in (rtable_ram_config_in[i/2]),
.ram_config_in_valid (rtable_ram_config_in_valid[i/2]),
.ram_config_out_valid (rtable_ram_config_in_valid[i/2+1]),
.ram_config_out (rtable_ram_config_in[i/2+1]),
.dest_ina (rtable_dest[i]),
.nexthop_outa ({w_temp_a, rtable_oport[i]}),
.dest_inb ({(`ADDR_WIDTH){1'b0}}),
.nexthop_outb ());
end
end
endgenerate
endmodule
|
`timescale 1ns / 1ps
/* RAMFIFO_ctrl_counter.v
* Counter-based control for RAM FIFO
*/
module RAMFIFO_ctrl_counter (
clock,
reset,
enable,
write,
read,
full,
empty,
ram_wen,
ram_waddr,
ram_raddr,
ram_raddr_next
);
parameter WIDTH = 36;
parameter LOG_DEP = 6;
localparam DEPTH = 1 << LOG_DEP;
input clock;
input reset;
input enable;
input write;
input read;
output full;
output empty;
output ram_wen;
output [LOG_DEP-1:0] ram_waddr;
output [LOG_DEP-1:0] ram_raddr;
output [LOG_DEP-1:0] ram_raddr_next;
// Control signals
wire valid_write;
wire valid_read;
wire next_head_is_tail;
wire [LOG_DEP-1:0] next_head;
wire [LOG_DEP-1:0] next_tail;
reg empty;
reg [LOG_DEP-1:0] tail;
reg [LOG_DEP-1:0] head;
// Output
assign full = (head == tail && empty == 1'b0) ? 1'b1 : 1'b0;
assign ram_wen = valid_write;
assign ram_waddr = tail;
assign ram_raddr = head;
assign ram_raddr_next = next_head;
// Valid write, high when valid to write data to the FIFO
assign valid_write = enable & ((read & write) | (write & ~full));
assign valid_read = enable & (read & ~empty);
// Empty state
always @(posedge clock)
begin
if (reset)
empty <= 1'b1;
else if (enable)
begin
if (empty & write)
empty <= 1'b0;
else if (read & ~write & next_head_is_tail)
empty <= 1'b1;
end
end
// W R Action
// 0 0 head <= head, tail <= tail
// 0 1 head <= head + 1, tail <= tail
// 1 0 head <= head, tail = tail + 1
// 1 1 head <= head + 1, tail <= tail + 1
always @(posedge clock)
begin
if (reset)
begin
head <= {(LOG_DEP){1'b0}};
tail <= {(LOG_DEP){1'b0}};
end
else
begin
if (valid_read) head <= next_head;
if (valid_write) tail <= next_tail;
end
end
assign next_head_is_tail = (next_head == tail) ? 1'b1 : 1'b0;
assign next_head = head + 1;
assign next_tail = tail + 1;
endmodule
|
`timescale 1ns / 1ps
/* RAMFIFO_ctrl_lfsr.v
* LFSR-based control for RAMFIFO
*/
module RAMFIFO_ctrl_lfsr (
clock,
reset,
enable,
write,
read,
full,
empty,
ram_wen,
ram_waddr,
ram_raddr,
ram_raddr_next
);
parameter LOG_DEP = 6;
localparam DEPTH = 1 << LOG_DEP;
input clock;
input reset;
input enable;
input write;
input read;
output full;
output empty;
output ram_wen;
output [LOG_DEP-1:0] ram_waddr;
output [LOG_DEP-1:0] ram_raddr;
output [LOG_DEP-1:0] ram_raddr_next;
// Control signals
wire valid_write;
wire valid_read;
wire next_head_is_tail;
wire [LOG_DEP-1:0] next_head;
wire [LOG_DEP-1:0] head;
wire [LOG_DEP-1:0] tail;
reg empty;
// Output
assign full = (head == tail && empty == 1'b0) ? 1'b1 : 1'b0;
assign ram_wen = valid_write;
assign ram_waddr = tail;
assign ram_raddr = head;
assign ram_raddr_next = next_head;
// Valid write, high when valid to write data to the FIFO
assign valid_write = enable & ((read & write) | (write & (~full)));
assign valid_read = enable & (read & (~empty));
// Empty state
always @(posedge clock)
begin
if (reset)
empty <= 1'b1;
else if (enable & empty & write)
empty <= 1'b0;
else if (enable & read & ~write & next_head_is_tail)
empty <= 1'b1;
end
// Head LFSR (where to read)
LFSR3_9 #(.LENGTH(LOG_DEP), .FULL_CYCLE(1)) lfsr_head (
.clock (clock),
.reset (reset),
.enable (valid_read),
.dout (head),
.dout_next (next_head));
// Tail LFSR (where to write)
LFSR3_9 #(.LENGTH(LOG_DEP), .FULL_CYCLE(1)) lfsr_tail (
.clock (clock),
.reset (reset),
.enable (valid_write),
.dout (tail),
.dout_next ());
assign next_head_is_tail = (next_head == tail) ? 1'b1 : 1'b0;
endmodule
|
`timescale 1ns / 1ps
/* RAMFIFO_ctrl_lfsr_dc.v
* LFSR-based control for RAMFIFO, assuming that the RAMFIFO
* has an output register that stores the first element
*/
module RAMFIFO_ctrl_lfsr_dc (
clock,
reset,
enable,
write,
read,
full,
empty,
ram_wen,
ram_waddr,
ram_raddr
);
parameter WIDTH = 36;
parameter LOG_DEP = 6;
localparam DEPTH = 1 << LOG_DEP;
input clock;
input reset;
input enable;
input write;
input read;
output full;
output empty;
output ram_wen;
output [LOG_DEP-1:0] ram_waddr;
output [LOG_DEP-1:0] ram_raddr;
// Control signals
wire valid_write;
wire valid_read;
wire next_head_is_tail;
wire [LOG_DEP-1:0] next_head;
wire [LOG_DEP-1:0] head;
wire [LOG_DEP-1:0] tail;
reg empty;
// Output
assign full = (head == tail && empty == 1'b0) ? 1'b1 : 1'b0;
assign ram_wen = valid_write;
assign ram_waddr = tail;
assign ram_raddr = next_head;
// Valid write, high when valid to write data to the FIFO
assign valid_write = enable & ((read & write) | (write & ~full));
assign valid_read = enable & (read & ~empty);
// Empty state
always @(posedge clock or posedge reset)
begin
if (reset)
empty <= 1'b1;
else if (enable & empty & write)
empty <= 1'b0;
else if (enable & read & ~write & next_head_is_tail)
empty <= 1'b1;
end
// Head LFSR (where to read)
LFSR3_9 #(.LENGTH(LOG_DEP), .FULL_CYCLE(1)) lfsr_head (
.clock (clock),
.reset (reset),
.enable (valid_read),
.dout (head),
.dout_next (next_head));
// Tail LFSR (where to write)
LFSR3_9 #(.LENGTH(LOG_DEP), .FULL_CYCLE(1)) lfsr_tail (
.clock (clock),
.reset (reset),
.enable (valid_write),
.dout (tail),
.dout_next ());
assign next_head_is_tail = (next_head == tail) ? 1'b1 : 1'b0;
// TODO
reg [15: 0] size;
always @(posedge clock or posedge reset)
begin
if (reset)
size <= 16'h0000;
else
begin
if (read & ~write)
size <= size - 1;
else if (write & ~read)
size <= size + 1;
end
end
endmodule
|
`timescale 1ns / 1ps
/* RAMFIFO_single.v
* Block RAM based FIFO (single context)
* If FIFO is empty, the new data appears at the output after 2
* clock cycle. Read signal dequeues the head of the FIFO.
*/
module RAMFIFO_single_slow #(
parameter WIDTH = 36,
parameter LOG_DEP = 4
)
(
input clock,
input reset,
input enable,
input [WIDTH-1:0] data_in,
output [WIDTH-1:0] data_out,
input write,
input read,
output full,
output empty,
output has_data
);
localparam DEPTH = 1 << LOG_DEP;
wire ram_wen;
wire [LOG_DEP-1:0] ram_waddr;
wire [LOG_DEP-1:0] ram_raddr;
wire [WIDTH-1:0] ram_dout;
wire w_empty;
wire w_full;
reg [WIDTH-1:0] s1_dout;
reg s2_empty;
reg rbusy; // Ensure read only registered in the 1st half cycle of the slow clock
wire fifo_read;
wire fifo_write;
assign data_out = s1_dout;
assign has_data = ~s2_empty & ~rbusy;
assign empty = s2_empty;
assign full = w_full;
assign fifo_read = enable & read & has_data;
assign fifo_write = enable & write & (~full);
always @(posedge clock)
begin
if (reset)
begin
rbusy <= 1'b0;
s2_empty <= 1'b1;
end
else if (enable)
begin
if (rbusy) rbusy <= 1'b0;
else rbusy <= fifo_read;
// Delay empty so it shows up 2 cycles after read to match dout
s2_empty <= w_empty;
end
end
// RAM control (1-cycle latency)
RAMFIFO_ctrl_lfsr #(.LOG_DEP(LOG_DEP)) ctrl (
.clock (clock),
.reset (reset),
.enable (enable),
.write (fifo_write), // caller is responsible for making sure write is only high for 1 cycle
.read (fifo_read),
.full (w_full),
.empty (w_empty),
.ram_wen (ram_wen),
.ram_waddr (ram_waddr),
.ram_raddr (),
.ram_raddr_next (ram_raddr));
// RAM storage
DualBRAM #(.WIDTH(WIDTH), .LOG_DEP(LOG_DEP)) ram (
.clock (clock),
.enable (enable),
.wen (ram_wen),
.waddr (ram_waddr),
.raddr (ram_raddr),
.din (data_in),
.dout (ram_dout),
.wdout ());
// First stage output register at posedge of clock
always @(posedge clock)
begin
if (reset)
s1_dout <= {(WIDTH){1'b0}};
else if (enable)
begin
if (write & w_empty)
s1_dout <= data_in;
else if (rbusy)
s1_dout <= ram_dout;
end
end
endmodule
|
`timescale 1ns / 1ps
/* RAMFIFO.v
* Block RAM based FIFO
* If FIFO is empty, the new data appears at the output after 2
* clock cycles. Read signal dequeues the head of the FIFO.
*/
module RAMFIFO_slow (
clock,
reset,
enable,
wcc_id,
rcc_id,
data_in,
data_out,
write,
read,
full,
empty,
has_data,
error
);
parameter WIDTH = 36;
parameter LOG_DEP = 6; // 64 elements
parameter LOG_CTX = 3;
localparam DEPTH = 1 << LOG_DEP;
localparam NUM_CTX = 1 << LOG_CTX;
input clock;
input reset;
input enable;
input [LOG_CTX-1:0] wcc_id; // Select context to write
input [LOG_CTX-1:0] rcc_id; // Select context to read for reading
input [WIDTH-1:0] data_in;
input write;
input read;
output [NUM_CTX*WIDTH-1:0] data_out;
output [NUM_CTX-1:0] full;
output [NUM_CTX-1:0] empty;
output [NUM_CTX-1:0] has_data;
output error;
wire ram_wen;
wire [LOG_DEP-1:0] ram_waddr;
wire [LOG_DEP-1:0] ram_raddr;
wire [WIDTH-1:0] ram_dout; // Regular read
wire [NUM_CTX-1:0] wen_all;
wire [NUM_CTX*LOG_DEP-1:0] waddr_all;
wire [NUM_CTX*LOG_DEP-1:0] raddr_all;
wire [NUM_CTX-1:0] w_empty;
wire [NUM_CTX-1:0] w_full;
wire [NUM_CTX-1:0] w_fifo_error;
wire [NUM_CTX-1:0] w_write_en;
wire [NUM_CTX-1:0] w_read_en;
wire [NUM_CTX-1:0] w_write;
wire [NUM_CTX-1:0] w_read;
wire [NUM_CTX-1:0] w_enable;
// Internal states
reg [NUM_CTX-1:0] rbusy;
reg [NUM_CTX-1:0] s2_empty;
// Output
assign empty = s2_empty;
assign full = w_full;
assign has_data = ~s2_empty & ~rbusy;
assign error = |w_fifo_error;
// Context decoder
wire [NUM_CTX-1:0] wcc_id_decoded;
wire [NUM_CTX-1:0] rcc_id_decoded;
assign w_enable = w_write_en | w_read_en;
assign w_write_en = (enable) ? wcc_id_decoded : {(NUM_CTX){1'b0}};
assign w_read_en = (enable) ? rcc_id_decoded : {(NUM_CTX){1'b0}};
decoder_N #(.SIZE(NUM_CTX)) wcc_decoder (
.encoded (wcc_id),
.decoded (wcc_id_decoded));
decoder_N #(.SIZE(NUM_CTX)) rcc_decoder (
.encoded (rcc_id),
.decoded (rcc_id_decoded));
// RAM control, one for each context (LFSR-based, 50% smaller than counter based)
genvar i;
generate
for (i = 0; i < NUM_CTX; i = i + 1)
begin : ram_ctrl
reg [WIDTH-1:0] s1_dout;
assign w_fifo_error[i] = (w_write[i] & full[i]) | (w_read[i] & empty[i]);
assign w_write[i] = w_write_en[i] & write & (~full[i]);
assign w_read[i] = w_read_en[i] & read & has_data[i];
RAMFIFO_ctrl_lfsr #(.LOG_DEP(LOG_DEP)) ctrl (
.clock (clock),
.reset (reset),
.enable (w_enable[i]),
.write (w_write[i]),
.read (w_read[i]),
.full (w_full[i]),
.empty (w_empty[i]),
.ram_wen (wen_all[i]),
.ram_waddr (waddr_all[(i+1)*LOG_DEP-1:i*LOG_DEP]),
.ram_raddr (),
.ram_raddr_next (raddr_all[(i+1)*LOG_DEP-1:i*LOG_DEP]));
always @(posedge clock)
begin
if (reset)
begin
rbusy[i] <= 1'b0;
s2_empty[i] <= 1'b1;
end
else if (enable)
begin
if (rbusy[i]) rbusy[i] <= 1'b0;
else rbusy[i] <= w_read[i];
s2_empty[i] <= w_empty[i];
end
end
// Output registers
always @(posedge clock)
begin
if (reset)
begin
s1_dout <= {(WIDTH){1'b0}};
end
else if (enable)
begin
if (w_write[i] & w_empty[i])
s1_dout <= data_in;
else if (rbusy[i])
s1_dout <= ram_dout;
end
end
assign data_out[(i+1)*WIDTH-1:i*WIDTH] = s1_dout;
end
endgenerate
// Multiplexer to select the control signals for the specified context
assign ram_wen = |wen_all;
mux_Nto1 #(.WIDTH(LOG_DEP), .SIZE(NUM_CTX)) ram_waddr_mux (
.in (waddr_all),
.sel (wcc_id),
.out (ram_waddr));
mux_Nto1 #(.WIDTH(LOG_DEP), .SIZE(NUM_CTX)) ram_raddr_mux (
.in (raddr_all),
.sel (rcc_id),
.out (ram_raddr));
// RAM storage
DualBRAM #(.WIDTH(WIDTH), .LOG_DEP(LOG_DEP + LOG_CTX)) ram (
.clock (clock),
.enable (enable),
.wen (ram_wen),
.waddr ({wcc_id, ram_waddr}),
.raddr ({rcc_id, ram_raddr}),
.din (data_in),
.dout (ram_dout),
.wdout ());
endmodule
|
`timescale 1ns / 1ps
/* RAMFIFO_wrapper.v
* Wrapper for RAMFIFO.v to measure post PAR resource utilization
* because otherwise MAP packs output registers into IOs
*/
module RAMFIFO_wrapper(
clock,
reset,
wctx_id,
rctx_id,
data_in,
data_out,
write,
read,
full,
empty
);
parameter WIDTH = 36;
parameter LOG_DEP = 6;
parameter LOG_CTX = 3;
localparam DEPTH = 1 << LOG_DEP;
localparam NUM_CTX = 1 << LOG_CTX;
input clock;
input reset;
input [LOG_CTX-1:0] wctx_id;
input [LOG_CTX-1:0] rctx_id;
input [WIDTH-1:0] data_in;
input write;
input read;
output [WIDTH-1:0] data_out;
output full;
output empty;
wire [NUM_CTX*WIDTH-1:0] w_dout_all;
wire [NUM_CTX-1:0] w_full_all;
wire [NUM_CTX-1:0] w_empty_all;
mux_Nto1 #(.WIDTH(WIDTH), .SIZE(NUM_CTX)) dout_mux (
.in (w_dout_all),
.sel (wctx_id),
.out (data_out));
mux_Nto1 #(.WIDTH(1), .SIZE(NUM_CTX)) full_mux (
.in (w_full_all),
.sel (rctx_id),
.out (full));
mux_Nto1 #(.WIDTH(1), .SIZE(NUM_CTX)) empty_mux (
.in (w_empty_all),
.sel (rctx_id),
.out (empty));
RAMFIFO #(.WIDTH(WIDTH), .LOG_DEP(LOG_DEP), .LOG_CTX(LOG_CTX)) ut (
.clock (clock),
.reset (reset),
.wcc_id (wctx_id),
.rcc_id (rctx_id),
.data_in (data_in),
.data_out (w_dout_all),
.write (write),
.read (read),
.full (w_full_all),
.empty (w_empty_all));
endmodule
|
`timescale 1 ns/100 ps // time unit = 1ns; precision = 1/10 ns
/* Random Number Generator
* rng.v
*
* This RNG implements a three-component Tausworth generator.
* It generates a 32-bit random value.
*
* The output of RNG is registered.
*
* Configuration path
* config_in -> s1 -> s2 -> s3 -> config_out
*/
module RNG (
clock,
reset,
enable,
rand_out,
config_in_valid,
config_in,
config_out_valid,
config_out
);
input clock;
input reset;
input enable;
input config_in_valid;
input [15: 0] config_in;
output config_out_valid;
output [15: 0] config_out;
output [31: 0] rand_out;
// Seeds
reg [31: 0] s1, s2, s3;
wire [31: 0] s1_wire, s2_wire, s3_wire, b1_wire, b2_wire, b3_wire;
assign b1_wire = (((s1 << 13) ^ s1) >> 19);
assign s1_wire = (((s1 & 32'hFFFFFFFE) << 12) ^ b1_wire);
assign b2_wire = (((s2 << 2) ^ s2) >> 25);
assign s2_wire = (((s2 & 32'hFFFFFFF8) << 4) ^ b2_wire);
assign b3_wire = (((s3 << 3) ^ s3) >> 11);
assign s3_wire = (((s3 & 32'hFFFFFFF0) << 17) ^ b3_wire);
assign rand_out = s1 ^ s2 ^ s3;
assign config_out_valid = config_in_valid;
assign config_out = s3[15:0];
always @(posedge clock)
begin
if (reset)
begin
s1 <= 32'hffff_fc02;
s2 <= 32'hffff_fc03;
s3 <= 32'hffff_fc04;
end
else
begin
// Configuration path
if (config_in_valid)
{s1, s2, s3} <= {config_in, s1, s2, s3[31:16]};
// Data path
else if (enable)
{s1, s2, s3} <= {s1_wire, s2_wire, s3_wire};
end
end
endmodule
|
`timescale 1 ns/100 ps // time unit = 1ns; precision = 1/10 ns
/* Rotating Priority Encoder
* rotate_prio.v
*
* Given a set of valid signals and a priority value, output
* one-hot select vector
*/
module rotate_prio (
prio,
in_valid,
out_sel
);
`include "math.v"
parameter SIZE = 2;
input [CLogB2(SIZE-1)-1: 0] prio;
input [SIZE-1: 0] in_valid;
output [SIZE-1: 0] out_sel;
wire [SIZE-1: 0] w_norm_valid;
wire [SIZE-1: 0] w_norm_sel;
assign w_norm_valid = (in_valid << (SIZE - prio)) | (in_valid >> prio);
assign out_sel = (w_norm_sel << prio) | (w_norm_sel >> (SIZE-prio));
arbiter_static #(.SIZE(SIZE)) arb (
.requests (w_norm_valid),
.grants (w_norm_sel),
.grant_valid ());
endmodule
|
`timescale 1ns/100 ps // time unit = 1ns; precision = 1/10 ns
/* Router
* Router.v
*
* Single N-port Router. NPORTS x NVCS input ports, 1 output port
*
* Configuration path:
* config_in -> CreditCounter_0 -> ... -> CreditCounter_N (N = nports * nvc) -> config_out
* ram_config_in -> Input RouterPortLookup -> Output RouterPortLookup -> ram_config_out
*/
`include "const.v"
module Router (
clock,
reset,
enable,
sim_time,
sim_time_tick,
error,
is_quiescent,
can_increment,
ram_config_in,
ram_config_in_valid,
ram_config_out,
ram_config_out_valid,
config_in,
config_in_valid,
config_out,
config_out_valid,
flit_in,
flit_in_valid,
flit_ack,
flit_out,
flit_out_valid,
nexthop_out,
dequeue,
credit_in,
credit_in_valid,
credit_ack,
credit_out,
credit_out_valid,
credit_out_nexthop,
credit_dequeue,
rtable_dest,
rtable_oport
);
`include "math.v"
`include "util.v"
parameter [`ADDR_WIDTH-1:0] HADDR = 0; // 8-bit global node ID
parameter NPORTS = 5;
parameter NVCS = 2;
localparam LOG_NPORTS = CLogB2(NPORTS-1);
localparam LOG_NVCS = CLogB2(NVCS-1);
localparam NINPUTS = NPORTS * NVCS;
localparam CC_WIDTH = 4; // Max credits = 16
// Global interface
input clock;
input reset;
input enable;
input [`TS_WIDTH-1: 0] sim_time;
input sim_time_tick;
output error;
output is_quiescent;
output can_increment;
// RAM config interface
input [15: 0] ram_config_in;
input ram_config_in_valid;
output [15: 0] ram_config_out;
output ram_config_out_valid;
// Data config interface
input [15: 0] config_in;
input config_in_valid;
output [15: 0] config_out;
output config_out_valid;
// Data interface
input [`FLIT_WIDTH*NINPUTS-1: 0] flit_in;
input [NINPUTS-1: 0] flit_in_valid;
output [NINPUTS-1: 0] flit_ack;
output [`FLIT_WIDTH-1: 0] flit_out;
output flit_out_valid;
output [`A_WIDTH-1: 0] nexthop_out;
input dequeue;
// Credit interface
input [`CREDIT_WIDTH*NPORTS-1: 0] credit_in;
input [NPORTS-1: 0] credit_in_valid;
output [NPORTS-1: 0] credit_ack;
output [`CREDIT_WIDTH-1: 0] credit_out;
output credit_out_valid;
output [`A_WIDTH-1: 0] credit_out_nexthop;
input credit_dequeue;
// Routing table interface
output [`ADDR_WIDTH-1: 0] rtable_dest;
input [LOG_NPORTS-1: 0] rtable_oport;
// Internal states
reg [ 7: 0] r_ovc_config_pad;
reg [`FLIT_WIDTH-1: 0] r_s2_flit;
reg r_s2_flit_valid;
reg r_error;
// Wires
wire w_enable_input_select;
wire [NINPUTS-1:0] w_s2_flit_iport_sel;
wire [`FLIT_WIDTH-1:0] w_s1_flit; // Input to pipeline registers
wire w_s1_flit_valid;
wire [`FLIT_WIDTH-1:0] w_s2_updated_flit; // Input to obuf
wire [`FLIT_WIDTH-1:0] w_s3_flit; // Output of obuf
wire [`CREDIT_WIDTH-1:0] w_s2_credit;
wire [`CREDIT_WIDTH-1:0] w_s3_credit;
wire [LOG_NPORTS-1:0] w_s3_credit_oport;
wire [LOG_NVCS-1:0] w_last_ovc_for_this_ivc;// Output VC allocated for this input VC
wire [LOG_NVCS-1:0] w_vc_alloc_out; // Allocated VC
wire w_vc_alloc_out_valid; // Indicate if VC Alloc was successful
wire w_obuf_full;
wire w_obuf_empty;
wire w_credit_obuf_full;
wire w_credit_obuf_empty;
wire w_s2_routed;
wire w_s2_vc_allocate_enable;// Head flit, enable VC allocation
wire w_s2_vc_free_enable; // Tail flit, free allocated VC
wire w_s2_route_enable;
wire w_s2_vc_valid; // Either a VC is inherited or VCAlloc was successful
wire [NINPUTS-1: 0] w_credit_in_valid;
wire [NINPUTS-1: 0] w_credit_ack;
wire [NINPUTS*4-1: 0] w_ovc_config_in;
wire [NINPUTS-1: 0] w_ovc_config_in_valid;
wire [NINPUTS*4-1: 0] w_ovc_config_out;
wire [NINPUTS-1: 0] w_ovc_config_out_valid;
wire [NINPUTS-1: 0] w_ovc_use_credit;
wire [NINPUTS*4-1: 0] w_ovc_credit;
wire [CC_WIDTH-1: 0] w_oport_credit;
wire error1;
wire error2;
always @(posedge clock)
begin
if (w_s2_routed)
$display ("T %d flit %x oport %d.%d credit %d", sim_time, w_s2_updated_flit, rtable_oport, w_s2_updated_flit[0], w_oport_credit);
end
//
// Output
//
assign error = r_error;
assign is_quiescent = w_obuf_empty & w_credit_obuf_empty;
assign config_out = {r_ovc_config_pad, w_ovc_config_out[39:32]};
assign config_out_valid = w_ovc_config_out_valid[9];
assign flit_out = w_s3_flit;
assign credit_out = w_s3_credit;
//
// Input select
//
assign w_enable_input_select = enable & ~w_obuf_full;
RouterInput #(.NPORTS(NPORTS), .NVCS(NVCS)) input_unit (
.clock (clock),
.reset (reset),
.enable (w_enable_input_select),
.sim_time_tick (sim_time_tick),
.flit_in (flit_in),
.flit_in_valid (flit_in_valid),
.s2_flit_routed (w_s2_routed),
.s2_flit_valid (r_s2_flit_valid),
.s2_flit_iport_decoded (w_s2_flit_iport_sel),
.s1_flit (w_s1_flit),
.s1_flit_valid (w_s1_flit_valid),
.flit_ack (flit_ack),
.can_increment (can_increment));
//
// Connections going to RoutingTable
//
assign rtable_dest = w_s1_flit[`F_DEST];
//
// Pipeline registers
//
always @(posedge clock)
begin
if (reset)
begin
r_s2_flit <= 0;
r_s2_flit_valid <= 1'b0;
end
else if (enable)
begin
r_s2_flit <= w_s1_flit;
r_s2_flit_valid <= w_s1_flit_valid;
end
end
//
// Generate new flit
//
rt_update_flit #(.VC_WIDTH(LOG_NVCS), .PORT_WIDTH(LOG_NPORTS)) update_flit (
.sim_time (sim_time),
.old_flit (r_s2_flit),
.old_flit_valid (r_s2_flit_valid),
.saved_vc (w_last_ovc_for_this_ivc),
.allocated_vc (w_vc_alloc_out),
.routed_oport (rtable_oport),
.updated_flit (w_s2_updated_flit));
//
// Output flit buffer
//
RAMFIFO_single_slow #(.WIDTH(`FLIT_WIDTH), .LOG_DEP(4)) obuf (
.clock (clock),
.reset (reset),
.enable (enable),
.data_in (w_s2_updated_flit),
.data_out (w_s3_flit),
.write (w_s2_routed),
.read (dequeue),
.full (w_obuf_full),
.empty (w_obuf_empty),
.has_data (flit_out_valid));
//
// Generate credit (same timestamp as routed flit)
//
assign w_s2_credit = {r_s2_flit[0], w_s2_updated_flit[`F_TS]};
//
// Output credit buffer
//
RAMFIFO_single_slow #(.WIDTH(`CREDIT_WIDTH+LOG_NPORTS), .LOG_DEP(4)) credit_obuf (
.clock (clock),
.reset (reset),
.enable (enable),
.data_in ({r_s2_flit[`F_OPORT], w_s2_credit}),
.data_out ({w_s3_credit_oport, w_s3_credit}),
.write (w_s2_routed),
.read (credit_dequeue),
.full (w_credit_obuf_full),
.empty (w_credit_obuf_empty),
.has_data (credit_out_valid));
//
// Translate outgoing oport to hardware addresses
//
RouterPortLookup #(.NPORTS(NPORTS), .WIDTH(`A_WIDTH)) oport_map (
.clock (clock),
.reset (reset),
.ram_config_in (ram_config_in),
.ram_config_in_valid (ram_config_in_valid),
.ram_config_out (ram_config_out),
.ram_config_out_valid (ram_config_out_valid),
.port_id_a (w_s3_flit[`F_OPORT]),
.haddr_a (nexthop_out),
.port_id_b (w_s3_credit_oport),
.haddr_b (credit_out_nexthop));
//------------------------------------------------------------------------
//
// VC Allocation
//
wire [NINPUTS-1:0] w_vc_alloc_mask;
genvar i;
generate
for (i = 0; i < NINPUTS; i = i + 1)
begin : vc_mask
assign w_vc_alloc_mask[i] = (ovc[i].credit_count == 0) ? 1'b0 : 1'b1;
end
endgenerate
assign w_s2_vc_allocate_enable = r_s2_flit_valid & r_s2_flit[`F_HEAD] & w_s2_route_enable;
assign w_s2_vc_free_enable = r_s2_flit_valid & r_s2_flit[`F_TAIL] & w_s2_route_enable;
VCAlloc #(.NPORTS(NPORTS), .NVCS(NVCS)) vc_alloc (
.clock (clock),
.reset (reset),
.enable (enable),
.mask (w_vc_alloc_mask),
.oport (rtable_oport), // Indicate the output port to allocate VC for
.allocate (w_s2_vc_allocate_enable),
.next_vc (w_vc_alloc_out),
.next_vc_valid (w_vc_alloc_out_valid),
.free (w_s2_vc_free_enable),
.free_vc (w_last_ovc_for_this_ivc));
//
// Output VCs allocated to the Input VCs
//
InputVCState #(.VC_WIDTH(LOG_NVCS), .NINPUTS(NINPUTS)) ivc_state (
.clock (clock),
.reset (reset),
.allocated_vc (w_vc_alloc_out),
.allocate_enable (w_s2_vc_allocate_enable),
.ivc_sel (w_s2_flit_iport_sel),
.assigned_vc (w_last_ovc_for_this_ivc));
//
// Credit Counters (1 for each output VC)
//
generate
// Decoded input credits
for (i = 0; i < NPORTS; i = i + 1)
begin : iport_credit
wire [NVCS-1:0] w_credit_in_vc_decoded;
decoder_N #(.SIZE(NVCS)) vc_decode (
.encoded (credit_vc(credit_in[(i+1)*`CREDIT_WIDTH-1:i*`CREDIT_WIDTH])),
.decoded (w_credit_in_vc_decoded));
assign w_credit_in_valid[(i+1)*NVCS-1:i*NVCS] = w_credit_in_vc_decoded & {(NVCS){credit_in_valid[i]}};
assign credit_ack[i] = |(w_credit_ack[(i+1)*NVCS-1:i*NVCS]);
end
// Credit counters
for (i = 0; i < NINPUTS; i = i + 1)
begin : ovc
wire [CC_WIDTH-1:0] credit_count;
assign w_ovc_credit[(i+1)*CC_WIDTH-1:i*CC_WIDTH] = credit_count;
CreditCounter #(.WIDTH(CC_WIDTH)) credit (
.clock (clock),
.reset (reset),
.enable (enable),
.sim_time_tick (sim_time_tick),
.config_in (w_ovc_config_in[(i+1)*4-1:i*4]),
.config_in_valid (w_ovc_config_in_valid[i]),
.config_out (w_ovc_config_out[(i+1)*4-1:i*4]),
.config_out_valid (w_ovc_config_out_valid[i]),
.credit_in_valid (w_credit_in_valid[i]),
.credit_ack (w_credit_ack[i]),
.decrement (w_ovc_use_credit[i] & w_s2_routed),
.count_out (credit_count));
end
endgenerate
mux_Nto1 #(.WIDTH(CC_WIDTH), .SIZE(NINPUTS)) oport_credit_mux (
.in (w_ovc_credit),
.sel ({rtable_oport, w_s2_updated_flit[0]}), // Use routed_vc to select credit
.out (w_oport_credit));
decoder_N #(.SIZE(NINPUTS)) credit_decode (
.encoded ({rtable_oport, w_s2_updated_flit[0]}),
.decoded (w_ovc_use_credit));
// For now this composition of credit config only works for 10 VCs x 4 bits
// psl ERROR_unsupported_router_oVCs: assert always {NINPUTS == 10 && CC_WIDTH == 4};
assign w_ovc_config_in = {w_ovc_config_out[23:0], config_in};
assign w_ovc_config_in_valid = {w_ovc_config_out_valid[5:0], {(4){config_in_valid}}};
always @(posedge clock)
begin
if (reset)
r_ovc_config_pad <= 8'h00;
else if (w_ovc_config_out_valid[6])
r_ovc_config_pad <= w_ovc_config_out[31:24];
end
//------------------------------------------------------------------------
//
// Control Signals
//
assign w_s2_vc_valid = r_s2_flit_valid & (~r_s2_flit[`F_HEAD] | w_vc_alloc_out_valid);
assign w_s2_route_enable = (w_oport_credit != 0) ? 1'b1 : 1'b0;
assign w_s2_routed = w_s2_route_enable & w_s2_vc_valid;
//------------------------------------------------------------------------
//
// Error
//
assign error1 = w_credit_obuf_full;
assign error2 = (r_s2_flit_valid == 1'b1 && rtable_oport == {(LOG_NPORTS){1'b1}}) ? 1'b1 : 1'b0;
always @(posedge clock)
begin
if (reset)
r_error <= 1'b0;
else if (enable & ~r_error)
r_error <= error1 | error2;
end
endmodule
|
`timescale 1ns / 1ps
/* RouterInput
* RouterInput.v
*
* Input module of a Router (connects to all NPORTS x NVCS input FQs)
*
*/
`include "const.v"
module RouterInput (
clock,
reset,
enable,
sim_time_tick,
flit_in,
flit_in_valid,
s2_flit_routed,
s2_flit_valid,
s2_flit_iport_decoded,
s1_flit,
s1_flit_valid,
flit_ack,
can_increment
);
`include "math.v"
`include "util.v"
parameter NPORTS = 5;
parameter NVCS = 2;
localparam NINPUTS = NPORTS * NVCS;
localparam LOG_NPORTS = CLogB2(NPORTS-1);
localparam LOG_NVCS = CLogB2(NVCS-1);
localparam LOG_NINPUTS = LOG_NPORTS + LOG_NVCS;
input clock;
input reset;
input enable;
input sim_time_tick;
input [NINPUTS*`FLIT_WIDTH-1: 0] flit_in;
input [NINPUTS-1: 0] flit_in_valid;
input s2_flit_routed; // Stage 2 flit is routed
input s2_flit_valid;
output [NINPUTS-1: 0] s2_flit_iport_decoded;
output [`FLIT_WIDTH-1: 0] s1_flit; // Unregistered selected flit
output s1_flit_valid;
output [NINPUTS-1: 0] flit_ack;
output can_increment;
// Internal states
reg [NINPUTS-1: 0] r_inspected;
reg [NINPUTS-1: 0] r_input_sel; // Registered input select
// Wires
wire w_ack_input; // Only ack input of last flit was routed
wire w_iport_info_reset;
wire [NINPUTS-1: 0] w_valid_uninspected_ports;
wire [NINPUTS-1: 0] w_input_sel; // Decoded select for inputs
wire [LOG_NINPUTS-1: 0] w_input_sel_encoded;
wire [`FLIT_WIDTH-1: 0] w_input_flit;
wire w_input_flit_valid;
// Output
assign s2_flit_iport_decoded = r_input_sel;
assign s1_flit = {w_input_flit[35:5], w_input_sel_encoded[3:1], 1'b0, w_input_sel_encoded[0]};
assign s1_flit_valid = w_input_flit_valid;
assign flit_ack = w_ack_input ? r_input_sel : {(NINPUTS){1'b0}};
assign w_valid_uninspected_ports = (~r_inspected) & flit_in_valid;
assign w_ack_input = s2_flit_valid & s2_flit_routed;
// Can increment logic: increment when no ready ports is left and there is
// no valid flit in the pipeline
assign can_increment = (w_valid_uninspected_ports == 0) ? ~s2_flit_valid : 1'b0;
// Select first ready port
arbiter_static #(.SIZE(NINPUTS)) in_select (
.requests (w_valid_uninspected_ports),
.grants (w_input_sel),
.grant_valid (w_input_flit_valid));
encoder_N #(.SIZE(NINPUTS)) input_sel_encoder (
.decoded (w_input_sel),
.encoded (w_input_sel_encoded),
.valid ());
// Input port MUX
mux_Nto1 #(.WIDTH(`FLIT_WIDTH), .SIZE(NINPUTS)) flit_in_mux (
.in (flit_in),
.sel (w_input_sel_encoded),
.out (w_input_flit));
// Input select pipeline register
always @(posedge clock)
begin
if (reset)
r_input_sel <= {(NINPUTS){1'b0}};
else if (enable)
r_input_sel <= w_input_sel;
end
// Input port info (sync reset here because glitches in sim_time_tick causes r_inspected
// to reset in simulation)
assign w_iport_info_reset = reset | sim_time_tick;
always @(posedge clock)
begin
if (w_iport_info_reset)
r_inspected <= {(NINPUTS){1'b0}};
else if (enable)
r_inspected <= r_inspected | w_input_sel;
end
endmodule
|
`timescale 1 ns/100 ps // time unit = 1ns; precision = 1/10 ns
/* Router Port Lookup Table
* RouterPortLookup.v
*
* Implement a small distributed RAM-based lookup table that converts
* Router port ID (3-bit) into physical node addresses (8-bit)
*
* Configuration path
* ram_config_in -> table -> ram_config_out
*/
`include "const.v"
module RouterPortLookup (
clock,
reset,
ram_config_in,
ram_config_in_valid,
ram_config_out,
ram_config_out_valid,
port_id_a,
haddr_a,
port_id_b,
haddr_b
);
`include "math.v"
parameter NPORTS = 5;
parameter WIDTH = 8;
localparam LOG_NPORTS = CLogB2(NPORTS-1);
// Global interface
input clock;
input reset;
// RAM configuration interface
input [15: 0] ram_config_in;
input ram_config_in_valid;
output [15: 0] ram_config_out;
output ram_config_out_valid;
// Data interface
input [LOG_NPORTS-1: 0] port_id_a;
output [WIDTH-1: 0] haddr_a;
input [LOG_NPORTS-1: 0] port_id_b;
output [WIDTH-1: 0] haddr_b;
// Internal states
reg [LOG_NPORTS-1: 0] n_words_loaded;
// Wires
wire [LOG_NPORTS-1: 0] w_ram_addr;
wire w_config_done;
// Output
assign ram_config_out = ram_config_in;
assign ram_config_out_valid = w_config_done ? ram_config_in_valid : 1'b0;
assign w_config_done = (n_words_loaded == NPORTS) ? 1'b1 : 1'b0;
// Config chain requires WIDTH <= 16
// psl ERROR_distroRAM_width: assert always {WIDTH <= 16};
// Lookup RAM
assign w_ram_addr = (w_config_done) ? port_id_a : n_words_loaded[LOG_NPORTS-1:0];
DistroRAM #(.WIDTH(WIDTH), .LOG_DEP(LOG_NPORTS)) port_table (
.clock (clock),
.wen (ram_config_in_valid & ~w_config_done),
.waddr (w_ram_addr),
.raddr (port_id_b),
.din (ram_config_in[WIDTH-1:0]),
.wdout (haddr_a),
.rdout (haddr_b));
// Configuration FSM
always @(posedge clock)
begin
if (reset)
n_words_loaded <= 0;
else if (ram_config_in_valid & ~w_config_done)
n_words_loaded <= n_words_loaded + 1;
end
endmodule
|
`timescale 1ns/100 ps // time unit = 1ns; precision = 1/10 ns
/* RoutingTable
* RoutingTable.v
*
* N-context dual-port Routing Table with 256 x 9 bits entries each
*/
`include "const.v"
module RoutingTable (
clock,
reset,
enable,
ram_config_in,
ram_config_in_valid,
ram_config_out,
ram_config_out_valid,
ccid_ina,
dest_ina,
ccid_outa,
nexthop_outa,
ccid_inb,
dest_inb,
ccid_outb,
nexthop_outb
);
`include "math.v"
parameter LOG_CTX = 3; // Specify number of contexts
localparam LOG_TBSIZE = 1 + LOG_CTX + `ADDR_WIDTH;
localparam TABLE_SIZE = 1 << LOG_TBSIZE;
// Global interface
input clock;
input reset;
input enable;
// RAM configuration interface
input [15: 0] ram_config_in;
input ram_config_in_valid;
output [15: 0] ram_config_out;
output ram_config_out_valid;
// Data interface (port A)
input [LOG_CTX-1: 0] ccid_ina;
input [`ADDR_WIDTH-1: 0] dest_ina;
output [LOG_CTX-1: 0] ccid_outa;
output [ 8: 0] nexthop_outa;
// port B
input [LOG_CTX-1: 0] ccid_inb;
input [`ADDR_WIDTH-1: 0] dest_inb;
output [LOG_CTX-1: 0] ccid_outb;
output [ 8: 0] nexthop_outb;
// Internal states
reg [LOG_TBSIZE: 0] n_words_loaded;
reg [LOG_CTX-1: 0] r_ccida;
reg [LOG_CTX-1: 0] r_ccidb;
// Wires
wire [LOG_TBSIZE-1: 0] w_waddr;
wire w_config_done;
// Output
assign ram_config_out = ram_config_in;
assign ram_config_out_valid = w_config_done ? ram_config_in_valid : 1'b0;
assign ccid_outa = r_ccida; // Match 1-cycle latency of RAM reading
assign ccid_outb = r_ccidb;
assign w_config_done = (n_words_loaded == TABLE_SIZE) ? 1'b1 : 1'b0;
assign w_waddr = (w_config_done) ? {1'b0, dest_ina} : n_words_loaded[LOG_TBSIZE-1:0];
// Routing Table
DualBRAM #(.WIDTH(9), .LOG_DEP(LOG_TBSIZE)) rtable (
.clock (clock),
.wen (ram_config_in_valid & ~w_config_done),
.waddr (w_waddr),
.raddr ({1'b1, ccid_inb, dest_inb}),
.din (ram_config_in[8:0]),
.dout (nexthop_outb),
.wdout (nexthop_outa));
// Pipeline register for cc_id
always @(posedge clock or posedge reset)
begin
if (reset)
begin
r_ccida <= 0;
r_ccidb <= 0;
end
else if (enable)
begin
r_ccida <= ccid_ina;
r_ccidb <= ccid_inb;
end
end
// Configuration FSM
always @(posedge clock or posedge reset)
begin
if (reset)
n_words_loaded <= 0;
else if (ram_config_in_valid & ~w_config_done)
n_words_loaded <= n_words_loaded + 1;
end
endmodule
|
`timescale 1ns/100 ps // time unit = 1ns; precision = 1/10 ns
/* RoutingTable
* RoutingTable.v
*
* N-context dual-port Routing Table with 256 x 9 bits entries each
*/
`include "const.v"
module RoutingTable_single (
clock,
reset,
enable,
ram_config_in,
ram_config_in_valid,
ram_config_out,
ram_config_out_valid,
dest_ina,
nexthop_outa,
dest_inb,
nexthop_outb
);
`include "math.v"
localparam LOG_TBSIZE = 1 + `ADDR_WIDTH;
localparam TABLE_SIZE = 1 << LOG_TBSIZE;
// Global interface
input clock;
input reset;
input enable;
// RAM configuration interface
input [15: 0] ram_config_in;
input ram_config_in_valid;
output [15: 0] ram_config_out;
output ram_config_out_valid;
// Data interface (port A)
input [`ADDR_WIDTH-1: 0] dest_ina;
output [ 8: 0] nexthop_outa;
// port B
input [`ADDR_WIDTH-1: 0] dest_inb;
output [ 8: 0] nexthop_outb;
// Internal states
reg [LOG_TBSIZE: 0] n_words_loaded;
// Wires
wire [LOG_TBSIZE-1: 0] w_waddr;
wire w_config_done;
// Output
assign ram_config_out = ram_config_in;
assign ram_config_out_valid = w_config_done ? ram_config_in_valid : 1'b0;
assign w_config_done = (n_words_loaded == TABLE_SIZE) ? 1'b1 : 1'b0;
assign w_waddr = (w_config_done) ? {1'b0, dest_ina} : n_words_loaded[LOG_TBSIZE-1:0];
// Routing Table
DualBRAM #(.WIDTH(9), .LOG_DEP(LOG_TBSIZE)) rtable (
.enable (enable),
.clock (clock),
.wen (ram_config_in_valid & ~w_config_done),
.waddr (w_waddr),
.raddr ({1'b1, dest_inb}),
.din (ram_config_in[8:0]),
.dout (nexthop_outb),
.wdout (nexthop_outa));
// Configuration FSM
always @(posedge clock)
begin
if (reset)
n_words_loaded <= 0;
else if (ram_config_in_valid & ~w_config_done)
n_words_loaded <= n_words_loaded + 1;
end
endmodule
|
`timescale 1ns / 1ps
/* Round-Robin Priority Encoder
*
* The bit selection logic is hard coded and works when prio is one-hot.
* The module that instantiates rr_prio must guarantee this condition.
*/
module rr_prio #(
parameter N = 4
)
(
input [N-1:0] ready,
input [N-1:0] prio,
output [N-1:0] select
);
// psl ERROR_unsupported_rr_prio_size: assert always {N == 2 || N == 4};
generate
if (N == 2)
begin
assign select[0] = (prio[0] | (prio[1] & ~ready[0])) & ready[0];
assign select[1] = ((prio[0] & ~ready[1]) | prio[1]) & ready[1];
end
else if (N == 4)
begin
assign select[0] = ( prio[0] |
(prio[1] & ~ready[1] & ~ready[2] & ~ready[3]) |
(prio[2] & ~ready[2] & ~ready[3]) |
(prio[3] & ~ready[3])
) & ready[0];
assign select[1] = ((prio[0] & ~ready[0]) |
prio[1] |
(prio[2] & ~ready[2] & ~ready[3] & ~ready[0]) |
(prio[3] & ~ready[3] & ~ready[0])
) & ready[1];
assign select[2] = ((prio[0] & ~ready[0] & ~ready[1]) |
(prio[1] & ~ready[1]) |
prio[2] |
(prio[3] & ~ready[3] & ~ready[0] & ~ready[1])
) & ready[2];
assign select[3] = ((prio[0] & ~ready[0] & ~ready[1] & ~ready[2]) |
(prio[1] & ~ready[1] & ~ready[2]) |
(prio[2] & ~ready[2]) |
prio[3]
) & ready[3];
end
else
assign select = 0;
endgenerate
endmodule
|
`timescale 1ns/100 ps // time unit = 1ns; precision = 1/10 ns
/* Router
* Router.v
*
* Single N-port Router. NPORTS x NVCS input ports, 1 output port
*
* Configuration path:
* config_in -> CreditCounter_0 -> ... -> CreditCounter_N (N = nports * nvc) -> config_out
* ram_config_in -> Input RouterPortLookup -> Output RouterPortLookup -> ram_config_out
*/
`include "const.v"
module rt_update_flit #(
parameter VC_WIDTH = 1,
PORT_WIDTH = 3
)
(
input [`TS_WIDTH-1:0] sim_time,
input [`FLIT_WIDTH-1:0] old_flit,
input old_flit_valid,
input [VC_WIDTH-1:0] saved_vc,
input [VC_WIDTH-1:0] allocated_vc,
input [PORT_WIDTH-1:0] routed_oport,
output [`FLIT_WIDTH-1:0] updated_flit
);
// New flit timestamp = max (old_flit.timestamp, sim_time) + router_latency (1)
wire [`TS_WIDTH-1:0] w_max_ts;
wire [`TS_WIDTH-1:0] w_routed_ts;
assign w_routed_ts = sim_time + 10'h005;
// Use newly allocated VC if this is a header flit, otherwise inherit VC
wire [VC_WIDTH-1:0] w_routed_vc;
assign w_routed_vc = (old_flit[`F_HEAD] & old_flit_valid) ? allocated_vc : saved_vc;
// Construct new flit
assign updated_flit[`F_FLAGS] = old_flit[`F_FLAGS];
assign updated_flit[`F_TS] = w_routed_ts;
assign updated_flit[`F_DEST] = old_flit[`F_DEST];
assign updated_flit[`F_SRC_INJ] = old_flit[`F_SRC_INJ];
assign updated_flit[`F_OPORT] = routed_oport;
assign updated_flit[`F_OVC] = {1'b0, w_routed_vc};
endmodule
|
`timescale 1 ns/100 ps // time unit = 1ns; precision = 1/10 ns
/* Select Early (use 3-bit timestamp LSb)
* select_early_3b.v
*
* Combinational module that selects the earliest of N input timestamps
*/
module select_early_3b (
ts_in,
valid,
tmin,
sel,
sel_valid
);
`include "math.v"
parameter N = 2;
localparam LOG_N = CLogB2(N-1);
input [3*N-1:0] ts_in;
input [N-1:0] valid;
output [2:0] tmin;
output [LOG_N-1:0] sel;
output sel_valid;
// We only support x2, x8 for now
// psl ERROR_unsupported_N: assert always {N == 2 || N == 8};
assign sel_valid = |valid;
// The strictly-earlier table:
//
// t1\t0 | 000 | 001 | 010 | 011 | 100 | 101 | 110 | 111
// ------------------------------------------------------
// 000 | t0 | t1 | t1 | t1 | t1 | t0 | t0 | t0
// 001 | t0 | t0 | t1 | t1 | t1 | t1 | t0 | t0
// 010 | t0 | t0 | t0 | t1 | t1 | t1 | t1 | t0
// 011 | t0 | t0 | t0 | t0 | t1 | t1 | t1 | t1
// 100 | t1 | t0 | t0 | t0 | t0 | t1 | t1 | t1
// 101 | t1 | t1 | t0 | t0 | t0 | t0 | t1 | t1
// 110 | t1 | t1 | t1 | t0 | t0 | t0 | t0 | t1
// 111 | t1 | t1 | t1 | t1 | t0 | t0 | t0 | t0
generate
if (N == 2)
begin
reg bsel;
reg [2:0] btmin;
assign sel = (bsel & valid[1]) | (~valid[0]);
//assign tmin = (sel == 1'b0) ? ts_in[2:0] : ts_in[5:3];
//assign tmin = (valid[1] == 1'b0) ? ts_in[2:0] : btmin;
assign tmin = btmin;
always @(*)
begin
case (ts_in)
// t1 = 000
6'b000_000: begin bsel = 1'b0; btmin = 3'b000;end // select t0
6'b000_001: begin bsel = 1'b1; btmin = 3'b000;end // select t1
6'b000_010: begin bsel = 1'b1; btmin = 3'b000;end
6'b000_011: begin bsel = 1'b1; btmin = 3'b000;end
6'b000_100: begin bsel = 1'b1; btmin = 3'b000;end
6'b000_101: begin bsel = 1'b0; btmin = 3'b101;end
6'b000_110: begin bsel = 1'b0; btmin = 3'b110;end
6'b000_111: begin bsel = 1'b0; btmin = 3'b111;end
// t1 = 001
6'b001_000: begin bsel = 1'b0; btmin = 3'b000;end
6'b001_001: begin bsel = 1'b0; btmin = 3'b001;end
6'b001_010: begin bsel = 1'b1; btmin = 3'b001;end
6'b001_011: begin bsel = 1'b1; btmin = 3'b001;end
6'b001_100: begin bsel = 1'b1; btmin = 3'b001;end
6'b001_101: begin bsel = 1'b1; btmin = 3'b001;end
6'b001_110: begin bsel = 1'b0; btmin = 3'b110;end
6'b001_111: begin bsel = 1'b0; btmin = 3'b111;end
// t1 = 010
6'b010_000: begin bsel = 1'b0; btmin = 3'b000;end
6'b010_001: begin bsel = 1'b0; btmin = 3'b001;end
6'b010_010: begin bsel = 1'b0; btmin = 3'b010;end
6'b010_011: begin bsel = 1'b1; btmin = 3'b010;end
6'b010_100: begin bsel = 1'b1; btmin = 3'b010;end
6'b010_101: begin bsel = 1'b1; btmin = 3'b010;end
6'b010_110: begin bsel = 1'b1; btmin = 3'b010;end
6'b010_111: begin bsel = 1'b0; btmin = 3'b111;end
// t1 = 011
6'b011_000: begin bsel = 1'b0; btmin = 3'b000;end
6'b011_001: begin bsel = 1'b0; btmin = 3'b001;end
6'b011_010: begin bsel = 1'b0; btmin = 3'b010;end
6'b011_011: begin bsel = 1'b0; btmin = 3'b011;end
6'b011_100: begin bsel = 1'b1; btmin = 3'b011;end
6'b011_101: begin bsel = 1'b1; btmin = 3'b011;end
6'b011_110: begin bsel = 1'b1; btmin = 3'b011;end
6'b011_111: begin bsel = 1'b1; btmin = 3'b011;end
// t1 = 100
6'b100_000: begin bsel = 1'b1; btmin = 3'b100;end
6'b100_001: begin bsel = 1'b0; btmin = 3'b001;end
6'b100_010: begin bsel = 1'b0; btmin = 3'b010;end
6'b100_011: begin bsel = 1'b0; btmin = 3'b011;end
6'b100_100: begin bsel = 1'b0; btmin = 3'b100;end
6'b100_101: begin bsel = 1'b1; btmin = 3'b100;end
6'b100_110: begin bsel = 1'b1; btmin = 3'b100;end
6'b100_111: begin bsel = 1'b1; btmin = 3'b100;end
// t1 = 101
6'b101_000: begin bsel = 1'b1; btmin = 3'b101;end
6'b101_001: begin bsel = 1'b1; btmin = 3'b101;end
6'b101_010: begin bsel = 1'b0; btmin = 3'b010;end
6'b101_011: begin bsel = 1'b0; btmin = 3'b011;end
6'b101_100: begin bsel = 1'b0; btmin = 3'b100;end
6'b101_101: begin bsel = 1'b0; btmin = 3'b101;end
6'b101_110: begin bsel = 1'b1; btmin = 3'b101;end
6'b101_111: begin bsel = 1'b1; btmin = 3'b101;end
// t1 = 110
6'b110_000: begin bsel = 1'b1; btmin = 3'b110;end
6'b110_001: begin bsel = 1'b1; btmin = 3'b110;end
6'b110_010: begin bsel = 1'b1; btmin = 3'b110;end
6'b110_011: begin bsel = 1'b0; btmin = 3'b011;end
6'b110_100: begin bsel = 1'b0; btmin = 3'b100;end
6'b110_101: begin bsel = 1'b0; btmin = 3'b101;end
6'b110_110: begin bsel = 1'b0; btmin = 3'b110;end
6'b110_111: begin bsel = 1'b1; btmin = 3'b110;end
// t1 = 111
6'b111_000: begin bsel = 1'b1; btmin = 3'b111;end
6'b111_001: begin bsel = 1'b1; btmin = 3'b111;end
6'b111_010: begin bsel = 1'b1; btmin = 3'b111;end
6'b111_011: begin bsel = 1'b1; btmin = 3'b111;end
6'b111_100: begin bsel = 1'b0; btmin = 3'b100;end
6'b111_101: begin bsel = 1'b0; btmin = 3'b101;end
6'b111_110: begin bsel = 1'b0; btmin = 3'b110;end
6'b111_111: begin bsel = 1'b0; btmin = 3'b111;end
endcase
end
end
else if (N == 4 || N == 8)
begin
wire [2:0] w_tmin;
wire [2:0] w_tmin_temp [1:0];
wire [LOG_N-2:0] w_sel_temp [1:0];
wire [1:0] w_valid_temp;
wire w_sel;
wire [LOG_N-2:0] w_sub_sel;
select_early_3b #(.N(N/2)) u0 (
.ts_in (ts_in[3*N/2-1:0]),
.valid (valid[N/2-1:0]),
.tmin (w_tmin_temp[0]),
.sel (w_sel_temp[0]),
.sel_valid (w_valid_temp[0]));
select_early_3b #(.N(N/2)) u1 (
.ts_in (ts_in[3*N-1:3*N/2]),
.valid (valid[N-1:N/2]),
.tmin (w_tmin_temp[1]),
.sel (w_sel_temp[1]),
.sel_valid (w_valid_temp[1]));
select_early_3b #(.N(2)) u (
.ts_in ({w_tmin_temp[1], w_tmin_temp[0]}),
.valid (w_valid_temp),
.tmin (w_tmin),
.sel (w_sel),
.sel_valid ());
assign w_sub_sel = (w_sel == 1'b0) ? w_sel_temp[0] : w_sel_temp[1];
assign tmin = w_tmin;
assign sel = {w_sel, w_sub_sel};
end
endgenerate
endmodule
|
`timescale 1 ns/100 ps // time unit = 1ns; precision = 1/10 ns
/* Select Early x N
* select_early_N.v
*
* Combinational module that selects the earliest of N (= 2^n) input timestamps
*/
module select_early_N (
ts_in,
valid,
tmin,
sel,
sel_valid
);
`include "math.v"
parameter N = 2;
parameter WIDTH = 3; // Width of the timestamp to be compared
localparam LOG_N = CLogB2(N-1);
input [N*WIDTH-1:0] ts_in;
input [N-1:0] valid;
output [WIDTH-1:0] tmin;
output [LOG_N-1:0] sel;
output sel_valid;
// We only support x2, x4 and x8 for now
// psl ERROR_unsupported_N: assert always {N == 2 || N == 4 || N == 8 || N == 9};
assign sel_valid = |valid;
generate
if (N == 2)
begin
wire [WIDTH-1:0] t0;
wire [WIDTH-1:0] t1;
wire [WIDTH-1:0] w_tdiff;
wire w_early;
assign t1 = ts_in[2*WIDTH-1:WIDTH];
assign t0 = ts_in[WIDTH-1:0];
assign w_tdiff = t1 - t0;
assign w_early = ~w_tdiff[WIDTH-1]; // w_early = (t1 - t0 >= 0)
assign sel = (w_early & valid[1]) | ~valid[0];
assign tmin = (sel == 1'b0) ? t0 : t1;
end
else if (N == 4 || N == 8)
begin
wire [WIDTH-1:0] w_tmin;
wire [WIDTH-1:0] w_tmin_0;
wire [WIDTH-1:0] w_tmin_1;
wire [LOG_N-2:0] w_sel_0;
wire [LOG_N-2:0] w_sel_1;
wire [1:0] w_valid;
wire w_sel;
wire [LOG_N-2:0] w_sub_sel;
select_early_N #(.N(N/2), .WIDTH(WIDTH)) u0 (
.ts_in (ts_in[N/2*WIDTH-1:0]),
.valid (valid[N/2-1:0]),
.tmin (w_tmin_0),
.sel (w_sel_0),
.sel_valid (w_valid[0]));
select_early_N #(.N(N/2), .WIDTH(WIDTH)) u1 (
.ts_in (ts_in[N*WIDTH-1:N/2*WIDTH]),
.valid (valid[N-1:N/2]),
.tmin (w_tmin_1),
.sel (w_sel_1),
.sel_valid (w_valid[1]));
select_early_N #(.N(2), .WIDTH(WIDTH)) u (
.ts_in ({w_tmin_1, w_tmin_0}),
.valid (w_valid),
.tmin (w_tmin),
.sel (w_sel),
.sel_valid ());
assign w_sub_sel = (w_sel == 1'b0) ? w_sel_0 : w_sel_1;
assign tmin = w_tmin;
assign sel = {w_sel, w_sub_sel};
end
else if (N == 9)
begin
wire [WIDTH-1:0] w_tmin_8;
wire [2:0] w_sel_8;
wire w_valid_8;
wire w_sel;
wire [2:0] w_sub_sel;
wire [1:0] w_tmin;
select_early_N #(.N(8), .WIDTH(WIDTH)) u8 (
.ts_in (ts_in[8*WIDTH-1:0]),
.valid (valid[7:0]),
.tmin (w_tmin_8),
.sel (w_sel_8),
.sel_valid (w_valid_8));
select_early_N #(.N(2), .WIDTH(WIDTH)) u2 (
.ts_in ({ts_in[9*WIDTH-1:8*WIDTH], w_tmin_8}),
.valid ({valid[8], w_valid_8}),
.tmin (w_tmin),
.sel (w_sel),
.sel_valid ());
assign w_sub_sel = (w_sel == 1'b0) ? w_sel_8 : 3'b000;
assign tmin = w_tmin;
assign sel = {w_sel, w_sub_sel};
end
else
begin
assign tmin = {(WIDTH){1'b0}};
assign sel = {(LOG_N){1'b0}};
end
endgenerate
endmodule
|
`timescale 1 ns/100 ps // time unit = 1ns; precision = 1/10 ns
/* Select Ready
*
* Input: N-bit ready and N-bit ready-urgent
* Output: N-bit grant vector
* Selects 1 ready input (priority to urgent-ready signals) among the requesters
*/
module select_ready #(
parameter N = 2
)
(
input [N-1:0] ready,
input [N-1:0] ready_urgent,
output [N-1:0] sel,
output sel_valid,
output sel_valid_urgent
);
wire [N-1:0] w_sel_normal;
wire [N-1:0] w_sel_urgent;
arbiter_static #(.SIZE(N)) arb_normal (
.requests (ready),
.grants (w_sel_normal),
.grant_valid (sel_valid));
arbiter_static #(.SIZE(N)) arb_urgent (
.requests (ready_urgent),
.grants (w_sel_urgent),
.grant_valid (sel_valid_urgent));
assign sel = (sel_valid_urgent == 1'b1) ? w_sel_urgent : w_sel_normal;
endmodule
|
`timescale 1ns / 1ps
/* 2-to-1 serializer and deserializer
*/
/* Deserializer acknolwedges the narrower data_in immediately
*/
module deserializer #(
parameter WIDTH = 8, // Width of each data chunk
parameter N = 2 // Number of data chunks to deserialize
)
(
input clock,
input reset,
input [WIDTH-1:0] data_in,
input data_in_valid,
output [WIDTH*N-1:0] data_out,
output data_out_valid
);
`include "math.v"
// Internal states
reg [WIDTH*N-1:0] data_store;
reg [CLogB2(N-1)-1:0] data_chunk_count;
reg data_store_valid;
// Output
assign data_out = data_store;
assign data_out_valid = data_store_valid;
always @(posedge clock)
begin
if (reset)
begin
data_store <= {(WIDTH*N){1'b0}};
data_chunk_count <= 1'b0;
data_store_valid <= 1'b0;
end
else
begin
if (data_in_valid)
begin
// Right shift to deserialize
data_store <= {data_in, data_store[WIDTH*N-1:WIDTH]};
if (data_chunk_count == N-1)
data_chunk_count <= 0;
else
data_chunk_count <= data_chunk_count + 1'b1;
end
// We have received all data chunks
if (data_chunk_count == N-1 && data_in_valid == 1'b1)
data_store_valid <= 1'b1;
else
data_store_valid <= 1'b0;
end
end
endmodule
/* Serializer acknowledges the wider data_in when it starts processing the word
*/
module serializer #(
parameter WIDTH = 8, // Width of each data chunk
parameter N = 2 // Number of data chunks to serialize
)
(
input clock,
input reset,
input [WIDTH*N-1:0] data_in,
input data_in_valid,
output [WIDTH-1:0] data_out,
output reg data_out_valid,
output busy
);
localparam IDLE = 0,
BUSY = 1;
`include "math.v"
// Internal states
reg [WIDTH*N-1:0] data_store;
reg [CLogB2(N-1)-1:0] data_chunk_count;
reg state;
assign data_out = data_store[WIDTH-1:0];
assign busy = (state == IDLE) ? 1'b0 : 1'b1;
always @(posedge clock)
begin
if (reset)
begin
data_store <= {(WIDTH*N){1'b0}};
data_chunk_count <= 0;
state <= IDLE;
end
else
begin
case (state)
IDLE:
begin
if (data_in_valid)
begin
data_store <= data_in;
data_chunk_count <= data_chunk_count + 1;
data_out_valid <= 1'b1;
state <= BUSY;
end
else
data_out_valid <= 1'b0;
end
BUSY:
begin
data_store <= {{(WIDTH-1){1'b0}}, data_store[WIDTH*N-1:WIDTH]};
data_chunk_count <= data_chunk_count + 1;
data_out_valid <= 1'b1;
if (data_chunk_count == N-1)
state <= IDLE;
end
endcase
end
end
endmodule
|
module sim32_8x8 (
input clock,
input reset,
input enable,
input stop_injection,
input measure,
output reg [9:0] sim_time,
output sim_time_tick,
output error,
output quiescent,
input [15:0] config_in,
input config_in_valid,
output [15:0] config_out,
output config_out_valid,
output [15:0] stats_out,
input stats_shift
);
// Internal states
reg tick_counter;
wire [0:0] can_increment;
wire [0:0] can_tick;
wire [7:0] part_error;
wire [7:0] part_quiescent;
wire [7:0] part_can_increment;
wire [15:0] part_config_in [8:0];
wire [8:0] part_config_in_valid;
wire [15:0] part_ram_config_in [8:0];
wire [8:0] part_ram_config_in_valid;
wire [15:0] part_stats_in [8:0];
wire [7:0] fdp_error;
wire [7:0] fdp_select [7:0];
wire [7:0] cdp_error;
wire [7:0] cdp_select [7:0];
wire [7:0] fsp_select [7:0];
wire [7:0] fsp_can_increment;
wire [7:0] csp_select [7:0];
wire [7:0] csp_can_increment;
wire [63:0] fsp_s1_nexthop;
wire [7:0] fsp_s1_valid;
wire [7:0] fsp_s1_valid_urgent;
wire [287:0] fsp_s2_data;
wire [63:0] fsp_s2_nexthop;
wire [63:0] csp_s1_nexthop;
wire [7:0] csp_s1_valid;
wire [7:0] csp_s1_valid_urgent;
wire [87:0] csp_s2_data;
wire [63:0] csp_s2_nexthop;
assign sim_time_tick = enable & can_increment & can_tick;
assign error = (|part_error) | (|fdp_error) | (|cdp_error);
assign quiescent = &part_quiescent;
assign can_increment = (&part_can_increment) & (&fsp_can_increment) & (&csp_can_increment);
assign config_out = part_config_in[8];
assign config_out_valid = part_config_in_valid[8];
assign stats_out = part_stats_in[8];
assign part_config_in_valid[0] = config_in_valid;
assign part_config_in[0] = config_in;
assign part_ram_config_in_valid[0] = config_in_valid;
assign part_ram_config_in[0] = config_in;
assign part_stats_in[0] = 16'h0000;
always @(posedge clock)
begin
if (reset)
sim_time <= 16'h0;
else if (sim_time_tick)
sim_time <= sim_time + 1;
end
always @(posedge clock)
begin
if (reset)
tick_counter <= 1'b0;
else if (enable)
begin
if (sim_time_tick)
tick_counter <= 1'b0;
else if (~tick_counter)
tick_counter <= tick_counter + 1'b1;
end
end
assign can_tick = tick_counter;
wire [3:0] fsp_0_vec_valid;
wire [3:0] fsp_0_vec_valid_urgent;
wire [143:0] fsp_0_vec_data;
wire [31:0] fsp_0_vec_nexthop;
wire [3:0] fsp_0_vec_dequeue;
wire [3:0] csp_0_vec_valid;
wire [3:0] csp_0_vec_valid_urgent;
wire [43:0] csp_0_vec_data;
wire [31:0] csp_0_vec_nexthop;
wire [3:0] csp_0_vec_dequeue;
wire [0:0] fdp_0_valid;
wire [35:0] fdp_0_data;
wire [4:0] fdp_0_nexthop;
wire [0:0] fdp_0_ack;
wire [0:0] cdp_0_valid;
wire [10:0] cdp_0_data;
wire [4:0] cdp_0_nexthop;
wire [0:0] cdp_0_ack;
Partition #(.DPID(0), .N(4)) part_0 (
.clock (clock),
.reset (reset),
.enable (enable),
.stop_injection (stop_injection),
.measure (measure),
.sim_time (sim_time),
.sim_time_tick (sim_time_tick),
.error (part_error[0]),
.is_quiescent (part_quiescent[0]),
.can_increment (part_can_increment[0]),
.config_in_valid (part_config_in_valid[0]),
.config_in (part_config_in[0]),
.config_out_valid (part_config_in_valid[1]),
.config_out (part_config_in[1]),
.ram_config_in_valid (part_ram_config_in_valid[0]),
.ram_config_in (part_ram_config_in[0]),
.ram_config_out_valid (part_ram_config_in_valid[1]),
.ram_config_out (part_ram_config_in[1]),
.stats_shift (stats_shift),
.stats_in (part_stats_in[0]),
.stats_out (part_stats_in[1]),
.fsp_vec_valid (fsp_0_vec_valid),
.fsp_vec_valid_urgent (fsp_0_vec_valid_urgent),
.fsp_vec_data (fsp_0_vec_data),
.fsp_vec_nexthop (fsp_0_vec_nexthop),
.fsp_vec_dequeue (fsp_0_vec_dequeue),
.csp_vec_valid (csp_0_vec_valid),
.csp_vec_valid_urgent (csp_0_vec_valid_urgent),
.csp_vec_data (csp_0_vec_data),
.csp_vec_nexthop (csp_0_vec_nexthop),
.csp_vec_dequeue (csp_0_vec_dequeue),
.fdp_valid (fdp_0_valid),
.fdp_data (fdp_0_data),
.fdp_nexthop (fdp_0_nexthop),
.fdp_ack (fdp_0_ack),
.cdp_valid (cdp_0_valid),
.cdp_data (cdp_0_data),
.cdp_nexthop (cdp_0_nexthop),
.cdp_ack (cdp_0_ack)
);
ICDestPart #(.PID(0), .NSP(8), .WIDTH(36)) fdp_0 (
.clock (clock),
.reset (reset),
.enable (enable),
.error (fdp_error[0]),
.src_s1_valid (fsp_s1_valid),
.src_s1_valid_urgent (fsp_s1_valid_urgent),
.src_s1_nexthop_in (fsp_s1_nexthop),
.src_s1_part_sel (fdp_select[0]),
.src_s2_data_in (fsp_s2_data),
.src_s2_nexthop_in (fsp_s2_nexthop),
.dequeue (fdp_0_ack),
.s3_data_out (fdp_0_data),
.s3_nexthop_out (fdp_0_nexthop),
.s3_data_valid (fdp_0_valid)
);
ICDestPart #(.PID(0), .NSP(8), .WIDTH(11)) cdp_0 (
.clock (clock),
.reset (reset),
.enable (enable),
.error (cdp_error[0]),
.src_s1_valid (csp_s1_valid),
.src_s1_valid_urgent (csp_s1_valid_urgent),
.src_s1_nexthop_in (csp_s1_nexthop),
.src_s1_part_sel (cdp_select[0]),
.src_s2_data_in (csp_s2_data),
.src_s2_nexthop_in (csp_s2_nexthop),
.dequeue (cdp_0_ack),
.s3_data_out (cdp_0_data),
.s3_nexthop_out (cdp_0_nexthop),
.s3_data_valid (cdp_0_valid)
);
ICSourcePart #(.N(4), .WIDTH(36)) fsp_0 (
.clock (clock),
.reset (reset),
.enable (enable),
.select (|fsp_select[0]),
.can_increment (fsp_can_increment[0]),
.src_data_valid (fsp_0_vec_valid[3:0]),
.src_data_valid_urgent (fsp_0_vec_valid_urgent[3:0]),
.src_data_in (fsp_0_vec_data[143:0]),
.src_nexthop_in (fsp_0_vec_nexthop[31:0]),
.src_dequeue (fsp_0_vec_dequeue[3:0]),
.s1_nexthop_out (fsp_s1_nexthop[7:0]),
.s1_valid (fsp_s1_valid[0]),
.s1_valid_urgent (fsp_s1_valid_urgent[0]),
.s2_data_out (fsp_s2_data[35:0]),
.s2_nexthop_out (fsp_s2_nexthop[7:0])
);
ICSourcePart #(.N(4), .WIDTH(11)) csp_0 (
.clock (clock),
.reset (reset),
.enable (enable),
.select (|csp_select[0]),
.can_increment (csp_can_increment[0]),
.src_data_valid (csp_0_vec_valid[3:0]),
.src_data_valid_urgent (csp_0_vec_valid_urgent[3:0]),
.src_data_in (csp_0_vec_data[43:0]),
.src_nexthop_in (csp_0_vec_nexthop[31:0]),
.src_dequeue (csp_0_vec_dequeue[3:0]),
.s1_nexthop_out (csp_s1_nexthop[7:0]),
.s1_valid (csp_s1_valid[0]),
.s1_valid_urgent (csp_s1_valid_urgent[0]),
.s2_data_out (csp_s2_data[10:0]),
.s2_nexthop_out (csp_s2_nexthop[7:0])
);
wire [3:0] fsp_1_vec_valid;
wire [3:0] fsp_1_vec_valid_urgent;
wire [143:0] fsp_1_vec_data;
wire [31:0] fsp_1_vec_nexthop;
wire [3:0] fsp_1_vec_dequeue;
wire [3:0] csp_1_vec_valid;
wire [3:0] csp_1_vec_valid_urgent;
wire [43:0] csp_1_vec_data;
wire [31:0] csp_1_vec_nexthop;
wire [3:0] csp_1_vec_dequeue;
wire [0:0] fdp_1_valid;
wire [35:0] fdp_1_data;
wire [4:0] fdp_1_nexthop;
wire [0:0] fdp_1_ack;
wire [0:0] cdp_1_valid;
wire [10:0] cdp_1_data;
wire [4:0] cdp_1_nexthop;
wire [0:0] cdp_1_ack;
Partition #(.DPID(1), .N(4)) part_1 (
.clock (clock),
.reset (reset),
.enable (enable),
.stop_injection (stop_injection),
.measure (measure),
.sim_time (sim_time),
.sim_time_tick (sim_time_tick),
.error (part_error[1]),
.is_quiescent (part_quiescent[1]),
.can_increment (part_can_increment[1]),
.config_in_valid (part_config_in_valid[1]),
.config_in (part_config_in[1]),
.config_out_valid (part_config_in_valid[2]),
.config_out (part_config_in[2]),
.ram_config_in_valid (part_ram_config_in_valid[1]),
.ram_config_in (part_ram_config_in[1]),
.ram_config_out_valid (part_ram_config_in_valid[2]),
.ram_config_out (part_ram_config_in[2]),
.stats_shift (stats_shift),
.stats_in (part_stats_in[1]),
.stats_out (part_stats_in[2]),
.fsp_vec_valid (fsp_1_vec_valid),
.fsp_vec_valid_urgent (fsp_1_vec_valid_urgent),
.fsp_vec_data (fsp_1_vec_data),
.fsp_vec_nexthop (fsp_1_vec_nexthop),
.fsp_vec_dequeue (fsp_1_vec_dequeue),
.csp_vec_valid (csp_1_vec_valid),
.csp_vec_valid_urgent (csp_1_vec_valid_urgent),
.csp_vec_data (csp_1_vec_data),
.csp_vec_nexthop (csp_1_vec_nexthop),
.csp_vec_dequeue (csp_1_vec_dequeue),
.fdp_valid (fdp_1_valid),
.fdp_data (fdp_1_data),
.fdp_nexthop (fdp_1_nexthop),
.fdp_ack (fdp_1_ack),
.cdp_valid (cdp_1_valid),
.cdp_data (cdp_1_data),
.cdp_nexthop (cdp_1_nexthop),
.cdp_ack (cdp_1_ack)
);
ICDestPart #(.PID(1), .NSP(8), .WIDTH(36)) fdp_1 (
.clock (clock),
.reset (reset),
.enable (enable),
.error (fdp_error[1]),
.src_s1_valid (fsp_s1_valid),
.src_s1_valid_urgent (fsp_s1_valid_urgent),
.src_s1_nexthop_in (fsp_s1_nexthop),
.src_s1_part_sel (fdp_select[1]),
.src_s2_data_in (fsp_s2_data),
.src_s2_nexthop_in (fsp_s2_nexthop),
.dequeue (fdp_1_ack),
.s3_data_out (fdp_1_data),
.s3_nexthop_out (fdp_1_nexthop),
.s3_data_valid (fdp_1_valid)
);
ICDestPart #(.PID(1), .NSP(8), .WIDTH(11)) cdp_1 (
.clock (clock),
.reset (reset),
.enable (enable),
.error (cdp_error[1]),
.src_s1_valid (csp_s1_valid),
.src_s1_valid_urgent (csp_s1_valid_urgent),
.src_s1_nexthop_in (csp_s1_nexthop),
.src_s1_part_sel (cdp_select[1]),
.src_s2_data_in (csp_s2_data),
.src_s2_nexthop_in (csp_s2_nexthop),
.dequeue (cdp_1_ack),
.s3_data_out (cdp_1_data),
.s3_nexthop_out (cdp_1_nexthop),
.s3_data_valid (cdp_1_valid)
);
ICSourcePart #(.N(4), .WIDTH(36)) fsp_1 (
.clock (clock),
.reset (reset),
.enable (enable),
.select (|fsp_select[1]),
.can_increment (fsp_can_increment[1]),
.src_data_valid (fsp_1_vec_valid[3:0]),
.src_data_valid_urgent (fsp_1_vec_valid_urgent[3:0]),
.src_data_in (fsp_1_vec_data[143:0]),
.src_nexthop_in (fsp_1_vec_nexthop[31:0]),
.src_dequeue (fsp_1_vec_dequeue[3:0]),
.s1_nexthop_out (fsp_s1_nexthop[15:8]),
.s1_valid (fsp_s1_valid[1]),
.s1_valid_urgent (fsp_s1_valid_urgent[1]),
.s2_data_out (fsp_s2_data[71:36]),
.s2_nexthop_out (fsp_s2_nexthop[15:8])
);
ICSourcePart #(.N(4), .WIDTH(11)) csp_1 (
.clock (clock),
.reset (reset),
.enable (enable),
.select (|csp_select[1]),
.can_increment (csp_can_increment[1]),
.src_data_valid (csp_1_vec_valid[3:0]),
.src_data_valid_urgent (csp_1_vec_valid_urgent[3:0]),
.src_data_in (csp_1_vec_data[43:0]),
.src_nexthop_in (csp_1_vec_nexthop[31:0]),
.src_dequeue (csp_1_vec_dequeue[3:0]),
.s1_nexthop_out (csp_s1_nexthop[15:8]),
.s1_valid (csp_s1_valid[1]),
.s1_valid_urgent (csp_s1_valid_urgent[1]),
.s2_data_out (csp_s2_data[21:11]),
.s2_nexthop_out (csp_s2_nexthop[15:8])
);
wire [3:0] fsp_2_vec_valid;
wire [3:0] fsp_2_vec_valid_urgent;
wire [143:0] fsp_2_vec_data;
wire [31:0] fsp_2_vec_nexthop;
wire [3:0] fsp_2_vec_dequeue;
wire [3:0] csp_2_vec_valid;
wire [3:0] csp_2_vec_valid_urgent;
wire [43:0] csp_2_vec_data;
wire [31:0] csp_2_vec_nexthop;
wire [3:0] csp_2_vec_dequeue;
wire [0:0] fdp_2_valid;
wire [35:0] fdp_2_data;
wire [4:0] fdp_2_nexthop;
wire [0:0] fdp_2_ack;
wire [0:0] cdp_2_valid;
wire [10:0] cdp_2_data;
wire [4:0] cdp_2_nexthop;
wire [0:0] cdp_2_ack;
Partition #(.DPID(2), .N(4)) part_2 (
.clock (clock),
.reset (reset),
.enable (enable),
.stop_injection (stop_injection),
.measure (measure),
.sim_time (sim_time),
.sim_time_tick (sim_time_tick),
.error (part_error[2]),
.is_quiescent (part_quiescent[2]),
.can_increment (part_can_increment[2]),
.config_in_valid (part_config_in_valid[2]),
.config_in (part_config_in[2]),
.config_out_valid (part_config_in_valid[3]),
.config_out (part_config_in[3]),
.ram_config_in_valid (part_ram_config_in_valid[2]),
.ram_config_in (part_ram_config_in[2]),
.ram_config_out_valid (part_ram_config_in_valid[3]),
.ram_config_out (part_ram_config_in[3]),
.stats_shift (stats_shift),
.stats_in (part_stats_in[2]),
.stats_out (part_stats_in[3]),
.fsp_vec_valid (fsp_2_vec_valid),
.fsp_vec_valid_urgent (fsp_2_vec_valid_urgent),
.fsp_vec_data (fsp_2_vec_data),
.fsp_vec_nexthop (fsp_2_vec_nexthop),
.fsp_vec_dequeue (fsp_2_vec_dequeue),
.csp_vec_valid (csp_2_vec_valid),
.csp_vec_valid_urgent (csp_2_vec_valid_urgent),
.csp_vec_data (csp_2_vec_data),
.csp_vec_nexthop (csp_2_vec_nexthop),
.csp_vec_dequeue (csp_2_vec_dequeue),
.fdp_valid (fdp_2_valid),
.fdp_data (fdp_2_data),
.fdp_nexthop (fdp_2_nexthop),
.fdp_ack (fdp_2_ack),
.cdp_valid (cdp_2_valid),
.cdp_data (cdp_2_data),
.cdp_nexthop (cdp_2_nexthop),
.cdp_ack (cdp_2_ack)
);
ICDestPart #(.PID(2), .NSP(8), .WIDTH(36)) fdp_2 (
.clock (clock),
.reset (reset),
.enable (enable),
.error (fdp_error[2]),
.src_s1_valid (fsp_s1_valid),
.src_s1_valid_urgent (fsp_s1_valid_urgent),
.src_s1_nexthop_in (fsp_s1_nexthop),
.src_s1_part_sel (fdp_select[2]),
.src_s2_data_in (fsp_s2_data),
.src_s2_nexthop_in (fsp_s2_nexthop),
.dequeue (fdp_2_ack),
.s3_data_out (fdp_2_data),
.s3_nexthop_out (fdp_2_nexthop),
.s3_data_valid (fdp_2_valid)
);
ICDestPart #(.PID(2), .NSP(8), .WIDTH(11)) cdp_2 (
.clock (clock),
.reset (reset),
.enable (enable),
.error (cdp_error[2]),
.src_s1_valid (csp_s1_valid),
.src_s1_valid_urgent (csp_s1_valid_urgent),
.src_s1_nexthop_in (csp_s1_nexthop),
.src_s1_part_sel (cdp_select[2]),
.src_s2_data_in (csp_s2_data),
.src_s2_nexthop_in (csp_s2_nexthop),
.dequeue (cdp_2_ack),
.s3_data_out (cdp_2_data),
.s3_nexthop_out (cdp_2_nexthop),
.s3_data_valid (cdp_2_valid)
);
ICSourcePart #(.N(4), .WIDTH(36)) fsp_2 (
.clock (clock),
.reset (reset),
.enable (enable),
.select (|fsp_select[2]),
.can_increment (fsp_can_increment[2]),
.src_data_valid (fsp_2_vec_valid[3:0]),
.src_data_valid_urgent (fsp_2_vec_valid_urgent[3:0]),
.src_data_in (fsp_2_vec_data[143:0]),
.src_nexthop_in (fsp_2_vec_nexthop[31:0]),
.src_dequeue (fsp_2_vec_dequeue[3:0]),
.s1_nexthop_out (fsp_s1_nexthop[23:16]),
.s1_valid (fsp_s1_valid[2]),
.s1_valid_urgent (fsp_s1_valid_urgent[2]),
.s2_data_out (fsp_s2_data[107:72]),
.s2_nexthop_out (fsp_s2_nexthop[23:16])
);
ICSourcePart #(.N(4), .WIDTH(11)) csp_2 (
.clock (clock),
.reset (reset),
.enable (enable),
.select (|csp_select[2]),
.can_increment (csp_can_increment[2]),
.src_data_valid (csp_2_vec_valid[3:0]),
.src_data_valid_urgent (csp_2_vec_valid_urgent[3:0]),
.src_data_in (csp_2_vec_data[43:0]),
.src_nexthop_in (csp_2_vec_nexthop[31:0]),
.src_dequeue (csp_2_vec_dequeue[3:0]),
.s1_nexthop_out (csp_s1_nexthop[23:16]),
.s1_valid (csp_s1_valid[2]),
.s1_valid_urgent (csp_s1_valid_urgent[2]),
.s2_data_out (csp_s2_data[32:22]),
.s2_nexthop_out (csp_s2_nexthop[23:16])
);
wire [3:0] fsp_3_vec_valid;
wire [3:0] fsp_3_vec_valid_urgent;
wire [143:0] fsp_3_vec_data;
wire [31:0] fsp_3_vec_nexthop;
wire [3:0] fsp_3_vec_dequeue;
wire [3:0] csp_3_vec_valid;
wire [3:0] csp_3_vec_valid_urgent;
wire [43:0] csp_3_vec_data;
wire [31:0] csp_3_vec_nexthop;
wire [3:0] csp_3_vec_dequeue;
wire [0:0] fdp_3_valid;
wire [35:0] fdp_3_data;
wire [4:0] fdp_3_nexthop;
wire [0:0] fdp_3_ack;
wire [0:0] cdp_3_valid;
wire [10:0] cdp_3_data;
wire [4:0] cdp_3_nexthop;
wire [0:0] cdp_3_ack;
Partition #(.DPID(3), .N(4)) part_3 (
.clock (clock),
.reset (reset),
.enable (enable),
.stop_injection (stop_injection),
.measure (measure),
.sim_time (sim_time),
.sim_time_tick (sim_time_tick),
.error (part_error[3]),
.is_quiescent (part_quiescent[3]),
.can_increment (part_can_increment[3]),
.config_in_valid (part_config_in_valid[3]),
.config_in (part_config_in[3]),
.config_out_valid (part_config_in_valid[4]),
.config_out (part_config_in[4]),
.ram_config_in_valid (part_ram_config_in_valid[3]),
.ram_config_in (part_ram_config_in[3]),
.ram_config_out_valid (part_ram_config_in_valid[4]),
.ram_config_out (part_ram_config_in[4]),
.stats_shift (stats_shift),
.stats_in (part_stats_in[3]),
.stats_out (part_stats_in[4]),
.fsp_vec_valid (fsp_3_vec_valid),
.fsp_vec_valid_urgent (fsp_3_vec_valid_urgent),
.fsp_vec_data (fsp_3_vec_data),
.fsp_vec_nexthop (fsp_3_vec_nexthop),
.fsp_vec_dequeue (fsp_3_vec_dequeue),
.csp_vec_valid (csp_3_vec_valid),
.csp_vec_valid_urgent (csp_3_vec_valid_urgent),
.csp_vec_data (csp_3_vec_data),
.csp_vec_nexthop (csp_3_vec_nexthop),
.csp_vec_dequeue (csp_3_vec_dequeue),
.fdp_valid (fdp_3_valid),
.fdp_data (fdp_3_data),
.fdp_nexthop (fdp_3_nexthop),
.fdp_ack (fdp_3_ack),
.cdp_valid (cdp_3_valid),
.cdp_data (cdp_3_data),
.cdp_nexthop (cdp_3_nexthop),
.cdp_ack (cdp_3_ack)
);
ICDestPart #(.PID(3), .NSP(8), .WIDTH(36)) fdp_3 (
.clock (clock),
.reset (reset),
.enable (enable),
.error (fdp_error[3]),
.src_s1_valid (fsp_s1_valid),
.src_s1_valid_urgent (fsp_s1_valid_urgent),
.src_s1_nexthop_in (fsp_s1_nexthop),
.src_s1_part_sel (fdp_select[3]),
.src_s2_data_in (fsp_s2_data),
.src_s2_nexthop_in (fsp_s2_nexthop),
.dequeue (fdp_3_ack),
.s3_data_out (fdp_3_data),
.s3_nexthop_out (fdp_3_nexthop),
.s3_data_valid (fdp_3_valid)
);
ICDestPart #(.PID(3), .NSP(8), .WIDTH(11)) cdp_3 (
.clock (clock),
.reset (reset),
.enable (enable),
.error (cdp_error[3]),
.src_s1_valid (csp_s1_valid),
.src_s1_valid_urgent (csp_s1_valid_urgent),
.src_s1_nexthop_in (csp_s1_nexthop),
.src_s1_part_sel (cdp_select[3]),
.src_s2_data_in (csp_s2_data),
.src_s2_nexthop_in (csp_s2_nexthop),
.dequeue (cdp_3_ack),
.s3_data_out (cdp_3_data),
.s3_nexthop_out (cdp_3_nexthop),
.s3_data_valid (cdp_3_valid)
);
ICSourcePart #(.N(4), .WIDTH(36)) fsp_3 (
.clock (clock),
.reset (reset),
.enable (enable),
.select (|fsp_select[3]),
.can_increment (fsp_can_increment[3]),
.src_data_valid (fsp_3_vec_valid[3:0]),
.src_data_valid_urgent (fsp_3_vec_valid_urgent[3:0]),
.src_data_in (fsp_3_vec_data[143:0]),
.src_nexthop_in (fsp_3_vec_nexthop[31:0]),
.src_dequeue (fsp_3_vec_dequeue[3:0]),
.s1_nexthop_out (fsp_s1_nexthop[31:24]),
.s1_valid (fsp_s1_valid[3]),
.s1_valid_urgent (fsp_s1_valid_urgent[3]),
.s2_data_out (fsp_s2_data[143:108]),
.s2_nexthop_out (fsp_s2_nexthop[31:24])
);
ICSourcePart #(.N(4), .WIDTH(11)) csp_3 (
.clock (clock),
.reset (reset),
.enable (enable),
.select (|csp_select[3]),
.can_increment (csp_can_increment[3]),
.src_data_valid (csp_3_vec_valid[3:0]),
.src_data_valid_urgent (csp_3_vec_valid_urgent[3:0]),
.src_data_in (csp_3_vec_data[43:0]),
.src_nexthop_in (csp_3_vec_nexthop[31:0]),
.src_dequeue (csp_3_vec_dequeue[3:0]),
.s1_nexthop_out (csp_s1_nexthop[31:24]),
.s1_valid (csp_s1_valid[3]),
.s1_valid_urgent (csp_s1_valid_urgent[3]),
.s2_data_out (csp_s2_data[43:33]),
.s2_nexthop_out (csp_s2_nexthop[31:24])
);
wire [3:0] fsp_4_vec_valid;
wire [3:0] fsp_4_vec_valid_urgent;
wire [143:0] fsp_4_vec_data;
wire [31:0] fsp_4_vec_nexthop;
wire [3:0] fsp_4_vec_dequeue;
wire [3:0] csp_4_vec_valid;
wire [3:0] csp_4_vec_valid_urgent;
wire [43:0] csp_4_vec_data;
wire [31:0] csp_4_vec_nexthop;
wire [3:0] csp_4_vec_dequeue;
wire [0:0] fdp_4_valid;
wire [35:0] fdp_4_data;
wire [4:0] fdp_4_nexthop;
wire [0:0] fdp_4_ack;
wire [0:0] cdp_4_valid;
wire [10:0] cdp_4_data;
wire [4:0] cdp_4_nexthop;
wire [0:0] cdp_4_ack;
Partition #(.DPID(4), .N(4)) part_4 (
.clock (clock),
.reset (reset),
.enable (enable),
.stop_injection (stop_injection),
.measure (measure),
.sim_time (sim_time),
.sim_time_tick (sim_time_tick),
.error (part_error[4]),
.is_quiescent (part_quiescent[4]),
.can_increment (part_can_increment[4]),
.config_in_valid (part_config_in_valid[4]),
.config_in (part_config_in[4]),
.config_out_valid (part_config_in_valid[5]),
.config_out (part_config_in[5]),
.ram_config_in_valid (part_ram_config_in_valid[4]),
.ram_config_in (part_ram_config_in[4]),
.ram_config_out_valid (part_ram_config_in_valid[5]),
.ram_config_out (part_ram_config_in[5]),
.stats_shift (stats_shift),
.stats_in (part_stats_in[4]),
.stats_out (part_stats_in[5]),
.fsp_vec_valid (fsp_4_vec_valid),
.fsp_vec_valid_urgent (fsp_4_vec_valid_urgent),
.fsp_vec_data (fsp_4_vec_data),
.fsp_vec_nexthop (fsp_4_vec_nexthop),
.fsp_vec_dequeue (fsp_4_vec_dequeue),
.csp_vec_valid (csp_4_vec_valid),
.csp_vec_valid_urgent (csp_4_vec_valid_urgent),
.csp_vec_data (csp_4_vec_data),
.csp_vec_nexthop (csp_4_vec_nexthop),
.csp_vec_dequeue (csp_4_vec_dequeue),
.fdp_valid (fdp_4_valid),
.fdp_data (fdp_4_data),
.fdp_nexthop (fdp_4_nexthop),
.fdp_ack (fdp_4_ack),
.cdp_valid (cdp_4_valid),
.cdp_data (cdp_4_data),
.cdp_nexthop (cdp_4_nexthop),
.cdp_ack (cdp_4_ack)
);
ICDestPart #(.PID(4), .NSP(8), .WIDTH(36)) fdp_4 (
.clock (clock),
.reset (reset),
.enable (enable),
.error (fdp_error[4]),
.src_s1_valid (fsp_s1_valid),
.src_s1_valid_urgent (fsp_s1_valid_urgent),
.src_s1_nexthop_in (fsp_s1_nexthop),
.src_s1_part_sel (fdp_select[4]),
.src_s2_data_in (fsp_s2_data),
.src_s2_nexthop_in (fsp_s2_nexthop),
.dequeue (fdp_4_ack),
.s3_data_out (fdp_4_data),
.s3_nexthop_out (fdp_4_nexthop),
.s3_data_valid (fdp_4_valid)
);
ICDestPart #(.PID(4), .NSP(8), .WIDTH(11)) cdp_4 (
.clock (clock),
.reset (reset),
.enable (enable),
.error (cdp_error[4]),
.src_s1_valid (csp_s1_valid),
.src_s1_valid_urgent (csp_s1_valid_urgent),
.src_s1_nexthop_in (csp_s1_nexthop),
.src_s1_part_sel (cdp_select[4]),
.src_s2_data_in (csp_s2_data),
.src_s2_nexthop_in (csp_s2_nexthop),
.dequeue (cdp_4_ack),
.s3_data_out (cdp_4_data),
.s3_nexthop_out (cdp_4_nexthop),
.s3_data_valid (cdp_4_valid)
);
ICSourcePart #(.N(4), .WIDTH(36)) fsp_4 (
.clock (clock),
.reset (reset),
.enable (enable),
.select (|fsp_select[4]),
.can_increment (fsp_can_increment[4]),
.src_data_valid (fsp_4_vec_valid[3:0]),
.src_data_valid_urgent (fsp_4_vec_valid_urgent[3:0]),
.src_data_in (fsp_4_vec_data[143:0]),
.src_nexthop_in (fsp_4_vec_nexthop[31:0]),
.src_dequeue (fsp_4_vec_dequeue[3:0]),
.s1_nexthop_out (fsp_s1_nexthop[39:32]),
.s1_valid (fsp_s1_valid[4]),
.s1_valid_urgent (fsp_s1_valid_urgent[4]),
.s2_data_out (fsp_s2_data[179:144]),
.s2_nexthop_out (fsp_s2_nexthop[39:32])
);
ICSourcePart #(.N(4), .WIDTH(11)) csp_4 (
.clock (clock),
.reset (reset),
.enable (enable),
.select (|csp_select[4]),
.can_increment (csp_can_increment[4]),
.src_data_valid (csp_4_vec_valid[3:0]),
.src_data_valid_urgent (csp_4_vec_valid_urgent[3:0]),
.src_data_in (csp_4_vec_data[43:0]),
.src_nexthop_in (csp_4_vec_nexthop[31:0]),
.src_dequeue (csp_4_vec_dequeue[3:0]),
.s1_nexthop_out (csp_s1_nexthop[39:32]),
.s1_valid (csp_s1_valid[4]),
.s1_valid_urgent (csp_s1_valid_urgent[4]),
.s2_data_out (csp_s2_data[54:44]),
.s2_nexthop_out (csp_s2_nexthop[39:32])
);
wire [3:0] fsp_5_vec_valid;
wire [3:0] fsp_5_vec_valid_urgent;
wire [143:0] fsp_5_vec_data;
wire [31:0] fsp_5_vec_nexthop;
wire [3:0] fsp_5_vec_dequeue;
wire [3:0] csp_5_vec_valid;
wire [3:0] csp_5_vec_valid_urgent;
wire [43:0] csp_5_vec_data;
wire [31:0] csp_5_vec_nexthop;
wire [3:0] csp_5_vec_dequeue;
wire [0:0] fdp_5_valid;
wire [35:0] fdp_5_data;
wire [4:0] fdp_5_nexthop;
wire [0:0] fdp_5_ack;
wire [0:0] cdp_5_valid;
wire [10:0] cdp_5_data;
wire [4:0] cdp_5_nexthop;
wire [0:0] cdp_5_ack;
Partition #(.DPID(5), .N(4)) part_5 (
.clock (clock),
.reset (reset),
.enable (enable),
.stop_injection (stop_injection),
.measure (measure),
.sim_time (sim_time),
.sim_time_tick (sim_time_tick),
.error (part_error[5]),
.is_quiescent (part_quiescent[5]),
.can_increment (part_can_increment[5]),
.config_in_valid (part_config_in_valid[5]),
.config_in (part_config_in[5]),
.config_out_valid (part_config_in_valid[6]),
.config_out (part_config_in[6]),
.ram_config_in_valid (part_ram_config_in_valid[5]),
.ram_config_in (part_ram_config_in[5]),
.ram_config_out_valid (part_ram_config_in_valid[6]),
.ram_config_out (part_ram_config_in[6]),
.stats_shift (stats_shift),
.stats_in (part_stats_in[5]),
.stats_out (part_stats_in[6]),
.fsp_vec_valid (fsp_5_vec_valid),
.fsp_vec_valid_urgent (fsp_5_vec_valid_urgent),
.fsp_vec_data (fsp_5_vec_data),
.fsp_vec_nexthop (fsp_5_vec_nexthop),
.fsp_vec_dequeue (fsp_5_vec_dequeue),
.csp_vec_valid (csp_5_vec_valid),
.csp_vec_valid_urgent (csp_5_vec_valid_urgent),
.csp_vec_data (csp_5_vec_data),
.csp_vec_nexthop (csp_5_vec_nexthop),
.csp_vec_dequeue (csp_5_vec_dequeue),
.fdp_valid (fdp_5_valid),
.fdp_data (fdp_5_data),
.fdp_nexthop (fdp_5_nexthop),
.fdp_ack (fdp_5_ack),
.cdp_valid (cdp_5_valid),
.cdp_data (cdp_5_data),
.cdp_nexthop (cdp_5_nexthop),
.cdp_ack (cdp_5_ack)
);
ICDestPart #(.PID(5), .NSP(8), .WIDTH(36)) fdp_5 (
.clock (clock),
.reset (reset),
.enable (enable),
.error (fdp_error[5]),
.src_s1_valid (fsp_s1_valid),
.src_s1_valid_urgent (fsp_s1_valid_urgent),
.src_s1_nexthop_in (fsp_s1_nexthop),
.src_s1_part_sel (fdp_select[5]),
.src_s2_data_in (fsp_s2_data),
.src_s2_nexthop_in (fsp_s2_nexthop),
.dequeue (fdp_5_ack),
.s3_data_out (fdp_5_data),
.s3_nexthop_out (fdp_5_nexthop),
.s3_data_valid (fdp_5_valid)
);
ICDestPart #(.PID(5), .NSP(8), .WIDTH(11)) cdp_5 (
.clock (clock),
.reset (reset),
.enable (enable),
.error (cdp_error[5]),
.src_s1_valid (csp_s1_valid),
.src_s1_valid_urgent (csp_s1_valid_urgent),
.src_s1_nexthop_in (csp_s1_nexthop),
.src_s1_part_sel (cdp_select[5]),
.src_s2_data_in (csp_s2_data),
.src_s2_nexthop_in (csp_s2_nexthop),
.dequeue (cdp_5_ack),
.s3_data_out (cdp_5_data),
.s3_nexthop_out (cdp_5_nexthop),
.s3_data_valid (cdp_5_valid)
);
ICSourcePart #(.N(4), .WIDTH(36)) fsp_5 (
.clock (clock),
.reset (reset),
.enable (enable),
.select (|fsp_select[5]),
.can_increment (fsp_can_increment[5]),
.src_data_valid (fsp_5_vec_valid[3:0]),
.src_data_valid_urgent (fsp_5_vec_valid_urgent[3:0]),
.src_data_in (fsp_5_vec_data[143:0]),
.src_nexthop_in (fsp_5_vec_nexthop[31:0]),
.src_dequeue (fsp_5_vec_dequeue[3:0]),
.s1_nexthop_out (fsp_s1_nexthop[47:40]),
.s1_valid (fsp_s1_valid[5]),
.s1_valid_urgent (fsp_s1_valid_urgent[5]),
.s2_data_out (fsp_s2_data[215:180]),
.s2_nexthop_out (fsp_s2_nexthop[47:40])
);
ICSourcePart #(.N(4), .WIDTH(11)) csp_5 (
.clock (clock),
.reset (reset),
.enable (enable),
.select (|csp_select[5]),
.can_increment (csp_can_increment[5]),
.src_data_valid (csp_5_vec_valid[3:0]),
.src_data_valid_urgent (csp_5_vec_valid_urgent[3:0]),
.src_data_in (csp_5_vec_data[43:0]),
.src_nexthop_in (csp_5_vec_nexthop[31:0]),
.src_dequeue (csp_5_vec_dequeue[3:0]),
.s1_nexthop_out (csp_s1_nexthop[47:40]),
.s1_valid (csp_s1_valid[5]),
.s1_valid_urgent (csp_s1_valid_urgent[5]),
.s2_data_out (csp_s2_data[65:55]),
.s2_nexthop_out (csp_s2_nexthop[47:40])
);
wire [3:0] fsp_6_vec_valid;
wire [3:0] fsp_6_vec_valid_urgent;
wire [143:0] fsp_6_vec_data;
wire [31:0] fsp_6_vec_nexthop;
wire [3:0] fsp_6_vec_dequeue;
wire [3:0] csp_6_vec_valid;
wire [3:0] csp_6_vec_valid_urgent;
wire [43:0] csp_6_vec_data;
wire [31:0] csp_6_vec_nexthop;
wire [3:0] csp_6_vec_dequeue;
wire [0:0] fdp_6_valid;
wire [35:0] fdp_6_data;
wire [4:0] fdp_6_nexthop;
wire [0:0] fdp_6_ack;
wire [0:0] cdp_6_valid;
wire [10:0] cdp_6_data;
wire [4:0] cdp_6_nexthop;
wire [0:0] cdp_6_ack;
Partition #(.DPID(6), .N(4)) part_6 (
.clock (clock),
.reset (reset),
.enable (enable),
.stop_injection (stop_injection),
.measure (measure),
.sim_time (sim_time),
.sim_time_tick (sim_time_tick),
.error (part_error[6]),
.is_quiescent (part_quiescent[6]),
.can_increment (part_can_increment[6]),
.config_in_valid (part_config_in_valid[6]),
.config_in (part_config_in[6]),
.config_out_valid (part_config_in_valid[7]),
.config_out (part_config_in[7]),
.ram_config_in_valid (part_ram_config_in_valid[6]),
.ram_config_in (part_ram_config_in[6]),
.ram_config_out_valid (part_ram_config_in_valid[7]),
.ram_config_out (part_ram_config_in[7]),
.stats_shift (stats_shift),
.stats_in (part_stats_in[6]),
.stats_out (part_stats_in[7]),
.fsp_vec_valid (fsp_6_vec_valid),
.fsp_vec_valid_urgent (fsp_6_vec_valid_urgent),
.fsp_vec_data (fsp_6_vec_data),
.fsp_vec_nexthop (fsp_6_vec_nexthop),
.fsp_vec_dequeue (fsp_6_vec_dequeue),
.csp_vec_valid (csp_6_vec_valid),
.csp_vec_valid_urgent (csp_6_vec_valid_urgent),
.csp_vec_data (csp_6_vec_data),
.csp_vec_nexthop (csp_6_vec_nexthop),
.csp_vec_dequeue (csp_6_vec_dequeue),
.fdp_valid (fdp_6_valid),
.fdp_data (fdp_6_data),
.fdp_nexthop (fdp_6_nexthop),
.fdp_ack (fdp_6_ack),
.cdp_valid (cdp_6_valid),
.cdp_data (cdp_6_data),
.cdp_nexthop (cdp_6_nexthop),
.cdp_ack (cdp_6_ack)
);
ICDestPart #(.PID(6), .NSP(8), .WIDTH(36)) fdp_6 (
.clock (clock),
.reset (reset),
.enable (enable),
.error (fdp_error[6]),
.src_s1_valid (fsp_s1_valid),
.src_s1_valid_urgent (fsp_s1_valid_urgent),
.src_s1_nexthop_in (fsp_s1_nexthop),
.src_s1_part_sel (fdp_select[6]),
.src_s2_data_in (fsp_s2_data),
.src_s2_nexthop_in (fsp_s2_nexthop),
.dequeue (fdp_6_ack),
.s3_data_out (fdp_6_data),
.s3_nexthop_out (fdp_6_nexthop),
.s3_data_valid (fdp_6_valid)
);
ICDestPart #(.PID(6), .NSP(8), .WIDTH(11)) cdp_6 (
.clock (clock),
.reset (reset),
.enable (enable),
.error (cdp_error[6]),
.src_s1_valid (csp_s1_valid),
.src_s1_valid_urgent (csp_s1_valid_urgent),
.src_s1_nexthop_in (csp_s1_nexthop),
.src_s1_part_sel (cdp_select[6]),
.src_s2_data_in (csp_s2_data),
.src_s2_nexthop_in (csp_s2_nexthop),
.dequeue (cdp_6_ack),
.s3_data_out (cdp_6_data),
.s3_nexthop_out (cdp_6_nexthop),
.s3_data_valid (cdp_6_valid)
);
ICSourcePart #(.N(4), .WIDTH(36)) fsp_6 (
.clock (clock),
.reset (reset),
.enable (enable),
.select (|fsp_select[6]),
.can_increment (fsp_can_increment[6]),
.src_data_valid (fsp_6_vec_valid[3:0]),
.src_data_valid_urgent (fsp_6_vec_valid_urgent[3:0]),
.src_data_in (fsp_6_vec_data[143:0]),
.src_nexthop_in (fsp_6_vec_nexthop[31:0]),
.src_dequeue (fsp_6_vec_dequeue[3:0]),
.s1_nexthop_out (fsp_s1_nexthop[55:48]),
.s1_valid (fsp_s1_valid[6]),
.s1_valid_urgent (fsp_s1_valid_urgent[6]),
.s2_data_out (fsp_s2_data[251:216]),
.s2_nexthop_out (fsp_s2_nexthop[55:48])
);
ICSourcePart #(.N(4), .WIDTH(11)) csp_6 (
.clock (clock),
.reset (reset),
.enable (enable),
.select (|csp_select[6]),
.can_increment (csp_can_increment[6]),
.src_data_valid (csp_6_vec_valid[3:0]),
.src_data_valid_urgent (csp_6_vec_valid_urgent[3:0]),
.src_data_in (csp_6_vec_data[43:0]),
.src_nexthop_in (csp_6_vec_nexthop[31:0]),
.src_dequeue (csp_6_vec_dequeue[3:0]),
.s1_nexthop_out (csp_s1_nexthop[55:48]),
.s1_valid (csp_s1_valid[6]),
.s1_valid_urgent (csp_s1_valid_urgent[6]),
.s2_data_out (csp_s2_data[76:66]),
.s2_nexthop_out (csp_s2_nexthop[55:48])
);
wire [3:0] fsp_7_vec_valid;
wire [3:0] fsp_7_vec_valid_urgent;
wire [143:0] fsp_7_vec_data;
wire [31:0] fsp_7_vec_nexthop;
wire [3:0] fsp_7_vec_dequeue;
wire [3:0] csp_7_vec_valid;
wire [3:0] csp_7_vec_valid_urgent;
wire [43:0] csp_7_vec_data;
wire [31:0] csp_7_vec_nexthop;
wire [3:0] csp_7_vec_dequeue;
wire [0:0] fdp_7_valid;
wire [35:0] fdp_7_data;
wire [4:0] fdp_7_nexthop;
wire [0:0] fdp_7_ack;
wire [0:0] cdp_7_valid;
wire [10:0] cdp_7_data;
wire [4:0] cdp_7_nexthop;
wire [0:0] cdp_7_ack;
Partition #(.DPID(7), .N(4)) part_7 (
.clock (clock),
.reset (reset),
.enable (enable),
.stop_injection (stop_injection),
.measure (measure),
.sim_time (sim_time),
.sim_time_tick (sim_time_tick),
.error (part_error[7]),
.is_quiescent (part_quiescent[7]),
.can_increment (part_can_increment[7]),
.config_in_valid (part_config_in_valid[7]),
.config_in (part_config_in[7]),
.config_out_valid (part_config_in_valid[8]),
.config_out (part_config_in[8]),
.ram_config_in_valid (part_ram_config_in_valid[7]),
.ram_config_in (part_ram_config_in[7]),
.ram_config_out_valid (part_ram_config_in_valid[8]),
.ram_config_out (part_ram_config_in[8]),
.stats_shift (stats_shift),
.stats_in (part_stats_in[7]),
.stats_out (part_stats_in[8]),
.fsp_vec_valid (fsp_7_vec_valid),
.fsp_vec_valid_urgent (fsp_7_vec_valid_urgent),
.fsp_vec_data (fsp_7_vec_data),
.fsp_vec_nexthop (fsp_7_vec_nexthop),
.fsp_vec_dequeue (fsp_7_vec_dequeue),
.csp_vec_valid (csp_7_vec_valid),
.csp_vec_valid_urgent (csp_7_vec_valid_urgent),
.csp_vec_data (csp_7_vec_data),
.csp_vec_nexthop (csp_7_vec_nexthop),
.csp_vec_dequeue (csp_7_vec_dequeue),
.fdp_valid (fdp_7_valid),
.fdp_data (fdp_7_data),
.fdp_nexthop (fdp_7_nexthop),
.fdp_ack (fdp_7_ack),
.cdp_valid (cdp_7_valid),
.cdp_data (cdp_7_data),
.cdp_nexthop (cdp_7_nexthop),
.cdp_ack (cdp_7_ack)
);
ICDestPart #(.PID(7), .NSP(8), .WIDTH(36)) fdp_7 (
.clock (clock),
.reset (reset),
.enable (enable),
.error (fdp_error[7]),
.src_s1_valid (fsp_s1_valid),
.src_s1_valid_urgent (fsp_s1_valid_urgent),
.src_s1_nexthop_in (fsp_s1_nexthop),
.src_s1_part_sel (fdp_select[7]),
.src_s2_data_in (fsp_s2_data),
.src_s2_nexthop_in (fsp_s2_nexthop),
.dequeue (fdp_7_ack),
.s3_data_out (fdp_7_data),
.s3_nexthop_out (fdp_7_nexthop),
.s3_data_valid (fdp_7_valid)
);
ICDestPart #(.PID(7), .NSP(8), .WIDTH(11)) cdp_7 (
.clock (clock),
.reset (reset),
.enable (enable),
.error (cdp_error[7]),
.src_s1_valid (csp_s1_valid),
.src_s1_valid_urgent (csp_s1_valid_urgent),
.src_s1_nexthop_in (csp_s1_nexthop),
.src_s1_part_sel (cdp_select[7]),
.src_s2_data_in (csp_s2_data),
.src_s2_nexthop_in (csp_s2_nexthop),
.dequeue (cdp_7_ack),
.s3_data_out (cdp_7_data),
.s3_nexthop_out (cdp_7_nexthop),
.s3_data_valid (cdp_7_valid)
);
ICSourcePart #(.N(4), .WIDTH(36)) fsp_7 (
.clock (clock),
.reset (reset),
.enable (enable),
.select (|fsp_select[7]),
.can_increment (fsp_can_increment[7]),
.src_data_valid (fsp_7_vec_valid[3:0]),
.src_data_valid_urgent (fsp_7_vec_valid_urgent[3:0]),
.src_data_in (fsp_7_vec_data[143:0]),
.src_nexthop_in (fsp_7_vec_nexthop[31:0]),
.src_dequeue (fsp_7_vec_dequeue[3:0]),
.s1_nexthop_out (fsp_s1_nexthop[63:56]),
.s1_valid (fsp_s1_valid[7]),
.s1_valid_urgent (fsp_s1_valid_urgent[7]),
.s2_data_out (fsp_s2_data[287:252]),
.s2_nexthop_out (fsp_s2_nexthop[63:56])
);
ICSourcePart #(.N(4), .WIDTH(11)) csp_7 (
.clock (clock),
.reset (reset),
.enable (enable),
.select (|csp_select[7]),
.can_increment (csp_can_increment[7]),
.src_data_valid (csp_7_vec_valid[3:0]),
.src_data_valid_urgent (csp_7_vec_valid_urgent[3:0]),
.src_data_in (csp_7_vec_data[43:0]),
.src_nexthop_in (csp_7_vec_nexthop[31:0]),
.src_dequeue (csp_7_vec_dequeue[3:0]),
.s1_nexthop_out (csp_s1_nexthop[63:56]),
.s1_valid (csp_s1_valid[7]),
.s1_valid_urgent (csp_s1_valid_urgent[7]),
.s2_data_out (csp_s2_data[87:77]),
.s2_nexthop_out (csp_s2_nexthop[63:56])
);
genvar i, j;
generate
for (j = 0; j < 8; j = j + 1)
begin : dp_sp_sel
for (i = 0; i < 8; i = i + 1)
begin: dp
assign fsp_select[j][i] = fdp_select[i][j];
assign csp_select[j][i] = cdp_select[i][j];
end
end
endgenerate
endmodule
|
module sim9_8x8 (
input clock,
input reset,
input enable,
input stop_injection,
input measure,
output reg [9:0] sim_time,
output sim_time_tick,
output error,
output [7:0] fdp_error,
output [7:0] cdp_error,
output [7:0] part_error,
output quiescent,
input [15:0] config_in,
input config_in_valid,
output [15:0] config_out,
output config_out_valid,
output [15:0] stats_out,
input stats_shift
);
// Internal states
reg tick_counter;
wire [0:0] can_increment;
wire [0:0] can_tick;
//wire [7:0] part_error;
wire [7:0] part_quiescent;
wire [7:0] part_can_increment;
wire [15:0] part_config_in [8:0];
wire [8:0] part_config_in_valid;
wire [15:0] part_ram_config_in [8:0];
wire [8:0] part_ram_config_in_valid;
wire [15:0] part_stats_in [8:0];
//wire [7:0] fdp_error;
wire [7:0] fdp_select [7:0];
//wire [7:0] cdp_error;
wire [7:0] cdp_select [7:0];
wire [7:0] fsp_select [7:0];
wire [7:0] fsp_can_increment;
wire [7:0] csp_select [7:0];
wire [7:0] csp_can_increment;
wire [63:0] fsp_s1_nexthop;
wire [7:0] fsp_s1_valid;
wire [7:0] fsp_s1_valid_urgent;
wire [287:0] fsp_s2_data;
wire [63:0] fsp_s2_nexthop;
wire [63:0] csp_s1_nexthop;
wire [7:0] csp_s1_valid;
wire [7:0] csp_s1_valid_urgent;
wire [87:0] csp_s2_data;
wire [63:0] csp_s2_nexthop;
assign sim_time_tick = enable & can_increment & can_tick;
assign error = (|part_error) | (|fdp_error) | (|cdp_error);
assign quiescent = &part_quiescent;
assign can_increment = (&part_can_increment) & (&fsp_can_increment) & (&csp_can_increment);
assign config_out = part_config_in[8];
assign config_out_valid = part_config_in_valid[8];
assign stats_out = part_stats_in[8];
assign part_config_in_valid[0] = config_in_valid;
assign part_config_in[0] = config_in;
assign part_ram_config_in_valid[0] = config_in_valid;
assign part_ram_config_in[0] = config_in;
assign part_stats_in[0] = 16'h0000;
wire [15:0] stats_in;
assign stats_in = 16'h0000;
always @(posedge clock)
begin
if (reset)
sim_time <= 16'h0;
else if (sim_time_tick)
sim_time <= sim_time + 1;
end
always @(posedge clock)
begin
if (reset)
tick_counter <= 1'b0;
else if (enable)
begin
if (sim_time_tick)
tick_counter <= 1'b0;
else if (~tick_counter)
tick_counter <= tick_counter + 1'b1;
end
end
assign can_tick = tick_counter;
wire [1:0] fsp_0_vec_valid;
wire [1:0] fsp_0_vec_valid_urgent;
wire [71:0] fsp_0_vec_data;
wire [15:0] fsp_0_vec_nexthop;
wire [1:0] fsp_0_vec_dequeue;
wire [1:0] csp_0_vec_valid;
wire [1:0] csp_0_vec_valid_urgent;
wire [21:0] csp_0_vec_data;
wire [15:0] csp_0_vec_nexthop;
wire [1:0] csp_0_vec_dequeue;
wire [0:0] fdp_0_valid;
wire [35:0] fdp_0_data;
wire [4:0] fdp_0_nexthop;
wire [0:0] fdp_0_ack;
wire [0:0] cdp_0_valid;
wire [10:0] cdp_0_data;
wire [4:0] cdp_0_nexthop;
wire [0:0] cdp_0_ack;
Partition #(.DPID(0), .N(2)) part_0 (
.clock (clock),
.reset (reset),
.enable (enable),
.stop_injection (stop_injection),
.measure (measure),
.sim_time (sim_time),
.sim_time_tick (sim_time_tick),
.error (part_error[0]),
.is_quiescent (part_quiescent[0]),
.can_increment (part_can_increment[0]),
.config_in_valid (part_config_in_valid[0]),
.config_in (part_config_in[0]),
.config_out_valid (part_config_in_valid[1]),
.config_out (part_config_in[1]),
.ram_config_in_valid (part_ram_config_in_valid[0]),
.ram_config_in (part_ram_config_in[0]),
.ram_config_out_valid (part_ram_config_in_valid[1]),
.ram_config_out (part_ram_config_in[1]),
.stats_shift (stats_shift),
.stats_in (part_stats_in[0]),
.stats_out (part_stats_in[1]),
.fsp_vec_valid (fsp_0_vec_valid),
.fsp_vec_valid_urgent (fsp_0_vec_valid_urgent),
.fsp_vec_data (fsp_0_vec_data),
.fsp_vec_nexthop (fsp_0_vec_nexthop),
.fsp_vec_dequeue (fsp_0_vec_dequeue),
.csp_vec_valid (csp_0_vec_valid),
.csp_vec_valid_urgent (csp_0_vec_valid_urgent),
.csp_vec_data (csp_0_vec_data),
.csp_vec_nexthop (csp_0_vec_nexthop),
.csp_vec_dequeue (csp_0_vec_dequeue),
.fdp_valid (fdp_0_valid),
.fdp_data (fdp_0_data),
.fdp_nexthop (fdp_0_nexthop),
.fdp_ack (fdp_0_ack),
.cdp_valid (cdp_0_valid),
.cdp_data (cdp_0_data),
.cdp_nexthop (cdp_0_nexthop),
.cdp_ack (cdp_0_ack)
);
ICDestPart #(.PID(0), .NSP(8), .WIDTH(36)) fdp_0 (
.clock (clock),
.reset (reset),
.enable (enable),
.error (fdp_error[0]),
.src_s1_valid (fsp_s1_valid),
.src_s1_valid_urgent (fsp_s1_valid_urgent),
.src_s1_nexthop_in (fsp_s1_nexthop),
.src_s1_part_sel (fdp_select[0]),
.src_s2_data_in (fsp_s2_data),
.src_s2_nexthop_in (fsp_s2_nexthop),
.dequeue (fdp_0_ack),
.s3_data_out (fdp_0_data),
.s3_nexthop_out (fdp_0_nexthop),
.s3_data_valid (fdp_0_valid)
);
ICDestPart #(.PID(0), .NSP(8), .WIDTH(11)) cdp_0 (
.clock (clock),
.reset (reset),
.enable (enable),
.error (cdp_error[0]),
.src_s1_valid (csp_s1_valid),
.src_s1_valid_urgent (csp_s1_valid_urgent),
.src_s1_nexthop_in (csp_s1_nexthop),
.src_s1_part_sel (cdp_select[0]),
.src_s2_data_in (csp_s2_data),
.src_s2_nexthop_in (csp_s2_nexthop),
.dequeue (cdp_0_ack),
.s3_data_out (cdp_0_data),
.s3_nexthop_out (cdp_0_nexthop),
.s3_data_valid (cdp_0_valid)
);
ICSourcePart #(.N(2), .WIDTH(36)) fsp_0 (
.clock (clock),
.reset (reset),
.enable (enable),
.select (|fsp_select[0]),
.can_increment (fsp_can_increment[0]),
.src_data_valid (fsp_0_vec_valid[1:0]),
.src_data_valid_urgent (fsp_0_vec_valid_urgent[1:0]),
.src_data_in (fsp_0_vec_data[71:0]),
.src_nexthop_in (fsp_0_vec_nexthop[15:0]),
.src_dequeue (fsp_0_vec_dequeue[1:0]),
.s1_nexthop_out (fsp_s1_nexthop[7:0]),
.s1_valid (fsp_s1_valid[0]),
.s1_valid_urgent (fsp_s1_valid_urgent[0]),
.s2_data_out (fsp_s2_data[35:0]),
.s2_nexthop_out (fsp_s2_nexthop[7:0])
);
ICSourcePart #(.N(2), .WIDTH(11)) csp_0 (
.clock (clock),
.reset (reset),
.enable (enable),
.select (|csp_select[0]),
.can_increment (csp_can_increment[0]),
.src_data_valid (csp_0_vec_valid[1:0]),
.src_data_valid_urgent (csp_0_vec_valid_urgent[1:0]),
.src_data_in (csp_0_vec_data[21:0]),
.src_nexthop_in (csp_0_vec_nexthop[15:0]),
.src_dequeue (csp_0_vec_dequeue[1:0]),
.s1_nexthop_out (csp_s1_nexthop[7:0]),
.s1_valid (csp_s1_valid[0]),
.s1_valid_urgent (csp_s1_valid_urgent[0]),
.s2_data_out (csp_s2_data[10:0]),
.s2_nexthop_out (csp_s2_nexthop[7:0])
);
wire [0:0] fsp_1_vec_valid;
wire [0:0] fsp_1_vec_valid_urgent;
wire [35:0] fsp_1_vec_data;
wire [7:0] fsp_1_vec_nexthop;
wire [0:0] fsp_1_vec_dequeue;
wire [0:0] csp_1_vec_valid;
wire [0:0] csp_1_vec_valid_urgent;
wire [10:0] csp_1_vec_data;
wire [7:0] csp_1_vec_nexthop;
wire [0:0] csp_1_vec_dequeue;
wire [0:0] fdp_1_valid;
wire [35:0] fdp_1_data;
wire [4:0] fdp_1_nexthop;
wire [0:0] fdp_1_ack;
wire [0:0] cdp_1_valid;
wire [10:0] cdp_1_data;
wire [4:0] cdp_1_nexthop;
wire [0:0] cdp_1_ack;
Partition #(.DPID(1), .N(1)) part_1 (
.clock (clock),
.reset (reset),
.enable (enable),
.stop_injection (stop_injection),
.measure (measure),
.sim_time (sim_time),
.sim_time_tick (sim_time_tick),
.error (part_error[1]),
.is_quiescent (part_quiescent[1]),
.can_increment (part_can_increment[1]),
.config_in_valid (part_config_in_valid[1]),
.config_in (part_config_in[1]),
.config_out_valid (part_config_in_valid[2]),
.config_out (part_config_in[2]),
.ram_config_in_valid (part_ram_config_in_valid[1]),
.ram_config_in (part_ram_config_in[1]),
.ram_config_out_valid (part_ram_config_in_valid[2]),
.ram_config_out (part_ram_config_in[2]),
.stats_shift (stats_shift),
.stats_in (part_stats_in[1]),
.stats_out (part_stats_in[2]),
.fsp_vec_valid (fsp_1_vec_valid),
.fsp_vec_valid_urgent (fsp_1_vec_valid_urgent),
.fsp_vec_data (fsp_1_vec_data),
.fsp_vec_nexthop (fsp_1_vec_nexthop),
.fsp_vec_dequeue (fsp_1_vec_dequeue),
.csp_vec_valid (csp_1_vec_valid),
.csp_vec_valid_urgent (csp_1_vec_valid_urgent),
.csp_vec_data (csp_1_vec_data),
.csp_vec_nexthop (csp_1_vec_nexthop),
.csp_vec_dequeue (csp_1_vec_dequeue),
.fdp_valid (fdp_1_valid),
.fdp_data (fdp_1_data),
.fdp_nexthop (fdp_1_nexthop),
.fdp_ack (fdp_1_ack),
.cdp_valid (cdp_1_valid),
.cdp_data (cdp_1_data),
.cdp_nexthop (cdp_1_nexthop),
.cdp_ack (cdp_1_ack)
);
ICDestPart #(.PID(1), .NSP(8), .WIDTH(36)) fdp_1 (
.clock (clock),
.reset (reset),
.enable (enable),
.error (fdp_error[1]),
.src_s1_valid (fsp_s1_valid),
.src_s1_valid_urgent (fsp_s1_valid_urgent),
.src_s1_nexthop_in (fsp_s1_nexthop),
.src_s1_part_sel (fdp_select[1]),
.src_s2_data_in (fsp_s2_data),
.src_s2_nexthop_in (fsp_s2_nexthop),
.dequeue (fdp_1_ack),
.s3_data_out (fdp_1_data),
.s3_nexthop_out (fdp_1_nexthop),
.s3_data_valid (fdp_1_valid)
);
ICDestPart #(.PID(1), .NSP(8), .WIDTH(11)) cdp_1 (
.clock (clock),
.reset (reset),
.enable (enable),
.error (cdp_error[1]),
.src_s1_valid (csp_s1_valid),
.src_s1_valid_urgent (csp_s1_valid_urgent),
.src_s1_nexthop_in (csp_s1_nexthop),
.src_s1_part_sel (cdp_select[1]),
.src_s2_data_in (csp_s2_data),
.src_s2_nexthop_in (csp_s2_nexthop),
.dequeue (cdp_1_ack),
.s3_data_out (cdp_1_data),
.s3_nexthop_out (cdp_1_nexthop),
.s3_data_valid (cdp_1_valid)
);
ICSourcePart #(.N(1), .WIDTH(36)) fsp_1 (
.clock (clock),
.reset (reset),
.enable (enable),
.select (|fsp_select[1]),
.can_increment (fsp_can_increment[1]),
.src_data_valid (fsp_1_vec_valid[0:0]),
.src_data_valid_urgent (fsp_1_vec_valid_urgent[0:0]),
.src_data_in (fsp_1_vec_data[35:0]),
.src_nexthop_in (fsp_1_vec_nexthop[7:0]),
.src_dequeue (fsp_1_vec_dequeue[0:0]),
.s1_nexthop_out (fsp_s1_nexthop[15:8]),
.s1_valid (fsp_s1_valid[1]),
.s1_valid_urgent (fsp_s1_valid_urgent[1]),
.s2_data_out (fsp_s2_data[71:36]),
.s2_nexthop_out (fsp_s2_nexthop[15:8])
);
ICSourcePart #(.N(1), .WIDTH(11)) csp_1 (
.clock (clock),
.reset (reset),
.enable (enable),
.select (|csp_select[1]),
.can_increment (csp_can_increment[1]),
.src_data_valid (csp_1_vec_valid[0:0]),
.src_data_valid_urgent (csp_1_vec_valid_urgent[0:0]),
.src_data_in (csp_1_vec_data[10:0]),
.src_nexthop_in (csp_1_vec_nexthop[7:0]),
.src_dequeue (csp_1_vec_dequeue[0:0]),
.s1_nexthop_out (csp_s1_nexthop[15:8]),
.s1_valid (csp_s1_valid[1]),
.s1_valid_urgent (csp_s1_valid_urgent[1]),
.s2_data_out (csp_s2_data[21:11]),
.s2_nexthop_out (csp_s2_nexthop[15:8])
);
wire [0:0] fsp_2_vec_valid;
wire [0:0] fsp_2_vec_valid_urgent;
wire [35:0] fsp_2_vec_data;
wire [7:0] fsp_2_vec_nexthop;
wire [0:0] fsp_2_vec_dequeue;
wire [0:0] csp_2_vec_valid;
wire [0:0] csp_2_vec_valid_urgent;
wire [10:0] csp_2_vec_data;
wire [7:0] csp_2_vec_nexthop;
wire [0:0] csp_2_vec_dequeue;
wire [0:0] fdp_2_valid;
wire [35:0] fdp_2_data;
wire [4:0] fdp_2_nexthop;
wire [0:0] fdp_2_ack;
wire [0:0] cdp_2_valid;
wire [10:0] cdp_2_data;
wire [4:0] cdp_2_nexthop;
wire [0:0] cdp_2_ack;
Partition #(.DPID(2), .N(1)) part_2 (
.clock (clock),
.reset (reset),
.enable (enable),
.stop_injection (stop_injection),
.measure (measure),
.sim_time (sim_time),
.sim_time_tick (sim_time_tick),
.error (part_error[2]),
.is_quiescent (part_quiescent[2]),
.can_increment (part_can_increment[2]),
.config_in_valid (part_config_in_valid[2]),
.config_in (part_config_in[2]),
.config_out_valid (part_config_in_valid[3]),
.config_out (part_config_in[3]),
.ram_config_in_valid (part_ram_config_in_valid[2]),
.ram_config_in (part_ram_config_in[2]),
.ram_config_out_valid (part_ram_config_in_valid[3]),
.ram_config_out (part_ram_config_in[3]),
.stats_shift (stats_shift),
.stats_in (part_stats_in[2]),
.stats_out (part_stats_in[3]),
.fsp_vec_valid (fsp_2_vec_valid),
.fsp_vec_valid_urgent (fsp_2_vec_valid_urgent),
.fsp_vec_data (fsp_2_vec_data),
.fsp_vec_nexthop (fsp_2_vec_nexthop),
.fsp_vec_dequeue (fsp_2_vec_dequeue),
.csp_vec_valid (csp_2_vec_valid),
.csp_vec_valid_urgent (csp_2_vec_valid_urgent),
.csp_vec_data (csp_2_vec_data),
.csp_vec_nexthop (csp_2_vec_nexthop),
.csp_vec_dequeue (csp_2_vec_dequeue),
.fdp_valid (fdp_2_valid),
.fdp_data (fdp_2_data),
.fdp_nexthop (fdp_2_nexthop),
.fdp_ack (fdp_2_ack),
.cdp_valid (cdp_2_valid),
.cdp_data (cdp_2_data),
.cdp_nexthop (cdp_2_nexthop),
.cdp_ack (cdp_2_ack)
);
ICDestPart #(.PID(2), .NSP(8), .WIDTH(36)) fdp_2 (
.clock (clock),
.reset (reset),
.enable (enable),
.error (fdp_error[2]),
.src_s1_valid (fsp_s1_valid),
.src_s1_valid_urgent (fsp_s1_valid_urgent),
.src_s1_nexthop_in (fsp_s1_nexthop),
.src_s1_part_sel (fdp_select[2]),
.src_s2_data_in (fsp_s2_data),
.src_s2_nexthop_in (fsp_s2_nexthop),
.dequeue (fdp_2_ack),
.s3_data_out (fdp_2_data),
.s3_nexthop_out (fdp_2_nexthop),
.s3_data_valid (fdp_2_valid)
);
ICDestPart #(.PID(2), .NSP(8), .WIDTH(11)) cdp_2 (
.clock (clock),
.reset (reset),
.enable (enable),
.error (cdp_error[2]),
.src_s1_valid (csp_s1_valid),
.src_s1_valid_urgent (csp_s1_valid_urgent),
.src_s1_nexthop_in (csp_s1_nexthop),
.src_s1_part_sel (cdp_select[2]),
.src_s2_data_in (csp_s2_data),
.src_s2_nexthop_in (csp_s2_nexthop),
.dequeue (cdp_2_ack),
.s3_data_out (cdp_2_data),
.s3_nexthop_out (cdp_2_nexthop),
.s3_data_valid (cdp_2_valid)
);
ICSourcePart #(.N(1), .WIDTH(36)) fsp_2 (
.clock (clock),
.reset (reset),
.enable (enable),
.select (|fsp_select[2]),
.can_increment (fsp_can_increment[2]),
.src_data_valid (fsp_2_vec_valid[0:0]),
.src_data_valid_urgent (fsp_2_vec_valid_urgent[0:0]),
.src_data_in (fsp_2_vec_data[35:0]),
.src_nexthop_in (fsp_2_vec_nexthop[7:0]),
.src_dequeue (fsp_2_vec_dequeue[0:0]),
.s1_nexthop_out (fsp_s1_nexthop[23:16]),
.s1_valid (fsp_s1_valid[2]),
.s1_valid_urgent (fsp_s1_valid_urgent[2]),
.s2_data_out (fsp_s2_data[107:72]),
.s2_nexthop_out (fsp_s2_nexthop[23:16])
);
ICSourcePart #(.N(1), .WIDTH(11)) csp_2 (
.clock (clock),
.reset (reset),
.enable (enable),
.select (|csp_select[2]),
.can_increment (csp_can_increment[2]),
.src_data_valid (csp_2_vec_valid[0:0]),
.src_data_valid_urgent (csp_2_vec_valid_urgent[0:0]),
.src_data_in (csp_2_vec_data[10:0]),
.src_nexthop_in (csp_2_vec_nexthop[7:0]),
.src_dequeue (csp_2_vec_dequeue[0:0]),
.s1_nexthop_out (csp_s1_nexthop[23:16]),
.s1_valid (csp_s1_valid[2]),
.s1_valid_urgent (csp_s1_valid_urgent[2]),
.s2_data_out (csp_s2_data[32:22]),
.s2_nexthop_out (csp_s2_nexthop[23:16])
);
wire [0:0] fsp_3_vec_valid;
wire [0:0] fsp_3_vec_valid_urgent;
wire [35:0] fsp_3_vec_data;
wire [7:0] fsp_3_vec_nexthop;
wire [0:0] fsp_3_vec_dequeue;
wire [0:0] csp_3_vec_valid;
wire [0:0] csp_3_vec_valid_urgent;
wire [10:0] csp_3_vec_data;
wire [7:0] csp_3_vec_nexthop;
wire [0:0] csp_3_vec_dequeue;
wire [0:0] fdp_3_valid;
wire [35:0] fdp_3_data;
wire [4:0] fdp_3_nexthop;
wire [0:0] fdp_3_ack;
wire [0:0] cdp_3_valid;
wire [10:0] cdp_3_data;
wire [4:0] cdp_3_nexthop;
wire [0:0] cdp_3_ack;
Partition #(.DPID(3), .N(1)) part_3 (
.clock (clock),
.reset (reset),
.enable (enable),
.stop_injection (stop_injection),
.measure (measure),
.sim_time (sim_time),
.sim_time_tick (sim_time_tick),
.error (part_error[3]),
.is_quiescent (part_quiescent[3]),
.can_increment (part_can_increment[3]),
.config_in_valid (part_config_in_valid[3]),
.config_in (part_config_in[3]),
.config_out_valid (part_config_in_valid[4]),
.config_out (part_config_in[4]),
.ram_config_in_valid (part_ram_config_in_valid[3]),
.ram_config_in (part_ram_config_in[3]),
.ram_config_out_valid (part_ram_config_in_valid[4]),
.ram_config_out (part_ram_config_in[4]),
.stats_shift (stats_shift),
.stats_in (part_stats_in[3]),
.stats_out (part_stats_in[4]),
.fsp_vec_valid (fsp_3_vec_valid),
.fsp_vec_valid_urgent (fsp_3_vec_valid_urgent),
.fsp_vec_data (fsp_3_vec_data),
.fsp_vec_nexthop (fsp_3_vec_nexthop),
.fsp_vec_dequeue (fsp_3_vec_dequeue),
.csp_vec_valid (csp_3_vec_valid),
.csp_vec_valid_urgent (csp_3_vec_valid_urgent),
.csp_vec_data (csp_3_vec_data),
.csp_vec_nexthop (csp_3_vec_nexthop),
.csp_vec_dequeue (csp_3_vec_dequeue),
.fdp_valid (fdp_3_valid),
.fdp_data (fdp_3_data),
.fdp_nexthop (fdp_3_nexthop),
.fdp_ack (fdp_3_ack),
.cdp_valid (cdp_3_valid),
.cdp_data (cdp_3_data),
.cdp_nexthop (cdp_3_nexthop),
.cdp_ack (cdp_3_ack)
);
ICDestPart #(.PID(3), .NSP(8), .WIDTH(36)) fdp_3 (
.clock (clock),
.reset (reset),
.enable (enable),
.error (fdp_error[3]),
.src_s1_valid (fsp_s1_valid),
.src_s1_valid_urgent (fsp_s1_valid_urgent),
.src_s1_nexthop_in (fsp_s1_nexthop),
.src_s1_part_sel (fdp_select[3]),
.src_s2_data_in (fsp_s2_data),
.src_s2_nexthop_in (fsp_s2_nexthop),
.dequeue (fdp_3_ack),
.s3_data_out (fdp_3_data),
.s3_nexthop_out (fdp_3_nexthop),
.s3_data_valid (fdp_3_valid)
);
ICDestPart #(.PID(3), .NSP(8), .WIDTH(11)) cdp_3 (
.clock (clock),
.reset (reset),
.enable (enable),
.error (cdp_error[3]),
.src_s1_valid (csp_s1_valid),
.src_s1_valid_urgent (csp_s1_valid_urgent),
.src_s1_nexthop_in (csp_s1_nexthop),
.src_s1_part_sel (cdp_select[3]),
.src_s2_data_in (csp_s2_data),
.src_s2_nexthop_in (csp_s2_nexthop),
.dequeue (cdp_3_ack),
.s3_data_out (cdp_3_data),
.s3_nexthop_out (cdp_3_nexthop),
.s3_data_valid (cdp_3_valid)
);
ICSourcePart #(.N(1), .WIDTH(36)) fsp_3 (
.clock (clock),
.reset (reset),
.enable (enable),
.select (|fsp_select[3]),
.can_increment (fsp_can_increment[3]),
.src_data_valid (fsp_3_vec_valid[0:0]),
.src_data_valid_urgent (fsp_3_vec_valid_urgent[0:0]),
.src_data_in (fsp_3_vec_data[35:0]),
.src_nexthop_in (fsp_3_vec_nexthop[7:0]),
.src_dequeue (fsp_3_vec_dequeue[0:0]),
.s1_nexthop_out (fsp_s1_nexthop[31:24]),
.s1_valid (fsp_s1_valid[3]),
.s1_valid_urgent (fsp_s1_valid_urgent[3]),
.s2_data_out (fsp_s2_data[143:108]),
.s2_nexthop_out (fsp_s2_nexthop[31:24])
);
ICSourcePart #(.N(1), .WIDTH(11)) csp_3 (
.clock (clock),
.reset (reset),
.enable (enable),
.select (|csp_select[3]),
.can_increment (csp_can_increment[3]),
.src_data_valid (csp_3_vec_valid[0:0]),
.src_data_valid_urgent (csp_3_vec_valid_urgent[0:0]),
.src_data_in (csp_3_vec_data[10:0]),
.src_nexthop_in (csp_3_vec_nexthop[7:0]),
.src_dequeue (csp_3_vec_dequeue[0:0]),
.s1_nexthop_out (csp_s1_nexthop[31:24]),
.s1_valid (csp_s1_valid[3]),
.s1_valid_urgent (csp_s1_valid_urgent[3]),
.s2_data_out (csp_s2_data[43:33]),
.s2_nexthop_out (csp_s2_nexthop[31:24])
);
wire [0:0] fsp_4_vec_valid;
wire [0:0] fsp_4_vec_valid_urgent;
wire [35:0] fsp_4_vec_data;
wire [7:0] fsp_4_vec_nexthop;
wire [0:0] fsp_4_vec_dequeue;
wire [0:0] csp_4_vec_valid;
wire [0:0] csp_4_vec_valid_urgent;
wire [10:0] csp_4_vec_data;
wire [7:0] csp_4_vec_nexthop;
wire [0:0] csp_4_vec_dequeue;
wire [0:0] fdp_4_valid;
wire [35:0] fdp_4_data;
wire [4:0] fdp_4_nexthop;
wire [0:0] fdp_4_ack;
wire [0:0] cdp_4_valid;
wire [10:0] cdp_4_data;
wire [4:0] cdp_4_nexthop;
wire [0:0] cdp_4_ack;
Partition #(.DPID(4), .N(1)) part_4 (
.clock (clock),
.reset (reset),
.enable (enable),
.stop_injection (stop_injection),
.measure (measure),
.sim_time (sim_time),
.sim_time_tick (sim_time_tick),
.error (part_error[4]),
.is_quiescent (part_quiescent[4]),
.can_increment (part_can_increment[4]),
.config_in_valid (part_config_in_valid[4]),
.config_in (part_config_in[4]),
.config_out_valid (part_config_in_valid[5]),
.config_out (part_config_in[5]),
.ram_config_in_valid (part_ram_config_in_valid[4]),
.ram_config_in (part_ram_config_in[4]),
.ram_config_out_valid (part_ram_config_in_valid[5]),
.ram_config_out (part_ram_config_in[5]),
.stats_shift (stats_shift),
.stats_in (part_stats_in[4]),
.stats_out (part_stats_in[5]),
.fsp_vec_valid (fsp_4_vec_valid),
.fsp_vec_valid_urgent (fsp_4_vec_valid_urgent),
.fsp_vec_data (fsp_4_vec_data),
.fsp_vec_nexthop (fsp_4_vec_nexthop),
.fsp_vec_dequeue (fsp_4_vec_dequeue),
.csp_vec_valid (csp_4_vec_valid),
.csp_vec_valid_urgent (csp_4_vec_valid_urgent),
.csp_vec_data (csp_4_vec_data),
.csp_vec_nexthop (csp_4_vec_nexthop),
.csp_vec_dequeue (csp_4_vec_dequeue),
.fdp_valid (fdp_4_valid),
.fdp_data (fdp_4_data),
.fdp_nexthop (fdp_4_nexthop),
.fdp_ack (fdp_4_ack),
.cdp_valid (cdp_4_valid),
.cdp_data (cdp_4_data),
.cdp_nexthop (cdp_4_nexthop),
.cdp_ack (cdp_4_ack)
);
ICDestPart #(.PID(4), .NSP(8), .WIDTH(36)) fdp_4 (
.clock (clock),
.reset (reset),
.enable (enable),
.error (fdp_error[4]),
.src_s1_valid (fsp_s1_valid),
.src_s1_valid_urgent (fsp_s1_valid_urgent),
.src_s1_nexthop_in (fsp_s1_nexthop),
.src_s1_part_sel (fdp_select[4]),
.src_s2_data_in (fsp_s2_data),
.src_s2_nexthop_in (fsp_s2_nexthop),
.dequeue (fdp_4_ack),
.s3_data_out (fdp_4_data),
.s3_nexthop_out (fdp_4_nexthop),
.s3_data_valid (fdp_4_valid)
);
ICDestPart #(.PID(4), .NSP(8), .WIDTH(11)) cdp_4 (
.clock (clock),
.reset (reset),
.enable (enable),
.error (cdp_error[4]),
.src_s1_valid (csp_s1_valid),
.src_s1_valid_urgent (csp_s1_valid_urgent),
.src_s1_nexthop_in (csp_s1_nexthop),
.src_s1_part_sel (cdp_select[4]),
.src_s2_data_in (csp_s2_data),
.src_s2_nexthop_in (csp_s2_nexthop),
.dequeue (cdp_4_ack),
.s3_data_out (cdp_4_data),
.s3_nexthop_out (cdp_4_nexthop),
.s3_data_valid (cdp_4_valid)
);
ICSourcePart #(.N(1), .WIDTH(36)) fsp_4 (
.clock (clock),
.reset (reset),
.enable (enable),
.select (|fsp_select[4]),
.can_increment (fsp_can_increment[4]),
.src_data_valid (fsp_4_vec_valid[0:0]),
.src_data_valid_urgent (fsp_4_vec_valid_urgent[0:0]),
.src_data_in (fsp_4_vec_data[35:0]),
.src_nexthop_in (fsp_4_vec_nexthop[7:0]),
.src_dequeue (fsp_4_vec_dequeue[0:0]),
.s1_nexthop_out (fsp_s1_nexthop[39:32]),
.s1_valid (fsp_s1_valid[4]),
.s1_valid_urgent (fsp_s1_valid_urgent[4]),
.s2_data_out (fsp_s2_data[179:144]),
.s2_nexthop_out (fsp_s2_nexthop[39:32])
);
ICSourcePart #(.N(1), .WIDTH(11)) csp_4 (
.clock (clock),
.reset (reset),
.enable (enable),
.select (|csp_select[4]),
.can_increment (csp_can_increment[4]),
.src_data_valid (csp_4_vec_valid[0:0]),
.src_data_valid_urgent (csp_4_vec_valid_urgent[0:0]),
.src_data_in (csp_4_vec_data[10:0]),
.src_nexthop_in (csp_4_vec_nexthop[7:0]),
.src_dequeue (csp_4_vec_dequeue[0:0]),
.s1_nexthop_out (csp_s1_nexthop[39:32]),
.s1_valid (csp_s1_valid[4]),
.s1_valid_urgent (csp_s1_valid_urgent[4]),
.s2_data_out (csp_s2_data[54:44]),
.s2_nexthop_out (csp_s2_nexthop[39:32])
);
wire [0:0] fsp_5_vec_valid;
wire [0:0] fsp_5_vec_valid_urgent;
wire [35:0] fsp_5_vec_data;
wire [7:0] fsp_5_vec_nexthop;
wire [0:0] fsp_5_vec_dequeue;
wire [0:0] csp_5_vec_valid;
wire [0:0] csp_5_vec_valid_urgent;
wire [10:0] csp_5_vec_data;
wire [7:0] csp_5_vec_nexthop;
wire [0:0] csp_5_vec_dequeue;
wire [0:0] fdp_5_valid;
wire [35:0] fdp_5_data;
wire [4:0] fdp_5_nexthop;
wire [0:0] fdp_5_ack;
wire [0:0] cdp_5_valid;
wire [10:0] cdp_5_data;
wire [4:0] cdp_5_nexthop;
wire [0:0] cdp_5_ack;
Partition #(.DPID(5), .N(1)) part_5 (
.clock (clock),
.reset (reset),
.enable (enable),
.stop_injection (stop_injection),
.measure (measure),
.sim_time (sim_time),
.sim_time_tick (sim_time_tick),
.error (part_error[5]),
.is_quiescent (part_quiescent[5]),
.can_increment (part_can_increment[5]),
.config_in_valid (part_config_in_valid[5]),
.config_in (part_config_in[5]),
.config_out_valid (part_config_in_valid[6]),
.config_out (part_config_in[6]),
.ram_config_in_valid (part_ram_config_in_valid[5]),
.ram_config_in (part_ram_config_in[5]),
.ram_config_out_valid (part_ram_config_in_valid[6]),
.ram_config_out (part_ram_config_in[6]),
.stats_shift (stats_shift),
.stats_in (part_stats_in[5]),
.stats_out (part_stats_in[6]),
.fsp_vec_valid (fsp_5_vec_valid),
.fsp_vec_valid_urgent (fsp_5_vec_valid_urgent),
.fsp_vec_data (fsp_5_vec_data),
.fsp_vec_nexthop (fsp_5_vec_nexthop),
.fsp_vec_dequeue (fsp_5_vec_dequeue),
.csp_vec_valid (csp_5_vec_valid),
.csp_vec_valid_urgent (csp_5_vec_valid_urgent),
.csp_vec_data (csp_5_vec_data),
.csp_vec_nexthop (csp_5_vec_nexthop),
.csp_vec_dequeue (csp_5_vec_dequeue),
.fdp_valid (fdp_5_valid),
.fdp_data (fdp_5_data),
.fdp_nexthop (fdp_5_nexthop),
.fdp_ack (fdp_5_ack),
.cdp_valid (cdp_5_valid),
.cdp_data (cdp_5_data),
.cdp_nexthop (cdp_5_nexthop),
.cdp_ack (cdp_5_ack)
);
ICDestPart #(.PID(5), .NSP(8), .WIDTH(36)) fdp_5 (
.clock (clock),
.reset (reset),
.enable (enable),
.error (fdp_error[5]),
.src_s1_valid (fsp_s1_valid),
.src_s1_valid_urgent (fsp_s1_valid_urgent),
.src_s1_nexthop_in (fsp_s1_nexthop),
.src_s1_part_sel (fdp_select[5]),
.src_s2_data_in (fsp_s2_data),
.src_s2_nexthop_in (fsp_s2_nexthop),
.dequeue (fdp_5_ack),
.s3_data_out (fdp_5_data),
.s3_nexthop_out (fdp_5_nexthop),
.s3_data_valid (fdp_5_valid)
);
ICDestPart #(.PID(5), .NSP(8), .WIDTH(11)) cdp_5 (
.clock (clock),
.reset (reset),
.enable (enable),
.error (cdp_error[5]),
.src_s1_valid (csp_s1_valid),
.src_s1_valid_urgent (csp_s1_valid_urgent),
.src_s1_nexthop_in (csp_s1_nexthop),
.src_s1_part_sel (cdp_select[5]),
.src_s2_data_in (csp_s2_data),
.src_s2_nexthop_in (csp_s2_nexthop),
.dequeue (cdp_5_ack),
.s3_data_out (cdp_5_data),
.s3_nexthop_out (cdp_5_nexthop),
.s3_data_valid (cdp_5_valid)
);
ICSourcePart #(.N(1), .WIDTH(36)) fsp_5 (
.clock (clock),
.reset (reset),
.enable (enable),
.select (|fsp_select[5]),
.can_increment (fsp_can_increment[5]),
.src_data_valid (fsp_5_vec_valid[0:0]),
.src_data_valid_urgent (fsp_5_vec_valid_urgent[0:0]),
.src_data_in (fsp_5_vec_data[35:0]),
.src_nexthop_in (fsp_5_vec_nexthop[7:0]),
.src_dequeue (fsp_5_vec_dequeue[0:0]),
.s1_nexthop_out (fsp_s1_nexthop[47:40]),
.s1_valid (fsp_s1_valid[5]),
.s1_valid_urgent (fsp_s1_valid_urgent[5]),
.s2_data_out (fsp_s2_data[215:180]),
.s2_nexthop_out (fsp_s2_nexthop[47:40])
);
ICSourcePart #(.N(1), .WIDTH(11)) csp_5 (
.clock (clock),
.reset (reset),
.enable (enable),
.select (|csp_select[5]),
.can_increment (csp_can_increment[5]),
.src_data_valid (csp_5_vec_valid[0:0]),
.src_data_valid_urgent (csp_5_vec_valid_urgent[0:0]),
.src_data_in (csp_5_vec_data[10:0]),
.src_nexthop_in (csp_5_vec_nexthop[7:0]),
.src_dequeue (csp_5_vec_dequeue[0:0]),
.s1_nexthop_out (csp_s1_nexthop[47:40]),
.s1_valid (csp_s1_valid[5]),
.s1_valid_urgent (csp_s1_valid_urgent[5]),
.s2_data_out (csp_s2_data[65:55]),
.s2_nexthop_out (csp_s2_nexthop[47:40])
);
wire [0:0] fsp_6_vec_valid;
wire [0:0] fsp_6_vec_valid_urgent;
wire [35:0] fsp_6_vec_data;
wire [7:0] fsp_6_vec_nexthop;
wire [0:0] fsp_6_vec_dequeue;
wire [0:0] csp_6_vec_valid;
wire [0:0] csp_6_vec_valid_urgent;
wire [10:0] csp_6_vec_data;
wire [7:0] csp_6_vec_nexthop;
wire [0:0] csp_6_vec_dequeue;
wire [0:0] fdp_6_valid;
wire [35:0] fdp_6_data;
wire [4:0] fdp_6_nexthop;
wire [0:0] fdp_6_ack;
wire [0:0] cdp_6_valid;
wire [10:0] cdp_6_data;
wire [4:0] cdp_6_nexthop;
wire [0:0] cdp_6_ack;
Partition #(.DPID(6), .N(1)) part_6 (
.clock (clock),
.reset (reset),
.enable (enable),
.stop_injection (stop_injection),
.measure (measure),
.sim_time (sim_time),
.sim_time_tick (sim_time_tick),
.error (part_error[6]),
.is_quiescent (part_quiescent[6]),
.can_increment (part_can_increment[6]),
.config_in_valid (part_config_in_valid[6]),
.config_in (part_config_in[6]),
.config_out_valid (part_config_in_valid[7]),
.config_out (part_config_in[7]),
.ram_config_in_valid (part_ram_config_in_valid[6]),
.ram_config_in (part_ram_config_in[6]),
.ram_config_out_valid (part_ram_config_in_valid[7]),
.ram_config_out (part_ram_config_in[7]),
.stats_shift (stats_shift),
.stats_in (part_stats_in[6]),
.stats_out (part_stats_in[7]),
.fsp_vec_valid (fsp_6_vec_valid),
.fsp_vec_valid_urgent (fsp_6_vec_valid_urgent),
.fsp_vec_data (fsp_6_vec_data),
.fsp_vec_nexthop (fsp_6_vec_nexthop),
.fsp_vec_dequeue (fsp_6_vec_dequeue),
.csp_vec_valid (csp_6_vec_valid),
.csp_vec_valid_urgent (csp_6_vec_valid_urgent),
.csp_vec_data (csp_6_vec_data),
.csp_vec_nexthop (csp_6_vec_nexthop),
.csp_vec_dequeue (csp_6_vec_dequeue),
.fdp_valid (fdp_6_valid),
.fdp_data (fdp_6_data),
.fdp_nexthop (fdp_6_nexthop),
.fdp_ack (fdp_6_ack),
.cdp_valid (cdp_6_valid),
.cdp_data (cdp_6_data),
.cdp_nexthop (cdp_6_nexthop),
.cdp_ack (cdp_6_ack)
);
ICDestPart #(.PID(6), .NSP(8), .WIDTH(36)) fdp_6 (
.clock (clock),
.reset (reset),
.enable (enable),
.error (fdp_error[6]),
.src_s1_valid (fsp_s1_valid),
.src_s1_valid_urgent (fsp_s1_valid_urgent),
.src_s1_nexthop_in (fsp_s1_nexthop),
.src_s1_part_sel (fdp_select[6]),
.src_s2_data_in (fsp_s2_data),
.src_s2_nexthop_in (fsp_s2_nexthop),
.dequeue (fdp_6_ack),
.s3_data_out (fdp_6_data),
.s3_nexthop_out (fdp_6_nexthop),
.s3_data_valid (fdp_6_valid)
);
ICDestPart #(.PID(6), .NSP(8), .WIDTH(11)) cdp_6 (
.clock (clock),
.reset (reset),
.enable (enable),
.error (cdp_error[6]),
.src_s1_valid (csp_s1_valid),
.src_s1_valid_urgent (csp_s1_valid_urgent),
.src_s1_nexthop_in (csp_s1_nexthop),
.src_s1_part_sel (cdp_select[6]),
.src_s2_data_in (csp_s2_data),
.src_s2_nexthop_in (csp_s2_nexthop),
.dequeue (cdp_6_ack),
.s3_data_out (cdp_6_data),
.s3_nexthop_out (cdp_6_nexthop),
.s3_data_valid (cdp_6_valid)
);
ICSourcePart #(.N(1), .WIDTH(36)) fsp_6 (
.clock (clock),
.reset (reset),
.enable (enable),
.select (|fsp_select[6]),
.can_increment (fsp_can_increment[6]),
.src_data_valid (fsp_6_vec_valid[0:0]),
.src_data_valid_urgent (fsp_6_vec_valid_urgent[0:0]),
.src_data_in (fsp_6_vec_data[35:0]),
.src_nexthop_in (fsp_6_vec_nexthop[7:0]),
.src_dequeue (fsp_6_vec_dequeue[0:0]),
.s1_nexthop_out (fsp_s1_nexthop[55:48]),
.s1_valid (fsp_s1_valid[6]),
.s1_valid_urgent (fsp_s1_valid_urgent[6]),
.s2_data_out (fsp_s2_data[251:216]),
.s2_nexthop_out (fsp_s2_nexthop[55:48])
);
ICSourcePart #(.N(1), .WIDTH(11)) csp_6 (
.clock (clock),
.reset (reset),
.enable (enable),
.select (|csp_select[6]),
.can_increment (csp_can_increment[6]),
.src_data_valid (csp_6_vec_valid[0:0]),
.src_data_valid_urgent (csp_6_vec_valid_urgent[0:0]),
.src_data_in (csp_6_vec_data[10:0]),
.src_nexthop_in (csp_6_vec_nexthop[7:0]),
.src_dequeue (csp_6_vec_dequeue[0:0]),
.s1_nexthop_out (csp_s1_nexthop[55:48]),
.s1_valid (csp_s1_valid[6]),
.s1_valid_urgent (csp_s1_valid_urgent[6]),
.s2_data_out (csp_s2_data[76:66]),
.s2_nexthop_out (csp_s2_nexthop[55:48])
);
wire [0:0] fsp_7_vec_valid;
wire [0:0] fsp_7_vec_valid_urgent;
wire [35:0] fsp_7_vec_data;
wire [7:0] fsp_7_vec_nexthop;
wire [0:0] fsp_7_vec_dequeue;
wire [0:0] csp_7_vec_valid;
wire [0:0] csp_7_vec_valid_urgent;
wire [10:0] csp_7_vec_data;
wire [7:0] csp_7_vec_nexthop;
wire [0:0] csp_7_vec_dequeue;
wire [0:0] fdp_7_valid;
wire [35:0] fdp_7_data;
wire [4:0] fdp_7_nexthop;
wire [0:0] fdp_7_ack;
wire [0:0] cdp_7_valid;
wire [10:0] cdp_7_data;
wire [4:0] cdp_7_nexthop;
wire [0:0] cdp_7_ack;
Partition #(.DPID(7), .N(1)) part_7 (
.clock (clock),
.reset (reset),
.enable (enable),
.stop_injection (stop_injection),
.measure (measure),
.sim_time (sim_time),
.sim_time_tick (sim_time_tick),
.error (part_error[7]),
.is_quiescent (part_quiescent[7]),
.can_increment (part_can_increment[7]),
.config_in_valid (part_config_in_valid[7]),
.config_in (part_config_in[7]),
.config_out_valid (part_config_in_valid[8]),
.config_out (part_config_in[8]),
.ram_config_in_valid (part_ram_config_in_valid[7]),
.ram_config_in (part_ram_config_in[7]),
.ram_config_out_valid (part_ram_config_in_valid[8]),
.ram_config_out (part_ram_config_in[8]),
.stats_shift (stats_shift),
.stats_in (part_stats_in[7]),
.stats_out (part_stats_in[8]),
.fsp_vec_valid (fsp_7_vec_valid),
.fsp_vec_valid_urgent (fsp_7_vec_valid_urgent),
.fsp_vec_data (fsp_7_vec_data),
.fsp_vec_nexthop (fsp_7_vec_nexthop),
.fsp_vec_dequeue (fsp_7_vec_dequeue),
.csp_vec_valid (csp_7_vec_valid),
.csp_vec_valid_urgent (csp_7_vec_valid_urgent),
.csp_vec_data (csp_7_vec_data),
.csp_vec_nexthop (csp_7_vec_nexthop),
.csp_vec_dequeue (csp_7_vec_dequeue),
.fdp_valid (fdp_7_valid),
.fdp_data (fdp_7_data),
.fdp_nexthop (fdp_7_nexthop),
.fdp_ack (fdp_7_ack),
.cdp_valid (cdp_7_valid),
.cdp_data (cdp_7_data),
.cdp_nexthop (cdp_7_nexthop),
.cdp_ack (cdp_7_ack)
);
ICDestPart #(.PID(7), .NSP(8), .WIDTH(36)) fdp_7 (
.clock (clock),
.reset (reset),
.enable (enable),
.error (fdp_error[7]),
.src_s1_valid (fsp_s1_valid),
.src_s1_valid_urgent (fsp_s1_valid_urgent),
.src_s1_nexthop_in (fsp_s1_nexthop),
.src_s1_part_sel (fdp_select[7]),
.src_s2_data_in (fsp_s2_data),
.src_s2_nexthop_in (fsp_s2_nexthop),
.dequeue (fdp_7_ack),
.s3_data_out (fdp_7_data),
.s3_nexthop_out (fdp_7_nexthop),
.s3_data_valid (fdp_7_valid)
);
ICDestPart #(.PID(7), .NSP(8), .WIDTH(11)) cdp_7 (
.clock (clock),
.reset (reset),
.enable (enable),
.error (cdp_error[7]),
.src_s1_valid (csp_s1_valid),
.src_s1_valid_urgent (csp_s1_valid_urgent),
.src_s1_nexthop_in (csp_s1_nexthop),
.src_s1_part_sel (cdp_select[7]),
.src_s2_data_in (csp_s2_data),
.src_s2_nexthop_in (csp_s2_nexthop),
.dequeue (cdp_7_ack),
.s3_data_out (cdp_7_data),
.s3_nexthop_out (cdp_7_nexthop),
.s3_data_valid (cdp_7_valid)
);
ICSourcePart #(.N(1), .WIDTH(36)) fsp_7 (
.clock (clock),
.reset (reset),
.enable (enable),
.select (|fsp_select[7]),
.can_increment (fsp_can_increment[7]),
.src_data_valid (fsp_7_vec_valid[0:0]),
.src_data_valid_urgent (fsp_7_vec_valid_urgent[0:0]),
.src_data_in (fsp_7_vec_data[35:0]),
.src_nexthop_in (fsp_7_vec_nexthop[7:0]),
.src_dequeue (fsp_7_vec_dequeue[0:0]),
.s1_nexthop_out (fsp_s1_nexthop[63:56]),
.s1_valid (fsp_s1_valid[7]),
.s1_valid_urgent (fsp_s1_valid_urgent[7]),
.s2_data_out (fsp_s2_data[287:252]),
.s2_nexthop_out (fsp_s2_nexthop[63:56])
);
ICSourcePart #(.N(1), .WIDTH(11)) csp_7 (
.clock (clock),
.reset (reset),
.enable (enable),
.select (|csp_select[7]),
.can_increment (csp_can_increment[7]),
.src_data_valid (csp_7_vec_valid[0:0]),
.src_data_valid_urgent (csp_7_vec_valid_urgent[0:0]),
.src_data_in (csp_7_vec_data[10:0]),
.src_nexthop_in (csp_7_vec_nexthop[7:0]),
.src_dequeue (csp_7_vec_dequeue[0:0]),
.s1_nexthop_out (csp_s1_nexthop[63:56]),
.s1_valid (csp_s1_valid[7]),
.s1_valid_urgent (csp_s1_valid_urgent[7]),
.s2_data_out (csp_s2_data[87:77]),
.s2_nexthop_out (csp_s2_nexthop[63:56])
);
genvar i, j;
generate
for (j = 0; j < 8; j = j + 1)
begin : dp_sp_sel
for (i = 0; i < 8; i = i + 1)
begin: dp
assign fsp_select[j][i] = fdp_select[i][j];
assign csp_select[j][i] = cdp_select[i][j];
end
end
endgenerate
endmodule
|
`timescale 1ns / 1ps
/* SRL16 based FIFO
*
* Verilog version adapted from OpenCores SRL FIFO project
* http://www.opencores.org/project,srl_fifo
*/
module srl_fifo (
clock,
reset,
data_in,
data_out,
write,
read,
full,
empty
);
parameter WIDTH = 11;
parameter LOG_DEP = 4;
localparam LENGTH = 1 << LOG_DEP;
input clock;
input reset;
input [WIDTH-1: 0] data_in;
output [WIDTH-1: 0] data_out;
input write;
input read;
output full;
output empty;
// Control signals
wire pointer_zero;
wire pointer_full;
wire valid_write;
wire valid_count;
reg empty;
reg [LOG_DEP-1: 0] pointer;
// Output
assign full = pointer_full;
// SRL
genvar i;
generate
for (i = 0; i < WIDTH; i = i + 1)
begin : srl_array
reg [LENGTH-1: 0] item;
always @(posedge clock)
begin
if (valid_write)
item <= {item[LENGTH-2:0], data_in[i]};
end
// Output
assign data_out[i] = item[pointer];
end
endgenerate
// Valid write, high when valid to write data to the FIFO
assign valid_write = ((read & write) | (write & ~pointer_full));
// Empty state
always @ (posedge clock)
begin
if (reset)
empty <= 1'b1;
else if (empty & write)
empty <= 1'b0;
else if (pointer_zero & read & ~write)
empty <= 1'b1;
end
// W R Action
// 0 0 pointer <= pointer
// 0 1 pointer <= pointer - 1
// 1 0 pointer <= pointer + 1
// 1 1 pointer <= pointer
assign valid_count = (write & ~read & ~pointer_full & ~empty) | (~write & read & ~pointer_zero);
always @(posedge clock)
begin
if (reset)
pointer <= 0;
else if (valid_count)
if (write)
pointer <= pointer + 1;
else
pointer <= pointer - 1;
end
// Detect when pointer is zero and maximum
assign pointer_zero = (pointer == 0) ? 1'b1 : 1'b0;
assign pointer_full = (pointer == LENGTH - 1) ? 1'b1 : 1'b0;
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 19:41:50 10/20/2009
// Design Name:
// Module Name: test_out_inf
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module test_out_inf(
clock,
reset,
flit_ts,
flit_valid,
sim_time,
ready
);
parameter nVCs = 2;
input clock;
input reset;
input [nVCs*TS_WIDTH-1:0] flit_ts;
input [nVCs-1:0] flit_valid;
input [TS_WIDTH-1:0] sim_time;
output ready;
endmodule
|
`timescale 1ns / 1ps
/* TGBernoulli.v
* Bernoulli traffic injection engine
* Injections a packet when 1) rand_wire < threshold
* 2) current time >= lag time
* Spits out a flit every clock cycle if there is a flit
* to inject and this unit is enabled
*/
`include "const.v"
module TGBernoulliFSM(
clock,
reset,
enable,
sim_time,
measure, // Approximation: global inject measurement flag
stop_injection,
psize,
sendto,
obuf_full, // Output buffer is full
rand_below_threshold,
flit_out,
ready,
tick_rng
);
parameter [`ADDR_WIDTH-1:0] HADDR = 0; // Hardware node address
parameter PSIZE_WIDTH = 10;
localparam START = 0,
INJECT_HEAD = 1,
INJECT_NORMAL = 2,
INJECT_WAIT = 3,
INJECT_TAIL = 3;
input clock;
input reset;
input enable;
input [`TS_WIDTH-1:0] sim_time;
input measure;
input stop_injection;
input [PSIZE_WIDTH-1:0] psize;
input [`ADDR_WIDTH-1:0] sendto;
input obuf_full;
input rand_below_threshold;
output [`FLIT_WIDTH-1:0] flit_out;
output ready;
output tick_rng;
// Internal states
reg [`TS_WIDTH-1: 0] lag_ts; // Current timestamp of the lagging injection process
reg [PSIZE_WIDTH-1: 0] flits_injected;
reg [CLogB2(3)-1:0] state;
reg [CLogB2(3)-1:0] next_state;
// Wires
reg w_inc_lag_ts;
reg w_tick_rng;
reg w_inject_head, w_inject_normal, w_inject_tail;
reg w_clear_flits_injected;
wire [PSIZE_WIDTH-1: 0] w_flits_injected;
wire [ 9: 0] w_src_or_injection;
reg r_tick_rng;
always @(posedge clock)
begin
if (reset)
r_tick_rng <= 1'b0;
else
r_tick_rng <= w_tick_rng;
end
// Output
assign flit_out = {w_inject_head, w_inject_tail, measure, lag_ts, sendto, w_src_or_injection, 5'h0};
assign ready = w_inject_head | w_inject_normal | w_inject_tail;
assign tick_rng = r_tick_rng;
assign w_src_or_injection = (w_inject_head) ? {2'b00, HADDR} : lag_ts;
assign w_flits_injected = flits_injected + ready;
function integer CLogB2;
input [31:0] Depth;
integer i;
begin
i = Depth;
for(CLogB2 = 0; i > 0; CLogB2 = CLogB2 + 1)
i = i >> 1;
end
endfunction
// FSM state register
always @(posedge clock)
begin
if (reset)
state <= 0;
else if (enable)
state <= next_state;
end
// lag_ts is never more than 1 step ahead of sim_time
wire [`TS_WIDTH-1:0] w_lag_ts_diff;
wire w_lag_ts_is_behind;
assign w_lag_ts_diff = lag_ts - sim_time;
assign w_lag_ts_is_behind = (w_lag_ts_diff[`TS_WIDTH-1:1] == 0) ? 1'b0 : 1'b1; // (lag_ts - sim_time) != 0 or 1
// FSM
always @(*)
begin
next_state = state;
w_inc_lag_ts = 1'b0;
w_tick_rng = 1'b0;
w_inject_head = 1'b0;
w_inject_normal = 1'b0;
w_inject_tail = 1'b0;
w_clear_flits_injected = 1'b0;
case (state)
START:
begin
if (w_lag_ts_is_behind && enable == 1'b1 && stop_injection == 1'b0)
begin
w_tick_rng = 1'b1;
if (~rand_below_threshold) // Don't inject packet this time step
w_inc_lag_ts = 1'b1;
else // Inject head
begin
next_state = INJECT_HEAD;
end
end
end
INJECT_HEAD:
begin
if (~obuf_full)
begin
w_inject_head = 1'b1;
if (flits_injected == psize)
next_state = INJECT_TAIL;
else
next_state = INJECT_NORMAL;
end
end
INJECT_TAIL:
begin
if (~obuf_full)
begin
w_inject_tail = 1'b1;
w_clear_flits_injected = 1'b1;
w_inc_lag_ts = 1'b1;
next_state = START;
end
end
INJECT_NORMAL:
begin
if (~obuf_full)
begin
w_inject_normal = 1'b1;
if (flits_injected == psize)
next_state = INJECT_TAIL;
end
end
endcase
end
// Update states
always @(posedge clock)
begin
if (reset)
begin
lag_ts <= {(`TS_WIDTH){1'b0}};
flits_injected <= {(PSIZE_WIDTH){1'b0}};
end
else if (enable)
begin
if (w_inc_lag_ts)
lag_ts <= lag_ts + 1;
if (w_clear_flits_injected)
flits_injected <= 0;
else
flits_injected <= w_flits_injected;
end
end
endmodule
|
`timescale 1ns / 1ps
/* TGPacketFSM
* FSM for trace-based flit injection
*/
`include "const.v"
module TGPacketFSM #(
parameter [`ADDR_WIDTH-1:0] HADDR = 0,
parameter NVCS = 2
)
(
input clock,
input reset,
input enable,
input [`TS_WIDTH-1:0] sim_time,
input [31:0] packet_in,
input packet_in_valid,
output packet_request,
input [NVCS-1:0] obuf_full,
output [`FLIT_WIDTH-1:0] flit_out,
output flit_out_valid
);
`include "math.v"
localparam logNVCS = CLogB2(NVCS-1);
localparam IDLE = 0,
LOAD_PACKET = 1,
INJECT_HEAD = 2,
INJECT_BODY = 3,
INJECT_TAIL = 4;
reg [3:0] state;
reg [3:0] next_state;
reg [31:0] r_packet;
reg [`P_SIZE_WIDTH-1:0] r_injected_flits;
reg inject_head;
reg inject_body;
reg inject_tail;
wire [1:0] vc;
wire [`ADDR_WIDTH-1:0] w_dest;
wire vc_obuf_full;
wire [9:0] w_src_or_inj;
// Output
assign packet_request = (state == IDLE) ? 1'b1 : 1'b0; // Can receive new packet only in IDLE state
assign flit_out[`F_FLAGS] = {inject_head, inject_tail, r_packet[`P_MEASURE]};
assign flit_out[`F_TS] = r_packet[`P_INJ];
assign flit_out[`F_DEST] = w_dest;
assign flit_out[`F_SRC_INJ] = w_src_or_inj;
assign flit_out[`F_OPORT] = 3'b000;
assign flit_out[`F_OVC] = vc;
assign flit_out_valid = inject_head | inject_body | inject_tail;
assign vc = r_packet[`P_VC];
assign w_dest = r_packet[`P_DEST]; // Dest node address (need to append 3'b000 port address before use)
assign w_src_or_inj = (inject_head) ? {2'b00, HADDR} : r_packet[`P_INJ];
// Buffer packet
always @(posedge clock)
begin
if (reset)
r_packet <= 0;
else if (state == LOAD_PACKET)
r_packet <= packet_in;
end
always @(posedge clock)
begin
if (reset)
r_injected_flits <= 0;
else if (state == LOAD_PACKET)
r_injected_flits <= 1<<packet_in[`P_SIZE];
else if (inject_head | inject_body | inject_tail)
r_injected_flits <= r_injected_flits - 1;
end
mux_Nto1 #(.WIDTH(1), .SIZE(NVCS)) obuf_full_mux (
.in (obuf_full),
.sel (vc[logNVCS-1:0]),
.out (vc_obuf_full));
wire [9:0] time_diff;
assign time_diff = r_packet[`P_INJ] - sim_time;
// FSM
always @(*)
begin
next_state = state;
inject_head = 1'b0;
inject_body = 1'b0;
inject_tail = 1'b0;
case (state)
IDLE:
begin
if (enable & packet_in_valid)
next_state = LOAD_PACKET;
end
LOAD_PACKET:
begin
next_state = INJECT_HEAD;
end
INJECT_HEAD:
begin
if (time_diff <= 0 && vc_obuf_full == 1'b0)
begin
inject_head = 1'b1;
if (r_injected_flits == 2)
next_state = INJECT_TAIL; // This is the second last flit
else
next_state = INJECT_BODY;
end
end
INJECT_BODY:
begin
if (~vc_obuf_full)
begin
inject_body = 1'b1;
if (r_injected_flits == 2)
next_state = INJECT_TAIL;
else
next_state = INJECT_BODY;
end
end
INJECT_TAIL:
begin
if (~vc_obuf_full)
begin
inject_tail = 1'b1;
next_state = IDLE;
end
end
endcase
end
always @(posedge clock)
begin
if (reset)
state <= IDLE;
else
state <= next_state;
end
endmodule
|
`timescale 1 ns/100 ps // time unit = 1ns; precision = 1/10 ns
/* TrafficGen.v
*
* Configuration path
* config_in -> RNG -> threshold (32) -> {sendto(8), psize(8)} ->
* IQ -> OQ -> config_out
*/
// TODO:
// 1. Multicontext
`include "const.v"
module TrafficGen (
clock,
reset,
enable,
stop_injection,
sim_time,
error,
is_quiescent,
config_in,
config_in_valid,
config_out,
config_out_valid,
stats_shift,
stats_in,
stats_out,
flit_in,
flit_in_valid,
nexthop_in,
flit_ack,
flit_full,
flit_out,
flit_out_valid,
dequeue,
credit_out,
credit_out_valid,
measure
);
`include "util.v"
parameter [`A_WIDTH-1:0] HADDR = 0; // 8-bit global node ID + 3-bit port ID
parameter LOG_NVCS = 1;
localparam NVCS = 1 << LOG_NVCS;
localparam PSIZE_WIDTH = 8;
input measure;
// Global ports
input clock;
input reset;
input enable;
input stop_injection;
input [`TS_WIDTH-1:0] sim_time;
output error;
output is_quiescent;
// Configuration ports
input [15: 0] config_in;
input config_in_valid;
output [15: 0] config_out;
output config_out_valid;
// Stats ports
input stats_shift;
input [15: 0] stats_in;
output [15: 0] stats_out;
// Data ports
input [`FLIT_WIDTH-1:0] flit_in;
input flit_in_valid;
input [`A_FQID] nexthop_in;
output flit_ack;
output [NVCS-1:0] flit_full;
input [NVCS-1:0] dequeue;
output [NVCS*`FLIT_WIDTH-1:0] flit_out;
output [NVCS-1:0] flit_out_valid;
output [`CREDIT_WIDTH-1:0] credit_out;
output credit_out_valid;
// Internal states
reg [31: 0] threshold; // Bernoulli threshold
reg [PSIZE_WIDTH-1: 0] psize;
reg [`ADDR_WIDTH-1:0] sendto;
reg [15: 0] stats_nreceived;
reg [15: 0] stats_ninjected;
reg [63: 0] stats_sum_latency;
reg [LOG_NVCS-1: 0] r_prio;
reg r_error;
// Wires
wire w_recv_flit;
wire w_tick_rng;
wire [15: 0] w_rng_config_out;
wire w_rng_config_out_valid;
wire [31: 0] w_rand_wire;
wire w_rand_below_threshold;
wire w_iq_error;
wire w_iq_is_quiescent;
wire w_oq_error;
wire w_oq_is_quiescent;
wire [15: 0] w_tg_config_out;
wire w_tg_config_out_valid;
wire [15: 0] w_iq_config_out;
wire w_iq_config_out_valid;
wire [15: 0] w_oq_config_out;
wire w_oq_config_out_valid;
wire [NVCS*`FLIT_WIDTH-1:0] w_iq_flit_out;
wire [NVCS-1: 0] w_iq_flit_out_valid;
// TODO: we only use 1 VC in the source queue
wire [`FLIT_WIDTH-1:0] w_oq_flit_out;
wire w_oq_flit_out_valid;
wire w_oq_flit_full;
wire w_oq_flit_dequeue;
wire [`FLIT_WIDTH-1:0] w_tg_flit_out;
wire w_tg_flit_out_valid;
wire [`TS_WIDTH-1:0] w_iq_flit_latency;
wire [NVCS-1: 0] w_iq_flit_dequeue;
wire [`FLIT_WIDTH-1:0] w_received_flit;
wire w_error_mismatch;
// Output
assign error = r_error;
assign is_quiescent = w_iq_is_quiescent & w_oq_is_quiescent;
assign config_out = w_oq_config_out;
assign config_out_valid = w_oq_config_out_valid;
assign stats_out = stats_ninjected;
assign flit_out = w_oq_flit_out;
assign flit_out_valid = w_oq_flit_out_valid;
assign credit_out = {flit_vc(flit_in), sim_time};
assign credit_out_valid = (nexthop_in == HADDR[`A_FQID] && flit_in_valid == 1'b1) ? 1'b1 : 1'b0;
assign w_recv_flit = |w_iq_flit_dequeue;
assign w_tg_config_out = {sendto, psize};
assign w_tg_config_out_valid = w_rng_config_out_valid;
// Simulation stuff
`ifdef SIMULATION
always @(posedge clock)
begin
if (dequeue)
$display ("T %x TG (%x) sends flit %x", sim_time, HADDR, flit_out);
if (w_recv_flit)
$display ("T %x TG (%x) recvs flit %x", sim_time, HADDR, w_received_flit);
if (enable & error)
$display ("ATTENTION: TG (%x) has an error", HADDR);
end
`endif
// Error
assign w_error_mismatch = (w_received_flit[`F_DEST] == HADDR) ? 1'b0 : 1'b1;
always @(posedge clock)
begin
if (reset)
r_error <= 1'b0;
else if (enable & ~r_error)
r_error <= w_iq_error | w_oq_error | (w_recv_flit & w_error_mismatch);
end
// Configuration chain
always @(posedge clock)
begin
if (reset)
begin
threshold <= {(32){1'b0}};
psize <= {(PSIZE_WIDTH){1'b0}};
sendto <= {(`ADDR_WIDTH){1'b0}};
end
else if (w_rng_config_out_valid)
begin
threshold <= {w_rng_config_out, threshold[31:16]};
{sendto, psize} <= threshold[15:0];
end
end
// Stats counters
assign w_iq_flit_latency = w_received_flit[`F_TS] - w_received_flit[`F_SRC_INJ];
always @(posedge clock)
begin
if (reset)
begin
stats_ninjected <= 0;
stats_nreceived <= 0;
stats_sum_latency <= 0;
end
else if (stats_shift)
begin
stats_sum_latency <= {stats_in, stats_sum_latency[63:16]};
stats_nreceived <= stats_sum_latency[15:0];
stats_ninjected <= stats_nreceived;
end
else if (enable)
begin
if (w_recv_flit & w_received_flit[`F_TAIL] & w_received_flit[`F_MEASURE])
begin
// Collect stats on tail flit injected during measurement
stats_nreceived <= stats_nreceived + 1;
stats_sum_latency <= stats_sum_latency + {{(64-`TS_WIDTH){1'b0}}, w_iq_flit_latency};
end
if (w_tg_flit_out_valid & w_tg_flit_out[`F_HEAD] & w_tg_flit_out[`F_MEASURE])
stats_ninjected <= stats_ninjected + 1;
end
end
// Random number generator
RNG rng (
.clock (clock),
.reset (reset),
.enable (enable & w_tick_rng),
.rand_out (w_rand_wire),
.config_in_valid (config_in_valid),
.config_in (config_in),
.config_out_valid (w_rng_config_out_valid),
.config_out (w_rng_config_out));
// Bernoulli injection process
assign w_rand_below_threshold = (w_rand_wire < threshold) ? 1'b1 : 1'b0;
TGBernoulliFSM #(.HADDR(HADDR[`A_DNID]), .PSIZE_WIDTH(PSIZE_WIDTH)) tg (
.clock (clock),
.reset (reset),
.enable (enable),
.sim_time (sim_time),
.measure (measure),
.stop_injection (stop_injection),
.psize (psize),
.sendto (sendto),
.obuf_full (w_oq_flit_full), // Only support 1 output VC now
.rand_below_threshold (w_rand_below_threshold),
.flit_out (w_tg_flit_out),
.ready (w_tg_flit_out_valid),
.tick_rng (w_tick_rng));
// Input and output queues
FlitQueue_NC #(.NPID(HADDR[`A_FQID]), .LOG_NVCS(LOG_NVCS)) iq (
.clock (clock),
.reset (reset),
.enable (enable),
.sim_time (sim_time),
.error (w_iq_error),
.is_quiescent (w_iq_is_quiescent),
.latency (),
.config_in (w_tg_config_out),
.config_in_valid (w_tg_config_out_valid),
.config_out (w_iq_config_out),
.config_out_valid (w_iq_config_out_valid),
.flit_full (flit_full),
.flit_in_valid (flit_in_valid),
.flit_in (flit_in),
.nexthop_in (nexthop_in),
.flit_ack (flit_ack),
.flit_out (w_iq_flit_out),
.flit_out_valid (w_iq_flit_out_valid),
.dequeue (w_iq_flit_dequeue));
// Output queue has only 1 VC
FlitQueue_NC #(.NPID(HADDR[`A_FQID]), .LOG_NVCS(0)) oq (
.clock (clock),
.reset (reset),
.enable (enable),
.sim_time (sim_time),
.error (w_oq_error),
.is_quiescent (w_oq_is_quiescent),
.latency (),
.config_in (w_iq_config_out),
.config_in_valid (w_iq_config_out_valid),
.config_out (w_oq_config_out),
.config_out_valid (w_oq_config_out_valid),
.flit_full (w_oq_flit_full),
.flit_in_valid (w_tg_flit_out_valid),
.flit_in (w_tg_flit_out),
.nexthop_in (HADDR[`A_FQID]),
.flit_ack (),
.flit_out (w_oq_flit_out),
.flit_out_valid (w_oq_flit_out_valid),
.dequeue (w_oq_flit_dequeue));
// Make sure dequeue only happens at the second half cycle of clock
assign w_oq_flit_dequeue = dequeue;
// Rotating priority encoder to figure out which input VC to dequeue
generate
if (NVCS == 1)
begin
always @(posedge clock)
begin
if (reset)
r_prio <= 1'b0;
else if (enable)
r_prio <= ~r_prio;
end
end
else
begin
always @(posedge clock)
begin
if (reset)
r_prio <= {(LOG_NVCS){1'b0}};
else if (enable)
r_prio <= r_prio + 1;
end
end
endgenerate
rotate_prio #(.SIZE(NVCS)) iq_prio_sel (
.prio (r_prio),
.in_valid (w_iq_flit_out_valid),
.out_sel (w_iq_flit_dequeue));
mux_Nto1_decoded #(.WIDTH(`FLIT_WIDTH), .SIZE(NVCS)) iq_flit_mux (
.in (w_iq_flit_out),
.sel (w_iq_flit_dequeue),
.out (w_received_flit));
endmodule
|
/* util.v
*
* This file contains globally accessed functions that can be included
* in any Verilog modules.
*/
/* Get flit timestamp
*/
function [9:0] flit_ts;
input [`FLIT_WIDTH-1: 0] flit;
flit_ts = flit[32:23];
endfunction
/* Get flit destination
*/
function [7:0] flit_dest;
input [`FLIT_WIDTH-1: 0] flit;
flit_dest = flit[22:15];
endfunction
/* Get flit source
*/
function [7:0] flit_source;
input [`FLIT_WIDTH-1: 0] flit;
flit_source = flit[14:7];
endfunction
/* Get flit injection timestamp
*/
function [9:0] flit_inject_ts;
input [`FLIT_WIDTH-1: 0] flit;
flit_inject_ts = flit[14:5];
endfunction
/* Return the head flag
*/
function flit_is_head;
input [`FLIT_WIDTH-1: 0] flit;
flit_is_head = flit[35];
endfunction
/* Return the tail flag
*/
function flit_is_tail;
input [`FLIT_WIDTH-1: 0] flit;
flit_is_tail = flit[34];
endfunction
/* Return the measurement flag
*/
function flit_is_measurement;
input [`FLIT_WIDTH-1: 0] flit;
flit_is_measurement = flit[33];
endfunction
/* Return the port
*/
function [2:0] flit_port;
input [`FLIT_WIDTH-1: 0] flit;
flit_port = flit[4:2];
endfunction
/* Return the port VC
*/
function flit_vc;
input [`FLIT_WIDTH-1: 0] flit;
flit_vc = flit[0];
endfunction
/* Form flit with new timestamp
*/
function [`FLIT_WIDTH-1:0] update_flit_ts;
input [`FLIT_WIDTH-1:0] old_flit;
input [`TS_WIDTH-1:0] new_ts;
update_flit_ts = {old_flit[35:33], new_ts, old_flit[22:0]};
endfunction
/* Form flit with new port and VC
*/
function [`FLIT_WIDTH-1:0] update_flit_port;
input [`FLIT_WIDTH-1:0] old_flit;
input [ 2: 0] new_oport;
input [ 1: 0] new_vc;
update_flit_port = {old_flit[35:5], new_oport, new_vc};
endfunction
/* Get credit timestamp
*/
function [9:0] credit_ts;
input [`CREDIT_WIDTH-1:0] credit;
credit_ts = credit[9:0];
endfunction
/* Get credit VC
*/
function credit_vc;
input [`CREDIT_WIDTH-1:0] credit;
credit_vc = credit[10];
endfunction
/* Assemble credit flit from individual components
*/
function [`CREDIT_WIDTH-1:0] assemble_credit;
input vc;
input [`TS_WIDTH-1:0] ts;
assemble_credit = {vc, ts};
endfunction
/* Form credit flit with new timestamp
*/
function [`CREDIT_WIDTH-1:0] update_credit_ts;
input [`CREDIT_WIDTH-1:0] old_credit;
input [`TS_WIDTH-1:0] new_ts;
update_credit_ts = {old_credit[10], new_ts};
endfunction
|
`timescale 1ns / 1ps
/* VC Allocator
* VCAlloc.v
*
* Simple first-available VC allocator
*/
module VCAlloc (
clock,
reset,
enable,
mask,
oport,
allocate,
free,
free_vc,
next_vc,
next_vc_valid
);
`include "math.v"
parameter NPORTS = 5;
parameter NVCS = 2;
localparam LOG_NPORTS = CLogB2(NPORTS-1);
localparam LOG_NVCS = CLogB2(NVCS-1);
localparam NINPUTS = NPORTS * NVCS;
input clock;
input reset;
input enable;
input [NINPUTS-1: 0] mask;
input [LOG_NPORTS-1: 0] oport;
input allocate;
input free;
input [LOG_NVCS-1: 0] free_vc;
output [LOG_NVCS-1: 0] next_vc;
output next_vc_valid;
// Internal states
reg [NINPUTS-1: 0] r_available; // Bit vector for available VCs (NVCS x NPORTS)
// Wires
wire [NVCS-1: 0] w_available_vcs;
wire [NVCS-1: 0] w_vc_select;
wire [NINPUTS-1: 0] w_available;
wire [NVCS-1: 0] w_vc_free_decoded;
wire [NPORTS-1: 0] w_oport_decoded;
// Select first available
mux_Nto1 #(.WIDTH(NVCS), .SIZE(NPORTS)) vc_avail_mux (
.in (r_available & mask),
.sel (oport),
.out (w_available_vcs));
// Use the static arbiter to choose a free VC
arbiter_static #(.SIZE(NVCS)) vc_select (
.requests (w_available_vcs),
.grants (w_vc_select),
.grant_valid (next_vc_valid));
encoder_N #(.SIZE(NVCS)) encode (
.decoded (w_vc_select),
.encoded (next_vc),
.valid ());
decoder_N #(.SIZE(NVCS)) decode (
.encoded (free_vc),
.decoded (w_vc_free_decoded));
decoder_N #(.SIZE(NPORTS)) oport_decode (
.encoded (oport),
.decoded (w_oport_decoded));
// Available vectors
always @(posedge clock)
begin
if (reset)
r_available <= {(NINPUTS){1'b1}};
else if (enable)
r_available <= w_available;
end
genvar i, j;
generate
for (i = 0; i < NPORTS; i = i + 1)
begin : port
for (j = 0; j < NVCS; j = j + 1)
begin : vc
assign w_clear = w_oport_decoded[i] & allocate & w_vc_select[j];
assign w_set = w_oport_decoded[i] & free & w_vc_free_decoded[j];
assign w_available[i*NVCS+j] = (r_available[i*NVCS+j] | w_set) & ~w_clear;
end
end
endgenerate
endmodule
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used *
* solely for design, simulation, implementation and creation of *
* design files limited to Xilinx devices or technologies. Use *
* with non-Xilinx devices or technologies is expressly prohibited *
* and immediately terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" *
* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR *
* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION *
* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION *
* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS *
* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, *
* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE *
* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY *
* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS *
* FOR A PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support *
* appliances, devices, or systems. Use in such applications are *
* expressly prohibited. *
* *
* (c) Copyright 1995-2007 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
// You must compile the wrapper file fifo.v when simulating
// the core, fifo. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
`timescale 1ns/1ps
module fifo(
clk,
din,
rd_en,
rst,
wr_en,
dout,
empty,
full);
input clk;
input [15 : 0] din;
input rd_en;
input rst;
input wr_en;
output [15 : 0] dout;
output empty;
output full;
// synthesis translate_off
FIFO_GENERATOR_V4_4 #(
.C_COMMON_CLOCK(1),
.C_COUNT_TYPE(0),
.C_DATA_COUNT_WIDTH(11),
.C_DEFAULT_VALUE("BlankString"),
.C_DIN_WIDTH(16),
.C_DOUT_RST_VAL("0"),
.C_DOUT_WIDTH(16),
.C_ENABLE_RLOCS(0),
.C_FAMILY("virtex2p"),
.C_FULL_FLAGS_RST_VAL(1),
.C_HAS_ALMOST_EMPTY(0),
.C_HAS_ALMOST_FULL(0),
.C_HAS_BACKUP(0),
.C_HAS_DATA_COUNT(0),
.C_HAS_INT_CLK(0),
.C_HAS_MEMINIT_FILE(0),
.C_HAS_OVERFLOW(0),
.C_HAS_RD_DATA_COUNT(0),
.C_HAS_RD_RST(0),
.C_HAS_RST(1),
.C_HAS_SRST(0),
.C_HAS_UNDERFLOW(0),
.C_HAS_VALID(0),
.C_HAS_WR_ACK(0),
.C_HAS_WR_DATA_COUNT(0),
.C_HAS_WR_RST(0),
.C_IMPLEMENTATION_TYPE(0),
.C_INIT_WR_PNTR_VAL(0),
.C_MEMORY_TYPE(1),
.C_MIF_FILE_NAME("BlankString"),
.C_MSGON_VAL(1),
.C_OPTIMIZATION_MODE(0),
.C_OVERFLOW_LOW(0),
.C_PRELOAD_LATENCY(0),
.C_PRELOAD_REGS(1),
.C_PRIM_FIFO_TYPE("1kx18"),
.C_PROG_EMPTY_THRESH_ASSERT_VAL(4),
.C_PROG_EMPTY_THRESH_NEGATE_VAL(5),
.C_PROG_EMPTY_TYPE(0),
.C_PROG_FULL_THRESH_ASSERT_VAL(1023),
.C_PROG_FULL_THRESH_NEGATE_VAL(1022),
.C_PROG_FULL_TYPE(0),
.C_RD_DATA_COUNT_WIDTH(11),
.C_RD_DEPTH(1024),
.C_RD_FREQ(1),
.C_RD_PNTR_WIDTH(10),
.C_UNDERFLOW_LOW(0),
.C_USE_DOUT_RST(1),
.C_USE_ECC(0),
.C_USE_EMBEDDED_REG(0),
.C_USE_FIFO16_FLAGS(0),
.C_USE_FWFT_DATA_COUNT(1),
.C_VALID_LOW(0),
.C_WR_ACK_LOW(0),
.C_WR_DATA_COUNT_WIDTH(11),
.C_WR_DEPTH(1024),
.C_WR_FREQ(1),
.C_WR_PNTR_WIDTH(10),
.C_WR_RESPONSE_LATENCY(1))
inst (
.CLK(clk),
.DIN(din),
.RD_EN(rd_en),
.RST(rst),
.WR_EN(wr_en),
.DOUT(dout),
.EMPTY(empty),
.FULL(full),
.INT_CLK(),
.BACKUP(),
.BACKUP_MARKER(),
.PROG_EMPTY_THRESH(),
.PROG_EMPTY_THRESH_ASSERT(),
.PROG_EMPTY_THRESH_NEGATE(),
.PROG_FULL_THRESH(),
.PROG_FULL_THRESH_ASSERT(),
.PROG_FULL_THRESH_NEGATE(),
.RD_CLK(),
.RD_RST(),
.SRST(),
.WR_CLK(),
.WR_RST(),
.ALMOST_EMPTY(),
.ALMOST_FULL(),
.DATA_COUNT(),
.OVERFLOW(),
.PROG_EMPTY(),
.PROG_FULL(),
.VALID(),
.RD_DATA_COUNT(),
.UNDERFLOW(),
.WR_ACK(),
.WR_DATA_COUNT(),
.SBITERR(),
.DBITERR());
// synthesis translate_on
// XST black box declaration
// box_type "black_box"
// synthesis attribute box_type of fifo is "black_box"
endmodule
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used *
* solely for design, simulation, implementation and creation of *
* design files limited to Xilinx devices or technologies. Use *
* with non-Xilinx devices or technologies is expressly prohibited *
* and immediately terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" *
* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR *
* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION *
* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION *
* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS *
* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, *
* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE *
* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY *
* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS *
* FOR A PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support *
* appliances, devices, or systems. Use in such applications are *
* expressly prohibited. *
* *
* (c) Copyright 1995-2007 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
// You must compile the wrapper file ram_fifo_32x36.v when simulating
// the core, ram_fifo_32x36. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
`timescale 1ns/1ps
module ram_fifo_32x36(
din,
rd_clk,
rd_en,
rst,
wr_clk,
wr_en,
dout,
empty,
full);
input [35 : 0] din;
input rd_clk;
input rd_en;
input rst;
input wr_clk;
input wr_en;
output [35 : 0] dout;
output empty;
output full;
// synthesis translate_off
FIFO_GENERATOR_V4_2 #(
.C_COMMON_CLOCK(0),
.C_COUNT_TYPE(0),
.C_DATA_COUNT_WIDTH(5),
.C_DEFAULT_VALUE("BlankString"),
.C_DIN_WIDTH(36),
.C_DOUT_RST_VAL("0"),
.C_DOUT_WIDTH(36),
.C_ENABLE_RLOCS(0),
.C_FAMILY("virtex2p"),
.C_FULL_FLAGS_RST_VAL(1),
.C_HAS_ALMOST_EMPTY(0),
.C_HAS_ALMOST_FULL(0),
.C_HAS_BACKUP(0),
.C_HAS_DATA_COUNT(0),
.C_HAS_INT_CLK(0),
.C_HAS_MEMINIT_FILE(0),
.C_HAS_OVERFLOW(0),
.C_HAS_RD_DATA_COUNT(0),
.C_HAS_RD_RST(0),
.C_HAS_RST(1),
.C_HAS_SRST(0),
.C_HAS_UNDERFLOW(0),
.C_HAS_VALID(0),
.C_HAS_WR_ACK(0),
.C_HAS_WR_DATA_COUNT(0),
.C_HAS_WR_RST(0),
.C_IMPLEMENTATION_TYPE(2),
.C_INIT_WR_PNTR_VAL(0),
.C_MEMORY_TYPE(1),
.C_MIF_FILE_NAME("BlankString"),
.C_OPTIMIZATION_MODE(0),
.C_OVERFLOW_LOW(0),
.C_PRELOAD_LATENCY(0),
.C_PRELOAD_REGS(1),
.C_PRIM_FIFO_TYPE("512x36"),
.C_PROG_EMPTY_THRESH_ASSERT_VAL(4),
.C_PROG_EMPTY_THRESH_NEGATE_VAL(5),
.C_PROG_EMPTY_TYPE(0),
.C_PROG_FULL_THRESH_ASSERT_VAL(31),
.C_PROG_FULL_THRESH_NEGATE_VAL(30),
.C_PROG_FULL_TYPE(0),
.C_RD_DATA_COUNT_WIDTH(5),
.C_RD_DEPTH(32),
.C_RD_FREQ(1),
.C_RD_PNTR_WIDTH(5),
.C_UNDERFLOW_LOW(0),
.C_USE_DOUT_RST(1),
.C_USE_ECC(0),
.C_USE_EMBEDDED_REG(0),
.C_USE_FIFO16_FLAGS(0),
.C_USE_FWFT_DATA_COUNT(0),
.C_VALID_LOW(0),
.C_WR_ACK_LOW(0),
.C_WR_DATA_COUNT_WIDTH(5),
.C_WR_DEPTH(32),
.C_WR_FREQ(1),
.C_WR_PNTR_WIDTH(5),
.C_WR_RESPONSE_LATENCY(1))
inst (
.DIN(din),
.RD_CLK(rd_clk),
.RD_EN(rd_en),
.RST(rst),
.WR_CLK(wr_clk),
.WR_EN(wr_en),
.DOUT(dout),
.EMPTY(empty),
.FULL(full),
.CLK(),
.INT_CLK(),
.BACKUP(),
.BACKUP_MARKER(),
.PROG_EMPTY_THRESH(),
.PROG_EMPTY_THRESH_ASSERT(),
.PROG_EMPTY_THRESH_NEGATE(),
.PROG_FULL_THRESH(),
.PROG_FULL_THRESH_ASSERT(),
.PROG_FULL_THRESH_NEGATE(),
.RD_RST(),
.SRST(),
.WR_RST(),
.ALMOST_EMPTY(),
.ALMOST_FULL(),
.DATA_COUNT(),
.OVERFLOW(),
.PROG_EMPTY(),
.PROG_FULL(),
.VALID(),
.RD_DATA_COUNT(),
.UNDERFLOW(),
.WR_ACK(),
.WR_DATA_COUNT(),
.SBITERR(),
.DBITERR());
// synthesis translate_on
endmodule
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used *
* solely for design, simulation, implementation and creation of *
* design files limited to Xilinx devices or technologies. Use *
* with non-Xilinx devices or technologies is expressly prohibited *
* and immediately terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" *
* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR *
* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION *
* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION *
* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS *
* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, *
* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE *
* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY *
* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS *
* FOR A PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support *
* appliances, devices, or systems. Use in such applications are *
* expressly prohibited. *
* *
* (c) Copyright 1995-2007 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
// You must compile the wrapper file ram_fifo_32x36_sync.v when simulating
// the core, ram_fifo_32x36_sync. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
`timescale 1ns/1ps
module ram_fifo_32x36_sync(
clk,
din,
rd_en,
rst,
wr_en,
dout,
empty,
full);
input clk;
input [35 : 0] din;
input rd_en;
input rst;
input wr_en;
output [35 : 0] dout;
output empty;
output full;
// synthesis translate_off
FIFO_GENERATOR_V4_2 #(
.C_COMMON_CLOCK(1),
.C_COUNT_TYPE(0),
.C_DATA_COUNT_WIDTH(6),
.C_DEFAULT_VALUE("BlankString"),
.C_DIN_WIDTH(36),
.C_DOUT_RST_VAL("0"),
.C_DOUT_WIDTH(36),
.C_ENABLE_RLOCS(0),
.C_FAMILY("virtex2p"),
.C_FULL_FLAGS_RST_VAL(1),
.C_HAS_ALMOST_EMPTY(0),
.C_HAS_ALMOST_FULL(0),
.C_HAS_BACKUP(0),
.C_HAS_DATA_COUNT(0),
.C_HAS_INT_CLK(0),
.C_HAS_MEMINIT_FILE(0),
.C_HAS_OVERFLOW(0),
.C_HAS_RD_DATA_COUNT(0),
.C_HAS_RD_RST(0),
.C_HAS_RST(1),
.C_HAS_SRST(0),
.C_HAS_UNDERFLOW(0),
.C_HAS_VALID(0),
.C_HAS_WR_ACK(0),
.C_HAS_WR_DATA_COUNT(0),
.C_HAS_WR_RST(0),
.C_IMPLEMENTATION_TYPE(0),
.C_INIT_WR_PNTR_VAL(0),
.C_MEMORY_TYPE(1),
.C_MIF_FILE_NAME("BlankString"),
.C_OPTIMIZATION_MODE(0),
.C_OVERFLOW_LOW(0),
.C_PRELOAD_LATENCY(0),
.C_PRELOAD_REGS(1),
.C_PRIM_FIFO_TYPE("512x36"),
.C_PROG_EMPTY_THRESH_ASSERT_VAL(4),
.C_PROG_EMPTY_THRESH_NEGATE_VAL(5),
.C_PROG_EMPTY_TYPE(0),
.C_PROG_FULL_THRESH_ASSERT_VAL(31),
.C_PROG_FULL_THRESH_NEGATE_VAL(30),
.C_PROG_FULL_TYPE(0),
.C_RD_DATA_COUNT_WIDTH(6),
.C_RD_DEPTH(32),
.C_RD_FREQ(1),
.C_RD_PNTR_WIDTH(5),
.C_UNDERFLOW_LOW(0),
.C_USE_DOUT_RST(1),
.C_USE_ECC(0),
.C_USE_EMBEDDED_REG(0),
.C_USE_FIFO16_FLAGS(0),
.C_USE_FWFT_DATA_COUNT(1),
.C_VALID_LOW(0),
.C_WR_ACK_LOW(0),
.C_WR_DATA_COUNT_WIDTH(6),
.C_WR_DEPTH(32),
.C_WR_FREQ(1),
.C_WR_PNTR_WIDTH(5),
.C_WR_RESPONSE_LATENCY(1))
inst (
.CLK(clk),
.DIN(din),
.RD_EN(rd_en),
.RST(rst),
.WR_EN(wr_en),
.DOUT(dout),
.EMPTY(empty),
.FULL(full),
.INT_CLK(),
.BACKUP(),
.BACKUP_MARKER(),
.PROG_EMPTY_THRESH(),
.PROG_EMPTY_THRESH_ASSERT(),
.PROG_EMPTY_THRESH_NEGATE(),
.PROG_FULL_THRESH(),
.PROG_FULL_THRESH_ASSERT(),
.PROG_FULL_THRESH_NEGATE(),
.RD_CLK(),
.RD_RST(),
.SRST(),
.WR_CLK(),
.WR_RST(),
.ALMOST_EMPTY(),
.ALMOST_FULL(),
.DATA_COUNT(),
.OVERFLOW(),
.PROG_EMPTY(),
.PROG_FULL(),
.VALID(),
.RD_DATA_COUNT(),
.UNDERFLOW(),
.WR_ACK(),
.WR_DATA_COUNT(),
.SBITERR(),
.DBITERR());
// synthesis translate_on
endmodule
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used *
* solely for design, simulation, implementation and creation of *
* design files limited to Xilinx devices or technologies. Use *
* with non-Xilinx devices or technologies is expressly prohibited *
* and immediately terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" *
* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR *
* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION *
* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION *
* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS *
* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, *
* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE *
* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY *
* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS *
* FOR A PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support *
* appliances, devices, or systems. Use in such applications are *
* expressly prohibited. *
* *
* (c) Copyright 1995-2007 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
// You must compile the wrapper file shift_reg_32x16.v when simulating
// the core, shift_reg_32x16. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
`timescale 1ns/1ps
module shift_reg_32x16(
clk,
din,
rd_en,
rst,
wr_en,
dout,
empty,
full);
input clk;
input [15 : 0] din;
input rd_en;
input rst;
input wr_en;
output [15 : 0] dout;
output empty;
output full;
// synthesis translate_off
FIFO_GENERATOR_V4_2 #(
.C_COMMON_CLOCK(1),
.C_COUNT_TYPE(0),
.C_DATA_COUNT_WIDTH(5),
.C_DEFAULT_VALUE("BlankString"),
.C_DIN_WIDTH(16),
.C_DOUT_RST_VAL("0"),
.C_DOUT_WIDTH(16),
.C_ENABLE_RLOCS(0),
.C_FAMILY("virtex2p"),
.C_FULL_FLAGS_RST_VAL(1),
.C_HAS_ALMOST_EMPTY(0),
.C_HAS_ALMOST_FULL(0),
.C_HAS_BACKUP(0),
.C_HAS_DATA_COUNT(0),
.C_HAS_INT_CLK(0),
.C_HAS_MEMINIT_FILE(0),
.C_HAS_OVERFLOW(0),
.C_HAS_RD_DATA_COUNT(0),
.C_HAS_RD_RST(0),
.C_HAS_RST(1),
.C_HAS_SRST(0),
.C_HAS_UNDERFLOW(0),
.C_HAS_VALID(0),
.C_HAS_WR_ACK(0),
.C_HAS_WR_DATA_COUNT(0),
.C_HAS_WR_RST(0),
.C_IMPLEMENTATION_TYPE(1),
.C_INIT_WR_PNTR_VAL(0),
.C_MEMORY_TYPE(3),
.C_MIF_FILE_NAME("BlankString"),
.C_OPTIMIZATION_MODE(0),
.C_OVERFLOW_LOW(0),
.C_PRELOAD_LATENCY(1),
.C_PRELOAD_REGS(0),
.C_PRIM_FIFO_TYPE("512x36"),
.C_PROG_EMPTY_THRESH_ASSERT_VAL(2),
.C_PROG_EMPTY_THRESH_NEGATE_VAL(3),
.C_PROG_EMPTY_TYPE(0),
.C_PROG_FULL_THRESH_ASSERT_VAL(30),
.C_PROG_FULL_THRESH_NEGATE_VAL(29),
.C_PROG_FULL_TYPE(0),
.C_RD_DATA_COUNT_WIDTH(5),
.C_RD_DEPTH(32),
.C_RD_FREQ(1),
.C_RD_PNTR_WIDTH(5),
.C_UNDERFLOW_LOW(0),
.C_USE_DOUT_RST(1),
.C_USE_ECC(0),
.C_USE_EMBEDDED_REG(0),
.C_USE_FIFO16_FLAGS(0),
.C_USE_FWFT_DATA_COUNT(0),
.C_VALID_LOW(0),
.C_WR_ACK_LOW(0),
.C_WR_DATA_COUNT_WIDTH(5),
.C_WR_DEPTH(32),
.C_WR_FREQ(1),
.C_WR_PNTR_WIDTH(5),
.C_WR_RESPONSE_LATENCY(1))
inst (
.CLK(clk),
.DIN(din),
.RD_EN(rd_en),
.RST(rst),
.WR_EN(wr_en),
.DOUT(dout),
.EMPTY(empty),
.FULL(full),
.INT_CLK(),
.BACKUP(),
.BACKUP_MARKER(),
.PROG_EMPTY_THRESH(),
.PROG_EMPTY_THRESH_ASSERT(),
.PROG_EMPTY_THRESH_NEGATE(),
.PROG_FULL_THRESH(),
.PROG_FULL_THRESH_ASSERT(),
.PROG_FULL_THRESH_NEGATE(),
.RD_CLK(),
.RD_RST(),
.SRST(),
.WR_CLK(),
.WR_RST(),
.ALMOST_EMPTY(),
.ALMOST_FULL(),
.DATA_COUNT(),
.OVERFLOW(),
.PROG_EMPTY(),
.PROG_FULL(),
.VALID(),
.RD_DATA_COUNT(),
.UNDERFLOW(),
.WR_ACK(),
.WR_DATA_COUNT(),
.SBITERR(),
.DBITERR());
// synthesis translate_on
endmodule
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used *
* solely for design, simulation, implementation and creation of *
* design files limited to Xilinx devices or technologies. Use *
* with non-Xilinx devices or technologies is expressly prohibited *
* and immediately terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" *
* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR *
* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION *
* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION *
* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS *
* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, *
* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE *
* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY *
* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS *
* FOR A PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support *
* appliances, devices, or systems. Use in such applications are *
* expressly prohibited. *
* *
* (c) Copyright 1995-2007 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
// You must compile the wrapper file rtable_256x8.v when simulating
// the core, rtable_256x8. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
`timescale 1ns/1ps
module rtable_256x8(
addr,
clk,
din,
dout,
sinit,
we);
input [7 : 0] addr;
input clk;
input [7 : 0] din;
output [7 : 0] dout;
input sinit;
input we;
// synthesis translate_off
BLKMEMSP_V6_2 #(
.c_addr_width(8),
.c_default_data("0"),
.c_depth(256),
.c_enable_rlocs(0),
.c_has_default_data(1),
.c_has_din(1),
.c_has_en(0),
.c_has_limit_data_pitch(0),
.c_has_nd(0),
.c_has_rdy(0),
.c_has_rfd(0),
.c_has_sinit(1),
.c_has_we(1),
.c_limit_data_pitch(18),
.c_mem_init_file("mif_file_16_1"),
.c_pipe_stages(1),
.c_reg_inputs(0),
.c_sinit_value("0"),
.c_width(8),
.c_write_mode(1),
.c_ybottom_addr("0"),
.c_yclk_is_rising(1),
.c_yen_is_high(1),
.c_yhierarchy("hierarchy1"),
.c_ymake_bmm(0),
.c_yprimitive_type("2kx9"),
.c_ysinit_is_high(1),
.c_ytop_addr("1024"),
.c_yuse_single_primitive(0),
.c_ywe_is_high(1),
.c_yydisable_warnings(0))
inst (
.ADDR(addr),
.CLK(clk),
.DIN(din),
.DOUT(dout),
.SINIT(sinit),
.WE(we),
.EN(),
.ND(),
.RFD(),
.RDY());
// synthesis translate_on
// XST black box declaration
// box_type "black_box"
// synthesis attribute box_type of rtable_256x8 is "black_box"
endmodule
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 00:21:10 05/28/2010
// Design Name: Control
// Module Name: D:/School/thesis/icsim/hdl/Control/Control_tb.v
// Project Name: Control
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: Control
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module Control_tb;
// Inputs
reg clock;
reg reset;
reg [15:0] rx_word;
reg rx_word_valid;
reg tx_ack;
reg [9:0] sim_time;
reg sim_time_tick;
reg sim_error_in;
reg sim_quiescent;
reg [15:0] stats_word;
// Outputs
wire control_error;
wire sim_error;
wire [15:0] tx_word;
wire tx_word_valid;
wire sim_reset;
wire sim_enable;
wire stop_injection;
wire measure;
wire [15:0] config_word;
wire config_valid;
wire stats_shift;
reg [63:0] data_word;
// Instantiate the Unit Under Test (UUT)
Control uut (
.clock(clock),
.reset(reset),
.control_error(control_error),
.sim_error(sim_error),
.rx_word(rx_word),
.rx_word_valid(rx_word_valid),
.tx_word(tx_word),
.tx_word_valid(tx_word_valid),
.tx_ack(tx_ack),
.sim_reset(sim_reset),
.sim_enable(sim_enable),
.stop_injection(stop_injection),
.measure(measure),
.sim_time(sim_time),
.sim_time_tick(sim_time_tick),
.sim_error_in(sim_error_in),
.sim_quiescent(sim_quiescent),
.config_word(config_word),
.config_valid(config_valid),
.stats_shift(stats_shift),
.stats_word(data_word[15:0])
);
initial begin
// Initialize Inputs
clock = 0;
reset = 0;
rx_word = 0;
rx_word_valid = 0;
tx_ack = 0;
sim_time = 0;
sim_time_tick = 0;
sim_error_in = 0;
sim_quiescent = 0;
stats_word = 0;
// Wait 100 ns for global reset to finish
#2 reset = 1;
#100 reset = 0;
#100;
// Add stimulus here
rx_word = 16'h0000; // Reset
rx_word_valid = 1;
#10;
rx_word_valid = 0;
#10;
rx_word = 16'h2004; // Set timer
rx_word_valid = 1;
#10;
rx_word_valid = 0;
#10;
rx_word = 16'h3BEF; // Send config words
rx_word_valid = 1;
#10;
rx_word_valid = 0;
#10;
rx_word = 16'h0005; // 5 Config words
rx_word_valid = 1;
#10;
rx_word = 16'hCA01; // Config 1
#10;
rx_word_valid = 0;
#10;
rx_word = 16'hBE02; // Config 2
rx_word_valid = 1;
#10;
rx_word_valid = 0;
#20;
rx_word = 16'hDF03; // Config 3
rx_word_valid = 1;
#10;
rx_word = 16'hEC04; // Config 4
#10;
rx_word = 16'hDB35; // Config 5
#10;
rx_word_valid = 0;
// Request data words
#10;
rx_word = 16'h4779;
rx_word_valid = 1;
#10;
rx_word = 16'h003;
#10;
rx_word_valid = 0;
#10 tx_ack = tx_word_valid;
#10 tx_ack = 0;
#10 tx_ack = tx_word_valid;
#10 tx_ack = 0;
#20 tx_ack = tx_word_valid;
#10 tx_ack = 0;
// Request states
#10;
rx_word = 16'h5864;
rx_word_valid = 1;
sim_time = 16'hEACB;
#10 rx_word_valid = 0;
#10 tx_ack = tx_word_valid;
#10 tx_ack = 0;
#10 tx_ack = tx_word_valid;
#10 tx_ack = 0;
#10 tx_ack = tx_word_valid;
#10 tx_ack = 0;
#10 tx_ack = tx_word_valid;
#10 tx_ack = 0;
// Write regular command
#10;
rx_word = 16'h100B; // LSB = 4'b1011 (timer_enable, stop_injection, measure, sim_enable}
rx_word_valid = 1;
#10;
rx_word_valid = 0;
sim_time_tick = 1;
#10 sim_time_tick = 0;
#10 sim_time_tick = 1;
#10 sim_time_tick = 0;
#10 sim_time_tick = 1;
#10 sim_time_tick = 0;
#10 sim_time_tick = 1;
#10 sim_time_tick = 0;
#10 sim_time_tick = 1;
#10 sim_time_tick = 0;
#10 sim_time_tick = 1;
#10 sim_time_tick = 0;
#10 sim_time_tick = 1;
#10 sim_time_tick = 0;
#10;
rx_word = 16'h100F; // Enable stop_injection
rx_word_valid = 1;
end
always #5 clock = ~clock;
always @(posedge clock)
begin
if (reset)
data_word <= 64'h1234_ABCD_5678_EF90;
else if (stats_shift)
data_word <= {data_word[15:0], data_word[63:16]};
end
endmodule
|
`timescale 1ns / 1ps
/* Testbench for CreditCounter
*/
module CreditCounter_tb;
parameter WIDTH = 4; // Width of credit counter
reg clock;
reg reset;
reg enable;
reg sim_time_tick;
reg [WIDTH-1: 0] config_in;
reg config_in_valid;
wire [WIDTH-1: 0] config_out;
wire config_out_valid;
reg credit_in_valid;
wire credit_ack;
reg decrement;
wire [WIDTH-1: 0] count_out;
// Unit-under-test
CreditCounter #(.WIDTH(WIDTH)) uut (
.clock (clock),
.reset (reset),
.enable (enable),
.sim_time_tick (sim_time_tick),
.config_in (config_in),
.config_in_valid (config_in_valid),
.config_out (config_out),
.config_out_valid (config_out_valid),
.credit_in_valid (credit_in_valid),
.credit_ack (credit_ack),
.decrement (decrement),
.count_out (count_out));
initial begin
clock = 0;
reset = 0;
enable = 0;
sim_time_tick = 0;
config_in = 0;
config_in_valid = 0;
credit_in_valid = 0;
decrement = 0;
#1 reset = 1;
#20 reset = 0;
#20 // Start configuration
config_in_valid = 1;
config_in = 4'h5;
#10
config_in_valid = 0;
#10 enable = 1;
// Use credit
#10 decrement = 1;
#10 decrement = 1;
#10 decrement = 1;
#10 decrement = 0;
// Add credit
#10 credit_in_valid = 1;
#10 credit_in_valid = 1;
#10 credit_in_valid = 0;
sim_time_tick = 1;
#10 sim_time_tick = 0;
// Add and use at the same time
#10 credit_in_valid = 1; decrement = 1;
#10 credit_in_valid = 0;
#10 decrement = 0;
#10 sim_time_tick = 1;
#10 sim_time_tick = 0;
end
always #5 clock = ~clock;
endmodule
|
`timescale 1ns / 1ps
/* Testbench for DistroRAM
*/
module DistroRAM_tb ();
parameter WIDTH = 8;
parameter LOG_DEP = 3;
localparam DEPTH = 1 << LOG_DEP;
reg clock;
reg wen;
reg [LOG_DEP-1: 0] addr;
reg [WIDTH-1: 0] din;
wire [WIDTH-1: 0] dout;
DistroRAM #(.WIDTH(WIDTH), .LOG_DEP(LOG_DEP)) uut (
.clock (clock),
.wen (wen),
.addr (addr),
.din (din),
.dout (dout));
// Write to FIFO Task
task write_value;
input [WIDTH-1: 0] val;
input [LOG_DEP-1:0] id;
begin
@(negedge clock);
wen <= 1'b1;
din <= val;
addr <= id;
end
endtask
task read_value;
input [LOG_DEP-1: 0] id;
begin
@(negedge clock);
addr <= id;
end
endtask
initial begin
clock = 0;
wen = 0;
addr = 0;
din = 0;
#20;
write_value (8'hCA, 0);
write_value (8'hBE, 2);
write_value (8'hDF, 5);
write_value (8'hEA, 1);
write_value (8'h99, 4);
write_value (8'h80, 3);
@(negedge clock); wen = 0;
read_value (2);
write_value (8'h35, 7);
write_value (8'h22, 6);
@(negedge clock); wen = 0;
read_value (0);
read_value (1);
read_value (2);
read_value (3);
read_value (4);
read_value (5);
read_value (6);
read_value (7);
end
always #5 clock = ~clock;
endmodule
|
`timescale 1ns / 1ps
/* Testbench for RAMFIFO
*/
module FIFO_tb ();
parameter WIDTH = 16;
parameter LOG_DEP = 3;
localparam DEPTH = 1 << LOG_DEP;
reg clock;
reg clock_2x;
reg reset;
reg [WIDTH-1: 0] data_in;
reg write;
reg read;
wire [WIDTH-1: 0] data_out;
wire full;
wire empty;
wire has_data;
wire [WIDTH-1: 0] srl_data_out;
wire srl_full;
wire srl_empty;
wire [WIDTH-1: 0] slow_data_out;
wire slow_full;
wire slow_empty;
wire slow_has_data;
reg [WIDTH-1: 0] r_data;
reg [WIDTH-1: 0] r_data_srl;
reg [WIDTH-1: 0] r_data_fwft;
reg wbusy;
integer i;
RAMFIFO_single #(.WIDTH(WIDTH), .LOG_DEP(LOG_DEP)) uut (
.clock (clock),
.clock_2x (clock_2x),
.reset (reset),
.data_in (data_in),
.data_out (data_out),
.write (write),
.read (read),
.full (full),
.empty (empty),
.has_data (has_data));
srl_fifo #(.WIDTH(WIDTH), .LOG_LEN(LOG_DEP)) srl (
.clock (clock),
.reset (reset),
.data_in (data_in),
.data_out (srl_data_out),
.write (write),
.read (read),
.full (srl_full),
.empty (srl_empty));
RAMFIFO_single_slow #(.WIDTH(WIDTH), .LOG_DEP(LOG_DEP)) slow (
.clock (clock_2x),
.reset (reset),
.data_in (data_in),
.data_out (slow_data_out),
.write (write & ~wbusy),
.read (read),
.full (slow_full),
.empty (slow_empty),
.has_data (slow_has_data));
/*RAMFIFO_fwft #(.WIDTH(WIDTH), .LOG_DEP(LOG_DEP)) latch_fifo (
.clock (clock),
.reset (reset),
.data_in (data_in),
.data_out (latch_data_out),
.write (write),
.read (read),
.full (latch_full),
.empty (latch_empty));*/
// Write to FIFO Task
task write_value;
input [WIDTH-1: 0] val;
begin
@(posedge clock);
#12 write <= 1'b1;
data_in <= val;
end
endtask
task read_write;
input [WIDTH-1: 0] val;
begin
@(posedge clock);
#12 write <= 1'b1;
read <= 1'b1;
data_in <= val;
end
endtask
task read_value;
begin
@(posedge clock);
#12 read <= 1'b1;
end
endtask
initial
begin
clock = 1'b0;
clock_2x = 1'b1;
reset = 1'b0;
write = 1'b0;
read = 1'b0;
data_in = {(WIDTH){1'b0}};
#1 reset = 1'b1;
#100 reset = 1'b0;
for (i = 1; i < DEPTH + 2; i = i + 1)
begin
write_value (i);
end
@(posedge clock); #12 read = 1'b0; write = 1'b0;
read_value ();
read_value ();
read_value ();
read_value ();
read_write (16'hCAFE);
read_write (16'hBEDF);
@(negedge clock); read = 1'b0; write = 1'b0;
for (i = 0; i < DEPTH - 1; i = i + 1)
begin
read_value ();
end
@(posedge clock); #12 read = 1'b0; write = 1'b0;
write_value (16'hEDAF);
write_value (16'h2345);
write_value (16'h3456);
read_write (16'h1234);
/*@(negedge clock); read = 1'b0; write = 1'b0;
read_value (1);
read_value (1);
read_value (1);*/
@(posedge clock); #12 read = 1'b0; write = 1'b0;
end
always #10 clock = ~clock;
always #5 clock_2x = ~clock_2x;
reg [WIDTH-1:0] rdout;
reg [WIDTH-1:0] rsrl_dout;
reg [WIDTH-1:0] rslow_dout;
always @(posedge clock or posedge reset)
begin
if (reset)
begin
rdout <= {(WIDTH){1'b0}};
rsrl_dout <= {(WIDTH){1'b0}};
rslow_dout <= {(WIDTH){1'b0}};
end
else
begin
if (has_data)
rdout <= data_out;
if (~srl_empty)
rsrl_dout <= srl_data_out;
if (slow_has_data)
rslow_dout <= slow_data_out;
end
end
// Make sure we write to RAMFIFO_single_slow once every 2 cycles
always @(posedge clock_2x or posedge reset)
begin
if (reset)
wbusy <= 1'b0;
else
if (wbusy)
wbusy <= 1'b0;
else
wbusy <= write;
end
endmodule
|
`timescale 1ns / 1ps
/* Testbench for FlitQueue
*/
`include "../../const.v"
module FlitQueue_tb;
parameter HADDR = 45;
parameter LOG_NVCS = 1;
localparam NVCS = 1 << LOG_NVCS;
// Inputs / Outputs
reg clock;
reg reset;
reg enable;
reg [`TS_WIDTH-1: 0] sim_time;
reg sim_time_tick;
wire error;
// Config interface
reg [15: 0] config_in;
reg config_in_valid;
wire [15: 0] config_out;
wire config_out_valid;
// Flit interface (1 in, NVCS out)
wire [NVCS-1: 0] flit_full;
reg [`FLIT_WIDTH-1:0] flit_in;
reg flit_in_valid;
reg test;
reg [`ADDR_WIDTH-1:0] nexthop_in;
wire flit_ack;
wire [NVCS*`FLIT_WIDTH-1:0] flit_out;
wire [NVCS-1: 0] flit_out_valid;
reg [NVCS-1: 0] dequeue;
// Credit interface (1 in, 1 out)
wire credit_full;
reg [`CREDIT_WIDTH-1:0] credit_in;
reg credit_in_valid;
reg [`ADDR_WIDTH-1:0] credit_nexthop_in;
wire credit_ack;
wire [`CREDIT_WIDTH-1:0] credit_out;
wire credit_out_valid;
reg credit_dequeue;
import "DPI-C" context task c_init ();
import "DPI-C" context task test_fq (output reset,
output enable,
output [`TS_WIDTH-1:0] tsim,
output tsim_tick,
output config_in_valid,
output [15: 0] config_in,
output flit_in_valid,
output [`FLIT_WIDTH-1:0] flit_in,
output [`ADDR_WIDTH-1:0] nexthop_in,
output [NVCS-1:0] dequeue,
input hw_flit_ack,
input [NVCS-1:0] hw_flit_out_valid,
input [NVCS*`FLIT_WIDTH-1:0] hw_flit_out);
import "DPI-C" context function void check_fq (
input flit_ack,
input [NVCS-1:0] hw_flit_out_valid);
export "DPI-C" function v_disp;
function void v_disp (input string s);
begin
$display ("%s", s);
end
endfunction
// Unit under test
FlitQueue #(.HADDR(HADDR), .LOG_NVCS(LOG_NVCS)) uut (
.clock (clock),
.reset (reset),
.enable (enable),
.sim_time (sim_time),
.sim_time_tick (sim_time_tick),
.error (error),
.config_in (config_in),
.config_in_valid (config_in_valid),
.config_out (config_out),
.config_out_valid (config_out_valid),
.flit_full (flit_full),
.flit_in_valid (flit_in_valid),
.flit_in (flit_in),
.nexthop_in (nexthop_in),
.flit_ack (flit_ack),
.flit_out (flit_out),
.flit_out_valid (flit_out_valid),
.dequeue (dequeue),
.credit_full (credit_full),
.credit_in (credit_in),
.credit_in_valid (credit_in_valid),
.credit_nexthop_in (credit_nexthop_in),
.credit_out (credit_out),
.credit_out_valid (credit_out_valid),
.credit_dequeue (credit_dequeue),
.credit_ack (credit_ack));
initial begin
clock = 0;
reset = 0;
credit_in = 0;
credit_in_valid = 0;
credit_nexthop_in = 0;
credit_dequeue = 0;
c_init ();
v_disp ("After initialization");
end
always #5 clock = ~clock;
always @(posedge clock)
begin
test_fq (reset, enable, sim_time, sim_time_tick, config_in_valid, config_in,
flit_in_valid, flit_in, nexthop_in, dequeue,
flit_ack, flit_out_valid, flit_out);
end
endmodule
|
`timescale 1ns / 1ps
/* Testbench for FQCtrl
*/
`include "../../const.v"
module FQCtrl_tb;
// Inputs
reg clock;
reg reset;
reg enable;
reg [ 9: 0] sim_time;
reg measure;
reg [ 9: 0] psize;
reg [ 7: 0] sendto;
reg obuf_full;
reg [31: 0] threshold;
reg [ 7: 0] total_packets_injected;
reg [15: 0] config_in;
reg config_in_valid;
// Outputs
wire [35: 0] tg_flit_out;
wire tg_ready;
wire tg_tick_rng;
wire [31: 0] tg_rand_wire;
wire tg_rand_below_threshold;
wire [`TS_WIDTH-1:0] fq_ts_out;
wire [15: 0] config_out;
wire config_out_valid;
FQCtrl fq_ctrl (
.clock (clock),
.reset (reset),
.in_ready (tg_ready),
.in_timestamp (tg_flit_out[32:23]),
.out_timestamp (fq_ts_out),
.config_in (config_in),
.config_in_valid (config_in_valid),
.config_out (config_out),
.config_out_valid (config_out_valid));
// TGBernoulli to generate traffic for the FQ
TGBernoulliFSM tg (
.clock(clock),
.reset(reset),
.enable(enable),
.sim_time(sim_time),
.measure(measure),
.psize(psize),
.sendto(sendto),
.obuf_full(obuf_full),
.rand_below_threshold(tg_rand_below_threshold),
.flit_out(tg_flit_out),
.ready(tg_ready),
.tick_rng(tg_tick_rng)
);
RNG rng (
.clock (clock),
.reset (reset),
.enable (tg_tick_rng),
.rand_out (tg_rand_wire),
.config_in_valid (1'b0),
.config_in (8'h00),
.config_out_valid (),
.config_out ());
assign tg_rand_below_threshold = (tg_rand_wire < threshold) ? 1'b1 : 1'b0;
integer i, j, z;
initial begin
// Initialize Inputs
clock = 0;
reset = 0;
enable = 0;
sim_time = 0;
measure = 0;
psize = 3;
sendto = 8'hCA;
obuf_full = 0;
threshold = 32'h1999_9999;
config_in = 16'h0104;
config_in_valid = 0;
#5 reset = 1;
// Wait 100 ns for global reset to finish
#92 reset = 0;
#10 config_in_valid = 1;
#10 config_in_valid = 0;
#10 enable = 1;
measure = 1;
// Add stimulus here
for (z = 0; z < 5; z = z + 1)
begin
for (i = 0; i < 30; i = i + 1)
begin
if (z > 3 && i > 20) measure = 1'b0;
for (j = 0; j < 3; j = j + 1)
#10;
sim_time = sim_time + 1;
end
obuf_full = ~obuf_full;
end
end
always #5 clock = ~clock;
always @(posedge clock or posedge reset)
begin
if (reset)
begin
total_packets_injected <= 8'h00;
end
else
begin
if (tg_ready & tg_flit_out[35])
total_packets_injected <= total_packets_injected + 1;
end
end
endmodule
|
`timescale 1ns / 1ps
/* Testbench for mux_Nto1.v and mux_Nto1_decoded.v
*/
module mux_tb;
// Try 4-bit 8-to-1 mux
// Inputs
reg [31: 0] in;
reg [ 2: 0] esel;
wire [ 7: 0] dsel;
// Outputs
wire [ 1: 0][ 3: 0] mux_out;
// Decoder
decoder_N #(.LOG_SIZE(3)) test_dec (
.encoded (esel),
.decoded (dsel));
// Encoded 8-to-1 MUX
mux_Nto1 #(.SIZE(8)) muxe (
.in (in),
.sel (esel),
.out (mux_out[0]));
// Decoded 8-to-1 MUX
mux_Nto1_decoded #(.SIZE(8)) muxd (
.in (in),
.sel (dsel),
.out (mux_out[1]));
integer i;
initial begin
in = 32'hABCDEF12;
for (i = 0; i < 8; i = i + 1)
begin
#20 esel = i;
end
end
endmodule
|
`timescale 1ns / 1ps
/* PacketPlayer Testbench
*/
`include "const.v"
module PacketPlayer_tb;
reg clock;
reg reset;
reg enable;
reg [9:0] sim_time;
wire error;
wire is_quiescent;
reg [31:0] packet_in;
reg packet_in_valid;
wire packet_request;
wire [1:0] flit_out_valid;
reg [1:0] r_flit_out_valid;
PacketPlayer #(.HADDR(8'h1B), .NVCS(2)) uut (
.clock (clock),
.reset (reset),
.enable (enable),
.sim_time (sim_time),
.error (error),
.is_quiescent (is_quiescent),
.config_in (16'h00),
.config_in_valid (1'b0),
.config_out (),
.config_out_valid (),
.stats_shift (1'b0),
.stats_in (16'h00),
.stats_out (),
.packet_in (packet_in),
.packet_in_valid (packet_in_valid),
.packet_request (packet_request),
.flit_in (36'h0),
.flit_in_valid (1'b0),
.nexthop_in (5'h00),
.flit_ack (),
.flit_out (),
.flit_out_valid (flit_out_valid),
.dequeue (r_flit_out_valid),
.credit_out (),
.credit_out_valid ());
always @(posedge clock)
begin
if (reset)
r_flit_out_valid <= 0;
else
r_flit_out_valid <= flit_out_valid;
end
reg [1:0] counter;
always @(posedge clock)
begin
if (reset)
counter <= 0;
else if (enable)
counter <= counter + 1;
end
always @(posedge clock)
begin
if (reset)
sim_time <= 0;
else if (enable == 1'b1 && (&counter == 1))
sim_time <= sim_time + 1;
end
always #5 clock = ~clock;
reg measure;
reg [9:0] inj_time;
reg vc;
reg [3:0] psize;
reg [6:0] dest_id;
reg [6:0] src_id;
integer i;
initial begin
clock = 0;
reset = 0;
enable = 0;
packet_in = 0;
packet_in_valid = 0;
measure = 1'b0;
inj_time = 10'h0;
vc = 0;
psize = 0;
dest_id = 0;
src_id = 0;
#1 reset = 1;
#20 reset = 0;
#10 enable = 1;
for (i = 0; i < 60; i = i + 1)
begin
#10;
if (i < 5)
measure = 1'b0;
else
measure = 1'b1;
inj_time = i;
vc = i >> 1;
psize = 3;
if (packet_request)
begin
packet_in_valid = 1;
if (i%2 == 1)
begin
packet_in[31] = 1'b0;
packet_in[`P_MEASURE] = measure;
packet_in[`P_INJ] = inj_time;
packet_in[`P_VC] = vc;
packet_in[`P_SIZE] = psize;
packet_in[`P_DEST] = 8'hEE;
packet_in[`P_SRC] = 8'h1A;
$display ("%x measure %d inj %d vc %d log_psize %d dest EE src 1A",
packet_in, measure, inj_time, vc, psize);
end
else
begin
packet_in[31] = 1'b0;
packet_in[`P_MEASURE] = measure;
packet_in[`P_INJ] = inj_time;
packet_in[`P_VC] = vc;
packet_in[`P_SIZE] = psize;
packet_in[`P_DEST] = 8'h10;
packet_in[`P_SRC] = 8'h1B;
$display ("%x measure %d inj %d vc %d log_psize %d dest %x src %x",
packet_in, measure, inj_time, vc, psize, packet_in[`P_DEST], packet_in[`P_SRC]);
end
end
end
packet_in_valid = 0;
end
endmodule
|
`timescale 1ns / 1ps
/* Testbench for RAMFIFO
*/
module RAMFIFO_tb ();
parameter WIDTH = 16;
parameter LOG_DEP = 3;
parameter LOG_CTX = 3;
localparam DEPTH = 1 << LOG_DEP;
localparam NUM_CTX = 1 << LOG_CTX;
reg clock;
reg clock_2x;
reg reset;
reg [LOG_CTX-1: 0] wcc;
reg [LOG_CTX-1: 0] rcc;
reg [WIDTH-1: 0] data_in;
reg write;
reg read;
wire [NUM_CTX-1:0][WIDTH-1:0] data_out;
wire [NUM_CTX-1:0] full;
wire [NUM_CTX-1:0] empty;
wire [NUM_CTX-1:0] has_data;
wire error;
wire [NUM_CTX-1:0][WIDTH-1:0] slow_data_out;
wire [NUM_CTX-1:0] slow_full;
wire [NUM_CTX-1:0] slow_empty;
wire [NUM_CTX-1:0] slow_has_data;
wire slow_error;
wire [NUM_CTX-1:0][WIDTH-1:0] pack_data_out;
wire [NUM_CTX-1:0] pack_full;
wire [NUM_CTX-1:0] pack_empty;
wire [NUM_CTX-1:0] pack_has_data;
wire pack_error;
reg auto_read;
reg [WIDTH-1: 0] r_auto_read_dout;
reg wbusy;
integer i, c;
RAMFIFO #(.WIDTH(WIDTH), .LOG_DEP(LOG_DEP), .LOG_CTX(LOG_CTX)) uut (
.clock (clock),
.clock_2x (clock_2x),
.reset (reset),
.wcc_id (wcc),
.rcc_id (rcc),
.data_in (data_in),
.data_out (data_out),
.write (write),
.read (read),
.full (full),
.empty (empty),
.has_data (has_data),
.error (error));
RAMFIFO_slow #(.WIDTH(WIDTH), .LOG_DEP(LOG_DEP), .LOG_CTX(LOG_CTX)) slow (
.clock (clock_2x),
.reset (reset),
.wcc_id (wcc),
.rcc_id (rcc),
.data_in (data_in),
.data_out (slow_data_out),
.write (write & ~wbusy),
.read (read),
.full (slow_full),
.empty (slow_empty),
.has_data (slow_has_data),
.error (slow_error));
PackedFIFO #(.WIDTH(WIDTH), .logDEPTH(LOG_DEP), .logN(LOG_CTX)) pack (
.clock (clock_2x),
.reset (reset),
.wid (wcc),
.rid (rcc),
.data_in (data_in),
.data_out (pack_data_out),
.write (write & ~wbusy),
.read (read),
.full (pack_full),
.empty (pack_empty),
.has_data (pack_has_data),
.error (pack_error));
reg [NUM_CTX-1:0] comp_error_slow;
reg [NUM_CTX-1:0] comp_error_pack;
always @(*)
begin
for (i = 0; i < NUM_CTX; i = i + 1)
begin
if (has_data[i] == 1 && data_out[i] != slow_data_out[i])
comp_error_slow = 1;
else
comp_error_slow = 0;
if (has_data[i] == 1 && data_out[i] != pack_data_out[i])
comp_error_pack = 1;
else
comp_error_pack = 0;
end
end
// Write to FIFO Task
task write_value;
input [WIDTH-1: 0] val;
input [LOG_CTX-1:0] id;
begin
@(negedge clock);
#12 write <= 1'b1;
data_in <= val;
wcc <= id;
end
endtask
task read_write;
input [WIDTH-1: 0] val;
input [LOG_CTX-1:0] wid;
input [LOG_CTX-1:0] rid;
begin
@(negedge clock);
#12 write <= 1'b1;
read <= 1'b1;
wcc <= wid;
rcc <= rid;
data_in <= val;
end
endtask
task read_value;
input [LOG_CTX-1:0] id;
begin
@(negedge clock);
#12 read <= 1'b1;
rcc <= id;
end
endtask
initial
begin
clock = 1'b0;
clock_2x = 1'b1;
reset = 1'b0;
write = 1'b0;
read = 1'b0;
data_in = {(WIDTH){1'b0}};
wcc = 0;
rcc = 0;
auto_read = 0;
#1 reset = 1'b1;
#100 reset = 1'b0;
for (i = 0; i < DEPTH + 1; i = i + 1)
begin
for (c = 0; c < NUM_CTX; c = c + 1)
begin
write_value (i * NUM_CTX + c, c);
end
end
@(negedge clock); #12 read = 1'b0; write = 1'b0;
read_value (0);
read_value (1);
read_value (2);
read_value (3);
read_write (16'hCAFE, 1, 2);
read_write (16'hBEDF, 2, 1);
@(negedge clock); #12 read = 1'b0; write = 1'b0;
for (i = 0; i < DEPTH - 1; i = i + 1)
begin
read_value (1);
end
@(negedge clock); #12 read = 1'b0; write = 1'b0;
write_value (16'hEDAF, 1);
write_value (16'h2345, 1);
write_value (16'h3456, 1);
read_write (16'h1234, 1, 3);
/*@(negedge clock); read = 1'b0; write = 1'b0;
read_value (1);
read_value (1);
read_value (1);*/
@(negedge clock); #12 read = 1'b0; write = 1'b0;
// Start auto read from FIFO 1
rcc = 1;
auto_read = 1;
end
always @(*)
begin
if (auto_read == 1)
begin
read = ~empty[1];
end
end
always @(posedge clock or posedge reset)
begin
if (reset)
r_auto_read_dout <= 0;
else if (auto_read & read)
r_auto_read_dout <= data_out[1];
end
always #10 clock = ~clock;
always #5 clock_2x = ~clock_2x;
reg [NUM_CTX-1:0][WIDTH-1:0] rdout, rslow_dout;
always @(posedge clock or posedge reset)
begin
if (reset)
begin
rdout <= {(NUM_CTX*WIDTH){1'b0}};
rslow_dout <= {(NUM_CTX*WIDTH){1'b0}};
end
else
begin
rdout <= data_out;
rslow_dout <= slow_data_out;
end
end
always @(posedge clock_2x or posedge reset)
begin
if (reset)
wbusy <= 1'b0;
else
if (wbusy)
wbusy <= 1'b0;
else
wbusy <= write;
end
endmodule
|
`timescale 1ns / 1ps
/* Testbench for rotate_prio.v
*/
module rotate_prio_tb;
parameter SIZE = 10;
reg [SIZE-1: 0] in_valid;
reg [CLogB2(SIZE-1)-1: 0] prio;
wire [SIZE-1: 0] out_sel;
// Unit under test
rotate_prio #(.SIZE(SIZE)) uut (
.in_valid (in_valid),
.prio (prio),
.out_sel (out_sel));
// Ceil of log base 2
function integer CLogB2;
input [31:0] size;
integer i;
begin
i = size;
for (CLogB2 = 0; i > 0; CLogB2 = CLogB2 + 1)
i = i >> 1;
end
endfunction
initial begin
in_valid = 0;
prio = 0;
#10 in_valid = 10'b0000111101;
#10 prio = 1;
#10 prio = 2;
#10 prio = 3;
#10 prio = 4;
#10 prio = 5;
#10 prio = 6;
#10 prio = 7;
#10 prio = 8;
#10 prio = 9;
#10 prio = 10;
end
endmodule
|
`timescale 1ns / 1ps
/* Testbench for FlitQueue
*/
`include "../../const.v"
`include "../../math.v"
module Router_tb;
parameter HADDR = 45;
parameter NPORTS = 5;
parameter NVCS = 2;
localparam LOG_NPORTS = CLogB2(NPORTS-1);
localparam LOG_NVCS = CLogB2(NVCS-1);
localparam NINPUTS = NPORTS * NVCS;
// Inputs / Outputs
reg clock;
reg reset;
reg enable;
reg [`TS_WIDTH-1: 0] sim_time;
reg sim_time_tick;
wire error;
wire is_quiescent;
wire can_increment;
// RAM config interface
wire [15: 0] ram_config_out;
wire ram_config_out_valid;
// Config interface
reg [15: 0] config_in;
reg config_in_valid;
wire [15: 0] config_out;
wire config_out_valid;
// Flit interface
reg [`FLIT_WIDTH*NINPUTS-1: 0] flit_in;
reg [NINPUTS-1: 0] flit_in_valid;
wire [NINPUTS-1: 0] flit_ack;
wire [`FLIT_WIDTH-1: 0] flit_out;
wire flit_out_valid;
wire [`A_WIDTH-1: 0] nexthop_out;
reg dequeue;
// Credit interface
reg [`CREDIT_WIDTH*NPORTS-1: 0] credit_in;
reg [NPORTS-1: 0] credit_in_valid;
wire [NPORTS-1: 0] credit_ack;
wire [`CREDIT_WIDTH-1: 0] credit_out;
wire credit_out_valid;
wire [`A_WIDTH-1: 0] credit_out_nexthop;
reg credit_dequeue;
// Routing table interface
wire [`ADDR_WIDTH-1: 0] rtable_dest;
wire [LOG_NPORTS-1: 0] rtable_oport;
import "DPI-C" context task c_init ();
import "DPI-C" context task test (output reset,
output enable,
output [`TS_WIDTH-1:0] tsim,
output tsim_tick,
output config_in_valid,
output [15: 0] config_in,
output [`FLIT_WIDTH*NINPUTS-1:0] flit_in,
output [NINPUTS-1:0] flit_in_valid,
input flit_ack,
input [`FLIT_WIDTH-1:0] flit_out,
input flit_out_valid,
input [`A_WIDTH-1:0] nexthop_out,
output dequeue,
output [`CREDIT_WIDTH*NPORTS-1:0] credit_in,
output [NPORTS-1:0] credit_in_valid,
input credit_ack,
input [`CREDIT_WIDTH-1:0] credit_out,
input credit_out_valid,
input [`A_WIDTH-1:0] credit_out_nexthop,
output credit_dequeue);
export "DPI-C" function v_disp;
function void v_disp (input string s);
begin
$display ("%s", s);
end
endfunction
wire [15: 0] w_rtable_ram_config_in;
wire w_rtable_ram_config_in_valid;
// Unit under test
Router #(.HADDR(HADDR), .NPORTS(NPORTS), .NVCS(NVCS)) uut (
.clock (clock),
.clock_2x (1'b0),
.reset (reset),
.enable (enable),
.sim_time (sim_time),
.sim_time_tick (sim_time_tick),
.error (error),
.is_quiescent (is_quiescent),
.can_increment (can_increment),
.ram_config_in (config_in),
.ram_config_in_valid (config_in_valid),
.ram_config_out (w_rtable_ram_config_in),
.ram_config_out_valid (w_rtable_ram_config_in_valid),
.config_in (config_in),
.config_in_valid (config_in_valid),
.config_out (config_out),
.config_out_valid (config_out_valid),
.flit_in (flit_in),
.flit_in_valid (flit_in_valid),
.flit_ack (flit_ack),
.flit_out (flit_out),
.flit_out_valid (flit_out_valid),
.nexthop_out (nexthop_out),
.dequeue (dequeue),
.credit_in (credit_in),
.credit_in_valid (credit_in_valid),
.credit_ack (credit_ack),
.credit_out (credit_out),
.credit_out_valid (credit_out_valid),
.credit_out_nexthop (credit_out_nexthop),
.credit_dequeue (credit_dequeue),
.rtable_dest (rtable_dest),
.rtable_oport (rtable_oport));
// Routing Table
wire [`ADDR_WIDTH-LOG_NPORTS:0] w_temp;
RoutingTable_single rtable (
.clock (clock),
.reset (reset),
.enable (enable | w_rtable_ram_config_in_valid),
.ram_config_in (w_rtable_ram_config_in),
.ram_config_in_valid (w_rtable_ram_config_in_valid),
.ram_config_out (ram_config_out),
.ram_config_out_valid (ram_config_out_valid),
.dest_ina (rtable_dest),
.nexthop_outa ({w_temp, rtable_oport}),
.dest_inb (8'h00),
.nexthop_outb ());
initial begin
clock = 0;
reset = 0;
c_init ();
v_disp ("After initialization");
end
always #5 clock = ~clock;
always @(posedge clock)
begin
#1;
test ( .reset (reset),
.enable (enable),
.tsim (sim_time),
.tsim_tick (sim_time_tick),
.config_in (config_in),
.config_in_valid (config_in_valid),
.flit_in (flit_in),
.flit_in_valid (flit_in_valid),
.flit_ack (flit_ack),
.flit_out (flit_out),
.flit_out_valid (flit_out_valid),
.nexthop_out (nexthop_out),
.dequeue (dequeue),
.credit_in (credit_in),
.credit_in_valid (credit_in_valid),
.credit_ack (credit_ack),
.credit_out (credit_out),
.credit_out_valid (credit_out_valid),
.credit_out_nexthop (credit_out_nexthop),
.credit_dequeue (credit_dequeue));
end
endmodule
|
`timescale 1ns / 1ps
/* Testbench for FlitQueue
*/
`include "../../const.v"
module sim_tb;
parameter HADDR = 45;
parameter LOG_NVCS = 1;
localparam NVCS = 1 << LOG_NVCS;
// Inputs / Outputs
reg clock;
reg clock_2x;
reg reset;
reg enable;
wire sim_time_tick;
wire [`TS_WIDTH-1:0] sim_time;
wire error;
wire quiescent;
// Configuration and stats interfaces
reg [15: 0] config_in;
reg config_in_valid;
wire [15: 0] config_out;
wire config_out_valid;
reg stats_shift;
wire [15: 0] stats_out;
import "DPI-C" context task c_init ();
import "DPI-C" context task test_sim ( output reset,
output enable,
output config_in_valid,
output [15:0] config_in,
output stats_shift,
input [15:0] stats_out,
input quiescent,
input [9:0] sim_time);
export "DPI-C" function v_disp;
function void v_disp (input string s);
begin
$display ("%s", s);
end
endfunction
// 9-node (9x4 interconnect) simulator
sim9_8x8 sim (
.clock (clock),
.clock_2x (clock_2x),
.reset (reset),
.enable (enable),
.stop_injection (1'b0),
.measure (1'b1),
.sim_time_tick (sim_time_tick),
.sim_time (sim_time),
.error (error),
.quiescent (quiescent),
.config_in (config_in),
.config_in_valid (config_in_valid),
.config_out (config_out),
.config_out_valid (config_out_valid),
.stats_out (stats_out),
.stats_shift (stats_shift));
// Testbench setup
initial begin
clock = 0;
clock_2x = 1;
reset = 0;
enable = 0;
config_in = 0;
config_in_valid = 0;
stats_shift = 0;
c_init ();
v_disp ("After initialization");
end
always #10 clock = ~clock;
always #5 clock_2x = ~clock_2x;
always @(posedge clock)
begin
#1 test_sim (
.reset (reset),
.enable (enable),
.config_in_valid (config_in_valid),
.config_in (config_in),
.stats_shift (stats_shift),
.stats_out (stats_out),
.quiescent (quiescent),
.sim_time (sim_time));
end
endmodule
|
`timescale 1ns / 1ps
/* Testbench for TGBernoulli
*/
module TGBernoulli_tb;
// Inputs
reg clock;
reg reset;
reg enable;
reg [ 9: 0] sim_time;
reg measure;
reg [ 9: 0] psize;
reg [ 7: 0] sendto;
reg obuf_full;
reg [31: 0] threshold;
reg [ 1: 0][ 7: 0] total_packets_injected;
// Outputs
wire [35: 0] ut0_flit_out;
wire ut0_ready;
wire ut0_tick_rng;
wire [31: 0] ut0_rand_wire;
wire ut0_rand_below_threshold;
wire [35: 0] ut1_flit_out;
wire ut1_ready;
wire ut1_tick_rng;
wire [31: 0] ut1_rand_wire;
wire ut1_rand_below_threshold;
// Instantiate the Unit Under Test (UUT)
TGBernoulli ut0 (
.clock(clock),
.reset(reset),
.enable(enable),
.sim_time(sim_time),
.measure(measure),
.psize(psize),
.sendto(sendto),
.obuf_full(obuf_full),
.rand_below_threshold(ut0_rand_below_threshold),
.flit_out(ut0_flit_out),
.ready(ut0_ready),
.tick_rng(ut0_tick_rng)
);
TGBernoulliFSM ut1 (
.clock(clock),
.reset(reset),
.enable(enable),
.sim_time(sim_time),
.measure(measure),
.psize(psize),
.sendto(sendto),
.obuf_full(obuf_full),
.rand_below_threshold(ut1_rand_below_threshold),
.flit_out(ut1_flit_out),
.ready(ut1_ready),
.tick_rng(ut1_tick_rng)
);
RNG rng0 (
.clock (clock),
.reset (reset),
.enable (ut0_tick_rng),
.rand_out (ut0_rand_wire),
.config_in_valid (1'b0),
.config_in (8'h00),
.config_out_valid (),
.config_out ());
RNG rng1 (
.clock (clock),
.reset (reset),
.enable (ut1_tick_rng),
.rand_out (ut1_rand_wire),
.config_in_valid (1'b0),
.config_in (8'h00),
.config_out_valid (),
.config_out ());
assign ut0_rand_below_threshold = (ut0_rand_wire < threshold) ? 1'b1 : 1'b0;
assign ut1_rand_below_threshold = (ut1_rand_wire < threshold) ? 1'b1 : 1'b0;
integer i, j, z;
initial begin
// Initialize Inputs
clock = 0;
reset = 0;
enable = 0;
sim_time = 0;
measure = 0;
psize = 3;
sendto = 8'hCA;
obuf_full = 0;
threshold = 32'h1999_9999;
#5 reset = 1;
// Wait 100 ns for global reset to finish
#92 reset = 0;
#10 enable = 1;
measure = 1;
// Add stimulus here
for (z = 0; z < 5; z = z + 1)
begin
for (i = 0; i < 30; i = i + 1)
begin
if (z > 3 && i > 20) measure = 1'b0;
for (j = 0; j < 3; j = j + 1)
#10;
sim_time = sim_time + 1;
end
obuf_full = ~obuf_full;
end
end
always #5 clock = ~clock;
always @(posedge clock or posedge reset)
begin
if (reset)
begin
total_packets_injected[0] <= 8'h00;
total_packets_injected[1] <= 8'h00;
end
else
begin
if (ut0_ready)
total_packets_injected[0] <= total_packets_injected[0] + 1;
if (ut1_ready)
total_packets_injected[1] <= total_packets_injected[1] + 1;
end
end
endmodule
|
`timescale 1ns / 1ps
/* Testbench for FlitQueue
*/
`include "../../const.v"
module TrafficGen_tb;
parameter HADDR = 45;
parameter LOG_NVCS = 1;
localparam NVCS = 1 << LOG_NVCS;
localparam FULL_ADDR_WIDTH = `ADDR_WIDTH + LOG_NVCS;
// Inputs / Outputs
reg clock;
reg reset;
reg enable;
reg [`TS_WIDTH-1: 0] sim_time;
reg sim_time_tick;
wire error;
// Config interface
reg [15: 0] config_in;
reg config_in_valid;
wire [15: 0] config_out;
wire config_out_valid;
// Stats interface
reg stats_shift;
reg [15: 0] stats_in;
wire [15: 0] stats_out;
// Flit interface
reg [`FLIT_WIDTH-1:0] flit_in;
reg flit_in_valid;
reg [FULL_ADDR_WIDTH-1:0] nexthop_in;
wire flit_ack;
reg [NVCS-1: 0] dequeue;
wire [NVCS*`FLIT_WIDTH-1: 0] flit_out;
wire [NVCS-1: 0] flit_out_valid;
reg measure;
import "DPI-C" context task c_init ();
import "DPI-C" context task test_tg (output reset,
output enable,
output [`TS_WIDTH-1:0] tsim,
output tsim_tick,
output config_in_valid,
output [15: 0] config_in,
output stats_shift,
input [15: 0] hw_stats_out,
output flit_in_valid,
output [`FLIT_WIDTH-1:0] flit_in,
output [FULL_ADDR_WIDTH-1:0] nexthop_in,
output [NVCS-1:0] dequeue,
output measure,
input hw_flit_ack,
input [NVCS-1:0] hw_flit_out_valid,
input [NVCS*`FLIT_WIDTH-1:0] hw_flit_out);
export "DPI-C" function v_disp;
function void v_disp (input string s);
begin
$display ("%s", s);
end
endfunction
// Unit under test
TrafficGen #(.HADDR(HADDR), .LOG_NVCS(LOG_NVCS)) uut (
.clock (clock),
.reset (reset),
.enable (enable),
.sim_time (sim_time),
.sim_time_tick (sim_time_tick),
.error (error),
.config_in (config_in),
.config_in_valid (config_in_valid),
.config_out (config_out),
.config_out_valid (config_out_valid),
.stats_shift (stats_shift),
.stats_in (stats_in),
.stats_out (stats_out),
.flit_in (flit_in),
.flit_in_valid (flit_in_valid),
.nexthop_in (nexthop_in),
.flit_ack (flit_ack),
.flit_out (flit_out),
.flit_out_valid (flit_out_valid),
.dequeue (dequeue),
.measure (measure));
initial begin
clock = 0;
reset = 0;
enable = 0;
sim_time = 0;
sim_time_tick = 0;
config_in = 0;
config_in_valid = 0;
stats_shift = 0;
stats_in = 0;
flit_in = 0;
flit_in_valid = 0;
nexthop_in = 0;
dequeue = 0;
measure = 0;
c_init ();
v_disp ("After initialization");
end
always #5 clock = ~clock;
always @(posedge clock)
begin
#1 test_tg (reset, enable, sim_time, sim_time_tick,
config_in_valid, config_in, stats_shift, stats_out,
flit_in_valid, flit_in, nexthop_in, dequeue, measure,
flit_ack, flit_out_valid, flit_out);
end
endmodule
|
`timescale 1ns / 1ps
/* Top level module that communicates with the PC
*/
module dart (
input SYSTEM_CLOCK,
input SW_0,
input SW_1,
input SW_2,
input SW_3,
input PB_ENTER,
input PB_UP,
input RS232_RX_DATA,
output RS232_TX_DATA,
output LED_0,
output LED_1,
output LED_2,
output LED_3
);
wire dcm_locked;
wire clock_100;
wire clock_50;
wire reset;
wire arst;
wire error;
wire rx_error;
wire tx_error;
wire control_error;
wire [15:0] rx_word;
wire rx_word_valid;
wire [15:0] tx_word;
wire tx_word_valid;
wire tx_ack;
wire sim_error;
wire sim_reset;
wire sim_enable;
wire [9:0] sim_time;
wire sim_time_tick;
wire [15:0] config_word;
wire config_valid;
wire [15:0] stats_word;
wire stats_shift;
wire stop_injection;
wire measure;
wire sim_quiescent;
wire [7:0] fdp_error;
wire [7:0] cdp_error;
wire [7:0] part_error;
reg [4:0] r_sync_reset;
always @(posedge clock_50)
begin
r_sync_reset <= {r_sync_reset[3:0], ~PB_ENTER};
end
assign reset = r_sync_reset[4];
IBUF dcm_arst_buf (.O(arst), .I(~PB_UP));
//
// LEDs for debugging
//
reg [3:0] led_out;
assign {LED_3, LED_2, LED_1, LED_0} = ~led_out;
always @(*)
begin
case ({SW_3, SW_2, SW_1, SW_0})
4'h0: led_out = {reset, dcm_locked, rx_error, tx_error};
4'h1: led_out = {sim_reset, sim_error, ~RS232_RX_DATA, ~RS232_TX_DATA};
4'h2: led_out = {stop_injection, measure, sim_enable, sim_quiescent};
4'h3: led_out = part_error[3:0];
4'h4: led_out = part_error[7:4];
4'h5: led_out = fdp_error[3:0];
4'h6: led_out = fdp_error[7:4];
4'h7: led_out = cdp_error[3:0];
4'h8: led_out = cdp_error[7:4];
4'h9: led_out = {control_error, 3'b000};
default: led_out = 4'b0000;
endcase
end
//
// DCM
//
wire dcm_sys_clk_in;
wire dcm_clk_100;
wire dcm_clk_50;
IBUFG sys_clk_buf (.O(dcm_sys_clk_in), .I(SYSTEM_CLOCK));
BUFG clk_100_buf (.O(clock_100), .I(dcm_clk_100));
BUFG clk_50_buf (.O(clock_50), .I(dcm_clk_50));
DCM #(
.SIM_MODE("SAFE"), // Simulation: "SAFE" vs. "FAST", see "Synthesis and Simulation Design Guide" for details
.CLKDV_DIVIDE(4.0), // Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
// 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
.CLKFX_DIVIDE(1), // Can be any integer from 1 to 32
.CLKFX_MULTIPLY(4), // Can be any integer from 2 to 32
.CLKIN_DIVIDE_BY_2("FALSE"), // TRUE/FALSE to enable CLKIN divide by two feature
.CLKIN_PERIOD(0.0), // Specify period of input clock
.CLKOUT_PHASE_SHIFT("NONE"), // Specify phase shift of NONE, FIXED or VARIABLE
.CLK_FEEDBACK("1X"), // Specify clock feedback of NONE, 1X or 2X
.DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), // SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
// an integer from 0 to 15
.DFS_FREQUENCY_MODE("LOW"), // HIGH or LOW frequency mode for frequency synthesis
.DLL_FREQUENCY_MODE("LOW"), // HIGH or LOW frequency mode for DLL
.DUTY_CYCLE_CORRECTION("TRUE"), // Duty cycle correction, TRUE or FALSE
.FACTORY_JF(16'hC080), // FACTORY JF values
.PHASE_SHIFT(0), // Amount of fixed phase shift from -255 to 255
.STARTUP_WAIT("FALSE") // Delay configuration DONE until DCM LOCK, TRUE/FALSE
) DCM_inst (
.CLK0(dcm_clk_100), // 0 degree DCM CLK output
.CLK180(), // 180 degree DCM CLK output
.CLK270(), // 270 degree DCM CLK output
.CLK2X(), // 2X DCM CLK output
.CLK2X180(), // 2X, 180 degree DCM CLK out
.CLK90(), // 90 degree DCM CLK output
.CLKDV(dcm_clk_50), // Divided DCM CLK out (CLKDV_DIVIDE)
.CLKFX(), // DCM CLK synthesis out (M/D)
.CLKFX180(), // 180 degree CLK synthesis out
.LOCKED(dcm_locked), // DCM LOCK status output
.PSDONE(), // Dynamic phase adjust done output
.STATUS(), // 8-bit DCM status bits output
.CLKFB(clock_100), // DCM clock feedback
.CLKIN(dcm_sys_clk_in), // Clock input (from IBUFG, BUFG or DCM)
.PSCLK(1'b0), // Dynamic phase adjust clock input
.PSEN(1'b0), // Dynamic phase adjust enable input
.PSINCDEC(0), // Dynamic phase adjust increment/decrement
.RST(arst) // DCM asynchronous reset input
);
//
// DART UART port (user data width = 16)
//
dartport #(.WIDTH(16), .BAUD_RATE(9600)) dartio (
.clock (clock_50),
.reset (reset),
.enable (dcm_locked),
.rx_error (rx_error),
.tx_error (tx_error),
.RS232_RX_DATA (RS232_RX_DATA),
.RS232_TX_DATA (RS232_TX_DATA),
.rx_data (rx_word),
.rx_valid (rx_word_valid),
.tx_data (tx_word),
.tx_valid (tx_word_valid),
.tx_ack (tx_ack));
//
// Control Unit
//
Control controller (
.clock (clock_50),
.reset (reset),
.enable (dcm_locked),
.control_error (control_error),
.rx_word (rx_word),
.rx_word_valid (rx_word_valid),
.tx_word (tx_word),
.tx_word_valid (tx_word_valid),
.tx_ack (tx_ack),
.sim_reset (sim_reset),
.sim_enable (sim_enable),
.sim_error (sim_error),
.stop_injection (stop_injection),
.measure (measure),
.sim_time (sim_time),
.sim_time_tick (sim_time_tick),
.sim_quiescent (sim_quiescent),
.config_word (config_word),
.config_valid (config_valid),
.stats_shift (stats_shift),
.stats_word (stats_word));
//
// Simulator
//
sim9_8x8 dart_sim (
.clock (clock_50),
.reset (sim_reset),
.enable (sim_enable),
.stop_injection (stop_injection),
.measure (measure),
.sim_time (sim_time),
.sim_time_tick (sim_time_tick),
.error (sim_error),
.fdp_error (fdp_error),
.cdp_error (cdp_error),
.part_error (part_error),
.quiescent (sim_quiescent),
.config_in (config_word),
.config_in_valid (config_valid),
.config_out (),
.config_out_valid (),
.stats_out (stats_word),
.stats_shift (stats_shift));
endmodule
|
`timescale 1ns / 1ps
/* gen_dequeue.v
* Generate the dequeue signal for double-pumped BRAM output queues
*
* Basically make dequeue happen at the 2nd half (neg half) of the clock cycle
*/
module gen_dequeue (
clock_2x,
reset,
dequeue_in,
dequeue_out
);
parameter N = 1;
input clock_2x;
input reset;
input [N-1:0] dequeue_in;
output [N-1:0] dequeue_out;
reg dequeue_cycle;
always @(posedge clock_2x or posedge reset)
begin
if (reset)
dequeue_cycle = 1'b0;
else
dequeue_cycle = ~dequeue_cycle;
end
assign dequeue_out = {(N){dequeue_cycle}} & dequeue_in;
endmodule
|
`timescale 1ns / 1ps
/* TGBernoulli.v
* Bernoulli traffic injection engine
* Injections a packet when 1) rand_wire < threshold
* 2) current time >= lag time
* Spits out a flit every clock cycle if there is a flit
* to inject and this unit is enabled
*/
`include "const.v"
module TGBernoulli(
clock,
reset,
enable,
sim_time,
measure, // Approximation: global inject measurement flag
psize,
sendto,
obuf_full, // Output buffer is full
rand_below_threshold,
flit_out,
ready,
tick_rng
);
parameter HADDR = 1; // Hardware node address
parameter PSIZE_WIDTH = 10;
input clock;
input reset;
input enable;
input [`TS_WIDTH-1:0] sim_time;
input measure;
input [PSIZE_WIDTH-1:0] psize;
input [`ADDR_WIDTH-1:0] sendto;
input obuf_full;
input rand_below_threshold;
output [`FLIT_WIDTH-1:0] flit_out;
output ready;
output tick_rng;
// Internal states
reg [`TS_WIDTH-1: 0] lag_ts; // Current timestamp of the lagging injection process
reg [PSIZE_WIDTH-1: 0] flits_injected;
// Wires
wire [ 9: 0] w_src_or_injection;
wire w_not_lagging;
wire w_complete_pkt;
wire w_try_inject_flit;
wire w_inject;
wire w_inject_head;
wire w_inject_normal;
wire w_inject_tail;
wire w_inject_flit;
wire w_tick_rng;
wire w_inc_lag_ts;
wire w_clear_flits_injected;
wire [PSIZE_WIDTH-1:0] w_flits_injected;
// Output
assign flit_out = {w_inject_head, w_inject_tail, measure, lag_ts, sendto, w_src_or_injection, 5'h0};
assign ready = w_inject_flit;
assign tick_rng = w_tick_rng;
assign w_src_or_injection = (w_inject_head) ? HADDR : lag_ts;
// Lagging Injection Process
is_less_than #(.N(`TS_WIDTH)) u0 (.a(sim_time), .b(lag_ts), .a_lt_b(w_not_lagging));
is_less_than #(.N(PSIZE_WIDTH)) u1 (.a(psize), .b(flits_injected), .a_lt_b(w_complete_pkt));
assign w_try_inject_flit = ~w_not_lagging & ~w_complete_pkt & measure;
assign w_inject = w_try_inject_flit & (~obuf_full);
assign w_tick_rng = (flits_injected == 0) ? w_inject : 1'b0;
assign w_inject_head = w_tick_rng & rand_below_threshold;
assign w_inject_normal = (flits_injected != 0) ? w_inject : 1'b0;
assign w_inject_tail = (flits_injected == psize) ? w_inject : 1'b0;
assign w_inject_flit = w_inject_head | w_inject_normal;
assign w_inc_lag_ts = (w_tick_rng & ~rand_below_threshold) | w_inject_tail;
assign w_clear_flits_injected = w_inject_tail;
`ifdef SIMULATION
always @(*)
begin
if (w_try_inject_flit & obuf_full)
$display ("TG (%u) can't inject. lag_ts 0x%h flits_injected 0x%h", HADDR, lag_ts, flits_injected);
end
`endif
assign w_flits_injected = flits_injected + w_inject_flit;
// Update states
always @(posedge clock or posedge reset)
begin
if (reset)
begin
lag_ts <= {(`TS_WIDTH){1'b0}};
flits_injected <= {(PSIZE_WIDTH){1'b0}};
end
else if (enable)
begin
if (w_inc_lag_ts)
lag_ts <= lag_ts + 1;
if (w_clear_flits_injected)
flits_injected <= 0;
else
flits_injected <= w_flits_injected;
end
end
endmodule
|
`timescale 1ns / 1ps
/* Top level module with sim-to-PC control interface and DCM
*/
`include "const.v"
module top(
clock_in,
reset,
sim_time,
error,
quiescent,
config_in,
config_in_valid,
config_out,
config_out_valid,
stats_out,
stats_shift
);
input clock_in;
input reset;
output [`TS_WIDTH-1:0] sim_time;
output error;
output quiescent;
input [15:0] config_in;
input config_in_valid;
output [15:0] config_out;
output config_out_valid;
output [15:0] stats_out;
input stats_shift;
wire clock;
wire dcm_locked;
// DCM: Digital Clock Manager Circuit
// Virtex-II/II-Pro and Spartan-3
// Xilinx HDL Language Template, version 10.1.3
DCM #(
.SIM_MODE("SAFE"), // Simulation: "SAFE" vs. "FAST", see "Synthesis and Simulation Design Guide" for details
.CLKDV_DIVIDE(2.0), // Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
// 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
.CLKFX_DIVIDE(1), // Can be any integer from 1 to 32
.CLKFX_MULTIPLY(4), // Can be any integer from 2 to 32
.CLKIN_DIVIDE_BY_2("FALSE"), // TRUE/FALSE to enable CLKIN divide by two feature
.CLKIN_PERIOD(0.0), // Specify period of input clock
.CLKOUT_PHASE_SHIFT("NONE"), // Specify phase shift of NONE, FIXED or VARIABLE
.CLK_FEEDBACK("1X"),// Specify clock feedback of NONE, 1X or 2X
.DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), // SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
// an integer from 0 to 15
.DFS_FREQUENCY_MODE("LOW"), // HIGH or LOW frequency mode for frequency synthesis
.DLL_FREQUENCY_MODE("LOW"), // HIGH or LOW frequency mode for DLL
.DUTY_CYCLE_CORRECTION("TRUE"), // Duty cycle correction, TRUE or FALSE
.FACTORY_JF(16'hC080), // FACTORY JF values
.PHASE_SHIFT(0), // Amount of fixed phase shift from -255 to 255
.STARTUP_WAIT("FALSE") // Delay configuration DONE until DCM LOCK, TRUE/FALSE
) DCM_inst (
.CLK0(clock), // 0 degree DCM CLK output
.CLK180(), // 180 degree DCM CLK output
.CLK270(), // 270 degree DCM CLK output
.CLK2X(), // 2X DCM CLK output
.CLK2X180(), // 2X, 180 degree DCM CLK out
.CLK90(), // 90 degree DCM CLK output
.CLKDV(), // Divided DCM CLK out (CLKDV_DIVIDE)
.CLKFX(), // DCM CLK synthesis out (M/D)
.CLKFX180(), // 180 degree CLK synthesis out
.LOCKED(dcm_locked), // DCM LOCK status output
.PSDONE(), // Dynamic phase adjust done output
.STATUS(), // 8-bit DCM status bits output
.CLKFB(clock), // DCM clock feedback
.CLKIN(clock_in), // Clock input (from IBUFG, BUFG or DCM)
.PSCLK(1'b0), // Dynamic phase adjust clock input
.PSEN(1'b0), // Dynamic phase adjust enable input
.PSINCDEC(0), // Dynamic phase adjust increment/decrement
.RST(reset) // DCM asynchronous reset input
);
sim9 simulator (
.clock (clock),
.reset (reset),
.enable (dcm_locked),
.sim_time_tick (),
.sim_time (sim_time),
.error (error),
.quiescent (quiescent),
.config_in (config_in),
.config_in_valid (config_in_valid),
.config_out (config_out),
.config_out_valid (config_out_valid),
.stats_out (stats_out),
.stats_shift (stats_shift));
endmodule
|
`timescale 1 ns/100 ps // time unit = 1ns; precision = 1/10 ns
/* Static arbiter. Grant to the first request starting from the
* least-significant bit
*/
module arbiter_static #(
parameter SIZE = 10
)
(
input [SIZE-1:0] requests,
output [SIZE-1:0] grants,
output grant_valid
);
// This module only supports SIZE = 1, 2, 4, 8
// psl ERROR_unsupported_arbiter_size: assert always {(SIZE > 0 && SIZE <= 10) || SIZE == 16};
reg [SIZE:0] grant_temp;
assign {grant_valid, grants} = grant_temp;
generate
if (SIZE == 1)
begin
always @(*)
begin
grant_temp = {requests, requests};
end
end
else if (SIZE == 2)
begin
always @(*)
begin
if (requests[0]) grant_temp = 3'b101;
else if (requests[1]) grant_temp = 3'b110;
else grant_temp = 3'b000;
end
end
else if (SIZE == 3)
begin
always @(*)
begin
if (requests[0]) grant_temp = 4'b1001;
else if (requests[1]) grant_temp = 4'b1010;
else if (requests[2]) grant_temp = 4'b1100;
else grant_temp = 4'b0000;
end
end
else if (SIZE == 4)
begin
always @(*)
begin
if (requests[0]) grant_temp = 5'b10001;
else if (requests[1]) grant_temp = 5'b10010;
else if (requests[2]) grant_temp = 5'b10100;
else if (requests[3]) grant_temp = 5'b11000;
else grant_temp = 5'b00000;
end
end
else if (SIZE == 5)
begin
always @(*)
begin
if (requests[0]) grant_temp = 6'b10_0001;
else if (requests[1]) grant_temp = 6'b10_0010;
else if (requests[2]) grant_temp = 6'b10_0100;
else if (requests[3]) grant_temp = 6'b10_1000;
else if (requests[4]) grant_temp = 6'b11_0000;
else grant_temp = 6'b00_0000;
end
end
else if (SIZE == 6)
begin
always @(*)
begin
if (requests[0]) grant_temp = 7'b100_0001;
else if (requests[1]) grant_temp = 7'b100_0010;
else if (requests[2]) grant_temp = 7'b100_0100;
else if (requests[3]) grant_temp = 7'b100_1000;
else if (requests[4]) grant_temp = 7'b101_0000;
else if (requests[5]) grant_temp = 7'b110_0000;
else grant_temp = 7'b000_0000;
end
end
else if (SIZE == 7)
begin
always @(*)
begin
if (requests[0]) grant_temp = 8'b1000_0001;
else if (requests[1]) grant_temp = 8'b1000_0010;
else if (requests[2]) grant_temp = 8'b1000_0100;
else if (requests[3]) grant_temp = 8'b1000_1000;
else if (requests[4]) grant_temp = 8'b1001_0000;
else if (requests[5]) grant_temp = 8'b1010_0000;
else if (requests[6]) grant_temp = 8'b1100_0000;
else grant_temp = 8'b0000_0000;
end
end
else if (SIZE == 8)
begin
always @(*)
begin
if (requests[0]) grant_temp = 9'b10000_0001;
else if (requests[1]) grant_temp = 9'b10000_0010;
else if (requests[2]) grant_temp = 9'b10000_0100;
else if (requests[3]) grant_temp = 9'b10000_1000;
else if (requests[4]) grant_temp = 9'b10001_0000;
else if (requests[5]) grant_temp = 9'b10010_0000;
else if (requests[6]) grant_temp = 9'b10100_0000;
else if (requests[7]) grant_temp = 9'b11000_0000;
else grant_temp = 9'b00000_0000;
end
end
else if (SIZE == 9)
begin
always @(*)
begin
if (requests[0]) grant_temp = 10'b10_0000_0001;
else if (requests[1]) grant_temp = 10'b10_0000_0010;
else if (requests[2]) grant_temp = 10'b10_0000_0100;
else if (requests[3]) grant_temp = 10'b10_0000_1000;
else if (requests[4]) grant_temp = 10'b10_0001_0000;
else if (requests[5]) grant_temp = 10'b10_0010_0000;
else if (requests[6]) grant_temp = 10'b10_0100_0000;
else if (requests[7]) grant_temp = 10'b10_1000_0000;
else if (requests[8]) grant_temp = 10'b11_0000_0000;
else grant_temp = 10'b00_0000_0000;
end
end
else if (SIZE == 10)
begin
always @(*)
begin
if (requests[0]) grant_temp = 11'b100_0000_0001;
else if (requests[1]) grant_temp = 11'b100_0000_0010;
else if (requests[2]) grant_temp = 11'b100_0000_0100;
else if (requests[3]) grant_temp = 11'b100_0000_1000;
else if (requests[4]) grant_temp = 11'b100_0001_0000;
else if (requests[5]) grant_temp = 11'b100_0010_0000;
else if (requests[6]) grant_temp = 11'b100_0100_0000;
else if (requests[7]) grant_temp = 11'b100_1000_0000;
else if (requests[8]) grant_temp = 11'b101_0000_0000;
else if (requests[9]) grant_temp = 11'b110_0000_0000;
else grant_temp = 11'b000_0000_0000;
end
end
else if (SIZE == 16)
begin
always @(*)
begin
if (requests[0]) grant_temp = 17'h10001;
else if (requests[1]) grant_temp = 17'h10002;
else if (requests[2]) grant_temp = 17'h10004;
else if (requests[3]) grant_temp = 17'h10008;
else if (requests[4]) grant_temp = 17'h10010;
else if (requests[5]) grant_temp = 17'h10020;
else if (requests[6]) grant_temp = 17'h10040;
else if (requests[7]) grant_temp = 17'h10080;
else if (requests[8]) grant_temp = 17'h10100;
else if (requests[9]) grant_temp = 17'h10200;
else if (requests[10]) grant_temp = 17'h10400;
else if (requests[11]) grant_temp = 17'h10800;
else if (requests[12]) grant_temp = 17'h11000;
else if (requests[13]) grant_temp = 17'h12000;
else if (requests[14]) grant_temp = 17'h14000;
else if (requests[15]) grant_temp = 17'h18000;
else grant_temp = 17'h00000;
end
end
endgenerate
endmodule
|
`timescale 1ns / 1ps
/* Baud rate generator (9600)
* Assume 50 MHz clock input
*/
module baud_gen #(
parameter BAUD_RATE = 9600
)
(
input clock,
input reset,
input start,
output reg baud_tick
);
`include "math.v"
localparam WIDTH = 16;
reg [WIDTH-1: 0] counter_r;
wire [WIDTH-1:0] max;
// Counter values are selected for each baud rate
generate
if (BAUD_RATE == 9600) // 9600
begin
reg [1:0] toggle;
assign max = (toggle == 0) ? 16'd5209 : 16'd5208;
always @(posedge clock)
begin
if (reset)
toggle <= 0;
else if (baud_tick)
if (toggle == 2)
toggle <= 0;
else
toggle <= toggle + 1;
end
end
else if (BAUD_RATE == 115200) // 115200
begin
reg [6:0] toggle;
assign max = (toggle == 0) ? 16'd435 : 16'd434;
always @(posedge clock)
begin
if (reset)
toggle <= 0;
else if (baud_tick)
if (toggle == 35)
toggle <= 0;
else
toggle <= toggle + 1;
end
end
else if (BAUD_RATE == 0) // Simulation
begin
assign max = 16'h4;
end
endgenerate
// Baud tick counter
always @(posedge clock)
begin
if (reset)
begin
counter_r <= {(WIDTH){1'b0}};
baud_tick <= 1'b0;
end
else
begin
if (counter_r == max)
begin
baud_tick <= 1'b1;
counter_r <= {(WIDTH){1'b0}};
end
else
begin
baud_tick <= 1'b0;
if (start)
counter_r <= {1'b0, max[WIDTH-1:1]}; // Reset counter to half the max value
else
counter_r <= counter_r + {{(WIDTH-1){1'b0}}, 1'b1};
end
end
end
endmodule
|
`timescale 1 ns/100 ps // time unit = 1ns; precision = 1/10 ns
/* Check Destination
* check_dest.v
*
* Given a set of input nexthop and enable bits, generate a vector
* that indicate if each incoming packet is for a node in this
* partition.
*
* Node addresses follow the convention below:
* addr2 = {partition ID (4), node ID (4), port ID (3)}
*/
`include "const.v"
module check_dest (
src_nexthop_in,
valid
);
parameter N = 8; // Number of incoming packets
parameter PID = 4'h0; // Partition number
input [N*`A_WIDTH-1:0] src_nexthop_in;
output [N-1:0] valid;
genvar i;
generate
for (i = 0; i < N; i = i + 1)
begin : in
wire [`A_WIDTH-1:0] nexthop;
assign nexthop = src_nexthop_in[(i+1)*`A_WIDTH-1:i*`A_WIDTH];
assign valid[i] = (nexthop[`A_DPID] == PID) ? 1'b1 : 1'b0;
end
endgenerate
endmodule
|
/* const.v
* This file contains all the global defines used by all
* Verilog modules.
*/
`define FLIT_WIDTH 36
`define CREDIT_WIDTH 11
`define TS_WIDTH 10
`define ADDR_WIDTH 8
`define VC_WIDTH 1
`define BW_WIDTH 8
`define LAT_WIDTH 8
`define ADDR_DPID 7:5 // DestPart ID
`define ADDR_NPID 4:0 // Node and port ID
`define F_HEAD 35 // Head flit
`define F_TAIL 34 // Tail flit
`define F_MEASURE 33 // Measurement flit
`define F_FLAGS 35:33
`define F_TS 32:23
`define F_DEST 22:15 // Does not include port ID
`define F_SRC_INJ 14:5
`define F_OPORT 4:2
`define F_OVC 1:0
`define A_WIDTH 11
`define A_DPID 10:7
`define A_NID 6:3 // 4-bit local node ID
`define A_PORTID 2:0
`define A_FQID 6:0 // 4-bit local node ID + 3-bit port ID
`define A_DNID 10:3 // 8-bit global node ID
// Packet descriptor
`define P_SRC 7:0 // 8-bit address
`define P_DEST 15:8
`define P_SIZE 18:16 // 3-bit packet size
`define P_VC 20:19 // 2-bit VC ID
`define P_INJ 30:21 // 10-bit timestamp
`define P_MEASURE 31
`define P_SIZE_WIDTH 4
|
`timescale 1ns / 1ps
/* Control Unit
*/
module Control (
input clock,
input reset,
input enable,
output control_error,
// To UART interface
input [15:0] rx_word,
input rx_word_valid,
output reg [15:0] tx_word,
output reg tx_word_valid,
input tx_ack,
// To simulator interface
output sim_reset,
output sim_enable,
input sim_error,
output stop_injection,
output measure,
input [9:0] sim_time,
input sim_time_tick,
input sim_quiescent,
output reg [15:0] config_word,
output reg config_valid,
output reg stats_shift,
input [15:0] stats_word
);
// Control bits
`define C_OFFSET 15:12
localparam [3:0] O_RESET = 0,
O_COMMON = 1,
O_TIMER_VALUE = 2,
O_TIMER_VALUE_HI = 3,
O_CONFIG_ENABLE = 4,
O_DATA_REQUEST = 5,
O_STATES_REQUEST = 6;
localparam C_SIM_ENABLE = 0,
C_MEASURE = 1,
C_STOP_INJECTION = 2,
C_TIMER_ENABLE = 3,
C_NUM_BITS = 4;
localparam DECODE = 0,
RESET_SIM = 1,
LOAD_CONFIG_LENGTH = 2,
CONFIG = 3,
LOAD_DATA_LENGTH = 4,
BLOCK_SEND_STATES = 5;
localparam TX_IDLE = 0,
TX_SHIFT_DATA = 1,
TX_SEND_STATE = 2,
TX_SEND_STATE_2 = 3,
TX_SEND_STATE_3 = 4,
TX_SEND_STATE_4 = 5;
// Internal states
reg [C_NUM_BITS-1:0] r_control;
reg r_sim_reset;
reg [2:0] r_state;
reg [2:0] r_tx_state;
reg [3:0] r_counter; // Reset counter
reg [23:0] r_timer_counter;
reg [15:0] r_config_counter;
reg [15:0] r_data_counter;
// Wires
reg [2:0] next_state;
reg next_sim_reset;
reg [C_NUM_BITS-1:0] next_control;
reg [2:0] next_tx_state;
reg [15:0] next_config_word;
reg next_config_valid;
reg reset_counter;
reg shift_timer_counter;
reg load_config_counter;
reg load_data_counter;
reg start_send_state;
// Output
assign control_error = 1'b0;
assign sim_reset = r_sim_reset;
assign sim_enable = (r_tx_state == TX_IDLE) ? r_control[C_SIM_ENABLE] : 1'b0;
assign stop_injection = r_control[C_STOP_INJECTION];
assign measure = r_control[C_MEASURE];
//
// Control FSM
//
always @(posedge clock)
begin
if (reset)
begin
r_state <= DECODE;
r_sim_reset <= 1'b0;
r_control <= 0;
config_word <= 0;
config_valid <= 0;
end
else if (enable)
begin
r_state <= next_state;
r_sim_reset <= next_sim_reset;
r_control <= next_control;
config_word <= next_config_word;
config_valid <= next_config_valid;
end
end
always @(*)
begin
next_state = r_state;
next_sim_reset = r_sim_reset;
next_control = r_control;
reset_counter = 1'b0;
shift_timer_counter = 1'b0;
load_config_counter = 1'b0;
load_data_counter = 1'b0;
start_send_state = 1'b0;
next_config_word = 0;
next_config_valid = 1'b0;
case (r_state)
DECODE:
begin
if (rx_word_valid)
begin
case (rx_word[`C_OFFSET])
O_RESET:
begin
next_sim_reset = 1'b1;
next_state = RESET_SIM;
reset_counter = 1'b1;
end
O_COMMON: // Load the command bits
begin
next_control = rx_word[C_NUM_BITS-1:0];
end
O_TIMER_VALUE: // Timer value is encoded in this command
begin
shift_timer_counter = 1'b1;
end
O_TIMER_VALUE_HI:
begin
shift_timer_counter = 1'b1;
end
O_CONFIG_ENABLE: // Counter value is in the next command
begin
next_state = LOAD_CONFIG_LENGTH;
end
O_DATA_REQUEST: // Counter value is in the next command
begin
next_state = LOAD_DATA_LENGTH;
end
O_STATES_REQUEST:
begin
if (r_control[C_TIMER_ENABLE] & rx_word[0])
begin // When timer-enable is set, block and send states after sim stops
next_state = BLOCK_SEND_STATES;
end
else // Non-blocking
start_send_state = 1'b1;
end
endcase
end
end
RESET_SIM: // Hold reset for 16 cycles
begin
if (r_counter == 0)
begin
next_sim_reset = 1'b0;
next_state = DECODE;
end
end
LOAD_CONFIG_LENGTH: // Load the # of config words to receive (N <= 64K)
begin
if (rx_word_valid)
begin
load_config_counter = 1'b1;
next_state = CONFIG;
end
end
CONFIG: // Receive words and send to config_word port
begin
if (rx_word_valid)
begin
next_config_valid = 1'b1;
next_config_word = rx_word;
if (r_config_counter == 1)
next_state = DECODE;
end
end
LOAD_DATA_LENGTH: // Load the # of data words to send back (N <= 64K)
begin
if (rx_word_valid)
begin
load_data_counter = 1'b1;
next_state = DECODE;
end
end
BLOCK_SEND_STATES: // Wait until sim_enable is low and initiate send states
begin
if (~r_control[C_SIM_ENABLE])
begin
start_send_state = 1'b1;
next_state = DECODE;
end
end
endcase
// Timer controlled simulation
if (r_control[C_TIMER_ENABLE] == 1'b1 && r_timer_counter == 0)
next_control[C_SIM_ENABLE] = 1'b0;
end
// Reset counter
always @(posedge clock)
begin
if (reset)
r_counter <= 4'hF;
else if (enable)
begin
if (reset_counter)
r_counter <= 4'hF;
else if (r_state == RESET_SIM)
r_counter <= r_counter - 1;
end
/* // This causes non-deterministic behaviours
if (reset_counter)
r_counter <= 4'hF;
else if (enable)
r_counter <= r_counter - 1;*/
end
// Timer counter
always @(posedge clock)
begin
if (reset)
r_timer_counter <= 0;
else if (enable)
begin
if (shift_timer_counter)
r_timer_counter <= {rx_word[11:0], r_timer_counter[23:12]}; // load low 12 bits first
else if (r_control[C_TIMER_ENABLE] & sim_time_tick)
r_timer_counter <= r_timer_counter - 1;
end
end
// Config word counter
always @(posedge clock)
begin
if (reset)
r_config_counter <= 0;
else if (enable)
begin
if (load_config_counter)
r_config_counter <= rx_word;
else if (rx_word_valid)
r_config_counter <= r_config_counter - 1;
end
end
// Data counter
always @(posedge clock)
begin
if (reset)
r_data_counter <= 0;
else if (enable)
begin
if (load_data_counter)
r_data_counter <= rx_word;
else if (tx_ack)
r_data_counter <= r_data_counter - 1;
end
end
//
// TX State Machine
//
always @(posedge clock)
begin
if (reset)
r_tx_state <= TX_IDLE;
else if (enable)
r_tx_state <= next_tx_state;
end
always @(*)
begin
next_tx_state = r_tx_state;
stats_shift = 1'b0;
tx_word = 0;
tx_word_valid = 1'b0;
case (r_tx_state)
TX_IDLE:
begin
if (load_data_counter) // Start sending data words
next_tx_state = TX_SHIFT_DATA;
else if (start_send_state)
next_tx_state = TX_SEND_STATE;
end
TX_SHIFT_DATA:
begin
tx_word = stats_word;
tx_word_valid = 1'b1;
if (tx_ack)
begin
stats_shift = 1'b1;
if (r_data_counter == 1)
next_tx_state = TX_IDLE;
end
end
TX_SEND_STATE:
begin
tx_word = {control_error, sim_error, r_control, sim_quiescent, r_state, r_tx_state, 3'h0};
tx_word_valid = 1'b1;
if (tx_ack)
next_tx_state = TX_SEND_STATE_2;
end
TX_SEND_STATE_2:
begin
tx_word = {6'h00, sim_time};
tx_word_valid = 1'b1;
if (tx_ack)
next_tx_state = TX_SEND_STATE_3;
end
TX_SEND_STATE_3:
begin
tx_word = r_timer_counter[15:0];
tx_word_valid = 1'b1;
if (tx_ack)
next_tx_state = TX_SEND_STATE_4;
end
TX_SEND_STATE_4:
begin
tx_word = {8'h00, r_timer_counter[23:16]};
tx_word_valid = 1'b1;
if (tx_ack)
next_tx_state = TX_IDLE;
end
endcase
end
endmodule
|
`timescale 1ns / 1ps
/* CreditCounter
* CreditCounter.v
*
* A single credit counter
*
* Config path:
* config_in -> r_count -> config_out
*/
module CreditCounter(
clock,
reset,
enable,
sim_time_tick,
config_in,
config_in_valid,
config_out,
config_out_valid,
credit_in_valid,
credit_ack,
decrement,
count_out
);
parameter WIDTH = 4; // Width of credit counter
// Global ports
input clock;
input reset;
input enable;
input sim_time_tick;
// Configuration ports
input [WIDTH-1: 0] config_in;
input config_in_valid;
output [WIDTH-1: 0] config_out;
output config_out_valid;
// Credit ports
input credit_in_valid;
output credit_ack;
input decrement;
output [WIDTH-1: 0] count_out;
reg [WIDTH-1:0] r_count;
reg [WIDTH-1:0] w_count;
// Output
assign count_out = r_count;
assign config_out = r_count;
assign config_out_valid = config_in_valid;
assign credit_ack = enable & credit_in_valid;
always @(posedge clock)
begin
if (reset)
r_count <= 0;
else if (config_in_valid)
r_count <= config_in;
else if (enable)
r_count <= w_count;
end
always @(*)
begin
if (credit_in_valid & ~decrement)
w_count = r_count + 1;
else if (~credit_in_valid & decrement)
w_count = r_count - 1;
else
w_count = r_count;
end
endmodule
|
`timescale 1ns / 1ps
/* Top level module that communicates with the PC
*/
module dart (
input SYSTEM_CLOCK,
input SW_0,
input SW_1,
input SW_2,
input SW_3,
input PB_ENTER,
input PB_UP,
input RS232_RX_DATA,
output RS232_TX_DATA,
output LED_0,
output LED_1,
output LED_2,
output LED_3
);
wire dcm_locked;
wire clock_100;
wire clock_50;
wire reset;
wire arst;
wire error;
wire rx_error;
wire tx_error;
wire control_error;
wire [15:0] rx_word;
wire rx_word_valid;
wire [15:0] tx_word;
wire tx_word_valid;
wire tx_ack;
wire sim_error;
wire sim_reset;
wire sim_enable;
wire [9:0] sim_time;
wire sim_time_tick;
wire [15:0] config_word;
wire config_valid;
wire [15:0] stats_word;
wire stats_shift;
wire stop_injection;
wire measure;
wire sim_quiescent;
wire [7:0] fdp_error;
wire [7:0] cdp_error;
wire [7:0] part_error;
reg [4:0] r_sync_reset;
always @(posedge clock_50)
begin
r_sync_reset <= {r_sync_reset[3:0], ~PB_ENTER};
end
assign reset = r_sync_reset[4];
//IBUF dcm_arst_buf (.O(arst), .I(~PB_UP));
assign arst = ~PB_UP;
//
// LEDs for debugging
//
reg [3:0] led_out;
assign {LED_3, LED_2, LED_1, LED_0} = ~led_out;
always @(*)
begin
case ({SW_3, SW_2, SW_1, SW_0})
4'h0: led_out = {reset, dcm_locked, rx_error, tx_error};
4'h1: led_out = {sim_reset, sim_error, ~RS232_RX_DATA, ~RS232_TX_DATA};
4'h2: led_out = {stop_injection, measure, sim_enable, sim_quiescent};
4'h3: led_out = part_error[3:0];
4'h4: led_out = part_error[7:4];
4'h5: led_out = fdp_error[3:0];
4'h6: led_out = fdp_error[7:4];
4'h7: led_out = cdp_error[3:0];
4'h8: led_out = cdp_error[7:4];
4'h9: led_out = {control_error, 3'b000};
default: led_out = 4'b0000;
endcase
end
//
// DCM
//
wire dcm_sys_clk_in;
wire dcm_clk_100;
wire dcm_clk_50;
/*)IBUFG sys_clk_buf (.O(dcm_sys_clk_in), .I(SYSTEM_CLOCK));
BUFG clk_100_buf (.O(clock_100), .I(dcm_clk_100));
BUFG clk_50_buf (.O(clock_50), .I(dcm_clk_50));*/
assign dcm_sys_clk_in = SYSTEM_CLOCK;
assign clock_100 = dcm_clk_100;
assign clock_50 = dcm_clk_50;
/*DCM #(
.SIM_MODE("SAFE"), // Simulation: "SAFE" vs. "FAST", see "Synthesis and Simulation Design Guide" for details
.CLKDV_DIVIDE(4.0), // Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
// 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
.CLKFX_DIVIDE(1), // Can be any integer from 1 to 32
.CLKFX_MULTIPLY(4), // Can be any integer from 2 to 32
.CLKIN_DIVIDE_BY_2("FALSE"), // TRUE/FALSE to enable CLKIN divide by two feature
.CLKIN_PERIOD(0.0), // Specify period of input clock
.CLKOUT_PHASE_SHIFT("NONE"), // Specify phase shift of NONE, FIXED or VARIABLE
.CLK_FEEDBACK("1X"), // Specify clock feedback of NONE, 1X or 2X
.DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), // SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
// an integer from 0 to 15
.DFS_FREQUENCY_MODE("LOW"), // HIGH or LOW frequency mode for frequency synthesis
.DLL_FREQUENCY_MODE("LOW"), // HIGH or LOW frequency mode for DLL
.DUTY_CYCLE_CORRECTION("TRUE"), // Duty cycle correction, TRUE or FALSE
.FACTORY_JF(16'hC080), // FACTORY JF values
.PHASE_SHIFT(0), // Amount of fixed phase shift from -255 to 255
.STARTUP_WAIT("FALSE") // Delay configuration DONE until DCM LOCK, TRUE/FALSE
) DCM_inst (
.CLK0(dcm_clk_100), // 0 degree DCM CLK output
.CLK180(), // 180 degree DCM CLK output
.CLK270(), // 270 degree DCM CLK output
.CLK2X(), // 2X DCM CLK output
.CLK2X180(), // 2X, 180 degree DCM CLK out
.CLK90(), // 90 degree DCM CLK output
.CLKDV(dcm_clk_50), // Divided DCM CLK out (CLKDV_DIVIDE)
.CLKFX(), // DCM CLK synthesis out (M/D)
.CLKFX180(), // 180 degree CLK synthesis out
.LOCKED(dcm_locked), // DCM LOCK status output
.PSDONE(), // Dynamic phase adjust done output
.STATUS(), // 8-bit DCM status bits output
.CLKFB(clock_100), // DCM clock feedback
.CLKIN(dcm_sys_clk_in), // Clock input (from IBUFG, BUFG or DCM)
.PSCLK(1'b0), // Dynamic phase adjust clock input
.PSEN(1'b0), // Dynamic phase adjust enable input
.PSINCDEC(0), // Dynamic phase adjust increment/decrement
.RST(arst) // DCM asynchronous reset input
);*/
pll_clocks pll_clocks_inst (
.areset ( arst ),
.inclk0 ( dcm_sys_clk_in ),
.c0 ( dcm_clk_100 ),
.c1 ( dcm_clk_50 ),
.locked ( dcm_locked )
);
//
// DART UART port (user data width = 16)
//
dartport #(.WIDTH(16), .BAUD_RATE(9600)) dartio (
.clock (clock_50),
.reset (reset),
.enable (dcm_locked),
.rx_error (rx_error),
.tx_error (tx_error),
.RS232_RX_DATA (RS232_RX_DATA),
.RS232_TX_DATA (RS232_TX_DATA),
.rx_data (rx_word),
.rx_valid (rx_word_valid),
.tx_data (tx_word),
.tx_valid (tx_word_valid),
.tx_ack (tx_ack));
//
// Control Unit
//
Control controller (
.clock (clock_50),
.reset (reset),
.enable (dcm_locked),
.control_error (control_error),
.rx_word (rx_word),
.rx_word_valid (rx_word_valid),
.tx_word (tx_word),
.tx_word_valid (tx_word_valid),
.tx_ack (tx_ack),
.sim_reset (sim_reset),
.sim_enable (sim_enable),
.sim_error (sim_error),
.stop_injection (stop_injection),
.measure (measure),
.sim_time (sim_time),
.sim_time_tick (sim_time_tick),
.sim_quiescent (sim_quiescent),
.config_word (config_word),
.config_valid (config_valid),
.stats_shift (stats_shift),
.stats_word (stats_word));
//
// Simulator
//
//sim9_8x8 dart_sim (
sim32_8x8 dart_sim (
.clock (clock_50),
//.clock_2x (clock_100),
.reset (sim_reset),
.enable (sim_enable),
.stop_injection (stop_injection),
.measure (measure),
.sim_time (sim_time),
.sim_time_tick (sim_time_tick),
.error (sim_error),
//.fdp_error (fdp_error),
//.cdp_error (cdp_error),
//.part_error (part_error),
.quiescent (sim_quiescent),
.config_in (config_word),
.config_in_valid (config_valid),
.config_out (),
.config_out_valid (),
.stats_out (stats_word),
.stats_shift (stats_shift));
endmodule
|
`timescale 1ns / 1ps
/* Top level module that communicates with the PC
*/
module dart32_8x8 (
input SYSTEM_CLOCK,
input SW_0,
input SW_1,
input SW_2,
input SW_3,
input PB_ENTER,
input RS232_RX_DATA,
output RS232_TX_DATA,
output LED_0,
output LED_1,
output LED_2,
output LED_3
);
wire dcm_locked;
wire clock_100;
wire clock_50;
wire reset;
wire error;
wire rx_error;
wire tx_error;
wire control_error;
wire [15:0] rx_word;
wire rx_word_valid;
wire [15:0] tx_word;
wire tx_word_valid;
wire tx_ack;
wire sim_error;
wire sim_reset;
wire sim_enable;
wire [9:0] sim_time;
wire sim_time_tick;
wire [15:0] config_word;
wire config_valid;
wire [15:0] stats_word;
wire stats_shift;
wire stop_injection;
wire measure;
wire sim_quiescent;
assign reset = SW_3;
//
// LEDs for debugging
//
reg [3:0] led_out;
assign {LED_3, LED_2, LED_1, LED_0} = ~led_out;
always @(*)
begin
case ({SW_1, SW_0})
2'b00: led_out = {reset, rx_error, tx_error, control_error};
2'b01: led_out = {sim_reset, sim_error, ~RS232_RX_DATA, ~RS232_TX_DATA};
2'b10: led_out = {stop_injection, measure, sim_enable, SW_2};
2'b11: led_out = stats_word[3:0];
default: led_out = 4'b0000;
endcase
end
//
// DCM
//
DCM #(
.SIM_MODE("SAFE"), // Simulation: "SAFE" vs. "FAST", see "Synthesis and Simulation Design Guide" for details
.CLKDV_DIVIDE(2.0), // Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
// 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
.CLKFX_DIVIDE(1), // Can be any integer from 1 to 32
.CLKFX_MULTIPLY(4), // Can be any integer from 2 to 32
.CLKIN_DIVIDE_BY_2("FALSE"), // TRUE/FALSE to enable CLKIN divide by two feature
.CLKIN_PERIOD(0.0), // Specify period of input clock
.CLKOUT_PHASE_SHIFT("NONE"), // Specify phase shift of NONE, FIXED or VARIABLE
.CLK_FEEDBACK("1X"), // Specify clock feedback of NONE, 1X or 2X
.DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), // SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
// an integer from 0 to 15
.DFS_FREQUENCY_MODE("LOW"), // HIGH or LOW frequency mode for frequency synthesis
.DLL_FREQUENCY_MODE("LOW"), // HIGH or LOW frequency mode for DLL
.DUTY_CYCLE_CORRECTION("TRUE"), // Duty cycle correction, TRUE or FALSE
.FACTORY_JF(16'hC080), // FACTORY JF values
.PHASE_SHIFT(0), // Amount of fixed phase shift from -255 to 255
.STARTUP_WAIT("FALSE") // Delay configuration DONE until DCM LOCK, TRUE/FALSE
) DCM_inst (
.CLK0(clock_100), // 0 degree DCM CLK output
.CLK180(), // 180 degree DCM CLK output
.CLK270(), // 270 degree DCM CLK output
.CLK2X(), // 2X DCM CLK output
.CLK2X180(), // 2X, 180 degree DCM CLK out
.CLK90(), // 90 degree DCM CLK output
.CLKDV(clock_50), // Divided DCM CLK out (CLKDV_DIVIDE)
.CLKFX(), // DCM CLK synthesis out (M/D)
.CLKFX180(), // 180 degree CLK synthesis out
.LOCKED(dcm_locked), // DCM LOCK status output
.PSDONE(), // Dynamic phase adjust done output
.STATUS(), // 8-bit DCM status bits output
.CLKFB(clock_100), // DCM clock feedback
.CLKIN(SYSTEM_CLOCK), // Clock input (from IBUFG, BUFG or DCM)
.PSCLK(1'b0), // Dynamic phase adjust clock input
.PSEN(1'b0), // Dynamic phase adjust enable input
.PSINCDEC(0), // Dynamic phase adjust increment/decrement
.RST(reset) // DCM asynchronous reset input
);
//
// DART UART port (user data width = 16)
//
dartport #(.WIDTH(16), .BAUD_RATE(9600)) dartio (
.clock (clock_50),
.reset (reset),
.enable (dcm_locked),
.rx_error (rx_error),
.tx_error (tx_error),
.RS232_RX_DATA (RS232_RX_DATA),
.RS232_TX_DATA (RS232_TX_DATA),
.rx_data (rx_word),
.rx_valid (rx_word_valid),
.tx_data (tx_word),
.tx_valid (tx_word_valid),
.tx_ack (tx_ack));
//
// Control Unit
//
Control controller (
.clock (clock_50),
.reset (reset),
.enable (dcm_locked),
.control_error (control_error),
.rx_word (rx_word),
.rx_word_valid (rx_word_valid),
.tx_word (tx_word),
.tx_word_valid (tx_word_valid),
.tx_ack (tx_ack),
.sim_reset (sim_reset),
.sim_enable (sim_enable),
.sim_error (sim_error),
.stop_injection (stop_injection),
.measure (measure),
.sim_time (sim_time),
.sim_time_tick (sim_time_tick),
.sim_quiescent (sim_quiescent),
.config_word (config_word),
.config_valid (config_valid),
.stats_shift (stats_shift),
.stats_word (stats_word));
//
// Simulator
//
sim32_8x8 dart_sim (
.clock (clock_50),
.reset (sim_reset),
.enable (sim_enable),
.stop_injection (stop_injection),
.measure (measure),
.sim_time (sim_time),
.sim_time_tick (sim_time_tick),
.error (sim_error),
.quiescent (sim_quiescent),
.config_in (config_word),
.config_in_valid (config_valid),
.config_out (),
.config_out_valid (),
.stats_out (stats_word),
.stats_shift (stats_shift));
endmodule
|
`timescale 1ns / 1ps
/* DART UART ports
*/
module dartport #(
parameter WIDTH = 16,
BAUD_RATE = 9600
)
(
input clock,
input reset,
input enable,
output rx_error,
output tx_error,
input RS232_RX_DATA,
output RS232_TX_DATA,
output [WIDTH-1:0] rx_data,
output rx_valid,
input [WIDTH-1:0] tx_data,
input tx_valid,
output tx_ack
);
localparam N = (WIDTH+7)>>3; // The number of 8-bit words required
localparam IDLE = 0, TRANSMITTING = 1;
wire [7:0] rx_word;
wire rx_word_valid;
wire [7:0] tx_to_fifo_word;
wire tx_to_fifo_valid;
wire tx_serializer_busy;
wire [7:0] tx_word;
wire tx_fifo_empty;
wire tx_fifo_full;
wire tx_start;
wire tx_ready;
reg tx_state;
// RX Side
// Receive data from UART (8-bit) and deserialize into WIDTH words
// Ready words must be consumed immediately
myuart_rx #(.BAUD_RATE(BAUD_RATE)) rx_module (
.clock (clock),
.reset (reset),
.enable (enable),
.error (rx_error),
.rx_data_in (RS232_RX_DATA),
.data_out (rx_word),
.data_out_valid (rx_word_valid));
deserializer #(.WIDTH(8), .N(N)) rx_deserializer (
.clock(clock),
.reset(reset),
.data_in(rx_word),
.data_in_valid(rx_word_valid & enable),
.data_out(rx_data),
.data_out_valid(rx_valid));
// TX Side
// Receive data from user. The user should not send a new word to the TX
// module until an ack is received.
// User data is serialized into 8-bit words before sending out through
// the UART's TX module
assign tx_ack = tx_valid & ~tx_fifo_full & ~tx_serializer_busy;
assign tx_start = (tx_state == IDLE) ? (~tx_fifo_empty & tx_ready) : 1'b0;
serializer #(.WIDTH(8), .N(N)) tx_serializer (
.clock (clock),
.reset (reset),
.data_in (tx_data),
.data_in_valid (tx_valid & enable),
.data_out (tx_to_fifo_word),
.data_out_valid (tx_to_fifo_valid),
.busy (tx_serializer_busy));
// TX FIFO
fifo_8bit tx_buffer (
.clk (clock),
.rst (reset),
.din (tx_to_fifo_word),
.wr_en (tx_to_fifo_valid & enable),
.dout (tx_word),
.rd_en (tx_start & enable),
.empty (tx_fifo_empty),
.full (tx_fifo_full));
myuart_tx #(.BAUD_RATE(BAUD_RATE)) tx_module (
.clock (clock),
.reset (reset),
.enable (enable),
.error (tx_error),
.data_in (tx_word),
.tx_start (tx_start),
.tx_data_out (RS232_TX_DATA),
.tx_ready (tx_ready));
// State machine that coordinates between tx_buffer and tx_module
always @(posedge clock)
begin
if (reset)
begin
tx_state <= IDLE;
end
else if (enable)
begin
case (tx_state)
IDLE:
begin
if (~tx_fifo_empty & tx_ready)
tx_state <= TRANSMITTING;
end
TRANSMITTING:
begin
if (tx_ready)
tx_state <= IDLE;
end
endcase
end
end
endmodule
|
`timescale 1ns / 1ps
/* decoder_N.v
* General N-bit decoder (one-hot)
*/
module decoder_N(
encoded,
decoded
);
`include "math.v"
parameter SIZE = 8;
input [CLogB2(SIZE-1)-1: 0] encoded;
output [SIZE-1: 0] decoded;
reg [SIZE-1: 0] decoded;
genvar i;
generate
for (i = 0; i < SIZE; i = i + 1)
begin : decode
always @(*)
begin
if (i == encoded)
decoded[i] = 1'b1;
else
decoded[i] = 1'b0;
end
end
endgenerate
endmodule
|
`timescale 1 ns/100 ps // time unit = 1ns; precision = 1/10 ns
/* Distributed RAM
* DistroRAM.v
*
* Implement a small dual-port RAM using distributed RAM
*/
module DistroRAM (
clock,
wen,
waddr,
raddr,
din,
wdout,
rdout
);
parameter WIDTH = 8;
parameter LOG_DEP = 3;
localparam DEPTH = 1 << LOG_DEP;
input clock;
input wen;
input [LOG_DEP-1: 0] waddr;
input [LOG_DEP-1: 0] raddr;
input [WIDTH-1: 0] din;
output [WIDTH-1: 0] wdout;
output [WIDTH-1: 0] rdout;
// Infer distributed RAM
reg [WIDTH-1: 0] ram [DEPTH-1: 0];
//// synthesis attribute RAM_STYLE of ram is distributed
always @(posedge clock)
begin
if (wen)
ram[waddr] <= din;
end
assign wdout = ram[waddr];
assign rdout = ram[raddr];
endmodule
|
`timescale 1ns / 1ps
/* Dual-Port RAM with synchronous read (read through)
*/
module DualBRAM #(
parameter WIDTH = 36,
parameter LOG_DEP = 6
)
(
input clock,
input enable,
input wen,
input [LOG_DEP-1:0] waddr,
input [LOG_DEP-1:0] raddr,
input [WIDTH-1:0] din,
output [WIDTH-1:0] dout,
output [WIDTH-1:0] wdout
);
localparam DEPTH = 1 << LOG_DEP;
// Infer Block RAM
reg [WIDTH-1:0] ram [DEPTH-1:0];
reg [LOG_DEP-1: 0] read_addr;
reg [LOG_DEP-1: 0] write_addr;
//// synthesis attribute RAM_STYLE of ram is block
always @(posedge clock)
begin
if (enable)
begin
if (wen)
ram[waddr] <= din;
read_addr <= raddr;
write_addr <= waddr;
end
end
assign dout = ram[read_addr];
assign wdout = ram[write_addr];
endmodule
|
`timescale 1ns / 1ps
/* encoder_N.v
* General N-bit encoder (input is one-hot)
*/
module encoder_N(
decoded,
encoded,
valid
);
`include "math.v"
parameter SIZE = 8;
localparam LOG_SIZE = CLogB2(SIZE-1);
localparam NPOT = 1 << LOG_SIZE;
input [SIZE-1:0] decoded;
output [LOG_SIZE-1:0] encoded;
output valid;
wire [NPOT-1:0] w_decoded;
assign valid = |decoded;
generate
if (NPOT == SIZE)
assign w_decoded = decoded;
else
assign w_decoded = {{(NPOT-SIZE){1'b0}}, decoded};
endgenerate
// Only a set of input sizes are selected
// psl ERROR_encoder_size: assert always {LOG_SIZE <= 4 && LOG_SIZE != 0};
generate
if (LOG_SIZE == 1)
begin
assign encoded = w_decoded[1];
end
else if (LOG_SIZE == 2)
begin
assign encoded = {w_decoded[2] | w_decoded[3], w_decoded[1] | w_decoded[3]};
end
else if (LOG_SIZE == 3)
begin
// This produces slightly smaller area than the case-statement based implementation
assign encoded = {w_decoded[4] | w_decoded[5] | w_decoded[6] | w_decoded[7],
w_decoded[2] | w_decoded[3] | w_decoded[6] | w_decoded[7],
w_decoded[1] | w_decoded[3] | w_decoded[5] | w_decoded[7]};
end
else if (LOG_SIZE == 4)
begin
reg [LOG_SIZE-1:0] w_encoded;
assign encoded = w_encoded;
always @(*)
begin
case (w_decoded)
16'h0001: w_encoded = 4'h0;
16'h0002: w_encoded = 4'h1;
16'h0004: w_encoded = 4'h2;
16'h0008: w_encoded = 4'h3;
16'h0010: w_encoded = 4'h4;
16'h0020: w_encoded = 4'h5;
16'h0040: w_encoded = 4'h6;
16'h0080: w_encoded = 4'h7;
16'h0100: w_encoded = 4'h8;
16'h0200: w_encoded = 4'h9;
16'h0400: w_encoded = 4'hA;
16'h0800: w_encoded = 4'hB;
16'h1000: w_encoded = 4'hC;
16'h2000: w_encoded = 4'hD;
16'h4000: w_encoded = 4'hE;
16'h8000: w_encoded = 4'hF;
default: w_encoded = 4'bxxxx;
endcase
end
end
endgenerate
endmodule
|
`timescale 1ns / 1ps
/* Flit Queue
* FlitQueue.v
*
* Models a single input unit of a Router
*
* Configuration path
* config_in -> FlitQueue_NC -> config_out
*/
`include "const.v"
module FlitQueue(
clock,
reset,
enable,
sim_time,
error,
is_quiescent,
config_in,
config_in_valid,
config_out,
config_out_valid,
flit_full,
flit_in_valid,
flit_in,
nexthop_in,
flit_ack,
flit_out,
flit_out_valid,
dequeue,
credit_full,
credit_in_valid,
credit_in,
credit_in_nexthop,
credit_ack,
credit_out,
credit_out_valid,
credit_dequeue
);
`include "util.v"
parameter [`A_WIDTH-1:0] HADDR = 1; // 8-bit global node ID + 3-bit port ID
parameter LOG_NVCS = 1;
// parameter NPID = 1;
localparam NVCS = 1 << LOG_NVCS;
input clock;
input reset;
input enable;
input [`TS_WIDTH-1:0] sim_time;
output error;
output is_quiescent;
// Config interface
input [15: 0] config_in;
input config_in_valid;
output [15: 0] config_out;
output config_out_valid;
// Flit interface (1 in, NVCS out)
output [NVCS-1: 0] flit_full;
input flit_in_valid;
input [`FLIT_WIDTH-1:0] flit_in;
input [`A_FQID] nexthop_in;
output flit_ack;
output [NVCS*`FLIT_WIDTH-1:0] flit_out; // One out interface per VC
output [NVCS-1: 0] flit_out_valid;
input [NVCS-1: 0] dequeue;
// Credit interface (1 in, 1 out)
output credit_full;
input credit_in_valid;
input [`CREDIT_WIDTH-1: 0] credit_in;
input [`A_FQID] credit_in_nexthop;
output credit_ack;
output [`CREDIT_WIDTH-1: 0] credit_out; // Two output interfaces for the two VCs
output credit_out_valid;
input credit_dequeue;
// Wires
wire w_flit_error;
wire [`LAT_WIDTH-1:0] w_latency;
wire [NVCS-1: 0] w_flit_full;
wire w_flit_is_quiescent;
wire [NVCS-1: 0] w_flit_dequeue;
wire [`TS_WIDTH-1:0] w_credit_in_ts;
wire [`TS_WIDTH-1:0] w_credit_new_ts;
wire [`TS_WIDTH-1:0] w_credit_out_ts;
wire [`CREDIT_WIDTH-1:0] w_credit_to_enqueue;
wire [`CREDIT_WIDTH-1:0] w_credit_out;
wire w_credit_enqueue;
wire w_credit_full;
wire w_credit_empty;
wire w_credit_error;
wire w_credit_has_data;
// Output
assign error = w_credit_error | w_flit_error;
assign is_quiescent = w_flit_is_quiescent & w_credit_empty;
assign flit_full = w_flit_full;
assign credit_full = w_credit_full;
assign credit_out = w_credit_out;
assign credit_ack = w_credit_enqueue;
// For now only supports 2 VCs (1 LSB in nexthop)
// psl ERROR_unsupported_NVCS: assert always {NVCS == 2};
// Simulation stuff
`ifdef SIMULATION
always @(posedge clock)
begin
if (credit_dequeue)
$display ("T %x FQ (%x) sends credit %x port 0", sim_time, HADDR, credit_out);
end
`endif
// Flit Queue
FlitQueue_NC #(.HADDR(HADDR), .LOG_NVCS(LOG_NVCS)) fq (
.clock (clock),
.reset (reset),
.enable (enable),
.sim_time (sim_time),
.error (w_flit_error),
.is_quiescent (w_flit_is_quiescent),
.latency (w_latency),
.config_in (config_in),
.config_in_valid (config_in_valid),
.config_out (config_out),
.config_out_valid (config_out_valid),
.flit_full (w_flit_full),
.flit_in_valid (flit_in_valid),
.flit_in (flit_in),
.nexthop_in (nexthop_in),
.flit_ack (flit_ack),
.flit_out (flit_out),
.flit_out_valid (flit_out_valid),
.dequeue (w_flit_dequeue));
// Credit FIFO (32 deep)
assign w_credit_in_ts = credit_ts (credit_in);
assign w_credit_to_enqueue = update_credit_ts (credit_in, w_credit_new_ts);
assign w_credit_enqueue = (credit_in_nexthop == HADDR[`A_FQID]) ? (enable & credit_in_valid & ~w_credit_full) : 1'b0;
assign w_credit_error = (credit_in_valid & w_credit_full) | (credit_dequeue & w_credit_empty);
assign w_credit_new_ts = w_credit_in_ts + w_latency;
//srl_fifo #(.WIDTH(`CREDIT_WIDTH), .LOG_LEN(5)) cq (
RAMFIFO_single_slow #(.WIDTH(`CREDIT_WIDTH), .LOG_DEP(5)) cq (
.clock (clock),
.reset (reset),
.enable (enable),
.data_in (w_credit_to_enqueue),
.data_out (w_credit_out),
.write (w_credit_enqueue),
.read (credit_dequeue),
.full (w_credit_full),
.empty (w_credit_empty),
.has_data (w_credit_has_data));
// Credit out interface
assign w_credit_out_ts = credit_ts (w_credit_out);
flit_out_inf cout_inf (
.clock (clock),
.reset (reset),
.dequeue (credit_dequeue),
.flit_valid (w_credit_has_data),
.flit_timestamp (w_credit_out_ts),
.sim_time (sim_time),
.ready (credit_out_valid));
// Generate dequeue signals
assign w_flit_dequeue = dequeue;
endmodule
|
`timescale 1ns / 1ps
/* Flit Queue
* FlitQueue.v
*
* Models a single 2-VC FlitQueue without credit channels
*
* Configuration path
* config_in -> FQCtrl -> config_out
*/
`include "const.v"
module FlitQueue_NC (
clock,
reset,
enable,
sim_time,
error,
is_quiescent,
latency, // For FQ to have access to the latency
config_in,
config_in_valid,
config_out,
config_out_valid,
flit_full,
flit_in_valid,
flit_in,
nexthop_in,
flit_ack,
flit_out,
flit_out_valid,
dequeue
);
`include "util.v"
parameter [`A_WIDTH-1:0] HADDR = 1; // 8-bit global node ID + 3-bit port ID
parameter LOG_NVCS = 1;
// parameter NPID = 1;
localparam NVCS = 1 << LOG_NVCS;
input clock;
input reset;
input enable;
input [`TS_WIDTH-1:0] sim_time;
output error;
output is_quiescent;
output [`LAT_WIDTH-1:0] latency;
// Config interface
input [15: 0] config_in;
input config_in_valid;
output [15: 0] config_out;
output config_out_valid;
// Flit interface (1 in, NVCS out)
output [NVCS-1: 0] flit_full;
input flit_in_valid;
input [`FLIT_WIDTH-1:0] flit_in;
input [`A_FQID] nexthop_in;
output flit_ack;
output [NVCS*`FLIT_WIDTH-1:0] flit_out; // One out interface per VC
output [NVCS-1: 0] flit_out_valid;
input [NVCS-1: 0] dequeue;
// Wires
wire [`LAT_WIDTH-1:0] w_latency;
wire w_flit_in_valid;
wire [`TS_WIDTH-1:0] w_flit_in_ts;
wire [`TS_WIDTH-1:0] w_flit_new_ts;
wire w_flit_in_vc;
wire [`FLIT_WIDTH-1:0] w_flit_to_enqueue;
wire [NVCS*`FLIT_WIDTH-1:0] w_flit_out;
wire w_flit_enqueue;
wire w_flit_dequeue;
wire [NVCS-1: 0] w_flit_full;
wire [NVCS-1: 0] w_flit_empty;
wire w_flit_error;
wire [NVCS-1: 0] w_flit_has_data;
wire w_ram_read;
wire w_ram_write;
genvar i;
// Output
assign error = w_flit_error;
assign is_quiescent = &w_flit_empty;
assign latency = w_latency;
assign flit_full = w_flit_full;
assign flit_ack = w_ram_write;
assign flit_out = w_flit_out;
assign w_ram_read = enable & w_flit_dequeue;
assign w_ram_write = enable & w_flit_enqueue;
// Simulation stuff
`ifdef SIMULATION
always @(posedge clock)
begin
if (w_ram_write)
$display ("T %x FQ (%x) recvs flit %x", sim_time, HADDR, flit_in);
end
generate
for (i = 0; i < NVCS; i = i + 1)
begin : sim_display
always @(posedge clock)
begin
if (dequeue[i])
$display ("T %x FQ (%x) sends flit %x (VC %d)", sim_time, HADDR, flit_out[(i+1)*`FLIT_WIDTH-1:i*`FLIT_WIDTH], flit_out[i*`FLIT_WIDTH]);
end
end
endgenerate
`endif
// FQ control unit (1 per context)
assign w_flit_in_valid = (nexthop_in == HADDR[`A_FQID]) ? (enable & flit_in_valid) : 1'b0;
assign w_flit_in_ts = flit_in[`F_TS];
FQCtrl ctrl (
.clock (clock),
.reset (reset),
.in_ready (w_flit_in_valid),
.in_timestamp (w_flit_in_ts),
.out_timestamp (w_flit_new_ts),
.config_in (config_in),
.config_in_valid (config_in_valid),
.config_out (config_out),
.config_out_valid (config_out_valid),
.bandwidth (),
.latency (w_latency));
// Flit FIFO (64 deep)
assign w_flit_in_vc = flit_vc (flit_in);
assign w_flit_to_enqueue = update_flit_ts (flit_in, w_flit_new_ts);
generate
if (LOG_NVCS == 0)
begin
assign w_flit_enqueue = w_flit_in_valid & ~w_flit_full;
assign w_flit_dequeue = dequeue;
assign w_flit_error = 1'b0;
RAMFIFO_single_slow #(.WIDTH(`FLIT_WIDTH), .LOG_DEP(6)) fq (
.clock (clock),
.reset (reset),
.enable (enable),
.data_in (w_flit_to_enqueue),
.data_out (w_flit_out),
.write (w_ram_write),
.read (w_ram_read),
.full (w_flit_full),
.empty (w_flit_empty),
.has_data (w_flit_has_data));
end
else
begin
wire [LOG_NVCS-1: 0] w_flit_dequeue_ccid;
wire w_flit_fifo_full;
assign w_flit_enqueue = w_flit_in_valid & ~w_flit_fifo_full;
mux_Nto1 #(.WIDTH(1), .SIZE(NVCS)) enqueue_mux (
.in (w_flit_full),
.sel (w_flit_in_vc),
.out (w_flit_fifo_full));
//RAMFIFO #(.WIDTH(`FLIT_WIDTH), .LOG_DEP(6), .LOG_CTX(LOG_NVCS)) fq (
RAMFIFO_slow #(.WIDTH(`FLIT_WIDTH), .LOG_DEP(6), .LOG_CTX(LOG_NVCS)) fq (
.clock (clock),
.reset (reset),
.enable (enable),
.rcc_id (w_flit_dequeue_ccid),
.wcc_id (w_flit_in_vc),
.data_in (w_flit_to_enqueue),
.data_out (w_flit_out),
.write (w_ram_write),
.read (w_ram_read),
.full (w_flit_full),
.empty (w_flit_empty),
.has_data (w_flit_has_data),
.error (w_flit_error));
encoder_N #(.SIZE(NVCS)) dequeue_encoder (
.decoded (dequeue),
.encoded (w_flit_dequeue_ccid),
.valid (w_flit_dequeue));
end
endgenerate
// Flit out interface
generate
for (i = 0; i < NVCS; i = i + 1)
begin : fout
wire [`TS_WIDTH-1:0] w_flit_out_ts;
assign w_flit_out_ts = flit_ts (w_flit_out[(i+1)*`FLIT_WIDTH-1:i*`FLIT_WIDTH]);
flit_out_inf inf (
.clock (clock),
.reset (reset),
.dequeue (dequeue[i]),
.flit_valid (w_flit_has_data[i]),
.flit_timestamp (w_flit_out_ts),
.sim_time (sim_time),
.ready (flit_out_valid[i]));
end
endgenerate
endmodule
|
`timescale 1 ns/100 ps // time unit = 1ns; precision = 1/10 ns
`include "const.v"
/* Flit Out Interface
* flit_out_inf.v
*
* Given timestamp of a flit, generate the ready signals.
* Since we only use 4-bit time differences, a flit that arrives at the output
* of the FQ more than 8 steps late will be considered a "future" flit due to
* timestamp overflow. However, this should not happen because incoming flits to
* the FQ should never be late.
* A flit may wait at the output of the FQ for more than 8 steps after its timestamp
* if the downstream Router cannot route this flit. In this case, the r_valid bi-modal
* state machine will keep the ready signal high even when timestamp overflows.
*/
module flit_out_inf (
input clock,
input reset,
input dequeue,
input flit_valid,
input [`TS_WIDTH-1:0] flit_timestamp,
input [`TS_WIDTH-1:0] sim_time,
output ready // ready when flit_timestamp <= sim_time
);
parameter WIDTH = `TS_WIDTH; // Number of bits to use to compute time difference
wire [WIDTH-1: 0] w_timestamp_diff;
wire w_valid;
reg r_valid;
// Ready
assign w_timestamp_diff = sim_time[WIDTH-1:0] - flit_timestamp[WIDTH-1:0];
assign w_valid = ~w_timestamp_diff[WIDTH-1] & flit_valid;
assign ready = w_valid | r_valid;
always @(posedge clock)
begin
if (reset)
r_valid <= 0;
else if (~r_valid)
r_valid <= w_valid & ~dequeue;
else if (dequeue)
r_valid <= 0;
end
endmodule
|
`timescale 1ns / 1ps
/* FQCtrl.v
* Bandwidth control unit for FQ. One per FQ. The path from in_ready to
* out_timestamp completes in 1 cycle.
*
* Config path
* config_in -> {bandwidth, latency} -> config_out
*/
`include "const.v"
module FQCtrl(
clock,
reset,
in_ready,
in_timestamp,
out_timestamp,
config_in,
config_in_valid,
config_out,
config_out_valid,
bandwidth,
latency
);
localparam RESET = 0, COUNT = 1;
input clock;
input reset;
input in_ready;
input [`TS_WIDTH-1:0] in_timestamp;
output [`TS_WIDTH-1:0] out_timestamp;
// Config ports
input config_in_valid;
input [15: 0] config_in;
output config_out_valid;
output [15: 0] config_out;
// Exposing parameters
output [`BW_WIDTH-1:0] bandwidth;
output [`LAT_WIDTH-1:0] latency;
// Internal states
reg [`BW_WIDTH-1:0] bandwidth;
reg [`LAT_WIDTH-1:0] latency;
reg [`BW_WIDTH-1:0] count;
reg [`TS_WIDTH-1:0] last_ts;
// Wires
reg [`BW_WIDTH-1:0] w_count;
reg [`TS_WIDTH-1:0] w_ts_bw_component;
// Output
assign config_out_valid = config_in_valid;
assign config_out = {bandwidth, latency};
assign out_timestamp = w_ts_bw_component + {2'b00, latency};
//
// Configuration logic
//
always @(posedge clock)
begin
if (reset)
{bandwidth, latency} <= {(`BW_WIDTH+`LAT_WIDTH){1'b0}};
else if (config_in_valid)
{bandwidth, latency} <= config_in;
end
//
// FQ Control
//
wire w_in_timestamp_gt_last_ts;
wire [`TS_WIDTH-1:0] w_ts_diff;
assign w_ts_diff = last_ts - in_timestamp;
assign w_in_timestamp_gt_last_ts = w_ts_diff[`TS_WIDTH-1];
always @(*)
begin
w_count = count;
w_ts_bw_component = in_timestamp;
if (in_ready)
begin
if (count == bandwidth || w_in_timestamp_gt_last_ts == 1'b1)
w_count = 1;
else
w_count = count + 1;
// Huge area...
if (w_in_timestamp_gt_last_ts)
w_ts_bw_component = in_timestamp;
else if (count == bandwidth)
w_ts_bw_component = last_ts + 1;
else
w_ts_bw_component = last_ts;
end
end
always @(posedge clock)
begin
if (reset)
begin
last_ts <= 0;
count <= 0;
end
else if (in_ready)
begin
last_ts <= w_ts_bw_component;
count <= w_count;
end
end
endmodule
|
`timescale 1ns / 1ps
/* FQCtrlFSM.v
* Bandwidth control unit for FQ. One per FQ. The path from in_ready to
* out_timestamp completes in 1 cycle.
*
* Config path
* config_in -> {bandwidth, latency} -> config_out
*/
//TODO: Not finished. Use FQCtrl.v instead.
`include "const.v"
module FQCtrlFSM(
clock,
reset,
sim_time,
sim_time_tick,
in_ready,
in_timestamp,
out_timestamp,
config_in,
config_in_valid,
config_out,
config_out_valid
);
localparam RESET = 0, COUNT = 1;
input clock;
input reset;
input [`TS_WIDTH-1:0] sim_time;
input sim_time_tick;
input in_ready;
input [`TS_WIDTH-1:0] in_timestamp;
output [`TS_WIDTH-1:0] out_timestamp;
// Config ports
input config_in_valid;
input [15: 0] config_in;
output config_out_valid;
output [15: 0] config_out;
// Internal states
reg [`BW_WIDTH-1:0] bandwidth;
reg [ 7: 0] latency;
reg [`BW_WIDTH-1:0] count;
reg [`TS_WIDTH-1:0] last_ts;
reg [`TS_WIDTH-1:0] reset_when;
reg state;
reg next_state;
// Wires
reg [ 1: 0] w_count_sel;
reg [`TS_WIDTH-1:0] w_ts_bw_component;
wire in_ts_is_newer;
// Output
assign config_out_valid = config_in_valid;
assign config_out = {bandwidth, latency};
assign out_timestamp = w_ts_bw_component + latency;
// Wires
assign in_ts_is_newer = (in_timestamp > last_ts) ? 1'b1 : 1'b0;
//
// Configuration logic
//
always @(posedge clock or posedge reset)
begin
if (reset)
{bandwidth, latency} <= {(`BW_WIDTH+8){1'b0}};
else if (config_in_valid)
{bandwidth, latency} <= config_in;
end
//
// FSM
//
always @(posedge clock or posedge reset)
begin
if (reset)
state <= 2'b00;
else
state <= next_state;
end
// FSM state transition
always @(*)
begin
next_state = state;
w_count_sel = 2; // Keep old count value
case (state)
RESET:
begin
if (in_ready)
begin
next_state = COUNT;
w_count_sel = 1; // Set count to 1
end
end
COUNT:
begin
if (in_ready)
begin
if (count == bandwidth || in_ts_is_newer == 1'b1)
w_count_sel = 1; // Set count to 1
else
w_count_sel = 3; // Increment count
end
/*else if (sim_time_tick == 1'b1 && reset_when == sim_time)
begin
next_state = RESET;
w_count_sel = 0; // Set count to 0
end*/
end
endcase
end
always @(posedge clock or posedge reset)
begin
if (reset)
begin
count <= {(`BW_WIDTH){1'b0}};
last_ts <= {(`TS_WIDTH){1'b0}};
reset_when <= {(`TS_WIDTH){1'b0}};
end
else
begin
if (w_count_sel[1] == 1'b0)
count <= {{(`BW_WIDTH-1){1'b0}}, w_count_sel[0]};
else
count <= count + {{(`BW_WIDTH-1){1'b0}}, w_count_sel[0]};
last_ts <= w_ts_bw_component;
if (w_count_sel == 0) // Reset counter
reset_when <= reset_when + 1;
else
reset_when <= out_timestamp;
end
end
always @(*)
begin
if (w_count_sel == 2'b1)
w_ts_bw_component = in_timestamp;
else
w_ts_bw_component = last_ts + 1;
end
endmodule
|
`timescale 1ns / 1ps
/* FQCtrl_test.v
* Wrapper module to test the critical path of FQCtrl
*/
`include "const.v"
module FQCtrl_wrapper(
clock,
reset,
in_ready,
in_timestamp,
config_in,
config_in_valid,
out
);
input clock;
input reset;
input in_ready;
input [`TS_WIDTH-1:0] in_timestamp;
output [15:0] out;
// Config ports
input config_in_valid;
input [15: 0] config_in;
reg r_in_ready;
reg [`TS_WIDTH-1:0] r_in_timestamp;
reg [15: 0] r_config_in;
reg r_config_in_valid;
reg [`TS_WIDTH-1:0] r_out_timestamp;
reg [15: 0] r_config_out;
reg r_config_out_valid;
wire [`TS_WIDTH-1:0] w_out_timestamp;
wire [15: 0] w_config_out;
wire w_config_out_valid;
assign out = (r_config_out_valid) ? r_config_out : r_out_timestamp;
always @(posedge clock or posedge reset)
begin
if (reset)
begin
r_in_ready <= 0;
r_in_timestamp <= 0;
r_config_in <= 0;
r_config_in_valid <= 0;
r_out_timestamp <= 0;
r_config_out <= 0;
r_config_out_valid <= 0;
end
else
begin
r_in_ready <= in_ready;
r_in_timestamp <= in_timestamp;
r_config_in <= config_in;
r_config_in_valid <= config_in_valid;
r_out_timestamp <= w_out_timestamp;
r_config_out <= w_config_out;
r_config_out_valid <= w_config_out_valid;
end
end
FQCtrl ut (
.clock (clock),
.reset (reset),
.in_ready (r_in_ready),
.in_timestamp (r_in_timestamp),
.out_timestamp (w_out_timestamp),
.config_in (r_config_in),
.config_in_valid (r_config_in_valid),
.config_out (w_config_out),
.config_out_valid (w_config_out_valid));
endmodule
|
`timescale 1 ns/100 ps // time unit = 1ns; precision = 1/10 ns
/* Interconnect Destination Side Partition
* ICDestPart.v
*/
`include "const.v"
module ICDestPart #(
parameter PID = 3'b000, // Partition ID
parameter NSP = 8, // Number of source partitions
parameter WIDTH = `FLIT_WIDTH // Data width
)
(
// Global interface
input clock,
input reset,
input enable,
output error,
// Stage 1 interface
input [NSP-1:0] src_s1_valid, // Stage 1 ready signals from all partitions
input [NSP-1:0] src_s1_valid_urgent, // Stage 1 urgent ready signals
input [NSP*`A_WIDTH-1:0] src_s1_nexthop_in, // Stage 1 nexthops
output [NSP-1:0] src_s1_part_sel, // Decoded source partition select
// Stage 2 input
input [NSP*WIDTH-1:0] src_s2_data_in, // Stage 2 data values
input [NSP*`A_WIDTH-1:0] src_s2_nexthop_in, // Stage 2 nexthop values
// Destination side interface
input dequeue, // Ack from node
output [WIDTH-1:0] s3_data_out, // Stage 3 data
output [`A_FQID] s3_nexthop_out, // Stage 3 nexthop (Node ID and port ID only)
output s3_data_valid
);
`include "math.v"
localparam PIPE_WIDTH = WIDTH + 7; // Data + (local node ID (4) + port ID (3))
// Internal stages
reg [CLogB2(NSP-1)-1:0] r_sel;
reg r_sel_valid; // A valid data was selected
reg [PIPE_WIDTH-1: 0] r_dest_bus_out;
reg r_dest_bus_valid;
reg r_error;
// Wires
wire [NSP-1:0] w_s1_dest_check;
wire [NSP-1:0] w_s1_valid;
wire [NSP-1:0] w_s1_valid_urgent;
wire [NSP-1:0] w_s1_sel;
wire w_s1_sel_valid;
wire [CLogB2(NSP-1)-1:0] w_s1_sel_encoded;
wire [NSP*PIPE_WIDTH-1:0] w_s2_mux_in;
wire [PIPE_WIDTH-1:0] w_s2_mux_out;
// Output
assign error = r_error;
assign src_s1_part_sel = (enable) ? w_s1_sel : {(NSP){1'b0}};
assign {s3_data_out, s3_nexthop_out} = r_dest_bus_out;
assign s3_data_valid = r_dest_bus_valid;
// Reorder input signals to connect to the MUX
genvar i;
generate
for (i = 0; i < NSP; i = i + 1)
begin : src_s2
wire [WIDTH-1:0] data;
wire [`A_WIDTH-1:0] nexthop; // 4-bit local node ID + 3-bit port ID
assign data = src_s2_data_in[(i+1)*WIDTH-1:i*WIDTH];
assign nexthop = src_s2_nexthop_in[(i+1)*`A_WIDTH-1:i*`A_WIDTH];
assign w_s2_mux_in[(i+1)*PIPE_WIDTH-1:i*PIPE_WIDTH] = {data, nexthop[`A_FQID]};
end
endgenerate
// Figure out which of the incoming datas are for this destination
check_dest #(.N(NSP), .PID(PID)) cd (
.src_nexthop_in (src_s1_nexthop_in),
.valid (w_s1_dest_check));
assign w_s1_valid = src_s1_valid & w_s1_dest_check;
assign w_s1_valid_urgent = src_s1_valid_urgent & w_s1_dest_check;
// Select a ready source part (pick an urgent one if applicable) among the 8
select_ready #(.N(NSP)) arb_src (
.ready (w_s1_valid),
.ready_urgent (w_s1_valid_urgent),
.sel (w_s1_sel),
.sel_valid (w_s1_sel_valid),
.sel_valid_urgent ());
encoder_N #(.SIZE(NSP)) src_sel_encode (
.decoded (w_s1_sel),
.encoded (w_s1_sel_encoded),
.valid ());
// Destination MUX (this is part of stage 2)
mux_Nto1 #(.WIDTH(PIPE_WIDTH), .SIZE(NSP)) dest_mux (
.in (w_s2_mux_in),
.sel (r_sel),
.out (w_s2_mux_out));
// Pipeline registers
always @(posedge clock)
begin
if (reset)
begin
r_sel <= 3'b000;
r_sel_valid <= 1'b0;
end
else if (enable)
begin
r_sel <= w_s1_sel_encoded;
r_sel_valid <= w_s1_sel_valid;
end
end
// Stage 2 FIFO registers (note this "FIFO" will never have more than 1 element)
always @(posedge clock)
begin
if (reset)
begin
r_dest_bus_valid <= 1'b0;
r_dest_bus_out <= {(72){1'b0}};
end
else if (enable)
begin
r_dest_bus_valid <= r_sel_valid;
r_dest_bus_out <= w_s2_mux_out;
end
end
// Errors
always @(posedge clock)
begin
if (reset)
begin
r_error <= 1'b0;
end
else if (r_dest_bus_valid & (~dequeue) & enable)
begin
r_error <= 1'b1; // Last data was valid, but not acknowledged
end
end
endmodule
|
`timescale 1 ns/100 ps // time unit = 1ns; precision = 1/10 ns
/* Interconnect Source Partition
* ICSourcePart.v
*
* Connects Routers to FQ/TGs. Does not stall the simulator.
*/
`include "const.v"
module ICSourcePart #(
parameter N = 2, // Number of nodes connected to this partition
parameter WIDTH = `FLIT_WIDTH
)
(
// Global interface
input clock,
input reset,
input enable,
// Partition control
input select, // This source partition is selected for stage 2
output can_increment,
// Source node interface
input [N-1:0] src_data_valid,
input [N-1:0] src_data_valid_urgent,
input [N*WIDTH-1:0] src_data_in,
input [N*`ADDR_WIDTH-1:0] src_nexthop_in,
output [N-1:0] src_dequeue,
// Stage 1 output
output [`ADDR_WIDTH-1:0] s1_nexthop_out,
output s1_valid,
output s1_valid_urgent,
// Stage 2 output
output [WIDTH-1:0] s2_data_out,
output [`ADDR_WIDTH-1:0] s2_nexthop_out
);
`include "math.v"
// Internal stages
reg [WIDTH-1:0] r_pipe_data;
reg [`ADDR_WIDTH-1:0] r_pipe_nexthop;
// Wires
wire [WIDTH-1:0] w_s1_data;
wire [`ADDR_WIDTH-1:0] w_s1_nexthop;
wire [N-1:0] w_s1_sel;
wire w_s1_valid;
wire w_s1_valid_urgent;
// Output
assign can_increment = ~w_s1_valid_urgent;
assign src_dequeue = (select & w_s1_valid) ? w_s1_sel : {(N){1'b0}};
assign s1_nexthop_out = w_s1_nexthop;
assign s1_valid = w_s1_valid;
assign s1_valid_urgent = w_s1_valid_urgent;
assign s2_data_out = r_pipe_data;
assign s2_nexthop_out = r_pipe_nexthop;
genvar i;
generate
// Only one node is connected to this SourcePart
if (N == 1)
begin
assign w_s1_sel = 1'b1;
assign w_s1_valid = src_data_valid;
assign w_s1_valid_urgent = src_data_valid_urgent;
assign w_s1_data = src_data_in;
assign w_s1_nexthop = src_nexthop_in;
end
// More than one node is connected to this SourcePart
else
begin
wire [N*(WIDTH+`ADDR_WIDTH)-1:0] w_source_mux_in;
// Scramble the input bits to generate the MUX in signals
for (i = 0; i < N; i = i + 1)
begin : in
wire [WIDTH-1: 0] data;
wire [`ADDR_WIDTH-1: 0] nexthop;
assign data = src_data_in[(i+1)*WIDTH-1:i*WIDTH];
assign nexthop = src_nexthop_in[(i+1)*`ADDR_WIDTH-1:i*`ADDR_WIDTH];
assign w_source_mux_in[(i+1)*(WIDTH+`ADDR_WIDTH)-1:i*(WIDTH+`ADDR_WIDTH)] = {data, nexthop};
end
// Source partition arbiter
select_ready #(.N(N)) arb_input (
.ready (src_data_valid),
.ready_urgent (src_data_valid_urgent),
.sel (w_s1_sel),
.sel_valid (w_s1_valid),
.sel_valid_urgent (w_s1_valid_urgent));
// Source partition MUX
mux_Nto1_decoded #(.WIDTH(WIDTH + `ADDR_WIDTH), .SIZE(N)) source_mux (
.in(w_source_mux_in),
.sel (w_s1_sel),
.out ({w_s1_data, w_s1_nexthop}));
end
endgenerate
// Pipeline registers for this partition
always @(posedge clock)
begin
if (reset)
begin
r_pipe_data <= {(WIDTH){1'b0}};
r_pipe_nexthop <= {(`ADDR_WIDTH){1'b0}};
end
else if (enable)
begin
r_pipe_data <= w_s1_data;
r_pipe_nexthop <= w_s1_nexthop;
end
end
endmodule
|
`timescale 1ns/100 ps // time unit = 1ns; precision = 1/10 ns
/* Router
* Router.v
*
* Single N-port Router. NPORTS x NVCS input ports, 1 output port
*
* Configuration path:
* config_in -> CreditCounter_0 -> ... -> CreditCounter_N (N = nports * nvc) -> config_out
* ram_config_in -> Input RouterPortLookup -> Output RouterPortLookup -> ram_config_out
*/
`include "const.v"
module InputVCState #(
parameter VC_WIDTH = 1,
NINPUTS = 10
)
(
input clock,
input reset,
input [VC_WIDTH-1:0] allocated_vc,
input allocate_enable,
input [NINPUTS-1:0] ivc_sel,
output [VC_WIDTH-1:0] assigned_vc
);
`include "math.v"
localparam LOG_NINPUTS = CLogB2(NINPUTS-1);
// Assigned output VC for each input VC
reg [VC_WIDTH*NINPUTS-1:0] assigned_ovc;
genvar i;
generate
for (i = 0; i < NINPUTS; i = i + 1)
begin : ivc
always @(posedge clock)
begin
if (reset)
begin
assigned_ovc[(i+1)*VC_WIDTH-1:i*VC_WIDTH] <= 0;
end
else if (allocate_enable & ivc_sel[i])
begin
assigned_ovc[(i+1)*VC_WIDTH-1:i*VC_WIDTH] <= allocated_vc;
end
end
end
endgenerate
// Select the output VC
mux_Nto1_decoded #(.WIDTH(VC_WIDTH), .SIZE(NINPUTS)) vc_mux (
.in (assigned_ovc),
.sel (ivc_sel),
.out (assigned_vc));
endmodule
|
`timescale 1ns / 1ps
module is_greater_than (
a,
b,
a_gt_b
);
parameter N = 32;
input [N-1:0] a;
input [N-1:0] b;
output a_gt_b;
wire [N-1:0] diff;
assign diff = b - a;
assign a_gt_b = diff[N-1];
endmodule
|
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