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// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// megafunction wizard: %ALTECC%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altecc_decoder
// ============================================================
// File Name: alt_mem_ddrx_ecc_decoder_32.v
// Megafunction Name(s):
// altecc_decoder
//
// Simulation Library Files(s):
// lpm
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 10.0 Internal Build 257 07/26/2010 SP 1 PN Full Version
// ************************************************************
//Copyright (C) 1991-2010 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
//altecc_decoder device_family="Stratix III" lpm_pipeline=0 width_codeword=39 width_dataword=32 data err_corrected err_detected err_fatal q
//VERSION_BEGIN 10.0SP1 cbx_altecc_decoder 2010:07:26:21:21:15:PN cbx_cycloneii 2010:07:26:21:21:15:PN cbx_lpm_add_sub 2010:07:26:21:21:15:PN cbx_lpm_compare 2010:07:26:21:21:15:PN cbx_lpm_decode 2010:07:26:21:21:15:PN cbx_mgl 2010:07:26:21:25:47:PN cbx_stratix 2010:07:26:21:21:16:PN cbx_stratixii 2010:07:26:21:21:16:PN VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
//lpm_decode DEVICE_FAMILY="Stratix III" LPM_DECODES=64 LPM_WIDTH=6 data eq
//VERSION_BEGIN 10.0SP1 cbx_cycloneii 2010:07:26:21:21:15:PN cbx_lpm_add_sub 2010:07:26:21:21:15:PN cbx_lpm_compare 2010:07:26:21:21:15:PN cbx_lpm_decode 2010:07:26:21:21:15:PN cbx_mgl 2010:07:26:21:25:47:PN cbx_stratix 2010:07:26:21:21:16:PN cbx_stratixii 2010:07:26:21:21:16:PN VERSION_END
//synthesis_resources = lut 72
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module alt_mem_ddrx_ecc_decoder_32_decode
(
data,
eq) /* synthesis synthesis_clearbox=1 */;
input [5:0] data;
output [63:0] eq;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 [5:0] data;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [5:0] data_wire;
wire [63:0] eq_node;
wire [63:0] eq_wire;
wire [3:0] w_anode1000w;
wire [3:0] w_anode1010w;
wire [3:0] w_anode1020w;
wire [3:0] w_anode1030w;
wire [3:0] w_anode1041w;
wire [3:0] w_anode1053w;
wire [3:0] w_anode1064w;
wire [3:0] w_anode1074w;
wire [3:0] w_anode1084w;
wire [3:0] w_anode1094w;
wire [3:0] w_anode1104w;
wire [3:0] w_anode1114w;
wire [3:0] w_anode1124w;
wire [3:0] w_anode1135w;
wire [3:0] w_anode1147w;
wire [3:0] w_anode1158w;
wire [3:0] w_anode1168w;
wire [3:0] w_anode1178w;
wire [3:0] w_anode1188w;
wire [3:0] w_anode1198w;
wire [3:0] w_anode1208w;
wire [3:0] w_anode1218w;
wire [3:0] w_anode464w;
wire [3:0] w_anode482w;
wire [3:0] w_anode499w;
wire [3:0] w_anode509w;
wire [3:0] w_anode519w;
wire [3:0] w_anode529w;
wire [3:0] w_anode539w;
wire [3:0] w_anode549w;
wire [3:0] w_anode559w;
wire [3:0] w_anode571w;
wire [3:0] w_anode583w;
wire [3:0] w_anode594w;
wire [3:0] w_anode604w;
wire [3:0] w_anode614w;
wire [3:0] w_anode624w;
wire [3:0] w_anode634w;
wire [3:0] w_anode644w;
wire [3:0] w_anode654w;
wire [3:0] w_anode665w;
wire [3:0] w_anode677w;
wire [3:0] w_anode688w;
wire [3:0] w_anode698w;
wire [3:0] w_anode708w;
wire [3:0] w_anode718w;
wire [3:0] w_anode728w;
wire [3:0] w_anode738w;
wire [3:0] w_anode748w;
wire [3:0] w_anode759w;
wire [3:0] w_anode771w;
wire [3:0] w_anode782w;
wire [3:0] w_anode792w;
wire [3:0] w_anode802w;
wire [3:0] w_anode812w;
wire [3:0] w_anode822w;
wire [3:0] w_anode832w;
wire [3:0] w_anode842w;
wire [3:0] w_anode853w;
wire [3:0] w_anode865w;
wire [3:0] w_anode876w;
wire [3:0] w_anode886w;
wire [3:0] w_anode896w;
wire [3:0] w_anode906w;
wire [3:0] w_anode916w;
wire [3:0] w_anode926w;
wire [3:0] w_anode936w;
wire [3:0] w_anode947w;
wire [3:0] w_anode959w;
wire [3:0] w_anode970w;
wire [3:0] w_anode980w;
wire [3:0] w_anode990w;
wire [2:0] w_data462w;
assign
data_wire = data,
eq = eq_node,
eq_node = eq_wire[63:0],
eq_wire = {{w_anode1218w[3], w_anode1208w[3], w_anode1198w[3], w_anode1188w[3], w_anode1178w[3], w_anode1168w[3], w_anode1158w[3], w_anode1147w[3]}, {w_anode1124w[3], w_anode1114w[3], w_anode1104w[3], w_anode1094w[3], w_anode1084w[3], w_anode1074w[3], w_anode1064w[3], w_anode1053w[3]}, {w_anode1030w[3], w_anode1020w[3], w_anode1010w[3], w_anode1000w[3], w_anode990w[3], w_anode980w[3], w_anode970w[3], w_anode959w[3]}, {w_anode936w[3], w_anode926w[3], w_anode916w[3], w_anode906w[3], w_anode896w[3], w_anode886w[3], w_anode876w[3], w_anode865w[3]}, {w_anode842w[3], w_anode832w[3], w_anode822w[3], w_anode812w[3], w_anode802w[3], w_anode792w[3], w_anode782w[3], w_anode771w[3]}, {w_anode748w[3], w_anode738w[3], w_anode728w[3], w_anode718w[3], w_anode708w[3], w_anode698w[3], w_anode688w[3], w_anode677w[3]}, {w_anode654w[3], w_anode644w[3], w_anode634w[3], w_anode624w[3], w_anode614w[3], w_anode604w[3], w_anode594w[3], w_anode583w[3]}, {w_anode559w[3], w_anode549w[3], w_anode539w[3], w_anode529w[3], w_anode519w[3], w_anode509w[3], w_anode499w[3], w_anode482w[3]}},
w_anode1000w = {(w_anode1000w[2] & w_data462w[2]), (w_anode1000w[1] & (~ w_data462w[1])), (w_anode1000w[0] & (~ w_data462w[0])), w_anode947w[3]},
w_anode1010w = {(w_anode1010w[2] & w_data462w[2]), (w_anode1010w[1] & (~ w_data462w[1])), (w_anode1010w[0] & w_data462w[0]), w_anode947w[3]},
w_anode1020w = {(w_anode1020w[2] & w_data462w[2]), (w_anode1020w[1] & w_data462w[1]), (w_anode1020w[0] & (~ w_data462w[0])), w_anode947w[3]},
w_anode1030w = {(w_anode1030w[2] & w_data462w[2]), (w_anode1030w[1] & w_data462w[1]), (w_anode1030w[0] & w_data462w[0]), w_anode947w[3]},
w_anode1041w = {(w_anode1041w[2] & data_wire[5]), (w_anode1041w[1] & data_wire[4]), (w_anode1041w[0] & (~ data_wire[3])), 1'b1},
w_anode1053w = {(w_anode1053w[2] & (~ w_data462w[2])), (w_anode1053w[1] & (~ w_data462w[1])), (w_anode1053w[0] & (~ w_data462w[0])), w_anode1041w[3]},
w_anode1064w = {(w_anode1064w[2] & (~ w_data462w[2])), (w_anode1064w[1] & (~ w_data462w[1])), (w_anode1064w[0] & w_data462w[0]), w_anode1041w[3]},
w_anode1074w = {(w_anode1074w[2] & (~ w_data462w[2])), (w_anode1074w[1] & w_data462w[1]), (w_anode1074w[0] & (~ w_data462w[0])), w_anode1041w[3]},
w_anode1084w = {(w_anode1084w[2] & (~ w_data462w[2])), (w_anode1084w[1] & w_data462w[1]), (w_anode1084w[0] & w_data462w[0]), w_anode1041w[3]},
w_anode1094w = {(w_anode1094w[2] & w_data462w[2]), (w_anode1094w[1] & (~ w_data462w[1])), (w_anode1094w[0] & (~ w_data462w[0])), w_anode1041w[3]},
w_anode1104w = {(w_anode1104w[2] & w_data462w[2]), (w_anode1104w[1] & (~ w_data462w[1])), (w_anode1104w[0] & w_data462w[0]), w_anode1041w[3]},
w_anode1114w = {(w_anode1114w[2] & w_data462w[2]), (w_anode1114w[1] & w_data462w[1]), (w_anode1114w[0] & (~ w_data462w[0])), w_anode1041w[3]},
w_anode1124w = {(w_anode1124w[2] & w_data462w[2]), (w_anode1124w[1] & w_data462w[1]), (w_anode1124w[0] & w_data462w[0]), w_anode1041w[3]},
w_anode1135w = {(w_anode1135w[2] & data_wire[5]), (w_anode1135w[1] & data_wire[4]), (w_anode1135w[0] & data_wire[3]), 1'b1},
w_anode1147w = {(w_anode1147w[2] & (~ w_data462w[2])), (w_anode1147w[1] & (~ w_data462w[1])), (w_anode1147w[0] & (~ w_data462w[0])), w_anode1135w[3]},
w_anode1158w = {(w_anode1158w[2] & (~ w_data462w[2])), (w_anode1158w[1] & (~ w_data462w[1])), (w_anode1158w[0] & w_data462w[0]), w_anode1135w[3]},
w_anode1168w = {(w_anode1168w[2] & (~ w_data462w[2])), (w_anode1168w[1] & w_data462w[1]), (w_anode1168w[0] & (~ w_data462w[0])), w_anode1135w[3]},
w_anode1178w = {(w_anode1178w[2] & (~ w_data462w[2])), (w_anode1178w[1] & w_data462w[1]), (w_anode1178w[0] & w_data462w[0]), w_anode1135w[3]},
w_anode1188w = {(w_anode1188w[2] & w_data462w[2]), (w_anode1188w[1] & (~ w_data462w[1])), (w_anode1188w[0] & (~ w_data462w[0])), w_anode1135w[3]},
w_anode1198w = {(w_anode1198w[2] & w_data462w[2]), (w_anode1198w[1] & (~ w_data462w[1])), (w_anode1198w[0] & w_data462w[0]), w_anode1135w[3]},
w_anode1208w = {(w_anode1208w[2] & w_data462w[2]), (w_anode1208w[1] & w_data462w[1]), (w_anode1208w[0] & (~ w_data462w[0])), w_anode1135w[3]},
w_anode1218w = {(w_anode1218w[2] & w_data462w[2]), (w_anode1218w[1] & w_data462w[1]), (w_anode1218w[0] & w_data462w[0]), w_anode1135w[3]},
w_anode464w = {(w_anode464w[2] & (~ data_wire[5])), (w_anode464w[1] & (~ data_wire[4])), (w_anode464w[0] & (~ data_wire[3])), 1'b1},
w_anode482w = {(w_anode482w[2] & (~ w_data462w[2])), (w_anode482w[1] & (~ w_data462w[1])), (w_anode482w[0] & (~ w_data462w[0])), w_anode464w[3]},
w_anode499w = {(w_anode499w[2] & (~ w_data462w[2])), (w_anode499w[1] & (~ w_data462w[1])), (w_anode499w[0] & w_data462w[0]), w_anode464w[3]},
w_anode509w = {(w_anode509w[2] & (~ w_data462w[2])), (w_anode509w[1] & w_data462w[1]), (w_anode509w[0] & (~ w_data462w[0])), w_anode464w[3]},
w_anode519w = {(w_anode519w[2] & (~ w_data462w[2])), (w_anode519w[1] & w_data462w[1]), (w_anode519w[0] & w_data462w[0]), w_anode464w[3]},
w_anode529w = {(w_anode529w[2] & w_data462w[2]), (w_anode529w[1] & (~ w_data462w[1])), (w_anode529w[0] & (~ w_data462w[0])), w_anode464w[3]},
w_anode539w = {(w_anode539w[2] & w_data462w[2]), (w_anode539w[1] & (~ w_data462w[1])), (w_anode539w[0] & w_data462w[0]), w_anode464w[3]},
w_anode549w = {(w_anode549w[2] & w_data462w[2]), (w_anode549w[1] & w_data462w[1]), (w_anode549w[0] & (~ w_data462w[0])), w_anode464w[3]},
w_anode559w = {(w_anode559w[2] & w_data462w[2]), (w_anode559w[1] & w_data462w[1]), (w_anode559w[0] & w_data462w[0]), w_anode464w[3]},
w_anode571w = {(w_anode571w[2] & (~ data_wire[5])), (w_anode571w[1] & (~ data_wire[4])), (w_anode571w[0] & data_wire[3]), 1'b1},
w_anode583w = {(w_anode583w[2] & (~ w_data462w[2])), (w_anode583w[1] & (~ w_data462w[1])), (w_anode583w[0] & (~ w_data462w[0])), w_anode571w[3]},
w_anode594w = {(w_anode594w[2] & (~ w_data462w[2])), (w_anode594w[1] & (~ w_data462w[1])), (w_anode594w[0] & w_data462w[0]), w_anode571w[3]},
w_anode604w = {(w_anode604w[2] & (~ w_data462w[2])), (w_anode604w[1] & w_data462w[1]), (w_anode604w[0] & (~ w_data462w[0])), w_anode571w[3]},
w_anode614w = {(w_anode614w[2] & (~ w_data462w[2])), (w_anode614w[1] & w_data462w[1]), (w_anode614w[0] & w_data462w[0]), w_anode571w[3]},
w_anode624w = {(w_anode624w[2] & w_data462w[2]), (w_anode624w[1] & (~ w_data462w[1])), (w_anode624w[0] & (~ w_data462w[0])), w_anode571w[3]},
w_anode634w = {(w_anode634w[2] & w_data462w[2]), (w_anode634w[1] & (~ w_data462w[1])), (w_anode634w[0] & w_data462w[0]), w_anode571w[3]},
w_anode644w = {(w_anode644w[2] & w_data462w[2]), (w_anode644w[1] & w_data462w[1]), (w_anode644w[0] & (~ w_data462w[0])), w_anode571w[3]},
w_anode654w = {(w_anode654w[2] & w_data462w[2]), (w_anode654w[1] & w_data462w[1]), (w_anode654w[0] & w_data462w[0]), w_anode571w[3]},
w_anode665w = {(w_anode665w[2] & (~ data_wire[5])), (w_anode665w[1] & data_wire[4]), (w_anode665w[0] & (~ data_wire[3])), 1'b1},
w_anode677w = {(w_anode677w[2] & (~ w_data462w[2])), (w_anode677w[1] & (~ w_data462w[1])), (w_anode677w[0] & (~ w_data462w[0])), w_anode665w[3]},
w_anode688w = {(w_anode688w[2] & (~ w_data462w[2])), (w_anode688w[1] & (~ w_data462w[1])), (w_anode688w[0] & w_data462w[0]), w_anode665w[3]},
w_anode698w = {(w_anode698w[2] & (~ w_data462w[2])), (w_anode698w[1] & w_data462w[1]), (w_anode698w[0] & (~ w_data462w[0])), w_anode665w[3]},
w_anode708w = {(w_anode708w[2] & (~ w_data462w[2])), (w_anode708w[1] & w_data462w[1]), (w_anode708w[0] & w_data462w[0]), w_anode665w[3]},
w_anode718w = {(w_anode718w[2] & w_data462w[2]), (w_anode718w[1] & (~ w_data462w[1])), (w_anode718w[0] & (~ w_data462w[0])), w_anode665w[3]},
w_anode728w = {(w_anode728w[2] & w_data462w[2]), (w_anode728w[1] & (~ w_data462w[1])), (w_anode728w[0] & w_data462w[0]), w_anode665w[3]},
w_anode738w = {(w_anode738w[2] & w_data462w[2]), (w_anode738w[1] & w_data462w[1]), (w_anode738w[0] & (~ w_data462w[0])), w_anode665w[3]},
w_anode748w = {(w_anode748w[2] & w_data462w[2]), (w_anode748w[1] & w_data462w[1]), (w_anode748w[0] & w_data462w[0]), w_anode665w[3]},
w_anode759w = {(w_anode759w[2] & (~ data_wire[5])), (w_anode759w[1] & data_wire[4]), (w_anode759w[0] & data_wire[3]), 1'b1},
w_anode771w = {(w_anode771w[2] & (~ w_data462w[2])), (w_anode771w[1] & (~ w_data462w[1])), (w_anode771w[0] & (~ w_data462w[0])), w_anode759w[3]},
w_anode782w = {(w_anode782w[2] & (~ w_data462w[2])), (w_anode782w[1] & (~ w_data462w[1])), (w_anode782w[0] & w_data462w[0]), w_anode759w[3]},
w_anode792w = {(w_anode792w[2] & (~ w_data462w[2])), (w_anode792w[1] & w_data462w[1]), (w_anode792w[0] & (~ w_data462w[0])), w_anode759w[3]},
w_anode802w = {(w_anode802w[2] & (~ w_data462w[2])), (w_anode802w[1] & w_data462w[1]), (w_anode802w[0] & w_data462w[0]), w_anode759w[3]},
w_anode812w = {(w_anode812w[2] & w_data462w[2]), (w_anode812w[1] & (~ w_data462w[1])), (w_anode812w[0] & (~ w_data462w[0])), w_anode759w[3]},
w_anode822w = {(w_anode822w[2] & w_data462w[2]), (w_anode822w[1] & (~ w_data462w[1])), (w_anode822w[0] & w_data462w[0]), w_anode759w[3]},
w_anode832w = {(w_anode832w[2] & w_data462w[2]), (w_anode832w[1] & w_data462w[1]), (w_anode832w[0] & (~ w_data462w[0])), w_anode759w[3]},
w_anode842w = {(w_anode842w[2] & w_data462w[2]), (w_anode842w[1] & w_data462w[1]), (w_anode842w[0] & w_data462w[0]), w_anode759w[3]},
w_anode853w = {(w_anode853w[2] & data_wire[5]), (w_anode853w[1] & (~ data_wire[4])), (w_anode853w[0] & (~ data_wire[3])), 1'b1},
w_anode865w = {(w_anode865w[2] & (~ w_data462w[2])), (w_anode865w[1] & (~ w_data462w[1])), (w_anode865w[0] & (~ w_data462w[0])), w_anode853w[3]},
w_anode876w = {(w_anode876w[2] & (~ w_data462w[2])), (w_anode876w[1] & (~ w_data462w[1])), (w_anode876w[0] & w_data462w[0]), w_anode853w[3]},
w_anode886w = {(w_anode886w[2] & (~ w_data462w[2])), (w_anode886w[1] & w_data462w[1]), (w_anode886w[0] & (~ w_data462w[0])), w_anode853w[3]},
w_anode896w = {(w_anode896w[2] & (~ w_data462w[2])), (w_anode896w[1] & w_data462w[1]), (w_anode896w[0] & w_data462w[0]), w_anode853w[3]},
w_anode906w = {(w_anode906w[2] & w_data462w[2]), (w_anode906w[1] & (~ w_data462w[1])), (w_anode906w[0] & (~ w_data462w[0])), w_anode853w[3]},
w_anode916w = {(w_anode916w[2] & w_data462w[2]), (w_anode916w[1] & (~ w_data462w[1])), (w_anode916w[0] & w_data462w[0]), w_anode853w[3]},
w_anode926w = {(w_anode926w[2] & w_data462w[2]), (w_anode926w[1] & w_data462w[1]), (w_anode926w[0] & (~ w_data462w[0])), w_anode853w[3]},
w_anode936w = {(w_anode936w[2] & w_data462w[2]), (w_anode936w[1] & w_data462w[1]), (w_anode936w[0] & w_data462w[0]), w_anode853w[3]},
w_anode947w = {(w_anode947w[2] & data_wire[5]), (w_anode947w[1] & (~ data_wire[4])), (w_anode947w[0] & data_wire[3]), 1'b1},
w_anode959w = {(w_anode959w[2] & (~ w_data462w[2])), (w_anode959w[1] & (~ w_data462w[1])), (w_anode959w[0] & (~ w_data462w[0])), w_anode947w[3]},
w_anode970w = {(w_anode970w[2] & (~ w_data462w[2])), (w_anode970w[1] & (~ w_data462w[1])), (w_anode970w[0] & w_data462w[0]), w_anode947w[3]},
w_anode980w = {(w_anode980w[2] & (~ w_data462w[2])), (w_anode980w[1] & w_data462w[1]), (w_anode980w[0] & (~ w_data462w[0])), w_anode947w[3]},
w_anode990w = {(w_anode990w[2] & (~ w_data462w[2])), (w_anode990w[1] & w_data462w[1]), (w_anode990w[0] & w_data462w[0]), w_anode947w[3]},
w_data462w = data_wire[2:0];
endmodule //alt_mem_ddrx_ecc_decoder_32_decode
//synthesis_resources = lut 72 mux21 32
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module alt_mem_ddrx_ecc_decoder_32_altecc_decoder
(
data,
err_corrected,
err_detected,
err_fatal,
err_sbe,
q) /* synthesis synthesis_clearbox=1 */;
input [38:0] data;
output err_corrected;
output err_detected;
output err_fatal;
output err_sbe;
output [31:0] q;
wire [63:0] wire_error_bit_decoder_eq;
wire wire_mux21_0_dataout;
wire wire_mux21_1_dataout;
wire wire_mux21_10_dataout;
wire wire_mux21_11_dataout;
wire wire_mux21_12_dataout;
wire wire_mux21_13_dataout;
wire wire_mux21_14_dataout;
wire wire_mux21_15_dataout;
wire wire_mux21_16_dataout;
wire wire_mux21_17_dataout;
wire wire_mux21_18_dataout;
wire wire_mux21_19_dataout;
wire wire_mux21_2_dataout;
wire wire_mux21_20_dataout;
wire wire_mux21_21_dataout;
wire wire_mux21_22_dataout;
wire wire_mux21_23_dataout;
wire wire_mux21_24_dataout;
wire wire_mux21_25_dataout;
wire wire_mux21_26_dataout;
wire wire_mux21_27_dataout;
wire wire_mux21_28_dataout;
wire wire_mux21_29_dataout;
wire wire_mux21_3_dataout;
wire wire_mux21_30_dataout;
wire wire_mux21_31_dataout;
wire wire_mux21_4_dataout;
wire wire_mux21_5_dataout;
wire wire_mux21_6_dataout;
wire wire_mux21_7_dataout;
wire wire_mux21_8_dataout;
wire wire_mux21_9_dataout;
wire data_bit;
wire [31:0] data_t;
wire [38:0] data_wire;
wire [63:0] decode_output;
wire err_corrected_wire;
wire err_detected_wire;
wire err_fatal_wire;
wire [18:0] parity_01_wire;
wire [9:0] parity_02_wire;
wire [4:0] parity_03_wire;
wire [1:0] parity_04_wire;
wire [0:0] parity_05_wire;
wire [5:0] parity_06_wire;
wire parity_bit;
wire [37:0] parity_final_wire;
wire [5:0] parity_t;
wire [31:0] q_wire;
wire syn_bit;
wire syn_e;
wire [4:0] syn_t;
wire [6:0] syndrome;
alt_mem_ddrx_ecc_decoder_32_decode error_bit_decoder
(
.data(syndrome[5:0]),
.eq(wire_error_bit_decoder_eq));
assign wire_mux21_0_dataout = (syndrome[6] == 1'b1) ? (decode_output[3] ^ data_wire[0]) : data_wire[0];
assign wire_mux21_1_dataout = (syndrome[6] == 1'b1) ? (decode_output[5] ^ data_wire[1]) : data_wire[1];
assign wire_mux21_10_dataout = (syndrome[6] == 1'b1) ? (decode_output[15] ^ data_wire[10]) : data_wire[10];
assign wire_mux21_11_dataout = (syndrome[6] == 1'b1) ? (decode_output[17] ^ data_wire[11]) : data_wire[11];
assign wire_mux21_12_dataout = (syndrome[6] == 1'b1) ? (decode_output[18] ^ data_wire[12]) : data_wire[12];
assign wire_mux21_13_dataout = (syndrome[6] == 1'b1) ? (decode_output[19] ^ data_wire[13]) : data_wire[13];
assign wire_mux21_14_dataout = (syndrome[6] == 1'b1) ? (decode_output[20] ^ data_wire[14]) : data_wire[14];
assign wire_mux21_15_dataout = (syndrome[6] == 1'b1) ? (decode_output[21] ^ data_wire[15]) : data_wire[15];
assign wire_mux21_16_dataout = (syndrome[6] == 1'b1) ? (decode_output[22] ^ data_wire[16]) : data_wire[16];
assign wire_mux21_17_dataout = (syndrome[6] == 1'b1) ? (decode_output[23] ^ data_wire[17]) : data_wire[17];
assign wire_mux21_18_dataout = (syndrome[6] == 1'b1) ? (decode_output[24] ^ data_wire[18]) : data_wire[18];
assign wire_mux21_19_dataout = (syndrome[6] == 1'b1) ? (decode_output[25] ^ data_wire[19]) : data_wire[19];
assign wire_mux21_2_dataout = (syndrome[6] == 1'b1) ? (decode_output[6] ^ data_wire[2]) : data_wire[2];
assign wire_mux21_20_dataout = (syndrome[6] == 1'b1) ? (decode_output[26] ^ data_wire[20]) : data_wire[20];
assign wire_mux21_21_dataout = (syndrome[6] == 1'b1) ? (decode_output[27] ^ data_wire[21]) : data_wire[21];
assign wire_mux21_22_dataout = (syndrome[6] == 1'b1) ? (decode_output[28] ^ data_wire[22]) : data_wire[22];
assign wire_mux21_23_dataout = (syndrome[6] == 1'b1) ? (decode_output[29] ^ data_wire[23]) : data_wire[23];
assign wire_mux21_24_dataout = (syndrome[6] == 1'b1) ? (decode_output[30] ^ data_wire[24]) : data_wire[24];
assign wire_mux21_25_dataout = (syndrome[6] == 1'b1) ? (decode_output[31] ^ data_wire[25]) : data_wire[25];
assign wire_mux21_26_dataout = (syndrome[6] == 1'b1) ? (decode_output[33] ^ data_wire[26]) : data_wire[26];
assign wire_mux21_27_dataout = (syndrome[6] == 1'b1) ? (decode_output[34] ^ data_wire[27]) : data_wire[27];
assign wire_mux21_28_dataout = (syndrome[6] == 1'b1) ? (decode_output[35] ^ data_wire[28]) : data_wire[28];
assign wire_mux21_29_dataout = (syndrome[6] == 1'b1) ? (decode_output[36] ^ data_wire[29]) : data_wire[29];
assign wire_mux21_3_dataout = (syndrome[6] == 1'b1) ? (decode_output[7] ^ data_wire[3]) : data_wire[3];
assign wire_mux21_30_dataout = (syndrome[6] == 1'b1) ? (decode_output[37] ^ data_wire[30]) : data_wire[30];
assign wire_mux21_31_dataout = (syndrome[6] == 1'b1) ? (decode_output[38] ^ data_wire[31]) : data_wire[31];
assign wire_mux21_4_dataout = (syndrome[6] == 1'b1) ? (decode_output[9] ^ data_wire[4]) : data_wire[4];
assign wire_mux21_5_dataout = (syndrome[6] == 1'b1) ? (decode_output[10] ^ data_wire[5]) : data_wire[5];
assign wire_mux21_6_dataout = (syndrome[6] == 1'b1) ? (decode_output[11] ^ data_wire[6]) : data_wire[6];
assign wire_mux21_7_dataout = (syndrome[6] == 1'b1) ? (decode_output[12] ^ data_wire[7]) : data_wire[7];
assign wire_mux21_8_dataout = (syndrome[6] == 1'b1) ? (decode_output[13] ^ data_wire[8]) : data_wire[8];
assign wire_mux21_9_dataout = (syndrome[6] == 1'b1) ? (decode_output[14] ^ data_wire[9]) : data_wire[9];
assign
data_bit = data_t[31],
data_t = {(data_t[30] | decode_output[38]), (data_t[29] | decode_output[37]), (data_t[28] | decode_output[36]), (data_t[27] | decode_output[35]), (data_t[26] | decode_output[34]), (data_t[25] | decode_output[33]), (data_t[24] | decode_output[31]), (data_t[23] | decode_output[30]), (data_t[22] | decode_output[29]), (data_t[21] | decode_output[28]), (data_t[20] | decode_output[27]), (data_t[19] | decode_output[26]), (data_t[18] | decode_output[25]), (data_t[17] | decode_output[24]), (data_t[16] | decode_output[23]), (data_t[15] | decode_output[22]), (data_t[14] | decode_output[21]), (data_t[13] | decode_output[20]), (data_t[12] | decode_output[19]), (data_t[11] | decode_output[18]), (data_t[10] | decode_output[17]), (data_t[9] | decode_output[15]), (data_t[8] | decode_output[14]), (data_t[7] | decode_output[13]), (data_t[6] | decode_output[12]), (data_t[5] | decode_output[11]), (data_t[4] | decode_output[10]), (data_t[3] | decode_output[9]), (data_t[2] | decode_output[7]), (data_t[1] | decode_output[6]), (data_t[0] | decode_output[5]), decode_output[3]},
data_wire = data,
decode_output = wire_error_bit_decoder_eq,
err_corrected = err_corrected_wire,
err_corrected_wire = ((syn_bit & syn_e) & data_bit),
err_detected = err_detected_wire,
err_detected_wire = (syn_bit & (~ (syn_e & parity_bit))),
err_fatal = err_fatal_wire,
err_sbe = syn_e,
err_fatal_wire = (err_detected_wire & (~ err_corrected_wire)),
parity_01_wire = {(data_wire[30] ^ parity_01_wire[17]), (data_wire[28] ^ parity_01_wire[16]), (data_wire[26] ^ parity_01_wire[15]), (data_wire[25] ^ parity_01_wire[14]), (data_wire[23] ^ parity_01_wire[13]), (data_wire[21] ^ parity_01_wire[12]), (data_wire[19] ^ parity_01_wire[11]), (data_wire[17] ^ parity_01_wire[10]), (data_wire[15] ^ parity_01_wire[9]), (data_wire[13] ^ parity_01_wire[8]), (data_wire[11] ^ parity_01_wire[7]), (data_wire[10] ^ parity_01_wire[6]), (data_wire[8] ^ parity_01_wire[5]), (data_wire[6] ^ parity_01_wire[4]), (data_wire[4] ^ parity_01_wire[3]), (data_wire[3] ^ parity_01_wire[2]), (data_wire[1] ^ parity_01_wire[1]), (data_wire[0] ^ parity_01_wire[0]), data_wire[32]},
parity_02_wire = {(data_wire[31] ^ parity_02_wire[8]), ((data_wire[27] ^ data_wire[28]) ^ parity_02_wire[7]), ((data_wire[24] ^ data_wire[25]) ^ parity_02_wire[6]), ((data_wire[20] ^ data_wire[21]) ^ parity_02_wire[5]), ((data_wire[16] ^ data_wire[17]) ^ parity_02_wire[4]), ((data_wire[12] ^ data_wire[13]) ^ parity_02_wire[3]), ((data_wire[9] ^ data_wire[10]) ^ parity_02_wire[2]), ((data_wire[5] ^ data_wire[6]) ^ parity_02_wire[1]), ((data_wire[2] ^ data_wire[3]) ^ parity_02_wire[0]), (data_wire[33] ^ data_wire[0])},
parity_03_wire = {(((data_wire[29] ^ data_wire[30]) ^ data_wire[31]) ^ parity_03_wire[3]), ((((data_wire[22] ^ data_wire[23]) ^ data_wire[24]) ^ data_wire[25]) ^ parity_03_wire[2]), ((((data_wire[14] ^ data_wire[15]) ^ data_wire[16]) ^ data_wire[17]) ^ parity_03_wire[1]), ((((data_wire[7] ^ data_wire[8]) ^ data_wire[9]) ^ data_wire[10]) ^ parity_03_wire[0]), (((data_wire[34] ^ data_wire[1]) ^ data_wire[2]) ^ data_wire[3])},
parity_04_wire = {((((((((data_wire[18] ^ data_wire[19]) ^ data_wire[20]) ^ data_wire[21]) ^ data_wire[22]) ^ data_wire[23]) ^ data_wire[24]) ^ data_wire[25]) ^ parity_04_wire[0]), (((((((data_wire[35] ^ data_wire[4]) ^ data_wire[5]) ^ data_wire[6]) ^ data_wire[7]) ^ data_wire[8]) ^ data_wire[9]) ^ data_wire[10])},
parity_05_wire = {(((((((((((((((data_wire[36] ^ data_wire[11]) ^ data_wire[12]) ^ data_wire[13]) ^ data_wire[14]) ^ data_wire[15]) ^ data_wire[16]) ^ data_wire[17]) ^ data_wire[18]) ^ data_wire[19]) ^ data_wire[20]) ^ data_wire[21]) ^ data_wire[22]) ^ data_wire[23]) ^ data_wire[24]) ^ data_wire[25])},
parity_06_wire = {(data_wire[31] ^ parity_06_wire[4]), (data_wire[30] ^ parity_06_wire[3]), (data_wire[29] ^ parity_06_wire[2]), (data_wire[28] ^ parity_06_wire[1]), (data_wire[27] ^ parity_06_wire[0]), (data_wire[37] ^ data_wire[26])},
parity_bit = parity_t[5],
parity_final_wire = {(data_wire[37] ^ parity_final_wire[36]), (data_wire[36] ^ parity_final_wire[35]), (data_wire[35] ^ parity_final_wire[34]), (data_wire[34] ^ parity_final_wire[33]), (data_wire[33] ^ parity_final_wire[32]), (data_wire[32] ^ parity_final_wire[31]), (data_wire[31] ^ parity_final_wire[30]), (data_wire[30] ^ parity_final_wire[29]), (data_wire[29] ^ parity_final_wire[28]), (data_wire[28] ^ parity_final_wire[27]), (data_wire[27] ^ parity_final_wire[26]), (data_wire[26] ^ parity_final_wire[25]), (data_wire[25] ^ parity_final_wire[24]), (data_wire[24] ^ parity_final_wire[23]), (data_wire[23] ^ parity_final_wire[22]), (data_wire[22] ^ parity_final_wire[21]), (data_wire[21] ^ parity_final_wire[20]), (data_wire[20] ^ parity_final_wire[19]), (data_wire[19] ^ parity_final_wire[18]), (data_wire[18] ^ parity_final_wire[17]), (data_wire[17] ^ parity_final_wire[16]), (data_wire[16] ^ parity_final_wire[15]), (data_wire[15] ^ parity_final_wire[14]), (data_wire[14] ^ parity_final_wire[13]), (data_wire[13] ^ parity_final_wire[12]), (data_wire[12] ^ parity_final_wire[11]), (data_wire[11] ^ parity_final_wire[10]), (data_wire[10] ^ parity_final_wire[9]), (data_wire[9] ^ parity_final_wire[8]), (data_wire[8] ^ parity_final_wire[7]), (data_wire[7] ^ parity_final_wire[6]), (data_wire[6] ^ parity_final_wire[5]), (data_wire[5] ^ parity_final_wire[4]), (data_wire[4] ^ parity_final_wire[3]), (data_wire[3] ^ parity_final_wire[2]), (data_wire[2] ^ parity_final_wire[1]), (data_wire[1] ^ parity_final_wire[0]), (data_wire[38] ^ data_wire[0])},
parity_t = {(parity_t[4] | decode_output[32]), (parity_t[3] | decode_output[16]), (parity_t[2] | decode_output[8]), (parity_t[1] | decode_output[4]), (parity_t[0] | decode_output[2]), decode_output[1]},
q = q_wire,
q_wire = {wire_mux21_31_dataout, wire_mux21_30_dataout, wire_mux21_29_dataout, wire_mux21_28_dataout, wire_mux21_27_dataout, wire_mux21_26_dataout, wire_mux21_25_dataout, wire_mux21_24_dataout, wire_mux21_23_dataout, wire_mux21_22_dataout, wire_mux21_21_dataout, wire_mux21_20_dataout, wire_mux21_19_dataout, wire_mux21_18_dataout, wire_mux21_17_dataout, wire_mux21_16_dataout, wire_mux21_15_dataout, wire_mux21_14_dataout, wire_mux21_13_dataout, wire_mux21_12_dataout, wire_mux21_11_dataout, wire_mux21_10_dataout, wire_mux21_9_dataout, wire_mux21_8_dataout, wire_mux21_7_dataout, wire_mux21_6_dataout, wire_mux21_5_dataout, wire_mux21_4_dataout, wire_mux21_3_dataout, wire_mux21_2_dataout, wire_mux21_1_dataout, wire_mux21_0_dataout},
syn_bit = syn_t[4],
syn_e = syndrome[6],
syn_t = {(syn_t[3] | syndrome[5]), (syn_t[2] | syndrome[4]), (syn_t[1] | syndrome[3]), (syn_t[0] | syndrome[2]), (syndrome[0] | syndrome[1])},
syndrome = {parity_final_wire[37], parity_06_wire[5], parity_05_wire[0], parity_04_wire[1], parity_03_wire[4], parity_02_wire[9], parity_01_wire[18]};
endmodule //alt_mem_ddrx_ecc_decoder_32_altecc_decoder
//VALID FILE
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module alt_mem_ddrx_ecc_decoder_32 (
data,
err_corrected,
err_detected,
err_fatal,
err_sbe,
q)/* synthesis synthesis_clearbox = 1 */;
input [38:0] data;
output err_corrected;
output err_detected;
output err_fatal;
output err_sbe;
output [31:0] q;
wire sub_wire0;
wire sub_wire1;
wire sub_wire2;
wire sub_wire4;
wire [31:0] sub_wire3;
wire err_detected = sub_wire0;
wire err_fatal = sub_wire1;
wire err_corrected = sub_wire2;
wire err_sbe = sub_wire4;
wire [31:0] q = sub_wire3[31:0];
alt_mem_ddrx_ecc_decoder_32_altecc_decoder alt_mem_ddrx_ecc_decoder_32_altecc_decoder_component (
.data (data),
.err_detected (sub_wire0),
.err_fatal (sub_wire1),
.err_corrected (sub_wire2),
.err_sbe (sub_wire4),
.q (sub_wire3));
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix III"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "1"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix III"
// Retrieval info: CONSTANT: lpm_pipeline NUMERIC "0"
// Retrieval info: CONSTANT: width_codeword NUMERIC "39"
// Retrieval info: CONSTANT: width_dataword NUMERIC "32"
// Retrieval info: USED_PORT: data 0 0 39 0 INPUT NODEFVAL "data[38..0]"
// Retrieval info: USED_PORT: err_corrected 0 0 0 0 OUTPUT NODEFVAL "err_corrected"
// Retrieval info: USED_PORT: err_detected 0 0 0 0 OUTPUT NODEFVAL "err_detected"
// Retrieval info: USED_PORT: err_fatal 0 0 0 0 OUTPUT NODEFVAL "err_fatal"
// Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL "q[31..0]"
// Retrieval info: CONNECT: @data 0 0 39 0 data 0 0 39 0
// Retrieval info: CONNECT: err_corrected 0 0 0 0 @err_corrected 0 0 0 0
// Retrieval info: CONNECT: err_detected 0 0 0 0 @err_detected 0 0 0 0
// Retrieval info: CONNECT: err_fatal 0 0 0 0 @err_fatal 0 0 0 0
// Retrieval info: CONNECT: q 0 0 32 0 @q 0 0 32 0
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder_bb.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder_32.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder_32.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder_32.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder_32.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder_32_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder_32_bb.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder_32_syn.v TRUE
// Retrieval info: LIB_FILE: lpm
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// megafunction wizard: %ALTECC%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altecc_decoder
// ============================================================
// File Name: alt_mem_ddrx_ecc_decoder_64.v
// Megafunction Name(s):
// altecc_decoder
//
// Simulation Library Files(s):
// lpm
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 10.0 Build 262 08/18/2010 SP 1 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2010 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
//altecc_decoder device_family="Stratix III" lpm_pipeline=0 width_codeword=72 width_dataword=64 data err_corrected err_detected err_fatal q
//VERSION_BEGIN 10.0SP1 cbx_altecc_decoder 2010:08:18:21:16:35:SJ cbx_cycloneii 2010:08:18:21:16:35:SJ cbx_lpm_add_sub 2010:08:18:21:16:35:SJ cbx_lpm_compare 2010:08:18:21:16:35:SJ cbx_lpm_decode 2010:08:18:21:16:35:SJ cbx_mgl 2010:08:18:21:20:44:SJ cbx_stratix 2010:08:18:21:16:35:SJ cbx_stratixii 2010:08:18:21:16:35:SJ VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
//lpm_decode DEVICE_FAMILY="Stratix III" LPM_DECODES=128 LPM_WIDTH=7 data eq
//VERSION_BEGIN 10.0SP1 cbx_cycloneii 2010:08:18:21:16:35:SJ cbx_lpm_add_sub 2010:08:18:21:16:35:SJ cbx_lpm_compare 2010:08:18:21:16:35:SJ cbx_lpm_decode 2010:08:18:21:16:35:SJ cbx_mgl 2010:08:18:21:20:44:SJ cbx_stratix 2010:08:18:21:16:35:SJ cbx_stratixii 2010:08:18:21:16:35:SJ VERSION_END
//synthesis_resources = lut 144
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module alt_mem_ddrx_ecc_decoder_64_decode
(
data,
eq) /* synthesis synthesis_clearbox=1 */;
input [6:0] data;
output [127:0] eq;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 [6:0] data;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [5:0] data_wire;
wire enable_wire1;
wire enable_wire2;
wire [127:0] eq_node;
wire [63:0] eq_wire1;
wire [63:0] eq_wire2;
wire [3:0] w_anode1006w;
wire [3:0] w_anode1018w;
wire [3:0] w_anode1029w;
wire [3:0] w_anode1040w;
wire [3:0] w_anode1050w;
wire [3:0] w_anode1060w;
wire [3:0] w_anode1070w;
wire [3:0] w_anode1080w;
wire [3:0] w_anode1090w;
wire [3:0] w_anode1100w;
wire [3:0] w_anode1111w;
wire [3:0] w_anode1122w;
wire [3:0] w_anode1133w;
wire [3:0] w_anode1143w;
wire [3:0] w_anode1153w;
wire [3:0] w_anode1163w;
wire [3:0] w_anode1173w;
wire [3:0] w_anode1183w;
wire [3:0] w_anode1193w;
wire [3:0] w_anode1204w;
wire [3:0] w_anode1215w;
wire [3:0] w_anode1226w;
wire [3:0] w_anode1236w;
wire [3:0] w_anode1246w;
wire [3:0] w_anode1256w;
wire [3:0] w_anode1266w;
wire [3:0] w_anode1276w;
wire [3:0] w_anode1286w;
wire [3:0] w_anode1297w;
wire [3:0] w_anode1308w;
wire [3:0] w_anode1319w;
wire [3:0] w_anode1329w;
wire [3:0] w_anode1339w;
wire [3:0] w_anode1349w;
wire [3:0] w_anode1359w;
wire [3:0] w_anode1369w;
wire [3:0] w_anode1379w;
wire [3:0] w_anode1390w;
wire [3:0] w_anode1401w;
wire [3:0] w_anode1412w;
wire [3:0] w_anode1422w;
wire [3:0] w_anode1432w;
wire [3:0] w_anode1442w;
wire [3:0] w_anode1452w;
wire [3:0] w_anode1462w;
wire [3:0] w_anode1472w;
wire [3:0] w_anode1483w;
wire [3:0] w_anode1494w;
wire [3:0] w_anode1505w;
wire [3:0] w_anode1515w;
wire [3:0] w_anode1525w;
wire [3:0] w_anode1535w;
wire [3:0] w_anode1545w;
wire [3:0] w_anode1555w;
wire [3:0] w_anode1565w;
wire [3:0] w_anode1576w;
wire [3:0] w_anode1587w;
wire [3:0] w_anode1598w;
wire [3:0] w_anode1608w;
wire [3:0] w_anode1618w;
wire [3:0] w_anode1628w;
wire [3:0] w_anode1638w;
wire [3:0] w_anode1648w;
wire [3:0] w_anode1658w;
wire [3:0] w_anode1670w;
wire [3:0] w_anode1681w;
wire [3:0] w_anode1698w;
wire [3:0] w_anode1708w;
wire [3:0] w_anode1718w;
wire [3:0] w_anode1728w;
wire [3:0] w_anode1738w;
wire [3:0] w_anode1748w;
wire [3:0] w_anode1758w;
wire [3:0] w_anode1770w;
wire [3:0] w_anode1781w;
wire [3:0] w_anode1792w;
wire [3:0] w_anode1802w;
wire [3:0] w_anode1812w;
wire [3:0] w_anode1822w;
wire [3:0] w_anode1832w;
wire [3:0] w_anode1842w;
wire [3:0] w_anode1852w;
wire [3:0] w_anode1863w;
wire [3:0] w_anode1874w;
wire [3:0] w_anode1885w;
wire [3:0] w_anode1895w;
wire [3:0] w_anode1905w;
wire [3:0] w_anode1915w;
wire [3:0] w_anode1925w;
wire [3:0] w_anode1935w;
wire [3:0] w_anode1945w;
wire [3:0] w_anode1956w;
wire [3:0] w_anode1967w;
wire [3:0] w_anode1978w;
wire [3:0] w_anode1988w;
wire [3:0] w_anode1998w;
wire [3:0] w_anode2008w;
wire [3:0] w_anode2018w;
wire [3:0] w_anode2028w;
wire [3:0] w_anode2038w;
wire [3:0] w_anode2049w;
wire [3:0] w_anode2060w;
wire [3:0] w_anode2071w;
wire [3:0] w_anode2081w;
wire [3:0] w_anode2091w;
wire [3:0] w_anode2101w;
wire [3:0] w_anode2111w;
wire [3:0] w_anode2121w;
wire [3:0] w_anode2131w;
wire [3:0] w_anode2142w;
wire [3:0] w_anode2153w;
wire [3:0] w_anode2164w;
wire [3:0] w_anode2174w;
wire [3:0] w_anode2184w;
wire [3:0] w_anode2194w;
wire [3:0] w_anode2204w;
wire [3:0] w_anode2214w;
wire [3:0] w_anode2224w;
wire [3:0] w_anode2235w;
wire [3:0] w_anode2246w;
wire [3:0] w_anode2257w;
wire [3:0] w_anode2267w;
wire [3:0] w_anode2277w;
wire [3:0] w_anode2287w;
wire [3:0] w_anode2297w;
wire [3:0] w_anode2307w;
wire [3:0] w_anode2317w;
wire [3:0] w_anode2328w;
wire [3:0] w_anode2339w;
wire [3:0] w_anode2350w;
wire [3:0] w_anode2360w;
wire [3:0] w_anode2370w;
wire [3:0] w_anode2380w;
wire [3:0] w_anode2390w;
wire [3:0] w_anode2400w;
wire [3:0] w_anode2410w;
wire [3:0] w_anode912w;
wire [3:0] w_anode929w;
wire [3:0] w_anode946w;
wire [3:0] w_anode956w;
wire [3:0] w_anode966w;
wire [3:0] w_anode976w;
wire [3:0] w_anode986w;
wire [3:0] w_anode996w;
wire [2:0] w_data1669w;
wire [2:0] w_data910w;
assign
data_wire = data[5:0],
enable_wire1 = (~ data[6]),
enable_wire2 = data[6],
eq = eq_node,
eq_node = {eq_wire2[63:0], eq_wire1},
eq_wire1 = {{w_anode1658w[3], w_anode1648w[3], w_anode1638w[3], w_anode1628w[3], w_anode1618w[3], w_anode1608w[3], w_anode1598w[3], w_anode1587w[3]}, {w_anode1565w[3], w_anode1555w[3], w_anode1545w[3], w_anode1535w[3], w_anode1525w[3], w_anode1515w[3], w_anode1505w[3], w_anode1494w[3]}, {w_anode1472w[3], w_anode1462w[3], w_anode1452w[3], w_anode1442w[3], w_anode1432w[3], w_anode1422w[3], w_anode1412w[3], w_anode1401w[3]}, {w_anode1379w[3], w_anode1369w[3], w_anode1359w[3], w_anode1349w[3], w_anode1339w[3], w_anode1329w[3], w_anode1319w[3], w_anode1308w[3]}, {w_anode1286w[3], w_anode1276w[3], w_anode1266w[3], w_anode1256w[3], w_anode1246w[3], w_anode1236w[3], w_anode1226w[3], w_anode1215w[3]}, {w_anode1193w[3], w_anode1183w[3], w_anode1173w[3], w_anode1163w[3], w_anode1153w[3], w_anode1143w[3], w_anode1133w[3], w_anode1122w[3]}, {w_anode1100w[3], w_anode1090w[3], w_anode1080w[3], w_anode1070w[3], w_anode1060w[3], w_anode1050w[3], w_anode1040w[3], w_anode1029w[3]}, {w_anode1006w[3], w_anode996w[3], w_anode986w[3], w_anode976w[3], w_anode966w[3], w_anode956w[3], w_anode946w[3], w_anode929w[3]}},
eq_wire2 = {{w_anode2410w[3], w_anode2400w[3], w_anode2390w[3], w_anode2380w[3], w_anode2370w[3], w_anode2360w[3], w_anode2350w[3], w_anode2339w[3]}, {w_anode2317w[3], w_anode2307w[3], w_anode2297w[3], w_anode2287w[3], w_anode2277w[3], w_anode2267w[3], w_anode2257w[3], w_anode2246w[3]}, {w_anode2224w[3], w_anode2214w[3], w_anode2204w[3], w_anode2194w[3], w_anode2184w[3], w_anode2174w[3], w_anode2164w[3], w_anode2153w[3]}, {w_anode2131w[3], w_anode2121w[3], w_anode2111w[3], w_anode2101w[3], w_anode2091w[3], w_anode2081w[3], w_anode2071w[3], w_anode2060w[3]}, {w_anode2038w[3], w_anode2028w[3], w_anode2018w[3], w_anode2008w[3], w_anode1998w[3], w_anode1988w[3], w_anode1978w[3], w_anode1967w[3]}, {w_anode1945w[3], w_anode1935w[3], w_anode1925w[3], w_anode1915w[3], w_anode1905w[3], w_anode1895w[3], w_anode1885w[3], w_anode1874w[3]}, {w_anode1852w[3], w_anode1842w[3], w_anode1832w[3], w_anode1822w[3], w_anode1812w[3], w_anode1802w[3], w_anode1792w[3], w_anode1781w[3]}, {w_anode1758w[3], w_anode1748w[3], w_anode1738w[3], w_anode1728w[3], w_anode1718w[3], w_anode1708w[3], w_anode1698w[3], w_anode1681w[3]}},
w_anode1006w = {(w_anode1006w[2] & w_data910w[2]), (w_anode1006w[1] & w_data910w[1]), (w_anode1006w[0] & w_data910w[0]), w_anode912w[3]},
w_anode1018w = {(w_anode1018w[2] & (~ data_wire[5])), (w_anode1018w[1] & (~ data_wire[4])), (w_anode1018w[0] & data_wire[3]), enable_wire1},
w_anode1029w = {(w_anode1029w[2] & (~ w_data910w[2])), (w_anode1029w[1] & (~ w_data910w[1])), (w_anode1029w[0] & (~ w_data910w[0])), w_anode1018w[3]},
w_anode1040w = {(w_anode1040w[2] & (~ w_data910w[2])), (w_anode1040w[1] & (~ w_data910w[1])), (w_anode1040w[0] & w_data910w[0]), w_anode1018w[3]},
w_anode1050w = {(w_anode1050w[2] & (~ w_data910w[2])), (w_anode1050w[1] & w_data910w[1]), (w_anode1050w[0] & (~ w_data910w[0])), w_anode1018w[3]},
w_anode1060w = {(w_anode1060w[2] & (~ w_data910w[2])), (w_anode1060w[1] & w_data910w[1]), (w_anode1060w[0] & w_data910w[0]), w_anode1018w[3]},
w_anode1070w = {(w_anode1070w[2] & w_data910w[2]), (w_anode1070w[1] & (~ w_data910w[1])), (w_anode1070w[0] & (~ w_data910w[0])), w_anode1018w[3]},
w_anode1080w = {(w_anode1080w[2] & w_data910w[2]), (w_anode1080w[1] & (~ w_data910w[1])), (w_anode1080w[0] & w_data910w[0]), w_anode1018w[3]},
w_anode1090w = {(w_anode1090w[2] & w_data910w[2]), (w_anode1090w[1] & w_data910w[1]), (w_anode1090w[0] & (~ w_data910w[0])), w_anode1018w[3]},
w_anode1100w = {(w_anode1100w[2] & w_data910w[2]), (w_anode1100w[1] & w_data910w[1]), (w_anode1100w[0] & w_data910w[0]), w_anode1018w[3]},
w_anode1111w = {(w_anode1111w[2] & (~ data_wire[5])), (w_anode1111w[1] & data_wire[4]), (w_anode1111w[0] & (~ data_wire[3])), enable_wire1},
w_anode1122w = {(w_anode1122w[2] & (~ w_data910w[2])), (w_anode1122w[1] & (~ w_data910w[1])), (w_anode1122w[0] & (~ w_data910w[0])), w_anode1111w[3]},
w_anode1133w = {(w_anode1133w[2] & (~ w_data910w[2])), (w_anode1133w[1] & (~ w_data910w[1])), (w_anode1133w[0] & w_data910w[0]), w_anode1111w[3]},
w_anode1143w = {(w_anode1143w[2] & (~ w_data910w[2])), (w_anode1143w[1] & w_data910w[1]), (w_anode1143w[0] & (~ w_data910w[0])), w_anode1111w[3]},
w_anode1153w = {(w_anode1153w[2] & (~ w_data910w[2])), (w_anode1153w[1] & w_data910w[1]), (w_anode1153w[0] & w_data910w[0]), w_anode1111w[3]},
w_anode1163w = {(w_anode1163w[2] & w_data910w[2]), (w_anode1163w[1] & (~ w_data910w[1])), (w_anode1163w[0] & (~ w_data910w[0])), w_anode1111w[3]},
w_anode1173w = {(w_anode1173w[2] & w_data910w[2]), (w_anode1173w[1] & (~ w_data910w[1])), (w_anode1173w[0] & w_data910w[0]), w_anode1111w[3]},
w_anode1183w = {(w_anode1183w[2] & w_data910w[2]), (w_anode1183w[1] & w_data910w[1]), (w_anode1183w[0] & (~ w_data910w[0])), w_anode1111w[3]},
w_anode1193w = {(w_anode1193w[2] & w_data910w[2]), (w_anode1193w[1] & w_data910w[1]), (w_anode1193w[0] & w_data910w[0]), w_anode1111w[3]},
w_anode1204w = {(w_anode1204w[2] & (~ data_wire[5])), (w_anode1204w[1] & data_wire[4]), (w_anode1204w[0] & data_wire[3]), enable_wire1},
w_anode1215w = {(w_anode1215w[2] & (~ w_data910w[2])), (w_anode1215w[1] & (~ w_data910w[1])), (w_anode1215w[0] & (~ w_data910w[0])), w_anode1204w[3]},
w_anode1226w = {(w_anode1226w[2] & (~ w_data910w[2])), (w_anode1226w[1] & (~ w_data910w[1])), (w_anode1226w[0] & w_data910w[0]), w_anode1204w[3]},
w_anode1236w = {(w_anode1236w[2] & (~ w_data910w[2])), (w_anode1236w[1] & w_data910w[1]), (w_anode1236w[0] & (~ w_data910w[0])), w_anode1204w[3]},
w_anode1246w = {(w_anode1246w[2] & (~ w_data910w[2])), (w_anode1246w[1] & w_data910w[1]), (w_anode1246w[0] & w_data910w[0]), w_anode1204w[3]},
w_anode1256w = {(w_anode1256w[2] & w_data910w[2]), (w_anode1256w[1] & (~ w_data910w[1])), (w_anode1256w[0] & (~ w_data910w[0])), w_anode1204w[3]},
w_anode1266w = {(w_anode1266w[2] & w_data910w[2]), (w_anode1266w[1] & (~ w_data910w[1])), (w_anode1266w[0] & w_data910w[0]), w_anode1204w[3]},
w_anode1276w = {(w_anode1276w[2] & w_data910w[2]), (w_anode1276w[1] & w_data910w[1]), (w_anode1276w[0] & (~ w_data910w[0])), w_anode1204w[3]},
w_anode1286w = {(w_anode1286w[2] & w_data910w[2]), (w_anode1286w[1] & w_data910w[1]), (w_anode1286w[0] & w_data910w[0]), w_anode1204w[3]},
w_anode1297w = {(w_anode1297w[2] & data_wire[5]), (w_anode1297w[1] & (~ data_wire[4])), (w_anode1297w[0] & (~ data_wire[3])), enable_wire1},
w_anode1308w = {(w_anode1308w[2] & (~ w_data910w[2])), (w_anode1308w[1] & (~ w_data910w[1])), (w_anode1308w[0] & (~ w_data910w[0])), w_anode1297w[3]},
w_anode1319w = {(w_anode1319w[2] & (~ w_data910w[2])), (w_anode1319w[1] & (~ w_data910w[1])), (w_anode1319w[0] & w_data910w[0]), w_anode1297w[3]},
w_anode1329w = {(w_anode1329w[2] & (~ w_data910w[2])), (w_anode1329w[1] & w_data910w[1]), (w_anode1329w[0] & (~ w_data910w[0])), w_anode1297w[3]},
w_anode1339w = {(w_anode1339w[2] & (~ w_data910w[2])), (w_anode1339w[1] & w_data910w[1]), (w_anode1339w[0] & w_data910w[0]), w_anode1297w[3]},
w_anode1349w = {(w_anode1349w[2] & w_data910w[2]), (w_anode1349w[1] & (~ w_data910w[1])), (w_anode1349w[0] & (~ w_data910w[0])), w_anode1297w[3]},
w_anode1359w = {(w_anode1359w[2] & w_data910w[2]), (w_anode1359w[1] & (~ w_data910w[1])), (w_anode1359w[0] & w_data910w[0]), w_anode1297w[3]},
w_anode1369w = {(w_anode1369w[2] & w_data910w[2]), (w_anode1369w[1] & w_data910w[1]), (w_anode1369w[0] & (~ w_data910w[0])), w_anode1297w[3]},
w_anode1379w = {(w_anode1379w[2] & w_data910w[2]), (w_anode1379w[1] & w_data910w[1]), (w_anode1379w[0] & w_data910w[0]), w_anode1297w[3]},
w_anode1390w = {(w_anode1390w[2] & data_wire[5]), (w_anode1390w[1] & (~ data_wire[4])), (w_anode1390w[0] & data_wire[3]), enable_wire1},
w_anode1401w = {(w_anode1401w[2] & (~ w_data910w[2])), (w_anode1401w[1] & (~ w_data910w[1])), (w_anode1401w[0] & (~ w_data910w[0])), w_anode1390w[3]},
w_anode1412w = {(w_anode1412w[2] & (~ w_data910w[2])), (w_anode1412w[1] & (~ w_data910w[1])), (w_anode1412w[0] & w_data910w[0]), w_anode1390w[3]},
w_anode1422w = {(w_anode1422w[2] & (~ w_data910w[2])), (w_anode1422w[1] & w_data910w[1]), (w_anode1422w[0] & (~ w_data910w[0])), w_anode1390w[3]},
w_anode1432w = {(w_anode1432w[2] & (~ w_data910w[2])), (w_anode1432w[1] & w_data910w[1]), (w_anode1432w[0] & w_data910w[0]), w_anode1390w[3]},
w_anode1442w = {(w_anode1442w[2] & w_data910w[2]), (w_anode1442w[1] & (~ w_data910w[1])), (w_anode1442w[0] & (~ w_data910w[0])), w_anode1390w[3]},
w_anode1452w = {(w_anode1452w[2] & w_data910w[2]), (w_anode1452w[1] & (~ w_data910w[1])), (w_anode1452w[0] & w_data910w[0]), w_anode1390w[3]},
w_anode1462w = {(w_anode1462w[2] & w_data910w[2]), (w_anode1462w[1] & w_data910w[1]), (w_anode1462w[0] & (~ w_data910w[0])), w_anode1390w[3]},
w_anode1472w = {(w_anode1472w[2] & w_data910w[2]), (w_anode1472w[1] & w_data910w[1]), (w_anode1472w[0] & w_data910w[0]), w_anode1390w[3]},
w_anode1483w = {(w_anode1483w[2] & data_wire[5]), (w_anode1483w[1] & data_wire[4]), (w_anode1483w[0] & (~ data_wire[3])), enable_wire1},
w_anode1494w = {(w_anode1494w[2] & (~ w_data910w[2])), (w_anode1494w[1] & (~ w_data910w[1])), (w_anode1494w[0] & (~ w_data910w[0])), w_anode1483w[3]},
w_anode1505w = {(w_anode1505w[2] & (~ w_data910w[2])), (w_anode1505w[1] & (~ w_data910w[1])), (w_anode1505w[0] & w_data910w[0]), w_anode1483w[3]},
w_anode1515w = {(w_anode1515w[2] & (~ w_data910w[2])), (w_anode1515w[1] & w_data910w[1]), (w_anode1515w[0] & (~ w_data910w[0])), w_anode1483w[3]},
w_anode1525w = {(w_anode1525w[2] & (~ w_data910w[2])), (w_anode1525w[1] & w_data910w[1]), (w_anode1525w[0] & w_data910w[0]), w_anode1483w[3]},
w_anode1535w = {(w_anode1535w[2] & w_data910w[2]), (w_anode1535w[1] & (~ w_data910w[1])), (w_anode1535w[0] & (~ w_data910w[0])), w_anode1483w[3]},
w_anode1545w = {(w_anode1545w[2] & w_data910w[2]), (w_anode1545w[1] & (~ w_data910w[1])), (w_anode1545w[0] & w_data910w[0]), w_anode1483w[3]},
w_anode1555w = {(w_anode1555w[2] & w_data910w[2]), (w_anode1555w[1] & w_data910w[1]), (w_anode1555w[0] & (~ w_data910w[0])), w_anode1483w[3]},
w_anode1565w = {(w_anode1565w[2] & w_data910w[2]), (w_anode1565w[1] & w_data910w[1]), (w_anode1565w[0] & w_data910w[0]), w_anode1483w[3]},
w_anode1576w = {(w_anode1576w[2] & data_wire[5]), (w_anode1576w[1] & data_wire[4]), (w_anode1576w[0] & data_wire[3]), enable_wire1},
w_anode1587w = {(w_anode1587w[2] & (~ w_data910w[2])), (w_anode1587w[1] & (~ w_data910w[1])), (w_anode1587w[0] & (~ w_data910w[0])), w_anode1576w[3]},
w_anode1598w = {(w_anode1598w[2] & (~ w_data910w[2])), (w_anode1598w[1] & (~ w_data910w[1])), (w_anode1598w[0] & w_data910w[0]), w_anode1576w[3]},
w_anode1608w = {(w_anode1608w[2] & (~ w_data910w[2])), (w_anode1608w[1] & w_data910w[1]), (w_anode1608w[0] & (~ w_data910w[0])), w_anode1576w[3]},
w_anode1618w = {(w_anode1618w[2] & (~ w_data910w[2])), (w_anode1618w[1] & w_data910w[1]), (w_anode1618w[0] & w_data910w[0]), w_anode1576w[3]},
w_anode1628w = {(w_anode1628w[2] & w_data910w[2]), (w_anode1628w[1] & (~ w_data910w[1])), (w_anode1628w[0] & (~ w_data910w[0])), w_anode1576w[3]},
w_anode1638w = {(w_anode1638w[2] & w_data910w[2]), (w_anode1638w[1] & (~ w_data910w[1])), (w_anode1638w[0] & w_data910w[0]), w_anode1576w[3]},
w_anode1648w = {(w_anode1648w[2] & w_data910w[2]), (w_anode1648w[1] & w_data910w[1]), (w_anode1648w[0] & (~ w_data910w[0])), w_anode1576w[3]},
w_anode1658w = {(w_anode1658w[2] & w_data910w[2]), (w_anode1658w[1] & w_data910w[1]), (w_anode1658w[0] & w_data910w[0]), w_anode1576w[3]},
w_anode1670w = {(w_anode1670w[2] & (~ data_wire[5])), (w_anode1670w[1] & (~ data_wire[4])), (w_anode1670w[0] & (~ data_wire[3])), enable_wire2},
w_anode1681w = {(w_anode1681w[2] & (~ w_data1669w[2])), (w_anode1681w[1] & (~ w_data1669w[1])), (w_anode1681w[0] & (~ w_data1669w[0])), w_anode1670w[3]},
w_anode1698w = {(w_anode1698w[2] & (~ w_data1669w[2])), (w_anode1698w[1] & (~ w_data1669w[1])), (w_anode1698w[0] & w_data1669w[0]), w_anode1670w[3]},
w_anode1708w = {(w_anode1708w[2] & (~ w_data1669w[2])), (w_anode1708w[1] & w_data1669w[1]), (w_anode1708w[0] & (~ w_data1669w[0])), w_anode1670w[3]},
w_anode1718w = {(w_anode1718w[2] & (~ w_data1669w[2])), (w_anode1718w[1] & w_data1669w[1]), (w_anode1718w[0] & w_data1669w[0]), w_anode1670w[3]},
w_anode1728w = {(w_anode1728w[2] & w_data1669w[2]), (w_anode1728w[1] & (~ w_data1669w[1])), (w_anode1728w[0] & (~ w_data1669w[0])), w_anode1670w[3]},
w_anode1738w = {(w_anode1738w[2] & w_data1669w[2]), (w_anode1738w[1] & (~ w_data1669w[1])), (w_anode1738w[0] & w_data1669w[0]), w_anode1670w[3]},
w_anode1748w = {(w_anode1748w[2] & w_data1669w[2]), (w_anode1748w[1] & w_data1669w[1]), (w_anode1748w[0] & (~ w_data1669w[0])), w_anode1670w[3]},
w_anode1758w = {(w_anode1758w[2] & w_data1669w[2]), (w_anode1758w[1] & w_data1669w[1]), (w_anode1758w[0] & w_data1669w[0]), w_anode1670w[3]},
w_anode1770w = {(w_anode1770w[2] & (~ data_wire[5])), (w_anode1770w[1] & (~ data_wire[4])), (w_anode1770w[0] & data_wire[3]), enable_wire2},
w_anode1781w = {(w_anode1781w[2] & (~ w_data1669w[2])), (w_anode1781w[1] & (~ w_data1669w[1])), (w_anode1781w[0] & (~ w_data1669w[0])), w_anode1770w[3]},
w_anode1792w = {(w_anode1792w[2] & (~ w_data1669w[2])), (w_anode1792w[1] & (~ w_data1669w[1])), (w_anode1792w[0] & w_data1669w[0]), w_anode1770w[3]},
w_anode1802w = {(w_anode1802w[2] & (~ w_data1669w[2])), (w_anode1802w[1] & w_data1669w[1]), (w_anode1802w[0] & (~ w_data1669w[0])), w_anode1770w[3]},
w_anode1812w = {(w_anode1812w[2] & (~ w_data1669w[2])), (w_anode1812w[1] & w_data1669w[1]), (w_anode1812w[0] & w_data1669w[0]), w_anode1770w[3]},
w_anode1822w = {(w_anode1822w[2] & w_data1669w[2]), (w_anode1822w[1] & (~ w_data1669w[1])), (w_anode1822w[0] & (~ w_data1669w[0])), w_anode1770w[3]},
w_anode1832w = {(w_anode1832w[2] & w_data1669w[2]), (w_anode1832w[1] & (~ w_data1669w[1])), (w_anode1832w[0] & w_data1669w[0]), w_anode1770w[3]},
w_anode1842w = {(w_anode1842w[2] & w_data1669w[2]), (w_anode1842w[1] & w_data1669w[1]), (w_anode1842w[0] & (~ w_data1669w[0])), w_anode1770w[3]},
w_anode1852w = {(w_anode1852w[2] & w_data1669w[2]), (w_anode1852w[1] & w_data1669w[1]), (w_anode1852w[0] & w_data1669w[0]), w_anode1770w[3]},
w_anode1863w = {(w_anode1863w[2] & (~ data_wire[5])), (w_anode1863w[1] & data_wire[4]), (w_anode1863w[0] & (~ data_wire[3])), enable_wire2},
w_anode1874w = {(w_anode1874w[2] & (~ w_data1669w[2])), (w_anode1874w[1] & (~ w_data1669w[1])), (w_anode1874w[0] & (~ w_data1669w[0])), w_anode1863w[3]},
w_anode1885w = {(w_anode1885w[2] & (~ w_data1669w[2])), (w_anode1885w[1] & (~ w_data1669w[1])), (w_anode1885w[0] & w_data1669w[0]), w_anode1863w[3]},
w_anode1895w = {(w_anode1895w[2] & (~ w_data1669w[2])), (w_anode1895w[1] & w_data1669w[1]), (w_anode1895w[0] & (~ w_data1669w[0])), w_anode1863w[3]},
w_anode1905w = {(w_anode1905w[2] & (~ w_data1669w[2])), (w_anode1905w[1] & w_data1669w[1]), (w_anode1905w[0] & w_data1669w[0]), w_anode1863w[3]},
w_anode1915w = {(w_anode1915w[2] & w_data1669w[2]), (w_anode1915w[1] & (~ w_data1669w[1])), (w_anode1915w[0] & (~ w_data1669w[0])), w_anode1863w[3]},
w_anode1925w = {(w_anode1925w[2] & w_data1669w[2]), (w_anode1925w[1] & (~ w_data1669w[1])), (w_anode1925w[0] & w_data1669w[0]), w_anode1863w[3]},
w_anode1935w = {(w_anode1935w[2] & w_data1669w[2]), (w_anode1935w[1] & w_data1669w[1]), (w_anode1935w[0] & (~ w_data1669w[0])), w_anode1863w[3]},
w_anode1945w = {(w_anode1945w[2] & w_data1669w[2]), (w_anode1945w[1] & w_data1669w[1]), (w_anode1945w[0] & w_data1669w[0]), w_anode1863w[3]},
w_anode1956w = {(w_anode1956w[2] & (~ data_wire[5])), (w_anode1956w[1] & data_wire[4]), (w_anode1956w[0] & data_wire[3]), enable_wire2},
w_anode1967w = {(w_anode1967w[2] & (~ w_data1669w[2])), (w_anode1967w[1] & (~ w_data1669w[1])), (w_anode1967w[0] & (~ w_data1669w[0])), w_anode1956w[3]},
w_anode1978w = {(w_anode1978w[2] & (~ w_data1669w[2])), (w_anode1978w[1] & (~ w_data1669w[1])), (w_anode1978w[0] & w_data1669w[0]), w_anode1956w[3]},
w_anode1988w = {(w_anode1988w[2] & (~ w_data1669w[2])), (w_anode1988w[1] & w_data1669w[1]), (w_anode1988w[0] & (~ w_data1669w[0])), w_anode1956w[3]},
w_anode1998w = {(w_anode1998w[2] & (~ w_data1669w[2])), (w_anode1998w[1] & w_data1669w[1]), (w_anode1998w[0] & w_data1669w[0]), w_anode1956w[3]},
w_anode2008w = {(w_anode2008w[2] & w_data1669w[2]), (w_anode2008w[1] & (~ w_data1669w[1])), (w_anode2008w[0] & (~ w_data1669w[0])), w_anode1956w[3]},
w_anode2018w = {(w_anode2018w[2] & w_data1669w[2]), (w_anode2018w[1] & (~ w_data1669w[1])), (w_anode2018w[0] & w_data1669w[0]), w_anode1956w[3]},
w_anode2028w = {(w_anode2028w[2] & w_data1669w[2]), (w_anode2028w[1] & w_data1669w[1]), (w_anode2028w[0] & (~ w_data1669w[0])), w_anode1956w[3]},
w_anode2038w = {(w_anode2038w[2] & w_data1669w[2]), (w_anode2038w[1] & w_data1669w[1]), (w_anode2038w[0] & w_data1669w[0]), w_anode1956w[3]},
w_anode2049w = {(w_anode2049w[2] & data_wire[5]), (w_anode2049w[1] & (~ data_wire[4])), (w_anode2049w[0] & (~ data_wire[3])), enable_wire2},
w_anode2060w = {(w_anode2060w[2] & (~ w_data1669w[2])), (w_anode2060w[1] & (~ w_data1669w[1])), (w_anode2060w[0] & (~ w_data1669w[0])), w_anode2049w[3]},
w_anode2071w = {(w_anode2071w[2] & (~ w_data1669w[2])), (w_anode2071w[1] & (~ w_data1669w[1])), (w_anode2071w[0] & w_data1669w[0]), w_anode2049w[3]},
w_anode2081w = {(w_anode2081w[2] & (~ w_data1669w[2])), (w_anode2081w[1] & w_data1669w[1]), (w_anode2081w[0] & (~ w_data1669w[0])), w_anode2049w[3]},
w_anode2091w = {(w_anode2091w[2] & (~ w_data1669w[2])), (w_anode2091w[1] & w_data1669w[1]), (w_anode2091w[0] & w_data1669w[0]), w_anode2049w[3]},
w_anode2101w = {(w_anode2101w[2] & w_data1669w[2]), (w_anode2101w[1] & (~ w_data1669w[1])), (w_anode2101w[0] & (~ w_data1669w[0])), w_anode2049w[3]},
w_anode2111w = {(w_anode2111w[2] & w_data1669w[2]), (w_anode2111w[1] & (~ w_data1669w[1])), (w_anode2111w[0] & w_data1669w[0]), w_anode2049w[3]},
w_anode2121w = {(w_anode2121w[2] & w_data1669w[2]), (w_anode2121w[1] & w_data1669w[1]), (w_anode2121w[0] & (~ w_data1669w[0])), w_anode2049w[3]},
w_anode2131w = {(w_anode2131w[2] & w_data1669w[2]), (w_anode2131w[1] & w_data1669w[1]), (w_anode2131w[0] & w_data1669w[0]), w_anode2049w[3]},
w_anode2142w = {(w_anode2142w[2] & data_wire[5]), (w_anode2142w[1] & (~ data_wire[4])), (w_anode2142w[0] & data_wire[3]), enable_wire2},
w_anode2153w = {(w_anode2153w[2] & (~ w_data1669w[2])), (w_anode2153w[1] & (~ w_data1669w[1])), (w_anode2153w[0] & (~ w_data1669w[0])), w_anode2142w[3]},
w_anode2164w = {(w_anode2164w[2] & (~ w_data1669w[2])), (w_anode2164w[1] & (~ w_data1669w[1])), (w_anode2164w[0] & w_data1669w[0]), w_anode2142w[3]},
w_anode2174w = {(w_anode2174w[2] & (~ w_data1669w[2])), (w_anode2174w[1] & w_data1669w[1]), (w_anode2174w[0] & (~ w_data1669w[0])), w_anode2142w[3]},
w_anode2184w = {(w_anode2184w[2] & (~ w_data1669w[2])), (w_anode2184w[1] & w_data1669w[1]), (w_anode2184w[0] & w_data1669w[0]), w_anode2142w[3]},
w_anode2194w = {(w_anode2194w[2] & w_data1669w[2]), (w_anode2194w[1] & (~ w_data1669w[1])), (w_anode2194w[0] & (~ w_data1669w[0])), w_anode2142w[3]},
w_anode2204w = {(w_anode2204w[2] & w_data1669w[2]), (w_anode2204w[1] & (~ w_data1669w[1])), (w_anode2204w[0] & w_data1669w[0]), w_anode2142w[3]},
w_anode2214w = {(w_anode2214w[2] & w_data1669w[2]), (w_anode2214w[1] & w_data1669w[1]), (w_anode2214w[0] & (~ w_data1669w[0])), w_anode2142w[3]},
w_anode2224w = {(w_anode2224w[2] & w_data1669w[2]), (w_anode2224w[1] & w_data1669w[1]), (w_anode2224w[0] & w_data1669w[0]), w_anode2142w[3]},
w_anode2235w = {(w_anode2235w[2] & data_wire[5]), (w_anode2235w[1] & data_wire[4]), (w_anode2235w[0] & (~ data_wire[3])), enable_wire2},
w_anode2246w = {(w_anode2246w[2] & (~ w_data1669w[2])), (w_anode2246w[1] & (~ w_data1669w[1])), (w_anode2246w[0] & (~ w_data1669w[0])), w_anode2235w[3]},
w_anode2257w = {(w_anode2257w[2] & (~ w_data1669w[2])), (w_anode2257w[1] & (~ w_data1669w[1])), (w_anode2257w[0] & w_data1669w[0]), w_anode2235w[3]},
w_anode2267w = {(w_anode2267w[2] & (~ w_data1669w[2])), (w_anode2267w[1] & w_data1669w[1]), (w_anode2267w[0] & (~ w_data1669w[0])), w_anode2235w[3]},
w_anode2277w = {(w_anode2277w[2] & (~ w_data1669w[2])), (w_anode2277w[1] & w_data1669w[1]), (w_anode2277w[0] & w_data1669w[0]), w_anode2235w[3]},
w_anode2287w = {(w_anode2287w[2] & w_data1669w[2]), (w_anode2287w[1] & (~ w_data1669w[1])), (w_anode2287w[0] & (~ w_data1669w[0])), w_anode2235w[3]},
w_anode2297w = {(w_anode2297w[2] & w_data1669w[2]), (w_anode2297w[1] & (~ w_data1669w[1])), (w_anode2297w[0] & w_data1669w[0]), w_anode2235w[3]},
w_anode2307w = {(w_anode2307w[2] & w_data1669w[2]), (w_anode2307w[1] & w_data1669w[1]), (w_anode2307w[0] & (~ w_data1669w[0])), w_anode2235w[3]},
w_anode2317w = {(w_anode2317w[2] & w_data1669w[2]), (w_anode2317w[1] & w_data1669w[1]), (w_anode2317w[0] & w_data1669w[0]), w_anode2235w[3]},
w_anode2328w = {(w_anode2328w[2] & data_wire[5]), (w_anode2328w[1] & data_wire[4]), (w_anode2328w[0] & data_wire[3]), enable_wire2},
w_anode2339w = {(w_anode2339w[2] & (~ w_data1669w[2])), (w_anode2339w[1] & (~ w_data1669w[1])), (w_anode2339w[0] & (~ w_data1669w[0])), w_anode2328w[3]},
w_anode2350w = {(w_anode2350w[2] & (~ w_data1669w[2])), (w_anode2350w[1] & (~ w_data1669w[1])), (w_anode2350w[0] & w_data1669w[0]), w_anode2328w[3]},
w_anode2360w = {(w_anode2360w[2] & (~ w_data1669w[2])), (w_anode2360w[1] & w_data1669w[1]), (w_anode2360w[0] & (~ w_data1669w[0])), w_anode2328w[3]},
w_anode2370w = {(w_anode2370w[2] & (~ w_data1669w[2])), (w_anode2370w[1] & w_data1669w[1]), (w_anode2370w[0] & w_data1669w[0]), w_anode2328w[3]},
w_anode2380w = {(w_anode2380w[2] & w_data1669w[2]), (w_anode2380w[1] & (~ w_data1669w[1])), (w_anode2380w[0] & (~ w_data1669w[0])), w_anode2328w[3]},
w_anode2390w = {(w_anode2390w[2] & w_data1669w[2]), (w_anode2390w[1] & (~ w_data1669w[1])), (w_anode2390w[0] & w_data1669w[0]), w_anode2328w[3]},
w_anode2400w = {(w_anode2400w[2] & w_data1669w[2]), (w_anode2400w[1] & w_data1669w[1]), (w_anode2400w[0] & (~ w_data1669w[0])), w_anode2328w[3]},
w_anode2410w = {(w_anode2410w[2] & w_data1669w[2]), (w_anode2410w[1] & w_data1669w[1]), (w_anode2410w[0] & w_data1669w[0]), w_anode2328w[3]},
w_anode912w = {(w_anode912w[2] & (~ data_wire[5])), (w_anode912w[1] & (~ data_wire[4])), (w_anode912w[0] & (~ data_wire[3])), enable_wire1},
w_anode929w = {(w_anode929w[2] & (~ w_data910w[2])), (w_anode929w[1] & (~ w_data910w[1])), (w_anode929w[0] & (~ w_data910w[0])), w_anode912w[3]},
w_anode946w = {(w_anode946w[2] & (~ w_data910w[2])), (w_anode946w[1] & (~ w_data910w[1])), (w_anode946w[0] & w_data910w[0]), w_anode912w[3]},
w_anode956w = {(w_anode956w[2] & (~ w_data910w[2])), (w_anode956w[1] & w_data910w[1]), (w_anode956w[0] & (~ w_data910w[0])), w_anode912w[3]},
w_anode966w = {(w_anode966w[2] & (~ w_data910w[2])), (w_anode966w[1] & w_data910w[1]), (w_anode966w[0] & w_data910w[0]), w_anode912w[3]},
w_anode976w = {(w_anode976w[2] & w_data910w[2]), (w_anode976w[1] & (~ w_data910w[1])), (w_anode976w[0] & (~ w_data910w[0])), w_anode912w[3]},
w_anode986w = {(w_anode986w[2] & w_data910w[2]), (w_anode986w[1] & (~ w_data910w[1])), (w_anode986w[0] & w_data910w[0]), w_anode912w[3]},
w_anode996w = {(w_anode996w[2] & w_data910w[2]), (w_anode996w[1] & w_data910w[1]), (w_anode996w[0] & (~ w_data910w[0])), w_anode912w[3]},
w_data1669w = data_wire[2:0],
w_data910w = data_wire[2:0];
endmodule //alt_mem_ddrx_ecc_decoder_64_decode
//synthesis_resources = lut 144 mux21 64
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module alt_mem_ddrx_ecc_decoder_64_altecc_decoder
(
data,
err_corrected,
err_detected,
err_fatal,
err_sbe,
q) /* synthesis synthesis_clearbox=1 */;
input [71:0] data;
output err_corrected;
output err_detected;
output err_fatal;
output err_sbe;
output [63:0] q;
wire [127:0] wire_error_bit_decoder_eq;
wire wire_mux21_0_dataout;
wire wire_mux21_1_dataout;
wire wire_mux21_10_dataout;
wire wire_mux21_11_dataout;
wire wire_mux21_12_dataout;
wire wire_mux21_13_dataout;
wire wire_mux21_14_dataout;
wire wire_mux21_15_dataout;
wire wire_mux21_16_dataout;
wire wire_mux21_17_dataout;
wire wire_mux21_18_dataout;
wire wire_mux21_19_dataout;
wire wire_mux21_2_dataout;
wire wire_mux21_20_dataout;
wire wire_mux21_21_dataout;
wire wire_mux21_22_dataout;
wire wire_mux21_23_dataout;
wire wire_mux21_24_dataout;
wire wire_mux21_25_dataout;
wire wire_mux21_26_dataout;
wire wire_mux21_27_dataout;
wire wire_mux21_28_dataout;
wire wire_mux21_29_dataout;
wire wire_mux21_3_dataout;
wire wire_mux21_30_dataout;
wire wire_mux21_31_dataout;
wire wire_mux21_32_dataout;
wire wire_mux21_33_dataout;
wire wire_mux21_34_dataout;
wire wire_mux21_35_dataout;
wire wire_mux21_36_dataout;
wire wire_mux21_37_dataout;
wire wire_mux21_38_dataout;
wire wire_mux21_39_dataout;
wire wire_mux21_4_dataout;
wire wire_mux21_40_dataout;
wire wire_mux21_41_dataout;
wire wire_mux21_42_dataout;
wire wire_mux21_43_dataout;
wire wire_mux21_44_dataout;
wire wire_mux21_45_dataout;
wire wire_mux21_46_dataout;
wire wire_mux21_47_dataout;
wire wire_mux21_48_dataout;
wire wire_mux21_49_dataout;
wire wire_mux21_5_dataout;
wire wire_mux21_50_dataout;
wire wire_mux21_51_dataout;
wire wire_mux21_52_dataout;
wire wire_mux21_53_dataout;
wire wire_mux21_54_dataout;
wire wire_mux21_55_dataout;
wire wire_mux21_56_dataout;
wire wire_mux21_57_dataout;
wire wire_mux21_58_dataout;
wire wire_mux21_59_dataout;
wire wire_mux21_6_dataout;
wire wire_mux21_60_dataout;
wire wire_mux21_61_dataout;
wire wire_mux21_62_dataout;
wire wire_mux21_63_dataout;
wire wire_mux21_7_dataout;
wire wire_mux21_8_dataout;
wire wire_mux21_9_dataout;
wire data_bit;
wire [63:0] data_t;
wire [71:0] data_wire;
wire [127:0] decode_output;
wire err_corrected_wire;
wire err_detected_wire;
wire err_fatal_wire;
wire [35:0] parity_01_wire;
wire [17:0] parity_02_wire;
wire [8:0] parity_03_wire;
wire [3:0] parity_04_wire;
wire [1:0] parity_05_wire;
wire [30:0] parity_06_wire;
wire [6:0] parity_07_wire;
wire parity_bit;
wire [70:0] parity_final_wire;
wire [6:0] parity_t;
wire [63:0] q_wire;
wire syn_bit;
wire syn_e;
wire [5:0] syn_t;
wire [7:0] syndrome;
alt_mem_ddrx_ecc_decoder_64_decode error_bit_decoder
(
.data(syndrome[6:0]),
.eq(wire_error_bit_decoder_eq));
assign wire_mux21_0_dataout = (syndrome[7] == 1'b1) ? (decode_output[3] ^ data_wire[0]) : data_wire[0];
assign wire_mux21_1_dataout = (syndrome[7] == 1'b1) ? (decode_output[5] ^ data_wire[1]) : data_wire[1];
assign wire_mux21_10_dataout = (syndrome[7] == 1'b1) ? (decode_output[15] ^ data_wire[10]) : data_wire[10];
assign wire_mux21_11_dataout = (syndrome[7] == 1'b1) ? (decode_output[17] ^ data_wire[11]) : data_wire[11];
assign wire_mux21_12_dataout = (syndrome[7] == 1'b1) ? (decode_output[18] ^ data_wire[12]) : data_wire[12];
assign wire_mux21_13_dataout = (syndrome[7] == 1'b1) ? (decode_output[19] ^ data_wire[13]) : data_wire[13];
assign wire_mux21_14_dataout = (syndrome[7] == 1'b1) ? (decode_output[20] ^ data_wire[14]) : data_wire[14];
assign wire_mux21_15_dataout = (syndrome[7] == 1'b1) ? (decode_output[21] ^ data_wire[15]) : data_wire[15];
assign wire_mux21_16_dataout = (syndrome[7] == 1'b1) ? (decode_output[22] ^ data_wire[16]) : data_wire[16];
assign wire_mux21_17_dataout = (syndrome[7] == 1'b1) ? (decode_output[23] ^ data_wire[17]) : data_wire[17];
assign wire_mux21_18_dataout = (syndrome[7] == 1'b1) ? (decode_output[24] ^ data_wire[18]) : data_wire[18];
assign wire_mux21_19_dataout = (syndrome[7] == 1'b1) ? (decode_output[25] ^ data_wire[19]) : data_wire[19];
assign wire_mux21_2_dataout = (syndrome[7] == 1'b1) ? (decode_output[6] ^ data_wire[2]) : data_wire[2];
assign wire_mux21_20_dataout = (syndrome[7] == 1'b1) ? (decode_output[26] ^ data_wire[20]) : data_wire[20];
assign wire_mux21_21_dataout = (syndrome[7] == 1'b1) ? (decode_output[27] ^ data_wire[21]) : data_wire[21];
assign wire_mux21_22_dataout = (syndrome[7] == 1'b1) ? (decode_output[28] ^ data_wire[22]) : data_wire[22];
assign wire_mux21_23_dataout = (syndrome[7] == 1'b1) ? (decode_output[29] ^ data_wire[23]) : data_wire[23];
assign wire_mux21_24_dataout = (syndrome[7] == 1'b1) ? (decode_output[30] ^ data_wire[24]) : data_wire[24];
assign wire_mux21_25_dataout = (syndrome[7] == 1'b1) ? (decode_output[31] ^ data_wire[25]) : data_wire[25];
assign wire_mux21_26_dataout = (syndrome[7] == 1'b1) ? (decode_output[33] ^ data_wire[26]) : data_wire[26];
assign wire_mux21_27_dataout = (syndrome[7] == 1'b1) ? (decode_output[34] ^ data_wire[27]) : data_wire[27];
assign wire_mux21_28_dataout = (syndrome[7] == 1'b1) ? (decode_output[35] ^ data_wire[28]) : data_wire[28];
assign wire_mux21_29_dataout = (syndrome[7] == 1'b1) ? (decode_output[36] ^ data_wire[29]) : data_wire[29];
assign wire_mux21_3_dataout = (syndrome[7] == 1'b1) ? (decode_output[7] ^ data_wire[3]) : data_wire[3];
assign wire_mux21_30_dataout = (syndrome[7] == 1'b1) ? (decode_output[37] ^ data_wire[30]) : data_wire[30];
assign wire_mux21_31_dataout = (syndrome[7] == 1'b1) ? (decode_output[38] ^ data_wire[31]) : data_wire[31];
assign wire_mux21_32_dataout = (syndrome[7] == 1'b1) ? (decode_output[39] ^ data_wire[32]) : data_wire[32];
assign wire_mux21_33_dataout = (syndrome[7] == 1'b1) ? (decode_output[40] ^ data_wire[33]) : data_wire[33];
assign wire_mux21_34_dataout = (syndrome[7] == 1'b1) ? (decode_output[41] ^ data_wire[34]) : data_wire[34];
assign wire_mux21_35_dataout = (syndrome[7] == 1'b1) ? (decode_output[42] ^ data_wire[35]) : data_wire[35];
assign wire_mux21_36_dataout = (syndrome[7] == 1'b1) ? (decode_output[43] ^ data_wire[36]) : data_wire[36];
assign wire_mux21_37_dataout = (syndrome[7] == 1'b1) ? (decode_output[44] ^ data_wire[37]) : data_wire[37];
assign wire_mux21_38_dataout = (syndrome[7] == 1'b1) ? (decode_output[45] ^ data_wire[38]) : data_wire[38];
assign wire_mux21_39_dataout = (syndrome[7] == 1'b1) ? (decode_output[46] ^ data_wire[39]) : data_wire[39];
assign wire_mux21_4_dataout = (syndrome[7] == 1'b1) ? (decode_output[9] ^ data_wire[4]) : data_wire[4];
assign wire_mux21_40_dataout = (syndrome[7] == 1'b1) ? (decode_output[47] ^ data_wire[40]) : data_wire[40];
assign wire_mux21_41_dataout = (syndrome[7] == 1'b1) ? (decode_output[48] ^ data_wire[41]) : data_wire[41];
assign wire_mux21_42_dataout = (syndrome[7] == 1'b1) ? (decode_output[49] ^ data_wire[42]) : data_wire[42];
assign wire_mux21_43_dataout = (syndrome[7] == 1'b1) ? (decode_output[50] ^ data_wire[43]) : data_wire[43];
assign wire_mux21_44_dataout = (syndrome[7] == 1'b1) ? (decode_output[51] ^ data_wire[44]) : data_wire[44];
assign wire_mux21_45_dataout = (syndrome[7] == 1'b1) ? (decode_output[52] ^ data_wire[45]) : data_wire[45];
assign wire_mux21_46_dataout = (syndrome[7] == 1'b1) ? (decode_output[53] ^ data_wire[46]) : data_wire[46];
assign wire_mux21_47_dataout = (syndrome[7] == 1'b1) ? (decode_output[54] ^ data_wire[47]) : data_wire[47];
assign wire_mux21_48_dataout = (syndrome[7] == 1'b1) ? (decode_output[55] ^ data_wire[48]) : data_wire[48];
assign wire_mux21_49_dataout = (syndrome[7] == 1'b1) ? (decode_output[56] ^ data_wire[49]) : data_wire[49];
assign wire_mux21_5_dataout = (syndrome[7] == 1'b1) ? (decode_output[10] ^ data_wire[5]) : data_wire[5];
assign wire_mux21_50_dataout = (syndrome[7] == 1'b1) ? (decode_output[57] ^ data_wire[50]) : data_wire[50];
assign wire_mux21_51_dataout = (syndrome[7] == 1'b1) ? (decode_output[58] ^ data_wire[51]) : data_wire[51];
assign wire_mux21_52_dataout = (syndrome[7] == 1'b1) ? (decode_output[59] ^ data_wire[52]) : data_wire[52];
assign wire_mux21_53_dataout = (syndrome[7] == 1'b1) ? (decode_output[60] ^ data_wire[53]) : data_wire[53];
assign wire_mux21_54_dataout = (syndrome[7] == 1'b1) ? (decode_output[61] ^ data_wire[54]) : data_wire[54];
assign wire_mux21_55_dataout = (syndrome[7] == 1'b1) ? (decode_output[62] ^ data_wire[55]) : data_wire[55];
assign wire_mux21_56_dataout = (syndrome[7] == 1'b1) ? (decode_output[63] ^ data_wire[56]) : data_wire[56];
assign wire_mux21_57_dataout = (syndrome[7] == 1'b1) ? (decode_output[65] ^ data_wire[57]) : data_wire[57];
assign wire_mux21_58_dataout = (syndrome[7] == 1'b1) ? (decode_output[66] ^ data_wire[58]) : data_wire[58];
assign wire_mux21_59_dataout = (syndrome[7] == 1'b1) ? (decode_output[67] ^ data_wire[59]) : data_wire[59];
assign wire_mux21_6_dataout = (syndrome[7] == 1'b1) ? (decode_output[11] ^ data_wire[6]) : data_wire[6];
assign wire_mux21_60_dataout = (syndrome[7] == 1'b1) ? (decode_output[68] ^ data_wire[60]) : data_wire[60];
assign wire_mux21_61_dataout = (syndrome[7] == 1'b1) ? (decode_output[69] ^ data_wire[61]) : data_wire[61];
assign wire_mux21_62_dataout = (syndrome[7] == 1'b1) ? (decode_output[70] ^ data_wire[62]) : data_wire[62];
assign wire_mux21_63_dataout = (syndrome[7] == 1'b1) ? (decode_output[71] ^ data_wire[63]) : data_wire[63];
assign wire_mux21_7_dataout = (syndrome[7] == 1'b1) ? (decode_output[12] ^ data_wire[7]) : data_wire[7];
assign wire_mux21_8_dataout = (syndrome[7] == 1'b1) ? (decode_output[13] ^ data_wire[8]) : data_wire[8];
assign wire_mux21_9_dataout = (syndrome[7] == 1'b1) ? (decode_output[14] ^ data_wire[9]) : data_wire[9];
assign
data_bit = data_t[63],
data_t = {(data_t[62] | decode_output[71]), (data_t[61] | decode_output[70]), (data_t[60] | decode_output[69]), (data_t[59] | decode_output[68]), (data_t[58] | decode_output[67]), (data_t[57] | decode_output[66]), (data_t[56] | decode_output[65]), (data_t[55] | decode_output[63]), (data_t[54] | decode_output[62]), (data_t[53] | decode_output[61]), (data_t[52] | decode_output[60]), (data_t[51] | decode_output[59]), (data_t[50] | decode_output[58]), (data_t[49] | decode_output[57]), (data_t[48] | decode_output[56]), (data_t[47] | decode_output[55]), (data_t[46] | decode_output[54]), (data_t[45] | decode_output[53]), (data_t[44] | decode_output[52]), (data_t[43] | decode_output[51]), (data_t[42] | decode_output[50]), (data_t[41] | decode_output[49]), (data_t[40] | decode_output[48]), (data_t[39] | decode_output[47]), (data_t[38] | decode_output[46]), (data_t[37] | decode_output[45]), (data_t[36] | decode_output[44]), (data_t[35] | decode_output[43]), (data_t[34] | decode_output[42]), (data_t[33] | decode_output[41]), (data_t[32] | decode_output[40]), (data_t[31] | decode_output[39]), (data_t[30] | decode_output[38]), (data_t[29] | decode_output[37]), (data_t[28] | decode_output[36]), (data_t[27] | decode_output[35]), (data_t[26] | decode_output[34]), (data_t[25] | decode_output[33]), (data_t[24] | decode_output[31]), (data_t[23] | decode_output[30]), (data_t[22] | decode_output[29]), (data_t[21] | decode_output[28]), (data_t[20] | decode_output[27]), (data_t[19] | decode_output[26]), (data_t[18] | decode_output[25]), (data_t[17] | decode_output[24]), (data_t[16] | decode_output[23]), (data_t[15] | decode_output[22]), (data_t[14] | decode_output[21]), (data_t[13] | decode_output[20]), (data_t[12] | decode_output[19]), (data_t[11] | decode_output[18]), (data_t[10] | decode_output[17]), (data_t[9] | decode_output[15]), (data_t[8] | decode_output[14]), (data_t[7] | decode_output[13]), (data_t[6] | decode_output[12]), (data_t[5] | decode_output[11]), (data_t[4] | decode_output[10]), (data_t[3] | decode_output[9]), (data_t[2]
| decode_output[7]), (data_t[1] | decode_output[6]), (data_t[0] | decode_output[5]), decode_output[3]},
data_wire = data,
decode_output = wire_error_bit_decoder_eq,
err_corrected = err_corrected_wire,
err_corrected_wire = ((syn_bit & syn_e) & data_bit),
err_detected = err_detected_wire,
err_detected_wire = (syn_bit & (~ (syn_e & parity_bit))),
err_fatal = err_fatal_wire,
err_sbe = syn_e,
err_fatal_wire = (err_detected_wire & (~ err_corrected_wire)),
parity_01_wire = {(data_wire[63] ^ parity_01_wire[34]), (data_wire[61] ^ parity_01_wire[33]), (data_wire[59] ^ parity_01_wire[32]), (data_wire[57] ^ parity_01_wire[31]), (data_wire[56] ^ parity_01_wire[30]), (data_wire[54] ^ parity_01_wire[29]), (data_wire[52] ^ parity_01_wire[28]), (data_wire[50] ^ parity_01_wire[27]), (data_wire[48] ^ parity_01_wire[26]), (data_wire[46] ^ parity_01_wire[25]), (data_wire[44] ^ parity_01_wire[24]), (data_wire[42] ^ parity_01_wire[23]), (data_wire[40] ^ parity_01_wire[22]), (data_wire[38] ^ parity_01_wire[21]), (data_wire[36] ^ parity_01_wire[20]), (data_wire[34] ^ parity_01_wire[19]), (data_wire[32] ^ parity_01_wire[18]), (data_wire[30] ^ parity_01_wire[17]), (data_wire[28] ^ parity_01_wire[16]), (data_wire[26] ^ parity_01_wire[15]), (data_wire[25] ^ parity_01_wire[14]), (data_wire[23] ^ parity_01_wire[13]), (data_wire[21] ^ parity_01_wire[12]), (data_wire[19] ^ parity_01_wire[11]), (data_wire[17] ^ parity_01_wire[10]), (data_wire[15] ^ parity_01_wire[9]), (data_wire[13] ^ parity_01_wire[8]), (data_wire[11] ^ parity_01_wire[7]), (data_wire[10] ^ parity_01_wire[6]), (data_wire[8] ^ parity_01_wire[5]), (data_wire[6] ^ parity_01_wire[4]), (data_wire[4] ^ parity_01_wire[3]), (data_wire[3] ^ parity_01_wire[2]), (data_wire[1] ^ parity_01_wire[1]), (data_wire[0] ^ parity_01_wire[0]), data_wire[64]},
parity_02_wire = {((data_wire[62] ^ data_wire[63]) ^ parity_02_wire[16]), ((data_wire[58] ^ data_wire[59]) ^ parity_02_wire[15]), ((data_wire[55] ^ data_wire[56]) ^ parity_02_wire[14]), ((data_wire[51] ^ data_wire[52]) ^ parity_02_wire[13]), ((data_wire[47] ^ data_wire[48]) ^ parity_02_wire[12]), ((data_wire[43] ^ data_wire[44]) ^ parity_02_wire[11]), ((data_wire[39] ^ data_wire[40]) ^ parity_02_wire[10]), ((data_wire[35] ^ data_wire[36]) ^ parity_02_wire[9]), ((data_wire[31] ^ data_wire[32]) ^ parity_02_wire[8]), ((data_wire[27] ^ data_wire[28]) ^ parity_02_wire[7]), ((data_wire[24] ^ data_wire[25]) ^ parity_02_wire[6]), ((data_wire[20] ^ data_wire[21]) ^ parity_02_wire[5]), ((data_wire[16] ^ data_wire[17]) ^ parity_02_wire[4]), ((data_wire[12] ^ data_wire[13]) ^ parity_02_wire[3]), ((data_wire[9] ^ data_wire[10]) ^ parity_02_wire[2]), ((data_wire[5] ^ data_wire[6]) ^ parity_02_wire[1]), ((data_wire[2] ^ data_wire[3]) ^ parity_02_wire[0]), (data_wire[65] ^ data_wire[0])},
parity_03_wire = {((((data_wire[60] ^ data_wire[61]) ^ data_wire[62]) ^ data_wire[63]) ^ parity_03_wire[7]), ((((data_wire[53] ^ data_wire[54]) ^ data_wire[55]) ^ data_wire[56]) ^ parity_03_wire[6]), ((((data_wire[45] ^ data_wire[46]) ^ data_wire[47]) ^ data_wire[48]) ^ parity_03_wire[5]), ((((data_wire[37] ^ data_wire[38]) ^ data_wire[39]) ^ data_wire[40]) ^ parity_03_wire[4]), ((((data_wire[29] ^ data_wire[30]) ^ data_wire[31]) ^ data_wire[32]) ^ parity_03_wire[3]), ((((data_wire[22] ^ data_wire[23]) ^ data_wire[24]) ^ data_wire[25]) ^ parity_03_wire[2]), ((((data_wire[14] ^ data_wire[15]) ^ data_wire[16]) ^ data_wire[17]) ^ parity_03_wire[1]), ((((data_wire[7] ^ data_wire[8]) ^ data_wire[9]) ^ data_wire[10]) ^ parity_03_wire[0]), (((data_wire[66] ^ data_wire[1]) ^ data_wire[2]) ^ data_wire[3])},
parity_04_wire = {((((((((data_wire[49] ^ data_wire[50]) ^ data_wire[51]) ^ data_wire[52]) ^ data_wire[53]) ^ data_wire[54]) ^ data_wire[55]) ^ data_wire[56]) ^ parity_04_wire[2]), ((((((((data_wire[33] ^ data_wire[34]) ^ data_wire[35]) ^ data_wire[36]) ^ data_wire[37]) ^ data_wire[38]) ^ data_wire[39]) ^ data_wire[40]) ^ parity_04_wire[1]), ((((((((data_wire[18] ^ data_wire[19]) ^ data_wire[20]) ^ data_wire[21]) ^ data_wire[22]) ^ data_wire[23]) ^ data_wire[24]) ^ data_wire[25]) ^ parity_04_wire[0]), (((((((data_wire[67] ^ data_wire[4]) ^ data_wire[5]) ^ data_wire[6]) ^ data_wire[7]) ^ data_wire[8]) ^ data_wire[9]) ^ data_wire[10])},
parity_05_wire = {((((((((((((((((data_wire[41] ^ data_wire[42]) ^ data_wire[43]) ^ data_wire[44]) ^ data_wire[45]) ^ data_wire[46]) ^ data_wire[47]) ^ data_wire[48]) ^ data_wire[49]) ^ data_wire[50]) ^ data_wire[51]) ^ data_wire[52]) ^ data_wire[53]) ^ data_wire[54]) ^ data_wire[55]) ^ data_wire[56]) ^ parity_05_wire[0]), (((((((((((((((data_wire[68] ^ data_wire[11]) ^ data_wire[12]) ^ data_wire[13]) ^ data_wire[14]) ^ data_wire[15]) ^ data_wire[16]) ^ data_wire[17]) ^ data_wire[18]) ^ data_wire[19]) ^ data_wire[20]) ^ data_wire[21]) ^ data_wire[22]) ^ data_wire[23]) ^ data_wire[24]) ^ data_wire[25])},
parity_06_wire = {(data_wire[56] ^ parity_06_wire[29]), (data_wire[55] ^ parity_06_wire[28]), (data_wire[54] ^ parity_06_wire[27]), (data_wire[53] ^ parity_06_wire[26]), (data_wire[52] ^ parity_06_wire[25]), (data_wire[51] ^ parity_06_wire[24]), (data_wire[50] ^ parity_06_wire[23]), (data_wire[49] ^ parity_06_wire[22]), (data_wire[48] ^ parity_06_wire[21]), (data_wire[47] ^ parity_06_wire[20]), (data_wire[46] ^ parity_06_wire[19]), (data_wire[45] ^ parity_06_wire[18]), (data_wire[44] ^ parity_06_wire[17]), (data_wire[43] ^ parity_06_wire[16]), (data_wire[42] ^ parity_06_wire[15]), (data_wire[41] ^ parity_06_wire[14]), (data_wire[40] ^ parity_06_wire[13]), (data_wire[39] ^ parity_06_wire[12]), (data_wire[38] ^ parity_06_wire[11]), (data_wire[37] ^ parity_06_wire[10]), (data_wire[36] ^ parity_06_wire[9]), (data_wire[35] ^ parity_06_wire[8]), (data_wire[34] ^ parity_06_wire[7]), (data_wire[33] ^ parity_06_wire[6]), (data_wire[32] ^ parity_06_wire[5]), (data_wire[31] ^ parity_06_wire[4]), (data_wire[30] ^ parity_06_wire[3]), (data_wire[29] ^ parity_06_wire[2]), (data_wire[28] ^ parity_06_wire[1]), (data_wire[27] ^ parity_06_wire[0]), (data_wire[69] ^ data_wire[26])},
parity_07_wire = {(data_wire[63] ^ parity_07_wire[5]), (data_wire[62] ^ parity_07_wire[4]), (data_wire[61] ^ parity_07_wire[3]), (data_wire[60] ^ parity_07_wire[2]), (data_wire[59] ^ parity_07_wire[1]), (data_wire[58] ^ parity_07_wire[0]), (data_wire[70] ^ data_wire[57])},
parity_bit = parity_t[6],
parity_final_wire = {(data_wire[70] ^ parity_final_wire[69]), (data_wire[69] ^ parity_final_wire[68]), (data_wire[68] ^ parity_final_wire[67]), (data_wire[67] ^ parity_final_wire[66]), (data_wire[66] ^ parity_final_wire[65]), (data_wire[65] ^ parity_final_wire[64]), (data_wire[64] ^ parity_final_wire[63]), (data_wire[63] ^ parity_final_wire[62]), (data_wire[62] ^ parity_final_wire[61]), (data_wire[61] ^ parity_final_wire[60]), (data_wire[60] ^ parity_final_wire[59]), (data_wire[59] ^ parity_final_wire[58]), (data_wire[58] ^ parity_final_wire[57]), (data_wire[57] ^ parity_final_wire[56]), (data_wire[56] ^ parity_final_wire[55]), (data_wire[55] ^ parity_final_wire[54]), (data_wire[54] ^ parity_final_wire[53]), (data_wire[53] ^ parity_final_wire[52]), (data_wire[52] ^ parity_final_wire[51]), (data_wire[51] ^ parity_final_wire[50]), (data_wire[50] ^ parity_final_wire[49]), (data_wire[49] ^ parity_final_wire[48]), (data_wire[48] ^ parity_final_wire[47]), (data_wire[47] ^ parity_final_wire[46]), (data_wire[46] ^ parity_final_wire[45]), (data_wire[45] ^ parity_final_wire[44]), (data_wire[44] ^ parity_final_wire[43]), (data_wire[43] ^ parity_final_wire[42]), (data_wire[42] ^ parity_final_wire[41]), (data_wire[41] ^ parity_final_wire[40]), (data_wire[40] ^ parity_final_wire[39]), (data_wire[39] ^ parity_final_wire[38]), (data_wire[38] ^ parity_final_wire[37]), (data_wire[37] ^ parity_final_wire[36]), (data_wire[36] ^ parity_final_wire[35]), (data_wire[35] ^ parity_final_wire[34]), (data_wire[34] ^ parity_final_wire[33]), (data_wire[33] ^ parity_final_wire[32]), (data_wire[32] ^ parity_final_wire[31]), (data_wire[31] ^ parity_final_wire[30]), (data_wire[30] ^ parity_final_wire[29]), (data_wire[29] ^ parity_final_wire[28]), (data_wire[28] ^ parity_final_wire[27]), (data_wire[27] ^ parity_final_wire[26]), (data_wire[26] ^ parity_final_wire[25]), (data_wire[25] ^ parity_final_wire[24]), (data_wire[24] ^ parity_final_wire[23]), (data_wire[23] ^ parity_final_wire[22]), (data_wire[22] ^ parity_final_wire[21]), (data_wire[21] ^
parity_final_wire[20]), (data_wire[20] ^ parity_final_wire[19]), (data_wire[19] ^ parity_final_wire[18]), (data_wire[18] ^ parity_final_wire[17]), (data_wire[17] ^ parity_final_wire[16]), (data_wire[16] ^ parity_final_wire[15]), (data_wire[15] ^ parity_final_wire[14]), (data_wire[14] ^ parity_final_wire[13]), (data_wire[13] ^ parity_final_wire[12]), (data_wire[12] ^ parity_final_wire[11]), (data_wire[11] ^ parity_final_wire[10]), (data_wire[10] ^ parity_final_wire[9]), (data_wire[9] ^ parity_final_wire[8]), (data_wire[8] ^ parity_final_wire[7]), (data_wire[7] ^ parity_final_wire[6]), (data_wire[6] ^ parity_final_wire[5]), (data_wire[5] ^ parity_final_wire[4]), (data_wire[4] ^ parity_final_wire[3]), (data_wire[3] ^ parity_final_wire[2]), (data_wire[2] ^ parity_final_wire[1]), (data_wire[1] ^ parity_final_wire[0]), (data_wire[71] ^ data_wire[0])},
parity_t = {(parity_t[5] | decode_output[64]), (parity_t[4] | decode_output[32]), (parity_t[3] | decode_output[16]), (parity_t[2] | decode_output[8]), (parity_t[1] | decode_output[4]), (parity_t[0] | decode_output[2]), decode_output[1]},
q = q_wire,
q_wire = {wire_mux21_63_dataout, wire_mux21_62_dataout, wire_mux21_61_dataout, wire_mux21_60_dataout, wire_mux21_59_dataout, wire_mux21_58_dataout, wire_mux21_57_dataout, wire_mux21_56_dataout, wire_mux21_55_dataout, wire_mux21_54_dataout, wire_mux21_53_dataout, wire_mux21_52_dataout, wire_mux21_51_dataout, wire_mux21_50_dataout, wire_mux21_49_dataout, wire_mux21_48_dataout, wire_mux21_47_dataout, wire_mux21_46_dataout, wire_mux21_45_dataout, wire_mux21_44_dataout, wire_mux21_43_dataout, wire_mux21_42_dataout, wire_mux21_41_dataout, wire_mux21_40_dataout, wire_mux21_39_dataout, wire_mux21_38_dataout, wire_mux21_37_dataout, wire_mux21_36_dataout, wire_mux21_35_dataout, wire_mux21_34_dataout, wire_mux21_33_dataout, wire_mux21_32_dataout, wire_mux21_31_dataout, wire_mux21_30_dataout, wire_mux21_29_dataout, wire_mux21_28_dataout, wire_mux21_27_dataout, wire_mux21_26_dataout, wire_mux21_25_dataout, wire_mux21_24_dataout, wire_mux21_23_dataout, wire_mux21_22_dataout, wire_mux21_21_dataout, wire_mux21_20_dataout, wire_mux21_19_dataout, wire_mux21_18_dataout, wire_mux21_17_dataout, wire_mux21_16_dataout, wire_mux21_15_dataout, wire_mux21_14_dataout, wire_mux21_13_dataout, wire_mux21_12_dataout, wire_mux21_11_dataout, wire_mux21_10_dataout, wire_mux21_9_dataout, wire_mux21_8_dataout, wire_mux21_7_dataout, wire_mux21_6_dataout, wire_mux21_5_dataout, wire_mux21_4_dataout, wire_mux21_3_dataout, wire_mux21_2_dataout, wire_mux21_1_dataout, wire_mux21_0_dataout},
syn_bit = syn_t[5],
syn_e = syndrome[7],
syn_t = {(syn_t[4] | syndrome[6]), (syn_t[3] | syndrome[5]), (syn_t[2] | syndrome[4]), (syn_t[1] | syndrome[3]), (syn_t[0] | syndrome[2]), (syndrome[0] | syndrome[1])},
syndrome = {parity_final_wire[70], parity_07_wire[6], parity_06_wire[30], parity_05_wire[1], parity_04_wire[3], parity_03_wire[8], parity_02_wire[17], parity_01_wire[35]};
endmodule //alt_mem_ddrx_ecc_decoder_64_altecc_decoder
//VALID FILE
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module alt_mem_ddrx_ecc_decoder_64 (
data,
err_corrected,
err_detected,
err_fatal,
err_sbe,
q)/* synthesis synthesis_clearbox = 1 */;
input [71:0] data;
output err_corrected;
output err_detected;
output err_fatal;
output err_sbe;
output [63:0] q;
wire sub_wire0;
wire sub_wire1;
wire sub_wire2;
wire sub_wire4;
wire [63:0] sub_wire3;
wire err_detected = sub_wire0;
wire err_fatal = sub_wire1;
wire err_corrected = sub_wire2;
wire err_sbe = sub_wire4;
wire [63:0] q = sub_wire3[63:0];
alt_mem_ddrx_ecc_decoder_64_altecc_decoder alt_mem_ddrx_ecc_decoder_64_altecc_decoder_component (
.data (data),
.err_detected (sub_wire0),
.err_fatal (sub_wire1),
.err_corrected (sub_wire2),
.err_sbe (sub_wire4),
.q (sub_wire3));
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix III"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "1"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix III"
// Retrieval info: CONSTANT: lpm_pipeline NUMERIC "0"
// Retrieval info: CONSTANT: width_codeword NUMERIC "72"
// Retrieval info: CONSTANT: width_dataword NUMERIC "64"
// Retrieval info: USED_PORT: data 0 0 72 0 INPUT NODEFVAL "data[71..0]"
// Retrieval info: USED_PORT: err_corrected 0 0 0 0 OUTPUT NODEFVAL "err_corrected"
// Retrieval info: USED_PORT: err_detected 0 0 0 0 OUTPUT NODEFVAL "err_detected"
// Retrieval info: USED_PORT: err_fatal 0 0 0 0 OUTPUT NODEFVAL "err_fatal"
// Retrieval info: USED_PORT: q 0 0 64 0 OUTPUT NODEFVAL "q[63..0]"
// Retrieval info: CONNECT: @data 0 0 72 0 data 0 0 72 0
// Retrieval info: CONNECT: err_corrected 0 0 0 0 @err_corrected 0 0 0 0
// Retrieval info: CONNECT: err_detected 0 0 0 0 @err_detected 0 0 0 0
// Retrieval info: CONNECT: err_fatal 0 0 0 0 @err_fatal 0 0 0 0
// Retrieval info: CONNECT: q 0 0 64 0 @q 0 0 64 0
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder_bb.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder_32.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder_32.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder_32.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder_32.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder_32_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder_32_bb.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder_32_syn.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder_64.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder_64.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder_64.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder_64.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder_64_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder_64_bb.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder_64_syn.v TRUE
// Retrieval info: LIB_FILE: lpm
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module alt_mem_ddrx_ecc_encoder #
( parameter
CFG_DATA_WIDTH = 40,
CFG_ECC_CODE_WIDTH = 8,
CFG_ECC_ENC_REG = 0,
CFG_MMR_DRAM_DATA_WIDTH = 7,
CFG_MMR_LOCAL_DATA_WIDTH = 7,
CFG_PORT_WIDTH_ENABLE_ECC = 1
)
(
ctl_clk,
ctl_reset_n,
cfg_local_data_width,
cfg_dram_data_width,
cfg_enable_ecc,
input_data,
input_ecc_code,
input_ecc_code_overwrite,
output_data
);
localparam CFG_ECC_DATA_WIDTH = (CFG_DATA_WIDTH > 8) ? (CFG_DATA_WIDTH - CFG_ECC_CODE_WIDTH) : (CFG_DATA_WIDTH);
input ctl_clk;
input ctl_reset_n;
input [CFG_MMR_DRAM_DATA_WIDTH - 1 : 0] cfg_local_data_width;
input [CFG_MMR_LOCAL_DATA_WIDTH - 1 : 0] cfg_dram_data_width;
input [CFG_PORT_WIDTH_ENABLE_ECC - 1 : 0] cfg_enable_ecc;
input [CFG_DATA_WIDTH - 1 : 0] input_data;
input [CFG_ECC_CODE_WIDTH - 1 : 0] input_ecc_code;
input input_ecc_code_overwrite;
output [CFG_DATA_WIDTH - 1 : 0] output_data;
//--------------------------------------------------------------------------------------------------------
//
// [START] Register & Wires
//
//--------------------------------------------------------------------------------------------------------
reg [CFG_DATA_WIDTH - 1 : 0] int_encoder_input;
reg [CFG_DATA_WIDTH - 1 : 0] int_input_data;
reg [CFG_ECC_CODE_WIDTH - 1 : 0] int_input_ecc_code;
reg int_input_ecc_code_overwrite;
reg [CFG_DATA_WIDTH - 1 : 0] int_encoder_output;
reg [CFG_DATA_WIDTH - 1 : 0] output_data;
reg [CFG_DATA_WIDTH - 1 : 0] int_encoder_output_modified;
wire [CFG_ECC_DATA_WIDTH - 1 : 0] encoder_input;
wire [CFG_DATA_WIDTH - 1 : 0] encoder_output;
//--------------------------------------------------------------------------------------------------------
//
// [END] Register & Wires
//
//--------------------------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------------------------
//
// [START] Common Logic
//
//--------------------------------------------------------------------------------------------------------
// Input data
generate
genvar i_data;
for (i_data = 0;i_data < CFG_DATA_WIDTH;i_data = i_data + 1)
begin : encoder_input_per_data_width
always @ (*)
begin
int_encoder_input [i_data] = input_data [i_data];
end
end
endgenerate
// Encoder input assignment
assign encoder_input = int_encoder_input [CFG_ECC_DATA_WIDTH - 1 : 0];
// Output data merging logic
// change
// <ECC code> - <Empty data> - <Data>
// into
// <Empty data> - <ECC code> - <Data>
always @ (*)
begin
int_encoder_output = encoder_output;
end
generate
if (CFG_DATA_WIDTH <= 8)
begin
// No support for ECC case
always @ (*)
begin
// Write data only
int_encoder_output_modified = int_encoder_output;
end
end
else
begin
always @ (*)
begin
// Write data
int_encoder_output_modified [CFG_ECC_DATA_WIDTH - 1 : 0] = int_encoder_output [CFG_ECC_DATA_WIDTH - 1 : 0];
// Ecc code
if (int_input_ecc_code_overwrite)
begin
int_encoder_output_modified [CFG_DATA_WIDTH - 1 : CFG_ECC_DATA_WIDTH] = int_input_ecc_code;
end
else
begin
int_encoder_output_modified [CFG_DATA_WIDTH - 1 : CFG_ECC_DATA_WIDTH] = int_encoder_output [CFG_DATA_WIDTH - 1 : CFG_ECC_DATA_WIDTH];
end
end
end
endgenerate
// Encoder output assignment
always @ (*)
begin
if (cfg_enable_ecc)
output_data = int_encoder_output_modified;
else
output_data = int_input_data;
end
generate
if (CFG_ECC_ENC_REG)
begin
// Registered version
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_input_data <= 0;
int_input_ecc_code <= 0;
int_input_ecc_code_overwrite <= 0;
end
else
begin
int_input_data <= input_data;
int_input_ecc_code <= input_ecc_code;
int_input_ecc_code_overwrite <= input_ecc_code_overwrite;
end
end
end
else
begin
// Non-registered version
always @ (*)
begin
int_input_data = input_data;
int_input_ecc_code = input_ecc_code;
int_input_ecc_code_overwrite = input_ecc_code_overwrite;
end
end
endgenerate
//--------------------------------------------------------------------------------------------------------
//
// [END] Common Logic
//
//--------------------------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------------------------
//
// [START] Instantiation
//
//--------------------------------------------------------------------------------------------------------
generate
begin
if (CFG_ECC_DATA_WIDTH == 8 && CFG_DATA_WIDTH > 8) // Make sure this is an ECC case else it will cause compilation error
begin
wire [39 : 0] int_encoder_output;
// Assign bit 39 to '0'
assign int_encoder_output [39] = 1'b0;
// Assign the lower data bits
assign encoder_output [CFG_ECC_DATA_WIDTH - 1 : 0] = int_encoder_output [31 : 0];
// Assign the upper ECC bits
assign encoder_output [CFG_DATA_WIDTH - 1 : CFG_ECC_DATA_WIDTH] = int_encoder_output [39 : 32];
// 32/39 bit encoder instantiation
alt_mem_ddrx_ecc_encoder_32 #
(
.CFG_ECC_ENC_REG (CFG_ECC_ENC_REG )
)
encoder_inst
(
.clk (ctl_clk ),
.reset_n (ctl_reset_n ),
.data ({24'd0, encoder_input} ),
.q (int_encoder_output [38 : 0])
);
end
else if (CFG_ECC_DATA_WIDTH == 16)
begin
wire [39 : 0] int_encoder_output;
// Assign bit 39 to '0'
assign int_encoder_output [39] = 1'b0;
// Assign the lower data bits
assign encoder_output [CFG_ECC_DATA_WIDTH - 1 : 0] = int_encoder_output [31 : 0];
// Assign the upper ECC bits
assign encoder_output [CFG_DATA_WIDTH - 1 : CFG_ECC_DATA_WIDTH] = int_encoder_output [39 : 32];
// 32/39 bit encoder instantiation
alt_mem_ddrx_ecc_encoder_32 #
(
.CFG_ECC_ENC_REG (CFG_ECC_ENC_REG )
)
encoder_inst
(
.clk (ctl_clk ),
.reset_n (ctl_reset_n ),
.data ({16'd0, encoder_input} ),
.q (int_encoder_output [38 : 0])
);
end
else if (CFG_ECC_DATA_WIDTH == 32)
begin
// Assign bit 39 to '0'
assign encoder_output [39] = 1'b0;
// 32/39 bit encoder instantiation
alt_mem_ddrx_ecc_encoder_32 #
(
.CFG_ECC_ENC_REG (CFG_ECC_ENC_REG )
)
encoder_inst
(
.clk (ctl_clk ),
.reset_n (ctl_reset_n ),
.data (encoder_input ),
.q (encoder_output [38 : 0])
);
end
else if (CFG_ECC_DATA_WIDTH == 64)
begin
// 64/72 bit encoder instantiation
alt_mem_ddrx_ecc_encoder_64 #
(
.CFG_ECC_ENC_REG (CFG_ECC_ENC_REG)
)
encoder_inst
(
.clk (ctl_clk ),
.reset_n (ctl_reset_n ),
.data (encoder_input ),
.q (encoder_output )
);
end
end
endgenerate
//--------------------------------------------------------------------------------------------------------
//
// [END] Instantiation
//
//--------------------------------------------------------------------------------------------------------
endmodule
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// megafunction wizard: %ALTECC%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altecc_encoder
// ============================================================
// File Name: alt_mem_ddrx_ecc_encoder_32.v
// Megafunction Name(s):
// altecc_encoder
//
// Simulation Library Files(s):
//
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 10.0 Internal Build 257 07/26/2010 SP 1 PN Full Version
// ************************************************************
//Copyright (C) 1991-2010 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
//altecc_encoder device_family="Stratix III" lpm_pipeline=0 width_codeword=39 width_dataword=32 data q
//VERSION_BEGIN 10.0SP1 cbx_altecc_encoder 2010:07:26:21:21:15:PN cbx_mgl 2010:07:26:21:25:47:PN VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module alt_mem_ddrx_ecc_encoder_32_altecc_encoder #
( parameter
CFG_ECC_ENC_REG = 0
)
(
clk,
reset_n,
data,
q
) /* synthesis synthesis_clearbox=1 */;
input clk;
input reset_n;
input [31:0] data;
output [38:0] q;
wire [31:0] data_wire;
wire [17:0] parity_01_wire;
wire [9:0] parity_02_wire;
wire [4:0] parity_03_wire;
wire [1:0] parity_04_wire;
wire [0:0] parity_05_wire;
wire [5:0] parity_06_wire;
wire [37:0] parity_final;
wire [37:0] parity_final_wire;
reg [37:0] parity_final_reg;
wire [37:0] q_wire;
reg [37:0] q_reg;
assign
data_wire = data,
parity_01_wire = {
(data_wire[30] ^ parity_01_wire[16]),
(data_wire[28] ^ parity_01_wire[15]),
(data_wire[26] ^ parity_01_wire[14]),
(data_wire[25] ^ parity_01_wire[13]),
(data_wire[23] ^ parity_01_wire[12]),
(data_wire[21] ^ parity_01_wire[11]),
(data_wire[19] ^ parity_01_wire[10]),
(data_wire[17] ^ parity_01_wire[9]),
(data_wire[15] ^ parity_01_wire[8]),
(data_wire[13] ^ parity_01_wire[7]),
(data_wire[11] ^ parity_01_wire[6]),
(data_wire[10] ^ parity_01_wire[5]),
(data_wire[8] ^ parity_01_wire[4]),
(data_wire[6] ^ parity_01_wire[3]),
(data_wire[4] ^ parity_01_wire[2]),
(data_wire[3] ^ parity_01_wire[1]),
(data_wire[1] ^ parity_01_wire[0]),
data_wire[0]
},
parity_02_wire = {
(data_wire[31] ^ parity_02_wire[8]),
((data_wire[27] ^ data_wire[28]) ^ parity_02_wire[7]),
((data_wire[24] ^ data_wire[25]) ^ parity_02_wire[6]),
((data_wire[20] ^ data_wire[21]) ^ parity_02_wire[5]),
((data_wire[16] ^ data_wire[17]) ^ parity_02_wire[4]),
((data_wire[12] ^ data_wire[13]) ^ parity_02_wire[3]),
((data_wire[9] ^ data_wire[10]) ^ parity_02_wire[2]),
((data_wire[5] ^ data_wire[6]) ^ parity_02_wire[1]),
((data_wire[2] ^ data_wire[3]) ^ parity_02_wire[0]),
data_wire[0]
},
parity_03_wire = {
(((data_wire[29] ^ data_wire[30]) ^ data_wire[31]) ^ parity_03_wire[3]),
((((data_wire[22] ^ data_wire[23]) ^ data_wire[24]) ^ data_wire[25]) ^ parity_03_wire[2]),
((((data_wire[14] ^ data_wire[15]) ^ data_wire[16]) ^ data_wire[17]) ^ parity_03_wire[1]),
((((data_wire[7] ^ data_wire[8]) ^ data_wire[9]) ^ data_wire[10]) ^ parity_03_wire[0]),
((data_wire[1] ^ data_wire[2]) ^ data_wire[3])
},
parity_04_wire = {
((((((((data_wire[18] ^ data_wire[19]) ^ data_wire[20]) ^ data_wire[21]) ^ data_wire[22]) ^ data_wire[23]) ^ data_wire[24]) ^ data_wire[25]) ^ parity_04_wire[0]),
((((((data_wire[4] ^ data_wire[5]) ^ data_wire[6]) ^ data_wire[7]) ^ data_wire[8]) ^ data_wire[9]) ^ data_wire[10])
},
parity_05_wire = {
((((((((((((((data_wire[11] ^ data_wire[12]) ^ data_wire[13]) ^ data_wire[14]) ^ data_wire[15]) ^ data_wire[16]) ^ data_wire[17]) ^ data_wire[18]) ^ data_wire[19]) ^ data_wire[20]) ^ data_wire[21]) ^ data_wire[22]) ^ data_wire[23]) ^ data_wire[24]) ^ data_wire[25])
},
parity_06_wire = {
(data_wire[31] ^ parity_06_wire[4]),
(data_wire[30] ^ parity_06_wire[3]),
(data_wire[29] ^ parity_06_wire[2]),
(data_wire[28] ^ parity_06_wire[1]),
(data_wire[27] ^ parity_06_wire[0]),
data_wire[26]
},
parity_final_wire = {
(q_wire[37] ^ parity_final_wire[36]),
(q_wire[36] ^ parity_final_wire[35]),
(q_wire[35] ^ parity_final_wire[34]),
(q_wire[34] ^ parity_final_wire[33]),
(q_wire[33] ^ parity_final_wire[32]),
(q_wire[32] ^ parity_final_wire[31]),
(q_wire[31] ^ parity_final_wire[30]),
(q_wire[30] ^ parity_final_wire[29]),
(q_wire[29] ^ parity_final_wire[28]),
(q_wire[28] ^ parity_final_wire[27]),
(q_wire[27] ^ parity_final_wire[26]),
(q_wire[26] ^ parity_final_wire[25]),
(q_wire[25] ^ parity_final_wire[24]),
(q_wire[24] ^ parity_final_wire[23]),
(q_wire[23] ^ parity_final_wire[22]),
(q_wire[22] ^ parity_final_wire[21]),
(q_wire[21] ^ parity_final_wire[20]),
(q_wire[20] ^ parity_final_wire[19]),
(q_wire[19] ^ parity_final_wire[18]),
(q_wire[18] ^ parity_final_wire[17]),
(q_wire[17] ^ parity_final_wire[16]),
(q_wire[16] ^ parity_final_wire[15]),
(q_wire[15] ^ parity_final_wire[14]),
(q_wire[14] ^ parity_final_wire[13]),
(q_wire[13] ^ parity_final_wire[12]),
(q_wire[12] ^ parity_final_wire[11]),
(q_wire[11] ^ parity_final_wire[10]),
(q_wire[10] ^ parity_final_wire[9]),
(q_wire[9] ^ parity_final_wire[8]),
(q_wire[8] ^ parity_final_wire[7]),
(q_wire[7] ^ parity_final_wire[6]),
(q_wire[6] ^ parity_final_wire[5]),
(q_wire[5] ^ parity_final_wire[4]),
(q_wire[4] ^ parity_final_wire[3]),
(q_wire[3] ^ parity_final_wire[2]),
(q_wire[2] ^ parity_final_wire[1]),
(q_wire[1] ^ parity_final_wire[0]),
q_wire[0]
},
parity_final = {
(q_reg[37] ^ parity_final[36]),
(q_reg[36] ^ parity_final[35]),
(q_reg[35] ^ parity_final[34]),
(q_reg[34] ^ parity_final[33]),
(q_reg[33] ^ parity_final[32]),
(q_reg[32] ^ parity_final[31]),
parity_final_reg[31 : 0]
},
q = {parity_final[37], q_reg},
q_wire = {parity_06_wire[5], parity_05_wire[0], parity_04_wire[1], parity_03_wire[4], parity_02_wire[9], parity_01_wire[17], data_wire};
generate
if (CFG_ECC_ENC_REG)
begin
always @ (posedge clk or negedge reset_n)
begin
if (!reset_n)
begin
q_reg <= 0;
parity_final_reg <= 0;
end
else
begin
q_reg <= q_wire;
parity_final_reg <= parity_final_wire;
end
end
end
else
begin
always @ (*)
begin
q_reg = q_wire;
parity_final_reg = parity_final_wire;
end
end
endgenerate
endmodule //alt_mem_ddrx_ecc_encoder_32_altecc_encoder
//VALID FILE
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module alt_mem_ddrx_ecc_encoder_32 #
( parameter
CFG_ECC_ENC_REG = 0
)
(
clk,
reset_n,
data,
q
)/* synthesis synthesis_clearbox = 1 */;
input clk;
input reset_n;
input [31:0] data;
output [38:0] q;
wire [38:0] sub_wire0;
wire [38:0] q = sub_wire0[38:0];
alt_mem_ddrx_ecc_encoder_32_altecc_encoder #
(
.CFG_ECC_ENC_REG (CFG_ECC_ENC_REG)
)
alt_mem_ddrx_ecc_encoder_32_altecc_encoder_component
(
.clk (clk),
.reset_n (reset_n),
.data (data),
.q (sub_wire0)
);
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix III"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "1"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix III"
// Retrieval info: CONSTANT: lpm_pipeline NUMERIC "0"
// Retrieval info: CONSTANT: width_codeword NUMERIC "39"
// Retrieval info: CONSTANT: width_dataword NUMERIC "32"
// Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL "data[31..0]"
// Retrieval info: USED_PORT: q 0 0 39 0 OUTPUT NODEFVAL "q[38..0]"
// Retrieval info: CONNECT: @data 0 0 32 0 data 0 0 32 0
// Retrieval info: CONNECT: q 0 0 39 0 @q 0 0 39 0
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_encoder.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_encoder.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_encoder.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_encoder.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_encoder_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_encoder_bb.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_encoder_32.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_encoder_32.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_encoder_32.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_encoder_32.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_encoder_32_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_encoder_32_bb.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_encoder_32_syn.v TRUE
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// megafunction wizard: %ALTECC%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altecc_encoder
// ============================================================
// File Name: alt_mem_ddrx_ecc_encoder_64.v
// Megafunction Name(s):
// altecc_encoder
//
// Simulation Library Files(s):
//
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 10.0 Build 262 08/18/2010 SP 1 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2010 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
//altecc_encoder device_family="Stratix III" lpm_pipeline=0 width_codeword=72 width_dataword=64 data q
//VERSION_BEGIN 10.0SP1 cbx_altecc_encoder 2010:08:18:21:16:35:SJ cbx_mgl 2010:08:18:21:20:44:SJ VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module alt_mem_ddrx_ecc_encoder_64_altecc_encoder #
( parameter
CFG_ECC_ENC_REG = 0
)
(
clk,
reset_n,
data,
q
) /* synthesis synthesis_clearbox=1 */;
input clk;
input reset_n;
input [63:0] data;
output [71:0] q;
wire [63:0] data_wire;
wire [34:0] parity_01_wire;
wire [17:0] parity_02_wire;
wire [8:0] parity_03_wire;
wire [3:0] parity_04_wire;
wire [1:0] parity_05_wire;
wire [30:0] parity_06_wire;
wire [6:0] parity_07_wire;
wire [70:0] parity_final;
wire [70:0] parity_final_wire;
reg [70:0] parity_final_reg;
wire [70:0] q_wire;
reg [70:0] q_reg;
assign
data_wire = data,
parity_01_wire = {
(data_wire[63] ^ parity_01_wire[33]),
(data_wire[61] ^ parity_01_wire[32]),
(data_wire[59] ^ parity_01_wire[31]),
(data_wire[57] ^ parity_01_wire[30]),
(data_wire[56] ^ parity_01_wire[29]),
(data_wire[54] ^ parity_01_wire[28]),
(data_wire[52] ^ parity_01_wire[27]),
(data_wire[50] ^ parity_01_wire[26]),
(data_wire[48] ^ parity_01_wire[25]),
(data_wire[46] ^ parity_01_wire[24]),
(data_wire[44] ^ parity_01_wire[23]),
(data_wire[42] ^ parity_01_wire[22]),
(data_wire[40] ^ parity_01_wire[21]),
(data_wire[38] ^ parity_01_wire[20]),
(data_wire[36] ^ parity_01_wire[19]),
(data_wire[34] ^ parity_01_wire[18]),
(data_wire[32] ^ parity_01_wire[17]),
(data_wire[30] ^ parity_01_wire[16]),
(data_wire[28] ^ parity_01_wire[15]),
(data_wire[26] ^ parity_01_wire[14]),
(data_wire[25] ^ parity_01_wire[13]),
(data_wire[23] ^ parity_01_wire[12]),
(data_wire[21] ^ parity_01_wire[11]),
(data_wire[19] ^ parity_01_wire[10]),
(data_wire[17] ^ parity_01_wire[9]),
(data_wire[15] ^ parity_01_wire[8]),
(data_wire[13] ^ parity_01_wire[7]),
(data_wire[11] ^ parity_01_wire[6]),
(data_wire[10] ^ parity_01_wire[5]),
(data_wire[8] ^ parity_01_wire[4]),
(data_wire[6] ^ parity_01_wire[3]),
(data_wire[4] ^ parity_01_wire[2]),
(data_wire[3] ^ parity_01_wire[1]),
(data_wire[1] ^ parity_01_wire[0]),
data_wire[0]
},
parity_02_wire = {
((data_wire[62] ^ data_wire[63]) ^ parity_02_wire[16]),
((data_wire[58] ^ data_wire[59]) ^ parity_02_wire[15]),
((data_wire[55] ^ data_wire[56]) ^ parity_02_wire[14]),
((data_wire[51] ^ data_wire[52]) ^ parity_02_wire[13]),
((data_wire[47] ^ data_wire[48]) ^ parity_02_wire[12]),
((data_wire[43] ^ data_wire[44]) ^ parity_02_wire[11]),
((data_wire[39] ^ data_wire[40]) ^ parity_02_wire[10]),
((data_wire[35] ^ data_wire[36]) ^ parity_02_wire[9]),
((data_wire[31] ^ data_wire[32]) ^ parity_02_wire[8]),
((data_wire[27] ^ data_wire[28]) ^ parity_02_wire[7]),
((data_wire[24] ^ data_wire[25]) ^ parity_02_wire[6]),
((data_wire[20] ^ data_wire[21]) ^ parity_02_wire[5]),
((data_wire[16] ^ data_wire[17]) ^ parity_02_wire[4]),
((data_wire[12] ^ data_wire[13]) ^ parity_02_wire[3]),
((data_wire[9] ^ data_wire[10]) ^ parity_02_wire[2]),
((data_wire[5] ^ data_wire[6]) ^ parity_02_wire[1]),
((data_wire[2] ^ data_wire[3]) ^ parity_02_wire[0]),
data_wire[0]
},
parity_03_wire = {
((((data_wire[60] ^ data_wire[61]) ^ data_wire[62]) ^ data_wire[63]) ^ parity_03_wire[7]),
((((data_wire[53] ^ data_wire[54]) ^ data_wire[55]) ^ data_wire[56]) ^ parity_03_wire[6]),
((((data_wire[45] ^ data_wire[46]) ^ data_wire[47]) ^ data_wire[48]) ^ parity_03_wire[5]),
((((data_wire[37] ^ data_wire[38]) ^ data_wire[39]) ^ data_wire[40]) ^ parity_03_wire[4]),
((((data_wire[29] ^ data_wire[30]) ^ data_wire[31]) ^ data_wire[32]) ^ parity_03_wire[3]),
((((data_wire[22] ^ data_wire[23]) ^ data_wire[24]) ^ data_wire[25]) ^ parity_03_wire[2]),
((((data_wire[14] ^ data_wire[15]) ^ data_wire[16]) ^ data_wire[17]) ^ parity_03_wire[1]),
((((data_wire[7] ^ data_wire[8]) ^ data_wire[9]) ^ data_wire[10]) ^ parity_03_wire[0]),
((data_wire[1] ^ data_wire[2]) ^ data_wire[3])
},
parity_04_wire = {
((((((((data_wire[49] ^ data_wire[50]) ^ data_wire[51]) ^ data_wire[52]) ^ data_wire[53]) ^ data_wire[54]) ^ data_wire[55]) ^ data_wire[56]) ^ parity_04_wire[2]),
((((((((data_wire[33] ^ data_wire[34]) ^ data_wire[35]) ^ data_wire[36]) ^ data_wire[37]) ^ data_wire[38]) ^ data_wire[39]) ^ data_wire[40]) ^ parity_04_wire[1]),
((((((((data_wire[18] ^ data_wire[19]) ^ data_wire[20]) ^ data_wire[21]) ^ data_wire[22]) ^ data_wire[23]) ^ data_wire[24]) ^ data_wire[25]) ^ parity_04_wire[0]),
((((((data_wire[4] ^ data_wire[5]) ^ data_wire[6]) ^ data_wire[7]) ^ data_wire[8]) ^ data_wire[9]) ^ data_wire[10])
},
parity_05_wire = {
((((((((((((((((data_wire[41] ^ data_wire[42]) ^ data_wire[43]) ^ data_wire[44]) ^ data_wire[45]) ^ data_wire[46]) ^ data_wire[47]) ^ data_wire[48]) ^ data_wire[49]) ^ data_wire[50]) ^ data_wire[51]) ^ data_wire[52]) ^ data_wire[53]) ^ data_wire[54]) ^ data_wire[55]) ^ data_wire[56]) ^ parity_05_wire[0]),
((((((((((((((data_wire[11] ^ data_wire[12]) ^ data_wire[13]) ^ data_wire[14]) ^ data_wire[15]) ^ data_wire[16]) ^ data_wire[17]) ^ data_wire[18]) ^ data_wire[19]) ^ data_wire[20]) ^ data_wire[21]) ^ data_wire[22]) ^ data_wire[23]) ^ data_wire[24]) ^ data_wire[25])
},
parity_06_wire = {
(data_wire[56] ^ parity_06_wire[29]),
(data_wire[55] ^ parity_06_wire[28]),
(data_wire[54] ^ parity_06_wire[27]),
(data_wire[53] ^ parity_06_wire[26]),
(data_wire[52] ^ parity_06_wire[25]),
(data_wire[51] ^ parity_06_wire[24]),
(data_wire[50] ^ parity_06_wire[23]),
(data_wire[49] ^ parity_06_wire[22]),
(data_wire[48] ^ parity_06_wire[21]),
(data_wire[47] ^ parity_06_wire[20]),
(data_wire[46] ^ parity_06_wire[19]),
(data_wire[45] ^ parity_06_wire[18]),
(data_wire[44] ^ parity_06_wire[17]),
(data_wire[43] ^ parity_06_wire[16]),
(data_wire[42] ^ parity_06_wire[15]),
(data_wire[41] ^ parity_06_wire[14]),
(data_wire[40] ^ parity_06_wire[13]),
(data_wire[39] ^ parity_06_wire[12]),
(data_wire[38] ^ parity_06_wire[11]),
(data_wire[37] ^ parity_06_wire[10]),
(data_wire[36] ^ parity_06_wire[9]),
(data_wire[35] ^ parity_06_wire[8]),
(data_wire[34] ^ parity_06_wire[7]),
(data_wire[33] ^ parity_06_wire[6]),
(data_wire[32] ^ parity_06_wire[5]),
(data_wire[31] ^ parity_06_wire[4]),
(data_wire[30] ^ parity_06_wire[3]),
(data_wire[29] ^ parity_06_wire[2]),
(data_wire[28] ^ parity_06_wire[1]),
(data_wire[27] ^ parity_06_wire[0]),
data_wire[26]
},
parity_07_wire = {
(data_wire[63] ^ parity_07_wire[5]),
(data_wire[62] ^ parity_07_wire[4]),
(data_wire[61] ^ parity_07_wire[3]),
(data_wire[60] ^ parity_07_wire[2]),
(data_wire[59] ^ parity_07_wire[1]),
(data_wire[58] ^ parity_07_wire[0]),
data_wire[57]
},
parity_final_wire = {
(q_wire[70] ^ parity_final_wire[69]),
(q_wire[69] ^ parity_final_wire[68]),
(q_wire[68] ^ parity_final_wire[67]),
(q_wire[67] ^ parity_final_wire[66]),
(q_wire[66] ^ parity_final_wire[65]),
(q_wire[65] ^ parity_final_wire[64]),
(q_wire[64] ^ parity_final_wire[63]),
(q_wire[63] ^ parity_final_wire[62]),
(q_wire[62] ^ parity_final_wire[61]),
(q_wire[61] ^ parity_final_wire[60]),
(q_wire[60] ^ parity_final_wire[59]),
(q_wire[59] ^ parity_final_wire[58]),
(q_wire[58] ^ parity_final_wire[57]),
(q_wire[57] ^ parity_final_wire[56]),
(q_wire[56] ^ parity_final_wire[55]),
(q_wire[55] ^ parity_final_wire[54]),
(q_wire[54] ^ parity_final_wire[53]),
(q_wire[53] ^ parity_final_wire[52]),
(q_wire[52] ^ parity_final_wire[51]),
(q_wire[51] ^ parity_final_wire[50]),
(q_wire[50] ^ parity_final_wire[49]),
(q_wire[49] ^ parity_final_wire[48]),
(q_wire[48] ^ parity_final_wire[47]),
(q_wire[47] ^ parity_final_wire[46]),
(q_wire[46] ^ parity_final_wire[45]),
(q_wire[45] ^ parity_final_wire[44]),
(q_wire[44] ^ parity_final_wire[43]),
(q_wire[43] ^ parity_final_wire[42]),
(q_wire[42] ^ parity_final_wire[41]),
(q_wire[41] ^ parity_final_wire[40]),
(q_wire[40] ^ parity_final_wire[39]),
(q_wire[39] ^ parity_final_wire[38]),
(q_wire[38] ^ parity_final_wire[37]),
(q_wire[37] ^ parity_final_wire[36]),
(q_wire[36] ^ parity_final_wire[35]),
(q_wire[35] ^ parity_final_wire[34]),
(q_wire[34] ^ parity_final_wire[33]),
(q_wire[33] ^ parity_final_wire[32]),
(q_wire[32] ^ parity_final_wire[31]),
(q_wire[31] ^ parity_final_wire[30]),
(q_wire[30] ^ parity_final_wire[29]),
(q_wire[29] ^ parity_final_wire[28]),
(q_wire[28] ^ parity_final_wire[27]),
(q_wire[27] ^ parity_final_wire[26]),
(q_wire[26] ^ parity_final_wire[25]),
(q_wire[25] ^ parity_final_wire[24]),
(q_wire[24] ^ parity_final_wire[23]),
(q_wire[23] ^ parity_final_wire[22]),
(q_wire[22] ^ parity_final_wire[21]),
(q_wire[21] ^ parity_final_wire[20]),
(q_wire[20] ^ parity_final_wire[19]),
(q_wire[19] ^ parity_final_wire[18]),
(q_wire[18] ^ parity_final_wire[17]),
(q_wire[17] ^ parity_final_wire[16]),
(q_wire[16] ^ parity_final_wire[15]),
(q_wire[15] ^ parity_final_wire[14]),
(q_wire[14] ^ parity_final_wire[13]),
(q_wire[13] ^ parity_final_wire[12]),
(q_wire[12] ^ parity_final_wire[11]),
(q_wire[11] ^ parity_final_wire[10]),
(q_wire[10] ^ parity_final_wire[9]),
(q_wire[9] ^ parity_final_wire[8]),
(q_wire[8] ^ parity_final_wire[7]),
(q_wire[7] ^ parity_final_wire[6]),
(q_wire[6] ^ parity_final_wire[5]),
(q_wire[5] ^ parity_final_wire[4]),
(q_wire[4] ^ parity_final_wire[3]),
(q_wire[3] ^ parity_final_wire[2]),
(q_wire[2] ^ parity_final_wire[1]),
(q_wire[1] ^ parity_final_wire[0]),
q_wire[0]
},
parity_final = {
(q_reg[70] ^ parity_final[69]),
(q_reg[69] ^ parity_final[68]),
(q_reg[68] ^ parity_final[67]),
(q_reg[67] ^ parity_final[66]),
(q_reg[66] ^ parity_final[65]),
(q_reg[65] ^ parity_final[64]),
parity_final_reg [64 : 0]
},
q = {parity_final[70], q_reg},
q_wire = {parity_07_wire[6], parity_06_wire[30], parity_05_wire[1], parity_04_wire[3], parity_03_wire[8], parity_02_wire[17], parity_01_wire[34], data_wire};
generate
if (CFG_ECC_ENC_REG)
begin
always @ (posedge clk or negedge reset_n)
begin
if (!reset_n)
begin
q_reg <= 0;
parity_final_reg <= 0;
end
else
begin
q_reg <= q_wire;
parity_final_reg <= parity_final_wire;
end
end
end
else
begin
always @ (*)
begin
q_reg = q_wire;
parity_final_reg = parity_final_wire;
end
end
endgenerate
endmodule //alt_mem_ddrx_ecc_encoder_64_altecc_encoder
//VALID FILE
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module alt_mem_ddrx_ecc_encoder_64 #
( parameter
CFG_ECC_ENC_REG = 0
)
(
clk,
reset_n,
data,
q
)/* synthesis synthesis_clearbox = 1 */;
input clk;
input reset_n;
input [63:0] data;
output [71:0] q;
wire [71:0] sub_wire0;
wire [71:0] q = sub_wire0[71:0];
alt_mem_ddrx_ecc_encoder_64_altecc_encoder #
(
.CFG_ECC_ENC_REG (CFG_ECC_ENC_REG)
)
alt_mem_ddrx_ecc_encoder_64_altecc_encoder_component
(
.clk (clk),
.reset_n (reset_n),
.data (data),
.q (sub_wire0)
);
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix III"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "1"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix III"
// Retrieval info: CONSTANT: lpm_pipeline NUMERIC "0"
// Retrieval info: CONSTANT: width_codeword NUMERIC "72"
// Retrieval info: CONSTANT: width_dataword NUMERIC "64"
// Retrieval info: USED_PORT: data 0 0 64 0 INPUT NODEFVAL "data[63..0]"
// Retrieval info: USED_PORT: q 0 0 72 0 OUTPUT NODEFVAL "q[71..0]"
// Retrieval info: CONNECT: @data 0 0 64 0 data 0 0 64 0
// Retrieval info: CONNECT: q 0 0 72 0 @q 0 0 72 0
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_encoder.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_encoder.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_encoder.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_encoder.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_encoder_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_encoder_bb.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_encoder_32.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_encoder_32.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_encoder_32.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_encoder_32.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_encoder_32_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_encoder_32_bb.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_encoder_32_syn.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_encoder_64.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_encoder_64.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_encoder_64.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_encoder_64.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_encoder_64_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_encoder_64_bb.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_encoder_64_syn.v TRUE
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
//altera message_off 10230 10036
`timescale 1 ps / 1 ps
module alt_mem_ddrx_ecc_encoder_decoder_wrapper #
( parameter
CFG_LOCAL_DATA_WIDTH = 80,
CFG_LOCAL_ADDR_WIDTH = 32,
CFG_DWIDTH_RATIO = 2,
CFG_MEM_IF_DQ_WIDTH = 40,
CFG_MEM_IF_DQS_WIDTH = 5,
CFG_ECC_CODE_WIDTH = 8,
CFG_ECC_MULTIPLES = 1,
CFG_ECC_ENC_REG = 0,
CFG_ECC_DEC_REG = 0,
CFG_ECC_RDATA_REG = 0,
CFG_PORT_WIDTH_INTERFACE_WIDTH = 8,
CFG_PORT_WIDTH_ENABLE_ECC = 1,
CFG_PORT_WIDTH_GEN_SBE = 1,
CFG_PORT_WIDTH_GEN_DBE = 1,
CFG_PORT_WIDTH_ENABLE_INTR = 1,
CFG_PORT_WIDTH_MASK_SBE_INTR = 1,
CFG_PORT_WIDTH_MASK_DBE_INTR = 1,
CFG_PORT_WIDTH_MASK_CORR_DROPPED_INTR = 1,
CFG_PORT_WIDTH_CLR_INTR = 1,
STS_PORT_WIDTH_SBE_ERROR = 1,
STS_PORT_WIDTH_DBE_ERROR = 1,
STS_PORT_WIDTH_SBE_COUNT = 8,
STS_PORT_WIDTH_DBE_COUNT = 8,
STS_PORT_WIDTH_CORR_DROP_ERROR = 1,
STS_PORT_WIDTH_CORR_DROP_COUNT = 8
)
(
ctl_clk,
ctl_reset_n,
// MMR Interface
cfg_interface_width,
cfg_enable_ecc,
cfg_gen_sbe,
cfg_gen_dbe,
cfg_enable_intr,
cfg_mask_sbe_intr,
cfg_mask_dbe_intr,
cfg_mask_corr_dropped_intr,
cfg_clr_intr,
// Wdata & Rdata Interface Inputs
wdatap_dm,
wdatap_data,
wdatap_rmw_partial_data,
wdatap_rmw_correct_data,
wdatap_rmw_partial,
wdatap_rmw_correct,
wdatap_ecc_code,
wdatap_ecc_code_overwrite,
rdatap_rcvd_addr,
rdatap_rcvd_cmd,
rdatap_rcvd_corr_dropped,
// AFI Interface Inputs
afi_rdata,
afi_rdata_valid,
// Wdata & Rdata Interface Outputs
ecc_rdata,
ecc_rdata_valid,
// AFI Inteface Outputs
ecc_dm,
ecc_wdata,
// ECC Error Information
ecc_sbe,
ecc_dbe,
ecc_code,
ecc_interrupt,
// MMR ECC Information
sts_sbe_error,
sts_dbe_error,
sts_sbe_count,
sts_dbe_count,
sts_err_addr,
sts_corr_dropped,
sts_corr_dropped_count,
sts_corr_dropped_addr
);
//--------------------------------------------------------------------------------------------------------
//
// Important Note:
//
// This block is coded with the following consideration in mind
// - Parameter
// - maximum LOCAL_DATA_WIDTH will be (40 * DWIDTH_RATIO)
// - maximum ECC_DATA_WIDTH will be (40 * DWIDTH_RATIO)
// - MMR configuration
// - ECC option disabled:
// - maximum DQ width is 40
// - maximum LOCAL_DATA width is (40 * DWIDTH_RATIO)
// - WDATAP_DATA and ECC_DATA size will match (no ECC code)
// - ECC option enabled:
// - maximum DQ width is 40
// - maximum LOCAL_DATA width is (32 * DWIDTH_RATIO)
// - WDATAP_DATA width will be (8 * DWIDTH_RATIO) lesser than ECC_DATA (ECC code)
//
// Block level diagram
// -----------------------------------
// Write Data Path (Per DRATE)
// -----------------------------------
// __________ ___________ ___________
// | | | | | |
// Local Write Data | Data | | | | |
// ---- 40 bits ---->| Mask |---- 32 bits ---->| Encoder |---- 40 bits ---->| ECC MUX |---- 40 bits ---->
// | | | | | | |
// | |__________| |___________| |___________|
// | ^
// |---------------------------------- 40 bits ---------------------------|
//
//
// -----------------------------------
// Read Data Path (Per DRATE)
// -----------------------------------
// __________ ___________ ___________
// | | | | | |
// AFI Read Data | Data | | | | |
// ---- 40 bits ---->| Mask |---- 40 bits ---->| Decoder |---- 32 bits ---->| ECC MUX |---- 40 bits ---->
// | | | | | | |
// | |__________| |___________| |___________|
// | ^
// |---------------------------------- 40 bits ---------------------------|
//
//--------------------------------------------------------------------------------------------------------
localparam CFG_MEM_IF_DQ_PER_DQS = CFG_MEM_IF_DQ_WIDTH / CFG_MEM_IF_DQS_WIDTH;
localparam CFG_ECC_DATA_WIDTH = CFG_MEM_IF_DQ_WIDTH * CFG_DWIDTH_RATIO;
localparam CFG_LOCAL_DM_WIDTH = CFG_LOCAL_DATA_WIDTH / CFG_MEM_IF_DQ_PER_DQS;
localparam CFG_ECC_DM_WIDTH = CFG_ECC_DATA_WIDTH / CFG_MEM_IF_DQ_PER_DQS;
localparam CFG_LOCAL_DATA_PER_WORD_WIDTH = CFG_LOCAL_DATA_WIDTH / CFG_ECC_MULTIPLES;
localparam CFG_LOCAL_DM_PER_WORD_WIDTH = CFG_LOCAL_DM_WIDTH / CFG_ECC_MULTIPLES;
localparam CFG_ECC_DATA_PER_WORD_WIDTH = CFG_ECC_DATA_WIDTH / CFG_ECC_MULTIPLES;
localparam CFG_ECC_DM_PER_WORD_WIDTH = CFG_ECC_DM_WIDTH / CFG_ECC_MULTIPLES;
localparam CFG_MMR_DRAM_DATA_WIDTH = CFG_PORT_WIDTH_INTERFACE_WIDTH;
localparam CFG_MMR_LOCAL_DATA_WIDTH = CFG_PORT_WIDTH_INTERFACE_WIDTH;
localparam CFG_MMR_DRAM_DM_WIDTH = CFG_PORT_WIDTH_INTERFACE_WIDTH - 2; // Minus 3 because byte enable will be divided by 4/8
localparam CFG_MMR_LOCAL_DM_WIDTH = CFG_PORT_WIDTH_INTERFACE_WIDTH - 2; // Minus 3 because byte enable will be divided by 4/8
// The following 2 parameters should match!
localparam CFG_ENCODER_DATA_WIDTH = CFG_ECC_DATA_PER_WORD_WIDTH; // supports only 24, 40 and 72
localparam CFG_DECODER_DATA_WIDTH = CFG_ECC_DATA_PER_WORD_WIDTH; // supports only 24, 40 and 72
input ctl_clk;
input ctl_reset_n;
// MMR Interface
input [CFG_PORT_WIDTH_INTERFACE_WIDTH - 1 : 0] cfg_interface_width;
input [CFG_PORT_WIDTH_ENABLE_ECC - 1 : 0] cfg_enable_ecc;
input [CFG_PORT_WIDTH_GEN_SBE - 1 : 0] cfg_gen_sbe;
input [CFG_PORT_WIDTH_GEN_DBE - 1 : 0] cfg_gen_dbe;
input [CFG_PORT_WIDTH_ENABLE_INTR - 1 : 0] cfg_enable_intr;
input [CFG_PORT_WIDTH_MASK_SBE_INTR - 1 : 0] cfg_mask_sbe_intr;
input [CFG_PORT_WIDTH_MASK_DBE_INTR - 1 : 0] cfg_mask_dbe_intr;
input [CFG_PORT_WIDTH_MASK_CORR_DROPPED_INTR - 1 : 0] cfg_mask_corr_dropped_intr;
input [CFG_PORT_WIDTH_CLR_INTR - 1 : 0] cfg_clr_intr;
// Wdata & Rdata Interface Inputs
input [CFG_LOCAL_DM_WIDTH - 1 : 0] wdatap_dm;
input [CFG_LOCAL_DATA_WIDTH - 1 : 0] wdatap_data;
input [CFG_LOCAL_DATA_WIDTH - 1 : 0] wdatap_rmw_partial_data;
input [CFG_LOCAL_DATA_WIDTH - 1 : 0] wdatap_rmw_correct_data;
input wdatap_rmw_partial;
input wdatap_rmw_correct;
input [CFG_ECC_MULTIPLES * CFG_ECC_CODE_WIDTH - 1 : 0] wdatap_ecc_code;
input [CFG_ECC_MULTIPLES - 1 : 0] wdatap_ecc_code_overwrite;
input [CFG_LOCAL_ADDR_WIDTH - 1 : 0] rdatap_rcvd_addr;
input rdatap_rcvd_cmd;
input rdatap_rcvd_corr_dropped;
// AFI Interface Inputs
input [CFG_ECC_DATA_WIDTH - 1 : 0] afi_rdata;
input [CFG_DWIDTH_RATIO / 2 - 1 : 0] afi_rdata_valid;
// Wdata & Rdata Interface Outputs
output [CFG_LOCAL_DATA_WIDTH - 1 : 0] ecc_rdata;
output ecc_rdata_valid;
// AFI Inteface Outputs
output [CFG_ECC_DM_WIDTH - 1 : 0] ecc_dm;
output [CFG_ECC_DATA_WIDTH - 1 : 0] ecc_wdata;
// ECC Error Information
output [CFG_ECC_MULTIPLES - 1 : 0] ecc_sbe;
output [CFG_ECC_MULTIPLES - 1 : 0] ecc_dbe;
output [CFG_ECC_MULTIPLES * CFG_ECC_CODE_WIDTH - 1 : 0] ecc_code;
output ecc_interrupt;
// MMR ECC Information
output [STS_PORT_WIDTH_SBE_ERROR - 1 : 0] sts_sbe_error;
output [STS_PORT_WIDTH_DBE_ERROR - 1 : 0] sts_dbe_error;
output [STS_PORT_WIDTH_SBE_COUNT - 1 : 0] sts_sbe_count;
output [STS_PORT_WIDTH_DBE_COUNT - 1 : 0] sts_dbe_count;
output [CFG_LOCAL_ADDR_WIDTH - 1 : 0] sts_err_addr;
output [STS_PORT_WIDTH_CORR_DROP_ERROR - 1 : 0] sts_corr_dropped;
output [STS_PORT_WIDTH_CORR_DROP_COUNT - 1 : 0] sts_corr_dropped_count;
output [CFG_LOCAL_ADDR_WIDTH - 1 : 0] sts_corr_dropped_addr;
//--------------------------------------------------------------------------------------------------------
//
// [START] Register & Wires
//
//--------------------------------------------------------------------------------------------------------
// Output registers
reg [CFG_LOCAL_DATA_WIDTH - 1 : 0] ecc_rdata;
reg ecc_rdata_valid;
reg [CFG_ECC_DM_WIDTH - 1 : 0] ecc_dm;
reg [CFG_ECC_DATA_WIDTH - 1 : 0] ecc_wdata;
reg [CFG_ECC_MULTIPLES - 1 : 0] ecc_sbe;
reg [CFG_ECC_MULTIPLES - 1 : 0] ecc_dbe;
reg [CFG_ECC_MULTIPLES * CFG_ECC_CODE_WIDTH - 1 : 0] ecc_code;
reg ecc_interrupt;
reg [STS_PORT_WIDTH_SBE_ERROR - 1 : 0] sts_sbe_error;
reg [STS_PORT_WIDTH_DBE_ERROR - 1 : 0] sts_dbe_error;
reg [STS_PORT_WIDTH_SBE_COUNT - 1 : 0] sts_sbe_count;
reg [STS_PORT_WIDTH_DBE_COUNT - 1 : 0] sts_dbe_count;
reg [CFG_LOCAL_ADDR_WIDTH - 1 : 0] sts_err_addr;
reg [STS_PORT_WIDTH_CORR_DROP_ERROR - 1 : 0] sts_corr_dropped;
reg [STS_PORT_WIDTH_CORR_DROP_COUNT - 1 : 0] sts_corr_dropped_count;
reg [CFG_LOCAL_ADDR_WIDTH - 1 : 0] sts_corr_dropped_addr;
// Common
reg [CFG_MMR_DRAM_DATA_WIDTH - 1 : 0] cfg_dram_data_width;
reg [CFG_MMR_LOCAL_DATA_WIDTH - 1 : 0] cfg_local_data_width;
reg [CFG_MMR_DRAM_DM_WIDTH - 1 : 0] cfg_dram_dm_width;
reg [CFG_MMR_LOCAL_DM_WIDTH - 1 : 0] cfg_local_dm_width;
// Input Logic
reg [CFG_LOCAL_DATA_WIDTH - 1 : 0] int_encoder_input_data;
reg [CFG_LOCAL_DATA_WIDTH - 1 : 0] int_encoder_input_rmw_partial_data;
reg [CFG_LOCAL_DATA_WIDTH - 1 : 0] int_encoder_input_rmw_correct_data;
reg int_encoder_input_rmw_partial;
reg int_encoder_input_rmw_correct;
reg wdatap_rmw_partial_r;
reg wdatap_rmw_correct_r;
reg [CFG_ECC_DATA_WIDTH - 1 : 0] int_decoder_input_data;
reg int_decoder_input_data_valid;
// Output Logic
reg [CFG_ECC_MULTIPLES - 1 : 0] int_sbe;
reg [CFG_ECC_MULTIPLES - 1 : 0] int_dbe;
reg [CFG_ECC_DM_WIDTH - 1 : 0] int_encoder_output_dm;
reg [CFG_ECC_DM_WIDTH - 1 : 0] int_encoder_output_dm_r;
wire [CFG_ECC_MULTIPLES - 1 : 0] int_decoder_output_data_valid;
reg [CFG_ECC_DATA_WIDTH - 1 : 0] int_encoder_output_data;
reg [CFG_ECC_DATA_WIDTH - 1 : 0] int_encoder_output_data_r;
wire [CFG_LOCAL_DATA_WIDTH - 1 : 0] int_decoder_output_data;
wire [CFG_ECC_MULTIPLES * CFG_ECC_CODE_WIDTH - 1 : 0] int_ecc_code;
// ECC specific logic
reg [1 : 0] inject_data_error;
reg int_sbe_detected;
reg int_dbe_detected;
wire int_be_detected;
reg int_sbe_store;
reg int_dbe_store;
reg int_sbe_valid;
reg int_dbe_valid;
reg int_sbe_valid_r;
reg int_dbe_valid_r;
reg int_ecc_interrupt;
wire int_interruptable_error_detected;
reg [STS_PORT_WIDTH_SBE_ERROR - 1 : 0] int_sbe_error;
reg [STS_PORT_WIDTH_DBE_ERROR - 1 : 0] int_dbe_error;
reg [STS_PORT_WIDTH_SBE_COUNT - 1 : 0] int_sbe_count;
reg [STS_PORT_WIDTH_DBE_COUNT - 1 : 0] int_dbe_count;
reg [CFG_LOCAL_ADDR_WIDTH - 1 : 0] int_err_addr ;
reg [STS_PORT_WIDTH_CORR_DROP_ERROR - 1 : 0] int_corr_dropped;
reg [STS_PORT_WIDTH_CORR_DROP_COUNT - 1 : 0] int_corr_dropped_count;
reg [CFG_LOCAL_ADDR_WIDTH - 1 : 0] int_corr_dropped_addr ;
reg int_corr_dropped_detected;
//--------------------------------------------------------------------------------------------------------
//
// [END] Register & Wires
//
//--------------------------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------------------------
//
// [START] Common
//
//--------------------------------------------------------------------------------------------------------
//----------------------------------------------------------------------------------------------------
// DRAM and local data width
//----------------------------------------------------------------------------------------------------
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
cfg_dram_data_width <= 0;
end
else
begin
cfg_dram_data_width <= cfg_interface_width;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
cfg_local_data_width <= 0;
end
else
begin
// Important note, if we set memory interface width (DQ width) to 8 and enable_ecc to 1,
// this will result in local data width of 0, this case is not supported
// this must be checked with assertion so that this case will not happen in regression
if (cfg_enable_ecc)
begin
cfg_local_data_width <= cfg_interface_width - CFG_ECC_CODE_WIDTH;
end
else
begin
cfg_local_data_width <= cfg_interface_width;
end
end
end
//----------------------------------------------------------------------------------------------------
// DRAM and local be width
//----------------------------------------------------------------------------------------------------
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
cfg_dram_dm_width <= 0;
end
else
begin
cfg_dram_dm_width <= cfg_dram_data_width / CFG_MEM_IF_DQ_PER_DQS;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
cfg_local_dm_width <= 0;
end
else
begin
cfg_local_dm_width <= cfg_local_data_width / CFG_MEM_IF_DQ_PER_DQS;
end
end
// Registered version
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
wdatap_rmw_partial_r <= 1'b0;
wdatap_rmw_correct_r <= 1'b0;
end
else
begin
wdatap_rmw_partial_r <= wdatap_rmw_partial;
wdatap_rmw_correct_r <= wdatap_rmw_correct;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_encoder_output_data_r <= 0;
int_encoder_output_dm_r <= 0;
end
else
begin
int_encoder_output_data_r <= int_encoder_output_data;
int_encoder_output_dm_r <= int_encoder_output_dm;
end
end
//--------------------------------------------------------------------------------------------------------
//
// [ENC] Common
//
//--------------------------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------------------------
//
// [START] Input Logic
//
//--------------------------------------------------------------------------------------------------------
//----------------------------------------------------------------------------------------------------
// Write data & byte enable from wdata_path
//----------------------------------------------------------------------------------------------------
always @ (*)
begin
int_encoder_input_data = wdatap_data;
int_encoder_input_rmw_partial_data = wdatap_rmw_partial_data;
int_encoder_input_rmw_correct_data = wdatap_rmw_correct_data;
if (CFG_ECC_ENC_REG)
begin
int_encoder_input_rmw_partial = wdatap_rmw_partial_r;
int_encoder_input_rmw_correct = wdatap_rmw_correct_r;
end
else
begin
int_encoder_input_rmw_partial = wdatap_rmw_partial;
int_encoder_input_rmw_correct = wdatap_rmw_correct;
end
end
generate
genvar i_drate;
for (i_drate = 0;i_drate < CFG_ECC_MULTIPLES;i_drate = i_drate + 1)
begin : encoder_input_dm_mux_per_dm_drate
wire [CFG_LOCAL_DM_PER_WORD_WIDTH-1:0] int_encoder_input_dm = wdatap_dm [(i_drate + 1) * CFG_LOCAL_DM_PER_WORD_WIDTH - 1 : i_drate * CFG_LOCAL_DM_PER_WORD_WIDTH];
wire int_encoder_input_dm_all_zeros = ~(|int_encoder_input_dm);
always @ (*)
begin
if (cfg_enable_ecc)
begin
if (int_encoder_input_dm_all_zeros)
begin
int_encoder_output_dm [ ((i_drate + 1) * CFG_ECC_DM_PER_WORD_WIDTH) - 1 : (i_drate * CFG_ECC_DM_PER_WORD_WIDTH)] = {{(CFG_ECC_DM_PER_WORD_WIDTH - CFG_LOCAL_DM_PER_WORD_WIDTH){1'b0}},int_encoder_input_dm};
end
else
begin
int_encoder_output_dm [ ((i_drate + 1) * CFG_ECC_DM_PER_WORD_WIDTH) - 1 : (i_drate * CFG_ECC_DM_PER_WORD_WIDTH)] = {{(CFG_ECC_DM_PER_WORD_WIDTH - CFG_LOCAL_DM_PER_WORD_WIDTH){1'b1}},int_encoder_input_dm};
end
end
else
begin
int_encoder_output_dm [ ((i_drate + 1) * CFG_ECC_DM_PER_WORD_WIDTH) - 1 : (i_drate * CFG_ECC_DM_PER_WORD_WIDTH)] = {{(CFG_ECC_DM_PER_WORD_WIDTH - CFG_LOCAL_DM_PER_WORD_WIDTH){1'b0}},int_encoder_input_dm};
end
end
end
endgenerate
//----------------------------------------------------------------------------------------------------
// Read data & read data valid from AFI
//----------------------------------------------------------------------------------------------------
always @ (*)
begin
int_decoder_input_data = afi_rdata;
end
always @ (*)
begin
int_decoder_input_data_valid = afi_rdata_valid [0];
end
//--------------------------------------------------------------------------------------------------------
//
// [END] Input Logic
//
//--------------------------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------------------------
//
// [START] Output Logic
//
//--------------------------------------------------------------------------------------------------------
//----------------------------------------------------------------------------------------------------
// Write data & byte enable to AFI interface
//----------------------------------------------------------------------------------------------------
always @ (*)
begin
ecc_wdata = int_encoder_output_data;
end
always @ (*)
begin
if (CFG_ECC_ENC_REG)
begin
ecc_dm = int_encoder_output_dm_r;
end
else
begin
ecc_dm = int_encoder_output_dm;
end
end
//----------------------------------------------------------------------------------------------------
// Read data to rdata_path
//----------------------------------------------------------------------------------------------------
always @ (*)
begin
ecc_rdata = int_decoder_output_data;
end
always @ (*)
begin
ecc_rdata_valid = |int_decoder_output_data_valid;
end
//----------------------------------------------------------------------------------------------------
// ECC specific logic
//----------------------------------------------------------------------------------------------------
// Single bit error
always @ (*)
begin
if (cfg_enable_ecc)
ecc_sbe = int_sbe;
else
ecc_sbe = 0;
end
// Double bit error
always @ (*)
begin
if (cfg_enable_ecc)
ecc_dbe = int_dbe;
else
ecc_dbe = 0;
end
// ECC code
always @ (*)
begin
if (cfg_enable_ecc)
ecc_code = int_ecc_code;
else
ecc_code = 0;
end
// Interrupt signal
always @ (*)
begin
ecc_interrupt = int_ecc_interrupt;
end
//----------------------------------------------------------------------------------------------------
// MMR ECC specific logic
//----------------------------------------------------------------------------------------------------
// Single bit error
always @ (*)
begin
sts_sbe_error = int_sbe_error;
end
// Double bit error
always @ (*)
begin
sts_dbe_error = int_dbe_error;
end
// Single bit error count
always @ (*)
begin
sts_sbe_count = int_sbe_count;
end
// Double bit error count
always @ (*)
begin
sts_dbe_count = int_dbe_count;
end
// Error address
always @ (*)
begin
sts_err_addr = int_err_addr;
end
// Correctable Error dropped
always @ (*)
begin
sts_corr_dropped = int_corr_dropped;
end
// Single bit error count
always @ (*)
begin
sts_corr_dropped_count = int_corr_dropped_count;
end
// Correctable Error dropped address
always @ (*)
begin
sts_corr_dropped_addr = int_corr_dropped_addr;
end
//--------------------------------------------------------------------------------------------------------
//
// [END] Output Logic
//
//--------------------------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------------------------
//
// [START] Encoder / Decoder Instantiation
//
//--------------------------------------------------------------------------------------------------------
//----------------------------------------------------------------------------------------------------
// Encoder
//----------------------------------------------------------------------------------------------------
generate
genvar m_drate;
for (m_drate = 0;m_drate < CFG_ECC_MULTIPLES;m_drate = m_drate + 1)
begin : encoder_inst_per_drate
wire [CFG_ENCODER_DATA_WIDTH - 1 : 0] input_data = {{CFG_ENCODER_DATA_WIDTH - CFG_LOCAL_DATA_PER_WORD_WIDTH{1'b0}}, int_encoder_input_data [(m_drate + 1) * CFG_LOCAL_DATA_PER_WORD_WIDTH - 1 : m_drate * CFG_LOCAL_DATA_PER_WORD_WIDTH]};
wire [CFG_ENCODER_DATA_WIDTH - 1 : 0] input_rmw_partial_data = {{CFG_ENCODER_DATA_WIDTH - CFG_LOCAL_DATA_PER_WORD_WIDTH{1'b0}}, int_encoder_input_rmw_partial_data [(m_drate + 1) * CFG_LOCAL_DATA_PER_WORD_WIDTH - 1 : m_drate * CFG_LOCAL_DATA_PER_WORD_WIDTH]};
wire [CFG_ENCODER_DATA_WIDTH - 1 : 0] input_rmw_correct_data = {{CFG_ENCODER_DATA_WIDTH - CFG_LOCAL_DATA_PER_WORD_WIDTH{1'b0}}, int_encoder_input_rmw_correct_data [(m_drate + 1) * CFG_LOCAL_DATA_PER_WORD_WIDTH - 1 : m_drate * CFG_LOCAL_DATA_PER_WORD_WIDTH]};
wire [CFG_ECC_CODE_WIDTH - 1 : 0] input_ecc_code = wdatap_ecc_code [(m_drate + 1) * CFG_ECC_CODE_WIDTH - 1 : m_drate * CFG_ECC_CODE_WIDTH];
wire input_ecc_code_overwrite = wdatap_ecc_code_overwrite [m_drate];
wire [CFG_ENCODER_DATA_WIDTH - 1 : 0] output_data;
wire [CFG_ENCODER_DATA_WIDTH - 1 : 0] output_rmw_partial_data;
wire [CFG_ENCODER_DATA_WIDTH - 1 : 0] output_rmw_correct_data;
always @ (*)
begin
if (int_encoder_input_rmw_partial)
begin
int_encoder_output_data [(m_drate + 1) * CFG_ECC_DATA_PER_WORD_WIDTH - 1 : m_drate * CFG_ECC_DATA_PER_WORD_WIDTH] = {output_rmw_partial_data [CFG_ECC_DATA_PER_WORD_WIDTH - 1 : 2], (output_rmw_partial_data [1 : 0] ^ inject_data_error [1 : 0])};
end
else if (int_encoder_input_rmw_correct)
begin
int_encoder_output_data [(m_drate + 1) * CFG_ECC_DATA_PER_WORD_WIDTH - 1 : m_drate * CFG_ECC_DATA_PER_WORD_WIDTH] = {output_rmw_correct_data [CFG_ECC_DATA_PER_WORD_WIDTH - 1 : 2], (output_rmw_correct_data [1 : 0] ^ inject_data_error [1 : 0])};
end
else
begin
int_encoder_output_data [(m_drate + 1) * CFG_ECC_DATA_PER_WORD_WIDTH - 1 : m_drate * CFG_ECC_DATA_PER_WORD_WIDTH] = {output_data [CFG_ECC_DATA_PER_WORD_WIDTH - 1 : 2], (output_data [1 : 0] ^ inject_data_error [1 : 0])};
end
end
alt_mem_ddrx_ecc_encoder #
(
.CFG_DATA_WIDTH (CFG_ENCODER_DATA_WIDTH ),
.CFG_ECC_CODE_WIDTH (CFG_ECC_CODE_WIDTH ),
.CFG_ECC_ENC_REG (CFG_ECC_ENC_REG ),
.CFG_MMR_DRAM_DATA_WIDTH (CFG_MMR_DRAM_DATA_WIDTH ),
.CFG_MMR_LOCAL_DATA_WIDTH (CFG_MMR_LOCAL_DATA_WIDTH ),
.CFG_PORT_WIDTH_ENABLE_ECC (CFG_PORT_WIDTH_ENABLE_ECC )
)
encoder_inst
(
.ctl_clk (ctl_clk ),
.ctl_reset_n (ctl_reset_n ),
.cfg_local_data_width (cfg_local_data_width ),
.cfg_dram_data_width (cfg_dram_data_width ),
.cfg_enable_ecc (cfg_enable_ecc ),
.input_data (input_data ),
.input_ecc_code (input_ecc_code ),
.input_ecc_code_overwrite (1'b0 ), // ECC code overwrite feature is only needed during RMW correct phase
.output_data (output_data )
);
alt_mem_ddrx_ecc_encoder #
(
.CFG_DATA_WIDTH (CFG_ENCODER_DATA_WIDTH ),
.CFG_ECC_CODE_WIDTH (CFG_ECC_CODE_WIDTH ),
.CFG_ECC_ENC_REG (CFG_ECC_ENC_REG ),
.CFG_MMR_DRAM_DATA_WIDTH (CFG_MMR_DRAM_DATA_WIDTH ),
.CFG_MMR_LOCAL_DATA_WIDTH (CFG_MMR_LOCAL_DATA_WIDTH ),
.CFG_PORT_WIDTH_ENABLE_ECC (CFG_PORT_WIDTH_ENABLE_ECC )
)
rmw_partial_encoder_inst
(
.ctl_clk (ctl_clk ),
.ctl_reset_n (ctl_reset_n ),
.cfg_local_data_width (cfg_local_data_width ),
.cfg_dram_data_width (cfg_dram_data_width ),
.cfg_enable_ecc (cfg_enable_ecc ),
.input_data (input_rmw_partial_data ),
.input_ecc_code (input_ecc_code ),
.input_ecc_code_overwrite (1'b0 ), // ECC code overwrite feature is only needed during RMW correct phase
.output_data (output_rmw_partial_data )
);
alt_mem_ddrx_ecc_encoder #
(
.CFG_DATA_WIDTH (CFG_ENCODER_DATA_WIDTH ),
.CFG_ECC_CODE_WIDTH (CFG_ECC_CODE_WIDTH ),
.CFG_ECC_ENC_REG (CFG_ECC_ENC_REG ),
.CFG_MMR_DRAM_DATA_WIDTH (CFG_MMR_DRAM_DATA_WIDTH ),
.CFG_MMR_LOCAL_DATA_WIDTH (CFG_MMR_LOCAL_DATA_WIDTH ),
.CFG_PORT_WIDTH_ENABLE_ECC (CFG_PORT_WIDTH_ENABLE_ECC )
)
rmw_correct_encoder_inst
(
.ctl_clk (ctl_clk ),
.ctl_reset_n (ctl_reset_n ),
.cfg_local_data_width (cfg_local_data_width ),
.cfg_dram_data_width (cfg_dram_data_width ),
.cfg_enable_ecc (cfg_enable_ecc ),
.input_data (input_rmw_correct_data ),
.input_ecc_code (input_ecc_code ),
.input_ecc_code_overwrite (input_ecc_code_overwrite ),
.output_data (output_rmw_correct_data )
);
end
endgenerate
//----------------------------------------------------------------------------------------------------
// Decoder
//----------------------------------------------------------------------------------------------------
generate
genvar n_drate;
for (n_drate = 0;n_drate < CFG_ECC_MULTIPLES;n_drate = n_drate + 1)
begin : decoder_inst_per_drate
wire err_corrected;
wire err_detected;
wire err_fatal;
wire err_sbe;
wire [CFG_DECODER_DATA_WIDTH - 1 : 0] input_data = {{CFG_DECODER_DATA_WIDTH - CFG_ECC_DATA_PER_WORD_WIDTH{1'b0}}, int_decoder_input_data [(n_drate + 1) * CFG_ECC_DATA_PER_WORD_WIDTH - 1 : n_drate * CFG_ECC_DATA_PER_WORD_WIDTH]};
wire input_data_valid = int_decoder_input_data_valid;
wire [CFG_DECODER_DATA_WIDTH - 1 : 0] output_data;
wire output_data_valid;
wire [CFG_ECC_CODE_WIDTH - 1 : 0] output_ecc_code;
assign int_decoder_output_data [(n_drate + 1) * CFG_LOCAL_DATA_PER_WORD_WIDTH - 1 : n_drate * CFG_LOCAL_DATA_PER_WORD_WIDTH] = output_data [CFG_LOCAL_DATA_PER_WORD_WIDTH - 1 : 0];
assign int_ecc_code [(n_drate + 1) * CFG_ECC_CODE_WIDTH - 1 : n_drate * CFG_ECC_CODE_WIDTH ] = output_ecc_code;
assign int_decoder_output_data_valid [n_drate] = output_data_valid;
alt_mem_ddrx_ecc_decoder #
(
.CFG_DATA_WIDTH (CFG_DECODER_DATA_WIDTH ),
.CFG_ECC_CODE_WIDTH (CFG_ECC_CODE_WIDTH ),
.CFG_ECC_DEC_REG (CFG_ECC_DEC_REG ),
.CFG_ECC_RDATA_REG (CFG_ECC_RDATA_REG ),
.CFG_MMR_DRAM_DATA_WIDTH (CFG_MMR_DRAM_DATA_WIDTH ),
.CFG_MMR_LOCAL_DATA_WIDTH (CFG_MMR_LOCAL_DATA_WIDTH ),
.CFG_PORT_WIDTH_ENABLE_ECC (CFG_PORT_WIDTH_ENABLE_ECC )
)
decoder_inst
(
.ctl_clk (ctl_clk ),
.ctl_reset_n (ctl_reset_n ),
.cfg_local_data_width (cfg_local_data_width ),
.cfg_dram_data_width (cfg_dram_data_width ),
.cfg_enable_ecc (cfg_enable_ecc ),
.input_data (input_data ),
.input_data_valid (input_data_valid ),
.output_data (output_data ),
.output_data_valid (output_data_valid ),
.output_ecc_code (output_ecc_code ),
.err_corrected (err_corrected ),
.err_detected (err_detected ),
.err_fatal (err_fatal ),
.err_sbe (err_sbe )
);
// Error detection
always @ (*)
begin
if (err_detected || err_sbe)
begin
if (err_corrected || err_sbe)
begin
int_sbe [n_drate] = 1'b1;
int_dbe [n_drate] = 1'b0;
end
else if (err_fatal)
begin
int_sbe [n_drate] = 1'b0;
int_dbe [n_drate] = 1'b1;
end
else
begin
int_sbe [n_drate] = 1'b0;
int_dbe [n_drate] = 1'b0;
end
end
else
begin
int_sbe [n_drate] = 1'b0;
int_dbe [n_drate] = 1'b0;
end
end
end
endgenerate
//--------------------------------------------------------------------------------------------------------
//
// [END] Encoder / Decoder Instantiation
//
//--------------------------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------------------------
//
// [START] ECC Specific Logic
//
//--------------------------------------------------------------------------------------------------------
//----------------------------------------------------------------------------------------------------
// Common Logic
//----------------------------------------------------------------------------------------------------
// Below information valid on same clock, when rdatap_rcvd_cmd is asserted (at end of every dram command)
// - int_sbe_detected
// - int_dbe_detected
// - int_be_detected
// - int_corr_dropped_detected
// - rdatap_rcvd_addr
//
// see SPR:362993
always @ (*)
begin
int_sbe_valid = |int_sbe & ecc_rdata_valid;
int_dbe_valid = |int_dbe & ecc_rdata_valid;
int_sbe_detected = ( int_sbe_store | int_sbe_valid_r ) & rdatap_rcvd_cmd;
int_dbe_detected = ( int_dbe_store | int_dbe_valid_r ) & rdatap_rcvd_cmd;
int_corr_dropped_detected = rdatap_rcvd_corr_dropped;
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
int_sbe_valid_r <= 0;
int_dbe_valid_r <= 0;
int_sbe_store <= 0;
int_dbe_store <= 0;
end
else
begin
int_sbe_valid_r <= int_sbe_valid;
int_dbe_valid_r <= int_dbe_valid;
int_sbe_store <= (int_sbe_store | int_sbe_valid_r) & ~rdatap_rcvd_cmd;
int_dbe_store <= (int_dbe_store | int_dbe_valid_r) & ~rdatap_rcvd_cmd;
end
end
//----------------------------------------------------------------------------------------------------
// Error Innjection Logic
//----------------------------------------------------------------------------------------------------
// Data error injection, this will cause output data to be injected with single/double bit error
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
inject_data_error <= 0;
end
else
begin
// Put DBE 1st so that when user sets both gen_sbe and gen_dbe, DBE will have higher priority
if (cfg_gen_dbe)
inject_data_error <= 2'b11;
else if (cfg_gen_sbe)
inject_data_error <= 2'b01;
else
inject_data_error <= 2'b00;
end
end
//----------------------------------------------------------------------------------------------------
// Single bit error
//----------------------------------------------------------------------------------------------------
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_sbe_error <= 1'b0;
end
else
begin
if (cfg_enable_ecc)
begin
if (int_sbe_detected)
int_sbe_error <= 1'b1;
else if (cfg_clr_intr)
int_sbe_error <= 1'b0;
end
else
begin
int_sbe_error <= 1'b0;
end
end
end
//----------------------------------------------------------------------------------------------------
// Single bit error count
//----------------------------------------------------------------------------------------------------
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_sbe_count <= 0;
end
else
begin
if (cfg_enable_ecc)
begin
if (cfg_clr_intr)
if (int_sbe_detected)
int_sbe_count <= 1;
else
int_sbe_count <= 0;
else if (int_sbe_detected)
int_sbe_count <= int_sbe_count + 1'b1;
end
else
begin
int_sbe_count <= {STS_PORT_WIDTH_SBE_COUNT{1'b0}};
end
end
end
//----------------------------------------------------------------------------------------------------
// Double bit error
//----------------------------------------------------------------------------------------------------
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_dbe_error <= 1'b0;
end
else
begin
if (cfg_enable_ecc)
begin
if (int_dbe_detected)
int_dbe_error <= 1'b1;
else if (cfg_clr_intr)
int_dbe_error <= 1'b0;
end
else
begin
int_dbe_error <= 1'b0;
end
end
end
//----------------------------------------------------------------------------------------------------
// Double bit error count
//----------------------------------------------------------------------------------------------------
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_dbe_count <= 0;
end
else
begin
if (cfg_enable_ecc)
begin
if (cfg_clr_intr)
if (int_dbe_detected)
int_dbe_count <= 1;
else
int_dbe_count <= 0;
else if (int_dbe_detected)
int_dbe_count <= int_dbe_count + 1'b1;
end
else
begin
int_dbe_count <= {STS_PORT_WIDTH_DBE_COUNT{1'b0}};
end
end
end
//----------------------------------------------------------------------------------------------------
// Error address
//----------------------------------------------------------------------------------------------------
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_err_addr <= 0;
end
else
begin
if (cfg_enable_ecc)
begin
if (int_be_detected)
int_err_addr <= rdatap_rcvd_addr;
else if (cfg_clr_intr)
int_err_addr <= 0;
end
else
begin
int_err_addr <= {CFG_LOCAL_ADDR_WIDTH{1'b0}};
end
end
end
//----------------------------------------------------------------------------------------------------
// Dropped Correctable Error
//----------------------------------------------------------------------------------------------------
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_corr_dropped <= 1'b0;
end
else
begin
if (cfg_enable_ecc)
begin
if (int_corr_dropped_detected)
int_corr_dropped <= 1'b1;
else if (cfg_clr_intr)
int_corr_dropped <= 1'b0;
end
else
begin
int_corr_dropped <= 1'b0;
end
end
end
//----------------------------------------------------------------------------------------------------
// Dropped Correctable Error count
//----------------------------------------------------------------------------------------------------
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_corr_dropped_count <= 0;
end
else
begin
if (cfg_enable_ecc)
begin
if (cfg_clr_intr)
if (int_corr_dropped_detected)
int_corr_dropped_count <= 1;
else
int_corr_dropped_count <= 0;
else if (int_corr_dropped_detected)
int_corr_dropped_count <= int_corr_dropped_count + 1'b1;
end
else
begin
int_corr_dropped_count <= {STS_PORT_WIDTH_CORR_DROP_COUNT{1'b0}};
end
end
end
//----------------------------------------------------------------------------------------------------
// Dropped Correctable Error address
//----------------------------------------------------------------------------------------------------
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_corr_dropped_addr <= 0;
end
else
begin
if (cfg_enable_ecc)
begin
if (int_corr_dropped_detected)
int_corr_dropped_addr <= rdatap_rcvd_addr;
else if (cfg_clr_intr)
int_corr_dropped_addr <= 0;
end
else
begin
int_corr_dropped_addr <= {CFG_LOCAL_ADDR_WIDTH{1'b0}};
end
end
end
//----------------------------------------------------------------------------------------------------
// Interrupt logic
//----------------------------------------------------------------------------------------------------
assign int_interruptable_error_detected = (int_sbe_detected & ~cfg_mask_sbe_intr) | (int_dbe_detected & ~cfg_mask_dbe_intr) | (int_corr_dropped_detected & ~cfg_mask_corr_dropped_intr);
assign int_be_detected = int_sbe_detected | int_dbe_detected;
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_ecc_interrupt <= 1'b0;
end
else
begin
if (cfg_enable_ecc && cfg_enable_intr)
begin
if (int_interruptable_error_detected)
int_ecc_interrupt <= 1'b1;
else if (cfg_clr_intr)
int_ecc_interrupt <= 1'b0;
end
else
begin
int_ecc_interrupt <= 1'b0;
end
end
end
//--------------------------------------------------------------------------------------------------------
//
// [END] ECC Specific Logic
//
//--------------------------------------------------------------------------------------------------------
endmodule
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module alt_mem_ddrx_fifo
# (
parameter
CTL_FIFO_DATA_WIDTH = 8,
CTL_FIFO_ADDR_WIDTH = 3
)
(
// general
ctl_clk,
ctl_reset_n,
// pop free fifo entry
get_valid,
get_ready,
get_data,
// push free fifo entry
put_valid,
put_ready,
put_data
);
// -----------------------------
// local parameter declarations
// -----------------------------
localparam CTL_FIFO_DEPTH = (2 ** CTL_FIFO_ADDR_WIDTH);
localparam CTL_FIFO_TYPE = "SCFIFO"; // SCFIFO, CUSTOM
// -----------------------------
// port declaration
// -----------------------------
input ctl_clk;
input ctl_reset_n;
// pop free fifo entry
input get_ready;
output get_valid;
output [CTL_FIFO_DATA_WIDTH-1:0] get_data;
// push free fifo entry
output put_ready;
input put_valid;
input [CTL_FIFO_DATA_WIDTH-1:0] put_data;
// -----------------------------
// port type declaration
// -----------------------------
wire get_valid;
wire get_ready;
wire [CTL_FIFO_DATA_WIDTH-1:0] get_data;
wire put_valid;
wire put_ready;
wire [CTL_FIFO_DATA_WIDTH-1:0] put_data;
// -----------------------------
// signal declaration
// -----------------------------
reg [CTL_FIFO_DATA_WIDTH-1:0] fifo [CTL_FIFO_DEPTH-1:0];
reg [CTL_FIFO_DEPTH-1:0] fifo_v;
wire fifo_get;
wire fifo_put;
wire fifo_empty;
wire fifo_full;
wire zero;
// -----------------------------
// module definition
// -----------------------------
assign fifo_get = get_valid & get_ready;
assign fifo_put = put_valid & put_ready;
assign zero = 1'b0;
generate
begin : gen_fifo_instance
if (CTL_FIFO_TYPE == "SCFIFO")
begin
assign get_valid = ~fifo_empty;
assign put_ready = ~fifo_full;
scfifo #(
.add_ram_output_register ( "ON" ),
.intended_device_family ( "Stratix IV" ),
.lpm_numwords ( CTL_FIFO_DEPTH ),
.lpm_showahead ( "ON" ),
.lpm_type ( "scfifo" ),
.lpm_width ( CTL_FIFO_DATA_WIDTH ),
.lpm_widthu ( CTL_FIFO_ADDR_WIDTH ),
.overflow_checking ( "OFF" ),
.underflow_checking ( "OFF" ),
.use_eab ( "ON" )
) scfifo_component (
.aclr (~ctl_reset_n),
.clock (ctl_clk),
.data (put_data),
.rdreq (fifo_get),
.wrreq (fifo_put),
.empty (fifo_empty),
.full (fifo_full),
.q (get_data),
.almost_empty (),
.almost_full (),
.sclr (zero),
.usedw ()
);
end
else // CTL_FIFO_TYPE == "CUSTOM"
begin
assign get_valid = fifo_v[0];
assign put_ready = ~fifo_v[CTL_FIFO_DEPTH-1];
assign get_data = fifo[0];
// put & get management
integer i;
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
for (i = 0; i < CTL_FIFO_DEPTH; i = i + 1'b1)
begin
// initialize every entry
fifo [i] <= 0;
fifo_v [i] <= 1'b0;
end
end
else
begin
// get request code must be above put request code
if (fifo_get)
begin
// on a get request, fifo entry is shifted to move next entry to head
for (i = 1; i < CTL_FIFO_DEPTH; i = i + 1'b1)
begin
fifo_v [i-1] <= fifo_v [i];
fifo [i-1] <= fifo [i];
end
fifo_v [CTL_FIFO_DEPTH-1] <= 0;
end
if (fifo_put)
begin
// on a put request, next empty fifo entry is written
if (~fifo_get)
begin
// put request only
for (i = 1; i < CTL_FIFO_DEPTH; i = i + 1'b1)
begin
if ( fifo_v[i-1] & ~fifo_v[i])
begin
fifo_v [i] <= 1'b1;
fifo [i] <= put_data;
end
end
if (~fifo_v[0])
begin
fifo_v [0] <= 1'b1;
fifo [0] <= put_data;
end
end
else
begin
// put & get request on same cycle
for (i = 1; i < CTL_FIFO_DEPTH; i = i + 1'b1)
begin
if ( fifo_v[i-1] & ~fifo_v[i])
begin
fifo_v [i-1] <= 1'b1;
fifo [i-1] <= put_data;
end
end
if (~fifo_v[0])
begin
$display("error - fifo underflow");
end
end
end
end
end
end
end
endgenerate
endmodule
//
// ASSERT
//
// fifo underflow
//
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1 ps / 1 ps
module alt_mem_ddrx_input_if
#(parameter
CFG_LOCAL_DATA_WIDTH = 64,
CFG_LOCAL_ID_WIDTH = 8,
CFG_LOCAL_ADDR_WIDTH = 33,
CFG_LOCAL_SIZE_WIDTH = 3,
CFG_MEM_IF_CHIP = 1,
CFG_AFI_INTF_PHASE_NUM = 2,
CFG_CTL_ARBITER_TYPE = "ROWCOL"
)
(
// cmd channel
itf_cmd_ready,
itf_cmd_valid,
itf_cmd,
itf_cmd_address,
itf_cmd_burstlen,
itf_cmd_id,
itf_cmd_priority,
itf_cmd_autopercharge,
itf_cmd_multicast,
// write data channel
itf_wr_data_ready,
itf_wr_data_valid,
itf_wr_data,
itf_wr_data_byte_en,
itf_wr_data_begin,
itf_wr_data_last,
itf_wr_data_id,
// read data channel
itf_rd_data_ready,
itf_rd_data_valid,
itf_rd_data,
itf_rd_data_error,
itf_rd_data_begin,
itf_rd_data_last,
itf_rd_data_id,
itf_rd_data_id_early,
itf_rd_data_id_early_valid,
// command generator
cmd_gen_full,
cmd_valid,
cmd_address,
cmd_write,
cmd_read,
cmd_multicast,
cmd_size,
cmd_priority,
cmd_autoprecharge,
cmd_id,
// write data path
wr_data_mem_full,
write_data_id,
write_data,
byte_en,
write_data_valid,
// read data path
read_data,
read_data_valid,
read_data_error,
read_data_localid,
read_data_begin,
read_data_last,
//side band
local_refresh_req,
local_refresh_chip,
local_deep_powerdn_req,
local_deep_powerdn_chip,
local_self_rfsh_req,
local_self_rfsh_chip,
local_refresh_ack,
local_deep_powerdn_ack,
local_power_down_ack,
local_self_rfsh_ack,
local_init_done,
bg_do_read,
bg_do_rmw_correct,
bg_do_rmw_partial,
bg_localid,
rfsh_req,
rfsh_chip,
deep_powerdn_req,
deep_powerdn_chip,
self_rfsh_req,
self_rfsh_chip,
rfsh_ack,
deep_powerdn_ack,
power_down_ack,
self_rfsh_ack,
init_done
);
localparam AFI_INTF_LOW_PHASE = 0;
localparam AFI_INTF_HIGH_PHASE = 1;
// command channel
output itf_cmd_ready;
input [CFG_LOCAL_ADDR_WIDTH-1:0] itf_cmd_address;
input itf_cmd_valid;
input itf_cmd;
input [CFG_LOCAL_SIZE_WIDTH-1:0] itf_cmd_burstlen;
input [CFG_LOCAL_ID_WIDTH - 1 : 0] itf_cmd_id;
input itf_cmd_priority;
input itf_cmd_autopercharge;
input itf_cmd_multicast;
// write data channel
output itf_wr_data_ready;
input itf_wr_data_valid;
input [CFG_LOCAL_DATA_WIDTH-1:0] itf_wr_data;
input [CFG_LOCAL_DATA_WIDTH/8-1:0] itf_wr_data_byte_en;
input itf_wr_data_begin;
input itf_wr_data_last;
input [CFG_LOCAL_ID_WIDTH-1:0] itf_wr_data_id;
// read data channel
input itf_rd_data_ready;
output itf_rd_data_valid;
output [CFG_LOCAL_DATA_WIDTH-1:0] itf_rd_data;
output itf_rd_data_error;
output itf_rd_data_begin;
output itf_rd_data_last;
output [CFG_LOCAL_ID_WIDTH-1:0] itf_rd_data_id;
output [CFG_LOCAL_ID_WIDTH-1:0] itf_rd_data_id_early;
output itf_rd_data_id_early_valid;
// command generator
input cmd_gen_full;
output cmd_valid;
output [CFG_LOCAL_ADDR_WIDTH-1:0] cmd_address;
output cmd_write;
output cmd_read;
output cmd_multicast;
output [CFG_LOCAL_SIZE_WIDTH-1:0] cmd_size;
output cmd_priority;
output cmd_autoprecharge;
output [CFG_LOCAL_ID_WIDTH-1:0] cmd_id;
// write data path
output [CFG_LOCAL_DATA_WIDTH-1:0] write_data;
output [CFG_LOCAL_DATA_WIDTH/8-1:0] byte_en;
output write_data_valid;
input wr_data_mem_full;
output [CFG_LOCAL_ID_WIDTH-1:0] write_data_id;
// read data path
input [CFG_LOCAL_DATA_WIDTH-1:0] read_data;
input read_data_valid;
input read_data_error;
input [CFG_LOCAL_ID_WIDTH-1:0]read_data_localid;
input read_data_begin;
input read_data_last;
//side band
input local_refresh_req;
input [CFG_MEM_IF_CHIP-1:0] local_refresh_chip;
input local_deep_powerdn_req;
input [CFG_MEM_IF_CHIP-1:0] local_deep_powerdn_chip;
input local_self_rfsh_req;
input [CFG_MEM_IF_CHIP-1:0] local_self_rfsh_chip;
output local_refresh_ack;
output local_deep_powerdn_ack;
output local_power_down_ack;
output local_self_rfsh_ack;
output local_init_done;
//side band
input [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_read;
input [CFG_LOCAL_ID_WIDTH - 1 : 0] bg_localid;
input [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_rmw_correct;
input [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_rmw_partial;
output rfsh_req;
output [CFG_MEM_IF_CHIP-1:0] rfsh_chip;
output deep_powerdn_req;
output [CFG_MEM_IF_CHIP-1:0] deep_powerdn_chip;
output self_rfsh_req;
output [CFG_MEM_IF_CHIP-1:0] self_rfsh_chip;
input rfsh_ack;
input deep_powerdn_ack;
input power_down_ack;
input self_rfsh_ack;
input init_done;
// command generator
wire cmd_priority;
wire [CFG_LOCAL_ADDR_WIDTH-1:0] cmd_address;
wire cmd_read;
wire cmd_write;
wire cmd_multicast;
wire cmd_gen_full;
wire cmd_valid;
wire itf_cmd_ready;
wire cmd_autoprecharge;
wire [CFG_LOCAL_SIZE_WIDTH-1:0] cmd_size;
//side band
wire [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_read;
wire [CFG_LOCAL_ID_WIDTH - 1 : 0] bg_localid;
wire [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_rmw_correct;
wire [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_rmw_partial;
wire rfsh_req;
wire [CFG_MEM_IF_CHIP-1:0] rfsh_chip;
wire deep_powerdn_req;
wire [CFG_MEM_IF_CHIP-1:0] deep_powerdn_chip;
wire self_rfsh_req;
//wire rfsh_ack;
//wire deep_powerdn_ack;
wire power_down_ack;
//wire self_rfsh_ack;
// wire init_done;
//write data path
wire itf_wr_data_ready;
wire [CFG_LOCAL_DATA_WIDTH-1:0] write_data;
wire write_data_valid;
wire [CFG_LOCAL_DATA_WIDTH/8-1:0] byte_en;
wire [CFG_LOCAL_ID_WIDTH-1:0] write_data_id;
//read data path
wire itf_rd_data_valid;
wire [CFG_LOCAL_DATA_WIDTH-1:0] itf_rd_data;
wire itf_rd_data_error;
wire itf_rd_data_begin;
wire itf_rd_data_last;
wire [CFG_LOCAL_ID_WIDTH-1:0] itf_rd_data_id;
wire [CFG_LOCAL_ID_WIDTH-1:0] itf_rd_data_id_early;
wire itf_rd_data_id_early_valid;
// commmand generator
assign cmd_priority = itf_cmd_priority;
assign cmd_address = itf_cmd_address;
assign cmd_multicast = itf_cmd_multicast;
assign cmd_size = itf_cmd_burstlen;
assign cmd_autoprecharge = itf_cmd_autopercharge;
assign cmd_id = itf_cmd_id;
// side band
assign rfsh_req = local_refresh_req;
assign rfsh_chip = local_refresh_chip;
assign deep_powerdn_req = local_deep_powerdn_req;
assign deep_powerdn_chip = local_deep_powerdn_chip;
assign self_rfsh_req = local_self_rfsh_req;
assign self_rfsh_chip = local_self_rfsh_chip;
assign local_refresh_ack = rfsh_ack;
assign local_deep_powerdn_ack = deep_powerdn_ack;
assign local_power_down_ack = power_down_ack;
assign local_self_rfsh_ack = self_rfsh_ack;
assign local_init_done = init_done;
//write data path
assign write_data = itf_wr_data;
assign byte_en = itf_wr_data_byte_en;
assign write_data_valid = itf_wr_data_valid;
assign write_data_id = itf_wr_data_id;
// read data path
assign itf_rd_data_id = read_data_localid;
assign itf_rd_data_error = read_data_error;
assign itf_rd_data_valid = read_data_valid;
assign itf_rd_data_begin = read_data_begin;
assign itf_rd_data_last = read_data_last;
assign itf_rd_data = read_data;
assign itf_rd_data_id_early = (itf_rd_data_id_early_valid) ? bg_localid : {CFG_LOCAL_ID_WIDTH{1'b0}};
//==============================================================================
// Logic below is to tie low itf_cmd_ready, itf_cmd_valid and itf_wr_data_ready when local_init_done is low
assign itf_cmd_ready = ~cmd_gen_full & local_init_done;
assign itf_wr_data_ready = ~wr_data_mem_full & local_init_done;
assign cmd_read = ~itf_cmd & itf_cmd_valid & local_init_done;
assign cmd_write = itf_cmd & itf_cmd_valid & local_init_done;
assign cmd_valid = itf_cmd_valid & local_init_done;
generate
begin : gen_rd_data_id_early_valid
if (CFG_CTL_ARBITER_TYPE == "COLROW")
begin
assign itf_rd_data_id_early_valid = bg_do_read [AFI_INTF_LOW_PHASE] & ~(bg_do_rmw_correct[AFI_INTF_LOW_PHASE]|bg_do_rmw_partial[AFI_INTF_LOW_PHASE]);
end
else
begin
assign itf_rd_data_id_early_valid = bg_do_read [AFI_INTF_HIGH_PHASE] & ~(bg_do_rmw_correct[AFI_INTF_HIGH_PHASE]|bg_do_rmw_partial[AFI_INTF_HIGH_PHASE]);
end
end
endgenerate
endmodule
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
//altera message_off 10230
module alt_mem_ddrx_list
# (
// module parameter port list
parameter
CTL_LIST_WIDTH = 3, // number of dram commands that can be tracked at a time
CTL_LIST_DEPTH = 8,
CTL_LIST_INIT_VALUE_TYPE = "INCR", // INCR, ZERO
CTL_LIST_INIT_VALID = "VALID" // VALID, INVALID
)
(
// port list
ctl_clk,
ctl_reset_n,
// pop free list
list_get_entry_valid,
list_get_entry_ready,
list_get_entry_id,
list_get_entry_id_vector,
// push free list
list_put_entry_valid,
list_put_entry_ready,
list_put_entry_id
);
// -----------------------------
// port declaration
// -----------------------------
input ctl_clk;
input ctl_reset_n;
// pop free list
input list_get_entry_ready;
output list_get_entry_valid;
output [CTL_LIST_WIDTH-1:0] list_get_entry_id;
output [CTL_LIST_DEPTH-1:0] list_get_entry_id_vector;
// push free list
output list_put_entry_ready;
input list_put_entry_valid;
input [CTL_LIST_WIDTH-1:0] list_put_entry_id;
// -----------------------------
// port type declaration
// -----------------------------
reg list_get_entry_valid;
wire list_get_entry_ready;
reg [CTL_LIST_WIDTH-1:0] list_get_entry_id;
reg [CTL_LIST_DEPTH-1:0] list_get_entry_id_vector;
wire list_put_entry_valid;
reg list_put_entry_ready;
wire [CTL_LIST_WIDTH-1:0] list_put_entry_id;
// -----------------------------
// signal declaration
// -----------------------------
reg [CTL_LIST_WIDTH-1:0] list [CTL_LIST_DEPTH-1:0];
reg list_v [CTL_LIST_DEPTH-1:0];
reg [CTL_LIST_DEPTH-1:0] list_vector;
wire list_get = list_get_entry_valid & list_get_entry_ready;
wire list_put = list_put_entry_valid & list_put_entry_ready;
// -----------------------------
// module definition
// -----------------------------
// generate interface signals
always @ (*)
begin
// connect interface signals to list head & tail
list_get_entry_valid = list_v[0];
list_get_entry_id = list[0];
list_get_entry_id_vector = list_vector;
list_put_entry_ready = ~list_v[CTL_LIST_DEPTH-1];
end
// list put & get management
integer i;
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
for (i = 0; i < CTL_LIST_DEPTH; i = i + 1'b1)
begin
// initialize every entry
if (CTL_LIST_INIT_VALUE_TYPE == "INCR")
begin
list [i] <= i;
end
else
begin
list [i] <= {CTL_LIST_WIDTH{1'b0}};
end
if (CTL_LIST_INIT_VALID == "VALID")
begin
list_v [i] <= 1'b1;
end
else
begin
list_v [i] <= 1'b0;
end
end
list_vector <= {CTL_LIST_DEPTH{1'b0}};
end
else
begin
// get request code must be above put request code
if (list_get)
begin
// on a get request, list is shifted to move next entry to head
for (i = 1; i < CTL_LIST_DEPTH; i = i + 1'b1)
begin
list_v [i-1] <= list_v [i];
list [i-1] <= list [i];
end
list_v [CTL_LIST_DEPTH-1] <= 0;
for (i = 0; i < CTL_LIST_DEPTH;i = i + 1'b1)
begin
if (i == list [1])
begin
list_vector [i] <= 1'b1;
end
else
begin
list_vector [i] <= 1'b0;
end
end
end
if (list_put)
begin
// on a put request, next empty list entry is written
if (~list_get)
begin
// put request only
for (i = 1; i < CTL_LIST_DEPTH; i = i + 1'b1)
begin
if ( list_v[i-1] & ~list_v[i])
begin
list_v [i] <= 1'b1;
list [i] <= list_put_entry_id;
end
end
if (~list_v[0])
begin
list_v [0] <= 1'b1;
list [0] <= list_put_entry_id;
for (i = 0; i < CTL_LIST_DEPTH;i = i + 1'b1)
begin
if (i == list_put_entry_id)
begin
list_vector [i] <= 1'b1;
end
else
begin
list_vector [i] <= 1'b0;
end
end
end
end
else
begin
// put & get request on same cycle
for (i = 1; i < CTL_LIST_DEPTH; i = i + 1'b1)
begin
if (list_v[i-1] & ~list_v[i])
begin
list_v [i-1] <= 1'b1;
list [i-1] <= list_put_entry_id;
end
end
// if (~list_v[0])
// begin
// $display("error - list underflow");
// end
for (i = 0; i < CTL_LIST_DEPTH;i = i + 1'b1)
begin
if (list_v[0] & ~list_v[1])
begin
if (i == list_put_entry_id)
begin
list_vector [i] <= 1'b1;
end
else
begin
list_vector [i] <= 1'b0;
end
end
else
begin
if (i == list [1])
begin
list_vector [i] <= 1'b1;
end
else
begin
list_vector [i] <= 1'b0;
end
end
end
end
end
end
end
endmodule
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
///////////////////////////////////////////////////////////////////////////////
// Title : LPDDR2 controller address and command decoder
//
// File : alt_mem_ddrx_lpddr2_addr_cmd.v
//
// Abstract : LPDDR2 Address and command decoder
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
module alt_mem_ddrx_lpddr2_addr_cmd
# (parameter
// Global parameters
CFG_PORT_WIDTH_OUTPUT_REGD = 1,
CFG_MEM_IF_CHIP = 1,
CFG_MEM_IF_CKE_WIDTH = 1, // same width as CS_WIDTH
CFG_MEM_IF_ADDR_WIDTH = 20,
CFG_MEM_IF_ROW_WIDTH = 15, // max supported row bits
CFG_MEM_IF_COL_WIDTH = 12, // max supported column bits
CFG_MEM_IF_BA_WIDTH = 3, // max supported bank bits
CFG_DWIDTH_RATIO = 2
)
(
ctl_clk,
ctl_reset_n,
ctl_cal_success,
//run-time configuration interface
cfg_output_regd,
// AFI interface (Signals from Arbiter block)
do_write,
do_read,
do_auto_precharge,
do_activate,
do_precharge,
do_precharge_all,
do_refresh,
do_self_refresh,
do_power_down,
do_lmr,
do_lmr_read, //Currently does not exist in arbiter
do_refresh_1bank, //Currently does not exist in arbiter
do_burst_terminate, //Currently does not exist in arbiter
do_deep_pwrdwn, //Currently does not exist in arbiter
// address information
to_chip, // active high input (one hot)
to_bank,
to_row,
to_col,
to_lmr,
lmr_opcode,
//output
afi_cke,
afi_cs_n,
afi_addr,
afi_rst_n
);
input ctl_clk;
input ctl_reset_n;
input ctl_cal_success;
//run-time configuration input
input [CFG_PORT_WIDTH_OUTPUT_REGD -1:0] cfg_output_regd;
// Arbiter command inputs
input do_write;
input do_read;
input do_auto_precharge;
input do_activate;
input do_precharge;
input [CFG_MEM_IF_CHIP-1:0] do_precharge_all;
input [CFG_MEM_IF_CHIP-1:0] do_refresh;
input [CFG_MEM_IF_CHIP-1:0] do_self_refresh;
input [CFG_MEM_IF_CHIP-1:0] do_power_down;
input [CFG_MEM_IF_CHIP-1:0] do_deep_pwrdwn;
input do_lmr;
input do_lmr_read;
input do_refresh_1bank;
input do_burst_terminate;
input [CFG_MEM_IF_CHIP-1:0] to_chip;
input [CFG_MEM_IF_BA_WIDTH-1:0] to_bank;
input [CFG_MEM_IF_ROW_WIDTH-1:0] to_row;
input [CFG_MEM_IF_COL_WIDTH-1:0] to_col;
input [7:0] to_lmr;
input [7:0] lmr_opcode;
//output
output [(CFG_MEM_IF_CKE_WIDTH * (CFG_DWIDTH_RATIO/2)) - 1:0] afi_cke;
output [(CFG_MEM_IF_CHIP * (CFG_DWIDTH_RATIO/2)) - 1:0] afi_cs_n;
output [(CFG_MEM_IF_ADDR_WIDTH * (CFG_DWIDTH_RATIO/2)) - 1:0] afi_addr;
output [(CFG_DWIDTH_RATIO/2) - 1:0] afi_rst_n;
wire do_write;
wire do_read;
wire do_auto_precharge;
wire do_activate;
wire do_precharge;
wire [CFG_MEM_IF_CHIP-1:0] do_precharge_all;
wire [CFG_MEM_IF_CHIP-1:0] do_refresh;
wire [CFG_MEM_IF_CHIP-1:0] do_self_refresh;
wire [CFG_MEM_IF_CHIP-1:0] do_power_down;
wire [CFG_MEM_IF_CHIP-1:0] do_deep_pwrdwn;
wire do_lmr;
wire do_lmr_read;
wire do_refresh_1bank;
wire do_burst_terminate;
reg [2:0] temp_bank_addr;
reg [14:0] temp_row_addr;
reg [11:0] temp_col_addr;
wire [(CFG_MEM_IF_CKE_WIDTH * (CFG_DWIDTH_RATIO/2)) - 1:0] afi_cke;
wire [(CFG_MEM_IF_CHIP * (CFG_DWIDTH_RATIO/2)) - 1:0] afi_cs_n;
wire [(CFG_MEM_IF_ADDR_WIDTH * (CFG_DWIDTH_RATIO/2)) - 1:0] afi_addr;
wire [(CFG_DWIDTH_RATIO/2) - 1:0] afi_rst_n;
reg [(CFG_MEM_IF_CKE_WIDTH) - 1:0] int_cke;
reg [(CFG_MEM_IF_CKE_WIDTH) - 1:0] int_cke_r;
reg [(CFG_MEM_IF_CHIP) - 1:0] int_cs_n;
reg [(CFG_MEM_IF_ADDR_WIDTH) - 1:0] int_addr;
reg [(CFG_MEM_IF_CKE_WIDTH) - 1:0] combi_cke;
reg [(CFG_MEM_IF_CHIP) - 1:0] combi_cs_n;
reg [(CFG_MEM_IF_ADDR_WIDTH) - 1:0] combi_addr;
reg [(CFG_MEM_IF_CKE_WIDTH) - 1:0] combi_cke_r;
reg [(CFG_MEM_IF_CHIP) - 1:0] combi_cs_n_r;
reg [(CFG_MEM_IF_ADDR_WIDTH) - 1:0] combi_addr_r;
reg [CFG_MEM_IF_CHIP-1:0] chip_in_self_refresh;
assign afi_rst_n = {(CFG_DWIDTH_RATIO/2){1'b1}};
generate
if (CFG_DWIDTH_RATIO == 2) begin
assign afi_cke = int_cke;
assign afi_cs_n = int_cs_n;
assign afi_addr = int_addr;
end
else begin
assign afi_cke = {int_cke,int_cke};
assign afi_cs_n = (do_burst_terminate)? {int_cs_n,int_cs_n} :{int_cs_n,{CFG_MEM_IF_CHIP{1'b1}}};
assign afi_addr = {int_addr,int_addr};
end
endgenerate
// need half rate code to adjust for half rate cke or cs
always @(posedge ctl_clk, negedge ctl_reset_n) // toogles cs_n for only one cyle when state machine continues to stay in slf rfsh mode or DPD
begin
if (!ctl_reset_n)
chip_in_self_refresh <= {(CFG_MEM_IF_CHIP){1'b0}};
else
if ((do_self_refresh) || (do_deep_pwrdwn))
chip_in_self_refresh <= do_self_refresh | do_deep_pwrdwn;
else
chip_in_self_refresh <= {(CFG_MEM_IF_CHIP){1'b0}};
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
combi_cke_r <= {CFG_MEM_IF_CKE_WIDTH{1'b1}} ;
combi_cs_n_r <= {CFG_MEM_IF_CHIP{1'b1}} ;
combi_addr_r <= {CFG_MEM_IF_ADDR_WIDTH{1'b0}};
end
else
begin
combi_cke_r <= combi_cke ;
combi_cs_n_r <= combi_cs_n ;
combi_addr_r <= combi_addr ;
end
end
always @(*)
begin
if (cfg_output_regd)
begin
int_cke = combi_cke_r;
int_cs_n = combi_cs_n_r;
int_addr = combi_addr_r;
end
else
begin
int_cke = combi_cke;
int_cs_n = combi_cs_n;
int_addr = combi_addr;
end
end
always @ (*)
begin
temp_row_addr = {CFG_MEM_IF_ROW_WIDTH{1'b0}} ;
temp_col_addr = {CFG_MEM_IF_COL_WIDTH{1'b0}} ;
temp_bank_addr = {CFG_MEM_IF_BA_WIDTH {1'b0}} ;
temp_row_addr = to_row ;
temp_col_addr = to_col ;
temp_bank_addr = to_bank;
end
//CKE generation block
always @(*)
begin
if (ctl_cal_success)
begin
combi_cke = ~(do_self_refresh | do_power_down | do_deep_pwrdwn);
end
else
begin
combi_cke = {(CFG_MEM_IF_CKE_WIDTH){1'b1}};
end
end
always @(*)
begin
if (ctl_cal_success)
begin
//combi_cke = {(CFG_MEM_IF_CKE_WIDTH){1'b1}};
combi_cs_n = {(CFG_MEM_IF_CHIP){1'b1}};
combi_addr = {(CFG_MEM_IF_ADDR_WIDTH){1'b0}};
if (|do_refresh)
begin
//combi_cke = {(CFG_MEM_IF_CKE_WIDTH){1'b1}};
combi_cs_n = ~do_refresh;
combi_addr[3:0] = 4'b1100;
combi_addr[(CFG_MEM_IF_ADDR_WIDTH/2) - 1 : 4] = {(CFG_MEM_IF_ADDR_WIDTH/2 - 4){1'b0}};
combi_addr[CFG_MEM_IF_ADDR_WIDTH - 1 : 10] = {(CFG_MEM_IF_ADDR_WIDTH/2){1'b0}};
end
if (do_refresh_1bank)
begin
//combi_cke = {(CFG_MEM_IF_CKE_WIDTH){1'b1}};
combi_cs_n = ~to_chip;
combi_addr[3:0] = 4'b0100;
combi_addr[(CFG_MEM_IF_ADDR_WIDTH/2) - 1 : 4] = {(CFG_MEM_IF_ADDR_WIDTH/2 - 4){1'b0}};
combi_addr[CFG_MEM_IF_ADDR_WIDTH - 1 : 10] = {(CFG_MEM_IF_ADDR_WIDTH/2){1'b0}};
end
if ((|do_precharge_all) || do_precharge)
begin
//combi_cke = {(CFG_MEM_IF_CKE_WIDTH){1'b1}};
combi_cs_n = ~ (do_precharge_all|do_precharge);
combi_addr[3:0] = 4'b1011;
combi_addr[(CFG_MEM_IF_ADDR_WIDTH/2) - 1 : 4] = {temp_bank_addr,2'b00,(|do_precharge_all)};
combi_addr[CFG_MEM_IF_ADDR_WIDTH - 1 : 10] = {(CFG_MEM_IF_ADDR_WIDTH/2){1'b0}};
end
if (do_activate)
begin
//combi_cke = {(CFG_MEM_IF_CKE_WIDTH){1'b1}};
combi_cs_n = ~to_chip;
combi_addr[3:0] = {temp_row_addr[9:8],2'b10};
combi_addr[(CFG_MEM_IF_ADDR_WIDTH/2) - 1 : 4] = {temp_bank_addr,temp_row_addr[12:10]};
combi_addr[CFG_MEM_IF_ADDR_WIDTH - 1 : 10] = {temp_row_addr[14:13],temp_row_addr[7:0]};
end
if (do_write)
begin
//combi_cke = {(CFG_MEM_IF_CKE_WIDTH){1'b1}};
combi_cs_n = ~to_chip;
combi_addr[3:0] = 4'b0001;
combi_addr[(CFG_MEM_IF_ADDR_WIDTH/2) - 1 : 4] = {temp_bank_addr,temp_col_addr[2:1],1'b0};
combi_addr[CFG_MEM_IF_ADDR_WIDTH - 1 : 10] = {temp_col_addr[11:3],do_auto_precharge};
end
if (do_read)
begin
//combi_cke = {(CFG_MEM_IF_CKE_WIDTH){1'b1}};
combi_cs_n = ~to_chip;
combi_addr[3:0] = 4'b0101;
combi_addr[(CFG_MEM_IF_ADDR_WIDTH/2) - 1 : 4] = {temp_bank_addr,temp_col_addr[2:1],1'b0};
combi_addr[CFG_MEM_IF_ADDR_WIDTH - 1 : 10] = {temp_col_addr[11:3],do_auto_precharge};
end
if (|do_power_down)
begin
//combi_cke = ~do_power_down;
combi_cs_n = {(CFG_MEM_IF_CHIP){1'b1}};
combi_addr[3:0] = 4'b0000;
combi_addr[(CFG_MEM_IF_ADDR_WIDTH/2) - 1 : 4] = {(CFG_MEM_IF_ADDR_WIDTH/2 - 4){1'b0}};
combi_addr[CFG_MEM_IF_ADDR_WIDTH - 1 : 10] = {(CFG_MEM_IF_ADDR_WIDTH/2){1'b0}};
end
if (|do_deep_pwrdwn)
begin
//combi_cke = ~do_deep_pwrdwn;
combi_cs_n = ~do_deep_pwrdwn; // toogles cs_n for only one cyle when state machine continues to stay in DPD;
combi_addr[3:0] = 4'b0011;
combi_addr[(CFG_MEM_IF_ADDR_WIDTH/2) - 1 : 4] = {(CFG_MEM_IF_ADDR_WIDTH/2 - 4){1'b0}};
combi_addr[CFG_MEM_IF_ADDR_WIDTH - 1 : 10] = {(CFG_MEM_IF_ADDR_WIDTH/2){1'b0}};
end
if (|do_self_refresh)
begin
//combi_cke = ~do_self_refresh;
combi_cs_n = ~do_self_refresh; // toogles cs_n for only one cyle when state machine continues to stay in DPD;
combi_addr[3:0] = 4'b0100;
combi_addr[(CFG_MEM_IF_ADDR_WIDTH/2) - 1 : 4] = {(CFG_MEM_IF_ADDR_WIDTH/2 - 4){1'b0}};
combi_addr[CFG_MEM_IF_ADDR_WIDTH - 1 : 10] = {(CFG_MEM_IF_ADDR_WIDTH/2){1'b0}};
end
if (do_lmr)
begin
//combi_cke = {(CFG_MEM_IF_CKE_WIDTH){1'b1}};
combi_cs_n = ~to_chip;
combi_addr[3:0] = 4'b0000;
combi_addr[(CFG_MEM_IF_ADDR_WIDTH/2) - 1 : 4] = to_lmr[5:0];
combi_addr[CFG_MEM_IF_ADDR_WIDTH - 1 : 10] = {to_lmr[7:6],lmr_opcode};
end
if (do_lmr_read)
begin
//combi_cke = {(CFG_MEM_IF_CKE_WIDTH){1'b1}};
combi_cs_n = ~to_chip;
combi_addr[3:0] = 4'b1000;
combi_addr[(CFG_MEM_IF_ADDR_WIDTH/2) - 1 : 4] = to_lmr[5:0];
combi_addr[CFG_MEM_IF_ADDR_WIDTH - 1 : 10] = {to_lmr[7:6],{8{1'b0}}};
end
if (do_burst_terminate)
begin
//combi_cke = {(CFG_MEM_IF_CKE_WIDTH){1'b1}};
combi_cs_n = ~to_chip;
combi_addr[3:0] = 4'b0011;
combi_addr[(CFG_MEM_IF_ADDR_WIDTH/2) - 1 : 4] = {(CFG_MEM_IF_ADDR_WIDTH/2 - 4){1'b0}};
combi_addr[CFG_MEM_IF_ADDR_WIDTH - 1 : 10] = {(CFG_MEM_IF_ADDR_WIDTH/2){1'b0}};
end
end
else
begin
//combi_cke = {(CFG_MEM_IF_CKE_WIDTH){1'b1}};
combi_cs_n = {(CFG_MEM_IF_CHIP){1'b1}};
combi_addr = {(CFG_MEM_IF_ADDR_WIDTH){1'b0}};
end
end
endmodule
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
///////////////////////////////////////////////////////////////////////////////
// Title : alt_mem_ddrx_mm_st_converter
//
// File : alt_mem_ddrx_mm_st_converter.v
//
// Abstract : take in Avalon MM interface and convert it to single cmd and
// multiple data Avalon ST
//
///////////////////////////////////////////////////////////////////////////////
module alt_mem_ddrx_mm_st_converter # (
parameter
AVL_SIZE_WIDTH = 3,
AVL_ADDR_WIDTH = 25,
AVL_DATA_WIDTH = 32,
LOCAL_ID_WIDTH = 8,
CFG_DWIDTH_RATIO = 4
)
(
ctl_clk, // controller clock
ctl_reset_n, // controller reset_n, synchronous to ctl_clk
ctl_half_clk, // controller clock, half-rate
ctl_half_clk_reset_n, // controller reset_n, synchronous to ctl_half_clk
// Avalon data slave interface
avl_ready, // Avalon wait_n
avl_read_req, // Avalon read
avl_write_req, // Avalon write
avl_size, // Avalon burstcount
avl_burstbegin, // Avalon burstbegin
avl_addr, // Avalon address
avl_rdata_valid, // Avalon readdata_valid
avl_rdata, // Avalon readdata
avl_wdata, // Avalon writedata
avl_be, // Avalon byteenble
local_rdata_error, // Avalon readdata_error
local_multicast, // In-band multicast
local_autopch_req, // In-band auto-precharge request signal
local_priority, // In-band priority signal
// cmd channel
itf_cmd_ready,
itf_cmd_valid,
itf_cmd,
itf_cmd_address,
itf_cmd_burstlen,
itf_cmd_id,
itf_cmd_priority,
itf_cmd_autopercharge,
itf_cmd_multicast,
// write data channel
itf_wr_data_ready,
itf_wr_data_valid,
itf_wr_data,
itf_wr_data_byte_en,
itf_wr_data_begin,
itf_wr_data_last,
itf_wr_data_id,
// read data channel
itf_rd_data_ready,
itf_rd_data_valid,
itf_rd_data,
itf_rd_data_error,
itf_rd_data_begin,
itf_rd_data_last,
itf_rd_data_id
);
input ctl_clk;
input ctl_reset_n;
input ctl_half_clk;
input ctl_half_clk_reset_n;
output avl_ready;
input avl_read_req;
input avl_write_req;
input [AVL_SIZE_WIDTH-1:0] avl_size;
input avl_burstbegin;
input [AVL_ADDR_WIDTH-1:0] avl_addr;
output avl_rdata_valid;
output [3:0] local_rdata_error;
output [AVL_DATA_WIDTH-1:0] avl_rdata;
input [AVL_DATA_WIDTH-1:0] avl_wdata;
input [AVL_DATA_WIDTH/8-1:0] avl_be;
input local_multicast;
input local_autopch_req;
input local_priority;
input itf_cmd_ready;
output itf_cmd_valid;
output itf_cmd;
output [AVL_ADDR_WIDTH-1:0] itf_cmd_address;
output [AVL_SIZE_WIDTH-1:0] itf_cmd_burstlen;
output [LOCAL_ID_WIDTH-1:0] itf_cmd_id;
output itf_cmd_priority;
output itf_cmd_autopercharge;
output itf_cmd_multicast;
input itf_wr_data_ready;
output itf_wr_data_valid;
output [AVL_DATA_WIDTH-1:0] itf_wr_data;
output [AVL_DATA_WIDTH/8-1:0] itf_wr_data_byte_en;
output itf_wr_data_begin;
output itf_wr_data_last;
output [LOCAL_ID_WIDTH-1:0] itf_wr_data_id;
output itf_rd_data_ready;
input itf_rd_data_valid;
input [AVL_DATA_WIDTH-1:0] itf_rd_data;
input itf_rd_data_error;
input itf_rd_data_begin;
input itf_rd_data_last;
input [LOCAL_ID_WIDTH-1:0] itf_rd_data_id;
reg [AVL_SIZE_WIDTH-1:0] burst_count;
wire int_ready;
wire itf_cmd; // high is write
wire itf_wr_if_ready;
reg data_pass;
reg [AVL_SIZE_WIDTH-1:0] burst_counter;
// when cmd_ready = 1'b1, avl_ready = 1'b1;
// when avl_write_req = 1'b1,
// take this write req and then then drive avl_ready until receive # of beats = avl_size?
// we will look at cmd_ready, if cmd_ready = 1'b0, avl_ready = 1'b0
// when cmd_ready = 1'b1, avl_ready = 1'b1;
// when local_ready_req = 1'b1,
// take this read_req
// we will look at cmd_ready, if cmd_ready = 1'b0, avl_ready = 1'b0
assign itf_cmd_valid = avl_read_req | itf_wr_if_ready;
assign itf_wr_if_ready = itf_wr_data_ready & avl_write_req & ~data_pass;
assign avl_ready = int_ready;
assign itf_rd_data_ready = 1'b1;
assign itf_cmd_address = avl_addr ;
assign itf_cmd_burstlen = avl_size ;
assign itf_cmd_autopercharge = local_autopch_req ;
assign itf_cmd_priority = local_priority ;
assign itf_cmd_multicast = local_multicast ;
assign itf_cmd = avl_write_req;
// write data channel
assign itf_wr_data_valid = (data_pass) ? avl_write_req : itf_cmd_ready & avl_write_req;
assign itf_wr_data = avl_wdata ;
assign itf_wr_data_byte_en = avl_be ;
// read data channel
assign avl_rdata_valid = itf_rd_data_valid;
assign avl_rdata = itf_rd_data;
assign local_rdata_error = itf_rd_data_error;
assign int_ready = (data_pass) ? itf_wr_data_ready : ((itf_cmd) ? (itf_wr_data_ready & itf_cmd_ready) : itf_cmd_ready);
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
burst_counter <= 0;
else
begin
if (itf_wr_if_ready && avl_size > 1 && itf_cmd_ready)
burst_counter <= avl_size - 1;
else if (avl_write_req && itf_wr_data_ready)
burst_counter <= burst_counter - 1;
end
end
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
data_pass <= 0;
else
begin
if (itf_wr_if_ready && avl_size > 1 && itf_cmd_ready)
data_pass <= 1;
else if (burst_counter == 1 && avl_write_req && itf_wr_data_ready)
data_pass <= 0;
end
end
endmodule
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
//altera message_off 10036
`include "alt_mem_ddrx_define.iv"
`timescale 1 ps / 1 ps
module alt_mem_ddrx_odt_gen
#( parameter
CFG_DWIDTH_RATIO = 2,
CFG_ODT_ENABLED = 1,
CFG_MEM_IF_CHIP = 2, //one_hot
CFG_MEM_IF_ODT_WIDTH = 2,
CFG_PORT_WIDTH_OUTPUT_REGD = 1,
CFG_PORT_WIDTH_CAS_WR_LAT = 4,
CFG_PORT_WIDTH_TCL = 4,
CFG_PORT_WIDTH_ADD_LAT = 3,
CFG_PORT_WIDTH_TYPE = 3,
CFG_PORT_WIDTH_WRITE_ODT_CHIP = 4,
CFG_PORT_WIDTH_READ_ODT_CHIP = 4
)
(
ctl_clk,
ctl_reset_n,
//Configuration Interface
cfg_type,
cfg_tcl,
cfg_cas_wr_lat,
cfg_add_lat,
cfg_write_odt_chip,
cfg_read_odt_chip,
cfg_burst_length,
cfg_output_regd,
//Arbiter Interface
bg_do_read,
bg_do_write,
bg_do_burst_chop,
bg_to_chip, //one_hot
//AFI Interface
afi_odt
);
//=================================================================================================//
// input/output declaration //
//=================================================================================================//
input ctl_clk;
input ctl_reset_n;
//Input from Configuration Interface
input [CFG_PORT_WIDTH_TYPE -1:0] cfg_type;
input [CFG_PORT_WIDTH_TCL -1:0] cfg_tcl;
input [CFG_PORT_WIDTH_CAS_WR_LAT -1:0] cfg_cas_wr_lat;
input [CFG_PORT_WIDTH_ADD_LAT -1:0] cfg_add_lat;
input [CFG_PORT_WIDTH_WRITE_ODT_CHIP -1:0] cfg_write_odt_chip;
input [CFG_PORT_WIDTH_READ_ODT_CHIP -1:0] cfg_read_odt_chip;
input [4:0] cfg_burst_length;
input [CFG_PORT_WIDTH_OUTPUT_REGD -1:0] cfg_output_regd;
//Inputs from Arbiter Interface
input bg_do_read;
input bg_do_write;
input bg_do_burst_chop;
input [CFG_MEM_IF_CHIP -1:0] bg_to_chip;
//Output to AFI Interface
output [(CFG_MEM_IF_ODT_WIDTH*(CFG_DWIDTH_RATIO/2))-1:0] afi_odt;
//=================================================================================================//
// reg/wire declaration //
//=================================================================================================//
wire [CFG_MEM_IF_ODT_WIDTH-1:0] write_odt_chip [CFG_MEM_IF_CHIP-1:0];
wire [CFG_MEM_IF_ODT_WIDTH-1:0] read_odt_chip [CFG_MEM_IF_CHIP-1:0];
wire [CFG_MEM_IF_ODT_WIDTH-1:0] ddr2_odt_l;
wire [CFG_MEM_IF_ODT_WIDTH-1:0] ddr2_odt_h;
wire [CFG_MEM_IF_ODT_WIDTH-1:0] ddr3_odt_l;
wire [CFG_MEM_IF_ODT_WIDTH-1:0] ddr3_odt_h;
wire [CFG_MEM_IF_ODT_WIDTH-1:0] ddr3_odt_i_1;
wire [CFG_MEM_IF_ODT_WIDTH-1:0] ddr3_odt_i_2;
reg [CFG_MEM_IF_ODT_WIDTH-1:0] int_odt_l;
reg [CFG_MEM_IF_ODT_WIDTH-1:0] int_odt_h;
reg [CFG_MEM_IF_ODT_WIDTH-1:0] int_odt_i_1;
reg [CFG_MEM_IF_ODT_WIDTH-1:0] int_odt_i_2;
reg [CFG_MEM_IF_ODT_WIDTH-1:0] int_write_odt_chip;
reg [CFG_MEM_IF_ODT_WIDTH-1:0] int_read_odt_chip;
integer i;
//=================================================================================================//
// cfg_write_odt_chip & cfg_read_odt_chip definition //
//=================================================================================================//
/*
DDR3
four chip selects odt scheme, for two ranks per dimm configuration
.---------------------------------------++---------------------------------------.
| write to || odt to |
+---------+---------+---------+---------++---------+---------+---------+---------+
| chip 0 | chip 1 | chip 2 | chip 3 || chip 0 | chip 1 | chip 2 | chip 3 |
|=--------+---------+---------+---------++---------+---------+---------+--------=|
| 1 | | | || 1 | | 1 | | //cfg_write_odt_chip[0] = 4'b0101; //chip[3] -> chip[0]
+---------+---------+---------+---------++---------+---------+---------+---------+
| | 1 | | || | 1 | | 1 | //cfg_write_odt_chip[1] = 4'b1010; //chip[3] -> chip[0]
+---------+---------+---------+---------++---------+---------+---------+---------+
| | | 1 | || 1 | | 1 | | //cfg_write_odt_chip[2] = 4'b0101; //chip[3] -> chip[0]
+---------+---------+---------+---------++---------+---------+---------+---------+
| | | | 1 || | 1 | | 1 | //cfg_write_odt_chip[3] = 4'b1010; //chip[3] -> chip[0]
'---------+---------+---------+---------++---------+---------+---------+---------'
.---------------------------------------++---------------------------------------.
| read to || odt to |
+---------+---------+---------+---------++---------+---------+---------+---------+
| chip 0 | chip 1 | chip 2 | chip 3 || chip 0 | chip 1 | chip 2 | chip 3 |
|=--------+---------+---------+---------++---------+---------+---------+--------=|
| 1 | | | || | | 1 | | //cfg_read_odt_chip[0] = 4'b0100; //chip[3] -> chip[0]
+---------+---------+---------+---------++---------+---------+---------+---------+
| | 1 | | || | | | 1 | //cfg_read_odt_chip[1] = 4'b1000; //chip[3] -> chip[0]
+---------+---------+---------+---------++---------+---------+---------+---------+
| | | 1 | || 1 | | | | //cfg_read_odt_chip[2] = 4'b0001; //chip[3] -> chip[0]
+---------+---------+---------+---------++---------+---------+---------+---------+
| | | | 1 || | 1 | | | //cfg_read_odt_chip[3] = 4'b0010; //chip[3] -> chip[0]
'---------+---------+---------+---------++---------+---------+---------+---------'
*/
/*
DDR2
four or more chip selects odt scheme, assumes two ranks per dimm
.---------------------------------------++---------------------------------------.
| write/read to || odt to |
+---------+---------+---------+---------++---------+---------+---------+---------+
| chipJ+0 | chipJ+1 | chipJ+2 | chipJ+3 || chipJ+0 | chipJ+1 | chipJ+2 | chipJ+3 |
|=--------+---------+---------+---------++---------+---------+---------+--------=|
| 1 | | | || | | 1 | |
+---------+---------+---------+---------++---------+---------+---------+---------+
| | 1 | | || | | | 1 |
+---------+---------+---------+---------++---------+---------+---------+---------+
| | | 1 | || 1 | | | |
+---------+---------+---------+---------++---------+---------+---------+---------+
| | | | 1 || | 1 | | |
'---------+---------+---------+---------++---------+---------+---------+---------'
*/
//Unpack read/write_odt_chip array into per chip array
generate
genvar a;
begin : unpack_odt_config
for (a=0; a<CFG_MEM_IF_CHIP; a=a+1)
begin : unpack_odt_config_per_chip
assign write_odt_chip[a] = cfg_write_odt_chip [(a*CFG_MEM_IF_ODT_WIDTH)+CFG_MEM_IF_ODT_WIDTH-1:a*CFG_MEM_IF_ODT_WIDTH];
assign read_odt_chip[a] = cfg_read_odt_chip [(a*CFG_MEM_IF_ODT_WIDTH)+CFG_MEM_IF_ODT_WIDTH-1:a*CFG_MEM_IF_ODT_WIDTH];
end
end
endgenerate
always @(*)
begin
int_write_odt_chip = {(CFG_MEM_IF_ODT_WIDTH){1'b0}};
int_read_odt_chip = {(CFG_MEM_IF_ODT_WIDTH){1'b0}};
for (i=0; i<CFG_MEM_IF_CHIP; i=i+1)
begin
if (bg_to_chip[i])
begin
int_write_odt_chip = write_odt_chip[i];
int_read_odt_chip = read_odt_chip[i];
end
end
end
//=================================================================================================//
// Instantiate DDR2 ODT generation Block //
//=================================================================================================//
generate
genvar b;
for (b=0; b<CFG_MEM_IF_ODT_WIDTH; b=b+1)
begin : ddr2_odt_gen
alt_mem_ddrx_ddr2_odt_gen
# (
.CFG_DWIDTH_RATIO (CFG_DWIDTH_RATIO),
.CFG_PORT_WIDTH_ADD_LAT (CFG_PORT_WIDTH_ADD_LAT),
.CFG_PORT_WIDTH_OUTPUT_REGD (CFG_PORT_WIDTH_OUTPUT_REGD),
.CFG_PORT_WIDTH_TCL (CFG_PORT_WIDTH_TCL)
)
alt_mem_ddrx_ddr2_odt_gen_inst
(
.ctl_clk (ctl_clk),
.ctl_reset_n (ctl_reset_n),
.cfg_tcl (cfg_tcl),
.cfg_add_lat (cfg_add_lat),
.cfg_burst_length (cfg_burst_length),
.cfg_output_regd (cfg_output_regd),
.bg_do_write (bg_do_write & int_write_odt_chip[b]),
.bg_do_read (bg_do_read & int_read_odt_chip[b]),
.int_odt_l (ddr2_odt_l[b]),
.int_odt_h (ddr2_odt_h[b])
);
end
endgenerate
//=================================================================================================//
// Instantiate DDR3 ODT generation Block //
//=================================================================================================//
generate
genvar c;
for (c=0; c<CFG_MEM_IF_ODT_WIDTH; c=c+1)
begin : ddr3_odt_gen
alt_mem_ddrx_ddr3_odt_gen
# (
.CFG_DWIDTH_RATIO (CFG_DWIDTH_RATIO),
.CFG_PORT_WIDTH_OUTPUT_REGD (CFG_PORT_WIDTH_OUTPUT_REGD),
.CFG_PORT_WIDTH_TCL (CFG_PORT_WIDTH_TCL),
.CFG_PORT_WIDTH_CAS_WR_LAT (CFG_PORT_WIDTH_CAS_WR_LAT)
)
alt_mem_ddrx_ddr3_odt_gen_inst
(
.ctl_clk (ctl_clk),
.ctl_reset_n (ctl_reset_n),
.cfg_tcl (cfg_tcl),
.cfg_cas_wr_lat (cfg_cas_wr_lat),
.cfg_output_regd (cfg_output_regd),
.bg_do_write (bg_do_write & int_write_odt_chip[c]),
.bg_do_read (bg_do_read & int_read_odt_chip[c]),
.bg_do_burst_chop (bg_do_burst_chop),
.int_odt_l (ddr3_odt_l[c]),
.int_odt_h (ddr3_odt_h[c]),
.int_odt_i_1 (ddr3_odt_i_1[c]),
.int_odt_i_2 (ddr3_odt_i_2[c])
);
end
endgenerate
//=================================================================================================//
// ODT Output generation based on memory type and ODT feature turned ON or not //
//=================================================================================================//
always @(*)
begin
if (cfg_type == `MMR_TYPE_DDR2)
begin
int_odt_l = ddr2_odt_l;
int_odt_h = ddr2_odt_h;
int_odt_i_1 = {(CFG_MEM_IF_ODT_WIDTH){1'b0}};
int_odt_i_2 = {(CFG_MEM_IF_ODT_WIDTH){1'b0}};
end
else if (cfg_type == `MMR_TYPE_DDR3)
begin
int_odt_l = ddr3_odt_l;
int_odt_h = ddr3_odt_h;
int_odt_i_1 = ddr3_odt_i_1;
int_odt_i_2 = ddr3_odt_i_2;
end
else
begin
int_odt_l = {(CFG_MEM_IF_ODT_WIDTH){1'b0}};
int_odt_h = {(CFG_MEM_IF_ODT_WIDTH){1'b0}};
int_odt_i_1 = {(CFG_MEM_IF_ODT_WIDTH){1'b0}};
int_odt_i_2 = {(CFG_MEM_IF_ODT_WIDTH){1'b0}};
end
end
generate
if (CFG_ODT_ENABLED == 1)
begin
if (CFG_DWIDTH_RATIO == 2) // quarter rate
assign afi_odt = int_odt_l;
else if (CFG_DWIDTH_RATIO == 4) // half rate
assign afi_odt = {int_odt_h,int_odt_l};
else if (CFG_DWIDTH_RATIO == 8) // quarter rate
assign afi_odt = {int_odt_h,int_odt_i_2, int_odt_i_1, int_odt_l};
end
else
assign afi_odt = {(CFG_MEM_IF_ODT_WIDTH * (CFG_DWIDTH_RATIO/2)){1'b0}};
endgenerate
endmodule
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
//altera message_off 10230 10036
`timescale 1 ps / 1 ps
(* altera_attribute = "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF" *)
module alt_mem_ddrx_rank_timer #
( parameter
CFG_DWIDTH_RATIO = 2,
CFG_CTL_TBP_NUM = 4,
CFG_CTL_ARBITER_TYPE = "ROWCOL",
CFG_MEM_IF_CHIP = 1,
CFG_MEM_IF_CS_WIDTH = 1,
CFG_INT_SIZE_WIDTH = 4,
CFG_AFI_INTF_PHASE_NUM = 2,
CFG_REG_GRANT = 0,
CFG_RANK_TIMER_OUTPUT_REG = 0,
CFG_PORT_WIDTH_BURST_LENGTH = 5,
T_PARAM_FOUR_ACT_TO_ACT_WIDTH = 0,
T_PARAM_ACT_TO_ACT_DIFF_BANK_WIDTH = 0,
T_PARAM_WR_TO_WR_WIDTH = 0,
T_PARAM_WR_TO_WR_DIFF_CHIP_WIDTH = 0,
T_PARAM_WR_TO_RD_WIDTH = 0,
T_PARAM_WR_TO_RD_BC_WIDTH = 0,
T_PARAM_WR_TO_RD_DIFF_CHIP_WIDTH = 0,
T_PARAM_RD_TO_RD_WIDTH = 0,
T_PARAM_RD_TO_RD_DIFF_CHIP_WIDTH = 0,
T_PARAM_RD_TO_WR_WIDTH = 0,
T_PARAM_RD_TO_WR_BC_WIDTH = 0,
T_PARAM_RD_TO_WR_DIFF_CHIP_WIDTH = 0
)
(
ctl_clk,
ctl_reset_n,
// MMR Configurations
cfg_burst_length,
// Timing parameters
t_param_four_act_to_act,
t_param_act_to_act_diff_bank,
t_param_wr_to_wr,
t_param_wr_to_wr_diff_chip,
t_param_wr_to_rd,
t_param_wr_to_rd_bc,
t_param_wr_to_rd_diff_chip,
t_param_rd_to_rd,
t_param_rd_to_rd_diff_chip,
t_param_rd_to_wr,
t_param_rd_to_wr_bc,
t_param_rd_to_wr_diff_chip,
// Arbiter Interface
bg_do_write,
bg_do_read,
bg_do_burst_chop,
bg_do_burst_terminate,
bg_do_activate,
bg_do_precharge,
bg_to_chip,
bg_effective_size,
bg_interrupt_ready,
// Command Generator Interface
cmd_gen_chipsel,
// TBP Interface
tbp_chipsel,
tbp_load,
// Sideband Interface
stall_chip,
can_activate,
can_precharge,
can_read,
can_write
);
input ctl_clk;
input ctl_reset_n;
input [CFG_PORT_WIDTH_BURST_LENGTH - 1 : 0] cfg_burst_length;
input [T_PARAM_FOUR_ACT_TO_ACT_WIDTH - 1 : 0] t_param_four_act_to_act;
input [T_PARAM_ACT_TO_ACT_DIFF_BANK_WIDTH - 1 : 0] t_param_act_to_act_diff_bank;
input [T_PARAM_WR_TO_WR_WIDTH - 1 : 0] t_param_wr_to_wr;
input [T_PARAM_WR_TO_WR_DIFF_CHIP_WIDTH - 1 : 0] t_param_wr_to_wr_diff_chip;
input [T_PARAM_WR_TO_RD_WIDTH - 1 : 0] t_param_wr_to_rd;
input [T_PARAM_WR_TO_RD_BC_WIDTH - 1 : 0] t_param_wr_to_rd_bc;
input [T_PARAM_WR_TO_RD_DIFF_CHIP_WIDTH - 1 : 0] t_param_wr_to_rd_diff_chip;
input [T_PARAM_RD_TO_RD_WIDTH - 1 : 0] t_param_rd_to_rd;
input [T_PARAM_RD_TO_RD_DIFF_CHIP_WIDTH - 1 : 0] t_param_rd_to_rd_diff_chip;
input [T_PARAM_RD_TO_WR_WIDTH - 1 : 0] t_param_rd_to_wr;
input [T_PARAM_RD_TO_WR_BC_WIDTH - 1 : 0] t_param_rd_to_wr_bc;
input [T_PARAM_RD_TO_WR_DIFF_CHIP_WIDTH - 1 : 0] t_param_rd_to_wr_diff_chip;
input [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_write;
input [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_read;
input [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_burst_chop;
input [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_burst_terminate;
input [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_activate;
input [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_precharge;
input [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_to_chip;
input [CFG_INT_SIZE_WIDTH - 1 : 0] bg_effective_size;
input bg_interrupt_ready;
input [CFG_MEM_IF_CS_WIDTH - 1 : 0] cmd_gen_chipsel;
input [(CFG_CTL_TBP_NUM * CFG_MEM_IF_CS_WIDTH) - 1 : 0] tbp_chipsel;
input [CFG_CTL_TBP_NUM - 1 : 0] tbp_load;
input [CFG_MEM_IF_CHIP - 1 : 0] stall_chip;
output [CFG_CTL_TBP_NUM - 1 : 0] can_activate;
output [CFG_CTL_TBP_NUM - 1 : 0] can_precharge;
output [CFG_CTL_TBP_NUM - 1 : 0] can_read;
output [CFG_CTL_TBP_NUM - 1 : 0] can_write;
//--------------------------------------------------------------------------------------------------------
//
// [START] Register & Wires
//
//--------------------------------------------------------------------------------------------------------
// General
localparam RANK_TIMER_COUNTER_OFFSET = (CFG_RANK_TIMER_OUTPUT_REG) ? ((CFG_REG_GRANT) ? 4 : 3) : ((CFG_REG_GRANT) ? 3 : 2);
localparam RANK_TIMER_TFAW_OFFSET = (CFG_RANK_TIMER_OUTPUT_REG) ? ((CFG_REG_GRANT) ? 2 : 1) : ((CFG_REG_GRANT) ? 1 : 0);
localparam ENABLE_BETTER_TRRD_EFFICIENCY = 1; // ONLY set to '1' when CFG_RANK_TIMER_OUTPUT_REG is enabled, else it will fail
wire one = 1'b1;
wire zero = 1'b0;
// Timing Parameter Comparison Logic
reg less_than_1_act_to_act_diff_bank;
reg less_than_2_act_to_act_diff_bank;
reg less_than_3_act_to_act_diff_bank;
reg less_than_4_act_to_act_diff_bank;
reg less_than_4_four_act_to_act;
reg less_than_1_rd_to_rd;
reg less_than_1_rd_to_wr;
reg less_than_1_wr_to_wr;
reg less_than_1_wr_to_rd;
reg less_than_1_rd_to_wr_bc;
reg less_than_1_wr_to_rd_bc;
reg less_than_1_rd_to_rd_diff_chip;
reg less_than_1_rd_to_wr_diff_chip;
reg less_than_1_wr_to_wr_diff_chip;
reg less_than_1_wr_to_rd_diff_chip;
reg less_than_2_rd_to_rd;
reg less_than_2_rd_to_wr;
reg less_than_2_wr_to_wr;
reg less_than_2_wr_to_rd;
reg less_than_2_rd_to_wr_bc;
reg less_than_2_wr_to_rd_bc;
reg less_than_2_rd_to_rd_diff_chip;
reg less_than_2_rd_to_wr_diff_chip;
reg less_than_2_wr_to_wr_diff_chip;
reg less_than_2_wr_to_rd_diff_chip;
reg less_than_3_rd_to_rd;
reg less_than_3_rd_to_wr;
reg less_than_3_wr_to_wr;
reg less_than_3_wr_to_rd;
reg less_than_3_rd_to_wr_bc;
reg less_than_3_wr_to_rd_bc;
reg less_than_3_rd_to_rd_diff_chip;
reg less_than_3_rd_to_wr_diff_chip;
reg less_than_3_wr_to_wr_diff_chip;
reg less_than_3_wr_to_rd_diff_chip;
reg less_than_4_rd_to_rd;
reg less_than_4_rd_to_wr;
reg less_than_4_wr_to_wr;
reg less_than_4_wr_to_rd;
reg less_than_4_rd_to_wr_bc;
reg less_than_4_wr_to_rd_bc;
reg less_than_4_rd_to_rd_diff_chip;
reg less_than_4_rd_to_wr_diff_chip;
reg less_than_4_wr_to_wr_diff_chip;
reg less_than_4_wr_to_rd_diff_chip;
reg more_than_3_rd_to_rd;
reg more_than_3_rd_to_wr;
reg more_than_3_wr_to_wr;
reg more_than_3_wr_to_rd;
reg more_than_3_rd_to_wr_bc;
reg more_than_3_wr_to_rd_bc;
reg more_than_3_rd_to_rd_diff_chip;
reg more_than_3_rd_to_wr_diff_chip;
reg more_than_3_wr_to_wr_diff_chip;
reg more_than_3_wr_to_rd_diff_chip;
reg less_than_xn1_act_to_act_diff_bank;
reg less_than_xn1_rd_to_rd;
reg less_than_xn1_rd_to_wr;
reg less_than_xn1_wr_to_wr;
reg less_than_xn1_wr_to_rd;
reg less_than_xn1_rd_to_wr_bc;
reg less_than_xn1_wr_to_rd_bc;
reg less_than_xn1_rd_to_rd_diff_chip;
reg less_than_xn1_rd_to_wr_diff_chip;
reg less_than_xn1_wr_to_wr_diff_chip;
reg less_than_xn1_wr_to_rd_diff_chip;
reg less_than_x0_act_to_act_diff_bank;
reg less_than_x0_rd_to_rd;
reg less_than_x0_rd_to_wr;
reg less_than_x0_wr_to_wr;
reg less_than_x0_wr_to_rd;
reg less_than_x0_rd_to_wr_bc;
reg less_than_x0_wr_to_rd_bc;
reg less_than_x0_rd_to_rd_diff_chip;
reg less_than_x0_rd_to_wr_diff_chip;
reg less_than_x0_wr_to_wr_diff_chip;
reg less_than_x0_wr_to_rd_diff_chip;
reg less_than_x1_act_to_act_diff_bank;
reg less_than_x1_rd_to_rd;
reg less_than_x1_rd_to_wr;
reg less_than_x1_wr_to_wr;
reg less_than_x1_wr_to_rd;
reg less_than_x1_rd_to_wr_bc;
reg less_than_x1_wr_to_rd_bc;
reg less_than_x1_rd_to_rd_diff_chip;
reg less_than_x1_rd_to_wr_diff_chip;
reg less_than_x1_wr_to_wr_diff_chip;
reg less_than_x1_wr_to_rd_diff_chip;
// Input
reg int_do_activate;
reg int_do_precharge;
reg int_do_burst_chop;
reg int_do_burst_terminate;
reg int_do_write;
reg int_do_read;
reg [CFG_MEM_IF_CHIP - 1 : 0] int_to_chip_r;
reg [CFG_MEM_IF_CHIP - 1 : 0] int_to_chip_c;
reg [CFG_INT_SIZE_WIDTH - 1 : 0] int_effective_size;
reg int_interrupt_ready;
// Activate Monitor
localparam ACTIVATE_COUNTER_WIDTH = T_PARAM_ACT_TO_ACT_DIFF_BANK_WIDTH;
localparam ACTIVATE_COMMAND_WIDTH = 3;
localparam NUM_OF_TFAW_SHIFT_REG = 2 ** T_PARAM_FOUR_ACT_TO_ACT_WIDTH;
reg [CFG_MEM_IF_CHIP - 1 : 0] act_tfaw_ready;
reg [CFG_MEM_IF_CHIP - 1 : 0] act_tfaw_ready_combi;
reg [CFG_MEM_IF_CHIP - 1 : 0] act_trrd_ready;
reg [CFG_MEM_IF_CHIP - 1 : 0] act_trrd_ready_combi;
reg [CFG_MEM_IF_CHIP - 1 : 0] act_ready;
wire [ACTIVATE_COMMAND_WIDTH - 1 : 0] act_tfaw_cmd_count [CFG_MEM_IF_CHIP - 1 : 0];
// Read/Write Monitor
localparam IDLE = 32'h49444C45;
localparam WR = 32'h20205752;
localparam RD = 32'h20205244;
localparam RDWR_COUNTER_WIDTH = (T_PARAM_RD_TO_WR_WIDTH > T_PARAM_WR_TO_RD_WIDTH) ? T_PARAM_RD_TO_WR_WIDTH : T_PARAM_WR_TO_RD_WIDTH;
reg [CFG_INT_SIZE_WIDTH - 1 : 0] max_local_burst_size;
reg [T_PARAM_RD_TO_WR_WIDTH - 1 : 0] effective_rd_to_wr_combi;
reg [T_PARAM_RD_TO_WR_DIFF_CHIP_WIDTH - 1 : 0] effective_rd_to_wr_diff_chip_combi;
reg [T_PARAM_WR_TO_RD_WIDTH - 1 : 0] effective_wr_to_rd_combi;
reg [T_PARAM_WR_TO_RD_DIFF_CHIP_WIDTH - 1 : 0] effective_wr_to_rd_diff_chip_combi;
reg [T_PARAM_RD_TO_WR_WIDTH - 1 : 0] effective_rd_to_wr;
reg [T_PARAM_RD_TO_WR_DIFF_CHIP_WIDTH - 1 : 0] effective_rd_to_wr_diff_chip;
reg [T_PARAM_WR_TO_RD_WIDTH - 1 : 0] effective_wr_to_rd;
reg [T_PARAM_WR_TO_RD_DIFF_CHIP_WIDTH - 1 : 0] effective_wr_to_rd_diff_chip;
reg [CFG_MEM_IF_CHIP - 1 : 0] read_ready;
reg [CFG_MEM_IF_CHIP - 1 : 0] write_ready;
// Precharge Monitor
reg [CFG_MEM_IF_CHIP - 1 : 0] pch_ready;
// Output
reg [CFG_CTL_TBP_NUM - 1 : 0] int_can_activate;
reg [CFG_CTL_TBP_NUM - 1 : 0] int_can_precharge;
reg [CFG_CTL_TBP_NUM - 1 : 0] int_can_read;
reg [CFG_CTL_TBP_NUM - 1 : 0] int_can_write;
reg [CFG_CTL_TBP_NUM - 1 : 0] can_activate;
reg [CFG_CTL_TBP_NUM - 1 : 0] can_precharge;
reg [CFG_CTL_TBP_NUM - 1 : 0] can_read;
reg [CFG_CTL_TBP_NUM - 1 : 0] can_write;
reg [T_PARAM_FOUR_ACT_TO_ACT_WIDTH - 1 : 0] sel_act_tfaw_shift_out_point;
//--------------------------------------------------------------------------------------------------------
//
// [END] Register & Wires
//
//--------------------------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------------------------
//
// [START] Input
//
//--------------------------------------------------------------------------------------------------------
// Do activate
always @ (*)
begin
int_do_activate = |bg_do_activate;
end
// Do precharge
always @ (*)
begin
int_do_precharge = |bg_do_precharge;
end
//Do burst chop
always @ (*)
begin
int_do_burst_chop = |bg_do_burst_chop;
end
//Do burst terminate
always @ (*)
begin
int_do_burst_terminate = |bg_do_burst_terminate;
end
// Do write
always @ (*)
begin
int_do_write = |bg_do_write;
end
// Do read
always @ (*)
begin
int_do_read = |bg_do_read;
end
// To chip
always @ (*)
begin
// _r for row command and _c for column command
if (CFG_CTL_ARBITER_TYPE == "COLROW")
begin
int_to_chip_c = bg_to_chip [CFG_MEM_IF_CHIP - 1 : 0 ];
int_to_chip_r = bg_to_chip [2 * CFG_MEM_IF_CHIP - 1 : CFG_MEM_IF_CHIP];
end
else if (CFG_CTL_ARBITER_TYPE == "ROWCOL")
begin
int_to_chip_r = bg_to_chip [CFG_MEM_IF_CHIP - 1 : 0 ];
int_to_chip_c = bg_to_chip [2 * CFG_MEM_IF_CHIP - 1 : CFG_MEM_IF_CHIP];
end
end
// Effective size
always @ (*)
begin
int_effective_size = bg_effective_size;
end
// Interrupt ready
always @ (*)
begin
int_interrupt_ready = bg_interrupt_ready;
end
//--------------------------------------------------------------------------------------------------------
//
// [END] Input
//
//--------------------------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------------------------
//
// [START] Output
//
//--------------------------------------------------------------------------------------------------------
generate
genvar x_cs;
for (x_cs = 0; x_cs < CFG_CTL_TBP_NUM;x_cs = x_cs + 1)
begin : can_logic_per_chip
reg [CFG_MEM_IF_CS_WIDTH - 1 : 0] chip_addr;
always @ (*)
begin
if (CFG_RANK_TIMER_OUTPUT_REG && tbp_load [x_cs])
begin
chip_addr = cmd_gen_chipsel;
end
else
begin
chip_addr = tbp_chipsel [(x_cs + 1) * CFG_MEM_IF_CS_WIDTH - 1 : x_cs * CFG_MEM_IF_CS_WIDTH];
end
end
if (CFG_RANK_TIMER_OUTPUT_REG)
begin
always @ (*)
begin
can_activate [x_cs] = int_can_activate [x_cs] ;
can_precharge [x_cs] = int_can_precharge [x_cs] ;
can_read [x_cs] = int_can_read [x_cs] & int_interrupt_ready;
can_write [x_cs] = int_can_write [x_cs] & int_interrupt_ready;
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_can_activate [x_cs] <= 1'b0;
end
else
begin
if (stall_chip [chip_addr])
begin
int_can_activate [x_cs] <= 1'b0;
end
else if (int_do_activate && int_to_chip_r [chip_addr] && !ENABLE_BETTER_TRRD_EFFICIENCY)
begin
int_can_activate [x_cs] <= 1'b0;
end
else
begin
int_can_activate [x_cs] <= act_ready [chip_addr];
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_can_precharge [x_cs] <= 1'b0;
end
else
begin
if (stall_chip [chip_addr])
begin
int_can_precharge [x_cs] <= 1'b0;
end
else
begin
int_can_precharge [x_cs] <= pch_ready [chip_addr];
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_can_read [x_cs] <= 1'b0;
end
else
begin
if (stall_chip [chip_addr])
begin
int_can_read [x_cs] <= 1'b0;
end
else if (int_do_write)
begin
if (int_to_chip_c [chip_addr]) // to same chip addr as compared to current TBP
begin
if (int_do_burst_chop && more_than_3_wr_to_rd_bc)
begin
int_can_read [x_cs] <= 1'b0;
end
else if (!int_do_burst_chop && more_than_3_wr_to_rd)
begin
int_can_read [x_cs] <= 1'b0;
end
else
begin
int_can_read [x_cs] <= 1'b1;
end
end
else // to other chip addr as compared to current TBP
begin
int_can_read [x_cs] <= 1'b0;
end
end
else if (int_do_read)
begin
if (int_to_chip_c [chip_addr]) // to same chip addr as compared to current TBP
begin
if (more_than_3_rd_to_rd)
begin
int_can_read [x_cs] <= 1'b0;
end
else
begin
int_can_read [x_cs] <= 1'b1;
end
end
else // to other chip addr as compared to current TBP
begin
int_can_read [x_cs] <= 1'b0;
end
end
else
begin
int_can_read [x_cs] <= read_ready [chip_addr];
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_can_write [x_cs] <= 1'b0;
end
else
begin
if (stall_chip [chip_addr])
begin
int_can_write [x_cs] <= 1'b0;
end
else if (int_do_read)
begin
if (int_to_chip_c [chip_addr]) // to same chip addr as compared to current TBP
begin
if (int_do_burst_chop && more_than_3_rd_to_wr_bc)
begin
int_can_write [x_cs] <= 1'b0;
end
else if (!int_do_burst_chop && more_than_3_rd_to_wr)
begin
int_can_write [x_cs] <= 1'b0;
end
else
begin
int_can_write [x_cs] <= 1'b1;
end
end
else // to other chip addr as compared to current TBP
begin
int_can_write [x_cs] <= 1'b0;
end
end
else if (int_do_write)
begin
if (int_to_chip_c [chip_addr]) // to same chip addr as compared to current TBP
begin
if (more_than_3_wr_to_wr)
begin
int_can_write [x_cs] <= 1'b0;
end
else
begin
int_can_write [x_cs] <= 1'b1;
end
end
else // to other chip addr as compared to current TBP
begin
int_can_write [x_cs] <= 1'b0;
end
end
else
begin
int_can_write [x_cs] <= write_ready [chip_addr];
end
end
end
end
else
begin
// Can activate
always @ (*)
begin
can_activate [x_cs] = act_ready [chip_addr];
end
// Can precharge
always @ (*)
begin
can_precharge [x_cs] = pch_ready [chip_addr];
end
// Can read
always @ (*)
begin
can_read [x_cs] = read_ready [chip_addr];
end
// Can write
always @ (*)
begin
can_write [x_cs] = write_ready [chip_addr];
end
end
end
endgenerate
//--------------------------------------------------------------------------------------------------------
//
// [END] Output
//
//--------------------------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------------------------
//
// [START] Timing Parameter Comparison Logic
//
//--------------------------------------------------------------------------------------------------------
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_1_act_to_act_diff_bank <= 1'b0;
end
else
begin
if (t_param_act_to_act_diff_bank <= 1)
less_than_1_act_to_act_diff_bank <= 1'b1;
else
less_than_1_act_to_act_diff_bank <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_2_act_to_act_diff_bank <= 1'b0;
end
else
begin
if (t_param_act_to_act_diff_bank <= 2)
less_than_2_act_to_act_diff_bank <= 1'b1;
else
less_than_2_act_to_act_diff_bank <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_3_act_to_act_diff_bank <= 1'b0;
end
else
begin
if (t_param_act_to_act_diff_bank <= 3)
less_than_3_act_to_act_diff_bank <= 1'b1;
else
less_than_3_act_to_act_diff_bank <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_4_act_to_act_diff_bank <= 1'b0;
end
else
begin
if (t_param_act_to_act_diff_bank <= 4)
less_than_4_act_to_act_diff_bank <= 1'b1;
else
less_than_4_act_to_act_diff_bank <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_4_four_act_to_act <= 1'b0;
end
else
begin
if (t_param_four_act_to_act <= 4)
less_than_4_four_act_to_act <= 1'b1;
else
less_than_4_four_act_to_act <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_1_rd_to_rd <= 1'b0;
end
else
begin
if (t_param_rd_to_rd <= 1)
less_than_1_rd_to_rd <= 1'b1;
else
less_than_1_rd_to_rd <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_1_rd_to_wr <= 1'b0;
end
else
begin
if (t_param_rd_to_wr <= 1)
less_than_1_rd_to_wr <= 1'b1;
else
less_than_1_rd_to_wr <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_1_wr_to_wr <= 1'b0;
end
else
begin
if (t_param_wr_to_wr <= 1)
less_than_1_wr_to_wr <= 1'b1;
else
less_than_1_wr_to_wr <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_1_wr_to_rd <= 1'b0;
end
else
begin
if (t_param_wr_to_rd <= 1)
less_than_1_wr_to_rd <= 1'b1;
else
less_than_1_wr_to_rd <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_1_rd_to_wr_bc <= 1'b0;
end
else
begin
if (t_param_rd_to_wr_bc <= 1)
less_than_1_rd_to_wr_bc <= 1'b1;
else
less_than_1_rd_to_wr_bc <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_1_wr_to_rd_bc <= 1'b0;
end
else
begin
if (t_param_wr_to_rd_bc <= 1)
less_than_1_wr_to_rd_bc <= 1'b1;
else
less_than_1_wr_to_rd_bc <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_1_rd_to_rd_diff_chip <= 1'b0;
end
else
begin
if (t_param_rd_to_rd_diff_chip <= 1)
less_than_1_rd_to_rd_diff_chip <= 1'b1;
else
less_than_1_rd_to_rd_diff_chip <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_1_rd_to_wr_diff_chip <= 1'b0;
end
else
begin
if (t_param_rd_to_wr_diff_chip <= 1)
less_than_1_rd_to_wr_diff_chip <= 1'b1;
else
less_than_1_rd_to_wr_diff_chip <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_1_wr_to_wr_diff_chip <= 1'b0;
end
else
begin
if (t_param_wr_to_wr_diff_chip <= 1)
less_than_1_wr_to_wr_diff_chip <= 1'b1;
else
less_than_1_wr_to_wr_diff_chip <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_1_wr_to_rd_diff_chip <= 1'b0;
end
else
begin
if (t_param_wr_to_rd_diff_chip <= 1)
less_than_1_wr_to_rd_diff_chip <= 1'b1;
else
less_than_1_wr_to_rd_diff_chip <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_2_rd_to_rd <= 1'b0;
end
else
begin
if (t_param_rd_to_rd <= 2)
less_than_2_rd_to_rd <= 1'b1;
else
less_than_2_rd_to_rd <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_2_rd_to_wr <= 1'b0;
end
else
begin
if (t_param_rd_to_wr <= 2)
less_than_2_rd_to_wr <= 1'b1;
else
less_than_2_rd_to_wr <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_2_wr_to_wr <= 1'b0;
end
else
begin
if (t_param_wr_to_wr <= 2)
less_than_2_wr_to_wr <= 1'b1;
else
less_than_2_wr_to_wr <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_2_wr_to_rd <= 1'b0;
end
else
begin
if (t_param_wr_to_rd <= 2)
less_than_2_wr_to_rd <= 1'b1;
else
less_than_2_wr_to_rd <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_2_rd_to_wr_bc <= 1'b0;
end
else
begin
if (t_param_rd_to_wr_bc <= 2)
less_than_2_rd_to_wr_bc <= 1'b1;
else
less_than_2_rd_to_wr_bc <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_2_wr_to_rd_bc <= 1'b0;
end
else
begin
if (t_param_wr_to_rd_bc <= 2)
less_than_2_wr_to_rd_bc <= 1'b1;
else
less_than_2_wr_to_rd_bc <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_2_rd_to_rd_diff_chip <= 1'b0;
end
else
begin
if (t_param_rd_to_rd_diff_chip <= 2)
less_than_2_rd_to_rd_diff_chip <= 1'b1;
else
less_than_2_rd_to_rd_diff_chip <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_2_rd_to_wr_diff_chip <= 1'b0;
end
else
begin
if (t_param_rd_to_wr_diff_chip <= 2)
less_than_2_rd_to_wr_diff_chip <= 1'b1;
else
less_than_2_rd_to_wr_diff_chip <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_2_wr_to_wr_diff_chip <= 1'b0;
end
else
begin
if (t_param_wr_to_wr_diff_chip <= 2)
less_than_2_wr_to_wr_diff_chip <= 1'b1;
else
less_than_2_wr_to_wr_diff_chip <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_2_wr_to_rd_diff_chip <= 1'b0;
end
else
begin
if (t_param_wr_to_rd_diff_chip <= 2)
less_than_2_wr_to_rd_diff_chip <= 1'b1;
else
less_than_2_wr_to_rd_diff_chip <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_3_rd_to_rd <= 1'b0;
end
else
begin
if (t_param_rd_to_rd <= 3)
less_than_3_rd_to_rd <= 1'b1;
else
less_than_3_rd_to_rd <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_3_rd_to_wr <= 1'b0;
end
else
begin
if (t_param_rd_to_wr <= 3)
less_than_3_rd_to_wr <= 1'b1;
else
less_than_3_rd_to_wr <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_3_wr_to_wr <= 1'b0;
end
else
begin
if (t_param_wr_to_wr <= 3)
less_than_3_wr_to_wr <= 1'b1;
else
less_than_3_wr_to_wr <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_3_wr_to_rd <= 1'b0;
end
else
begin
if (t_param_wr_to_rd <= 3)
less_than_3_wr_to_rd <= 1'b1;
else
less_than_3_wr_to_rd <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_3_rd_to_wr_bc <= 1'b0;
end
else
begin
if (t_param_rd_to_wr_bc <= 3)
less_than_3_rd_to_wr_bc <= 1'b1;
else
less_than_3_rd_to_wr_bc <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_3_wr_to_rd_bc <= 1'b0;
end
else
begin
if (t_param_wr_to_rd_bc <= 3)
less_than_3_wr_to_rd_bc <= 1'b1;
else
less_than_3_wr_to_rd_bc <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_3_rd_to_rd_diff_chip <= 1'b0;
end
else
begin
if (t_param_rd_to_rd_diff_chip <= 3)
less_than_3_rd_to_rd_diff_chip <= 1'b1;
else
less_than_3_rd_to_rd_diff_chip <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_3_rd_to_wr_diff_chip <= 1'b0;
end
else
begin
if (t_param_rd_to_wr_diff_chip <= 3)
less_than_3_rd_to_wr_diff_chip <= 1'b1;
else
less_than_3_rd_to_wr_diff_chip <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_3_wr_to_wr_diff_chip <= 1'b0;
end
else
begin
if (t_param_wr_to_wr_diff_chip <= 3)
less_than_3_wr_to_wr_diff_chip <= 1'b1;
else
less_than_3_wr_to_wr_diff_chip <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_3_wr_to_rd_diff_chip <= 1'b0;
end
else
begin
if (t_param_wr_to_rd_diff_chip <= 3)
less_than_3_wr_to_rd_diff_chip <= 1'b1;
else
less_than_3_wr_to_rd_diff_chip <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_4_rd_to_rd <= 1'b0;
end
else
begin
if (t_param_rd_to_rd <= 4)
less_than_4_rd_to_rd <= 1'b1;
else
less_than_4_rd_to_rd <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_4_rd_to_wr <= 1'b0;
end
else
begin
if (t_param_rd_to_wr <= 4)
less_than_4_rd_to_wr <= 1'b1;
else
less_than_4_rd_to_wr <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_4_wr_to_wr <= 1'b0;
end
else
begin
if (t_param_wr_to_wr <= 4)
less_than_4_wr_to_wr <= 1'b1;
else
less_than_4_wr_to_wr <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_4_wr_to_rd <= 1'b0;
end
else
begin
if (t_param_wr_to_rd <= 4)
less_than_4_wr_to_rd <= 1'b1;
else
less_than_4_wr_to_rd <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_4_rd_to_wr_bc <= 1'b0;
end
else
begin
if (t_param_rd_to_wr_bc <= 4)
less_than_4_rd_to_wr_bc <= 1'b1;
else
less_than_4_rd_to_wr_bc <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_4_wr_to_rd_bc <= 1'b0;
end
else
begin
if (t_param_wr_to_rd_bc <= 4)
less_than_4_wr_to_rd_bc <= 1'b1;
else
less_than_4_wr_to_rd_bc <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_4_rd_to_rd_diff_chip <= 1'b0;
end
else
begin
if (t_param_rd_to_rd_diff_chip <= 4)
less_than_4_rd_to_rd_diff_chip <= 1'b1;
else
less_than_4_rd_to_rd_diff_chip <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_4_rd_to_wr_diff_chip <= 1'b0;
end
else
begin
if (t_param_rd_to_wr_diff_chip <= 4)
less_than_4_rd_to_wr_diff_chip <= 1'b1;
else
less_than_4_rd_to_wr_diff_chip <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_4_wr_to_wr_diff_chip <= 1'b0;
end
else
begin
if (t_param_wr_to_wr_diff_chip <= 4)
less_than_4_wr_to_wr_diff_chip <= 1'b1;
else
less_than_4_wr_to_wr_diff_chip <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_4_wr_to_rd_diff_chip <= 1'b0;
end
else
begin
if (t_param_wr_to_rd_diff_chip <= 4)
less_than_4_wr_to_rd_diff_chip <= 1'b1;
else
less_than_4_wr_to_rd_diff_chip <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
more_than_3_rd_to_rd <= 1'b0;
end
else
begin
if (t_param_rd_to_rd >= 3)
more_than_3_rd_to_rd <= 1'b1;
else
more_than_3_rd_to_rd <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
more_than_3_rd_to_wr <= 1'b0;
end
else
begin
if (t_param_rd_to_wr >= 3)
more_than_3_rd_to_wr <= 1'b1;
else
more_than_3_rd_to_wr <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
more_than_3_wr_to_wr <= 1'b0;
end
else
begin
if (t_param_wr_to_wr >= 3)
more_than_3_wr_to_wr <= 1'b1;
else
more_than_3_wr_to_wr <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
more_than_3_wr_to_rd <= 1'b0;
end
else
begin
if (t_param_wr_to_rd >= 3)
more_than_3_wr_to_rd <= 1'b1;
else
more_than_3_wr_to_rd <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
more_than_3_rd_to_wr_bc <= 1'b0;
end
else
begin
if (t_param_rd_to_wr_bc >= 3)
more_than_3_rd_to_wr_bc <= 1'b1;
else
more_than_3_rd_to_wr_bc <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
more_than_3_wr_to_rd_bc <= 1'b0;
end
else
begin
if (t_param_wr_to_rd_bc >= 3)
more_than_3_wr_to_rd_bc <= 1'b1;
else
more_than_3_wr_to_rd_bc <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
more_than_3_rd_to_rd_diff_chip <= 1'b0;
end
else
begin
if (t_param_rd_to_rd_diff_chip >= 3)
more_than_3_rd_to_rd_diff_chip <= 1'b1;
else
more_than_3_rd_to_rd_diff_chip <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
more_than_3_rd_to_wr_diff_chip <= 1'b0;
end
else
begin
if (t_param_rd_to_wr_diff_chip >= 3)
more_than_3_rd_to_wr_diff_chip <= 1'b1;
else
more_than_3_rd_to_wr_diff_chip <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
more_than_3_wr_to_wr_diff_chip <= 1'b0;
end
else
begin
if (t_param_wr_to_wr_diff_chip >= 3)
more_than_3_wr_to_wr_diff_chip <= 1'b1;
else
more_than_3_wr_to_wr_diff_chip <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
more_than_3_wr_to_rd_diff_chip <= 1'b0;
end
else
begin
if (t_param_wr_to_rd_diff_chip >= 3)
more_than_3_wr_to_rd_diff_chip <= 1'b1;
else
more_than_3_wr_to_rd_diff_chip <= 1'b0;
end
end
generate
begin
if (CFG_REG_GRANT)
begin
always @ (*)
begin
if (CFG_RANK_TIMER_OUTPUT_REG)
begin
less_than_xn1_act_to_act_diff_bank = less_than_2_act_to_act_diff_bank;
less_than_xn1_rd_to_rd = less_than_2_rd_to_rd;
less_than_xn1_rd_to_wr = less_than_2_rd_to_wr;
less_than_xn1_wr_to_wr = less_than_2_wr_to_wr;
less_than_xn1_wr_to_rd = less_than_2_wr_to_rd;
less_than_xn1_rd_to_wr_bc = less_than_2_rd_to_wr_bc;
less_than_xn1_wr_to_rd_bc = less_than_2_wr_to_rd_bc;
less_than_xn1_rd_to_rd_diff_chip = less_than_2_rd_to_rd_diff_chip;
less_than_xn1_rd_to_wr_diff_chip = less_than_2_rd_to_wr_diff_chip;
less_than_xn1_wr_to_wr_diff_chip = less_than_2_wr_to_wr_diff_chip;
less_than_xn1_wr_to_rd_diff_chip = less_than_2_wr_to_rd_diff_chip;
less_than_x0_act_to_act_diff_bank = less_than_3_act_to_act_diff_bank;
less_than_x0_rd_to_rd = less_than_3_rd_to_rd;
less_than_x0_rd_to_wr = less_than_3_rd_to_wr;
less_than_x0_wr_to_wr = less_than_3_wr_to_wr;
less_than_x0_wr_to_rd = less_than_3_wr_to_rd;
less_than_x0_rd_to_wr_bc = less_than_3_rd_to_wr_bc;
less_than_x0_wr_to_rd_bc = less_than_3_wr_to_rd_bc;
less_than_x0_rd_to_rd_diff_chip = less_than_3_rd_to_rd_diff_chip;
less_than_x0_rd_to_wr_diff_chip = less_than_3_rd_to_wr_diff_chip;
less_than_x0_wr_to_wr_diff_chip = less_than_3_wr_to_wr_diff_chip;
less_than_x0_wr_to_rd_diff_chip = less_than_3_wr_to_rd_diff_chip;
less_than_x1_act_to_act_diff_bank = less_than_4_act_to_act_diff_bank;
less_than_x1_rd_to_rd = less_than_4_rd_to_rd;
less_than_x1_rd_to_wr = less_than_4_rd_to_wr;
less_than_x1_wr_to_wr = less_than_4_wr_to_wr;
less_than_x1_wr_to_rd = less_than_4_wr_to_rd;
less_than_x1_rd_to_wr_bc = less_than_4_rd_to_wr_bc;
less_than_x1_wr_to_rd_bc = less_than_4_wr_to_rd_bc;
less_than_x1_rd_to_rd_diff_chip = less_than_4_rd_to_rd_diff_chip;
less_than_x1_rd_to_wr_diff_chip = less_than_4_rd_to_wr_diff_chip;
less_than_x1_wr_to_wr_diff_chip = less_than_4_wr_to_wr_diff_chip;
less_than_x1_wr_to_rd_diff_chip = less_than_4_wr_to_rd_diff_chip;
end
else
begin
// Doesn't matter for less_than_xn1_* if CFG_RANK_TIMER_OUTPUT_REG is '0'
less_than_xn1_act_to_act_diff_bank = less_than_2_act_to_act_diff_bank;
less_than_xn1_rd_to_rd = less_than_2_rd_to_rd;
less_than_xn1_rd_to_wr = less_than_2_rd_to_wr;
less_than_xn1_wr_to_wr = less_than_2_wr_to_wr;
less_than_xn1_wr_to_rd = less_than_2_wr_to_rd;
less_than_xn1_rd_to_wr_bc = less_than_2_rd_to_wr_bc;
less_than_xn1_wr_to_rd_bc = less_than_2_wr_to_rd_bc;
less_than_xn1_rd_to_rd_diff_chip = less_than_2_rd_to_rd_diff_chip;
less_than_xn1_rd_to_wr_diff_chip = less_than_2_rd_to_wr_diff_chip;
less_than_xn1_wr_to_wr_diff_chip = less_than_2_wr_to_wr_diff_chip;
less_than_xn1_wr_to_rd_diff_chip = less_than_2_wr_to_rd_diff_chip;
less_than_x0_act_to_act_diff_bank = less_than_2_act_to_act_diff_bank;
less_than_x0_rd_to_rd = less_than_2_rd_to_rd;
less_than_x0_rd_to_wr = less_than_2_rd_to_wr;
less_than_x0_wr_to_wr = less_than_2_wr_to_wr;
less_than_x0_wr_to_rd = less_than_2_wr_to_rd;
less_than_x0_rd_to_wr_bc = less_than_2_rd_to_wr_bc;
less_than_x0_wr_to_rd_bc = less_than_2_wr_to_rd_bc;
less_than_x0_rd_to_rd_diff_chip = less_than_2_rd_to_rd_diff_chip;
less_than_x0_rd_to_wr_diff_chip = less_than_2_rd_to_wr_diff_chip;
less_than_x0_wr_to_wr_diff_chip = less_than_2_wr_to_wr_diff_chip;
less_than_x0_wr_to_rd_diff_chip = less_than_2_wr_to_rd_diff_chip;
less_than_x1_act_to_act_diff_bank = less_than_3_act_to_act_diff_bank;
less_than_x1_rd_to_rd = less_than_3_rd_to_rd;
less_than_x1_rd_to_wr = less_than_3_rd_to_wr;
less_than_x1_wr_to_wr = less_than_3_wr_to_wr;
less_than_x1_wr_to_rd = less_than_3_wr_to_rd;
less_than_x1_rd_to_wr_bc = less_than_3_rd_to_wr_bc;
less_than_x1_wr_to_rd_bc = less_than_3_wr_to_rd_bc;
less_than_x1_rd_to_rd_diff_chip = less_than_3_rd_to_rd_diff_chip;
less_than_x1_rd_to_wr_diff_chip = less_than_3_rd_to_wr_diff_chip;
less_than_x1_wr_to_wr_diff_chip = less_than_3_wr_to_wr_diff_chip;
less_than_x1_wr_to_rd_diff_chip = less_than_3_wr_to_rd_diff_chip;
end
end
end
else
begin
always @ (*)
begin
if (CFG_RANK_TIMER_OUTPUT_REG)
begin
less_than_xn1_act_to_act_diff_bank = less_than_1_act_to_act_diff_bank;
less_than_xn1_rd_to_rd = less_than_1_rd_to_rd;
less_than_xn1_rd_to_wr = less_than_1_rd_to_wr;
less_than_xn1_wr_to_wr = less_than_1_wr_to_wr;
less_than_xn1_wr_to_rd = less_than_1_wr_to_rd;
less_than_xn1_rd_to_wr_bc = less_than_1_rd_to_wr_bc;
less_than_xn1_wr_to_rd_bc = less_than_1_wr_to_rd_bc;
less_than_xn1_rd_to_rd_diff_chip = less_than_1_rd_to_rd_diff_chip;
less_than_xn1_rd_to_wr_diff_chip = less_than_1_rd_to_wr_diff_chip;
less_than_xn1_wr_to_wr_diff_chip = less_than_1_wr_to_wr_diff_chip;
less_than_xn1_wr_to_rd_diff_chip = less_than_1_wr_to_rd_diff_chip;
less_than_x0_act_to_act_diff_bank = less_than_2_act_to_act_diff_bank;
less_than_x0_rd_to_rd = less_than_2_rd_to_rd;
less_than_x0_rd_to_wr = less_than_2_rd_to_wr;
less_than_x0_wr_to_wr = less_than_2_wr_to_wr;
less_than_x0_wr_to_rd = less_than_2_wr_to_rd;
less_than_x0_rd_to_wr_bc = less_than_2_rd_to_wr_bc;
less_than_x0_wr_to_rd_bc = less_than_2_wr_to_rd_bc;
less_than_x0_rd_to_rd_diff_chip = less_than_2_rd_to_rd_diff_chip;
less_than_x0_rd_to_wr_diff_chip = less_than_2_rd_to_wr_diff_chip;
less_than_x0_wr_to_wr_diff_chip = less_than_2_wr_to_wr_diff_chip;
less_than_x0_wr_to_rd_diff_chip = less_than_2_wr_to_rd_diff_chip;
less_than_x1_act_to_act_diff_bank = less_than_3_act_to_act_diff_bank;
less_than_x1_rd_to_rd = less_than_3_rd_to_rd;
less_than_x1_rd_to_wr = less_than_3_rd_to_wr;
less_than_x1_wr_to_wr = less_than_3_wr_to_wr;
less_than_x1_wr_to_rd = less_than_3_wr_to_rd;
less_than_x1_rd_to_wr_bc = less_than_3_rd_to_wr_bc;
less_than_x1_wr_to_rd_bc = less_than_3_wr_to_rd_bc;
less_than_x1_rd_to_rd_diff_chip = less_than_3_rd_to_rd_diff_chip;
less_than_x1_rd_to_wr_diff_chip = less_than_3_rd_to_wr_diff_chip;
less_than_x1_wr_to_wr_diff_chip = less_than_3_wr_to_wr_diff_chip;
less_than_x1_wr_to_rd_diff_chip = less_than_3_wr_to_rd_diff_chip;
end
else
begin
// Doesn't matter for less_than_xn1_* if CFG_RANK_TIMER_OUTPUT_REG is '0'
less_than_xn1_act_to_act_diff_bank = less_than_1_act_to_act_diff_bank;
less_than_xn1_rd_to_rd = less_than_1_rd_to_rd;
less_than_xn1_rd_to_wr = less_than_1_rd_to_wr;
less_than_xn1_wr_to_wr = less_than_1_wr_to_wr;
less_than_xn1_wr_to_rd = less_than_1_wr_to_rd;
less_than_xn1_rd_to_wr_bc = less_than_1_rd_to_wr_bc;
less_than_xn1_wr_to_rd_bc = less_than_1_wr_to_rd_bc;
less_than_xn1_rd_to_rd_diff_chip = less_than_1_rd_to_rd_diff_chip;
less_than_xn1_rd_to_wr_diff_chip = less_than_1_rd_to_wr_diff_chip;
less_than_xn1_wr_to_wr_diff_chip = less_than_1_wr_to_wr_diff_chip;
less_than_xn1_wr_to_rd_diff_chip = less_than_1_wr_to_rd_diff_chip;
less_than_x0_act_to_act_diff_bank = less_than_1_act_to_act_diff_bank;
less_than_x0_rd_to_rd = less_than_1_rd_to_rd;
less_than_x0_rd_to_wr = less_than_1_rd_to_wr;
less_than_x0_wr_to_wr = less_than_1_wr_to_wr;
less_than_x0_wr_to_rd = less_than_1_wr_to_rd;
less_than_x0_rd_to_wr_bc = less_than_1_rd_to_wr_bc;
less_than_x0_wr_to_rd_bc = less_than_1_wr_to_rd_bc;
less_than_x0_rd_to_rd_diff_chip = less_than_1_rd_to_rd_diff_chip;
less_than_x0_rd_to_wr_diff_chip = less_than_1_rd_to_wr_diff_chip;
less_than_x0_wr_to_wr_diff_chip = less_than_1_wr_to_wr_diff_chip;
less_than_x0_wr_to_rd_diff_chip = less_than_1_wr_to_rd_diff_chip;
less_than_x1_act_to_act_diff_bank = less_than_2_act_to_act_diff_bank;
less_than_x1_rd_to_rd = less_than_2_rd_to_rd;
less_than_x1_rd_to_wr = less_than_2_rd_to_wr;
less_than_x1_wr_to_wr = less_than_2_wr_to_wr;
less_than_x1_wr_to_rd = less_than_2_wr_to_rd;
less_than_x1_rd_to_wr_bc = less_than_2_rd_to_wr_bc;
less_than_x1_wr_to_rd_bc = less_than_2_wr_to_rd_bc;
less_than_x1_rd_to_rd_diff_chip = less_than_2_rd_to_rd_diff_chip;
less_than_x1_rd_to_wr_diff_chip = less_than_2_rd_to_wr_diff_chip;
less_than_x1_wr_to_wr_diff_chip = less_than_2_wr_to_wr_diff_chip;
less_than_x1_wr_to_rd_diff_chip = less_than_2_wr_to_rd_diff_chip;
end
end
end
end
endgenerate
//--------------------------------------------------------------------------------------------------------
//
// [END] Timing Parameter Comparison Logic
//
//--------------------------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------------------------
//
// [START] Activate Monitor
//
// Monitors the following rank timing parameters:
//
// - tFAW, four activate window, only four activate is allowed in a specific timing window
// - tRRD, activate to activate different bank
//
//--------------------------------------------------------------------------------------------------------
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
sel_act_tfaw_shift_out_point <= 0;
end
else
begin
if (ENABLE_BETTER_TRRD_EFFICIENCY)
begin
sel_act_tfaw_shift_out_point <= t_param_four_act_to_act - RANK_TIMER_TFAW_OFFSET + 1;
end
else
begin
sel_act_tfaw_shift_out_point <= t_param_four_act_to_act - RANK_TIMER_TFAW_OFFSET;
end
end
end
generate
genvar t_cs;
genvar t_tfaw;
for (t_cs = 0;t_cs < CFG_MEM_IF_CHIP;t_cs = t_cs + 1)
begin : act_monitor_per_chip
//----------------------------------------------------------------------------------------------------
// tFAW Monitor
//----------------------------------------------------------------------------------------------------
reg [ACTIVATE_COMMAND_WIDTH - 1 : 0] act_tfaw_cmd_cnt;
reg [NUM_OF_TFAW_SHIFT_REG - 1 : 0] act_tfaw_shift_reg;
assign act_tfaw_cmd_count [t_cs] = act_tfaw_cmd_cnt;
// Shift register to keep track of tFAW
// Shift in -> n, n-1, n-2, n-3.......4, 3 -> Shift out
// Shift in '1' when there is an activate else shift in '0'
// Shift out every clock cycles
// Shift register [3]
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
act_tfaw_shift_reg [3] <= 1'b0;
end
else
begin
// Shift in '1' if there is an activate
// else shift in '0'
if (int_do_activate && int_to_chip_r [t_cs])
act_tfaw_shift_reg [3] <= 1'b1;
else
act_tfaw_shift_reg [3] <= 1'b0;
end
end
// Shift register [n : 3]
for (t_tfaw = 4;t_tfaw < NUM_OF_TFAW_SHIFT_REG;t_tfaw = t_tfaw + 1)
begin : tfaw_shift_register
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
act_tfaw_shift_reg [t_tfaw] <= 1'b0;
end
else
begin
act_tfaw_shift_reg [t_tfaw] <= act_tfaw_shift_reg [t_tfaw - 1];
end
end
end
// Activate command counter
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
act_tfaw_cmd_cnt <= 0;
end
else
begin
if (int_do_activate && int_to_chip_r [t_cs])
begin
if (act_tfaw_shift_reg [sel_act_tfaw_shift_out_point]) // Shift out when activate reaches tFAW point in shift register
act_tfaw_cmd_cnt <= act_tfaw_cmd_cnt;
else
act_tfaw_cmd_cnt <= act_tfaw_cmd_cnt + 1'b1;
end
else if (act_tfaw_shift_reg [sel_act_tfaw_shift_out_point]) // Shift out when activate reaches tFAW point in shift register
act_tfaw_cmd_cnt <= act_tfaw_cmd_cnt - 1'b1;
end
end
// tFAW ready signal
always @ (*)
begin
// If tFAW is lesser than 4, this means we can do back-to-back activate without tFAW constraint
if (less_than_4_four_act_to_act)
begin
act_tfaw_ready_combi [t_cs] = 1'b1;
end
else
begin
if (int_do_activate && int_to_chip_r [t_cs] && act_tfaw_cmd_cnt == 3'd3)
act_tfaw_ready_combi [t_cs] = 1'b0;
else if (act_tfaw_cmd_cnt < 3'd4)
act_tfaw_ready_combi [t_cs] = 1'b1;
else
act_tfaw_ready_combi [t_cs] = 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
act_tfaw_ready [t_cs] <= 1'b0;
end
else
begin
act_tfaw_ready [t_cs] <= act_tfaw_ready_combi [t_cs];
end
end
//----------------------------------------------------------------------------------------------------
// tRRD Monitor
//----------------------------------------------------------------------------------------------------
reg [ACTIVATE_COUNTER_WIDTH - 1 : 0] act_trrd_cnt;
// tRRD counter
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
act_trrd_cnt <= 0;
end
else
begin
if (int_do_activate && int_to_chip_r [t_cs])
begin
if (ENABLE_BETTER_TRRD_EFFICIENCY)
begin
act_trrd_cnt <= RANK_TIMER_COUNTER_OFFSET - 1;
end
else
begin
act_trrd_cnt <= RANK_TIMER_COUNTER_OFFSET;
end
end
else if (act_trrd_cnt != {ACTIVATE_COUNTER_WIDTH{1'b1}})
begin
act_trrd_cnt <= act_trrd_cnt + 1'b1;
end
end
end
// tRRD monitor
always @ (*)
begin
if (int_do_activate && int_to_chip_r [t_cs])
begin
if (!ENABLE_BETTER_TRRD_EFFICIENCY && less_than_x0_act_to_act_diff_bank)
act_trrd_ready_combi [t_cs] = 1'b1;
else if (ENABLE_BETTER_TRRD_EFFICIENCY && less_than_xn1_act_to_act_diff_bank)
act_trrd_ready_combi [t_cs] = 1'b1;
else
act_trrd_ready_combi [t_cs] = 1'b0;
end
else if (act_trrd_cnt >= t_param_act_to_act_diff_bank)
act_trrd_ready_combi [t_cs] = 1'b1;
else
act_trrd_ready_combi [t_cs] = 1'b0;
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
act_trrd_ready [t_cs] <= 1'b0;
end
else
begin
act_trrd_ready [t_cs] <= act_trrd_ready_combi [t_cs];
end
end
//----------------------------------------------------------------------------------------------------
// Overall activate ready
//----------------------------------------------------------------------------------------------------
always @ (*)
begin
if (!CFG_RANK_TIMER_OUTPUT_REG && stall_chip [t_cs])
begin
act_ready [t_cs] = 1'b0;
end
else
begin
if (ENABLE_BETTER_TRRD_EFFICIENCY)
begin
act_ready [t_cs] = act_trrd_ready_combi [t_cs] & act_tfaw_ready_combi [t_cs];
end
else
begin
act_ready [t_cs] = act_trrd_ready [t_cs] & act_tfaw_ready [t_cs];
end
end
end
end
endgenerate
//--------------------------------------------------------------------------------------------------------
//
// [END] Activate Monitor
//
//--------------------------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------------------------
//
// [START] Read/Write Monitor
//
// Monitors the following rank timing parameters:
//
// - Write to read timing parameter (tWTR)
// - Read to write timing parameter
//
// Missing Features:
//
// - Burst interrupt
// - Burst terminate
//
//--------------------------------------------------------------------------------------------------------
//----------------------------------------------------------------------------------------------------
// Effective Timing Parameters
// Only when burst interrupt option is enabled
//----------------------------------------------------------------------------------------------------
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
max_local_burst_size <= 0;
end
else
begin
max_local_burst_size <= cfg_burst_length / CFG_DWIDTH_RATIO;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
effective_rd_to_wr <= 0;
effective_rd_to_wr_diff_chip <= 0;
effective_wr_to_rd <= 0;
effective_wr_to_rd_diff_chip <= 0;
end
else
begin
if (int_do_burst_chop)
begin
effective_rd_to_wr <= t_param_rd_to_wr_bc;
effective_rd_to_wr_diff_chip <= t_param_rd_to_wr_diff_chip;
effective_wr_to_rd <= t_param_wr_to_rd_bc;
effective_wr_to_rd_diff_chip <= t_param_wr_to_rd_diff_chip;
end
else if (int_do_burst_terminate)
begin
if (t_param_rd_to_wr > (max_local_burst_size - int_effective_size))
effective_rd_to_wr <= t_param_rd_to_wr - (max_local_burst_size - int_effective_size);
else
effective_rd_to_wr <= 1'b1;
if (t_param_rd_to_wr_diff_chip > (max_local_burst_size - int_effective_size))
effective_rd_to_wr_diff_chip <= t_param_rd_to_wr_diff_chip - (max_local_burst_size - int_effective_size);
else
effective_rd_to_wr_diff_chip <= 1'b1;
if (t_param_wr_to_rd > (max_local_burst_size - int_effective_size))
effective_wr_to_rd <= t_param_wr_to_rd - (max_local_burst_size - int_effective_size);
else
effective_wr_to_rd <= 1'b1;
if (t_param_wr_to_rd_diff_chip > (max_local_burst_size - int_effective_size))
effective_wr_to_rd_diff_chip <= t_param_wr_to_rd_diff_chip - (max_local_burst_size - int_effective_size);
else
effective_wr_to_rd_diff_chip <= 1'b1;
end
end
end
//----------------------------------------------------------------------------------------------------
// Read / Write State Machine
//----------------------------------------------------------------------------------------------------
generate
genvar s_cs;
for (s_cs = 0;s_cs < CFG_MEM_IF_CHIP;s_cs = s_cs + 1)
begin : rdwr_monitor_per_chip
reg [31 : 0] rdwr_state;
reg [RDWR_COUNTER_WIDTH - 1 : 0] read_cnt_this_chip;
reg [RDWR_COUNTER_WIDTH - 1 : 0] write_cnt_this_chip;
reg [RDWR_COUNTER_WIDTH - 1 : 0] read_cnt_diff_chip;
reg [RDWR_COUNTER_WIDTH - 1 : 0] write_cnt_diff_chip;
reg int_do_read_this_chip;
reg int_do_write_this_chip;
reg int_do_read_diff_chip;
reg int_do_write_diff_chip;
reg doing_burst_chop;
reg doing_burst_terminate;
reg int_read_ready;
reg int_write_ready;
// Do read/write to this/different chip
always @ (*)
begin
if (int_do_read)
begin
if (int_to_chip_c [s_cs])
begin
int_do_read_this_chip = 1'b1;
int_do_read_diff_chip = 1'b0;
end
else
begin
int_do_read_this_chip = 1'b0;
int_do_read_diff_chip = 1'b1;
end
end
else
begin
int_do_read_this_chip = 1'b0;
int_do_read_diff_chip = 1'b0;
end
end
always @ (*)
begin
if (int_do_write)
begin
if (int_to_chip_c [s_cs])
begin
int_do_write_this_chip = 1'b1;
int_do_write_diff_chip = 1'b0;
end
else
begin
int_do_write_this_chip = 1'b0;
int_do_write_diff_chip = 1'b1;
end
end
else
begin
int_do_write_this_chip = 1'b0;
int_do_write_diff_chip = 1'b0;
end
end
// Read write counter to this chip address
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
read_cnt_this_chip <= 0;
write_cnt_this_chip <= 0;
end
else
begin
if (int_do_read_this_chip)
read_cnt_this_chip <= RANK_TIMER_COUNTER_OFFSET;
else if (read_cnt_this_chip != {RDWR_COUNTER_WIDTH{1'b1}})
read_cnt_this_chip <= read_cnt_this_chip + 1'b1;
if (int_do_write_this_chip)
write_cnt_this_chip <= RANK_TIMER_COUNTER_OFFSET;
else if (write_cnt_this_chip != {RDWR_COUNTER_WIDTH{1'b1}})
write_cnt_this_chip <= write_cnt_this_chip + 1'b1;
end
end
// Read write counter to different chip address
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
read_cnt_diff_chip <= 0;
write_cnt_diff_chip <= 0;
end
else
begin
if (int_do_read_diff_chip)
read_cnt_diff_chip <= RANK_TIMER_COUNTER_OFFSET;
else if (read_cnt_diff_chip != {RDWR_COUNTER_WIDTH{1'b1}})
read_cnt_diff_chip <= read_cnt_diff_chip + 1'b1;
if (int_do_write_diff_chip)
write_cnt_diff_chip <= RANK_TIMER_COUNTER_OFFSET;
else if (write_cnt_diff_chip != {RDWR_COUNTER_WIDTH{1'b1}})
write_cnt_diff_chip <= write_cnt_diff_chip + 1'b1;
end
end
// Doing burst chop signal
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
doing_burst_chop <= 1'b0;
end
else
begin
if (int_do_read || int_do_write)
begin
if (int_do_burst_chop)
doing_burst_chop <= 1'b1;
else
doing_burst_chop <= 1'b0;
end
end
end
// Doing burst terminate signal
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
doing_burst_terminate <= 1'b0;
end
else
begin
if (int_do_read || int_do_write)
doing_burst_terminate <= 1'b0;
else if (int_do_burst_terminate)
doing_burst_terminate <= 1'b1;
end
end
// Register comparison logic for better fMAX
reg compare_rd_cnt_this_chip_greater_eq_than_t_param_rd_to_rd;
reg compare_rd_cnt_diff_chip_greater_eq_than_t_param_rd_to_rd_diff_chip;
reg compare_rd_cnt_this_chip_greater_eq_than_t_param_rd_to_wr;
reg compare_rd_cnt_diff_chip_greater_eq_than_t_param_rd_to_wr_diff_chip;
reg compare_wr_cnt_this_chip_greater_eq_than_t_param_wr_to_wr;
reg compare_wr_cnt_diff_chip_greater_eq_than_t_param_wr_to_wr_diff_chip;
reg compare_wr_cnt_this_chip_greater_eq_than_t_param_wr_to_rd;
reg compare_wr_cnt_diff_chip_greater_eq_than_t_param_wr_to_rd_diff_chip;
reg compare_rd_cnt_this_chip_greater_eq_than_effective_rd_to_wr;
reg compare_rd_cnt_diff_chip_greater_eq_than_effective_rd_to_wr_diff_chip;
reg compare_wr_cnt_this_chip_greater_eq_than_effective_wr_to_rd;
reg compare_wr_cnt_diff_chip_greater_eq_than_effective_wr_to_rd_diff_chip;
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
compare_rd_cnt_this_chip_greater_eq_than_t_param_rd_to_rd <= 1'b0;
compare_rd_cnt_diff_chip_greater_eq_than_t_param_rd_to_rd_diff_chip <= 1'b0;
compare_rd_cnt_this_chip_greater_eq_than_t_param_rd_to_wr <= 1'b0;
compare_rd_cnt_diff_chip_greater_eq_than_t_param_rd_to_wr_diff_chip <= 1'b0;
compare_wr_cnt_this_chip_greater_eq_than_t_param_wr_to_wr <= 1'b0;
compare_wr_cnt_diff_chip_greater_eq_than_t_param_wr_to_wr_diff_chip <= 1'b0;
compare_wr_cnt_this_chip_greater_eq_than_t_param_wr_to_rd <= 1'b0;
compare_wr_cnt_diff_chip_greater_eq_than_t_param_wr_to_rd_diff_chip <= 1'b0;
end
else
begin
// Read to this chip comparison
if (int_do_read_this_chip)
begin
if (less_than_x1_rd_to_rd)
begin
compare_rd_cnt_this_chip_greater_eq_than_t_param_rd_to_rd <= 1'b1;
end
else
begin
compare_rd_cnt_this_chip_greater_eq_than_t_param_rd_to_rd <= 1'b0;
end
if (less_than_x1_rd_to_wr)
begin
compare_rd_cnt_this_chip_greater_eq_than_t_param_rd_to_wr <= 1'b1;
end
else
begin
compare_rd_cnt_this_chip_greater_eq_than_t_param_rd_to_wr <= 1'b0;
end
end
else
begin
if (read_cnt_this_chip >= (t_param_rd_to_rd - 1'b1))
begin
compare_rd_cnt_this_chip_greater_eq_than_t_param_rd_to_rd <= 1'b1;
end
else
begin
compare_rd_cnt_this_chip_greater_eq_than_t_param_rd_to_rd <= 1'b0;
end
if (read_cnt_this_chip >= (t_param_rd_to_wr - 1'b1))
begin
compare_rd_cnt_this_chip_greater_eq_than_t_param_rd_to_wr <= 1'b1;
end
else
begin
compare_rd_cnt_this_chip_greater_eq_than_t_param_rd_to_wr <= 1'b0;
end
end
// Read to different chip comparison
if (int_do_read_diff_chip)
begin
if (less_than_x1_rd_to_rd_diff_chip)
begin
compare_rd_cnt_diff_chip_greater_eq_than_t_param_rd_to_rd_diff_chip <= 1'b1;
end
else
begin
compare_rd_cnt_diff_chip_greater_eq_than_t_param_rd_to_rd_diff_chip <= 1'b0;
end
if (less_than_x1_rd_to_wr_diff_chip)
begin
compare_rd_cnt_diff_chip_greater_eq_than_t_param_rd_to_wr_diff_chip <= 1'b1;
end
else
begin
compare_rd_cnt_diff_chip_greater_eq_than_t_param_rd_to_wr_diff_chip <= 1'b0;
end
end
else
begin
if (read_cnt_diff_chip >= (t_param_rd_to_rd_diff_chip - 1'b1))
begin
compare_rd_cnt_diff_chip_greater_eq_than_t_param_rd_to_rd_diff_chip <= 1'b1;
end
else
begin
compare_rd_cnt_diff_chip_greater_eq_than_t_param_rd_to_rd_diff_chip <= 1'b0;
end
if (read_cnt_diff_chip >= (t_param_rd_to_wr_diff_chip - 1'b1))
begin
compare_rd_cnt_diff_chip_greater_eq_than_t_param_rd_to_wr_diff_chip <= 1'b1;
end
else
begin
compare_rd_cnt_diff_chip_greater_eq_than_t_param_rd_to_wr_diff_chip <= 1'b0;
end
end
// Write to this chip comparison
if (int_do_write_this_chip)
begin
if (less_than_x1_wr_to_wr)
begin
compare_wr_cnt_this_chip_greater_eq_than_t_param_wr_to_wr <= 1'b1;
end
else
begin
compare_wr_cnt_this_chip_greater_eq_than_t_param_wr_to_wr <= 1'b0;
end
if (less_than_x1_wr_to_rd)
begin
compare_wr_cnt_this_chip_greater_eq_than_t_param_wr_to_rd <= 1'b1;
end
else
begin
compare_wr_cnt_this_chip_greater_eq_than_t_param_wr_to_rd <= 1'b0;
end
end
else
begin
if (write_cnt_this_chip >= (t_param_wr_to_wr - 1'b1))
begin
compare_wr_cnt_this_chip_greater_eq_than_t_param_wr_to_wr <= 1'b1;
end
else
begin
compare_wr_cnt_this_chip_greater_eq_than_t_param_wr_to_wr <= 1'b0;
end
if (write_cnt_this_chip >= (t_param_wr_to_rd - 1'b1))
begin
compare_wr_cnt_this_chip_greater_eq_than_t_param_wr_to_rd <= 1'b1;
end
else
begin
compare_wr_cnt_this_chip_greater_eq_than_t_param_wr_to_rd <= 1'b0;
end
end
// Write to different chip comparison
if (int_do_write_diff_chip)
begin
if (less_than_x1_wr_to_wr_diff_chip)
begin
compare_wr_cnt_diff_chip_greater_eq_than_t_param_wr_to_wr_diff_chip <= 1'b1;
end
else
begin
compare_wr_cnt_diff_chip_greater_eq_than_t_param_wr_to_wr_diff_chip <= 1'b0;
end
if (less_than_x1_wr_to_rd_diff_chip)
begin
compare_wr_cnt_diff_chip_greater_eq_than_t_param_wr_to_rd_diff_chip <= 1'b1;
end
else
begin
compare_wr_cnt_diff_chip_greater_eq_than_t_param_wr_to_rd_diff_chip <= 1'b0;
end
end
else
begin
if (write_cnt_diff_chip >= (t_param_wr_to_wr_diff_chip - 1'b1))
begin
compare_wr_cnt_diff_chip_greater_eq_than_t_param_wr_to_wr_diff_chip <= 1'b1;
end
else
begin
compare_wr_cnt_diff_chip_greater_eq_than_t_param_wr_to_wr_diff_chip <= 1'b0;
end
if (write_cnt_diff_chip >= (t_param_wr_to_rd_diff_chip - 1'b1))
begin
compare_wr_cnt_diff_chip_greater_eq_than_t_param_wr_to_rd_diff_chip <= 1'b1;
end
else
begin
compare_wr_cnt_diff_chip_greater_eq_than_t_param_wr_to_rd_diff_chip <= 1'b0;
end
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
compare_rd_cnt_this_chip_greater_eq_than_effective_rd_to_wr <= 1'b0;
compare_rd_cnt_diff_chip_greater_eq_than_effective_rd_to_wr_diff_chip <= 1'b0;
compare_wr_cnt_this_chip_greater_eq_than_effective_wr_to_rd <= 1'b0;
compare_wr_cnt_diff_chip_greater_eq_than_effective_wr_to_rd_diff_chip <= 1'b0;
end
else
begin
// Read to this chip comparison
if (int_do_read_this_chip)
begin
if (t_param_rd_to_wr <= RANK_TIMER_COUNTER_OFFSET)
// We're not comparing against effective_timing_param because it is not loaded yet!
// It'll take one clock cycle to load, therefore we'r taking the worst case parameter (to be safe on all scenario)
begin
compare_rd_cnt_this_chip_greater_eq_than_effective_rd_to_wr <= 1'b1;
end
else
begin
compare_rd_cnt_this_chip_greater_eq_than_effective_rd_to_wr <= 1'b0;
end
end
else
begin
if (read_cnt_this_chip >= (effective_rd_to_wr - 1'b1))
begin
compare_rd_cnt_this_chip_greater_eq_than_effective_rd_to_wr <= 1'b1;
end
else
begin
compare_rd_cnt_this_chip_greater_eq_than_effective_rd_to_wr <= 1'b0;
end
end
// Read to different chip comparison
if (int_do_read_diff_chip)
begin
if (t_param_rd_to_wr_diff_chip <= RANK_TIMER_COUNTER_OFFSET)
// We're not comparing against effective_timing_param because it is not loaded yet!
// It'll take one clock cycle to load, therefore we'r taking the worst case parameter (to be safe on all scenario)
begin
compare_rd_cnt_diff_chip_greater_eq_than_effective_rd_to_wr_diff_chip <= 1'b1;
end
else
begin
compare_rd_cnt_diff_chip_greater_eq_than_effective_rd_to_wr_diff_chip <= 1'b0;
end
end
else
begin
if (read_cnt_diff_chip >= (effective_rd_to_wr_diff_chip - 1'b1))
begin
compare_rd_cnt_diff_chip_greater_eq_than_effective_rd_to_wr_diff_chip <= 1'b1;
end
else
begin
compare_rd_cnt_diff_chip_greater_eq_than_effective_rd_to_wr_diff_chip <= 1'b0;
end
end
// Write to this chip comparison
if (int_do_write_this_chip)
begin
if (t_param_wr_to_rd <= RANK_TIMER_COUNTER_OFFSET)
// We're not comparing against effective_timing_param because it is not loaded yet!
// It'll take one clock cycle to load, therefore we'r taking the worst case parameter (to be safe on all scenario)
begin
compare_wr_cnt_this_chip_greater_eq_than_effective_wr_to_rd <= 1'b1;
end
else
begin
compare_wr_cnt_this_chip_greater_eq_than_effective_wr_to_rd <= 1'b0;
end
end
else
begin
if (write_cnt_this_chip >= (effective_wr_to_rd - 1'b1))
begin
compare_wr_cnt_this_chip_greater_eq_than_effective_wr_to_rd <= 1'b1;
end
else
begin
compare_wr_cnt_this_chip_greater_eq_than_effective_wr_to_rd <= 1'b0;
end
end
// Write to different chip comparison
if (int_do_write_diff_chip)
begin
if (t_param_wr_to_rd_diff_chip <= RANK_TIMER_COUNTER_OFFSET)
// We're not comparing against effective_timing_param because it is not loaded yet!
// It'll take one clock cycle to load, therefore we'r taking the worst case parameter (to be safe on all scenario)
begin
compare_wr_cnt_diff_chip_greater_eq_than_effective_wr_to_rd_diff_chip <= 1'b1;
end
else
begin
compare_wr_cnt_diff_chip_greater_eq_than_effective_wr_to_rd_diff_chip <= 1'b0;
end
end
else
begin
if (write_cnt_diff_chip >= (effective_wr_to_rd_diff_chip - 1'b1))
begin
compare_wr_cnt_diff_chip_greater_eq_than_effective_wr_to_rd_diff_chip <= 1'b1;
end
else
begin
compare_wr_cnt_diff_chip_greater_eq_than_effective_wr_to_rd_diff_chip <= 1'b0;
end
end
end
end
// Read write monitor state machine
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
rdwr_state <= IDLE;
int_read_ready <= 1'b0;
int_write_ready <= 1'b0;
end
else
begin
case (rdwr_state)
IDLE :
begin
if (int_do_write_this_chip)
begin
rdwr_state <= WR;
if (int_do_burst_chop) // burst chop
begin
if (less_than_x0_wr_to_rd_bc)
int_read_ready <= 1'b1;
else
int_read_ready <= 1'b0;
end
else
begin
if (less_than_x0_wr_to_rd)
int_read_ready <= 1'b1;
else
int_read_ready <= 1'b0;
end
if (less_than_x0_wr_to_wr)
int_write_ready <= 1'b1;
else
int_write_ready <= 1'b0;
end
else if (int_do_write_diff_chip)
begin
rdwr_state <= WR;
if (less_than_x0_wr_to_rd_diff_chip)
int_read_ready <= 1'b1;
else
int_read_ready <= 1'b0;
if (less_than_x0_wr_to_wr_diff_chip)
int_write_ready <= 1'b1;
else
int_write_ready <= 1'b0;
end
else if (int_do_read_this_chip)
begin
rdwr_state <= RD;
if (less_than_x0_rd_to_rd)
int_read_ready <= 1'b1;
else
int_read_ready <= 1'b0;
if (int_do_burst_chop) // burst chop
begin
if (less_than_x0_rd_to_wr_bc)
int_write_ready <= 1'b1;
else
int_write_ready <= 1'b0;
end
else
begin
if (less_than_x0_rd_to_wr)
int_write_ready <= 1'b1;
else
int_write_ready <= 1'b0;
end
end
else if (int_do_read_diff_chip)
begin
rdwr_state <= RD;
if (less_than_x0_rd_to_rd_diff_chip)
int_read_ready <= 1'b1;
else
int_read_ready <= 1'b0;
if (less_than_x0_rd_to_wr_diff_chip)
int_write_ready <= 1'b1;
else
int_write_ready <= 1'b0;
end
else
begin
rdwr_state <= IDLE;
int_read_ready <= 1'b1;
int_write_ready <= 1'b1;
end
end
WR :
begin
if (int_do_write_this_chip)
begin
rdwr_state <= WR;
if (int_do_burst_chop) // burst chop
begin
if (less_than_x0_wr_to_rd_bc)
int_read_ready <= 1'b1;
else
int_read_ready <= 1'b0;
end
else
begin
if (less_than_x0_wr_to_rd)
int_read_ready <= 1'b1;
else
int_read_ready <= 1'b0;
end
if (less_than_x0_wr_to_wr)
int_write_ready <= 1'b1;
else
int_write_ready <= 1'b0;
end
else if (int_do_write_diff_chip)
begin
rdwr_state <= WR;
if (less_than_x0_wr_to_rd_diff_chip && compare_wr_cnt_this_chip_greater_eq_than_t_param_wr_to_rd) // making sure previous write timing is satisfied
int_read_ready <= 1'b1;
else
int_read_ready <= 1'b0;
if (less_than_x0_wr_to_wr_diff_chip && compare_rd_cnt_this_chip_greater_eq_than_t_param_rd_to_wr) // making sure previous read timing is satisfied
int_write_ready <= 1'b1;
else
int_write_ready <= 1'b0;
end
else if (int_do_read_this_chip)
begin
rdwr_state <= RD;
if (less_than_x0_rd_to_rd)
int_read_ready <= 1'b1;
else
int_read_ready <= 1'b0;
if (int_do_burst_chop) // burst chop
begin
if (less_than_x0_rd_to_wr_bc)
int_write_ready <= 1'b1;
else
int_write_ready <= 1'b0;
end
else
begin
if (less_than_x0_rd_to_wr)
int_write_ready <= 1'b1;
else
int_write_ready <= 1'b0;
end
end
else if (int_do_read_diff_chip)
begin
rdwr_state <= RD;
if (less_than_x0_rd_to_rd_diff_chip && compare_wr_cnt_this_chip_greater_eq_than_t_param_wr_to_rd) // making sure previous write timing is satisfied
int_read_ready <= 1'b1;
else
int_read_ready <= 1'b0;
if (less_than_x0_rd_to_wr_diff_chip && compare_rd_cnt_this_chip_greater_eq_than_t_param_rd_to_wr) // making sure previous read timing is satisfied
int_write_ready <= 1'b1;
else
int_write_ready <= 1'b0;
end
else
begin
if (doing_burst_chop || doing_burst_terminate) // burst chop or burst terminate
begin
if (compare_wr_cnt_this_chip_greater_eq_than_effective_wr_to_rd && compare_rd_cnt_this_chip_greater_eq_than_t_param_rd_to_rd &&
compare_wr_cnt_diff_chip_greater_eq_than_effective_wr_to_rd_diff_chip && compare_rd_cnt_diff_chip_greater_eq_than_t_param_rd_to_rd_diff_chip )
int_read_ready <= 1'b1;
else
int_read_ready <= 1'b0;
if (compare_wr_cnt_this_chip_greater_eq_than_t_param_wr_to_wr && compare_rd_cnt_this_chip_greater_eq_than_effective_rd_to_wr &&
compare_wr_cnt_diff_chip_greater_eq_than_t_param_wr_to_wr_diff_chip && compare_rd_cnt_diff_chip_greater_eq_than_effective_rd_to_wr_diff_chip )
int_write_ready <= 1'b1;
else
int_write_ready <= 1'b0;
end
else
begin
if (compare_wr_cnt_this_chip_greater_eq_than_t_param_wr_to_rd && compare_rd_cnt_this_chip_greater_eq_than_t_param_rd_to_rd &&
compare_wr_cnt_diff_chip_greater_eq_than_t_param_wr_to_rd_diff_chip && compare_rd_cnt_diff_chip_greater_eq_than_t_param_rd_to_rd_diff_chip )
int_read_ready <= 1'b1;
else
int_read_ready <= 1'b0;
if (compare_wr_cnt_this_chip_greater_eq_than_t_param_wr_to_wr && compare_rd_cnt_this_chip_greater_eq_than_t_param_rd_to_wr &&
compare_wr_cnt_diff_chip_greater_eq_than_t_param_wr_to_wr_diff_chip && compare_rd_cnt_diff_chip_greater_eq_than_t_param_rd_to_wr_diff_chip )
int_write_ready <= 1'b1;
else
int_write_ready <= 1'b0;
end
end
end
RD :
begin
if (int_do_write_this_chip)
begin
rdwr_state <= WR;
if (int_do_burst_chop) // burst chop
begin
if (less_than_x0_wr_to_rd_bc)
int_read_ready <= 1'b1;
else
int_read_ready <= 1'b0;
end
else
begin
if (less_than_x0_wr_to_rd)
int_read_ready <= 1'b1;
else
int_read_ready <= 1'b0;
end
if (less_than_x0_wr_to_wr)
int_write_ready <= 1'b1;
else
int_write_ready <= 1'b0;
end
else if (int_do_write_diff_chip)
begin
rdwr_state <= WR;
if (less_than_x0_wr_to_rd_diff_chip && compare_wr_cnt_this_chip_greater_eq_than_effective_wr_to_rd) // making sure previous write timing is satisfied
int_read_ready <= 1'b1;
else
int_read_ready <= 1'b0;
if (less_than_x0_wr_to_wr_diff_chip && compare_rd_cnt_this_chip_greater_eq_than_t_param_rd_to_wr) // making sure previous read timing is satisfied
int_write_ready <= 1'b1;
else
int_write_ready <= 1'b0;
end
else if (int_do_read_this_chip)
begin
rdwr_state <= RD;
if (less_than_x0_rd_to_rd)
int_read_ready <= 1'b1;
else
int_read_ready <= 1'b0;
if (int_do_burst_chop) // burst chop
begin
if (less_than_x0_rd_to_wr_bc)
int_write_ready <= 1'b1;
else
int_write_ready <= 1'b0;
end
else
begin
if (less_than_x0_rd_to_wr)
int_write_ready <= 1'b1;
else
int_write_ready <= 1'b0;
end
end
else if (int_do_read_diff_chip)
begin
rdwr_state <= RD;
if (less_than_x0_rd_to_rd_diff_chip && compare_wr_cnt_this_chip_greater_eq_than_effective_wr_to_rd) // making sure previous write timing is satisfied
int_read_ready <= 1'b1;
else
int_read_ready <= 1'b0;
if (less_than_x0_rd_to_wr_diff_chip && compare_rd_cnt_this_chip_greater_eq_than_t_param_rd_to_wr) // making sure previous read timing is satisfied
int_write_ready <= 1'b1;
else
int_write_ready <= 1'b0;
end
else
begin
if (doing_burst_chop || doing_burst_terminate) // burst chop or burst terminate
begin
if (compare_rd_cnt_this_chip_greater_eq_than_t_param_rd_to_rd && compare_wr_cnt_this_chip_greater_eq_than_effective_wr_to_rd &&
compare_rd_cnt_diff_chip_greater_eq_than_t_param_rd_to_rd_diff_chip && compare_wr_cnt_diff_chip_greater_eq_than_effective_wr_to_rd_diff_chip )
int_read_ready <= 1'b1;
else
int_read_ready <= 1'b0;
if (compare_rd_cnt_this_chip_greater_eq_than_effective_rd_to_wr && compare_wr_cnt_this_chip_greater_eq_than_t_param_wr_to_wr &&
compare_rd_cnt_diff_chip_greater_eq_than_effective_rd_to_wr_diff_chip && compare_wr_cnt_diff_chip_greater_eq_than_t_param_wr_to_wr_diff_chip )
int_write_ready <= 1'b1;
else
int_write_ready <= 1'b0;
end
else
begin
if (compare_rd_cnt_this_chip_greater_eq_than_t_param_rd_to_rd && compare_wr_cnt_this_chip_greater_eq_than_t_param_wr_to_rd &&
compare_rd_cnt_diff_chip_greater_eq_than_t_param_rd_to_rd_diff_chip && compare_wr_cnt_diff_chip_greater_eq_than_t_param_wr_to_rd_diff_chip )
int_read_ready <= 1'b1;
else
int_read_ready <= 1'b0;
if (compare_rd_cnt_this_chip_greater_eq_than_t_param_rd_to_wr && compare_wr_cnt_this_chip_greater_eq_than_t_param_wr_to_wr &&
compare_rd_cnt_diff_chip_greater_eq_than_t_param_rd_to_wr_diff_chip && compare_wr_cnt_diff_chip_greater_eq_than_t_param_wr_to_wr_diff_chip)
int_write_ready <= 1'b1;
else
int_write_ready <= 1'b0;
end
end
end
default :
rdwr_state <= IDLE;
endcase
end
end
// Assign read/write ready signal to top
always @ (*)
begin
if (!CFG_RANK_TIMER_OUTPUT_REG && stall_chip [s_cs])
begin
read_ready [s_cs] = 1'b0;
write_ready [s_cs] = 1'b0;
end
else
begin
if (CFG_RANK_TIMER_OUTPUT_REG)
begin
read_ready [s_cs] = int_read_ready;
write_ready [s_cs] = int_write_ready;
end
else
begin
read_ready [s_cs] = int_read_ready & int_interrupt_ready;
write_ready [s_cs] = int_write_ready & int_interrupt_ready;
end
end
end
end
endgenerate
//--------------------------------------------------------------------------------------------------------
//
// [END] Read/Write Monitor
//
//--------------------------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------------------------
//
// [START] Precharge Monitor
//
//--------------------------------------------------------------------------------------------------------
generate
genvar u_cs;
for (u_cs = 0;u_cs < CFG_MEM_IF_CHIP;u_cs = u_cs + 1)
begin : pch_monitor_per_chip
always @ (*)
begin
if (!CFG_RANK_TIMER_OUTPUT_REG && stall_chip [u_cs])
pch_ready [u_cs] = 1'b0;
else
pch_ready [u_cs] = one;
end
end
endgenerate
//--------------------------------------------------------------------------------------------------------
//
// [END] Precharge Monitor
//
//--------------------------------------------------------------------------------------------------------
endmodule
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
//altera message_off 10230 10036
`include "alt_mem_ddrx_define.iv"
module alt_mem_ddrx_rdata_path
# (
// module parameter port list
parameter
CFG_LOCAL_DATA_WIDTH = 8,
CFG_INT_SIZE_WIDTH = 2,
CFG_DATA_ID_WIDTH = 3, // number of buckets
CFG_LOCAL_ID_WIDTH = 3,
CFG_LOCAL_ADDR_WIDTH = 32,
CFG_BUFFER_ADDR_WIDTH = 5,
CFG_MEM_IF_CS_WIDTH = 2,
CFG_MEM_IF_BA_WIDTH = 3,
CFG_MEM_IF_ROW_WIDTH = 13,
CFG_MEM_IF_COL_WIDTH = 10,
CFG_MAX_READ_CMD_NUM_WIDTH = 4, // expected in-flight read commands at a time
CFG_RDATA_RETURN_MODE = "PASSTHROUGH", // INORDER, PASSTHROUGH
CFG_AFI_INTF_PHASE_NUM = 2,
CFG_ERRCMD_FIFO_ADDR_WIDTH = 3,
CFG_DWIDTH_RATIO = 2,
CFG_ECC_MULTIPLES = 1,
CFG_ECC_CODE_WIDTH = 8,
CFG_PORT_WIDTH_TYPE = 3,
CFG_PORT_WIDTH_ENABLE_ECC = 1,
CFG_PORT_WIDTH_ENABLE_AUTO_CORR = 1,
CFG_PORT_WIDTH_ENABLE_NO_DM = 1,
CFG_PORT_WIDTH_BURST_LENGTH = 5,
CFG_PORT_WIDTH_ADDR_ORDER = 2,
CFG_PORT_WIDTH_COL_ADDR_WIDTH = 9,
CFG_PORT_WIDTH_ROW_ADDR_WIDTH = 12,
CFG_PORT_WIDTH_BANK_ADDR_WIDTH = 3,
CFG_PORT_WIDTH_CS_ADDR_WIDTH = 2
)
(
// port list
ctl_clk,
ctl_reset_n,
// configuration
cfg_type,
cfg_enable_ecc,
cfg_enable_auto_corr,
cfg_enable_no_dm,
cfg_burst_length,
cfg_addr_order,
cfg_col_addr_width,
cfg_row_addr_width,
cfg_bank_addr_width,
cfg_cs_addr_width,
// command generator & TBP command load interface / cmd update interface
rdatap_free_id_valid,
rdatap_free_id_dataid,
proc_busy,
proc_load,
proc_load_dataid,
proc_read,
proc_size,
proc_localid,
// input interface data channel / buffer read interface
read_data_valid, // data sent to either dataid_manager, or input interface
read_data,
read_data_error,
read_data_localid,
// Arbiter issued reads interface
bg_do_read,
bg_to_chipsel,
bg_to_bank,
bg_to_row,
bg_to_column,
bg_dataid,
bg_localid,
bg_size,
bg_do_rmw_correct,
bg_do_rmw_partial,
// read data from memory interface
ecc_rdata,
ecc_rdatav,
ecc_sbe,
ecc_dbe,
ecc_code,
// ECC Error commands interface, to command generator
errcmd_ready,
errcmd_valid,
errcmd_chipsel,
errcmd_bank,
errcmd_row,
errcmd_column,
errcmd_size,
errcmd_localid,
// ECC Error address interface, to ECC block
rdatap_rcvd_addr,
rdatap_rcvd_cmd,
rdatap_rcvd_corr_dropped,
// RMW fifo interface, to wdatap
rmwfifo_data_valid,
rmwfifo_data,
rmwfifo_ecc_dbe,
rmwfifo_ecc_code
);
// -----------------------------
// local parameter declarations
// -----------------------------
localparam CFG_ECC_RDATA_COUNTER_REG = 0; // set to 1 to improve timing
localparam CFG_RMW_BIT_WIDTH = 1;
localparam CFG_RMW_PARTIAL_BIT_WIDTH = 1;
localparam CFG_PENDING_RD_FIFO_WIDTH = CFG_MEM_IF_CS_WIDTH + CFG_MEM_IF_BA_WIDTH + CFG_MEM_IF_ROW_WIDTH + CFG_MEM_IF_COL_WIDTH + CFG_LOCAL_ID_WIDTH + CFG_INT_SIZE_WIDTH + CFG_DATA_ID_WIDTH + CFG_RMW_BIT_WIDTH + CFG_RMW_PARTIAL_BIT_WIDTH;
localparam CFG_ERRCMD_FIFO_WIDTH = CFG_MEM_IF_CS_WIDTH + CFG_MEM_IF_BA_WIDTH + CFG_MEM_IF_ROW_WIDTH + CFG_MEM_IF_COL_WIDTH + CFG_INT_SIZE_WIDTH + CFG_LOCAL_ID_WIDTH;
localparam CFG_INORDER_INFO_FIFO_WIDTH = CFG_INT_SIZE_WIDTH+CFG_LOCAL_ID_WIDTH;
localparam integer CFG_DATAID_ARRAY_DEPTH = 2**CFG_DATA_ID_WIDTH;
localparam CFG_RDATA_ERROR_WIDTH = 1;
localparam CFG_IN_ORDER_BUFFER_DATA_WIDTH = CFG_LOCAL_DATA_WIDTH + CFG_RDATA_ERROR_WIDTH;
localparam CFG_MAX_READ_CMD_NUM = 2**CFG_MAX_READ_CMD_NUM_WIDTH;
localparam MIN_COL = 8;
localparam MIN_ROW = 12;
localparam MIN_BANK = 2;
localparam MIN_CS = 1;
localparam MAX_COL = CFG_MEM_IF_COL_WIDTH;
localparam MAX_ROW = CFG_MEM_IF_ROW_WIDTH;
localparam MAX_BANK = CFG_MEM_IF_BA_WIDTH;
localparam MAX_CS = CFG_MEM_IF_CS_WIDTH;
localparam CFG_IGNORE_NUM_BITS_COL = log2 (CFG_DWIDTH_RATIO);
localparam CFG_LOCAL_ADDR_BITSELECT_WIDTH = log2 (CFG_LOCAL_ADDR_WIDTH);
integer j,k,m,n;
// -----------------------------
// port declaration
// -----------------------------
input ctl_clk;
input ctl_reset_n;
// configuration
input [CFG_PORT_WIDTH_TYPE- 1:0] cfg_type;
input [CFG_PORT_WIDTH_ENABLE_ECC-1:0] cfg_enable_ecc;
input [CFG_PORT_WIDTH_ENABLE_AUTO_CORR-1:0] cfg_enable_auto_corr;
input [CFG_PORT_WIDTH_ENABLE_NO_DM-1:0] cfg_enable_no_dm;
input [CFG_PORT_WIDTH_BURST_LENGTH-1:0] cfg_burst_length;
input [CFG_PORT_WIDTH_ADDR_ORDER - 1 : 0] cfg_addr_order;
input [CFG_PORT_WIDTH_COL_ADDR_WIDTH - 1 : 0] cfg_col_addr_width;
input [CFG_PORT_WIDTH_ROW_ADDR_WIDTH - 1 : 0] cfg_row_addr_width;
input [CFG_PORT_WIDTH_BANK_ADDR_WIDTH - 1 : 0] cfg_bank_addr_width;
input [CFG_PORT_WIDTH_CS_ADDR_WIDTH - 1 : 0] cfg_cs_addr_width;
// command generator & TBP command load interface / cmd update interface
output rdatap_free_id_valid;
output [CFG_DATA_ID_WIDTH-1:0] rdatap_free_id_dataid;
input proc_busy;
input proc_load;
input proc_load_dataid;
input proc_read;
input [CFG_INT_SIZE_WIDTH-1:0] proc_size;
input [CFG_LOCAL_ID_WIDTH-1:0] proc_localid;
// input interface data channel
output read_data_valid;
output [CFG_LOCAL_DATA_WIDTH-1:0] read_data;
output read_data_error;
output [CFG_LOCAL_ID_WIDTH-1:0] read_data_localid;
// Arbiter issued reads interface
input [CFG_AFI_INTF_PHASE_NUM-1:0] bg_do_read;
input [CFG_AFI_INTF_PHASE_NUM-1:0] bg_do_rmw_correct;
input [CFG_AFI_INTF_PHASE_NUM-1:0] bg_do_rmw_partial;
input [(CFG_AFI_INTF_PHASE_NUM*CFG_MEM_IF_CS_WIDTH ) -1:0] bg_to_chipsel;
input [(CFG_AFI_INTF_PHASE_NUM*CFG_MEM_IF_BA_WIDTH ) -1:0] bg_to_bank;
input [(CFG_AFI_INTF_PHASE_NUM*CFG_MEM_IF_ROW_WIDTH ) -1:0] bg_to_row;
input [(CFG_AFI_INTF_PHASE_NUM*CFG_MEM_IF_COL_WIDTH ) -1:0] bg_to_column;
input [( CFG_DATA_ID_WIDTH ) -1:0] bg_dataid;
input [( CFG_LOCAL_ID_WIDTH ) -1:0] bg_localid;
input [( CFG_INT_SIZE_WIDTH ) -1:0] bg_size;
// read data from memory interface
input [CFG_LOCAL_DATA_WIDTH-1:0] ecc_rdata;
input ecc_rdatav;
input [CFG_ECC_MULTIPLES - 1 : 0] ecc_sbe;
input [CFG_ECC_MULTIPLES - 1 : 0] ecc_dbe;
input [CFG_ECC_MULTIPLES * CFG_ECC_CODE_WIDTH - 1 : 0] ecc_code;
// ECC Error commands interface, to command generator
input errcmd_ready;
output errcmd_valid;
output [CFG_MEM_IF_CS_WIDTH-1:0] errcmd_chipsel;
output [CFG_MEM_IF_BA_WIDTH-1:0] errcmd_bank;
output [CFG_MEM_IF_ROW_WIDTH-1:0] errcmd_row;
output [CFG_MEM_IF_COL_WIDTH-1:0] errcmd_column;
output [CFG_INT_SIZE_WIDTH-1:0] errcmd_size;
output [CFG_LOCAL_ID_WIDTH-1:0] errcmd_localid;
// ECC Error address interface, to ECC block
output [CFG_LOCAL_ADDR_WIDTH-1:0] rdatap_rcvd_addr;
output rdatap_rcvd_cmd;
output rdatap_rcvd_corr_dropped;
// RMW fifo interface, to wdatap
output rmwfifo_data_valid;
output [CFG_LOCAL_DATA_WIDTH-1:0] rmwfifo_data;
output [CFG_ECC_MULTIPLES - 1 : 0] rmwfifo_ecc_dbe;
output [CFG_ECC_MULTIPLES * CFG_ECC_CODE_WIDTH - 1 : 0] rmwfifo_ecc_code;
// -----------------------------
// port type declaration
// -----------------------------
wire ctl_clk;
wire ctl_reset_n;
// configuration
wire [CFG_PORT_WIDTH_TYPE- 1:0] cfg_type;
wire [CFG_PORT_WIDTH_ENABLE_ECC-1:0] cfg_enable_ecc;
wire [CFG_PORT_WIDTH_ENABLE_AUTO_CORR-1:0] cfg_enable_auto_corr;
wire [CFG_PORT_WIDTH_BURST_LENGTH-1:0] cfg_burst_length;
wire [CFG_PORT_WIDTH_ADDR_ORDER - 1 : 0] cfg_addr_order;
wire [CFG_PORT_WIDTH_COL_ADDR_WIDTH - 1 : 0] cfg_col_addr_width;
wire [CFG_PORT_WIDTH_ROW_ADDR_WIDTH - 1 : 0] cfg_row_addr_width;
wire [CFG_PORT_WIDTH_BANK_ADDR_WIDTH - 1 : 0] cfg_bank_addr_width;
wire [CFG_PORT_WIDTH_CS_ADDR_WIDTH - 1 : 0] cfg_cs_addr_width;
// command generator & TBP command load interface / cmd update interface
reg rdatap_free_id_valid;
reg [CFG_DATA_ID_WIDTH-1:0] rdatap_free_id_dataid;
wire proc_busy;
wire proc_load;
wire proc_load_dataid;
wire proc_read;
wire [CFG_INT_SIZE_WIDTH-1:0] proc_size;
wire [CFG_LOCAL_ID_WIDTH-1:0] proc_localid;
// input interface data channel
reg read_data_valid;
reg [CFG_LOCAL_DATA_WIDTH-1:0] read_data;
reg read_data_error;
reg [CFG_LOCAL_ID_WIDTH-1:0] read_data_localid;
// Arbiter issued reads interface
wire [CFG_AFI_INTF_PHASE_NUM-1:0] bg_do_read;
wire [CFG_AFI_INTF_PHASE_NUM-1:0] bg_do_rmw_correct;
wire [CFG_AFI_INTF_PHASE_NUM-1:0] bg_do_rmw_partial;
wire [(CFG_AFI_INTF_PHASE_NUM*CFG_MEM_IF_CS_WIDTH ) -1:0] bg_to_chipsel;
wire [(CFG_AFI_INTF_PHASE_NUM*CFG_MEM_IF_BA_WIDTH ) -1:0] bg_to_bank;
wire [(CFG_AFI_INTF_PHASE_NUM*CFG_MEM_IF_ROW_WIDTH ) -1:0] bg_to_row;
wire [(CFG_AFI_INTF_PHASE_NUM*CFG_MEM_IF_COL_WIDTH ) -1:0] bg_to_column;
wire [( CFG_DATA_ID_WIDTH ) -1:0] bg_dataid;
wire [( CFG_LOCAL_ID_WIDTH ) -1:0] bg_localid;
wire [( CFG_INT_SIZE_WIDTH ) -1:0] bg_size;
reg [CFG_AFI_INTF_PHASE_NUM-1:0] int_bg_do_read;
reg [CFG_AFI_INTF_PHASE_NUM-1:0] int_bg_do_rmw_correct;
reg [CFG_AFI_INTF_PHASE_NUM-1:0] int_bg_do_rmw_partial;
reg [CFG_MEM_IF_CS_WIDTH -1:0] int_bg_to_chipsel[CFG_AFI_INTF_PHASE_NUM-1:0];
reg [CFG_MEM_IF_BA_WIDTH -1:0] int_bg_to_bank [CFG_AFI_INTF_PHASE_NUM-1:0];
reg [CFG_MEM_IF_ROW_WIDTH -1:0] int_bg_to_row [CFG_AFI_INTF_PHASE_NUM-1:0];
reg [CFG_MEM_IF_COL_WIDTH -1:0] int_bg_to_column [CFG_AFI_INTF_PHASE_NUM-1:0];
reg [CFG_DATA_ID_WIDTH -1:0] int_bg_dataid;
reg [CFG_LOCAL_ID_WIDTH -1:0] int_bg_localid;
reg [CFG_INT_SIZE_WIDTH -1:0] int_bg_size;
// read data from memory interface
wire [CFG_LOCAL_DATA_WIDTH-1:0] ecc_rdata;
wire ecc_rdatav;
wire [CFG_ECC_MULTIPLES- 1 : 0] ecc_sbe;
wire [CFG_ECC_MULTIPLES- 1 : 0] ecc_dbe;
wire [CFG_ECC_MULTIPLES * CFG_ECC_CODE_WIDTH - 1 : 0] ecc_code;
// ECC Error commands interface, to command generator
wire errcmd_ready;
wire errcmd_valid;
wire [CFG_MEM_IF_CS_WIDTH-1:0] errcmd_chipsel;
wire [CFG_MEM_IF_BA_WIDTH-1:0] errcmd_bank;
wire [CFG_MEM_IF_ROW_WIDTH-1:0] errcmd_row;
wire [CFG_MEM_IF_COL_WIDTH-1:0] errcmd_column;
wire [CFG_INT_SIZE_WIDTH-1:0] errcmd_size;
wire [CFG_LOCAL_ID_WIDTH-1:0] errcmd_localid;
// RMW fifo interface, to wdatap
wire rmwfifo_data_valid;
wire [CFG_LOCAL_DATA_WIDTH-1:0] rmwfifo_data;
wire [CFG_ECC_MULTIPLES- 1 : 0] rmwfifo_ecc_dbe;
wire [CFG_ECC_MULTIPLES * CFG_ECC_CODE_WIDTH - 1 : 0] rmwfifo_ecc_code;
reg rdatap_rcvd_cmd;
reg rdatap_rcvd_corr_dropped;
// -----------------------------
// signal declaration
// -----------------------------
wire[CFG_INT_SIZE_WIDTH-1:0] cfg_max_cmd_burstcount;
reg [CFG_LOCAL_ADDR_BITSELECT_WIDTH -1 : 0] cfg_addr_bitsel_chipsel;
reg [CFG_LOCAL_ADDR_BITSELECT_WIDTH -1 : 0] cfg_addr_bitsel_bank;
reg [CFG_LOCAL_ADDR_BITSELECT_WIDTH -1 : 0] cfg_addr_bitsel_row;
wire cmdload_valid;
reg [CFG_MAX_READ_CMD_NUM_WIDTH-1:0] cmd_counter;
reg cmd_counter_full;
wire cmd_counter_load;
wire free_id_get_ready;
wire free_id_valid;
wire [CFG_DATA_ID_WIDTH-1:0] free_id_dataid;
wire [CFG_DATAID_ARRAY_DEPTH-1:0]free_id_dataid_vector;
wire allocated_put_ready;
wire allocated_put_valid;
wire int_free_id_valid;
wire [CFG_PENDING_RD_FIFO_WIDTH-1:0] pfifo_input;
wire [CFG_PENDING_RD_FIFO_WIDTH-1:0] pfifo_output;
wire pfifo_output_valid;
wire pfifo_input_ready;
wire rdata_burst_complete;
reg rdata_burst_complete_r;
reg rout_data_valid; // rout_data sent to dataid_manager
reg rout_cmd_valid; // rout_cmd sent to dataid_manager
reg rout_data_rmwfifo_valid; // rout_data sent to rmwfifo
reg rout_cmd_rmwfifo_valid; // rout_cmd sent to rmwfifo
wire rout_rmw_rmwpartial;
reg rout_data_error;
reg rout_sbecmd_valid;
reg rout_errnotify_valid;
wire [CFG_LOCAL_DATA_WIDTH-1:0] rout_data;
wire [CFG_DATA_ID_WIDTH-1:0] rout_data_dataid;
wire [CFG_LOCAL_ID_WIDTH-1:0] rout_data_localid;
wire [CFG_INT_SIZE_WIDTH-1:0] rout_data_burstcount;
wire [CFG_ECC_MULTIPLES- 1 : 0] rout_ecc_dbe;
wire [CFG_ECC_MULTIPLES * CFG_ECC_CODE_WIDTH - 1 : 0] rout_ecc_code;
reg pfifo_input_do_read;
reg pfifo_input_rmw;
reg pfifo_input_rmw_partial;
reg [CFG_MEM_IF_CS_WIDTH-1:0] pfifo_input_chipsel;
reg [CFG_MEM_IF_BA_WIDTH-1:0] pfifo_input_bank;
reg [CFG_MEM_IF_ROW_WIDTH-1:0] pfifo_input_row;
reg [CFG_MEM_IF_COL_WIDTH-1:0] pfifo_input_column;
reg [CFG_DATA_ID_WIDTH-1:0] pfifo_input_dataid;
reg [CFG_LOCAL_ID_WIDTH-1:0] pfifo_input_localid;
reg [CFG_INT_SIZE_WIDTH-1:0] pfifo_input_size;
reg mux_pfifo_input_rmw [CFG_AFI_INTF_PHASE_NUM -1 : 0];
reg mux_pfifo_input_rmw_partial [CFG_AFI_INTF_PHASE_NUM -1 : 0];
reg [CFG_MEM_IF_CS_WIDTH-1:0] mux_pfifo_input_chipsel [CFG_AFI_INTF_PHASE_NUM -1 : 0];
reg [CFG_MEM_IF_BA_WIDTH-1:0] mux_pfifo_input_bank [CFG_AFI_INTF_PHASE_NUM -1 : 0];
reg [CFG_MEM_IF_ROW_WIDTH-1:0] mux_pfifo_input_row [CFG_AFI_INTF_PHASE_NUM -1 : 0];
reg [CFG_MEM_IF_COL_WIDTH-1:0] mux_pfifo_input_column [CFG_AFI_INTF_PHASE_NUM -1 : 0];
wire pfifo_rmw;
wire pfifo_rmw_partial;
wire [CFG_MEM_IF_CS_WIDTH-1:0] pfifo_chipsel;
wire [CFG_MEM_IF_BA_WIDTH-1:0] pfifo_bank;
wire [CFG_MEM_IF_ROW_WIDTH-1:0] pfifo_row;
wire [CFG_MEM_IF_COL_WIDTH-1:0] pfifo_column;
wire [CFG_MEM_IF_COL_WIDTH-1:0] pfifo_column_burst_aligned;
reg [CFG_MEM_IF_CS_WIDTH-1:0] pfifo_chipsel_r;
reg [CFG_MEM_IF_BA_WIDTH-1:0] pfifo_bank_r;
reg [CFG_MEM_IF_ROW_WIDTH-1:0] pfifo_row_r;
reg [CFG_MEM_IF_COL_WIDTH-1:0] pfifo_column_r;
reg [CFG_MEM_IF_COL_WIDTH-1:0] pfifo_column_burst_aligned_r;
wire [CFG_DATA_ID_WIDTH-1:0] pfifo_dataid;
wire [CFG_LOCAL_ID_WIDTH-1:0] pfifo_localid;
wire [CFG_INT_SIZE_WIDTH-1:0] pfifo_size;
reg [CFG_LOCAL_ADDR_WIDTH-1:0] pfifo_addr;
wire [CFG_INT_SIZE_WIDTH-1:0] ecc_rdata_current_count;
reg [CFG_INT_SIZE_WIDTH-1:0] ecc_rdata_counter;
wire [CFG_INT_SIZE_WIDTH-1:0] ecc_rdatavalid_count;
wire [CFG_INT_SIZE_WIDTH-1:0] ecc_rdata_burst_complete_count;
reg ecc_sbe_cmd_detected;
reg ecc_dbe_cmd_detected;
wire [CFG_DATAID_ARRAY_DEPTH-1:0] dataid_array_valid;
reg [CFG_DATAID_ARRAY_DEPTH-1:0] dataid_array_data_ready;
reg [CFG_BUFFER_ADDR_WIDTH-1:0] dataid_array_burstcount [CFG_DATAID_ARRAY_DEPTH-1:0];
reg [CFG_LOCAL_ID_WIDTH-1:0] dataid_array_localid [CFG_DATAID_ARRAY_DEPTH-1:0];
wire inordr_id_data_complete;
reg inordr_id_data_complete_r;
wire inordr_id_valid;
wire inordr_id_list_valid;
wire inordr_read_data_valid;
reg inordr_read_data_valid_r;
wire [CFG_LOCAL_DATA_WIDTH-1:0] inordr_read_data;
wire inordr_read_data_error;
wire [CFG_DATA_ID_WIDTH-1:0] inordr_id_dataid;
wire [CFG_DATAID_ARRAY_DEPTH-1:0] inordr_id_dataid_vector;
wire [CFG_LOCAL_ID_WIDTH-1:0] inordr_id_localid;
reg [CFG_LOCAL_ID_WIDTH-1:0] inordr_id_localid_r;
reg [CFG_INT_SIZE_WIDTH-1:0] inordr_data_counter;
reg [CFG_INT_SIZE_WIDTH-1:0] inordr_data_counter_plus_1;
wire [CFG_INT_SIZE_WIDTH-1:0] inordr_next_data_counter;
wire [CFG_INT_SIZE_WIDTH-1:0] inordr_id_expected_burstcount;
reg [CFG_DATAID_ARRAY_DEPTH-1:0] mux_inordr_data_ready;
wire inordr_info_input_ready;
wire inordr_info_output_valid;
wire [CFG_INORDER_INFO_FIFO_WIDTH-1:0] inordr_info_input;
wire [CFG_INORDER_INFO_FIFO_WIDTH-1:0] inordr_info_output;
wire [CFG_BUFFER_ADDR_WIDTH-1:0] buffwrite_address;
wire [CFG_INT_SIZE_WIDTH-1:0] buffwrite_offset;
wire [CFG_IN_ORDER_BUFFER_DATA_WIDTH-1:0] buffwrite_data;
wire [CFG_BUFFER_ADDR_WIDTH-1:0] buffread_address;
wire [CFG_INT_SIZE_WIDTH-1:0] buffread_offset;
wire [CFG_IN_ORDER_BUFFER_DATA_WIDTH-1:0] buffread_data;
wire int_ecc_sbe;
wire int_ecc_dbe;
wire errcmd_fifo_in_cmddropped;
reg errcmd_fifo_in_cmddropped_r;
wire errcmd_fifo_in_ready;
wire errcmd_fifo_in_valid;
wire [CFG_ERRCMD_FIFO_WIDTH-1:0] errcmd_fifo_in;
wire [CFG_ERRCMD_FIFO_WIDTH-1:0] errcmd_fifo_out;
// -----------------------------
// module definition
// -----------------------------
//
// READ DATA MAIN OUTPUT MUX
//
generate
begin : gen_rdata_output_mux
if (CFG_RDATA_RETURN_MODE == "PASSTHROUGH")
begin
always @ (*)
begin
read_data_valid = rout_data_valid;
read_data = rout_data;
read_data_error = rout_data_error;
read_data_localid = rout_data_localid;
rdatap_free_id_valid = ~cmd_counter_full;
rdatap_free_id_dataid = 0;
end
end
else
begin
always @ (*)
begin
read_data_valid = inordr_read_data_valid_r;
read_data = inordr_read_data;
read_data_error = inordr_read_data_error;
read_data_localid = inordr_id_localid_r;
rdatap_free_id_valid = ~cmd_counter_full & free_id_valid;
rdatap_free_id_dataid = free_id_dataid;
end
end
end
endgenerate
//
// RDATA_ROUTER
//
// mux to select correct burst gen output phase for read command
// assumes bg_do_read only asserted for 1 of the CFG_AFI_INTF_PHASE_NUM
genvar rdp_k;
generate
for (rdp_k = 0; rdp_k < CFG_AFI_INTF_PHASE_NUM; rdp_k = rdp_k + 1)
begin : gen_bg_afi_signal_decode
always @ (*)
begin
int_bg_do_read [rdp_k] = bg_do_read [rdp_k];
int_bg_do_rmw_correct [rdp_k] = bg_do_rmw_correct [rdp_k];
int_bg_do_rmw_partial [rdp_k] = bg_do_rmw_partial [rdp_k];
int_bg_to_chipsel [rdp_k] = bg_to_chipsel [(((rdp_k+1)*CFG_MEM_IF_CS_WIDTH )-1):(rdp_k*CFG_MEM_IF_CS_WIDTH )];
int_bg_to_bank [rdp_k] = bg_to_bank [(((rdp_k+1)*CFG_MEM_IF_BA_WIDTH )-1):(rdp_k*CFG_MEM_IF_BA_WIDTH )];
int_bg_to_row [rdp_k] = bg_to_row [(((rdp_k+1)*CFG_MEM_IF_ROW_WIDTH)-1):(rdp_k*CFG_MEM_IF_ROW_WIDTH)];
int_bg_to_column [rdp_k] = bg_to_column [(((rdp_k+1)*CFG_MEM_IF_COL_WIDTH)-1):(rdp_k*CFG_MEM_IF_COL_WIDTH)];
end
end
endgenerate
always @ (*)
begin
int_bg_dataid = bg_dataid;
int_bg_localid = bg_localid;
int_bg_size = bg_size;
end
always @ (*)
begin
mux_pfifo_input_rmw [0] = (int_bg_do_read [0]) ? int_bg_do_rmw_correct [0] : 0;
mux_pfifo_input_rmw_partial [0] = (int_bg_do_read [0]) ? int_bg_do_rmw_partial [0] : 0;
mux_pfifo_input_chipsel [0] = (int_bg_do_read [0]) ? int_bg_to_chipsel [0] : 0;
mux_pfifo_input_bank [0] = (int_bg_do_read [0]) ? int_bg_to_bank [0] : 0;
mux_pfifo_input_row [0] = (int_bg_do_read [0]) ? int_bg_to_row [0] : 0;
mux_pfifo_input_column [0] = (int_bg_do_read [0]) ? int_bg_to_column [0] : 0;
end
genvar rdp_j;
generate
for (rdp_j = 1; rdp_j < CFG_AFI_INTF_PHASE_NUM; rdp_j = rdp_j + 1)
begin : gen_bg_afi_phase_mux
always @ (*)
begin
mux_pfifo_input_rmw [rdp_j] = mux_pfifo_input_rmw [rdp_j - 1] | ((int_bg_do_read [rdp_j]) ? int_bg_do_rmw_correct [rdp_j] : 0);
mux_pfifo_input_rmw_partial [rdp_j] = mux_pfifo_input_rmw_partial [rdp_j - 1] | ((int_bg_do_read [rdp_j]) ? int_bg_do_rmw_partial [rdp_j] : 0);
mux_pfifo_input_chipsel [rdp_j] = mux_pfifo_input_chipsel [rdp_j - 1] | ((int_bg_do_read [rdp_j]) ? int_bg_to_chipsel [rdp_j] : 0);
mux_pfifo_input_bank [rdp_j] = mux_pfifo_input_bank [rdp_j - 1] | ((int_bg_do_read [rdp_j]) ? int_bg_to_bank [rdp_j] : 0);
mux_pfifo_input_row [rdp_j] = mux_pfifo_input_row [rdp_j - 1] | ((int_bg_do_read [rdp_j]) ? int_bg_to_row [rdp_j] : 0);
mux_pfifo_input_column [rdp_j] = mux_pfifo_input_column [rdp_j - 1] | ((int_bg_do_read [rdp_j]) ? int_bg_to_column [rdp_j] : 0);
end
end
endgenerate
always @ (*)
begin
pfifo_input_do_read = |int_bg_do_read;
pfifo_input_rmw = mux_pfifo_input_rmw [CFG_AFI_INTF_PHASE_NUM-1];
pfifo_input_rmw_partial = mux_pfifo_input_rmw_partial [CFG_AFI_INTF_PHASE_NUM-1];
pfifo_input_chipsel = mux_pfifo_input_chipsel [CFG_AFI_INTF_PHASE_NUM-1];
pfifo_input_bank = mux_pfifo_input_bank [CFG_AFI_INTF_PHASE_NUM-1];
pfifo_input_row = mux_pfifo_input_row [CFG_AFI_INTF_PHASE_NUM-1];
pfifo_input_column = mux_pfifo_input_column [CFG_AFI_INTF_PHASE_NUM-1];
pfifo_input_dataid = int_bg_dataid ;
pfifo_input_localid = int_bg_localid ;
pfifo_input_size = int_bg_size ;
end
// format for pfifo_input & pfifo_output must be same
assign pfifo_input = {pfifo_input_chipsel, pfifo_input_bank, pfifo_input_row, pfifo_input_column, pfifo_input_localid, pfifo_input_size, pfifo_input_rmw, pfifo_input_rmw_partial, pfifo_input_dataid};
assign {pfifo_chipsel, pfifo_bank, pfifo_row, pfifo_column, pfifo_localid, pfifo_size, pfifo_rmw, pfifo_rmw_partial, pfifo_dataid} = pfifo_output;
// read data for this command has been fully received from memory
assign rdata_burst_complete = (pfifo_output_valid & (pfifo_size == ecc_rdata_current_count)) ? 1 : 0;
alt_mem_ddrx_fifo
#(
.CTL_FIFO_DATA_WIDTH (CFG_PENDING_RD_FIFO_WIDTH),
.CTL_FIFO_ADDR_WIDTH (CFG_MAX_READ_CMD_NUM_WIDTH)
)
pending_rd_fifo
(
.ctl_clk (ctl_clk),
.ctl_reset_n (ctl_reset_n),
.get_ready (rdata_burst_complete),
.get_valid (pfifo_output_valid),
.get_data (pfifo_output),
.put_ready (pfifo_input_ready), // no back-pressure allowed
.put_valid (pfifo_input_do_read),
.put_data (pfifo_input)
);
assign cmd_counter_load = ~proc_busy & proc_load & proc_read;
assign cmdload_valid = cmd_counter_load & proc_load_dataid;
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
cmd_counter <= 0;
cmd_counter_full <= 1'b0;
end
else
begin
if (cmd_counter_load & rdata_burst_complete)
begin
cmd_counter <= cmd_counter;
cmd_counter_full <= cmd_counter_full;
end
else if (cmd_counter_load)
begin
cmd_counter <= cmd_counter + 1;
if (cmd_counter == {{(CFG_MAX_READ_CMD_NUM_WIDTH - 1){1'b1}}, 1'b0}) // when cmd counter is counting up to all_ones
begin
cmd_counter_full <= 1'b1;
end
else
begin
cmd_counter_full <= 1'b0;
end
end
else if (rdata_burst_complete)
begin
cmd_counter <= cmd_counter - 1;
cmd_counter_full <= 1'b0;
end
end
end
assign rout_data = ecc_rdata;
assign rout_data_dataid = pfifo_dataid;
assign rout_data_localid = pfifo_localid;
assign rout_data_burstcount = ecc_rdata_current_count;
assign rout_rmw_rmwpartial = (pfifo_rmw | pfifo_rmw_partial);
assign rout_ecc_dbe = ecc_dbe;
assign rout_ecc_code = ecc_code;
always @ (*)
begin
//rout_data_valid = 0;
//rout_cmd_valid = 0;
rout_data_rmwfifo_valid = 0;
rout_cmd_rmwfifo_valid = 0;
rout_sbecmd_valid = 0;
rout_data_error = 0;
rout_errnotify_valid = 0;
if (~cfg_enable_ecc & ~cfg_enable_no_dm)
begin
rout_data_valid = ecc_rdatav;
rout_cmd_valid = rout_data_valid & rdata_burst_complete;
end
else
begin
rout_data_rmwfifo_valid = ecc_rdatav & rout_rmw_rmwpartial;
rout_data_valid = ecc_rdatav & ~rout_rmw_rmwpartial;
rout_cmd_valid = rout_data_valid & rdata_burst_complete;
rout_cmd_rmwfifo_valid = rout_data_rmwfifo_valid & rdata_burst_complete;
rout_data_error = int_ecc_dbe;
rout_errnotify_valid = ecc_rdatav & ( int_ecc_sbe | int_ecc_dbe );
if (cfg_enable_auto_corr)
begin
rout_sbecmd_valid = rout_cmd_valid & (ecc_sbe_cmd_detected | int_ecc_sbe);
end
end
end
// rmwfifo interface
assign rmwfifo_data_valid = rout_data_rmwfifo_valid;
assign rmwfifo_data = rout_data;
assign rmwfifo_ecc_dbe = rout_ecc_dbe;
assign rmwfifo_ecc_code = rout_ecc_code;
// ecc_sbe_cmd_detected
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
ecc_sbe_cmd_detected <= 0;
ecc_dbe_cmd_detected <= 0;
end
else
begin
if (rdata_burst_complete)
begin
ecc_sbe_cmd_detected <= 0;
ecc_dbe_cmd_detected <= 0;
end
else if (int_ecc_sbe)
begin
ecc_sbe_cmd_detected <= 1;
end
else if (int_ecc_dbe)
begin
ecc_dbe_cmd_detected <= 1;
end
end
end
assign int_ecc_sbe = ecc_rdatav & (|ecc_sbe);
assign int_ecc_dbe = ecc_rdatav & (|ecc_dbe);
//
// ECC_RDATA counter
//
assign ecc_rdata_current_count = (CFG_ECC_RDATA_COUNTER_REG) ? ecc_rdata_counter : ecc_rdatavalid_count;
assign ecc_rdatavalid_count = (ecc_rdatav) ? ecc_rdata_counter + 1 : ecc_rdata_counter;
assign ecc_rdata_burst_complete_count = pfifo_size;
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
ecc_rdata_counter <= 0;
end
else
begin
if (rdata_burst_complete)
begin
ecc_rdata_counter <= ecc_rdatavalid_count - ecc_rdata_burst_complete_count;
end
else
begin
ecc_rdata_counter <= ecc_rdatavalid_count;
end
end
end
assign errcmd_fifo_in_valid = rout_sbecmd_valid;
assign errcmd_fifo_in = {pfifo_chipsel, pfifo_bank, pfifo_row, pfifo_column_burst_aligned, cfg_max_cmd_burstcount, pfifo_localid};
assign {errcmd_chipsel, errcmd_bank, errcmd_row, errcmd_column, errcmd_size, errcmd_localid} = errcmd_fifo_out;
assign errcmd_fifo_in_cmddropped = ~errcmd_fifo_in_ready & errcmd_fifo_in_valid;
assign cfg_max_cmd_burstcount = (cfg_burst_length / CFG_DWIDTH_RATIO);
// DDR3, pfifo_column_burst_aligned is burst length 8 aligned
// DDR2, pfifo_column is already burst aligned
assign pfifo_column_burst_aligned = (cfg_type == `MMR_TYPE_DDR3) ? {pfifo_column[(CFG_MEM_IF_COL_WIDTH-1):3],{3{1'b0}} } : pfifo_column;
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
pfifo_chipsel_r <= 0;
pfifo_bank_r <= 0;
pfifo_row_r <= 0;
pfifo_column_r <= 0;
pfifo_column_burst_aligned_r <= 0;
end
else
begin
pfifo_chipsel_r <= pfifo_chipsel ;
pfifo_bank_r <= pfifo_bank ;
pfifo_row_r <= pfifo_row ;
pfifo_column_r <= pfifo_column ;
pfifo_column_burst_aligned_r <= pfifo_column_burst_aligned;
end
end
alt_mem_ddrx_fifo
# (
.CTL_FIFO_DATA_WIDTH (CFG_ERRCMD_FIFO_WIDTH),
.CTL_FIFO_ADDR_WIDTH (CFG_ERRCMD_FIFO_ADDR_WIDTH)
)
errcmd_fifo_inst
(
.ctl_clk (ctl_clk),
.ctl_reset_n (ctl_reset_n),
.get_ready (errcmd_ready),
.get_valid (errcmd_valid),
.get_data (errcmd_fifo_out),
.put_ready (errcmd_fifo_in_ready),
.put_valid (errcmd_fifo_in_valid),
.put_data (errcmd_fifo_in)
);
//
// error address information for MMR's
//
// - rdatap_rcvd_addr, rdatap_rcvd_cmd & rdatap_rcvd_corr_dropped
// - rdatap_rcvd_addr generation takes 1 cycle after an error, so need to register
// rdatap_rcvd_cmd & rdatap_rcvd_corr_dropped to keep in sync, see SPR:362993
//
assign rdatap_rcvd_addr = pfifo_addr;
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
rdata_burst_complete_r <= 0;
errcmd_fifo_in_cmddropped_r <= 0;
rdatap_rcvd_cmd <= 0;
rdatap_rcvd_corr_dropped <= 0;
end
else
begin
rdata_burst_complete_r <= rdata_burst_complete;
errcmd_fifo_in_cmddropped_r <= errcmd_fifo_in_cmddropped;
rdatap_rcvd_cmd <= rdata_burst_complete;
rdatap_rcvd_corr_dropped <= errcmd_fifo_in_cmddropped;
end
end
// generate local address from chip, bank, row, column addresses
always @(*)
begin : addr_loop
pfifo_addr = 0;
// column
pfifo_addr[MIN_COL - CFG_IGNORE_NUM_BITS_COL - 1 : 0] = pfifo_column_burst_aligned_r[MIN_COL - 1 : CFG_IGNORE_NUM_BITS_COL];
for (n=MIN_COL; n<MAX_COL; n=n+1'b1) begin
if(n < cfg_col_addr_width) begin // bit of col_addr can be configured in CSR using cfg_col_addr_width
pfifo_addr[n - CFG_IGNORE_NUM_BITS_COL] = pfifo_column_burst_aligned_r[n];
end
end
// row
for (j=0; j<MIN_ROW; j=j+1'b1) begin //The purpose of using this for-loop is to get rid of "if(j < cfg_row_addr_width) begin" which causes multiplexers
pfifo_addr[j + cfg_addr_bitsel_row] = pfifo_row_r[j];
end
for (j=MIN_ROW; j<MAX_ROW; j=j+1'b1) begin
if(j < cfg_row_addr_width) begin // bit of row_addr can be configured in CSR using cfg_row_addr_width
pfifo_addr[j + cfg_addr_bitsel_row] = pfifo_row_r[j];
end
end
// bank
for (k=0; k<MIN_BANK; k=k+1'b1) begin //The purpose of using this for-loop is to get rid of "if(k < cfg_bank_addr_width) begin" which causes multiplexers
pfifo_addr[k + cfg_addr_bitsel_bank] = pfifo_bank_r[k];
end
for (k=MIN_BANK; k<MAX_BANK; k=k+1'b1) begin
if(k < cfg_bank_addr_width) begin // bit of bank_addr can be configured in CSR using cfg_bank_addr_width
pfifo_addr[k + cfg_addr_bitsel_bank] = pfifo_bank_r[k];
end
end
// cs
m = 0;
if (cfg_cs_addr_width > 1'b0) begin //if cfg_cs_addr_width =< 1'b1, address doesn't have cs_addr bit
for (m=0; m<MIN_CS; m=m+1'b1) begin //The purpose of using this for-loop is to get rid of "if(m < cfg_cs_addr_width) begin" which causes multiplexers
pfifo_addr[m + cfg_addr_bitsel_chipsel] = pfifo_chipsel_r[m];
end
for (m=MIN_CS; m<MAX_CS; m=m+1'b1) begin
if(m < cfg_cs_addr_width) begin // bit of cs_addr can be configured in CSR using cfg_cs_addr_width
pfifo_addr[m + cfg_addr_bitsel_chipsel] = pfifo_chipsel_r[m];
end
end
end
end
// pre-calculate pfifo_addr chipsel, bank, row, col bit select offsets
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
cfg_addr_bitsel_chipsel <= 0;
cfg_addr_bitsel_bank <= 0;
cfg_addr_bitsel_row <= 0;
end
else
begin
//row
if(cfg_addr_order == `MMR_ADDR_ORDER_ROW_CS_BA_COL)
cfg_addr_bitsel_row <= cfg_cs_addr_width + cfg_bank_addr_width + cfg_col_addr_width - CFG_IGNORE_NUM_BITS_COL;
else if(cfg_addr_order == `MMR_ADDR_ORDER_CS_BA_ROW_COL)
cfg_addr_bitsel_row <= cfg_col_addr_width - CFG_IGNORE_NUM_BITS_COL;
else // cfg_addr_order == `MMR_ADDR_ORDER_CS_ROW_BA_COL
cfg_addr_bitsel_row <= cfg_bank_addr_width + cfg_col_addr_width - CFG_IGNORE_NUM_BITS_COL;
// bank
if(cfg_addr_order == `MMR_ADDR_ORDER_CS_BA_ROW_COL)
cfg_addr_bitsel_bank <= cfg_row_addr_width + cfg_col_addr_width - CFG_IGNORE_NUM_BITS_COL;
else // cfg_addr_order == `MMR_ADDR_ORDER_ROW_CS_BA_COL || `MMR_ADDR_ORDER_CS_ROW_BA_COL
cfg_addr_bitsel_bank <= cfg_col_addr_width - CFG_IGNORE_NUM_BITS_COL;
//chipsel
if(cfg_addr_order == `MMR_ADDR_ORDER_ROW_CS_BA_COL)
cfg_addr_bitsel_chipsel <= cfg_bank_addr_width + cfg_col_addr_width - CFG_IGNORE_NUM_BITS_COL;
else // cfg_addr_order == `MMR_ADDR_ORDER_CS_BA_ROW_COL || `MMR_ADDR_ORDER_CS_ROW_BA_COL
cfg_addr_bitsel_chipsel <= cfg_bank_addr_width + cfg_row_addr_width + cfg_col_addr_width - CFG_IGNORE_NUM_BITS_COL;
end
end
//
// Everything below is for
// CFG_RDATA_RETURN_MODE == INORDER support
//
generate
begin : gen_rdata_return_inorder
if (CFG_RDATA_RETURN_MODE == "INORDER")
begin
//
// DATAID MANAGEMENT
//
genvar i;
for (i = 0; i < CFG_DATAID_ARRAY_DEPTH; i = i + 1)
begin : gen_dataid_array
assign dataid_array_valid[i] = |(dataid_array_burstcount[i]);
// dataid_array
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
dataid_array_data_ready[i] <= 1'b0;
dataid_array_burstcount[i] <= 0;
dataid_array_localid [i] <= 0;
end
else
begin
// update command
if (cmdload_valid & free_id_dataid_vector[i])
begin
dataid_array_burstcount[i] <= proc_size;
end
// writing data to buffer
if (rout_data_valid & (rout_data_dataid == i))
begin
dataid_array_data_ready[i] <= 1'b1;
dataid_array_localid[i] <= rout_data_localid;
end
// completed reading data from buffer
if (inordr_id_data_complete & inordr_id_dataid_vector[i])
begin
dataid_array_data_ready[i] <= 1'b0;
dataid_array_burstcount[i] <= 0;
end
end
end
// dataid_array output decode mux
always @ (*)
begin
if (inordr_id_valid & inordr_id_dataid_vector[i])
begin
mux_inordr_data_ready[i] = dataid_array_data_ready[i];
end
else
begin
mux_inordr_data_ready[i] = 1'b0;
end
end
end
assign inordr_read_data_valid = |mux_inordr_data_ready;
//
// FREE & ALLOCATED DATAID LIST
//
assign free_id_get_ready = cmdload_valid;
assign allocated_put_valid = free_id_get_ready & free_id_valid;
// list & fifo ready & valid assertion/de-assertion behavior may differ based on implementation, SPR:358527
assign free_id_valid = int_free_id_valid & inordr_info_input_ready;
assign inordr_id_valid = inordr_id_list_valid & inordr_info_output_valid;
alt_mem_ddrx_list
#(
.CTL_LIST_WIDTH (CFG_DATA_ID_WIDTH),
.CTL_LIST_DEPTH (CFG_DATAID_ARRAY_DEPTH),
.CTL_LIST_INIT_VALUE_TYPE ("INCR"),
.CTL_LIST_INIT_VALID ("VALID")
)
list_freeid_inst
(
.ctl_clk (ctl_clk),
.ctl_reset_n (ctl_reset_n),
.list_get_entry_ready (free_id_get_ready),
.list_get_entry_valid (int_free_id_valid),
.list_get_entry_id (free_id_dataid),
.list_get_entry_id_vector (free_id_dataid_vector),
// ready can be ignored, list entry availability is guaranteed
.list_put_entry_ready (),
.list_put_entry_valid (inordr_id_data_complete),
.list_put_entry_id (inordr_id_dataid)
);
alt_mem_ddrx_list
#(
.CTL_LIST_WIDTH (CFG_DATA_ID_WIDTH),
.CTL_LIST_DEPTH (CFG_DATAID_ARRAY_DEPTH),
.CTL_LIST_INIT_VALUE_TYPE ("ZERO"),
.CTL_LIST_INIT_VALID ("INVALID")
)
list_allocated_id_inst
(
.ctl_clk (ctl_clk),
.ctl_reset_n (ctl_reset_n),
.list_get_entry_ready (inordr_id_data_complete),
.list_get_entry_valid (inordr_id_list_valid),
.list_get_entry_id (inordr_id_dataid),
.list_get_entry_id_vector (inordr_id_dataid_vector),
// allocated_put_ready can be ignored, list entry availability is guaranteed
.list_put_entry_ready (allocated_put_ready),
.list_put_entry_valid (allocated_put_valid),
.list_put_entry_id (free_id_dataid)
);
// format for inordr_info_input & inordr_info_output must be same
assign inordr_info_input = {proc_localid,proc_size};
assign {inordr_id_localid,inordr_id_expected_burstcount} = inordr_info_output;
alt_mem_ddrx_fifo
# (
.CTL_FIFO_DATA_WIDTH (CFG_INORDER_INFO_FIFO_WIDTH),
.CTL_FIFO_ADDR_WIDTH (CFG_DATA_ID_WIDTH)
)
inordr_info_fifo_inst
(
.ctl_clk (ctl_clk),
.ctl_reset_n (ctl_reset_n),
.get_ready (inordr_id_data_complete),
.get_valid (inordr_info_output_valid),
.get_data (inordr_info_output),
.put_ready (inordr_info_input_ready),
.put_valid (allocated_put_valid),
.put_data (inordr_info_input)
);
//
// IN-ORDER READ MANAGER
//
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
inordr_data_counter <= 0;
inordr_data_counter_plus_1 <= 0;
inordr_read_data_valid_r <= 0;
inordr_id_data_complete_r <= 0;
inordr_id_localid_r <= 0;
end
else
begin
if (inordr_id_data_complete)
begin
inordr_data_counter <= 0;
inordr_data_counter_plus_1 <= 1;
end
else
begin
inordr_data_counter <= inordr_next_data_counter;
inordr_data_counter_plus_1 <= inordr_next_data_counter + 1;
end
inordr_id_localid_r <= inordr_id_localid;
// original signal used to read from buffer
// _r version used to pop the fifos
inordr_read_data_valid_r <= inordr_read_data_valid;
inordr_id_data_complete_r <= inordr_id_data_complete;
end
end
assign inordr_next_data_counter = (inordr_read_data_valid) ? (inordr_data_counter_plus_1) : inordr_data_counter;
assign inordr_id_data_complete = inordr_read_data_valid & (inordr_data_counter_plus_1 == inordr_id_expected_burstcount);
//
// BUFFER
//
assign buffwrite_offset = ecc_rdata_counter;
assign buffwrite_address = {rout_data_dataid,buffwrite_offset};
assign buffwrite_data = {rout_data_error,rout_data};
assign buffread_offset = inordr_data_counter;
assign buffread_address = {inordr_id_dataid,buffread_offset};
assign {inordr_read_data_error,inordr_read_data} = buffread_data;
alt_mem_ddrx_buffer
# (
.ADDR_WIDTH (CFG_BUFFER_ADDR_WIDTH),
.DATA_WIDTH (CFG_IN_ORDER_BUFFER_DATA_WIDTH)
)
in_order_buffer_inst
(
// port list
.ctl_clk (ctl_clk),
.ctl_reset_n (ctl_reset_n),
// write interface
.write_valid (rout_data_valid),
.write_address (buffwrite_address),
.write_data (buffwrite_data),
// read interface
.read_valid (inordr_read_data_valid),
.read_address (buffread_address),
.read_data (buffread_data)
);
end
end
endgenerate
function integer log2;
input [31:0] value;
integer i;
begin
log2 = 0;
for(i = 0; 2**i < value; i = i + 1)
log2 = i + 1;
end
endfunction
endmodule
//
// assert
//
// - rdatap_free_id_valid XOR rdatap_allocated_put_ready must always be 1
// - CFG_BUFFER_ADDR_WIDTH must be >= CFG_INT_SIZE_WIDTH. must have enough location to store 1 dram command worth of data
// - put_ready goes low
// - ecc_rdatav is high, but pfifo_output_valid is low
// - buffer size must be dataid x max size per command
// - is rdata_burst_complete allowed to be high every cycle?
// - CFG_BUFFER_ADDR_WIDTH > CFG_DATA_ID_WIDTH
// - if cfg_enable_ecc is low, sbe, dbe, rdata error must all be low
// - if cfg_enable_auto_corr is low, rmw & rmw_partial must be low, errcmd_valid must never be high
// - cmd_counter_full & cmdload_valid
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
//altera message_off 10036
///////////////////////////////////////////////////////////////////////////////
// Title : DDR controller AFi interfacing block
//
// File : afi_block.v
//
// Abstract : AFi block
///////////////////////////////////////////////////////////////////////////////
//Things to check
//1. Does afi_wlat need to be registered?
//2. Does ecc_wdata_fifo_read generation changes with ECC
//3. Why in ddrx controller int_dqs_burst and int_wdata_valid signals are registered when CFG_OUTPUT_REGD is 1. Why complex logic instead of simple registering??
//4. We need rdwr_data_valid signal from arbiter to determine how many datas are valid within one dram burst
//5. Do we need to end rdwr_data_valid with doing_write to generate ecc_wdata_fifo_read? Yes
//6. Look at all comments and SPRs for old ddrx afi block
//7. Currently additive_latency, ECC, HR features are not supported
`timescale 1 ps / 1 ps
module alt_mem_ddrx_rdwr_data_tmg
# (parameter
CFG_DWIDTH_RATIO = 2,
CFG_MEM_IF_DQ_WIDTH = 8,
CFG_MEM_IF_DQS_WIDTH = 1,
CFG_MEM_IF_DM_WIDTH = 1,
CFG_WLAT_BUS_WIDTH = 6,
CFG_DRAM_WLAT_GROUP = 1,
CFG_DATA_ID_WIDTH = 10,
CFG_WDATA_REG = 0,
CFG_ECC_ENC_REG = 0,
CFG_AFI_INTF_PHASE_NUM = 2,
CFG_PORT_WIDTH_ENABLE_ECC = 1,
CFG_PORT_WIDTH_OUTPUT_REGD = 1
)
(
ctl_clk,
ctl_reset_n,
// configuration
cfg_enable_ecc,
cfg_output_regd,
cfg_output_regd_for_afi_output,
//Arbiter command input
bg_doing_read,
bg_doing_write,
bg_rdwr_data_valid, //Required for user burst length lesser than dram burst length
dataid,
bg_do_rmw_correct,
bg_do_rmw_partial,
//Inputs from ECC/WFIFO blocks
ecc_wdata,
ecc_dm,
//Input from AFI Block
afi_wlat,
//Output from AFI Block
afi_doing_read, //Use to generate rdata_valid signals in PHY
afi_doing_read_full, //AFI 2.0 signal, used by UniPHY for dqs enable control
ecc_wdata_fifo_read,
ecc_wdata_fifo_dataid,
ecc_wdata_fifo_dataid_vector,
ecc_wdata_fifo_rmw_correct,
ecc_wdata_fifo_rmw_partial,
ecc_wdata_fifo_read_first,
ecc_wdata_fifo_dataid_first,
ecc_wdata_fifo_dataid_vector_first,
ecc_wdata_fifo_rmw_correct_first,
ecc_wdata_fifo_rmw_partial_first,
ecc_wdata_fifo_first_vector,
ecc_wdata_fifo_read_last,
ecc_wdata_fifo_dataid_last,
ecc_wdata_fifo_dataid_vector_last,
ecc_wdata_fifo_rmw_correct_last,
ecc_wdata_fifo_rmw_partial_last,
afi_dqs_burst,
afi_wdata_valid,
afi_wdata,
afi_dm
);
localparam integer CFG_WLAT_PIPE_LENGTH = 2**(CFG_WLAT_BUS_WIDTH/CFG_DRAM_WLAT_GROUP);
localparam integer CFG_DATAID_ARRAY_DEPTH = 2**CFG_DATA_ID_WIDTH;
integer i;
//=================================================================================================//
// input/output declaration //
//=================================================================================================//
input ctl_clk;
input ctl_reset_n;
// configuration
input [CFG_PORT_WIDTH_ENABLE_ECC-1:0] cfg_enable_ecc;
input [CFG_PORT_WIDTH_OUTPUT_REGD-1:0] cfg_output_regd;
output [CFG_PORT_WIDTH_OUTPUT_REGD-1:0] cfg_output_regd_for_afi_output;
//Arbiter command input
input bg_doing_read;
input bg_doing_write;
input bg_rdwr_data_valid;
input [CFG_DATA_ID_WIDTH-1:0] dataid;
input [CFG_AFI_INTF_PHASE_NUM-1:0] bg_do_rmw_correct;
input [CFG_AFI_INTF_PHASE_NUM-1:0] bg_do_rmw_partial;
//Inputs from ECC/WFIFO blocks
input [CFG_MEM_IF_DQ_WIDTH*CFG_DWIDTH_RATIO-1:0] ecc_wdata;
input [(CFG_MEM_IF_DQ_WIDTH*CFG_DWIDTH_RATIO)/(CFG_MEM_IF_DQ_WIDTH/CFG_MEM_IF_DQS_WIDTH)-1:0] ecc_dm;
//Input from AFI Block
input [CFG_WLAT_BUS_WIDTH-1:0] afi_wlat;
//output to AFI block
output [CFG_MEM_IF_DQS_WIDTH*(CFG_DWIDTH_RATIO/2)-1:0] afi_doing_read;
output [CFG_MEM_IF_DQS_WIDTH*(CFG_DWIDTH_RATIO/2)-1:0] afi_doing_read_full;
output [CFG_DRAM_WLAT_GROUP-1:0] ecc_wdata_fifo_read;
output [CFG_DRAM_WLAT_GROUP*CFG_DATA_ID_WIDTH-1:0] ecc_wdata_fifo_dataid;
output [CFG_DRAM_WLAT_GROUP*CFG_DATAID_ARRAY_DEPTH-1:0] ecc_wdata_fifo_dataid_vector;
output [CFG_DRAM_WLAT_GROUP-1:0] ecc_wdata_fifo_rmw_correct;
output [CFG_DRAM_WLAT_GROUP-1:0] ecc_wdata_fifo_rmw_partial;
output ecc_wdata_fifo_read_first;
output [CFG_DATA_ID_WIDTH-1:0] ecc_wdata_fifo_dataid_first;
output [CFG_DATAID_ARRAY_DEPTH-1:0] ecc_wdata_fifo_dataid_vector_first;
output ecc_wdata_fifo_rmw_correct_first;
output ecc_wdata_fifo_rmw_partial_first;
output [CFG_DRAM_WLAT_GROUP-1:0] ecc_wdata_fifo_first_vector;
output ecc_wdata_fifo_read_last;
output [CFG_DATA_ID_WIDTH-1:0] ecc_wdata_fifo_dataid_last;
output [CFG_DATAID_ARRAY_DEPTH-1:0] ecc_wdata_fifo_dataid_vector_last;
output ecc_wdata_fifo_rmw_correct_last;
output ecc_wdata_fifo_rmw_partial_last;
output [CFG_MEM_IF_DQS_WIDTH*(CFG_DWIDTH_RATIO/2)-1:0] afi_dqs_burst;
output [CFG_MEM_IF_DQS_WIDTH*(CFG_DWIDTH_RATIO/2)-1:0] afi_wdata_valid;
output [CFG_MEM_IF_DQ_WIDTH*CFG_DWIDTH_RATIO-1:0] afi_wdata;
output [CFG_MEM_IF_DM_WIDTH*CFG_DWIDTH_RATIO-1:0] afi_dm;
//=================================================================================================//
// reg/wire declaration //
//=================================================================================================//
wire bg_doing_read;
wire bg_doing_write;
wire bg_rdwr_data_valid;
wire [CFG_DATA_ID_WIDTH-1:0] dataid;
wire [CFG_AFI_INTF_PHASE_NUM-1:0] bg_do_rmw_correct;
wire [CFG_AFI_INTF_PHASE_NUM-1:0] bg_do_rmw_partial;
wire [CFG_MEM_IF_DQS_WIDTH*(CFG_DWIDTH_RATIO/2)-1:0] afi_doing_read;
wire [CFG_MEM_IF_DQS_WIDTH*(CFG_DWIDTH_RATIO/2)-1:0] afi_doing_read_full;
wire [CFG_DRAM_WLAT_GROUP-1:0] ecc_wdata_fifo_read;
reg [CFG_DRAM_WLAT_GROUP-1:0] ecc_wdata_fifo_read_r;
wire [CFG_DRAM_WLAT_GROUP*CFG_DATA_ID_WIDTH-1:0] ecc_wdata_fifo_dataid;
wire [CFG_DRAM_WLAT_GROUP*CFG_DATAID_ARRAY_DEPTH-1:0] ecc_wdata_fifo_dataid_vector;
wire [CFG_DRAM_WLAT_GROUP-1:0] ecc_wdata_fifo_rmw_correct;
wire [CFG_DRAM_WLAT_GROUP-1:0] ecc_wdata_fifo_rmw_partial;
wire ecc_wdata_fifo_read_first;
wire [CFG_DATA_ID_WIDTH-1:0] ecc_wdata_fifo_dataid_first;
wire [CFG_DATAID_ARRAY_DEPTH-1:0] ecc_wdata_fifo_dataid_vector_first;
wire ecc_wdata_fifo_rmw_correct_first;
wire ecc_wdata_fifo_rmw_partial_first;
reg [CFG_DRAM_WLAT_GROUP-1:0] ecc_wdata_fifo_first_vector;
wire ecc_wdata_fifo_read_last;
wire [CFG_DATA_ID_WIDTH-1:0] ecc_wdata_fifo_dataid_last;
wire [CFG_DATAID_ARRAY_DEPTH-1:0] ecc_wdata_fifo_dataid_vector_last;
wire ecc_wdata_fifo_rmw_correct_last;
wire ecc_wdata_fifo_rmw_partial_last;
wire [CFG_MEM_IF_DQS_WIDTH*(CFG_DWIDTH_RATIO/2)-1:0] afi_dqs_burst;
wire [CFG_MEM_IF_DQS_WIDTH*(CFG_DWIDTH_RATIO/2)-1:0] afi_wdata_valid;
wire [CFG_MEM_IF_DQ_WIDTH*CFG_DWIDTH_RATIO-1:0] afi_wdata;
wire [CFG_MEM_IF_DM_WIDTH*CFG_DWIDTH_RATIO-1:0] afi_dm;
//Internal signals
reg [CFG_PORT_WIDTH_OUTPUT_REGD-1:0] cfg_output_regd_for_afi_output_combi [CFG_DRAM_WLAT_GROUP-1:0];
reg [CFG_PORT_WIDTH_OUTPUT_REGD-1:0] cfg_output_regd_for_wdata_path_combi [CFG_DRAM_WLAT_GROUP-1:0];
reg [CFG_PORT_WIDTH_OUTPUT_REGD-1:0] cfg_output_regd_for_afi_output_mux [CFG_DRAM_WLAT_GROUP-1:0];
reg [CFG_PORT_WIDTH_OUTPUT_REGD-1:0] cfg_output_regd_for_wdata_path_mux [CFG_DRAM_WLAT_GROUP-1:0];
reg [CFG_PORT_WIDTH_OUTPUT_REGD-1:0] cfg_output_regd_for_afi_output;
reg [CFG_PORT_WIDTH_OUTPUT_REGD-1:0] cfg_output_regd_for_wdata_path;
reg doing_read_combi;
reg doing_read_full_combi;
reg doing_read_r;
reg doing_read_full_r;
reg [CFG_WLAT_PIPE_LENGTH-1:0] doing_write_pipe;
reg [CFG_WLAT_PIPE_LENGTH-1:0] rdwr_data_valid_pipe;
reg [CFG_WLAT_PIPE_LENGTH-1:0] rmw_correct_pipe;
reg [CFG_WLAT_PIPE_LENGTH-1:0] rmw_partial_pipe;
reg [CFG_DATA_ID_WIDTH-1:0] dataid_pipe [CFG_WLAT_PIPE_LENGTH-1:0];
reg [CFG_DATAID_ARRAY_DEPTH-1:0] dataid_vector_pipe [CFG_WLAT_PIPE_LENGTH-1:0];
reg [CFG_DATAID_ARRAY_DEPTH-1:0] dataid_vector;
reg int_dqs_burst;
reg int_dqs_burst_r;
reg int_wdata_valid;
reg int_wdata_valid_r;
reg int_real_wdata_valid;
reg [CFG_DRAM_WLAT_GROUP-1:0] int_ecc_wdata_fifo_read;
reg [CFG_DRAM_WLAT_GROUP-1:0] int_ecc_wdata_fifo_read_r;
reg [CFG_DATA_ID_WIDTH-1:0] int_ecc_wdata_fifo_dataid [CFG_DRAM_WLAT_GROUP-1:0];
reg [CFG_DATA_ID_WIDTH-1:0] int_ecc_wdata_fifo_dataid_r [CFG_DRAM_WLAT_GROUP-1:0];
reg [CFG_DATAID_ARRAY_DEPTH-1:0] int_ecc_wdata_fifo_dataid_vector [CFG_DRAM_WLAT_GROUP-1:0];
reg [CFG_DATAID_ARRAY_DEPTH-1:0] int_ecc_wdata_fifo_dataid_vector_r [CFG_DRAM_WLAT_GROUP-1:0];
reg [CFG_DRAM_WLAT_GROUP-1:0] int_ecc_wdata_fifo_rmw_correct;
reg [CFG_DRAM_WLAT_GROUP-1:0] int_ecc_wdata_fifo_rmw_correct_r;
reg [CFG_DRAM_WLAT_GROUP-1:0] int_ecc_wdata_fifo_rmw_partial;
reg [CFG_DRAM_WLAT_GROUP-1:0] int_ecc_wdata_fifo_rmw_partial_r;
wire int_do_rmw_correct;
wire int_do_rmw_partial;
// DQS burst logic for half rate design
reg int_dqs_burst_half_rate;
reg int_dqs_burst_half_rate_r;
reg [CFG_DRAM_WLAT_GROUP-1:0] first_afi_wlat;
reg [CFG_DRAM_WLAT_GROUP-1:0] last_afi_wlat;
reg [CFG_WLAT_BUS_WIDTH/CFG_DRAM_WLAT_GROUP-1:0] smallest_afi_wlat [CFG_DRAM_WLAT_GROUP-1:0];
reg [CFG_WLAT_BUS_WIDTH/CFG_DRAM_WLAT_GROUP-1:0] largest_afi_wlat [CFG_DRAM_WLAT_GROUP-1:0];
reg smallest_afi_wlat_eq_0;
reg [CFG_WLAT_BUS_WIDTH/CFG_DRAM_WLAT_GROUP-1:0] smallest_afi_wlat_minus_1;
reg [CFG_WLAT_BUS_WIDTH/CFG_DRAM_WLAT_GROUP-1:0] smallest_afi_wlat_minus_2;
reg [CFG_WLAT_BUS_WIDTH/CFG_DRAM_WLAT_GROUP-1:0] smallest_afi_wlat_minus_3;
reg smallest_doing_write_pipe_eq_afi_wlat_minus_0;
reg smallest_doing_write_pipe_eq_afi_wlat_minus_1;
reg smallest_doing_write_pipe_eq_afi_wlat_minus_2;
reg smallest_rdwr_data_valid_pipe_eq_afi_wlat_minus_1;
reg smallest_rdwr_data_valid_pipe_eq_afi_wlat_minus_2;
reg [CFG_DATA_ID_WIDTH-1:0] smallest_dataid_pipe_eq_afi_wlat_minus_1;
reg [CFG_DATA_ID_WIDTH-1:0] smallest_dataid_pipe_eq_afi_wlat_minus_2;
reg [CFG_DATAID_ARRAY_DEPTH-1:0] smallest_dataid_vector_pipe_eq_afi_wlat_minus_1;
reg [CFG_DATAID_ARRAY_DEPTH-1:0] smallest_dataid_vector_pipe_eq_afi_wlat_minus_2;
reg smallest_rmw_correct_pipe_eq_afi_wlat_minus_1;
reg smallest_rmw_correct_pipe_eq_afi_wlat_minus_2;
reg smallest_rmw_partial_pipe_eq_afi_wlat_minus_1;
reg smallest_rmw_partial_pipe_eq_afi_wlat_minus_2;
reg smallest_doing_write_pipe_eq_afi_wlat_minus_x;
reg smallest_rdwr_data_valid_pipe_eq_afi_wlat_minus_x;
reg [CFG_DATA_ID_WIDTH-1:0] smallest_dataid_pipe_eq_afi_wlat_minus_x;
reg [CFG_DATAID_ARRAY_DEPTH-1:0] smallest_dataid_vector_pipe_eq_afi_wlat_minus_x;
reg smallest_rmw_correct_pipe_eq_afi_wlat_minus_x;
reg smallest_rmw_partial_pipe_eq_afi_wlat_minus_x;
reg largest_afi_wlat_eq_0;
reg [CFG_WLAT_BUS_WIDTH/CFG_DRAM_WLAT_GROUP-1:0] largest_afi_wlat_minus_1;
reg [CFG_WLAT_BUS_WIDTH/CFG_DRAM_WLAT_GROUP-1:0] largest_afi_wlat_minus_2;
reg [CFG_WLAT_BUS_WIDTH/CFG_DRAM_WLAT_GROUP-1:0] largest_afi_wlat_minus_3;
reg largest_doing_write_pipe_eq_afi_wlat_minus_0;
reg largest_doing_write_pipe_eq_afi_wlat_minus_1;
reg largest_doing_write_pipe_eq_afi_wlat_minus_2;
reg largest_rdwr_data_valid_pipe_eq_afi_wlat_minus_1;
reg largest_rdwr_data_valid_pipe_eq_afi_wlat_minus_2;
reg [CFG_DATA_ID_WIDTH-1:0] largest_dataid_pipe_eq_afi_wlat_minus_1;
reg [CFG_DATA_ID_WIDTH-1:0] largest_dataid_pipe_eq_afi_wlat_minus_2;
reg [CFG_DATAID_ARRAY_DEPTH-1:0] largest_dataid_vector_pipe_eq_afi_wlat_minus_1;
reg [CFG_DATAID_ARRAY_DEPTH-1:0] largest_dataid_vector_pipe_eq_afi_wlat_minus_2;
reg largest_rmw_correct_pipe_eq_afi_wlat_minus_1;
reg largest_rmw_correct_pipe_eq_afi_wlat_minus_2;
reg largest_rmw_partial_pipe_eq_afi_wlat_minus_1;
reg largest_rmw_partial_pipe_eq_afi_wlat_minus_2;
reg largest_doing_write_pipe_eq_afi_wlat_minus_x;
reg largest_rdwr_data_valid_pipe_eq_afi_wlat_minus_x;
reg [CFG_DATA_ID_WIDTH-1:0] largest_dataid_pipe_eq_afi_wlat_minus_x;
reg [CFG_DATAID_ARRAY_DEPTH-1:0] largest_dataid_vector_pipe_eq_afi_wlat_minus_x;
reg largest_rmw_correct_pipe_eq_afi_wlat_minus_x;
reg largest_rmw_partial_pipe_eq_afi_wlat_minus_x;
reg afi_wlat_eq_0 [CFG_DRAM_WLAT_GROUP-1:0];
reg [CFG_WLAT_BUS_WIDTH/CFG_DRAM_WLAT_GROUP-1:0] afi_wlat_minus_1 [CFG_DRAM_WLAT_GROUP-1:0];
reg [CFG_WLAT_BUS_WIDTH/CFG_DRAM_WLAT_GROUP-1:0] afi_wlat_minus_2 [CFG_DRAM_WLAT_GROUP-1:0];
reg [CFG_WLAT_BUS_WIDTH/CFG_DRAM_WLAT_GROUP-1:0] afi_wlat_minus_3 [CFG_DRAM_WLAT_GROUP-1:0];
reg doing_write_pipe_eq_afi_wlat_minus_0 [CFG_DRAM_WLAT_GROUP-1:0];
reg doing_write_pipe_eq_afi_wlat_minus_1 [CFG_DRAM_WLAT_GROUP-1:0];
reg doing_write_pipe_eq_afi_wlat_minus_2 [CFG_DRAM_WLAT_GROUP-1:0];
reg rdwr_data_valid_pipe_eq_afi_wlat_minus_1 [CFG_DRAM_WLAT_GROUP-1:0];
reg rdwr_data_valid_pipe_eq_afi_wlat_minus_2 [CFG_DRAM_WLAT_GROUP-1:0];
reg [CFG_DATA_ID_WIDTH-1:0] dataid_pipe_eq_afi_wlat_minus_1 [CFG_DRAM_WLAT_GROUP-1:0];
reg [CFG_DATA_ID_WIDTH-1:0] dataid_pipe_eq_afi_wlat_minus_2 [CFG_DRAM_WLAT_GROUP-1:0];
reg [CFG_DATAID_ARRAY_DEPTH-1:0] dataid_vector_pipe_eq_afi_wlat_minus_1 [CFG_DRAM_WLAT_GROUP-1:0];
reg [CFG_DATAID_ARRAY_DEPTH-1:0] dataid_vector_pipe_eq_afi_wlat_minus_2 [CFG_DRAM_WLAT_GROUP-1:0];
reg rmw_correct_pipe_eq_afi_wlat_minus_1 [CFG_DRAM_WLAT_GROUP-1:0];
reg rmw_correct_pipe_eq_afi_wlat_minus_2 [CFG_DRAM_WLAT_GROUP-1:0];
reg rmw_partial_pipe_eq_afi_wlat_minus_1 [CFG_DRAM_WLAT_GROUP-1:0];
reg rmw_partial_pipe_eq_afi_wlat_minus_2 [CFG_DRAM_WLAT_GROUP-1:0];
reg doing_write_pipe_eq_afi_wlat_minus_x [CFG_DRAM_WLAT_GROUP-1:0];
reg rdwr_data_valid_pipe_eq_afi_wlat_minus_x [CFG_DRAM_WLAT_GROUP-1:0];
reg [CFG_DATA_ID_WIDTH-1:0] dataid_pipe_eq_afi_wlat_minus_x [CFG_DRAM_WLAT_GROUP-1:0];
reg [CFG_DATAID_ARRAY_DEPTH-1:0] dataid_vector_pipe_eq_afi_wlat_minus_x [CFG_DRAM_WLAT_GROUP-1:0];
reg rmw_correct_pipe_eq_afi_wlat_minus_x [CFG_DRAM_WLAT_GROUP-1:0];
reg rmw_partial_pipe_eq_afi_wlat_minus_x [CFG_DRAM_WLAT_GROUP-1:0];
//=================================================================================================//
// Internal cfg_output_regd //
//=================================================================================================//
generate
genvar N;
for (N = 0;N < CFG_DRAM_WLAT_GROUP;N = N + 1)
begin : output_regd_logic_per_dqs_group
always @ (*)
begin
if (CFG_WDATA_REG || CFG_ECC_ENC_REG)
begin
if (afi_wlat [(N + 1) * (CFG_WLAT_BUS_WIDTH / CFG_DRAM_WLAT_GROUP) - 1 : N * (CFG_WLAT_BUS_WIDTH / CFG_DRAM_WLAT_GROUP)] <= 1)
begin
// We enable output_regd for signals going to PHY
// because we need to fetch data 2 clock cycles earlier
cfg_output_regd_for_afi_output_combi [N] = 1'b1;
// We disable output_regd for signals going to wdata_path
// because we need to fecth data 2 clock cycles earlier
cfg_output_regd_for_wdata_path_combi [N] = 1'b0;
end
else
begin
cfg_output_regd_for_afi_output_combi [N] = cfg_output_regd;
cfg_output_regd_for_wdata_path_combi [N] = cfg_output_regd;
end
end
else
begin
cfg_output_regd_for_afi_output_combi [N] = cfg_output_regd;
cfg_output_regd_for_wdata_path_combi [N] = cfg_output_regd;
end
end
end
for (N = 1;N < CFG_DRAM_WLAT_GROUP;N = N + 1)
begin : output_regd_mux_logic
always @ (*)
begin
cfg_output_regd_for_afi_output_mux [N] = cfg_output_regd_for_afi_output_combi [N] | cfg_output_regd_for_afi_output_mux [N-1];
cfg_output_regd_for_wdata_path_mux [N] = cfg_output_regd_for_wdata_path_combi [N] | cfg_output_regd_for_wdata_path_mux [N-1];
end
end
endgenerate
always @ (*)
begin
cfg_output_regd_for_afi_output_mux [0] = cfg_output_regd_for_afi_output_combi [0];
cfg_output_regd_for_wdata_path_mux [0] = cfg_output_regd_for_wdata_path_combi [0];
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
cfg_output_regd_for_afi_output <= 1'b0;
cfg_output_regd_for_wdata_path <= 1'b0;
end
else
begin
cfg_output_regd_for_afi_output <= cfg_output_regd_for_afi_output_mux [CFG_DRAM_WLAT_GROUP-1];
cfg_output_regd_for_wdata_path <= cfg_output_regd_for_wdata_path_mux [CFG_DRAM_WLAT_GROUP-1];
end
end
//=================================================================================================//
// Read timing logic //
//=================================================================================================//
//*************************************************************************************************//
// afi_doing_read generation logic //
//*************************************************************************************************//
always @(*)
begin
if (bg_doing_read && bg_rdwr_data_valid)
begin
doing_read_combi = 1'b1;
end
else
begin
doing_read_combi = 1'b0;
end
doing_read_full_combi = bg_doing_read;
end
// registered output
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
doing_read_r <= 1'b0;
doing_read_full_r <= 1'b0;
end
else
begin
doing_read_r <= doing_read_combi;
doing_read_full_r <= doing_read_full_combi;
end
end
generate
genvar I;
for (I = 0; I < CFG_MEM_IF_DQS_WIDTH*(CFG_DWIDTH_RATIO/2); I = I + 1)
begin : B
assign afi_doing_read [I] = (cfg_output_regd_for_afi_output) ? doing_read_r : doing_read_combi;
assign afi_doing_read_full [I] = (cfg_output_regd_for_afi_output) ? doing_read_full_r : doing_read_full_combi;
end
endgenerate
//=================================================================================================//
// Write timing logic //
//=================================================================================================//
// Content of pipe shows how long dqs should toggle, used to generate dqs_burst
// content of pipe is also used to generate wdata_valid signal
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
doing_write_pipe <= 0;
end
else
begin
doing_write_pipe <= {doing_write_pipe[CFG_WLAT_PIPE_LENGTH -2 :0],bg_doing_write};
end
end
// content of pipe shows how much data should be read out of the write data FIFO
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
rdwr_data_valid_pipe <= 0;
end
else
begin
rdwr_data_valid_pipe <= {rdwr_data_valid_pipe[CFG_WLAT_PIPE_LENGTH - 2:0],bg_rdwr_data_valid};
end
end
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_WLAT_PIPE_LENGTH; i=i+1)
begin
dataid_pipe [i] <= 0;
end
end
else
begin
dataid_pipe [0] <= dataid;
for (i=1; i<CFG_WLAT_PIPE_LENGTH; i=i+1)
begin
dataid_pipe [i] <= dataid_pipe[i-1];
end
end
end
//pre-calculated dataid comparison logic
always @ (*)
begin
for (i=0; i<(CFG_DATAID_ARRAY_DEPTH); i=i+1)
begin
if (dataid == i)
begin
dataid_vector [i] = 1'b1;
end
else
begin
dataid_vector [i] = 1'b0;
end
end
end
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
dataid_vector_pipe [0] <= 0;
for (i=1; i<CFG_WLAT_PIPE_LENGTH; i=i+1)
begin
dataid_vector_pipe [i] <= 0;
end
end
else
begin
dataid_vector_pipe [0] <= dataid_vector;
for (i=1; i<CFG_WLAT_PIPE_LENGTH; i=i+1)
begin
dataid_vector_pipe [i] <= dataid_vector_pipe[i-1];
end
end
end
assign int_do_rmw_correct = |bg_do_rmw_correct;
assign int_do_rmw_partial = |bg_do_rmw_partial;
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
rmw_correct_pipe <= 0;
end
else
begin
rmw_correct_pipe <= {rmw_correct_pipe[CFG_WLAT_PIPE_LENGTH - 2:0],int_do_rmw_correct};
end
end
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
rmw_partial_pipe <= 0;
end
else
begin
rmw_partial_pipe <= {rmw_partial_pipe[CFG_WLAT_PIPE_LENGTH - 2:0],int_do_rmw_partial};
end
end
// Pre-calculated logic for each DQS group
generate
genvar P;
for (P = 0;P < CFG_DRAM_WLAT_GROUP;P = P + 1)
begin : pre_calculate_logic_per_dqs_group
// afi_wlat for current DQS group
wire [(CFG_WLAT_BUS_WIDTH / CFG_DRAM_WLAT_GROUP) - 1 : 0] current_afi_wlat = afi_wlat [(P + 1) * (CFG_WLAT_BUS_WIDTH / CFG_DRAM_WLAT_GROUP) - 1 : P * (CFG_WLAT_BUS_WIDTH / CFG_DRAM_WLAT_GROUP)];
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
afi_wlat_eq_0 [P] <= 1'b0;
afi_wlat_minus_1 [P] <= {(CFG_WLAT_BUS_WIDTH / CFG_DRAM_WLAT_GROUP){1'b0}};
afi_wlat_minus_2 [P] <= {(CFG_WLAT_BUS_WIDTH / CFG_DRAM_WLAT_GROUP){1'b0}};
afi_wlat_minus_3 [P] <= {(CFG_WLAT_BUS_WIDTH / CFG_DRAM_WLAT_GROUP){1'b0}};
end
else
begin
if (current_afi_wlat == 0)
begin
afi_wlat_eq_0 [P] <= 1'b1;
end
else
begin
afi_wlat_eq_0 [P] <= 1'b0;
end
afi_wlat_minus_1 [P] <= current_afi_wlat - 1;
afi_wlat_minus_2 [P] <= current_afi_wlat - 2;
afi_wlat_minus_3 [P] <= current_afi_wlat - 3;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
doing_write_pipe_eq_afi_wlat_minus_0 [P] <= 1'b0;
doing_write_pipe_eq_afi_wlat_minus_1 [P] <= 1'b0;
doing_write_pipe_eq_afi_wlat_minus_2 [P] <= 1'b0;
end
else
begin
if (current_afi_wlat == 0)
begin
doing_write_pipe_eq_afi_wlat_minus_0 [P] <= 1'b0;
doing_write_pipe_eq_afi_wlat_minus_1 [P] <= 1'b0;
doing_write_pipe_eq_afi_wlat_minus_2 [P] <= 1'b0;
end
else if (current_afi_wlat == 1)
begin
if (doing_write_pipe[0])
begin
doing_write_pipe_eq_afi_wlat_minus_0 [P] <= 1'b1;
end
else
begin
doing_write_pipe_eq_afi_wlat_minus_0 [P] <= 1'b0;
end
if (bg_doing_write)
begin
doing_write_pipe_eq_afi_wlat_minus_1 [P] <= 1'b1;
end
else
begin
doing_write_pipe_eq_afi_wlat_minus_1 [P] <= 1'b0;
end
if (bg_doing_write) // we must disable int_cfg_output_regd when (afi_wlat < 2)
begin
doing_write_pipe_eq_afi_wlat_minus_2 [P] <= 1'b1;
end
else
begin
doing_write_pipe_eq_afi_wlat_minus_2 [P] <= 1'b0;
end
end
else if (current_afi_wlat == 2)
begin
if (doing_write_pipe[1])
begin
doing_write_pipe_eq_afi_wlat_minus_0 [P] <= 1'b1;
end
else
begin
doing_write_pipe_eq_afi_wlat_minus_0 [P] <= 1'b0;
end
if (doing_write_pipe[0])
begin
doing_write_pipe_eq_afi_wlat_minus_1 [P] <= 1'b1;
end
else
begin
doing_write_pipe_eq_afi_wlat_minus_1 [P] <= 1'b0;
end
if (bg_doing_write)
begin
doing_write_pipe_eq_afi_wlat_minus_2 [P] <= 1'b1;
end
else
begin
doing_write_pipe_eq_afi_wlat_minus_2 [P] <= 1'b0;
end
end
else
begin
if (doing_write_pipe[afi_wlat_minus_1 [P]])
begin
doing_write_pipe_eq_afi_wlat_minus_0 [P] <= 1'b1;
end
else
begin
doing_write_pipe_eq_afi_wlat_minus_0 [P] <= 1'b0;
end
if (doing_write_pipe[afi_wlat_minus_2 [P]])
begin
doing_write_pipe_eq_afi_wlat_minus_1 [P] <= 1'b1;
end
else
begin
doing_write_pipe_eq_afi_wlat_minus_1 [P] <= 1'b0;
end
if (doing_write_pipe[afi_wlat_minus_3 [P]])
begin
doing_write_pipe_eq_afi_wlat_minus_2 [P] <= 1'b1;
end
else
begin
doing_write_pipe_eq_afi_wlat_minus_2 [P] <= 1'b0;
end
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
rdwr_data_valid_pipe_eq_afi_wlat_minus_1 [P] <= 1'b0;
rdwr_data_valid_pipe_eq_afi_wlat_minus_2 [P] <= 1'b0;
end
else
begin
if (current_afi_wlat == 0)
begin
rdwr_data_valid_pipe_eq_afi_wlat_minus_1 [P] <= 1'b0;
rdwr_data_valid_pipe_eq_afi_wlat_minus_2 [P] <= 1'b0;
end
else if (current_afi_wlat == 1)
begin
if (bg_rdwr_data_valid)
begin
rdwr_data_valid_pipe_eq_afi_wlat_minus_1 [P] <= 1'b1;
end
else
begin
rdwr_data_valid_pipe_eq_afi_wlat_minus_1 [P] <= 1'b0;
end
if (bg_rdwr_data_valid) // we must disable int_cfg_output_regd when (afi_wlat < 2)
begin
rdwr_data_valid_pipe_eq_afi_wlat_minus_2 [P] <= 1'b1;
end
else
begin
rdwr_data_valid_pipe_eq_afi_wlat_minus_2 [P] <= 1'b0;
end
end
else if (current_afi_wlat == 2)
begin
if (rdwr_data_valid_pipe[0])
begin
rdwr_data_valid_pipe_eq_afi_wlat_minus_1 [P] <= 1'b1;
end
else
begin
rdwr_data_valid_pipe_eq_afi_wlat_minus_1 [P] <= 1'b0;
end
if (bg_rdwr_data_valid)
begin
rdwr_data_valid_pipe_eq_afi_wlat_minus_2 [P] <= 1'b1;
end
else
begin
rdwr_data_valid_pipe_eq_afi_wlat_minus_2 [P] <= 1'b0;
end
end
else
begin
if (rdwr_data_valid_pipe[afi_wlat_minus_2 [P]])
begin
rdwr_data_valid_pipe_eq_afi_wlat_minus_1 [P] <= 1'b1;
end
else
begin
rdwr_data_valid_pipe_eq_afi_wlat_minus_1 [P] <= 1'b0;
end
if (rdwr_data_valid_pipe[afi_wlat_minus_3 [P]])
begin
rdwr_data_valid_pipe_eq_afi_wlat_minus_2 [P] <= 1'b1;
end
else
begin
rdwr_data_valid_pipe_eq_afi_wlat_minus_2 [P] <= 1'b0;
end
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
dataid_pipe_eq_afi_wlat_minus_1 [P] <= 0;
dataid_pipe_eq_afi_wlat_minus_2 [P] <= 0;
dataid_vector_pipe_eq_afi_wlat_minus_1 [P] <= 0;
dataid_vector_pipe_eq_afi_wlat_minus_2 [P] <= 0;
end
else
begin
if (current_afi_wlat == 0)
begin
dataid_pipe_eq_afi_wlat_minus_1 [P] <= 0;
dataid_pipe_eq_afi_wlat_minus_2 [P] <= 0;
dataid_vector_pipe_eq_afi_wlat_minus_1 [P] <= 0;
dataid_vector_pipe_eq_afi_wlat_minus_2 [P] <= 0;
end
else if (current_afi_wlat == 1)
begin
dataid_pipe_eq_afi_wlat_minus_1 [P] <= dataid;
dataid_pipe_eq_afi_wlat_minus_2 [P] <= dataid; // we must disable int_cfg_output_regd when (afi_wlat < 2)
dataid_vector_pipe_eq_afi_wlat_minus_1 [P] <= dataid_vector;
dataid_vector_pipe_eq_afi_wlat_minus_2 [P] <= dataid_vector; // we must disable int_cfg_output_regd when (afi_wlat < 2)
end
else if (current_afi_wlat == 2)
begin
dataid_pipe_eq_afi_wlat_minus_1 [P] <= dataid_pipe [0];
dataid_pipe_eq_afi_wlat_minus_2 [P] <= dataid;
dataid_vector_pipe_eq_afi_wlat_minus_1 [P] <= dataid_vector_pipe[0];
dataid_vector_pipe_eq_afi_wlat_minus_2 [P] <= dataid_vector;
end
else
begin
dataid_pipe_eq_afi_wlat_minus_1 [P] <= dataid_pipe [afi_wlat_minus_2 [P]];
dataid_pipe_eq_afi_wlat_minus_2 [P] <= dataid_pipe [afi_wlat_minus_3 [P]];
dataid_vector_pipe_eq_afi_wlat_minus_1 [P] <= dataid_vector_pipe[afi_wlat_minus_2 [P]];
dataid_vector_pipe_eq_afi_wlat_minus_2 [P] <= dataid_vector_pipe[afi_wlat_minus_3 [P]];
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
rmw_correct_pipe_eq_afi_wlat_minus_1 [P] <= 1'b0;
rmw_correct_pipe_eq_afi_wlat_minus_2 [P] <= 1'b0;
rmw_partial_pipe_eq_afi_wlat_minus_1 [P] <= 1'b0;
rmw_partial_pipe_eq_afi_wlat_minus_2 [P] <= 1'b0;
end
else
begin
if (current_afi_wlat == 0)
begin
rmw_correct_pipe_eq_afi_wlat_minus_1 [P] <= 1'b0;
rmw_correct_pipe_eq_afi_wlat_minus_2 [P] <= 1'b0;
rmw_partial_pipe_eq_afi_wlat_minus_1 [P] <= 1'b0;
rmw_partial_pipe_eq_afi_wlat_minus_2 [P] <= 1'b0;
end
else if (current_afi_wlat == 1)
begin
if (int_do_rmw_correct)
begin
rmw_correct_pipe_eq_afi_wlat_minus_1 [P] <= 1'b1;
end
else
begin
rmw_correct_pipe_eq_afi_wlat_minus_1 [P] <= 1'b0;
end
if (int_do_rmw_partial)
begin
rmw_partial_pipe_eq_afi_wlat_minus_1 [P] <= 1'b1;
end
else
begin
rmw_partial_pipe_eq_afi_wlat_minus_1 [P] <= 1'b0;
end
if (int_do_rmw_correct) // we must disable int_cfg_output_regd when (afi_wlat < 2)
begin
rmw_correct_pipe_eq_afi_wlat_minus_2 [P] <= 1'b1;
end
else
begin
rmw_correct_pipe_eq_afi_wlat_minus_2 [P] <= 1'b0;
end
if (int_do_rmw_partial) // we must disable int_cfg_output_regd when (afi_wlat < 2)
begin
rmw_partial_pipe_eq_afi_wlat_minus_2 [P] <= 1'b1;
end
else
begin
rmw_partial_pipe_eq_afi_wlat_minus_2 [P] <= 1'b0;
end
end
else if (current_afi_wlat == 2)
begin
if (rmw_correct_pipe[0])
begin
rmw_correct_pipe_eq_afi_wlat_minus_1 [P] <= 1'b1;
end
else
begin
rmw_correct_pipe_eq_afi_wlat_minus_1 [P] <= 1'b0;
end
if (rmw_partial_pipe[0])
begin
rmw_partial_pipe_eq_afi_wlat_minus_1 [P] <= 1'b1;
end
else
begin
rmw_partial_pipe_eq_afi_wlat_minus_1 [P] <= 1'b0;
end
if (int_do_rmw_correct)
begin
rmw_correct_pipe_eq_afi_wlat_minus_2 [P] <= 1'b1;
end
else
begin
rmw_correct_pipe_eq_afi_wlat_minus_2 [P] <= 1'b0;
end
if (int_do_rmw_partial)
begin
rmw_partial_pipe_eq_afi_wlat_minus_2 [P] <= 1'b1;
end
else
begin
rmw_partial_pipe_eq_afi_wlat_minus_2 [P] <= 1'b0;
end
end
else
begin
if (rmw_correct_pipe[afi_wlat_minus_2 [P]])
begin
rmw_correct_pipe_eq_afi_wlat_minus_1 [P] <= 1'b1;
end
else
begin
rmw_correct_pipe_eq_afi_wlat_minus_1 [P] <= 1'b0;
end
if (rmw_partial_pipe[afi_wlat_minus_2 [P]])
begin
rmw_partial_pipe_eq_afi_wlat_minus_1 [P] <= 1'b1;
end
else
begin
rmw_partial_pipe_eq_afi_wlat_minus_1 [P] <= 1'b0;
end
if (rmw_correct_pipe[afi_wlat_minus_3 [P]])
begin
rmw_correct_pipe_eq_afi_wlat_minus_2 [P] <= 1'b1;
end
else
begin
rmw_correct_pipe_eq_afi_wlat_minus_2 [P] <= 1'b0;
end
if (rmw_partial_pipe[afi_wlat_minus_3 [P]])
begin
rmw_partial_pipe_eq_afi_wlat_minus_2 [P] <= 1'b1;
end
else
begin
rmw_partial_pipe_eq_afi_wlat_minus_2 [P] <= 1'b0;
end
end
end
end
always @ (*)
begin
if (CFG_WDATA_REG || CFG_ECC_ENC_REG)
begin
doing_write_pipe_eq_afi_wlat_minus_x [P] = doing_write_pipe_eq_afi_wlat_minus_2 [P];
rdwr_data_valid_pipe_eq_afi_wlat_minus_x [P] = rdwr_data_valid_pipe_eq_afi_wlat_minus_2 [P];
dataid_pipe_eq_afi_wlat_minus_x [P] = dataid_pipe_eq_afi_wlat_minus_2 [P];
dataid_vector_pipe_eq_afi_wlat_minus_x [P] = dataid_vector_pipe_eq_afi_wlat_minus_2 [P];
rmw_correct_pipe_eq_afi_wlat_minus_x [P] = rmw_correct_pipe_eq_afi_wlat_minus_2 [P];
rmw_partial_pipe_eq_afi_wlat_minus_x [P] = rmw_partial_pipe_eq_afi_wlat_minus_2 [P];
end
else
begin
doing_write_pipe_eq_afi_wlat_minus_x [P] = doing_write_pipe_eq_afi_wlat_minus_1 [P];
rdwr_data_valid_pipe_eq_afi_wlat_minus_x [P] = rdwr_data_valid_pipe_eq_afi_wlat_minus_1 [P];
dataid_pipe_eq_afi_wlat_minus_x [P] = dataid_pipe_eq_afi_wlat_minus_1 [P];
dataid_vector_pipe_eq_afi_wlat_minus_x [P] = dataid_vector_pipe_eq_afi_wlat_minus_1 [P];
rmw_correct_pipe_eq_afi_wlat_minus_x [P] = rmw_correct_pipe_eq_afi_wlat_minus_1 [P];
rmw_partial_pipe_eq_afi_wlat_minus_x [P] = rmw_partial_pipe_eq_afi_wlat_minus_1 [P];
end
end
// First vector
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
ecc_wdata_fifo_first_vector [P] <= 1'b0;
end
else
begin
if (current_afi_wlat == smallest_afi_wlat [CFG_DRAM_WLAT_GROUP - 1])
begin
ecc_wdata_fifo_first_vector [P] <= 1'b1;
end
else
begin
ecc_wdata_fifo_first_vector [P] <= 1'b0;
end
end
end
end
for (P = 1;P < CFG_DRAM_WLAT_GROUP;P = P + 1)
begin : afi_wlat_info_logic
// afi_wlat for current DQS group
wire [(CFG_WLAT_BUS_WIDTH / CFG_DRAM_WLAT_GROUP) - 1 : 0] current_afi_wlat = afi_wlat [(P + 1) * (CFG_WLAT_BUS_WIDTH / CFG_DRAM_WLAT_GROUP) - 1 : P * (CFG_WLAT_BUS_WIDTH / CFG_DRAM_WLAT_GROUP)];
// Smallest/largest afi_wlat logic
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
smallest_afi_wlat [P] <= 0;
largest_afi_wlat [P] <= 0;
end
else
begin
if (current_afi_wlat < smallest_afi_wlat [P-1])
begin
smallest_afi_wlat [P] <= current_afi_wlat;
end
else
begin
smallest_afi_wlat [P] <= smallest_afi_wlat [P-1];
end
if (current_afi_wlat > largest_afi_wlat [P-1])
begin
largest_afi_wlat [P] <= current_afi_wlat;
end
else
begin
largest_afi_wlat [P] <= largest_afi_wlat [P-1];
end
end
end
end
endgenerate
// Smallest/largest afi_wlat logic
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
smallest_afi_wlat [0] <= 0;
largest_afi_wlat [0] <= 0;
end
else
begin
smallest_afi_wlat [0] <= afi_wlat [(CFG_WLAT_BUS_WIDTH / CFG_DRAM_WLAT_GROUP) - 1 : 0];
largest_afi_wlat [0] <= afi_wlat [(CFG_WLAT_BUS_WIDTH / CFG_DRAM_WLAT_GROUP) - 1 : 0];
end
end
generate
if (CFG_DRAM_WLAT_GROUP == 1) // only one group of afi_wlat
begin
always @ (*)
begin
smallest_afi_wlat_eq_0 = afi_wlat_eq_0 [0];
smallest_afi_wlat_minus_1 = afi_wlat_minus_1 [0];
smallest_afi_wlat_minus_2 = afi_wlat_minus_2 [0];
smallest_afi_wlat_minus_3 = afi_wlat_minus_3 [0];
smallest_doing_write_pipe_eq_afi_wlat_minus_0 = doing_write_pipe_eq_afi_wlat_minus_0 [0];
smallest_doing_write_pipe_eq_afi_wlat_minus_1 = doing_write_pipe_eq_afi_wlat_minus_1 [0];
smallest_doing_write_pipe_eq_afi_wlat_minus_2 = doing_write_pipe_eq_afi_wlat_minus_2 [0];
smallest_rdwr_data_valid_pipe_eq_afi_wlat_minus_1 = rdwr_data_valid_pipe_eq_afi_wlat_minus_1 [0];
smallest_rdwr_data_valid_pipe_eq_afi_wlat_minus_2 = rdwr_data_valid_pipe_eq_afi_wlat_minus_2 [0];
smallest_dataid_pipe_eq_afi_wlat_minus_1 = dataid_pipe_eq_afi_wlat_minus_1 [0];
smallest_dataid_pipe_eq_afi_wlat_minus_2 = dataid_pipe_eq_afi_wlat_minus_2 [0];
smallest_dataid_vector_pipe_eq_afi_wlat_minus_1 = dataid_vector_pipe_eq_afi_wlat_minus_1 [0];
smallest_dataid_vector_pipe_eq_afi_wlat_minus_2 = dataid_vector_pipe_eq_afi_wlat_minus_2 [0];
smallest_rmw_correct_pipe_eq_afi_wlat_minus_1 = rmw_correct_pipe_eq_afi_wlat_minus_1 [0];
smallest_rmw_correct_pipe_eq_afi_wlat_minus_2 = rmw_correct_pipe_eq_afi_wlat_minus_2 [0];
smallest_rmw_partial_pipe_eq_afi_wlat_minus_1 = rmw_partial_pipe_eq_afi_wlat_minus_1 [0];
smallest_rmw_partial_pipe_eq_afi_wlat_minus_2 = rmw_partial_pipe_eq_afi_wlat_minus_2 [0];
smallest_doing_write_pipe_eq_afi_wlat_minus_x = doing_write_pipe_eq_afi_wlat_minus_x [0];
smallest_rdwr_data_valid_pipe_eq_afi_wlat_minus_x = rdwr_data_valid_pipe_eq_afi_wlat_minus_x [0];
smallest_dataid_pipe_eq_afi_wlat_minus_x = dataid_pipe_eq_afi_wlat_minus_x [0];
smallest_dataid_vector_pipe_eq_afi_wlat_minus_x = dataid_vector_pipe_eq_afi_wlat_minus_x [0];
smallest_rmw_correct_pipe_eq_afi_wlat_minus_x = rmw_correct_pipe_eq_afi_wlat_minus_x [0];
smallest_rmw_partial_pipe_eq_afi_wlat_minus_x = rmw_partial_pipe_eq_afi_wlat_minus_x [0];
largest_afi_wlat_eq_0 = afi_wlat_eq_0 [0];
largest_afi_wlat_minus_1 = afi_wlat_minus_1 [0];
largest_afi_wlat_minus_2 = afi_wlat_minus_2 [0];
largest_afi_wlat_minus_3 = afi_wlat_minus_3 [0];
largest_doing_write_pipe_eq_afi_wlat_minus_0 = doing_write_pipe_eq_afi_wlat_minus_0 [0];
largest_doing_write_pipe_eq_afi_wlat_minus_1 = doing_write_pipe_eq_afi_wlat_minus_1 [0];
largest_doing_write_pipe_eq_afi_wlat_minus_2 = doing_write_pipe_eq_afi_wlat_minus_2 [0];
largest_rdwr_data_valid_pipe_eq_afi_wlat_minus_1 = rdwr_data_valid_pipe_eq_afi_wlat_minus_1 [0];
largest_rdwr_data_valid_pipe_eq_afi_wlat_minus_2 = rdwr_data_valid_pipe_eq_afi_wlat_minus_2 [0];
largest_dataid_pipe_eq_afi_wlat_minus_1 = dataid_pipe_eq_afi_wlat_minus_1 [0];
largest_dataid_pipe_eq_afi_wlat_minus_2 = dataid_pipe_eq_afi_wlat_minus_2 [0];
largest_dataid_vector_pipe_eq_afi_wlat_minus_1 = dataid_vector_pipe_eq_afi_wlat_minus_1 [0];
largest_dataid_vector_pipe_eq_afi_wlat_minus_2 = dataid_vector_pipe_eq_afi_wlat_minus_2 [0];
largest_rmw_correct_pipe_eq_afi_wlat_minus_1 = rmw_correct_pipe_eq_afi_wlat_minus_1 [0];
largest_rmw_correct_pipe_eq_afi_wlat_minus_2 = rmw_correct_pipe_eq_afi_wlat_minus_2 [0];
largest_rmw_partial_pipe_eq_afi_wlat_minus_1 = rmw_partial_pipe_eq_afi_wlat_minus_1 [0];
largest_rmw_partial_pipe_eq_afi_wlat_minus_2 = rmw_partial_pipe_eq_afi_wlat_minus_2 [0];
largest_doing_write_pipe_eq_afi_wlat_minus_x = doing_write_pipe_eq_afi_wlat_minus_x [0];
largest_rdwr_data_valid_pipe_eq_afi_wlat_minus_x = rdwr_data_valid_pipe_eq_afi_wlat_minus_x [0];
largest_dataid_pipe_eq_afi_wlat_minus_x = dataid_pipe_eq_afi_wlat_minus_x [0];
largest_dataid_vector_pipe_eq_afi_wlat_minus_x = dataid_vector_pipe_eq_afi_wlat_minus_x [0];
largest_rmw_correct_pipe_eq_afi_wlat_minus_x = rmw_correct_pipe_eq_afi_wlat_minus_x [0];
largest_rmw_partial_pipe_eq_afi_wlat_minus_x = rmw_partial_pipe_eq_afi_wlat_minus_x [0];
end
end
else
begin
// Pre-calculated logic for smallest/largest afi_wlat (for afi addr/cmd logic)
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
smallest_afi_wlat_eq_0 <= 1'b0;
smallest_afi_wlat_minus_1 <= {(CFG_WLAT_BUS_WIDTH / CFG_DRAM_WLAT_GROUP){1'b0}};
smallest_afi_wlat_minus_2 <= {(CFG_WLAT_BUS_WIDTH / CFG_DRAM_WLAT_GROUP){1'b0}};
smallest_afi_wlat_minus_3 <= {(CFG_WLAT_BUS_WIDTH / CFG_DRAM_WLAT_GROUP){1'b0}};
end
else
begin
if (smallest_afi_wlat [CFG_DRAM_WLAT_GROUP-1] == 0)
begin
smallest_afi_wlat_eq_0 <= 1'b1;
end
else
begin
smallest_afi_wlat_eq_0 <= 1'b0;
end
smallest_afi_wlat_minus_1 <= smallest_afi_wlat [CFG_DRAM_WLAT_GROUP-1] - 1;
smallest_afi_wlat_minus_2 <= smallest_afi_wlat [CFG_DRAM_WLAT_GROUP-1] - 2;
smallest_afi_wlat_minus_3 <= smallest_afi_wlat [CFG_DRAM_WLAT_GROUP-1] - 3;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
smallest_doing_write_pipe_eq_afi_wlat_minus_0 <= 1'b0;
smallest_doing_write_pipe_eq_afi_wlat_minus_1 <= 1'b0;
smallest_doing_write_pipe_eq_afi_wlat_minus_2 <= 1'b0;
end
else
begin
if (smallest_afi_wlat [CFG_DRAM_WLAT_GROUP-1] == 0)
begin
smallest_doing_write_pipe_eq_afi_wlat_minus_0 <= 1'b0;
smallest_doing_write_pipe_eq_afi_wlat_minus_1 <= 1'b0;
smallest_doing_write_pipe_eq_afi_wlat_minus_2 <= 1'b0;
end
else if (smallest_afi_wlat [CFG_DRAM_WLAT_GROUP-1] == 1)
begin
if (doing_write_pipe[0])
begin
smallest_doing_write_pipe_eq_afi_wlat_minus_0 <= 1'b1;
end
else
begin
smallest_doing_write_pipe_eq_afi_wlat_minus_0 <= 1'b0;
end
if (bg_doing_write)
begin
smallest_doing_write_pipe_eq_afi_wlat_minus_1 <= 1'b1;
end
else
begin
smallest_doing_write_pipe_eq_afi_wlat_minus_1 <= 1'b0;
end
if (bg_doing_write) // we must disable int_cfg_output_regd when (afi_wlat < 2)
begin
smallest_doing_write_pipe_eq_afi_wlat_minus_2 <= 1'b1;
end
else
begin
smallest_doing_write_pipe_eq_afi_wlat_minus_2 <= 1'b0;
end
end
else if (smallest_afi_wlat [CFG_DRAM_WLAT_GROUP-1] == 2)
begin
if (doing_write_pipe[1])
begin
smallest_doing_write_pipe_eq_afi_wlat_minus_0 <= 1'b1;
end
else
begin
smallest_doing_write_pipe_eq_afi_wlat_minus_0 <= 1'b0;
end
if (doing_write_pipe[0])
begin
smallest_doing_write_pipe_eq_afi_wlat_minus_1 <= 1'b1;
end
else
begin
smallest_doing_write_pipe_eq_afi_wlat_minus_1 <= 1'b0;
end
if (bg_doing_write)
begin
smallest_doing_write_pipe_eq_afi_wlat_minus_2 <= 1'b1;
end
else
begin
smallest_doing_write_pipe_eq_afi_wlat_minus_2 <= 1'b0;
end
end
else
begin
if (doing_write_pipe[smallest_afi_wlat_minus_1])
begin
smallest_doing_write_pipe_eq_afi_wlat_minus_0 <= 1'b1;
end
else
begin
smallest_doing_write_pipe_eq_afi_wlat_minus_0 <= 1'b0;
end
if (doing_write_pipe[smallest_afi_wlat_minus_2])
begin
smallest_doing_write_pipe_eq_afi_wlat_minus_1 <= 1'b1;
end
else
begin
smallest_doing_write_pipe_eq_afi_wlat_minus_1 <= 1'b0;
end
if (doing_write_pipe[smallest_afi_wlat_minus_3])
begin
smallest_doing_write_pipe_eq_afi_wlat_minus_2 <= 1'b1;
end
else
begin
smallest_doing_write_pipe_eq_afi_wlat_minus_2 <= 1'b0;
end
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
smallest_rdwr_data_valid_pipe_eq_afi_wlat_minus_1 <= 1'b0;
smallest_rdwr_data_valid_pipe_eq_afi_wlat_minus_2 <= 1'b0;
end
else
begin
if (smallest_afi_wlat [CFG_DRAM_WLAT_GROUP-1] == 0)
begin
smallest_rdwr_data_valid_pipe_eq_afi_wlat_minus_1 <= 1'b0;
smallest_rdwr_data_valid_pipe_eq_afi_wlat_minus_2 <= 1'b0;
end
else if (smallest_afi_wlat [CFG_DRAM_WLAT_GROUP-1] == 1)
begin
if (bg_rdwr_data_valid)
begin
smallest_rdwr_data_valid_pipe_eq_afi_wlat_minus_1 <= 1'b1;
end
else
begin
smallest_rdwr_data_valid_pipe_eq_afi_wlat_minus_1 <= 1'b0;
end
if (bg_rdwr_data_valid) // we must disable int_cfg_output_regd when (afi_wlat < 2)
begin
smallest_rdwr_data_valid_pipe_eq_afi_wlat_minus_2 <= 1'b1;
end
else
begin
smallest_rdwr_data_valid_pipe_eq_afi_wlat_minus_2 <= 1'b0;
end
end
else if (smallest_afi_wlat [CFG_DRAM_WLAT_GROUP-1] == 2)
begin
if (rdwr_data_valid_pipe[0])
begin
smallest_rdwr_data_valid_pipe_eq_afi_wlat_minus_1 <= 1'b1;
end
else
begin
smallest_rdwr_data_valid_pipe_eq_afi_wlat_minus_1 <= 1'b0;
end
if (bg_rdwr_data_valid)
begin
smallest_rdwr_data_valid_pipe_eq_afi_wlat_minus_2 <= 1'b1;
end
else
begin
smallest_rdwr_data_valid_pipe_eq_afi_wlat_minus_2 <= 1'b0;
end
end
else
begin
if (rdwr_data_valid_pipe[smallest_afi_wlat_minus_2])
begin
smallest_rdwr_data_valid_pipe_eq_afi_wlat_minus_1 <= 1'b1;
end
else
begin
smallest_rdwr_data_valid_pipe_eq_afi_wlat_minus_1 <= 1'b0;
end
if (rdwr_data_valid_pipe[smallest_afi_wlat_minus_3])
begin
smallest_rdwr_data_valid_pipe_eq_afi_wlat_minus_2 <= 1'b1;
end
else
begin
smallest_rdwr_data_valid_pipe_eq_afi_wlat_minus_2 <= 1'b0;
end
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
smallest_dataid_pipe_eq_afi_wlat_minus_1 <= 0;
smallest_dataid_pipe_eq_afi_wlat_minus_2 <= 0;
smallest_dataid_vector_pipe_eq_afi_wlat_minus_1 <= 0;
smallest_dataid_vector_pipe_eq_afi_wlat_minus_2 <= 0;
end
else
begin
if (smallest_afi_wlat [CFG_DRAM_WLAT_GROUP-1] == 0)
begin
smallest_dataid_pipe_eq_afi_wlat_minus_1 <= 0;
smallest_dataid_pipe_eq_afi_wlat_minus_2 <= 0;
smallest_dataid_vector_pipe_eq_afi_wlat_minus_1 <= 0;
smallest_dataid_vector_pipe_eq_afi_wlat_minus_2 <= 0;
end
else if (smallest_afi_wlat [CFG_DRAM_WLAT_GROUP-1] == 1)
begin
smallest_dataid_pipe_eq_afi_wlat_minus_1 <= dataid;
smallest_dataid_pipe_eq_afi_wlat_minus_2 <= dataid; // we must disable int_cfg_output_regd when (afi_wlat < 2)
smallest_dataid_vector_pipe_eq_afi_wlat_minus_1 <= dataid_vector;
smallest_dataid_vector_pipe_eq_afi_wlat_minus_2 <= dataid_vector; // we must disable int_cfg_output_regd when (afi_wlat < 2)
end
else if (smallest_afi_wlat [CFG_DRAM_WLAT_GROUP-1] == 2)
begin
smallest_dataid_pipe_eq_afi_wlat_minus_1 <= dataid_pipe [0];
smallest_dataid_pipe_eq_afi_wlat_minus_2 <= dataid;
smallest_dataid_vector_pipe_eq_afi_wlat_minus_1 <= dataid_vector_pipe[0];
smallest_dataid_vector_pipe_eq_afi_wlat_minus_2 <= dataid_vector;
end
else
begin
smallest_dataid_pipe_eq_afi_wlat_minus_1 <= dataid_pipe [smallest_afi_wlat_minus_2];
smallest_dataid_pipe_eq_afi_wlat_minus_2 <= dataid_pipe [smallest_afi_wlat_minus_3];
smallest_dataid_vector_pipe_eq_afi_wlat_minus_1 <= dataid_vector_pipe[smallest_afi_wlat_minus_2];
smallest_dataid_vector_pipe_eq_afi_wlat_minus_2 <= dataid_vector_pipe[smallest_afi_wlat_minus_3];
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
smallest_rmw_correct_pipe_eq_afi_wlat_minus_1 <= 1'b0;
smallest_rmw_correct_pipe_eq_afi_wlat_minus_2 <= 1'b0;
smallest_rmw_partial_pipe_eq_afi_wlat_minus_1 <= 1'b0;
smallest_rmw_partial_pipe_eq_afi_wlat_minus_2 <= 1'b0;
end
else
begin
if (smallest_afi_wlat [CFG_DRAM_WLAT_GROUP-1] == 0)
begin
smallest_rmw_correct_pipe_eq_afi_wlat_minus_1 <= 1'b0;
smallest_rmw_correct_pipe_eq_afi_wlat_minus_2 <= 1'b0;
smallest_rmw_partial_pipe_eq_afi_wlat_minus_1 <= 1'b0;
smallest_rmw_partial_pipe_eq_afi_wlat_minus_2 <= 1'b0;
end
else if (smallest_afi_wlat [CFG_DRAM_WLAT_GROUP-1] == 1)
begin
if (int_do_rmw_correct)
begin
smallest_rmw_correct_pipe_eq_afi_wlat_minus_1 <= 1'b1;
end
else
begin
smallest_rmw_correct_pipe_eq_afi_wlat_minus_1 <= 1'b0;
end
if (int_do_rmw_partial)
begin
smallest_rmw_partial_pipe_eq_afi_wlat_minus_1 <= 1'b1;
end
else
begin
smallest_rmw_partial_pipe_eq_afi_wlat_minus_1 <= 1'b0;
end
if (int_do_rmw_correct) // we must disable int_cfg_output_regd when (afi_wlat < 2)
begin
smallest_rmw_correct_pipe_eq_afi_wlat_minus_2 <= 1'b1;
end
else
begin
smallest_rmw_correct_pipe_eq_afi_wlat_minus_2 <= 1'b0;
end
if (int_do_rmw_partial) // we must disable int_cfg_output_regd when (afi_wlat < 2)
begin
smallest_rmw_partial_pipe_eq_afi_wlat_minus_2 <= 1'b1;
end
else
begin
smallest_rmw_partial_pipe_eq_afi_wlat_minus_2 <= 1'b0;
end
end
else if (smallest_afi_wlat [CFG_DRAM_WLAT_GROUP-1] == 2)
begin
if (rmw_correct_pipe[0])
begin
smallest_rmw_correct_pipe_eq_afi_wlat_minus_1 <= 1'b1;
end
else
begin
smallest_rmw_correct_pipe_eq_afi_wlat_minus_1 <= 1'b0;
end
if (rmw_partial_pipe[0])
begin
smallest_rmw_partial_pipe_eq_afi_wlat_minus_1 <= 1'b1;
end
else
begin
smallest_rmw_partial_pipe_eq_afi_wlat_minus_1 <= 1'b0;
end
if (int_do_rmw_correct)
begin
smallest_rmw_correct_pipe_eq_afi_wlat_minus_2 <= 1'b1;
end
else
begin
smallest_rmw_correct_pipe_eq_afi_wlat_minus_2 <= 1'b0;
end
if (int_do_rmw_partial)
begin
smallest_rmw_partial_pipe_eq_afi_wlat_minus_2 <= 1'b1;
end
else
begin
smallest_rmw_partial_pipe_eq_afi_wlat_minus_2 <= 1'b0;
end
end
else
begin
if (rmw_correct_pipe[smallest_afi_wlat_minus_2])
begin
smallest_rmw_correct_pipe_eq_afi_wlat_minus_1 <= 1'b1;
end
else
begin
smallest_rmw_correct_pipe_eq_afi_wlat_minus_1 <= 1'b0;
end
if (rmw_partial_pipe[smallest_afi_wlat_minus_2])
begin
smallest_rmw_partial_pipe_eq_afi_wlat_minus_1 <= 1'b1;
end
else
begin
smallest_rmw_partial_pipe_eq_afi_wlat_minus_1 <= 1'b0;
end
if (rmw_correct_pipe[smallest_afi_wlat_minus_3])
begin
smallest_rmw_correct_pipe_eq_afi_wlat_minus_2 <= 1'b1;
end
else
begin
smallest_rmw_correct_pipe_eq_afi_wlat_minus_2 <= 1'b0;
end
if (rmw_partial_pipe[smallest_afi_wlat_minus_3])
begin
smallest_rmw_partial_pipe_eq_afi_wlat_minus_2 <= 1'b1;
end
else
begin
smallest_rmw_partial_pipe_eq_afi_wlat_minus_2 <= 1'b0;
end
end
end
end
always @ (*)
begin
if (CFG_WDATA_REG || CFG_ECC_ENC_REG)
begin
smallest_doing_write_pipe_eq_afi_wlat_minus_x = smallest_doing_write_pipe_eq_afi_wlat_minus_2 ;
smallest_rdwr_data_valid_pipe_eq_afi_wlat_minus_x = smallest_rdwr_data_valid_pipe_eq_afi_wlat_minus_2;
smallest_dataid_pipe_eq_afi_wlat_minus_x = smallest_dataid_pipe_eq_afi_wlat_minus_2 ;
smallest_dataid_vector_pipe_eq_afi_wlat_minus_x = smallest_dataid_vector_pipe_eq_afi_wlat_minus_2 ;
smallest_rmw_correct_pipe_eq_afi_wlat_minus_x = smallest_rmw_correct_pipe_eq_afi_wlat_minus_2 ;
smallest_rmw_partial_pipe_eq_afi_wlat_minus_x = smallest_rmw_partial_pipe_eq_afi_wlat_minus_2 ;
end
else
begin
smallest_doing_write_pipe_eq_afi_wlat_minus_x = smallest_doing_write_pipe_eq_afi_wlat_minus_1 ;
smallest_rdwr_data_valid_pipe_eq_afi_wlat_minus_x = smallest_rdwr_data_valid_pipe_eq_afi_wlat_minus_1;
smallest_dataid_pipe_eq_afi_wlat_minus_x = smallest_dataid_pipe_eq_afi_wlat_minus_1 ;
smallest_dataid_vector_pipe_eq_afi_wlat_minus_x = smallest_dataid_vector_pipe_eq_afi_wlat_minus_1 ;
smallest_rmw_correct_pipe_eq_afi_wlat_minus_x = smallest_rmw_correct_pipe_eq_afi_wlat_minus_1 ;
smallest_rmw_partial_pipe_eq_afi_wlat_minus_x = smallest_rmw_partial_pipe_eq_afi_wlat_minus_1 ;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
largest_afi_wlat_eq_0 <= 1'b0;
largest_afi_wlat_minus_1 <= {(CFG_WLAT_BUS_WIDTH / CFG_DRAM_WLAT_GROUP){1'b0}};
largest_afi_wlat_minus_2 <= {(CFG_WLAT_BUS_WIDTH / CFG_DRAM_WLAT_GROUP){1'b0}};
largest_afi_wlat_minus_3 <= {(CFG_WLAT_BUS_WIDTH / CFG_DRAM_WLAT_GROUP){1'b0}};
end
else
begin
if (largest_afi_wlat [CFG_DRAM_WLAT_GROUP-1] == 0)
begin
largest_afi_wlat_eq_0 <= 1'b1;
end
else
begin
largest_afi_wlat_eq_0 <= 1'b0;
end
largest_afi_wlat_minus_1 <= largest_afi_wlat [CFG_DRAM_WLAT_GROUP-1] - 1;
largest_afi_wlat_minus_2 <= largest_afi_wlat [CFG_DRAM_WLAT_GROUP-1] - 2;
largest_afi_wlat_minus_3 <= largest_afi_wlat [CFG_DRAM_WLAT_GROUP-1] - 3;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
largest_doing_write_pipe_eq_afi_wlat_minus_0 <= 1'b0;
largest_doing_write_pipe_eq_afi_wlat_minus_1 <= 1'b0;
largest_doing_write_pipe_eq_afi_wlat_minus_2 <= 1'b0;
end
else
begin
if (largest_afi_wlat [CFG_DRAM_WLAT_GROUP-1] == 0)
begin
largest_doing_write_pipe_eq_afi_wlat_minus_0 <= 1'b0;
largest_doing_write_pipe_eq_afi_wlat_minus_1 <= 1'b0;
largest_doing_write_pipe_eq_afi_wlat_minus_2 <= 1'b0;
end
else if (largest_afi_wlat [CFG_DRAM_WLAT_GROUP-1] == 1)
begin
if (doing_write_pipe[0])
begin
largest_doing_write_pipe_eq_afi_wlat_minus_0 <= 1'b1;
end
else
begin
largest_doing_write_pipe_eq_afi_wlat_minus_0 <= 1'b0;
end
if (bg_doing_write)
begin
largest_doing_write_pipe_eq_afi_wlat_minus_1 <= 1'b1;
end
else
begin
largest_doing_write_pipe_eq_afi_wlat_minus_1 <= 1'b0;
end
if (bg_doing_write) // we must disable int_cfg_output_regd when (afi_wlat < 2)
begin
largest_doing_write_pipe_eq_afi_wlat_minus_2 <= 1'b1;
end
else
begin
largest_doing_write_pipe_eq_afi_wlat_minus_2 <= 1'b0;
end
end
else if (largest_afi_wlat [CFG_DRAM_WLAT_GROUP-1] == 2)
begin
if (doing_write_pipe[1])
begin
largest_doing_write_pipe_eq_afi_wlat_minus_0 <= 1'b1;
end
else
begin
largest_doing_write_pipe_eq_afi_wlat_minus_0 <= 1'b0;
end
if (doing_write_pipe[0])
begin
largest_doing_write_pipe_eq_afi_wlat_minus_1 <= 1'b1;
end
else
begin
largest_doing_write_pipe_eq_afi_wlat_minus_1 <= 1'b0;
end
if (bg_doing_write)
begin
largest_doing_write_pipe_eq_afi_wlat_minus_2 <= 1'b1;
end
else
begin
largest_doing_write_pipe_eq_afi_wlat_minus_2 <= 1'b0;
end
end
else
begin
if (doing_write_pipe[largest_afi_wlat_minus_1])
begin
largest_doing_write_pipe_eq_afi_wlat_minus_0 <= 1'b1;
end
else
begin
largest_doing_write_pipe_eq_afi_wlat_minus_0 <= 1'b0;
end
if (doing_write_pipe[largest_afi_wlat_minus_2])
begin
largest_doing_write_pipe_eq_afi_wlat_minus_1 <= 1'b1;
end
else
begin
largest_doing_write_pipe_eq_afi_wlat_minus_1 <= 1'b0;
end
if (doing_write_pipe[largest_afi_wlat_minus_3])
begin
largest_doing_write_pipe_eq_afi_wlat_minus_2 <= 1'b1;
end
else
begin
largest_doing_write_pipe_eq_afi_wlat_minus_2 <= 1'b0;
end
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
largest_rdwr_data_valid_pipe_eq_afi_wlat_minus_1 <= 1'b0;
largest_rdwr_data_valid_pipe_eq_afi_wlat_minus_2 <= 1'b0;
end
else
begin
if (largest_afi_wlat [CFG_DRAM_WLAT_GROUP-1] == 0)
begin
largest_rdwr_data_valid_pipe_eq_afi_wlat_minus_1 <= 1'b0;
largest_rdwr_data_valid_pipe_eq_afi_wlat_minus_2 <= 1'b0;
end
else if (largest_afi_wlat [CFG_DRAM_WLAT_GROUP-1] == 1)
begin
if (bg_rdwr_data_valid)
begin
largest_rdwr_data_valid_pipe_eq_afi_wlat_minus_1 <= 1'b1;
end
else
begin
largest_rdwr_data_valid_pipe_eq_afi_wlat_minus_1 <= 1'b0;
end
if (bg_rdwr_data_valid) // we must disable int_cfg_output_regd when (afi_wlat < 2)
begin
largest_rdwr_data_valid_pipe_eq_afi_wlat_minus_2 <= 1'b1;
end
else
begin
largest_rdwr_data_valid_pipe_eq_afi_wlat_minus_2 <= 1'b0;
end
end
else if (largest_afi_wlat [CFG_DRAM_WLAT_GROUP-1] == 2)
begin
if (rdwr_data_valid_pipe[0])
begin
largest_rdwr_data_valid_pipe_eq_afi_wlat_minus_1 <= 1'b1;
end
else
begin
largest_rdwr_data_valid_pipe_eq_afi_wlat_minus_1 <= 1'b0;
end
if (bg_rdwr_data_valid)
begin
largest_rdwr_data_valid_pipe_eq_afi_wlat_minus_2 <= 1'b1;
end
else
begin
largest_rdwr_data_valid_pipe_eq_afi_wlat_minus_2 <= 1'b0;
end
end
else
begin
if (rdwr_data_valid_pipe[largest_afi_wlat_minus_2])
begin
largest_rdwr_data_valid_pipe_eq_afi_wlat_minus_1 <= 1'b1;
end
else
begin
largest_rdwr_data_valid_pipe_eq_afi_wlat_minus_1 <= 1'b0;
end
if (rdwr_data_valid_pipe[largest_afi_wlat_minus_3])
begin
largest_rdwr_data_valid_pipe_eq_afi_wlat_minus_2 <= 1'b1;
end
else
begin
largest_rdwr_data_valid_pipe_eq_afi_wlat_minus_2 <= 1'b0;
end
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
largest_dataid_pipe_eq_afi_wlat_minus_1 <= 0;
largest_dataid_pipe_eq_afi_wlat_minus_2 <= 0;
largest_dataid_vector_pipe_eq_afi_wlat_minus_1 <= 0;
largest_dataid_vector_pipe_eq_afi_wlat_minus_2 <= 0;
end
else
begin
if (largest_afi_wlat [CFG_DRAM_WLAT_GROUP-1] == 0)
begin
largest_dataid_pipe_eq_afi_wlat_minus_1 <= 0;
largest_dataid_pipe_eq_afi_wlat_minus_2 <= 0;
largest_dataid_vector_pipe_eq_afi_wlat_minus_1 <= 0;
largest_dataid_vector_pipe_eq_afi_wlat_minus_2 <= 0;
end
else if (largest_afi_wlat [CFG_DRAM_WLAT_GROUP-1] == 1)
begin
largest_dataid_pipe_eq_afi_wlat_minus_1 <= dataid;
largest_dataid_pipe_eq_afi_wlat_minus_2 <= dataid; // we must disable int_cfg_output_regd when (afi_wlat < 2)
largest_dataid_vector_pipe_eq_afi_wlat_minus_1 <= dataid_vector;
largest_dataid_vector_pipe_eq_afi_wlat_minus_2 <= dataid_vector; // we must disable int_cfg_output_regd when (afi_wlat < 2)
end
else if (largest_afi_wlat [CFG_DRAM_WLAT_GROUP-1] == 2)
begin
largest_dataid_pipe_eq_afi_wlat_minus_1 <= dataid_pipe [0];
largest_dataid_pipe_eq_afi_wlat_minus_2 <= dataid;
largest_dataid_vector_pipe_eq_afi_wlat_minus_1 <= dataid_vector_pipe[0];
largest_dataid_vector_pipe_eq_afi_wlat_minus_2 <= dataid_vector;
end
else
begin
largest_dataid_pipe_eq_afi_wlat_minus_1 <= dataid_pipe [largest_afi_wlat_minus_2];
largest_dataid_pipe_eq_afi_wlat_minus_2 <= dataid_pipe [largest_afi_wlat_minus_3];
largest_dataid_vector_pipe_eq_afi_wlat_minus_1 <= dataid_vector_pipe[largest_afi_wlat_minus_2];
largest_dataid_vector_pipe_eq_afi_wlat_minus_2 <= dataid_vector_pipe[largest_afi_wlat_minus_3];
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
largest_rmw_correct_pipe_eq_afi_wlat_minus_1 <= 1'b0;
largest_rmw_correct_pipe_eq_afi_wlat_minus_2 <= 1'b0;
largest_rmw_partial_pipe_eq_afi_wlat_minus_1 <= 1'b0;
largest_rmw_partial_pipe_eq_afi_wlat_minus_2 <= 1'b0;
end
else
begin
if (largest_afi_wlat [CFG_DRAM_WLAT_GROUP-1] == 0)
begin
largest_rmw_correct_pipe_eq_afi_wlat_minus_1 <= 1'b0;
largest_rmw_correct_pipe_eq_afi_wlat_minus_2 <= 1'b0;
largest_rmw_partial_pipe_eq_afi_wlat_minus_1 <= 1'b0;
largest_rmw_partial_pipe_eq_afi_wlat_minus_2 <= 1'b0;
end
else if (largest_afi_wlat [CFG_DRAM_WLAT_GROUP-1] == 1)
begin
if (int_do_rmw_correct)
begin
largest_rmw_correct_pipe_eq_afi_wlat_minus_1 <= 1'b1;
end
else
begin
largest_rmw_correct_pipe_eq_afi_wlat_minus_1 <= 1'b0;
end
if (int_do_rmw_partial)
begin
largest_rmw_partial_pipe_eq_afi_wlat_minus_1 <= 1'b1;
end
else
begin
largest_rmw_partial_pipe_eq_afi_wlat_minus_1 <= 1'b0;
end
if (int_do_rmw_correct) // we must disable int_cfg_output_regd when (afi_wlat < 2)
begin
largest_rmw_correct_pipe_eq_afi_wlat_minus_2 <= 1'b1;
end
else
begin
largest_rmw_correct_pipe_eq_afi_wlat_minus_2 <= 1'b0;
end
if (int_do_rmw_partial) // we must disable int_cfg_output_regd when (afi_wlat < 2)
begin
largest_rmw_partial_pipe_eq_afi_wlat_minus_2 <= 1'b1;
end
else
begin
largest_rmw_partial_pipe_eq_afi_wlat_minus_2 <= 1'b0;
end
end
else if (largest_afi_wlat [CFG_DRAM_WLAT_GROUP-1] == 2)
begin
if (rmw_correct_pipe[0])
begin
largest_rmw_correct_pipe_eq_afi_wlat_minus_1 <= 1'b1;
end
else
begin
largest_rmw_correct_pipe_eq_afi_wlat_minus_1 <= 1'b0;
end
if (rmw_partial_pipe[0])
begin
largest_rmw_partial_pipe_eq_afi_wlat_minus_1 <= 1'b1;
end
else
begin
largest_rmw_partial_pipe_eq_afi_wlat_minus_1 <= 1'b0;
end
if (int_do_rmw_correct)
begin
largest_rmw_correct_pipe_eq_afi_wlat_minus_2 <= 1'b1;
end
else
begin
largest_rmw_correct_pipe_eq_afi_wlat_minus_2 <= 1'b0;
end
if (int_do_rmw_partial)
begin
largest_rmw_partial_pipe_eq_afi_wlat_minus_2 <= 1'b1;
end
else
begin
largest_rmw_partial_pipe_eq_afi_wlat_minus_2 <= 1'b0;
end
end
else
begin
if (rmw_correct_pipe[largest_afi_wlat_minus_2])
begin
largest_rmw_correct_pipe_eq_afi_wlat_minus_1 <= 1'b1;
end
else
begin
largest_rmw_correct_pipe_eq_afi_wlat_minus_1 <= 1'b0;
end
if (rmw_partial_pipe[largest_afi_wlat_minus_2])
begin
largest_rmw_partial_pipe_eq_afi_wlat_minus_1 <= 1'b1;
end
else
begin
largest_rmw_partial_pipe_eq_afi_wlat_minus_1 <= 1'b0;
end
if (rmw_correct_pipe[largest_afi_wlat_minus_3])
begin
largest_rmw_correct_pipe_eq_afi_wlat_minus_2 <= 1'b1;
end
else
begin
largest_rmw_correct_pipe_eq_afi_wlat_minus_2 <= 1'b0;
end
if (rmw_partial_pipe[largest_afi_wlat_minus_3])
begin
largest_rmw_partial_pipe_eq_afi_wlat_minus_2 <= 1'b1;
end
else
begin
largest_rmw_partial_pipe_eq_afi_wlat_minus_2 <= 1'b0;
end
end
end
end
always @ (*)
begin
if (CFG_WDATA_REG || CFG_ECC_ENC_REG)
begin
largest_doing_write_pipe_eq_afi_wlat_minus_x = largest_doing_write_pipe_eq_afi_wlat_minus_2 ;
largest_rdwr_data_valid_pipe_eq_afi_wlat_minus_x = largest_rdwr_data_valid_pipe_eq_afi_wlat_minus_2;
largest_dataid_pipe_eq_afi_wlat_minus_x = largest_dataid_pipe_eq_afi_wlat_minus_2 ;
largest_dataid_vector_pipe_eq_afi_wlat_minus_x = largest_dataid_vector_pipe_eq_afi_wlat_minus_2 ;
largest_rmw_correct_pipe_eq_afi_wlat_minus_x = largest_rmw_correct_pipe_eq_afi_wlat_minus_2 ;
largest_rmw_partial_pipe_eq_afi_wlat_minus_x = largest_rmw_partial_pipe_eq_afi_wlat_minus_2 ;
end
else
begin
largest_doing_write_pipe_eq_afi_wlat_minus_x = largest_doing_write_pipe_eq_afi_wlat_minus_1 ;
largest_rdwr_data_valid_pipe_eq_afi_wlat_minus_x = largest_rdwr_data_valid_pipe_eq_afi_wlat_minus_1;
largest_dataid_pipe_eq_afi_wlat_minus_x = largest_dataid_pipe_eq_afi_wlat_minus_1 ;
largest_dataid_vector_pipe_eq_afi_wlat_minus_x = largest_dataid_vector_pipe_eq_afi_wlat_minus_1 ;
largest_rmw_correct_pipe_eq_afi_wlat_minus_x = largest_rmw_correct_pipe_eq_afi_wlat_minus_1 ;
largest_rmw_partial_pipe_eq_afi_wlat_minus_x = largest_rmw_partial_pipe_eq_afi_wlat_minus_1 ;
end
end
end
endgenerate
//*************************************************************************************************//
// afi_dqs_burst generation logic //
//*************************************************************************************************//
// high earlier than wdata_valid but ends the same
// for writes only, where dqs should toggle, use doing_write_pipe
always @(*)
begin
if (smallest_afi_wlat_eq_0)
begin
if (bg_doing_write || doing_write_pipe[0])
begin
int_dqs_burst = 1'b1;
end
else
begin
int_dqs_burst = 1'b0;
end
end
else
begin
if (smallest_doing_write_pipe_eq_afi_wlat_minus_1 || smallest_doing_write_pipe_eq_afi_wlat_minus_0)
begin
int_dqs_burst = 1'b1;
end
else
begin
int_dqs_burst = 1'b0;
end
end
end
// registered output
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_dqs_burst_r <= 1'b0;
end
else
begin
int_dqs_burst_r <= int_dqs_burst;
end
end
always @ (*)
begin
if (smallest_afi_wlat_eq_0)
begin
if (doing_write_pipe[0])
begin
int_dqs_burst_half_rate = 1'b1;
end
else
begin
int_dqs_burst_half_rate = 1'b0;
end
end
else
begin
if (smallest_doing_write_pipe_eq_afi_wlat_minus_0)
begin
int_dqs_burst_half_rate = 1'b1;
end
else
begin
int_dqs_burst_half_rate = 1'b0;
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_dqs_burst_half_rate_r <= 1'b0;
end
else
begin
int_dqs_burst_half_rate_r <= int_dqs_burst_half_rate;
end
end
generate
genvar K;
if (CFG_DWIDTH_RATIO == 2) // fullrate
begin
for (K = 0; K < CFG_MEM_IF_DQS_WIDTH; K = K + 1)
begin : C
assign afi_dqs_burst[K] = (cfg_output_regd_for_afi_output == 1) ? int_dqs_burst_r : int_dqs_burst;
end
end
else if (CFG_DWIDTH_RATIO == 4) // halfrate
begin
for (K = 0; K < CFG_MEM_IF_DQS_WIDTH; K = K + 1)
begin : C
assign afi_dqs_burst[K + CFG_MEM_IF_DQS_WIDTH] = (cfg_output_regd_for_afi_output == 1) ? int_dqs_burst_r : int_dqs_burst ;
assign afi_dqs_burst[K ] = (cfg_output_regd_for_afi_output == 1) ? int_dqs_burst_half_rate_r : int_dqs_burst_half_rate;
end
end
else if (CFG_DWIDTH_RATIO == 8) // quarterrate
begin
for (K = 0; K < CFG_MEM_IF_DQS_WIDTH; K = K + 1)
begin : C
assign afi_dqs_burst[K + CFG_MEM_IF_DQS_WIDTH * 3] = (cfg_output_regd_for_afi_output == 1) ? int_dqs_burst_r : int_dqs_burst ;
assign afi_dqs_burst[K + CFG_MEM_IF_DQS_WIDTH * 2] = (cfg_output_regd_for_afi_output == 1) ? int_dqs_burst_half_rate_r : int_dqs_burst_half_rate;
assign afi_dqs_burst[K + CFG_MEM_IF_DQS_WIDTH * 1] = (cfg_output_regd_for_afi_output == 1) ? int_dqs_burst_half_rate_r : int_dqs_burst_half_rate;
assign afi_dqs_burst[K ] = (cfg_output_regd_for_afi_output == 1) ? int_dqs_burst_half_rate_r : int_dqs_burst_half_rate;
end
end
endgenerate
//*************************************************************************************************//
// afi_wdata_valid generation logic //
//*************************************************************************************************//
always @(*)
begin
if (smallest_afi_wlat_eq_0)
begin
if (doing_write_pipe[0])
begin
int_wdata_valid = 1'b1;
end
else
begin
int_wdata_valid = 1'b0;
end
end
else
begin
if (smallest_doing_write_pipe_eq_afi_wlat_minus_0)
begin
int_wdata_valid = 1'b1;
end
else
begin
int_wdata_valid = 1'b0;
end
end
end
// registered output
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_wdata_valid_r <= 1'b0;
end
else
begin
int_wdata_valid_r <= int_wdata_valid;
end
end
generate
genvar L;
for (L = 0; L < CFG_MEM_IF_DQS_WIDTH*(CFG_DWIDTH_RATIO/2); L = L + 1)
begin : D
assign afi_wdata_valid[L] = (cfg_output_regd_for_afi_output) ? int_wdata_valid_r : int_wdata_valid;
end
endgenerate
//*************************************************************************************************//
// afi_wdata generation logic //
//*************************************************************************************************//
generate
genvar M;
for (M = 0;M < CFG_DRAM_WLAT_GROUP;M = M + 1) // generate wlat logic for each DQS group
begin : wlat_logic_per_dqs_group
//*************************************************************************************************//
// ecc_wdata_fifo_read //
//*************************************************************************************************//
// Indicate when to read from write data buffer
// based on burst_gen signals
always @(*)
begin
if (afi_wlat_eq_0 [M])
begin
if (bg_rdwr_data_valid && bg_doing_write)
begin
int_ecc_wdata_fifo_read [M] = 1'b1;
end
else
begin
int_ecc_wdata_fifo_read [M] = 1'b0;
end
end
else
begin
if (rdwr_data_valid_pipe_eq_afi_wlat_minus_x [M] && doing_write_pipe_eq_afi_wlat_minus_x [M])
begin
int_ecc_wdata_fifo_read [M] = 1'b1;
end
else
begin
int_ecc_wdata_fifo_read [M] = 1'b0;
end
end
end
// Registered output
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_ecc_wdata_fifo_read_r [M] <= 1'b0;
end
else
begin
int_ecc_wdata_fifo_read_r [M] <= int_ecc_wdata_fifo_read [M];
end
end
// Determine write data buffer read signal based on output_regd info
// output_regd info is derived based on afi_wlat value
assign ecc_wdata_fifo_read [M] = (cfg_output_regd_for_wdata_path) ? int_ecc_wdata_fifo_read_r [M] : int_ecc_wdata_fifo_read [M];
// Registered output
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
ecc_wdata_fifo_read_r [M] <= 1'b0;
end
else
begin
ecc_wdata_fifo_read_r [M] <= ecc_wdata_fifo_read [M];
end
end
//*************************************************************************************************//
// ecc_wdata_fifo_dataid/dataid_vector //
//*************************************************************************************************//
// Dataid generation to write buffer, to indicate which wdata should be passed to AFI
always @(*)
begin
if (afi_wlat_eq_0 [M])
begin
if (bg_rdwr_data_valid && bg_doing_write)
begin
int_ecc_wdata_fifo_dataid [M] = dataid;
int_ecc_wdata_fifo_dataid_vector [M] = dataid_vector;
end
else
begin
int_ecc_wdata_fifo_dataid [M] = {(CFG_DATA_ID_WIDTH){1'b0}};
int_ecc_wdata_fifo_dataid_vector [M] = {(CFG_DATAID_ARRAY_DEPTH){1'b0}};
end
end
else
begin
if (rdwr_data_valid_pipe_eq_afi_wlat_minus_x [M] && doing_write_pipe_eq_afi_wlat_minus_x [M])
begin
int_ecc_wdata_fifo_dataid [M] = dataid_pipe_eq_afi_wlat_minus_x [M];
int_ecc_wdata_fifo_dataid_vector [M] = dataid_vector_pipe_eq_afi_wlat_minus_x [M];
end
else
begin
int_ecc_wdata_fifo_dataid [M] = {(CFG_DATA_ID_WIDTH){1'b0}};
int_ecc_wdata_fifo_dataid_vector [M] = {(CFG_DATAID_ARRAY_DEPTH){1'b0}};
end
end
end
// Registered output
always @ (posedge ctl_clk, negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
int_ecc_wdata_fifo_dataid_r [M] <= 0;
int_ecc_wdata_fifo_dataid_vector_r [M] <= 0;
end
else
begin
int_ecc_wdata_fifo_dataid_r [M] <= int_ecc_wdata_fifo_dataid [M];
int_ecc_wdata_fifo_dataid_vector_r [M] <= int_ecc_wdata_fifo_dataid_vector [M];
end
end
assign ecc_wdata_fifo_dataid [(M + 1) * CFG_DATA_ID_WIDTH - 1 : M * CFG_DATA_ID_WIDTH ] = (cfg_output_regd_for_wdata_path) ? int_ecc_wdata_fifo_dataid_r [M] : int_ecc_wdata_fifo_dataid [M];
assign ecc_wdata_fifo_dataid_vector [(M + 1) * CFG_DATAID_ARRAY_DEPTH - 1 : M * CFG_DATAID_ARRAY_DEPTH] = (cfg_output_regd_for_wdata_path) ? int_ecc_wdata_fifo_dataid_vector_r [M] : int_ecc_wdata_fifo_dataid_vector [M];
//*************************************************************************************************//
// ecc_wdata_fifo_rmw_correct/partial //
//*************************************************************************************************//
// Read modify write info logic
always @(*)
begin
if (afi_wlat_eq_0 [M])
begin
if (bg_rdwr_data_valid && bg_doing_write)
begin
int_ecc_wdata_fifo_rmw_correct [M] = int_do_rmw_correct;
int_ecc_wdata_fifo_rmw_partial [M] = int_do_rmw_partial;
end
else
begin
int_ecc_wdata_fifo_rmw_correct [M] = 1'b0;
int_ecc_wdata_fifo_rmw_partial [M] = 1'b0;
end
end
else
begin
if (rdwr_data_valid_pipe_eq_afi_wlat_minus_x [M] && doing_write_pipe_eq_afi_wlat_minus_x [M])
begin
int_ecc_wdata_fifo_rmw_correct [M] = rmw_correct_pipe_eq_afi_wlat_minus_x [M];
int_ecc_wdata_fifo_rmw_partial [M] = rmw_partial_pipe_eq_afi_wlat_minus_x [M];
end
else
begin
int_ecc_wdata_fifo_rmw_correct [M] = 1'b0;
int_ecc_wdata_fifo_rmw_partial [M] = 1'b0;
end
end
end
always @ (posedge ctl_clk, negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
int_ecc_wdata_fifo_rmw_correct_r [M] <= 0;
int_ecc_wdata_fifo_rmw_partial_r [M] <= 0;
end
else
begin
int_ecc_wdata_fifo_rmw_correct_r [M] <= int_ecc_wdata_fifo_rmw_correct [M];
int_ecc_wdata_fifo_rmw_partial_r [M] <= int_ecc_wdata_fifo_rmw_partial [M];
end
end
assign ecc_wdata_fifo_rmw_correct [M] = (cfg_output_regd_for_wdata_path) ? int_ecc_wdata_fifo_rmw_correct_r [M] : int_ecc_wdata_fifo_rmw_correct [M];
assign ecc_wdata_fifo_rmw_partial [M] = (cfg_output_regd_for_wdata_path) ? int_ecc_wdata_fifo_rmw_partial_r [M] : int_ecc_wdata_fifo_rmw_partial [M];
end
endgenerate
generate
if (CFG_DRAM_WLAT_GROUP == 1) // only one group of afi_wlat
begin
assign ecc_wdata_fifo_read_first = ecc_wdata_fifo_read;
assign ecc_wdata_fifo_dataid_first = ecc_wdata_fifo_dataid;
assign ecc_wdata_fifo_dataid_vector_first = ecc_wdata_fifo_dataid_vector;
assign ecc_wdata_fifo_rmw_correct_first = ecc_wdata_fifo_rmw_correct;
assign ecc_wdata_fifo_rmw_partial_first = ecc_wdata_fifo_rmw_partial;
assign ecc_wdata_fifo_read_last = ecc_wdata_fifo_read;
assign ecc_wdata_fifo_dataid_last = ecc_wdata_fifo_dataid;
assign ecc_wdata_fifo_dataid_vector_last = ecc_wdata_fifo_dataid_vector;
assign ecc_wdata_fifo_rmw_correct_last = ecc_wdata_fifo_rmw_correct;
assign ecc_wdata_fifo_rmw_partial_last = ecc_wdata_fifo_rmw_partial;
end
else
begin
reg ecc_wdata_fifo_read_first_r;
reg int_ecc_wdata_fifo_read_first;
reg int_ecc_wdata_fifo_read_first_r;
reg [CFG_DATA_ID_WIDTH-1:0] int_ecc_wdata_fifo_dataid_first;
reg [CFG_DATA_ID_WIDTH-1:0] int_ecc_wdata_fifo_dataid_first_r;
reg [CFG_DATAID_ARRAY_DEPTH-1:0] int_ecc_wdata_fifo_dataid_vector_first;
reg [CFG_DATAID_ARRAY_DEPTH-1:0] int_ecc_wdata_fifo_dataid_vector_first_r;
reg int_ecc_wdata_fifo_rmw_correct_first;
reg int_ecc_wdata_fifo_rmw_correct_first_r;
reg int_ecc_wdata_fifo_rmw_partial_first;
reg int_ecc_wdata_fifo_rmw_partial_first_r;
reg ecc_wdata_fifo_read_last_r;
reg int_ecc_wdata_fifo_read_last;
reg int_ecc_wdata_fifo_read_last_r;
reg [CFG_DATA_ID_WIDTH-1:0] int_ecc_wdata_fifo_dataid_last;
reg [CFG_DATA_ID_WIDTH-1:0] int_ecc_wdata_fifo_dataid_last_r;
reg [CFG_DATAID_ARRAY_DEPTH-1:0] int_ecc_wdata_fifo_dataid_vector_last;
reg [CFG_DATAID_ARRAY_DEPTH-1:0] int_ecc_wdata_fifo_dataid_vector_last_r;
reg int_ecc_wdata_fifo_rmw_correct_last;
reg int_ecc_wdata_fifo_rmw_correct_last_r;
reg int_ecc_wdata_fifo_rmw_partial_last;
reg int_ecc_wdata_fifo_rmw_partial_last_r;
// Determine first ecc_wdata_fifo_* info
//*************************************************************************************************//
// ecc_wdata_fifo_read //
//*************************************************************************************************//
// Indicate when to read from write data buffer
// based on burst_gen signals
always @(*)
begin
if (smallest_afi_wlat_eq_0)
begin
if (bg_rdwr_data_valid && bg_doing_write)
begin
int_ecc_wdata_fifo_read_first = 1'b1;
end
else
begin
int_ecc_wdata_fifo_read_first = 1'b0;
end
end
else
begin
if (smallest_rdwr_data_valid_pipe_eq_afi_wlat_minus_x && smallest_doing_write_pipe_eq_afi_wlat_minus_x)
begin
int_ecc_wdata_fifo_read_first = 1'b1;
end
else
begin
int_ecc_wdata_fifo_read_first = 1'b0;
end
end
end
// Registered output
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_ecc_wdata_fifo_read_first_r <= 1'b0;
end
else
begin
int_ecc_wdata_fifo_read_first_r <= int_ecc_wdata_fifo_read_first;
end
end
// Determine write data buffer read signal based on output_regd info
// output_regd info is derived based on afi_wlat value
assign ecc_wdata_fifo_read_first = (cfg_output_regd_for_wdata_path) ? int_ecc_wdata_fifo_read_first_r : int_ecc_wdata_fifo_read_first;
// Registered output
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
ecc_wdata_fifo_read_first_r <= 1'b0;
end
else
begin
ecc_wdata_fifo_read_first_r <= ecc_wdata_fifo_read_first;
end
end
//*************************************************************************************************//
// ecc_wdata_fifo_dataid/dataid_vector //
//*************************************************************************************************//
// Dataid generation to write buffer, to indicate which wdata should be passed to AFI
always @(*)
begin
if (smallest_afi_wlat_eq_0)
begin
if (bg_rdwr_data_valid && bg_doing_write)
begin
int_ecc_wdata_fifo_dataid_first = dataid;
int_ecc_wdata_fifo_dataid_vector_first = dataid_vector;
end
else
begin
int_ecc_wdata_fifo_dataid_first = {(CFG_DATA_ID_WIDTH){1'b0}};
int_ecc_wdata_fifo_dataid_vector_first = {(CFG_DATAID_ARRAY_DEPTH){1'b0}};
end
end
else
begin
if (smallest_rdwr_data_valid_pipe_eq_afi_wlat_minus_x && smallest_doing_write_pipe_eq_afi_wlat_minus_x)
begin
int_ecc_wdata_fifo_dataid_first = smallest_dataid_pipe_eq_afi_wlat_minus_x ;
int_ecc_wdata_fifo_dataid_vector_first = smallest_dataid_vector_pipe_eq_afi_wlat_minus_x;
end
else
begin
int_ecc_wdata_fifo_dataid_first = {(CFG_DATA_ID_WIDTH){1'b0}};
int_ecc_wdata_fifo_dataid_vector_first = {(CFG_DATAID_ARRAY_DEPTH){1'b0}};
end
end
end
// Registered output
always @ (posedge ctl_clk, negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
int_ecc_wdata_fifo_dataid_first_r <= 0;
int_ecc_wdata_fifo_dataid_vector_first_r <= 0;
end
else
begin
int_ecc_wdata_fifo_dataid_first_r <= int_ecc_wdata_fifo_dataid_first ;
int_ecc_wdata_fifo_dataid_vector_first_r <= int_ecc_wdata_fifo_dataid_vector_first;
end
end
assign ecc_wdata_fifo_dataid_first = (cfg_output_regd_for_wdata_path) ? int_ecc_wdata_fifo_dataid_first_r : int_ecc_wdata_fifo_dataid_first ;
assign ecc_wdata_fifo_dataid_vector_first = (cfg_output_regd_for_wdata_path) ? int_ecc_wdata_fifo_dataid_vector_first_r : int_ecc_wdata_fifo_dataid_vector_first;
//*************************************************************************************************//
// ecc_wdata_fifo_rmw_correct/partial //
//*************************************************************************************************//
// Read modify write info logic
always @(*)
begin
if (smallest_afi_wlat_eq_0)
begin
if (bg_rdwr_data_valid && bg_doing_write)
begin
int_ecc_wdata_fifo_rmw_correct_first = int_do_rmw_correct;
int_ecc_wdata_fifo_rmw_partial_first = int_do_rmw_partial;
end
else
begin
int_ecc_wdata_fifo_rmw_correct_first = 1'b0;
int_ecc_wdata_fifo_rmw_partial_first = 1'b0;
end
end
else
begin
if (smallest_rdwr_data_valid_pipe_eq_afi_wlat_minus_x && smallest_doing_write_pipe_eq_afi_wlat_minus_x)
begin
int_ecc_wdata_fifo_rmw_correct_first = smallest_rmw_correct_pipe_eq_afi_wlat_minus_x;
int_ecc_wdata_fifo_rmw_partial_first = smallest_rmw_partial_pipe_eq_afi_wlat_minus_x;
end
else
begin
int_ecc_wdata_fifo_rmw_correct_first = 1'b0;
int_ecc_wdata_fifo_rmw_partial_first = 1'b0;
end
end
end
always @ (posedge ctl_clk, negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
int_ecc_wdata_fifo_rmw_correct_first_r <= 0;
int_ecc_wdata_fifo_rmw_partial_first_r <= 0;
end
else
begin
int_ecc_wdata_fifo_rmw_correct_first_r <= int_ecc_wdata_fifo_rmw_correct_first;
int_ecc_wdata_fifo_rmw_partial_first_r <= int_ecc_wdata_fifo_rmw_partial_first;
end
end
assign ecc_wdata_fifo_rmw_correct_first = (cfg_output_regd_for_wdata_path) ? int_ecc_wdata_fifo_rmw_correct_first_r : int_ecc_wdata_fifo_rmw_correct_first;
assign ecc_wdata_fifo_rmw_partial_first = (cfg_output_regd_for_wdata_path) ? int_ecc_wdata_fifo_rmw_partial_first_r : int_ecc_wdata_fifo_rmw_partial_first;
// Determine last ecc_wdata_fifo_* info
//*************************************************************************************************//
// ecc_wdata_fifo_read //
//*************************************************************************************************//
// Indicate when to read from write data buffer
// based on burst_gen signals
always @(*)
begin
if (largest_afi_wlat_eq_0)
begin
if (bg_rdwr_data_valid && bg_doing_write)
begin
int_ecc_wdata_fifo_read_last = 1'b1;
end
else
begin
int_ecc_wdata_fifo_read_last = 1'b0;
end
end
else
begin
if (largest_rdwr_data_valid_pipe_eq_afi_wlat_minus_x && largest_doing_write_pipe_eq_afi_wlat_minus_x)
begin
int_ecc_wdata_fifo_read_last = 1'b1;
end
else
begin
int_ecc_wdata_fifo_read_last = 1'b0;
end
end
end
// Registered output
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_ecc_wdata_fifo_read_last_r <= 1'b0;
end
else
begin
int_ecc_wdata_fifo_read_last_r <= int_ecc_wdata_fifo_read_last;
end
end
// Determine write data buffer read signal based on output_regd info
// output_regd info is derived based on afi_wlat value
assign ecc_wdata_fifo_read_last = (cfg_output_regd_for_wdata_path) ? int_ecc_wdata_fifo_read_last_r : int_ecc_wdata_fifo_read_last;
// Registered output
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
ecc_wdata_fifo_read_last_r <= 1'b0;
end
else
begin
ecc_wdata_fifo_read_last_r <= ecc_wdata_fifo_read_last;
end
end
//*************************************************************************************************//
// ecc_wdata_fifo_dataid/dataid_vector //
//*************************************************************************************************//
// Dataid generation to write buffer, to indicate which wdata should be passed to AFI
always @(*)
begin
if (largest_afi_wlat_eq_0)
begin
if (bg_rdwr_data_valid && bg_doing_write)
begin
int_ecc_wdata_fifo_dataid_last = dataid;
int_ecc_wdata_fifo_dataid_vector_last = dataid_vector;
end
else
begin
int_ecc_wdata_fifo_dataid_last = {(CFG_DATA_ID_WIDTH){1'b0}};
int_ecc_wdata_fifo_dataid_vector_last = {(CFG_DATAID_ARRAY_DEPTH){1'b0}};
end
end
else
begin
if (largest_rdwr_data_valid_pipe_eq_afi_wlat_minus_x && largest_doing_write_pipe_eq_afi_wlat_minus_x)
begin
int_ecc_wdata_fifo_dataid_last = largest_dataid_pipe_eq_afi_wlat_minus_x ;
int_ecc_wdata_fifo_dataid_vector_last = largest_dataid_vector_pipe_eq_afi_wlat_minus_x;
end
else
begin
int_ecc_wdata_fifo_dataid_last = {(CFG_DATA_ID_WIDTH){1'b0}};
int_ecc_wdata_fifo_dataid_vector_last = {(CFG_DATAID_ARRAY_DEPTH){1'b0}};
end
end
end
// Registered output
always @ (posedge ctl_clk, negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
int_ecc_wdata_fifo_dataid_last_r <= 0;
int_ecc_wdata_fifo_dataid_vector_last_r <= 0;
end
else
begin
int_ecc_wdata_fifo_dataid_last_r <= int_ecc_wdata_fifo_dataid_last ;
int_ecc_wdata_fifo_dataid_vector_last_r <= int_ecc_wdata_fifo_dataid_vector_last;
end
end
assign ecc_wdata_fifo_dataid_last = (cfg_output_regd_for_wdata_path) ? int_ecc_wdata_fifo_dataid_last_r : int_ecc_wdata_fifo_dataid_last ;
assign ecc_wdata_fifo_dataid_vector_last = (cfg_output_regd_for_wdata_path) ? int_ecc_wdata_fifo_dataid_vector_last_r : int_ecc_wdata_fifo_dataid_vector_last;
//*************************************************************************************************//
// ecc_wdata_fifo_rmw_correct/partial //
//*************************************************************************************************//
// Read modify write info logic
always @(*)
begin
if (largest_afi_wlat_eq_0)
begin
if (bg_rdwr_data_valid && bg_doing_write)
begin
int_ecc_wdata_fifo_rmw_correct_last = int_do_rmw_correct;
int_ecc_wdata_fifo_rmw_partial_last = int_do_rmw_partial;
end
else
begin
int_ecc_wdata_fifo_rmw_correct_last = 1'b0;
int_ecc_wdata_fifo_rmw_partial_last = 1'b0;
end
end
else
begin
if (largest_rdwr_data_valid_pipe_eq_afi_wlat_minus_x && largest_doing_write_pipe_eq_afi_wlat_minus_x)
begin
int_ecc_wdata_fifo_rmw_correct_last = largest_rmw_correct_pipe_eq_afi_wlat_minus_x;
int_ecc_wdata_fifo_rmw_partial_last = largest_rmw_partial_pipe_eq_afi_wlat_minus_x;
end
else
begin
int_ecc_wdata_fifo_rmw_correct_last = 1'b0;
int_ecc_wdata_fifo_rmw_partial_last = 1'b0;
end
end
end
always @ (posedge ctl_clk, negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
int_ecc_wdata_fifo_rmw_correct_last_r <= 0;
int_ecc_wdata_fifo_rmw_partial_last_r <= 0;
end
else
begin
int_ecc_wdata_fifo_rmw_correct_last_r <= int_ecc_wdata_fifo_rmw_correct_last;
int_ecc_wdata_fifo_rmw_partial_last_r <= int_ecc_wdata_fifo_rmw_partial_last;
end
end
assign ecc_wdata_fifo_rmw_correct_last = (cfg_output_regd_for_wdata_path) ? int_ecc_wdata_fifo_rmw_correct_last_r : int_ecc_wdata_fifo_rmw_correct_last;
assign ecc_wdata_fifo_rmw_partial_last = (cfg_output_regd_for_wdata_path) ? int_ecc_wdata_fifo_rmw_partial_last_r : int_ecc_wdata_fifo_rmw_partial_last;
end
endgenerate
// No data manipulation on wdata
assign afi_wdata = ecc_wdata;
//*************************************************************************************************//
// afi_dm generation logic //
//*************************************************************************************************//
//Why do we need ecc_dm and rdwr_data_valid to determine DM
// ecc_dm will not get updated till we read another data from wrfifo, so we need to drive DMs based on rdwr_data_valid
//Output registered information already backed in ecc_wdata_fifo_read
// data valid one clock cycle after read
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_real_wdata_valid <= 1'b0;
end
else
begin
if (CFG_WDATA_REG || CFG_ECC_ENC_REG)
begin
int_real_wdata_valid <= ecc_wdata_fifo_read_r;
end
else
begin
int_real_wdata_valid <= ecc_wdata_fifo_read;
end
end
end
generate
genvar J;
for (J = 0; J < CFG_MEM_IF_DM_WIDTH*CFG_DWIDTH_RATIO; J = J + 1)
begin : F
assign afi_dm[J] = ~ecc_dm[J] | ~int_real_wdata_valid;
end
endgenerate
endmodule
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
//altera message_off 10230
`include "alt_mem_ddrx_define.iv"
`timescale 1 ps / 1 ps
module alt_mem_ddrx_sideband
# (parameter
// parameters
CFG_PORT_WIDTH_TYPE = 3,
CFG_DWIDTH_RATIO = 2, //2-FR,4-HR,8-QR
CFG_REG_GRANT = 1,
CFG_CTL_TBP_NUM = 4,
CFG_MEM_IF_CS_WIDTH = 1,
CFG_MEM_IF_CHIP = 1, // one hot
CFG_MEM_IF_BA_WIDTH = 3,
CFG_PORT_WIDTH_TCL = 4,
CFG_MEM_IF_CLK_PAIR_COUNT = 2,
CFG_RANK_TIMER_OUTPUT_REG = 0,
T_PARAM_ARF_TO_VALID_WIDTH = 10,
T_PARAM_ARF_PERIOD_WIDTH = 13,
T_PARAM_PCH_ALL_TO_VALID_WIDTH = 10,
T_PARAM_SRF_TO_VALID_WIDTH = 10,
T_PARAM_SRF_TO_ZQ_CAL_WIDTH = 10,
T_PARAM_PDN_TO_VALID_WIDTH = 6,
BANK_TIMER_COUNTER_OFFSET = 2, //used to be 4
T_PARAM_PDN_PERIOD_WIDTH = 16,// temporary
T_PARAM_POWER_SAVING_EXIT_WIDTH = 6
)
(
ctl_clk,
ctl_reset_n,
// local interface
rfsh_req,
rfsh_chip,
rfsh_ack,
self_rfsh_req,
self_rfsh_chip,
self_rfsh_ack,
deep_powerdn_req,
deep_powerdn_chip,
deep_powerdn_ack,
power_down_ack,
// sideband output
stall_row_arbiter,
stall_col_arbiter,
stall_chip,
sb_do_precharge_all,
sb_do_refresh,
sb_do_self_refresh,
sb_do_power_down,
sb_do_deep_pdown,
sb_do_zq_cal,
sb_tbp_precharge_all,
// PHY interface
ctl_mem_clk_disable,
ctl_init_req,
ctl_cal_success,
// tbp & cmd gen
cmd_gen_chipsel,
tbp_chipsel,
tbp_load,
// timing
t_param_arf_to_valid,
t_param_arf_period,
t_param_pch_all_to_valid,
t_param_srf_to_valid,
t_param_srf_to_zq_cal,
t_param_pdn_to_valid,
t_param_pdn_period,
t_param_power_saving_exit,
// block status
tbp_empty,
tbp_bank_active,
tbp_timer_ready,
row_grant,
col_grant,
// dqs tracking
afi_ctl_refresh_done,
afi_seq_busy,
afi_ctl_long_idle,
// config ports
cfg_enable_dqs_tracking,
cfg_user_rfsh,
cfg_type,
cfg_tcl,
cfg_regdimm_enable
);
// states for our DQS bus monitor state machine
localparam IDLE = 32'h49444C45;
localparam ARF = 32'h20415246;
localparam PDN = 32'h2050444E;
localparam SRF = 32'h20535246;
localparam INIT = 32'h696e6974;
localparam PCHALL = 32'h70636861;
localparam REFRESH = 32'h72667368;
localparam PDOWN = 32'h7064776e;
localparam SELFRFSH = 32'h736c7266;
localparam DEEPPDN = 32'h64656570;
localparam ZQCAL = 32'h7a63616c;
localparam DQSTRK = 32'h6471746b;
localparam DQSLONG = 32'h64716c6e;
localparam POWER_SAVING_COUNTER_WIDTH = T_PARAM_SRF_TO_VALID_WIDTH;
localparam POWER_SAVING_EXIT_COUNTER_WIDTH = T_PARAM_POWER_SAVING_EXIT_WIDTH;
localparam ARF_COUNTER_WIDTH = T_PARAM_ARF_PERIOD_WIDTH;
localparam PDN_COUNTER_WIDTH = T_PARAM_PDN_PERIOD_WIDTH;
localparam integer CFG_MEM_IF_BA_WIDTH_SQRD = 2**CFG_MEM_IF_BA_WIDTH;
localparam integer CFG_PORT_WIDTH_TCL_SQRD = 2**CFG_PORT_WIDTH_TCL;
input ctl_clk;
input ctl_reset_n;
input rfsh_req;
input [CFG_MEM_IF_CHIP-1:0] rfsh_chip;
output rfsh_ack;
input self_rfsh_req;
input [CFG_MEM_IF_CHIP-1:0] self_rfsh_chip;
output self_rfsh_ack;
input deep_powerdn_req;
input [CFG_MEM_IF_CHIP-1:0] deep_powerdn_chip;
output deep_powerdn_ack;
output power_down_ack;
output stall_row_arbiter;
output stall_col_arbiter;
output [CFG_MEM_IF_CHIP-1:0] stall_chip;
output [CFG_MEM_IF_CHIP-1:0] sb_do_precharge_all;
output [CFG_MEM_IF_CHIP-1:0] sb_do_refresh;
output [CFG_MEM_IF_CHIP-1:0] sb_do_self_refresh;
output [CFG_MEM_IF_CHIP-1:0] sb_do_power_down;
output [CFG_MEM_IF_CHIP-1:0] sb_do_deep_pdown;
output [CFG_MEM_IF_CHIP-1:0] sb_do_zq_cal;
output [CFG_CTL_TBP_NUM-1:0] sb_tbp_precharge_all;
output [CFG_MEM_IF_CLK_PAIR_COUNT-1:0] ctl_mem_clk_disable;
output ctl_init_req;
input ctl_cal_success;
input [CFG_MEM_IF_CS_WIDTH-1:0] cmd_gen_chipsel;
input [(CFG_CTL_TBP_NUM*CFG_MEM_IF_CS_WIDTH)-1:0] tbp_chipsel;
input [CFG_CTL_TBP_NUM-1:0] tbp_load;
input [T_PARAM_ARF_TO_VALID_WIDTH - 1 : 0] t_param_arf_to_valid;
input [T_PARAM_ARF_PERIOD_WIDTH - 1 : 0] t_param_arf_period;
input [T_PARAM_PCH_ALL_TO_VALID_WIDTH - 1 : 0] t_param_pch_all_to_valid;
input [T_PARAM_SRF_TO_VALID_WIDTH - 1 : 0] t_param_srf_to_valid;
input [T_PARAM_SRF_TO_ZQ_CAL_WIDTH - 1 : 0] t_param_srf_to_zq_cal;
input [T_PARAM_PDN_TO_VALID_WIDTH - 1 : 0] t_param_pdn_to_valid;
input [T_PARAM_PDN_PERIOD_WIDTH - 1 : 0] t_param_pdn_period;
input [T_PARAM_POWER_SAVING_EXIT_WIDTH - 1 : 0] t_param_power_saving_exit;
input tbp_empty;
input [CFG_MEM_IF_CHIP-1:0] tbp_bank_active;
input [CFG_MEM_IF_CHIP-1:0] tbp_timer_ready;
input row_grant;
input col_grant;
output [CFG_MEM_IF_CHIP-1:0] afi_ctl_refresh_done;
input [CFG_MEM_IF_CHIP-1:0] afi_seq_busy;
output [CFG_MEM_IF_CHIP-1:0] afi_ctl_long_idle;
input cfg_enable_dqs_tracking;
input cfg_user_rfsh;
input [CFG_PORT_WIDTH_TYPE - 1 : 0] cfg_type;
input [CFG_PORT_WIDTH_TCL - 1 : 0] cfg_tcl;
input cfg_regdimm_enable;
// end of port declaration
wire self_rfsh_ack;
wire deep_powerdn_ack;
wire power_down_ack;
wire [CFG_MEM_IF_CLK_PAIR_COUNT-1:0] ctl_mem_clk_disable;
wire ctl_init_req;
reg [CFG_MEM_IF_CHIP-1:0] sb_do_precharge_all;
reg [CFG_MEM_IF_CHIP-1:0] sb_do_refresh;
reg [CFG_MEM_IF_CHIP-1:0] sb_do_self_refresh;
reg [CFG_MEM_IF_CHIP-1:0] sb_do_power_down;
reg [CFG_MEM_IF_CHIP-1:0] sb_do_deep_pdown;
reg [CFG_MEM_IF_CHIP-1:0] sb_do_zq_cal;
reg [CFG_CTL_TBP_NUM-1:0] sb_tbp_precharge_all;
reg [CFG_MEM_IF_CHIP-1:0] do_refresh;
reg [CFG_MEM_IF_CHIP-1:0] do_power_down;
reg [CFG_MEM_IF_CHIP-1:0] do_deep_pdown;
reg [CFG_MEM_IF_CHIP-1:0] do_self_rfsh;
reg [CFG_MEM_IF_CHIP-1:0] do_self_rfsh_r;
reg [CFG_MEM_IF_CHIP-1:0] do_precharge_all;
reg [CFG_MEM_IF_CHIP-1:0] do_zqcal;
reg [CFG_MEM_IF_CHIP-1:0] stall_chip;
reg [CFG_MEM_IF_CHIP-1:0] int_stall_chip;
reg [CFG_MEM_IF_CHIP-1:0] int_stall_chip_combi;
reg [CFG_MEM_IF_CHIP-1:0] stall_arbiter;
reg [CFG_MEM_IF_CHIP-1:0] afi_ctl_refresh_done;
reg [CFG_MEM_IF_CHIP-1:0] afi_ctl_long_idle;
reg [CFG_MEM_IF_CHIP-1:0] dqstrk_exit;
reg [CFG_MEM_IF_CHIP-1:0] dqslong_exit;
reg [CFG_MEM_IF_CHIP-1:0] doing_zqcal;
reg [CFG_MEM_IF_CHIP-1:0] refresh_chip_req;
reg [CFG_MEM_IF_CHIP-1:0] self_refresh_chip_req;
reg self_rfsh_req_r;
reg [CFG_MEM_IF_CHIP-1:0] deep_pdown_chip_req;
reg [CFG_MEM_IF_CHIP-1:0] power_down_chip_req;
wire [CFG_MEM_IF_CHIP-1:0] power_down_chip_req_combi;
wire [CFG_MEM_IF_CHIP-1:0] all_banks_closed;
wire [CFG_MEM_IF_CHIP-1:0] tcom_not_running;
reg [CFG_PORT_WIDTH_TCL_SQRD-1:0] tcom_not_running_pipe [CFG_MEM_IF_CHIP-1:0];
reg [CFG_MEM_IF_CHIP-1:0] can_refresh;
reg [CFG_MEM_IF_CHIP-1:0] can_self_rfsh;
reg [CFG_MEM_IF_CHIP-1:0] can_deep_pdown;
reg [CFG_MEM_IF_CHIP-1:0] can_power_down;
reg [CFG_MEM_IF_CHIP-1:0] can_exit_power_saving_mode;
reg [CFG_MEM_IF_CHIP-1:0] cs_refresh_req;
wire grant;
wire [CFG_MEM_IF_CHIP-1:0] cs_zq_cal_req;
wire [CFG_MEM_IF_CHIP-1:0] power_saving_enter_ready;
wire [CFG_MEM_IF_CHIP-1:0] power_saving_exit_ready;
reg [PDN_COUNTER_WIDTH - 1 : 0] power_down_cnt;
reg no_command_r1;
reg [CFG_MEM_IF_CHIP-1:0] afi_seq_busy_r; // synchronizer
reg [CFG_MEM_IF_CHIP-1:0] afi_seq_busy_r2; // synchronizer
//new! to avoid contention
reg [CFG_MEM_IF_CHIP-1:0] do_refresh_req;
reg refresh_req_ack;
reg dummy_do_refresh;
reg dummy_do_refresh_r;
reg do_refresh_r;
reg [CFG_MEM_IF_CHIP-1:0] do_self_rfsh_req;
reg self_rfsh_req_ack;
reg dummy_do_self_rfsh;
reg [CFG_MEM_IF_CHIP-1:0] do_zqcal_req;
reg zqcal_req_ack;
reg dummy_do_zqcal;
reg [CFG_MEM_IF_CHIP-1:0] do_pch_all_req;
reg pch_all_req_ack;
reg dummy_do_pch_all;
integer i;
assign ctl_mem_clk_disable = {CFG_MEM_IF_CLK_PAIR_COUNT{1'b0}};
//generate *_chip_ok signals by checking can_*[chip], only when for_chip[chip] is 1
generate
genvar chip;
for (chip = 0; chip < CFG_MEM_IF_CHIP; chip = chip + 1)
begin : gen_chip_ok
// check can_* only for chips that we'd like to precharge_all to, ^~ is XNOR
assign tcom_not_running[chip] = tbp_timer_ready[chip];
assign all_banks_closed[chip] = ~tbp_bank_active[chip];
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
tcom_not_running_pipe[chip] <= 0;
end
else
begin
if (!tcom_not_running[chip])
tcom_not_running_pipe[chip] <= 0;
else
tcom_not_running_pipe[chip] <= {tcom_not_running_pipe[chip][CFG_PORT_WIDTH_TCL_SQRD -2 :0],tcom_not_running[chip]};
end
end
end
endgenerate
assign rfsh_ack = (!(cfg_regdimm_enable && cfg_type == `MMR_TYPE_DDR3 && CFG_MEM_IF_CHIP != 1)) ? |do_refresh : ((|do_refresh | do_refresh_r) & refresh_req_ack);
assign self_rfsh_ack = |do_self_rfsh;
assign deep_powerdn_ack = |do_deep_pdown;
assign power_down_ack = |do_power_down;
// Register sideband signals when CFG_REG_GRANT is '1'
// to prevent sideband request going out on the same cycle as tbp request
generate
begin
genvar j;
if (CFG_REG_GRANT == 1)
begin
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
sb_do_precharge_all <= 0;
sb_do_refresh <= 0;
sb_do_self_refresh <= 0;
sb_do_power_down <= 0;
sb_do_deep_pdown <= 0;
sb_do_zq_cal <= 0;
end
else
begin
sb_do_precharge_all <= do_precharge_all;
sb_do_refresh <= do_refresh;
sb_do_self_refresh <= do_self_rfsh;
sb_do_power_down <= do_power_down;
sb_do_deep_pdown <= do_deep_pdown;
sb_do_zq_cal <= do_zqcal;
end
end
for (j = 0;j < CFG_CTL_TBP_NUM;j = j + 1)
begin : tbp_loop_1
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
sb_tbp_precharge_all [j] <= 1'b0;
end
else
begin
if (tbp_load[j])
begin
sb_tbp_precharge_all [j] <= do_precharge_all [cmd_gen_chipsel];
end
else
begin
sb_tbp_precharge_all [j] <= do_precharge_all [tbp_chipsel [(j + 1) * CFG_MEM_IF_CS_WIDTH - 1 : j * CFG_MEM_IF_CS_WIDTH]];
end
end
end
end
end
else
begin
always @ (*)
begin
sb_do_precharge_all = do_precharge_all;
sb_do_refresh = do_refresh;
sb_do_self_refresh = do_self_rfsh;
sb_do_power_down = do_power_down;
sb_do_deep_pdown = do_deep_pdown;
sb_do_zq_cal = do_zqcal;
end
for (j = 0;j < CFG_CTL_TBP_NUM;j = j + 1)
begin : tbp_loop_2
always @ (*)
begin
sb_tbp_precharge_all [j] = do_precharge_all [tbp_chipsel [(j + 1) * CFG_MEM_IF_CS_WIDTH - 1 : j * CFG_MEM_IF_CS_WIDTH]];
end
end
end
end
endgenerate
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
refresh_req_ack <= 0;
zqcal_req_ack <= 0;
pch_all_req_ack <= 0;
self_rfsh_req_ack <= 0;
dummy_do_refresh_r <= dummy_do_refresh;
do_refresh_r <= 0;
end
else
begin
refresh_req_ack <= dummy_do_refresh;
zqcal_req_ack <= dummy_do_zqcal;
pch_all_req_ack <= dummy_do_pch_all;
self_rfsh_req_ack <= dummy_do_self_rfsh;
dummy_do_refresh_r <= dummy_do_refresh;
if (dummy_do_refresh && !dummy_do_refresh_r)
do_refresh_r <= |do_refresh;
else
do_refresh_r <= 0;
end
end
always @(*)
begin
i = 0;
dummy_do_refresh = 0;
dummy_do_pch_all = 0;
dummy_do_zqcal = 0;
if (|do_refresh_req)
begin
if (!(cfg_regdimm_enable && cfg_type == `MMR_TYPE_DDR3 && CFG_MEM_IF_CHIP != 1)) // if not (regdimm and DDR3), normal refresh
do_refresh = do_refresh_req;
else
begin
for (i = 0;i < CFG_MEM_IF_CHIP;i = i + 1)
begin
if (i%2 == 0)
begin
do_refresh[i] = do_refresh_req[i];
dummy_do_refresh= |do_refresh_req;
end
else if (i%2 == 1 && refresh_req_ack)
do_refresh[i] = do_refresh_req[i];
else
do_refresh[i] = 0;
end
end
do_precharge_all = 0;
do_zqcal = 0;
end
else if (|do_pch_all_req)
begin
do_refresh = 0;
if (!(cfg_regdimm_enable && cfg_type == `MMR_TYPE_DDR3 && CFG_MEM_IF_CHIP != 1))
do_precharge_all = do_pch_all_req;
else
begin
for (i = 0;i < CFG_MEM_IF_CHIP;i = i + 1)
begin
if (i%2 == 0)
begin
do_precharge_all[i] = do_pch_all_req[i];
dummy_do_pch_all = |do_pch_all_req;
end
else if (i%2 == 1 && pch_all_req_ack)
do_precharge_all[i] = do_pch_all_req[i];
else
do_precharge_all[i] = 0;
end
end
do_zqcal = 0;
end
else if (|do_zqcal_req)
begin
do_refresh = 0;
do_precharge_all = 0;
if (!(cfg_regdimm_enable && cfg_type == `MMR_TYPE_DDR3 && CFG_MEM_IF_CHIP != 1))
do_zqcal = do_zqcal_req;
else
begin
for (i = 0;i < CFG_MEM_IF_CHIP;i = i + 1)
begin
if (i%2 == 0)
begin
do_zqcal[i] = do_zqcal_req[i];
dummy_do_zqcal= |do_zqcal_req;
end
else if (i%2 == 1 && zqcal_req_ack)
do_zqcal[i] = do_zqcal_req[i];
else
do_zqcal[i] = 0;
end
end
end
else
begin
do_refresh = 0;
dummy_do_refresh = 0;
do_precharge_all = 0;
dummy_do_pch_all = 0;
do_zqcal = 0;
dummy_do_zqcal = 0;
end
end
always @(*)
begin
i = 0;
dummy_do_self_rfsh = 1'b0;
if (|do_refresh || |do_precharge_all || |do_zqcal)
begin
if (|do_self_rfsh_r)
begin
do_self_rfsh = do_self_rfsh_req;
dummy_do_self_rfsh = 1'b1;
end
else
do_self_rfsh = 0;
end
else
begin
if (!(cfg_regdimm_enable && cfg_type == `MMR_TYPE_DDR3 && CFG_MEM_IF_CHIP != 1))
do_self_rfsh = do_self_rfsh_req;
else
begin
for (i = 0;i < CFG_MEM_IF_CHIP;i = i + 1)
begin
if (i%2 == 0)
begin
do_self_rfsh[i] = do_self_rfsh_req[i];
dummy_do_self_rfsh= |do_self_rfsh_req;
end
else if (i%2 == 1 && self_rfsh_req_ack)
do_self_rfsh[i] = do_self_rfsh_req[i];
else
do_self_rfsh[i] = 0;
end
end
end
end
assign stall_row_arbiter = |stall_arbiter;
assign stall_col_arbiter = |stall_arbiter;
assign grant = (CFG_REG_GRANT == 1) ? (row_grant | col_grant) : 1'b0;
//register self_rfsh_req and deep_powerdn_req
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
self_refresh_chip_req <= 0;
deep_pdown_chip_req <= 0;
self_rfsh_req_r <= 0;
do_self_rfsh_r <= 0;
end
else
begin
if (self_rfsh_req)
self_refresh_chip_req <= self_rfsh_chip;
else
self_refresh_chip_req <= 0;
self_rfsh_req_r <= self_rfsh_req & |self_rfsh_chip;
do_self_rfsh_r <= do_self_rfsh;
if (deep_powerdn_req)
deep_pdown_chip_req <= deep_powerdn_chip;
else
deep_pdown_chip_req <= 0;
end
end
//combi user refresh
always @(*)
begin
if (cfg_user_rfsh)
begin
if (rfsh_req)
refresh_chip_req = rfsh_chip;
else
refresh_chip_req = 0;
end
else
refresh_chip_req = cs_refresh_req;
end
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
afi_seq_busy_r <= 0;
afi_seq_busy_r2 <= 0;
end
else
begin
afi_seq_busy_r <= afi_seq_busy;
afi_seq_busy_r2 <= afi_seq_busy_r;
end
end
// cans
generate
genvar w_cs;
for (w_cs = 0;w_cs < CFG_MEM_IF_CHIP;w_cs = w_cs + 1)
begin : can_signal_per_chip
// Can refresh signal for each rank
always @ (*)
begin
can_refresh [w_cs] = power_saving_enter_ready [w_cs] & all_banks_closed[w_cs] & tcom_not_running[w_cs] & ~grant;
end
// Can self refresh signal for each rank
always @ (*)
begin
can_self_rfsh [w_cs] = power_saving_enter_ready [w_cs] & all_banks_closed[w_cs] & tcom_not_running[w_cs] & tcom_not_running_pipe[w_cs][cfg_tcl] & ~grant;
end
always @ (*)
begin
can_deep_pdown [w_cs] = power_saving_enter_ready [w_cs] & all_banks_closed[w_cs] & tcom_not_running[w_cs] & ~grant;
end
// Can power down signal for each rank
always @ (*)
begin
can_power_down [w_cs] = power_saving_enter_ready [w_cs] & all_banks_closed[w_cs] & tcom_not_running[w_cs] & tcom_not_running_pipe[w_cs][cfg_tcl] & ~grant;
end
// Can exit power saving mode signal for each rank
always @ (*)
begin
can_exit_power_saving_mode [w_cs] = power_saving_exit_ready [w_cs];
end
end
endgenerate
/*------------------------------------------------------------------------------
[START] Power Saving Rank Monitor
------------------------------------------------------------------------------*/
/*------------------------------------------------------------------------------
Power Saving State Machine
------------------------------------------------------------------------------*/
generate
genvar u_cs;
for (u_cs = 0;u_cs < CFG_MEM_IF_CHIP;u_cs = u_cs + 1)
begin : power_saving_logic_per_chip
reg [POWER_SAVING_COUNTER_WIDTH - 1 : 0] power_saving_cnt;
reg [POWER_SAVING_EXIT_COUNTER_WIDTH - 1 : 0] power_saving_exit_cnt;
reg [31 : 0] state;
reg [31 : 0] sideband_state;
reg int_enter_power_saving_ready;
reg int_exit_power_saving_ready;
reg registered_reset;
reg int_zq_cal_req;
reg int_do_power_down;
reg int_do_power_down_r1;
reg int_do_power_down_r2;
reg int_do_self_refresh;
reg int_do_self_refresh_r1;
reg int_do_self_refresh_r2;
reg int_do_self_refresh_r3;
// assignment
assign power_saving_enter_ready [u_cs] = int_enter_power_saving_ready;
assign power_saving_exit_ready [u_cs] = int_exit_power_saving_ready & ~((int_do_power_down & ~int_do_power_down_r1) | (int_do_self_refresh & ~int_do_self_refresh_r1));
assign cs_zq_cal_req [u_cs] = int_zq_cal_req;
// counter for power saving state machine
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
power_saving_cnt <= 0;
else
begin
if (do_precharge_all[u_cs] || do_refresh[u_cs] || do_self_rfsh[u_cs] || do_power_down[u_cs])
power_saving_cnt <= BANK_TIMER_COUNTER_OFFSET;
else if (power_saving_cnt != {POWER_SAVING_COUNTER_WIDTH{1'b1}})
power_saving_cnt <= power_saving_cnt + 1'b1;
end
end
// Do power down and self refresh register
always @ (*)
begin
int_do_power_down = do_power_down[u_cs];
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_do_power_down_r1 <= 1'b0;
int_do_power_down_r2 <= 1'b0;
end
else
begin
int_do_power_down_r1 <= int_do_power_down;
int_do_power_down_r2 <= int_do_power_down_r1;
end
end
always @ (*)
begin
int_do_self_refresh = do_self_rfsh[u_cs];
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_do_self_refresh_r1 <= 1'b0;
int_do_self_refresh_r2 <= 1'b0;
int_do_self_refresh_r3 <= 1'b0;
end
else
begin
int_do_self_refresh_r1 <= int_do_self_refresh;
int_do_self_refresh_r2 <= int_do_self_refresh_r1;
int_do_self_refresh_r3 <= int_do_self_refresh_r2;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
power_saving_exit_cnt <= 0;
end
else
begin
if ((int_do_power_down & !int_do_power_down_r1) || (int_do_self_refresh & !int_do_self_refresh_r1))
begin
power_saving_exit_cnt <= BANK_TIMER_COUNTER_OFFSET;
end
else if (power_saving_exit_cnt != {POWER_SAVING_EXIT_COUNTER_WIDTH{1'b1}})
begin
power_saving_exit_cnt = power_saving_exit_cnt + 1'b1;
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_exit_power_saving_ready <= 1'b0;
end
else
begin
if (( int_do_power_down) && (!int_do_power_down_r1)) // positive edge detector but late by one clock cycle
begin
int_exit_power_saving_ready <= 1'b0;
end
else if (( int_do_self_refresh ) && (!int_do_self_refresh_r1 )) // positive edge detector
begin
int_exit_power_saving_ready <= 1'b0;
end
else if (power_saving_exit_cnt >= t_param_power_saving_exit)
begin
int_exit_power_saving_ready <= 1'b1;
end
else
begin
int_exit_power_saving_ready <= 1'b0;
end
end
end
// stall_chip output signal
always @ (*)
begin
if (CFG_RANK_TIMER_OUTPUT_REG)
begin
stall_chip[u_cs] = int_stall_chip[u_cs] | int_stall_chip_combi[u_cs];
end
else
begin
stall_chip[u_cs] = int_stall_chip[u_cs];
end
end
// int_stall_chip_combi signal, we need to issue stall chip one clock cycle earlier to rank timer
// because rank timer is using a register output
always @ (*)
begin
if (state == IDLE)
begin
if (refresh_chip_req[u_cs] && !do_refresh[u_cs])
begin
int_stall_chip_combi[u_cs] = 1'b1;
end
else if (self_refresh_chip_req[u_cs])
begin
int_stall_chip_combi[u_cs] = 1'b1;
end
else if (deep_pdown_chip_req[u_cs])
begin
int_stall_chip_combi[u_cs] = 1'b1;
end
else if (power_down_chip_req_combi[u_cs])
begin
int_stall_chip_combi[u_cs] = 1'b1;
end
else
begin
int_stall_chip_combi[u_cs] = 1'b0;
end
end
else
begin
int_stall_chip_combi[u_cs] = 1'b0;
end
end
// command issuing state machine
always @(posedge ctl_clk, negedge ctl_reset_n)
begin : FSM
if (!ctl_reset_n)
begin
state <= INIT;
int_stall_chip[u_cs] <= 1'b0;
stall_arbiter[u_cs] <= 1'b0;
do_power_down[u_cs] <= 1'b0;
do_deep_pdown[u_cs] <= 1'b0;
do_self_rfsh_req[u_cs] <= 1'b0;
do_zqcal_req[u_cs] <= 1'b0;
doing_zqcal[u_cs] <= 1'b0;
do_pch_all_req[u_cs] <= 1'b0;
do_refresh_req[u_cs] <= 1'b0;
afi_ctl_refresh_done[u_cs] <= 1'b0;
afi_ctl_long_idle[u_cs] <= 1'b0;
dqstrk_exit[u_cs] <= 1'b0;
dqslong_exit[u_cs] <= 1'b0;
end
else
case(state)
INIT :
if (ctl_cal_success == 1'b1)
begin
state <= IDLE;
int_stall_chip[u_cs] <= 1'b0;
end
else
begin
state <= INIT;
int_stall_chip[u_cs] <= 1'b1;
end
IDLE :
begin
do_pch_all_req[u_cs] <= 1'b0;
if (do_zqcal_req[u_cs])
begin
if (do_zqcal[u_cs])
begin
do_zqcal_req[u_cs] <= 1'b0;
doing_zqcal[u_cs] <= 1'b0;
stall_arbiter[u_cs] <= 1'b0;
end
end
else if (refresh_chip_req[u_cs] && !do_refresh[u_cs])
begin
int_stall_chip[u_cs] <= 1'b1;
if (all_banks_closed[u_cs])
state <= REFRESH;
else
state <= PCHALL;
end
else if (self_refresh_chip_req[u_cs])
begin
int_stall_chip[u_cs] <= 1'b1;
if (all_banks_closed[u_cs])
state <= SELFRFSH;
else
state <= PCHALL;
end
else if (deep_pdown_chip_req[u_cs])
begin
int_stall_chip[u_cs] <= 1'b1;
if (all_banks_closed[u_cs])
state <= DEEPPDN;
else
state <= PCHALL;
end
else if (power_down_chip_req_combi[u_cs])
begin
int_stall_chip[u_cs] <= 1'b1;
if (all_banks_closed[u_cs])
state <= PDOWN;
else
state <= PCHALL;
end
else if (int_stall_chip[u_cs] && !do_refresh[u_cs] && power_saving_enter_ready[u_cs])
int_stall_chip[u_cs] <= 1'b0;
end
PCHALL :
begin
if (refresh_chip_req[u_cs] | self_refresh_chip_req[u_cs] | power_down_chip_req_combi[u_cs])
begin
if (do_precharge_all[u_cs] || all_banks_closed[u_cs])
begin
do_pch_all_req[u_cs] <= 1'b0;
stall_arbiter[u_cs] <= 1'b0;
if (refresh_chip_req[u_cs])
state <= REFRESH;
else if (self_refresh_chip_req[u_cs])
state <= SELFRFSH;
else state <= PDOWN;
end
else if (refresh_chip_req[u_cs])
begin
if ((~all_banks_closed&refresh_chip_req)==(~all_banks_closed&tcom_not_running&refresh_chip_req) && !grant)
begin
do_pch_all_req[u_cs] <= 1'b1;
stall_arbiter[u_cs] <= 1'b1;
end
end
else if (self_refresh_chip_req[u_cs])
begin
if ((~all_banks_closed&self_refresh_chip_req)==(~all_banks_closed&tcom_not_running&self_refresh_chip_req) && !grant)
begin
do_pch_all_req[u_cs] <= 1'b1;
stall_arbiter[u_cs] <= 1'b1;
end
end
else if (&tcom_not_running && !grant)
begin
do_pch_all_req[u_cs] <= 1'b1;
stall_arbiter[u_cs] <= 1'b1;
end
end
else
begin
state <= IDLE;
do_pch_all_req[u_cs] <= 1'b0;
stall_arbiter[u_cs] <= 1'b0;
end
end
REFRESH :
begin
if (do_refresh[u_cs])
begin
do_refresh_req[u_cs] <= 1'b0;
stall_arbiter[u_cs] <= 1'b0;
if (cfg_enable_dqs_tracking && &do_refresh)
state <= DQSTRK;
else if (!refresh_chip_req[u_cs] && power_down_chip_req_combi[u_cs])
state <= PDOWN;
else
state <= IDLE;
end
else if (refresh_chip_req[u_cs])
begin
if (!all_banks_closed[u_cs])
state <= PCHALL;
else if (refresh_chip_req==(can_refresh&refresh_chip_req))
begin
do_refresh_req[u_cs] <= 1'b1;
stall_arbiter[u_cs] <= 1'b1;
end
end
else
begin
state <= IDLE;
stall_arbiter[u_cs] <= 1'b0;
end
end
DQSTRK :
begin
if (!dqstrk_exit[u_cs] && !afi_ctl_refresh_done[u_cs] && !do_refresh[u_cs] && power_saving_enter_ready[u_cs])
afi_ctl_refresh_done[u_cs] <= 1'b1;
else if (!dqstrk_exit[u_cs] && afi_seq_busy_r2[u_cs] && afi_ctl_refresh_done[u_cs]) // stall until seq_busy is deasserted
dqstrk_exit[u_cs] <= 1;
else if (dqstrk_exit[u_cs] && !afi_seq_busy_r2[u_cs])
begin
afi_ctl_refresh_done[u_cs] <= 1'b0;
dqstrk_exit[u_cs] <= 1'b0;
if (!refresh_chip_req[u_cs] && power_down_chip_req_combi[u_cs])
state <= PDOWN;
else
state <= IDLE;
end
end
DQSLONG :
begin
if (do_zqcal[u_cs])
begin
do_zqcal_req[u_cs] <= 1'b0;
doing_zqcal[u_cs] <= 1'b0;
stall_arbiter[u_cs] <= 1'b0;
end
if (!dqslong_exit[u_cs] && !afi_ctl_long_idle[u_cs] && power_saving_enter_ready[u_cs])
afi_ctl_long_idle[u_cs] <= 1'b1;
else if (!dqslong_exit[u_cs] && afi_seq_busy_r2[u_cs] && afi_ctl_long_idle[u_cs])
dqslong_exit[u_cs] <= 1;
else if (dqslong_exit[u_cs] && !afi_seq_busy_r2[u_cs])
begin
afi_ctl_long_idle[u_cs] <= 1'b0;
dqslong_exit[u_cs] <= 1'b0;
state <= IDLE;
end
end
PDOWN :
begin
if (refresh_chip_req[u_cs] && !do_refresh[u_cs] && can_exit_power_saving_mode[u_cs])
begin
state <= REFRESH;
do_power_down[u_cs] <= 1'b0;
stall_arbiter[u_cs] <= 1'b0;
end
else if (!power_down_chip_req_combi[u_cs] && can_exit_power_saving_mode[u_cs])
begin
if (self_refresh_chip_req[u_cs])
state <= SELFRFSH;
else
state <= IDLE;
do_power_down[u_cs] <= 1'b0;
stall_arbiter[u_cs] <= 1'b0;
end
else if (&can_power_down && !(|refresh_chip_req))
begin
do_power_down[u_cs] <= 1'b1;
stall_arbiter[u_cs] <= 1'b1;
end
else
state <= PDOWN;
end
DEEPPDN :
begin
if (!deep_pdown_chip_req[u_cs] && can_exit_power_saving_mode[u_cs])
begin
do_deep_pdown[u_cs] <= 1'b0;
stall_arbiter[u_cs] <= 1'b0;
if (cfg_enable_dqs_tracking)
state <= DQSLONG;
else
state <= IDLE;
end
else if (can_deep_pdown[u_cs] && !do_precharge_all[u_cs])
begin
do_deep_pdown[u_cs] <= 1'b1;
stall_arbiter[u_cs] <= 1'b1;
end
end
SELFRFSH :
begin
if (!all_banks_closed[u_cs])
state <= PCHALL;
else if (!self_refresh_chip_req[u_cs] && can_exit_power_saving_mode[u_cs])
begin
do_self_rfsh_req[u_cs] <= 1'b0;
stall_arbiter[u_cs] <= 1'b0;
if (cfg_type == `MMR_TYPE_DDR3) // DDR3
begin
state <= ZQCAL;
doing_zqcal[u_cs] <= 1'b1;
end
else if (cfg_enable_dqs_tracking && &do_self_rfsh)
state <= DQSLONG;
else
state <= IDLE;
end
else if (self_refresh_chip_req==(can_self_rfsh&self_refresh_chip_req) && !(|do_precharge_all))
begin
do_self_rfsh_req[u_cs] <= 1'b1;
stall_arbiter[u_cs] <= 1'b1;
end
end
ZQCAL :
begin
if (cs_zq_cal_req[u_cs])
begin
do_zqcal_req[u_cs] <= 1'b1;
stall_arbiter[u_cs] <= 1'b1;
if (cfg_enable_dqs_tracking && &cs_zq_cal_req)
state <= DQSLONG;
else
state <= IDLE;
end
end
default : state <= IDLE;
endcase
end
// sideband state machine
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
sideband_state <= IDLE;
int_enter_power_saving_ready <= 1'b0;
int_zq_cal_req <= 1'b0;
end
else
begin
case (sideband_state)
IDLE :
begin
int_zq_cal_req <= 1'b0;
if (power_saving_cnt >= t_param_pch_all_to_valid)
int_enter_power_saving_ready <= 1'b1;
else
int_enter_power_saving_ready <= 1'b0;
if (do_precharge_all[u_cs])
begin
int_enter_power_saving_ready <= 1'b0;
end
if (do_refresh[u_cs])
begin
sideband_state <= ARF;
int_enter_power_saving_ready <= 1'b0;
end
if (do_self_rfsh[u_cs])
begin
sideband_state <= SRF;
int_enter_power_saving_ready <= 1'b0;
end
if (do_power_down[u_cs])
begin
sideband_state <= PDN;
int_enter_power_saving_ready <= 1'b0;
end
end
ARF :
begin
int_zq_cal_req <= 1'b0;
if (power_saving_cnt >= t_param_arf_to_valid)
begin
sideband_state <= IDLE;
int_enter_power_saving_ready <= 1'b1;
end
else
begin
sideband_state <= ARF;
int_enter_power_saving_ready <= 1'b0;
end
end
SRF :
begin
// ZQ request to state machine
if (power_saving_cnt == t_param_srf_to_zq_cal) // only one cycle
int_zq_cal_req <= 1'b1;
else
int_zq_cal_req <= 1'b0;
if (!do_self_rfsh[u_cs] && power_saving_cnt >= t_param_srf_to_valid)
begin
sideband_state <= IDLE;
int_enter_power_saving_ready <= 1'b1;
end
else
begin
sideband_state <= SRF;
int_enter_power_saving_ready <= 1'b0;
end
end
PDN :
begin
int_zq_cal_req <= 1'b0;
if (!do_power_down[u_cs] && power_saving_cnt >= t_param_pdn_to_valid)
begin
sideband_state <= IDLE;
int_enter_power_saving_ready <= 1'b1;
end
else
begin
sideband_state <= PDN;
int_enter_power_saving_ready <= 1'b0;
end
end
default :
begin
sideband_state <= IDLE;
end
endcase
end
end
end
endgenerate
/*------------------------------------------------------------------------------
Refresh Request
------------------------------------------------------------------------------*/
generate
genvar s_cs;
for (s_cs = 0;s_cs < CFG_MEM_IF_CHIP;s_cs = s_cs + 1)
begin : auto_refresh_logic_per_chip
reg [ARF_COUNTER_WIDTH - 1 : 0] refresh_cnt;
// refresh counter
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
refresh_cnt <= 0;
end
else
begin
if (self_rfsh_req && |self_rfsh_chip && !self_rfsh_req_r)
refresh_cnt <= {ARF_COUNTER_WIDTH{1'b1}};
else if (do_refresh[s_cs])
refresh_cnt <= 3;
else if (refresh_cnt != {ARF_COUNTER_WIDTH{1'b1}})
refresh_cnt <= refresh_cnt + 1'b1;
end
end
// refresh request logic
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
cs_refresh_req [s_cs] <= 1'b0;
end
else
begin
if (self_rfsh_req && |self_rfsh_chip && !self_rfsh_req_r)
cs_refresh_req [s_cs] <= 1'b1;
else if (do_refresh[s_cs] || do_self_rfsh[s_cs])
cs_refresh_req [s_cs] <= 1'b0;
else if (refresh_cnt >= t_param_arf_period)
cs_refresh_req [s_cs] <= 1'b1;
else
cs_refresh_req [s_cs] <= 1'b0;
end
end
end
endgenerate
/*------------------------------------------------------------------------------
Power Down Request
------------------------------------------------------------------------------*/
// register no command signal
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
no_command_r1 <= 1'b0;
end
else
begin
no_command_r1 <= tbp_empty;
end
end
// power down counter
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
power_down_cnt <= 0;
end
else
begin
if ((!tbp_empty && no_command_r1) || self_rfsh_req) // negative edge detector
power_down_cnt <= 3;
else if (tbp_empty && power_down_cnt != {PDN_COUNTER_WIDTH{1'b1}} && ctl_cal_success)
power_down_cnt <= power_down_cnt + 1'b1;
end
end
// power down request logic
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
power_down_chip_req <= 0;
end
else
begin
if (t_param_pdn_period == 0) // when auto power down cycles is set to '0', auto power down mode will be disabled
power_down_chip_req <= 0;
else
begin
if (!tbp_empty || self_rfsh_req) // we need to make sure power down request to go low as fast as possible to avoid unnecessary power down
power_down_chip_req <= 0;
else if (power_down_chip_req == 0)
begin
if (power_down_cnt >= t_param_pdn_period && !(|doing_zqcal))
power_down_chip_req <= {CFG_MEM_IF_CHIP{1'b1}};
else
power_down_chip_req <= 0;
end
else if (!(power_down_cnt >= t_param_pdn_period))
power_down_chip_req <= 0;
end
end
end
assign power_down_chip_req_combi = power_down_chip_req & {CFG_MEM_IF_CHIP{tbp_empty}} & {CFG_MEM_IF_CHIP{~(|refresh_chip_req)}};
/*------------------------------------------------------------------------------
[END] Power Saving Rank Monitor
------------------------------------------------------------------------------*/
endmodule
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// altera message_off 10230 10036
`include "alt_mem_ddrx_define.iv"
`timescale 1 ps / 1 ps
module alt_mem_ddrx_tbp
#( parameter
CFG_CTL_TBP_NUM = 4,
CFG_CTL_SHADOW_TBP_NUM = 4,
CFG_ENABLE_SHADOW_TBP = 0,
CFG_DWIDTH_RATIO = 2,
CFG_CTL_ARBITER_TYPE = "ROWCOL",
CFG_MEM_IF_CHIP = 1, // one hot
CFG_MEM_IF_CS_WIDTH = 1, // binary encoded
CFG_MEM_IF_BA_WIDTH = 3,
CFG_MEM_IF_ROW_WIDTH = 13,
CFG_MEM_IF_COL_WIDTH = 10,
CFG_LOCAL_ID_WIDTH = 8,
CFG_INT_SIZE_WIDTH = 4,
CFG_DATA_ID_WIDTH = 10,
CFG_REG_REQ = 0,
CFG_REG_GRANT = 0,
CFG_DATA_REORDERING_TYPE = "INTER_BANK",
CFG_DISABLE_READ_REODERING = 0,
CFG_DISABLE_PRIORITY = 0,
CFG_PORT_WIDTH_REORDER_DATA = 1,
CFG_PORT_WIDTH_STARVE_LIMIT = 6,
CFG_PORT_WIDTH_TYPE = 3,
T_PARAM_ACT_TO_RDWR_WIDTH = 4,
T_PARAM_ACT_TO_ACT_WIDTH = 4,
T_PARAM_ACT_TO_PCH_WIDTH = 4,
T_PARAM_RD_TO_PCH_WIDTH = 4,
T_PARAM_WR_TO_PCH_WIDTH = 4,
T_PARAM_PCH_TO_VALID_WIDTH = 4,
T_PARAM_RD_AP_TO_VALID_WIDTH = 4,
T_PARAM_WR_AP_TO_VALID_WIDTH = 4
)
(
ctl_clk,
ctl_reset_n,
// Cmd gen interface
tbp_full,
tbp_empty,
cmd_gen_load,
cmd_gen_chipsel,
cmd_gen_bank,
cmd_gen_row,
cmd_gen_col,
cmd_gen_write,
cmd_gen_read,
cmd_gen_size,
cmd_gen_localid,
cmd_gen_dataid,
cmd_gen_priority,
cmd_gen_rmw_correct,
cmd_gen_rmw_partial,
cmd_gen_autopch,
cmd_gen_complete,
cmd_gen_same_chipsel_addr,
cmd_gen_same_bank_addr,
cmd_gen_same_row_addr,
cmd_gen_same_col_addr,
cmd_gen_same_read_cmd,
cmd_gen_same_write_cmd,
cmd_gen_same_shadow_chipsel_addr,
cmd_gen_same_shadow_bank_addr,
cmd_gen_same_shadow_row_addr,
// Arbiter interface
row_req,
act_req,
pch_req,
row_grant,
act_grant,
pch_grant,
col_req,
rd_req,
wr_req,
col_grant,
rd_grant,
wr_grant,
log2_row_grant,
log2_col_grant,
log2_act_grant,
log2_pch_grant,
log2_rd_grant,
log2_wr_grant,
or_row_grant,
or_col_grant,
tbp_read,
tbp_write,
tbp_precharge,
tbp_activate,
tbp_chipsel,
tbp_bank,
tbp_row,
tbp_col,
tbp_shadow_chipsel,
tbp_shadow_bank,
tbp_shadow_row,
tbp_size,
tbp_localid,
tbp_dataid,
tbp_ap,
tbp_burst_chop,
tbp_age,
tbp_priority,
tbp_rmw_correct,
tbp_rmw_partial,
sb_tbp_precharge_all,
sb_do_precharge_all,
// Timer value
t_param_act_to_rdwr,
t_param_act_to_act,
t_param_act_to_pch,
t_param_rd_to_pch,
t_param_wr_to_pch,
t_param_pch_to_valid,
t_param_rd_ap_to_valid,
t_param_wr_ap_to_valid,
// Misc interface
tbp_bank_active,
tbp_timer_ready,
tbp_load,
data_complete,
// Config interface
cfg_reorder_data,
cfg_starve_limit,
cfg_type
);
localparam integer CFG_MEM_IF_BA_WIDTH_SQRD = 2**CFG_MEM_IF_BA_WIDTH;
localparam TBP_COUNTER_OFFSET = (CFG_REG_GRANT) ? 2 : 1;
localparam RDWR_AP_TO_VALID_WIDTH = (T_PARAM_RD_AP_TO_VALID_WIDTH > T_PARAM_WR_AP_TO_VALID_WIDTH) ? T_PARAM_RD_AP_TO_VALID_WIDTH : T_PARAM_WR_AP_TO_VALID_WIDTH;
localparam COL_TIMER_WIDTH = T_PARAM_ACT_TO_RDWR_WIDTH;
localparam ROW_TIMER_WIDTH = (T_PARAM_ACT_TO_ACT_WIDTH > RDWR_AP_TO_VALID_WIDTH) ? T_PARAM_ACT_TO_ACT_WIDTH : RDWR_AP_TO_VALID_WIDTH;
localparam TRC_TIMER_WIDTH = T_PARAM_ACT_TO_ACT_WIDTH;
// Start of port declaration
input ctl_clk;
input ctl_reset_n;
output tbp_full;
output tbp_empty;
input cmd_gen_load;
input [CFG_MEM_IF_CS_WIDTH-1:0] cmd_gen_chipsel;
input [CFG_MEM_IF_BA_WIDTH-1:0] cmd_gen_bank;
input [CFG_MEM_IF_ROW_WIDTH-1:0] cmd_gen_row;
input [CFG_MEM_IF_COL_WIDTH-1:0] cmd_gen_col;
input cmd_gen_write;
input cmd_gen_read;
input [CFG_INT_SIZE_WIDTH-1:0] cmd_gen_size;
input [CFG_LOCAL_ID_WIDTH-1:0] cmd_gen_localid;
input [CFG_DATA_ID_WIDTH-1:0] cmd_gen_dataid;
input cmd_gen_priority;
input cmd_gen_rmw_correct;
input cmd_gen_rmw_partial;
input cmd_gen_autopch;
input cmd_gen_complete;
input [CFG_CTL_TBP_NUM-1:0] cmd_gen_same_chipsel_addr;
input [CFG_CTL_TBP_NUM-1:0] cmd_gen_same_bank_addr;
input [CFG_CTL_TBP_NUM-1:0] cmd_gen_same_row_addr;
input [CFG_CTL_TBP_NUM-1:0] cmd_gen_same_col_addr;
input [CFG_CTL_TBP_NUM-1:0] cmd_gen_same_read_cmd;
input [CFG_CTL_TBP_NUM-1:0] cmd_gen_same_write_cmd;
input [CFG_CTL_SHADOW_TBP_NUM-1:0] cmd_gen_same_shadow_chipsel_addr;
input [CFG_CTL_SHADOW_TBP_NUM-1:0] cmd_gen_same_shadow_bank_addr;
input [CFG_CTL_SHADOW_TBP_NUM-1:0] cmd_gen_same_shadow_row_addr;
output [CFG_CTL_TBP_NUM-1:0] row_req;
output [CFG_CTL_TBP_NUM-1:0] act_req;
output [CFG_CTL_TBP_NUM-1:0] pch_req;
input [CFG_CTL_TBP_NUM-1:0] row_grant;
input [CFG_CTL_TBP_NUM-1:0] act_grant;
input [CFG_CTL_TBP_NUM-1:0] pch_grant;
output [CFG_CTL_TBP_NUM-1:0] col_req;
output [CFG_CTL_TBP_NUM-1:0] rd_req;
output [CFG_CTL_TBP_NUM-1:0] wr_req;
input [CFG_CTL_TBP_NUM-1:0] col_grant;
input [CFG_CTL_TBP_NUM-1:0] rd_grant;
input [CFG_CTL_TBP_NUM-1:0] wr_grant;
input [log2(CFG_CTL_TBP_NUM)-1:0] log2_row_grant;
input [log2(CFG_CTL_TBP_NUM)-1:0] log2_col_grant;
input [log2(CFG_CTL_TBP_NUM)-1:0] log2_act_grant;
input [log2(CFG_CTL_TBP_NUM)-1:0] log2_pch_grant;
input [log2(CFG_CTL_TBP_NUM)-1:0] log2_rd_grant;
input [log2(CFG_CTL_TBP_NUM)-1:0] log2_wr_grant;
input or_row_grant;
input or_col_grant;
output [CFG_CTL_TBP_NUM-1:0] tbp_read;
output [CFG_CTL_TBP_NUM-1:0] tbp_write;
output [CFG_CTL_TBP_NUM-1:0] tbp_precharge;
output [CFG_CTL_TBP_NUM-1:0] tbp_activate;
output [(CFG_CTL_TBP_NUM*CFG_MEM_IF_CS_WIDTH)-1:0] tbp_chipsel;
output [(CFG_CTL_TBP_NUM*CFG_MEM_IF_BA_WIDTH)-1:0] tbp_bank;
output [(CFG_CTL_TBP_NUM*CFG_MEM_IF_ROW_WIDTH)-1:0] tbp_row;
output [(CFG_CTL_TBP_NUM*CFG_MEM_IF_COL_WIDTH)-1:0] tbp_col;
output [(CFG_CTL_SHADOW_TBP_NUM*CFG_MEM_IF_CS_WIDTH)-1:0] tbp_shadow_chipsel;
output [(CFG_CTL_SHADOW_TBP_NUM*CFG_MEM_IF_BA_WIDTH)-1:0] tbp_shadow_bank;
output [(CFG_CTL_SHADOW_TBP_NUM*CFG_MEM_IF_ROW_WIDTH)-1:0] tbp_shadow_row;
output [(CFG_CTL_TBP_NUM*CFG_INT_SIZE_WIDTH)-1:0] tbp_size;
output [(CFG_CTL_TBP_NUM*CFG_LOCAL_ID_WIDTH)-1:0] tbp_localid;
output [(CFG_CTL_TBP_NUM*CFG_DATA_ID_WIDTH)-1:0] tbp_dataid;
output [CFG_CTL_TBP_NUM-1:0] tbp_ap;
output [CFG_CTL_TBP_NUM-1:0] tbp_burst_chop;
output [(CFG_CTL_TBP_NUM*CFG_CTL_TBP_NUM)-1:0] tbp_age;
output [CFG_CTL_TBP_NUM-1:0] tbp_priority;
output [CFG_CTL_TBP_NUM-1:0] tbp_rmw_correct;
output [CFG_CTL_TBP_NUM-1:0] tbp_rmw_partial;
input [CFG_CTL_TBP_NUM-1:0] sb_tbp_precharge_all;
input [CFG_MEM_IF_CHIP-1:0] sb_do_precharge_all;
input [T_PARAM_ACT_TO_RDWR_WIDTH-1:0] t_param_act_to_rdwr;
input [T_PARAM_ACT_TO_ACT_WIDTH-1:0] t_param_act_to_act;
input [T_PARAM_ACT_TO_PCH_WIDTH-1:0] t_param_act_to_pch;
input [T_PARAM_RD_TO_PCH_WIDTH-1:0] t_param_rd_to_pch;
input [T_PARAM_WR_TO_PCH_WIDTH-1:0] t_param_wr_to_pch;
input [T_PARAM_PCH_TO_VALID_WIDTH-1:0] t_param_pch_to_valid;
input [T_PARAM_RD_AP_TO_VALID_WIDTH-1:0] t_param_rd_ap_to_valid;
input [T_PARAM_WR_AP_TO_VALID_WIDTH-1:0] t_param_wr_ap_to_valid;
output [CFG_MEM_IF_CHIP-1:0] tbp_bank_active;
output [CFG_MEM_IF_CHIP-1:0] tbp_timer_ready;
output [CFG_CTL_TBP_NUM-1:0] tbp_load;
input [CFG_CTL_TBP_NUM-1:0] data_complete;
input [CFG_PORT_WIDTH_REORDER_DATA-1:0] cfg_reorder_data;
input [CFG_PORT_WIDTH_STARVE_LIMIT-1:0] cfg_starve_limit;
input [CFG_PORT_WIDTH_TYPE-1:0] cfg_type;
// End of port declaration
// Logic operators
wire tbp_full;
wire tbp_empty;
wire [CFG_CTL_TBP_NUM-1:0] tbp_load;
wire [CFG_CTL_TBP_NUM-1:0] load_tbp;
reg [CFG_CTL_TBP_NUM-1:0] load_tbp_index;
wire [CFG_CTL_TBP_NUM-1:0] flush_tbp;
reg [CFG_CTL_TBP_NUM-1:0] precharge_tbp;
reg [CFG_CTL_TBP_NUM-1:0] row_req;
reg [CFG_CTL_TBP_NUM-1:0] act_req;
reg [CFG_CTL_TBP_NUM-1:0] pch_req;
reg [CFG_CTL_TBP_NUM-1:0] col_req;
reg [CFG_CTL_TBP_NUM-1:0] rd_req;
reg [CFG_CTL_TBP_NUM-1:0] wr_req;
reg int_tbp_full;
wire int_tbp_empty;
reg [CFG_CTL_TBP_NUM-1:0] valid;
wire [CFG_CTL_TBP_NUM-1:0] valid_combi;
reg [CFG_MEM_IF_CS_WIDTH-1:0] chipsel [CFG_CTL_TBP_NUM-1:0];
reg [CFG_MEM_IF_BA_WIDTH-1:0] bank [CFG_CTL_TBP_NUM-1:0];
reg [CFG_MEM_IF_ROW_WIDTH-1:0] row [CFG_CTL_TBP_NUM-1:0];
reg [CFG_MEM_IF_COL_WIDTH-1:0] col [CFG_CTL_TBP_NUM-1:0];
reg [CFG_CTL_TBP_NUM-1:0] write;
reg [CFG_CTL_TBP_NUM-1:0] read;
wire [CFG_CTL_TBP_NUM-1:0] precharge;
wire [CFG_CTL_TBP_NUM-1:0] activate;
reg [CFG_INT_SIZE_WIDTH-1:0] size [CFG_CTL_TBP_NUM-1:0];
reg [CFG_CTL_TBP_NUM-1:0] autopch;
reg [CFG_LOCAL_ID_WIDTH-1:0] localid [CFG_CTL_TBP_NUM-1:0];
reg [CFG_DATA_ID_WIDTH-1:0] dataid [CFG_CTL_TBP_NUM-1:0];
reg [CFG_CTL_TBP_NUM-1:0] priority_a;
reg [CFG_CTL_TBP_NUM-1:0] activated;
reg [CFG_CTL_TBP_NUM-1:0] activated_p;
reg [CFG_CTL_TBP_NUM-1:0] activated_combi;
reg [CFG_CTL_TBP_NUM-1:0] precharged;
reg [CFG_CTL_TBP_NUM-1:0] precharged_combi;
reg [CFG_CTL_TBP_NUM-1:0] not_done_tbp_row_pass_flush;
reg [CFG_CTL_TBP_NUM-1:0] not_done_tbp_row_pass_flush_r;
reg [CFG_CTL_TBP_NUM-1:0] done_tbp_row_pass_flush;
reg [CFG_CTL_TBP_NUM-1:0] done_tbp_row_pass_flush_r;
reg [CFG_CTL_TBP_NUM-1:0] open_row_pass;
reg [CFG_CTL_TBP_NUM-1:0] open_row_pass_r;
wire [CFG_CTL_TBP_NUM-1:0] open_row_pass_flush;
reg [CFG_CTL_TBP_NUM-1:0] open_row_pass_flush_r;
reg [CFG_CTL_TBP_NUM-1:0] log2_open_row_pass_flush [CFG_CTL_TBP_NUM-1:0];
reg [CFG_CTL_TBP_NUM-1:0] log2_open_row_pass_flush_r [CFG_CTL_TBP_NUM-1:0];
reg [CFG_CTL_TBP_NUM-1:0] done;
reg [CFG_CTL_TBP_NUM-1:0] done_combi;
reg [CFG_CTL_TBP_NUM-1:0] complete;
reg [CFG_CTL_TBP_NUM-1:0] complete_rd;
reg [CFG_CTL_TBP_NUM-1:0] complete_wr;
reg [CFG_CTL_TBP_NUM-1:0] complete_combi;
reg [CFG_CTL_TBP_NUM-1:0] complete_combi_rd;
reg [CFG_CTL_TBP_NUM-1:0] complete_combi_wr;
reg [CFG_CTL_TBP_NUM-1:0] wst;
reg [CFG_CTL_TBP_NUM-1:0] wst_p;
reg [CFG_CTL_TBP_NUM-1:0] ssb;
reg [CFG_CTL_TBP_NUM-1:0] ssbr;
reg [CFG_CTL_TBP_NUM-1:0] ap;
reg [CFG_CTL_TBP_NUM-1:0] real_ap;
reg [CFG_CTL_TBP_NUM-1:0] rmw_correct;
reg [CFG_CTL_TBP_NUM-1:0] rmw_partial;
reg [CFG_CTL_TBP_NUM-1:0] require_flush;
reg [CFG_CTL_TBP_NUM-1:0] require_flush_calc;
reg [CFG_CTL_TBP_NUM-1:0] require_pch_combi [CFG_CTL_TBP_NUM-1:0];
reg [CFG_CTL_TBP_NUM-1:0] require_pch;
reg [CFG_CTL_TBP_NUM-1:0] burst_chop;
reg [CFG_CTL_TBP_NUM-1:0] age [CFG_CTL_TBP_NUM-1:0];
reg [CFG_PORT_WIDTH_STARVE_LIMIT-1:0] starvation [CFG_CTL_TBP_NUM-1:0];
// bit vectors
reg [CFG_CTL_TBP_NUM-1:0] apvo_combi; // vector for smart autopch open page
reg [CFG_CTL_TBP_NUM-1:0] apvo; // vector for smart autopch open page
reg [CFG_CTL_TBP_NUM-1:0] apvc_combi; // vector for smart autopch close page
reg [CFG_CTL_TBP_NUM-1:0] apvc; // vector for smart autopch close page
reg [CFG_CTL_TBP_NUM-1:0] rpv_combi [CFG_CTL_TBP_NUM-1:0];
reg [CFG_CTL_TBP_NUM-1:0] rpv [CFG_CTL_TBP_NUM-1:0];
reg [CFG_CTL_TBP_NUM-1:0] cpv_combi [CFG_CTL_TBP_NUM-1:0];
reg [CFG_CTL_TBP_NUM-1:0] cpv [CFG_CTL_TBP_NUM-1:0];
reg [CFG_CTL_TBP_NUM-1:0] wrt_combi [CFG_CTL_TBP_NUM-1:0];
reg [CFG_CTL_TBP_NUM-1:0] wrt [CFG_CTL_TBP_NUM-1:0];
reg [CFG_CTL_TBP_NUM-1:0] sbv_combi [CFG_CTL_TBP_NUM-1:0];
reg [CFG_CTL_TBP_NUM-1:0] sbv [CFG_CTL_TBP_NUM-1:0];
reg [CFG_CTL_TBP_NUM-1:0] sbvt_combi [CFG_CTL_TBP_NUM-1:0];
reg [CFG_CTL_TBP_NUM-1:0] sbvt [CFG_CTL_TBP_NUM-1:0];
reg [CFG_CTL_SHADOW_TBP_NUM-1:0] shadow_rpv_combi [CFG_CTL_TBP_NUM-1:0];
reg [CFG_CTL_SHADOW_TBP_NUM-1:0] shadow_rpv [CFG_CTL_TBP_NUM-1:0];
reg [CFG_CTL_SHADOW_TBP_NUM-1:0] shadow_sbvt_combi [CFG_CTL_TBP_NUM-1:0];
reg [CFG_CTL_SHADOW_TBP_NUM-1:0] shadow_sbvt [CFG_CTL_TBP_NUM-1:0];
reg [CFG_CTL_TBP_NUM-1:0] or_wrt;
reg [CFG_CTL_TBP_NUM-1:0] nor_rpv;
reg [CFG_CTL_TBP_NUM-1:0] nor_cpv;
reg [CFG_CTL_TBP_NUM-1:0] nor_wrt;
reg [CFG_CTL_TBP_NUM-1:0] nor_sbv;
reg [CFG_CTL_TBP_NUM-1:0] nor_sbvt;
wire [CFG_CTL_TBP_NUM-1:0] tbp_read;
wire [CFG_CTL_TBP_NUM-1:0] tbp_write;
wire [CFG_CTL_TBP_NUM-1:0] tbp_ap;
wire [(CFG_CTL_TBP_NUM*CFG_MEM_IF_CS_WIDTH)-1:0] tbp_chipsel;
wire [(CFG_CTL_TBP_NUM*CFG_MEM_IF_BA_WIDTH)-1:0] tbp_bank;
wire [(CFG_CTL_TBP_NUM*CFG_MEM_IF_ROW_WIDTH)-1:0] tbp_row;
wire [(CFG_CTL_TBP_NUM*CFG_MEM_IF_COL_WIDTH)-1:0] tbp_col;
wire [(CFG_CTL_SHADOW_TBP_NUM*CFG_MEM_IF_CS_WIDTH)-1:0] tbp_shadow_chipsel;
wire [(CFG_CTL_SHADOW_TBP_NUM*CFG_MEM_IF_BA_WIDTH)-1:0] tbp_shadow_bank;
wire [(CFG_CTL_SHADOW_TBP_NUM*CFG_MEM_IF_ROW_WIDTH)-1:0] tbp_shadow_row;
wire [(CFG_CTL_TBP_NUM*CFG_INT_SIZE_WIDTH)-1:0] tbp_size;
wire [(CFG_CTL_TBP_NUM*CFG_LOCAL_ID_WIDTH)-1:0] tbp_localid;
wire [(CFG_CTL_TBP_NUM*CFG_DATA_ID_WIDTH)-1:0] tbp_dataid;
wire [(CFG_CTL_TBP_NUM*CFG_CTL_TBP_NUM)-1:0] tbp_age;
wire [CFG_CTL_TBP_NUM-1:0] tbp_priority;
wire [CFG_CTL_TBP_NUM-1:0] tbp_rmw_correct;
wire [CFG_CTL_TBP_NUM-1:0] tbp_rmw_partial;
wire [CFG_MEM_IF_CHIP-1:0] tbp_bank_active;
wire [CFG_MEM_IF_CHIP-1:0] tbp_timer_ready;
reg [CFG_MEM_IF_CHIP-1:0] bank_active;
reg [CFG_MEM_IF_CHIP-1:0] timer_ready;
reg [CFG_CTL_TBP_NUM-1:0] int_bank_active [CFG_MEM_IF_CHIP-1:0];
reg [CFG_CTL_TBP_NUM-1:0] int_timer_ready [CFG_MEM_IF_CHIP-1:0];
reg [CFG_CTL_SHADOW_TBP_NUM-1:0] int_shadow_timer_ready [CFG_MEM_IF_CHIP-1:0];
reg [CFG_CTL_TBP_NUM-1:0] same_command_read;
reg [CFG_CTL_TBP_NUM-1:0] same_chip_bank_row;
reg [CFG_CTL_TBP_NUM-1:0] same_chip_bank_diff_row;
reg [CFG_CTL_TBP_NUM-1:0] same_chip_bank;
reg [CFG_CTL_SHADOW_TBP_NUM-1:0] same_shadow_command_read;
reg [CFG_CTL_SHADOW_TBP_NUM-1:0] same_shadow_chip_bank_row;
reg [CFG_CTL_SHADOW_TBP_NUM-1:0] same_shadow_chip_bank_diff_row;
reg [CFG_CTL_SHADOW_TBP_NUM-1:0] same_shadow_chip_bank;
reg [CFG_CTL_TBP_NUM-1:0] pre_calculated_same_chip_bank_diff_row [CFG_CTL_TBP_NUM-1:0];
reg [CFG_CTL_TBP_NUM-1:0] pre_calculated_same_chip_bank_row [CFG_CTL_TBP_NUM-1:0];
reg [CFG_CTL_TBP_NUM-1:0] pre_calculated_same_chip_bank [CFG_CTL_TBP_NUM-1:0];
reg [CFG_CTL_SHADOW_TBP_NUM-1:0] pre_calculated_same_shadow_chip_bank [CFG_CTL_TBP_NUM-1:0];
reg [COL_TIMER_WIDTH-1:0] col_timer [CFG_CTL_TBP_NUM-1:0];
reg [CFG_CTL_TBP_NUM-1:0] col_timer_ready;
reg [CFG_CTL_TBP_NUM-1:0] col_timer_pre_ready;
reg [ROW_TIMER_WIDTH-1:0] row_timer_combi [CFG_CTL_TBP_NUM-1:0];
reg [ROW_TIMER_WIDTH-1:0] row_timer [CFG_CTL_TBP_NUM-1:0];
reg [CFG_CTL_TBP_NUM-1:0] row_timer_ready;
reg [CFG_CTL_TBP_NUM-1:0] row_timer_pre_ready;
reg [TRC_TIMER_WIDTH-1:0] trc_timer [CFG_CTL_TBP_NUM-1:0];
reg [CFG_CTL_TBP_NUM-1:0] trc_timer_ready;
reg [CFG_CTL_TBP_NUM-1:0] trc_timer_pre_ready;
reg [CFG_CTL_TBP_NUM-1:0] trc_timer_pre_ready_combi;
reg [CFG_CTL_TBP_NUM-1:0] pch_ready;
reg [CFG_CTL_TBP_NUM-1:0] compare_t_param_rd_ap_to_valid_greater_than_trc_timer;
reg [CFG_CTL_TBP_NUM-1:0] compare_t_param_wr_ap_to_valid_greater_than_trc_timer;
reg [CFG_CTL_TBP_NUM-1:0] compare_t_param_rd_to_pch_greater_than_row_timer;
reg [CFG_CTL_TBP_NUM-1:0] compare_t_param_wr_to_pch_greater_than_row_timer;
reg compare_t_param_act_to_rdwr_less_than_offset;
reg compare_t_param_act_to_act_less_than_offset;
reg compare_t_param_act_to_pch_less_than_offset;
reg compare_t_param_rd_to_pch_less_than_offset;
reg compare_t_param_wr_to_pch_less_than_offset;
reg compare_t_param_pch_to_valid_less_than_offset;
reg compare_t_param_rd_ap_to_valid_less_than_offset;
reg compare_t_param_wr_ap_to_valid_less_than_offset;
reg compare_offset_t_param_act_to_rdwr_less_than_0;
reg compare_offset_t_param_act_to_rdwr_less_than_1;
reg [T_PARAM_ACT_TO_RDWR_WIDTH-1:0] offset_t_param_act_to_rdwr;
reg [T_PARAM_ACT_TO_ACT_WIDTH-1:0] offset_t_param_act_to_act;
reg [T_PARAM_ACT_TO_PCH_WIDTH-1:0] offset_t_param_act_to_pch;
reg [T_PARAM_RD_TO_PCH_WIDTH-1:0] offset_t_param_rd_to_pch;
reg [T_PARAM_WR_TO_PCH_WIDTH-1:0] offset_t_param_wr_to_pch;
reg [T_PARAM_PCH_TO_VALID_WIDTH-1:0] offset_t_param_pch_to_valid;
reg [T_PARAM_RD_AP_TO_VALID_WIDTH-1:0] offset_t_param_rd_ap_to_valid;
reg [T_PARAM_WR_AP_TO_VALID_WIDTH-1:0] offset_t_param_wr_ap_to_valid;
reg [CFG_CTL_TBP_NUM-1:0] can_act;
reg [CFG_CTL_TBP_NUM-1:0] can_pch;
reg [CFG_CTL_TBP_NUM-1:0] can_rd;
reg [CFG_CTL_TBP_NUM-1:0] can_wr;
reg [CFG_CTL_TBP_NUM-1:0] finish_tbp;
wire [CFG_CTL_SHADOW_TBP_NUM-1:0] flush_shadow_tbp;
reg [CFG_CTL_SHADOW_TBP_NUM-1:0] push_tbp_combi;
reg [CFG_CTL_SHADOW_TBP_NUM-1:0] push_tbp;
reg [CFG_CTL_SHADOW_TBP_NUM-1:0] ready_to_push_tbp_combi;
reg [CFG_CTL_SHADOW_TBP_NUM-1:0] ready_to_push_tbp;
reg [CFG_CTL_SHADOW_TBP_NUM-1:0] shadow_valid;
reg [CFG_MEM_IF_CS_WIDTH-1:0] shadow_chipsel [CFG_CTL_SHADOW_TBP_NUM-1:0];
reg [CFG_MEM_IF_BA_WIDTH-1:0] shadow_bank [CFG_CTL_SHADOW_TBP_NUM-1:0];
reg [CFG_MEM_IF_ROW_WIDTH-1:0] shadow_row [CFG_CTL_SHADOW_TBP_NUM-1:0];
reg [ROW_TIMER_WIDTH-1:0] shadow_row_timer [CFG_CTL_SHADOW_TBP_NUM-1:0];
reg [CFG_CTL_SHADOW_TBP_NUM-1:0] shadow_row_timer_pre_ready;
reg [CFG_CTL_SHADOW_TBP_NUM-1:0] shadow_row_timer_ready;
wire one = 1'b1;
wire zero = 1'b0;
integer i;
integer j;
genvar k;
//----------------------------------------------------------------------------------------------------
// Output port assignments
//----------------------------------------------------------------------------------------------------
assign tbp_read = read;
assign tbp_write = write;
assign tbp_ap = real_ap;
assign tbp_burst_chop = burst_chop;
assign tbp_precharge = precharge;
assign tbp_activate = activate;
assign tbp_priority = priority_a;
assign tbp_rmw_correct = rmw_correct;
assign tbp_rmw_partial = rmw_partial;
generate
begin
for(k=0; k<CFG_CTL_TBP_NUM; k=k+1)
begin : tbp_name
assign tbp_chipsel[(k*CFG_MEM_IF_CS_WIDTH)+CFG_MEM_IF_CS_WIDTH-1:k*CFG_MEM_IF_CS_WIDTH] = chipsel[k];
assign tbp_bank [(k*CFG_MEM_IF_BA_WIDTH)+CFG_MEM_IF_BA_WIDTH-1:k*CFG_MEM_IF_BA_WIDTH] = bank [k];
assign tbp_row [(k*CFG_MEM_IF_ROW_WIDTH)+CFG_MEM_IF_ROW_WIDTH-1:k*CFG_MEM_IF_ROW_WIDTH] = row [k];
assign tbp_col [(k*CFG_MEM_IF_COL_WIDTH)+CFG_MEM_IF_COL_WIDTH-1:k*CFG_MEM_IF_COL_WIDTH] = col [k];
assign tbp_localid[(k*CFG_LOCAL_ID_WIDTH)+CFG_LOCAL_ID_WIDTH-1:k*CFG_LOCAL_ID_WIDTH] = localid[k];
assign tbp_dataid [(k*CFG_DATA_ID_WIDTH)+CFG_DATA_ID_WIDTH-1:k*CFG_DATA_ID_WIDTH] = dataid [k];
assign tbp_age [(k*CFG_CTL_TBP_NUM)+CFG_CTL_TBP_NUM-1:k*CFG_CTL_TBP_NUM] = age [k];
assign tbp_size [(k*CFG_INT_SIZE_WIDTH)+CFG_INT_SIZE_WIDTH-1:k*CFG_INT_SIZE_WIDTH] = size [k];
end
for(k=0; k<CFG_CTL_SHADOW_TBP_NUM; k=k+1)
begin : tbp_shadow_name
if (CFG_ENABLE_SHADOW_TBP)
begin
assign tbp_shadow_chipsel[(k*CFG_MEM_IF_CS_WIDTH)+CFG_MEM_IF_CS_WIDTH-1:k*CFG_MEM_IF_CS_WIDTH] = shadow_chipsel[k];
assign tbp_shadow_bank [(k*CFG_MEM_IF_BA_WIDTH)+CFG_MEM_IF_BA_WIDTH-1:k*CFG_MEM_IF_BA_WIDTH] = shadow_bank [k];
assign tbp_shadow_row [(k*CFG_MEM_IF_ROW_WIDTH)+CFG_MEM_IF_ROW_WIDTH-1:k*CFG_MEM_IF_ROW_WIDTH] = shadow_row [k];
end
else
begin
assign tbp_shadow_chipsel[(k*CFG_MEM_IF_CS_WIDTH)+CFG_MEM_IF_CS_WIDTH-1:k*CFG_MEM_IF_CS_WIDTH] = 0;
assign tbp_shadow_bank [(k*CFG_MEM_IF_BA_WIDTH)+CFG_MEM_IF_BA_WIDTH-1:k*CFG_MEM_IF_BA_WIDTH] = 0;
assign tbp_shadow_row [(k*CFG_MEM_IF_ROW_WIDTH)+CFG_MEM_IF_ROW_WIDTH-1:k*CFG_MEM_IF_ROW_WIDTH] = 0;
end
end
end
endgenerate
assign tbp_full = int_tbp_full;
assign tbp_empty = int_tbp_empty;
assign int_tbp_empty = &(valid ^~ done); // empty if valid and done are the same
assign load_tbp = (~int_tbp_full & cmd_gen_load) ? load_tbp_index : 0;
assign flush_tbp = open_row_pass_flush_r | finish_tbp | (done & precharge_tbp);
assign tbp_load = load_tbp;
assign tbp_bank_active = bank_active;
assign tbp_timer_ready = timer_ready;
assign precharge = activated;
assign activate = ~activated;
//----------------------------------------------------------------------------------------------------
// TBP General Functions
//----------------------------------------------------------------------------------------------------
assign valid_combi = (valid | load_tbp) & ~flush_tbp;
// Decide which TBP to load
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
load_tbp_index <= 0;
end
else
begin
load_tbp_index <= ~valid_combi & (valid_combi + 1);
end
end
// Assert when TBP is full to prevent further load
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_tbp_full <= 0;
end
else
begin
int_tbp_full <= &valid_combi;
end
end
//----------------------------------------------------------------------------------------------------
// Finish TBP
//----------------------------------------------------------------------------------------------------
// Logic to determine when can we flush a done TBP
// in non-shadow TBP case, we can only flush once the timer finished counting
// in shadow TBP case, we can flush once it is pushed into shadow TBP
always @ (*)
begin
for (i=0; i<CFG_CTL_SHADOW_TBP_NUM; i=i+1)
begin
if (CFG_ENABLE_SHADOW_TBP)
begin
finish_tbp[i] = push_tbp[i] | (done[i] & precharged[i] & row_timer_pre_ready[i]);
end
else
begin
finish_tbp[i] = done[i] & precharged[i] & row_timer_pre_ready[i];
end
end
end
//----------------------------------------------------------------------------------------------------
// Shadow TBP Logic
//----------------------------------------------------------------------------------------------------
// Determine when can we flush TBP
assign flush_shadow_tbp = shadow_valid & shadow_row_timer_pre_ready;
// Determine when it's ready to push into shadow TBP
always @ (*)
begin
for (i=0; i<CFG_CTL_SHADOW_TBP_NUM; i=i+1)
begin
if (CFG_ENABLE_SHADOW_TBP)
begin
if (flush_tbp[i]) // TBP might flush before shadow TBP is still allocated
begin
ready_to_push_tbp_combi[i] = 1'b0;
end
else if (push_tbp[i]) // we want push_tbp to pulse for one clock cycle only
begin
ready_to_push_tbp_combi[i] = 1'b0;
end
else if ((col_grant[i] && real_ap[i]) || (pch_grant[i] && done[i])) // indicate ready to push TBP once TBP is done
begin
ready_to_push_tbp_combi[i] = 1'b1;
end
else
begin
ready_to_push_tbp_combi[i] = ready_to_push_tbp[i];
end
end
else
begin
ready_to_push_tbp_combi[i] = zero;
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_SHADOW_TBP_NUM; i=i+1)
begin
ready_to_push_tbp[i] <= 1'b0;
end
end
else
begin
for (i=0; i<CFG_CTL_SHADOW_TBP_NUM; i=i+1)
begin
ready_to_push_tbp[i] <= ready_to_push_tbp_combi[i];
end
end
end
// Determine when to push into shadow TBP
always @ (*)
begin
for (i=0; i<CFG_CTL_SHADOW_TBP_NUM; i=i+1)
begin
if (CFG_ENABLE_SHADOW_TBP)
begin
if (push_tbp[i]) // we want push_tbp to pulse for one clock cycle only
begin
push_tbp_combi[i] = 1'b0;
end
else if (ready_to_push_tbp_combi[i] && shadow_row_timer_pre_ready[i]) // prevent pushing into an allocated shadow TBP
begin
push_tbp_combi[i] = 1'b1;
end
else
begin
push_tbp_combi[i] = push_tbp[i];
end
end
else
begin
push_tbp_combi[i] = zero;
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_SHADOW_TBP_NUM; i=i+1)
begin
push_tbp[i] <= 1'b0;
end
end
else
begin
for (i=0; i<CFG_CTL_SHADOW_TBP_NUM; i=i+1)
begin
push_tbp[i] <= push_tbp_combi[i];
end
end
end
// Shadow TBP information
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_SHADOW_TBP_NUM; i=i+1)
begin
shadow_chipsel[i] <= 0;
shadow_bank [i] <= 0;
shadow_row [i] <= 0;
end
end
else
begin
for (i=0; i<CFG_CTL_SHADOW_TBP_NUM; i=i+1)
begin
if (CFG_ENABLE_SHADOW_TBP)
begin
if (push_tbp_combi[i])
begin
shadow_chipsel[i] <= chipsel[i];
shadow_bank [i] <= bank [i];
shadow_row [i] <= row [i];
end
end
else
begin
shadow_chipsel[i] <= 0;
shadow_bank [i] <= 0;
shadow_row [i] <= 0;
end
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_SHADOW_TBP_NUM; i=i+1)
begin
shadow_valid[i] <= 1'b0;
end
end
else
begin
for (i=0; i<CFG_CTL_SHADOW_TBP_NUM; i=i+1)
begin
if (CFG_ENABLE_SHADOW_TBP)
begin
if (flush_shadow_tbp[i])
begin
shadow_valid[i] <= 1'b0;
end
else if (push_tbp[i])
begin
shadow_valid[i] <= 1'b1;
end
end
else
begin
shadow_valid[i] <= 1'b0;
end
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_SHADOW_TBP_NUM; i=i+1)
begin
shadow_row_timer [i] <= 0;
shadow_row_timer_pre_ready[i] <= 1'b0;
shadow_row_timer_ready [i] <= 1'b0;
end
end
else
begin
for (i=0; i<CFG_CTL_SHADOW_TBP_NUM; i=i+1)
begin
if (CFG_ENABLE_SHADOW_TBP)
begin
if (push_tbp[i])
begin
if (!row_timer_pre_ready[i] || !trc_timer_pre_ready[i])
begin
// Decide to take the larger timer value between row/trc timer
if (row_timer[i] > trc_timer[i])
begin
shadow_row_timer[i] <= row_timer[i] - 1'b1;
end
else
begin
shadow_row_timer[i] <= trc_timer[i] - 1'b1;
end
shadow_row_timer_pre_ready[i] <= 1'b0;
shadow_row_timer_ready [i] <= 1'b0;
end
else
begin
shadow_row_timer [i] <= 0;
shadow_row_timer_pre_ready[i] <= 1'b1;
shadow_row_timer_ready [i] <= 1'b1;
end
end
else
begin
if (shadow_row_timer[i] != 0)
begin
shadow_row_timer[i] <= shadow_row_timer[i] - 1'b1;
end
if (shadow_row_timer[i] <= 1)
begin
shadow_row_timer_ready[i] <= 1'b1;
end
if (shadow_row_timer[i] <= 2)
begin
shadow_row_timer_pre_ready[i] <= 1'b1;
end
end
end
else
begin
shadow_row_timer [i] <= 0;
shadow_row_timer_pre_ready[i] <= 1'b0;
shadow_row_timer_ready [i] <= 1'b0;
end
end
end
end
//----------------------------------------------------------------------------------------------------
// Request logic
//----------------------------------------------------------------------------------------------------
// Can_* logic for request logic, indicate whether TBP can request now
// Can activate
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
can_act[i] <= 1'b0;
end
end
else
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
if (activated_combi[i]) // activated, so there is no need to enable activate again
begin
can_act[i] <= 1'b0;
end
else if (col_grant[i]) //done, there is no need to enable activate again
begin
can_act[i] <= 1'b0;
end
else if (load_tbp[i]) // new TBP command, assume no open-row-pass (handled by statement above)
begin
can_act[i] <= 1'b1;
end
else if
(
!done[i] && valid[i] &&
(
( cfg_reorder_data && CFG_DATA_REORDERING_TYPE == "INTER_ROW" && (precharge_tbp[i] || pch_grant[i])) ||
( cfg_reorder_data && CFG_DATA_REORDERING_TYPE == "INTER_BANK" && (precharge_tbp[i] )) ||
(!cfg_reorder_data && precharge_tbp[i])
)
)
// precharge or precharge all command, re-enable since it is not done
// (INTER_ROW) we need to validate pch_grant because precharge might happen to a newly loaded TBP due to TBP interlock case (see require_pch logic)
begin
can_act[i] <= 1'b1;
end
end
end
end
// Can precharge
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
can_pch[i] <= 1'b0;
end
end
else
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
can_pch[i] <= one; // there is no logic required for precharge, keeping this for future use
end
end
end
// Can read
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
can_rd[i] <= 1'b0;
end
end
else
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
if (col_grant[i] || done[i]) // done, there is no need to enable read again
begin
can_rd[i] <= 1'b0;
end
else if
(
( cfg_reorder_data && CFG_DATA_REORDERING_TYPE == "INTER_ROW" && (precharge_tbp[i] || pch_grant[i])) ||
( cfg_reorder_data && CFG_DATA_REORDERING_TYPE == "INTER_BANK" && (precharge_tbp[i] )) ||
(!cfg_reorder_data && precharge_tbp[i])
)
// precharge or precharge all command, can't read since bank is not active
// (INTER_ROW) we need to validate pch_grant because precharge might happen to a newly loaded TBP due to TBP interlock case (see require_pch logic)
begin
can_rd[i] <= 1'b0;
end
else if (((act_grant[i] && compare_t_param_act_to_rdwr_less_than_offset) || open_row_pass[i] || activated[i]) && col_timer_pre_ready[i]) // activated and timer is ready
begin
can_rd[i] <= 1'b1;
end
end
end
end
// Can write
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
can_wr[i] <= 1'b0;
end
end
else
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
if (col_grant[i] || done[i]) // done, there is no need to enable read again
begin
can_wr[i] <= 1'b0;
end
else if
(
( cfg_reorder_data && CFG_DATA_REORDERING_TYPE == "INTER_ROW" && (precharge_tbp[i] || pch_grant[i])) ||
( cfg_reorder_data && CFG_DATA_REORDERING_TYPE == "INTER_BANK" && (precharge_tbp[i] )) ||
(!cfg_reorder_data && precharge_tbp[i])
)
// precharge or precharge all command, can't write since bank is not active
// (INTER_ROW) we need to validate pch_grant because precharge might happen to a newly loaded TBP due to TBP interlock case (see require_pch logic)
begin
can_wr[i] <= 1'b0;
end
else if (((act_grant[i] && compare_t_param_act_to_rdwr_less_than_offset) || open_row_pass[i] || activated[i]) && col_timer_pre_ready[i]) // activated and timer is ready
begin
can_wr[i] <= 1'b1;
end
end
end
end
// Row request
always @(*)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
row_req[i] = act_req[i] | pch_req[i];
end
end
// Column request
always @(*)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
col_req[i] = rd_req[i] | wr_req[i];
end
end
// Individual activate, precharge, read and write request logic
always @ (*)
begin
for (i = 0;i < CFG_CTL_TBP_NUM;i = i + 1)
begin
act_req[i] = nor_rpv[i] & nor_sbv[i] & nor_sbvt[i] & ~or_wrt[i] & can_act[i];
pch_req[i] = require_pch[i] & pch_ready[i] & can_pch[i];
rd_req [i] = nor_cpv[i] & can_rd[i] & complete_rd[i];
wr_req [i] = nor_cpv[i] & can_wr[i] & complete_wr[i];
end
end
//----------------------------------------------------------------------------------------------------
// Valid logic
//----------------------------------------------------------------------------------------------------
// Indicates that current TBP is valid after load an invalid after flush
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
valid[i] <= 1'b0;
end
end
else
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
if (load_tbp[i])
begin
valid[i] <= 1'b1;
end
else if (flush_tbp[i])
begin
valid[i] <= 1'b0;
end
end
end
end
//----------------------------------------------------------------------------------------------------
// TBP information
//----------------------------------------------------------------------------------------------------
// Keeps information from cmd_gen after load
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
chipsel [i] <= 0;
bank [i] <= 0;
row [i] <= 0;
col [i] <= 0;
write [i] <= 0;
read [i] <= 0;
size [i] <= 0;
autopch [i] <= 0;
localid [i] <= 0;
dataid [i] <= 0;
rmw_correct[i] <= 0;
rmw_partial[i] <= 0;
end
else
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
if (load_tbp[i])
begin
chipsel [i] <= cmd_gen_chipsel;
bank [i] <= cmd_gen_bank;
row [i] <= cmd_gen_row;
col [i] <= cmd_gen_col;
write [i] <= cmd_gen_write;
read [i] <= cmd_gen_read;
size [i] <= cmd_gen_size;
autopch [i] <= cmd_gen_autopch;
localid [i] <= cmd_gen_localid;
dataid [i] <= cmd_gen_dataid;
rmw_correct[i] <= cmd_gen_rmw_correct;
rmw_partial[i] <= cmd_gen_rmw_partial;
end
end
end
// Priority information
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
priority_a[i] <= 1'b0;
end
else
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
if (CFG_DISABLE_PRIORITY == 1)
begin
priority_a[i] <= zero;
end
else
begin
if (load_tbp[i])
begin
if (cfg_reorder_data) // priority will be ignored when data reordering is OFF
begin
priority_a[i] <= cmd_gen_priority;
end
else
begin
priority_a[i] <= 1'b0;
end
end
else if (starvation[i] == cfg_starve_limit) // assert priority when starvation limit is reached
begin
priority_a[i] <= 1'b1;
end
end
end
end
//----------------------------------------------------------------------------------------------------
// Row dependency vector
//----------------------------------------------------------------------------------------------------
// RPV, TBP is only allowed to request row command when RPV is all zero, meaning no dependencies on other TBPs
always @(*)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
for (j=0; j<CFG_CTL_TBP_NUM; j=j+1)
begin
if (load_tbp[i])
begin
if
(
!flush_tbp[j] && !push_tbp[j] &&
(
( cfg_reorder_data && CFG_DATA_REORDERING_TYPE == "INTER_ROW" && valid[j] && (same_chip_bank_row[j] || (same_chip_bank[j] && (rmw_partial[j] || rmw_correct[j])))) ||
( cfg_reorder_data && CFG_DATA_REORDERING_TYPE == "INTER_BANK" && valid[j] && same_chip_bank[j]) ||
(!cfg_reorder_data && valid[j] && same_chip_bank[j])
)
)
// (INTER_ROW) Set RPV to '1' when a new TBP has same-chip-bank-row address with any other existing TBPs
// (INTER_ROW) Set RPV to '1' when existing TBP is a RMW command, we don't allow reordering between RMW commands
// This is to prevent activate going to the later RMW commands
// (INTER_BANK) Set RPV to '1' when a new TBP has same-chip-bank address with any other existing TBPs
// (NON_REORDER) Set RPV to '1' when a new TBP has same-chip-bank address with any other existing TBPs, to allow command reordering
begin
rpv_combi[i][j] = 1'b1;
end
else
begin
rpv_combi[i][j] = 1'b0;
end
end
else if (flush_tbp[j] || push_tbp[j])
// (INTER_ROW) Set RPV to '0' after flush
// (INTER_BANK) Set RPV to '0' after flush
begin
rpv_combi[i][j] = 1'b0;
end
else
begin
rpv_combi[i][j] = rpv[i][j];
end
end
end
end
always @ (*)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
for (j=0; j<CFG_CTL_SHADOW_TBP_NUM; j=j+1)
begin
if (CFG_ENABLE_SHADOW_TBP)
begin
if (load_tbp[i])
begin
if (!flush_shadow_tbp[j] && ((shadow_valid[j] && same_shadow_chip_bank[j]) || (push_tbp[j] && same_chip_bank[j])))
// Set Shadow RPV to '1' when a new TBP has same-chip-bank address with any other existing TBPs
begin
shadow_rpv_combi[i][j] = 1'b1;
end
else
begin
shadow_rpv_combi[i][j] = 1'b0;
end
end
else if (push_tbp[j] && rpv[i][j])
// If there is a push_tbp and RPV is set to '1'
// We need to shift RPV to Shadow RPV
begin
shadow_rpv_combi[i][j] = 1'b1;
end
else if (flush_shadow_tbp[j])
// (INTER_ROW) Set RPV to '0' after flush
// (INTER_BANK) Set RPV to '0' after flush
begin
shadow_rpv_combi[i][j] = 1'b0;
end
else
begin
shadow_rpv_combi[i][j] = shadow_rpv[i][j];
end
end
else
begin
shadow_rpv_combi[i][j] = zero;
end
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
nor_rpv[i] <= 1'b0;
for (j=0; j<CFG_CTL_TBP_NUM; j=j+1)
begin
rpv[i][j] <= 1'b0;
end
end
end
else
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
nor_rpv[i] <= ~|{shadow_rpv_combi[i], rpv_combi[i]};
for (j=0; j<CFG_CTL_TBP_NUM; j=j+1)
begin
if (i == j) // Hard-coded to '0' for own vector bit, since we only need to know the dependencies for other TBPs not ourself
begin
rpv[i][j] <= 1'b0;
end
else
begin
rpv[i][j] <= rpv_combi[i][j];
end
end
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
for (j=0; j<CFG_CTL_SHADOW_TBP_NUM; j=j+1)
begin
shadow_rpv[i][j] <= 1'b0;
end
end
end
else
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
for (j=0; j<CFG_CTL_SHADOW_TBP_NUM; j=j+1)
begin
shadow_rpv[i][j] <= shadow_rpv_combi[i][j];
end
end
end
end
//----------------------------------------------------------------------------------------------------
// Column dependency vector
//----------------------------------------------------------------------------------------------------
// CPV, TBP is only allowed to request column command when CPV is all zero, meaning no dependencies on other TBPs
always @(*)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
for (j=0; j<CFG_CTL_TBP_NUM; j=j+1)
begin
if (load_tbp[i])
begin
if
(
!flush_tbp[j] && !col_grant[j] &&
(
( cfg_reorder_data && CFG_DATA_REORDERING_TYPE == "INTER_ROW" && valid[j] && !done[j] && (priority_a[j] || same_chip_bank_row[j] || rmw_partial[j] || rmw_correct[j] || same_command_read[j])) ||
( cfg_reorder_data && CFG_DATA_REORDERING_TYPE == "INTER_BANK" && valid[j] && !done[j] && (priority_a[j] || same_chip_bank [j] || rmw_partial[j] || rmw_correct[j] || same_command_read[j])) ||
(!cfg_reorder_data && valid[j] && !done[j])
)
)
// (INTER_ROW) Set CPV to '1' when a new TBP has same-chip-bank-row address with any other existing TBPs
// (INTER_ROW) Set CPV to '1' when existing TBP is a RMW command, we don't allow reordering between RMW commands
// (INTER_ROW) Set CPV to '1' when existing TBP is a priority command, we don't want new TBP to take over priority command
// (INTER_BANK) Set CPV to '1' when a new TBP has same-chip-bank address with any other existing TBPs
// (INTER_BANK) Set CPV to '1' when existing TBP is a RMW command, we don't allow reordering between RMW commands
// (INTER_BANK) Set CPV to '1' when existing TBP is a priority command, we don't want new TBP to take over priority command
// (NON_REORDER) Set CPV to '1' when a new TBP is loaded, all column command must be executed in order
begin
cpv_combi[i][j] = 1'b1;
end
else
begin
cpv_combi[i][j] = 1'b0;
end
end
else if (col_grant[j])
// (INTER_ROW) Set CPV to '0' after col_grant
// (INTER_BANK) Set CPV to '0' after col_grant
begin
cpv_combi[i][j] = 1'b0;
end
else
begin
cpv_combi[i][j] = cpv[i][j];
end
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
nor_cpv[i] <= 1'b0;
for (j=0; j<CFG_CTL_TBP_NUM; j=j+1)
begin
cpv[i][j] <= 1'b0;
end
end
end
else
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
nor_cpv[i] <= ~|cpv_combi[i];
for (j=0; j<CFG_CTL_TBP_NUM; j=j+1)
begin
if (i == j) // Hard-coded to '0' for own vector bit, since we only need to know the dependencies for other TBPs not ourself
begin
cpv[i][j] <= 1'b0;
end
else
begin
cpv[i][j] <= cpv_combi[i][j];
end
end
end
end
end
//----------------------------------------------------------------------------------------------------
// Activate related logic
//----------------------------------------------------------------------------------------------------
// Open-row-pass flush logic
// after a granted command and WST (open row pass to another TBP with same page from just granted command) OR
// after a done command and WST (open row pass to another TBP with same page from a done command with page open)
// Logic to determine which not-done TBP should be flushed to perform open-row-pass
always @ (*)
begin
not_done_tbp_row_pass_flush = col_grant & wst_p;
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
not_done_tbp_row_pass_flush_r[i] <= 1'b0;
end
end
else
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
not_done_tbp_row_pass_flush_r[i] <= not_done_tbp_row_pass_flush[i];
end
end
end
// Logic to determine which done TBP should be flushed to perform open-row-pass
always @ (*)
begin
done_tbp_row_pass_flush = done & wst_p & ~row_grant & ~precharge_tbp;
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
done_tbp_row_pass_flush_r[i] <= 1'b0;
end
end
else
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
if (done_tbp_row_pass_flush_r[i])
begin
done_tbp_row_pass_flush_r[i] <= 1'b0;
end
else
begin
done_tbp_row_pass_flush_r[i] <= done_tbp_row_pass_flush[i];
end
end
end
end
// Using done_tbp_row_pass_flush_r to improve timing
// it's acceptable to add one clock cycle latency when performing open-row-pass from a done command
// [REMARK] there is potential to optimize the flush logic (for done-open-row-pass case), because flush_tbp depends on open_row_pass_flush logic
assign open_row_pass_flush = not_done_tbp_row_pass_flush | done_tbp_row_pass_flush;
// Open-row-pass logic, TBP will pass related information to same page command (increase efficiency)
always @ (*)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
open_row_pass[i] = |open_row_pass_flush && or_wrt[i] && |(wrt[i] & open_row_pass_flush);
end
end
// Registered version
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
open_row_pass_r [i] <= 1'b0;
open_row_pass_flush_r[i] <= 1'b0;
end
end
else
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
open_row_pass_r [i] <= open_row_pass [i];
open_row_pass_flush_r[i] <= open_row_pass_flush[i];
end
end
end
// Activated logic
// indicate that current TBP is activated by activate command or open-row-pass
always @(*)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
if (act_grant[i] || open_row_pass[i])
begin
activated_combi[i] = 1'b1;
end
else
begin
activated_combi[i] = 1'b0;
end
end
end
// activated need not to be validated with valid
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
activated [i] <= 1'b0;
activated_p[i] <= 1'b0;
end
end
else
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
activated_p[i] <= activated_combi[i]; // activated pulse
if (flush_tbp[i] || pch_grant[i])
begin
activated[i] <= 1'b0;
end
else if (precharge_tbp[i])
begin
activated[i] <= 1'b0;
end
else if (activated_combi[i])
begin
activated[i] <= 1'b1;
end
end
end
//----------------------------------------------------------------------------------------------------
// Precharge related logic
//----------------------------------------------------------------------------------------------------
// Precharge all logic
// indicate which TBP is precharged cause of sideband precharge all command
always @(*)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
precharge_tbp[i] = sb_tbp_precharge_all[i];
end
end
// Precharge logic
// indicate which TBP is precharged
always @ (*)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
if (load_tbp[i])
begin
precharged_combi[i] = 1'b0;
end
else if (activated_combi[i] && cfg_reorder_data && CFG_DATA_REORDERING_TYPE == "INTER_ROW")
// Only required in INTER-ROW reordering case since TBP might request precharge after TBP load
// due to TBP interlock case
begin
precharged_combi[i] = 1'b0;
end
else if (col_grant[i] && real_ap[i])
begin
precharged_combi[i] = 1'b1;
end
else if (pch_grant[i])
begin
precharged_combi[i] = 1'b1;
end
else
begin
precharged_combi[i] = precharged[i];
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
precharged[i] <= 1'b0;
end
end
else
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
precharged[i] <= precharged_combi[i];
end
end
end
//----------------------------------------------------------------------------------------------------
// Auto-precharge related logic
//----------------------------------------------------------------------------------------------------
// Auto precharge related logic, to determine which TBP should be closed or kept open
// OPP - autoprecharge when there is another command to same chip-bank different row
// CPP - do not autoprecharge when there is another command to the same chip-bank-row
always @ (*)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
if (flush_tbp[i])
begin
apvo_combi[i] = 1'b0;
apvc_combi[i] = 1'b0;
end
else if
(
(load_tbp[i] && CFG_DATA_REORDERING_TYPE == "INTER_ROW") || // load self
(
(|load_tbp && !load_tbp[i]) && // load other TBP
(
( cfg_reorder_data && CFG_DATA_REORDERING_TYPE == "INTER_ROW") ||
( cfg_reorder_data && CFG_DATA_REORDERING_TYPE == "INTER_BANK" && !ssb[i]) ||
(!cfg_reorder_data && !ssb[i])
)
)
)
// (INTER_ROW) update multiple times whenever there is a load so that it'll get the latest AP info
// (INTER_BANK) only update this once after same chip-bank command is loaded, masked by SSB (seen same bank)
// (NON_REORDER) only update this once after same chip-bank command is loaded, masked by SSB (seen same bank)
begin
if
(
(load_tbp[i] && |(valid & same_chip_bank_diff_row) && cfg_reorder_data && CFG_DATA_REORDERING_TYPE == "INTER_ROW") ||
((|load_tbp && !load_tbp[i]) && valid[i] && same_chip_bank_diff_row[i])
)
// (INTER_ROW) on self load, set to '1' if other valid TBP is same-chip-bank-diff-row with self
// set to '1' if there is a new command with same-chip-bank-diff-row with current TBP
begin
apvo_combi[i] = 1'b1;
end
else
begin
apvo_combi[i] = apvo[i];
end
if ((|load_tbp && !load_tbp[i]) && valid[i] && same_chip_bank_row[i])
// set to '1' if there is a new command with same-chip-bank-row with current TBP
begin
apvc_combi[i] = 1'b1;
end
else
begin
apvc_combi[i] = apvc[i];
end
end
else
begin
apvo_combi[i] = apvo[i];
apvc_combi[i] = apvc[i];
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
apvo[i] <= 1'b0;
apvc[i] <= 1'b0;
end
end
else
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
apvo[i] <= apvo_combi[i];
apvc[i] <= apvc_combi[i];
end
end
end
// Auto precharge
always @(*)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
if (apvc[i]) // keeping a page open have higher priority that keeping a close page (improve efficiency)
begin
ap[i] = 1'b0;
end
else if (apvo[i])
begin
ap[i] = 1'b1;
end
else
begin
ap[i] = autopch[i] | require_flush[i];
end
end
end
// Real auto-precharge
// purpose is to make pipelining easier in the future (if needed)
always @ (*)
begin
real_ap = ap;
end
//----------------------------------------------------------------------------------------------------
// Done logic
//----------------------------------------------------------------------------------------------------
// Indicate that current TBP has finished issuing column command
always @ (*)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
if (load_tbp[i])
begin
done_combi[i] = 1'b0;
end
else if (flush_tbp[i])
begin
done_combi[i] = 1'b0;
end
else if (col_grant[i])
begin
done_combi[i] = 1'b1;
end
else
begin
done_combi[i] = done[i];
end
end
end
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
done[i] <= 1'b0;
end
end
else
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
done[i] <= done_combi[i];
end
end
end
//----------------------------------------------------------------------------------------------------
// Complete logic
//----------------------------------------------------------------------------------------------------
// Indicate that the data for current TBP is complete and ready to be issued
always @(*)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
if (load_tbp[i])
begin
if (cmd_gen_read)
begin
complete_combi_rd[i] = cmd_gen_complete;
complete_combi_wr[i] = 1'b0;
end
else
begin
complete_combi_rd[i] = 1'b0;
complete_combi_wr[i] = cmd_gen_complete;
end
end
else if (write[i] && !complete[i])
begin
complete_combi_rd[i] = complete_rd[i];
complete_combi_wr[i] = data_complete[i];
end
else
begin
complete_combi_rd[i] = complete_rd[i];
complete_combi_wr[i] = complete_wr[i];
end
end
end
always @ (*)
begin
complete_combi = complete_combi_rd | complete_combi_wr;
end
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
complete <= 0;
complete_rd <= 0;
complete_wr <= 0;
end
else
begin
complete <= complete_combi;
complete_rd <= complete_combi_rd;
complete_wr <= complete_combi_wr;
end
end
//----------------------------------------------------------------------------------------------------
// Same bank vector logic
//----------------------------------------------------------------------------------------------------
// This bit vector (same bank vector) is to stop a TBP from requesting activate when another row in the same chip-bank was granted
// SBV stops TBP from requesting activate when there is another same-chip-bank-diff-row was granted
// prevents activate to and activated bank
always @(*)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
for (j=0; j<CFG_CTL_TBP_NUM; j=j+1)
begin
if (CFG_DATA_REORDERING_TYPE == "INTER_BANK")
begin
// There is no need to SBV in INTER_BANK case
sbv_combi[i][j] = zero;
end
else if (CFG_DATA_REORDERING_TYPE == "INTER_ROW")
begin
if
(
(load_tbp[i] && !flush_tbp[j] && (activated[j] || activated_combi[j]) && same_chip_bank_diff_row[j]) ||
(activated_combi[j] && valid[i] && pre_calculated_same_chip_bank_diff_row [i][j])
)
// Set SBV to '1' if new TBP is same-chip-bank-diff-row with other existing TBP
// Set SBV to '1' if there is a row_grant or open-row-pass to other existing TBP with same-chip-bank-diff-row
begin
sbv_combi[i][j] = 1'b1;
end
else if (flush_tbp[j] || pch_grant[j] || precharge_tbp[j])
// Set SBV to '0' if there is a flush to other TBP
// Set SBV to '0' if there is a precharge to other TBP
// Set SBV to '0' if there is a precharge all command from sideband
begin
sbv_combi[i][j] = 1'b0;
end
else
begin
sbv_combi[i][j] = sbv[i][j];
end
end
else
begin
sbv_combi[i][j] = sbv[i][j];
end
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
nor_sbv[i] <= 1'b0;
for (j=0; j<CFG_CTL_TBP_NUM; j=j+1)
begin
sbv[i][j] <= 1'b0;
end
end
end
else
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
nor_sbv[i] <= ~|sbv_combi[i];
for (j=0; j<CFG_CTL_TBP_NUM; j=j+1)
begin
if (i == j) // Hard-coded to '0' for own vector bit, since we only need to know the dependencies for other TBPs not ourself
begin
sbv[i][j] <= 1'b0;
end
else
begin
sbv[i][j] <= sbv_combi[i][j];
end
end
end
end
end
//----------------------------------------------------------------------------------------------------
// Same bank timer vector logic
//----------------------------------------------------------------------------------------------------
// SBTV stops TBP from requesting activate when the timer for same-chip-bank is still running
always @ (*)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
for (j=0; j<CFG_CTL_TBP_NUM; j=j+1)
begin
if (CFG_DATA_REORDERING_TYPE == "INTER_BANK")
begin
sbvt_combi[i][j] = zero;
end
else if (CFG_DATA_REORDERING_TYPE == "INTER_ROW")
begin
if (flush_tbp[i])
begin
sbvt_combi[i][j] = 1'b0;
end
else if (push_tbp[j])
begin
sbvt_combi[i][j] = 1'b0;
end
else if
(
(pch_grant[j] || (col_grant[j] && real_ap[j])) &&
(
(load_tbp[i] && same_chip_bank[j]) ||
(valid[i] && pre_calculated_same_chip_bank[i][j])
)
)
// Set to '1' when there is a precharge/auto-precharge to same-chip-bank address
begin
sbvt_combi[i][j] = 1'b1;
end
else if
(
precharged[j] && valid[j] &&
(
(load_tbp[i] && same_chip_bank[j]) ||
(valid[i] && pre_calculated_same_chip_bank[i][j])
)
)
// Set to '1' when same-chip-bank address TBP is still in precharge state
begin
sbvt_combi[i][j] = ~row_timer_pre_ready[j];
end
else
begin
sbvt_combi[i][j] = zero;
end
end
else
begin
sbvt_combi[i][j] = sbvt[i][j];
end
end
end
end
always @ (*)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
for (j=0; j<CFG_CTL_SHADOW_TBP_NUM; j=j+1)
begin
if (CFG_ENABLE_SHADOW_TBP)
begin
if (CFG_DATA_REORDERING_TYPE == "INTER_BANK")
begin
shadow_sbvt_combi[i][j] = zero;
end
else if (CFG_DATA_REORDERING_TYPE == "INTER_ROW")
begin
if (flush_shadow_tbp[j])
begin
shadow_sbvt_combi[i][j] = 1'b0;
end
else if (push_tbp[j] && sbvt[i][j])
begin
shadow_sbvt_combi[i][j] = 1'b1;
end
else if (valid[i] && shadow_valid[j] && pre_calculated_same_shadow_chip_bank[i][j])
// Set to 'timer-pre-ready' when own TBP is valid, shadow TBP is valid and same chip-bank address
begin
shadow_sbvt_combi[i][j] = ~shadow_row_timer_pre_ready[j];
end
else
begin
shadow_sbvt_combi[i][j] = shadow_sbvt[i][j];
end
end
else
begin
shadow_sbvt_combi[i][j] = zero;
end
end
else
begin
shadow_sbvt_combi[i][j] = zero;
end
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
for (j=0; j<CFG_CTL_TBP_NUM; j=j+1)
begin
sbvt[i][j] <= 1'b0;
end
end
end
else
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
nor_sbvt[i] <= ~|{shadow_sbvt_combi[i], sbvt_combi[i]};
for (j=0; j<CFG_CTL_TBP_NUM; j=j+1)
begin
if (i == j) // Hard-coded to '0' for own vector bit, since we only need to know the dependencies for other TBPs not ourself
begin
sbvt[i][j] <= 1'b0;
end
else
begin
sbvt[i][j] <= sbvt_combi[i][j];
end
end
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
for (j=0; j<CFG_CTL_SHADOW_TBP_NUM; j=j+1)
begin
shadow_sbvt[i][j] <= 1'b0;
end
end
end
else
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
for (j=0; j<CFG_CTL_SHADOW_TBP_NUM; j=j+1)
begin
shadow_sbvt[i][j] <= shadow_sbvt_combi[i][j];
end
end
end
end
//----------------------------------------------------------------------------------------------------
// Seen same bank logic
//----------------------------------------------------------------------------------------------------
// Indicate that it sees a new TBP which is same-chip-bank with current TBP
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
ssb[i] <= 1'b0;
end
end
else
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
for (j=0; j<CFG_CTL_TBP_NUM; j=j+1)
begin
if (flush_tbp[i])
begin
ssb[i] <= 1'b0;
end
else if (load_tbp[j] && valid[i] && same_chip_bank[i])
begin
ssb[i] <= 1'b1;
end
end
end
end
end
//----------------------------------------------------------------------------------------------------
// Seen same bank row logic
//----------------------------------------------------------------------------------------------------
// Indicate that it sees a new TBP which is same-chip-bank-row with current TBP
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
ssbr[i] <= 1'b0;
end
end
else
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
for (j=0; j<CFG_CTL_TBP_NUM; j=j+1)
begin
if (flush_tbp[i])
begin
ssbr[i] <= 1'b0;
end
else if (load_tbp[j] && valid[i] && same_chip_bank_row[i])
begin
ssbr[i] <= 1'b1;
end
end
end
end
end
//----------------------------------------------------------------------------------------------------
// Will send transfer logic
//----------------------------------------------------------------------------------------------------
// Indicate that it will pass current TBP information (timing/page) over to other TBP
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
wst [i] <= 1'b0;
wst_p[i] <= 1'b0;
end
end
else
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
for (j=0; j<CFG_CTL_TBP_NUM; j=j+1)
begin
if (load_tbp[i]) // Reset back to '0'
begin
wst [i] <= 1'b0;
wst_p[i] <= 1'b0;
end
else if
(
( cfg_reorder_data && CFG_DATA_REORDERING_TYPE == "INTER_ROW" && precharged_combi[i] && done_combi[i]) ||
( cfg_reorder_data && CFG_DATA_REORDERING_TYPE == "INTER_BANK" && precharged_combi[i] ) ||
(!cfg_reorder_data && precharged_combi[i])
)
// Set to '0' when there is a precharge to current TBP, after a precharge, it's not possible to perform open-row-pass anymore
// (INTER_ROW) included done_combi because precharge can happen to a newly loaded TBP due to TBP interlock case (see require_pch logic)
// to make sure we're able to open-row-pass a not-done precharged command
begin
wst [i] <= 1'b0;
wst_p[i] <= 1'b0;
end
else if (open_row_pass_flush[i]) // make sure open-row-pass only asserts for one clock cycle
begin
wst_p[i] <= 1'b0;
end
else if
(
load_tbp[j] && same_chip_bank_row[i] &&
(
( cfg_reorder_data && CFG_DATA_REORDERING_TYPE == "INTER_ROW" && !ssbr[i] && !(precharged_combi[i] && done_combi[i])) ||
( cfg_reorder_data && CFG_DATA_REORDERING_TYPE == "INTER_BANK" && !ssb [i] && !(precharged_combi[i] )) ||
(!cfg_reorder_data && !ssb[i] && !precharged_combi[i])
)
)
// Set to '1' when there is a new TBP being loaded, with same-chip-bank-row with current TBP
// make sure current TBP is not precharged so that information can be pass over to same-chip-bank-row TBP
// (INTER_ROW) included done_combi because precharge can happen to a newly loaded TBP due to TBP interlock case (see require_pch logic)
// to make sure we're able to open-row-pass a not-done precharged command
// (INTER_BANK) make sure SSB is not set (only set WST once)
// (NON_REORDER) make sure SSB is not set (only set WST once)
begin
wst [i] <= 1'b1;
wst_p[i] <= 1'b1;
end
end
end
end
end
//----------------------------------------------------------------------------------------------------
// Will receive transfer logic
//----------------------------------------------------------------------------------------------------
// Indicate that it will receive TBP information (timing/page) from other TBP (also tells which TBP it is receiving from)
always @ (*)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
for (j=0; j<CFG_CTL_TBP_NUM; j=j+1)
begin
if
(
load_tbp[i] && !flush_tbp[j] && valid[j] && same_chip_bank_row[j] &&
(
( cfg_reorder_data && CFG_DATA_REORDERING_TYPE == "INTER_ROW" && !ssbr[j]) ||
( cfg_reorder_data && CFG_DATA_REORDERING_TYPE == "INTER_BANK" && !ssb [j]) ||
(!cfg_reorder_data && !ssb[j])
)
)
// Set to '1' when there is a new TBp being loaded, with same-chip-bank-row with other existing TBP
// provided other TBP is valid and not precharged
// (INTER_BANK) make sure SSB of other TBP is not set, to handle row interrupt case
begin
wrt_combi[i][j] = 1'b1;
end
else if (flush_tbp[j])
begin
wrt_combi[i][j] = 1'b0;
end
else
begin
wrt_combi[i][j] = wrt[i][j];
end
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i = 0;i < CFG_CTL_TBP_NUM;i = i + 1)
begin
wrt [i] <= 0;
or_wrt [i] <= 1'b0;
nor_wrt[i] <= 1'b0;
end
end
else
begin
for (i = 0;i < CFG_CTL_TBP_NUM;i = i + 1)
begin
or_wrt [i] <= |wrt_combi[i];
nor_wrt[i] <= ~|wrt_combi[i];
for (j = 0;j < CFG_CTL_TBP_NUM;j = j + 1)
begin
if (i == j)
wrt[i][j] <= 1'b0;
else
wrt[i][j] <= wrt_combi[i][j];
end
end
end
end
//----------------------------------------------------------------------------------------------------
// Require flush logic
//----------------------------------------------------------------------------------------------------
// On demand flush selection, command with same chip-bank-diff-row first, we dont want to precharge twice
// if there are none, flush cmd to diff chip-bank, we might have cmd to the same row in tbp already
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
require_flush[i] <= 1'b0;
end
end
else
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
if (CFG_CTL_TBP_NUM == 1)
begin
require_flush[i] <= cmd_gen_load;
end
else
begin
if (|flush_tbp) // tbp will not be full on the next clock cycle
begin
require_flush[i] <= 1'b0;
end
else if (int_tbp_full && cmd_gen_load)
begin
if (same_chip_bank_row[i])
require_flush[i] <= 1'b0;
else
require_flush[i] <= 1'b1;
end
else
begin
require_flush[i] <= 1'b0;
end
end
end
end
end
//----------------------------------------------------------------------------------------------------
// Require precharge logic
//----------------------------------------------------------------------------------------------------
// Precharge request logic, to clear up lockup state in TBP
always @(*)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
for (j=0; j<CFG_CTL_TBP_NUM; j=j+1)
begin
if (CFG_DATA_REORDERING_TYPE == "INTER_BANK")
begin
require_pch_combi[i][j] = zero;
end
else
begin
if (i == j)
begin
require_pch_combi[i][j] = 1'b0;
end
else if (activated[i] && !done[i])
begin
if (cpv[i][j] && sbv[j][i])
begin
require_pch_combi[i][j] = 1'b1;
end
else
begin
require_pch_combi[i][j] = 1'b0;
end
end
else
begin
require_pch_combi[i][j] = 1'b0;
end
end
end
end
end
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
require_pch[i] <= 1'b0;
end
end
else
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
if (flush_tbp[i])
begin
require_pch[i] <= 1'b0;
end
else
begin
// included real_ap since real_ap is part of precharge request (!apvc so that it will deassert pch_req when not needed)
require_pch[i] <= |require_pch_combi[i] | (done[i] & real_ap[i] & !apvc_combi[i]);
end
end
end
end
//----------------------------------------------------------------------------------------------------
// Address/command comparison logic
//----------------------------------------------------------------------------------------------------
// Command comparator
always @ (*)
begin
if (CFG_DISABLE_READ_REODERING) // logic only enabled when parameter is set to '1'
begin
same_command_read = cmd_gen_same_read_cmd;
end
else
begin
same_command_read = {CFG_CTL_TBP_NUM{zero}};
end
end
always @ (*)
begin
same_shadow_command_read = {CFG_CTL_SHADOW_TBP_NUM{zero}};
end
// Address comparator
always @(*)
begin
same_chip_bank = cmd_gen_same_chipsel_addr & cmd_gen_same_bank_addr;
same_chip_bank_row = cmd_gen_same_chipsel_addr & cmd_gen_same_bank_addr & cmd_gen_same_row_addr;
same_chip_bank_diff_row = cmd_gen_same_chipsel_addr & cmd_gen_same_bank_addr & ~cmd_gen_same_row_addr;
end
always @ (*)
begin
same_shadow_chip_bank = cmd_gen_same_shadow_chipsel_addr & cmd_gen_same_shadow_bank_addr;
same_shadow_chip_bank_row = cmd_gen_same_shadow_chipsel_addr & cmd_gen_same_shadow_bank_addr & cmd_gen_same_shadow_row_addr;
same_shadow_chip_bank_diff_row = cmd_gen_same_shadow_chipsel_addr & cmd_gen_same_shadow_bank_addr & ~cmd_gen_same_shadow_row_addr;
end
// Registered version, to improve fMAX
generate
begin
genvar i_tbp;
genvar j_tbp;
for (i_tbp = 0;i_tbp < CFG_CTL_TBP_NUM;i_tbp = i_tbp + 1)
begin : i_compare_loop
for (j_tbp = 0;j_tbp < CFG_CTL_TBP_NUM;j_tbp = j_tbp + 1)
begin : j_compare_loop
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
pre_calculated_same_chip_bank_diff_row [i_tbp][j_tbp] <= 1'b0;
pre_calculated_same_chip_bank_row [i_tbp][j_tbp] <= 1'b0;
pre_calculated_same_chip_bank [i_tbp][j_tbp] <= 1'b0;
end
else
begin
if (load_tbp [i_tbp])
begin
pre_calculated_same_chip_bank_diff_row [i_tbp][j_tbp] <= same_chip_bank_diff_row [j_tbp];
pre_calculated_same_chip_bank_row [i_tbp][j_tbp] <= same_chip_bank_row [j_tbp];
pre_calculated_same_chip_bank [i_tbp][j_tbp] <= same_chip_bank [j_tbp];
end
else if (load_tbp [j_tbp])
begin
if (chipsel [i_tbp] == cmd_gen_chipsel && bank [i_tbp] == cmd_gen_bank && row [i_tbp] != cmd_gen_row)
pre_calculated_same_chip_bank_diff_row [i_tbp][j_tbp] <= 1'b1;
else
pre_calculated_same_chip_bank_diff_row [i_tbp][j_tbp] <= 1'b0;
if (chipsel [i_tbp] == cmd_gen_chipsel && bank [i_tbp] == cmd_gen_bank && row [i_tbp] == cmd_gen_row)
pre_calculated_same_chip_bank_row [i_tbp][j_tbp] <= 1'b1;
else
pre_calculated_same_chip_bank_row [i_tbp][j_tbp] <= 1'b0;
if (chipsel [i_tbp] == cmd_gen_chipsel && bank [i_tbp] == cmd_gen_bank)
pre_calculated_same_chip_bank [i_tbp][j_tbp] <= 1'b1;
else
pre_calculated_same_chip_bank [i_tbp][j_tbp] <= 1'b0;
end
else if (chipsel [i_tbp] == chipsel [j_tbp] && bank [i_tbp] == bank [j_tbp])
begin
if (row [i_tbp] != row [j_tbp])
begin
pre_calculated_same_chip_bank_diff_row [i_tbp][j_tbp] <= 1'b1;
pre_calculated_same_chip_bank_row [i_tbp][j_tbp] <= 1'b0;
end
else
begin
pre_calculated_same_chip_bank_diff_row [i_tbp][j_tbp] <= 1'b0;
pre_calculated_same_chip_bank_row [i_tbp][j_tbp] <= 1'b1;
end
pre_calculated_same_chip_bank [i_tbp][j_tbp] <= 1'b1;
end
else
begin
pre_calculated_same_chip_bank_diff_row [i_tbp][j_tbp] <= 1'b0;
pre_calculated_same_chip_bank_row [i_tbp][j_tbp] <= 1'b0;
pre_calculated_same_chip_bank [i_tbp][j_tbp] <= 1'b0;
end
end
end
end
end
for (i_tbp = 0;i_tbp < CFG_CTL_TBP_NUM;i_tbp = i_tbp + 1)
begin : i_compare_loop_shadow
for (j_tbp = 0;j_tbp < CFG_CTL_SHADOW_TBP_NUM;j_tbp = j_tbp + 1)
begin : j_compare_loop_shadow
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
pre_calculated_same_shadow_chip_bank [i_tbp][j_tbp] <= 1'b0;
end
else
begin
if (load_tbp [i_tbp])
begin
if (push_tbp [j_tbp])
pre_calculated_same_shadow_chip_bank [i_tbp][j_tbp] <= same_chip_bank [j_tbp];
else
pre_calculated_same_shadow_chip_bank [i_tbp][j_tbp] <= same_shadow_chip_bank [j_tbp];
end
else if (push_tbp [j_tbp])
begin
if (chipsel [i_tbp] == chipsel [j_tbp] && bank [i_tbp] == bank [j_tbp])
pre_calculated_same_shadow_chip_bank [i_tbp][j_tbp] <= 1'b1;
else
pre_calculated_same_shadow_chip_bank [i_tbp][j_tbp] <= 1'b0;
end
else if (chipsel [i_tbp] == shadow_chipsel [j_tbp] && bank [i_tbp] == shadow_bank [j_tbp])
begin
pre_calculated_same_shadow_chip_bank [i_tbp][j_tbp] <= 1'b1;
end
else
begin
pre_calculated_same_shadow_chip_bank [i_tbp][j_tbp] <= 1'b0;
end
end
end
end
end
end
endgenerate
//----------------------------------------------------------------------------------------------------
// Bank specific timer related logic
//----------------------------------------------------------------------------------------------------
// Offset timing paramter to achieve accurate timing gap between commands
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
compare_t_param_act_to_rdwr_less_than_offset <= 0;
compare_t_param_act_to_act_less_than_offset <= 0;
compare_t_param_act_to_pch_less_than_offset <= 0;
compare_t_param_rd_to_pch_less_than_offset <= 0;
compare_t_param_wr_to_pch_less_than_offset <= 0;
compare_t_param_pch_to_valid_less_than_offset <= 0;
compare_t_param_rd_ap_to_valid_less_than_offset <= 0;
compare_t_param_wr_ap_to_valid_less_than_offset <= 0;
compare_offset_t_param_act_to_rdwr_less_than_0 <= 0;
compare_offset_t_param_act_to_rdwr_less_than_1 <= 0;
end
else
begin
if (t_param_act_to_rdwr > TBP_COUNTER_OFFSET)
begin
compare_t_param_act_to_rdwr_less_than_offset <= 1'b0;
end
else
begin
compare_t_param_act_to_rdwr_less_than_offset <= 1'b1;
end
if (t_param_act_to_act > TBP_COUNTER_OFFSET)
begin
compare_t_param_act_to_act_less_than_offset <= 1'b0;
end
else
begin
compare_t_param_act_to_act_less_than_offset <= 1'b1;
end
if (t_param_act_to_pch > TBP_COUNTER_OFFSET)
begin
compare_t_param_act_to_pch_less_than_offset <= 1'b0;
end
else
begin
compare_t_param_act_to_pch_less_than_offset <= 1'b1;
end
if (t_param_rd_to_pch > TBP_COUNTER_OFFSET)
begin
compare_t_param_rd_to_pch_less_than_offset <= 1'b0;
end
else
begin
compare_t_param_rd_to_pch_less_than_offset <= 1'b1;
end
if (t_param_wr_to_pch > TBP_COUNTER_OFFSET)
begin
compare_t_param_wr_to_pch_less_than_offset <= 1'b0;
end
else
begin
compare_t_param_wr_to_pch_less_than_offset <= 1'b1;
end
if (t_param_pch_to_valid > TBP_COUNTER_OFFSET)
begin
compare_t_param_pch_to_valid_less_than_offset <= 1'b0;
end
else
begin
compare_t_param_pch_to_valid_less_than_offset <= 1'b1;
end
if (t_param_rd_ap_to_valid > TBP_COUNTER_OFFSET)
begin
compare_t_param_rd_ap_to_valid_less_than_offset <= 1'b0;
end
else
begin
compare_t_param_rd_ap_to_valid_less_than_offset <= 1'b1;
end
if (t_param_wr_ap_to_valid > TBP_COUNTER_OFFSET)
begin
compare_t_param_wr_ap_to_valid_less_than_offset <= 1'b0;
end
else
begin
compare_t_param_wr_ap_to_valid_less_than_offset <= 1'b1;
end
if (offset_t_param_act_to_rdwr <= 0)
begin
compare_offset_t_param_act_to_rdwr_less_than_0 <= 1'b1;
end
else
begin
compare_offset_t_param_act_to_rdwr_less_than_0 <= 1'b0;
end
if (offset_t_param_act_to_rdwr <= 1)
begin
compare_offset_t_param_act_to_rdwr_less_than_1 <= 1'b1;
end
else
begin
compare_offset_t_param_act_to_rdwr_less_than_1 <= 1'b0;
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
offset_t_param_act_to_rdwr <= 0;
offset_t_param_act_to_act <= 0;
offset_t_param_act_to_pch <= 0;
offset_t_param_rd_to_pch <= 0;
offset_t_param_wr_to_pch <= 0;
offset_t_param_pch_to_valid <= 0;
offset_t_param_rd_ap_to_valid <= 0;
offset_t_param_wr_ap_to_valid <= 0;
end
else
begin
if (!compare_t_param_act_to_rdwr_less_than_offset)
begin
offset_t_param_act_to_rdwr <= t_param_act_to_rdwr - TBP_COUNTER_OFFSET;
end
else
begin
offset_t_param_act_to_rdwr <= 0;
end
if (!compare_t_param_act_to_act_less_than_offset)
begin
offset_t_param_act_to_act <= t_param_act_to_act - TBP_COUNTER_OFFSET;
end
else
begin
offset_t_param_act_to_act <= 0;
end
if (!compare_t_param_act_to_pch_less_than_offset)
begin
offset_t_param_act_to_pch <= t_param_act_to_pch - TBP_COUNTER_OFFSET;
end
else
begin
offset_t_param_act_to_pch <= 0;
end
if (!compare_t_param_rd_to_pch_less_than_offset)
begin
offset_t_param_rd_to_pch <= t_param_rd_to_pch - TBP_COUNTER_OFFSET;
end
else
begin
offset_t_param_rd_to_pch <= 0;
end
if (!compare_t_param_wr_to_pch_less_than_offset)
begin
offset_t_param_wr_to_pch <= t_param_wr_to_pch - TBP_COUNTER_OFFSET;
end
else
begin
offset_t_param_wr_to_pch <= 0;
end
if (!compare_t_param_pch_to_valid_less_than_offset)
begin
offset_t_param_pch_to_valid <= t_param_pch_to_valid - TBP_COUNTER_OFFSET;
end
else
begin
offset_t_param_pch_to_valid <= 0;
end
if (!compare_t_param_rd_ap_to_valid_less_than_offset)
begin
offset_t_param_rd_ap_to_valid <= t_param_rd_ap_to_valid - TBP_COUNTER_OFFSET;
end
else
begin
offset_t_param_rd_ap_to_valid <= 0;
end
if (!compare_t_param_wr_ap_to_valid_less_than_offset)
begin
offset_t_param_wr_ap_to_valid <= t_param_wr_ap_to_valid - TBP_COUNTER_OFFSET;
end
else
begin
offset_t_param_wr_ap_to_valid <= 0;
end
end
end
// Pre-calculated logic to improve timing, for row_timer and trc_timer
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
compare_t_param_rd_ap_to_valid_greater_than_trc_timer[i] <= 1'b0;
compare_t_param_wr_ap_to_valid_greater_than_trc_timer[i] <= 1'b0;
compare_t_param_rd_to_pch_greater_than_row_timer [i] <= 1'b0;
compare_t_param_wr_to_pch_greater_than_row_timer [i] <= 1'b0;
end
end
else
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
if (CFG_REG_GRANT == 0 && open_row_pass[i])
begin
if (t_param_rd_ap_to_valid > ((trc_timer[log2_open_row_pass_flush[i]] > 1) ? (trc_timer[log2_open_row_pass_flush[i]] - 1'b1) : 0))
begin
compare_t_param_rd_ap_to_valid_greater_than_trc_timer[i] <= 1'b1;
end
else
begin
compare_t_param_rd_ap_to_valid_greater_than_trc_timer[i] <= 1'b0;
end
if (t_param_wr_ap_to_valid > ((trc_timer[log2_open_row_pass_flush[i]] > 1) ? (trc_timer[log2_open_row_pass_flush[i]] - 1'b1) : 0))
begin
compare_t_param_wr_ap_to_valid_greater_than_trc_timer[i] <= 1'b1;
end
else
begin
compare_t_param_wr_ap_to_valid_greater_than_trc_timer[i] <= 1'b0;
end
if (t_param_rd_to_pch > ((row_timer[log2_open_row_pass_flush[i]] > 1) ? (row_timer[log2_open_row_pass_flush[i]] - 1'b1) : 0))
begin
compare_t_param_rd_to_pch_greater_than_row_timer[i] <= 1'b1;
end
else
begin
compare_t_param_rd_to_pch_greater_than_row_timer[i] <= 1'b0;
end
if (t_param_wr_to_pch > ((row_timer[log2_open_row_pass_flush[i]] > 1) ? (row_timer[log2_open_row_pass_flush[i]] - 1'b1) : 0))
begin
compare_t_param_wr_to_pch_greater_than_row_timer[i] <= 1'b1;
end
else
begin
compare_t_param_wr_to_pch_greater_than_row_timer[i] <= 1'b0;
end
end
else if (CFG_REG_GRANT == 1 && open_row_pass_r[i])
begin
if (t_param_rd_ap_to_valid > ((trc_timer[log2_open_row_pass_flush_r[i]] > 1) ? (trc_timer[log2_open_row_pass_flush_r[i]] - 1'b1) : 0))
begin
compare_t_param_rd_ap_to_valid_greater_than_trc_timer[i] <= 1'b1;
end
else
begin
compare_t_param_rd_ap_to_valid_greater_than_trc_timer[i] <= 1'b0;
end
if (t_param_wr_ap_to_valid > ((trc_timer[log2_open_row_pass_flush_r[i]] > 1) ? (trc_timer[log2_open_row_pass_flush_r[i]] - 1'b1) : 0))
begin
compare_t_param_wr_ap_to_valid_greater_than_trc_timer[i] <= 1'b1;
end
else
begin
compare_t_param_wr_ap_to_valid_greater_than_trc_timer[i] <= 1'b0;
end
if (t_param_rd_to_pch > ((row_timer[log2_open_row_pass_flush_r[i]] > 1) ? (row_timer[log2_open_row_pass_flush_r[i]] - 1'b1) : 0))
begin
compare_t_param_rd_to_pch_greater_than_row_timer[i] <= 1'b1;
end
else
begin
compare_t_param_rd_to_pch_greater_than_row_timer[i] <= 1'b0;
end
if (t_param_wr_to_pch > ((row_timer[log2_open_row_pass_flush_r[i]] > 1) ? (row_timer[log2_open_row_pass_flush_r[i]] - 1'b1) : 0))
begin
compare_t_param_wr_to_pch_greater_than_row_timer[i] <= 1'b1;
end
else
begin
compare_t_param_wr_to_pch_greater_than_row_timer[i] <= 1'b0;
end
end
else
begin
if (t_param_rd_ap_to_valid > ((trc_timer[i] > 1) ? (trc_timer[i] - 1'b1) : 0))
begin
compare_t_param_rd_ap_to_valid_greater_than_trc_timer[i] <= 1'b1;
end
else
begin
compare_t_param_rd_ap_to_valid_greater_than_trc_timer[i] <= 1'b0;
end
if (t_param_wr_ap_to_valid > ((trc_timer[i] > 1) ? (trc_timer[i] - 1'b1) : 0))
begin
compare_t_param_wr_ap_to_valid_greater_than_trc_timer[i] <= 1'b1;
end
else
begin
compare_t_param_wr_ap_to_valid_greater_than_trc_timer[i] <= 1'b0;
end
if (t_param_rd_to_pch > ((row_timer[i] > 1) ? (row_timer[i] - 1'b1) : 0))
begin
compare_t_param_rd_to_pch_greater_than_row_timer[i] <= 1'b1;
end
else
begin
compare_t_param_rd_to_pch_greater_than_row_timer[i] <= 1'b0;
end
if (t_param_wr_to_pch > ((row_timer[i] > 1) ? (row_timer[i] - 1'b1) : 0))
begin
compare_t_param_wr_to_pch_greater_than_row_timer[i] <= 1'b1;
end
else
begin
compare_t_param_wr_to_pch_greater_than_row_timer[i] <= 1'b0;
end
end
end
end
end
// Column timer logic
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
col_timer [i] <= 0;
col_timer_ready [i] <= 1'b0;
col_timer_pre_ready[i] <= 1'b0;
end
else
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
if (row_grant[i])
begin
if (compare_t_param_act_to_rdwr_less_than_offset)
begin
col_timer [i] <= 0;
col_timer_ready [i] <= 1'b1;
col_timer_pre_ready[i] <= 1'b1;
end
else
begin
col_timer [i] <= offset_t_param_act_to_rdwr;
if (compare_offset_t_param_act_to_rdwr_less_than_0)
begin
col_timer_ready [i] <= 1'b1;
end
else
begin
col_timer_ready [i] <= 1'b0;
end
if (compare_offset_t_param_act_to_rdwr_less_than_1)
begin
col_timer_pre_ready[i] <= 1'b1;
end
else
begin
col_timer_pre_ready[i] <= 1'b0;
end
end
end
else
begin
if (col_timer[i] != 0)
begin
col_timer[i] <= col_timer[i] - 1'b1;
end
if (col_timer[i] <= 1)
begin
col_timer_ready[i] <= 1'b1;
end
else
begin
col_timer_ready[i] <= 1'b0;
end
if (col_timer[i] <= 2)
begin
col_timer_pre_ready[i] <= 1'b1;
end
else
begin
col_timer_pre_ready[i] <= 1'b0;
end
end
end
end
// log2 result of open-row-pass-flush, to be used during timer information pass
always @ (*)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
log2_open_row_pass_flush[i] = log2(open_row_pass_flush & wrt[i]);
end
end
// Registered version
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
log2_open_row_pass_flush_r[i] <= 0;
end
end
else
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
log2_open_row_pass_flush_r[i] <= log2_open_row_pass_flush[i];
end
end
end
// Row timer logic
always @ (*)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
if (trc_timer[i] <= 1)
begin
trc_timer_pre_ready_combi[i] = 1'b1;
end
else
begin
trc_timer_pre_ready_combi[i] = 1'b0;
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
trc_timer [i] <= 0;
trc_timer_ready [i] <= 1'b0;
trc_timer_pre_ready[i] <= 1'b0;
end
end
else
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
// Reset row_timer after push
if (push_tbp[i])
begin
trc_timer [i] <= 0;
trc_timer_ready [i] <= 1'b1;
trc_timer_pre_ready[i] <= 1'b1;
end
// We need to update the timer as soon as possible when CFG_REG_GRANT == 0
// because after open-row-pass, row grant can happen on the next clock cycle
else if
(
(CFG_REG_GRANT == 0 && open_row_pass [i]) ||
(CFG_REG_GRANT == 1 && open_row_pass_r[i])
)
begin
if (CFG_REG_GRANT == 0 && !trc_timer_pre_ready_combi[log2_open_row_pass_flush[i]])
begin
trc_timer [i] <= trc_timer[log2_open_row_pass_flush[i]] - 1'b1;
trc_timer_ready [i] <= 1'b0;
trc_timer_pre_ready[i] <= 1'b0;
end
else if (CFG_REG_GRANT == 1 && !trc_timer_pre_ready[log2_open_row_pass_flush_r[i]])
begin
trc_timer [i] <= trc_timer[log2_open_row_pass_flush_r[i]] - 1'b1;
trc_timer_ready [i] <= 1'b0;
trc_timer_pre_ready[i] <= 1'b0;
end
else
begin
trc_timer [i] <= 0;
trc_timer_ready [i] <= 1'b1;
trc_timer_pre_ready[i] <= 1'b1;
end
end
else if (act_grant[i])
begin
trc_timer [i] <= offset_t_param_act_to_act;
trc_timer_ready [i] <= 1'b0;
trc_timer_pre_ready[i] <= 1'b0;
end
else
begin
if (trc_timer[i] != 0)
begin
trc_timer[i] <= trc_timer[i] - 1'b1;
end
if (trc_timer[i] <= 1)
begin
trc_timer_ready[i] <= 1'b1;
end
if (trc_timer[i] <= 2)
begin
trc_timer_pre_ready[i] <= 1'b1;
end
end
end
end
end
always @ (*)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
if (rd_grant[i])
begin
if (real_ap[i])
begin
if
(
(CFG_REG_GRANT == 1 && compare_t_param_rd_ap_to_valid_greater_than_trc_timer[i]) ||
(CFG_REG_GRANT == 0 && t_param_rd_ap_to_valid > trc_timer[i])
)
begin
row_timer_combi[i] = offset_t_param_rd_ap_to_valid;
end
else
begin
row_timer_combi[i] = trc_timer[i] - 1'b1;
end
end
else
begin
if
(
(CFG_REG_GRANT == 1 && compare_t_param_rd_to_pch_greater_than_row_timer[i]) ||
(CFG_REG_GRANT == 0 && t_param_rd_to_pch > row_timer[i])
)
begin
row_timer_combi[i] = offset_t_param_rd_to_pch;
end
else
begin
row_timer_combi[i] = row_timer[i] - 1'b1;
end
end
end
else if (wr_grant[i])
begin
if (real_ap[i])
begin
if
(
(CFG_REG_GRANT == 1 && compare_t_param_wr_ap_to_valid_greater_than_trc_timer[i]) ||
(CFG_REG_GRANT == 0 && t_param_wr_ap_to_valid > trc_timer[i])
)
begin
row_timer_combi[i] = offset_t_param_wr_ap_to_valid;
end
else
begin
row_timer_combi[i] = trc_timer[i] - 1'b1;
end
end
else
begin
if
(
(CFG_REG_GRANT == 1 && compare_t_param_wr_to_pch_greater_than_row_timer[i]) ||
(CFG_REG_GRANT == 0 && t_param_wr_to_pch > row_timer[i])
)
begin
row_timer_combi[i] = offset_t_param_wr_to_pch;
end
else
begin
row_timer_combi[i] = row_timer[i] - 1'b1;
end
end
end
else
begin
if (row_timer[i] != 0)
begin
row_timer_combi[i] = row_timer[i] - 1'b1;
end
else
begin
row_timer_combi[i] = 0;
end
end
end
end
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
row_timer [i] <= 0;
row_timer_ready [i] <= 1'b0;
row_timer_pre_ready[i] <= 1'b0;
end
end
else
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
// Reset row_timer after push
if (push_tbp[i])
begin
row_timer [i] <= 0;
row_timer_ready [i] <= 1'b1;
row_timer_pre_ready[i] <= 1'b1;
end
// We need to update the timer as soon as possible when CFG_REG_GRANT == 0
// because after open-row-pass, row grant can happen on the next clock cycle
else if
(
(CFG_REG_GRANT == 0 && open_row_pass [i]) ||
(CFG_REG_GRANT == 1 && open_row_pass_r[i])
)
begin
if (CFG_REG_GRANT == 0)
begin
row_timer [i] <= row_timer_combi[log2_open_row_pass_flush[i]];
row_timer_ready [i] <= 1'b0;
row_timer_pre_ready[i] <= 1'b0;
end
else if (CFG_REG_GRANT == 1 && !row_timer_pre_ready[log2_open_row_pass_flush_r[i]])
begin
row_timer [i] <= row_timer[log2_open_row_pass_flush_r[i]] - 1'b1;
row_timer_ready [i] <= 1'b0;
row_timer_pre_ready[i] <= 1'b0;
end
else
begin
row_timer [i] <= 1'b0;
row_timer_ready [i] <= 1'b1;
row_timer_pre_ready[i] <= 1'b1;
end
end
else if (act_grant[i])
begin
if (compare_t_param_act_to_pch_less_than_offset)
begin
row_timer [i] <= 0;
row_timer_ready [i] <= 1'b1;
row_timer_pre_ready[i] <= 1'b1;
end
else
begin
// Load tRAS after precharge command
row_timer [i] <= offset_t_param_act_to_pch;
row_timer_ready [i] <= 1'b0;
row_timer_pre_ready[i] <= 1'b0;
end
end
else if (pch_grant[i])
begin
if (compare_t_param_pch_to_valid_less_than_offset)
begin
row_timer [i] <= 0;
row_timer_ready [i] <= 1'b1;
row_timer_pre_ready[i] <= 1'b1;
end
else
begin
// Load tRP after precharge command
row_timer [i] <= offset_t_param_pch_to_valid;
row_timer_ready [i] <= 1'b0;
row_timer_pre_ready[i] <= 1'b0;
end
end
else if (col_grant[i])
begin
row_timer [i] <= row_timer_combi[i];
row_timer_ready [i] <= 1'b0;
row_timer_pre_ready[i] <= 1'b0;
end
else
begin
if (row_timer[i] != 0)
begin
row_timer[i] <= row_timer[i] - 1'b1;
end
if (row_timer[i] <= 1)
begin
row_timer_ready[i] <= 1'b1;
end
if (row_timer[i] <= 2)
begin
row_timer_pre_ready[i] <= 1'b1;
end
end
end
end
end
// Logic to let precharge request logic that it is ready to request now
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
pch_ready[i] <= 1'b0;
end
end
else
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
if (open_row_pass[i] || open_row_pass_r[i] || pch_grant[i] || col_grant[i])
// disable pch_ready after open-row-pass and grant
// since precharge is not needed immediately after TBP is loaded
begin
pch_ready[i] <= 1'b0;
end
else if (row_timer_pre_ready[i])
begin
pch_ready[i] <= 1'b1;
end
else
begin
pch_ready[i] <= 1'b0;
end
end
end
end
// Logic to let sideband know which chip contains active banks
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_MEM_IF_CHIP; i=i+1)
begin
for (j=0; j<CFG_CTL_TBP_NUM; j=j+1)
begin
int_bank_active[i][j] <= 1'b0;
end
end
end
else
begin
for (i=0; i<CFG_MEM_IF_CHIP; i=i+1)
begin
for (j=0; j<CFG_CTL_TBP_NUM; j=j+1)
begin
if (chipsel[j] == i && valid[j])
begin
if (sb_tbp_precharge_all[j])
begin
int_bank_active[i][j] <= 1'b0;
end
else if (precharged_combi[j])
begin
int_bank_active[i][j] <= 1'b0;
end
else if (activated_combi[j])
begin
int_bank_active[i][j] <= 1'b1;
end
end
else
begin
int_bank_active[i][j] <= 1'b0; // else default to '0'
end
end
end
end
end
// Logic to let sideband know which chip contains running timer
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_MEM_IF_CHIP; i=i+1)
begin
for (j=0; j<CFG_CTL_TBP_NUM; j=j+1)
begin
int_timer_ready[i][j] <= 1'b0;
end
end
end
else
begin
for (i=0; i<CFG_MEM_IF_CHIP; i=i+1)
begin
for (j=0; j<CFG_CTL_TBP_NUM; j=j+1)
begin
if (chipsel[j] == i)
begin
if (col_grant[j] || row_grant[j])
begin
int_timer_ready[i][j] <= 1'b0;
end
else if (trc_timer_pre_ready[j] && row_timer_pre_ready[j])
begin
int_timer_ready[i][j] <= 1'b1;
end
else
begin
int_timer_ready[i][j] <= 1'b0;
end
end
else
begin
int_timer_ready[i][j] <= 1'b1; // else default to '1'
end
end
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_MEM_IF_CHIP; i=i+1)
begin
for (j=0; j<CFG_CTL_SHADOW_TBP_NUM; j=j+1)
begin
int_shadow_timer_ready[i][j] <= 1'b0;
end
end
end
else
begin
for (i=0; i<CFG_MEM_IF_CHIP; i=i+1)
begin
for (j=0; j<CFG_CTL_SHADOW_TBP_NUM; j=j+1)
begin
if (CFG_ENABLE_SHADOW_TBP)
begin
if (shadow_chipsel[j] == i)
begin
if (push_tbp[j])
begin
int_shadow_timer_ready[i][j] <= 1'b0;
end
else if (shadow_row_timer_pre_ready[j])
begin
int_shadow_timer_ready[i][j] <= 1'b1;
end
else
begin
int_shadow_timer_ready[i][j] <= 1'b0;
end
end
else
begin
int_shadow_timer_ready[i][j] <= 1'b1; // else default to '1'
end
end
else
begin
int_shadow_timer_ready[i][j] <= one;
end
end
end
end
end
always @ (*)
begin
for (i=0; i<CFG_MEM_IF_CHIP; i=i+1)
begin
bank_active[i] = |int_bank_active[i];
timer_ready[i] = &{int_shadow_timer_ready[i], int_timer_ready[i]};
end
end
//----------------------------------------------------------------------------------------------------
// Age logic
//----------------------------------------------------------------------------------------------------
// To tell the current age of each TBP entry
// so that arbiter will be able to grant the oldest entry (if there is a tie-break)
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
age[i] <= 0;
else
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
for (j=0; j<CFG_CTL_TBP_NUM; j=j+1)
begin
if (i == j)
begin
age[i][j] <= 1'b0;
end
else
begin
if (load_tbp[i])
if (!flush_tbp[j] && (valid[j]))
age[i][j] <= 1'b1;
else
age[i][j] <= 1'b0;
else if (flush_tbp[j])
age[i][j] <= 1'b0;
end
end
end
end
//----------------------------------------------------------------------------------------------------
// Starvation logic
//----------------------------------------------------------------------------------------------------
// Logic will increments when there is a col_grant to other TBP
// will cause priority to be asserted when the count reaches starvation threshold
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
starvation[i] <= 0;
else
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
if (load_tbp[i] || done[i]) // stop starvation count when the current TBP is done
starvation[i] <= 0;
else if (|col_grant && starvation[i] < cfg_starve_limit)
starvation[i] <= starvation[i]+1'b1;
end
end
//----------------------------------------------------------------------------------------------------
// Burst chop logic
//----------------------------------------------------------------------------------------------------
// Logic to determine whether we will issue burst chop in DDR3 mode only
generate
begin
if (CFG_DWIDTH_RATIO == 2)
begin
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i = 0;i < CFG_CTL_TBP_NUM;i = i + 1)
begin
burst_chop [i] <= 1'b0;
end
end
else
begin
for (i = 0;i < CFG_CTL_TBP_NUM;i = i + 1)
begin
if (cfg_type == `MMR_TYPE_DDR3)
begin
if (load_tbp [i])
begin
if (cmd_gen_size <= 2'd2 && cmd_gen_col [(CFG_DWIDTH_RATIO / 2)] == 1'b0)
burst_chop [i] <= 1'b1;
else if (cmd_gen_size == 1'b1)
burst_chop [i] <= 1'b1;
else
burst_chop [i] <= 1'b0;
end
end
else
begin
burst_chop [i] <= 1'b0;
end
end
end
end
end
else if (CFG_DWIDTH_RATIO == 4)
begin
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i = 0;i < CFG_CTL_TBP_NUM;i = i + 1)
begin
burst_chop [i] <= 1'b0;
end
end
else
begin
for (i = 0;i < CFG_CTL_TBP_NUM;i = i + 1)
begin
if (cfg_type == `MMR_TYPE_DDR3)
begin
if (load_tbp [i])
begin
if (cmd_gen_size == 1'b1)
burst_chop [i] <= 1'b1;
else
burst_chop [i] <= 1'b0;
end
end
else
begin
burst_chop [i] <= 1'b0;
end
end
end
end
end
else if (CFG_DWIDTH_RATIO == 8)
begin
// Burst chop is not available in quarter rate
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i = 0;i < CFG_CTL_TBP_NUM;i = i + 1)
begin
burst_chop [i] <= 1'b0;
end
end
else
begin
for (i = 0;i < CFG_CTL_TBP_NUM;i = i + 1)
begin
burst_chop [i] <= 1'b0;
end
end
end
end
end
endgenerate
//----------------------------------------------------------------------------------------------------------------
function integer log2;
input [31:0] value;
integer i;
begin
log2 = 0;
for(i = 0; 2**i < value; i = i + 1)
begin
log2 = i + 1;
end
end
endfunction
endmodule
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
//altera message_off 10230
`include "alt_mem_ddrx_define.iv"
`timescale 1 ps / 1 ps
module alt_mem_ddrx_timing_param #
( parameter
CFG_DWIDTH_RATIO = 2,
CFG_CTL_ARBITER_TYPE = "ROWCOL",
// cfg: general
CFG_PORT_WIDTH_TYPE = 3,
CFG_PORT_WIDTH_BURST_LENGTH = 5,
// cfg: timing parameters
CFG_PORT_WIDTH_CAS_WR_LAT = 4, // max will be 8 in DDR3
CFG_PORT_WIDTH_ADD_LAT = 3, // max will be 10 in DDR3
CFG_PORT_WIDTH_TCL = 4, // max will be 11 in DDR3
CFG_PORT_WIDTH_TRRD = 4, // 2 - 8 enough?
CFG_PORT_WIDTH_TFAW = 6, // 6 - 32 enough?
CFG_PORT_WIDTH_TRFC = 8, // 12-140 enough?
CFG_PORT_WIDTH_TREFI = 13, // 780 - 6240 enough?
CFG_PORT_WIDTH_TRCD = 4, // 2 - 11 enough?
CFG_PORT_WIDTH_TRP = 4, // 2 - 11 enough?
CFG_PORT_WIDTH_TWR = 4, // 2 - 12 enough?
CFG_PORT_WIDTH_TWTR = 4, // 1 - 10 enough?
CFG_PORT_WIDTH_TRTP = 4, // 2 - 8 enough?
CFG_PORT_WIDTH_TRAS = 5, // 4 - 29 enough?
CFG_PORT_WIDTH_TRC = 6, // 8 - 40 enough?
CFG_PORT_WIDTH_TCCD = 3, // max will be 4 in 4n prefetch architecture?
CFG_PORT_WIDTH_TMRD = 3, // 4 - ? enough?
CFG_PORT_WIDTH_SELF_RFSH_EXIT_CYCLES = 10, // max will be 512 in DDR3
CFG_PORT_WIDTH_PDN_EXIT_CYCLES = 4, // 3 - ? enough?
CFG_PORT_WIDTH_AUTO_PD_CYCLES = 16, // enough?
CFG_PORT_WIDTH_POWER_SAVING_EXIT_CYCLES = 4, // enough?
// cfg: extra timing parameters
CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_RDWR = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_PCH = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_ACT = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_RD = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_RD_DIFF_CHIP = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_WR = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_WR_BC = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_PCH = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_AP_TO_VALID = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_WR = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_WR_DIFF_CHIP = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_RD = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_RD_BC = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_RD_DIFF_CHIP = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_PCH = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_AP_TO_VALID = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_PCH_TO_VALID = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_PCH_ALL_TO_VALID = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_ACT_DIFF_BANK = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_FOUR_ACT_TO_ACT = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_ARF_TO_VALID = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_PDN_TO_VALID = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_SRF_TO_VALID = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_SRF_TO_ZQ_CAL = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_ARF_PERIOD = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_PDN_PERIOD = 4,
// Output - derived timing parameters width
T_PARAM_ACT_TO_RDWR_WIDTH = 6, // temporary
T_PARAM_ACT_TO_PCH_WIDTH = 6, // temporary
T_PARAM_ACT_TO_ACT_WIDTH = 6, // temporary
T_PARAM_RD_TO_RD_WIDTH = 6, // temporary
T_PARAM_RD_TO_RD_DIFF_CHIP_WIDTH = 6, // temporary
T_PARAM_RD_TO_WR_WIDTH = 6, // temporary
T_PARAM_RD_TO_WR_BC_WIDTH = 6, // temporary
T_PARAM_RD_TO_WR_DIFF_CHIP_WIDTH = 6, // temporary
T_PARAM_RD_TO_PCH_WIDTH = 6, // temporary
T_PARAM_RD_AP_TO_VALID_WIDTH = 6, // temporary
T_PARAM_WR_TO_WR_WIDTH = 6, // temporary
T_PARAM_WR_TO_WR_DIFF_CHIP_WIDTH = 6, // temporary
T_PARAM_WR_TO_RD_WIDTH = 6, // temporary
T_PARAM_WR_TO_RD_BC_WIDTH = 6, // temporary
T_PARAM_WR_TO_RD_DIFF_CHIP_WIDTH = 6, // temporary
T_PARAM_WR_TO_PCH_WIDTH = 6, // temporary
T_PARAM_WR_AP_TO_VALID_WIDTH = 6, // temporary
T_PARAM_PCH_TO_VALID_WIDTH = 6, // temporary
T_PARAM_PCH_ALL_TO_VALID_WIDTH = 6, // temporary
T_PARAM_ACT_TO_ACT_DIFF_BANK_WIDTH = 6, // temporary
T_PARAM_FOUR_ACT_TO_ACT_WIDTH = 6, // temporary
T_PARAM_ARF_TO_VALID_WIDTH = 8, // temporary
T_PARAM_PDN_TO_VALID_WIDTH = 6, // temporary
T_PARAM_SRF_TO_VALID_WIDTH = 10, // temporary
T_PARAM_SRF_TO_ZQ_CAL_WIDTH = 10, // temporary
T_PARAM_ARF_PERIOD_WIDTH = 13, // temporary
T_PARAM_PDN_PERIOD_WIDTH = 16, // temporary
T_PARAM_POWER_SAVING_EXIT_WIDTH = 6 // temporary
)
(
ctl_clk,
ctl_reset_n,
// Input - configuration
cfg_burst_length,
cfg_type,
// Input - memory timing parameter
cfg_cas_wr_lat,
cfg_add_lat,
cfg_tcl,
cfg_trrd,
cfg_tfaw,
cfg_trfc,
cfg_trefi,
cfg_trcd,
cfg_trp,
cfg_twr,
cfg_twtr,
cfg_trtp,
cfg_tras,
cfg_trc,
cfg_tccd,
cfg_tmrd,
cfg_self_rfsh_exit_cycles,
cfg_pdn_exit_cycles,
cfg_auto_pd_cycles,
cfg_power_saving_exit_cycles,
// Input - extra derived timing parameter
cfg_extra_ctl_clk_act_to_rdwr,
cfg_extra_ctl_clk_act_to_pch,
cfg_extra_ctl_clk_act_to_act,
cfg_extra_ctl_clk_rd_to_rd,
cfg_extra_ctl_clk_rd_to_rd_diff_chip,
cfg_extra_ctl_clk_rd_to_wr,
cfg_extra_ctl_clk_rd_to_wr_bc,
cfg_extra_ctl_clk_rd_to_wr_diff_chip,
cfg_extra_ctl_clk_rd_to_pch,
cfg_extra_ctl_clk_rd_ap_to_valid,
cfg_extra_ctl_clk_wr_to_wr,
cfg_extra_ctl_clk_wr_to_wr_diff_chip,
cfg_extra_ctl_clk_wr_to_rd,
cfg_extra_ctl_clk_wr_to_rd_bc,
cfg_extra_ctl_clk_wr_to_rd_diff_chip,
cfg_extra_ctl_clk_wr_to_pch,
cfg_extra_ctl_clk_wr_ap_to_valid,
cfg_extra_ctl_clk_pch_to_valid,
cfg_extra_ctl_clk_pch_all_to_valid,
cfg_extra_ctl_clk_act_to_act_diff_bank,
cfg_extra_ctl_clk_four_act_to_act,
cfg_extra_ctl_clk_arf_to_valid,
cfg_extra_ctl_clk_pdn_to_valid,
cfg_extra_ctl_clk_srf_to_valid,
cfg_extra_ctl_clk_srf_to_zq_cal,
cfg_extra_ctl_clk_arf_period,
cfg_extra_ctl_clk_pdn_period,
// Output - derived timing parameters
t_param_act_to_rdwr,
t_param_act_to_pch,
t_param_act_to_act,
t_param_rd_to_rd,
t_param_rd_to_rd_diff_chip,
t_param_rd_to_wr,
t_param_rd_to_wr_bc,
t_param_rd_to_wr_diff_chip,
t_param_rd_to_pch,
t_param_rd_ap_to_valid,
t_param_wr_to_wr,
t_param_wr_to_wr_diff_chip,
t_param_wr_to_rd,
t_param_wr_to_rd_bc,
t_param_wr_to_rd_diff_chip,
t_param_wr_to_pch,
t_param_wr_ap_to_valid,
t_param_pch_to_valid,
t_param_pch_all_to_valid,
t_param_act_to_act_diff_bank,
t_param_four_act_to_act,
t_param_arf_to_valid,
t_param_pdn_to_valid,
t_param_srf_to_valid,
t_param_srf_to_zq_cal,
t_param_arf_period,
t_param_pdn_period,
t_param_power_saving_exit
);
input ctl_clk;
input ctl_reset_n;
// Input - configuration
input [CFG_PORT_WIDTH_BURST_LENGTH - 1 : 0] cfg_burst_length;
input [CFG_PORT_WIDTH_TYPE - 1 : 0] cfg_type;
// Input - memory timing parameter
input [CFG_PORT_WIDTH_CAS_WR_LAT - 1 : 0] cfg_cas_wr_lat;
input [CFG_PORT_WIDTH_ADD_LAT - 1 : 0] cfg_add_lat;
input [CFG_PORT_WIDTH_TCL - 1 : 0] cfg_tcl;
input [CFG_PORT_WIDTH_TRRD - 1 : 0] cfg_trrd;
input [CFG_PORT_WIDTH_TFAW - 1 : 0] cfg_tfaw;
input [CFG_PORT_WIDTH_TRFC - 1 : 0] cfg_trfc;
input [CFG_PORT_WIDTH_TREFI - 1 : 0] cfg_trefi;
input [CFG_PORT_WIDTH_TRCD - 1 : 0] cfg_trcd;
input [CFG_PORT_WIDTH_TRP - 1 : 0] cfg_trp;
input [CFG_PORT_WIDTH_TWR - 1 : 0] cfg_twr;
input [CFG_PORT_WIDTH_TWTR - 1 : 0] cfg_twtr;
input [CFG_PORT_WIDTH_TRTP - 1 : 0] cfg_trtp;
input [CFG_PORT_WIDTH_TRAS - 1 : 0] cfg_tras;
input [CFG_PORT_WIDTH_TRC - 1 : 0] cfg_trc;
input [CFG_PORT_WIDTH_TCCD - 1 : 0] cfg_tccd;
input [CFG_PORT_WIDTH_TMRD - 1 : 0] cfg_tmrd;
input [CFG_PORT_WIDTH_SELF_RFSH_EXIT_CYCLES - 1 : 0] cfg_self_rfsh_exit_cycles;
input [CFG_PORT_WIDTH_PDN_EXIT_CYCLES - 1 : 0] cfg_pdn_exit_cycles;
input [CFG_PORT_WIDTH_AUTO_PD_CYCLES - 1 : 0] cfg_auto_pd_cycles;
input [CFG_PORT_WIDTH_POWER_SAVING_EXIT_CYCLES - 1 : 0] cfg_power_saving_exit_cycles;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_RDWR - 1 : 0] cfg_extra_ctl_clk_act_to_rdwr;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_PCH - 1 : 0] cfg_extra_ctl_clk_act_to_pch;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_ACT - 1 : 0] cfg_extra_ctl_clk_act_to_act;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_RD - 1 : 0] cfg_extra_ctl_clk_rd_to_rd;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_RD_DIFF_CHIP - 1 : 0] cfg_extra_ctl_clk_rd_to_rd_diff_chip;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_WR - 1 : 0] cfg_extra_ctl_clk_rd_to_wr;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_WR_BC - 1 : 0] cfg_extra_ctl_clk_rd_to_wr_bc;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP - 1 : 0] cfg_extra_ctl_clk_rd_to_wr_diff_chip;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_PCH - 1 : 0] cfg_extra_ctl_clk_rd_to_pch;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_AP_TO_VALID - 1 : 0] cfg_extra_ctl_clk_rd_ap_to_valid;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_WR - 1 : 0] cfg_extra_ctl_clk_wr_to_wr;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_WR_DIFF_CHIP - 1 : 0] cfg_extra_ctl_clk_wr_to_wr_diff_chip;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_RD - 1 : 0] cfg_extra_ctl_clk_wr_to_rd;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_RD_BC - 1 : 0] cfg_extra_ctl_clk_wr_to_rd_bc;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_RD_DIFF_CHIP - 1 : 0] cfg_extra_ctl_clk_wr_to_rd_diff_chip;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_PCH - 1 : 0] cfg_extra_ctl_clk_wr_to_pch;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_AP_TO_VALID - 1 : 0] cfg_extra_ctl_clk_wr_ap_to_valid;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_PCH_TO_VALID - 1 : 0] cfg_extra_ctl_clk_pch_to_valid;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_PCH_ALL_TO_VALID - 1 : 0] cfg_extra_ctl_clk_pch_all_to_valid;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_ACT_DIFF_BANK - 1 : 0] cfg_extra_ctl_clk_act_to_act_diff_bank;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_FOUR_ACT_TO_ACT - 1 : 0] cfg_extra_ctl_clk_four_act_to_act;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_ARF_TO_VALID - 1 : 0] cfg_extra_ctl_clk_arf_to_valid;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_PDN_TO_VALID - 1 : 0] cfg_extra_ctl_clk_pdn_to_valid;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_SRF_TO_VALID - 1 : 0] cfg_extra_ctl_clk_srf_to_valid;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_SRF_TO_ZQ_CAL - 1 : 0] cfg_extra_ctl_clk_srf_to_zq_cal;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_ARF_PERIOD - 1 : 0] cfg_extra_ctl_clk_arf_period;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_PDN_PERIOD - 1 : 0] cfg_extra_ctl_clk_pdn_period;
// Output - derived timing parameters
output [T_PARAM_ACT_TO_RDWR_WIDTH - 1 : 0] t_param_act_to_rdwr;
output [T_PARAM_ACT_TO_PCH_WIDTH - 1 : 0] t_param_act_to_pch;
output [T_PARAM_ACT_TO_ACT_WIDTH - 1 : 0] t_param_act_to_act;
output [T_PARAM_RD_TO_RD_WIDTH - 1 : 0] t_param_rd_to_rd;
output [T_PARAM_RD_TO_RD_DIFF_CHIP_WIDTH - 1 : 0] t_param_rd_to_rd_diff_chip;
output [T_PARAM_RD_TO_WR_WIDTH - 1 : 0] t_param_rd_to_wr;
output [T_PARAM_RD_TO_WR_BC_WIDTH - 1 : 0] t_param_rd_to_wr_bc;
output [T_PARAM_RD_TO_WR_DIFF_CHIP_WIDTH - 1 : 0] t_param_rd_to_wr_diff_chip;
output [T_PARAM_RD_TO_PCH_WIDTH - 1 : 0] t_param_rd_to_pch;
output [T_PARAM_RD_AP_TO_VALID_WIDTH - 1 : 0] t_param_rd_ap_to_valid;
output [T_PARAM_WR_TO_WR_WIDTH - 1 : 0] t_param_wr_to_wr;
output [T_PARAM_WR_TO_WR_DIFF_CHIP_WIDTH - 1 : 0] t_param_wr_to_wr_diff_chip;
output [T_PARAM_WR_TO_RD_WIDTH - 1 : 0] t_param_wr_to_rd;
output [T_PARAM_WR_TO_RD_BC_WIDTH - 1 : 0] t_param_wr_to_rd_bc;
output [T_PARAM_WR_TO_RD_DIFF_CHIP_WIDTH - 1 : 0] t_param_wr_to_rd_diff_chip;
output [T_PARAM_WR_TO_PCH_WIDTH - 1 : 0] t_param_wr_to_pch;
output [T_PARAM_WR_AP_TO_VALID_WIDTH - 1 : 0] t_param_wr_ap_to_valid;
output [T_PARAM_PCH_TO_VALID_WIDTH - 1 : 0] t_param_pch_to_valid;
output [T_PARAM_PCH_ALL_TO_VALID_WIDTH - 1 : 0] t_param_pch_all_to_valid;
output [T_PARAM_ACT_TO_ACT_DIFF_BANK_WIDTH - 1 : 0] t_param_act_to_act_diff_bank;
output [T_PARAM_FOUR_ACT_TO_ACT_WIDTH - 1 : 0] t_param_four_act_to_act;
output [T_PARAM_ARF_TO_VALID_WIDTH - 1 : 0] t_param_arf_to_valid;
output [T_PARAM_PDN_TO_VALID_WIDTH - 1 : 0] t_param_pdn_to_valid;
output [T_PARAM_SRF_TO_VALID_WIDTH - 1 : 0] t_param_srf_to_valid;
output [T_PARAM_SRF_TO_ZQ_CAL_WIDTH - 1 : 0] t_param_srf_to_zq_cal;
output [T_PARAM_ARF_PERIOD_WIDTH - 1 : 0] t_param_arf_period;
output [T_PARAM_PDN_PERIOD_WIDTH - 1 : 0] t_param_pdn_period;
output [T_PARAM_POWER_SAVING_EXIT_WIDTH - 1 : 0] t_param_power_saving_exit;
//--------------------------------------------------------------------------------------------------------
//
// [START] Register & Wires
//
//--------------------------------------------------------------------------------------------------------
// Output
reg [T_PARAM_ACT_TO_RDWR_WIDTH - 1 : 0] t_param_act_to_rdwr;
reg [T_PARAM_ACT_TO_PCH_WIDTH - 1 : 0] t_param_act_to_pch;
reg [T_PARAM_ACT_TO_ACT_WIDTH - 1 : 0] t_param_act_to_act;
reg [T_PARAM_RD_TO_RD_WIDTH - 1 : 0] t_param_rd_to_rd;
reg [T_PARAM_RD_TO_RD_DIFF_CHIP_WIDTH - 1 : 0] t_param_rd_to_rd_diff_chip;
reg [T_PARAM_RD_TO_WR_WIDTH - 1 : 0] t_param_rd_to_wr;
reg [T_PARAM_RD_TO_WR_BC_WIDTH - 1 : 0] t_param_rd_to_wr_bc;
reg [T_PARAM_RD_TO_WR_DIFF_CHIP_WIDTH - 1 : 0] t_param_rd_to_wr_diff_chip;
reg [T_PARAM_RD_TO_PCH_WIDTH - 1 : 0] t_param_rd_to_pch;
reg [T_PARAM_RD_AP_TO_VALID_WIDTH - 1 : 0] t_param_rd_ap_to_valid;
reg [T_PARAM_WR_TO_WR_WIDTH - 1 : 0] t_param_wr_to_wr;
reg [T_PARAM_WR_TO_WR_DIFF_CHIP_WIDTH - 1 : 0] t_param_wr_to_wr_diff_chip;
reg [T_PARAM_WR_TO_RD_WIDTH - 1 : 0] t_param_wr_to_rd;
reg [T_PARAM_WR_TO_RD_BC_WIDTH - 1 : 0] t_param_wr_to_rd_bc;
reg [T_PARAM_WR_TO_RD_DIFF_CHIP_WIDTH - 1 : 0] t_param_wr_to_rd_diff_chip;
reg [T_PARAM_WR_TO_PCH_WIDTH - 1 : 0] t_param_wr_to_pch;
reg [T_PARAM_WR_AP_TO_VALID_WIDTH - 1 : 0] t_param_wr_ap_to_valid;
reg [T_PARAM_PCH_TO_VALID_WIDTH - 1 : 0] t_param_pch_to_valid;
reg [T_PARAM_PCH_ALL_TO_VALID_WIDTH - 1 : 0] t_param_pch_all_to_valid;
reg [T_PARAM_ACT_TO_ACT_DIFF_BANK_WIDTH - 1 : 0] t_param_act_to_act_diff_bank;
reg [T_PARAM_FOUR_ACT_TO_ACT_WIDTH - 1 : 0] t_param_four_act_to_act;
reg [T_PARAM_ARF_TO_VALID_WIDTH - 1 : 0] t_param_arf_to_valid;
reg [T_PARAM_PDN_TO_VALID_WIDTH - 1 : 0] t_param_pdn_to_valid;
reg [T_PARAM_SRF_TO_VALID_WIDTH - 1 : 0] t_param_srf_to_valid;
reg [T_PARAM_SRF_TO_ZQ_CAL_WIDTH - 1 : 0] t_param_srf_to_zq_cal;
reg [T_PARAM_ARF_PERIOD_WIDTH - 1 : 0] t_param_arf_period;
reg [T_PARAM_PDN_PERIOD_WIDTH - 1 : 0] t_param_pdn_period;
reg [T_PARAM_POWER_SAVING_EXIT_WIDTH - 1 : 0] t_param_power_saving_exit;
//--------------------------------------------------------------------------------------------------------
//
// [END] Register & Wires
//
//--------------------------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------------------------
//
// [START] Timing Parameter Calculation
//
// Important Note:
//
// - Added "cfg_extra_ctl_clk_*" ports into our timing parameter calculation in order for us to
// tweak the timing parameter gaps in the future without changing the code
//
// - This will be very useful in HIP implementation
//
// - "cfg_extra_ctl_clk_*" must be set in term of controller clock cycles
//
//--------------------------------------------------------------------------------------------------------
// DIV is a divider for our timing parameters, DIV will be '1' in fullrate, '2' in halfrate
// and '4' in quarter rate
localparam DIV = CFG_DWIDTH_RATIO / 2;
// Use the following table to determine the optimum timing parameter
// ==========================================================================================================
// || Controller Rate || Arbiter Type || Command Transition || Remainder DIV || Offset ||
// ==========================================================================================================
// || FR || Don't care || Don't care || Yes || No ||
// ----------------------------------------------------------------------------------------------------------
// || || || Row -> Col || Yes || No ||
// -- -- ROWCOL ---------------------------------------------------------------
// || || || Col -> Row || No || Yes ||
// -- HR -----------------------------------------------------------------------------------
// || || || Row -> Col || No || Yes ||
// -- -- COLROW ---------------------------------------------------------------
// || || || Col -> Row || Yes || No ||
// ----------------------------------------------------------------------------------------------------------
// || || || Row -> Col || Yes* || No ||
// -- -- ROWCOL ---------------------------------------------------------------
// || || || Col -> Row || Yes* || Yes ||
// -- QR -----------------------------------------------------------------------------------
// || || || Row -> Col || Yes* || Yes ||
// -- -- COLROW ---------------------------------------------------------------
// || || || Col -> Row || Yes* || No ||
// ----------------------------------------------------------------------------------------------------------
// Footnote:
// * for calculation with remainder of '3' only
//---------------------------------------------------
// Remainder calculation
//---------------------------------------------------
// We need to remove the extra clock cycle in half and quarter rate
// for two subsequent different commands but remain for two subsequent same commands
// example of two subsequent different commands: ROW-TO-COL, COL-TO-ROW
// example of two subsequent same commands: ROW-TO-ROW, COL-TO-COL
// Self to self command require DIV
localparam DIV_ROW_TO_ROW = DIV;
localparam DIV_COL_TO_COL = DIV;
localparam DIV_SB_TO_SB = DIV;
localparam DIV_ROW_TO_COL = (
(CFG_DWIDTH_RATIO == 2 || CFG_DWIDTH_RATIO == 8) ?
(
DIV // Need DIV in full & quarter rate
) :
(
(CFG_DWIDTH_RATIO == 4) ?
(
(CFG_CTL_ARBITER_TYPE == "ROWCOL") ? DIV : 1 // Only need DIV in ROWCOL arbiter mode
) :
(
DIV // DIV is assigned by default
)
)
);
localparam DIV_COL_TO_ROW = (
(CFG_DWIDTH_RATIO == 2 || CFG_DWIDTH_RATIO == 8) ?
(
DIV // Need DIV in full & quarter rate
) :
(
(CFG_DWIDTH_RATIO == 4) ?
(
(CFG_CTL_ARBITER_TYPE == "COLROW") ? DIV : 1 // Only need DIV in COLROW arbiter mode
) :
(
DIV // DIV is assigned by default
)
)
);
localparam DIV_SB_TO_ROW = DIV_COL_TO_ROW; // Similar to COL_TO_ROW parameter
//---------------------------------------------------
// Remainder offset calculation
//---------------------------------------------------
// In QR, odd number calculation will only need to add extra offset when calculation's remainder is > 2
// Self to self command's remainder offset will be 0
localparam DIV_ROW_TO_ROW_OFFSET = 0;
localparam DIV_COL_TO_COL_OFFSET = 0;
localparam DIV_SB_TO_SB_OFFSET = 0;
localparam DIV_ROW_TO_COL_OFFSET = (CFG_DWIDTH_RATIO == 8) ? 2 : 0;
localparam DIV_COL_TO_ROW_OFFSET = (CFG_DWIDTH_RATIO == 8) ? 2 : 0;
localparam DIV_SB_TO_ROW_OFFSET = DIV_COL_TO_ROW_OFFSET; // Similar to COL_TO_ROW parameter
//---------------------------------------------------
// Offset calculation
//---------------------------------------------------
// We need to offset timing parameter due to HR 1T and QR 2T support
// this is because we can issue a row and column command in one controller clock cycle
// Self to self command doesn't require offset
localparam ROW_TO_ROW_OFFSET = 0;
localparam COL_TO_COL_OFFSET = 0;
localparam SB_TO_SB_OFFSET = 0;
localparam ROW_TO_COL_OFFSET = (
(CFG_DWIDTH_RATIO == 2) ?
(
0 // Offset is not required in full rate
) :
(
(CFG_CTL_ARBITER_TYPE == "ROWCOL") ? 0 : 1 // Need offset in ROWCOL arbiter mode
)
);
localparam COL_TO_ROW_OFFSET = (
(CFG_DWIDTH_RATIO == 2) ?
(
0 // Offset is not required in full rate
) :
(
(CFG_CTL_ARBITER_TYPE == "COLROW") ? 0 : 1 // Need offset in COLROW arbiter mode
)
);
localparam SB_TO_ROW_OFFSET = COL_TO_ROW_OFFSET; // Similar to COL_TO_ROW parameter
//----------------------------------------------------------------------------------------------------
// Common timing parameters, not memory type specific
//----------------------------------------------------------------------------------------------------
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
t_param_act_to_rdwr <= 0;
t_param_act_to_pch <= 0;
t_param_act_to_act <= 0;
t_param_pch_to_valid <= 0;
t_param_act_to_act_diff_bank <= 0;
t_param_four_act_to_act <= 0;
t_param_arf_to_valid <= 0;
t_param_pdn_to_valid <= 0;
t_param_srf_to_valid <= 0;
t_param_arf_period <= 0;
t_param_pdn_period <= 0;
t_param_power_saving_exit <= 0;
end
else
begin
// Set act_to_rdwr to '0' when additive latency is enabled
if (cfg_add_lat >= (cfg_trcd - 1))
t_param_act_to_rdwr <= 0 + ROW_TO_COL_OFFSET + cfg_extra_ctl_clk_act_to_rdwr ;
else
t_param_act_to_rdwr <= ((cfg_trcd - cfg_add_lat) / DIV) + (((cfg_trcd - cfg_add_lat) % DIV_ROW_TO_COL) > DIV_ROW_TO_COL_OFFSET ? 1 : 0) + ROW_TO_COL_OFFSET + cfg_extra_ctl_clk_act_to_rdwr ; // ACT to RD/WR - tRCD
t_param_act_to_pch <= (cfg_tras / DIV) + ((cfg_tras % DIV_ROW_TO_ROW) > DIV_ROW_TO_ROW_OFFSET ? 1 : 0) + ROW_TO_ROW_OFFSET + cfg_extra_ctl_clk_act_to_pch ; // ACT to PCH - tRAS
t_param_act_to_act <= (cfg_trc / DIV) + ((cfg_trc % DIV_ROW_TO_ROW) > DIV_ROW_TO_ROW_OFFSET ? 1 : 0) + ROW_TO_ROW_OFFSET + cfg_extra_ctl_clk_act_to_act ; // ACT to ACT (same bank) - tRC
t_param_pch_to_valid <= (cfg_trp / DIV) + ((cfg_trp % DIV_ROW_TO_ROW) > DIV_ROW_TO_ROW_OFFSET ? 1 : 0) + ROW_TO_ROW_OFFSET + cfg_extra_ctl_clk_pch_to_valid ; // PCH to ACT - tRP
t_param_act_to_act_diff_bank <= (cfg_trrd / DIV) + ((cfg_trrd % DIV_ROW_TO_ROW) > DIV_ROW_TO_ROW_OFFSET ? 1 : 0) + ROW_TO_ROW_OFFSET + cfg_extra_ctl_clk_act_to_act_diff_bank; // ACT to ACT (diff banks) - tRRD
t_param_four_act_to_act <= (cfg_tfaw / DIV) + ((cfg_tfaw % DIV_ROW_TO_ROW) > DIV_ROW_TO_ROW_OFFSET ? 1 : 0) + ROW_TO_ROW_OFFSET + cfg_extra_ctl_clk_four_act_to_act ; // Valid window for 4 ACT - tFAW
t_param_arf_to_valid <= (cfg_trfc / DIV) + ((cfg_trfc % DIV_SB_TO_ROW ) > DIV_ROW_TO_ROW_OFFSET ? 1 : 0) + SB_TO_ROW_OFFSET + cfg_extra_ctl_clk_arf_to_valid ; // ARF to VALID - tRFC
t_param_pdn_to_valid <= (cfg_pdn_exit_cycles / DIV) + ((cfg_pdn_exit_cycles % DIV_SB_TO_ROW ) > DIV_ROW_TO_ROW_OFFSET ? 1 : 0) + SB_TO_ROW_OFFSET + cfg_extra_ctl_clk_pdn_to_valid ; // PDN to VALID - normally 3 clock cycles
t_param_srf_to_valid <= (cfg_self_rfsh_exit_cycles / DIV) + ((cfg_self_rfsh_exit_cycles % DIV_SB_TO_ROW ) > DIV_ROW_TO_ROW_OFFSET ? 1 : 0) + SB_TO_ROW_OFFSET + cfg_extra_ctl_clk_srf_to_valid ; // SRF to VALID - normally 200 clock cycles
t_param_arf_period <= (cfg_trefi / DIV) + ((cfg_trefi % DIV_SB_TO_SB ) > DIV_SB_TO_SB_OFFSET ? 1 : 0) + SB_TO_SB_OFFSET + cfg_extra_ctl_clk_arf_period ; // ARF period - tREFI
t_param_pdn_period <= cfg_auto_pd_cycles + SB_TO_SB_OFFSET + cfg_extra_ctl_clk_pdn_period ; // PDN count after TBP is empty - specified by user
t_param_power_saving_exit <= (cfg_power_saving_exit_cycles / DIV) + ((cfg_power_saving_exit_cycles % DIV_SB_TO_SB ) > DIV_SB_TO_SB_OFFSET ? 1 : 0) + SB_TO_SB_OFFSET ; // SRF and PDN exit cycles
end
end
//----------------------------------------------------------------------------------------------------
// Memory type specific timing parameters
//----------------------------------------------------------------------------------------------------
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
t_param_rd_to_rd <= 0;
t_param_rd_to_rd_diff_chip <= 0;
t_param_rd_to_wr <= 0;
t_param_rd_to_wr_bc <= 0;
t_param_rd_to_wr_diff_chip <= 0;
t_param_rd_to_pch <= 0;
t_param_rd_ap_to_valid <= 0;
t_param_wr_to_wr <= 0;
t_param_wr_to_wr_diff_chip <= 0;
t_param_wr_to_rd <= 0;
t_param_wr_to_rd_bc <= 0;
t_param_wr_to_rd_diff_chip <= 0;
t_param_wr_to_pch <= 0;
t_param_wr_ap_to_valid <= 0;
t_param_pch_all_to_valid <= 0;
t_param_srf_to_zq_cal <= 0;
end
else
begin
if (cfg_type == `MMR_TYPE_DDR1)
begin
// DDR
// ******************************
// Note, if the below formulas are changed then the formulas in the report_timing_core.tcl files need to be changed
// to remain consistent with the controller
// ******************************
t_param_rd_to_rd <= (cfg_tccd / DIV) + ((cfg_tccd % DIV_COL_TO_COL) > DIV_COL_TO_COL_OFFSET ? 1 : 0) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_rd_to_rd ; // RD to RD - tCCD
t_param_rd_to_rd_diff_chip <= (((cfg_burst_length / 2) + 2) / DIV) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_rd_to_rd_diff_chip; // RD to RD diff rank - (BL/2) + 2 (dead cycle), should be set to tCCD for burst interrupt support
t_param_rd_to_wr <= (((cfg_burst_length / 2) + cfg_tcl) / DIV) + ((((cfg_burst_length / 2) + cfg_tcl) % DIV_COL_TO_COL) > DIV_COL_TO_COL_OFFSET ? 1 : 0) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_rd_to_wr ; // RD to WR - RL + (BL/2)
t_param_rd_to_wr_bc <= 0 + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_rd_to_wr_bc ; // RDBC to WR - 0, DDR3 specific only
t_param_rd_to_wr_diff_chip <= (((cfg_burst_length / 2) + 2) / DIV) + ((((cfg_burst_length / 2) + 2) % DIV_COL_TO_COL) > DIV_COL_TO_COL_OFFSET ? 1 : 0) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_rd_to_wr_diff_chip; // RD to WR diff rank - Same as RD to WR
t_param_rd_to_pch <= ((cfg_burst_length / 2) / DIV) + (((cfg_burst_length / 2) % DIV_COL_TO_ROW) > DIV_COL_TO_ROW_OFFSET ? 1 : 0) + COL_TO_ROW_OFFSET + cfg_extra_ctl_clk_rd_to_pch ; // RD to PCH - (BL/2)
t_param_rd_ap_to_valid <= (((cfg_burst_length / 2) + cfg_trp) / DIV) + ((((cfg_burst_length / 2) + cfg_trp) % DIV_COL_TO_ROW) > DIV_COL_TO_ROW_OFFSET ? 1 : 0) + COL_TO_ROW_OFFSET + cfg_extra_ctl_clk_rd_ap_to_valid ; // RDAP to VALID - RD to PCH + PCH to VALID
t_param_wr_to_wr <= (cfg_tccd / DIV) + ((cfg_tccd % DIV_COL_TO_COL) > DIV_COL_TO_COL_OFFSET ? 1 : 0) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_wr_to_wr ; // WR to WR - tCCD
t_param_wr_to_wr_diff_chip <= (((cfg_burst_length / 2) + 2) / DIV) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_wr_to_wr_diff_chip; // WR to WR diff rank - (BL/2) + 2 (dead cycle), should be set to tCCD for burst interrupt support
t_param_wr_to_rd <= ((1 + (cfg_burst_length / 2) + cfg_twtr) / DIV) + (((1 + (cfg_burst_length / 2) + cfg_twtr) % DIV_COL_TO_COL) > DIV_COL_TO_COL_OFFSET ? 1 : 0) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_wr_to_rd ; // WR to RD - WL + (BL/2) + tWTR, WL always 1
t_param_wr_to_rd_bc <= 0 + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_wr_to_rd_bc ; // WRBC to RD - 0, DDR3 specific only
t_param_wr_to_rd_diff_chip <= (((cfg_burst_length / 2) + 3) / DIV) + ((((cfg_burst_length / 2) + 3) % DIV_COL_TO_COL) > DIV_COL_TO_COL_OFFSET ? 1 : 0) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_wr_to_rd_diff_chip; // WR to RD diff rank - 1 + (BL/2) + 2, extra 2 dead cycles for DQS post and preamble
t_param_wr_to_pch <= ((1 + (cfg_burst_length / 2) + cfg_twr) / DIV) + (((1 + (cfg_burst_length / 2) + cfg_twr) % DIV_COL_TO_ROW) > DIV_COL_TO_ROW_OFFSET ? 1 : 0) + COL_TO_ROW_OFFSET + cfg_extra_ctl_clk_wr_to_pch ; // WR to PCH - WL + (BL/2) + tWR
t_param_wr_ap_to_valid <= ((1 + (cfg_burst_length / 2) + cfg_twr + cfg_trp) / DIV) + (((1 + (cfg_burst_length / 2) + cfg_twr + cfg_trp) % DIV_COL_TO_ROW) > DIV_COL_TO_ROW_OFFSET ? 1 : 0) + COL_TO_ROW_OFFSET + cfg_extra_ctl_clk_wr_ap_to_valid ; // WRAP to VALID - WR to PCH + PCH to VALID
t_param_pch_all_to_valid <= ((cfg_trp + 1) / DIV) + (((cfg_trp + 1) % DIV_SB_TO_ROW ) > DIV_SB_TO_ROW_OFFSET ? 1 : 0) + SB_TO_ROW_OFFSET + cfg_extra_ctl_clk_pch_all_to_valid ; // PCHALL to VALID - tRPA = tRP + 1
t_param_srf_to_zq_cal <= 0 + SB_TO_SB_OFFSET + cfg_extra_ctl_clk_srf_to_zq_cal ; // SRF to ZQ CAL - 0, DDR3 specific only
end
else if (cfg_type == `MMR_TYPE_DDR2)
begin
// DDR2
// ******************************
// Note, if the below formulas are changed then the formulas in the report_timing_core.tcl files need to be changed
// to remain consistent with the controller
// ******************************
t_param_rd_to_rd <= (cfg_tccd / DIV) + ((cfg_tccd % DIV_COL_TO_COL) > DIV_COL_TO_COL_OFFSET ? 1 : 0) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_rd_to_rd ; // RD to RD - tCCD
t_param_rd_to_rd_diff_chip <= (((cfg_burst_length / 2) + 2) / DIV) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_rd_to_rd_diff_chip; // RD to RD diff rank - (BL/2) + 2 (dead cycle), should be set to tCCD for burst interrupt support
t_param_rd_to_wr <= (((cfg_burst_length / 2) + 2) / DIV) + ((((cfg_burst_length / 2) + 2) % DIV_COL_TO_COL) > DIV_COL_TO_COL_OFFSET ? 1 : 0) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_rd_to_wr ; // RD to WR - RL - WL + (BL/2) + 1, (RL - WL) will always be '1'
t_param_rd_to_wr_bc <= 0 + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_rd_to_wr_bc ; // RDBC to WR - 0, DDR3 specific only
t_param_rd_to_wr_diff_chip <= (((cfg_burst_length / 2) + 2) / DIV) + ((((cfg_burst_length / 2) + 2) % DIV_COL_TO_COL) > DIV_COL_TO_COL_OFFSET ? 1 : 0) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_rd_to_wr_diff_chip; // RD to WR diff rank - Same as RD to WR
t_param_rd_to_pch <= ((cfg_add_lat + (cfg_burst_length / 2) - 2 + max(cfg_trtp, 2)) / DIV) + (((cfg_add_lat + (cfg_burst_length / 2) - 2 + max(cfg_trtp, 2)) % DIV_COL_TO_ROW) > DIV_COL_TO_ROW_OFFSET ? 1 : 0) + COL_TO_ROW_OFFSET + cfg_extra_ctl_clk_rd_to_pch ; // RD to PCH - AL + (BL/2) - 2 + max(tRTP or 2)
t_param_rd_ap_to_valid <= ((cfg_add_lat + (cfg_burst_length / 2) - 2 + max(cfg_trtp, 2) + cfg_trp) / DIV) + (((cfg_add_lat + (cfg_burst_length / 2) - 2 + max(cfg_trtp, 2) + cfg_trp) % DIV_COL_TO_ROW) > DIV_COL_TO_ROW_OFFSET ? 1 : 0) + COL_TO_ROW_OFFSET + cfg_extra_ctl_clk_rd_ap_to_valid ; // RDAP to VALID - RD to PCH + PCH to VALID
t_param_wr_to_wr <= (cfg_tccd / DIV) + ((cfg_tccd % DIV_COL_TO_COL) > DIV_COL_TO_COL_OFFSET ? 1 : 0) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_wr_to_wr ; // WR to WR - tCCD
t_param_wr_to_wr_diff_chip <= (((cfg_burst_length / 2) + 2) / DIV) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_wr_to_wr_diff_chip; // WR to WR diff rank - (BL/2) + 2 (dead cycle), should be set to tCCD for burst interrupt support
t_param_wr_to_rd <= ((cfg_tcl - 1 + (cfg_burst_length / 2) + cfg_twtr) / DIV) + (((cfg_tcl - 1 + (cfg_burst_length / 2) + cfg_twtr) % DIV_COL_TO_COL) > DIV_COL_TO_COL_OFFSET ? 1 : 0) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_wr_to_rd ; // WR to RD - WL + (BL/2) + tWTR
t_param_wr_to_rd_bc <= 0 + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_wr_to_rd_bc ; // WRBC to RD - 0, DDR3 specific only
t_param_wr_to_rd_diff_chip <= (((cfg_burst_length / 2) + 1) / DIV) + ((((cfg_burst_length / 2) + 1) % DIV_COL_TO_COL) > DIV_COL_TO_COL_OFFSET ? 1 : 0) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_wr_to_rd_diff_chip; // WR to RD diff rank - WL - RL + (BL/2) + 2, extra 2 dead cycles for DQS post and preamble
t_param_wr_to_pch <= ((cfg_add_lat + cfg_tcl - 1 + (cfg_burst_length / 2) + cfg_twr) / DIV) + (((cfg_add_lat + cfg_tcl - 1 + (cfg_burst_length / 2) + cfg_twr) % DIV_COL_TO_ROW) > DIV_COL_TO_ROW_OFFSET ? 1 : 0) + COL_TO_ROW_OFFSET + cfg_extra_ctl_clk_wr_to_pch ; // WR to PCH - WL + (BL/2) + tWR
t_param_wr_ap_to_valid <= ((cfg_add_lat + cfg_tcl - 1 + (cfg_burst_length / 2) + cfg_twr + cfg_trp) / DIV) + (((cfg_add_lat + cfg_tcl - 1 + (cfg_burst_length / 2) + cfg_twr + cfg_trp) % DIV_COL_TO_ROW) > DIV_COL_TO_ROW_OFFSET ? 1 : 0) + COL_TO_ROW_OFFSET + cfg_extra_ctl_clk_wr_ap_to_valid ; // WRAP to VALID - WR to PCH + PCH to VALID
t_param_pch_all_to_valid <= ((cfg_trp + 1) / DIV) + (((cfg_trp + 1) % DIV_SB_TO_ROW ) > DIV_SB_TO_ROW_OFFSET ? 1 : 0) + SB_TO_ROW_OFFSET + cfg_extra_ctl_clk_pch_all_to_valid ; // PCHALL to VALID - tRPA = tRP + 1
t_param_srf_to_zq_cal <= 0 + SB_TO_SB_OFFSET + cfg_extra_ctl_clk_srf_to_zq_cal ; // SRF to ZQ CAL - 0, DDR3 specific only
end
else if (cfg_type == `MMR_TYPE_DDR3)
begin
// ******************************
// Note, if the below formulas are changed then the formulas in the report_timing_core.tcl files need to be changed
// to remain consistent with the controller
// ******************************
t_param_rd_to_rd <= ((cfg_burst_length / 2) / DIV) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_rd_to_rd ; // RD to RD - BL/2, not tCCD because there is no burst interrupt support in DDR3
t_param_rd_to_rd_diff_chip <= (((cfg_burst_length / 2) + 2) / DIV) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_rd_to_rd_diff_chip; // RD to RD diff rank - (BL/2) + 2 (dead cycle), should be set to tCCD for burst interrupt support
t_param_rd_to_wr <= ((cfg_tcl - cfg_cas_wr_lat + (cfg_burst_length / 2) + 2) / DIV) + (((cfg_tcl - cfg_cas_wr_lat + (cfg_burst_length / 2) + 2) % DIV_COL_TO_COL) > DIV_COL_TO_COL_OFFSET ? 1 : 0) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_rd_to_wr ; // RD to WR - RL - WL + (BL/2) + 2
t_param_rd_to_wr_bc <= ((cfg_tcl - cfg_cas_wr_lat + (cfg_burst_length / 4) + 2) / DIV) + (((cfg_tcl - cfg_cas_wr_lat + (cfg_burst_length / 4) + 2) % DIV_COL_TO_COL) > DIV_COL_TO_COL_OFFSET ? 1 : 0) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_rd_to_wr_bc ; // RDBC to WR - RL - WL + (BL/4) + 2
t_param_rd_to_wr_diff_chip <= ((cfg_tcl - cfg_cas_wr_lat + (cfg_burst_length / 2) + 2) / DIV) + (((cfg_tcl - cfg_cas_wr_lat + (cfg_burst_length / 2) + 2) % DIV_COL_TO_COL) > DIV_COL_TO_COL_OFFSET ? 1 : 0) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_rd_to_wr_diff_chip; // RD to WR diff rank - Same as RD to WR
t_param_rd_to_pch <= ((cfg_add_lat + max(cfg_trtp, 4)) / DIV) + (((cfg_add_lat + max(cfg_trtp, 4)) % DIV_COL_TO_ROW) > DIV_COL_TO_ROW_OFFSET ? 1 : 0) + COL_TO_ROW_OFFSET + cfg_extra_ctl_clk_rd_to_pch ; // RD to PCH - AL + max(tRTP or 4)
t_param_rd_ap_to_valid <= ((cfg_add_lat + max(cfg_trtp, 4) + cfg_trp) / DIV) + (((cfg_add_lat + max(cfg_trtp, 4) + cfg_trp) % DIV_COL_TO_ROW) > DIV_COL_TO_ROW_OFFSET ? 1 : 0) + COL_TO_ROW_OFFSET + cfg_extra_ctl_clk_rd_ap_to_valid ; // RDAP to VALID - RD to PCH + PCH to VALID
t_param_wr_to_wr <= ((cfg_burst_length / 2) / DIV) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_wr_to_wr ; // WR to WR - BL/2, not tCCD because there is no burst interrupt support in DDR3
t_param_wr_to_wr_diff_chip <= (((cfg_burst_length / 2) + 2) / DIV) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_wr_to_wr_diff_chip; // WR to WR diff rank - (BL/2) + 2 (dead cycle), should be set to tCCD for burst interrupt support
t_param_wr_to_rd <= ((cfg_cas_wr_lat + (cfg_burst_length / 2) + max(cfg_twtr, 4)) / DIV) + (((cfg_cas_wr_lat + (cfg_burst_length / 2) + max(cfg_twtr, 4)) % DIV_COL_TO_COL) > DIV_COL_TO_COL_OFFSET ? 1 : 0) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_wr_to_rd ; // WR to RD - WL + (BL/2) + max(tWTR or 4)
t_param_wr_to_rd_bc <= ((cfg_cas_wr_lat + (cfg_burst_length / 2) + max(cfg_twtr, 4)) / DIV) + (((cfg_cas_wr_lat + (cfg_burst_length / 2) + max(cfg_twtr, 4)) % DIV_COL_TO_COL) > DIV_COL_TO_COL_OFFSET ? 1 : 0) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_wr_to_rd_bc ; // WRBC to RD - Same as WR to RD
t_param_wr_to_rd_diff_chip <= (((cfg_cas_wr_lat - cfg_tcl) + (cfg_burst_length / 2) + 2) / DIV) + ((((cfg_cas_wr_lat - cfg_tcl) + (cfg_burst_length / 2) + 2) % DIV_COL_TO_COL) > DIV_COL_TO_COL_OFFSET ? 1 : 0) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_wr_to_rd_diff_chip; // WR to RD diff rank - WL - RL + (BL/2) + 2, extra 2 dead cycles for DQS post and preamble
t_param_wr_to_pch <= ((cfg_add_lat + cfg_cas_wr_lat + (cfg_burst_length / 2) + cfg_twr) / DIV) + (((cfg_add_lat + cfg_cas_wr_lat + (cfg_burst_length / 2) + cfg_twr) % DIV_COL_TO_ROW) > DIV_COL_TO_ROW_OFFSET ? 1 : 0) + COL_TO_ROW_OFFSET + cfg_extra_ctl_clk_wr_to_pch ; // WR to PCH - WL + (BL/2) + tWR
t_param_wr_ap_to_valid <= ((cfg_add_lat + cfg_cas_wr_lat + (cfg_burst_length / 2) + cfg_twr + cfg_trp) / DIV) + (((cfg_add_lat + cfg_cas_wr_lat + (cfg_burst_length / 2) + cfg_twr + cfg_trp) % DIV_COL_TO_ROW) > DIV_COL_TO_ROW_OFFSET ? 1 : 0) + COL_TO_ROW_OFFSET + cfg_extra_ctl_clk_wr_ap_to_valid ; // WRAP to VALID - WR to PCH + PCH to VALID
t_param_pch_all_to_valid <= (cfg_trp / DIV) + ((cfg_trp % DIV_SB_TO_ROW ) > DIV_SB_TO_ROW_OFFSET ? 1 : 0) + SB_TO_ROW_OFFSET + cfg_extra_ctl_clk_pch_all_to_valid ; // PCHALL to VALID - tRP
t_param_srf_to_zq_cal <= ((cfg_self_rfsh_exit_cycles / 2) / DIV) + SB_TO_SB_OFFSET + cfg_extra_ctl_clk_srf_to_zq_cal ; // SRF to ZQ CAL - SRF exit time divided by 2
end
else if (cfg_type == `MMR_TYPE_LPDDR1)
begin
// LPDDR
// ******************************
// Note, if the below formulas are changed then the formulas in the report_timing_core.tcl files need to be changed
// to remain consistent with the controller
// ******************************
t_param_rd_to_rd <= (cfg_tccd / DIV) + ((cfg_tccd % DIV_COL_TO_COL) > DIV_COL_TO_COL_OFFSET ? 1 : 0) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_rd_to_rd ; // RD to RD - tCCD
t_param_rd_to_rd_diff_chip <= (((cfg_burst_length / 2) + 2) / DIV) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_rd_to_rd_diff_chip; // RD to RD diff rank - (BL/2) + 2 (dead cycle), should be set to tCCD for burst interrupt support
t_param_rd_to_wr <= (((cfg_burst_length / 2) + cfg_tcl) / DIV) + ((((cfg_burst_length / 2) + cfg_tcl) % DIV_COL_TO_COL) > DIV_COL_TO_COL_OFFSET ? 1 : 0) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_rd_to_wr ; // RD to WR - RL + (BL/2)
t_param_rd_to_wr_bc <= 0 + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_rd_to_wr_bc ; // RDBC to WR - 0, DDR3 specific only
t_param_rd_to_wr_diff_chip <= (((cfg_burst_length / 2) + 2) / DIV) + ((((cfg_burst_length / 2) + 2) % DIV_COL_TO_COL) > DIV_COL_TO_COL_OFFSET ? 1 : 0) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_rd_to_wr_diff_chip; // RD to WR diff rank - Same as RD to WR
t_param_rd_to_pch <= ((cfg_burst_length / 2) / DIV) + (((cfg_burst_length / 2) % DIV_COL_TO_ROW) > DIV_COL_TO_ROW_OFFSET ? 1 : 0) + COL_TO_ROW_OFFSET + cfg_extra_ctl_clk_rd_to_pch ; // RD to PCH - (BL/2)
t_param_rd_ap_to_valid <= (((cfg_burst_length / 2) + cfg_trp) / DIV) + ((((cfg_burst_length / 2) + cfg_trp) % DIV_COL_TO_ROW) > DIV_COL_TO_ROW_OFFSET ? 1 : 0) + COL_TO_ROW_OFFSET + cfg_extra_ctl_clk_rd_ap_to_valid ; // RDAP to VALID - RD to PCH + PCH to VALID
t_param_wr_to_wr <= (cfg_tccd / DIV) + ((cfg_tccd % DIV_COL_TO_COL) > DIV_COL_TO_COL_OFFSET ? 1 : 0) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_wr_to_wr ; // WR to WR - tCCD
t_param_wr_to_wr_diff_chip <= (((cfg_burst_length / 2) + 2) / DIV) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_wr_to_wr_diff_chip; // WR to WR diff rank - (BL/2) + 2 (dead cycle), should be set to tCCD for burst interrupt support
t_param_wr_to_rd <= ((1 + (cfg_burst_length / 2) + cfg_twtr) / DIV) + (((1 + (cfg_burst_length / 2) + cfg_twtr) % DIV_COL_TO_COL) > DIV_COL_TO_COL_OFFSET ? 1 : 0) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_wr_to_rd ; // WR to RD - WL + (BL/2) + tWTR, WL always 1
t_param_wr_to_rd_bc <= 0 + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_wr_to_rd_bc ; // WRBC to RD - 0, DDR3 specific only
t_param_wr_to_rd_diff_chip <= (((cfg_burst_length / 2) + 3) / DIV) + ((((cfg_burst_length / 2) + 3) % DIV_COL_TO_COL) > DIV_COL_TO_COL_OFFSET ? 1 : 0) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_wr_to_rd_diff_chip; // WR to RD diff rank - 1 + (BL/2) + 2, extra 2 dead cycles for DQS post and preamble
t_param_wr_to_pch <= ((1 + (cfg_burst_length / 2) + cfg_twr) / DIV) + (((1 + (cfg_burst_length / 2) + cfg_twr) % DIV_COL_TO_ROW) > DIV_COL_TO_ROW_OFFSET ? 1 : 0) + COL_TO_ROW_OFFSET + cfg_extra_ctl_clk_wr_to_pch ; // WR to PCH - WL + (BL/2) + tWR
t_param_wr_ap_to_valid <= ((1 + (cfg_burst_length / 2) + cfg_twr + cfg_trp) / DIV) + (((1 + (cfg_burst_length / 2) + cfg_twr + cfg_trp) % DIV_COL_TO_ROW) > DIV_COL_TO_ROW_OFFSET ? 1 : 0) + COL_TO_ROW_OFFSET + cfg_extra_ctl_clk_wr_ap_to_valid ; // WRAP to VALID - WR to PCH + PCH to VALID
t_param_pch_all_to_valid <= ((cfg_trp + 1) / DIV) + (((cfg_trp + 1) % DIV_SB_TO_ROW ) > DIV_SB_TO_ROW_OFFSET ? 1 : 0) + SB_TO_ROW_OFFSET + cfg_extra_ctl_clk_pch_all_to_valid ; // PCHALL to VALID - tRPA = tRP + 1
t_param_srf_to_zq_cal <= 0 + SB_TO_SB_OFFSET + cfg_extra_ctl_clk_srf_to_zq_cal ; // SRF to ZQ CAL - 0, DDR3 specific only
end
else if (cfg_type == `MMR_TYPE_LPDDR2)
begin
// LPDDR2
// ******************************
// Note, if the below formulas are changed then the formulas in the report_timing_core.tcl files need to be changed
// to remain consistent with the controller
// ******************************
t_param_rd_to_rd <= (cfg_tccd / DIV) + ((cfg_tccd % DIV_COL_TO_COL) > DIV_COL_TO_COL_OFFSET ? 1 : 0) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_rd_to_rd ; // RD to RD - tCCD
t_param_rd_to_rd_diff_chip <= (((cfg_burst_length / 2) + 2) / DIV) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_rd_to_rd_diff_chip; // RD to RD diff rank - (BL/2) + 2 (dead cycle), should be set to tCCD for burst interrupt support
t_param_rd_to_wr <= ((cfg_tcl - cfg_cas_wr_lat + (cfg_burst_length / 2) + 1) / DIV) + (((cfg_tcl - cfg_cas_wr_lat + (cfg_burst_length / 2) + 1) % DIV_COL_TO_COL) > DIV_COL_TO_COL_OFFSET ? 1 : 0) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_rd_to_wr ; // RD to WR - RL - WL + (BL/2) + 2
t_param_rd_to_wr_bc <= 0 + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_rd_to_wr_bc ; // RDBC to WR - 0, DDR3 specific only
t_param_rd_to_wr_diff_chip <= ((cfg_tcl - cfg_cas_wr_lat + (cfg_burst_length / 2) + 1) / DIV) + (((cfg_tcl - cfg_cas_wr_lat + (cfg_burst_length / 2) + 1) % DIV_COL_TO_COL) > DIV_COL_TO_COL_OFFSET ? 1 : 0) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_rd_to_wr_diff_chip; // RD to WR diff rank - Same as RD to WR
t_param_rd_to_pch <= ((cfg_add_lat + (cfg_burst_length / 2) - cfg_tccd + max(cfg_trtp, 2)) / DIV) + (((cfg_add_lat + (cfg_burst_length / 2) - cfg_tccd + max(cfg_trtp, 2)) % DIV_COL_TO_ROW) > DIV_COL_TO_ROW_OFFSET ? 1 : 0) + COL_TO_ROW_OFFSET + cfg_extra_ctl_clk_rd_to_pch ; // RD to PCH - AL + (BL/2) - 2 + max(tRTP or 2)
t_param_rd_ap_to_valid <= ((cfg_add_lat + (cfg_burst_length / 2) - cfg_tccd + max(cfg_trtp, 2) + cfg_trp) / DIV) + (((cfg_add_lat + (cfg_burst_length / 2) - cfg_tccd + max(cfg_trtp, 2) + cfg_trp) % DIV_COL_TO_ROW) > DIV_COL_TO_ROW_OFFSET ? 1 : 0) + COL_TO_ROW_OFFSET + cfg_extra_ctl_clk_rd_ap_to_valid ; // RDAP to VALID - RD to PCH + PCH to VALID
t_param_wr_to_wr <= (cfg_tccd / DIV) + ((cfg_tccd % DIV_COL_TO_COL) > DIV_COL_TO_COL_OFFSET ? 1 : 0) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_wr_to_wr ; // WR to WR - tCCD
t_param_wr_to_wr_diff_chip <= (((cfg_burst_length / 2) + 2) / DIV) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_wr_to_wr_diff_chip; // WR to WR diff rank - (BL/2) + 2 (dead cycle), should be set to tCCD for burst interrupt support
t_param_wr_to_rd <= ((cfg_cas_wr_lat + (cfg_burst_length / 2) + max(cfg_twtr, 2) + 1) / DIV) + (((cfg_cas_wr_lat + (cfg_burst_length / 2) + max(cfg_twtr, 2) + 1) % DIV_COL_TO_COL) > DIV_COL_TO_COL_OFFSET ? 1 : 0) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_wr_to_rd ; // WR to RD - WL + (BL/2) + max(tWTR or 4)
t_param_wr_to_rd_bc <= 0 + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_wr_to_rd_bc ; // WRBC to RD - 0, DDR3 specific only
t_param_wr_to_rd_diff_chip <= (((cfg_cas_wr_lat - cfg_tcl) + (cfg_burst_length / 2) + 2) / DIV) + ((((cfg_cas_wr_lat - cfg_tcl) + (cfg_burst_length / 2) + 2) % DIV_COL_TO_COL) > DIV_COL_TO_COL_OFFSET ? 1 : 0) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_wr_to_rd_diff_chip; // WR to RD diff rank - WL - RL + (BL/2) + 2, extra 2 dead cycles for DQS post and preamble
t_param_wr_to_pch <= ((cfg_add_lat + cfg_cas_wr_lat + (cfg_burst_length / 2) + cfg_twr + 1) / DIV) + (((cfg_add_lat + cfg_cas_wr_lat + (cfg_burst_length / 2) + cfg_twr + 1) % DIV_COL_TO_ROW) > DIV_COL_TO_ROW_OFFSET ? 1 : 0) + COL_TO_ROW_OFFSET + cfg_extra_ctl_clk_wr_to_pch ; // WR to PCH - WL + (BL/2) + tWR
t_param_wr_ap_to_valid <= ((cfg_add_lat + cfg_cas_wr_lat + (cfg_burst_length / 2) + cfg_twr + 1 + cfg_trp) / DIV) + (((cfg_add_lat + cfg_cas_wr_lat + (cfg_burst_length / 2) + cfg_twr + 1 + cfg_trp) % DIV_COL_TO_ROW) > DIV_COL_TO_ROW_OFFSET ? 1 : 0) + COL_TO_ROW_OFFSET + cfg_extra_ctl_clk_wr_ap_to_valid ; // WRAP to VALID - WR to PCH + PCH to VALID
t_param_pch_all_to_valid <= ((cfg_trp + 1) / DIV) + (((cfg_trp + 1) % DIV_SB_TO_ROW ) > DIV_SB_TO_ROW_OFFSET ? 1 : 0) + SB_TO_ROW_OFFSET + cfg_extra_ctl_clk_pch_all_to_valid ; // PCHALL to VALID - tRPA = tRP + 1
t_param_srf_to_zq_cal <= 0 + SB_TO_SB_OFFSET + cfg_extra_ctl_clk_srf_to_zq_cal ; // SRF to ZQ CAL - 0, DDR3 specific only
end
end
end
// Function to determine max of 2 inputs
localparam MAX_FUNCTION_PORT_WIDTH = (CFG_PORT_WIDTH_TRTP > CFG_PORT_WIDTH_TWTR) ? CFG_PORT_WIDTH_TRTP : CFG_PORT_WIDTH_TWTR;
function [MAX_FUNCTION_PORT_WIDTH - 1 : 0] max;
input [MAX_FUNCTION_PORT_WIDTH - 1 : 0] value1;
input [MAX_FUNCTION_PORT_WIDTH - 1 : 0] value2;
begin
if (value1 > value2)
max = value1;
else
max = value2;
end
endfunction
//--------------------------------------------------------------------------------------------------------
//
// [END] Timing Parameter Calculation
//
//--------------------------------------------------------------------------------------------------------
endmodule
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
//altera message_off 10230 10036
module alt_mem_ddrx_wdata_path
# (
// module parameter port list
parameter
CFG_LOCAL_DATA_WIDTH = 16,
CFG_MEM_IF_DQ_WIDTH = 8,
CFG_MEM_IF_DQS_WIDTH = 1,
CFG_INT_SIZE_WIDTH = 5,
CFG_DATA_ID_WIDTH = 4,
CFG_DRAM_WLAT_GROUP = 1,
CFG_LOCAL_WLAT_GROUP = 1,
CFG_TBP_NUM = 8,
CFG_BUFFER_ADDR_WIDTH = 10,
CFG_DWIDTH_RATIO = 2,
CFG_ECC_MULTIPLES = 1,
CFG_WDATA_REG = 0,
CFG_PARTIAL_BE_PER_WORD_ENABLE = 1,
CFG_ECC_CODE_WIDTH = 8,
CFG_PORT_WIDTH_BURST_LENGTH = 5,
CFG_PORT_WIDTH_ENABLE_ECC = 1,
CFG_PORT_WIDTH_ENABLE_AUTO_CORR = 1,
CFG_PORT_WIDTH_ENABLE_NO_DM = 1,
CFG_PORT_WIDTH_ENABLE_ECC_CODE_OVERWRITES = 1,
CFG_PORT_WIDTH_INTERFACE_WIDTH = 8
)
(
// port list
ctl_clk,
ctl_reset_n,
// configuration signals
cfg_burst_length,
cfg_enable_ecc,
cfg_enable_auto_corr,
cfg_enable_no_dm,
cfg_enable_ecc_code_overwrites,
cfg_interface_width,
// command generator & TBP command load interface / cmd update interface
wdatap_free_id_valid,
wdatap_free_id_dataid,
proc_busy,
proc_load,
proc_load_dataid,
proc_write,
tbp_load_index,
proc_size,
// input interface data channel / buffer write interface
wr_data_mem_full,
write_data_en,
write_data,
byte_en,
// notify TBP interface
data_complete,
data_rmw_complete,
data_partial_be,
// AFI interface / buffer read interface
doing_write,
dataid,
dataid_vector,
rdwr_data_valid,
rmw_correct,
rmw_partial,
doing_write_first,
dataid_first,
dataid_vector_first,
rdwr_data_valid_first,
rmw_correct_first,
rmw_partial_first,
doing_write_first_vector,
rdwr_data_valid_first_vector,
doing_write_last,
dataid_last,
dataid_vector_last,
rdwr_data_valid_last,
rmw_correct_last,
rmw_partial_last,
wdatap_data,
wdatap_rmw_partial_data,
wdatap_rmw_correct_data,
wdatap_rmw_partial,
wdatap_rmw_correct,
wdatap_dm,
wdatap_ecc_code,
wdatap_ecc_code_overwrite,
// RMW fifo interface, from rdatap
rmwfifo_data_valid,
rmwfifo_data,
rmwfifo_ecc_dbe,
rmwfifo_ecc_code
);
// -----------------------------
// local parameter declarations
// -----------------------------
localparam CFG_MEM_IF_DQ_PER_DQS = CFG_MEM_IF_DQ_WIDTH / CFG_MEM_IF_DQS_WIDTH;
localparam CFG_BURSTCOUNT_TRACKING_WIDTH = CFG_BUFFER_ADDR_WIDTH+1;
localparam CFG_RMWFIFO_ECC_DBE_WIDTH = CFG_ECC_MULTIPLES;
localparam CFG_RMWFIFO_ECC_CODE_WIDTH = CFG_ECC_MULTIPLES * CFG_ECC_CODE_WIDTH;
localparam CFG_RMWDATA_FIFO_DATA_WIDTH = CFG_LOCAL_DATA_WIDTH + CFG_RMWFIFO_ECC_DBE_WIDTH + CFG_RMWFIFO_ECC_CODE_WIDTH;
localparam CFG_RMWDATA_FIFO_ADDR_WIDTH = (CFG_INT_SIZE_WIDTH == 1) ? CFG_INT_SIZE_WIDTH : CFG_INT_SIZE_WIDTH-1;
localparam CFG_LOCAL_BE_WIDTH = CFG_LOCAL_DATA_WIDTH / 8;
localparam CFG_LOCAL_DM_WIDTH = CFG_LOCAL_DATA_WIDTH / CFG_MEM_IF_DQ_PER_DQS; // to get the correct DM width based on x4 or x8 mode
localparam CFG_MMR_DRAM_DATA_WIDTH = CFG_PORT_WIDTH_INTERFACE_WIDTH;
localparam CFG_MMR_DRAM_DM_WIDTH = CFG_PORT_WIDTH_INTERFACE_WIDTH - 2; // Minus 3 because byte enable will be divided by 4/8
localparam integer CFG_DATAID_ARRAY_DEPTH = (2**CFG_DATA_ID_WIDTH);
localparam CFG_WR_DATA_WIDTH_PER_DQS_GROUP = CFG_LOCAL_DATA_WIDTH / CFG_LOCAL_WLAT_GROUP / CFG_DWIDTH_RATIO;
localparam CFG_WR_DM_WIDTH_PER_DQS_GROUP = CFG_LOCAL_DM_WIDTH / CFG_LOCAL_WLAT_GROUP / CFG_DWIDTH_RATIO;
// -----------------------------
// port declaration
// -----------------------------
// clock and reset
input ctl_clk;
input ctl_reset_n;
// configuration signals
input [CFG_PORT_WIDTH_BURST_LENGTH - 1 : 0] cfg_burst_length;
input [CFG_PORT_WIDTH_ENABLE_ECC - 1 : 0] cfg_enable_ecc;
input [CFG_PORT_WIDTH_ENABLE_AUTO_CORR - 1 : 0] cfg_enable_auto_corr;
input [CFG_PORT_WIDTH_ENABLE_NO_DM - 1 : 0] cfg_enable_no_dm;
input [CFG_PORT_WIDTH_ENABLE_ECC_CODE_OVERWRITES - 1 : 0] cfg_enable_ecc_code_overwrites; // overwrite (and don't re-calculate) ecc code on DBE
input [CFG_PORT_WIDTH_INTERFACE_WIDTH - 1 : 0] cfg_interface_width;
// command generator free dataid interface
output wdatap_free_id_valid;
output [CFG_DATA_ID_WIDTH-1:0] wdatap_free_id_dataid;
// command generator & TBP command load interface / cmd update interface
input proc_busy;
input proc_load;
input proc_load_dataid;
input proc_write;
input [CFG_TBP_NUM-1:0] tbp_load_index;
input [CFG_INT_SIZE_WIDTH-1:0] proc_size;
// input interface data channel / buffer write interface
output wr_data_mem_full;
input write_data_en;
input [CFG_LOCAL_DATA_WIDTH-1:0] write_data;
input [CFG_LOCAL_BE_WIDTH-1:0] byte_en;
// notify TBP interface
output [CFG_TBP_NUM-1:0] data_complete;
output data_rmw_complete; // broadcast to TBP's
output data_partial_be;
// AFI interface / buffer read interface
input [CFG_DRAM_WLAT_GROUP-1:0] doing_write;
input [CFG_DRAM_WLAT_GROUP*CFG_DATA_ID_WIDTH-1:0] dataid;
input [CFG_DRAM_WLAT_GROUP*CFG_DATAID_ARRAY_DEPTH-1:0] dataid_vector;
input [CFG_DRAM_WLAT_GROUP-1:0] rdwr_data_valid;
input [CFG_DRAM_WLAT_GROUP-1:0] rmw_correct;
input [CFG_DRAM_WLAT_GROUP-1:0] rmw_partial;
input doing_write_first;
input [CFG_DATA_ID_WIDTH-1:0] dataid_first;
input [CFG_DATAID_ARRAY_DEPTH-1:0] dataid_vector_first;
input rdwr_data_valid_first;
input rmw_correct_first;
input rmw_partial_first;
input [CFG_DRAM_WLAT_GROUP-1:0] doing_write_first_vector;
input [CFG_DRAM_WLAT_GROUP-1:0] rdwr_data_valid_first_vector;
input doing_write_last;
input [CFG_DATA_ID_WIDTH-1:0] dataid_last;
input [CFG_DATAID_ARRAY_DEPTH-1:0] dataid_vector_last;
input rdwr_data_valid_last;
input rmw_correct_last;
input rmw_partial_last;
output [CFG_LOCAL_DATA_WIDTH-1:0] wdatap_data;
output [CFG_LOCAL_DATA_WIDTH-1:0] wdatap_rmw_partial_data;
output [CFG_LOCAL_DATA_WIDTH-1:0] wdatap_rmw_correct_data;
output wdatap_rmw_partial;
output wdatap_rmw_correct;
output [CFG_LOCAL_DM_WIDTH-1:0] wdatap_dm;
output [CFG_ECC_MULTIPLES * CFG_ECC_CODE_WIDTH - 1 : 0] wdatap_ecc_code;
output [CFG_ECC_MULTIPLES - 1 : 0] wdatap_ecc_code_overwrite;
// RMW fifo interface
input rmwfifo_data_valid;
input [CFG_LOCAL_DATA_WIDTH-1:0] rmwfifo_data;
input [CFG_ECC_MULTIPLES- 1 : 0] rmwfifo_ecc_dbe;
input [CFG_ECC_MULTIPLES * CFG_ECC_CODE_WIDTH - 1 : 0] rmwfifo_ecc_code;
// -----------------------------
// port type declaration
// -----------------------------
// clock and reset
wire ctl_clk;
wire ctl_reset_n;
// configuration signals
wire [CFG_PORT_WIDTH_BURST_LENGTH - 1 : 0] cfg_burst_length;
wire [CFG_PORT_WIDTH_ENABLE_ECC - 1 : 0] cfg_enable_ecc;
wire [CFG_PORT_WIDTH_ENABLE_AUTO_CORR - 1 : 0] cfg_enable_auto_corr;
wire [CFG_PORT_WIDTH_ENABLE_NO_DM - 1 : 0] cfg_enable_no_dm;
wire [CFG_PORT_WIDTH_ENABLE_ECC_CODE_OVERWRITES - 1 : 0] cfg_enable_ecc_code_overwrites; // overwrite (and don't re-calculate) ecc code on DBE
wire [CFG_PORT_WIDTH_INTERFACE_WIDTH - 1 : 0] cfg_interface_width;
// command generator free dataid interface
wire wdatap_free_id_valid;
wire wdatap_int_free_id_valid;
wire [CFG_DATA_ID_WIDTH-1:0] wdatap_free_id_dataid;
wire [CFG_DATAID_ARRAY_DEPTH-1:0] wdatap_free_id_dataid_vector;
// command generator & TBP command load interface / cmd update interface
wire proc_busy;
wire proc_load;
wire proc_load_dataid;
wire proc_write;
wire [CFG_TBP_NUM-1:0] tbp_load_index;
wire [CFG_INT_SIZE_WIDTH-1:0] proc_size;
// input interface data channel / buffer write interface
wire wr_data_mem_full;
wire write_data_en;
wire [CFG_LOCAL_DATA_WIDTH-1:0] write_data;
wire [CFG_LOCAL_BE_WIDTH-1:0] byte_en;
// notify TBP interface
wire [CFG_TBP_NUM-1:0] data_complete;
wire data_rmw_complete;
wire data_partial_be;
// AFI interface / buffer read interface
wire [CFG_DRAM_WLAT_GROUP-1:0] doing_write;
wire [CFG_DRAM_WLAT_GROUP*CFG_DATA_ID_WIDTH-1:0] dataid;
wire [CFG_DRAM_WLAT_GROUP-1:0] rdwr_data_valid;
wire [CFG_DRAM_WLAT_GROUP-1:0] rmw_correct;
wire [CFG_DRAM_WLAT_GROUP-1:0] rmw_partial;
wire [CFG_LOCAL_DATA_WIDTH-1:0] wdatap_data;
wire [CFG_LOCAL_DATA_WIDTH-1:0] wdatap_rmw_partial_data;
wire [CFG_LOCAL_DATA_WIDTH-1:0] wdatap_rmw_correct_data;
wire wdatap_rmw_partial;
wire wdatap_rmw_correct;
wire [CFG_LOCAL_DM_WIDTH-1:0] wdatap_dm;
reg [CFG_ECC_MULTIPLES * CFG_ECC_CODE_WIDTH - 1 : 0] wdatap_ecc_code;
reg [CFG_ECC_MULTIPLES - 1 : 0] wdatap_ecc_code_overwrite;
// RMW fifo interface
wire rmwfifo_data_valid;
wire [CFG_LOCAL_DATA_WIDTH-1:0] rmwfifo_data;
wire [CFG_ECC_MULTIPLES- 1 : 0] rmwfifo_ecc_dbe;
wire [CFG_ECC_MULTIPLES * CFG_ECC_CODE_WIDTH - 1 : 0] rmwfifo_ecc_code;
// -----------------------------
// signal declaration
// -----------------------------
// configuration
reg [CFG_MMR_DRAM_DATA_WIDTH - 1 : 0] cfg_dram_data_width;
reg [CFG_MMR_DRAM_DM_WIDTH - 1 : 0] cfg_dram_dm_width;
// command generator & TBP command load interface / cmd update interface
wire wdatap_cmdload_ready;
wire wdatap_cmdload_valid;
wire [CFG_DATA_ID_WIDTH-1:0] wdatap_cmdload_dataid;
wire [CFG_TBP_NUM-1:0] wdatap_cmdload_tbp_index;
wire [CFG_INT_SIZE_WIDTH-1:0] wdatap_cmdload_burstcount;
// input interface data channel / buffer write interface
wire wdatap_datawrite_ready;
wire wdatap_datawrite_valid;
wire wdatap_datawrite_accepted;
wire [CFG_LOCAL_DATA_WIDTH-1:0] wdatap_datawrite_data;
wire [CFG_LOCAL_BE_WIDTH-1:0] wdatap_datawrite_be;
reg [CFG_LOCAL_DM_WIDTH-1:0] wdatap_datawrite_dm;
reg [CFG_LOCAL_DM_WIDTH-1:0] int_datawrite_dm;
wire wdatap_datawrite_partial_dm;
wire [CFG_BUFFER_ADDR_WIDTH-1:0] wdatap_datawrite_address;
reg [CFG_ECC_MULTIPLES-1:0] int_datawrite_partial_dm;
// notify TBP interface
wire [CFG_TBP_NUM-1:0] wdatap_tbp_data_ready;
wire wdatap_tbp_data_partial_be;
// AFI interface data channel / buffer read interface
wire [CFG_DRAM_WLAT_GROUP-1:0] wdatap_dataread_valid;
wire [CFG_DRAM_WLAT_GROUP*CFG_DATA_ID_WIDTH-1:0] wdatap_dataread_dataid;
wire [CFG_DRAM_WLAT_GROUP*CFG_DATAID_ARRAY_DEPTH-1:0] wdatap_dataread_dataid_vector;
reg [CFG_DRAM_WLAT_GROUP*CFG_DATA_ID_WIDTH-1:0] wdatap_dataread_dataid_r;
wire wdatap_dataread_valid_first;
wire [CFG_DATA_ID_WIDTH-1:0] wdatap_dataread_dataid_first;
wire [CFG_DATAID_ARRAY_DEPTH-1:0] wdatap_dataread_dataid_vector_first;
wire [CFG_DRAM_WLAT_GROUP-1:0] wdatap_dataread_valid_first_vector;
wire wdatap_dataread_valid_last;
wire [CFG_DATA_ID_WIDTH-1:0] wdatap_dataread_dataid_last;
wire [CFG_DATAID_ARRAY_DEPTH-1:0] wdatap_dataread_dataid_vector_last;
wire [CFG_DRAM_WLAT_GROUP-1:0] wdatap_dataread_datavalid;
reg [CFG_LOCAL_DATA_WIDTH-1:0] wdatap_dataread_data;
reg [CFG_LOCAL_DATA_WIDTH-1:0] wdatap_dataread_rmw_partial_data;
reg [CFG_LOCAL_DATA_WIDTH-1:0] wdatap_dataread_rmw_correct_data;
reg wdatap_dataread_rmw_partial;
reg wdatap_dataread_rmw_correct;
reg [CFG_LOCAL_DM_WIDTH-1:0] wdatap_dataread_dm;
wire [CFG_DRAM_WLAT_GROUP*CFG_BUFFER_ADDR_WIDTH-1:0] wdatap_dataread_address;
wire wdatap_dataread_done;
wire wdatap_dataread_ready;
wire [CFG_LOCAL_DATA_WIDTH-1:0] wdatap_dataread_buffer_data;
wire [CFG_LOCAL_DM_WIDTH-1:0] wdatap_dataread_buffer_dm;
wire wdatap_free_id_get_ready;
wire wdatap_allocated_put_ready;
wire wdatap_allocated_put_valid;
wire wdatap_update_data_dataid_valid;
wire [CFG_DATA_ID_WIDTH-1:0] wdatap_update_data_dataid;
wire [CFG_DATAID_ARRAY_DEPTH-1:0] wdatap_update_data_dataid_vector;
wire [CFG_BURSTCOUNT_TRACKING_WIDTH-1:0] wdatap_update_data_burstcount;
wire [CFG_BURSTCOUNT_TRACKING_WIDTH-1:0] wdatap_update_data_next_burstcount;
wire wdatap_notify_data_valid;
wire [CFG_INT_SIZE_WIDTH-1:0] wdatap_notify_data_burstcount_consumed;
// buffer read/write signals
wire wdatap_buffwrite_valid;
wire [CFG_BUFFER_ADDR_WIDTH-1:0] wdatap_buffwrite_address;
wire wdatap_buffread_valid;
wire [CFG_BUFFER_ADDR_WIDTH-1:0] wdatap_buffread_address;
wire [CFG_RMWDATA_FIFO_DATA_WIDTH-1:0] rmwfifo_input;
wire [CFG_RMWDATA_FIFO_DATA_WIDTH-1:0] rmwfifo_output;
wire rmwfifo_output_read;
wire rmwfifo_output_valid;
reg rmwfifo_output_valid_r;
wire rmwfifo_output_valid_pulse;
wire [CFG_LOCAL_DATA_WIDTH-1:0] rmwfifo_output_data;
wire [CFG_ECC_MULTIPLES- 1 : 0] rmwfifo_output_ecc_dbe;
wire [CFG_ECC_MULTIPLES * CFG_ECC_CODE_WIDTH - 1 : 0] rmwfifo_output_ecc_code;
reg [CFG_LOCAL_DATA_WIDTH-1:0] rmw_merged_data;
reg rmw_correct_r;
reg rmw_partial_r;
wire rmwfifo_ready;
// debug signals, for assertions
wire err_rmwfifo_overflow;
// -----------------------------
// module definition
// -----------------------------
// renaming port names to more meaningfull internal names
assign wdatap_cmdload_valid = ~proc_busy & proc_load & proc_write & proc_load_dataid;
assign wdatap_cmdload_tbp_index = tbp_load_index;
assign wdatap_cmdload_burstcount = proc_size;
assign wdatap_cmdload_dataid = wdatap_free_id_dataid;
assign wr_data_mem_full = ~wdatap_datawrite_ready;
assign wdatap_datawrite_valid = write_data_en;
assign wdatap_datawrite_data = write_data;
assign wdatap_datawrite_be = byte_en; // we need to replicate
assign data_complete = wdatap_tbp_data_ready;
assign data_rmw_complete = rmwfifo_output_valid_pulse; // broadcast to all TBP's
assign data_partial_be = wdatap_tbp_data_partial_be;
assign wdatap_dataread_valid = doing_write & rdwr_data_valid & ~rmw_correct;
assign wdatap_dataread_dataid = dataid;
assign wdatap_dataread_dataid_vector = dataid_vector;
assign wdatap_dataread_valid_first = doing_write_first & rdwr_data_valid_first & ~rmw_correct_first;
assign wdatap_dataread_dataid_first = dataid_first;
assign wdatap_dataread_dataid_vector_first = dataid_vector_first;
assign wdatap_dataread_valid_first_vector = rdwr_data_valid_first_vector;
assign wdatap_dataread_valid_last = doing_write_last & rdwr_data_valid_last & ~rmw_correct_last ;
assign wdatap_dataread_dataid_last = dataid_last;
assign wdatap_dataread_dataid_vector_last = dataid_vector_last;
assign wdatap_data = wdatap_dataread_data;
assign wdatap_rmw_partial_data = wdatap_dataread_rmw_partial_data;
assign wdatap_rmw_correct_data = wdatap_dataread_rmw_correct_data;
assign wdatap_rmw_partial = wdatap_dataread_rmw_partial;
assign wdatap_rmw_correct = wdatap_dataread_rmw_correct;
assign wdatap_dm = wdatap_dataread_dm;
// internal signals
// flow control between free list & allocated list
assign wdatap_free_id_get_ready = wdatap_cmdload_valid;
assign wdatap_allocated_put_valid= wdatap_free_id_get_ready & wdatap_free_id_valid;
assign wdatap_free_id_valid = wdatap_int_free_id_valid & wdatap_cmdload_ready;
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
cfg_dram_data_width <= 0;
end
else
begin
if (cfg_enable_ecc)
begin
cfg_dram_data_width <= cfg_interface_width - CFG_ECC_CODE_WIDTH; // SPR:362973
end
else
begin
cfg_dram_data_width <= cfg_interface_width;
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
cfg_dram_dm_width <= 0;
end
else
begin
cfg_dram_dm_width <= cfg_dram_data_width / CFG_MEM_IF_DQ_PER_DQS;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
//reset state ...
wdatap_dataread_dataid_r <= 0;
end
else
begin
//active state ...
wdatap_dataread_dataid_r <= wdatap_dataread_dataid;
end
end
alt_mem_ddrx_list
#(
.CTL_LIST_WIDTH (CFG_DATA_ID_WIDTH),
.CTL_LIST_DEPTH (CFG_DATAID_ARRAY_DEPTH),
.CTL_LIST_INIT_VALUE_TYPE ("INCR"),
.CTL_LIST_INIT_VALID ("VALID")
)
wdatap_list_freeid_inst
(
.ctl_clk (ctl_clk),
.ctl_reset_n (ctl_reset_n),
.list_get_entry_ready (wdatap_free_id_get_ready),
.list_get_entry_valid (wdatap_int_free_id_valid),
.list_get_entry_id (wdatap_free_id_dataid),
.list_get_entry_id_vector (wdatap_free_id_dataid_vector),
// wdatap_dataread_ready can be ignored, list entry availability is guaranteed
.list_put_entry_ready (wdatap_dataread_ready),
.list_put_entry_valid (wdatap_dataread_done),
.list_put_entry_id (wdatap_dataread_dataid_r)
);
alt_mem_ddrx_list
#(
.CTL_LIST_WIDTH (CFG_DATA_ID_WIDTH),
.CTL_LIST_DEPTH (CFG_DATAID_ARRAY_DEPTH),
.CTL_LIST_INIT_VALUE_TYPE ("ZERO"),
.CTL_LIST_INIT_VALID ("INVALID")
)
wdatap_list_allocated_id_inst
(
.ctl_clk (ctl_clk),
.ctl_reset_n (ctl_reset_n),
.list_get_entry_ready (wdatap_notify_data_valid),
.list_get_entry_valid (wdatap_update_data_dataid_valid),
.list_get_entry_id (wdatap_update_data_dataid),
.list_get_entry_id_vector (wdatap_update_data_dataid_vector),
// wdatap_allocated_put_ready can be ignored, list entry availability is guaranteed
.list_put_entry_ready (wdatap_allocated_put_ready),
.list_put_entry_valid (wdatap_allocated_put_valid),
.list_put_entry_id (wdatap_free_id_dataid)
);
alt_mem_ddrx_burst_tracking
# (
.CFG_BURSTCOUNT_TRACKING_WIDTH (CFG_BURSTCOUNT_TRACKING_WIDTH),
.CFG_BUFFER_ADDR_WIDTH (CFG_BUFFER_ADDR_WIDTH),
.CFG_INT_SIZE_WIDTH (CFG_INT_SIZE_WIDTH)
)
wdatap_burst_tracking_inst
(
// port list
.ctl_clk (ctl_clk),
.ctl_reset_n (ctl_reset_n),
// data burst interface
.burst_ready (wdatap_datawrite_ready),
.burst_valid (wdatap_datawrite_valid),
// burstcount counter sent to data_id_manager
.burst_pending_burstcount (wdatap_update_data_burstcount),
.burst_next_pending_burstcount (wdatap_update_data_next_burstcount),
// burstcount consumed by data_id_manager
.burst_consumed_valid (wdatap_notify_data_valid),
.burst_counsumed_burstcount (wdatap_notify_data_burstcount_consumed)
);
alt_mem_ddrx_dataid_manager
# (
.CFG_DATA_ID_WIDTH (CFG_DATA_ID_WIDTH),
.CFG_LOCAL_WLAT_GROUP (CFG_LOCAL_WLAT_GROUP),
.CFG_DRAM_WLAT_GROUP (CFG_DRAM_WLAT_GROUP),
.CFG_BUFFER_ADDR_WIDTH (CFG_BUFFER_ADDR_WIDTH),
.CFG_INT_SIZE_WIDTH (CFG_INT_SIZE_WIDTH),
.CFG_TBP_NUM (CFG_TBP_NUM),
.CFG_BURSTCOUNT_TRACKING_WIDTH (CFG_BURSTCOUNT_TRACKING_WIDTH),
.CFG_PORT_WIDTH_BURST_LENGTH (CFG_PORT_WIDTH_BURST_LENGTH),
.CFG_DWIDTH_RATIO (CFG_DWIDTH_RATIO)
)
wdatap_dataid_manager_inst
(
// clock & reset
.ctl_clk (ctl_clk),
.ctl_reset_n (ctl_reset_n),
// configuration signals
.cfg_burst_length (cfg_burst_length),
.cfg_enable_ecc (cfg_enable_ecc),
.cfg_enable_auto_corr (cfg_enable_auto_corr),
.cfg_enable_no_dm (cfg_enable_no_dm),
// update cmd interface
.update_cmd_if_ready (wdatap_cmdload_ready),
.update_cmd_if_valid (wdatap_cmdload_valid),
.update_cmd_if_data_id (wdatap_cmdload_dataid),
.update_cmd_if_burstcount (wdatap_cmdload_burstcount),
.update_cmd_if_tbp_id (wdatap_cmdload_tbp_index),
// update data interface
.update_data_if_valid (wdatap_update_data_dataid_valid),
.update_data_if_data_id (wdatap_update_data_dataid),
.update_data_if_data_id_vector (wdatap_update_data_dataid_vector),
.update_data_if_burstcount (wdatap_update_data_burstcount),
.update_data_if_next_burstcount (wdatap_update_data_next_burstcount),
// notify data interface
.notify_data_if_valid (wdatap_notify_data_valid),
.notify_data_if_burstcount (wdatap_notify_data_burstcount_consumed),
// notify tbp interface
.notify_tbp_data_ready (wdatap_tbp_data_ready),
.notify_tbp_data_partial_be (wdatap_tbp_data_partial_be),
// buffer write address generate interface
.write_data_if_ready (wdatap_datawrite_ready),
.write_data_if_valid (wdatap_datawrite_valid),
.write_data_if_accepted (wdatap_datawrite_accepted),
.write_data_if_address (wdatap_datawrite_address),
.write_data_if_partial_dm (wdatap_datawrite_partial_dm),
// read data interface
.read_data_if_valid (wdatap_dataread_valid),
.read_data_if_data_id (wdatap_dataread_dataid),
.read_data_if_data_id_vector (wdatap_dataread_dataid_vector),
.read_data_if_valid_first (wdatap_dataread_valid_first),
.read_data_if_data_id_first (wdatap_dataread_dataid_first),
.read_data_if_data_id_vector_first (wdatap_dataread_dataid_vector_first),
.read_data_if_valid_first_vector (wdatap_dataread_valid_first_vector),
.read_data_if_valid_last (wdatap_dataread_valid_last),
.read_data_if_data_id_last (wdatap_dataread_dataid_last),
.read_data_if_data_id_vector_last (wdatap_dataread_dataid_vector_last),
.read_data_if_address (wdatap_dataread_address),
.read_data_if_datavalid (wdatap_dataread_datavalid),
.read_data_if_done (wdatap_dataread_done) // use with wdatap_dataread_dataid_r
);
genvar wdatap_m;
genvar wdatap_n;
generate
for (wdatap_m = 0;wdatap_m < CFG_DWIDTH_RATIO;wdatap_m = wdatap_m + 1)
begin : wdata_buffer_per_dwidth_ratio
for (wdatap_n = 0;wdatap_n < CFG_LOCAL_WLAT_GROUP;wdatap_n = wdatap_n + 1)
begin : wdata_buffer_per_dqs_group
alt_mem_ddrx_buffer
# (
.ADDR_WIDTH (CFG_BUFFER_ADDR_WIDTH),
.DATA_WIDTH (CFG_WR_DATA_WIDTH_PER_DQS_GROUP)
)
wdatap_buffer_data_inst
(
// port list
.ctl_clk (ctl_clk),
.ctl_reset_n (ctl_reset_n),
// write interface
.write_valid (wdatap_datawrite_accepted),
.write_address (wdatap_datawrite_address),
.write_data (wdatap_datawrite_data [(wdatap_m * CFG_WR_DATA_WIDTH_PER_DQS_GROUP * CFG_LOCAL_WLAT_GROUP) + ((wdatap_n + 1) * CFG_WR_DATA_WIDTH_PER_DQS_GROUP) - 1 : (wdatap_m * CFG_WR_DATA_WIDTH_PER_DQS_GROUP * CFG_LOCAL_WLAT_GROUP) + (wdatap_n * CFG_WR_DATA_WIDTH_PER_DQS_GROUP)]),
// read interface
.read_valid (wdatap_dataread_valid [wdatap_n]),
.read_address (wdatap_dataread_address [(wdatap_n + 1) * CFG_BUFFER_ADDR_WIDTH - 1 : wdatap_n * CFG_BUFFER_ADDR_WIDTH]),
.read_data (wdatap_dataread_buffer_data [(wdatap_m * CFG_WR_DATA_WIDTH_PER_DQS_GROUP * CFG_LOCAL_WLAT_GROUP) + ((wdatap_n + 1) * CFG_WR_DATA_WIDTH_PER_DQS_GROUP) - 1 : (wdatap_m * CFG_WR_DATA_WIDTH_PER_DQS_GROUP * CFG_LOCAL_WLAT_GROUP) + (wdatap_n * CFG_WR_DATA_WIDTH_PER_DQS_GROUP)])
);
alt_mem_ddrx_buffer
# (
.ADDR_WIDTH (CFG_BUFFER_ADDR_WIDTH),
.DATA_WIDTH (CFG_WR_DM_WIDTH_PER_DQS_GROUP)
)
wdatap_buffer_be_inst
(
// port list
.ctl_clk (ctl_clk),
.ctl_reset_n (ctl_reset_n),
// write interface
.write_valid (wdatap_datawrite_accepted),
.write_address (wdatap_datawrite_address),
.write_data (int_datawrite_dm [(wdatap_m * CFG_WR_DM_WIDTH_PER_DQS_GROUP * CFG_LOCAL_WLAT_GROUP) + ((wdatap_n + 1) * CFG_WR_DM_WIDTH_PER_DQS_GROUP) - 1 : (wdatap_m * CFG_WR_DM_WIDTH_PER_DQS_GROUP * CFG_LOCAL_WLAT_GROUP) + (wdatap_n * CFG_WR_DM_WIDTH_PER_DQS_GROUP)]),
// read interface
.read_valid (wdatap_dataread_valid [wdatap_n]),
.read_address (wdatap_dataread_address [(wdatap_n + 1) * CFG_BUFFER_ADDR_WIDTH - 1 : wdatap_n * CFG_BUFFER_ADDR_WIDTH]),
.read_data (wdatap_dataread_buffer_dm [(wdatap_m * CFG_WR_DM_WIDTH_PER_DQS_GROUP * CFG_LOCAL_WLAT_GROUP) + ((wdatap_n + 1) * CFG_WR_DM_WIDTH_PER_DQS_GROUP) - 1 : (wdatap_m * CFG_WR_DM_WIDTH_PER_DQS_GROUP * CFG_LOCAL_WLAT_GROUP) + (wdatap_n * CFG_WR_DM_WIDTH_PER_DQS_GROUP)])
);
end
end
endgenerate
//
// byteenables analysis & generation
//
// - generate partial byteenable signal, per DQ word or per local word
// - set unused interface width byteenables to either 0 or 1
//
genvar wdatap_j, wdatap_k;
generate
reg [(CFG_LOCAL_DM_WIDTH/CFG_ECC_MULTIPLES)-1:0] wdatap_datawrite_dm_widthratio [CFG_ECC_MULTIPLES-1:0];
reg [(CFG_LOCAL_DM_WIDTH/CFG_ECC_MULTIPLES)-1:0] int_datawrite_dm_unused1 [CFG_ECC_MULTIPLES-1:0];
reg [(CFG_LOCAL_DM_WIDTH/CFG_ECC_MULTIPLES)-1:0] int_datawrite_dm_unused0 [CFG_ECC_MULTIPLES-1:0];
assign wdatap_datawrite_partial_dm = |int_datawrite_partial_dm;
for (wdatap_k = 0;wdatap_k < CFG_LOCAL_DM_WIDTH;wdatap_k = wdatap_k + 1)
begin : local_dm
always @ (*)
begin
if (CFG_MEM_IF_DQ_PER_DQS == 4)
begin
wdatap_datawrite_dm [wdatap_k] = wdatap_datawrite_be [wdatap_k / 2];
end
else
begin
wdatap_datawrite_dm [wdatap_k] = wdatap_datawrite_be [wdatap_k];
end
end
end
for (wdatap_j = 0; wdatap_j < CFG_ECC_MULTIPLES; wdatap_j = wdatap_j + 1)
begin : gen_partial_be
wire dm_all_ones = &int_datawrite_dm_unused1[wdatap_j];
wire dm_all_zeros = ~(|int_datawrite_dm_unused0[wdatap_j]);
always @ (*)
begin
wdatap_datawrite_dm_widthratio [wdatap_j] = wdatap_datawrite_dm [(wdatap_j+1)*(CFG_LOCAL_DM_WIDTH/CFG_ECC_MULTIPLES)-1 : (wdatap_j*(CFG_LOCAL_DM_WIDTH/CFG_ECC_MULTIPLES))];
end
for (wdatap_k = 0; wdatap_k < (CFG_LOCAL_DM_WIDTH/CFG_ECC_MULTIPLES); wdatap_k = wdatap_k + 1'b1)
begin : gen_dm_unused_bits
always @ (*)
begin
if (wdatap_k < cfg_dram_dm_width)
begin
int_datawrite_dm_unused1 [wdatap_j] [wdatap_k] = wdatap_datawrite_dm_widthratio [wdatap_j][wdatap_k];
int_datawrite_dm_unused0 [wdatap_j] [wdatap_k] = wdatap_datawrite_dm_widthratio [wdatap_j][wdatap_k];
end
else
begin
int_datawrite_dm_unused1 [wdatap_j] [wdatap_k] = {1'b1};
int_datawrite_dm_unused0 [wdatap_j] [wdatap_k] = {1'b0};
end
end
end
always @ (*)
begin
// partial be calculated for every dq width if byteenables, not partial be if either all ones, or all zeros
if (cfg_enable_no_dm)
begin
int_datawrite_partial_dm[wdatap_j] = ~dm_all_ones;
end
else
begin
int_datawrite_partial_dm[wdatap_j] = ~( dm_all_ones | dm_all_zeros );
end
if (cfg_enable_ecc)
begin
if (dm_all_zeros)
begin
// no ECC code will be written
int_datawrite_dm [(wdatap_j+1)*(CFG_LOCAL_DM_WIDTH/CFG_ECC_MULTIPLES)-1 : (wdatap_j*(CFG_LOCAL_DM_WIDTH/CFG_ECC_MULTIPLES))] = int_datawrite_dm_unused0 [wdatap_j];
end
else
begin
// higher unused be bit will be used for ECC word
int_datawrite_dm [(wdatap_j+1)*(CFG_LOCAL_DM_WIDTH/CFG_ECC_MULTIPLES)-1 : (wdatap_j*(CFG_LOCAL_DM_WIDTH/CFG_ECC_MULTIPLES))] = int_datawrite_dm_unused1 [wdatap_j];
end
end
else
begin
int_datawrite_dm [(wdatap_j+1)*(CFG_LOCAL_DM_WIDTH/CFG_ECC_MULTIPLES)-1 : (wdatap_j*(CFG_LOCAL_DM_WIDTH/CFG_ECC_MULTIPLES))] = int_datawrite_dm_unused0 [wdatap_j];
end
end
end
endgenerate
//
// rmw data fifo
//
// assume rmw data for 2 commands doesn't came back to back, causing rmwfifo_output_valid_pulse not to be generated for 2nd commands data
assign rmwfifo_output_valid_pulse = rmwfifo_output_valid & ~rmwfifo_output_valid_r;
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
rmwfifo_output_valid_r <= 1'b0;
rmw_correct_r <= 1'b0;
rmw_partial_r <= 1'b0;
end
else
begin
rmwfifo_output_valid_r <= rmwfifo_output_valid;
rmw_correct_r <= rmw_correct;
rmw_partial_r <= rmw_partial;
end
end
assign rmwfifo_input = {rmwfifo_ecc_code, rmwfifo_ecc_dbe, rmwfifo_data};
assign {rmwfifo_output_ecc_code, rmwfifo_output_ecc_dbe, rmwfifo_output_data} = rmwfifo_output;
assign rmwfifo_output_read = rmw_correct_r | (&wdatap_dataread_datavalid & rmw_partial_r); // wdatap_dataread_datavalid must be all high together in ECC case (afi_wlat same for all DQS group), limitation in 11.0sp1
assign err_rmwfifo_overflow = rmwfifo_data_valid & ~rmwfifo_ready;
alt_mem_ddrx_fifo
#(
.CTL_FIFO_DATA_WIDTH (CFG_RMWDATA_FIFO_DATA_WIDTH),
.CTL_FIFO_ADDR_WIDTH (CFG_RMWDATA_FIFO_ADDR_WIDTH)
)
rmw_data_fifo_inst
(
.ctl_clk (ctl_clk),
.ctl_reset_n (ctl_reset_n),
.get_ready (rmwfifo_output_read),
.get_valid (rmwfifo_output_valid),
.get_data (rmwfifo_output),
.put_ready (rmwfifo_ready),
.put_valid (rmwfifo_data_valid),
.put_data (rmwfifo_input)
);
//
// rmw data merge block
//
genvar wdatap_i;
generate
for (wdatap_i = 0; wdatap_i < ((CFG_LOCAL_DM_WIDTH)); wdatap_i = wdatap_i + 1)
begin : gen_rmw_data_merge
always @ (*)
begin
if (wdatap_dataread_buffer_dm[wdatap_i])
begin
// data from wdatap buffer
rmw_merged_data [ ((wdatap_i + 1) * CFG_MEM_IF_DQ_PER_DQS) - 1 : (wdatap_i * CFG_MEM_IF_DQ_PER_DQS) ] = wdatap_dataread_buffer_data [ ((wdatap_i + 1) * CFG_MEM_IF_DQ_PER_DQS) - 1 : (wdatap_i * CFG_MEM_IF_DQ_PER_DQS) ];
end
else
begin
// data from rmwfifo
rmw_merged_data [ ((wdatap_i + 1) * CFG_MEM_IF_DQ_PER_DQS) - 1 : (wdatap_i * CFG_MEM_IF_DQ_PER_DQS) ] = rmwfifo_output_data [ ((wdatap_i + 1) * CFG_MEM_IF_DQ_PER_DQS) - 1 : (wdatap_i * CFG_MEM_IF_DQ_PER_DQS) ];
end
end
end
endgenerate
//
// wdata output mux
//
// drives wdatap_data & wdatap_be from either of
// if cfg_enabled etc ?
// - wdatap buffer (~rmw_correct & ~rmw_partial)
// - rmwfifo (rmw_correct)
// - merged wdatap buffer & rmwfifo (rmw_partial)
//
generate
if (CFG_WDATA_REG)
begin
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
wdatap_dataread_dm <= 0;
wdatap_dataread_data <= 0;
wdatap_dataread_rmw_partial_data <= 0;
wdatap_dataread_rmw_correct_data <= 0;
wdatap_dataread_rmw_partial <= 0;
wdatap_dataread_rmw_correct <= 0;
end
else
begin
if (cfg_enable_ecc | cfg_enable_no_dm)
begin
wdatap_dataread_data <= wdatap_dataread_buffer_data;
wdatap_dataread_rmw_partial_data <= rmw_merged_data;
wdatap_dataread_rmw_correct_data <= rmwfifo_output_data;
wdatap_dataread_rmw_partial <= rmw_partial_r;
wdatap_dataread_rmw_correct <= rmw_correct_r;
if (rmw_correct_r | rmw_partial_r)
begin
wdatap_dataread_dm <= {(CFG_LOCAL_DM_WIDTH){1'b1}};
end
else
begin
wdatap_dataread_dm <= wdatap_dataread_buffer_dm;
end
end
else
begin
wdatap_dataread_dm <= wdatap_dataread_buffer_dm;
wdatap_dataread_data <= wdatap_dataread_buffer_data;
wdatap_dataread_rmw_partial_data <= 0;
wdatap_dataread_rmw_correct_data <= 0;
wdatap_dataread_rmw_partial <= 1'b0;
wdatap_dataread_rmw_correct <= 1'b0;
end
end
end
// ecc code overwrite
// - is asserted when we don't want controller to re-calculate the ecc code
// - only allowed when we're not doing any writes in this clock
// - only allowed when rmwfifo output is valid
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
wdatap_ecc_code <= 0;
wdatap_ecc_code_overwrite <= 0;
end
else
begin
wdatap_ecc_code <= rmwfifo_output_ecc_code;
if (cfg_enable_ecc_code_overwrites)
begin
if (rmw_correct_r)
begin
wdatap_ecc_code_overwrite <= rmwfifo_output_ecc_dbe;
end
else if (rmw_partial_r)
begin
if ( (|wdatap_dataread_buffer_dm) | (~rmwfifo_output_valid) )
begin
wdatap_ecc_code_overwrite <= {CFG_ECC_MULTIPLES{1'b0}};
end
else
begin
wdatap_ecc_code_overwrite <= rmwfifo_output_ecc_dbe;
end
end
else
begin
wdatap_ecc_code_overwrite <= {CFG_ECC_MULTIPLES{1'b0}};
end
end
else
begin
wdatap_ecc_code_overwrite <= {CFG_ECC_MULTIPLES{1'b0}};
end
end
end
end
else
begin
always @ (*)
begin
if (cfg_enable_ecc | cfg_enable_no_dm)
begin
wdatap_dataread_data = wdatap_dataread_buffer_data;
wdatap_dataread_rmw_partial_data = rmw_merged_data;
wdatap_dataread_rmw_correct_data = rmwfifo_output_data;
wdatap_dataread_rmw_partial = rmw_partial_r;
wdatap_dataread_rmw_correct = rmw_correct_r;
if (rmw_correct_r | rmw_partial_r)
begin
wdatap_dataread_dm = {(CFG_LOCAL_DM_WIDTH){1'b1}};
end
else
begin
wdatap_dataread_dm = wdatap_dataread_buffer_dm;
end
end
else
begin
wdatap_dataread_dm = wdatap_dataread_buffer_dm;
wdatap_dataread_data = wdatap_dataread_buffer_data;
wdatap_dataread_rmw_partial_data = 0;
wdatap_dataread_rmw_correct_data = 0;
wdatap_dataread_rmw_partial = 1'b0;
wdatap_dataread_rmw_correct = 1'b0;
end
end
// ecc code overwrite
// - is asserted when we don't want controller to re-calculate the ecc code
// - only allowed when we're not doing any writes in this clock
// - only allowed when rmwfifo output is valid
always @ (*)
begin
wdatap_ecc_code = rmwfifo_output_ecc_code;
if (cfg_enable_ecc_code_overwrites)
begin
if (rmw_correct_r)
begin
wdatap_ecc_code_overwrite = rmwfifo_output_ecc_dbe;
end
else if (rmw_partial_r)
begin
if ( (|wdatap_dataread_buffer_dm) | (~rmwfifo_output_valid) )
begin
wdatap_ecc_code_overwrite = {CFG_ECC_MULTIPLES{1'b0}};
end
else
begin
wdatap_ecc_code_overwrite = rmwfifo_output_ecc_dbe;
end
end
else
begin
wdatap_ecc_code_overwrite = {CFG_ECC_MULTIPLES{1'b0}};
end
end
else
begin
wdatap_ecc_code_overwrite = {CFG_ECC_MULTIPLES{1'b0}};
end
end
end
endgenerate
endmodule
|
//altpll_avalon avalon_use_separate_sysclk="NO" CBX_SINGLE_OUTPUT_FILE="ON" CBX_SUBMODULE_USED_PORTS="altpll:areset,clk,locked,inclk" address areset c0 c1 c2 c3 clk locked phasedone read readdata reset write writedata bandwidth_type="AUTO" clk0_divide_by=3 clk0_duty_cycle=50 clk0_multiply_by=2 clk0_phase_shift="0" clk1_divide_by=3 clk1_duty_cycle=50 clk1_multiply_by=2 clk1_phase_shift="0" clk2_divide_by=3 clk2_duty_cycle=50 clk2_multiply_by=2 clk2_phase_shift="0" clk3_divide_by=1 clk3_duty_cycle=50 clk3_multiply_by=2 clk3_phase_shift="1000" compensate_clock="CLK0" device_family="STRATIXIV" inclk0_input_frequency=20000 intended_device_family="Stratix IV" operation_mode="normal" pll_type="AUTO" port_clk0="PORT_USED" port_clk1="PORT_USED" port_clk2="PORT_UNUSED" port_clk3="PORT_UNUSED" port_clk4="PORT_UNUSED" port_clk5="PORT_UNUSED" port_clk6="PORT_UNUSED" port_clk7="PORT_UNUSED" port_clk8="PORT_UNUSED" port_clk9="PORT_UNUSED" port_inclk1="PORT_UNUSED" port_phasecounterselect="PORT_UNUSED" port_phasedone="PORT_UNUSED" port_scandata="PORT_UNUSED" port_scandataout="PORT_UNUSED" using_fbmimicbidir_port="OFF" width_clock=10
//VERSION_BEGIN 11.1 cbx_altclkbuf 2011:10:31:21:09:45:SJ cbx_altiobuf_bidir 2011:10:31:21:09:45:SJ cbx_altiobuf_in 2011:10:31:21:09:45:SJ cbx_altiobuf_out 2011:10:31:21:09:45:SJ cbx_altpll 2011:10:31:21:09:45:SJ cbx_altpll_avalon 2011:10:31:21:09:45:SJ cbx_cycloneii 2011:10:31:21:09:45:SJ cbx_lpm_add_sub 2011:10:31:21:09:45:SJ cbx_lpm_compare 2011:10:31:21:09:45:SJ cbx_lpm_decode 2011:10:31:21:09:45:SJ cbx_lpm_mux 2011:10:31:21:09:45:SJ cbx_lpm_shiftreg 2011:10:31:21:09:45:SJ cbx_mgl 2011:10:31:21:20:20:SJ cbx_stratix 2011:10:31:21:09:45:SJ cbx_stratixii 2011:10:31:21:09:45:SJ cbx_stratixiii 2011:10:31:21:09:45:SJ cbx_stratixv 2011:10:31:21:09:45:SJ cbx_util_mgl 2011:10:31:21:09:45:SJ VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
// Copyright (C) 1991-2011 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, Altera MegaCore Function License
// Agreement, or other applicable license agreement, including,
// without limitation, that your use is for the sole purpose of
// programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the
// applicable agreement for further details.
//altera_std_synchronizer CBX_SINGLE_OUTPUT_FILE="ON" clk din dout reset_n
//VERSION_BEGIN 11.1 cbx_mgl 2011:10:31:21:20:20:SJ cbx_stratixii 2011:10:31:21:09:45:SJ cbx_util_mgl 2011:10:31:21:09:45:SJ VERSION_END
//dffpipe CBX_SINGLE_OUTPUT_FILE="ON" DELAY=3 WIDTH=1 clock clrn d q ALTERA_INTERNAL_OPTIONS=AUTO_SHIFT_REGISTER_RECOGNITION=OFF
//VERSION_BEGIN 11.1 cbx_mgl 2011:10:31:21:20:20:SJ cbx_stratixii 2011:10:31:21:09:45:SJ cbx_util_mgl 2011:10:31:21:09:45:SJ VERSION_END
//synthesis_resources = reg 3
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
(* ALTERA_ATTRIBUTE = {"AUTO_SHIFT_REGISTER_RECOGNITION=OFF"} *)
module DE4_SOPC_altpll_0_dffpipe_l2c
(
clock,
clrn,
d,
q) /* synthesis synthesis_clearbox=1 */;
input clock;
input clrn;
input [0:0] d;
output [0:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 clock;
tri1 clrn;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
reg [0:0] dffe4a;
reg [0:0] dffe5a;
reg [0:0] dffe6a;
wire ena;
wire prn;
wire sclr;
// synopsys translate_off
initial
dffe4a = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe4a <= {1{1'b1}};
else if (clrn == 1'b0) dffe4a <= 1'b0;
else if (ena == 1'b1) dffe4a <= (d & (~ sclr));
// synopsys translate_off
initial
dffe5a = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe5a <= {1{1'b1}};
else if (clrn == 1'b0) dffe5a <= 1'b0;
else if (ena == 1'b1) dffe5a <= (dffe4a & (~ sclr));
// synopsys translate_off
initial
dffe6a = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe6a <= {1{1'b1}};
else if (clrn == 1'b0) dffe6a <= 1'b0;
else if (ena == 1'b1) dffe6a <= (dffe5a & (~ sclr));
assign
ena = 1'b1,
prn = 1'b1,
q = dffe6a,
sclr = 1'b0;
endmodule //DE4_SOPC_altpll_0_dffpipe_l2c
//synthesis_resources = reg 3
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module DE4_SOPC_altpll_0_stdsync_sv6
(
clk,
din,
dout,
reset_n) /* synthesis synthesis_clearbox=1 */;
input clk;
input din;
output dout;
input reset_n;
wire [0:0] wire_dffpipe3_q;
DE4_SOPC_altpll_0_dffpipe_l2c dffpipe3
(
.clock(clk),
.clrn(reset_n),
.d(din),
.q(wire_dffpipe3_q));
assign
dout = wire_dffpipe3_q;
endmodule //DE4_SOPC_altpll_0_stdsync_sv6
//altpll bandwidth_type="AUTO" CBX_SINGLE_OUTPUT_FILE="ON" clk0_divide_by=3 clk0_duty_cycle=50 clk0_multiply_by=2 clk0_phase_shift="0" clk1_divide_by=3 clk1_duty_cycle=50 clk1_multiply_by=2 clk1_phase_shift="0" clk2_divide_by=3 clk2_duty_cycle=50 clk2_multiply_by=2 clk2_phase_shift="0" clk3_divide_by=1 clk3_duty_cycle=50 clk3_multiply_by=2 clk3_phase_shift="1000" compensate_clock="CLK0" device_family="STRATIXIV" inclk0_input_frequency=20000 intended_device_family="Stratix IV" operation_mode="normal" pll_type="AUTO" port_clk0="PORT_USED" port_clk1="PORT_USED" port_clk2="PORT_UNUSED" port_clk3="PORT_UNUSED" port_clk4="PORT_UNUSED" port_clk5="PORT_UNUSED" port_clk6="PORT_UNUSED" port_clk7="PORT_UNUSED" port_clk8="PORT_UNUSED" port_clk9="PORT_UNUSED" port_inclk1="PORT_UNUSED" port_phasecounterselect="PORT_UNUSED" port_phasedone="PORT_UNUSED" port_scandata="PORT_UNUSED" port_scandataout="PORT_UNUSED" using_fbmimicbidir_port="OFF" width_clock=10 areset clk inclk locked
//VERSION_BEGIN 11.1 cbx_altclkbuf 2011:10:31:21:09:45:SJ cbx_altiobuf_bidir 2011:10:31:21:09:45:SJ cbx_altiobuf_in 2011:10:31:21:09:45:SJ cbx_altiobuf_out 2011:10:31:21:09:45:SJ cbx_altpll 2011:10:31:21:09:45:SJ cbx_cycloneii 2011:10:31:21:09:45:SJ cbx_lpm_add_sub 2011:10:31:21:09:45:SJ cbx_lpm_compare 2011:10:31:21:09:45:SJ cbx_lpm_decode 2011:10:31:21:09:45:SJ cbx_lpm_mux 2011:10:31:21:09:45:SJ cbx_mgl 2011:10:31:21:20:20:SJ cbx_stratix 2011:10:31:21:09:45:SJ cbx_stratixii 2011:10:31:21:09:45:SJ cbx_stratixiii 2011:10:31:21:09:45:SJ cbx_stratixv 2011:10:31:21:09:45:SJ cbx_util_mgl 2011:10:31:21:09:45:SJ VERSION_END
//synthesis_resources = reg 1 stratixiv_pll 1
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
(* ALTERA_ATTRIBUTE = {"SUPPRESS_DA_RULE_INTERNAL=C104"} *)
module DE4_SOPC_altpll_0_altpll_2op2
(
areset,
clk,
inclk,
locked) /* synthesis synthesis_clearbox=1 */;
input areset;
output [9:0] clk;
input [1:0] inclk;
output locked;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 areset;
tri0 [1:0] inclk;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
reg pll_lock_sync;
wire [9:0] wire_pll7_clk;
wire wire_pll7_fbout;
wire wire_pll7_locked;
// synopsys translate_off
initial
pll_lock_sync = 0;
// synopsys translate_on
always @ ( posedge wire_pll7_locked or posedge areset)
if (areset == 1'b1) pll_lock_sync <= 1'b0;
else pll_lock_sync <= 1'b1;
stratixiv_pll pll7
(
.activeclock(),
.areset(areset),
.clk(wire_pll7_clk),
.clkbad(),
.fbin(wire_pll7_fbout),
.fbout(wire_pll7_fbout),
.inclk(inclk),
.locked(wire_pll7_locked),
.phasedone(),
.scandataout(),
.scandone(),
.vcooverrange(),
.vcounderrange()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.clkswitch(1'b0),
.configupdate(1'b0),
.pfdena(1'b1),
.phasecounterselect({4{1'b0}}),
.phasestep(1'b0),
.phaseupdown(1'b0),
.scanclk(1'b0),
.scanclkena(1'b1),
.scandata(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
pll7.bandwidth_type = "auto",
pll7.clk0_divide_by = 3,
pll7.clk0_duty_cycle = 50,
pll7.clk0_multiply_by = 2,
pll7.clk0_phase_shift = "0",
pll7.clk1_divide_by = 3,
pll7.clk1_duty_cycle = 50,
pll7.clk1_multiply_by = 2,
pll7.clk1_phase_shift = "0",
pll7.clk2_divide_by = 3,
pll7.clk2_duty_cycle = 50,
pll7.clk2_multiply_by = 2,
pll7.clk2_phase_shift = "0",
pll7.clk3_divide_by = 1,
pll7.clk3_duty_cycle = 50,
pll7.clk3_multiply_by = 2,
pll7.clk3_phase_shift = "1000",
pll7.compensate_clock = "clk0",
pll7.inclk0_input_frequency = 20000,
pll7.operation_mode = "normal",
pll7.pll_type = "auto",
pll7.lpm_type = "stratixiv_pll";
assign
clk = wire_pll7_clk,
locked = (wire_pll7_locked & pll_lock_sync);
endmodule //DE4_SOPC_altpll_0_altpll_2op2
//synthesis_resources = reg 6 stratixiv_pll 1
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module DE4_SOPC_altpll_0
(
address,
areset,
c0,
c1,
c2,
c3,
clk,
locked,
phasedone,
read,
readdata,
reset,
write,
writedata) /* synthesis synthesis_clearbox=1 */;
input [1:0] address;
input areset;
output c0;
output c1;
output c2;
output c3;
input clk;
output locked;
output phasedone;
input read;
output [31:0] readdata;
input reset;
input write;
input [31:0] writedata;
wire wire_stdsync2_dout;
wire [9:0] wire_sd1_clk;
wire wire_sd1_locked;
(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=HIGH"} *)
reg pfdena_reg;
wire wire_pfdena_reg_ena;
reg prev_reset;
wire w_locked;
wire w_pfdena;
wire w_phasedone;
wire w_pll_areset_in;
wire w_reset;
wire w_select_control;
wire w_select_status;
DE4_SOPC_altpll_0_stdsync_sv6 stdsync2
(
.clk(clk),
.din(wire_sd1_locked),
.dout(wire_stdsync2_dout),
.reset_n((~ reset)));
DE4_SOPC_altpll_0_altpll_2op2 sd1
(
.areset((w_pll_areset_in | areset)),
.clk(wire_sd1_clk),
.inclk({{1{1'b0}}, clk}),
.locked(wire_sd1_locked));
// synopsys translate_off
initial
pfdena_reg = {1{1'b1}};
// synopsys translate_on
always @ ( posedge clk or posedge reset)
if (reset == 1'b1) pfdena_reg <= {1{1'b1}};
else if (wire_pfdena_reg_ena == 1'b1) pfdena_reg <= writedata[1];
assign
wire_pfdena_reg_ena = (write & w_select_control);
// synopsys translate_off
initial
prev_reset = 0;
// synopsys translate_on
always @ ( posedge clk or posedge reset)
if (reset == 1'b1) prev_reset <= 1'b0;
else prev_reset <= w_reset;
assign
c0 = wire_sd1_clk[0],
c1 = wire_sd1_clk[1],
locked = wire_sd1_locked,
phasedone = 1'b0,
readdata = {{30{1'b0}}, (read & ((w_select_control & w_pfdena) | (w_select_status & w_phasedone))), (read & ((w_select_control & w_pll_areset_in) | (w_select_status & w_locked)))},
w_locked = wire_stdsync2_dout,
w_pfdena = pfdena_reg,
w_phasedone = 1'b1,
w_pll_areset_in = prev_reset,
w_reset = ((write & w_select_control) & writedata[0]),
w_select_control = ((~ address[1]) & address[0]),
w_select_status = ((~ address[1]) & (~ address[0]));
endmodule //DE4_SOPC_altpll_0
//VALID FILE
|
//Legal Notice: (C)2013 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module DE4_SOPC_data_uart_log_module (
// inputs:
clk,
data,
strobe,
valid
)
;
input clk;
input [ 7: 0] data;
input strobe;
input valid;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
reg [31:0] text_handle; // for $fopen
initial text_handle = $fopen ("DE4_SOPC_data_uart_output_stream.dat");
always @(posedge clk) begin
if (valid && strobe) begin
$fwrite (text_handle, "%b\n", data);
// echo raw binary strings to file as ascii to screen
$write("%s", ((data == 8'hd) ? 8'ha : data));
// non-standard; poorly documented; required to get real data stream.
$fflush (text_handle);
end
end // clk
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module DE4_SOPC_data_uart_sim_scfifo_w (
// inputs:
clk,
fifo_wdata,
fifo_wr,
// outputs:
fifo_FF,
r_dat,
wfifo_empty,
wfifo_used
)
;
output fifo_FF;
output [ 7: 0] r_dat;
output wfifo_empty;
output [ 5: 0] wfifo_used;
input clk;
input [ 7: 0] fifo_wdata;
input fifo_wr;
wire fifo_FF;
wire [ 7: 0] r_dat;
wire wfifo_empty;
wire [ 5: 0] wfifo_used;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
//DE4_SOPC_data_uart_log, which is an e_log
DE4_SOPC_data_uart_log_module DE4_SOPC_data_uart_log
(
.clk (clk),
.data (fifo_wdata),
.strobe (fifo_wr),
.valid (fifo_wr)
);
assign wfifo_used = {6{1'b0}};
assign r_dat = {8{1'b0}};
assign fifo_FF = 1'b0;
assign wfifo_empty = 1'b1;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module DE4_SOPC_data_uart_scfifo_w (
// inputs:
clk,
fifo_clear,
fifo_wdata,
fifo_wr,
rd_wfifo,
// outputs:
fifo_FF,
r_dat,
wfifo_empty,
wfifo_used
)
;
output fifo_FF;
output [ 7: 0] r_dat;
output wfifo_empty;
output [ 5: 0] wfifo_used;
input clk;
input fifo_clear;
input [ 7: 0] fifo_wdata;
input fifo_wr;
input rd_wfifo;
wire fifo_FF;
wire [ 7: 0] r_dat;
wire wfifo_empty;
wire [ 5: 0] wfifo_used;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
DE4_SOPC_data_uart_sim_scfifo_w the_DE4_SOPC_data_uart_sim_scfifo_w
(
.clk (clk),
.fifo_FF (fifo_FF),
.fifo_wdata (fifo_wdata),
.fifo_wr (fifo_wr),
.r_dat (r_dat),
.wfifo_empty (wfifo_empty),
.wfifo_used (wfifo_used)
);
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// scfifo wfifo
// (
// .aclr (fifo_clear),
// .clock (clk),
// .data (fifo_wdata),
// .empty (wfifo_empty),
// .full (fifo_FF),
// .q (r_dat),
// .rdreq (rd_wfifo),
// .usedw (wfifo_used),
// .wrreq (fifo_wr)
// );
//
// defparam wfifo.lpm_hint = "RAM_BLOCK_TYPE=AUTO",
// wfifo.lpm_numwords = 64,
// wfifo.lpm_showahead = "OFF",
// wfifo.lpm_type = "scfifo",
// wfifo.lpm_width = 8,
// wfifo.lpm_widthu = 6,
// wfifo.overflow_checking = "OFF",
// wfifo.underflow_checking = "OFF",
// wfifo.use_eab = "ON";
//
//synthesis read_comments_as_HDL off
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module DE4_SOPC_data_uart_drom_module (
// inputs:
clk,
incr_addr,
reset_n,
// outputs:
new_rom,
num_bytes,
q,
safe
)
;
parameter POLL_RATE = 100;
output new_rom;
output [ 31: 0] num_bytes;
output [ 7: 0] q;
output safe;
input clk;
input incr_addr;
input reset_n;
reg [ 11: 0] address;
reg d1_pre;
reg d2_pre;
reg d3_pre;
reg d4_pre;
reg d5_pre;
reg d6_pre;
reg d7_pre;
reg d8_pre;
reg d9_pre;
reg [ 7: 0] mem_array [2047: 0];
reg [ 31: 0] mutex [ 1: 0];
reg new_rom;
wire [ 31: 0] num_bytes;
reg pre;
wire [ 7: 0] q;
wire safe;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
assign q = mem_array[address];
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
d1_pre <= 0;
d2_pre <= 0;
d3_pre <= 0;
d4_pre <= 0;
d5_pre <= 0;
d6_pre <= 0;
d7_pre <= 0;
d8_pre <= 0;
d9_pre <= 0;
new_rom <= 0;
end
else
begin
d1_pre <= pre;
d2_pre <= d1_pre;
d3_pre <= d2_pre;
d4_pre <= d3_pre;
d5_pre <= d4_pre;
d6_pre <= d5_pre;
d7_pre <= d6_pre;
d8_pre <= d7_pre;
d9_pre <= d8_pre;
new_rom <= d9_pre;
end
end
assign num_bytes = mutex[1];
reg safe_delay;
reg [31:0] poll_count;
reg [31:0] mutex_handle;
wire interactive = 1'b0 ; // '
assign safe = (address < mutex[1]);
initial poll_count = POLL_RATE;
always @(posedge clk or negedge reset_n) begin
if (reset_n !== 1) begin
safe_delay <= 0;
end else begin
safe_delay <= safe;
end
end // safe_delay
always @(posedge clk or negedge reset_n) begin
if (reset_n !== 1) begin // dont worry about null _stream.dat file
address <= 0;
mem_array[0] <= 0;
mutex[0] <= 0;
mutex[1] <= 0;
pre <= 0;
end else begin // deal with the non-reset case
pre <= 0;
if (incr_addr && safe) address <= address + 1;
if (mutex[0] && !safe && safe_delay) begin
// and blast the mutex after falling edge of safe if interactive
if (interactive) begin
mutex_handle = $fopen ("DE4_SOPC_data_uart_input_mutex.dat");
$fdisplay (mutex_handle, "0");
$fclose (mutex_handle);
// $display ($stime, "\t%m:\n\t\tMutex cleared!");
end else begin
// sleep until next reset, do not bash mutex.
wait (!reset_n);
end
end // OK to bash mutex.
if (poll_count < POLL_RATE) begin // wait
poll_count = poll_count + 1;
end else begin // do the interesting stuff.
poll_count = 0;
if (mutex_handle) begin
$readmemh ("DE4_SOPC_data_uart_input_mutex.dat", mutex);
end
if (mutex[0] && !safe) begin
// read stream into mem_array after current characters are gone!
// save mutex[0] value to compare to address (generates 'safe')
mutex[1] <= mutex[0];
// $display ($stime, "\t%m:\n\t\tMutex hit: Trying to read %d bytes...", mutex[0]);
$readmemb("DE4_SOPC_data_uart_input_stream.dat", mem_array);
// bash address and send pulse outside to send the char:
address <= 0;
pre <= -1;
end // else mutex miss...
end // poll_count
end // reset
end // posedge clk
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module DE4_SOPC_data_uart_sim_scfifo_r (
// inputs:
clk,
fifo_rd,
rst_n,
// outputs:
fifo_EF,
fifo_rdata,
rfifo_full,
rfifo_used
)
;
output fifo_EF;
output [ 7: 0] fifo_rdata;
output rfifo_full;
output [ 5: 0] rfifo_used;
input clk;
input fifo_rd;
input rst_n;
reg [ 31: 0] bytes_left;
wire fifo_EF;
reg fifo_rd_d;
wire [ 7: 0] fifo_rdata;
wire new_rom;
wire [ 31: 0] num_bytes;
wire [ 6: 0] rfifo_entries;
wire rfifo_full;
wire [ 5: 0] rfifo_used;
wire safe;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
//DE4_SOPC_data_uart_drom, which is an e_drom
DE4_SOPC_data_uart_drom_module DE4_SOPC_data_uart_drom
(
.clk (clk),
.incr_addr (fifo_rd_d),
.new_rom (new_rom),
.num_bytes (num_bytes),
.q (fifo_rdata),
.reset_n (rst_n),
.safe (safe)
);
// Generate rfifo_entries for simulation
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 0)
begin
bytes_left <= 32'h0;
fifo_rd_d <= 1'b0;
end
else
begin
fifo_rd_d <= fifo_rd;
// decrement on read
if (fifo_rd_d)
bytes_left <= bytes_left - 1'b1;
// catch new contents
if (new_rom)
bytes_left <= num_bytes;
end
end
assign fifo_EF = bytes_left == 32'b0;
assign rfifo_full = bytes_left > 7'h40;
assign rfifo_entries = (rfifo_full) ? 7'h40 : bytes_left;
assign rfifo_used = rfifo_entries[5 : 0];
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module DE4_SOPC_data_uart_scfifo_r (
// inputs:
clk,
fifo_clear,
fifo_rd,
rst_n,
t_dat,
wr_rfifo,
// outputs:
fifo_EF,
fifo_rdata,
rfifo_full,
rfifo_used
)
;
output fifo_EF;
output [ 7: 0] fifo_rdata;
output rfifo_full;
output [ 5: 0] rfifo_used;
input clk;
input fifo_clear;
input fifo_rd;
input rst_n;
input [ 7: 0] t_dat;
input wr_rfifo;
wire fifo_EF;
wire [ 7: 0] fifo_rdata;
wire rfifo_full;
wire [ 5: 0] rfifo_used;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
DE4_SOPC_data_uart_sim_scfifo_r the_DE4_SOPC_data_uart_sim_scfifo_r
(
.clk (clk),
.fifo_EF (fifo_EF),
.fifo_rd (fifo_rd),
.fifo_rdata (fifo_rdata),
.rfifo_full (rfifo_full),
.rfifo_used (rfifo_used),
.rst_n (rst_n)
);
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// scfifo rfifo
// (
// .aclr (fifo_clear),
// .clock (clk),
// .data (t_dat),
// .empty (fifo_EF),
// .full (rfifo_full),
// .q (fifo_rdata),
// .rdreq (fifo_rd),
// .usedw (rfifo_used),
// .wrreq (wr_rfifo)
// );
//
// defparam rfifo.lpm_hint = "RAM_BLOCK_TYPE=AUTO",
// rfifo.lpm_numwords = 64,
// rfifo.lpm_showahead = "OFF",
// rfifo.lpm_type = "scfifo",
// rfifo.lpm_width = 8,
// rfifo.lpm_widthu = 6,
// rfifo.overflow_checking = "OFF",
// rfifo.underflow_checking = "OFF",
// rfifo.use_eab = "ON";
//
//synthesis read_comments_as_HDL off
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module DE4_SOPC_data_uart (
// inputs:
av_address,
av_chipselect,
av_read_n,
av_write_n,
av_writedata,
clk,
rst_n,
// outputs:
av_irq,
av_readdata,
av_waitrequest,
dataavailable,
readyfordata
)
/* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"R101,C106,D101,D103\"" */ ;
output av_irq;
output [ 31: 0] av_readdata;
output av_waitrequest;
output dataavailable;
output readyfordata;
input av_address;
input av_chipselect;
input av_read_n;
input av_write_n;
input [ 31: 0] av_writedata;
input clk;
input rst_n;
reg ac;
wire activity;
wire av_irq;
wire [ 31: 0] av_readdata;
reg av_waitrequest;
reg dataavailable;
reg fifo_AE;
reg fifo_AF;
wire fifo_EF;
wire fifo_FF;
wire fifo_clear;
wire fifo_rd;
wire [ 7: 0] fifo_rdata;
wire [ 7: 0] fifo_wdata;
reg fifo_wr;
reg ien_AE;
reg ien_AF;
wire ipen_AE;
wire ipen_AF;
reg pause_irq;
wire [ 7: 0] r_dat;
wire r_ena;
reg r_val;
wire rd_wfifo;
reg read_0;
reg readyfordata;
wire rfifo_full;
wire [ 5: 0] rfifo_used;
reg rvalid;
reg sim_r_ena;
reg sim_t_dat;
reg sim_t_ena;
reg sim_t_pause;
wire [ 7: 0] t_dat;
reg t_dav;
wire t_ena;
wire t_pause;
wire wfifo_empty;
wire [ 5: 0] wfifo_used;
reg woverflow;
wire wr_rfifo;
//avalon_jtag_slave, which is an e_avalon_slave
assign rd_wfifo = r_ena & ~wfifo_empty;
assign wr_rfifo = t_ena & ~rfifo_full;
assign fifo_clear = ~rst_n;
DE4_SOPC_data_uart_scfifo_w the_DE4_SOPC_data_uart_scfifo_w
(
.clk (clk),
.fifo_FF (fifo_FF),
.fifo_clear (fifo_clear),
.fifo_wdata (fifo_wdata),
.fifo_wr (fifo_wr),
.r_dat (r_dat),
.rd_wfifo (rd_wfifo),
.wfifo_empty (wfifo_empty),
.wfifo_used (wfifo_used)
);
DE4_SOPC_data_uart_scfifo_r the_DE4_SOPC_data_uart_scfifo_r
(
.clk (clk),
.fifo_EF (fifo_EF),
.fifo_clear (fifo_clear),
.fifo_rd (fifo_rd),
.fifo_rdata (fifo_rdata),
.rfifo_full (rfifo_full),
.rfifo_used (rfifo_used),
.rst_n (rst_n),
.t_dat (t_dat),
.wr_rfifo (wr_rfifo)
);
assign ipen_AE = ien_AE & fifo_AE;
assign ipen_AF = ien_AF & (pause_irq | fifo_AF);
assign av_irq = ipen_AE | ipen_AF;
assign activity = t_pause | t_ena;
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 0)
pause_irq <= 1'b0;
else // only if fifo is not empty...
if (t_pause & ~fifo_EF)
pause_irq <= 1'b1;
else if (read_0)
pause_irq <= 1'b0;
end
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 0)
begin
r_val <= 1'b0;
t_dav <= 1'b1;
end
else
begin
r_val <= r_ena & ~wfifo_empty;
t_dav <= ~rfifo_full;
end
end
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 0)
begin
fifo_AE <= 1'b0;
fifo_AF <= 1'b0;
fifo_wr <= 1'b0;
rvalid <= 1'b0;
read_0 <= 1'b0;
ien_AE <= 1'b0;
ien_AF <= 1'b0;
ac <= 1'b0;
woverflow <= 1'b0;
av_waitrequest <= 1'b1;
end
else
begin
fifo_AE <= {fifo_FF,wfifo_used} <= 8;
fifo_AF <= (7'h40 - {rfifo_full,rfifo_used}) <= 8;
fifo_wr <= 1'b0;
read_0 <= 1'b0;
av_waitrequest <= ~(av_chipselect & (~av_write_n | ~av_read_n) & av_waitrequest);
if (activity)
ac <= 1'b1;
// write
if (av_chipselect & ~av_write_n & av_waitrequest)
// addr 1 is control; addr 0 is data
if (av_address)
begin
ien_AF <= av_writedata[0];
ien_AE <= av_writedata[1];
if (av_writedata[10] & ~activity)
ac <= 1'b0;
end
else
begin
fifo_wr <= ~fifo_FF;
woverflow <= fifo_FF;
end
// read
if (av_chipselect & ~av_read_n & av_waitrequest)
begin
// addr 1 is interrupt; addr 0 is data
if (~av_address)
rvalid <= ~fifo_EF;
read_0 <= ~av_address;
end
end
end
assign fifo_wdata = av_writedata[7 : 0];
assign fifo_rd = (av_chipselect & ~av_read_n & av_waitrequest & ~av_address) ? ~fifo_EF : 1'b0;
assign av_readdata = read_0 ? { {9{1'b0}},rfifo_full,rfifo_used,rvalid,woverflow,~fifo_FF,~fifo_EF,1'b0,ac,ipen_AE,ipen_AF,fifo_rdata } : { {9{1'b0}},(7'h40 - {fifo_FF,wfifo_used}),rvalid,woverflow,~fifo_FF,~fifo_EF,1'b0,ac,ipen_AE,ipen_AF,{6{1'b0}},ien_AE,ien_AF };
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 0)
readyfordata <= 0;
else
readyfordata <= ~fifo_FF;
end
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
// Tie off Atlantic Interface signals not used for simulation
always @(posedge clk)
begin
sim_t_pause <= 1'b0;
sim_t_ena <= 1'b0;
sim_t_dat <= t_dav ? r_dat : {8{r_val}};
sim_r_ena <= 1'b0;
end
assign r_ena = sim_r_ena;
assign t_ena = sim_t_ena;
assign t_dat = sim_t_dat;
assign t_pause = sim_t_pause;
always @(fifo_EF)
begin
dataavailable = ~fifo_EF;
end
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// alt_jtag_atlantic DE4_SOPC_data_uart_alt_jtag_atlantic
// (
// .clk (clk),
// .r_dat (r_dat),
// .r_ena (r_ena),
// .r_val (r_val),
// .rst_n (rst_n),
// .t_dat (t_dat),
// .t_dav (t_dav),
// .t_ena (t_ena),
// .t_pause (t_pause)
// );
//
// defparam DE4_SOPC_data_uart_alt_jtag_atlantic.INSTANCE_ID = 0,
// DE4_SOPC_data_uart_alt_jtag_atlantic.LOG2_RXFIFO_DEPTH = 6,
// DE4_SOPC_data_uart_alt_jtag_atlantic.LOG2_TXFIFO_DEPTH = 6,
// DE4_SOPC_data_uart_alt_jtag_atlantic.SLD_AUTO_INSTANCE_INDEX = "YES";
//
// always @(posedge clk or negedge rst_n)
// begin
// if (rst_n == 0)
// dataavailable <= 0;
// else
// dataavailable <= ~fifo_EF;
// end
//
//
//synthesis read_comments_as_HDL off
endmodule
|
// DE4_SOPC_ddr2_0.v
// This file was auto-generated from alt_mem_if_ddr2_emif_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 12.1 177 at 2013.01.18.10:32:44
`timescale 1 ps / 1 ps
module DE4_SOPC_ddr2_0 (
input wire pll_ref_clk, // pll_ref_clk.clk
input wire global_reset_n, // global_reset.reset_n
input wire soft_reset_n, // soft_reset.reset_n
output wire afi_clk, // afi_clk.clk
output wire afi_half_clk, // afi_half_clk.clk
output wire afi_reset_n, // afi_reset.reset_n
output wire [13:0] mem_a, // memory.mem_a
output wire [2:0] mem_ba, // .mem_ba
output wire [1:0] mem_ck, // .mem_ck
output wire [1:0] mem_ck_n, // .mem_ck_n
output wire [0:0] mem_cke, // .mem_cke
output wire [0:0] mem_cs_n, // .mem_cs_n
output wire [7:0] mem_dm, // .mem_dm
output wire [0:0] mem_ras_n, // .mem_ras_n
output wire [0:0] mem_cas_n, // .mem_cas_n
output wire [0:0] mem_we_n, // .mem_we_n
inout wire [63:0] mem_dq, // .mem_dq
inout wire [7:0] mem_dqs, // .mem_dqs
inout wire [7:0] mem_dqs_n, // .mem_dqs_n
output wire [0:0] mem_odt, // .mem_odt
output wire avl_ready, // avl.waitrequest_n
input wire avl_burstbegin, // .beginbursttransfer
input wire [24:0] avl_addr, // .address
output wire avl_rdata_valid, // .readdatavalid
output wire [255:0] avl_rdata, // .readdata
input wire [255:0] avl_wdata, // .writedata
input wire [31:0] avl_be, // .byteenable
input wire avl_read_req, // .read
input wire avl_write_req, // .write
input wire [3:0] avl_size, // .burstcount
output wire local_init_done, // status.local_init_done
output wire local_cal_success, // .local_cal_success
output wire local_cal_fail, // .local_cal_fail
input wire oct_rdn, // oct.rdn
input wire oct_rup // .rup
);
wire p0_addr_cmd_clk_clk; // p0:addr_cmd_clk -> m0:clk
wire [27:0] m0_phy_mux_afi_addr; // m0:phy_mux_addr -> p0:afi_addr
wire [1:0] m0_phy_mux_afi_odt; // m0:phy_mux_odt -> p0:afi_odt
wire [5:0] p0_afi_afi_wlat; // p0:afi_wlat -> m0:phy_mux_wlat
wire [1:0] p0_afi_afi_rdata_valid; // p0:afi_rdata_valid -> m0:phy_mux_rdata_valid
wire [1:0] m0_phy_mux_afi_rdata_en_full; // m0:phy_mux_rdata_en_full -> p0:afi_rdata_en_full
wire [1:0] m0_phy_mux_afi_we_n; // m0:phy_mux_we_n -> p0:afi_we_n
wire [5:0] m0_phy_mux_afi_ba; // m0:phy_mux_ba -> p0:afi_ba
wire [1:0] m0_phy_mux_afi_cke; // m0:phy_mux_cke -> p0:afi_cke
wire [1:0] m0_phy_mux_afi_cs_n; // m0:phy_mux_cs_n -> p0:afi_cs_n
wire [255:0] m0_phy_mux_afi_wdata; // m0:phy_mux_wdata -> p0:afi_wdata
wire [1:0] m0_phy_mux_afi_rdata_en; // m0:phy_mux_rdata_en -> p0:afi_rdata_en
wire [1:0] m0_phy_mux_afi_cas_n; // m0:phy_mux_cas_n -> p0:afi_cas_n
wire p0_afi_afi_cal_success; // p0:afi_cal_success -> m0:phy_mux_cal_success
wire [1:0] m0_phy_mux_afi_ras_n; // m0:phy_mux_ras_n -> p0:afi_ras_n
wire [5:0] p0_afi_afi_rlat; // p0:afi_rlat -> m0:phy_mux_rlat
wire [255:0] p0_afi_afi_rdata; // p0:afi_rdata -> m0:phy_mux_rdata
wire p0_afi_afi_cal_fail; // p0:afi_cal_fail -> m0:phy_mux_cal_fail
wire [15:0] m0_phy_mux_afi_wdata_valid; // m0:phy_mux_wdata_valid -> p0:afi_wdata_valid
wire [15:0] m0_phy_mux_afi_dqs_burst; // m0:phy_mux_dqs_burst -> p0:afi_dqs_burst
wire [31:0] m0_phy_mux_afi_dm; // m0:phy_mux_dm -> p0:afi_dm
wire [5:0] m0_afi_afi_wlat; // m0:afi_wlat -> c0:afi_wlat
wire [1:0] m0_afi_afi_rdata_valid; // m0:afi_rdata_valid -> c0:afi_rdata_valid
wire m0_afi_afi_cal_success; // m0:afi_cal_success -> c0:afi_cal_success
wire [5:0] m0_afi_afi_rlat; // m0:afi_rlat -> c0:afi_rlat
wire [255:0] m0_afi_afi_rdata; // m0:afi_rdata -> c0:afi_rdata
wire m0_afi_afi_cal_fail; // m0:afi_cal_fail -> c0:afi_cal_fail
wire p0_avl_clk_clk; // p0:avl_clk -> s0:avl_clk
wire p0_avl_reset_reset; // p0:avl_reset_n -> s0:avl_reset_n
wire p0_scc_clk_clk; // p0:scc_clk -> s0:scc_clk
wire p0_scc_reset_reset; // p0:scc_reset_n -> s0:reset_n_scc_clk
wire [27:0] s0_afi_afi_addr; // s0:afi_addr -> m0:seq_mux_addr
wire [1:0] s0_afi_afi_odt; // s0:afi_odt -> m0:seq_mux_odt
wire [1:0] m0_seq_mux_afi_rdata_valid; // m0:seq_mux_rdata_valid -> s0:afi_rdata_valid
wire [1:0] s0_afi_afi_rdata_en_full; // s0:afi_rdata_en_full -> m0:seq_mux_rdata_en_full
wire [1:0] s0_afi_afi_we_n; // s0:afi_we_n -> m0:seq_mux_we_n
wire [5:0] s0_afi_afi_ba; // s0:afi_ba -> m0:seq_mux_ba
wire [1:0] s0_afi_afi_cke; // s0:afi_cke -> m0:seq_mux_cke
wire [1:0] s0_afi_afi_cs_n; // s0:afi_cs_n -> m0:seq_mux_cs_n
wire [255:0] s0_afi_afi_wdata; // s0:afi_wdata -> m0:seq_mux_wdata
wire [1:0] s0_afi_afi_rdata_en; // s0:afi_rdata_en -> m0:seq_mux_rdata_en
wire [1:0] s0_afi_afi_cas_n; // s0:afi_cas_n -> m0:seq_mux_cas_n
wire [1:0] s0_afi_afi_ras_n; // s0:afi_ras_n -> m0:seq_mux_ras_n
wire [255:0] m0_seq_mux_afi_rdata; // m0:seq_mux_rdata -> s0:afi_rdata
wire [15:0] s0_afi_afi_wdata_valid; // s0:afi_wdata_valid -> m0:seq_mux_wdata_valid
wire [15:0] s0_afi_afi_dqs_burst; // s0:afi_dqs_burst -> m0:seq_mux_dqs_burst
wire [31:0] s0_afi_afi_dm; // s0:afi_dm -> m0:seq_mux_dm
wire s0_mux_sel_mux_sel; // s0:phy_mux_sel -> m0:mux_sel
wire s0_phy_phy_cal_success; // s0:phy_cal_success -> p0:phy_cal_success
wire p0_phy_phy_reset_n; // p0:phy_reset_n -> s0:phy_reset_n
wire s0_phy_phy_cal_fail; // s0:phy_cal_fail -> p0:phy_cal_fail
wire [7:0] s0_phy_phy_read_increment_vfifo_qr; // s0:phy_read_increment_vfifo_qr -> p0:phy_read_increment_vfifo_qr
wire p0_phy_phy_clk; // p0:phy_clk -> s0:phy_clk
wire [5:0] s0_phy_phy_afi_rlat; // s0:phy_afi_rlat -> p0:phy_afi_rlat
wire [7:0] s0_phy_phy_read_increment_vfifo_hr; // s0:phy_read_increment_vfifo_hr -> p0:phy_read_increment_vfifo_hr
wire [7:0] s0_phy_phy_vfifo_rd_en_override; // s0:phy_vfifo_rd_en_override -> p0:phy_vfifo_rd_en_override
wire [255:0] p0_phy_phy_read_fifo_q; // p0:phy_read_fifo_q -> s0:phy_read_fifo_q
wire [3:0] s0_phy_phy_read_latency_counter; // s0:phy_read_latency_counter -> p0:phy_read_latency_counter
wire [7:0] s0_phy_phy_read_fifo_reset; // s0:phy_read_fifo_reset -> p0:phy_read_fifo_reset
wire [7:0] s0_phy_phy_read_increment_vfifo_fr; // s0:phy_read_increment_vfifo_fr -> p0:phy_read_increment_vfifo_fr
wire [31:0] s0_phy_phy_cal_debug_info; // s0:phy_cal_debug_info -> p0:phy_cal_debug_info
wire s0_phy_phy_reset_mem_stable; // s0:phy_reset_mem_stable -> p0:phy_reset_mem_stable
wire [5:0] s0_phy_phy_afi_wlat; // s0:phy_afi_wlat -> p0:phy_afi_wlat
wire [7:0] p0_calib_calib_skip_steps; // p0:calib_skip_steps -> s0:calib_skip_steps
wire [7:0] s0_scc_scc_dm_ena; // s0:scc_dm_ena -> p0:scc_dm_ena
wire [63:0] s0_scc_scc_dq_ena; // s0:scc_dq_ena -> p0:scc_dq_ena
wire [7:0] s0_scc_scc_dqs_ena; // s0:scc_dqs_ena -> p0:scc_dqs_ena
wire [0:0] s0_scc_scc_upd; // s0:scc_upd -> p0:scc_upd
wire [7:0] p0_scc_capture_strobe_tracking; // p0:capture_strobe_tracking -> s0:capture_strobe_tracking
wire [7:0] s0_scc_scc_dqs_io_ena; // s0:scc_dqs_io_ena -> p0:scc_dqs_io_ena
wire s0_scc_scc_data; // s0:scc_data -> p0:scc_data
wire [27:0] c0_afi_afi_addr; // c0:afi_addr -> m0:afi_addr
wire [1:0] c0_afi_afi_odt; // c0:afi_odt -> m0:afi_odt
wire c0_afi_afi_cal_req; // c0:afi_cal_req -> s0:afi_cal_req
wire [1:0] c0_afi_afi_rdata_en_full; // c0:afi_rdata_en_full -> m0:afi_rdata_en_full
wire [1:0] c0_afi_afi_we_n; // c0:afi_we_n -> m0:afi_we_n
wire [5:0] c0_afi_afi_ba; // c0:afi_ba -> m0:afi_ba
wire [1:0] c0_afi_afi_cke; // c0:afi_cke -> m0:afi_cke
wire [1:0] c0_afi_afi_cs_n; // c0:afi_cs_n -> m0:afi_cs_n
wire [255:0] c0_afi_afi_wdata; // c0:afi_wdata -> m0:afi_wdata
wire [1:0] c0_afi_afi_rdata_en; // c0:afi_rdata_en -> m0:afi_rdata_en
wire [1:0] c0_afi_afi_cas_n; // c0:afi_cas_n -> m0:afi_cas_n
wire [1:0] c0_afi_afi_ras_n; // c0:afi_ras_n -> m0:afi_ras_n
wire [1:0] c0_afi_afi_mem_clk_disable; // c0:afi_mem_clk_disable -> p0:afi_mem_clk_disable
wire c0_afi_afi_init_req; // c0:afi_init_req -> s0:afi_init_req
wire [15:0] c0_afi_afi_wdata_valid; // c0:afi_wdata_valid -> m0:afi_wdata_valid
wire [15:0] c0_afi_afi_dqs_burst; // c0:afi_dqs_burst -> m0:afi_dqs_burst
wire [31:0] c0_afi_afi_dm; // c0:afi_dm -> m0:afi_dm
wire [13:0] oct0_oct_sharing_parallelterminationcontrol; // oct0:parallelterminationcontrol -> p0:parallelterminationcontrol
wire [13:0] oct0_oct_sharing_seriesterminationcontrol; // oct0:seriesterminationcontrol -> p0:seriesterminationcontrol
wire pll0_pll_sharing_pll_avl_clk; // pll0:pll_avl_clk -> p0:pll_avl_clk
wire pll0_pll_sharing_pll_config_clk; // pll0:pll_config_clk -> p0:pll_config_clk
wire pll0_pll_sharing_pll_addr_cmd_clk; // pll0:pll_addr_cmd_clk -> p0:pll_addr_cmd_clk
wire pll0_pll_sharing_pll_mem_clk; // pll0:pll_mem_clk -> p0:pll_mem_clk
wire pll0_pll_sharing_pll_locked; // pll0:pll_locked -> p0:pll_locked
wire pll0_pll_sharing_pll_write_clk_pre_phy_clk; // pll0:pll_write_clk_pre_phy_clk -> p0:pll_write_clk_pre_phy_clk
wire pll0_pll_sharing_pll_write_clk; // pll0:pll_write_clk -> p0:pll_write_clk
wire p0_dll_clk_clk; // p0:dll_clk -> dll0:clk
wire p0_dll_sharing_dll_pll_locked; // p0:dll_pll_locked -> dll0:dll_pll_locked
wire [5:0] dll0_dll_sharing_dll_delayctrl; // dll0:dll_delayctrl -> p0:dll_delayctrl
DE4_SOPC_ddr2_0_pll0 pll0 (
.global_reset_n (global_reset_n), // global_reset.reset_n
.afi_clk (afi_clk), // afi_clk.clk
.afi_half_clk (afi_half_clk), // afi_half_clk.clk
.pll_ref_clk (pll_ref_clk), // pll_ref_clk.clk
.pll_mem_clk (pll0_pll_sharing_pll_mem_clk), // pll_sharing.pll_mem_clk
.pll_write_clk (pll0_pll_sharing_pll_write_clk), // .pll_write_clk
.pll_write_clk_pre_phy_clk (pll0_pll_sharing_pll_write_clk_pre_phy_clk), // .pll_write_clk_pre_phy_clk
.pll_addr_cmd_clk (pll0_pll_sharing_pll_addr_cmd_clk), // .pll_addr_cmd_clk
.pll_locked (pll0_pll_sharing_pll_locked), // .pll_locked
.pll_avl_clk (pll0_pll_sharing_pll_avl_clk), // .pll_avl_clk
.pll_config_clk (pll0_pll_sharing_pll_config_clk) // .pll_config_clk
);
DE4_SOPC_ddr2_0_p0 p0 (
.global_reset_n (global_reset_n), // global_reset.reset_n
.soft_reset_n (soft_reset_n), // soft_reset.reset_n
.afi_reset_n (afi_reset_n), // afi_reset.reset_n
.afi_clk (afi_clk), // afi_clk.clk
.afi_half_clk (afi_half_clk), // afi_half_clk.clk
.addr_cmd_clk (p0_addr_cmd_clk_clk), // addr_cmd_clk.clk
.avl_clk (p0_avl_clk_clk), // avl_clk.clk
.avl_reset_n (p0_avl_reset_reset), // avl_reset.reset_n
.scc_clk (p0_scc_clk_clk), // scc_clk.clk
.scc_reset_n (p0_scc_reset_reset), // scc_reset.reset_n
.dll_clk (p0_dll_clk_clk), // dll_clk.clk
.afi_addr (m0_phy_mux_afi_addr), // afi.afi_addr
.afi_ba (m0_phy_mux_afi_ba), // .afi_ba
.afi_ras_n (m0_phy_mux_afi_ras_n), // .afi_ras_n
.afi_we_n (m0_phy_mux_afi_we_n), // .afi_we_n
.afi_cas_n (m0_phy_mux_afi_cas_n), // .afi_cas_n
.afi_odt (m0_phy_mux_afi_odt), // .afi_odt
.afi_cke (m0_phy_mux_afi_cke), // .afi_cke
.afi_cs_n (m0_phy_mux_afi_cs_n), // .afi_cs_n
.afi_dqs_burst (m0_phy_mux_afi_dqs_burst), // .afi_dqs_burst
.afi_wdata_valid (m0_phy_mux_afi_wdata_valid), // .afi_wdata_valid
.afi_wdata (m0_phy_mux_afi_wdata), // .afi_wdata
.afi_dm (m0_phy_mux_afi_dm), // .afi_dm
.afi_rdata (p0_afi_afi_rdata), // .afi_rdata
.afi_rdata_en (m0_phy_mux_afi_rdata_en), // .afi_rdata_en
.afi_rdata_en_full (m0_phy_mux_afi_rdata_en_full), // .afi_rdata_en_full
.afi_rdata_valid (p0_afi_afi_rdata_valid), // .afi_rdata_valid
.afi_cal_success (p0_afi_afi_cal_success), // .afi_cal_success
.afi_cal_fail (p0_afi_afi_cal_fail), // .afi_cal_fail
.afi_wlat (p0_afi_afi_wlat), // .afi_wlat
.afi_rlat (p0_afi_afi_rlat), // .afi_rlat
.phy_clk (p0_phy_phy_clk), // phy.phy_clk
.phy_reset_n (p0_phy_phy_reset_n), // .phy_reset_n
.phy_read_latency_counter (s0_phy_phy_read_latency_counter), // .phy_read_latency_counter
.phy_afi_wlat (s0_phy_phy_afi_wlat), // .phy_afi_wlat
.phy_afi_rlat (s0_phy_phy_afi_rlat), // .phy_afi_rlat
.phy_read_increment_vfifo_fr (s0_phy_phy_read_increment_vfifo_fr), // .phy_read_increment_vfifo_fr
.phy_read_increment_vfifo_hr (s0_phy_phy_read_increment_vfifo_hr), // .phy_read_increment_vfifo_hr
.phy_read_increment_vfifo_qr (s0_phy_phy_read_increment_vfifo_qr), // .phy_read_increment_vfifo_qr
.phy_reset_mem_stable (s0_phy_phy_reset_mem_stable), // .phy_reset_mem_stable
.phy_cal_success (s0_phy_phy_cal_success), // .phy_cal_success
.phy_cal_fail (s0_phy_phy_cal_fail), // .phy_cal_fail
.phy_cal_debug_info (s0_phy_phy_cal_debug_info), // .phy_cal_debug_info
.phy_read_fifo_reset (s0_phy_phy_read_fifo_reset), // .phy_read_fifo_reset
.phy_vfifo_rd_en_override (s0_phy_phy_vfifo_rd_en_override), // .phy_vfifo_rd_en_override
.phy_read_fifo_q (p0_phy_phy_read_fifo_q), // .phy_read_fifo_q
.calib_skip_steps (p0_calib_calib_skip_steps), // calib.calib_skip_steps
.scc_data (s0_scc_scc_data), // scc.scc_data
.scc_dqs_ena (s0_scc_scc_dqs_ena), // .scc_dqs_ena
.scc_dqs_io_ena (s0_scc_scc_dqs_io_ena), // .scc_dqs_io_ena
.scc_dq_ena (s0_scc_scc_dq_ena), // .scc_dq_ena
.scc_dm_ena (s0_scc_scc_dm_ena), // .scc_dm_ena
.capture_strobe_tracking (p0_scc_capture_strobe_tracking), // .capture_strobe_tracking
.scc_upd (s0_scc_scc_upd), // .scc_upd
.afi_mem_clk_disable (c0_afi_afi_mem_clk_disable), // afi_mem_clk_disable.afi_mem_clk_disable
.pll_mem_clk (pll0_pll_sharing_pll_mem_clk), // pll_sharing.pll_mem_clk
.pll_write_clk (pll0_pll_sharing_pll_write_clk), // .pll_write_clk
.pll_write_clk_pre_phy_clk (pll0_pll_sharing_pll_write_clk_pre_phy_clk), // .pll_write_clk_pre_phy_clk
.pll_addr_cmd_clk (pll0_pll_sharing_pll_addr_cmd_clk), // .pll_addr_cmd_clk
.pll_locked (pll0_pll_sharing_pll_locked), // .pll_locked
.pll_avl_clk (pll0_pll_sharing_pll_avl_clk), // .pll_avl_clk
.pll_config_clk (pll0_pll_sharing_pll_config_clk), // .pll_config_clk
.dll_pll_locked (p0_dll_sharing_dll_pll_locked), // dll_sharing.dll_pll_locked
.dll_delayctrl (dll0_dll_sharing_dll_delayctrl), // .dll_delayctrl
.seriesterminationcontrol (oct0_oct_sharing_seriesterminationcontrol), // oct_sharing.seriesterminationcontrol
.parallelterminationcontrol (oct0_oct_sharing_parallelterminationcontrol), // .parallelterminationcontrol
.mem_a (mem_a), // memory.mem_a
.mem_ba (mem_ba), // .mem_ba
.mem_ck (mem_ck), // .mem_ck
.mem_ck_n (mem_ck_n), // .mem_ck_n
.mem_cke (mem_cke), // .mem_cke
.mem_cs_n (mem_cs_n), // .mem_cs_n
.mem_dm (mem_dm), // .mem_dm
.mem_ras_n (mem_ras_n), // .mem_ras_n
.mem_cas_n (mem_cas_n), // .mem_cas_n
.mem_we_n (mem_we_n), // .mem_we_n
.mem_dq (mem_dq), // .mem_dq
.mem_dqs (mem_dqs), // .mem_dqs
.mem_dqs_n (mem_dqs_n), // .mem_dqs_n
.mem_odt (mem_odt), // .mem_odt
.csr_soft_reset_req (1'b0) // (terminated)
);
afi_mux_ddrx #(
.AFI_RATE_RATIO (2),
.AFI_ADDR_WIDTH (28),
.AFI_BANKADDR_WIDTH (6),
.AFI_CONTROL_WIDTH (2),
.AFI_CS_WIDTH (2),
.AFI_CLK_EN_WIDTH (2),
.AFI_DM_WIDTH (32),
.AFI_DQ_WIDTH (256),
.AFI_ODT_WIDTH (2),
.AFI_WRITE_DQS_WIDTH (16),
.AFI_RLAT_WIDTH (6),
.AFI_WLAT_WIDTH (6)
) m0 (
.clk (p0_addr_cmd_clk_clk), // clk.clk
.afi_addr (c0_afi_afi_addr), // afi.afi_addr
.afi_ba (c0_afi_afi_ba), // .afi_ba
.afi_ras_n (c0_afi_afi_ras_n), // .afi_ras_n
.afi_we_n (c0_afi_afi_we_n), // .afi_we_n
.afi_cas_n (c0_afi_afi_cas_n), // .afi_cas_n
.afi_odt (c0_afi_afi_odt), // .afi_odt
.afi_cke (c0_afi_afi_cke), // .afi_cke
.afi_cs_n (c0_afi_afi_cs_n), // .afi_cs_n
.afi_dqs_burst (c0_afi_afi_dqs_burst), // .afi_dqs_burst
.afi_wdata_valid (c0_afi_afi_wdata_valid), // .afi_wdata_valid
.afi_wdata (c0_afi_afi_wdata), // .afi_wdata
.afi_dm (c0_afi_afi_dm), // .afi_dm
.afi_rdata (m0_afi_afi_rdata), // .afi_rdata
.afi_rdata_en (c0_afi_afi_rdata_en), // .afi_rdata_en
.afi_rdata_en_full (c0_afi_afi_rdata_en_full), // .afi_rdata_en_full
.afi_rdata_valid (m0_afi_afi_rdata_valid), // .afi_rdata_valid
.afi_cal_success (m0_afi_afi_cal_success), // .afi_cal_success
.afi_cal_fail (m0_afi_afi_cal_fail), // .afi_cal_fail
.afi_wlat (m0_afi_afi_wlat), // .afi_wlat
.afi_rlat (m0_afi_afi_rlat), // .afi_rlat
.seq_mux_addr (s0_afi_afi_addr), // seq_mux.afi_addr
.seq_mux_ba (s0_afi_afi_ba), // .afi_ba
.seq_mux_ras_n (s0_afi_afi_ras_n), // .afi_ras_n
.seq_mux_we_n (s0_afi_afi_we_n), // .afi_we_n
.seq_mux_cas_n (s0_afi_afi_cas_n), // .afi_cas_n
.seq_mux_odt (s0_afi_afi_odt), // .afi_odt
.seq_mux_cke (s0_afi_afi_cke), // .afi_cke
.seq_mux_cs_n (s0_afi_afi_cs_n), // .afi_cs_n
.seq_mux_dqs_burst (s0_afi_afi_dqs_burst), // .afi_dqs_burst
.seq_mux_wdata_valid (s0_afi_afi_wdata_valid), // .afi_wdata_valid
.seq_mux_wdata (s0_afi_afi_wdata), // .afi_wdata
.seq_mux_dm (s0_afi_afi_dm), // .afi_dm
.seq_mux_rdata (m0_seq_mux_afi_rdata), // .afi_rdata
.seq_mux_rdata_en (s0_afi_afi_rdata_en), // .afi_rdata_en
.seq_mux_rdata_en_full (s0_afi_afi_rdata_en_full), // .afi_rdata_en_full
.seq_mux_rdata_valid (m0_seq_mux_afi_rdata_valid), // .afi_rdata_valid
.phy_mux_addr (m0_phy_mux_afi_addr), // phy_mux.afi_addr
.phy_mux_ba (m0_phy_mux_afi_ba), // .afi_ba
.phy_mux_ras_n (m0_phy_mux_afi_ras_n), // .afi_ras_n
.phy_mux_we_n (m0_phy_mux_afi_we_n), // .afi_we_n
.phy_mux_cas_n (m0_phy_mux_afi_cas_n), // .afi_cas_n
.phy_mux_odt (m0_phy_mux_afi_odt), // .afi_odt
.phy_mux_cke (m0_phy_mux_afi_cke), // .afi_cke
.phy_mux_cs_n (m0_phy_mux_afi_cs_n), // .afi_cs_n
.phy_mux_dqs_burst (m0_phy_mux_afi_dqs_burst), // .afi_dqs_burst
.phy_mux_wdata_valid (m0_phy_mux_afi_wdata_valid), // .afi_wdata_valid
.phy_mux_wdata (m0_phy_mux_afi_wdata), // .afi_wdata
.phy_mux_dm (m0_phy_mux_afi_dm), // .afi_dm
.phy_mux_rdata (p0_afi_afi_rdata), // .afi_rdata
.phy_mux_rdata_en (m0_phy_mux_afi_rdata_en), // .afi_rdata_en
.phy_mux_rdata_en_full (m0_phy_mux_afi_rdata_en_full), // .afi_rdata_en_full
.phy_mux_rdata_valid (p0_afi_afi_rdata_valid), // .afi_rdata_valid
.phy_mux_cal_success (p0_afi_afi_cal_success), // .afi_cal_success
.phy_mux_cal_fail (p0_afi_afi_cal_fail), // .afi_cal_fail
.phy_mux_wlat (p0_afi_afi_wlat), // .afi_wlat
.phy_mux_rlat (p0_afi_afi_rlat), // .afi_rlat
.mux_sel (s0_mux_sel_mux_sel) // mux_sel.mux_sel
);
DE4_SOPC_ddr2_0_s0 s0 (
.avl_clk (p0_avl_clk_clk), // avl_clk.clk
.avl_reset_n (p0_avl_reset_reset), // avl_reset.reset_n
.scc_clk (p0_scc_clk_clk), // scc_clk.clk
.reset_n_scc_clk (p0_scc_reset_reset), // scc_reset.reset_n
.scc_data (s0_scc_scc_data), // scc.scc_data
.scc_dqs_ena (s0_scc_scc_dqs_ena), // .scc_dqs_ena
.scc_dqs_io_ena (s0_scc_scc_dqs_io_ena), // .scc_dqs_io_ena
.scc_dq_ena (s0_scc_scc_dq_ena), // .scc_dq_ena
.scc_dm_ena (s0_scc_scc_dm_ena), // .scc_dm_ena
.capture_strobe_tracking (p0_scc_capture_strobe_tracking), // .capture_strobe_tracking
.scc_upd (s0_scc_scc_upd), // .scc_upd
.afi_init_req (c0_afi_afi_init_req), // afi_init_cal_req.afi_init_req
.afi_cal_req (c0_afi_afi_cal_req), // .afi_cal_req
.phy_clk (p0_phy_phy_clk), // phy.phy_clk
.phy_reset_n (p0_phy_phy_reset_n), // .phy_reset_n
.phy_read_latency_counter (s0_phy_phy_read_latency_counter), // .phy_read_latency_counter
.phy_afi_wlat (s0_phy_phy_afi_wlat), // .phy_afi_wlat
.phy_afi_rlat (s0_phy_phy_afi_rlat), // .phy_afi_rlat
.phy_read_increment_vfifo_fr (s0_phy_phy_read_increment_vfifo_fr), // .phy_read_increment_vfifo_fr
.phy_read_increment_vfifo_hr (s0_phy_phy_read_increment_vfifo_hr), // .phy_read_increment_vfifo_hr
.phy_read_increment_vfifo_qr (s0_phy_phy_read_increment_vfifo_qr), // .phy_read_increment_vfifo_qr
.phy_reset_mem_stable (s0_phy_phy_reset_mem_stable), // .phy_reset_mem_stable
.phy_cal_success (s0_phy_phy_cal_success), // .phy_cal_success
.phy_cal_fail (s0_phy_phy_cal_fail), // .phy_cal_fail
.phy_cal_debug_info (s0_phy_phy_cal_debug_info), // .phy_cal_debug_info
.phy_read_fifo_reset (s0_phy_phy_read_fifo_reset), // .phy_read_fifo_reset
.phy_vfifo_rd_en_override (s0_phy_phy_vfifo_rd_en_override), // .phy_vfifo_rd_en_override
.phy_read_fifo_q (p0_phy_phy_read_fifo_q), // .phy_read_fifo_q
.calib_skip_steps (p0_calib_calib_skip_steps), // calib.calib_skip_steps
.phy_mux_sel (s0_mux_sel_mux_sel), // mux_sel.mux_sel
.afi_clk (afi_clk), // afi_clk.clk
.afi_reset_n (afi_reset_n), // afi_reset.reset_n
.afi_addr (s0_afi_afi_addr), // afi.afi_addr
.afi_ba (s0_afi_afi_ba), // .afi_ba
.afi_ras_n (s0_afi_afi_ras_n), // .afi_ras_n
.afi_we_n (s0_afi_afi_we_n), // .afi_we_n
.afi_cas_n (s0_afi_afi_cas_n), // .afi_cas_n
.afi_odt (s0_afi_afi_odt), // .afi_odt
.afi_cke (s0_afi_afi_cke), // .afi_cke
.afi_cs_n (s0_afi_afi_cs_n), // .afi_cs_n
.afi_dqs_burst (s0_afi_afi_dqs_burst), // .afi_dqs_burst
.afi_wdata_valid (s0_afi_afi_wdata_valid), // .afi_wdata_valid
.afi_wdata (s0_afi_afi_wdata), // .afi_wdata
.afi_dm (s0_afi_afi_dm), // .afi_dm
.afi_rdata (m0_seq_mux_afi_rdata), // .afi_rdata
.afi_rdata_en (s0_afi_afi_rdata_en), // .afi_rdata_en
.afi_rdata_en_full (s0_afi_afi_rdata_en_full), // .afi_rdata_en_full
.afi_rdata_valid (m0_seq_mux_afi_rdata_valid), // .afi_rdata_valid
.phy_write_fr_cycle_shifts () // (terminated)
);
DE4_SOPC_ddr2_0_c0 c0 (
.afi_reset_n (afi_reset_n), // afi_reset.reset_n
.afi_clk (afi_clk), // afi_clk.clk
.afi_half_clk (afi_half_clk), // afi_half_clk.clk
.local_init_done (local_init_done), // status.local_init_done
.local_cal_success (local_cal_success), // .local_cal_success
.local_cal_fail (local_cal_fail), // .local_cal_fail
.afi_addr (c0_afi_afi_addr), // afi.afi_addr
.afi_ba (c0_afi_afi_ba), // .afi_ba
.afi_ras_n (c0_afi_afi_ras_n), // .afi_ras_n
.afi_we_n (c0_afi_afi_we_n), // .afi_we_n
.afi_cas_n (c0_afi_afi_cas_n), // .afi_cas_n
.afi_odt (c0_afi_afi_odt), // .afi_odt
.afi_cke (c0_afi_afi_cke), // .afi_cke
.afi_cs_n (c0_afi_afi_cs_n), // .afi_cs_n
.afi_dqs_burst (c0_afi_afi_dqs_burst), // .afi_dqs_burst
.afi_wdata_valid (c0_afi_afi_wdata_valid), // .afi_wdata_valid
.afi_wdata (c0_afi_afi_wdata), // .afi_wdata
.afi_dm (c0_afi_afi_dm), // .afi_dm
.afi_rdata (m0_afi_afi_rdata), // .afi_rdata
.afi_mem_clk_disable (c0_afi_afi_mem_clk_disable), // .afi_mem_clk_disable
.afi_init_req (c0_afi_afi_init_req), // .afi_init_req
.afi_cal_req (c0_afi_afi_cal_req), // .afi_cal_req
.afi_rdata_en (c0_afi_afi_rdata_en), // .afi_rdata_en
.afi_rdata_en_full (c0_afi_afi_rdata_en_full), // .afi_rdata_en_full
.afi_rdata_valid (m0_afi_afi_rdata_valid), // .afi_rdata_valid
.afi_cal_success (m0_afi_afi_cal_success), // .afi_cal_success
.afi_cal_fail (m0_afi_afi_cal_fail), // .afi_cal_fail
.afi_wlat (m0_afi_afi_wlat), // .afi_wlat
.afi_rlat (m0_afi_afi_rlat), // .afi_rlat
.avl_ready (avl_ready), // avl.waitrequest_n
.avl_burstbegin (avl_burstbegin), // .beginbursttransfer
.avl_addr (avl_addr), // .address
.avl_rdata_valid (avl_rdata_valid), // .readdatavalid
.avl_rdata (avl_rdata), // .readdata
.avl_wdata (avl_wdata), // .writedata
.avl_be (avl_be), // .byteenable
.avl_read_req (avl_read_req), // .read
.avl_write_req (avl_write_req), // .write
.avl_size (avl_size) // .burstcount
);
altera_mem_if_oct_stratixiv #(
.OCT_TERM_CONTROL_WIDTH (14)
) oct0 (
.oct_rdn (oct_rdn), // oct.rdn
.oct_rup (oct_rup), // .rup
.seriesterminationcontrol (oct0_oct_sharing_seriesterminationcontrol), // oct_sharing.seriesterminationcontrol
.parallelterminationcontrol (oct0_oct_sharing_parallelterminationcontrol) // .parallelterminationcontrol
);
altera_mem_if_dll_stratixiv #(
.DLL_DELAY_CTRL_WIDTH (6),
.DLL_OFFSET_CTRL_WIDTH (6),
.DELAY_BUFFER_MODE ("HIGH"),
.DELAY_CHAIN_LENGTH (10),
.DLL_INPUT_FREQUENCY_PS_STR ("5000 ps")
) dll0 (
.clk (p0_dll_clk_clk), // clk.clk
.dll_pll_locked (p0_dll_sharing_dll_pll_locked), // dll_sharing.dll_pll_locked
.dll_delayctrl (dll0_dll_sharing_dll_delayctrl) // .dll_delayctrl
);
endmodule
|
// DE4_SOPC_ddr2_0_c0.v
// This file was auto-generated from alt_mem_if_nextgen_ddr2_controller_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 11.1 173 at 2012.08.31.13:49:30
`timescale 1 ps / 1 ps
module DE4_SOPC_ddr2_0_c0 (
input wire afi_reset_n, // afi_reset.reset_n
input wire afi_clk, // afi_clk.clk
input wire afi_half_clk, // afi_half_clk.clk
output wire local_init_done, // status.local_init_done
output wire local_cal_success, // .local_cal_success
output wire local_cal_fail, // .local_cal_fail
output wire [27:0] afi_addr, // afi.afi_addr
output wire [5:0] afi_ba, // .afi_ba
output wire [1:0] afi_cke, // .afi_cke
output wire [1:0] afi_cs_n, // .afi_cs_n
output wire [1:0] afi_ras_n, // .afi_ras_n
output wire [1:0] afi_we_n, // .afi_we_n
output wire [1:0] afi_cas_n, // .afi_cas_n
output wire [1:0] afi_odt, // .afi_odt
output wire [1:0] afi_mem_clk_disable, // .afi_mem_clk_disable
output wire afi_init_req, // .afi_init_req
output wire afi_cal_req, // .afi_cal_req
output wire [15:0] afi_dqs_burst, // .afi_dqs_burst
output wire [15:0] afi_wdata_valid, // .afi_wdata_valid
output wire [255:0] afi_wdata, // .afi_wdata
output wire [31:0] afi_dm, // .afi_dm
input wire [255:0] afi_rdata, // .afi_rdata
output wire [1:0] afi_rdata_en, // .afi_rdata_en
output wire [1:0] afi_rdata_en_full, // .afi_rdata_en_full
input wire [1:0] afi_rdata_valid, // .afi_rdata_valid
input wire afi_cal_success, // .afi_cal_success
input wire afi_cal_fail, // .afi_cal_fail
input wire [5:0] afi_wlat, // .afi_wlat
input wire [5:0] afi_rlat, // .afi_rlat
output wire avl_ready, // avl.waitrequest_n
input wire avl_burstbegin, // .beginbursttransfer
input wire [24:0] avl_addr, // .address
output wire avl_rdata_valid, // .readdatavalid
output wire [255:0] avl_rdata, // .readdata
input wire [255:0] avl_wdata, // .writedata
input wire [31:0] avl_be, // .byteenable
input wire avl_read_req, // .read
input wire avl_write_req, // .write
input wire [3:0] avl_size // .burstcount
);
wire a0_native_st_itf_wr_data_begin; // a0:itf_wr_data_begin -> ng0:itf_wr_data_begin
wire a0_native_st_itf_rd_data_ready; // a0:itf_rd_data_ready -> ng0:itf_rd_data_ready
wire [255:0] a0_native_st_itf_wr_data; // a0:itf_wr_data -> ng0:itf_wr_data
wire ng0_native_st_itf_rd_data_error; // ng0:itf_rd_data_error -> a0:itf_rd_data_error
wire ng0_native_st_itf_rd_data_begin; // ng0:itf_rd_data_begin -> a0:itf_rd_data_begin
wire [7:0] a0_native_st_itf_wr_data_id; // a0:itf_wr_data_id -> ng0:itf_wr_data_id
wire ng0_native_st_itf_cmd_ready; // ng0:itf_cmd_ready -> a0:itf_cmd_ready
wire a0_native_st_itf_wr_data_last; // a0:itf_wr_data_last -> ng0:itf_wr_data_last
wire [31:0] a0_native_st_itf_wr_data_byte_en; // a0:itf_wr_data_byte_en -> ng0:itf_wr_data_byte_en
wire [24:0] a0_native_st_itf_cmd_address; // a0:itf_cmd_address -> ng0:itf_cmd_address
wire a0_native_st_itf_cmd_valid; // a0:itf_cmd_valid -> ng0:itf_cmd_valid
wire a0_native_st_itf_wr_data_valid; // a0:itf_wr_data_valid -> ng0:itf_wr_data_valid
wire a0_native_st_itf_cmd_autopercharge; // a0:itf_cmd_autopercharge -> ng0:itf_cmd_autopercharge
wire ng0_native_st_itf_rd_data_last; // ng0:itf_rd_data_last -> a0:itf_rd_data_last
wire [255:0] ng0_native_st_itf_rd_data; // ng0:itf_rd_data -> a0:itf_rd_data
wire [3:0] a0_native_st_itf_cmd_burstlen; // a0:itf_cmd_burstlen -> ng0:itf_cmd_burstlen
wire ng0_native_st_itf_rd_data_valid; // ng0:itf_rd_data_valid -> a0:itf_rd_data_valid
wire a0_native_st_itf_cmd_multicast; // a0:itf_cmd_multicast -> ng0:itf_cmd_multicast
wire [7:0] a0_native_st_itf_cmd_id; // a0:itf_cmd_id -> ng0:itf_cmd_id
wire ng0_native_st_itf_wr_data_ready; // ng0:itf_wr_data_ready -> a0:itf_wr_data_ready
wire [7:0] ng0_native_st_itf_rd_data_id; // ng0:itf_rd_data_id -> a0:itf_rd_data_id
wire a0_native_st_itf_cmd; // a0:itf_cmd -> ng0:itf_cmd
wire a0_native_st_itf_cmd_priority; // a0:itf_cmd_priority -> ng0:itf_cmd_priority
alt_mem_if_nextgen_ddr2_controller_core #(
.MEM_IF_ADDR_WIDTH (14),
.MEM_IF_ROW_ADDR_WIDTH (14),
.MEM_IF_COL_ADDR_WIDTH (10),
.MEM_IF_DM_WIDTH (8),
.MEM_IF_DQS_WIDTH (8),
.MEM_IF_CS_WIDTH (1),
.MEM_IF_CHIP_BITS (1),
.MEM_IF_BANKADDR_WIDTH (3),
.MEM_IF_DQ_WIDTH (64),
.MEM_IF_CLK_PAIR_COUNT (2),
.MEM_TRC (11),
.MEM_TRAS (8),
.MEM_TRCD (3),
.MEM_TRP (3),
.MEM_TREFI (1560),
.MEM_TRFC (26),
.MEM_TWR (3),
.MEM_TFAW (8),
.MEM_TRRD (2),
.MEM_TRTP (2),
.MEM_IF_ODT_WIDTH (1),
.MEM_WTCL_INT (5),
.MEM_IF_RD_TO_WR_TURNAROUND_OCT (3),
.MEM_IF_WR_TO_RD_TURNAROUND_OCT (3),
.CTL_RD_TO_PCH_EXTRA_CLK (0),
.MEM_TCL (6),
.MEM_TMRD_CK (5),
.MEM_TWTR (3),
.CSR_ADDR_WIDTH (8),
.CSR_DATA_WIDTH (32),
.CSR_BE_WIDTH (4),
.AVL_ADDR_WIDTH (25),
.AVL_BE_WIDTH (32),
.AVL_DATA_WIDTH (256),
.AVL_SIZE_WIDTH (4),
.DWIDTH_RATIO (4),
.CTL_ODT_ENABLED (1),
.CTL_OUTPUT_REGD (0),
.CTL_ECC_MULTIPLES_16_24_40_72 (1),
.CTL_REGDIMM_ENABLED (0),
.CTL_TBP_NUM (1),
.CTL_USR_REFRESH (0),
.CFG_TYPE (1),
.CFG_INTERFACE_WIDTH (64),
.CFG_BURST_LENGTH (4),
.CFG_ADDR_ORDER (0),
.CFG_PDN_EXIT_CYCLES (3),
.CFG_POWER_SAVING_EXIT_CYCLES (5),
.CFG_MEM_CLK_ENTRY_CYCLES (10),
.CFG_SELF_RFSH_EXIT_CYCLES (200),
.CFG_PORT_WIDTH_WRITE_ODT_CHIP (1),
.CFG_PORT_WIDTH_READ_ODT_CHIP (1),
.CFG_WRITE_ODT_CHIP (1),
.CFG_READ_ODT_CHIP (0),
.LOCAL_CS_WIDTH (0),
.CFG_CLR_INTR (0),
.CFG_ENABLE_NO_DM (0),
.MEM_ADD_LAT (0),
.MEM_AUTO_PD_CYCLES (0),
.CFG_REORDER_DATA (0),
.CFG_STARVE_LIMIT (10),
.CTL_CSR_ENABLED (0),
.CTL_ECC_ENABLED (0),
.CTL_ECC_AUTO_CORRECTION_ENABLED (0),
.CTL_ENABLE_BURST_INTERRUPT (0),
.CTL_ENABLE_BURST_TERMINATE (0),
.LOCAL_ID_WIDTH (8),
.RDBUFFER_ADDR_WIDTH (7),
.WRBUFFER_ADDR_WIDTH (6),
.CFG_DATA_REORDERING_TYPE ("INTER_BANK"),
.AFI_RATE_RATIO (2),
.AFI_ADDR_WIDTH (28),
.AFI_BANKADDR_WIDTH (6),
.AFI_CONTROL_WIDTH (2),
.AFI_CS_WIDTH (2),
.AFI_DM_WIDTH (32),
.AFI_DQ_WIDTH (256),
.AFI_ODT_WIDTH (2),
.AFI_WRITE_DQS_WIDTH (16),
.AFI_RLAT_WIDTH (6),
.AFI_WLAT_WIDTH (6)
) ng0 (
.afi_reset_n (afi_reset_n), // afi_reset.reset_n
.afi_half_clk (afi_half_clk), // afi_half_clk.clk
.afi_clk (afi_clk), // afi_clk.clk
.local_init_done (local_init_done), // status.local_init_done
.local_cal_success (local_cal_success), // .local_cal_success
.local_cal_fail (local_cal_fail), // .local_cal_fail
.itf_cmd_ready (ng0_native_st_itf_cmd_ready), // native_st.itf_cmd_ready
.itf_cmd_valid (a0_native_st_itf_cmd_valid), // .itf_cmd_valid
.itf_cmd (a0_native_st_itf_cmd), // .itf_cmd
.itf_cmd_address (a0_native_st_itf_cmd_address), // .itf_cmd_address
.itf_cmd_burstlen (a0_native_st_itf_cmd_burstlen), // .itf_cmd_burstlen
.itf_cmd_id (a0_native_st_itf_cmd_id), // .itf_cmd_id
.itf_cmd_priority (a0_native_st_itf_cmd_priority), // .itf_cmd_priority
.itf_cmd_autopercharge (a0_native_st_itf_cmd_autopercharge), // .itf_cmd_autopercharge
.itf_cmd_multicast (a0_native_st_itf_cmd_multicast), // .itf_cmd_multicast
.itf_wr_data_ready (ng0_native_st_itf_wr_data_ready), // .itf_wr_data_ready
.itf_wr_data_valid (a0_native_st_itf_wr_data_valid), // .itf_wr_data_valid
.itf_wr_data (a0_native_st_itf_wr_data), // .itf_wr_data
.itf_wr_data_byte_en (a0_native_st_itf_wr_data_byte_en), // .itf_wr_data_byte_en
.itf_wr_data_begin (a0_native_st_itf_wr_data_begin), // .itf_wr_data_begin
.itf_wr_data_last (a0_native_st_itf_wr_data_last), // .itf_wr_data_last
.itf_wr_data_id (a0_native_st_itf_wr_data_id), // .itf_wr_data_id
.itf_rd_data_ready (a0_native_st_itf_rd_data_ready), // .itf_rd_data_ready
.itf_rd_data_valid (ng0_native_st_itf_rd_data_valid), // .itf_rd_data_valid
.itf_rd_data (ng0_native_st_itf_rd_data), // .itf_rd_data
.itf_rd_data_error (ng0_native_st_itf_rd_data_error), // .itf_rd_data_error
.itf_rd_data_begin (ng0_native_st_itf_rd_data_begin), // .itf_rd_data_begin
.itf_rd_data_last (ng0_native_st_itf_rd_data_last), // .itf_rd_data_last
.itf_rd_data_id (ng0_native_st_itf_rd_data_id), // .itf_rd_data_id
.afi_addr (afi_addr), // afi.afi_addr
.afi_ba (afi_ba), // .afi_ba
.afi_cke (afi_cke), // .afi_cke
.afi_cs_n (afi_cs_n), // .afi_cs_n
.afi_ras_n (afi_ras_n), // .afi_ras_n
.afi_we_n (afi_we_n), // .afi_we_n
.afi_cas_n (afi_cas_n), // .afi_cas_n
.afi_odt (afi_odt), // .afi_odt
.afi_mem_clk_disable (afi_mem_clk_disable), // .afi_mem_clk_disable
.afi_init_req (afi_init_req), // .afi_init_req
.afi_cal_req (afi_cal_req), // .afi_cal_req
.afi_dqs_burst (afi_dqs_burst), // .afi_dqs_burst
.afi_wdata_valid (afi_wdata_valid), // .afi_wdata_valid
.afi_wdata (afi_wdata), // .afi_wdata
.afi_dm (afi_dm), // .afi_dm
.afi_rdata (afi_rdata), // .afi_rdata
.afi_rdata_en (afi_rdata_en), // .afi_rdata_en
.afi_rdata_en_full (afi_rdata_en_full), // .afi_rdata_en_full
.afi_rdata_valid (afi_rdata_valid), // .afi_rdata_valid
.afi_cal_success (afi_cal_success), // .afi_cal_success
.afi_cal_fail (afi_cal_fail), // .afi_cal_fail
.afi_wlat (afi_wlat), // .afi_wlat
.afi_rlat (afi_rlat), // .afi_rlat
.csr_write_req (1'b0), // (terminated)
.csr_read_req (1'b0), // (terminated)
.csr_waitrequest (), // (terminated)
.csr_addr (8'b00000000), // (terminated)
.csr_be (4'b0000), // (terminated)
.csr_wdata (32'b00000000000000000000000000000000), // (terminated)
.csr_rdata (), // (terminated)
.csr_rdata_valid (), // (terminated)
.local_multicast (1'b0), // (terminated)
.local_refresh_req (1'b0), // (terminated)
.local_refresh_chip (1'b0), // (terminated)
.local_refresh_ack (), // (terminated)
.local_self_rfsh_req (1'b0), // (terminated)
.local_self_rfsh_chip (1'b0), // (terminated)
.local_self_rfsh_ack (), // (terminated)
.local_deep_powerdn_req (1'b0), // (terminated)
.local_deep_powerdn_chip (1'b0), // (terminated)
.local_deep_powerdn_ack (), // (terminated)
.local_powerdn_ack (), // (terminated)
.local_priority (1'b0) // (terminated)
);
alt_mem_ddrx_mm_st_converter #(
.AVL_SIZE_WIDTH (4),
.AVL_ADDR_WIDTH (25),
.AVL_DATA_WIDTH (256),
.LOCAL_ID_WIDTH (8),
.CFG_DWIDTH_RATIO (4)
) a0 (
.ctl_clk (afi_clk), // afi_clk.clk
.ctl_reset_n (afi_reset_n), // afi_reset.reset_n
.ctl_half_clk (afi_half_clk), // afi_half_clk.clk
.ctl_half_clk_reset_n (afi_reset_n), // afi_half_reset.reset_n
.avl_ready (avl_ready), // avl.waitrequest_n
.avl_burstbegin (avl_burstbegin), // .beginbursttransfer
.avl_addr (avl_addr), // .address
.avl_rdata_valid (avl_rdata_valid), // .readdatavalid
.avl_rdata (avl_rdata), // .readdata
.avl_wdata (avl_wdata), // .writedata
.avl_be (avl_be), // .byteenable
.avl_read_req (avl_read_req), // .read
.avl_write_req (avl_write_req), // .write
.avl_size (avl_size), // .burstcount
.itf_cmd_ready (ng0_native_st_itf_cmd_ready), // native_st.itf_cmd_ready
.itf_cmd_valid (a0_native_st_itf_cmd_valid), // .itf_cmd_valid
.itf_cmd (a0_native_st_itf_cmd), // .itf_cmd
.itf_cmd_address (a0_native_st_itf_cmd_address), // .itf_cmd_address
.itf_cmd_burstlen (a0_native_st_itf_cmd_burstlen), // .itf_cmd_burstlen
.itf_cmd_id (a0_native_st_itf_cmd_id), // .itf_cmd_id
.itf_cmd_priority (a0_native_st_itf_cmd_priority), // .itf_cmd_priority
.itf_cmd_autopercharge (a0_native_st_itf_cmd_autopercharge), // .itf_cmd_autopercharge
.itf_cmd_multicast (a0_native_st_itf_cmd_multicast), // .itf_cmd_multicast
.itf_wr_data_ready (ng0_native_st_itf_wr_data_ready), // .itf_wr_data_ready
.itf_wr_data_valid (a0_native_st_itf_wr_data_valid), // .itf_wr_data_valid
.itf_wr_data (a0_native_st_itf_wr_data), // .itf_wr_data
.itf_wr_data_byte_en (a0_native_st_itf_wr_data_byte_en), // .itf_wr_data_byte_en
.itf_wr_data_begin (a0_native_st_itf_wr_data_begin), // .itf_wr_data_begin
.itf_wr_data_last (a0_native_st_itf_wr_data_last), // .itf_wr_data_last
.itf_wr_data_id (a0_native_st_itf_wr_data_id), // .itf_wr_data_id
.itf_rd_data_ready (a0_native_st_itf_rd_data_ready), // .itf_rd_data_ready
.itf_rd_data_valid (ng0_native_st_itf_rd_data_valid), // .itf_rd_data_valid
.itf_rd_data (ng0_native_st_itf_rd_data), // .itf_rd_data
.itf_rd_data_error (ng0_native_st_itf_rd_data_error), // .itf_rd_data_error
.itf_rd_data_begin (ng0_native_st_itf_rd_data_begin), // .itf_rd_data_begin
.itf_rd_data_last (ng0_native_st_itf_rd_data_last), // .itf_rd_data_last
.itf_rd_data_id (ng0_native_st_itf_rd_data_id), // .itf_rd_data_id
.local_multicast (1'b0), // (terminated)
.local_autopch_req (1'b0), // (terminated)
.local_priority (1'b0) // (terminated)
);
endmodule
|
// (C) 2001-2012 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1 ps / 1 ps
module DE4_SOPC_ddr2_0_p0_acv_ldc
(
pll_hr_clk,
pll_dq_clk,
pll_dqs_clk,
dll_phy_delayctrl,
afi_clk,
avl_clk,
adc_clk,
adc_clk_cps,
hr_clk
);
parameter DLL_DELAY_CTRL_WIDTH = "";
parameter ADC_PHASE_SETTING = 0;
parameter ADC_INVERT_PHASE = "false";
parameter IS_HHP_HPS = "false";
input pll_hr_clk;
input pll_dq_clk;
input pll_dqs_clk;
input [DLL_DELAY_CTRL_WIDTH-1:0] dll_phy_delayctrl;
output afi_clk;
output avl_clk;
output adc_clk;
output adc_clk_cps;
output hr_clk;
wire phy_clk_dqs;
wire phy_clk_dq;
wire phy_clk_hr;
wire phy_clk_dqs_2x;
wire phy_clk_addr_cmd;
wire phy_clk_addr_cmd_cps;
generate
if (IS_HHP_HPS == "true") begin
assign phy_clk_hr = pll_hr_clk;
assign phy_clk_dq = pll_dq_clk;
assign phy_clk_dqs = pll_dqs_clk;
assign phy_clk_dqs_2x = 1'b0;
end else begin
cyclonev_phy_clkbuf phy_clkbuf (
.inclk ({pll_hr_clk, pll_dq_clk, pll_dqs_clk, 1'b0}),
.outclk ({phy_clk_hr, phy_clk_dq, phy_clk_dqs, phy_clk_dqs_2x})
);
end
endgenerate
wire [3:0] leveled_dqs_clocks;
wire [3:0] leveled_hr_clocks;
wire hr_seq_clock;
cyclonev_leveling_delay_chain leveling_delay_chain_dqs (
.clkin (phy_clk_dqs),
.delayctrlin (dll_phy_delayctrl),
.clkout(leveled_dqs_clocks)
);
defparam leveling_delay_chain_dqs.physical_clock_source = "DQS";
assign afi_clk = leveled_dqs_clocks[0];
cyclonev_leveling_delay_chain leveling_delay_chain_hr (
.clkin (phy_clk_hr),
.delayctrlin (),
.clkout(leveled_hr_clocks)
);
defparam leveling_delay_chain_hr.physical_clock_source = "HR";
assign avl_clk = leveled_hr_clocks[0];
cyclonev_clk_phase_select clk_phase_select_addr_cmd (
.clkin(leveled_dqs_clocks),
.clkout(adc_clk_cps)
);
defparam clk_phase_select_addr_cmd.physical_clock_source = "ADD_CMD";
defparam clk_phase_select_addr_cmd.use_phasectrlin = "false";
defparam clk_phase_select_addr_cmd.phase_setting = ADC_PHASE_SETTING;
defparam clk_phase_select_addr_cmd.invert_phase = ADC_INVERT_PHASE;
cyclonev_clk_phase_select clk_phase_select_hr (
.phasectrlin(),
.phaseinvertctrl(),
.dqsin(),
`ifndef SIMGEN
.clkin (leveled_hr_clocks[0]),
`else
.clkin (leveled_hr_clocks),
`endif
.clkout (hr_seq_clock)
);
defparam clk_phase_select_hr.physical_clock_source = "HR";
defparam clk_phase_select_hr.use_phasectrlin = "false";
defparam clk_phase_select_hr.phase_setting = 0;
assign hr_clk = hr_seq_clock;
generate
if (ADC_INVERT_PHASE == "true")
begin
assign adc_clk = ~leveled_dqs_clocks[ADC_PHASE_SETTING];
end else begin
assign adc_clk = leveled_dqs_clocks[ADC_PHASE_SETTING];
end
endgenerate
endmodule
|
// (C) 2001-2012 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1 ps / 1 ps
module DE4_SOPC_ddr2_0_p0_addr_cmd_datapath(
clk,
reset_n,
afi_address,
afi_bank,
afi_cs_n,
afi_cke,
afi_odt,
afi_ras_n,
afi_cas_n,
afi_we_n,
phy_ddio_address,
phy_ddio_bank,
phy_ddio_cs_n,
phy_ddio_cke,
phy_ddio_we_n,
phy_ddio_ras_n,
phy_ddio_cas_n,
phy_ddio_odt
);
parameter MEM_ADDRESS_WIDTH = "";
parameter MEM_BANK_WIDTH = "";
parameter MEM_CHIP_SELECT_WIDTH = "";
parameter MEM_CLK_EN_WIDTH = "";
parameter MEM_ODT_WIDTH = "";
parameter MEM_DM_WIDTH = "";
parameter MEM_CONTROL_WIDTH = "";
parameter MEM_DQ_WIDTH = "";
parameter MEM_READ_DQS_WIDTH = "";
parameter MEM_WRITE_DQS_WIDTH = "";
parameter AFI_ADDRESS_WIDTH = "";
parameter AFI_BANK_WIDTH = "";
parameter AFI_CHIP_SELECT_WIDTH = "";
parameter AFI_CLK_EN_WIDTH = "";
parameter AFI_ODT_WIDTH = "";
parameter AFI_DATA_MASK_WIDTH = "";
parameter AFI_CONTROL_WIDTH = "";
parameter AFI_DATA_WIDTH = "";
parameter NUM_AC_FR_CYCLE_SHIFTS = "";
localparam RATE_MULT = 2;
input reset_n;
input clk;
input [AFI_ADDRESS_WIDTH-1:0] afi_address;
input [AFI_BANK_WIDTH-1:0] afi_bank;
input [AFI_CHIP_SELECT_WIDTH-1:0] afi_cs_n;
input [AFI_CLK_EN_WIDTH-1:0] afi_cke;
input [AFI_ODT_WIDTH-1:0] afi_odt;
input [AFI_CONTROL_WIDTH-1:0] afi_ras_n;
input [AFI_CONTROL_WIDTH-1:0] afi_cas_n;
input [AFI_CONTROL_WIDTH-1:0] afi_we_n;
output [AFI_ADDRESS_WIDTH-1:0] phy_ddio_address;
output [AFI_BANK_WIDTH-1:0] phy_ddio_bank;
output [AFI_CHIP_SELECT_WIDTH-1:0] phy_ddio_cs_n;
output [AFI_CLK_EN_WIDTH-1:0] phy_ddio_cke;
output [AFI_ODT_WIDTH-1:0] phy_ddio_odt;
output [AFI_CONTROL_WIDTH-1:0] phy_ddio_ras_n;
output [AFI_CONTROL_WIDTH-1:0] phy_ddio_cas_n;
output [AFI_CONTROL_WIDTH-1:0] phy_ddio_we_n;
wire [AFI_ADDRESS_WIDTH-1:0] afi_address_r = afi_address;
wire [AFI_BANK_WIDTH-1:0] afi_bank_r = afi_bank;
wire [AFI_CHIP_SELECT_WIDTH-1:0] afi_cs_n_r = afi_cs_n;
wire [AFI_CLK_EN_WIDTH-1:0] afi_cke_r = afi_cke;
wire [AFI_ODT_WIDTH-1:0] afi_odt_r = afi_odt;
wire [AFI_CONTROL_WIDTH-1:0] afi_ras_n_r = afi_ras_n;
wire [AFI_CONTROL_WIDTH-1:0] afi_cas_n_r = afi_cas_n;
wire [AFI_CONTROL_WIDTH-1:0] afi_we_n_r = afi_we_n;
wire [1:0] shift_fr_cycle =
(NUM_AC_FR_CYCLE_SHIFTS == 0) ? 2'b00 : (
(NUM_AC_FR_CYCLE_SHIFTS == 1) ? 2'b01 : (
(NUM_AC_FR_CYCLE_SHIFTS == 2) ? 2'b10 : (
2'b11 )));
DE4_SOPC_ddr2_0_p0_fr_cycle_shifter uaddr_cmd_shift_address(
.clk (clk),
.reset_n (reset_n),
.shift_by (shift_fr_cycle),
.datain (afi_address_r),
.dataout (phy_ddio_address)
);
defparam uaddr_cmd_shift_address.DATA_WIDTH = MEM_ADDRESS_WIDTH;
defparam uaddr_cmd_shift_address.REG_POST_RESET_HIGH = "false";
DE4_SOPC_ddr2_0_p0_fr_cycle_shifter uaddr_cmd_shift_bank(
.clk (clk),
.reset_n (reset_n),
.shift_by (shift_fr_cycle),
.datain (afi_bank_r),
.dataout (phy_ddio_bank)
);
defparam uaddr_cmd_shift_bank.DATA_WIDTH = MEM_BANK_WIDTH;
defparam uaddr_cmd_shift_bank.REG_POST_RESET_HIGH = "false";
DE4_SOPC_ddr2_0_p0_fr_cycle_shifter uaddr_cmd_shift_cke(
.clk (clk),
.reset_n (reset_n),
.shift_by (shift_fr_cycle),
.datain (afi_cke_r),
.dataout (phy_ddio_cke)
);
defparam uaddr_cmd_shift_cke.DATA_WIDTH = MEM_CLK_EN_WIDTH;
defparam uaddr_cmd_shift_cke.REG_POST_RESET_HIGH = "false";
DE4_SOPC_ddr2_0_p0_fr_cycle_shifter uaddr_cmd_shift_cs_n(
.clk (clk),
.reset_n (reset_n),
.shift_by (shift_fr_cycle),
.datain (afi_cs_n_r),
.dataout (phy_ddio_cs_n)
);
defparam uaddr_cmd_shift_cs_n.DATA_WIDTH = MEM_CHIP_SELECT_WIDTH;
defparam uaddr_cmd_shift_cs_n.REG_POST_RESET_HIGH = "true";
DE4_SOPC_ddr2_0_p0_fr_cycle_shifter uaddr_cmd_shift_odt(
.clk (clk),
.reset_n (reset_n),
.shift_by (shift_fr_cycle),
.datain (afi_odt_r),
.dataout (phy_ddio_odt)
);
defparam uaddr_cmd_shift_odt.DATA_WIDTH = MEM_ODT_WIDTH;
defparam uaddr_cmd_shift_odt.REG_POST_RESET_HIGH = "false";
DE4_SOPC_ddr2_0_p0_fr_cycle_shifter uaddr_cmd_shift_ras_n(
.clk (clk),
.reset_n (reset_n),
.shift_by (shift_fr_cycle),
.datain (afi_ras_n_r),
.dataout (phy_ddio_ras_n)
);
defparam uaddr_cmd_shift_ras_n.DATA_WIDTH = MEM_CONTROL_WIDTH;
defparam uaddr_cmd_shift_ras_n.REG_POST_RESET_HIGH = "true";
DE4_SOPC_ddr2_0_p0_fr_cycle_shifter uaddr_cmd_shift_cas_n(
.clk (clk),
.reset_n (reset_n),
.shift_by (shift_fr_cycle),
.datain (afi_cas_n_r),
.dataout (phy_ddio_cas_n)
);
defparam uaddr_cmd_shift_cas_n.DATA_WIDTH = MEM_CONTROL_WIDTH;
defparam uaddr_cmd_shift_cas_n.REG_POST_RESET_HIGH = "true";
DE4_SOPC_ddr2_0_p0_fr_cycle_shifter uaddr_cmd_shift_we_n(
.clk (clk),
.reset_n (reset_n),
.shift_by (shift_fr_cycle),
.datain (afi_we_n_r),
.dataout (phy_ddio_we_n)
);
defparam uaddr_cmd_shift_we_n.DATA_WIDTH = MEM_CONTROL_WIDTH;
defparam uaddr_cmd_shift_we_n.REG_POST_RESET_HIGH = "true";
endmodule
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// *****************************************************************
// File name: addr_cmd_ldc_pad.v
//
// Address/command pad using leveling hardware.
// See comments in addr_cmd_ldc_pads.v for details.
//
// *****************************************************************
`timescale 1 ps / 1 ps
module DE4_SOPC_ddr2_0_p0_addr_cmd_ldc_pad (
pll_afi_clk,
pll_hr_clk,
pll_c2p_write_clk,
pll_write_clk,
dll_delayctrl_in,
afi_datain,
mem_dataout
);
// *****************************************************************
// BEGIN PARAMETER SECTION
// All parameters default to "" will have their values passed in
// from higher level wrapper with the controller and driver
parameter AFI_DATA_WIDTH = "";
parameter MEM_DATA_WIDTH = "";
parameter DLL_WIDTH = "";
parameter REGISTER_C2P = "";
localparam DDR_MULT = AFI_DATA_WIDTH / MEM_DATA_WIDTH / 2;
// *****************************************************************
// BEGIN PORT SECTION
input pll_afi_clk;
input pll_hr_clk;
input pll_c2p_write_clk;
input pll_write_clk;
input [DLL_WIDTH-1:0] dll_delayctrl_in;
input [AFI_DATA_WIDTH-1:0] afi_datain;
output [MEM_DATA_WIDTH-1:0] mem_dataout;
// *****************************************************************
// BEGIN SIGNALS SECTION
wire [2 * DDR_MULT * MEM_DATA_WIDTH - 1:0] hr_data;
wire [1 * DDR_MULT * MEM_DATA_WIDTH - 1:0] fr_data;
reg [MEM_DATA_WIDTH - 1:0] fr_data_reg;
// *****************************************************************
// The AFI domain is the half-rate domain.
// Register the C2P boundary if needed.
generate
if (REGISTER_C2P == "false") begin
assign hr_data = afi_datain;
end else begin
reg [2 * DDR_MULT * MEM_DATA_WIDTH - 1:0] tmp_hr_data_reg;
always @(posedge pll_afi_clk) begin
tmp_hr_data_reg <= afi_datain;
end
assign hr_data = tmp_hr_data_reg;
end
endgenerate
// *****************************************************************
// Half-rate to full-rate conversion using half-rate register
DE4_SOPC_ddr2_0_p0_simple_ddio_out # (
.DATA_WIDTH (MEM_DATA_WIDTH),
.OUTPUT_FULL_DATA_WIDTH (MEM_DATA_WIDTH),
.USE_CORE_LOGIC ("false"),
.HALF_RATE_MODE ("true")
) hr_to_fr (
.clk (pll_c2p_write_clk),
.datain (hr_data),
.dataout (fr_data),
.reset_n (1'b1)
);
generate
genvar i;
for (i = 0; i < MEM_DATA_WIDTH; i = i + 1)
begin: sdio_out
wire [3:0] delayed_clks;
wire leveling_clk;
// We instantiate one leveling delay chain and clock phase select
// block per pin. The fitter merges these blocks as needed
// to maximize pin placement flexibility.
stratixv_leveling_delay_chain # (
.physical_clock_source ("dqs")
) ldc (
.clkin (pll_write_clk),
.delayctrlin (dll_delayctrl_in),
.clkout (delayed_clks)
);
stratixv_clk_phase_select # (
.physical_clock_source ("add_cmd"),
.use_phasectrlin ("false"),
.invert_phase ("false"),
.phase_setting (0)
) cps (
.clkin (delayed_clks),
.clkout (leveling_clk)
);
// Output data goes through the SDIO register to phase-align it
// with the leveling clock which has the property of center-
// aligning the addr/cmd signals with the ck/ck# clock.
always @(posedge leveling_clk) begin
fr_data_reg[i] = fr_data[i];
end
assign mem_dataout[i] = fr_data_reg[i];
end
endgenerate
endmodule
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// *****************************************************************
// File name: addr_cmd_ldc_pads.v
//
// Address/command pads using PHY clock and leveling hardware.
//
// Inputs are addr/cmd signals in the AFI domain.
//
// Outputs are addr/cmd signals that can be readily connected to
// top-level ports going out to external memory.
//
// This version offers higher performance than previous generation
// of addr/cmd pads. To highlight the differences:
//
// 1) We use the PHY clock tree to clock the addr/cmd I/Os, instead
// of core clock. The PHY clock tree has much smaller clock skew
// compared to the core clock, giving us more timing margin.
//
// 2) The PHY clock tree drives a leveling delay chain which
// generates both the CK/CK# clock and the launch clock for the
// addr/cmd signals. The similarity between the CK/CK# path and
// the addr/cmd signal paths reduces timing margin loss due to
// min/max. Previous generation uses separate PLL output counter
// and global networks for CK/CK# and addr/cmd signals.
//
// Important clock signals:
//
// pll_afi_clk -- AFI clock. Only used by 1/4-rate designs to
// convert 1/4 addr/cmd signals to 1/2 rate, or
// when REGISTER_C2P is true.
//
// pll_c2p_write_clk -- Half-rate clock that clocks the HR registers
// for 1/2-rate to full rate conversion. Only
// used in 1/4 rate and 1/2 rate designs.
// This signal must come from the PHY clock.
//
// pll_write_clk -- Full-rate clock that goes into the leveling
// delay chain and then used to clock the SDIO
// register (or DDIO_OUT) and for CK/CK# generation.
// This signal must come from the PHY clock.
//
// *****************************************************************
`timescale 1 ps / 1 ps
module DE4_SOPC_ddr2_0_p0_addr_cmd_ldc_pads (
reset_n,
reset_n_afi_clk,
pll_afi_clk,
pll_mem_clk,
pll_hr_clk,
pll_c2p_write_clk,
pll_write_clk,
phy_ddio_addr_cmd_clk,
phy_ddio_address,
dll_delayctrl_in,
enable_mem_clk,
phy_ddio_bank,
phy_ddio_cs_n,
phy_ddio_cke,
phy_ddio_odt,
phy_ddio_we_n,
phy_ddio_ras_n,
phy_ddio_cas_n,
phy_mem_address,
phy_mem_bank,
phy_mem_cs_n,
phy_mem_cke,
phy_mem_odt,
phy_mem_we_n,
phy_mem_ras_n,
phy_mem_cas_n,
phy_mem_ck,
phy_mem_ck_n
);
// *****************************************************************
// BEGIN PARAMETER SECTION
// All parameters default to "" will have their values passed in
// from higher level wrapper with the controller and driver
parameter DEVICE_FAMILY = "";
parameter DLL_WIDTH = "";
parameter REGISTER_C2P = "";
// Width of the addr/cmd signals going out to the external memory
parameter MEM_ADDRESS_WIDTH = "";
parameter MEM_CONTROL_WIDTH = "";
parameter MEM_BANK_WIDTH = "";
parameter MEM_CHIP_SELECT_WIDTH = "";
parameter MEM_CLK_EN_WIDTH = "";
parameter MEM_CK_WIDTH = "";
parameter MEM_ODT_WIDTH = "";
// Width of the addr/cmd signals coming in from the AFI
parameter AFI_ADDRESS_WIDTH = "";
parameter AFI_CONTROL_WIDTH = "";
parameter AFI_BANK_WIDTH = "";
parameter AFI_CHIP_SELECT_WIDTH = "";
parameter AFI_CLK_EN_WIDTH = "";
parameter AFI_ODT_WIDTH = "";
// *****************************************************************
// BEGIN PORT SECTION
input reset_n;
input reset_n_afi_clk;
input pll_afi_clk;
input pll_mem_clk;
input pll_write_clk;
input pll_hr_clk;
input pll_c2p_write_clk;
input phy_ddio_addr_cmd_clk;
input [DLL_WIDTH-1:0] dll_delayctrl_in;
input [MEM_CK_WIDTH-1:0] enable_mem_clk;
input [AFI_ADDRESS_WIDTH-1:0] phy_ddio_address;
input [AFI_BANK_WIDTH-1:0] phy_ddio_bank;
input [AFI_CHIP_SELECT_WIDTH-1:0] phy_ddio_cs_n;
input [AFI_CLK_EN_WIDTH-1:0] phy_ddio_cke;
input [AFI_ODT_WIDTH-1:0] phy_ddio_odt;
input [AFI_CONTROL_WIDTH-1:0] phy_ddio_ras_n;
input [AFI_CONTROL_WIDTH-1:0] phy_ddio_cas_n;
input [AFI_CONTROL_WIDTH-1:0] phy_ddio_we_n;
output [MEM_ADDRESS_WIDTH-1:0] phy_mem_address;
output [MEM_BANK_WIDTH-1:0] phy_mem_bank;
output [MEM_CHIP_SELECT_WIDTH-1:0] phy_mem_cs_n;
output [MEM_CLK_EN_WIDTH-1:0] phy_mem_cke;
output [MEM_ODT_WIDTH-1:0] phy_mem_odt;
output [MEM_CONTROL_WIDTH-1:0] phy_mem_we_n;
output [MEM_CONTROL_WIDTH-1:0] phy_mem_ras_n;
output [MEM_CONTROL_WIDTH-1:0] phy_mem_cas_n;
output [MEM_CK_WIDTH-1:0] phy_mem_ck;
output [MEM_CK_WIDTH-1:0] phy_mem_ck_n;
// *****************************************************************
// Instantiate pads for every a/c signal
DE4_SOPC_ddr2_0_p0_addr_cmd_ldc_pad # (
.AFI_DATA_WIDTH (AFI_ADDRESS_WIDTH),
.MEM_DATA_WIDTH (MEM_ADDRESS_WIDTH),
.DLL_WIDTH (DLL_WIDTH),
.REGISTER_C2P (REGISTER_C2P)
) uaddress_pad (
.pll_afi_clk (pll_afi_clk),
.pll_hr_clk (pll_hr_clk),
.pll_c2p_write_clk (pll_c2p_write_clk),
.pll_write_clk (pll_write_clk),
.dll_delayctrl_in (dll_delayctrl_in),
.afi_datain (phy_ddio_address),
.mem_dataout (phy_mem_address)
);
DE4_SOPC_ddr2_0_p0_addr_cmd_ldc_pad # (
.AFI_DATA_WIDTH (AFI_BANK_WIDTH),
.MEM_DATA_WIDTH (MEM_BANK_WIDTH),
.DLL_WIDTH (DLL_WIDTH),
.REGISTER_C2P (REGISTER_C2P)
) ubank_pad (
.pll_afi_clk (pll_afi_clk),
.pll_hr_clk (pll_hr_clk),
.pll_c2p_write_clk (pll_c2p_write_clk),
.pll_write_clk (pll_write_clk),
.dll_delayctrl_in (dll_delayctrl_in),
.afi_datain (phy_ddio_bank),
.mem_dataout (phy_mem_bank)
);
DE4_SOPC_ddr2_0_p0_addr_cmd_ldc_pad # (
.AFI_DATA_WIDTH (AFI_CHIP_SELECT_WIDTH),
.MEM_DATA_WIDTH (MEM_CHIP_SELECT_WIDTH),
.DLL_WIDTH (DLL_WIDTH),
.REGISTER_C2P (REGISTER_C2P)
) ucs_n_pad (
.pll_afi_clk (pll_afi_clk),
.pll_hr_clk (pll_hr_clk),
.pll_c2p_write_clk (pll_c2p_write_clk),
.pll_write_clk (pll_write_clk),
.dll_delayctrl_in (dll_delayctrl_in),
.afi_datain (phy_ddio_cs_n),
.mem_dataout (phy_mem_cs_n)
);
DE4_SOPC_ddr2_0_p0_addr_cmd_ldc_pad # (
.AFI_DATA_WIDTH (AFI_CLK_EN_WIDTH),
.MEM_DATA_WIDTH (MEM_CLK_EN_WIDTH),
.DLL_WIDTH (DLL_WIDTH),
.REGISTER_C2P (REGISTER_C2P)
) ucke_pad (
.pll_afi_clk (pll_afi_clk),
.pll_hr_clk (pll_hr_clk),
.pll_c2p_write_clk (pll_c2p_write_clk),
.pll_write_clk (pll_write_clk),
.dll_delayctrl_in (dll_delayctrl_in),
.afi_datain (phy_ddio_cke),
.mem_dataout (phy_mem_cke)
);
DE4_SOPC_ddr2_0_p0_addr_cmd_ldc_pad # (
.AFI_DATA_WIDTH (AFI_ODT_WIDTH),
.MEM_DATA_WIDTH (MEM_ODT_WIDTH),
.DLL_WIDTH (DLL_WIDTH),
.REGISTER_C2P (REGISTER_C2P)
) uodt_pad (
.pll_afi_clk (pll_afi_clk),
.pll_hr_clk (pll_hr_clk),
.pll_c2p_write_clk (pll_c2p_write_clk),
.pll_write_clk (pll_write_clk),
.dll_delayctrl_in (dll_delayctrl_in),
.afi_datain (phy_ddio_odt),
.mem_dataout (phy_mem_odt)
);
DE4_SOPC_ddr2_0_p0_addr_cmd_ldc_pad # (
.AFI_DATA_WIDTH (AFI_CONTROL_WIDTH),
.MEM_DATA_WIDTH (MEM_CONTROL_WIDTH),
.DLL_WIDTH (DLL_WIDTH),
.REGISTER_C2P (REGISTER_C2P)
) uwe_n_pad (
.pll_afi_clk (pll_afi_clk),
.pll_hr_clk (pll_hr_clk),
.pll_c2p_write_clk (pll_c2p_write_clk),
.pll_write_clk (pll_write_clk),
.dll_delayctrl_in (dll_delayctrl_in),
.afi_datain (phy_ddio_we_n),
.mem_dataout (phy_mem_we_n)
);
DE4_SOPC_ddr2_0_p0_addr_cmd_ldc_pad # (
.AFI_DATA_WIDTH (AFI_CONTROL_WIDTH),
.MEM_DATA_WIDTH (MEM_CONTROL_WIDTH),
.DLL_WIDTH (DLL_WIDTH),
.REGISTER_C2P (REGISTER_C2P)
) uras_n_pad (
.pll_afi_clk (pll_afi_clk),
.pll_hr_clk (pll_hr_clk),
.pll_c2p_write_clk (pll_c2p_write_clk),
.pll_write_clk (pll_write_clk),
.dll_delayctrl_in (dll_delayctrl_in),
.afi_datain (phy_ddio_ras_n),
.mem_dataout (phy_mem_ras_n)
);
DE4_SOPC_ddr2_0_p0_addr_cmd_ldc_pad # (
.AFI_DATA_WIDTH (AFI_CONTROL_WIDTH),
.MEM_DATA_WIDTH (MEM_CONTROL_WIDTH),
.DLL_WIDTH (DLL_WIDTH),
.REGISTER_C2P (REGISTER_C2P)
) ucas_n_pad (
.pll_afi_clk (pll_afi_clk),
.pll_hr_clk (pll_hr_clk),
.pll_c2p_write_clk (pll_c2p_write_clk),
.pll_write_clk (pll_write_clk),
.dll_delayctrl_in (dll_delayctrl_in),
.afi_datain (phy_ddio_cas_n),
.mem_dataout (phy_mem_cas_n)
);
// *****************************************************************
// Instantiate CK/CK# generation circuitry if needed
genvar clock_width;
generate
for (clock_width = 0; clock_width < MEM_CK_WIDTH; clock_width = clock_width + 1)
begin: clock_gen
wire [MEM_CK_WIDTH-1:0] mem_ck_ddio_out;
wire [3:0] delayed_clks;
wire leveling_clk;
stratixv_leveling_delay_chain # (
.physical_clock_source ("dqs")
) ldc (
.clkin (pll_write_clk),
.delayctrlin (dll_delayctrl_in),
.clkout (delayed_clks)
);
stratixv_clk_phase_select # (
.physical_clock_source ("add_cmd"),
.use_phasectrlin ("false"),
.invert_phase ("false"),
.phase_setting (0)
) cps (
.clkin (delayed_clks),
.clkout (leveling_clk)
);
altddio_out # (
.extend_oe_disable ("UNUSED"),
.intended_device_family (DEVICE_FAMILY),
.invert_output ("OFF"),
.lpm_hint ("UNUSED"),
.lpm_type ("altddio_out"),
.oe_reg ("UNUSED"),
.power_up_high ("OFF"),
.width (1)
) umem_ck_pad (
.aclr (1'b0),
.aset (1'b0),
.datain_h (1'b0),
.datain_l (1'b1),
.dataout (mem_ck_ddio_out[clock_width]),
.oe (enable_mem_clk[clock_width]),
.outclock (leveling_clk),
.outclocken (1'b1)
);
DE4_SOPC_ddr2_0_p0_clock_pair_generator uclk_generator (
.datain (mem_ck_ddio_out[clock_width]),
.dataout (phy_mem_ck[clock_width]),
.dataout_b (phy_mem_ck_n[clock_width])
);
end
endgenerate
endmodule
|
// (C) 2001-2012 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1 ps / 1 ps
module DE4_SOPC_ddr2_0_p0_addr_cmd_pads(
reset_n,
reset_n_afi_clk,
pll_afi_clk,
pll_mem_clk,
pll_c2p_write_clk,
pll_write_clk,
pll_hr_clk,
phy_ddio_addr_cmd_clk,
phy_ddio_address,
dll_delayctrl_in,
enable_mem_clk,
phy_ddio_bank,
phy_ddio_cs_n,
phy_ddio_cke,
phy_ddio_odt,
phy_ddio_we_n,
phy_ddio_ras_n,
phy_ddio_cas_n,
phy_mem_address,
phy_mem_bank,
phy_mem_cs_n,
phy_mem_cke,
phy_mem_odt,
phy_mem_we_n,
phy_mem_ras_n,
phy_mem_cas_n,
phy_mem_ck,
phy_mem_ck_n
);
parameter DEVICE_FAMILY = "";
parameter MEM_ADDRESS_WIDTH = "";
parameter MEM_BANK_WIDTH = "";
parameter MEM_CHIP_SELECT_WIDTH = "";
parameter MEM_CLK_EN_WIDTH = "";
parameter MEM_CK_WIDTH = "";
parameter MEM_ODT_WIDTH = "";
parameter MEM_CONTROL_WIDTH = "";
parameter AFI_ADDRESS_WIDTH = "";
parameter AFI_BANK_WIDTH = "";
parameter AFI_CHIP_SELECT_WIDTH = "";
parameter AFI_CLK_EN_WIDTH = "";
parameter AFI_ODT_WIDTH = "";
parameter AFI_CONTROL_WIDTH = "";
parameter DLL_WIDTH = "";
parameter REGISTER_C2P = "";
parameter IS_HHP_HPS = "";
input reset_n;
input reset_n_afi_clk;
input pll_afi_clk;
input pll_mem_clk;
input pll_write_clk;
input pll_hr_clk;
input pll_c2p_write_clk;
input phy_ddio_addr_cmd_clk;
input [DLL_WIDTH-1:0] dll_delayctrl_in;
input [MEM_CK_WIDTH-1:0] enable_mem_clk;
input [AFI_ADDRESS_WIDTH-1:0] phy_ddio_address;
input [AFI_BANK_WIDTH-1:0] phy_ddio_bank;
input [AFI_CHIP_SELECT_WIDTH-1:0] phy_ddio_cs_n;
input [AFI_CLK_EN_WIDTH-1:0] phy_ddio_cke;
input [AFI_ODT_WIDTH-1:0] phy_ddio_odt;
input [AFI_CONTROL_WIDTH-1:0] phy_ddio_ras_n;
input [AFI_CONTROL_WIDTH-1:0] phy_ddio_cas_n;
input [AFI_CONTROL_WIDTH-1:0] phy_ddio_we_n;
output [MEM_ADDRESS_WIDTH-1:0] phy_mem_address;
output [MEM_BANK_WIDTH-1:0] phy_mem_bank;
output [MEM_CHIP_SELECT_WIDTH-1:0] phy_mem_cs_n;
output [MEM_CLK_EN_WIDTH-1:0] phy_mem_cke;
output [MEM_ODT_WIDTH-1:0] phy_mem_odt;
output [MEM_CONTROL_WIDTH-1:0] phy_mem_we_n;
output [MEM_CONTROL_WIDTH-1:0] phy_mem_ras_n;
output [MEM_CONTROL_WIDTH-1:0] phy_mem_cas_n;
output [MEM_CK_WIDTH-1:0] phy_mem_ck;
output [MEM_CK_WIDTH-1:0] phy_mem_ck_n;
wire [MEM_ADDRESS_WIDTH-1:0] address_l;
wire [MEM_ADDRESS_WIDTH-1:0] address_h;
wire adc_ldc_ck;
wire [MEM_CHIP_SELECT_WIDTH-1:0] cs_n_l;
wire [MEM_CHIP_SELECT_WIDTH-1:0] cs_n_h;
wire [MEM_CLK_EN_WIDTH-1:0] cke_l;
wire [MEM_CLK_EN_WIDTH-1:0] cke_h;
reg [AFI_ADDRESS_WIDTH-1:0] phy_ddio_address_hr;
reg [AFI_BANK_WIDTH-1:0] phy_ddio_bank_hr;
reg [AFI_CHIP_SELECT_WIDTH-1:0] phy_ddio_cs_n_hr;
reg [AFI_CLK_EN_WIDTH-1:0] phy_ddio_cke_hr;
reg [AFI_ODT_WIDTH-1:0] phy_ddio_odt_hr;
reg [AFI_CONTROL_WIDTH-1:0] phy_ddio_ras_n_hr;
reg [AFI_CONTROL_WIDTH-1:0] phy_ddio_cas_n_hr;
reg [AFI_CONTROL_WIDTH-1:0] phy_ddio_we_n_hr;
generate
if (REGISTER_C2P == "false") begin
always @(*) begin
phy_ddio_address_hr = phy_ddio_address;
phy_ddio_bank_hr = phy_ddio_bank;
phy_ddio_cs_n_hr = phy_ddio_cs_n;
phy_ddio_cke_hr = phy_ddio_cke;
phy_ddio_odt_hr = phy_ddio_odt;
phy_ddio_ras_n_hr = phy_ddio_ras_n;
phy_ddio_cas_n_hr = phy_ddio_cas_n;
phy_ddio_we_n_hr = phy_ddio_we_n;
end
end else begin
always @(posedge phy_ddio_addr_cmd_clk) begin
phy_ddio_address_hr <= phy_ddio_address;
phy_ddio_bank_hr <= phy_ddio_bank;
phy_ddio_cs_n_hr <= phy_ddio_cs_n;
phy_ddio_cke_hr <= phy_ddio_cke;
phy_ddio_odt_hr <= phy_ddio_odt;
phy_ddio_ras_n_hr <= phy_ddio_ras_n;
phy_ddio_cas_n_hr <= phy_ddio_cas_n;
phy_ddio_we_n_hr <= phy_ddio_we_n;
end
end
endgenerate
wire [MEM_ADDRESS_WIDTH-1:0] phy_ddio_address_l;
wire [MEM_ADDRESS_WIDTH-1:0] phy_ddio_address_h;
wire [MEM_BANK_WIDTH-1:0] phy_ddio_bank_l;
wire [MEM_BANK_WIDTH-1:0] phy_ddio_bank_h;
wire [MEM_CHIP_SELECT_WIDTH-1:0] phy_ddio_cs_n_l;
wire [MEM_CHIP_SELECT_WIDTH-1:0] phy_ddio_cs_n_h;
wire [MEM_CLK_EN_WIDTH-1:0] phy_ddio_cke_l;
wire [MEM_CLK_EN_WIDTH-1:0] phy_ddio_cke_h;
wire [MEM_ODT_WIDTH-1:0] phy_ddio_odt_l;
wire [MEM_ODT_WIDTH-1:0] phy_ddio_odt_h;
wire [MEM_CONTROL_WIDTH-1:0] phy_ddio_ras_n_l;
wire [MEM_CONTROL_WIDTH-1:0] phy_ddio_ras_n_h;
wire [MEM_CONTROL_WIDTH-1:0] phy_ddio_cas_n_l;
wire [MEM_CONTROL_WIDTH-1:0] phy_ddio_cas_n_h;
wire [MEM_CONTROL_WIDTH-1:0] phy_ddio_we_n_l;
wire [MEM_CONTROL_WIDTH-1:0] phy_ddio_we_n_h;
// each signal has a high and a low portion,
// connecting to the high and low inputs of the DDIO_OUT,
// for the purpose of creating double data rate
assign phy_ddio_address_l = phy_ddio_address_hr[MEM_ADDRESS_WIDTH-1:0];
assign phy_ddio_bank_l = phy_ddio_bank_hr[MEM_BANK_WIDTH-1:0];
assign phy_ddio_cke_l = phy_ddio_cke_hr[MEM_CLK_EN_WIDTH-1:0];
assign phy_ddio_odt_l = phy_ddio_odt_hr[MEM_ODT_WIDTH-1:0];
assign phy_ddio_cs_n_l = phy_ddio_cs_n_hr[MEM_CHIP_SELECT_WIDTH-1:0];
assign phy_ddio_we_n_l = phy_ddio_we_n_hr[MEM_CONTROL_WIDTH-1:0];
assign phy_ddio_ras_n_l = phy_ddio_ras_n_hr[MEM_CONTROL_WIDTH-1:0];
assign phy_ddio_cas_n_l = phy_ddio_cas_n_hr[MEM_CONTROL_WIDTH-1:0];
assign phy_ddio_address_h = phy_ddio_address_hr[2*MEM_ADDRESS_WIDTH-1:MEM_ADDRESS_WIDTH];
assign phy_ddio_bank_h = phy_ddio_bank_hr[2*MEM_BANK_WIDTH-1:MEM_BANK_WIDTH];
assign phy_ddio_cke_h = phy_ddio_cke_hr[2*MEM_CLK_EN_WIDTH-1:MEM_CLK_EN_WIDTH];
assign phy_ddio_odt_h = phy_ddio_odt_hr[2*MEM_ODT_WIDTH-1:MEM_ODT_WIDTH];
assign phy_ddio_cs_n_h = phy_ddio_cs_n_hr[2*MEM_CHIP_SELECT_WIDTH-1:MEM_CHIP_SELECT_WIDTH];
assign phy_ddio_we_n_h = phy_ddio_we_n_hr[2*MEM_CONTROL_WIDTH-1:MEM_CONTROL_WIDTH];
assign phy_ddio_ras_n_h = phy_ddio_ras_n_hr[2*MEM_CONTROL_WIDTH-1:MEM_CONTROL_WIDTH];
assign phy_ddio_cas_n_h = phy_ddio_cas_n_hr[2*MEM_CONTROL_WIDTH-1:MEM_CONTROL_WIDTH];
assign address_l = phy_ddio_address_l;
assign address_h = phy_ddio_address_h;
altddio_out uaddress_pad(
.aclr (~reset_n),
.aset (1'b0),
.datain_h (address_l),
.datain_l (address_h),
.dataout (phy_mem_address),
.oe (1'b1),
.outclock (phy_ddio_addr_cmd_clk),
.outclocken (1'b1)
);
defparam
uaddress_pad.extend_oe_disable = "UNUSED",
uaddress_pad.intended_device_family = DEVICE_FAMILY,
uaddress_pad.invert_output = "OFF",
uaddress_pad.lpm_hint = "UNUSED",
uaddress_pad.lpm_type = "altddio_out",
uaddress_pad.oe_reg = "UNUSED",
uaddress_pad.power_up_high = "OFF",
uaddress_pad.width = MEM_ADDRESS_WIDTH;
altddio_out ubank_pad(
.aclr (~reset_n),
.aset (1'b0),
.datain_h (phy_ddio_bank_l),
.datain_l (phy_ddio_bank_h),
.dataout (phy_mem_bank),
.oe (1'b1),
.outclock (phy_ddio_addr_cmd_clk),
.outclocken (1'b1)
);
defparam
ubank_pad.extend_oe_disable = "UNUSED",
ubank_pad.intended_device_family = DEVICE_FAMILY,
ubank_pad.invert_output = "OFF",
ubank_pad.lpm_hint = "UNUSED",
ubank_pad.lpm_type = "altddio_out",
ubank_pad.oe_reg = "UNUSED",
ubank_pad.power_up_high = "OFF",
ubank_pad.width = MEM_BANK_WIDTH;
assign cs_n_l = phy_ddio_cs_n_l;
assign cs_n_h = phy_ddio_cs_n_h;
altddio_out ucs_n_pad(
.aclr (1'b0),
.aset (~reset_n),
.datain_h (cs_n_l),
.datain_l (cs_n_h),
.dataout (phy_mem_cs_n),
.oe (1'b1),
.outclock (phy_ddio_addr_cmd_clk),
.outclocken (1'b1)
);
defparam
ucs_n_pad.extend_oe_disable = "UNUSED",
ucs_n_pad.intended_device_family = DEVICE_FAMILY,
ucs_n_pad.invert_output = "OFF",
ucs_n_pad.lpm_hint = "UNUSED",
ucs_n_pad.lpm_type = "altddio_out",
ucs_n_pad.oe_reg = "UNUSED",
ucs_n_pad.power_up_high = "OFF",
ucs_n_pad.width = MEM_CHIP_SELECT_WIDTH;
assign cke_l = phy_ddio_cke_l;
assign cke_h = phy_ddio_cke_h;
altddio_out ucke_pad(
.aclr (~reset_n),
.aset (1'b0),
.datain_h (cke_l),
.datain_l (cke_h),
.dataout (phy_mem_cke),
.oe (1'b1),
.outclock (phy_ddio_addr_cmd_clk),
.outclocken (1'b1)
);
defparam
ucke_pad.extend_oe_disable = "UNUSED",
ucke_pad.intended_device_family = DEVICE_FAMILY,
ucke_pad.invert_output = "OFF",
ucke_pad.lpm_hint = "UNUSED",
ucke_pad.lpm_type = "altddio_out",
ucke_pad.oe_reg = "UNUSED",
ucke_pad.power_up_high = "OFF",
ucke_pad.width = MEM_CLK_EN_WIDTH;
altddio_out uodt_pad(
.aclr (~reset_n),
.aset (1'b0),
.datain_h (phy_ddio_odt_l),
.datain_l (phy_ddio_odt_h),
.dataout (phy_mem_odt),
.oe (1'b1),
.outclock (phy_ddio_addr_cmd_clk),
.outclocken (1'b1)
);
defparam
uodt_pad.extend_oe_disable = "UNUSED",
uodt_pad.intended_device_family = DEVICE_FAMILY,
uodt_pad.invert_output = "OFF",
uodt_pad.lpm_hint = "UNUSED",
uodt_pad.lpm_type = "altddio_out",
uodt_pad.oe_reg = "UNUSED",
uodt_pad.power_up_high = "OFF",
uodt_pad.width = MEM_ODT_WIDTH;
altddio_out uwe_n_pad(
.aclr (1'b0),
.aset (~reset_n),
.datain_h (phy_ddio_we_n_l),
.datain_l (phy_ddio_we_n_h),
.dataout (phy_mem_we_n),
.oe (1'b1),
.outclock (phy_ddio_addr_cmd_clk),
.outclocken (1'b1)
);
defparam
uwe_n_pad.extend_oe_disable = "UNUSED",
uwe_n_pad.intended_device_family = DEVICE_FAMILY,
uwe_n_pad.invert_output = "OFF",
uwe_n_pad.lpm_hint = "UNUSED",
uwe_n_pad.lpm_type = "altddio_out",
uwe_n_pad.oe_reg = "UNUSED",
uwe_n_pad.power_up_high = "OFF",
uwe_n_pad.width = MEM_CONTROL_WIDTH;
altddio_out uras_n_pad(
.aclr (1'b0),
.aset (~reset_n),
.datain_h (phy_ddio_ras_n_l),
.datain_l (phy_ddio_ras_n_h),
.dataout (phy_mem_ras_n),
.oe (1'b1),
.outclock (phy_ddio_addr_cmd_clk),
.outclocken (1'b1)
);
defparam
uras_n_pad.extend_oe_disable = "UNUSED",
uras_n_pad.intended_device_family = DEVICE_FAMILY,
uras_n_pad.invert_output = "OFF",
uras_n_pad.lpm_hint = "UNUSED",
uras_n_pad.lpm_type = "altddio_out",
uras_n_pad.oe_reg = "UNUSED",
uras_n_pad.power_up_high = "OFF",
uras_n_pad.width = MEM_CONTROL_WIDTH;
altddio_out ucas_n_pad(
.aclr (1'b0),
.aset (~reset_n),
.datain_h (phy_ddio_cas_n_l),
.datain_l (phy_ddio_cas_n_h),
.dataout (phy_mem_cas_n),
.oe (1'b1),
.outclock (phy_ddio_addr_cmd_clk),
.outclocken (1'b1)
);
defparam
ucas_n_pad.extend_oe_disable = "UNUSED",
ucas_n_pad.intended_device_family = DEVICE_FAMILY,
ucas_n_pad.invert_output = "OFF",
ucas_n_pad.lpm_hint = "UNUSED",
ucas_n_pad.lpm_type = "altddio_out",
ucas_n_pad.oe_reg = "UNUSED",
ucas_n_pad.power_up_high = "OFF",
ucas_n_pad.width = MEM_CONTROL_WIDTH;
wire [MEM_CK_WIDTH-1:0] mem_ck_source;
wire [MEM_CK_WIDTH-1:0] mem_ck;
localparam USE_ADDR_CMD_CPS_FOR_MEM_CK = "true";
generate
genvar clock_width;
for (clock_width=0; clock_width<MEM_CK_WIDTH; clock_width=clock_width+1)
begin: clock_gen
assign mem_ck_source[clock_width] = pll_mem_clk;
altddio_out umem_ck_pad(
.aclr (1'b0),
.aset (1'b0),
.datain_h (enable_mem_clk[clock_width]),
.datain_l (1'b0),
.dataout (mem_ck[clock_width]),
.oe (1'b1),
.outclock (mem_ck_source[clock_width]),
.outclocken (1'b1)
);
defparam
umem_ck_pad.extend_oe_disable = "UNUSED",
umem_ck_pad.intended_device_family = DEVICE_FAMILY,
umem_ck_pad.invert_output = "OFF",
umem_ck_pad.lpm_hint = "UNUSED",
umem_ck_pad.lpm_type = "altddio_out",
umem_ck_pad.oe_reg = "UNUSED",
umem_ck_pad.power_up_high = "OFF",
umem_ck_pad.width = 1;
wire mem_ck_temp;
assign mem_ck_temp = mem_ck[clock_width];
DE4_SOPC_ddr2_0_p0_clock_pair_generator uclk_generator(
.datain (mem_ck_temp),
.dataout (phy_mem_ck[clock_width]),
.dataout_b (phy_mem_ck_n[clock_width])
);
end
endgenerate
endmodule
|
// (C) 2001-2012 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1 ps / 1 ps
module DE4_SOPC_ddr2_0_p0_altdqdqs (
core_clock_in,
reset_n_core_clock_in,
fr_clock_in,
hr_clock_in,
write_strobe_clock_in,
strobe_ena_hr_clock_in,
strobe_ena_clock_in,
capture_strobe_ena,
read_write_data_io,
write_oe_in,
strobe_io,
output_strobe_ena,
strobe_n_io,
oct_ena_in,
read_data_out,
capture_strobe_out,
write_data_in,
extra_write_data_in,
extra_write_data_out,
parallelterminationcontrol_in,
seriesterminationcontrol_in,
config_data_in,
config_update,
config_dqs_ena,
config_io_ena,
config_extra_io_ena,
config_dqs_io_ena,
config_clock_in,
dll_delayctrl_in
);
input [6-1:0] dll_delayctrl_in;
input core_clock_in;
input reset_n_core_clock_in;
input fr_clock_in;
input hr_clock_in;
input write_strobe_clock_in;
input strobe_ena_hr_clock_in;
input strobe_ena_clock_in;
input [1-1:0] capture_strobe_ena;
inout [8-1:0] read_write_data_io;
input [2*8-1:0] write_oe_in;
inout strobe_io;
input [2-1:0] output_strobe_ena;
inout strobe_n_io;
input [2-1:0] oct_ena_in;
output [2 * 2 * 8-1:0] read_data_out;
output capture_strobe_out;
input [2 * 2 * 8-1:0] write_data_in;
input [2 * 2 * 1-1:0] extra_write_data_in;
output [1-1:0] extra_write_data_out;
input [14-1:0] parallelterminationcontrol_in;
input [14-1:0] seriesterminationcontrol_in;
input config_data_in;
input config_update;
input config_dqs_ena;
input [8-1:0] config_io_ena;
input [1-1:0] config_extra_io_ena;
input config_dqs_io_ena;
input config_clock_in;
parameter ALTERA_ALTDQ_DQS2_FAST_SIM_MODEL = "";
altdq_dqs2_ddio_3reg_stratixiv altdq_dqs2_inst (
.core_clock_in( core_clock_in),
.reset_n_core_clock_in (reset_n_core_clock_in),
.fr_data_clock_in (),
.fr_strobe_clock_in (),
.fr_clock_in( fr_clock_in),
.hr_clock_in( hr_clock_in),
.dr_clock_in( ),
.write_strobe_clock_in (write_strobe_clock_in),
.strobe_ena_hr_clock_in( strobe_ena_hr_clock_in),
.strobe_ena_clock_in( strobe_ena_clock_in),
.capture_strobe_ena( capture_strobe_ena),
.capture_strobe_tracking (),
.read_write_data_io( read_write_data_io),
.write_oe_in( write_oe_in),
.read_data_in( ),
.write_data_out( ),
.strobe_io( strobe_io),
.output_strobe_ena( output_strobe_ena),
.output_strobe_out(),
.output_strobe_n_out(),
.capture_strobe_in(),
.capture_strobe_n_in(),
.strobe_n_io( strobe_n_io),
.corerankselectwritein(),
.corerankselectreadin(),
.coredqsenabledelayctrlin(),
.coredqsdisablendelayctrlin(),
.coremultirankdelayctrlin(),
.oct_ena_in( oct_ena_in),
.read_data_out( read_data_out),
.capture_strobe_out( capture_strobe_out),
.write_data_in( write_data_in),
.extra_write_data_in( extra_write_data_in),
.extra_write_data_out( extra_write_data_out),
.parallelterminationcontrol_in( parallelterminationcontrol_in),
.seriesterminationcontrol_in( seriesterminationcontrol_in),
.config_data_in( config_data_in),
.config_update( config_update),
.config_dqs_ena( config_dqs_ena),
.config_io_ena( config_io_ena),
.config_extra_io_ena( config_extra_io_ena),
.config_dqs_io_ena( config_dqs_io_ena),
.config_clock_in( config_clock_in),
.dll_offsetdelay_in (),
.lfifo_rden(1'b0),
.vfifo_qvld(1'b0),
.rfifo_reset_n(1'b0),
.dll_delayctrl_in(dll_delayctrl_in)
);
defparam altdq_dqs2_inst.PIN_WIDTH = 8;
defparam altdq_dqs2_inst.PIN_TYPE = "bidir";
defparam altdq_dqs2_inst.USE_INPUT_PHASE_ALIGNMENT = "false";
defparam altdq_dqs2_inst.USE_OUTPUT_PHASE_ALIGNMENT = "false";
defparam altdq_dqs2_inst.USE_LDC_AS_LOW_SKEW_CLOCK = "false";
defparam altdq_dqs2_inst.OUTPUT_DQS_PHASE_SETTING = 0;
defparam altdq_dqs2_inst.OUTPUT_DQ_PHASE_SETTING = 0;
defparam altdq_dqs2_inst.USE_HALF_RATE_INPUT = "false";
defparam altdq_dqs2_inst.USE_HALF_RATE_OUTPUT = "true";
defparam altdq_dqs2_inst.DIFFERENTIAL_CAPTURE_STROBE = "true";
defparam altdq_dqs2_inst.SEPARATE_CAPTURE_STROBE = "false";
defparam altdq_dqs2_inst.INPUT_FREQ = 200.0;
defparam altdq_dqs2_inst.INPUT_FREQ_PS = "5000 ps";
defparam altdq_dqs2_inst.DELAY_CHAIN_BUFFER_MODE = "HIGH";
defparam altdq_dqs2_inst.DQS_PHASE_SETTING = 2;
defparam altdq_dqs2_inst.DQS_PHASE_SHIFT = 7200;
defparam altdq_dqs2_inst.DQS_ENABLE_PHASE_SETTING = 3;
defparam altdq_dqs2_inst.USE_DYNAMIC_CONFIG = "true";
defparam altdq_dqs2_inst.INVERT_CAPTURE_STROBE = "true";
defparam altdq_dqs2_inst.SWAP_CAPTURE_STROBE_POLARITY = "false";
defparam altdq_dqs2_inst.EXTRA_OUTPUTS_USE_SEPARATE_GROUP = "false";
defparam altdq_dqs2_inst.USE_TERMINATION_CONTROL = "true";
defparam altdq_dqs2_inst.USE_DQS_ENABLE = "true";
defparam altdq_dqs2_inst.USE_OUTPUT_STROBE = "true";
defparam altdq_dqs2_inst.USE_OUTPUT_STROBE_RESET = "false";
defparam altdq_dqs2_inst.DIFFERENTIAL_OUTPUT_STROBE = "true";
defparam altdq_dqs2_inst.USE_BIDIR_STROBE = "true";
defparam altdq_dqs2_inst.REVERSE_READ_WORDS = "false";
defparam altdq_dqs2_inst.EXTRA_OUTPUT_WIDTH = 1;
defparam altdq_dqs2_inst.DYNAMIC_MODE = "dynamic";
defparam altdq_dqs2_inst.OCT_SERIES_TERM_CONTROL_WIDTH = 14;
defparam altdq_dqs2_inst.OCT_PARALLEL_TERM_CONTROL_WIDTH = 14;
defparam altdq_dqs2_inst.DLL_WIDTH = 6;
defparam altdq_dqs2_inst.USE_DATA_OE_FOR_OCT = "false";
defparam altdq_dqs2_inst.DQS_ENABLE_WIDTH = 1;
defparam altdq_dqs2_inst.USE_OCT_ENA_IN_FOR_OCT = "true";
defparam altdq_dqs2_inst.PREAMBLE_TYPE = "low";
defparam altdq_dqs2_inst.USE_OFFSET_CTRL = "false";
defparam altdq_dqs2_inst.HR_DDIO_OUT_HAS_THREE_REGS = "true";
defparam altdq_dqs2_inst.DQS_ENABLE_PHASECTRL = "true";
defparam altdq_dqs2_inst.USE_2X_FF = "false";
defparam altdq_dqs2_inst.DLL_USE_2X_CLK = "false";
defparam altdq_dqs2_inst.USE_DQS_TRACKING = "false";
defparam altdq_dqs2_inst.USE_HARD_FIFOS = "false";
defparam altdq_dqs2_inst.CALIBRATION_SUPPORT = "false";
defparam altdq_dqs2_inst.DQS_ENABLE_AFTER_T7 = "true";
defparam altdq_dqs2_inst.DELAY_CHAIN_WIDTH = 4;
endmodule
|
//altiobuf_out CBX_AUTO_BLACKBOX="ALL" CBX_SINGLE_OUTPUT_FILE="ON" DEVICE_FAMILY="Stratix IV" ENABLE_BUS_HOLD="FALSE" NUMBER_OF_CHANNELS=1 OPEN_DRAIN_OUTPUT="FALSE" PSEUDO_DIFFERENTIAL_MODE="TRUE" USE_DIFFERENTIAL_MODE="TRUE" USE_OE="FALSE" USE_OUT_DYNAMIC_DELAY_CHAIN1="FALSE" USE_OUT_DYNAMIC_DELAY_CHAIN2="FALSE" USE_TERMINATION_CONTROL="FALSE" datain dataout dataout_b
//VERSION_BEGIN 12.1 cbx_altiobuf_out 2012:11:07:18:03:20:SJ cbx_mgl 2012:11:07:18:50:05:SJ cbx_stratixiii 2012:11:07:18:03:20:SJ cbx_stratixv 2012:11:07:18:03:20:SJ VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
// Copyright (C) 1991-2012 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, Altera MegaCore Function License
// Agreement, or other applicable license agreement, including,
// without limitation, that your use is for the sole purpose of
// programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the
// applicable agreement for further details.
//synthesis_resources = stratixiv_io_obuf 2 stratixiv_pseudo_diff_out 1
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module DE4_SOPC_ddr2_0_p0_clock_pair_generator
(
datain,
dataout,
dataout_b) /* synthesis synthesis_clearbox=1 */;
input [0:0] datain;
output [0:0] dataout;
output [0:0] dataout_b;
wire [0:0] wire_obuf_ba_o;
wire [0:0] wire_obufa_o;
wire [0:0] wire_pseudo_diffa_o;
wire [0:0] wire_pseudo_diffa_obar;
wire [0:0] oe_b;
wire [0:0] oe_w;
stratixiv_io_obuf obuf_ba_0
(
.i(wire_pseudo_diffa_obar),
.o(wire_obuf_ba_o[0:0]),
.obar(),
.oe(oe_b)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.dynamicterminationcontrol(1'b0),
.parallelterminationcontrol({14{1'b0}}),
.seriesterminationcontrol({14{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devoe(1'b1)
// synopsys translate_on
);
defparam
obuf_ba_0.bus_hold = "false",
obuf_ba_0.open_drain_output = "false",
obuf_ba_0.lpm_type = "stratixiv_io_obuf";
stratixiv_io_obuf obufa_0
(
.i(wire_pseudo_diffa_o),
.o(wire_obufa_o[0:0]),
.obar(),
.oe(oe_w)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.dynamicterminationcontrol(1'b0),
.parallelterminationcontrol({14{1'b0}}),
.seriesterminationcontrol({14{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devoe(1'b1)
// synopsys translate_on
);
defparam
obufa_0.bus_hold = "false",
obufa_0.open_drain_output = "false",
obufa_0.shift_series_termination_control = "false",
obufa_0.lpm_type = "stratixiv_io_obuf";
stratixiv_pseudo_diff_out pseudo_diffa_0
(
.i(datain),
.o(wire_pseudo_diffa_o[0:0]),
.obar(wire_pseudo_diffa_obar[0:0]));
assign
dataout = wire_obufa_o,
dataout_b = wire_obuf_ba_o,
oe_b = 1'b1,
oe_w = 1'b1;
endmodule //DE4_SOPC_ddr2_0_p0_clock_pair_generator
//VALID FILE
|
// (C) 2001-2012 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1 ps / 1 ps
(* altera_attribute = "-name ALLOW_SYNCH_CTRL_USAGE ON;-name AUTO_CLOCK_ENABLE_RECOGNITION ON" *)
module DE4_SOPC_ddr2_0_p0_flop_mem(
wr_reset_n,
wr_clk,
wr_en,
wr_addr,
wr_data,
rd_reset_n,
rd_clk,
rd_en,
rd_addr,
rd_data
);
parameter WRITE_MEM_DEPTH = "";
parameter WRITE_ADDR_WIDTH = "";
parameter WRITE_DATA_WIDTH = "";
parameter READ_MEM_DEPTH = "";
parameter READ_ADDR_WIDTH = "";
parameter READ_DATA_WIDTH = "";
input wr_reset_n;
input wr_clk;
input wr_en;
input [WRITE_ADDR_WIDTH-1:0] wr_addr;
input [WRITE_DATA_WIDTH-1:0] wr_data;
input rd_reset_n;
input rd_clk;
input rd_en;
input [READ_ADDR_WIDTH-1:0] rd_addr;
output [READ_DATA_WIDTH-1:0] rd_data;
wire [WRITE_DATA_WIDTH*WRITE_MEM_DEPTH-1:0] all_data;
wire [READ_DATA_WIDTH-1:0] mux_data_out;
// declare a memory with WRITE_MEM_DEPTH entries
// each entry contains a data size of WRITE_DATA_WIDTH
reg [WRITE_DATA_WIDTH-1:0] data_stored [0:WRITE_MEM_DEPTH-1] /* synthesis syn_preserve = 1 */;
reg [READ_DATA_WIDTH-1:0] rd_data;
generate
genvar entry;
for (entry=0; entry < WRITE_MEM_DEPTH; entry=entry+1)
begin: mem_location
assign all_data[(WRITE_DATA_WIDTH*(entry+1)-1) : (WRITE_DATA_WIDTH*entry)] = data_stored[entry];
always @(posedge wr_clk or negedge wr_reset_n)
begin
if (~wr_reset_n) begin
data_stored[entry] <= {WRITE_DATA_WIDTH{1'b0}};
end else begin
if (wr_en) begin
if (entry == wr_addr) begin
data_stored[entry] <= wr_data;
end
end
end
end
end
endgenerate
// mux to select the correct output data based on read address
lpm_mux uread_mux(
.sel (rd_addr),
.data (all_data),
.result (mux_data_out)
// synopsys translate_off
,
.aclr (),
.clken (),
.clock ()
// synopsys translate_on
);
defparam uread_mux.lpm_size = READ_MEM_DEPTH;
defparam uread_mux.lpm_type = "LPM_MUX";
defparam uread_mux.lpm_width = READ_DATA_WIDTH;
defparam uread_mux.lpm_widths = READ_ADDR_WIDTH;
always @(posedge rd_clk or negedge rd_reset_n)
begin
if (~rd_reset_n) begin
rd_data <= {READ_DATA_WIDTH{1'b0}};
end else begin
rd_data <= mux_data_out;
end
end
endmodule
|
// (C) 2001-2012 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1 ps / 1 ps
module DE4_SOPC_ddr2_0_p0_fr_cycle_extender(
clk,
reset_n,
extend_by,
datain,
dataout
);
// ********************************************************************************************************************************
// BEGIN PARAMETER SECTION
// All parameters default to "" will have their values passed in from higher level wrapper with the controller and driver
parameter DATA_WIDTH = "";
parameter REG_POST_RESET_HIGH = "false";
localparam RATE_MULT = 2;
localparam REG_STAGES = 2;
localparam FULL_DATA_WIDTH = DATA_WIDTH*RATE_MULT;
// END PARAMETER SECTION
// ********************************************************************************************************************************
input clk;
input reset_n;
input [1:0] extend_by;
input [FULL_DATA_WIDTH-1:0] datain;
output [FULL_DATA_WIDTH-1:0] dataout;
reg [FULL_DATA_WIDTH-1:0] datain_r [REG_STAGES-1:0] /* synthesis dont_merge */;
generate
genvar stage;
for (stage = 0; stage < REG_STAGES; stage = stage + 1)
begin : stage_gen
always @(posedge clk or negedge reset_n)
begin
if (~reset_n)
if (REG_POST_RESET_HIGH == "true")
datain_r[stage] <= {FULL_DATA_WIDTH{1'b1}};
else
datain_r[stage] <= {FULL_DATA_WIDTH{1'b0}};
else
datain_r[stage] <= (stage == 0) ? datain : datain_r[stage-1];
end
end
endgenerate
wire [DATA_WIDTH-1:0] datain_t0 = datain[(DATA_WIDTH*1)-1:(DATA_WIDTH*0)];
wire [DATA_WIDTH-1:0] datain_t1 = datain[(DATA_WIDTH*2)-1:(DATA_WIDTH*1)];
wire [DATA_WIDTH-1:0] datain_r_t0 = datain_r[0][(DATA_WIDTH*1)-1:(DATA_WIDTH*0)];
wire [DATA_WIDTH-1:0] datain_r_t1 = datain_r[0][(DATA_WIDTH*2)-1:(DATA_WIDTH*1)];
wire [DATA_WIDTH-1:0] datain_rr_t1 = datain_r[1][(DATA_WIDTH*2)-1:(DATA_WIDTH*1)];
assign dataout = (extend_by == 2'b01) ? {datain_t1 | datain_t0,
datain_t0 | datain_r_t1} : (
(extend_by == 2'b10) ? {datain_t1 | datain_t0 | datain_r_t1,
datain_t0 | datain_r_t1 | datain_r_t0} : (
(extend_by == 2'b11) ? {datain_t1 | datain_t0 | datain_r_t1 | datain_r_t0,
datain_t0 | datain_r_t1 | datain_r_t0 | datain_rr_t1} : (
{datain_t1, datain_t0} )));
endmodule
|
// (C) 2001-2012 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// ********************************************************************************************************************************
// File name: fr_cycle_shifter.v
//
// The fr-cycle shifter shifts the input data by X number of full-rate-cycles, where X is specified by the shift_by port.
// datain is a bus that combines data of multiple full rate cycles, in specific time order. For example,
// in a quarter-rate system, the datain bus must be ordered as {T3, T2, T1, T0}, where Ty represents the y'th fr-cycle
// data item, of width DATA_WIDTH. The following illustrates outputs at the dataout port for various values of shift_by.
// "__" means don't-care.
//
// shift_by dataout in current cycle dataout in next clock cycle
// 00 {T3, T2, T1, T0} {__, __, __, __}
// 01 {T2, T1, T0, __} {__, __, __, T3}
// 10 {T1, T0, __, __} {__, __, T3, T2}
// 11 {T0, __, __, __} {__, T3, T2, T1}
//
// In full-rate or half-rate systems, only the least-significant bit of shift-by has an effect
// (i.e. you can only shift by 0 or 1 fr-cycle).
// In quarter-rate systems, all bits of shift_by are used (i.e. you can shift by 0, 1, 2, or 3 fr-cycles).
//
// ********************************************************************************************************************************
`timescale 1 ps / 1 ps
module DE4_SOPC_ddr2_0_p0_fr_cycle_shifter(
clk,
reset_n,
shift_by,
datain,
dataout
);
// ********************************************************************************************************************************
// BEGIN PARAMETER SECTION
// All parameters default to "" will have their values passed in from higher level wrapper with the controller and driver
parameter DATA_WIDTH = "";
parameter REG_POST_RESET_HIGH = "false";
localparam RATE_MULT = 2;
localparam FULL_DATA_WIDTH = DATA_WIDTH*RATE_MULT;
// END PARAMETER SECTION
// ********************************************************************************************************************************
input clk;
input reset_n;
input [1:0] shift_by;
input [FULL_DATA_WIDTH-1:0] datain;
output [FULL_DATA_WIDTH-1:0] dataout;
reg [FULL_DATA_WIDTH-1:0] datain_r;
always @(posedge clk or negedge reset_n)
begin
if (~reset_n) begin
if (REG_POST_RESET_HIGH == "true")
datain_r <= {FULL_DATA_WIDTH{1'b1}};
else
datain_r <= {FULL_DATA_WIDTH{1'b0}};
end else begin
datain_r <= datain;
end
end
wire [FULL_DATA_WIDTH-1:0] dataout_pre;
wire [DATA_WIDTH-1:0] datain_t0 = datain[(DATA_WIDTH*1)-1:(DATA_WIDTH*0)];
wire [DATA_WIDTH-1:0] datain_t1 = datain[(DATA_WIDTH*2)-1:(DATA_WIDTH*1)];
wire [DATA_WIDTH-1:0] datain_r_t1 = datain_r[(DATA_WIDTH*2)-1:(DATA_WIDTH*1)];
assign dataout = (shift_by[0] == 1'b1) ? {datain_t0, datain_r_t1} : {datain_t1, datain_t0};
endmodule
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module DE4_SOPC_ddr2_0_p0_hr_to_fr(
clk,
d_h0,
d_h1,
d_l0,
d_l1,
q0,
q1
);
input clk;
input d_h0;
input d_h1;
input d_l0;
input d_l1;
output q0;
output q1;
reg q_h0;
reg q_h1;
reg q_l0;
reg q_l1;
reg q_l0_neg;
reg q_l1_neg;
always @(posedge clk)
begin
q_h0 <= d_h0;
q_l0 <= d_l0;
q_h1 <= d_h1;
q_l1 <= d_l1;
end
always @(negedge clk)
begin
q_l0_neg <= q_l0;
q_l1_neg <= q_l1;
end
assign q0 = clk ? q_l0_neg : q_h0;
assign q1 = clk ? q_l1_neg : q_h1;
endmodule
|
// (C) 2001-2012 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1 ps / 1 ps
module DE4_SOPC_ddr2_0_p0_iss_probe (
probe_input
);
parameter WIDTH = 1;
parameter ID_NAME = "PROB";
input [WIDTH-1:0] probe_input;
altsource_probe iss_probe_inst (
.probe (probe_input),
.source ()
// synopsys translate_off
,
.clrn (),
.ena (),
.ir_in (),
.ir_out (),
.jtag_state_cdr (),
.jtag_state_cir (),
.jtag_state_e1dr (),
.jtag_state_sdr (),
.jtag_state_tlr (),
.jtag_state_udr (),
.jtag_state_uir (),
.raw_tck (),
.source_clk (),
.source_ena (),
.tdi (),
.tdo (),
.usr1 ()
// synopsys translate_on
);
defparam
iss_probe_inst.enable_metastability = "NO",
iss_probe_inst.instance_id = ID_NAME,
iss_probe_inst.probe_width = WIDTH,
iss_probe_inst.sld_auto_instance_index = "YES",
iss_probe_inst.sld_instance_index = 0,
iss_probe_inst.source_initial_value = "0",
iss_probe_inst.source_width = 0;
endmodule
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// ********************************************************************************************************************************
// File name: memphy.v
// This file instantiates all the main components of the PHY.
// ********************************************************************************************************************************
module DE4_SOPC_ddr2_0_p0_memphy(
global_reset_n,
soft_reset_n,
reset_request_n,
ctl_reset_n,
pll_locked,
oct_ctl_rs_value,
oct_ctl_rt_value,
afi_addr,
afi_cke,
afi_cs_n,
afi_ba,
afi_cas_n,
afi_odt,
afi_ras_n,
afi_we_n,
afi_mem_clk_disable,
afi_dqs_burst,
afi_wlat,
afi_rlat,
afi_wdata,
afi_wdata_valid,
afi_dm,
afi_rdata,
afi_rdata_en,
afi_rdata_en_full,
afi_rdata_valid,
afi_cal_debug_info,
afi_ctl_refresh_done,
afi_ctl_long_idle,
afi_seq_busy,
afi_cal_success,
afi_cal_fail,
mem_a,
mem_ba,
mem_ck,
mem_ck_n,
mem_cke,
mem_cs_n,
mem_dm,
mem_odt,
mem_ras_n,
mem_cas_n,
mem_we_n,
mem_dq,
mem_dqs,
mem_dqs_n,
reset_n_scc_clk,
reset_n_avl_clk,
scc_data,
scc_dqs_ena,
scc_dqs_io_ena,
scc_dq_ena,
scc_dm_ena,
scc_upd,
capture_strobe_tracking,
phy_clk,
phy_reset_n,
phy_read_latency_counter,
phy_afi_wlat,
phy_afi_rlat,
phy_num_write_fr_cycle_shifts,
phy_read_increment_vfifo_fr,
phy_read_increment_vfifo_hr,
phy_read_increment_vfifo_qr,
phy_reset_mem_stable,
phy_cal_debug_info,
phy_read_fifo_reset,
phy_vfifo_rd_en_override,
phy_read_fifo_q,
calib_skip_steps,
pll_afi_clk,
pll_afi_half_clk,
pll_addr_cmd_clk,
pll_mem_clk,
pll_write_clk,
pll_write_clk_pre_phy_clk,
pll_dqs_ena_clk,
seq_clk,
pll_avl_clk,
pll_config_clk,
dll_clk,
dll_phy_delayctrl
);
// ********************************************************************************************************************************
// BEGIN PARAMETER SECTION
// All parameters default to "" will have their values passed in from higher level wrapper with the controller and driver
parameter DEVICE_FAMILY = "";
// On-chip termination
parameter OCT_SERIES_TERM_CONTROL_WIDTH = "";
parameter OCT_PARALLEL_TERM_CONTROL_WIDTH = "";
// PHY-Memory Interface
// Memory device specific parameters, they are set according to the memory spec
parameter MEM_ADDRESS_WIDTH = "";
parameter MEM_BANK_WIDTH = "";
parameter MEM_CLK_EN_WIDTH = "";
parameter MEM_CK_WIDTH = "";
parameter MEM_ODT_WIDTH = "";
parameter MEM_DQS_WIDTH = "";
parameter MEM_CHIP_SELECT_WIDTH = "";
parameter MEM_CONTROL_WIDTH = "";
parameter MEM_DM_WIDTH = "";
parameter MEM_DQ_WIDTH = "";
parameter MEM_READ_DQS_WIDTH = "";
parameter MEM_WRITE_DQS_WIDTH = "";
// PHY-Controller (AFI) Interface
// The AFI interface widths are derived from the memory interface widths based on full/half rate operations
// The calculations are done on higher level wrapper
parameter AFI_ADDRESS_WIDTH = "";
parameter AFI_DEBUG_INFO_WIDTH = "";
parameter AFI_BANK_WIDTH = "";
parameter AFI_CHIP_SELECT_WIDTH = "";
parameter AFI_CLK_EN_WIDTH = "";
parameter AFI_ODT_WIDTH = "";
parameter AFI_MAX_WRITE_LATENCY_COUNT_WIDTH = "";
parameter AFI_MAX_READ_LATENCY_COUNT_WIDTH = "";
parameter AFI_DATA_MASK_WIDTH = "";
parameter AFI_CONTROL_WIDTH = "";
parameter AFI_DATA_WIDTH = "";
parameter AFI_DQS_WIDTH = "";
parameter AFI_RATE_RATIO = "";
// DLL Interface
// The DLL delay output control is always 6 bits for current existing devices
parameter DLL_DELAY_CTRL_WIDTH = "";
// Read Datapath parameters for timing purposes
parameter NUM_SUBGROUP_PER_READ_DQS = "";
parameter QVLD_EXTRA_FLOP_STAGES = "";
parameter QVLD_WR_ADDRESS_OFFSET = "";
// Read Datapath parameters, the values should not be changed unless the intention is to change the architecture
parameter READ_VALID_FIFO_SIZE = "";
parameter READ_FIFO_SIZE = "";
// Latency calibration parameters
parameter MAX_LATENCY_COUNT_WIDTH = "";
parameter MAX_READ_LATENCY = "";
// Write Datapath
// The sequencer uses this value to control write latency during calibration
parameter MAX_WRITE_LATENCY_COUNT_WIDTH = "";
parameter NUM_WRITE_PATH_FLOP_STAGES = "";
parameter NUM_WRITE_FR_CYCLE_SHIFTS = "";
// Add register stage between core and periphery for C2P transfers
parameter REGISTER_C2P = "";
// Address/Command Datapath
parameter NUM_AC_FR_CYCLE_SHIFTS = "";
parameter MEM_T_RL = "";
parameter MR1_ODS = "";
parameter MR1_RTT = "";
parameter ALTDQDQS_INPUT_FREQ = "";
parameter ALTDQDQS_DELAY_CHAIN_BUFFER_MODE = "";
parameter ALTDQDQS_DQS_PHASE_SETTING = "";
parameter ALTDQDQS_DQS_PHASE_SHIFT = "";
parameter ALTDQDQS_DELAYED_CLOCK_PHASE_SETTING = "";
parameter TB_PROTOCOL = "";
parameter TB_MEM_CLK_FREQ = "";
parameter TB_RATE = "";
parameter TB_MEM_DQ_WIDTH = "";
parameter TB_MEM_DQS_WIDTH = "";
parameter TB_PLL_DLL_MASTER = "";
parameter FAST_SIM_MODEL = "";
parameter FAST_SIM_CALIBRATION = "";
// Local parameters
localparam DOUBLE_MEM_DQ_WIDTH = MEM_DQ_WIDTH * 2;
localparam HALF_AFI_DATA_WIDTH = AFI_DATA_WIDTH / 2;
// Width of the calibration status register used to control calibration skipping.
parameter CALIB_REG_WIDTH = "";
// The number of AFI Resets to generate
localparam NUM_AFI_RESET = 4;
// Read valid predication parameters
localparam READ_VALID_FIFO_WRITE_MEM_DEPTH = READ_VALID_FIFO_SIZE / 2; // write operates on half rate clock
localparam READ_VALID_FIFO_READ_MEM_DEPTH = READ_VALID_FIFO_SIZE; // valid-read-prediction operates on full rate clock
localparam READ_VALID_FIFO_PER_DQS_WIDTH = 1; // valid fifo output is a full-rate signal
localparam READ_VALID_FIFO_WIDTH = READ_VALID_FIFO_PER_DQS_WIDTH * MEM_READ_DQS_WIDTH;
localparam READ_VALID_FIFO_WRITE_ADDR_WIDTH = ceil_log2(READ_VALID_FIFO_WRITE_MEM_DEPTH);
localparam READ_VALID_FIFO_READ_ADDR_WIDTH = ceil_log2(READ_VALID_FIFO_READ_MEM_DEPTH);
// Data resynchronization FIFO
localparam READ_FIFO_WRITE_MEM_DEPTH = READ_FIFO_SIZE / 2; // data is written on half rate clock
localparam READ_FIFO_READ_MEM_DEPTH = READ_FIFO_SIZE / 2; // data is read out on half rate clock
localparam READ_FIFO_WRITE_ADDR_WIDTH = ceil_log2(READ_FIFO_WRITE_MEM_DEPTH);
localparam READ_FIFO_READ_ADDR_WIDTH = ceil_log2(READ_FIFO_READ_MEM_DEPTH);
// Sequencer parameters
localparam SEQ_ADDRESS_WIDTH = AFI_ADDRESS_WIDTH;
localparam SEQ_BANK_WIDTH = AFI_BANK_WIDTH;
localparam SEQ_CHIP_SELECT_WIDTH = AFI_CHIP_SELECT_WIDTH;
localparam SEQ_CLK_EN_WIDTH = AFI_CLK_EN_WIDTH;
localparam SEQ_ODT_WIDTH = AFI_ODT_WIDTH;
localparam SEQ_DATA_MASK_WIDTH = AFI_DATA_MASK_WIDTH;
localparam SEQ_CONTROL_WIDTH = AFI_CONTROL_WIDTH;
localparam SEQ_DATA_WIDTH = AFI_DATA_WIDTH;
localparam SEQ_DQS_WIDTH = AFI_DQS_WIDTH;
localparam MAX_LATENCY_COUNT_WIDTH_SAFE = (MAX_LATENCY_COUNT_WIDTH < 5)? 5 : MAX_LATENCY_COUNT_WIDTH;
// END PARAMETER SECTION
// ********************************************************************************************************************************
// ********************************************************************************************************************************
// BEGIN PORT SECTION
// Reset Interface
input global_reset_n; // Resets (active-low) the whole system (all PHY logic + PLL)
input soft_reset_n; // Resets (active-low) PHY logic only, PLL is NOT reset
input pll_locked; // Indicates that PLL is locked
output reset_request_n; // When 1, PLL is out of lock
output ctl_reset_n; // Asynchronously asserted and synchronously de-asserted on afi_clk domain
input [OCT_SERIES_TERM_CONTROL_WIDTH-1:0] oct_ctl_rs_value;
input [OCT_PARALLEL_TERM_CONTROL_WIDTH-1:0] oct_ctl_rt_value;
// PHY-Controller Interface, AFI 2.0
// Control Interface
input [AFI_ADDRESS_WIDTH-1:0] afi_addr; // address
input [AFI_CLK_EN_WIDTH-1:0] afi_cke;
input [AFI_CHIP_SELECT_WIDTH-1:0] afi_cs_n;
input [AFI_BANK_WIDTH-1:0] afi_ba;
input [AFI_CONTROL_WIDTH-1:0] afi_cas_n;
input [AFI_ODT_WIDTH-1:0] afi_odt;
input [AFI_CONTROL_WIDTH-1:0] afi_ras_n;
input [AFI_CONTROL_WIDTH-1:0] afi_we_n;
input [MEM_CK_WIDTH-1:0] afi_mem_clk_disable;
input [AFI_DQS_WIDTH-1:0] afi_dqs_burst;
output [AFI_MAX_WRITE_LATENCY_COUNT_WIDTH-1:0] afi_wlat;
output [AFI_MAX_READ_LATENCY_COUNT_WIDTH-1:0] afi_rlat;
// Write data interface
input [AFI_DATA_WIDTH-1:0] afi_wdata; // write data
input [AFI_DQS_WIDTH-1:0] afi_wdata_valid; // write data valid, used to maintain write latency required by protocol spec
input [AFI_DATA_MASK_WIDTH-1:0] afi_dm; // write data mask
// Read data interface
output [AFI_DATA_WIDTH-1:0] afi_rdata; // read data
input [AFI_RATE_RATIO-1:0] afi_rdata_en; // read enable, used to maintain the read latency calibrated by PHY
input [AFI_RATE_RATIO-1:0] afi_rdata_en_full; // read enable full burst, used to create DQS enable
output [AFI_RATE_RATIO-1:0] afi_rdata_valid; // read data valid
// Status interface
input afi_cal_success; // calibration success
input afi_cal_fail; // calibration failure
output [AFI_DEBUG_INFO_WIDTH - 1:0] afi_cal_debug_info;
input [MEM_CHIP_SELECT_WIDTH-1:0] afi_ctl_refresh_done;
input [MEM_CHIP_SELECT_WIDTH-1:0] afi_ctl_long_idle;
output [MEM_CHIP_SELECT_WIDTH-1:0] afi_seq_busy;
// PHY-Memory Interface
output [MEM_ADDRESS_WIDTH-1:0] mem_a;
output [MEM_BANK_WIDTH-1:0] mem_ba;
output [MEM_CK_WIDTH-1:0] mem_ck;
output [MEM_CK_WIDTH-1:0] mem_ck_n;
output [MEM_CLK_EN_WIDTH-1:0] mem_cke;
output [MEM_CHIP_SELECT_WIDTH-1:0] mem_cs_n;
output [MEM_DM_WIDTH-1:0] mem_dm;
output [MEM_ODT_WIDTH-1:0] mem_odt;
output [MEM_CONTROL_WIDTH-1:0] mem_ras_n;
output [MEM_CONTROL_WIDTH-1:0] mem_cas_n;
output [MEM_CONTROL_WIDTH-1:0] mem_we_n;
inout [MEM_DQ_WIDTH-1:0] mem_dq;
inout [MEM_DQS_WIDTH-1:0] mem_dqs;
inout [MEM_DQS_WIDTH-1:0] mem_dqs_n;
output reset_n_scc_clk;
output reset_n_avl_clk;
input scc_data;
input [MEM_READ_DQS_WIDTH-1:0] scc_dqs_ena;
input [MEM_READ_DQS_WIDTH-1:0] scc_dqs_io_ena;
input [MEM_DQ_WIDTH-1:0] scc_dq_ena;
input [MEM_DM_WIDTH-1:0] scc_dm_ena;
input scc_upd;
output [MEM_READ_DQS_WIDTH-1:0] capture_strobe_tracking;
output phy_clk;
output phy_reset_n;
input [MAX_LATENCY_COUNT_WIDTH-1:0] phy_read_latency_counter;
input [AFI_MAX_WRITE_LATENCY_COUNT_WIDTH-1:0] phy_afi_wlat;
input [AFI_MAX_READ_LATENCY_COUNT_WIDTH-1:0] phy_afi_rlat;
input [MEM_WRITE_DQS_WIDTH*2-1:0] phy_num_write_fr_cycle_shifts;
input [MEM_READ_DQS_WIDTH-1:0] phy_read_increment_vfifo_fr;
input [MEM_READ_DQS_WIDTH-1:0] phy_read_increment_vfifo_hr;
input [MEM_READ_DQS_WIDTH-1:0] phy_read_increment_vfifo_qr;
input phy_reset_mem_stable;
input [AFI_DEBUG_INFO_WIDTH - 1:0] phy_cal_debug_info;
input [MEM_READ_DQS_WIDTH-1:0] phy_read_fifo_reset;
input [MEM_READ_DQS_WIDTH-1:0] phy_vfifo_rd_en_override;
output [AFI_DATA_WIDTH-1:0] phy_read_fifo_q;
output [CALIB_REG_WIDTH-1:0] calib_skip_steps;
// PLL Interface
input pll_afi_clk; // clocks AFI interface logic
input pll_afi_half_clk; //
input pll_addr_cmd_clk; // clocks address/command DDIO
input pll_mem_clk; // output clock to memory
input pll_write_clk; // clocks write data DDIO
input pll_write_clk_pre_phy_clk;
input pll_dqs_ena_clk;
input seq_clk;
input pll_avl_clk;
input pll_config_clk;
// DLL Interface
output dll_clk;
input [DLL_DELAY_CTRL_WIDTH-1:0] dll_phy_delayctrl; // dll output used to control the input DQS phase shift
// END PARAMETER SECTION
// ********************************************************************************************************************************
wire [AFI_ADDRESS_WIDTH-1:0] phy_ddio_address;
wire [AFI_BANK_WIDTH-1:0] phy_ddio_bank;
wire [AFI_CHIP_SELECT_WIDTH-1:0] phy_ddio_cs_n;
wire [AFI_CLK_EN_WIDTH-1:0] phy_ddio_cke;
wire [AFI_ODT_WIDTH-1:0] phy_ddio_odt;
wire [AFI_CONTROL_WIDTH-1:0] phy_ddio_ras_n;
wire [AFI_CONTROL_WIDTH-1:0] phy_ddio_cas_n;
wire [AFI_CONTROL_WIDTH-1:0] phy_ddio_we_n;
wire [AFI_DATA_WIDTH-1:0] phy_ddio_dq;
wire [AFI_DQS_WIDTH-1:0] phy_ddio_dqs_en;
wire [AFI_DQS_WIDTH-1:0] phy_ddio_oct_ena;
wire [AFI_DQS_WIDTH-1:0] phy_ddio_wrdata_en;
wire [AFI_DATA_MASK_WIDTH-1:0] phy_ddio_wrdata_mask;
localparam DDIO_PHY_DQ_WIDTH = DOUBLE_MEM_DQ_WIDTH;
wire [DDIO_PHY_DQ_WIDTH-1:0] ddio_phy_dq;
wire [MEM_READ_DQS_WIDTH-1:0] read_capture_clk;
wire [AFI_DATA_WIDTH-1:0] afi_rdata;
wire [AFI_RATE_RATIO-1:0] afi_rdata_valid;
wire [SEQ_ADDRESS_WIDTH-1:0] seq_mux_address;
wire [SEQ_BANK_WIDTH-1:0] seq_mux_bank;
wire [SEQ_CHIP_SELECT_WIDTH-1:0] seq_mux_cs_n;
wire [SEQ_CLK_EN_WIDTH-1:0] seq_mux_cke;
wire [SEQ_ODT_WIDTH-1:0] seq_mux_odt;
wire [SEQ_CONTROL_WIDTH-1:0] seq_mux_ras_n;
wire [SEQ_CONTROL_WIDTH-1:0] seq_mux_cas_n;
wire [SEQ_CONTROL_WIDTH-1:0] seq_mux_we_n;
wire [SEQ_DQS_WIDTH-1:0] seq_mux_dqs_en;
wire [SEQ_DATA_WIDTH-1:0] seq_mux_wdata;
wire [SEQ_DQS_WIDTH-1:0] seq_mux_wdata_valid;
wire [SEQ_DATA_MASK_WIDTH-1:0] seq_mux_dm;
wire seq_mux_rdata_en;
wire [SEQ_DATA_WIDTH-1:0] mux_seq_rdata;
wire mux_seq_rdata_valid;
wire mux_sel;
wire [NUM_AFI_RESET-1:0] reset_n_afi_clk;
wire reset_n_addr_cmd_clk;
wire reset_n_seq_clk;
wire reset_n_resync_clk;
wire [READ_VALID_FIFO_WIDTH-1:0] dqs_enable_ctrl;
wire [AFI_DQS_WIDTH-1:0] force_oct_off;
wire reset_n_scc_clk;
wire reset_n_avl_clk;
wire csr_soft_reset_req;
wire [MEM_READ_DQS_WIDTH-1:0] dqs_edge_detect;
wire [MEM_CK_WIDTH-1:0] afi_mem_clk_disable;
localparam SKIP_CALIBRATION_STEPS = 7'b1111111;
localparam CALIBRATION_STEPS = SKIP_CALIBRATION_STEPS;
localparam SKIP_MEM_INIT = (FAST_SIM_MODEL ? 1'b1 : 1'b0);
localparam SEQ_CALIB_INIT = {CALIBRATION_STEPS, SKIP_MEM_INIT};
reg [CALIB_REG_WIDTH-1:0] seq_calib_init_reg /* synthesis syn_noprune syn_preserve = 1 */;
// Initialization of the sequencer status register. This register
// is preserved in the netlist so that it can be forced during simulation
always @(posedge pll_afi_clk)
`ifndef SYNTH_FOR_SIM
//synthesis translate_off
`endif
seq_calib_init_reg <= SEQ_CALIB_INIT;
`ifndef SYNTH_FOR_SIM
//synthesis translate_on
//synthesis read_comments_as_HDL on
`endif
// seq_calib_init_reg <= {CALIB_REG_WIDTH{1'b0}};
`ifndef SYNTH_FOR_SIM
// synthesis read_comments_as_HDL off
`endif
// ********************************************************************************************************************************
// The reset scheme used in the UNIPHY is asynchronous assert and synchronous de-assert
// The reset block has 2 main functionalities:
// 1. Keep all the PHY logic in reset state until after the PLL is locked
// 2. Synchronize the reset to each clock domain
// ********************************************************************************************************************************
DE4_SOPC_ddr2_0_p0_reset ureset(
.pll_afi_clk (pll_afi_clk),
.pll_addr_cmd_clk (pll_addr_cmd_clk),
.pll_dqs_ena_clk (pll_dqs_ena_clk),
.seq_clk (seq_clk),
.pll_avl_clk (pll_avl_clk),
.scc_clk (pll_config_clk),
.reset_n_scc_clk (reset_n_scc_clk),
.reset_n_avl_clk (reset_n_avl_clk),
.read_capture_clk (read_capture_clk),
.pll_locked (pll_locked),
.global_reset_n (global_reset_n),
.soft_reset_n (soft_reset_n),
.csr_soft_reset_req (csr_soft_reset_req),
.reset_request_n (reset_request_n),
.ctl_reset_n (ctl_reset_n),
.reset_n_afi_clk (reset_n_afi_clk),
.reset_n_addr_cmd_clk (reset_n_addr_cmd_clk),
.reset_n_seq_clk (reset_n_seq_clk),
.reset_n_resync_clk (reset_n_resync_clk)
);
defparam ureset.MEM_READ_DQS_WIDTH = MEM_READ_DQS_WIDTH;
defparam ureset.NUM_AFI_RESET = NUM_AFI_RESET;
wire scc_data;
wire [MEM_READ_DQS_WIDTH - 1:0] scc_dqs_ena;
wire [MEM_READ_DQS_WIDTH - 1:0] scc_dqs_io_ena;
wire [MEM_DQ_WIDTH - 1:0] scc_dq_ena;
wire [MEM_DM_WIDTH - 1:0] scc_dm_ena;
wire scc_upd;
wire [MEM_READ_DQS_WIDTH - 1:0] capture_strobe_tracking;
assign calib_skip_steps = seq_calib_init_reg;
assign afi_cal_debug_info = phy_cal_debug_info;
assign phy_clk = seq_clk;
assign phy_reset_n = reset_n_seq_clk;
assign dll_clk = pll_write_clk_pre_phy_clk;
assign afi_wlat = phy_afi_wlat;
assign afi_rlat = phy_afi_rlat;
// ********************************************************************************************************************************
// The address and command datapath is responsible for adding any flop stages/extra logic that may be required between the AFI
// interface and the output DDIOs.
// ********************************************************************************************************************************
DE4_SOPC_ddr2_0_p0_addr_cmd_datapath uaddr_cmd_datapath(
.clk (pll_addr_cmd_clk),
.reset_n (reset_n_afi_clk[1]),
.afi_address (afi_addr),
.afi_bank (afi_ba),
.afi_cs_n (afi_cs_n),
.afi_cke (afi_cke),
.afi_odt (afi_odt),
.afi_ras_n (afi_ras_n),
.afi_cas_n (afi_cas_n),
.afi_we_n (afi_we_n),
.phy_ddio_address (phy_ddio_address),
.phy_ddio_odt (phy_ddio_odt),
.phy_ddio_bank (phy_ddio_bank),
.phy_ddio_cs_n (phy_ddio_cs_n),
.phy_ddio_cke (phy_ddio_cke),
.phy_ddio_we_n (phy_ddio_we_n),
.phy_ddio_ras_n (phy_ddio_ras_n),
.phy_ddio_cas_n (phy_ddio_cas_n)
);
defparam uaddr_cmd_datapath.MEM_ADDRESS_WIDTH = MEM_ADDRESS_WIDTH;
defparam uaddr_cmd_datapath.MEM_BANK_WIDTH = MEM_BANK_WIDTH;
defparam uaddr_cmd_datapath.MEM_CHIP_SELECT_WIDTH = MEM_CHIP_SELECT_WIDTH;
defparam uaddr_cmd_datapath.MEM_CLK_EN_WIDTH = MEM_CLK_EN_WIDTH;
defparam uaddr_cmd_datapath.MEM_ODT_WIDTH = MEM_ODT_WIDTH;
defparam uaddr_cmd_datapath.MEM_DM_WIDTH = MEM_DM_WIDTH;
defparam uaddr_cmd_datapath.MEM_CONTROL_WIDTH = MEM_CONTROL_WIDTH;
defparam uaddr_cmd_datapath.MEM_DQ_WIDTH = MEM_DQ_WIDTH;
defparam uaddr_cmd_datapath.MEM_READ_DQS_WIDTH = MEM_READ_DQS_WIDTH;
defparam uaddr_cmd_datapath.MEM_WRITE_DQS_WIDTH = MEM_WRITE_DQS_WIDTH;
defparam uaddr_cmd_datapath.AFI_ADDRESS_WIDTH = AFI_ADDRESS_WIDTH;
defparam uaddr_cmd_datapath.AFI_BANK_WIDTH = AFI_BANK_WIDTH;
defparam uaddr_cmd_datapath.AFI_CHIP_SELECT_WIDTH = AFI_CHIP_SELECT_WIDTH;
defparam uaddr_cmd_datapath.AFI_CLK_EN_WIDTH = AFI_CLK_EN_WIDTH;
defparam uaddr_cmd_datapath.AFI_ODT_WIDTH = AFI_ODT_WIDTH;
defparam uaddr_cmd_datapath.AFI_DATA_MASK_WIDTH = AFI_DATA_MASK_WIDTH;
defparam uaddr_cmd_datapath.AFI_CONTROL_WIDTH = AFI_CONTROL_WIDTH;
defparam uaddr_cmd_datapath.AFI_DATA_WIDTH = AFI_DATA_WIDTH;
defparam uaddr_cmd_datapath.NUM_AC_FR_CYCLE_SHIFTS = NUM_AC_FR_CYCLE_SHIFTS;
// ********************************************************************************************************************************
// The write datapath is responsible for adding any flop stages/extra logic that may be required between the AFI interface
// and the output DDIOs.
// ********************************************************************************************************************************
DE4_SOPC_ddr2_0_p0_write_datapath uwrite_datapath(
.pll_afi_clk (pll_afi_clk),
.reset_n (reset_n_afi_clk[2]),
.force_oct_off (force_oct_off),
.phy_ddio_oct_ena (phy_ddio_oct_ena),
.afi_dqs_en (afi_dqs_burst),
.afi_wdata (afi_wdata),
.afi_wdata_valid (afi_wdata_valid),
.afi_dm (afi_dm),
.phy_ddio_dq (phy_ddio_dq),
.phy_ddio_dqs_en (phy_ddio_dqs_en),
.phy_ddio_wrdata_en (phy_ddio_wrdata_en),
.phy_ddio_wrdata_mask (phy_ddio_wrdata_mask),
.seq_num_write_fr_cycle_shifts (phy_num_write_fr_cycle_shifts)
);
defparam uwrite_datapath.MEM_ADDRESS_WIDTH = MEM_ADDRESS_WIDTH;
defparam uwrite_datapath.MEM_DM_WIDTH = MEM_DM_WIDTH;
defparam uwrite_datapath.MEM_CONTROL_WIDTH = MEM_CONTROL_WIDTH;
defparam uwrite_datapath.MEM_DQ_WIDTH = MEM_DQ_WIDTH;
defparam uwrite_datapath.MEM_READ_DQS_WIDTH = MEM_READ_DQS_WIDTH;
defparam uwrite_datapath.MEM_WRITE_DQS_WIDTH = MEM_WRITE_DQS_WIDTH;
defparam uwrite_datapath.AFI_ADDRESS_WIDTH = AFI_ADDRESS_WIDTH;
defparam uwrite_datapath.AFI_DATA_MASK_WIDTH = AFI_DATA_MASK_WIDTH;
defparam uwrite_datapath.AFI_CONTROL_WIDTH = AFI_CONTROL_WIDTH;
defparam uwrite_datapath.AFI_DATA_WIDTH = AFI_DATA_WIDTH;
defparam uwrite_datapath.AFI_DQS_WIDTH = AFI_DQS_WIDTH;
defparam uwrite_datapath.NUM_WRITE_PATH_FLOP_STAGES = NUM_WRITE_PATH_FLOP_STAGES;
defparam uwrite_datapath.NUM_WRITE_FR_CYCLE_SHIFTS = NUM_WRITE_FR_CYCLE_SHIFTS;
// ********************************************************************************************************************************
// The read datapath is responsible for read data resynchronization from the memory clock domain to the AFI clock domain.
// It contains 1 FIFO per DQS group for read valid prediction and 1 FIFO per DQS group for read data synchronization.
// ********************************************************************************************************************************
DE4_SOPC_ddr2_0_p0_read_datapath uread_datapath(
.reset_n_afi_clk (reset_n_afi_clk[3]),
.reset_n_resync_clk (reset_n_resync_clk),
.seq_read_fifo_reset (phy_read_fifo_reset),
.pll_afi_clk (pll_afi_clk),
.pll_dqs_ena_clk (pll_dqs_ena_clk),
.read_capture_clk (read_capture_clk),
.ddio_phy_dq (ddio_phy_dq),
.seq_read_latency_counter (phy_read_latency_counter),
.seq_read_increment_vfifo_fr (phy_read_increment_vfifo_fr),
.seq_read_increment_vfifo_hr (phy_read_increment_vfifo_hr),
.seq_read_increment_vfifo_qr (phy_read_increment_vfifo_qr),
.force_oct_off (force_oct_off),
.dqs_enable_ctrl (dqs_enable_ctrl),
.afi_rdata_en (afi_rdata_en),
.afi_rdata_en_full (afi_rdata_en_full),
.afi_rdata (afi_rdata),
.phy_mux_read_fifo_q (phy_read_fifo_q),
.afi_rdata_valid (afi_rdata_valid),
.seq_calib_init (seq_calib_init_reg),
.dqs_edge_detect (dqs_edge_detect)
);
defparam uread_datapath.DEVICE_FAMILY = DEVICE_FAMILY;
defparam uread_datapath.MEM_ADDRESS_WIDTH = MEM_ADDRESS_WIDTH;
defparam uread_datapath.MEM_DM_WIDTH = MEM_DM_WIDTH;
defparam uread_datapath.MEM_CONTROL_WIDTH = MEM_CONTROL_WIDTH;
defparam uread_datapath.MEM_DQ_WIDTH = MEM_DQ_WIDTH;
defparam uread_datapath.MEM_READ_DQS_WIDTH = MEM_READ_DQS_WIDTH;
defparam uread_datapath.MEM_WRITE_DQS_WIDTH = MEM_WRITE_DQS_WIDTH;
defparam uread_datapath.AFI_ADDRESS_WIDTH = AFI_ADDRESS_WIDTH;
defparam uread_datapath.AFI_DATA_MASK_WIDTH = AFI_DATA_MASK_WIDTH;
defparam uread_datapath.AFI_CONTROL_WIDTH = AFI_CONTROL_WIDTH;
defparam uread_datapath.AFI_DATA_WIDTH = AFI_DATA_WIDTH;
defparam uread_datapath.AFI_DQS_WIDTH = AFI_DQS_WIDTH;
defparam uread_datapath.MAX_LATENCY_COUNT_WIDTH = MAX_LATENCY_COUNT_WIDTH;
defparam uread_datapath.MAX_READ_LATENCY = MAX_READ_LATENCY;
defparam uread_datapath.READ_FIFO_READ_MEM_DEPTH = READ_FIFO_READ_MEM_DEPTH;
defparam uread_datapath.READ_FIFO_READ_ADDR_WIDTH = READ_FIFO_READ_ADDR_WIDTH;
defparam uread_datapath.READ_FIFO_WRITE_MEM_DEPTH = READ_FIFO_WRITE_MEM_DEPTH;
defparam uread_datapath.READ_FIFO_WRITE_ADDR_WIDTH = READ_FIFO_WRITE_ADDR_WIDTH;
defparam uread_datapath.READ_VALID_FIFO_SIZE = READ_VALID_FIFO_SIZE;
defparam uread_datapath.READ_VALID_FIFO_READ_MEM_DEPTH = READ_VALID_FIFO_READ_MEM_DEPTH;
defparam uread_datapath.READ_VALID_FIFO_READ_ADDR_WIDTH = READ_VALID_FIFO_READ_ADDR_WIDTH;
defparam uread_datapath.READ_VALID_FIFO_WRITE_MEM_DEPTH = READ_VALID_FIFO_WRITE_MEM_DEPTH;
defparam uread_datapath.READ_VALID_FIFO_WRITE_ADDR_WIDTH = READ_VALID_FIFO_WRITE_ADDR_WIDTH;
defparam uread_datapath.READ_VALID_FIFO_PER_DQS_WIDTH = READ_VALID_FIFO_PER_DQS_WIDTH;
defparam uread_datapath.NUM_SUBGROUP_PER_READ_DQS = NUM_SUBGROUP_PER_READ_DQS;
defparam uread_datapath.MEM_T_RL = MEM_T_RL;
defparam uread_datapath.CALIB_REG_WIDTH = CALIB_REG_WIDTH;
defparam uread_datapath.QVLD_EXTRA_FLOP_STAGES = QVLD_EXTRA_FLOP_STAGES;
defparam uread_datapath.QVLD_WR_ADDRESS_OFFSET = QVLD_WR_ADDRESS_OFFSET;
defparam uread_datapath.FAST_SIM_MODEL = FAST_SIM_MODEL;
// ********************************************************************************************************************************
// The I/O block is responsible for instantiating all the built-in I/O logic in the FPGA
// ********************************************************************************************************************************
DE4_SOPC_ddr2_0_p0_new_io_pads uio_pads (
.reset_n_addr_cmd_clk (reset_n_addr_cmd_clk),
.reset_n_afi_clk (reset_n_afi_clk[1]),
.oct_ctl_rs_value (oct_ctl_rs_value),
.oct_ctl_rt_value (oct_ctl_rt_value),
// Address and Command
.phy_ddio_addr_cmd_clk (pll_addr_cmd_clk),
.phy_ddio_address (phy_ddio_address),
.phy_ddio_bank (phy_ddio_bank),
.phy_ddio_cs_n (phy_ddio_cs_n),
.phy_ddio_cke (phy_ddio_cke),
.phy_ddio_odt (phy_ddio_odt),
.phy_ddio_we_n (phy_ddio_we_n),
.phy_ddio_ras_n (phy_ddio_ras_n),
.phy_ddio_cas_n (phy_ddio_cas_n),
.phy_mem_address (mem_a),
.phy_mem_bank (mem_ba),
.phy_mem_cs_n (mem_cs_n),
.phy_mem_cke (mem_cke),
.phy_mem_odt (mem_odt),
.phy_mem_we_n (mem_we_n),
.phy_mem_ras_n (mem_ras_n),
.phy_mem_cas_n (mem_cas_n),
// Write
.pll_afi_clk (pll_afi_clk),
.pll_mem_clk (pll_mem_clk),
.pll_write_clk (pll_write_clk),
.pll_dqs_ena_clk (pll_dqs_ena_clk),
.phy_ddio_dq (phy_ddio_dq),
.phy_ddio_dqs_en (phy_ddio_dqs_en),
.phy_ddio_oct_ena (phy_ddio_oct_ena),
.dqs_enable_ctrl (dqs_enable_ctrl),
.phy_ddio_wrdata_en (phy_ddio_wrdata_en),
.phy_ddio_wrdata_mask (phy_ddio_wrdata_mask),
.phy_mem_dq (mem_dq),
.phy_mem_dm (mem_dm),
.phy_mem_ck (mem_ck),
.phy_mem_ck_n (mem_ck_n),
.mem_dqs (mem_dqs),
.mem_dqs_n (mem_dqs_n),
// Read
.dll_phy_delayctrl (dll_phy_delayctrl),
.ddio_phy_dq (ddio_phy_dq),
.read_capture_clk (read_capture_clk)
,
.scc_clk (pll_config_clk),
.scc_data (scc_data),
.scc_dqs_ena (scc_dqs_ena),
.scc_dqs_io_ena (scc_dqs_io_ena),
.scc_dq_ena (scc_dq_ena),
.scc_dm_ena (scc_dm_ena),
.scc_upd (scc_upd),
.enable_mem_clk (~afi_mem_clk_disable),
.capture_strobe_tracking (capture_strobe_tracking)
);
defparam uio_pads.DEVICE_FAMILY = DEVICE_FAMILY;
defparam uio_pads.OCT_SERIES_TERM_CONTROL_WIDTH = OCT_SERIES_TERM_CONTROL_WIDTH;
defparam uio_pads.OCT_PARALLEL_TERM_CONTROL_WIDTH = OCT_PARALLEL_TERM_CONTROL_WIDTH;
defparam uio_pads.MEM_ADDRESS_WIDTH = MEM_ADDRESS_WIDTH;
defparam uio_pads.MEM_BANK_WIDTH = MEM_BANK_WIDTH;
defparam uio_pads.MEM_CHIP_SELECT_WIDTH = MEM_CHIP_SELECT_WIDTH;
defparam uio_pads.MEM_CLK_EN_WIDTH = MEM_CLK_EN_WIDTH;
defparam uio_pads.MEM_CK_WIDTH = MEM_CK_WIDTH;
defparam uio_pads.MEM_ODT_WIDTH = MEM_ODT_WIDTH;
defparam uio_pads.MEM_DQS_WIDTH = MEM_DQS_WIDTH;
defparam uio_pads.MEM_DM_WIDTH = MEM_DM_WIDTH;
defparam uio_pads.MEM_CONTROL_WIDTH = MEM_CONTROL_WIDTH;
defparam uio_pads.MEM_DQ_WIDTH = MEM_DQ_WIDTH;
defparam uio_pads.MEM_READ_DQS_WIDTH = MEM_READ_DQS_WIDTH;
defparam uio_pads.MEM_WRITE_DQS_WIDTH = MEM_WRITE_DQS_WIDTH;
defparam uio_pads.AFI_ADDRESS_WIDTH = AFI_ADDRESS_WIDTH;
defparam uio_pads.AFI_BANK_WIDTH = AFI_BANK_WIDTH;
defparam uio_pads.AFI_CHIP_SELECT_WIDTH = AFI_CHIP_SELECT_WIDTH;
defparam uio_pads.AFI_CLK_EN_WIDTH = AFI_CLK_EN_WIDTH;
defparam uio_pads.AFI_ODT_WIDTH = AFI_ODT_WIDTH;
defparam uio_pads.AFI_DATA_MASK_WIDTH = AFI_DATA_MASK_WIDTH;
defparam uio_pads.AFI_CONTROL_WIDTH = AFI_CONTROL_WIDTH;
defparam uio_pads.AFI_DATA_WIDTH = AFI_DATA_WIDTH;
defparam uio_pads.AFI_DQS_WIDTH = AFI_DQS_WIDTH;
defparam uio_pads.DLL_DELAY_CTRL_WIDTH = DLL_DELAY_CTRL_WIDTH;
defparam uio_pads.REGISTER_C2P = REGISTER_C2P;
defparam uio_pads.DQS_ENABLE_CTRL_WIDTH = READ_VALID_FIFO_WIDTH;
defparam uio_pads.ALTDQDQS_INPUT_FREQ = ALTDQDQS_INPUT_FREQ;
defparam uio_pads.ALTDQDQS_DELAY_CHAIN_BUFFER_MODE = ALTDQDQS_DELAY_CHAIN_BUFFER_MODE;
defparam uio_pads.ALTDQDQS_DQS_PHASE_SETTING = ALTDQDQS_DQS_PHASE_SETTING;
defparam uio_pads.ALTDQDQS_DQS_PHASE_SHIFT = ALTDQDQS_DQS_PHASE_SHIFT;
defparam uio_pads.ALTDQDQS_DELAYED_CLOCK_PHASE_SETTING = ALTDQDQS_DELAYED_CLOCK_PHASE_SETTING;
defparam uio_pads.FAST_SIM_MODEL = FAST_SIM_MODEL;
assign csr_soft_reset_req = 1'b0;
reg afi_half_clk_reg /* synthesis dont_merge syn_noprune syn_preserve = 1 */;
always @(posedge pll_afi_half_clk)
afi_half_clk_reg <= ~afi_half_clk_reg;
// Calculate the ceiling of log_2 of the input value
function integer ceil_log2;
input integer value;
begin
value = value - 1;
for (ceil_log2 = 0; value > 0; ceil_log2 = ceil_log2 + 1)
value = value >> 1;
end
endfunction
endmodule
|
// (C) 2001-2012 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1 ps / 1 ps
// altera message_off 10036
module DE4_SOPC_ddr2_0_p0_new_io_pads(
reset_n_addr_cmd_clk,
reset_n_afi_clk,
phy_reset_mem_stable,
oct_ctl_rs_value,
oct_ctl_rt_value,
phy_ddio_addr_cmd_clk,
phy_ddio_address,
phy_ddio_bank,
phy_ddio_cs_n,
phy_ddio_cke,
phy_ddio_odt,
phy_ddio_we_n,
phy_ddio_ras_n,
phy_ddio_cas_n,
phy_mem_address,
phy_mem_bank,
phy_mem_cs_n,
phy_mem_cke,
phy_mem_odt,
phy_mem_we_n,
phy_mem_ras_n,
phy_mem_cas_n,
pll_afi_clk,
pll_mem_clk,
pll_write_clk,
pll_dqs_ena_clk,
phy_ddio_dq,
phy_ddio_dqs_en,
phy_ddio_oct_ena,
dqs_enable_ctrl,
phy_ddio_wrdata_en,
phy_ddio_wrdata_mask,
phy_mem_dq,
phy_mem_dm,
phy_mem_ck,
phy_mem_ck_n,
mem_dqs,
mem_dqs_n,
dll_phy_delayctrl,
ddio_phy_dq,
read_capture_clk,
scc_clk,
scc_data,
scc_dqs_ena,
scc_dqs_io_ena,
scc_dq_ena,
scc_dm_ena,
scc_sr_dqsenable_delayctrl,
scc_sr_dqsdisablen_delayctrl,
scc_sr_multirank_delayctrl,
scc_upd,
enable_mem_clk,
capture_strobe_tracking
);
parameter DEVICE_FAMILY = "";
parameter REGISTER_C2P = "";
parameter LDC_MEM_CK_CPS_PHASE = "";
parameter OCT_SERIES_TERM_CONTROL_WIDTH = "";
parameter OCT_PARALLEL_TERM_CONTROL_WIDTH = "";
parameter MEM_ADDRESS_WIDTH = "";
parameter MEM_BANK_WIDTH = "";
parameter MEM_CHIP_SELECT_WIDTH = "";
parameter MEM_CLK_EN_WIDTH = "";
parameter MEM_CK_WIDTH = "";
parameter MEM_ODT_WIDTH = "";
parameter MEM_DQS_WIDTH = "";
parameter MEM_DM_WIDTH = "";
parameter MEM_CONTROL_WIDTH = "";
parameter MEM_DQ_WIDTH = "";
parameter MEM_READ_DQS_WIDTH = "";
parameter MEM_WRITE_DQS_WIDTH = "";
parameter AFI_ADDRESS_WIDTH = "";
parameter AFI_BANK_WIDTH = "";
parameter AFI_CHIP_SELECT_WIDTH = "";
parameter AFI_CLK_EN_WIDTH = "";
parameter AFI_ODT_WIDTH = "";
parameter AFI_DATA_MASK_WIDTH = "";
parameter AFI_CONTROL_WIDTH = "";
parameter AFI_DATA_WIDTH = "";
parameter AFI_DQS_WIDTH = "";
parameter AFI_RATE_RATIO = "";
parameter DLL_DELAY_CTRL_WIDTH = "";
parameter DQS_ENABLE_CTRL_WIDTH = "";
parameter ALTDQDQS_INPUT_FREQ = "";
parameter ALTDQDQS_DELAY_CHAIN_BUFFER_MODE = "";
parameter ALTDQDQS_DQS_PHASE_SETTING = "";
parameter ALTDQDQS_DQS_PHASE_SHIFT = "";
parameter ALTDQDQS_DELAYED_CLOCK_PHASE_SETTING = "";
parameter FAST_SIM_MODEL = "";
parameter IS_HHP_HPS = "";
localparam DOUBLE_MEM_DQ_WIDTH = MEM_DQ_WIDTH * 2;
localparam HALF_AFI_DATA_WIDTH = AFI_DATA_WIDTH / 2;
localparam HALF_AFI_DQS_WIDTH = AFI_DQS_WIDTH / 2;
input reset_n_afi_clk;
input reset_n_addr_cmd_clk;
input phy_reset_mem_stable;
input [OCT_SERIES_TERM_CONTROL_WIDTH-1:0] oct_ctl_rs_value;
input [OCT_PARALLEL_TERM_CONTROL_WIDTH-1:0] oct_ctl_rt_value;
input phy_ddio_addr_cmd_clk;
input [AFI_ADDRESS_WIDTH-1:0] phy_ddio_address;
input [AFI_BANK_WIDTH-1:0] phy_ddio_bank;
input [AFI_CHIP_SELECT_WIDTH-1:0] phy_ddio_cs_n;
input [AFI_CLK_EN_WIDTH-1:0] phy_ddio_cke;
input [AFI_ODT_WIDTH-1:0] phy_ddio_odt;
input [AFI_CONTROL_WIDTH-1:0] phy_ddio_ras_n;
input [AFI_CONTROL_WIDTH-1:0] phy_ddio_cas_n;
input [AFI_CONTROL_WIDTH-1:0] phy_ddio_we_n;
output [MEM_ADDRESS_WIDTH-1:0] phy_mem_address;
output [MEM_BANK_WIDTH-1:0] phy_mem_bank;
output [MEM_CHIP_SELECT_WIDTH-1:0] phy_mem_cs_n;
output [MEM_CLK_EN_WIDTH-1:0] phy_mem_cke;
output [MEM_ODT_WIDTH-1:0] phy_mem_odt;
output [MEM_CONTROL_WIDTH-1:0] phy_mem_we_n;
output [MEM_CONTROL_WIDTH-1:0] phy_mem_ras_n;
output [MEM_CONTROL_WIDTH-1:0] phy_mem_cas_n;
input pll_afi_clk;
input pll_mem_clk;
input pll_write_clk;
input pll_dqs_ena_clk;
input [AFI_DATA_WIDTH-1:0] phy_ddio_dq;
input [AFI_DQS_WIDTH-1:0] phy_ddio_dqs_en;
input [AFI_DQS_WIDTH-1:0] phy_ddio_oct_ena;
input [DQS_ENABLE_CTRL_WIDTH-1:0] dqs_enable_ctrl;
input [AFI_DQS_WIDTH-1:0] phy_ddio_wrdata_en;
input [AFI_DATA_MASK_WIDTH-1:0] phy_ddio_wrdata_mask;
inout [MEM_DQ_WIDTH-1:0] phy_mem_dq;
output [MEM_DM_WIDTH-1:0] phy_mem_dm;
output [MEM_CK_WIDTH-1:0] phy_mem_ck;
output [MEM_CK_WIDTH-1:0] phy_mem_ck_n;
inout [MEM_DQS_WIDTH-1:0] mem_dqs;
inout [MEM_DQS_WIDTH-1:0] mem_dqs_n;
input [DLL_DELAY_CTRL_WIDTH-1:0] dll_phy_delayctrl;
localparam DDIO_PHY_DQ_WIDTH = DOUBLE_MEM_DQ_WIDTH;
output [DDIO_PHY_DQ_WIDTH-1:0] ddio_phy_dq;
output [MEM_READ_DQS_WIDTH-1:0] read_capture_clk;
input scc_clk;
input scc_data;
input [MEM_READ_DQS_WIDTH - 1:0] scc_dqs_ena;
input [MEM_READ_DQS_WIDTH - 1:0] scc_dqs_io_ena;
input [MEM_DQ_WIDTH - 1:0] scc_dq_ena;
input [MEM_DM_WIDTH - 1:0] scc_dm_ena;
input [7:0] scc_sr_dqsenable_delayctrl;
input [7:0] scc_sr_dqsdisablen_delayctrl;
input [7:0] scc_sr_multirank_delayctrl;
input [0:0] scc_upd;
input [MEM_CK_WIDTH-1:0] enable_mem_clk;
output [MEM_READ_DQS_WIDTH - 1:0] capture_strobe_tracking;
assign capture_strobe_tracking = 1'd0;
wire [MEM_DQ_WIDTH-1:0] mem_phy_dq;
wire [DLL_DELAY_CTRL_WIDTH-1:0] read_bidir_dll_phy_delayctrl;
wire [MEM_READ_DQS_WIDTH-1:0] bidir_read_dqs_bus_out;
wire [MEM_DQ_WIDTH-1:0] bidir_read_dq_input_data_out_high;
wire [MEM_DQ_WIDTH-1:0] bidir_read_dq_input_data_out_low;
wire hr_clk = pll_afi_clk;
wire core_clk = pll_afi_clk;
wire reset_n_core_clk = reset_n_afi_clk;
reg [AFI_DATA_WIDTH-1:0] phy_ddio_dq_int;
reg [AFI_DQS_WIDTH-1:0] phy_ddio_wrdata_en_int;
reg [AFI_DATA_MASK_WIDTH-1:0] phy_ddio_wrdata_mask_int;
reg [AFI_DQS_WIDTH-1:0] phy_ddio_dqs_en_int;
reg [AFI_DQS_WIDTH-1:0] phy_ddio_oct_ena_int;
generate
if (REGISTER_C2P == "false") begin
always @(*) begin
phy_ddio_dq_int = phy_ddio_dq;
phy_ddio_wrdata_en_int = phy_ddio_wrdata_en;
phy_ddio_wrdata_mask_int = phy_ddio_wrdata_mask;
phy_ddio_dqs_en_int = phy_ddio_dqs_en;
phy_ddio_oct_ena_int = phy_ddio_oct_ena;
end
end else begin
always @(posedge pll_afi_clk) begin
phy_ddio_dq_int <= phy_ddio_dq;
phy_ddio_wrdata_en_int <= phy_ddio_wrdata_en;
phy_ddio_wrdata_mask_int <= phy_ddio_wrdata_mask;
phy_ddio_dqs_en_int <= phy_ddio_dqs_en;
phy_ddio_oct_ena_int <= phy_ddio_oct_ena;
end
end
endgenerate
DE4_SOPC_ddr2_0_p0_addr_cmd_pads uaddr_cmd_pads(
.reset_n (reset_n_addr_cmd_clk),
.reset_n_afi_clk (reset_n_afi_clk),
.pll_afi_clk (pll_afi_clk),
.pll_mem_clk (pll_mem_clk),
.pll_write_clk (pll_write_clk),
.phy_ddio_addr_cmd_clk (phy_ddio_addr_cmd_clk),
.dll_delayctrl_in (dll_phy_delayctrl),
.enable_mem_clk (enable_mem_clk),
.phy_ddio_address (phy_ddio_address),
.phy_ddio_bank (phy_ddio_bank),
.phy_ddio_cs_n (phy_ddio_cs_n),
.phy_ddio_cke (phy_ddio_cke),
.phy_ddio_odt (phy_ddio_odt),
.phy_ddio_we_n (phy_ddio_we_n),
.phy_ddio_ras_n (phy_ddio_ras_n),
.phy_ddio_cas_n (phy_ddio_cas_n),
.phy_mem_address (phy_mem_address),
.phy_mem_bank (phy_mem_bank),
.phy_mem_cs_n (phy_mem_cs_n),
.phy_mem_cke (phy_mem_cke),
.phy_mem_odt (phy_mem_odt),
.phy_mem_we_n (phy_mem_we_n),
.phy_mem_ras_n (phy_mem_ras_n),
.phy_mem_cas_n (phy_mem_cas_n),
.phy_mem_ck (phy_mem_ck),
.phy_mem_ck_n (phy_mem_ck_n)
);
defparam uaddr_cmd_pads.DEVICE_FAMILY = DEVICE_FAMILY;
defparam uaddr_cmd_pads.MEM_ADDRESS_WIDTH = MEM_ADDRESS_WIDTH;
defparam uaddr_cmd_pads.MEM_BANK_WIDTH = MEM_BANK_WIDTH;
defparam uaddr_cmd_pads.MEM_CHIP_SELECT_WIDTH = MEM_CHIP_SELECT_WIDTH;
defparam uaddr_cmd_pads.MEM_CLK_EN_WIDTH = MEM_CLK_EN_WIDTH;
defparam uaddr_cmd_pads.MEM_CK_WIDTH = MEM_CK_WIDTH;
defparam uaddr_cmd_pads.MEM_ODT_WIDTH = MEM_ODT_WIDTH;
defparam uaddr_cmd_pads.MEM_CONTROL_WIDTH = MEM_CONTROL_WIDTH;
defparam uaddr_cmd_pads.AFI_ADDRESS_WIDTH = AFI_ADDRESS_WIDTH;
defparam uaddr_cmd_pads.AFI_BANK_WIDTH = AFI_BANK_WIDTH;
defparam uaddr_cmd_pads.AFI_CHIP_SELECT_WIDTH = AFI_CHIP_SELECT_WIDTH;
defparam uaddr_cmd_pads.AFI_CLK_EN_WIDTH = AFI_CLK_EN_WIDTH;
defparam uaddr_cmd_pads.AFI_ODT_WIDTH = AFI_ODT_WIDTH;
defparam uaddr_cmd_pads.AFI_CONTROL_WIDTH = AFI_CONTROL_WIDTH;
defparam uaddr_cmd_pads.DLL_WIDTH = DLL_DELAY_CTRL_WIDTH;
defparam uaddr_cmd_pads.REGISTER_C2P = REGISTER_C2P;
defparam uaddr_cmd_pads.IS_HHP_HPS = IS_HHP_HPS;
localparam NUM_OF_DQDQS = MEM_WRITE_DQS_WIDTH;
localparam DQDQS_DATA_WIDTH = MEM_DQ_WIDTH / NUM_OF_DQDQS;
localparam DQDQS_DDIO_PHY_DQ_WIDTH = DDIO_PHY_DQ_WIDTH / NUM_OF_DQDQS;
localparam DQDQS_DM_WIDTH = MEM_DM_WIDTH / MEM_WRITE_DQS_WIDTH;
localparam NUM_OF_DQDQS_WITH_DM = MEM_WRITE_DQS_WIDTH;
generate
genvar i;
for (i=0; i<NUM_OF_DQDQS; i=i+1)
begin: dq_ddio
wire dqs_busout;
// The phy_ddio_dq_int bus is the write data for all DQS groups in one
// AFI cycle. The bus is ordered by time slot and subordered by DQS group:
//
// FR: D1_T1, D0_T1, D1_T0, D0_T0
// HR: D1_T3, D0_T3, D1_T2, D0_T2, D1_T1, D0_T1, D1_T0, D0_T0
//
// Extract the write data targeting the current DQS group
wire [DQDQS_DATA_WIDTH-1:0] phy_ddio_dq_t0 = phy_ddio_dq_int [DQDQS_DATA_WIDTH*(i+1+0*NUM_OF_DQDQS)-1 : DQDQS_DATA_WIDTH*(i+0*NUM_OF_DQDQS)];
wire [DQDQS_DATA_WIDTH-1:0] phy_ddio_dq_t1 = phy_ddio_dq_int [DQDQS_DATA_WIDTH*(i+1+1*NUM_OF_DQDQS)-1 : DQDQS_DATA_WIDTH*(i+1*NUM_OF_DQDQS)];
wire [DQDQS_DATA_WIDTH-1:0] phy_ddio_dq_t2 = phy_ddio_dq_int [DQDQS_DATA_WIDTH*(i+1+2*NUM_OF_DQDQS)-1 : DQDQS_DATA_WIDTH*(i+2*NUM_OF_DQDQS)];
wire [DQDQS_DATA_WIDTH-1:0] phy_ddio_dq_t3 = phy_ddio_dq_int [DQDQS_DATA_WIDTH*(i+1+3*NUM_OF_DQDQS)-1 : DQDQS_DATA_WIDTH*(i+3*NUM_OF_DQDQS)];
// Extract the OE signal targeting the current DQS group
wire [DQDQS_DATA_WIDTH-1:0] phy_ddio_wrdata_en_t0 = {DQDQS_DATA_WIDTH{phy_ddio_wrdata_en_int[i]}};
wire [DQDQS_DATA_WIDTH-1:0] phy_ddio_wrdata_en_t1 = {DQDQS_DATA_WIDTH{phy_ddio_wrdata_en_int[i+MEM_WRITE_DQS_WIDTH]}};
// Extract the dynamic OCT control signal targeting the current DQS group
wire phy_ddio_oct_ena_t0 = phy_ddio_oct_ena_int[i];
wire phy_ddio_oct_ena_t1 = phy_ddio_oct_ena_int[i+MEM_WRITE_DQS_WIDTH];
// Extract the write data mask signal targeting the current DQS group
wire [DQDQS_DM_WIDTH-1:0] phy_ddio_wrdata_mask_t0;
wire [DQDQS_DM_WIDTH-1:0] phy_ddio_wrdata_mask_t1;
wire [DQDQS_DM_WIDTH-1:0] phy_ddio_wrdata_mask_t2;
wire [DQDQS_DM_WIDTH-1:0] phy_ddio_wrdata_mask_t3;
assign phy_ddio_wrdata_mask_t0 = phy_ddio_wrdata_mask_int [DQDQS_DM_WIDTH*(i+1+0*NUM_OF_DQDQS_WITH_DM)-1 : DQDQS_DM_WIDTH*(i+0*NUM_OF_DQDQS_WITH_DM)];
assign phy_ddio_wrdata_mask_t1 = phy_ddio_wrdata_mask_int [DQDQS_DM_WIDTH*(i+1+1*NUM_OF_DQDQS_WITH_DM)-1 : DQDQS_DM_WIDTH*(i+1*NUM_OF_DQDQS_WITH_DM)];
assign phy_ddio_wrdata_mask_t2 = phy_ddio_wrdata_mask_int [DQDQS_DM_WIDTH*(i+1+2*NUM_OF_DQDQS_WITH_DM)-1 : DQDQS_DM_WIDTH*(i+2*NUM_OF_DQDQS_WITH_DM)];
assign phy_ddio_wrdata_mask_t3 = phy_ddio_wrdata_mask_int [DQDQS_DM_WIDTH*(i+1+3*NUM_OF_DQDQS_WITH_DM)-1 : DQDQS_DM_WIDTH*(i+3*NUM_OF_DQDQS_WITH_DM)];
DE4_SOPC_ddr2_0_p0_altdqdqs ubidir_dq_dqs (
.write_strobe_clock_in (pll_mem_clk),
.reset_n_core_clock_in (reset_n_core_clk),
.core_clock_in (core_clk),
.fr_clock_in (pll_write_clk),
.hr_clock_in (hr_clk),
.parallelterminationcontrol_in(oct_ctl_rt_value),
.seriesterminationcontrol_in(oct_ctl_rs_value),
.strobe_ena_hr_clock_in (hr_clk),
.strobe_ena_clock_in (pll_dqs_ena_clk),
.read_write_data_io (phy_mem_dq[(DQDQS_DATA_WIDTH*(i+1)-1) : DQDQS_DATA_WIDTH*i]),
.read_data_out (ddio_phy_dq [(DQDQS_DDIO_PHY_DQ_WIDTH*(i+1)-1) : DQDQS_DDIO_PHY_DQ_WIDTH*i]),
.capture_strobe_out(dqs_busout),
.extra_write_data_in ({phy_ddio_wrdata_mask_t3, phy_ddio_wrdata_mask_t2, phy_ddio_wrdata_mask_t1, phy_ddio_wrdata_mask_t0}),
.write_data_in ({phy_ddio_dq_t3, phy_ddio_dq_t2, phy_ddio_dq_t1, phy_ddio_dq_t0}),
.write_oe_in ({phy_ddio_wrdata_en_t1, phy_ddio_wrdata_en_t0}),
.strobe_io (mem_dqs[i]),
.strobe_n_io (mem_dqs_n[i]),
.output_strobe_ena ({phy_ddio_dqs_en_int[i+NUM_OF_DQDQS], phy_ddio_dqs_en_int[i]}),
.oct_ena_in ({phy_ddio_oct_ena_t1, phy_ddio_oct_ena_t0}),
.capture_strobe_ena (dqs_enable_ctrl[i]),
.extra_write_data_out (phy_mem_dm[i]),
.config_data_in (scc_data),
.config_dqs_ena (scc_dqs_ena[i]),
.config_io_ena (scc_dq_ena[(DQDQS_DATA_WIDTH*(i+1)-1) : DQDQS_DATA_WIDTH*i]),
.config_dqs_io_ena (scc_dqs_io_ena[i]),
.config_update (scc_upd[0]),
.config_clock_in (scc_clk),
.config_extra_io_ena (scc_dm_ena[i]),
.dll_delayctrl_in (dll_phy_delayctrl)
);
defparam ubidir_dq_dqs.ALTERA_ALTDQ_DQS2_FAST_SIM_MODEL = FAST_SIM_MODEL;
assign read_capture_clk[i] = ~dqs_busout;
end
endgenerate
endmodule
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// ********************************************************************************************************************************
// File name: read_datapath.v
// The read datapath is responsible for read data resynchronization from the memory clock domain to the AFI clock domain.
// It contains 1 FIFO per DQS group for read valid prediction and 1 FIFO per DQS group for read data synchronization.
// ********************************************************************************************************************************
`timescale 1 ps / 1 ps
(* altera_attribute = "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF" *)
// altera message_off 10036
module DE4_SOPC_ddr2_0_p0_read_datapath(
reset_n_afi_clk,
seq_read_fifo_reset,
reset_n_resync_clk,
pll_dqs_ena_clk,
read_capture_clk,
ddio_phy_dq,
pll_afi_clk,
seq_read_latency_counter,
seq_read_increment_vfifo_fr,
seq_read_increment_vfifo_hr,
seq_read_increment_vfifo_qr,
afi_rdata_en,
afi_rdata_en_full,
afi_rdata,
phy_mux_read_fifo_q,
force_oct_off,
dqs_enable_ctrl,
afi_rdata_valid,
seq_calib_init,
dqs_edge_detect
);
// ********************************************************************************************************************************
// BEGIN PARAMETER SECTION
// All parameters default to "" will have their values passed in from higher level wrapper with the controller and driver
parameter DEVICE_FAMILY = "";
// PHY-Memory Interface
parameter MEM_ADDRESS_WIDTH = "";
parameter MEM_DM_WIDTH = "";
parameter MEM_CONTROL_WIDTH = "";
parameter MEM_DQ_WIDTH = "";
parameter MEM_READ_DQS_WIDTH = "";
parameter MEM_WRITE_DQS_WIDTH = "";
// PHY-Controller (AFI) Interface
parameter AFI_ADDRESS_WIDTH = "";
parameter AFI_DATA_MASK_WIDTH = "";
parameter AFI_CONTROL_WIDTH = "";
parameter AFI_DATA_WIDTH = "";
parameter AFI_DQS_WIDTH = "";
// Read Datapath
parameter MAX_LATENCY_COUNT_WIDTH = "";
parameter MAX_READ_LATENCY = "";
parameter READ_FIFO_READ_MEM_DEPTH = "";
parameter READ_FIFO_READ_ADDR_WIDTH = "";
parameter READ_FIFO_WRITE_MEM_DEPTH = "";
parameter READ_FIFO_WRITE_ADDR_WIDTH = "";
parameter READ_VALID_FIFO_SIZE = "";
parameter READ_VALID_FIFO_READ_MEM_DEPTH = "";
parameter READ_VALID_FIFO_READ_ADDR_WIDTH = "";
parameter READ_VALID_FIFO_WRITE_MEM_DEPTH = "";
parameter READ_VALID_FIFO_WRITE_ADDR_WIDTH = "";
parameter READ_VALID_FIFO_PER_DQS_WIDTH = "";
parameter NUM_SUBGROUP_PER_READ_DQS = "";
parameter MEM_T_RL = "";
parameter QVLD_EXTRA_FLOP_STAGES = "";
parameter QVLD_WR_ADDRESS_OFFSET = "";
// Width of the calibration status register used to control calibration skipping.
parameter CALIB_REG_WIDTH = "";
parameter FAST_SIM_MODEL = "";
// Local parameters
localparam RATE_MULT = 2;
localparam MAKE_FIFOS_IN_ALTDQDQS = "false";
localparam DOUBLE_MEM_DQ_WIDTH = MEM_DQ_WIDTH * 2;
localparam DDIO_PHY_DQ_WIDTH = DOUBLE_MEM_DQ_WIDTH;
localparam DQ_GROUP_WIDTH = MEM_DQ_WIDTH / MEM_READ_DQS_WIDTH;
localparam USE_NUM_SUBGROUP_PER_READ_DQS = FAST_SIM_MODEL ? 1 : NUM_SUBGROUP_PER_READ_DQS;
localparam AFI_DQ_GROUP_DATA_WIDTH = AFI_DATA_WIDTH / MEM_READ_DQS_WIDTH;
localparam DDIO_DQ_GROUP_DATA_WIDTH = DDIO_PHY_DQ_WIDTH / MEM_READ_DQS_WIDTH;
localparam DDIO_DQ_GROUP_DATA_WIDTH_SUBGROUP = DDIO_PHY_DQ_WIDTH / (MEM_READ_DQS_WIDTH * USE_NUM_SUBGROUP_PER_READ_DQS);
localparam VFIFO_RATE_MULT = 1;
localparam READ_FIFO_DQ_GROUP_OUTPUT_WIDTH = 4 * DQ_GROUP_WIDTH;
localparam OCT_ON_DELAY = (MEM_T_RL > 4) ? ((MEM_T_RL - 4) / 2) : 0;
localparam OCT_OFF_DELAY = (MEM_T_RL + 6) / 2;
// END PARAMETER SECTION
// ********************************************************************************************************************************
input reset_n_afi_clk;
input [MEM_READ_DQS_WIDTH-1:0] seq_read_fifo_reset; // reset from sequencer to read and write pointers of the data resynchronization FIFO
input [MEM_READ_DQS_WIDTH-1:0] read_capture_clk;
input reset_n_resync_clk;
input pll_dqs_ena_clk;
input [DDIO_PHY_DQ_WIDTH-1:0] ddio_phy_dq;
input pll_afi_clk;
input [MAX_LATENCY_COUNT_WIDTH-1:0] seq_read_latency_counter;
input [MEM_READ_DQS_WIDTH-1:0] seq_read_increment_vfifo_fr; // increment valid prediction FIFO write pointer by an extra full rate cycle
input [MEM_READ_DQS_WIDTH-1:0] seq_read_increment_vfifo_hr; // increment valid prediction FIFO write pointer by an extra half rate cycle
// in full rate core, both will mean an extra full rate cycle
input [MEM_READ_DQS_WIDTH-1:0] seq_read_increment_vfifo_qr; // increment valid prediction FIFO write pointer by an extra quarter rate cycle.
// not used in full/half rate core
input afi_rdata_en;
input afi_rdata_en_full;
output [AFI_DATA_WIDTH-1:0] afi_rdata;
output afi_rdata_valid;
// read data (no reordering) for indepedently FIFO calibrations (multiple FIFOs for multiple DQS groups)
output [AFI_DATA_WIDTH-1:0] phy_mux_read_fifo_q;
output [AFI_DQS_WIDTH-1:0] force_oct_off;
output [MEM_READ_DQS_WIDTH*READ_VALID_FIFO_PER_DQS_WIDTH-1:0] dqs_enable_ctrl;
output [MEM_READ_DQS_WIDTH-1:0] dqs_edge_detect;
input [CALIB_REG_WIDTH-1:0] seq_calib_init;
// Mark the following register as a keeper because the pin_map.tcl
// script uses it as anchor for finding the AFI clock
reg afi_rdata_valid /* synthesis dont_merge syn_noprune syn_preserve = 1 */;
reg [1:0] qvld_num_fr_cycle_shift [MEM_READ_DQS_WIDTH-1:0];
wire [MEM_READ_DQS_WIDTH*READ_VALID_FIFO_PER_DQS_WIDTH-1:0] qvld;
wire [MEM_READ_DQS_WIDTH-1:0] read_valid;
wire [MEM_READ_DQS_WIDTH-1:0] valid_predict_clk;
wire [MEM_READ_DQS_WIDTH-1:0] reset_n_valid_predict_clk;
reg [MEM_READ_DQS_WIDTH-1:0] reset_n_fifo_write_side;
reg [MEM_READ_DQS_WIDTH-1:0] reset_n_fifo_wraddress;
wire [MEM_READ_DQS_WIDTH-1:0] read_capture_clk_pos;
wire [MEM_READ_DQS_WIDTH-1:0] read_capture_clk_neg;
reg [MEM_READ_DQS_WIDTH-1:0] read_capture_clk_div2;
wire [AFI_DATA_WIDTH-1:0] read_fifo_output;
wire read_fifo_read_clk = pll_afi_clk;
wire reset_n_read_fifo_read_clk = reset_n_afi_clk;
wire seq_calib_skip_vfifo;
assign seq_calib_skip_vfifo = seq_calib_init[3];
// *******************************************************************************************************************
// VALID PREDICTION
// Read request (afi_rdata_en) is generated on the AFI clock domain (pll_afi_clk).
// Read data is captured on the read_capture_clk domain (output clock from I/O).
// The purpose of valid prediction is to determine which read_capture_clk cycle valid data will be returned to the core
// after the request is issued on pll_afi_clk; this is essentially the latency between read request seen on
// AFI interface and valid data available at the output of ALTDQ_DQS.
// The clock domain crossing between pll_afi_clk and read_capture_clk is handled by a FIFO (uread_valid_fifo).
// The pll_afi_clk controls the write side of the FIFO and the read_capture_clk controls the read side.
// The pll_afi_clk writes into the FIFO on every clock cycle. When there is no read request, it writes a 0;
// when there is a read request, it writes a 1 (refer to as a token) into the FIFO.
// The read_capture_clk reads from the FIFO every clock cycle, whenever it reads a token, it means that valid data
// is available during that cycle. Each token represents 1 cycle of valid data.
// In full rate, BL=2, 1 read results in 1 AFI cycle of valid data, controller asserts afi_rdata_en for 1 cycle
// In full rate, BL=4, 1 read results in 2 AFI cycles of valid data, controller asserts afi_rdata_en for 2 cycles
// In full rate, BL=8, 1 read results in 4 AFI cycles of valid data, controller asserts afi_rdata_en for 4 cycles
// In half rate, BL=2, not supported
// In half rate, BL=4, 1 read results in 1 AFI cycle of valid data, controller asserts afi_rdata_en for 1 cycle
// In half rate, BL=8, 1 read results in 2 AFI cycle of valid data, controller asserts afi_rdata_en for 2 cycles
// In full rate, 1 afi_rdata_en cycle = 1 token
// In half rate, 1 afi_rdata_en cycle = 2 tokens
//
// After reset is released, the relationship between the read and write pointers can be arbitrary.
// During calibration, the sequencer keeps incrementing the write pointer (both the sequencer and write pointer operates
// on pll_afi_clk) until the correct latency has been tuned.
// *******************************************************************************************************************
assign valid_predict_clk = {MEM_READ_DQS_WIDTH{pll_dqs_ena_clk}};
assign reset_n_valid_predict_clk = {MEM_READ_DQS_WIDTH{reset_n_resync_clk}};
generate
if (MAKE_FIFOS_IN_ALTDQDQS != "true")
begin
genvar dqsgroup, vfifo_i;
for (dqsgroup=0; dqsgroup<MEM_READ_DQS_WIDTH; dqsgroup=dqsgroup+1)
begin: read_valid_predict
wire [VFIFO_RATE_MULT-1:0] vfifo_out_per_dqs;
reg [READ_VALID_FIFO_WRITE_ADDR_WIDTH-1:0] qvld_wr_address;
reg [READ_VALID_FIFO_READ_ADDR_WIDTH-1:0] qvld_rd_address;
`ifndef SYNTH_FOR_SIM
// synthesis translate_off
`endif
wire [ceil_log2(READ_VALID_FIFO_SIZE)-1:0] qvld_wr_address_offset;
assign qvld_wr_address_offset = qvld_rd_address + QVLD_WR_ADDRESS_OFFSET;
`ifndef SYNTH_FOR_SIM
// synthesis translate_on
`endif
wire qvld_increment_wr_address = seq_read_increment_vfifo_hr[dqsgroup];
// In half rate, 1 afi_rdata_en_full cycle = 2 tokens, qvld_in[0] and qvld_in[1]
// In 1/4 rate, 1 afi_rdata_en_full cycle = 4 tokens, qvld_in[0..3]
// etc.
// Tokens are written at AFI clock rate but read at full rate.
// During calibration the latency needs to be tuned at full rate granularity.
// For example, in half rate, in the base case, 1 afi_rdata_en_full will result
// in two tokens in write address 0, that means read address 0 and read address 1
// will both have tokens. If the sequencer request to increase the latency by
// full rate cycle, the write side first writes 10 into write address 0, then
// it writes 01 into write address 1; this means there are tokens in read
// address 1 and read address 2.
always @(posedge pll_afi_clk or negedge reset_n_afi_clk)
begin
if (~reset_n_afi_clk) begin
`ifndef SYNTH_FOR_SIM
// synthesis translate_off
`endif
qvld_num_fr_cycle_shift[dqsgroup] <= {1'b0, ((seq_calib_skip_vfifo) ? qvld_wr_address_offset[0] : 1'b0)};
`ifndef SYNTH_FOR_SIM
// synthesis translate_on
// synthesis read_comments_as_HDL on
// qvld_num_fr_cycle_shift[dqsgroup] <= 2'b00;
// synthesis read_comments_as_HDL off
`endif
end else begin
if (seq_read_increment_vfifo_fr[dqsgroup]) begin
qvld_num_fr_cycle_shift[dqsgroup] <= 2'b01;
end else if (seq_read_increment_vfifo_hr[dqsgroup]) begin
qvld_num_fr_cycle_shift[dqsgroup] <= 2'b00;
end
end
end
wire [RATE_MULT-1:0] qvld_in;
DE4_SOPC_ddr2_0_p0_fr_cycle_shifter uread_fr_cycle_shifter(
.clk (pll_afi_clk),
.reset_n (reset_n_afi_clk),
.shift_by (qvld_num_fr_cycle_shift[dqsgroup]),
.datain ({RATE_MULT{afi_rdata_en_full}}),
.dataout (qvld_in));
defparam uread_fr_cycle_shifter.DATA_WIDTH = 1;
wire vfifo_read_clk = valid_predict_clk[dqsgroup];
wire vfifo_read_clk_reset_n = reset_n_valid_predict_clk[dqsgroup];
always @(posedge pll_afi_clk)
begin
`ifndef SYNTH_FOR_SIM
// synthesis translate_off
`endif
if (~reset_n_afi_clk) begin
qvld_wr_address <= (seq_calib_skip_vfifo) ? (qvld_wr_address_offset >> ceil_log2(RATE_MULT)) : {READ_VALID_FIFO_WRITE_ADDR_WIDTH{1'b0}};
`ifndef SYNTH_FOR_SIM
// synthesis translate_on
// synthesis read_comments_as_HDL on
// if (~reset_n_afi_clk) begin
// qvld_wr_address <= {READ_VALID_FIFO_WRITE_ADDR_WIDTH{1'b0}};
// synthesis read_comments_as_HDL off
`endif
end else begin
qvld_wr_address <= qvld_increment_wr_address ? (qvld_wr_address + 2'd2) : (qvld_wr_address + 2'd1);
end
end
always @(posedge vfifo_read_clk or negedge vfifo_read_clk_reset_n)
begin
if (~vfifo_read_clk_reset_n)
qvld_rd_address <= {READ_VALID_FIFO_READ_ADDR_WIDTH{1'b0}};
else
qvld_rd_address <= qvld_rd_address + 1'b1;
end
wire [VFIFO_RATE_MULT-1:0] vfifo_out_per_dqs_tmp;
DE4_SOPC_ddr2_0_p0_flop_mem uread_valid_fifo(
.wr_clk (pll_afi_clk),
.wr_en (1'b1),
.wr_addr (qvld_wr_address),
.wr_data (qvld_in),
.rd_reset_n (vfifo_read_clk_reset_n),
.rd_clk (vfifo_read_clk),
.rd_en (1'b1),
.rd_addr (qvld_rd_address),
.rd_data (vfifo_out_per_dqs_tmp)
);
defparam uread_valid_fifo.WRITE_MEM_DEPTH = READ_VALID_FIFO_WRITE_MEM_DEPTH;
defparam uread_valid_fifo.WRITE_ADDR_WIDTH = READ_VALID_FIFO_WRITE_ADDR_WIDTH;
defparam uread_valid_fifo.WRITE_DATA_WIDTH = RATE_MULT;
defparam uread_valid_fifo.READ_MEM_DEPTH = READ_VALID_FIFO_READ_MEM_DEPTH;
defparam uread_valid_fifo.READ_ADDR_WIDTH = READ_VALID_FIFO_READ_ADDR_WIDTH;
defparam uread_valid_fifo.READ_DATA_WIDTH = VFIFO_RATE_MULT;
// These extra flop stages are added to the output of the VFIFO
// These adds delay without expanding the VFIFO size
// Expanding the VFIFO size (also means bigger address counters) to 32 causes timing failures
for (vfifo_i=0; vfifo_i<VFIFO_RATE_MULT; vfifo_i=vfifo_i+1)
begin: qvld_extra_flop
reg [QVLD_EXTRA_FLOP_STAGES-1:0] vfifo_out_per_dqs_r;
always @(posedge vfifo_read_clk)
begin
vfifo_out_per_dqs_r <= {vfifo_out_per_dqs_r[QVLD_EXTRA_FLOP_STAGES-2:0], vfifo_out_per_dqs_tmp[vfifo_i]};
end
assign vfifo_out_per_dqs[vfifo_i] = vfifo_out_per_dqs_r[QVLD_EXTRA_FLOP_STAGES-1];
end
wire [READ_VALID_FIFO_PER_DQS_WIDTH-1:0] qvld_per_dqs = vfifo_out_per_dqs;
// Map per-dqs vfifo output bus to the per-interface vfifo output bus.
for (vfifo_i=0; vfifo_i<READ_VALID_FIFO_PER_DQS_WIDTH; vfifo_i=vfifo_i+1)
begin: map_qvld_per_dqs_to_qvld
assign qvld[dqsgroup+(vfifo_i*MEM_READ_DQS_WIDTH)] = qvld_per_dqs[vfifo_i];
end
end
end
endgenerate
assign dqs_enable_ctrl = qvld;
reg [MAX_READ_LATENCY-1:0] latency_shifter;
reg [MAX_READ_LATENCY-1:0] full_latency_shifter;
always @(posedge pll_afi_clk or negedge reset_n_afi_clk)
begin
if (~reset_n_afi_clk) begin
full_latency_shifter <= {MAX_READ_LATENCY{1'b0}};
latency_shifter <= {MAX_READ_LATENCY{1'b0}};
end
else begin
full_latency_shifter <= {full_latency_shifter[MAX_READ_LATENCY-2:0], afi_rdata_en_full};
latency_shifter <= {latency_shifter[MAX_READ_LATENCY-2:0], afi_rdata_en};
end
end
generate
if (MAKE_FIFOS_IN_ALTDQDQS != "true")
begin
genvar dqs_count, subgroup, dq_count, timeslot;
for (dqs_count=0; dqs_count<MEM_READ_DQS_WIDTH; dqs_count=dqs_count+1)
begin: read_buffering
wire [USE_NUM_SUBGROUP_PER_READ_DQS-1:0] wren;
wire [USE_NUM_SUBGROUP_PER_READ_DQS-1:0] wren_neg;
wire read_enable;
wire [READ_FIFO_DQ_GROUP_OUTPUT_WIDTH-1:0] read_fifo_output_per_dqs;
// Perform read data mapping from ddio_phy_dq to ddio_phy_dq_per_dqs.
//
// The ddio_phy_dq bus is the read data coming out of the DDIO, and so
// is 2x the interface data width. The bus is ordered by DQS group
// and sub-ordered by time slot:
//
// D1_T1, D1_T0, D0_T1, D0_T0
//
// The ddio_phy_dq_per_dqs bus is a subset of the ddio_phy_dq bus that
// is specific to the current DQS group. Like ddio_phy_dq, it's ordered
// by time slot:
//
// D0_T1, D0_T0
wire [DDIO_DQ_GROUP_DATA_WIDTH-1:0] ddio_phy_dq_per_dqs;
assign ddio_phy_dq_per_dqs = ddio_phy_dq[(DDIO_DQ_GROUP_DATA_WIDTH*(dqs_count+1)-1) : (DDIO_DQ_GROUP_DATA_WIDTH*dqs_count)];
DE4_SOPC_ddr2_0_p0_read_valid_selector uread_valid_selector(
.reset_n (reset_n_afi_clk),
.pll_afi_clk (pll_afi_clk),
.latency_shifter (latency_shifter),
.latency_counter (seq_read_latency_counter),
.read_enable (),
.read_valid (read_valid[dqs_count])
);
defparam uread_valid_selector.MAX_LATENCY_COUNT_WIDTH = MAX_LATENCY_COUNT_WIDTH;
DE4_SOPC_ddr2_0_p0_read_valid_selector uread_valid_full_selector(
.reset_n (reset_n_afi_clk),
.pll_afi_clk (pll_afi_clk),
.latency_shifter (full_latency_shifter),
.latency_counter (seq_read_latency_counter),
.read_enable (read_enable),
.read_valid ()
);
defparam uread_valid_full_selector.MAX_LATENCY_COUNT_WIDTH = MAX_LATENCY_COUNT_WIDTH;
always @(posedge pll_afi_clk or negedge reset_n_afi_clk)
begin
if (~reset_n_afi_clk) begin
reset_n_fifo_write_side[dqs_count] <= 1'b0;
reset_n_fifo_wraddress[dqs_count] <= 1'b0;
end
else begin
reset_n_fifo_write_side[dqs_count] <= ~seq_read_fifo_reset[dqs_count];
reset_n_fifo_wraddress[dqs_count] <= ~seq_read_fifo_reset[dqs_count];
end
end
wire [READ_FIFO_DQ_GROUP_OUTPUT_WIDTH-1:0] read_fifo_output_per_dqs_tmp;
always @(posedge read_capture_clk[dqs_count] or negedge reset_n_fifo_write_side[dqs_count])
begin
if (~reset_n_fifo_write_side[dqs_count])
read_capture_clk_div2[dqs_count] <= 1'b0;
else
read_capture_clk_div2[dqs_count] <= ~read_capture_clk_div2[dqs_count];
end
`ifndef SIMGEN
assign #10 read_capture_clk_pos[dqs_count] = read_capture_clk_div2[dqs_count];
`else
DE4_SOPC_ddr2_0_p0_sim_delay #(
.delay(10)
)
sim_delay_inst(
.o(read_capture_clk_pos[dqs_count]),
.i(read_capture_clk_div2[dqs_count]),
);
`endif
assign read_capture_clk_neg[dqs_count] = ~read_capture_clk_pos[dqs_count];
for (subgroup=0; subgroup<USE_NUM_SUBGROUP_PER_READ_DQS; subgroup=subgroup+1)
begin: read_subgroup
assign wren[subgroup] = 1'b1;
assign wren_neg[subgroup] = 1'b1;
reg [READ_FIFO_WRITE_ADDR_WIDTH-1:0] wraddress /* synthesis dont_merge */;
reg [READ_FIFO_WRITE_ADDR_WIDTH-1:0] wraddress_neg /* synthesis dont_merge */;
// The clock is read_capture_clk while reset_n_fifo_wraddress is a signal synchronous to
// the AFI clk domain but asynchronous to read_capture_clk. reset_n_fifo_wraddress goes
// '0' when either the system is reset, or when the sequencer asserts seq_read_fifo_reset.
// By design we ensure that wren has been '0' for at least one cycle when reset_n_fifo_wraddress
// is deasserted (i.e. '0' -> '1'). When wren is '0', the input and output of the
// wraddress registers are both '0', so there's no risk of metastability due to reset
// recovery.
always @(posedge read_capture_clk_pos[dqs_count] or negedge reset_n_fifo_wraddress[dqs_count])
begin
if (~reset_n_fifo_wraddress[dqs_count])
wraddress <= {READ_FIFO_WRITE_ADDR_WIDTH{1'b0}};
else if (wren[subgroup])
begin
if (READ_FIFO_WRITE_MEM_DEPTH == 2 ** READ_FIFO_WRITE_ADDR_WIDTH)
wraddress <= wraddress + 1'b1;
else
wraddress <= (wraddress == READ_FIFO_WRITE_MEM_DEPTH - 1) ? {READ_FIFO_WRITE_ADDR_WIDTH{1'b0}} : wraddress + 1'b1;
end
end
always @(posedge read_capture_clk_neg[dqs_count] or negedge reset_n_fifo_wraddress[dqs_count])
begin
if (~reset_n_fifo_wraddress[dqs_count])
wraddress_neg <= {READ_FIFO_WRITE_ADDR_WIDTH{1'b0}};
else if (wren_neg[subgroup])
begin
if (READ_FIFO_WRITE_MEM_DEPTH == 2 ** READ_FIFO_WRITE_ADDR_WIDTH)
wraddress_neg <= wraddress_neg + 1'b1;
else
wraddress_neg <= (wraddress_neg == READ_FIFO_WRITE_MEM_DEPTH - 1) ? {READ_FIFO_WRITE_ADDR_WIDTH{1'b0}} : wraddress_neg + 1'b1;
end
end
reg [READ_FIFO_READ_ADDR_WIDTH-1:0] rdaddress /* synthesis dont_merge */;
always @(posedge read_fifo_read_clk)
begin
if (seq_read_fifo_reset[dqs_count])
rdaddress <= {READ_FIFO_READ_ADDR_WIDTH{1'b0}};
else if (read_enable)
begin
if (READ_FIFO_READ_MEM_DEPTH == 2 ** READ_FIFO_READ_ADDR_WIDTH)
rdaddress <= rdaddress + 1'b1;
else
rdaddress <= (rdaddress == READ_FIFO_READ_MEM_DEPTH - 1) ? {READ_FIFO_READ_ADDR_WIDTH{1'b0}} : rdaddress + 1'b1;
end
end
DE4_SOPC_ddr2_0_p0_flop_mem uread_fifo(
.wr_clk (read_capture_clk_pos[dqs_count]),
.wr_en (wren[subgroup]),
.wr_addr (wraddress),
.wr_data (ddio_phy_dq_per_dqs[(DDIO_DQ_GROUP_DATA_WIDTH_SUBGROUP*(subgroup+1)-1) :
(DDIO_DQ_GROUP_DATA_WIDTH_SUBGROUP*subgroup)]),
.rd_reset_n (reset_n_read_fifo_read_clk),
.rd_clk (read_fifo_read_clk),
.rd_en (read_enable),
.rd_addr (rdaddress),
.rd_data (read_fifo_output_per_dqs_tmp[(DDIO_DQ_GROUP_DATA_WIDTH_SUBGROUP*(subgroup+1)-1) :
(DDIO_DQ_GROUP_DATA_WIDTH_SUBGROUP*subgroup)])
);
defparam uread_fifo.WRITE_MEM_DEPTH = READ_FIFO_WRITE_MEM_DEPTH;
defparam uread_fifo.WRITE_ADDR_WIDTH = READ_FIFO_WRITE_ADDR_WIDTH;
defparam uread_fifo.WRITE_DATA_WIDTH = DDIO_DQ_GROUP_DATA_WIDTH_SUBGROUP;
defparam uread_fifo.READ_MEM_DEPTH = READ_FIFO_READ_MEM_DEPTH;
defparam uread_fifo.READ_ADDR_WIDTH = READ_FIFO_READ_ADDR_WIDTH;
defparam uread_fifo.READ_DATA_WIDTH = READ_FIFO_DQ_GROUP_OUTPUT_WIDTH / (USE_NUM_SUBGROUP_PER_READ_DQS * 2);
DE4_SOPC_ddr2_0_p0_flop_mem uread_fifo_neg(
.wr_clk (read_capture_clk_neg[dqs_count]),
.wr_en (wren_neg[subgroup]),
.wr_addr (wraddress_neg),
.wr_data (ddio_phy_dq_per_dqs[(DDIO_DQ_GROUP_DATA_WIDTH_SUBGROUP*(subgroup+1)-1) :
(DDIO_DQ_GROUP_DATA_WIDTH_SUBGROUP*subgroup)]),
.rd_reset_n (reset_n_read_fifo_read_clk),
.rd_clk (read_fifo_read_clk),
.rd_en (read_enable),
.rd_addr (rdaddress),
.rd_data (read_fifo_output_per_dqs_tmp[(DDIO_DQ_GROUP_DATA_WIDTH_SUBGROUP*(subgroup+1)-1+DDIO_DQ_GROUP_DATA_WIDTH) :
(DDIO_DQ_GROUP_DATA_WIDTH_SUBGROUP*subgroup+DDIO_DQ_GROUP_DATA_WIDTH)])
);
defparam uread_fifo_neg.WRITE_MEM_DEPTH = READ_FIFO_WRITE_MEM_DEPTH;
defparam uread_fifo_neg.WRITE_ADDR_WIDTH = READ_FIFO_WRITE_ADDR_WIDTH;
defparam uread_fifo_neg.WRITE_DATA_WIDTH = DDIO_DQ_GROUP_DATA_WIDTH_SUBGROUP;
defparam uread_fifo_neg.READ_MEM_DEPTH = READ_FIFO_READ_MEM_DEPTH;
defparam uread_fifo_neg.READ_ADDR_WIDTH = READ_FIFO_READ_ADDR_WIDTH;
defparam uread_fifo_neg.READ_DATA_WIDTH = READ_FIFO_DQ_GROUP_OUTPUT_WIDTH / (USE_NUM_SUBGROUP_PER_READ_DQS * 2);
end
assign read_fifo_output_per_dqs = read_fifo_output_per_dqs_tmp;
// Perform mapping from read_fifo_output_per_dqs to read_fifo_output
//
// The read_fifo_output_per_dqs bus is the read data coming out of the read FIFO.
// It has the read data for the current dqs group. In FR, it has 2x the
// width of a dqs group on the interface. In HR, it has 4x the width of
// a dqs group on the interface. The bus is ordered by time slot:
//
// FR: D0_T1, D0_T0
// HR: D0_T3, D0_T2, D0_T1, D0_T0
//
// The read_fifo_output bus is the read data from read fifo. In FR, it has
// the same width as ddio_phy_dq (i.e. 2x interface width). In HR, it has
// 4x the interface width. The bus is ordered by time slot and
// sub-ordered by DQS group:
//
// FR: D1_T1, D0_T1, D1_T0, D0_T0
// HR: D1_T3, D0_T3, D1_T2, D0_T2, D1_T1, D0_T1, D1_T0, D0_T0
//
for (timeslot=0; timeslot<4; timeslot=timeslot+1)
begin: read_mapping_timeslot
wire [DQ_GROUP_WIDTH-1:0] rdata = read_fifo_output_per_dqs[DQ_GROUP_WIDTH * (timeslot + 1) - 1 : DQ_GROUP_WIDTH * timeslot];
assign read_fifo_output[DQ_GROUP_WIDTH * (dqs_count + 1) + MEM_DQ_WIDTH * timeslot - 1 : DQ_GROUP_WIDTH * dqs_count + MEM_DQ_WIDTH * timeslot] = rdata;
end
end
end else begin
// Read FIFOS are instantiated in ALTDQDQS. Just pass through to afi_rdata.
genvar dqs_count, timeslot;
for (dqs_count=0; dqs_count<MEM_READ_DQS_WIDTH; dqs_count=dqs_count+1)
begin: read_mapping_dqsgroup
wire [DDIO_DQ_GROUP_DATA_WIDTH-1:0] ddio_phy_dq_per_dqs;
assign ddio_phy_dq_per_dqs = ddio_phy_dq[(DDIO_DQ_GROUP_DATA_WIDTH*(dqs_count+1)-1) : (DDIO_DQ_GROUP_DATA_WIDTH*dqs_count)];
for (timeslot=0; timeslot<4; timeslot=timeslot+1)
begin: read_mapping_timeslot
wire [DQ_GROUP_WIDTH-1:0] rdata = ddio_phy_dq_per_dqs[DQ_GROUP_WIDTH * (timeslot + 1) - 1 : DQ_GROUP_WIDTH * timeslot];
assign read_fifo_output[MEM_DQ_WIDTH * timeslot + DQ_GROUP_WIDTH * (dqs_count + 1) - 1 : MEM_DQ_WIDTH * timeslot + DQ_GROUP_WIDTH * dqs_count] = rdata;
end
end
for (dqs_count=0; dqs_count<MEM_READ_DQS_WIDTH; dqs_count=dqs_count+1)
begin: read_buffering
DE4_SOPC_ddr2_0_p0_read_valid_selector uread_valid_selector(
.reset_n (reset_n_afi_clk),
.pll_afi_clk (pll_afi_clk),
.latency_shifter (latency_shifter),
.latency_counter ({1'b0, seq_read_latency_counter[MAX_LATENCY_COUNT_WIDTH-1:1]}),
.read_enable (),
.read_valid (read_valid[dqs_count])
);
defparam uread_valid_selector.MAX_LATENCY_COUNT_WIDTH = MAX_LATENCY_COUNT_WIDTH;
end
end
endgenerate
// Data from read-fifo is synchronous to the AFI clock and so can be sent
// directly to the afi_rdata bus.
assign afi_rdata = read_fifo_output;
// Perform data re-mapping from afi_rdata to phy_mux_read_fifo_q
//
// The afi_rdata bus is the read data going out to the AFI. In FR, it has
// the same width as ddio_phy_dq (i.e. 2x interface width). In HR, it has
// 4x the interface width. The bus is ordered by time slot and
// sub-ordered by DQS group:
//
// FR: D1_T1, D0_T1, D1_T0, D0_T0
// HR: D1_T3, D0_T3, D1_T2, D0_T2, D1_T1, D0_T1, D1_T0, D0_T0
//
// The phy_mux_read_fifo_q bus is the read data going into the sequencer
// for calibration. It has the same width as afi_rdata. The bus is ordered
// by DQS group, and sub-ordered by time slot:
//
// FR: D1_T1, D1_T0, D0_T1, D0_T0
// HR: D1_T3, D1_T2, D1_T1, D1_T0, D0_T3, D0_T2, D0_T1, D0_T0
//
//As of Nov 1 2010, the NIOS sequencer doesn't use the phy_mux_read_fifo_q signal.
generate
genvar k, t;
for (k=0; k<MEM_READ_DQS_WIDTH; k=k+1)
begin: read_mapping_for_seq
wire [AFI_DQ_GROUP_DATA_WIDTH-1:0] rdata_per_dqs_group;
for (t=0; t<RATE_MULT*2; t=t+1)
begin: build_rdata_per_dqs_group
wire [DQ_GROUP_WIDTH-1:0] rdata_t = afi_rdata[DQ_GROUP_WIDTH * (k+1) + MEM_DQ_WIDTH * t - 1 : DQ_GROUP_WIDTH * k + MEM_DQ_WIDTH * t];
assign rdata_per_dqs_group[(t+1)*DQ_GROUP_WIDTH-1:t*DQ_GROUP_WIDTH] = rdata_t;
end
assign phy_mux_read_fifo_q[(k+1)*AFI_DQ_GROUP_DATA_WIDTH-1 : k*AFI_DQ_GROUP_DATA_WIDTH] = rdata_per_dqs_group;
end
endgenerate
// Generate an AFI read valid signal from all the read valid signals from all FIFOs
always @(posedge pll_afi_clk or negedge reset_n_afi_clk)
begin
if (~reset_n_afi_clk) begin
afi_rdata_valid <= 1'b0;
end else begin
afi_rdata_valid <= &read_valid;
end
end
reg [AFI_DQS_WIDTH-1:0] force_oct_off;
generate
genvar oct_num;
for (oct_num = 0; oct_num < AFI_DQS_WIDTH; oct_num = oct_num + 1)
begin : oct_gen
reg [OCT_OFF_DELAY-1:0] rdata_en_r /* synthesis dont_merge */;
wire [OCT_OFF_DELAY:0] rdata_en_shifter;
assign rdata_en_shifter = {rdata_en_r,afi_rdata_en_full};
always @(posedge pll_afi_clk or negedge reset_n_afi_clk)
begin
if (~reset_n_afi_clk)
begin
rdata_en_r <= {OCT_OFF_DELAY{1'b0}};
force_oct_off[oct_num] <= 1'b0;
end
else
begin
rdata_en_r <= {rdata_en_r[OCT_OFF_DELAY-2:0],afi_rdata_en_full};
force_oct_off[oct_num] <= ~(|rdata_en_shifter[OCT_OFF_DELAY:OCT_ON_DELAY]);
end
end
end
endgenerate
// Track if any DQS edges were captured as method of determining if the interface is
// alive during debug.
wire [MEM_READ_DQS_WIDTH-1:0] dqs_detect_reset_n;
reg [MEM_READ_DQS_WIDTH-1:0] dqs_edge_detect_reg;
generate
genvar dqs_detect_count;
for (dqs_detect_count=0; dqs_detect_count<MEM_READ_DQS_WIDTH; dqs_detect_count=dqs_detect_count+1)
begin: dqs_detection
always @(posedge read_capture_clk_pos[dqs_detect_count] or negedge reset_n_fifo_write_side[dqs_detect_count])
if (~reset_n_fifo_write_side[dqs_detect_count])
dqs_edge_detect_reg[dqs_detect_count] <= 0;
else
dqs_edge_detect_reg[dqs_detect_count] <= 1;
end
endgenerate
assign dqs_edge_detect = dqs_edge_detect_reg;
// Calculate the ceiling of log_2 of the input value
function integer ceil_log2;
input integer value;
begin
value = value - 1;
for (ceil_log2 = 0; value > 0; ceil_log2 = ceil_log2 + 1)
value = value >> 1;
end
endfunction
endmodule
|
// (C) 2001-2012 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1 ps / 1 ps
module DE4_SOPC_ddr2_0_p0_read_valid_selector(
reset_n,
pll_afi_clk,
latency_shifter,
latency_counter,
read_enable,
read_valid
);
parameter MAX_LATENCY_COUNT_WIDTH = "";
localparam LATENCY_NUM = 2**MAX_LATENCY_COUNT_WIDTH;
input reset_n;
input pll_afi_clk;
input [LATENCY_NUM-1:0] latency_shifter;
input [MAX_LATENCY_COUNT_WIDTH-1:0] latency_counter;
output read_enable;
output read_valid;
wire [LATENCY_NUM-1:0] selector;
reg [LATENCY_NUM-1:0] selector_reg;
reg read_enable;
reg reading_data;
reg read_valid;
wire [LATENCY_NUM-1:0] valid_select;
lpm_decode uvalid_select(
.data (latency_counter),
.eq (selector)
// synopsys translate_off
,
.aclr (),
.clken (),
.clock (),
.enable ()
// synopsys translate_on
);
defparam uvalid_select.lpm_decodes = LATENCY_NUM;
defparam uvalid_select.lpm_type = "LPM_DECODE";
defparam uvalid_select.lpm_width = MAX_LATENCY_COUNT_WIDTH;
always @(posedge pll_afi_clk or negedge reset_n)
begin
if (~reset_n)
selector_reg <= {LATENCY_NUM{1'b0}};
else
selector_reg <= selector;
end
assign valid_select = selector_reg & latency_shifter;
always @(posedge pll_afi_clk or negedge reset_n)
begin
if (~reset_n)
begin
read_enable <= 1'b0;
read_valid <= 1'b0;
end
else
begin
read_enable <= |valid_select;
read_valid <= |valid_select;
end
end
endmodule
|
// (C) 2001-2012 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1 ps / 1 ps
(* altera_attribute = "-name GLOBAL_SIGNAL OFF" *)
module DE4_SOPC_ddr2_0_p0_reset(
seq_reset_mem_stable,
pll_afi_clk,
pll_addr_cmd_clk,
pll_dqs_ena_clk,
seq_clk,
scc_clk,
pll_avl_clk,
reset_n_scc_clk,
reset_n_avl_clk,
read_capture_clk,
pll_locked,
global_reset_n,
soft_reset_n,
ctl_reset_n,
reset_n_afi_clk,
reset_n_addr_cmd_clk,
reset_n_resync_clk,
reset_n_seq_clk,
reset_n_read_capture_clk
);
parameter MEM_READ_DQS_WIDTH = "";
parameter NUM_AFI_RESET = 1;
input seq_reset_mem_stable;
input pll_afi_clk;
input pll_addr_cmd_clk;
input pll_dqs_ena_clk;
input seq_clk;
input scc_clk;
input pll_avl_clk;
output reset_n_scc_clk;
output reset_n_avl_clk;
input [MEM_READ_DQS_WIDTH-1:0] read_capture_clk;
input pll_locked;
input global_reset_n;
input soft_reset_n;
output ctl_reset_n;
output [NUM_AFI_RESET-1:0] reset_n_afi_clk;
output reset_n_addr_cmd_clk;
output reset_n_resync_clk;
output reset_n_seq_clk;
output [MEM_READ_DQS_WIDTH-1:0] reset_n_read_capture_clk;
// Apply the synthesis keep attribute on the synchronized reset wires
// so that these names can be constrained using QSF settings to keep
// the resets on local routing.
wire phy_reset_n /* synthesis keep = 1 */;
wire phy_reset_mem_stable_n /* synthesis keep = 1*/;
wire [MEM_READ_DQS_WIDTH-1:0] reset_n_read_capture;
assign phy_reset_mem_stable_n = phy_reset_n & seq_reset_mem_stable;
assign reset_n_read_capture_clk = reset_n_read_capture;
assign phy_reset_n = pll_locked & global_reset_n & soft_reset_n;
DE4_SOPC_ddr2_0_p0_reset_sync ureset_afi_clk(
.reset_n (phy_reset_n),
.clk (pll_afi_clk),
.reset_n_sync (reset_n_afi_clk)
);
defparam ureset_afi_clk.RESET_SYNC_STAGES = 5;
defparam ureset_afi_clk.NUM_RESET_OUTPUT = NUM_AFI_RESET;
DE4_SOPC_ddr2_0_p0_reset_sync ureset_ctl_reset_clk(
.reset_n (phy_reset_n),
.clk (pll_afi_clk),
.reset_n_sync (ctl_reset_n)
);
defparam ureset_ctl_reset_clk.RESET_SYNC_STAGES = 5;
DE4_SOPC_ddr2_0_p0_reset_sync ureset_addr_cmd_clk(
.reset_n (phy_reset_n),
.clk (pll_addr_cmd_clk),
.reset_n_sync (reset_n_addr_cmd_clk)
);
DE4_SOPC_ddr2_0_p0_reset_sync ureset_resync_clk(
.reset_n (phy_reset_n),
.clk (pll_dqs_ena_clk),
.reset_n_sync (reset_n_resync_clk)
);
DE4_SOPC_ddr2_0_p0_reset_sync ureset_seq_clk(
.reset_n (phy_reset_n),
.clk (seq_clk),
.reset_n_sync (reset_n_seq_clk)
);
DE4_SOPC_ddr2_0_p0_reset_sync ureset_scc_clk(
.reset_n (phy_reset_n),
.clk (scc_clk),
.reset_n_sync (reset_n_scc_clk)
);
DE4_SOPC_ddr2_0_p0_reset_sync ureset_avl_clk(
.reset_n (phy_reset_n),
.clk (pll_avl_clk),
.reset_n_sync (reset_n_avl_clk)
);
generate
genvar i;
for (i=0; i<MEM_READ_DQS_WIDTH; i=i+1)
begin: read_capture_reset
DE4_SOPC_ddr2_0_p0_reset_sync ureset_read_capture_clk(
.reset_n (phy_reset_mem_stable_n),
.clk (read_capture_clk[i]),
.reset_n_sync (reset_n_read_capture[i])
);
end
endgenerate
endmodule
|
// (C) 2001-2012 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1 ps / 1 ps
module DE4_SOPC_ddr2_0_p0_reset_sync(
reset_n,
clk,
reset_n_sync
);
parameter RESET_SYNC_STAGES = 4;
parameter NUM_RESET_OUTPUT = 1;
input reset_n;
input clk;
output [NUM_RESET_OUTPUT-1:0] reset_n_sync;
// identify the synchronizer chain so that Quartus can analyze metastability.
// Since these resets are localized to the PHY alone, make them routed locally
// to avoid using global networks.
(* altera_attribute = {"-name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS; -name GLOBAL_SIGNAL OFF"}*) reg [RESET_SYNC_STAGES+NUM_RESET_OUTPUT-2:0] reset_reg /*synthesis dont_merge */;
generate
genvar i;
for (i=0; i<RESET_SYNC_STAGES+NUM_RESET_OUTPUT-1; i=i+1)
begin: reset_stage
always @(posedge clk or negedge reset_n)
begin
if (~reset_n)
reset_reg[i] <= 1'b0;
else
begin
if (i==0)
reset_reg[i] <= 1'b1;
else if (i < RESET_SYNC_STAGES)
reset_reg[i] <= reset_reg[i-1];
else
reset_reg[i] <= reset_reg[RESET_SYNC_STAGES-2];
end
end
end
endgenerate
assign reset_n_sync = reset_reg[RESET_SYNC_STAGES+NUM_RESET_OUTPUT-2:RESET_SYNC_STAGES-1];
endmodule
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// *****************************************************************
// File name: simple_ddio_out.v
//
// This module can be used to double the data rate of the datain
// bus. Outputs at the dataout. Conversion is either done in soft
// logic or using hard ddio blocks in I/O periphery.
//
// Example 1:
//
// datain = {T1, T0} at clk cycle x, where each Ty is a data item
// with width DATA_WIDTH
//
// dataout = {T0} at positive phase of clk cycle x
// dataout = {T1} at negative phase of clk cycle x
//
// In this case, set OUTPUT_FULL_DATA_WIDTH == DATA_WIDTH.
//
//
// Example 2:
//
// datain = {T3, T2, T1, T0} at clk cycle x, where each Ty is a data
// item with width DATA_WIDTH
//
// dataout = {T1, T0} at positive phase of clk cycle x
// dataout = {T3, T2} at negative phase of clk cycle x
//
// dataout can then be fed into another ddio_out stage for further
// rate doubling, as in example 1.
//
// Note that in this case, OUTPUT_FULL_DATA_WIDTH == 2 * DATA_WIDTH
//
//
// Parameter Descriptions:
// =======================
//
// DATA_WIDTH - see examples above
//
// OUTPUT_FULL_DATA_WIDTH - see examples above
//
// USE_CORE_LOGIC - specifies whether to use core logic, or to
// ("true"|"false") use hard ddio_out blocks in the I/O periphery.
//
// HALF_RATE_MODE - specifies whether the hard ddio_out is in
// ("true"|"false") "half-rate" mode or not. Only applicable
// when USE_CORE_LOGIC is "false".
//
// REG_POST_RESET_HIGH - specifies whether the ddio registers
// ("true"|"false") should come out as logic-1 or logic-0
// after reset.
//
// REGISTER_OUTPUT - Specifies whether the output is registered.
// ("true"|"false") If "true", an extra FF (clocked by dr_clk
// and reset by dr_reset_n) is synthesized at
// the output. Only applicable when
// USE_CORE_LOGIC is "true".
//
// USE_EXTRA_OUTPUT_REG - Specifies whether the soft logic structure
// generated resembles the Stratix IV 3 register
// structure. Only applicable when
// USE_CORE_LOGIC is "true".
//
// *****************************************************************
`timescale 1 ps / 1 ps
module DE4_SOPC_ddr2_0_p0_simple_ddio_out(
clk,
reset_n,
dr_clk,
dr_reset_n,
datain,
dataout
);
// *****************************************************************
// BEGIN PARAMETER SECTION
parameter DATA_WIDTH = "";
parameter OUTPUT_FULL_DATA_WIDTH = "";
parameter USE_CORE_LOGIC = "";
parameter REG_POST_RESET_HIGH = "false";
parameter HALF_RATE_MODE = ""; //only applicable when USE_CORE_LOGIC is "false"
parameter REGISTER_OUTPUT = "false"; //only applicable when USE_CORE_LOGIC is "true"
parameter USE_EXTRA_OUTPUT_REG = "false"; //only applicable when USE_CORE_LOGIC is "true"
localparam OUTPUT_WIDTH_MULT = OUTPUT_FULL_DATA_WIDTH / DATA_WIDTH;
localparam INPUT_WIDTH_MULT = OUTPUT_WIDTH_MULT * 2;
localparam INPUT_FULL_DATA_WIDTH = DATA_WIDTH * INPUT_WIDTH_MULT;
localparam HARD_DDIO_ASYNC_MODE = (REG_POST_RESET_HIGH == "true") ? "preset" : "clear";
localparam HARD_DDIO_POWER_UP = (REG_POST_RESET_HIGH == "true") ? "high" : "low";
// END PARAMETER SECTION
// *****************************************************************
input clk;
input reset_n;
input [INPUT_FULL_DATA_WIDTH-1:0] datain;
output [OUTPUT_FULL_DATA_WIDTH-1:0] dataout;
input dr_clk; //only used when USE_CORE_LOGIC and REGISTER_OUTPUT are "true"
input dr_reset_n; //only used when USE_CORE_LOGIC and REGISTER_OUTPUT are "true"
generate
genvar i, j, k;
if (USE_CORE_LOGIC == "true") begin
//Use core logic to implement ddio_out.
//This is always the 2-flop implementation regardless of HALF_RATE_MODE setting
reg [INPUT_FULL_DATA_WIDTH-1:0] datain_r;
reg [INPUT_FULL_DATA_WIDTH-1:0] datain_rr;
always @(posedge clk or negedge reset_n)
begin
if (~reset_n) begin
if (REG_POST_RESET_HIGH == "true")
datain_r <= {INPUT_FULL_DATA_WIDTH{1'b1}};
else
datain_r <= {INPUT_FULL_DATA_WIDTH{1'b0}};
end else begin
datain_r <= datain;
end
end
if (USE_EXTRA_OUTPUT_REG == "true") begin
always @(negedge clk or negedge reset_n)
begin
if (~reset_n) begin
if (REG_POST_RESET_HIGH == "true") begin
datain_rr <= {INPUT_FULL_DATA_WIDTH{1'b1}};
end
else begin
datain_rr <= {INPUT_FULL_DATA_WIDTH{1'b0}};
end
end else begin
datain_rr <= datain_r;
end
end
end
wire [OUTPUT_FULL_DATA_WIDTH-1:0] dataout_wire;
for (i=0; i<OUTPUT_WIDTH_MULT; i=i+1)
begin: ddio_group
for (j=0; j<DATA_WIDTH; j=j+1)
begin: sig
if (USE_EXTRA_OUTPUT_REG == "true") begin
//wire delay is to avoid glitch during sim which makes things harder to see.
//in reality glitches are unimportant as long as paths between output
//and next flop meet timing.
wire t0 = datain_r[i*DATA_WIDTH+j];
wire #1 t1 = datain_rr[(i+OUTPUT_WIDTH_MULT)*DATA_WIDTH+j];
wire #1 muxsel = clk;
//There's a timing path from from muxsel to the target FF fed by dataout.
//If the clock signal driving muxsel is a global signal (which is likely),
//the router won't try to insert delay to fix hold. We therefore insert
//lcell buffers to help hold timing.
wire muxsel_buff_out /* synthesis syn_noprune syn_preserve = 1 */;
lcell muxsel_buff(.in(muxsel), .out(muxsel_buff_out)) /* synthesis syn_noprune syn_preserve = 1 */;
assign dataout_wire[i*DATA_WIDTH+j] = (muxsel_buff_out == 1'b0) ? t0 : t1;
end
else begin
//wire delay is to avoid glitch during sim which makes things harder to see.
//in reality glitches are unimportant as long as paths between output
//and next flop meet timing.
wire t0 = datain_r[i*DATA_WIDTH+j];
wire #1 t1 = datain_r[(i+OUTPUT_WIDTH_MULT)*DATA_WIDTH+j];
wire #1 muxsel = clk;
//There's a timing path from from muxsel to the target FF fed by dataout.
//If the clock signal driving muxsel is a global signal (which is likely),
//the router won't try to insert delay to fix hold. We therefore insert
//lcell buffers to help hold timing.
wire muxsel_buff_out /* synthesis syn_noprune syn_preserve = 1 */;
lcell muxsel_buff(.in(muxsel), .out(muxsel_buff_out)) /* synthesis syn_noprune syn_preserve = 1 */;
assign dataout_wire[i*DATA_WIDTH+j] = (muxsel_buff_out == 1'b1) ? t0 : t1;
end
end
end
//register output if needed
if (REGISTER_OUTPUT == "false") begin
assign dataout = dataout_wire;
end else begin
reg [OUTPUT_FULL_DATA_WIDTH-1:0] dataout_r /* synthesis dont_merge syn_noprune syn_preserve = 1 */;
always @(posedge dr_clk or negedge dr_reset_n)
begin
if (~dr_reset_n) begin
if (REG_POST_RESET_HIGH == "true")
dataout_r <= {OUTPUT_FULL_DATA_WIDTH{1'b1}};
else
dataout_r <= {OUTPUT_FULL_DATA_WIDTH{1'b0}};
end else begin
dataout_r <= dataout_wire;
end
end
assign dataout = dataout_r;
end
end else begin
//Use ddio_out at the I/O periphery of the device
for (i=0; i<OUTPUT_WIDTH_MULT; i=i+1)
begin: ddio_group
for (j=0; j<DATA_WIDTH; j=j+1)
begin: sig
wire t0;
wire t1;
//3-flop half-rate ddio_outs have reversed output ordering
if (HALF_RATE_MODE == "true") begin
assign t0 = datain[(i+OUTPUT_WIDTH_MULT)*DATA_WIDTH+j];
assign t1 = datain[i*DATA_WIDTH+j];
end else begin
assign t0 = datain[i*DATA_WIDTH+j];
assign t1 = datain[(i+OUTPUT_WIDTH_MULT)*DATA_WIDTH+j];
end
//NOTE that arriaiigx doesn't support half-rate ddio_out (arriaiigz does).
stratixiv_ddio_out ddio_o (
.areset(~reset_n),
.datainhi(t0),
.datainlo(t1),
.dataout(dataout[i*DATA_WIDTH+j]),
.clkhi (clk),
.clklo (clk),
.muxsel (clk)
);
defparam
ddio_o.use_new_clocking_model = "true",
ddio_o.half_rate_mode = HALF_RATE_MODE,
ddio_o.power_up = HARD_DDIO_POWER_UP,
ddio_o.async_mode = HARD_DDIO_ASYNC_MODE;
end
end
end
endgenerate
endmodule
|
// (C) 2001-2012 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// ***************************************************************************
// File name: write_datapath.v
// ***************************************************************************
`timescale 1 ps / 1 ps
(* altera_attribute = "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF" *)
module DE4_SOPC_ddr2_0_p0_write_datapath(
pll_afi_clk,
reset_n,
force_oct_off,
afi_dqs_en,
phy_ddio_oct_ena,
afi_wdata,
afi_wdata_valid,
afi_dm,
phy_ddio_dq,
phy_ddio_dqs_en,
phy_ddio_wrdata_en,
phy_ddio_wrdata_mask,
seq_num_write_fr_cycle_shifts
);
parameter MEM_ADDRESS_WIDTH = "";
parameter MEM_DM_WIDTH = "";
parameter MEM_CONTROL_WIDTH = "";
parameter MEM_DQ_WIDTH = "";
parameter MEM_READ_DQS_WIDTH = "";
parameter MEM_WRITE_DQS_WIDTH = "";
parameter AFI_ADDRESS_WIDTH = "";
parameter AFI_DATA_MASK_WIDTH = "";
parameter AFI_CONTROL_WIDTH = "";
parameter AFI_DATA_WIDTH = "";
parameter AFI_DQS_WIDTH = "";
parameter NUM_WRITE_PATH_FLOP_STAGES = "";
parameter NUM_WRITE_FR_CYCLE_SHIFTS = "";
localparam RATE_MULT = 2;
localparam DQ_GROUP_WIDTH = MEM_DQ_WIDTH / MEM_WRITE_DQS_WIDTH;
localparam DM_GROUP_WIDTH = MEM_DM_WIDTH / MEM_WRITE_DQS_WIDTH;
input pll_afi_clk;
input reset_n;
input [AFI_DQS_WIDTH-1:0] force_oct_off;
input [AFI_DQS_WIDTH-1:0] afi_dqs_en;
output [AFI_DQS_WIDTH-1:0] phy_ddio_oct_ena;
input [AFI_DATA_WIDTH-1:0] afi_wdata;
input [AFI_DQS_WIDTH-1:0] afi_wdata_valid;
input [AFI_DATA_MASK_WIDTH-1:0] afi_dm;
output [AFI_DATA_WIDTH-1:0] phy_ddio_dq;
output [AFI_DQS_WIDTH-1:0] phy_ddio_dqs_en;
output [AFI_DQS_WIDTH-1:0] phy_ddio_wrdata_en;
output [AFI_DATA_MASK_WIDTH-1:0] phy_ddio_wrdata_mask;
input [MEM_WRITE_DQS_WIDTH * 2 - 1:0] seq_num_write_fr_cycle_shifts;
wire [AFI_DQS_WIDTH-1:0] oct_ena_source = afi_dqs_en;
wire [AFI_DQS_WIDTH-1:0] phy_ddio_dqs_en_pre_shift;
wire [AFI_DQS_WIDTH-1:0] phy_ddio_oct_ena_pre_shift;
wire [AFI_DATA_WIDTH-1:0] phy_ddio_dq_pre_shift;
wire [AFI_DQS_WIDTH-1:0] phy_ddio_wrdata_en_pre_shift;
wire [AFI_DATA_MASK_WIDTH-1:0] phy_ddio_wrdata_mask_pre_shift;
generate
genvar stage;
if (NUM_WRITE_PATH_FLOP_STAGES == 0)
begin
wire [AFI_DQS_WIDTH-1:0] oct_ena_source_extended;
DE4_SOPC_ddr2_0_p0_fr_cycle_extender oct_ena_source_extender(
.clk (pll_afi_clk),
.extend_by (2'b10),
.reset_n (1'b1),
.datain (oct_ena_source),
.dataout (oct_ena_source_extended)
);
defparam oct_ena_source_extender.DATA_WIDTH = MEM_WRITE_DQS_WIDTH;
assign phy_ddio_oct_ena_pre_shift = ~oct_ena_source_extended & ~force_oct_off;
DE4_SOPC_ddr2_0_p0_fr_cycle_shifter afi_dqs_en_shifter(
.clk (pll_afi_clk),
.shift_by (2'b01),
.reset_n (1'b1),
.datain (afi_dqs_en),
.dataout (phy_ddio_dqs_en_pre_shift)
);
defparam afi_dqs_en_shifter.DATA_WIDTH = MEM_WRITE_DQS_WIDTH;
DE4_SOPC_ddr2_0_p0_fr_cycle_shifter afi_wdata_shifter(
.clk (pll_afi_clk),
.shift_by (2'b01),
.reset_n (1'b1),
.datain (afi_wdata),
.dataout (phy_ddio_dq_pre_shift)
);
defparam afi_wdata_shifter.DATA_WIDTH = (MEM_DQ_WIDTH * 2);
DE4_SOPC_ddr2_0_p0_fr_cycle_extender afi_wdata_valid_extender(
.clk (pll_afi_clk),
.extend_by (2'b10),
.reset_n (1'b1),
.datain (afi_wdata_valid),
.dataout (phy_ddio_wrdata_en_pre_shift)
);
defparam afi_wdata_valid_extender.DATA_WIDTH = MEM_WRITE_DQS_WIDTH;
DE4_SOPC_ddr2_0_p0_fr_cycle_shifter afi_dm_shifter(
.clk (pll_afi_clk),
.shift_by (2'b01),
.reset_n (1'b1),
.datain (afi_dm),
.dataout (phy_ddio_wrdata_mask_pre_shift)
);
defparam afi_dm_shifter.DATA_WIDTH = (MEM_DM_WIDTH * 2);
end
else
begin
reg [AFI_DATA_WIDTH-1:0] afi_wdata_r [NUM_WRITE_PATH_FLOP_STAGES-1:0];
reg [AFI_DQS_WIDTH-1:0] afi_wdata_valid_r [NUM_WRITE_PATH_FLOP_STAGES-1:0] /* synthesis dont_merge */;
reg [AFI_DQS_WIDTH-1:0] oct_ena_source_r [NUM_WRITE_PATH_FLOP_STAGES-1:0] /* synthesis dont_merge */;
reg [AFI_DQS_WIDTH-1:0] afi_dqs_en_r [NUM_WRITE_PATH_FLOP_STAGES-1:0];
// phy_ddio_wrdata_mask is tied low during calibration
// the purpose of the assignment is to avoid Quartus from connecting the signal to the sclr pin of the flop
// sclr pin is very slow and causes timing failures
(* altera_attribute = {"-name ALLOW_SYNCH_CTRL_USAGE OFF"}*) reg [AFI_DATA_MASK_WIDTH-1:0] afi_dm_r [NUM_WRITE_PATH_FLOP_STAGES-1:0];
for (stage = 0; stage < NUM_WRITE_PATH_FLOP_STAGES; stage = stage + 1)
begin : stage_gen
always @(posedge pll_afi_clk)
begin
oct_ena_source_r[stage] <= (stage == 0) ? oct_ena_source : oct_ena_source_r[stage-1];
afi_wdata_r[stage] <= (stage == 0) ? afi_wdata : afi_wdata_r[stage-1];
afi_wdata_valid_r[stage] <= (stage == 0) ? afi_wdata_valid : afi_wdata_valid_r[stage-1];
afi_dm_r[stage] <= (stage == 0) ? afi_dm : afi_dm_r[stage-1];
afi_dqs_en_r[stage] <= (stage == 0) ? afi_dqs_en : afi_dqs_en_r[stage-1];
end
end
assign phy_ddio_dq_pre_shift = afi_wdata_r[NUM_WRITE_PATH_FLOP_STAGES-1];
assign phy_ddio_wrdata_en_pre_shift = afi_wdata_valid_r[NUM_WRITE_PATH_FLOP_STAGES-1];
assign phy_ddio_wrdata_mask_pre_shift = afi_dm_r[NUM_WRITE_PATH_FLOP_STAGES-1];
assign phy_ddio_dqs_en_pre_shift = afi_dqs_en_r[NUM_WRITE_PATH_FLOP_STAGES-1];
wire [AFI_DQS_WIDTH-1:0] oct_ena_source_extended;
DE4_SOPC_ddr2_0_p0_fr_cycle_extender oct_ena_source_extender(
.clk (pll_afi_clk),
.reset_n (1'b1),
.extend_by (2'b10),
.datain ((NUM_WRITE_PATH_FLOP_STAGES == 1) ? oct_ena_source : oct_ena_source_r[NUM_WRITE_PATH_FLOP_STAGES - 2]),
.dataout (oct_ena_source_extended)
);
defparam oct_ena_source_extender.DATA_WIDTH = MEM_WRITE_DQS_WIDTH;
wire [AFI_DQS_WIDTH-1:0] oct_ena_source_extended_shifted;
DE4_SOPC_ddr2_0_p0_fr_cycle_shifter oct_ena_source_extended_shifter(
.clk (pll_afi_clk),
.shift_by (2'b01),
.reset_n (1'b1),
.datain (oct_ena_source_extended),
.dataout (oct_ena_source_extended_shifted)
);
defparam oct_ena_source_extended_shifter.DATA_WIDTH = MEM_WRITE_DQS_WIDTH;
assign phy_ddio_oct_ena_pre_shift = ~oct_ena_source_extended_shifted & ~force_oct_off;
end
endgenerate
generate
genvar i, t;
for (i=0; i<MEM_WRITE_DQS_WIDTH; i=i+1)
begin: bs_wr_grp
wire [1:0] seq_num_write_fr_cycle_shifts_per_group = seq_num_write_fr_cycle_shifts[2 * (i + 1) - 1 : i * 2];
wire [1:0] shift_fr_cycle =
(NUM_WRITE_FR_CYCLE_SHIFTS == 0) ? 2'b00 : (
(NUM_WRITE_FR_CYCLE_SHIFTS == 1) ? 2'b01 : (
(NUM_WRITE_FR_CYCLE_SHIFTS == 2) ? 2'b10 : (
(NUM_WRITE_FR_CYCLE_SHIFTS == 3) ? 2'b11 : (
seq_num_write_fr_cycle_shifts_per_group))));
wire [AFI_DQS_WIDTH / MEM_WRITE_DQS_WIDTH - 1:0] grp_oct_ena_pre_shift;
wire [AFI_DQS_WIDTH / MEM_WRITE_DQS_WIDTH - 1:0] grp_oct_ena;
wire [AFI_DQS_WIDTH / MEM_WRITE_DQS_WIDTH - 1:0] grp_dqs_en_pre_shift;
wire [AFI_DQS_WIDTH / MEM_WRITE_DQS_WIDTH - 1:0] grp_dqs_en;
wire [AFI_DATA_WIDTH / MEM_WRITE_DQS_WIDTH - 1:0] grp_dq_pre_shift;
wire [AFI_DATA_WIDTH / MEM_WRITE_DQS_WIDTH - 1:0] grp_dq;
wire [AFI_DQS_WIDTH / MEM_WRITE_DQS_WIDTH - 1:0] grp_wrdata_en_pre_shift;
wire [AFI_DQS_WIDTH / MEM_WRITE_DQS_WIDTH - 1:0] grp_wrdata_en;
wire [AFI_DATA_MASK_WIDTH / MEM_WRITE_DQS_WIDTH - 1:0] grp_wrdata_mask_pre_shift;
wire [AFI_DATA_MASK_WIDTH / MEM_WRITE_DQS_WIDTH - 1:0] grp_wrdata_mask;
DE4_SOPC_ddr2_0_p0_fr_cycle_shifter dq_shifter(
.clk (pll_afi_clk),
.shift_by (shift_fr_cycle),
.reset_n (1'b1),
.datain (grp_dq_pre_shift),
.dataout (grp_dq)
);
defparam dq_shifter.DATA_WIDTH = (DQ_GROUP_WIDTH * 2);
DE4_SOPC_ddr2_0_p0_fr_cycle_shifter wrdata_mask_shifter(
.clk (pll_afi_clk),
.shift_by (shift_fr_cycle),
.reset_n (1'b1),
.datain (grp_wrdata_mask_pre_shift),
.dataout (grp_wrdata_mask)
);
defparam wrdata_mask_shifter.DATA_WIDTH = (DM_GROUP_WIDTH * 2);
DE4_SOPC_ddr2_0_p0_fr_cycle_shifter wrdata_en_shifter(
.clk (pll_afi_clk),
.shift_by (shift_fr_cycle),
.reset_n (1'b1),
.datain (grp_wrdata_en_pre_shift),
.dataout (grp_wrdata_en)
);
defparam wrdata_en_shifter.DATA_WIDTH = 1;
DE4_SOPC_ddr2_0_p0_fr_cycle_shifter dqs_en_shifter(
.clk (pll_afi_clk),
.shift_by (shift_fr_cycle),
.reset_n (1'b1),
.datain (grp_dqs_en_pre_shift),
.dataout (grp_dqs_en)
);
defparam dqs_en_shifter.DATA_WIDTH = 1;
DE4_SOPC_ddr2_0_p0_fr_cycle_shifter oct_ena_shifter(
.clk (pll_afi_clk),
.shift_by (shift_fr_cycle),
.reset_n (1'b1),
.datain (grp_oct_ena_pre_shift),
.dataout (grp_oct_ena)
);
defparam oct_ena_shifter.DATA_WIDTH = 1;
for (t=0; t<RATE_MULT*2; t=t+1)
begin: extract_ddr_grp
wire [DQ_GROUP_WIDTH-1:0] dq_t_pre_shift = phy_ddio_dq_pre_shift[DQ_GROUP_WIDTH * (i+1) + MEM_DQ_WIDTH * t - 1 : DQ_GROUP_WIDTH * i + MEM_DQ_WIDTH * t];
assign grp_dq_pre_shift[(t+1) * DQ_GROUP_WIDTH - 1 : t * DQ_GROUP_WIDTH] = dq_t_pre_shift;
wire [DQ_GROUP_WIDTH-1:0] dq_t = grp_dq[(t+1) * DQ_GROUP_WIDTH - 1 : t * DQ_GROUP_WIDTH];
assign phy_ddio_dq[DQ_GROUP_WIDTH * (i+1) + MEM_DQ_WIDTH * t - 1 : DQ_GROUP_WIDTH * i + MEM_DQ_WIDTH * t] = dq_t;
wire [DM_GROUP_WIDTH-1:0] wrdata_mask_t_pre_shift = phy_ddio_wrdata_mask_pre_shift[DM_GROUP_WIDTH * (i+1) + MEM_DM_WIDTH * t - 1 : DM_GROUP_WIDTH * i + MEM_DM_WIDTH * t];
assign grp_wrdata_mask_pre_shift[(t+1) * DM_GROUP_WIDTH - 1 : t * DM_GROUP_WIDTH] = wrdata_mask_t_pre_shift;
wire [DM_GROUP_WIDTH-1:0] wrdata_mask_t = grp_wrdata_mask[(t+1) * DM_GROUP_WIDTH - 1 : t * DM_GROUP_WIDTH];
assign phy_ddio_wrdata_mask[DM_GROUP_WIDTH * (i+1) + MEM_DM_WIDTH * t - 1 : DM_GROUP_WIDTH * i + MEM_DM_WIDTH * t] = wrdata_mask_t;
end
for (t=0; t<RATE_MULT; t=t+1)
begin: extract_sdr_grp
assign grp_oct_ena_pre_shift[t] = phy_ddio_oct_ena_pre_shift[i + MEM_WRITE_DQS_WIDTH * t];
assign phy_ddio_oct_ena[i + MEM_WRITE_DQS_WIDTH * t] = grp_oct_ena[t];
assign grp_dqs_en_pre_shift[t] = phy_ddio_dqs_en_pre_shift[i + MEM_WRITE_DQS_WIDTH * t];
assign phy_ddio_dqs_en[i + MEM_WRITE_DQS_WIDTH * t] = grp_dqs_en[t];
assign grp_wrdata_en_pre_shift[t] = phy_ddio_wrdata_en_pre_shift[i + MEM_WRITE_DQS_WIDTH * t];
assign phy_ddio_wrdata_en[i + MEM_WRITE_DQS_WIDTH * t] = grp_wrdata_en[t];
end
end
endgenerate
endmodule
|
// DE4_SOPC_ddr2_0_s0.v
// This file was auto-generated from qsys_sequencer_110_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 12.1 177 at 2013.01.18.10:33:18
`timescale 1 ps / 1 ps
module DE4_SOPC_ddr2_0_s0 (
input wire avl_clk, // avl_clk.clk
input wire avl_reset_n, // avl_reset.reset_n
input wire phy_clk, // phy.phy_clk
input wire phy_reset_n, // .phy_reset_n
output wire [3:0] phy_read_latency_counter, // .phy_read_latency_counter
output wire [5:0] phy_afi_wlat, // .phy_afi_wlat
output wire [5:0] phy_afi_rlat, // .phy_afi_rlat
output wire [7:0] phy_read_increment_vfifo_fr, // .phy_read_increment_vfifo_fr
output wire [7:0] phy_read_increment_vfifo_hr, // .phy_read_increment_vfifo_hr
output wire [7:0] phy_read_increment_vfifo_qr, // .phy_read_increment_vfifo_qr
output wire phy_reset_mem_stable, // .phy_reset_mem_stable
output wire phy_cal_success, // .phy_cal_success
output wire phy_cal_fail, // .phy_cal_fail
output wire [31:0] phy_cal_debug_info, // .phy_cal_debug_info
output wire [7:0] phy_read_fifo_reset, // .phy_read_fifo_reset
output wire [7:0] phy_vfifo_rd_en_override, // .phy_vfifo_rd_en_override
input wire [255:0] phy_read_fifo_q, // .phy_read_fifo_q
output wire [15:0] phy_write_fr_cycle_shifts, // .phy_write_fr_cycle_shifts
output wire phy_mux_sel, // mux_sel.mux_sel
input wire [7:0] calib_skip_steps, // calib.calib_skip_steps
input wire afi_clk, // afi_clk.clk
input wire afi_reset_n, // afi_reset.reset_n
output wire [27:0] afi_addr, // afi.afi_addr
output wire [5:0] afi_ba, // .afi_ba
output wire [1:0] afi_cs_n, // .afi_cs_n
output wire [1:0] afi_cke, // .afi_cke
output wire [1:0] afi_odt, // .afi_odt
output wire [1:0] afi_ras_n, // .afi_ras_n
output wire [1:0] afi_cas_n, // .afi_cas_n
output wire [1:0] afi_we_n, // .afi_we_n
output wire [15:0] afi_dqs_burst, // .afi_dqs_burst
output wire [255:0] afi_wdata, // .afi_wdata
output wire [15:0] afi_wdata_valid, // .afi_wdata_valid
output wire [31:0] afi_dm, // .afi_dm
output wire [1:0] afi_rdata_en, // .afi_rdata_en
output wire [1:0] afi_rdata_en_full, // .afi_rdata_en_full
input wire [255:0] afi_rdata, // .afi_rdata
input wire [1:0] afi_rdata_valid, // .afi_rdata_valid
output wire scc_data, // scc.scc_data
output wire [7:0] scc_dqs_ena, // .scc_dqs_ena
output wire [7:0] scc_dqs_io_ena, // .scc_dqs_io_ena
output wire [63:0] scc_dq_ena, // .scc_dq_ena
output wire [7:0] scc_dm_ena, // .scc_dm_ena
input wire [7:0] capture_strobe_tracking, // .capture_strobe_tracking
output wire [0:0] scc_upd, // .scc_upd
input wire afi_init_req, // afi_init_cal_req.afi_init_req
input wire afi_cal_req, // .afi_cal_req
input wire scc_clk, // scc_clk.clk
input wire reset_n_scc_clk // scc_reset.reset_n
);
wire cpu_inst_data_master_waitrequest; // cpu_inst_data_master_translator:av_waitrequest -> cpu_inst:d_waitrequest
wire [31:0] cpu_inst_data_master_writedata; // cpu_inst:d_writedata -> cpu_inst_data_master_translator:av_writedata
wire [19:0] cpu_inst_data_master_address; // cpu_inst:d_address -> cpu_inst_data_master_translator:av_address
wire cpu_inst_data_master_write; // cpu_inst:d_write -> cpu_inst_data_master_translator:av_write
wire cpu_inst_data_master_read; // cpu_inst:d_read -> cpu_inst_data_master_translator:av_read
wire [31:0] cpu_inst_data_master_readdata; // cpu_inst_data_master_translator:av_readdata -> cpu_inst:d_readdata
wire [3:0] cpu_inst_data_master_byteenable; // cpu_inst:d_byteenable -> cpu_inst_data_master_translator:av_byteenable
wire cpu_inst_instruction_master_waitrequest; // cpu_inst_instruction_master_translator:av_waitrequest -> cpu_inst:i_waitrequest
wire [16:0] cpu_inst_instruction_master_address; // cpu_inst:i_address -> cpu_inst_instruction_master_translator:av_address
wire cpu_inst_instruction_master_read; // cpu_inst:i_read -> cpu_inst_instruction_master_translator:av_read
wire [31:0] cpu_inst_instruction_master_readdata; // cpu_inst_instruction_master_translator:av_readdata -> cpu_inst:i_readdata
wire sequencer_phy_mgr_inst_avl_translator_avalon_anti_slave_0_waitrequest; // sequencer_phy_mgr_inst:avl_waitrequest -> sequencer_phy_mgr_inst_avl_translator:av_waitrequest
wire [31:0] sequencer_phy_mgr_inst_avl_translator_avalon_anti_slave_0_writedata; // sequencer_phy_mgr_inst_avl_translator:av_writedata -> sequencer_phy_mgr_inst:avl_writedata
wire [12:0] sequencer_phy_mgr_inst_avl_translator_avalon_anti_slave_0_address; // sequencer_phy_mgr_inst_avl_translator:av_address -> sequencer_phy_mgr_inst:avl_address
wire sequencer_phy_mgr_inst_avl_translator_avalon_anti_slave_0_write; // sequencer_phy_mgr_inst_avl_translator:av_write -> sequencer_phy_mgr_inst:avl_write
wire sequencer_phy_mgr_inst_avl_translator_avalon_anti_slave_0_read; // sequencer_phy_mgr_inst_avl_translator:av_read -> sequencer_phy_mgr_inst:avl_read
wire [31:0] sequencer_phy_mgr_inst_avl_translator_avalon_anti_slave_0_readdata; // sequencer_phy_mgr_inst:avl_readdata -> sequencer_phy_mgr_inst_avl_translator:av_readdata
wire sequencer_data_mgr_inst_avl_translator_avalon_anti_slave_0_waitrequest; // sequencer_data_mgr_inst:avl_waitrequest -> sequencer_data_mgr_inst_avl_translator:av_waitrequest
wire [31:0] sequencer_data_mgr_inst_avl_translator_avalon_anti_slave_0_writedata; // sequencer_data_mgr_inst_avl_translator:av_writedata -> sequencer_data_mgr_inst:avl_writedata
wire [12:0] sequencer_data_mgr_inst_avl_translator_avalon_anti_slave_0_address; // sequencer_data_mgr_inst_avl_translator:av_address -> sequencer_data_mgr_inst:avl_address
wire sequencer_data_mgr_inst_avl_translator_avalon_anti_slave_0_write; // sequencer_data_mgr_inst_avl_translator:av_write -> sequencer_data_mgr_inst:avl_write
wire sequencer_data_mgr_inst_avl_translator_avalon_anti_slave_0_read; // sequencer_data_mgr_inst_avl_translator:av_read -> sequencer_data_mgr_inst:avl_read
wire [31:0] sequencer_data_mgr_inst_avl_translator_avalon_anti_slave_0_readdata; // sequencer_data_mgr_inst:avl_readdata -> sequencer_data_mgr_inst_avl_translator:av_readdata
wire sequencer_rw_mgr_inst_avl_translator_avalon_anti_slave_0_waitrequest; // sequencer_rw_mgr_inst:avl_waitrequest -> sequencer_rw_mgr_inst_avl_translator:av_waitrequest
wire [31:0] sequencer_rw_mgr_inst_avl_translator_avalon_anti_slave_0_writedata; // sequencer_rw_mgr_inst_avl_translator:av_writedata -> sequencer_rw_mgr_inst:avl_writedata
wire [12:0] sequencer_rw_mgr_inst_avl_translator_avalon_anti_slave_0_address; // sequencer_rw_mgr_inst_avl_translator:av_address -> sequencer_rw_mgr_inst:avl_address
wire sequencer_rw_mgr_inst_avl_translator_avalon_anti_slave_0_write; // sequencer_rw_mgr_inst_avl_translator:av_write -> sequencer_rw_mgr_inst:avl_write
wire sequencer_rw_mgr_inst_avl_translator_avalon_anti_slave_0_read; // sequencer_rw_mgr_inst_avl_translator:av_read -> sequencer_rw_mgr_inst:avl_read
wire [31:0] sequencer_rw_mgr_inst_avl_translator_avalon_anti_slave_0_readdata; // sequencer_rw_mgr_inst:avl_readdata -> sequencer_rw_mgr_inst_avl_translator:av_readdata
wire [31:0] sequencer_mem_s1_translator_avalon_anti_slave_0_writedata; // sequencer_mem_s1_translator:av_writedata -> sequencer_mem:s1_writedata
wire [11:0] sequencer_mem_s1_translator_avalon_anti_slave_0_address; // sequencer_mem_s1_translator:av_address -> sequencer_mem:s1_address
wire sequencer_mem_s1_translator_avalon_anti_slave_0_chipselect; // sequencer_mem_s1_translator:av_chipselect -> sequencer_mem:s1_chipselect
wire sequencer_mem_s1_translator_avalon_anti_slave_0_clken; // sequencer_mem_s1_translator:av_clken -> sequencer_mem:s1_clken
wire sequencer_mem_s1_translator_avalon_anti_slave_0_write; // sequencer_mem_s1_translator:av_write -> sequencer_mem:s1_write
wire [31:0] sequencer_mem_s1_translator_avalon_anti_slave_0_readdata; // sequencer_mem:s1_readdata -> sequencer_mem_s1_translator:av_readdata
wire [3:0] sequencer_mem_s1_translator_avalon_anti_slave_0_byteenable; // sequencer_mem_s1_translator:av_byteenable -> sequencer_mem:s1_be
wire sequencer_scc_mgr_inst_avl_translator_avalon_anti_slave_0_waitrequest; // sequencer_scc_mgr_inst:avl_waitrequest -> sequencer_scc_mgr_inst_avl_translator:av_waitrequest
wire [31:0] sequencer_scc_mgr_inst_avl_translator_avalon_anti_slave_0_writedata; // sequencer_scc_mgr_inst_avl_translator:av_writedata -> sequencer_scc_mgr_inst:avl_writedata
wire [12:0] sequencer_scc_mgr_inst_avl_translator_avalon_anti_slave_0_address; // sequencer_scc_mgr_inst_avl_translator:av_address -> sequencer_scc_mgr_inst:avl_address
wire sequencer_scc_mgr_inst_avl_translator_avalon_anti_slave_0_write; // sequencer_scc_mgr_inst_avl_translator:av_write -> sequencer_scc_mgr_inst:avl_write
wire sequencer_scc_mgr_inst_avl_translator_avalon_anti_slave_0_read; // sequencer_scc_mgr_inst_avl_translator:av_read -> sequencer_scc_mgr_inst:avl_read
wire [31:0] sequencer_scc_mgr_inst_avl_translator_avalon_anti_slave_0_readdata; // sequencer_scc_mgr_inst:avl_readdata -> sequencer_scc_mgr_inst_avl_translator:av_readdata
wire sequencer_reg_file_inst_avl_translator_avalon_anti_slave_0_waitrequest; // sequencer_reg_file_inst:avl_waitrequest -> sequencer_reg_file_inst_avl_translator:av_waitrequest
wire [31:0] sequencer_reg_file_inst_avl_translator_avalon_anti_slave_0_writedata; // sequencer_reg_file_inst_avl_translator:av_writedata -> sequencer_reg_file_inst:avl_writedata
wire [3:0] sequencer_reg_file_inst_avl_translator_avalon_anti_slave_0_address; // sequencer_reg_file_inst_avl_translator:av_address -> sequencer_reg_file_inst:avl_address
wire sequencer_reg_file_inst_avl_translator_avalon_anti_slave_0_write; // sequencer_reg_file_inst_avl_translator:av_write -> sequencer_reg_file_inst:avl_write
wire sequencer_reg_file_inst_avl_translator_avalon_anti_slave_0_read; // sequencer_reg_file_inst_avl_translator:av_read -> sequencer_reg_file_inst:avl_read
wire [31:0] sequencer_reg_file_inst_avl_translator_avalon_anti_slave_0_readdata; // sequencer_reg_file_inst:avl_readdata -> sequencer_reg_file_inst_avl_translator:av_readdata
wire [3:0] sequencer_reg_file_inst_avl_translator_avalon_anti_slave_0_byteenable; // sequencer_reg_file_inst_avl_translator:av_byteenable -> sequencer_reg_file_inst:avl_be
wire cpu_inst_data_master_translator_avalon_universal_master_0_waitrequest; // cpu_inst_data_master_translator_avalon_universal_master_0_agent:av_waitrequest -> cpu_inst_data_master_translator:uav_waitrequest
wire [2:0] cpu_inst_data_master_translator_avalon_universal_master_0_burstcount; // cpu_inst_data_master_translator:uav_burstcount -> cpu_inst_data_master_translator_avalon_universal_master_0_agent:av_burstcount
wire [31:0] cpu_inst_data_master_translator_avalon_universal_master_0_writedata; // cpu_inst_data_master_translator:uav_writedata -> cpu_inst_data_master_translator_avalon_universal_master_0_agent:av_writedata
wire [19:0] cpu_inst_data_master_translator_avalon_universal_master_0_address; // cpu_inst_data_master_translator:uav_address -> cpu_inst_data_master_translator_avalon_universal_master_0_agent:av_address
wire cpu_inst_data_master_translator_avalon_universal_master_0_lock; // cpu_inst_data_master_translator:uav_lock -> cpu_inst_data_master_translator_avalon_universal_master_0_agent:av_lock
wire cpu_inst_data_master_translator_avalon_universal_master_0_write; // cpu_inst_data_master_translator:uav_write -> cpu_inst_data_master_translator_avalon_universal_master_0_agent:av_write
wire cpu_inst_data_master_translator_avalon_universal_master_0_read; // cpu_inst_data_master_translator:uav_read -> cpu_inst_data_master_translator_avalon_universal_master_0_agent:av_read
wire [31:0] cpu_inst_data_master_translator_avalon_universal_master_0_readdata; // cpu_inst_data_master_translator_avalon_universal_master_0_agent:av_readdata -> cpu_inst_data_master_translator:uav_readdata
wire cpu_inst_data_master_translator_avalon_universal_master_0_debugaccess; // cpu_inst_data_master_translator:uav_debugaccess -> cpu_inst_data_master_translator_avalon_universal_master_0_agent:av_debugaccess
wire [3:0] cpu_inst_data_master_translator_avalon_universal_master_0_byteenable; // cpu_inst_data_master_translator:uav_byteenable -> cpu_inst_data_master_translator_avalon_universal_master_0_agent:av_byteenable
wire cpu_inst_data_master_translator_avalon_universal_master_0_readdatavalid; // cpu_inst_data_master_translator_avalon_universal_master_0_agent:av_readdatavalid -> cpu_inst_data_master_translator:uav_readdatavalid
wire cpu_inst_instruction_master_translator_avalon_universal_master_0_waitrequest; // cpu_inst_instruction_master_translator_avalon_universal_master_0_agent:av_waitrequest -> cpu_inst_instruction_master_translator:uav_waitrequest
wire [2:0] cpu_inst_instruction_master_translator_avalon_universal_master_0_burstcount; // cpu_inst_instruction_master_translator:uav_burstcount -> cpu_inst_instruction_master_translator_avalon_universal_master_0_agent:av_burstcount
wire [31:0] cpu_inst_instruction_master_translator_avalon_universal_master_0_writedata; // cpu_inst_instruction_master_translator:uav_writedata -> cpu_inst_instruction_master_translator_avalon_universal_master_0_agent:av_writedata
wire [19:0] cpu_inst_instruction_master_translator_avalon_universal_master_0_address; // cpu_inst_instruction_master_translator:uav_address -> cpu_inst_instruction_master_translator_avalon_universal_master_0_agent:av_address
wire cpu_inst_instruction_master_translator_avalon_universal_master_0_lock; // cpu_inst_instruction_master_translator:uav_lock -> cpu_inst_instruction_master_translator_avalon_universal_master_0_agent:av_lock
wire cpu_inst_instruction_master_translator_avalon_universal_master_0_write; // cpu_inst_instruction_master_translator:uav_write -> cpu_inst_instruction_master_translator_avalon_universal_master_0_agent:av_write
wire cpu_inst_instruction_master_translator_avalon_universal_master_0_read; // cpu_inst_instruction_master_translator:uav_read -> cpu_inst_instruction_master_translator_avalon_universal_master_0_agent:av_read
wire [31:0] cpu_inst_instruction_master_translator_avalon_universal_master_0_readdata; // cpu_inst_instruction_master_translator_avalon_universal_master_0_agent:av_readdata -> cpu_inst_instruction_master_translator:uav_readdata
wire cpu_inst_instruction_master_translator_avalon_universal_master_0_debugaccess; // cpu_inst_instruction_master_translator:uav_debugaccess -> cpu_inst_instruction_master_translator_avalon_universal_master_0_agent:av_debugaccess
wire [3:0] cpu_inst_instruction_master_translator_avalon_universal_master_0_byteenable; // cpu_inst_instruction_master_translator:uav_byteenable -> cpu_inst_instruction_master_translator_avalon_universal_master_0_agent:av_byteenable
wire cpu_inst_instruction_master_translator_avalon_universal_master_0_readdatavalid; // cpu_inst_instruction_master_translator_avalon_universal_master_0_agent:av_readdatavalid -> cpu_inst_instruction_master_translator:uav_readdatavalid
wire sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_waitrequest; // sequencer_phy_mgr_inst_avl_translator:uav_waitrequest -> sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_waitrequest
wire [2:0] sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_burstcount; // sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_burstcount -> sequencer_phy_mgr_inst_avl_translator:uav_burstcount
wire [31:0] sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_writedata; // sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_writedata -> sequencer_phy_mgr_inst_avl_translator:uav_writedata
wire [19:0] sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_address; // sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_address -> sequencer_phy_mgr_inst_avl_translator:uav_address
wire sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_write; // sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_write -> sequencer_phy_mgr_inst_avl_translator:uav_write
wire sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_lock; // sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_lock -> sequencer_phy_mgr_inst_avl_translator:uav_lock
wire sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_read; // sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_read -> sequencer_phy_mgr_inst_avl_translator:uav_read
wire [31:0] sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_readdata; // sequencer_phy_mgr_inst_avl_translator:uav_readdata -> sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_readdata
wire sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // sequencer_phy_mgr_inst_avl_translator:uav_readdatavalid -> sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_readdatavalid
wire sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_debugaccess; // sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_debugaccess -> sequencer_phy_mgr_inst_avl_translator:uav_debugaccess
wire [3:0] sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_byteenable; // sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_byteenable -> sequencer_phy_mgr_inst_avl_translator:uav_byteenable
wire sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
wire sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_valid; // sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_source_valid -> sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
wire sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
wire [93:0] sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_data; // sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_source_data -> sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
wire sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_ready; // sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_source_ready
wire sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
wire sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_sink_valid
wire sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
wire [93:0] sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_sink_data
wire sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_sink_ready -> sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
wire sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
wire [31:0] sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
wire sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
wire sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_waitrequest; // sequencer_data_mgr_inst_avl_translator:uav_waitrequest -> sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_waitrequest
wire [2:0] sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_burstcount; // sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_burstcount -> sequencer_data_mgr_inst_avl_translator:uav_burstcount
wire [31:0] sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_writedata; // sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_writedata -> sequencer_data_mgr_inst_avl_translator:uav_writedata
wire [19:0] sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_address; // sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_address -> sequencer_data_mgr_inst_avl_translator:uav_address
wire sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_write; // sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_write -> sequencer_data_mgr_inst_avl_translator:uav_write
wire sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_lock; // sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_lock -> sequencer_data_mgr_inst_avl_translator:uav_lock
wire sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_read; // sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_read -> sequencer_data_mgr_inst_avl_translator:uav_read
wire [31:0] sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_readdata; // sequencer_data_mgr_inst_avl_translator:uav_readdata -> sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_readdata
wire sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // sequencer_data_mgr_inst_avl_translator:uav_readdatavalid -> sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_readdatavalid
wire sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_debugaccess; // sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_debugaccess -> sequencer_data_mgr_inst_avl_translator:uav_debugaccess
wire [3:0] sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_byteenable; // sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_byteenable -> sequencer_data_mgr_inst_avl_translator:uav_byteenable
wire sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
wire sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_valid; // sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_source_valid -> sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
wire sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
wire [93:0] sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_data; // sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_source_data -> sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
wire sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_ready; // sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_source_ready
wire sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
wire sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_sink_valid
wire sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
wire [93:0] sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_sink_data
wire sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_sink_ready -> sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
wire sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
wire [31:0] sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
wire sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
wire sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_waitrequest; // sequencer_rw_mgr_inst_avl_translator:uav_waitrequest -> sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_waitrequest
wire [2:0] sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_burstcount; // sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_burstcount -> sequencer_rw_mgr_inst_avl_translator:uav_burstcount
wire [31:0] sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_writedata; // sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_writedata -> sequencer_rw_mgr_inst_avl_translator:uav_writedata
wire [19:0] sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_address; // sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_address -> sequencer_rw_mgr_inst_avl_translator:uav_address
wire sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_write; // sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_write -> sequencer_rw_mgr_inst_avl_translator:uav_write
wire sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_lock; // sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_lock -> sequencer_rw_mgr_inst_avl_translator:uav_lock
wire sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_read; // sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_read -> sequencer_rw_mgr_inst_avl_translator:uav_read
wire [31:0] sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_readdata; // sequencer_rw_mgr_inst_avl_translator:uav_readdata -> sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_readdata
wire sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // sequencer_rw_mgr_inst_avl_translator:uav_readdatavalid -> sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_readdatavalid
wire sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_debugaccess; // sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_debugaccess -> sequencer_rw_mgr_inst_avl_translator:uav_debugaccess
wire [3:0] sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_byteenable; // sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_byteenable -> sequencer_rw_mgr_inst_avl_translator:uav_byteenable
wire sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
wire sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_valid; // sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_source_valid -> sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
wire sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
wire [93:0] sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_data; // sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_source_data -> sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
wire sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_ready; // sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_source_ready
wire sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
wire sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_sink_valid
wire sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
wire [93:0] sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_sink_data
wire sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_sink_ready -> sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
wire sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
wire [31:0] sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
wire sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
wire sequencer_mem_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest; // sequencer_mem_s1_translator:uav_waitrequest -> sequencer_mem_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest
wire [2:0] sequencer_mem_s1_translator_avalon_universal_slave_0_agent_m0_burstcount; // sequencer_mem_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> sequencer_mem_s1_translator:uav_burstcount
wire [31:0] sequencer_mem_s1_translator_avalon_universal_slave_0_agent_m0_writedata; // sequencer_mem_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> sequencer_mem_s1_translator:uav_writedata
wire [19:0] sequencer_mem_s1_translator_avalon_universal_slave_0_agent_m0_address; // sequencer_mem_s1_translator_avalon_universal_slave_0_agent:m0_address -> sequencer_mem_s1_translator:uav_address
wire sequencer_mem_s1_translator_avalon_universal_slave_0_agent_m0_write; // sequencer_mem_s1_translator_avalon_universal_slave_0_agent:m0_write -> sequencer_mem_s1_translator:uav_write
wire sequencer_mem_s1_translator_avalon_universal_slave_0_agent_m0_lock; // sequencer_mem_s1_translator_avalon_universal_slave_0_agent:m0_lock -> sequencer_mem_s1_translator:uav_lock
wire sequencer_mem_s1_translator_avalon_universal_slave_0_agent_m0_read; // sequencer_mem_s1_translator_avalon_universal_slave_0_agent:m0_read -> sequencer_mem_s1_translator:uav_read
wire [31:0] sequencer_mem_s1_translator_avalon_universal_slave_0_agent_m0_readdata; // sequencer_mem_s1_translator:uav_readdata -> sequencer_mem_s1_translator_avalon_universal_slave_0_agent:m0_readdata
wire sequencer_mem_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // sequencer_mem_s1_translator:uav_readdatavalid -> sequencer_mem_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid
wire sequencer_mem_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess; // sequencer_mem_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> sequencer_mem_s1_translator:uav_debugaccess
wire [3:0] sequencer_mem_s1_translator_avalon_universal_slave_0_agent_m0_byteenable; // sequencer_mem_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> sequencer_mem_s1_translator:uav_byteenable
wire sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // sequencer_mem_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
wire sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rf_source_valid; // sequencer_mem_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
wire sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // sequencer_mem_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
wire [93:0] sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rf_source_data; // sequencer_mem_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
wire sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rf_source_ready; // sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> sequencer_mem_s1_translator_avalon_universal_slave_0_agent:rf_source_ready
wire sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> sequencer_mem_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
wire sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> sequencer_mem_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid
wire sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> sequencer_mem_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
wire [93:0] sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> sequencer_mem_s1_translator_avalon_universal_slave_0_agent:rf_sink_data
wire sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // sequencer_mem_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
wire sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // sequencer_mem_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> sequencer_mem_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
wire [31:0] sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // sequencer_mem_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> sequencer_mem_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
wire sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // sequencer_mem_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> sequencer_mem_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
wire sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_waitrequest; // sequencer_scc_mgr_inst_avl_translator:uav_waitrequest -> sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_waitrequest
wire [2:0] sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_burstcount; // sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_burstcount -> sequencer_scc_mgr_inst_avl_translator:uav_burstcount
wire [31:0] sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_writedata; // sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_writedata -> sequencer_scc_mgr_inst_avl_translator:uav_writedata
wire [19:0] sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_address; // sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_address -> sequencer_scc_mgr_inst_avl_translator:uav_address
wire sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_write; // sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_write -> sequencer_scc_mgr_inst_avl_translator:uav_write
wire sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_lock; // sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_lock -> sequencer_scc_mgr_inst_avl_translator:uav_lock
wire sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_read; // sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_read -> sequencer_scc_mgr_inst_avl_translator:uav_read
wire [31:0] sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_readdata; // sequencer_scc_mgr_inst_avl_translator:uav_readdata -> sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_readdata
wire sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // sequencer_scc_mgr_inst_avl_translator:uav_readdatavalid -> sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_readdatavalid
wire sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_debugaccess; // sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_debugaccess -> sequencer_scc_mgr_inst_avl_translator:uav_debugaccess
wire [3:0] sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_byteenable; // sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_byteenable -> sequencer_scc_mgr_inst_avl_translator:uav_byteenable
wire sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
wire sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_valid; // sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_source_valid -> sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
wire sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
wire [93:0] sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_data; // sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_source_data -> sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
wire sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_ready; // sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_source_ready
wire sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
wire sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_sink_valid
wire sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
wire [93:0] sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_sink_data
wire sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_sink_ready -> sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
wire sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
wire [31:0] sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
wire sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
wire sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_m0_waitrequest; // sequencer_reg_file_inst_avl_translator:uav_waitrequest -> sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent:m0_waitrequest
wire [2:0] sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_m0_burstcount; // sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent:m0_burstcount -> sequencer_reg_file_inst_avl_translator:uav_burstcount
wire [31:0] sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_m0_writedata; // sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent:m0_writedata -> sequencer_reg_file_inst_avl_translator:uav_writedata
wire [19:0] sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_m0_address; // sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent:m0_address -> sequencer_reg_file_inst_avl_translator:uav_address
wire sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_m0_write; // sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent:m0_write -> sequencer_reg_file_inst_avl_translator:uav_write
wire sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_m0_lock; // sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent:m0_lock -> sequencer_reg_file_inst_avl_translator:uav_lock
wire sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_m0_read; // sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent:m0_read -> sequencer_reg_file_inst_avl_translator:uav_read
wire [31:0] sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_m0_readdata; // sequencer_reg_file_inst_avl_translator:uav_readdata -> sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent:m0_readdata
wire sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // sequencer_reg_file_inst_avl_translator:uav_readdatavalid -> sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent:m0_readdatavalid
wire sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_m0_debugaccess; // sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent:m0_debugaccess -> sequencer_reg_file_inst_avl_translator:uav_debugaccess
wire [3:0] sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_m0_byteenable; // sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent:m0_byteenable -> sequencer_reg_file_inst_avl_translator:uav_byteenable
wire sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
wire sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_valid; // sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent:rf_source_valid -> sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
wire sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
wire [93:0] sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_data; // sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent:rf_source_data -> sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
wire sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_ready; // sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent:rf_source_ready
wire sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
wire sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent:rf_sink_valid
wire sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
wire [93:0] sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent:rf_sink_data
wire sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent:rf_sink_ready -> sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
wire sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
wire [31:0] sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
wire sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
wire cpu_inst_data_master_translator_avalon_universal_master_0_agent_cp_endofpacket; // cpu_inst_data_master_translator_avalon_universal_master_0_agent:cp_endofpacket -> addr_router:sink_endofpacket
wire cpu_inst_data_master_translator_avalon_universal_master_0_agent_cp_valid; // cpu_inst_data_master_translator_avalon_universal_master_0_agent:cp_valid -> addr_router:sink_valid
wire cpu_inst_data_master_translator_avalon_universal_master_0_agent_cp_startofpacket; // cpu_inst_data_master_translator_avalon_universal_master_0_agent:cp_startofpacket -> addr_router:sink_startofpacket
wire [92:0] cpu_inst_data_master_translator_avalon_universal_master_0_agent_cp_data; // cpu_inst_data_master_translator_avalon_universal_master_0_agent:cp_data -> addr_router:sink_data
wire cpu_inst_data_master_translator_avalon_universal_master_0_agent_cp_ready; // addr_router:sink_ready -> cpu_inst_data_master_translator_avalon_universal_master_0_agent:cp_ready
wire cpu_inst_instruction_master_translator_avalon_universal_master_0_agent_cp_endofpacket; // cpu_inst_instruction_master_translator_avalon_universal_master_0_agent:cp_endofpacket -> addr_router_001:sink_endofpacket
wire cpu_inst_instruction_master_translator_avalon_universal_master_0_agent_cp_valid; // cpu_inst_instruction_master_translator_avalon_universal_master_0_agent:cp_valid -> addr_router_001:sink_valid
wire cpu_inst_instruction_master_translator_avalon_universal_master_0_agent_cp_startofpacket; // cpu_inst_instruction_master_translator_avalon_universal_master_0_agent:cp_startofpacket -> addr_router_001:sink_startofpacket
wire [92:0] cpu_inst_instruction_master_translator_avalon_universal_master_0_agent_cp_data; // cpu_inst_instruction_master_translator_avalon_universal_master_0_agent:cp_data -> addr_router_001:sink_data
wire cpu_inst_instruction_master_translator_avalon_universal_master_0_agent_cp_ready; // addr_router_001:sink_ready -> cpu_inst_instruction_master_translator_avalon_universal_master_0_agent:cp_ready
wire sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_endofpacket; // sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router:sink_endofpacket
wire sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_valid; // sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rp_valid -> id_router:sink_valid
wire sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_startofpacket; // sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router:sink_startofpacket
wire [92:0] sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_data; // sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rp_data -> id_router:sink_data
wire sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_ready; // id_router:sink_ready -> sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rp_ready
wire sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_endofpacket; // sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_001:sink_endofpacket
wire sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_valid; // sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_001:sink_valid
wire sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_startofpacket; // sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_001:sink_startofpacket
wire [92:0] sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_data; // sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rp_data -> id_router_001:sink_data
wire sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_001:sink_ready -> sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rp_ready
wire sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_endofpacket; // sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_002:sink_endofpacket
wire sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_valid; // sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_002:sink_valid
wire sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_startofpacket; // sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_002:sink_startofpacket
wire [92:0] sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_data; // sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rp_data -> id_router_002:sink_data
wire sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_002:sink_ready -> sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rp_ready
wire sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket; // sequencer_mem_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_003:sink_endofpacket
wire sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rp_valid; // sequencer_mem_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_003:sink_valid
wire sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket; // sequencer_mem_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_003:sink_startofpacket
wire [92:0] sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rp_data; // sequencer_mem_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_003:sink_data
wire sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_003:sink_ready -> sequencer_mem_s1_translator_avalon_universal_slave_0_agent:rp_ready
wire sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_endofpacket; // sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_004:sink_endofpacket
wire sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_valid; // sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_004:sink_valid
wire sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_startofpacket; // sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_004:sink_startofpacket
wire [92:0] sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_data; // sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rp_data -> id_router_004:sink_data
wire sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_004:sink_ready -> sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rp_ready
wire sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rp_endofpacket; // sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_005:sink_endofpacket
wire sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rp_valid; // sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_005:sink_valid
wire sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rp_startofpacket; // sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_005:sink_startofpacket
wire [92:0] sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rp_data; // sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent:rp_data -> id_router_005:sink_data
wire sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_005:sink_ready -> sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent:rp_ready
wire rst_controller_reset_out_reset; // rst_controller:reset_out -> [addr_router:reset, addr_router_001:reset, cmd_xbar_demux:reset, cmd_xbar_demux_001:reset, cmd_xbar_mux_003:reset, cpu_inst:reset_n, cpu_inst_data_master_translator:reset, cpu_inst_data_master_translator_avalon_universal_master_0_agent:reset, cpu_inst_instruction_master_translator:reset, cpu_inst_instruction_master_translator_avalon_universal_master_0_agent:reset, id_router:reset, id_router_001:reset, id_router_002:reset, id_router_003:reset, id_router_004:reset, id_router_005:reset, irq_mapper:reset, rsp_xbar_demux:reset, rsp_xbar_demux_001:reset, rsp_xbar_demux_002:reset, rsp_xbar_demux_003:reset, rsp_xbar_demux_004:reset, rsp_xbar_demux_005:reset, rsp_xbar_mux:reset, sequencer_data_mgr_inst:avl_reset_n, sequencer_data_mgr_inst_avl_translator:reset, sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:reset, sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, sequencer_mem:reset1, sequencer_mem_s1_translator:reset, sequencer_mem_s1_translator_avalon_universal_slave_0_agent:reset, sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, sequencer_phy_mgr_inst:avl_reset_n, sequencer_phy_mgr_inst_avl_translator:reset, sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:reset, sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, sequencer_reg_file_inst:avl_reset_n, sequencer_reg_file_inst_avl_translator:reset, sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent:reset, sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, sequencer_rw_mgr_inst:avl_reset_n, sequencer_rw_mgr_inst_avl_translator:reset, sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:reset, sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, sequencer_scc_mgr_inst:avl_reset_n, sequencer_scc_mgr_inst_avl_translator:reset, sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:reset, sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:reset]
wire cmd_xbar_demux_src0_endofpacket; // cmd_xbar_demux:src0_endofpacket -> sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:cp_endofpacket
wire cmd_xbar_demux_src0_valid; // cmd_xbar_demux:src0_valid -> sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:cp_valid
wire cmd_xbar_demux_src0_startofpacket; // cmd_xbar_demux:src0_startofpacket -> sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:cp_startofpacket
wire [92:0] cmd_xbar_demux_src0_data; // cmd_xbar_demux:src0_data -> sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:cp_data
wire [5:0] cmd_xbar_demux_src0_channel; // cmd_xbar_demux:src0_channel -> sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:cp_channel
wire cmd_xbar_demux_src1_endofpacket; // cmd_xbar_demux:src1_endofpacket -> sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:cp_endofpacket
wire cmd_xbar_demux_src1_valid; // cmd_xbar_demux:src1_valid -> sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:cp_valid
wire cmd_xbar_demux_src1_startofpacket; // cmd_xbar_demux:src1_startofpacket -> sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:cp_startofpacket
wire [92:0] cmd_xbar_demux_src1_data; // cmd_xbar_demux:src1_data -> sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:cp_data
wire [5:0] cmd_xbar_demux_src1_channel; // cmd_xbar_demux:src1_channel -> sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:cp_channel
wire cmd_xbar_demux_src2_endofpacket; // cmd_xbar_demux:src2_endofpacket -> sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:cp_endofpacket
wire cmd_xbar_demux_src2_valid; // cmd_xbar_demux:src2_valid -> sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:cp_valid
wire cmd_xbar_demux_src2_startofpacket; // cmd_xbar_demux:src2_startofpacket -> sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:cp_startofpacket
wire [92:0] cmd_xbar_demux_src2_data; // cmd_xbar_demux:src2_data -> sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:cp_data
wire [5:0] cmd_xbar_demux_src2_channel; // cmd_xbar_demux:src2_channel -> sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:cp_channel
wire cmd_xbar_demux_src3_endofpacket; // cmd_xbar_demux:src3_endofpacket -> cmd_xbar_mux_003:sink0_endofpacket
wire cmd_xbar_demux_src3_valid; // cmd_xbar_demux:src3_valid -> cmd_xbar_mux_003:sink0_valid
wire cmd_xbar_demux_src3_startofpacket; // cmd_xbar_demux:src3_startofpacket -> cmd_xbar_mux_003:sink0_startofpacket
wire [92:0] cmd_xbar_demux_src3_data; // cmd_xbar_demux:src3_data -> cmd_xbar_mux_003:sink0_data
wire [5:0] cmd_xbar_demux_src3_channel; // cmd_xbar_demux:src3_channel -> cmd_xbar_mux_003:sink0_channel
wire cmd_xbar_demux_src3_ready; // cmd_xbar_mux_003:sink0_ready -> cmd_xbar_demux:src3_ready
wire cmd_xbar_demux_src4_endofpacket; // cmd_xbar_demux:src4_endofpacket -> sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:cp_endofpacket
wire cmd_xbar_demux_src4_valid; // cmd_xbar_demux:src4_valid -> sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:cp_valid
wire cmd_xbar_demux_src4_startofpacket; // cmd_xbar_demux:src4_startofpacket -> sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:cp_startofpacket
wire [92:0] cmd_xbar_demux_src4_data; // cmd_xbar_demux:src4_data -> sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:cp_data
wire [5:0] cmd_xbar_demux_src4_channel; // cmd_xbar_demux:src4_channel -> sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:cp_channel
wire cmd_xbar_demux_src5_endofpacket; // cmd_xbar_demux:src5_endofpacket -> sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent:cp_endofpacket
wire cmd_xbar_demux_src5_valid; // cmd_xbar_demux:src5_valid -> sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent:cp_valid
wire cmd_xbar_demux_src5_startofpacket; // cmd_xbar_demux:src5_startofpacket -> sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent:cp_startofpacket
wire [92:0] cmd_xbar_demux_src5_data; // cmd_xbar_demux:src5_data -> sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent:cp_data
wire [5:0] cmd_xbar_demux_src5_channel; // cmd_xbar_demux:src5_channel -> sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent:cp_channel
wire cmd_xbar_demux_001_src0_endofpacket; // cmd_xbar_demux_001:src0_endofpacket -> cmd_xbar_mux_003:sink1_endofpacket
wire cmd_xbar_demux_001_src0_valid; // cmd_xbar_demux_001:src0_valid -> cmd_xbar_mux_003:sink1_valid
wire cmd_xbar_demux_001_src0_startofpacket; // cmd_xbar_demux_001:src0_startofpacket -> cmd_xbar_mux_003:sink1_startofpacket
wire [92:0] cmd_xbar_demux_001_src0_data; // cmd_xbar_demux_001:src0_data -> cmd_xbar_mux_003:sink1_data
wire [5:0] cmd_xbar_demux_001_src0_channel; // cmd_xbar_demux_001:src0_channel -> cmd_xbar_mux_003:sink1_channel
wire cmd_xbar_demux_001_src0_ready; // cmd_xbar_mux_003:sink1_ready -> cmd_xbar_demux_001:src0_ready
wire rsp_xbar_demux_src0_endofpacket; // rsp_xbar_demux:src0_endofpacket -> rsp_xbar_mux:sink0_endofpacket
wire rsp_xbar_demux_src0_valid; // rsp_xbar_demux:src0_valid -> rsp_xbar_mux:sink0_valid
wire rsp_xbar_demux_src0_startofpacket; // rsp_xbar_demux:src0_startofpacket -> rsp_xbar_mux:sink0_startofpacket
wire [92:0] rsp_xbar_demux_src0_data; // rsp_xbar_demux:src0_data -> rsp_xbar_mux:sink0_data
wire [5:0] rsp_xbar_demux_src0_channel; // rsp_xbar_demux:src0_channel -> rsp_xbar_mux:sink0_channel
wire rsp_xbar_demux_src0_ready; // rsp_xbar_mux:sink0_ready -> rsp_xbar_demux:src0_ready
wire rsp_xbar_demux_001_src0_endofpacket; // rsp_xbar_demux_001:src0_endofpacket -> rsp_xbar_mux:sink1_endofpacket
wire rsp_xbar_demux_001_src0_valid; // rsp_xbar_demux_001:src0_valid -> rsp_xbar_mux:sink1_valid
wire rsp_xbar_demux_001_src0_startofpacket; // rsp_xbar_demux_001:src0_startofpacket -> rsp_xbar_mux:sink1_startofpacket
wire [92:0] rsp_xbar_demux_001_src0_data; // rsp_xbar_demux_001:src0_data -> rsp_xbar_mux:sink1_data
wire [5:0] rsp_xbar_demux_001_src0_channel; // rsp_xbar_demux_001:src0_channel -> rsp_xbar_mux:sink1_channel
wire rsp_xbar_demux_001_src0_ready; // rsp_xbar_mux:sink1_ready -> rsp_xbar_demux_001:src0_ready
wire rsp_xbar_demux_002_src0_endofpacket; // rsp_xbar_demux_002:src0_endofpacket -> rsp_xbar_mux:sink2_endofpacket
wire rsp_xbar_demux_002_src0_valid; // rsp_xbar_demux_002:src0_valid -> rsp_xbar_mux:sink2_valid
wire rsp_xbar_demux_002_src0_startofpacket; // rsp_xbar_demux_002:src0_startofpacket -> rsp_xbar_mux:sink2_startofpacket
wire [92:0] rsp_xbar_demux_002_src0_data; // rsp_xbar_demux_002:src0_data -> rsp_xbar_mux:sink2_data
wire [5:0] rsp_xbar_demux_002_src0_channel; // rsp_xbar_demux_002:src0_channel -> rsp_xbar_mux:sink2_channel
wire rsp_xbar_demux_002_src0_ready; // rsp_xbar_mux:sink2_ready -> rsp_xbar_demux_002:src0_ready
wire rsp_xbar_demux_003_src0_endofpacket; // rsp_xbar_demux_003:src0_endofpacket -> rsp_xbar_mux:sink3_endofpacket
wire rsp_xbar_demux_003_src0_valid; // rsp_xbar_demux_003:src0_valid -> rsp_xbar_mux:sink3_valid
wire rsp_xbar_demux_003_src0_startofpacket; // rsp_xbar_demux_003:src0_startofpacket -> rsp_xbar_mux:sink3_startofpacket
wire [92:0] rsp_xbar_demux_003_src0_data; // rsp_xbar_demux_003:src0_data -> rsp_xbar_mux:sink3_data
wire [5:0] rsp_xbar_demux_003_src0_channel; // rsp_xbar_demux_003:src0_channel -> rsp_xbar_mux:sink3_channel
wire rsp_xbar_demux_003_src0_ready; // rsp_xbar_mux:sink3_ready -> rsp_xbar_demux_003:src0_ready
wire rsp_xbar_demux_003_src1_endofpacket; // rsp_xbar_demux_003:src1_endofpacket -> cpu_inst_instruction_master_translator_avalon_universal_master_0_agent:rp_endofpacket
wire rsp_xbar_demux_003_src1_valid; // rsp_xbar_demux_003:src1_valid -> cpu_inst_instruction_master_translator_avalon_universal_master_0_agent:rp_valid
wire rsp_xbar_demux_003_src1_startofpacket; // rsp_xbar_demux_003:src1_startofpacket -> cpu_inst_instruction_master_translator_avalon_universal_master_0_agent:rp_startofpacket
wire [92:0] rsp_xbar_demux_003_src1_data; // rsp_xbar_demux_003:src1_data -> cpu_inst_instruction_master_translator_avalon_universal_master_0_agent:rp_data
wire [5:0] rsp_xbar_demux_003_src1_channel; // rsp_xbar_demux_003:src1_channel -> cpu_inst_instruction_master_translator_avalon_universal_master_0_agent:rp_channel
wire rsp_xbar_demux_004_src0_endofpacket; // rsp_xbar_demux_004:src0_endofpacket -> rsp_xbar_mux:sink4_endofpacket
wire rsp_xbar_demux_004_src0_valid; // rsp_xbar_demux_004:src0_valid -> rsp_xbar_mux:sink4_valid
wire rsp_xbar_demux_004_src0_startofpacket; // rsp_xbar_demux_004:src0_startofpacket -> rsp_xbar_mux:sink4_startofpacket
wire [92:0] rsp_xbar_demux_004_src0_data; // rsp_xbar_demux_004:src0_data -> rsp_xbar_mux:sink4_data
wire [5:0] rsp_xbar_demux_004_src0_channel; // rsp_xbar_demux_004:src0_channel -> rsp_xbar_mux:sink4_channel
wire rsp_xbar_demux_004_src0_ready; // rsp_xbar_mux:sink4_ready -> rsp_xbar_demux_004:src0_ready
wire rsp_xbar_demux_005_src0_endofpacket; // rsp_xbar_demux_005:src0_endofpacket -> rsp_xbar_mux:sink5_endofpacket
wire rsp_xbar_demux_005_src0_valid; // rsp_xbar_demux_005:src0_valid -> rsp_xbar_mux:sink5_valid
wire rsp_xbar_demux_005_src0_startofpacket; // rsp_xbar_demux_005:src0_startofpacket -> rsp_xbar_mux:sink5_startofpacket
wire [92:0] rsp_xbar_demux_005_src0_data; // rsp_xbar_demux_005:src0_data -> rsp_xbar_mux:sink5_data
wire [5:0] rsp_xbar_demux_005_src0_channel; // rsp_xbar_demux_005:src0_channel -> rsp_xbar_mux:sink5_channel
wire rsp_xbar_demux_005_src0_ready; // rsp_xbar_mux:sink5_ready -> rsp_xbar_demux_005:src0_ready
wire addr_router_src_endofpacket; // addr_router:src_endofpacket -> cmd_xbar_demux:sink_endofpacket
wire addr_router_src_valid; // addr_router:src_valid -> cmd_xbar_demux:sink_valid
wire addr_router_src_startofpacket; // addr_router:src_startofpacket -> cmd_xbar_demux:sink_startofpacket
wire [92:0] addr_router_src_data; // addr_router:src_data -> cmd_xbar_demux:sink_data
wire [5:0] addr_router_src_channel; // addr_router:src_channel -> cmd_xbar_demux:sink_channel
wire addr_router_src_ready; // cmd_xbar_demux:sink_ready -> addr_router:src_ready
wire rsp_xbar_mux_src_endofpacket; // rsp_xbar_mux:src_endofpacket -> cpu_inst_data_master_translator_avalon_universal_master_0_agent:rp_endofpacket
wire rsp_xbar_mux_src_valid; // rsp_xbar_mux:src_valid -> cpu_inst_data_master_translator_avalon_universal_master_0_agent:rp_valid
wire rsp_xbar_mux_src_startofpacket; // rsp_xbar_mux:src_startofpacket -> cpu_inst_data_master_translator_avalon_universal_master_0_agent:rp_startofpacket
wire [92:0] rsp_xbar_mux_src_data; // rsp_xbar_mux:src_data -> cpu_inst_data_master_translator_avalon_universal_master_0_agent:rp_data
wire [5:0] rsp_xbar_mux_src_channel; // rsp_xbar_mux:src_channel -> cpu_inst_data_master_translator_avalon_universal_master_0_agent:rp_channel
wire rsp_xbar_mux_src_ready; // cpu_inst_data_master_translator_avalon_universal_master_0_agent:rp_ready -> rsp_xbar_mux:src_ready
wire addr_router_001_src_endofpacket; // addr_router_001:src_endofpacket -> cmd_xbar_demux_001:sink_endofpacket
wire addr_router_001_src_valid; // addr_router_001:src_valid -> cmd_xbar_demux_001:sink_valid
wire addr_router_001_src_startofpacket; // addr_router_001:src_startofpacket -> cmd_xbar_demux_001:sink_startofpacket
wire [92:0] addr_router_001_src_data; // addr_router_001:src_data -> cmd_xbar_demux_001:sink_data
wire [5:0] addr_router_001_src_channel; // addr_router_001:src_channel -> cmd_xbar_demux_001:sink_channel
wire addr_router_001_src_ready; // cmd_xbar_demux_001:sink_ready -> addr_router_001:src_ready
wire rsp_xbar_demux_003_src1_ready; // cpu_inst_instruction_master_translator_avalon_universal_master_0_agent:rp_ready -> rsp_xbar_demux_003:src1_ready
wire cmd_xbar_demux_src0_ready; // sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux:src0_ready
wire id_router_src_endofpacket; // id_router:src_endofpacket -> rsp_xbar_demux:sink_endofpacket
wire id_router_src_valid; // id_router:src_valid -> rsp_xbar_demux:sink_valid
wire id_router_src_startofpacket; // id_router:src_startofpacket -> rsp_xbar_demux:sink_startofpacket
wire [92:0] id_router_src_data; // id_router:src_data -> rsp_xbar_demux:sink_data
wire [5:0] id_router_src_channel; // id_router:src_channel -> rsp_xbar_demux:sink_channel
wire id_router_src_ready; // rsp_xbar_demux:sink_ready -> id_router:src_ready
wire cmd_xbar_demux_src1_ready; // sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux:src1_ready
wire id_router_001_src_endofpacket; // id_router_001:src_endofpacket -> rsp_xbar_demux_001:sink_endofpacket
wire id_router_001_src_valid; // id_router_001:src_valid -> rsp_xbar_demux_001:sink_valid
wire id_router_001_src_startofpacket; // id_router_001:src_startofpacket -> rsp_xbar_demux_001:sink_startofpacket
wire [92:0] id_router_001_src_data; // id_router_001:src_data -> rsp_xbar_demux_001:sink_data
wire [5:0] id_router_001_src_channel; // id_router_001:src_channel -> rsp_xbar_demux_001:sink_channel
wire id_router_001_src_ready; // rsp_xbar_demux_001:sink_ready -> id_router_001:src_ready
wire cmd_xbar_demux_src2_ready; // sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux:src2_ready
wire id_router_002_src_endofpacket; // id_router_002:src_endofpacket -> rsp_xbar_demux_002:sink_endofpacket
wire id_router_002_src_valid; // id_router_002:src_valid -> rsp_xbar_demux_002:sink_valid
wire id_router_002_src_startofpacket; // id_router_002:src_startofpacket -> rsp_xbar_demux_002:sink_startofpacket
wire [92:0] id_router_002_src_data; // id_router_002:src_data -> rsp_xbar_demux_002:sink_data
wire [5:0] id_router_002_src_channel; // id_router_002:src_channel -> rsp_xbar_demux_002:sink_channel
wire id_router_002_src_ready; // rsp_xbar_demux_002:sink_ready -> id_router_002:src_ready
wire cmd_xbar_mux_003_src_endofpacket; // cmd_xbar_mux_003:src_endofpacket -> sequencer_mem_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket
wire cmd_xbar_mux_003_src_valid; // cmd_xbar_mux_003:src_valid -> sequencer_mem_s1_translator_avalon_universal_slave_0_agent:cp_valid
wire cmd_xbar_mux_003_src_startofpacket; // cmd_xbar_mux_003:src_startofpacket -> sequencer_mem_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket
wire [92:0] cmd_xbar_mux_003_src_data; // cmd_xbar_mux_003:src_data -> sequencer_mem_s1_translator_avalon_universal_slave_0_agent:cp_data
wire [5:0] cmd_xbar_mux_003_src_channel; // cmd_xbar_mux_003:src_channel -> sequencer_mem_s1_translator_avalon_universal_slave_0_agent:cp_channel
wire cmd_xbar_mux_003_src_ready; // sequencer_mem_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_mux_003:src_ready
wire id_router_003_src_endofpacket; // id_router_003:src_endofpacket -> rsp_xbar_demux_003:sink_endofpacket
wire id_router_003_src_valid; // id_router_003:src_valid -> rsp_xbar_demux_003:sink_valid
wire id_router_003_src_startofpacket; // id_router_003:src_startofpacket -> rsp_xbar_demux_003:sink_startofpacket
wire [92:0] id_router_003_src_data; // id_router_003:src_data -> rsp_xbar_demux_003:sink_data
wire [5:0] id_router_003_src_channel; // id_router_003:src_channel -> rsp_xbar_demux_003:sink_channel
wire id_router_003_src_ready; // rsp_xbar_demux_003:sink_ready -> id_router_003:src_ready
wire cmd_xbar_demux_src4_ready; // sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux:src4_ready
wire id_router_004_src_endofpacket; // id_router_004:src_endofpacket -> rsp_xbar_demux_004:sink_endofpacket
wire id_router_004_src_valid; // id_router_004:src_valid -> rsp_xbar_demux_004:sink_valid
wire id_router_004_src_startofpacket; // id_router_004:src_startofpacket -> rsp_xbar_demux_004:sink_startofpacket
wire [92:0] id_router_004_src_data; // id_router_004:src_data -> rsp_xbar_demux_004:sink_data
wire [5:0] id_router_004_src_channel; // id_router_004:src_channel -> rsp_xbar_demux_004:sink_channel
wire id_router_004_src_ready; // rsp_xbar_demux_004:sink_ready -> id_router_004:src_ready
wire cmd_xbar_demux_src5_ready; // sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux:src5_ready
wire id_router_005_src_endofpacket; // id_router_005:src_endofpacket -> rsp_xbar_demux_005:sink_endofpacket
wire id_router_005_src_valid; // id_router_005:src_valid -> rsp_xbar_demux_005:sink_valid
wire id_router_005_src_startofpacket; // id_router_005:src_startofpacket -> rsp_xbar_demux_005:sink_startofpacket
wire [92:0] id_router_005_src_data; // id_router_005:src_data -> rsp_xbar_demux_005:sink_data
wire [5:0] id_router_005_src_channel; // id_router_005:src_channel -> rsp_xbar_demux_005:sink_channel
wire id_router_005_src_ready; // rsp_xbar_demux_005:sink_ready -> id_router_005:src_ready
wire [31:0] cpu_inst_d_irq_irq; // irq_mapper:sender_irq -> cpu_inst:d_irq
altera_mem_if_sequencer_cpu_no_ifdef_params_synth_cpu_inst cpu_inst (
.clk (avl_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset_n.reset_n
.d_address (cpu_inst_data_master_address), // data_master.address
.d_byteenable (cpu_inst_data_master_byteenable), // .byteenable
.d_read (cpu_inst_data_master_read), // .read
.d_readdata (cpu_inst_data_master_readdata), // .readdata
.d_waitrequest (cpu_inst_data_master_waitrequest), // .waitrequest
.d_write (cpu_inst_data_master_write), // .write
.d_writedata (cpu_inst_data_master_writedata), // .writedata
.i_address (cpu_inst_instruction_master_address), // instruction_master.address
.i_read (cpu_inst_instruction_master_read), // .read
.i_readdata (cpu_inst_instruction_master_readdata), // .readdata
.i_waitrequest (cpu_inst_instruction_master_waitrequest), // .waitrequest
.d_irq (cpu_inst_d_irq_irq), // d_irq.irq
.no_ci_readra () // custom_instruction_master.readra
);
sequencer_scc_mgr #(
.AVL_DATA_WIDTH (32),
.AVL_ADDR_WIDTH (13),
.MEM_IF_READ_DQS_WIDTH (8),
.MEM_IF_WRITE_DQS_WIDTH (8),
.MEM_IF_DQ_WIDTH (64),
.MEM_IF_DM_WIDTH (8),
.MEM_NUMBER_OF_RANKS (1),
.DLL_DELAY_CHAIN_LENGTH (10),
.FAMILY ("STRATIXIV"),
.USE_SHADOW_REGS (0),
.USE_DQS_TRACKING (0),
.DUAL_WRITE_CLOCK (0)
) sequencer_scc_mgr_inst (
.avl_clk (avl_clk), // avl_clk.clk
.avl_reset_n (~rst_controller_reset_out_reset), // avl_reset.reset_n
.avl_address (sequencer_scc_mgr_inst_avl_translator_avalon_anti_slave_0_address), // avl.address
.avl_write (sequencer_scc_mgr_inst_avl_translator_avalon_anti_slave_0_write), // .write
.avl_writedata (sequencer_scc_mgr_inst_avl_translator_avalon_anti_slave_0_writedata), // .writedata
.avl_read (sequencer_scc_mgr_inst_avl_translator_avalon_anti_slave_0_read), // .read
.avl_readdata (sequencer_scc_mgr_inst_avl_translator_avalon_anti_slave_0_readdata), // .readdata
.avl_waitrequest (sequencer_scc_mgr_inst_avl_translator_avalon_anti_slave_0_waitrequest), // .waitrequest
.scc_clk (scc_clk), // scc_clk.clk
.scc_reset_n (reset_n_scc_clk), // scc_reset.reset_n
.scc_data (scc_data), // scc.scc_data
.scc_dqs_ena (scc_dqs_ena), // .scc_dqs_ena
.scc_dqs_io_ena (scc_dqs_io_ena), // .scc_dqs_io_ena
.scc_dq_ena (scc_dq_ena), // .scc_dq_ena
.scc_dm_ena (scc_dm_ena), // .scc_dm_ena
.capture_strobe_tracking (capture_strobe_tracking), // .capture_strobe_tracking
.scc_upd (scc_upd), // .scc_upd
.afi_init_req (afi_init_req), // afi_init_cal_req.afi_init_req
.afi_cal_req (afi_cal_req), // .afi_cal_req
.scc_sr_dqsenable_delayctrl (), // (terminated)
.scc_sr_dqsdisablen_delayctrl (), // (terminated)
.scc_sr_multirank_delayctrl () // (terminated)
);
sequencer_reg_file #(
.AVL_DATA_WIDTH (32),
.AVL_ADDR_WIDTH (4),
.AVL_NUM_SYMBOLS (4),
.AVL_SYMBOL_WIDTH (8),
.REGISTER_RDATA (0),
.NUM_REGFILE_WORDS (16)
) sequencer_reg_file_inst (
.avl_clk (avl_clk), // avl_clk.clk
.avl_reset_n (~rst_controller_reset_out_reset), // avl_reset.reset_n
.avl_address (sequencer_reg_file_inst_avl_translator_avalon_anti_slave_0_address), // avl.address
.avl_write (sequencer_reg_file_inst_avl_translator_avalon_anti_slave_0_write), // .write
.avl_writedata (sequencer_reg_file_inst_avl_translator_avalon_anti_slave_0_writedata), // .writedata
.avl_read (sequencer_reg_file_inst_avl_translator_avalon_anti_slave_0_read), // .read
.avl_readdata (sequencer_reg_file_inst_avl_translator_avalon_anti_slave_0_readdata), // .readdata
.avl_waitrequest (sequencer_reg_file_inst_avl_translator_avalon_anti_slave_0_waitrequest), // .waitrequest
.avl_be (sequencer_reg_file_inst_avl_translator_avalon_anti_slave_0_byteenable) // .byteenable
);
sequencer_phy_mgr #(
.AVL_DATA_WIDTH (32),
.AVL_ADDR_WIDTH (13),
.MAX_LATENCY_COUNT_WIDTH (4),
.MEM_IF_READ_DQS_WIDTH (8),
.MEM_IF_WRITE_DQS_WIDTH (8),
.AFI_DQ_WIDTH (256),
.AFI_DEBUG_INFO_WIDTH (32),
.AFI_MAX_WRITE_LATENCY_COUNT_WIDTH (6),
.AFI_MAX_READ_LATENCY_COUNT_WIDTH (6),
.CALIB_VFIFO_OFFSET (14),
.CALIB_LFIFO_OFFSET (5),
.CALIB_REG_WIDTH (8),
.READ_VALID_FIFO_SIZE (16),
.MEM_T_WL (4),
.MEM_T_RL (6),
.CTL_REGDIMM_ENABLED (0),
.NUM_WRITE_FR_CYCLE_SHIFTS (0),
.VFIFO_CONTROL_WIDTH_PER_DQS (1),
.DEVICE_FAMILY ("STRATIXIV")
) sequencer_phy_mgr_inst (
.avl_clk (avl_clk), // avl_clk.clk
.avl_reset_n (~rst_controller_reset_out_reset), // avl_reset.reset_n
.avl_address (sequencer_phy_mgr_inst_avl_translator_avalon_anti_slave_0_address), // avl.address
.avl_write (sequencer_phy_mgr_inst_avl_translator_avalon_anti_slave_0_write), // .write
.avl_writedata (sequencer_phy_mgr_inst_avl_translator_avalon_anti_slave_0_writedata), // .writedata
.avl_read (sequencer_phy_mgr_inst_avl_translator_avalon_anti_slave_0_read), // .read
.avl_readdata (sequencer_phy_mgr_inst_avl_translator_avalon_anti_slave_0_readdata), // .readdata
.avl_waitrequest (sequencer_phy_mgr_inst_avl_translator_avalon_anti_slave_0_waitrequest), // .waitrequest
.phy_clk (phy_clk), // phy.phy_clk
.phy_reset_n (phy_reset_n), // .phy_reset_n
.phy_read_latency_counter (phy_read_latency_counter), // .phy_read_latency_counter
.phy_afi_wlat (phy_afi_wlat), // .phy_afi_wlat
.phy_afi_rlat (phy_afi_rlat), // .phy_afi_rlat
.phy_read_increment_vfifo_fr (phy_read_increment_vfifo_fr), // .phy_read_increment_vfifo_fr
.phy_read_increment_vfifo_hr (phy_read_increment_vfifo_hr), // .phy_read_increment_vfifo_hr
.phy_read_increment_vfifo_qr (phy_read_increment_vfifo_qr), // .phy_read_increment_vfifo_qr
.phy_reset_mem_stable (phy_reset_mem_stable), // .phy_reset_mem_stable
.phy_cal_success (phy_cal_success), // .phy_cal_success
.phy_cal_fail (phy_cal_fail), // .phy_cal_fail
.phy_cal_debug_info (phy_cal_debug_info), // .phy_cal_debug_info
.phy_read_fifo_reset (phy_read_fifo_reset), // .phy_read_fifo_reset
.phy_vfifo_rd_en_override (phy_vfifo_rd_en_override), // .phy_vfifo_rd_en_override
.phy_read_fifo_q (phy_read_fifo_q), // .phy_read_fifo_q
.phy_write_fr_cycle_shifts (phy_write_fr_cycle_shifts), // .phy_write_fr_cycle_shifts
.calib_skip_steps (calib_skip_steps), // calib.calib_skip_steps
.phy_mux_sel (phy_mux_sel) // mux_sel.mux_sel
);
sequencer_data_mgr #(
.AVL_DATA_WIDTH (32),
.AVL_ADDR_WIDTH (13),
.MAX_LATENCY_COUNT_WIDTH (4),
.MEM_READ_DQS_WIDTH (8),
.AFI_DEBUG_INFO_WIDTH (32),
.AFI_MAX_WRITE_LATENCY_COUNT_WIDTH (6),
.AFI_MAX_READ_LATENCY_COUNT_WIDTH (6),
.CALIB_VFIFO_OFFSET (14),
.CALIB_LFIFO_OFFSET (5),
.CALIB_SKIP_STEPS_WIDTH (8),
.READ_VALID_FIFO_SIZE (16),
.MEM_T_WL (4),
.MEM_T_RL (6),
.CTL_REGDIMM_ENABLED (0),
.SEQUENCER_VERSION (12)
) sequencer_data_mgr_inst (
.avl_clk (avl_clk), // avl_clk.clk
.avl_reset_n (~rst_controller_reset_out_reset), // avl_reset.reset_n
.avl_address (sequencer_data_mgr_inst_avl_translator_avalon_anti_slave_0_address), // avl.address
.avl_write (sequencer_data_mgr_inst_avl_translator_avalon_anti_slave_0_write), // .write
.avl_writedata (sequencer_data_mgr_inst_avl_translator_avalon_anti_slave_0_writedata), // .writedata
.avl_read (sequencer_data_mgr_inst_avl_translator_avalon_anti_slave_0_read), // .read
.avl_readdata (sequencer_data_mgr_inst_avl_translator_avalon_anti_slave_0_readdata), // .readdata
.avl_waitrequest (sequencer_data_mgr_inst_avl_translator_avalon_anti_slave_0_waitrequest) // .waitrequest
);
rw_manager_ddr2 #(
.RATE ("Half"),
.AVL_DATA_WIDTH (32),
.AVL_ADDR_WIDTH (13),
.MEM_ADDRESS_WIDTH (14),
.MEM_CONTROL_WIDTH (1),
.MEM_DQ_WIDTH (64),
.MEM_DM_WIDTH (8),
.MEM_NUMBER_OF_RANKS (1),
.MEM_CLK_EN_WIDTH (1),
.MEM_BANK_WIDTH (3),
.MEM_ODT_WIDTH (1),
.MEM_CHIP_SELECT_WIDTH (1),
.MEM_READ_DQS_WIDTH (8),
.MEM_WRITE_DQS_WIDTH (8),
.AFI_RATIO (2),
.AC_BUS_WIDTH (26),
.HCX_COMPAT_MODE (0),
.DEVICE_FAMILY ("STRATIXIV"),
.AC_ROM_INIT_FILE_NAME ("DE4_SOPC_ddr2_0_s0_AC_ROM.hex"),
.INST_ROM_INIT_FILE_NAME ("DE4_SOPC_ddr2_0_s0_inst_ROM.hex"),
.DEBUG_WRITE_TO_READ_RATIO_2_EXPONENT (0),
.DEBUG_WRITE_TO_READ_RATIO (1),
.MAX_DI_BUFFER_WORDS_LOG_2 (2)
) sequencer_rw_mgr_inst (
.avl_clk (avl_clk), // avl_clk.clk
.avl_reset_n (~rst_controller_reset_out_reset), // avl_reset.reset_n
.avl_address (sequencer_rw_mgr_inst_avl_translator_avalon_anti_slave_0_address), // avl.address
.avl_write (sequencer_rw_mgr_inst_avl_translator_avalon_anti_slave_0_write), // .write
.avl_writedata (sequencer_rw_mgr_inst_avl_translator_avalon_anti_slave_0_writedata), // .writedata
.avl_read (sequencer_rw_mgr_inst_avl_translator_avalon_anti_slave_0_read), // .read
.avl_readdata (sequencer_rw_mgr_inst_avl_translator_avalon_anti_slave_0_readdata), // .readdata
.avl_waitrequest (sequencer_rw_mgr_inst_avl_translator_avalon_anti_slave_0_waitrequest), // .waitrequest
.afi_clk (afi_clk), // afi_clk.clk
.afi_reset_n (afi_reset_n), // afi_reset.reset_n
.afi_addr (afi_addr), // afi.afi_addr
.afi_ba (afi_ba), // .afi_ba
.afi_cs_n (afi_cs_n), // .afi_cs_n
.afi_cke (afi_cke), // .afi_cke
.afi_odt (afi_odt), // .afi_odt
.afi_ras_n (afi_ras_n), // .afi_ras_n
.afi_cas_n (afi_cas_n), // .afi_cas_n
.afi_we_n (afi_we_n), // .afi_we_n
.afi_dqs_burst (afi_dqs_burst), // .afi_dqs_burst
.afi_wdata (afi_wdata), // .afi_wdata
.afi_wdata_valid (afi_wdata_valid), // .afi_wdata_valid
.afi_dm (afi_dm), // .afi_dm
.afi_rdata_en (afi_rdata_en), // .afi_rdata_en
.afi_rdata_en_full (afi_rdata_en_full), // .afi_rdata_en_full
.afi_rdata (afi_rdata), // .afi_rdata
.afi_rdata_valid (afi_rdata_valid), // .afi_rdata_valid
.csr_clk (), // csr.csr_clk
.csr_ena (), // .csr_ena
.csr_dout_phy (), // .csr_dout_phy
.csr_dout () // .csr_dout
);
altera_mem_if_sequencer_mem_no_ifdef_params #(
.AVL_DATA_WIDTH (32),
.AVL_ADDR_WIDTH (12),
.AVL_NUM_SYMBOLS (4),
.AVL_SYMBOL_WIDTH (8),
.MEM_SIZE (13312),
.INIT_FILE ("DE4_SOPC_ddr2_0_s0_sequencer_mem.hex"),
.RAM_BLOCK_TYPE ("AUTO")
) sequencer_mem (
.clk1 (avl_clk), // clk1.clk
.reset1 (rst_controller_reset_out_reset), // reset1.reset
.s1_address (sequencer_mem_s1_translator_avalon_anti_slave_0_address), // s1.address
.s1_write (sequencer_mem_s1_translator_avalon_anti_slave_0_write), // .write
.s1_writedata (sequencer_mem_s1_translator_avalon_anti_slave_0_writedata), // .writedata
.s1_readdata (sequencer_mem_s1_translator_avalon_anti_slave_0_readdata), // .readdata
.s1_be (sequencer_mem_s1_translator_avalon_anti_slave_0_byteenable), // .byteenable
.s1_chipselect (sequencer_mem_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect
.s1_clken (sequencer_mem_s1_translator_avalon_anti_slave_0_clken) // .clken
);
altera_merlin_master_translator #(
.AV_ADDRESS_W (20),
.AV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (20),
.UAV_BURSTCOUNT_W (3),
.USE_READ (1),
.USE_WRITE (1),
.USE_BEGINBURSTTRANSFER (0),
.USE_BEGINTRANSFER (0),
.USE_CHIPSELECT (0),
.USE_BURSTCOUNT (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (1),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_LINEWRAPBURSTS (0),
.AV_REGISTERINCOMINGSIGNALS (1)
) cpu_inst_data_master_translator (
.clk (avl_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // reset.reset
.uav_address (cpu_inst_data_master_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
.uav_burstcount (cpu_inst_data_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.uav_read (cpu_inst_data_master_translator_avalon_universal_master_0_read), // .read
.uav_write (cpu_inst_data_master_translator_avalon_universal_master_0_write), // .write
.uav_waitrequest (cpu_inst_data_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.uav_readdatavalid (cpu_inst_data_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.uav_byteenable (cpu_inst_data_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.uav_readdata (cpu_inst_data_master_translator_avalon_universal_master_0_readdata), // .readdata
.uav_writedata (cpu_inst_data_master_translator_avalon_universal_master_0_writedata), // .writedata
.uav_lock (cpu_inst_data_master_translator_avalon_universal_master_0_lock), // .lock
.uav_debugaccess (cpu_inst_data_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_address (cpu_inst_data_master_address), // avalon_anti_master_0.address
.av_waitrequest (cpu_inst_data_master_waitrequest), // .waitrequest
.av_byteenable (cpu_inst_data_master_byteenable), // .byteenable
.av_read (cpu_inst_data_master_read), // .read
.av_readdata (cpu_inst_data_master_readdata), // .readdata
.av_write (cpu_inst_data_master_write), // .write
.av_writedata (cpu_inst_data_master_writedata), // .writedata
.av_burstcount (1'b1), // (terminated)
.av_beginbursttransfer (1'b0), // (terminated)
.av_begintransfer (1'b0), // (terminated)
.av_chipselect (1'b0), // (terminated)
.av_readdatavalid (), // (terminated)
.av_lock (1'b0), // (terminated)
.av_debugaccess (1'b0), // (terminated)
.uav_clken (), // (terminated)
.av_clken (1'b1) // (terminated)
);
altera_merlin_master_translator #(
.AV_ADDRESS_W (17),
.AV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (20),
.UAV_BURSTCOUNT_W (3),
.USE_READ (1),
.USE_WRITE (0),
.USE_BEGINBURSTTRANSFER (0),
.USE_BEGINTRANSFER (0),
.USE_CHIPSELECT (0),
.USE_BURSTCOUNT (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (1),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_LINEWRAPBURSTS (1),
.AV_REGISTERINCOMINGSIGNALS (0)
) cpu_inst_instruction_master_translator (
.clk (avl_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // reset.reset
.uav_address (cpu_inst_instruction_master_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
.uav_burstcount (cpu_inst_instruction_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.uav_read (cpu_inst_instruction_master_translator_avalon_universal_master_0_read), // .read
.uav_write (cpu_inst_instruction_master_translator_avalon_universal_master_0_write), // .write
.uav_waitrequest (cpu_inst_instruction_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.uav_readdatavalid (cpu_inst_instruction_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.uav_byteenable (cpu_inst_instruction_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.uav_readdata (cpu_inst_instruction_master_translator_avalon_universal_master_0_readdata), // .readdata
.uav_writedata (cpu_inst_instruction_master_translator_avalon_universal_master_0_writedata), // .writedata
.uav_lock (cpu_inst_instruction_master_translator_avalon_universal_master_0_lock), // .lock
.uav_debugaccess (cpu_inst_instruction_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_address (cpu_inst_instruction_master_address), // avalon_anti_master_0.address
.av_waitrequest (cpu_inst_instruction_master_waitrequest), // .waitrequest
.av_read (cpu_inst_instruction_master_read), // .read
.av_readdata (cpu_inst_instruction_master_readdata), // .readdata
.av_burstcount (1'b1), // (terminated)
.av_byteenable (4'b1111), // (terminated)
.av_beginbursttransfer (1'b0), // (terminated)
.av_begintransfer (1'b0), // (terminated)
.av_chipselect (1'b0), // (terminated)
.av_readdatavalid (), // (terminated)
.av_write (1'b0), // (terminated)
.av_writedata (32'b00000000000000000000000000000000), // (terminated)
.av_lock (1'b0), // (terminated)
.av_debugaccess (1'b0), // (terminated)
.uav_clken (), // (terminated)
.av_clken (1'b1) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (13),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (20),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) sequencer_phy_mgr_inst_avl_translator (
.clk (avl_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // reset.reset
.uav_address (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.uav_read (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_read), // .read
.uav_write (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_write), // .write
.uav_waitrequest (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.uav_readdata (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.uav_writedata (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.uav_lock (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.uav_debugaccess (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.av_address (sequencer_phy_mgr_inst_avl_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address
.av_write (sequencer_phy_mgr_inst_avl_translator_avalon_anti_slave_0_write), // .write
.av_read (sequencer_phy_mgr_inst_avl_translator_avalon_anti_slave_0_read), // .read
.av_readdata (sequencer_phy_mgr_inst_avl_translator_avalon_anti_slave_0_readdata), // .readdata
.av_writedata (sequencer_phy_mgr_inst_avl_translator_avalon_anti_slave_0_writedata), // .writedata
.av_waitrequest (sequencer_phy_mgr_inst_avl_translator_avalon_anti_slave_0_waitrequest), // .waitrequest
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable () // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (13),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (20),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) sequencer_data_mgr_inst_avl_translator (
.clk (avl_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // reset.reset
.uav_address (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.uav_read (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_read), // .read
.uav_write (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_write), // .write
.uav_waitrequest (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.uav_readdata (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.uav_writedata (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.uav_lock (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.uav_debugaccess (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.av_address (sequencer_data_mgr_inst_avl_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address
.av_write (sequencer_data_mgr_inst_avl_translator_avalon_anti_slave_0_write), // .write
.av_read (sequencer_data_mgr_inst_avl_translator_avalon_anti_slave_0_read), // .read
.av_readdata (sequencer_data_mgr_inst_avl_translator_avalon_anti_slave_0_readdata), // .readdata
.av_writedata (sequencer_data_mgr_inst_avl_translator_avalon_anti_slave_0_writedata), // .writedata
.av_waitrequest (sequencer_data_mgr_inst_avl_translator_avalon_anti_slave_0_waitrequest), // .waitrequest
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable () // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (13),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (20),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) sequencer_rw_mgr_inst_avl_translator (
.clk (avl_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // reset.reset
.uav_address (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.uav_read (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_read), // .read
.uav_write (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_write), // .write
.uav_waitrequest (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.uav_readdata (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.uav_writedata (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.uav_lock (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.uav_debugaccess (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.av_address (sequencer_rw_mgr_inst_avl_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address
.av_write (sequencer_rw_mgr_inst_avl_translator_avalon_anti_slave_0_write), // .write
.av_read (sequencer_rw_mgr_inst_avl_translator_avalon_anti_slave_0_read), // .read
.av_readdata (sequencer_rw_mgr_inst_avl_translator_avalon_anti_slave_0_readdata), // .readdata
.av_writedata (sequencer_rw_mgr_inst_avl_translator_avalon_anti_slave_0_writedata), // .writedata
.av_waitrequest (sequencer_rw_mgr_inst_avl_translator_avalon_anti_slave_0_waitrequest), // .waitrequest
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable () // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (12),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (20),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (1),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (0),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) sequencer_mem_s1_translator (
.clk (avl_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // reset.reset
.uav_address (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.uav_read (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read
.uav_write (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write
.uav_waitrequest (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.uav_readdata (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.uav_writedata (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.uav_lock (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.uav_debugaccess (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.av_address (sequencer_mem_s1_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address
.av_write (sequencer_mem_s1_translator_avalon_anti_slave_0_write), // .write
.av_readdata (sequencer_mem_s1_translator_avalon_anti_slave_0_readdata), // .readdata
.av_writedata (sequencer_mem_s1_translator_avalon_anti_slave_0_writedata), // .writedata
.av_byteenable (sequencer_mem_s1_translator_avalon_anti_slave_0_byteenable), // .byteenable
.av_chipselect (sequencer_mem_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect
.av_clken (sequencer_mem_s1_translator_avalon_anti_slave_0_clken), // .clken
.av_read (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable () // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (13),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (20),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) sequencer_scc_mgr_inst_avl_translator (
.clk (avl_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // reset.reset
.uav_address (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.uav_read (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_read), // .read
.uav_write (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_write), // .write
.uav_waitrequest (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.uav_readdata (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.uav_writedata (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.uav_lock (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.uav_debugaccess (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.av_address (sequencer_scc_mgr_inst_avl_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address
.av_write (sequencer_scc_mgr_inst_avl_translator_avalon_anti_slave_0_write), // .write
.av_read (sequencer_scc_mgr_inst_avl_translator_avalon_anti_slave_0_read), // .read
.av_readdata (sequencer_scc_mgr_inst_avl_translator_avalon_anti_slave_0_readdata), // .readdata
.av_writedata (sequencer_scc_mgr_inst_avl_translator_avalon_anti_slave_0_writedata), // .writedata
.av_waitrequest (sequencer_scc_mgr_inst_avl_translator_avalon_anti_slave_0_waitrequest), // .waitrequest
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable () // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (4),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (20),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) sequencer_reg_file_inst_avl_translator (
.clk (avl_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // reset.reset
.uav_address (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.uav_read (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_m0_read), // .read
.uav_write (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_m0_write), // .write
.uav_waitrequest (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.uav_readdata (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.uav_writedata (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.uav_lock (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.uav_debugaccess (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.av_address (sequencer_reg_file_inst_avl_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address
.av_write (sequencer_reg_file_inst_avl_translator_avalon_anti_slave_0_write), // .write
.av_read (sequencer_reg_file_inst_avl_translator_avalon_anti_slave_0_read), // .read
.av_readdata (sequencer_reg_file_inst_avl_translator_avalon_anti_slave_0_readdata), // .readdata
.av_writedata (sequencer_reg_file_inst_avl_translator_avalon_anti_slave_0_writedata), // .writedata
.av_byteenable (sequencer_reg_file_inst_avl_translator_avalon_anti_slave_0_byteenable), // .byteenable
.av_waitrequest (sequencer_reg_file_inst_avl_translator_avalon_anti_slave_0_waitrequest), // .waitrequest
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable () // (terminated)
);
altera_merlin_master_agent #(
.PKT_PROTECTION_H (86),
.PKT_PROTECTION_L (84),
.PKT_BEGIN_BURST (75),
.PKT_BURSTWRAP_H (67),
.PKT_BURSTWRAP_L (65),
.PKT_BURST_SIZE_H (70),
.PKT_BURST_SIZE_L (68),
.PKT_BURST_TYPE_H (72),
.PKT_BURST_TYPE_L (71),
.PKT_BYTE_CNT_H (64),
.PKT_BYTE_CNT_L (62),
.PKT_ADDR_H (55),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (56),
.PKT_TRANS_POSTED (57),
.PKT_TRANS_WRITE (58),
.PKT_TRANS_READ (59),
.PKT_TRANS_LOCK (60),
.PKT_TRANS_EXCLUSIVE (61),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (79),
.PKT_SRC_ID_L (77),
.PKT_DEST_ID_H (82),
.PKT_DEST_ID_L (80),
.PKT_THREAD_ID_H (83),
.PKT_THREAD_ID_L (83),
.PKT_CACHE_H (90),
.PKT_CACHE_L (87),
.PKT_DATA_SIDEBAND_H (74),
.PKT_DATA_SIDEBAND_L (74),
.PKT_QOS_H (76),
.PKT_QOS_L (76),
.PKT_ADDR_SIDEBAND_H (73),
.PKT_ADDR_SIDEBAND_L (73),
.ST_DATA_W (93),
.ST_CHANNEL_W (6),
.AV_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_RSP (0),
.ID (0),
.BURSTWRAP_VALUE (7),
.CACHE_VALUE (4'b0000)
) cpu_inst_data_master_translator_avalon_universal_master_0_agent (
.clk (avl_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.av_address (cpu_inst_data_master_translator_avalon_universal_master_0_address), // av.address
.av_write (cpu_inst_data_master_translator_avalon_universal_master_0_write), // .write
.av_read (cpu_inst_data_master_translator_avalon_universal_master_0_read), // .read
.av_writedata (cpu_inst_data_master_translator_avalon_universal_master_0_writedata), // .writedata
.av_readdata (cpu_inst_data_master_translator_avalon_universal_master_0_readdata), // .readdata
.av_waitrequest (cpu_inst_data_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.av_readdatavalid (cpu_inst_data_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.av_byteenable (cpu_inst_data_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.av_burstcount (cpu_inst_data_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.av_debugaccess (cpu_inst_data_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_lock (cpu_inst_data_master_translator_avalon_universal_master_0_lock), // .lock
.cp_valid (cpu_inst_data_master_translator_avalon_universal_master_0_agent_cp_valid), // cp.valid
.cp_data (cpu_inst_data_master_translator_avalon_universal_master_0_agent_cp_data), // .data
.cp_startofpacket (cpu_inst_data_master_translator_avalon_universal_master_0_agent_cp_startofpacket), // .startofpacket
.cp_endofpacket (cpu_inst_data_master_translator_avalon_universal_master_0_agent_cp_endofpacket), // .endofpacket
.cp_ready (cpu_inst_data_master_translator_avalon_universal_master_0_agent_cp_ready), // .ready
.rp_valid (rsp_xbar_mux_src_valid), // rp.valid
.rp_data (rsp_xbar_mux_src_data), // .data
.rp_channel (rsp_xbar_mux_src_channel), // .channel
.rp_startofpacket (rsp_xbar_mux_src_startofpacket), // .startofpacket
.rp_endofpacket (rsp_xbar_mux_src_endofpacket), // .endofpacket
.rp_ready (rsp_xbar_mux_src_ready) // .ready
);
altera_merlin_master_agent #(
.PKT_PROTECTION_H (86),
.PKT_PROTECTION_L (84),
.PKT_BEGIN_BURST (75),
.PKT_BURSTWRAP_H (67),
.PKT_BURSTWRAP_L (65),
.PKT_BURST_SIZE_H (70),
.PKT_BURST_SIZE_L (68),
.PKT_BURST_TYPE_H (72),
.PKT_BURST_TYPE_L (71),
.PKT_BYTE_CNT_H (64),
.PKT_BYTE_CNT_L (62),
.PKT_ADDR_H (55),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (56),
.PKT_TRANS_POSTED (57),
.PKT_TRANS_WRITE (58),
.PKT_TRANS_READ (59),
.PKT_TRANS_LOCK (60),
.PKT_TRANS_EXCLUSIVE (61),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (79),
.PKT_SRC_ID_L (77),
.PKT_DEST_ID_H (82),
.PKT_DEST_ID_L (80),
.PKT_THREAD_ID_H (83),
.PKT_THREAD_ID_L (83),
.PKT_CACHE_H (90),
.PKT_CACHE_L (87),
.PKT_DATA_SIDEBAND_H (74),
.PKT_DATA_SIDEBAND_L (74),
.PKT_QOS_H (76),
.PKT_QOS_L (76),
.PKT_ADDR_SIDEBAND_H (73),
.PKT_ADDR_SIDEBAND_L (73),
.ST_DATA_W (93),
.ST_CHANNEL_W (6),
.AV_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_RSP (0),
.ID (1),
.BURSTWRAP_VALUE (3),
.CACHE_VALUE (4'b0000)
) cpu_inst_instruction_master_translator_avalon_universal_master_0_agent (
.clk (avl_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.av_address (cpu_inst_instruction_master_translator_avalon_universal_master_0_address), // av.address
.av_write (cpu_inst_instruction_master_translator_avalon_universal_master_0_write), // .write
.av_read (cpu_inst_instruction_master_translator_avalon_universal_master_0_read), // .read
.av_writedata (cpu_inst_instruction_master_translator_avalon_universal_master_0_writedata), // .writedata
.av_readdata (cpu_inst_instruction_master_translator_avalon_universal_master_0_readdata), // .readdata
.av_waitrequest (cpu_inst_instruction_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.av_readdatavalid (cpu_inst_instruction_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.av_byteenable (cpu_inst_instruction_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.av_burstcount (cpu_inst_instruction_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.av_debugaccess (cpu_inst_instruction_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_lock (cpu_inst_instruction_master_translator_avalon_universal_master_0_lock), // .lock
.cp_valid (cpu_inst_instruction_master_translator_avalon_universal_master_0_agent_cp_valid), // cp.valid
.cp_data (cpu_inst_instruction_master_translator_avalon_universal_master_0_agent_cp_data), // .data
.cp_startofpacket (cpu_inst_instruction_master_translator_avalon_universal_master_0_agent_cp_startofpacket), // .startofpacket
.cp_endofpacket (cpu_inst_instruction_master_translator_avalon_universal_master_0_agent_cp_endofpacket), // .endofpacket
.cp_ready (cpu_inst_instruction_master_translator_avalon_universal_master_0_agent_cp_ready), // .ready
.rp_valid (rsp_xbar_demux_003_src1_valid), // rp.valid
.rp_data (rsp_xbar_demux_003_src1_data), // .data
.rp_channel (rsp_xbar_demux_003_src1_channel), // .channel
.rp_startofpacket (rsp_xbar_demux_003_src1_startofpacket), // .startofpacket
.rp_endofpacket (rsp_xbar_demux_003_src1_endofpacket), // .endofpacket
.rp_ready (rsp_xbar_demux_003_src1_ready) // .ready
);
altera_merlin_slave_agent #(
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (75),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_ADDR_H (55),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (56),
.PKT_TRANS_POSTED (57),
.PKT_TRANS_WRITE (58),
.PKT_TRANS_READ (59),
.PKT_TRANS_LOCK (60),
.PKT_SRC_ID_H (79),
.PKT_SRC_ID_L (77),
.PKT_DEST_ID_H (82),
.PKT_DEST_ID_L (80),
.PKT_BURSTWRAP_H (67),
.PKT_BURSTWRAP_L (65),
.PKT_BYTE_CNT_H (64),
.PKT_BYTE_CNT_L (62),
.PKT_PROTECTION_H (86),
.PKT_PROTECTION_L (84),
.PKT_RESPONSE_STATUS_H (92),
.PKT_RESPONSE_STATUS_L (91),
.PKT_BURST_SIZE_H (70),
.PKT_BURST_SIZE_L (68),
.ST_CHANNEL_W (6),
.ST_DATA_W (93),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1)
) sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent (
.clk (avl_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.m0_address (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_address), // m0.address
.m0_burstcount (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.m0_byteenable (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.m0_debugaccess (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.m0_lock (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.m0_readdata (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.m0_readdatavalid (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.m0_read (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_read), // .read
.m0_waitrequest (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.m0_writedata (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.m0_write (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_write), // .write
.rp_endofpacket (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_ready), // .ready
.rp_valid (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.rp_data (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_data), // .data
.rp_startofpacket (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_xbar_demux_src0_ready), // cp.ready
.cp_valid (cmd_xbar_demux_src0_valid), // .valid
.cp_data (cmd_xbar_demux_src0_data), // .data
.cp_startofpacket (cmd_xbar_demux_src0_startofpacket), // .startofpacket
.cp_endofpacket (cmd_xbar_demux_src0_endofpacket), // .endofpacket
.cp_channel (cmd_xbar_demux_src0_channel), // .channel
.rf_sink_ready (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data
.rf_source_ready (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.rf_source_startofpacket (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data) // .data
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (94),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo (
.clk (avl_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.in_data (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data
.in_valid (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.in_ready (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready
.in_startofpacket (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.out_data (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data
.out_valid (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.out_ready (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (75),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_ADDR_H (55),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (56),
.PKT_TRANS_POSTED (57),
.PKT_TRANS_WRITE (58),
.PKT_TRANS_READ (59),
.PKT_TRANS_LOCK (60),
.PKT_SRC_ID_H (79),
.PKT_SRC_ID_L (77),
.PKT_DEST_ID_H (82),
.PKT_DEST_ID_L (80),
.PKT_BURSTWRAP_H (67),
.PKT_BURSTWRAP_L (65),
.PKT_BYTE_CNT_H (64),
.PKT_BYTE_CNT_L (62),
.PKT_PROTECTION_H (86),
.PKT_PROTECTION_L (84),
.PKT_RESPONSE_STATUS_H (92),
.PKT_RESPONSE_STATUS_L (91),
.PKT_BURST_SIZE_H (70),
.PKT_BURST_SIZE_L (68),
.ST_CHANNEL_W (6),
.ST_DATA_W (93),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1)
) sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent (
.clk (avl_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.m0_address (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_address), // m0.address
.m0_burstcount (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.m0_byteenable (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.m0_debugaccess (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.m0_lock (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.m0_readdata (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.m0_readdatavalid (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.m0_read (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_read), // .read
.m0_waitrequest (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.m0_writedata (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.m0_write (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_write), // .write
.rp_endofpacket (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_ready), // .ready
.rp_valid (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.rp_data (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_data), // .data
.rp_startofpacket (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_xbar_demux_src1_ready), // cp.ready
.cp_valid (cmd_xbar_demux_src1_valid), // .valid
.cp_data (cmd_xbar_demux_src1_data), // .data
.cp_startofpacket (cmd_xbar_demux_src1_startofpacket), // .startofpacket
.cp_endofpacket (cmd_xbar_demux_src1_endofpacket), // .endofpacket
.cp_channel (cmd_xbar_demux_src1_channel), // .channel
.rf_sink_ready (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data
.rf_source_ready (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.rf_source_startofpacket (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data) // .data
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (94),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo (
.clk (avl_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.in_data (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data
.in_valid (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.in_ready (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready
.in_startofpacket (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.out_data (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data
.out_valid (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.out_ready (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (75),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_ADDR_H (55),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (56),
.PKT_TRANS_POSTED (57),
.PKT_TRANS_WRITE (58),
.PKT_TRANS_READ (59),
.PKT_TRANS_LOCK (60),
.PKT_SRC_ID_H (79),
.PKT_SRC_ID_L (77),
.PKT_DEST_ID_H (82),
.PKT_DEST_ID_L (80),
.PKT_BURSTWRAP_H (67),
.PKT_BURSTWRAP_L (65),
.PKT_BYTE_CNT_H (64),
.PKT_BYTE_CNT_L (62),
.PKT_PROTECTION_H (86),
.PKT_PROTECTION_L (84),
.PKT_RESPONSE_STATUS_H (92),
.PKT_RESPONSE_STATUS_L (91),
.PKT_BURST_SIZE_H (70),
.PKT_BURST_SIZE_L (68),
.ST_CHANNEL_W (6),
.ST_DATA_W (93),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1)
) sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent (
.clk (avl_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.m0_address (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_address), // m0.address
.m0_burstcount (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.m0_byteenable (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.m0_debugaccess (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.m0_lock (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.m0_readdata (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.m0_readdatavalid (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.m0_read (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_read), // .read
.m0_waitrequest (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.m0_writedata (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.m0_write (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_write), // .write
.rp_endofpacket (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_ready), // .ready
.rp_valid (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.rp_data (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_data), // .data
.rp_startofpacket (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_xbar_demux_src2_ready), // cp.ready
.cp_valid (cmd_xbar_demux_src2_valid), // .valid
.cp_data (cmd_xbar_demux_src2_data), // .data
.cp_startofpacket (cmd_xbar_demux_src2_startofpacket), // .startofpacket
.cp_endofpacket (cmd_xbar_demux_src2_endofpacket), // .endofpacket
.cp_channel (cmd_xbar_demux_src2_channel), // .channel
.rf_sink_ready (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data
.rf_source_ready (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.rf_source_startofpacket (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data) // .data
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (94),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo (
.clk (avl_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.in_data (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data
.in_valid (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.in_ready (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready
.in_startofpacket (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.out_data (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data
.out_valid (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.out_ready (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (75),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_ADDR_H (55),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (56),
.PKT_TRANS_POSTED (57),
.PKT_TRANS_WRITE (58),
.PKT_TRANS_READ (59),
.PKT_TRANS_LOCK (60),
.PKT_SRC_ID_H (79),
.PKT_SRC_ID_L (77),
.PKT_DEST_ID_H (82),
.PKT_DEST_ID_L (80),
.PKT_BURSTWRAP_H (67),
.PKT_BURSTWRAP_L (65),
.PKT_BYTE_CNT_H (64),
.PKT_BYTE_CNT_L (62),
.PKT_PROTECTION_H (86),
.PKT_PROTECTION_L (84),
.PKT_RESPONSE_STATUS_H (92),
.PKT_RESPONSE_STATUS_L (91),
.PKT_BURST_SIZE_H (70),
.PKT_BURST_SIZE_L (68),
.ST_CHANNEL_W (6),
.ST_DATA_W (93),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1)
) sequencer_mem_s1_translator_avalon_universal_slave_0_agent (
.clk (avl_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.m0_address (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_m0_address), // m0.address
.m0_burstcount (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.m0_byteenable (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.m0_debugaccess (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.m0_lock (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.m0_readdata (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.m0_readdatavalid (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.m0_read (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read
.m0_waitrequest (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.m0_writedata (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.m0_write (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write
.rp_endofpacket (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rp_ready), // .ready
.rp_valid (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.rp_data (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data
.rp_startofpacket (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_xbar_mux_003_src_ready), // cp.ready
.cp_valid (cmd_xbar_mux_003_src_valid), // .valid
.cp_data (cmd_xbar_mux_003_src_data), // .data
.cp_startofpacket (cmd_xbar_mux_003_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_xbar_mux_003_src_endofpacket), // .endofpacket
.cp_channel (cmd_xbar_mux_003_src_channel), // .channel
.rf_sink_ready (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data
.rf_source_ready (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.rf_source_startofpacket (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data) // .data
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (94),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rsp_fifo (
.clk (avl_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.in_data (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data
.in_valid (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.in_ready (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready
.in_startofpacket (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.out_data (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data
.out_valid (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.out_ready (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (75),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_ADDR_H (55),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (56),
.PKT_TRANS_POSTED (57),
.PKT_TRANS_WRITE (58),
.PKT_TRANS_READ (59),
.PKT_TRANS_LOCK (60),
.PKT_SRC_ID_H (79),
.PKT_SRC_ID_L (77),
.PKT_DEST_ID_H (82),
.PKT_DEST_ID_L (80),
.PKT_BURSTWRAP_H (67),
.PKT_BURSTWRAP_L (65),
.PKT_BYTE_CNT_H (64),
.PKT_BYTE_CNT_L (62),
.PKT_PROTECTION_H (86),
.PKT_PROTECTION_L (84),
.PKT_RESPONSE_STATUS_H (92),
.PKT_RESPONSE_STATUS_L (91),
.PKT_BURST_SIZE_H (70),
.PKT_BURST_SIZE_L (68),
.ST_CHANNEL_W (6),
.ST_DATA_W (93),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1)
) sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent (
.clk (avl_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.m0_address (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_address), // m0.address
.m0_burstcount (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.m0_byteenable (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.m0_debugaccess (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.m0_lock (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.m0_readdata (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.m0_readdatavalid (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.m0_read (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_read), // .read
.m0_waitrequest (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.m0_writedata (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.m0_write (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_write), // .write
.rp_endofpacket (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_ready), // .ready
.rp_valid (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.rp_data (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_data), // .data
.rp_startofpacket (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_xbar_demux_src4_ready), // cp.ready
.cp_valid (cmd_xbar_demux_src4_valid), // .valid
.cp_data (cmd_xbar_demux_src4_data), // .data
.cp_startofpacket (cmd_xbar_demux_src4_startofpacket), // .startofpacket
.cp_endofpacket (cmd_xbar_demux_src4_endofpacket), // .endofpacket
.cp_channel (cmd_xbar_demux_src4_channel), // .channel
.rf_sink_ready (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data
.rf_source_ready (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.rf_source_startofpacket (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data) // .data
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (94),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo (
.clk (avl_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.in_data (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data
.in_valid (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.in_ready (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready
.in_startofpacket (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.out_data (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data
.out_valid (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.out_ready (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (75),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_ADDR_H (55),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (56),
.PKT_TRANS_POSTED (57),
.PKT_TRANS_WRITE (58),
.PKT_TRANS_READ (59),
.PKT_TRANS_LOCK (60),
.PKT_SRC_ID_H (79),
.PKT_SRC_ID_L (77),
.PKT_DEST_ID_H (82),
.PKT_DEST_ID_L (80),
.PKT_BURSTWRAP_H (67),
.PKT_BURSTWRAP_L (65),
.PKT_BYTE_CNT_H (64),
.PKT_BYTE_CNT_L (62),
.PKT_PROTECTION_H (86),
.PKT_PROTECTION_L (84),
.PKT_RESPONSE_STATUS_H (92),
.PKT_RESPONSE_STATUS_L (91),
.PKT_BURST_SIZE_H (70),
.PKT_BURST_SIZE_L (68),
.ST_CHANNEL_W (6),
.ST_DATA_W (93),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1)
) sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent (
.clk (avl_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.m0_address (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_m0_address), // m0.address
.m0_burstcount (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.m0_byteenable (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.m0_debugaccess (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.m0_lock (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.m0_readdata (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.m0_readdatavalid (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.m0_read (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_m0_read), // .read
.m0_waitrequest (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.m0_writedata (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.m0_write (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_m0_write), // .write
.rp_endofpacket (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rp_ready), // .ready
.rp_valid (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.rp_data (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rp_data), // .data
.rp_startofpacket (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_xbar_demux_src5_ready), // cp.ready
.cp_valid (cmd_xbar_demux_src5_valid), // .valid
.cp_data (cmd_xbar_demux_src5_data), // .data
.cp_startofpacket (cmd_xbar_demux_src5_startofpacket), // .startofpacket
.cp_endofpacket (cmd_xbar_demux_src5_endofpacket), // .endofpacket
.cp_channel (cmd_xbar_demux_src5_channel), // .channel
.rf_sink_ready (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data
.rf_source_ready (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.rf_source_startofpacket (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data) // .data
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (94),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo (
.clk (avl_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.in_data (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data
.in_valid (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.in_ready (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready
.in_startofpacket (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.out_data (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data
.out_valid (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.out_ready (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
DE4_SOPC_ddr2_0_s0_addr_router addr_router (
.sink_ready (cpu_inst_data_master_translator_avalon_universal_master_0_agent_cp_ready), // sink.ready
.sink_valid (cpu_inst_data_master_translator_avalon_universal_master_0_agent_cp_valid), // .valid
.sink_data (cpu_inst_data_master_translator_avalon_universal_master_0_agent_cp_data), // .data
.sink_startofpacket (cpu_inst_data_master_translator_avalon_universal_master_0_agent_cp_startofpacket), // .startofpacket
.sink_endofpacket (cpu_inst_data_master_translator_avalon_universal_master_0_agent_cp_endofpacket), // .endofpacket
.clk (avl_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.src_ready (addr_router_src_ready), // src.ready
.src_valid (addr_router_src_valid), // .valid
.src_data (addr_router_src_data), // .data
.src_channel (addr_router_src_channel), // .channel
.src_startofpacket (addr_router_src_startofpacket), // .startofpacket
.src_endofpacket (addr_router_src_endofpacket) // .endofpacket
);
DE4_SOPC_ddr2_0_s0_addr_router_001 addr_router_001 (
.sink_ready (cpu_inst_instruction_master_translator_avalon_universal_master_0_agent_cp_ready), // sink.ready
.sink_valid (cpu_inst_instruction_master_translator_avalon_universal_master_0_agent_cp_valid), // .valid
.sink_data (cpu_inst_instruction_master_translator_avalon_universal_master_0_agent_cp_data), // .data
.sink_startofpacket (cpu_inst_instruction_master_translator_avalon_universal_master_0_agent_cp_startofpacket), // .startofpacket
.sink_endofpacket (cpu_inst_instruction_master_translator_avalon_universal_master_0_agent_cp_endofpacket), // .endofpacket
.clk (avl_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.src_ready (addr_router_001_src_ready), // src.ready
.src_valid (addr_router_001_src_valid), // .valid
.src_data (addr_router_001_src_data), // .data
.src_channel (addr_router_001_src_channel), // .channel
.src_startofpacket (addr_router_001_src_startofpacket), // .startofpacket
.src_endofpacket (addr_router_001_src_endofpacket) // .endofpacket
);
DE4_SOPC_ddr2_0_s0_id_router id_router (
.sink_ready (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready
.sink_valid (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.sink_data (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_data), // .data
.sink_startofpacket (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket
.clk (avl_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.src_ready (id_router_src_ready), // src.ready
.src_valid (id_router_src_valid), // .valid
.src_data (id_router_src_data), // .data
.src_channel (id_router_src_channel), // .channel
.src_startofpacket (id_router_src_startofpacket), // .startofpacket
.src_endofpacket (id_router_src_endofpacket) // .endofpacket
);
DE4_SOPC_ddr2_0_s0_id_router id_router_001 (
.sink_ready (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready
.sink_valid (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.sink_data (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_data), // .data
.sink_startofpacket (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket
.clk (avl_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.src_ready (id_router_001_src_ready), // src.ready
.src_valid (id_router_001_src_valid), // .valid
.src_data (id_router_001_src_data), // .data
.src_channel (id_router_001_src_channel), // .channel
.src_startofpacket (id_router_001_src_startofpacket), // .startofpacket
.src_endofpacket (id_router_001_src_endofpacket) // .endofpacket
);
DE4_SOPC_ddr2_0_s0_id_router id_router_002 (
.sink_ready (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready
.sink_valid (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.sink_data (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_data), // .data
.sink_startofpacket (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket
.clk (avl_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.src_ready (id_router_002_src_ready), // src.ready
.src_valid (id_router_002_src_valid), // .valid
.src_data (id_router_002_src_data), // .data
.src_channel (id_router_002_src_channel), // .channel
.src_startofpacket (id_router_002_src_startofpacket), // .startofpacket
.src_endofpacket (id_router_002_src_endofpacket) // .endofpacket
);
DE4_SOPC_ddr2_0_s0_id_router_003 id_router_003 (
.sink_ready (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready
.sink_valid (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.sink_data (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data
.sink_startofpacket (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket
.clk (avl_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.src_ready (id_router_003_src_ready), // src.ready
.src_valid (id_router_003_src_valid), // .valid
.src_data (id_router_003_src_data), // .data
.src_channel (id_router_003_src_channel), // .channel
.src_startofpacket (id_router_003_src_startofpacket), // .startofpacket
.src_endofpacket (id_router_003_src_endofpacket) // .endofpacket
);
DE4_SOPC_ddr2_0_s0_id_router id_router_004 (
.sink_ready (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready
.sink_valid (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.sink_data (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_data), // .data
.sink_startofpacket (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket
.clk (avl_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.src_ready (id_router_004_src_ready), // src.ready
.src_valid (id_router_004_src_valid), // .valid
.src_data (id_router_004_src_data), // .data
.src_channel (id_router_004_src_channel), // .channel
.src_startofpacket (id_router_004_src_startofpacket), // .startofpacket
.src_endofpacket (id_router_004_src_endofpacket) // .endofpacket
);
DE4_SOPC_ddr2_0_s0_id_router id_router_005 (
.sink_ready (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready
.sink_valid (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.sink_data (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rp_data), // .data
.sink_startofpacket (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket
.clk (avl_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.src_ready (id_router_005_src_ready), // src.ready
.src_valid (id_router_005_src_valid), // .valid
.src_data (id_router_005_src_data), // .data
.src_channel (id_router_005_src_channel), // .channel
.src_startofpacket (id_router_005_src_startofpacket), // .startofpacket
.src_endofpacket (id_router_005_src_endofpacket) // .endofpacket
);
altera_reset_controller #(
.NUM_RESET_INPUTS (1),
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
.SYNC_DEPTH (2)
) rst_controller (
.reset_in0 (~avl_reset_n), // reset_in0.reset
.clk (avl_clk), // clk.clk
.reset_out (rst_controller_reset_out_reset), // reset_out.reset
.reset_in1 (1'b0), // (terminated)
.reset_in2 (1'b0), // (terminated)
.reset_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_in10 (1'b0), // (terminated)
.reset_in11 (1'b0), // (terminated)
.reset_in12 (1'b0), // (terminated)
.reset_in13 (1'b0), // (terminated)
.reset_in14 (1'b0), // (terminated)
.reset_in15 (1'b0) // (terminated)
);
DE4_SOPC_ddr2_0_s0_cmd_xbar_demux cmd_xbar_demux (
.clk (avl_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.sink_ready (addr_router_src_ready), // sink.ready
.sink_channel (addr_router_src_channel), // .channel
.sink_data (addr_router_src_data), // .data
.sink_startofpacket (addr_router_src_startofpacket), // .startofpacket
.sink_endofpacket (addr_router_src_endofpacket), // .endofpacket
.sink_valid (addr_router_src_valid), // .valid
.src0_ready (cmd_xbar_demux_src0_ready), // src0.ready
.src0_valid (cmd_xbar_demux_src0_valid), // .valid
.src0_data (cmd_xbar_demux_src0_data), // .data
.src0_channel (cmd_xbar_demux_src0_channel), // .channel
.src0_startofpacket (cmd_xbar_demux_src0_startofpacket), // .startofpacket
.src0_endofpacket (cmd_xbar_demux_src0_endofpacket), // .endofpacket
.src1_ready (cmd_xbar_demux_src1_ready), // src1.ready
.src1_valid (cmd_xbar_demux_src1_valid), // .valid
.src1_data (cmd_xbar_demux_src1_data), // .data
.src1_channel (cmd_xbar_demux_src1_channel), // .channel
.src1_startofpacket (cmd_xbar_demux_src1_startofpacket), // .startofpacket
.src1_endofpacket (cmd_xbar_demux_src1_endofpacket), // .endofpacket
.src2_ready (cmd_xbar_demux_src2_ready), // src2.ready
.src2_valid (cmd_xbar_demux_src2_valid), // .valid
.src2_data (cmd_xbar_demux_src2_data), // .data
.src2_channel (cmd_xbar_demux_src2_channel), // .channel
.src2_startofpacket (cmd_xbar_demux_src2_startofpacket), // .startofpacket
.src2_endofpacket (cmd_xbar_demux_src2_endofpacket), // .endofpacket
.src3_ready (cmd_xbar_demux_src3_ready), // src3.ready
.src3_valid (cmd_xbar_demux_src3_valid), // .valid
.src3_data (cmd_xbar_demux_src3_data), // .data
.src3_channel (cmd_xbar_demux_src3_channel), // .channel
.src3_startofpacket (cmd_xbar_demux_src3_startofpacket), // .startofpacket
.src3_endofpacket (cmd_xbar_demux_src3_endofpacket), // .endofpacket
.src4_ready (cmd_xbar_demux_src4_ready), // src4.ready
.src4_valid (cmd_xbar_demux_src4_valid), // .valid
.src4_data (cmd_xbar_demux_src4_data), // .data
.src4_channel (cmd_xbar_demux_src4_channel), // .channel
.src4_startofpacket (cmd_xbar_demux_src4_startofpacket), // .startofpacket
.src4_endofpacket (cmd_xbar_demux_src4_endofpacket), // .endofpacket
.src5_ready (cmd_xbar_demux_src5_ready), // src5.ready
.src5_valid (cmd_xbar_demux_src5_valid), // .valid
.src5_data (cmd_xbar_demux_src5_data), // .data
.src5_channel (cmd_xbar_demux_src5_channel), // .channel
.src5_startofpacket (cmd_xbar_demux_src5_startofpacket), // .startofpacket
.src5_endofpacket (cmd_xbar_demux_src5_endofpacket) // .endofpacket
);
DE4_SOPC_ddr2_0_s0_cmd_xbar_demux_001 cmd_xbar_demux_001 (
.clk (avl_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.sink_ready (addr_router_001_src_ready), // sink.ready
.sink_channel (addr_router_001_src_channel), // .channel
.sink_data (addr_router_001_src_data), // .data
.sink_startofpacket (addr_router_001_src_startofpacket), // .startofpacket
.sink_endofpacket (addr_router_001_src_endofpacket), // .endofpacket
.sink_valid (addr_router_001_src_valid), // .valid
.src0_ready (cmd_xbar_demux_001_src0_ready), // src0.ready
.src0_valid (cmd_xbar_demux_001_src0_valid), // .valid
.src0_data (cmd_xbar_demux_001_src0_data), // .data
.src0_channel (cmd_xbar_demux_001_src0_channel), // .channel
.src0_startofpacket (cmd_xbar_demux_001_src0_startofpacket), // .startofpacket
.src0_endofpacket (cmd_xbar_demux_001_src0_endofpacket) // .endofpacket
);
DE4_SOPC_ddr2_0_s0_cmd_xbar_mux_003 cmd_xbar_mux_003 (
.clk (avl_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.src_ready (cmd_xbar_mux_003_src_ready), // src.ready
.src_valid (cmd_xbar_mux_003_src_valid), // .valid
.src_data (cmd_xbar_mux_003_src_data), // .data
.src_channel (cmd_xbar_mux_003_src_channel), // .channel
.src_startofpacket (cmd_xbar_mux_003_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_xbar_mux_003_src_endofpacket), // .endofpacket
.sink0_ready (cmd_xbar_demux_src3_ready), // sink0.ready
.sink0_valid (cmd_xbar_demux_src3_valid), // .valid
.sink0_channel (cmd_xbar_demux_src3_channel), // .channel
.sink0_data (cmd_xbar_demux_src3_data), // .data
.sink0_startofpacket (cmd_xbar_demux_src3_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_xbar_demux_src3_endofpacket), // .endofpacket
.sink1_ready (cmd_xbar_demux_001_src0_ready), // sink1.ready
.sink1_valid (cmd_xbar_demux_001_src0_valid), // .valid
.sink1_channel (cmd_xbar_demux_001_src0_channel), // .channel
.sink1_data (cmd_xbar_demux_001_src0_data), // .data
.sink1_startofpacket (cmd_xbar_demux_001_src0_startofpacket), // .startofpacket
.sink1_endofpacket (cmd_xbar_demux_001_src0_endofpacket) // .endofpacket
);
DE4_SOPC_ddr2_0_s0_cmd_xbar_demux_001 rsp_xbar_demux (
.clk (avl_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.sink_ready (id_router_src_ready), // sink.ready
.sink_channel (id_router_src_channel), // .channel
.sink_data (id_router_src_data), // .data
.sink_startofpacket (id_router_src_startofpacket), // .startofpacket
.sink_endofpacket (id_router_src_endofpacket), // .endofpacket
.sink_valid (id_router_src_valid), // .valid
.src0_ready (rsp_xbar_demux_src0_ready), // src0.ready
.src0_valid (rsp_xbar_demux_src0_valid), // .valid
.src0_data (rsp_xbar_demux_src0_data), // .data
.src0_channel (rsp_xbar_demux_src0_channel), // .channel
.src0_startofpacket (rsp_xbar_demux_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_xbar_demux_src0_endofpacket) // .endofpacket
);
DE4_SOPC_ddr2_0_s0_cmd_xbar_demux_001 rsp_xbar_demux_001 (
.clk (avl_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.sink_ready (id_router_001_src_ready), // sink.ready
.sink_channel (id_router_001_src_channel), // .channel
.sink_data (id_router_001_src_data), // .data
.sink_startofpacket (id_router_001_src_startofpacket), // .startofpacket
.sink_endofpacket (id_router_001_src_endofpacket), // .endofpacket
.sink_valid (id_router_001_src_valid), // .valid
.src0_ready (rsp_xbar_demux_001_src0_ready), // src0.ready
.src0_valid (rsp_xbar_demux_001_src0_valid), // .valid
.src0_data (rsp_xbar_demux_001_src0_data), // .data
.src0_channel (rsp_xbar_demux_001_src0_channel), // .channel
.src0_startofpacket (rsp_xbar_demux_001_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_xbar_demux_001_src0_endofpacket) // .endofpacket
);
DE4_SOPC_ddr2_0_s0_cmd_xbar_demux_001 rsp_xbar_demux_002 (
.clk (avl_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.sink_ready (id_router_002_src_ready), // sink.ready
.sink_channel (id_router_002_src_channel), // .channel
.sink_data (id_router_002_src_data), // .data
.sink_startofpacket (id_router_002_src_startofpacket), // .startofpacket
.sink_endofpacket (id_router_002_src_endofpacket), // .endofpacket
.sink_valid (id_router_002_src_valid), // .valid
.src0_ready (rsp_xbar_demux_002_src0_ready), // src0.ready
.src0_valid (rsp_xbar_demux_002_src0_valid), // .valid
.src0_data (rsp_xbar_demux_002_src0_data), // .data
.src0_channel (rsp_xbar_demux_002_src0_channel), // .channel
.src0_startofpacket (rsp_xbar_demux_002_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_xbar_demux_002_src0_endofpacket) // .endofpacket
);
DE4_SOPC_ddr2_0_s0_rsp_xbar_demux_003 rsp_xbar_demux_003 (
.clk (avl_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.sink_ready (id_router_003_src_ready), // sink.ready
.sink_channel (id_router_003_src_channel), // .channel
.sink_data (id_router_003_src_data), // .data
.sink_startofpacket (id_router_003_src_startofpacket), // .startofpacket
.sink_endofpacket (id_router_003_src_endofpacket), // .endofpacket
.sink_valid (id_router_003_src_valid), // .valid
.src0_ready (rsp_xbar_demux_003_src0_ready), // src0.ready
.src0_valid (rsp_xbar_demux_003_src0_valid), // .valid
.src0_data (rsp_xbar_demux_003_src0_data), // .data
.src0_channel (rsp_xbar_demux_003_src0_channel), // .channel
.src0_startofpacket (rsp_xbar_demux_003_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_xbar_demux_003_src0_endofpacket), // .endofpacket
.src1_ready (rsp_xbar_demux_003_src1_ready), // src1.ready
.src1_valid (rsp_xbar_demux_003_src1_valid), // .valid
.src1_data (rsp_xbar_demux_003_src1_data), // .data
.src1_channel (rsp_xbar_demux_003_src1_channel), // .channel
.src1_startofpacket (rsp_xbar_demux_003_src1_startofpacket), // .startofpacket
.src1_endofpacket (rsp_xbar_demux_003_src1_endofpacket) // .endofpacket
);
DE4_SOPC_ddr2_0_s0_cmd_xbar_demux_001 rsp_xbar_demux_004 (
.clk (avl_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.sink_ready (id_router_004_src_ready), // sink.ready
.sink_channel (id_router_004_src_channel), // .channel
.sink_data (id_router_004_src_data), // .data
.sink_startofpacket (id_router_004_src_startofpacket), // .startofpacket
.sink_endofpacket (id_router_004_src_endofpacket), // .endofpacket
.sink_valid (id_router_004_src_valid), // .valid
.src0_ready (rsp_xbar_demux_004_src0_ready), // src0.ready
.src0_valid (rsp_xbar_demux_004_src0_valid), // .valid
.src0_data (rsp_xbar_demux_004_src0_data), // .data
.src0_channel (rsp_xbar_demux_004_src0_channel), // .channel
.src0_startofpacket (rsp_xbar_demux_004_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_xbar_demux_004_src0_endofpacket) // .endofpacket
);
DE4_SOPC_ddr2_0_s0_cmd_xbar_demux_001 rsp_xbar_demux_005 (
.clk (avl_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.sink_ready (id_router_005_src_ready), // sink.ready
.sink_channel (id_router_005_src_channel), // .channel
.sink_data (id_router_005_src_data), // .data
.sink_startofpacket (id_router_005_src_startofpacket), // .startofpacket
.sink_endofpacket (id_router_005_src_endofpacket), // .endofpacket
.sink_valid (id_router_005_src_valid), // .valid
.src0_ready (rsp_xbar_demux_005_src0_ready), // src0.ready
.src0_valid (rsp_xbar_demux_005_src0_valid), // .valid
.src0_data (rsp_xbar_demux_005_src0_data), // .data
.src0_channel (rsp_xbar_demux_005_src0_channel), // .channel
.src0_startofpacket (rsp_xbar_demux_005_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_xbar_demux_005_src0_endofpacket) // .endofpacket
);
DE4_SOPC_ddr2_0_s0_rsp_xbar_mux rsp_xbar_mux (
.clk (avl_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.src_ready (rsp_xbar_mux_src_ready), // src.ready
.src_valid (rsp_xbar_mux_src_valid), // .valid
.src_data (rsp_xbar_mux_src_data), // .data
.src_channel (rsp_xbar_mux_src_channel), // .channel
.src_startofpacket (rsp_xbar_mux_src_startofpacket), // .startofpacket
.src_endofpacket (rsp_xbar_mux_src_endofpacket), // .endofpacket
.sink0_ready (rsp_xbar_demux_src0_ready), // sink0.ready
.sink0_valid (rsp_xbar_demux_src0_valid), // .valid
.sink0_channel (rsp_xbar_demux_src0_channel), // .channel
.sink0_data (rsp_xbar_demux_src0_data), // .data
.sink0_startofpacket (rsp_xbar_demux_src0_startofpacket), // .startofpacket
.sink0_endofpacket (rsp_xbar_demux_src0_endofpacket), // .endofpacket
.sink1_ready (rsp_xbar_demux_001_src0_ready), // sink1.ready
.sink1_valid (rsp_xbar_demux_001_src0_valid), // .valid
.sink1_channel (rsp_xbar_demux_001_src0_channel), // .channel
.sink1_data (rsp_xbar_demux_001_src0_data), // .data
.sink1_startofpacket (rsp_xbar_demux_001_src0_startofpacket), // .startofpacket
.sink1_endofpacket (rsp_xbar_demux_001_src0_endofpacket), // .endofpacket
.sink2_ready (rsp_xbar_demux_002_src0_ready), // sink2.ready
.sink2_valid (rsp_xbar_demux_002_src0_valid), // .valid
.sink2_channel (rsp_xbar_demux_002_src0_channel), // .channel
.sink2_data (rsp_xbar_demux_002_src0_data), // .data
.sink2_startofpacket (rsp_xbar_demux_002_src0_startofpacket), // .startofpacket
.sink2_endofpacket (rsp_xbar_demux_002_src0_endofpacket), // .endofpacket
.sink3_ready (rsp_xbar_demux_003_src0_ready), // sink3.ready
.sink3_valid (rsp_xbar_demux_003_src0_valid), // .valid
.sink3_channel (rsp_xbar_demux_003_src0_channel), // .channel
.sink3_data (rsp_xbar_demux_003_src0_data), // .data
.sink3_startofpacket (rsp_xbar_demux_003_src0_startofpacket), // .startofpacket
.sink3_endofpacket (rsp_xbar_demux_003_src0_endofpacket), // .endofpacket
.sink4_ready (rsp_xbar_demux_004_src0_ready), // sink4.ready
.sink4_valid (rsp_xbar_demux_004_src0_valid), // .valid
.sink4_channel (rsp_xbar_demux_004_src0_channel), // .channel
.sink4_data (rsp_xbar_demux_004_src0_data), // .data
.sink4_startofpacket (rsp_xbar_demux_004_src0_startofpacket), // .startofpacket
.sink4_endofpacket (rsp_xbar_demux_004_src0_endofpacket), // .endofpacket
.sink5_ready (rsp_xbar_demux_005_src0_ready), // sink5.ready
.sink5_valid (rsp_xbar_demux_005_src0_valid), // .valid
.sink5_channel (rsp_xbar_demux_005_src0_channel), // .channel
.sink5_data (rsp_xbar_demux_005_src0_data), // .data
.sink5_startofpacket (rsp_xbar_demux_005_src0_startofpacket), // .startofpacket
.sink5_endofpacket (rsp_xbar_demux_005_src0_endofpacket) // .endofpacket
);
DE4_SOPC_ddr2_0_s0_irq_mapper irq_mapper (
.clk (avl_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.sender_irq (cpu_inst_d_irq_irq) // sender.irq
);
endmodule
|
//Legal Notice: (C)2013 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module DE4_SOPC_debug_uart_log_module (
// inputs:
clk,
data,
strobe,
valid
)
;
input clk;
input [ 7: 0] data;
input strobe;
input valid;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
reg [31:0] text_handle; // for $fopen
initial text_handle = $fopen ("DE4_SOPC_debug_uart_output_stream.dat");
always @(posedge clk) begin
if (valid && strobe) begin
$fwrite (text_handle, "%b\n", data);
// echo raw binary strings to file as ascii to screen
$write("%s", ((data == 8'hd) ? 8'ha : data));
// non-standard; poorly documented; required to get real data stream.
$fflush (text_handle);
end
end // clk
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module DE4_SOPC_debug_uart_sim_scfifo_w (
// inputs:
clk,
fifo_wdata,
fifo_wr,
// outputs:
fifo_FF,
r_dat,
wfifo_empty,
wfifo_used
)
;
output fifo_FF;
output [ 7: 0] r_dat;
output wfifo_empty;
output [ 5: 0] wfifo_used;
input clk;
input [ 7: 0] fifo_wdata;
input fifo_wr;
wire fifo_FF;
wire [ 7: 0] r_dat;
wire wfifo_empty;
wire [ 5: 0] wfifo_used;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
//DE4_SOPC_debug_uart_log, which is an e_log
DE4_SOPC_debug_uart_log_module DE4_SOPC_debug_uart_log
(
.clk (clk),
.data (fifo_wdata),
.strobe (fifo_wr),
.valid (fifo_wr)
);
assign wfifo_used = {6{1'b0}};
assign r_dat = {8{1'b0}};
assign fifo_FF = 1'b0;
assign wfifo_empty = 1'b1;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module DE4_SOPC_debug_uart_scfifo_w (
// inputs:
clk,
fifo_clear,
fifo_wdata,
fifo_wr,
rd_wfifo,
// outputs:
fifo_FF,
r_dat,
wfifo_empty,
wfifo_used
)
;
output fifo_FF;
output [ 7: 0] r_dat;
output wfifo_empty;
output [ 5: 0] wfifo_used;
input clk;
input fifo_clear;
input [ 7: 0] fifo_wdata;
input fifo_wr;
input rd_wfifo;
wire fifo_FF;
wire [ 7: 0] r_dat;
wire wfifo_empty;
wire [ 5: 0] wfifo_used;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
DE4_SOPC_debug_uart_sim_scfifo_w the_DE4_SOPC_debug_uart_sim_scfifo_w
(
.clk (clk),
.fifo_FF (fifo_FF),
.fifo_wdata (fifo_wdata),
.fifo_wr (fifo_wr),
.r_dat (r_dat),
.wfifo_empty (wfifo_empty),
.wfifo_used (wfifo_used)
);
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// scfifo wfifo
// (
// .aclr (fifo_clear),
// .clock (clk),
// .data (fifo_wdata),
// .empty (wfifo_empty),
// .full (fifo_FF),
// .q (r_dat),
// .rdreq (rd_wfifo),
// .usedw (wfifo_used),
// .wrreq (fifo_wr)
// );
//
// defparam wfifo.lpm_hint = "RAM_BLOCK_TYPE=AUTO",
// wfifo.lpm_numwords = 64,
// wfifo.lpm_showahead = "OFF",
// wfifo.lpm_type = "scfifo",
// wfifo.lpm_width = 8,
// wfifo.lpm_widthu = 6,
// wfifo.overflow_checking = "OFF",
// wfifo.underflow_checking = "OFF",
// wfifo.use_eab = "ON";
//
//synthesis read_comments_as_HDL off
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module DE4_SOPC_debug_uart_drom_module (
// inputs:
clk,
incr_addr,
reset_n,
// outputs:
new_rom,
num_bytes,
q,
safe
)
;
parameter POLL_RATE = 100;
output new_rom;
output [ 31: 0] num_bytes;
output [ 7: 0] q;
output safe;
input clk;
input incr_addr;
input reset_n;
reg [ 11: 0] address;
reg d1_pre;
reg d2_pre;
reg d3_pre;
reg d4_pre;
reg d5_pre;
reg d6_pre;
reg d7_pre;
reg d8_pre;
reg d9_pre;
reg [ 7: 0] mem_array [2047: 0];
reg [ 31: 0] mutex [ 1: 0];
reg new_rom;
wire [ 31: 0] num_bytes;
reg pre;
wire [ 7: 0] q;
wire safe;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
assign q = mem_array[address];
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
d1_pre <= 0;
d2_pre <= 0;
d3_pre <= 0;
d4_pre <= 0;
d5_pre <= 0;
d6_pre <= 0;
d7_pre <= 0;
d8_pre <= 0;
d9_pre <= 0;
new_rom <= 0;
end
else
begin
d1_pre <= pre;
d2_pre <= d1_pre;
d3_pre <= d2_pre;
d4_pre <= d3_pre;
d5_pre <= d4_pre;
d6_pre <= d5_pre;
d7_pre <= d6_pre;
d8_pre <= d7_pre;
d9_pre <= d8_pre;
new_rom <= d9_pre;
end
end
assign num_bytes = mutex[1];
reg safe_delay;
reg [31:0] poll_count;
reg [31:0] mutex_handle;
wire interactive = 1'b0 ; // '
assign safe = (address < mutex[1]);
initial poll_count = POLL_RATE;
always @(posedge clk or negedge reset_n) begin
if (reset_n !== 1) begin
safe_delay <= 0;
end else begin
safe_delay <= safe;
end
end // safe_delay
always @(posedge clk or negedge reset_n) begin
if (reset_n !== 1) begin // dont worry about null _stream.dat file
address <= 0;
mem_array[0] <= 0;
mutex[0] <= 0;
mutex[1] <= 0;
pre <= 0;
end else begin // deal with the non-reset case
pre <= 0;
if (incr_addr && safe) address <= address + 1;
if (mutex[0] && !safe && safe_delay) begin
// and blast the mutex after falling edge of safe if interactive
if (interactive) begin
mutex_handle = $fopen ("DE4_SOPC_debug_uart_input_mutex.dat");
$fdisplay (mutex_handle, "0");
$fclose (mutex_handle);
// $display ($stime, "\t%m:\n\t\tMutex cleared!");
end else begin
// sleep until next reset, do not bash mutex.
wait (!reset_n);
end
end // OK to bash mutex.
if (poll_count < POLL_RATE) begin // wait
poll_count = poll_count + 1;
end else begin // do the interesting stuff.
poll_count = 0;
if (mutex_handle) begin
$readmemh ("DE4_SOPC_debug_uart_input_mutex.dat", mutex);
end
if (mutex[0] && !safe) begin
// read stream into mem_array after current characters are gone!
// save mutex[0] value to compare to address (generates 'safe')
mutex[1] <= mutex[0];
// $display ($stime, "\t%m:\n\t\tMutex hit: Trying to read %d bytes...", mutex[0]);
$readmemb("DE4_SOPC_debug_uart_input_stream.dat", mem_array);
// bash address and send pulse outside to send the char:
address <= 0;
pre <= -1;
end // else mutex miss...
end // poll_count
end // reset
end // posedge clk
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module DE4_SOPC_debug_uart_sim_scfifo_r (
// inputs:
clk,
fifo_rd,
rst_n,
// outputs:
fifo_EF,
fifo_rdata,
rfifo_full,
rfifo_used
)
;
output fifo_EF;
output [ 7: 0] fifo_rdata;
output rfifo_full;
output [ 5: 0] rfifo_used;
input clk;
input fifo_rd;
input rst_n;
reg [ 31: 0] bytes_left;
wire fifo_EF;
reg fifo_rd_d;
wire [ 7: 0] fifo_rdata;
wire new_rom;
wire [ 31: 0] num_bytes;
wire [ 6: 0] rfifo_entries;
wire rfifo_full;
wire [ 5: 0] rfifo_used;
wire safe;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
//DE4_SOPC_debug_uart_drom, which is an e_drom
DE4_SOPC_debug_uart_drom_module DE4_SOPC_debug_uart_drom
(
.clk (clk),
.incr_addr (fifo_rd_d),
.new_rom (new_rom),
.num_bytes (num_bytes),
.q (fifo_rdata),
.reset_n (rst_n),
.safe (safe)
);
// Generate rfifo_entries for simulation
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 0)
begin
bytes_left <= 32'h0;
fifo_rd_d <= 1'b0;
end
else
begin
fifo_rd_d <= fifo_rd;
// decrement on read
if (fifo_rd_d)
bytes_left <= bytes_left - 1'b1;
// catch new contents
if (new_rom)
bytes_left <= num_bytes;
end
end
assign fifo_EF = bytes_left == 32'b0;
assign rfifo_full = bytes_left > 7'h40;
assign rfifo_entries = (rfifo_full) ? 7'h40 : bytes_left;
assign rfifo_used = rfifo_entries[5 : 0];
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module DE4_SOPC_debug_uart_scfifo_r (
// inputs:
clk,
fifo_clear,
fifo_rd,
rst_n,
t_dat,
wr_rfifo,
// outputs:
fifo_EF,
fifo_rdata,
rfifo_full,
rfifo_used
)
;
output fifo_EF;
output [ 7: 0] fifo_rdata;
output rfifo_full;
output [ 5: 0] rfifo_used;
input clk;
input fifo_clear;
input fifo_rd;
input rst_n;
input [ 7: 0] t_dat;
input wr_rfifo;
wire fifo_EF;
wire [ 7: 0] fifo_rdata;
wire rfifo_full;
wire [ 5: 0] rfifo_used;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
DE4_SOPC_debug_uart_sim_scfifo_r the_DE4_SOPC_debug_uart_sim_scfifo_r
(
.clk (clk),
.fifo_EF (fifo_EF),
.fifo_rd (fifo_rd),
.fifo_rdata (fifo_rdata),
.rfifo_full (rfifo_full),
.rfifo_used (rfifo_used),
.rst_n (rst_n)
);
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// scfifo rfifo
// (
// .aclr (fifo_clear),
// .clock (clk),
// .data (t_dat),
// .empty (fifo_EF),
// .full (rfifo_full),
// .q (fifo_rdata),
// .rdreq (fifo_rd),
// .usedw (rfifo_used),
// .wrreq (wr_rfifo)
// );
//
// defparam rfifo.lpm_hint = "RAM_BLOCK_TYPE=AUTO",
// rfifo.lpm_numwords = 64,
// rfifo.lpm_showahead = "OFF",
// rfifo.lpm_type = "scfifo",
// rfifo.lpm_width = 8,
// rfifo.lpm_widthu = 6,
// rfifo.overflow_checking = "OFF",
// rfifo.underflow_checking = "OFF",
// rfifo.use_eab = "ON";
//
//synthesis read_comments_as_HDL off
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module DE4_SOPC_debug_uart (
// inputs:
av_address,
av_chipselect,
av_read_n,
av_write_n,
av_writedata,
clk,
rst_n,
// outputs:
av_irq,
av_readdata,
av_waitrequest,
dataavailable,
readyfordata
)
/* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"R101,C106,D101,D103\"" */ ;
output av_irq;
output [ 31: 0] av_readdata;
output av_waitrequest;
output dataavailable;
output readyfordata;
input av_address;
input av_chipselect;
input av_read_n;
input av_write_n;
input [ 31: 0] av_writedata;
input clk;
input rst_n;
reg ac;
wire activity;
wire av_irq;
wire [ 31: 0] av_readdata;
reg av_waitrequest;
reg dataavailable;
reg fifo_AE;
reg fifo_AF;
wire fifo_EF;
wire fifo_FF;
wire fifo_clear;
wire fifo_rd;
wire [ 7: 0] fifo_rdata;
wire [ 7: 0] fifo_wdata;
reg fifo_wr;
reg ien_AE;
reg ien_AF;
wire ipen_AE;
wire ipen_AF;
reg pause_irq;
wire [ 7: 0] r_dat;
wire r_ena;
reg r_val;
wire rd_wfifo;
reg read_0;
reg readyfordata;
wire rfifo_full;
wire [ 5: 0] rfifo_used;
reg rvalid;
reg sim_r_ena;
reg sim_t_dat;
reg sim_t_ena;
reg sim_t_pause;
wire [ 7: 0] t_dat;
reg t_dav;
wire t_ena;
wire t_pause;
wire wfifo_empty;
wire [ 5: 0] wfifo_used;
reg woverflow;
wire wr_rfifo;
//avalon_jtag_slave, which is an e_avalon_slave
assign rd_wfifo = r_ena & ~wfifo_empty;
assign wr_rfifo = t_ena & ~rfifo_full;
assign fifo_clear = ~rst_n;
DE4_SOPC_debug_uart_scfifo_w the_DE4_SOPC_debug_uart_scfifo_w
(
.clk (clk),
.fifo_FF (fifo_FF),
.fifo_clear (fifo_clear),
.fifo_wdata (fifo_wdata),
.fifo_wr (fifo_wr),
.r_dat (r_dat),
.rd_wfifo (rd_wfifo),
.wfifo_empty (wfifo_empty),
.wfifo_used (wfifo_used)
);
DE4_SOPC_debug_uart_scfifo_r the_DE4_SOPC_debug_uart_scfifo_r
(
.clk (clk),
.fifo_EF (fifo_EF),
.fifo_clear (fifo_clear),
.fifo_rd (fifo_rd),
.fifo_rdata (fifo_rdata),
.rfifo_full (rfifo_full),
.rfifo_used (rfifo_used),
.rst_n (rst_n),
.t_dat (t_dat),
.wr_rfifo (wr_rfifo)
);
assign ipen_AE = ien_AE & fifo_AE;
assign ipen_AF = ien_AF & (pause_irq | fifo_AF);
assign av_irq = ipen_AE | ipen_AF;
assign activity = t_pause | t_ena;
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 0)
pause_irq <= 1'b0;
else // only if fifo is not empty...
if (t_pause & ~fifo_EF)
pause_irq <= 1'b1;
else if (read_0)
pause_irq <= 1'b0;
end
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 0)
begin
r_val <= 1'b0;
t_dav <= 1'b1;
end
else
begin
r_val <= r_ena & ~wfifo_empty;
t_dav <= ~rfifo_full;
end
end
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 0)
begin
fifo_AE <= 1'b0;
fifo_AF <= 1'b0;
fifo_wr <= 1'b0;
rvalid <= 1'b0;
read_0 <= 1'b0;
ien_AE <= 1'b0;
ien_AF <= 1'b0;
ac <= 1'b0;
woverflow <= 1'b0;
av_waitrequest <= 1'b1;
end
else
begin
fifo_AE <= {fifo_FF,wfifo_used} <= 8;
fifo_AF <= (7'h40 - {rfifo_full,rfifo_used}) <= 8;
fifo_wr <= 1'b0;
read_0 <= 1'b0;
av_waitrequest <= ~(av_chipselect & (~av_write_n | ~av_read_n) & av_waitrequest);
if (activity)
ac <= 1'b1;
// write
if (av_chipselect & ~av_write_n & av_waitrequest)
// addr 1 is control; addr 0 is data
if (av_address)
begin
ien_AF <= av_writedata[0];
ien_AE <= av_writedata[1];
if (av_writedata[10] & ~activity)
ac <= 1'b0;
end
else
begin
fifo_wr <= ~fifo_FF;
woverflow <= fifo_FF;
end
// read
if (av_chipselect & ~av_read_n & av_waitrequest)
begin
// addr 1 is interrupt; addr 0 is data
if (~av_address)
rvalid <= ~fifo_EF;
read_0 <= ~av_address;
end
end
end
assign fifo_wdata = av_writedata[7 : 0];
assign fifo_rd = (av_chipselect & ~av_read_n & av_waitrequest & ~av_address) ? ~fifo_EF : 1'b0;
assign av_readdata = read_0 ? { {9{1'b0}},rfifo_full,rfifo_used,rvalid,woverflow,~fifo_FF,~fifo_EF,1'b0,ac,ipen_AE,ipen_AF,fifo_rdata } : { {9{1'b0}},(7'h40 - {fifo_FF,wfifo_used}),rvalid,woverflow,~fifo_FF,~fifo_EF,1'b0,ac,ipen_AE,ipen_AF,{6{1'b0}},ien_AE,ien_AF };
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 0)
readyfordata <= 0;
else
readyfordata <= ~fifo_FF;
end
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
// Tie off Atlantic Interface signals not used for simulation
always @(posedge clk)
begin
sim_t_pause <= 1'b0;
sim_t_ena <= 1'b0;
sim_t_dat <= t_dav ? r_dat : {8{r_val}};
sim_r_ena <= 1'b0;
end
assign r_ena = sim_r_ena;
assign t_ena = sim_t_ena;
assign t_dat = sim_t_dat;
assign t_pause = sim_t_pause;
always @(fifo_EF)
begin
dataavailable = ~fifo_EF;
end
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// alt_jtag_atlantic DE4_SOPC_debug_uart_alt_jtag_atlantic
// (
// .clk (clk),
// .r_dat (r_dat),
// .r_ena (r_ena),
// .r_val (r_val),
// .rst_n (rst_n),
// .t_dat (t_dat),
// .t_dav (t_dav),
// .t_ena (t_ena),
// .t_pause (t_pause)
// );
//
// defparam DE4_SOPC_debug_uart_alt_jtag_atlantic.INSTANCE_ID = 0,
// DE4_SOPC_debug_uart_alt_jtag_atlantic.LOG2_RXFIFO_DEPTH = 6,
// DE4_SOPC_debug_uart_alt_jtag_atlantic.LOG2_TXFIFO_DEPTH = 6,
// DE4_SOPC_debug_uart_alt_jtag_atlantic.SLD_AUTO_INSTANCE_INDEX = "YES";
//
// always @(posedge clk or negedge rst_n)
// begin
// if (rst_n == 0)
// dataavailable <= 0;
// else
// dataavailable <= ~fifo_EF;
// end
//
//
//synthesis read_comments_as_HDL off
endmodule
|
//Legal Notice: (C)2013 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module DE4_SOPC_LEDs (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
out_port,
readdata
)
;
output [ 7: 0] out_port;
output [ 31: 0] readdata;
input [ 1: 0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input [ 31: 0] writedata;
wire clk_en;
reg [ 7: 0] data_out;
wire [ 7: 0] out_port;
wire [ 7: 0] read_mux_out;
wire [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {8 {(address == 0)}} & data_out;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
data_out <= 0;
else if (chipselect && ~write_n && (address == 0))
data_out <= writedata[7 : 0];
end
assign readdata = {32'b0 | read_mux_out};
assign out_port = data_out;
endmodule
|
//Legal Notice: (C)2013 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module DE4_SOPC_onchip_memory_MIPS (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
reset,
write,
writedata,
// outputs:
readdata
)
;
parameter INIT_FILE = "../initial.hex";
output [ 31: 0] readdata;
input [ 12: 0] address;
input [ 3: 0] byteenable;
input chipselect;
input clk;
input clken;
input reset;
input write;
input [ 31: 0] writedata;
wire [ 31: 0] readdata;
wire wren;
assign wren = chipselect & write;
//s1, which is an e_avalon_slave
//s2, which is an e_avalon_slave
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
altsyncram the_altsyncram
(
.address_a (address),
.byteena_a (byteenable),
.clock0 (clk),
.clocken0 (clken),
.data_a (writedata),
.q_a (readdata),
.wren_a (wren)
);
defparam the_altsyncram.byte_size = 8,
the_altsyncram.init_file = INIT_FILE,
the_altsyncram.lpm_type = "altsyncram",
the_altsyncram.maximum_depth = 8192,
the_altsyncram.numwords_a = 8192,
the_altsyncram.operation_mode = "SINGLE_PORT",
the_altsyncram.outdata_reg_a = "UNREGISTERED",
the_altsyncram.ram_block_type = "AUTO",
the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE",
the_altsyncram.width_a = 32,
the_altsyncram.width_byteena_a = 4,
the_altsyncram.widthad_a = 13;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// altsyncram the_altsyncram
// (
// .address_a (address),
// .byteena_a (byteenable),
// .clock0 (clk),
// .clocken0 (clken),
// .data_a (writedata),
// .q_a (readdata),
// .wren_a (wren)
// );
//
// defparam the_altsyncram.byte_size = 8,
// the_altsyncram.init_file = "initial.hex",
// the_altsyncram.lpm_type = "altsyncram",
// the_altsyncram.maximum_depth = 8192,
// the_altsyncram.numwords_a = 8192,
// the_altsyncram.operation_mode = "SINGLE_PORT",
// the_altsyncram.outdata_reg_a = "UNREGISTERED",
// the_altsyncram.ram_block_type = "AUTO",
// the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE",
// the_altsyncram.width_a = 32,
// the_altsyncram.width_byteena_a = 4,
// the_altsyncram.widthad_a = 13;
//
//synthesis read_comments_as_HDL off
endmodule
|
//Legal Notice: (C)2013 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module DE4_SOPC_receive_fifo_dual_clock_fifo (
// inputs:
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
// outputs:
q,
rdempty,
rdfull,
rdusedw,
wrfull,
wrusedw
)
;
output [ 31: 0] q;
output rdempty;
output rdfull;
output [ 3: 0] rdusedw;
output wrfull;
output [ 3: 0] wrusedw;
input aclr;
input [ 31: 0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
wire int_rdfull;
wire int_wrfull;
wire [ 31: 0] q;
wire rdempty;
wire rdfull;
wire [ 3: 0] rdusedw;
wire wrfull;
wire [ 3: 0] wrusedw;
assign wrfull = (wrusedw >= 16-3) | int_wrfull;
assign rdfull = (rdusedw >= 16-3) | int_rdfull;
dcfifo dual_clock_fifo
(
.aclr (aclr),
.data (data),
.q (q),
.rdclk (rdclk),
.rdempty (rdempty),
.rdfull (int_rdfull),
.rdreq (rdreq),
.rdusedw (rdusedw),
.wrclk (wrclk),
.wrfull (int_wrfull),
.wrreq (wrreq),
.wrusedw (wrusedw)
);
defparam dual_clock_fifo.add_ram_output_register = "OFF",
dual_clock_fifo.clocks_are_synchronized = "FALSE",
dual_clock_fifo.intended_device_family = "STRATIXIV",
dual_clock_fifo.lpm_numwords = 16,
dual_clock_fifo.lpm_showahead = "OFF",
dual_clock_fifo.lpm_type = "dcfifo",
dual_clock_fifo.lpm_width = 32,
dual_clock_fifo.lpm_widthu = 4,
dual_clock_fifo.overflow_checking = "ON",
dual_clock_fifo.underflow_checking = "ON",
dual_clock_fifo.use_eab = "ON";
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module DE4_SOPC_receive_fifo_dcfifo_with_controls (
// inputs:
data,
rdclk,
rdclk_control_slave_address,
rdclk_control_slave_read,
rdclk_control_slave_write,
rdclk_control_slave_writedata,
rdreq,
rdreset_n,
wrclk,
wrreq,
wrreset_n,
// outputs:
q,
rdclk_control_slave_irq,
rdclk_control_slave_readdata,
rdempty,
wrfull,
wrlevel
)
;
output [ 31: 0] q;
output rdclk_control_slave_irq;
output [ 31: 0] rdclk_control_slave_readdata;
output rdempty;
output wrfull;
output [ 4: 0] wrlevel;
input [ 31: 0] data;
input rdclk;
input [ 2: 0] rdclk_control_slave_address;
input rdclk_control_slave_read;
input rdclk_control_slave_write;
input [ 31: 0] rdclk_control_slave_writedata;
input rdreq;
input rdreset_n;
input wrclk;
input wrreq;
input wrreset_n;
wire [ 31: 0] q;
reg rdclk_control_slave_almostempty_n_reg;
wire rdclk_control_slave_almostempty_pulse;
wire rdclk_control_slave_almostempty_signal;
reg [ 4: 0] rdclk_control_slave_almostempty_threshold_register;
reg rdclk_control_slave_almostfull_n_reg;
wire rdclk_control_slave_almostfull_pulse;
wire rdclk_control_slave_almostfull_signal;
reg [ 4: 0] rdclk_control_slave_almostfull_threshold_register;
reg rdclk_control_slave_empty_n_reg;
wire rdclk_control_slave_empty_pulse;
wire rdclk_control_slave_empty_signal;
reg rdclk_control_slave_event_almostempty_q;
wire rdclk_control_slave_event_almostempty_signal;
reg rdclk_control_slave_event_almostfull_q;
wire rdclk_control_slave_event_almostfull_signal;
reg rdclk_control_slave_event_empty_q;
wire rdclk_control_slave_event_empty_signal;
reg rdclk_control_slave_event_full_q;
wire rdclk_control_slave_event_full_signal;
reg rdclk_control_slave_event_overflow_q;
wire rdclk_control_slave_event_overflow_signal;
wire [ 5: 0] rdclk_control_slave_event_register;
reg rdclk_control_slave_event_underflow_q;
wire rdclk_control_slave_event_underflow_signal;
reg rdclk_control_slave_full_n_reg;
wire rdclk_control_slave_full_pulse;
wire rdclk_control_slave_full_signal;
reg [ 5: 0] rdclk_control_slave_ienable_register;
wire rdclk_control_slave_irq;
wire [ 4: 0] rdclk_control_slave_level_register;
wire [ 31: 0] rdclk_control_slave_read_mux;
reg [ 31: 0] rdclk_control_slave_readdata;
reg rdclk_control_slave_status_almostempty_q;
wire rdclk_control_slave_status_almostempty_signal;
reg rdclk_control_slave_status_almostfull_q;
wire rdclk_control_slave_status_almostfull_signal;
reg rdclk_control_slave_status_empty_q;
wire rdclk_control_slave_status_empty_signal;
reg rdclk_control_slave_status_full_q;
wire rdclk_control_slave_status_full_signal;
reg rdclk_control_slave_status_overflow_q;
wire rdclk_control_slave_status_overflow_signal;
wire [ 5: 0] rdclk_control_slave_status_register;
reg rdclk_control_slave_status_underflow_q;
wire rdclk_control_slave_status_underflow_signal;
wire [ 4: 0] rdclk_control_slave_threshold_writedata;
wire rdempty;
wire rdfull;
wire [ 4: 0] rdlevel;
wire rdoverflow;
wire rdunderflow;
wire [ 3: 0] rdusedw;
wire wrfull;
wire [ 4: 0] wrlevel;
wire wrreq_valid;
wire [ 3: 0] wrusedw;
//the_dcfifo, which is an e_instance
DE4_SOPC_receive_fifo_dual_clock_fifo the_dcfifo
(
.aclr (~wrreset_n),
.data (data),
.q (q),
.rdclk (rdclk),
.rdempty (rdempty),
.rdfull (rdfull),
.rdreq (rdreq),
.rdusedw (rdusedw),
.wrclk (wrclk),
.wrfull (wrfull),
.wrreq (wrreq_valid),
.wrusedw (wrusedw)
);
assign wrlevel = {1'b0,
wrusedw};
assign wrreq_valid = wrreq & ~wrfull;
assign rdlevel = {1'b0,
rdusedw};
assign rdoverflow = wrreq & rdfull;
assign rdunderflow = rdreq & rdempty;
assign rdclk_control_slave_threshold_writedata = (rdclk_control_slave_writedata < 1) ? 1 :
(rdclk_control_slave_writedata > 12) ? 12 :
rdclk_control_slave_writedata[4 : 0];
assign rdclk_control_slave_event_almostfull_signal = rdclk_control_slave_almostfull_pulse;
assign rdclk_control_slave_event_almostempty_signal = rdclk_control_slave_almostempty_pulse;
assign rdclk_control_slave_status_almostfull_signal = rdclk_control_slave_almostfull_signal;
assign rdclk_control_slave_status_almostempty_signal = rdclk_control_slave_almostempty_signal;
assign rdclk_control_slave_event_full_signal = rdclk_control_slave_full_pulse;
assign rdclk_control_slave_event_empty_signal = rdclk_control_slave_empty_pulse;
assign rdclk_control_slave_status_full_signal = rdclk_control_slave_full_signal;
assign rdclk_control_slave_status_empty_signal = rdclk_control_slave_empty_signal;
assign rdclk_control_slave_event_overflow_signal = rdoverflow;
assign rdclk_control_slave_event_underflow_signal = rdunderflow;
assign rdclk_control_slave_status_overflow_signal = rdoverflow;
assign rdclk_control_slave_status_underflow_signal = rdunderflow;
assign rdclk_control_slave_empty_signal = rdempty;
assign rdclk_control_slave_empty_pulse = rdclk_control_slave_empty_signal & rdclk_control_slave_empty_n_reg;
always @(posedge rdclk or negedge rdreset_n)
begin
if (rdreset_n == 0)
rdclk_control_slave_empty_n_reg <= 0;
else
rdclk_control_slave_empty_n_reg <= !rdclk_control_slave_empty_signal;
end
assign rdclk_control_slave_full_signal = rdfull;
assign rdclk_control_slave_full_pulse = rdclk_control_slave_full_signal & rdclk_control_slave_full_n_reg;
always @(posedge rdclk or negedge rdreset_n)
begin
if (rdreset_n == 0)
rdclk_control_slave_full_n_reg <= 0;
else
rdclk_control_slave_full_n_reg <= !rdclk_control_slave_full_signal;
end
assign rdclk_control_slave_almostempty_signal = rdlevel <= rdclk_control_slave_almostempty_threshold_register;
assign rdclk_control_slave_almostempty_pulse = rdclk_control_slave_almostempty_signal & rdclk_control_slave_almostempty_n_reg;
always @(posedge rdclk or negedge rdreset_n)
begin
if (rdreset_n == 0)
rdclk_control_slave_almostempty_n_reg <= 0;
else
rdclk_control_slave_almostempty_n_reg <= !rdclk_control_slave_almostempty_signal;
end
assign rdclk_control_slave_almostfull_signal = rdlevel >= rdclk_control_slave_almostfull_threshold_register;
assign rdclk_control_slave_almostfull_pulse = rdclk_control_slave_almostfull_signal & rdclk_control_slave_almostfull_n_reg;
always @(posedge rdclk or negedge rdreset_n)
begin
if (rdreset_n == 0)
rdclk_control_slave_almostfull_n_reg <= 0;
else
rdclk_control_slave_almostfull_n_reg <= !rdclk_control_slave_almostfull_signal;
end
always @(posedge rdclk or negedge rdreset_n)
begin
if (rdreset_n == 0)
rdclk_control_slave_almostempty_threshold_register <= 1;
else if ((rdclk_control_slave_address == 5) & rdclk_control_slave_write)
rdclk_control_slave_almostempty_threshold_register <= rdclk_control_slave_threshold_writedata;
end
always @(posedge rdclk or negedge rdreset_n)
begin
if (rdreset_n == 0)
rdclk_control_slave_almostfull_threshold_register <= 12;
else if ((rdclk_control_slave_address == 4) & rdclk_control_slave_write)
rdclk_control_slave_almostfull_threshold_register <= rdclk_control_slave_threshold_writedata;
end
always @(posedge rdclk or negedge rdreset_n)
begin
if (rdreset_n == 0)
rdclk_control_slave_ienable_register <= 0;
else if ((rdclk_control_slave_address == 3) & rdclk_control_slave_write)
rdclk_control_slave_ienable_register <= rdclk_control_slave_writedata[5 : 0];
end
assign rdclk_control_slave_level_register = rdlevel;
always @(posedge rdclk or negedge rdreset_n)
begin
if (rdreset_n == 0)
rdclk_control_slave_event_underflow_q <= 0;
else if (rdclk_control_slave_write &
(rdclk_control_slave_address == 2) &
rdclk_control_slave_writedata[5])
rdclk_control_slave_event_underflow_q <= 0;
else if (rdclk_control_slave_event_underflow_signal)
rdclk_control_slave_event_underflow_q <= -1;
end
always @(posedge rdclk or negedge rdreset_n)
begin
if (rdreset_n == 0)
rdclk_control_slave_event_overflow_q <= 0;
else if (rdclk_control_slave_write &
(rdclk_control_slave_address == 2) &
rdclk_control_slave_writedata[4])
rdclk_control_slave_event_overflow_q <= 0;
else if (rdclk_control_slave_event_overflow_signal)
rdclk_control_slave_event_overflow_q <= -1;
end
always @(posedge rdclk or negedge rdreset_n)
begin
if (rdreset_n == 0)
rdclk_control_slave_event_almostempty_q <= 0;
else if (rdclk_control_slave_write &
(rdclk_control_slave_address == 2) &
rdclk_control_slave_writedata[3])
rdclk_control_slave_event_almostempty_q <= 0;
else if (rdclk_control_slave_event_almostempty_signal)
rdclk_control_slave_event_almostempty_q <= -1;
end
always @(posedge rdclk or negedge rdreset_n)
begin
if (rdreset_n == 0)
rdclk_control_slave_event_almostfull_q <= 0;
else if (rdclk_control_slave_write &
(rdclk_control_slave_address == 2) &
rdclk_control_slave_writedata[2])
rdclk_control_slave_event_almostfull_q <= 0;
else if (rdclk_control_slave_event_almostfull_signal)
rdclk_control_slave_event_almostfull_q <= -1;
end
always @(posedge rdclk or negedge rdreset_n)
begin
if (rdreset_n == 0)
rdclk_control_slave_event_empty_q <= 0;
else if (rdclk_control_slave_write &
(rdclk_control_slave_address == 2) &
rdclk_control_slave_writedata[1])
rdclk_control_slave_event_empty_q <= 0;
else if (rdclk_control_slave_event_empty_signal)
rdclk_control_slave_event_empty_q <= -1;
end
always @(posedge rdclk or negedge rdreset_n)
begin
if (rdreset_n == 0)
rdclk_control_slave_event_full_q <= 0;
else if (rdclk_control_slave_write &
(rdclk_control_slave_address == 2) &
rdclk_control_slave_writedata[0])
rdclk_control_slave_event_full_q <= 0;
else if (rdclk_control_slave_event_full_signal)
rdclk_control_slave_event_full_q <= -1;
end
assign rdclk_control_slave_event_register = {rdclk_control_slave_event_underflow_q,
rdclk_control_slave_event_overflow_q,
rdclk_control_slave_event_almostempty_q,
rdclk_control_slave_event_almostfull_q,
rdclk_control_slave_event_empty_q,
rdclk_control_slave_event_full_q};
assign rdclk_control_slave_irq = | (rdclk_control_slave_event_register & rdclk_control_slave_ienable_register);
always @(posedge rdclk or negedge rdreset_n)
begin
if (rdreset_n == 0)
rdclk_control_slave_status_underflow_q <= 0;
else
rdclk_control_slave_status_underflow_q <= rdclk_control_slave_status_underflow_signal;
end
always @(posedge rdclk or negedge rdreset_n)
begin
if (rdreset_n == 0)
rdclk_control_slave_status_overflow_q <= 0;
else
rdclk_control_slave_status_overflow_q <= rdclk_control_slave_status_overflow_signal;
end
always @(posedge rdclk or negedge rdreset_n)
begin
if (rdreset_n == 0)
rdclk_control_slave_status_almostempty_q <= 0;
else
rdclk_control_slave_status_almostempty_q <= rdclk_control_slave_status_almostempty_signal;
end
always @(posedge rdclk or negedge rdreset_n)
begin
if (rdreset_n == 0)
rdclk_control_slave_status_almostfull_q <= 0;
else
rdclk_control_slave_status_almostfull_q <= rdclk_control_slave_status_almostfull_signal;
end
always @(posedge rdclk or negedge rdreset_n)
begin
if (rdreset_n == 0)
rdclk_control_slave_status_empty_q <= 0;
else
rdclk_control_slave_status_empty_q <= rdclk_control_slave_status_empty_signal;
end
always @(posedge rdclk or negedge rdreset_n)
begin
if (rdreset_n == 0)
rdclk_control_slave_status_full_q <= 0;
else
rdclk_control_slave_status_full_q <= rdclk_control_slave_status_full_signal;
end
assign rdclk_control_slave_status_register = {rdclk_control_slave_status_underflow_q,
rdclk_control_slave_status_overflow_q,
rdclk_control_slave_status_almostempty_q,
rdclk_control_slave_status_almostfull_q,
rdclk_control_slave_status_empty_q,
rdclk_control_slave_status_full_q};
assign rdclk_control_slave_read_mux = ({32 {(rdclk_control_slave_address == 0)}} & rdclk_control_slave_level_register) |
({32 {(rdclk_control_slave_address == 1)}} & rdclk_control_slave_status_register) |
({32 {(rdclk_control_slave_address == 2)}} & rdclk_control_slave_event_register) |
({32 {(rdclk_control_slave_address == 3)}} & rdclk_control_slave_ienable_register) |
({32 {(rdclk_control_slave_address == 4)}} & rdclk_control_slave_almostfull_threshold_register) |
({32 {(rdclk_control_slave_address == 5)}} & rdclk_control_slave_almostempty_threshold_register) |
({32 {(~((rdclk_control_slave_address == 0))) && (~((rdclk_control_slave_address == 1))) && (~((rdclk_control_slave_address == 2))) && (~((rdclk_control_slave_address == 3))) && (~((rdclk_control_slave_address == 4))) && (~((rdclk_control_slave_address == 5)))}} & rdclk_control_slave_level_register);
always @(posedge rdclk or negedge rdreset_n)
begin
if (rdreset_n == 0)
rdclk_control_slave_readdata <= 0;
else if (rdclk_control_slave_read)
rdclk_control_slave_readdata <= rdclk_control_slave_read_mux;
end
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module DE4_SOPC_receive_fifo_map_avalonst_to_avalonmm (
// inputs:
avalonst_data,
// outputs:
avalonmm_data
)
;
output [ 31: 0] avalonmm_data;
input [ 31: 0] avalonst_data;
wire [ 31: 0] avalonmm_data;
assign avalonmm_data[7 : 0] = avalonst_data[31 : 24];
assign avalonmm_data[15 : 8] = avalonst_data[23 : 16];
assign avalonmm_data[23 : 16] = avalonst_data[15 : 8];
assign avalonmm_data[31 : 24] = avalonst_data[7 : 0];
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module DE4_SOPC_receive_fifo_dual_clock_fifo_for_other_info (
// inputs:
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
// outputs:
q
)
;
output [ 9: 0] q;
input aclr;
input [ 9: 0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
wire [ 9: 0] q;
dcfifo dual_clock_fifo
(
.aclr (aclr),
.data (data),
.q (q),
.rdclk (rdclk),
.rdreq (rdreq),
.wrclk (wrclk),
.wrreq (wrreq)
);
defparam dual_clock_fifo.add_ram_output_register = "OFF",
dual_clock_fifo.clocks_are_synchronized = "FALSE",
dual_clock_fifo.intended_device_family = "STRATIXIV",
dual_clock_fifo.lpm_numwords = 16,
dual_clock_fifo.lpm_showahead = "OFF",
dual_clock_fifo.lpm_type = "dcfifo",
dual_clock_fifo.lpm_width = 10,
dual_clock_fifo.lpm_widthu = 4,
dual_clock_fifo.overflow_checking = "ON",
dual_clock_fifo.underflow_checking = "ON",
dual_clock_fifo.use_eab = "ON";
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module DE4_SOPC_receive_fifo_map_avalonst_to_avalonmm_other_info (
// inputs:
avalonst_other_info,
// outputs:
avalonmm_other_info
)
;
output [ 31: 0] avalonmm_other_info;
input [ 9: 0] avalonst_other_info;
wire [ 7: 0] avalonmm_channel;
wire [ 5: 0] avalonmm_empty;
wire avalonmm_eop;
wire [ 7: 0] avalonmm_error;
wire [ 31: 0] avalonmm_other_info;
wire avalonmm_sop;
assign avalonmm_sop = avalonst_other_info[0];
assign avalonmm_eop = avalonst_other_info[1];
assign avalonmm_empty = {4'b0,
avalonst_other_info[3 : 2]};
assign avalonmm_channel = 8'b0;
assign avalonmm_error = {2'b0,
avalonst_other_info[9 : 4]};
assign avalonmm_other_info = {8'b0,
avalonmm_error,
avalonmm_channel,
avalonmm_empty,
avalonmm_eop,
avalonmm_sop};
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module DE4_SOPC_receive_fifo (
// inputs:
avalonmm_read_slave_address,
avalonmm_read_slave_read,
avalonst_sink_data,
avalonst_sink_empty,
avalonst_sink_endofpacket,
avalonst_sink_error,
avalonst_sink_startofpacket,
avalonst_sink_valid,
rdclk_control_slave_address,
rdclk_control_slave_read,
rdclk_control_slave_write,
rdclk_control_slave_writedata,
rdclock,
rdreset_n,
wrclock,
wrreset_n,
// outputs:
avalonmm_read_slave_readdata,
avalonmm_read_slave_waitrequest,
avalonst_sink_ready,
rdclk_control_slave_irq,
rdclk_control_slave_readdata
)
;
output [ 31: 0] avalonmm_read_slave_readdata;
output avalonmm_read_slave_waitrequest;
output avalonst_sink_ready;
output rdclk_control_slave_irq;
output [ 31: 0] rdclk_control_slave_readdata;
input avalonmm_read_slave_address;
input avalonmm_read_slave_read;
input [ 31: 0] avalonst_sink_data;
input [ 1: 0] avalonst_sink_empty;
input avalonst_sink_endofpacket;
input [ 5: 0] avalonst_sink_error;
input avalonst_sink_startofpacket;
input avalonst_sink_valid;
input [ 2: 0] rdclk_control_slave_address;
input rdclk_control_slave_read;
input rdclk_control_slave_write;
input [ 31: 0] rdclk_control_slave_writedata;
input rdclock;
input rdreset_n;
input wrclock;
input wrreset_n;
wire [ 31: 0] avalonmm_map_data_out;
wire [ 31: 0] avalonmm_other_info_map_out;
reg avalonmm_read_slave_address_delayed;
reg avalonmm_read_slave_read_delayed;
wire [ 31: 0] avalonmm_read_slave_readdata;
wire avalonmm_read_slave_waitrequest;
wire [ 31: 0] avalonst_map_data_in;
wire [ 9: 0] avalonst_other_info_map_in;
wire avalonst_sink_ready;
wire [ 31: 0] data;
wire deassert_waitrequest;
wire no_stop_write;
reg no_stop_write_d1;
wire [ 31: 0] q;
wire rdclk;
wire rdclk_control_slave_irq;
wire [ 31: 0] rdclk_control_slave_readdata;
wire rdempty;
wire rdreq;
wire rdreq_driver;
wire rdreset_to_be_optimized;
wire ready_0;
wire ready_1;
wire ready_selector;
wire wrclk;
wire wrfull;
wire [ 4: 0] wrlevel;
wire wrreq;
assign rdreset_to_be_optimized = rdreset_n;
//the_dcfifo_with_controls, which is an e_instance
DE4_SOPC_receive_fifo_dcfifo_with_controls the_dcfifo_with_controls
(
.data (data),
.q (q),
.rdclk (rdclk),
.rdclk_control_slave_address (rdclk_control_slave_address),
.rdclk_control_slave_irq (rdclk_control_slave_irq),
.rdclk_control_slave_read (rdclk_control_slave_read),
.rdclk_control_slave_readdata (rdclk_control_slave_readdata),
.rdclk_control_slave_write (rdclk_control_slave_write),
.rdclk_control_slave_writedata (rdclk_control_slave_writedata),
.rdempty (rdempty),
.rdreq (rdreq),
.rdreset_n (rdreset_n),
.wrclk (wrclk),
.wrfull (wrfull),
.wrlevel (wrlevel),
.wrreq (wrreq),
.wrreset_n (wrreset_n)
);
//out, which is an e_avalon_slave
assign deassert_waitrequest = avalonmm_read_slave_address & avalonmm_read_slave_read;
assign avalonmm_read_slave_waitrequest = !deassert_waitrequest & rdempty;
//the_map_avalonst_to_avalonmm, which is an e_instance
DE4_SOPC_receive_fifo_map_avalonst_to_avalonmm the_map_avalonst_to_avalonmm
(
.avalonmm_data (avalonmm_map_data_out),
.avalonst_data (avalonst_map_data_in)
);
assign wrclk = wrclock;
assign rdclk = rdclock;
assign rdreq_driver = (avalonmm_read_slave_address == 0) & avalonmm_read_slave_read;
assign avalonst_map_data_in = q;
assign rdreq = rdreq_driver;
assign data = avalonst_sink_data;
assign wrreq = avalonst_sink_valid & no_stop_write_d1;
assign no_stop_write = (ready_selector & ready_1) | (!ready_selector & ready_0);
assign ready_1 = !wrfull;
assign ready_0 = !wrfull & !avalonst_sink_valid;
assign ready_selector = wrlevel < 12;
always @(posedge wrclk or negedge wrreset_n)
begin
if (wrreset_n == 0)
no_stop_write_d1 <= 0;
else
no_stop_write_d1 <= no_stop_write;
end
assign avalonst_sink_ready = no_stop_write & no_stop_write_d1;
//the_dcfifo_other_info, which is an e_instance
DE4_SOPC_receive_fifo_dual_clock_fifo_for_other_info the_dcfifo_other_info
(
.aclr (~wrreset_n),
.data ({avalonst_sink_error,
avalonst_sink_empty,
avalonst_sink_endofpacket,
avalonst_sink_startofpacket}),
.q (avalonst_other_info_map_in),
.rdclk (rdclk),
.rdreq ((avalonmm_read_slave_address == 0) & avalonmm_read_slave_read),
.wrclk (wrclk),
.wrreq (avalonst_sink_valid & no_stop_write_d1)
);
//the_map_avalonst_to_avalonmm_other_info, which is an e_instance
DE4_SOPC_receive_fifo_map_avalonst_to_avalonmm_other_info the_map_avalonst_to_avalonmm_other_info
(
.avalonmm_other_info (avalonmm_other_info_map_out),
.avalonst_other_info (avalonst_other_info_map_in)
);
always @(posedge rdclk or negedge rdreset_n)
begin
if (rdreset_n == 0)
avalonmm_read_slave_address_delayed <= 0;
else
avalonmm_read_slave_address_delayed <= avalonmm_read_slave_address;
end
always @(posedge rdclk or negedge rdreset_n)
begin
if (rdreset_n == 0)
avalonmm_read_slave_read_delayed <= 0;
else
avalonmm_read_slave_read_delayed <= avalonmm_read_slave_read;
end
assign avalonmm_read_slave_readdata = ({32 {((avalonmm_read_slave_address_delayed == 1) & avalonmm_read_slave_read_delayed)}} & avalonmm_other_info_map_out) |
({32 {((avalonmm_read_slave_address_delayed == 0) & avalonmm_read_slave_read_delayed)}} & avalonmm_map_data_out);
//in, which is an e_atlantic_slave
//out_csr, which is an e_avalon_slave
endmodule
|
//Legal Notice: (C)2013 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module DE4_SOPC_Switches (
// inputs:
address,
clk,
in_port,
reset_n,
// outputs:
readdata
)
;
output [ 31: 0] readdata;
input [ 1: 0] address;
input clk;
input [ 15: 0] in_port;
input reset_n;
wire clk_en;
wire [ 15: 0] data_in;
wire [ 15: 0] read_mux_out;
reg [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {16 {(address == 0)}} & data_in;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
readdata <= 0;
else if (clk_en)
readdata <= {32'b0 | read_mux_out};
end
assign data_in = in_port;
endmodule
|
//Legal Notice: (C)2013 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module DE4_SOPC_terminal_uart_log_module (
// inputs:
clk,
data,
strobe,
valid
)
;
input clk;
input [ 7: 0] data;
input strobe;
input valid;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
reg [31:0] text_handle; // for $fopen
initial text_handle = $fopen ("DE4_SOPC_terminal_uart_output_stream.dat");
always @(posedge clk) begin
if (valid && strobe) begin
$fwrite (text_handle, "%b\n", data);
// echo raw binary strings to file as ascii to screen
$write("%s", ((data == 8'hd) ? 8'ha : data));
// non-standard; poorly documented; required to get real data stream.
$fflush (text_handle);
end
end // clk
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module DE4_SOPC_terminal_uart_sim_scfifo_w (
// inputs:
clk,
fifo_wdata,
fifo_wr,
// outputs:
fifo_FF,
r_dat,
wfifo_empty,
wfifo_used
)
;
output fifo_FF;
output [ 7: 0] r_dat;
output wfifo_empty;
output [ 8: 0] wfifo_used;
input clk;
input [ 7: 0] fifo_wdata;
input fifo_wr;
wire fifo_FF;
wire [ 7: 0] r_dat;
wire wfifo_empty;
wire [ 8: 0] wfifo_used;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
//DE4_SOPC_terminal_uart_log, which is an e_log
DE4_SOPC_terminal_uart_log_module DE4_SOPC_terminal_uart_log
(
.clk (clk),
.data (fifo_wdata),
.strobe (fifo_wr),
.valid (fifo_wr)
);
assign wfifo_used = {9{1'b0}};
assign r_dat = {8{1'b0}};
assign fifo_FF = 1'b0;
assign wfifo_empty = 1'b1;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module DE4_SOPC_terminal_uart_scfifo_w (
// inputs:
clk,
fifo_clear,
fifo_wdata,
fifo_wr,
rd_wfifo,
// outputs:
fifo_FF,
r_dat,
wfifo_empty,
wfifo_used
)
;
output fifo_FF;
output [ 7: 0] r_dat;
output wfifo_empty;
output [ 8: 0] wfifo_used;
input clk;
input fifo_clear;
input [ 7: 0] fifo_wdata;
input fifo_wr;
input rd_wfifo;
wire fifo_FF;
wire [ 7: 0] r_dat;
wire wfifo_empty;
wire [ 8: 0] wfifo_used;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
DE4_SOPC_terminal_uart_sim_scfifo_w the_DE4_SOPC_terminal_uart_sim_scfifo_w
(
.clk (clk),
.fifo_FF (fifo_FF),
.fifo_wdata (fifo_wdata),
.fifo_wr (fifo_wr),
.r_dat (r_dat),
.wfifo_empty (wfifo_empty),
.wfifo_used (wfifo_used)
);
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// scfifo wfifo
// (
// .aclr (fifo_clear),
// .clock (clk),
// .data (fifo_wdata),
// .empty (wfifo_empty),
// .full (fifo_FF),
// .q (r_dat),
// .rdreq (rd_wfifo),
// .usedw (wfifo_used),
// .wrreq (fifo_wr)
// );
//
// defparam wfifo.lpm_hint = "RAM_BLOCK_TYPE=AUTO",
// wfifo.lpm_numwords = 512,
// wfifo.lpm_showahead = "OFF",
// wfifo.lpm_type = "scfifo",
// wfifo.lpm_width = 8,
// wfifo.lpm_widthu = 9,
// wfifo.overflow_checking = "OFF",
// wfifo.underflow_checking = "OFF",
// wfifo.use_eab = "ON";
//
//synthesis read_comments_as_HDL off
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module DE4_SOPC_terminal_uart_drom_module (
// inputs:
clk,
incr_addr,
reset_n,
// outputs:
new_rom,
num_bytes,
q,
safe
)
;
parameter POLL_RATE = 100;
output new_rom;
output [ 31: 0] num_bytes;
output [ 7: 0] q;
output safe;
input clk;
input incr_addr;
input reset_n;
reg [ 11: 0] address;
reg d1_pre;
reg d2_pre;
reg d3_pre;
reg d4_pre;
reg d5_pre;
reg d6_pre;
reg d7_pre;
reg d8_pre;
reg d9_pre;
reg [ 7: 0] mem_array [2047: 0];
reg [ 31: 0] mutex [ 1: 0];
reg new_rom;
wire [ 31: 0] num_bytes;
reg pre;
wire [ 7: 0] q;
wire safe;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
assign q = mem_array[address];
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
d1_pre <= 0;
d2_pre <= 0;
d3_pre <= 0;
d4_pre <= 0;
d5_pre <= 0;
d6_pre <= 0;
d7_pre <= 0;
d8_pre <= 0;
d9_pre <= 0;
new_rom <= 0;
end
else
begin
d1_pre <= pre;
d2_pre <= d1_pre;
d3_pre <= d2_pre;
d4_pre <= d3_pre;
d5_pre <= d4_pre;
d6_pre <= d5_pre;
d7_pre <= d6_pre;
d8_pre <= d7_pre;
d9_pre <= d8_pre;
new_rom <= d9_pre;
end
end
assign num_bytes = mutex[1];
reg safe_delay;
reg [31:0] poll_count;
reg [31:0] mutex_handle;
wire interactive = 1'b0 ; // '
assign safe = (address < mutex[1]);
initial poll_count = POLL_RATE;
always @(posedge clk or negedge reset_n) begin
if (reset_n !== 1) begin
safe_delay <= 0;
end else begin
safe_delay <= safe;
end
end // safe_delay
always @(posedge clk or negedge reset_n) begin
if (reset_n !== 1) begin // dont worry about null _stream.dat file
address <= 0;
mem_array[0] <= 0;
mutex[0] <= 0;
mutex[1] <= 0;
pre <= 0;
end else begin // deal with the non-reset case
pre <= 0;
if (incr_addr && safe) address <= address + 1;
if (mutex[0] && !safe && safe_delay) begin
// and blast the mutex after falling edge of safe if interactive
if (interactive) begin
mutex_handle = $fopen ("DE4_SOPC_terminal_uart_input_mutex.dat");
$fdisplay (mutex_handle, "0");
$fclose (mutex_handle);
// $display ($stime, "\t%m:\n\t\tMutex cleared!");
end else begin
// sleep until next reset, do not bash mutex.
wait (!reset_n);
end
end // OK to bash mutex.
if (poll_count < POLL_RATE) begin // wait
poll_count = poll_count + 1;
end else begin // do the interesting stuff.
poll_count = 0;
if (mutex_handle) begin
$readmemh ("DE4_SOPC_terminal_uart_input_mutex.dat", mutex);
end
if (mutex[0] && !safe) begin
// read stream into mem_array after current characters are gone!
// save mutex[0] value to compare to address (generates 'safe')
mutex[1] <= mutex[0];
// $display ($stime, "\t%m:\n\t\tMutex hit: Trying to read %d bytes...", mutex[0]);
$readmemb("DE4_SOPC_terminal_uart_input_stream.dat", mem_array);
// bash address and send pulse outside to send the char:
address <= 0;
pre <= -1;
end // else mutex miss...
end // poll_count
end // reset
end // posedge clk
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module DE4_SOPC_terminal_uart_sim_scfifo_r (
// inputs:
clk,
fifo_rd,
rst_n,
// outputs:
fifo_EF,
fifo_rdata,
rfifo_full,
rfifo_used
)
;
output fifo_EF;
output [ 7: 0] fifo_rdata;
output rfifo_full;
output [ 5: 0] rfifo_used;
input clk;
input fifo_rd;
input rst_n;
reg [ 31: 0] bytes_left;
wire fifo_EF;
reg fifo_rd_d;
wire [ 7: 0] fifo_rdata;
wire new_rom;
wire [ 31: 0] num_bytes;
wire [ 6: 0] rfifo_entries;
wire rfifo_full;
wire [ 5: 0] rfifo_used;
wire safe;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
//DE4_SOPC_terminal_uart_drom, which is an e_drom
DE4_SOPC_terminal_uart_drom_module DE4_SOPC_terminal_uart_drom
(
.clk (clk),
.incr_addr (fifo_rd_d),
.new_rom (new_rom),
.num_bytes (num_bytes),
.q (fifo_rdata),
.reset_n (rst_n),
.safe (safe)
);
// Generate rfifo_entries for simulation
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 0)
begin
bytes_left <= 32'h0;
fifo_rd_d <= 1'b0;
end
else
begin
fifo_rd_d <= fifo_rd;
// decrement on read
if (fifo_rd_d)
bytes_left <= bytes_left - 1'b1;
// catch new contents
if (new_rom)
bytes_left <= num_bytes;
end
end
assign fifo_EF = bytes_left == 32'b0;
assign rfifo_full = bytes_left > 7'h40;
assign rfifo_entries = (rfifo_full) ? 7'h40 : bytes_left;
assign rfifo_used = rfifo_entries[5 : 0];
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module DE4_SOPC_terminal_uart_scfifo_r (
// inputs:
clk,
fifo_clear,
fifo_rd,
rst_n,
t_dat,
wr_rfifo,
// outputs:
fifo_EF,
fifo_rdata,
rfifo_full,
rfifo_used
)
;
output fifo_EF;
output [ 7: 0] fifo_rdata;
output rfifo_full;
output [ 5: 0] rfifo_used;
input clk;
input fifo_clear;
input fifo_rd;
input rst_n;
input [ 7: 0] t_dat;
input wr_rfifo;
wire fifo_EF;
wire [ 7: 0] fifo_rdata;
wire rfifo_full;
wire [ 5: 0] rfifo_used;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
DE4_SOPC_terminal_uart_sim_scfifo_r the_DE4_SOPC_terminal_uart_sim_scfifo_r
(
.clk (clk),
.fifo_EF (fifo_EF),
.fifo_rd (fifo_rd),
.fifo_rdata (fifo_rdata),
.rfifo_full (rfifo_full),
.rfifo_used (rfifo_used),
.rst_n (rst_n)
);
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// scfifo rfifo
// (
// .aclr (fifo_clear),
// .clock (clk),
// .data (t_dat),
// .empty (fifo_EF),
// .full (rfifo_full),
// .q (fifo_rdata),
// .rdreq (fifo_rd),
// .usedw (rfifo_used),
// .wrreq (wr_rfifo)
// );
//
// defparam rfifo.lpm_hint = "RAM_BLOCK_TYPE=AUTO",
// rfifo.lpm_numwords = 64,
// rfifo.lpm_showahead = "OFF",
// rfifo.lpm_type = "scfifo",
// rfifo.lpm_width = 8,
// rfifo.lpm_widthu = 6,
// rfifo.overflow_checking = "OFF",
// rfifo.underflow_checking = "OFF",
// rfifo.use_eab = "ON";
//
//synthesis read_comments_as_HDL off
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module DE4_SOPC_terminal_uart (
// inputs:
av_address,
av_chipselect,
av_read_n,
av_write_n,
av_writedata,
clk,
rst_n,
// outputs:
av_irq,
av_readdata,
av_waitrequest,
dataavailable,
readyfordata
)
/* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"R101,C106,D101,D103\"" */ ;
output av_irq;
output [ 31: 0] av_readdata;
output av_waitrequest;
output dataavailable;
output readyfordata;
input av_address;
input av_chipselect;
input av_read_n;
input av_write_n;
input [ 31: 0] av_writedata;
input clk;
input rst_n;
reg ac;
wire activity;
wire av_irq;
wire [ 31: 0] av_readdata;
reg av_waitrequest;
reg dataavailable;
reg fifo_AE;
reg fifo_AF;
wire fifo_EF;
wire fifo_FF;
wire fifo_clear;
wire fifo_rd;
wire [ 7: 0] fifo_rdata;
wire [ 7: 0] fifo_wdata;
reg fifo_wr;
reg ien_AE;
reg ien_AF;
wire ipen_AE;
wire ipen_AF;
reg pause_irq;
wire [ 7: 0] r_dat;
wire r_ena;
reg r_val;
wire rd_wfifo;
reg read_0;
reg readyfordata;
wire rfifo_full;
wire [ 5: 0] rfifo_used;
reg rvalid;
reg sim_r_ena;
reg sim_t_dat;
reg sim_t_ena;
reg sim_t_pause;
wire [ 7: 0] t_dat;
reg t_dav;
wire t_ena;
wire t_pause;
wire wfifo_empty;
wire [ 8: 0] wfifo_used;
reg woverflow;
wire wr_rfifo;
//avalon_jtag_slave, which is an e_avalon_slave
assign rd_wfifo = r_ena & ~wfifo_empty;
assign wr_rfifo = t_ena & ~rfifo_full;
assign fifo_clear = ~rst_n;
DE4_SOPC_terminal_uart_scfifo_w the_DE4_SOPC_terminal_uart_scfifo_w
(
.clk (clk),
.fifo_FF (fifo_FF),
.fifo_clear (fifo_clear),
.fifo_wdata (fifo_wdata),
.fifo_wr (fifo_wr),
.r_dat (r_dat),
.rd_wfifo (rd_wfifo),
.wfifo_empty (wfifo_empty),
.wfifo_used (wfifo_used)
);
DE4_SOPC_terminal_uart_scfifo_r the_DE4_SOPC_terminal_uart_scfifo_r
(
.clk (clk),
.fifo_EF (fifo_EF),
.fifo_clear (fifo_clear),
.fifo_rd (fifo_rd),
.fifo_rdata (fifo_rdata),
.rfifo_full (rfifo_full),
.rfifo_used (rfifo_used),
.rst_n (rst_n),
.t_dat (t_dat),
.wr_rfifo (wr_rfifo)
);
assign ipen_AE = ien_AE & fifo_AE;
assign ipen_AF = ien_AF & (pause_irq | fifo_AF);
assign av_irq = ipen_AE | ipen_AF;
assign activity = t_pause | t_ena;
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 0)
pause_irq <= 1'b0;
else // only if fifo is not empty...
if (t_pause & ~fifo_EF)
pause_irq <= 1'b1;
else if (read_0)
pause_irq <= 1'b0;
end
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 0)
begin
r_val <= 1'b0;
t_dav <= 1'b1;
end
else
begin
r_val <= r_ena & ~wfifo_empty;
t_dav <= ~rfifo_full;
end
end
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 0)
begin
fifo_AE <= 1'b0;
fifo_AF <= 1'b0;
fifo_wr <= 1'b0;
rvalid <= 1'b0;
read_0 <= 1'b0;
ien_AE <= 1'b0;
ien_AF <= 1'b0;
ac <= 1'b0;
woverflow <= 1'b0;
av_waitrequest <= 1'b1;
end
else
begin
fifo_AE <= {fifo_FF,wfifo_used} <= 8;
fifo_AF <= (7'h40 - {rfifo_full,rfifo_used}) <= 8;
fifo_wr <= 1'b0;
read_0 <= 1'b0;
av_waitrequest <= ~(av_chipselect & (~av_write_n | ~av_read_n) & av_waitrequest);
if (activity)
ac <= 1'b1;
// write
if (av_chipselect & ~av_write_n & av_waitrequest)
// addr 1 is control; addr 0 is data
if (av_address)
begin
ien_AF <= av_writedata[0];
ien_AE <= av_writedata[1];
if (av_writedata[10] & ~activity)
ac <= 1'b0;
end
else
begin
fifo_wr <= ~fifo_FF;
woverflow <= fifo_FF;
end
// read
if (av_chipselect & ~av_read_n & av_waitrequest)
begin
// addr 1 is interrupt; addr 0 is data
if (~av_address)
rvalid <= ~fifo_EF;
read_0 <= ~av_address;
end
end
end
assign fifo_wdata = av_writedata[7 : 0];
assign fifo_rd = (av_chipselect & ~av_read_n & av_waitrequest & ~av_address) ? ~fifo_EF : 1'b0;
assign av_readdata = read_0 ? { {9{1'b0}},rfifo_full,rfifo_used,rvalid,woverflow,~fifo_FF,~fifo_EF,1'b0,ac,ipen_AE,ipen_AF,fifo_rdata } : { {6{1'b0}},(10'h200 - {fifo_FF,wfifo_used}),rvalid,woverflow,~fifo_FF,~fifo_EF,1'b0,ac,ipen_AE,ipen_AF,{6{1'b0}},ien_AE,ien_AF };
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 0)
readyfordata <= 0;
else
readyfordata <= ~fifo_FF;
end
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
// Tie off Atlantic Interface signals not used for simulation
always @(posedge clk)
begin
sim_t_pause <= 1'b0;
sim_t_ena <= 1'b0;
sim_t_dat <= t_dav ? r_dat : {8{r_val}};
sim_r_ena <= 1'b0;
end
assign r_ena = sim_r_ena;
assign t_ena = sim_t_ena;
assign t_dat = sim_t_dat;
assign t_pause = sim_t_pause;
always @(fifo_EF)
begin
dataavailable = ~fifo_EF;
end
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// alt_jtag_atlantic DE4_SOPC_terminal_uart_alt_jtag_atlantic
// (
// .clk (clk),
// .r_dat (r_dat),
// .r_ena (r_ena),
// .r_val (r_val),
// .rst_n (rst_n),
// .t_dat (t_dat),
// .t_dav (t_dav),
// .t_ena (t_ena),
// .t_pause (t_pause)
// );
//
// defparam DE4_SOPC_terminal_uart_alt_jtag_atlantic.INSTANCE_ID = 0,
// DE4_SOPC_terminal_uart_alt_jtag_atlantic.LOG2_RXFIFO_DEPTH = 9,
// DE4_SOPC_terminal_uart_alt_jtag_atlantic.LOG2_TXFIFO_DEPTH = 6,
// DE4_SOPC_terminal_uart_alt_jtag_atlantic.SLD_AUTO_INSTANCE_INDEX = "YES";
//
// always @(posedge clk or negedge rst_n)
// begin
// if (rst_n == 0)
// dataavailable <= 0;
// else
// dataavailable <= ~fifo_EF;
// end
//
//
//synthesis read_comments_as_HDL off
endmodule
|
// --------------------------------------------------------------------------------
//| Avalon Streaming Timing Adapter
// --------------------------------------------------------------------------------
// altera message_level level1
`timescale 1ns / 100ps
module DE4_SOPC_timing_adapter (
// Interface: clk
input clk,
// Interface: reset
input reset_n,
// Interface: in
output reg in_ready,
input in_valid,
input [31: 0] in_data,
input in_error,
input in_startofpacket,
input in_endofpacket,
input [ 1: 0] in_empty,
// Interface: out
input out_ready,
output reg out_valid,
output reg [31: 0] out_data,
output reg out_error,
output reg out_startofpacket,
output reg out_endofpacket,
output reg [ 1: 0] out_empty
);
// ---------------------------------------------------------------------
//| Signal Declarations
// ---------------------------------------------------------------------
reg [36: 0] in_payload;
wire [36: 0] out_payload;
wire in_ready_wire;
wire out_valid_wire;
wire [ 3: 0] fifo_fill;
reg [ 0: 0] ready;
// ---------------------------------------------------------------------
//| Payload Mapping
// ---------------------------------------------------------------------
always @* begin
in_payload = {in_data,in_error,in_startofpacket,in_endofpacket,in_empty};
{out_data,out_error,out_startofpacket,out_endofpacket,out_empty} = out_payload;
end
// ---------------------------------------------------------------------
//| FIFO
// ---------------------------------------------------------------------
DE4_SOPC_timing_adapter_fifo DE4_SOPC_timing_adapter_fifo
(
.clk (clk),
.reset_n (reset_n),
.in_ready (),
.in_valid (in_valid),
.in_data (in_payload),
.out_ready (ready[0]),
.out_valid (out_valid_wire),
.out_data (out_payload),
.fill_level (fifo_fill)
);
// ---------------------------------------------------------------------
//| Ready & valid signals.
// ---------------------------------------------------------------------
always @* begin
in_ready = (fifo_fill < 4 );
out_valid = out_valid_wire;
ready[0] = out_ready;
end
endmodule
|
// --------------------------------------------------------------------------------
//| Avalon Streaming Timing Adapter
// --------------------------------------------------------------------------------
// altera message_level level1
`timescale 1ns / 100ps
module DE4_SOPC_timing_adapter_1 (
// Interface: clk
input clk,
// Interface: reset
input reset_n,
// Interface: in
output reg in_ready,
input in_valid,
input [31: 0] in_data,
input [ 5: 0] in_error,
input in_startofpacket,
input in_endofpacket,
input [ 1: 0] in_empty,
// Interface: out
input out_ready,
output reg out_valid,
output reg [31: 0] out_data,
output reg [ 5: 0] out_error,
output reg out_startofpacket,
output reg out_endofpacket,
output reg [ 1: 0] out_empty
);
// ---------------------------------------------------------------------
//| Signal Declarations
// ---------------------------------------------------------------------
reg [41: 0] in_payload;
reg [41: 0] out_payload;
reg [ 1: 0] ready;
// ---------------------------------------------------------------------
//| Payload Mapping
// ---------------------------------------------------------------------
always @* begin
in_payload = {in_data,in_error,in_startofpacket,in_endofpacket,in_empty};
{out_data,out_error,out_startofpacket,out_endofpacket,out_empty} = out_payload;
end
// ---------------------------------------------------------------------
//| Ready & valid signals.
// ---------------------------------------------------------------------
always @* begin
ready[1] = out_ready;
out_valid = in_valid && ready[0];
out_payload = in_payload;
in_ready = ready[0];
end
always @(posedge clk or negedge reset_n) begin
if (!reset_n) begin
ready[1-1:0] <= 0;
end else begin
ready[1-1:0] <= ready[1:1];
end
end
endmodule
|
// --------------------------------------------------------------------------------
// | simple_atlantic_fifo
// --------------------------------------------------------------------------------
`timescale 1ns / 100ps
module DE4_SOPC_timing_adapter_fifo (
output reg [ 3: 0] fill_level ,
// Interface: clock
input clk,
input reset_n,
// Interface: data_in
output reg in_ready,
input in_valid,
input [36: 0] in_data,
// Interface: data_out
input out_ready,
output reg out_valid,
output reg [36: 0] out_data
);
// ---------------------------------------------------------------------
//| Internal Parameters
// ---------------------------------------------------------------------
parameter DEPTH = 8;
parameter DATA_WIDTH = 37;
parameter ADDR_WIDTH = 3;
// ---------------------------------------------------------------------
//| Signals
// ---------------------------------------------------------------------
reg [ADDR_WIDTH-1:0] wr_addr;
reg [ADDR_WIDTH-1:0] rd_addr;
reg [ADDR_WIDTH-1:0] next_wr_addr;
reg [ADDR_WIDTH-1:0] next_rd_addr;
reg [ADDR_WIDTH-1:0] mem_rd_addr;
reg [DATA_WIDTH-1:0] mem[DEPTH-1:0];
reg empty;
reg full;
reg [0:0] out_ready_vector;
// ---------------------------------------------------------------------
//| FIFO Status
// ---------------------------------------------------------------------
always @* begin
// out_valid = !empty;
out_ready_vector[0] = out_ready;
in_ready = !full;
next_wr_addr = wr_addr + 1'b1;
next_rd_addr = rd_addr + 1'b1;
fill_level[ADDR_WIDTH-1:0] = wr_addr - rd_addr;
fill_level[ADDR_WIDTH] = 0;
if (full)
fill_level = DEPTH[ADDR_WIDTH:0];
end
// ---------------------------------------------------------------------
//| Manage Pointers
// ---------------------------------------------------------------------
always @ (negedge reset_n, posedge clk) begin
if (!reset_n) begin
wr_addr <= 0;
rd_addr <= 0;
empty <= 1;
rd_addr <= 0;
full <= 0;
out_valid <= 0;
end else begin
out_valid <= !empty;
if (in_ready && in_valid) begin
wr_addr <= next_wr_addr;
empty <= 0;
if (next_wr_addr == rd_addr)
full <= 1;
end
if (out_ready_vector[0] && out_valid) begin
rd_addr <= next_rd_addr;
full <= 0;
if (next_rd_addr == wr_addr) begin
empty <= 1;
out_valid <= 0;
end
end
if (out_ready_vector[0] && out_valid && in_ready && in_valid) begin
full <= full;
empty <= empty;
end
end
end // always @ (negedge reset_n, posedge clk)
always @* begin
mem_rd_addr = rd_addr;
if (out_ready && out_valid) begin
mem_rd_addr = next_rd_addr;
end
end
// ---------------------------------------------------------------------
//| Infer Memory
// ---------------------------------------------------------------------
always @ (posedge clk) begin
if (in_ready && in_valid)
mem[wr_addr] <= in_data;
out_data <= mem[mem_rd_addr];
end
endmodule // simple_atlantic_fifo
// synthesis translate_off
// --------------------------------------------------------------------------------
// | test bench
// --------------------------------------------------------------------------------
module test_DE4_SOPC_timing_adapter_fifo;
parameter DEPTH = 8;
parameter DATA_WIDTH = 37;
parameter ADDR_WIDTH = 3;
// ---------------------------------------------------------------------
//| Internal Parameters
// ---------------------------------------------------------------------
localparam CLOCK_HALF_PERIOD = 10;
localparam CLOCK_PERIOD = 2*CLOCK_HALF_PERIOD;
localparam RESET_TIME = 25;
// ---------------------------------------------------------------------
//| Signals
// ---------------------------------------------------------------------
reg clk = 0;
reg reset_n = 0;
reg test_success = 1;
reg success = 1;
wire in_ready;
reg in_valid;
reg [DATA_WIDTH-1:0] in_data;
reg out_ready;
wire out_valid;
wire [DATA_WIDTH-1:0] out_data;
reg [DATA_WIDTH-1:0] next_out_data;
// ---------------------------------------------------------------------
//| DUT
// ---------------------------------------------------------------------
DE4_SOPC_timing_adapter_fifo dut (
.clk (clk),
.reset_n (reset_n),
.in_ready (in_ready),
.in_valid (in_valid),
.in_data (in_data),
.out_ready (out_ready),
.out_valid (out_valid),
.out_data (out_data)
);
// ---------------------------------------------------------------------
//| Clock & Reset
// ---------------------------------------------------------------------
initial begin
reset_n = 0;
#RESET_TIME;
reset_n = 1;
end
always begin
#CLOCK_HALF_PERIOD;
clk <= ~clk;
end
// ---------------------------------------------------------------------
//| Data Source
// ---------------------------------------------------------------------
always @(posedge clk) begin
if (reset_n == 0)
in_data <= 0;
else
if (in_ready && in_valid)
in_data <= in_data + 1;
end
// ---------------------------------------------------------------------
//| Data Sink
// ---------------------------------------------------------------------
always @(posedge clk) begin
if (reset_n == 0)
next_out_data <= 0;
else
if (out_ready && out_valid) begin
test_assert ("Data Error",out_data == next_out_data);
next_out_data <= next_out_data + 1;
end
end
// ---------------------------------------------------------------------
//| Main Test
// ---------------------------------------------------------------------
initial begin
test_exactly_full_and_empty();
test_random();
$finish;
end
// ---------------------------------------------------------------------
//| Test exactly full and empty
// ---------------------------------------------------------------------
task test_exactly_full_and_empty;
begin
test_success = 1;
wait (reset_n == 1);
@(posedge clk);
empty_the_fifo();
test_assert ("Empty: should be ready", in_ready == 1);
test_assert ("Empty: should not be valid", out_valid == 0);
@(posedge clk);
in_valid <= 1;
out_ready <= 0;
@(posedge clk);
in_valid <= 0;
@(posedge clk);
in_valid <= 1;
#1;
test_assert ("Almost Empty: should be ready", in_ready == 1);
test_assert ("Almost Empty: should be valid", out_valid == 1);
repeat (DEPTH-2) @(posedge clk);
#1;
test_assert ("Almost Full: should be ready", in_ready == 1);
test_assert ("Almost Full: should be valid", out_valid == 1);
@(posedge clk);
#1;
test_assert ("Full: should be NOT ready", in_ready == 0);
test_assert ("Full: should be valid", out_valid == 1);
in_valid <= 0;
out_ready <= 0;
@(posedge clk);
#1;
test_assert ("Still Full: should be NOT ready", in_ready == 0);
test_assert ("Still Full: should be valid", out_valid == 1);
in_valid <= 0;
out_ready <= 1;
@(posedge clk);
#1;
test_assert ("Almost Full: should be ready", in_ready == 1);
test_assert ("Almost Full 2: should be valid", out_valid == 1);
repeat (DEPTH-2) @(posedge clk);
#1;
test_assert ("Almost Empty: should be ready", in_ready == 1);
test_assert ("Almost Empty 2: should be valid", out_valid == 1);
@(posedge clk);
#1;
test_assert ("Empty: should be ready", in_ready == 1);
test_assert ("Empty 2: should not be valid", out_valid == 0);
endtest("test_exactly_full_and_empty");
end
endtask
// ---------------------------------------------------------------------
//| Test random in & out rates
// ---------------------------------------------------------------------
task test_random;
integer seed;
begin
seed = 23;
test_success = 1;
repeat(20 * DEPTH) begin
@(posedge clk);
in_valid <= ($random(seed) & 1);
out_ready <= ($random(seed) & 1);
end
endtest("test_random");
end
endtask // test_random
// ---------------------------------------------------------------------
//| Empty the FIFO
// ---------------------------------------------------------------------
task empty_the_fifo;
begin
in_valid <= 0;
out_ready <= 1;
repeat (DEPTH) @(posedge clk);
out_ready = 0;
end
endtask
// ---------------------------------------------------------------------
//| AssertFail
// ---------------------------------------------------------------------
task test_assert;
input [256:0] message;
input condition;
begin
if (! condition) begin
$display("(sim)%t: %s",$time, message);
success = 0;
test_success = 0;
end
end
endtask
// ---------------------------------------------------------------------
//| End Test
// ---------------------------------------------------------------------
task endtest;
input [256:0] message;
begin
if (test_success) begin
$display("(sim)%t: %-40s: Pass",$time, message);
end else begin
$display("(sim)%t: %-40s: Fail",$time, message);
end
success = success & test_success;
end
endtask
endmodule
// synthesis translate_on
|
//Legal Notice: (C)2013 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module DE4_SOPC_transmit_fifo_single_clock_fifo (
// inputs:
aclr,
clock,
data,
rdreq,
wrreq,
// outputs:
empty,
full,
q,
usedw
)
;
output empty;
output full;
output [ 31: 0] q;
output [ 3: 0] usedw;
input aclr;
input clock;
input [ 31: 0] data;
input rdreq;
input wrreq;
wire empty;
wire full;
wire [ 31: 0] q;
wire [ 3: 0] usedw;
scfifo single_clock_fifo
(
.aclr (aclr),
.clock (clock),
.data (data),
.empty (empty),
.full (full),
.q (q),
.rdreq (rdreq),
.usedw (usedw),
.wrreq (wrreq)
);
defparam single_clock_fifo.add_ram_output_register = "OFF",
single_clock_fifo.intended_device_family = "STRATIXIV",
single_clock_fifo.lpm_numwords = 16,
single_clock_fifo.lpm_showahead = "OFF",
single_clock_fifo.lpm_type = "scfifo",
single_clock_fifo.lpm_width = 32,
single_clock_fifo.lpm_widthu = 4,
single_clock_fifo.overflow_checking = "ON",
single_clock_fifo.underflow_checking = "ON",
single_clock_fifo.use_eab = "ON";
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module DE4_SOPC_transmit_fifo_scfifo_with_controls (
// inputs:
clock,
data,
rdreq,
reset_n,
wrclk_control_slave_address,
wrclk_control_slave_read,
wrclk_control_slave_write,
wrclk_control_slave_writedata,
wrreq,
// outputs:
empty,
full,
q,
wrclk_control_slave_irq,
wrclk_control_slave_readdata
)
;
output empty;
output full;
output [ 31: 0] q;
output wrclk_control_slave_irq;
output [ 31: 0] wrclk_control_slave_readdata;
input clock;
input [ 31: 0] data;
input rdreq;
input reset_n;
input [ 2: 0] wrclk_control_slave_address;
input wrclk_control_slave_read;
input wrclk_control_slave_write;
input [ 31: 0] wrclk_control_slave_writedata;
input wrreq;
wire empty;
wire full;
wire [ 4: 0] level;
wire overflow;
wire [ 31: 0] q;
wire underflow;
wire [ 3: 0] usedw;
reg wrclk_control_slave_almostempty_n_reg;
wire wrclk_control_slave_almostempty_pulse;
wire wrclk_control_slave_almostempty_signal;
reg [ 4: 0] wrclk_control_slave_almostempty_threshold_register;
reg wrclk_control_slave_almostfull_n_reg;
wire wrclk_control_slave_almostfull_pulse;
wire wrclk_control_slave_almostfull_signal;
reg [ 4: 0] wrclk_control_slave_almostfull_threshold_register;
reg wrclk_control_slave_empty_n_reg;
wire wrclk_control_slave_empty_pulse;
wire wrclk_control_slave_empty_signal;
reg wrclk_control_slave_event_almostempty_q;
wire wrclk_control_slave_event_almostempty_signal;
reg wrclk_control_slave_event_almostfull_q;
wire wrclk_control_slave_event_almostfull_signal;
reg wrclk_control_slave_event_empty_q;
wire wrclk_control_slave_event_empty_signal;
reg wrclk_control_slave_event_full_q;
wire wrclk_control_slave_event_full_signal;
reg wrclk_control_slave_event_overflow_q;
wire wrclk_control_slave_event_overflow_signal;
wire [ 5: 0] wrclk_control_slave_event_register;
reg wrclk_control_slave_event_underflow_q;
wire wrclk_control_slave_event_underflow_signal;
reg wrclk_control_slave_full_n_reg;
wire wrclk_control_slave_full_pulse;
wire wrclk_control_slave_full_signal;
reg [ 5: 0] wrclk_control_slave_ienable_register;
wire wrclk_control_slave_irq;
wire [ 4: 0] wrclk_control_slave_level_register;
wire [ 31: 0] wrclk_control_slave_read_mux;
reg [ 31: 0] wrclk_control_slave_readdata;
reg wrclk_control_slave_status_almostempty_q;
wire wrclk_control_slave_status_almostempty_signal;
reg wrclk_control_slave_status_almostfull_q;
wire wrclk_control_slave_status_almostfull_signal;
reg wrclk_control_slave_status_empty_q;
wire wrclk_control_slave_status_empty_signal;
reg wrclk_control_slave_status_full_q;
wire wrclk_control_slave_status_full_signal;
reg wrclk_control_slave_status_overflow_q;
wire wrclk_control_slave_status_overflow_signal;
wire [ 5: 0] wrclk_control_slave_status_register;
reg wrclk_control_slave_status_underflow_q;
wire wrclk_control_slave_status_underflow_signal;
wire [ 4: 0] wrclk_control_slave_threshold_writedata;
wire wrreq_valid;
//the_scfifo, which is an e_instance
DE4_SOPC_transmit_fifo_single_clock_fifo the_scfifo
(
.aclr (~reset_n),
.clock (clock),
.data (data),
.empty (empty),
.full (full),
.q (q),
.rdreq (rdreq),
.usedw (usedw),
.wrreq (wrreq_valid)
);
assign level = {full,
usedw};
assign wrreq_valid = wrreq & ~full;
assign overflow = wrreq & full;
assign underflow = rdreq & empty;
assign wrclk_control_slave_threshold_writedata = (wrclk_control_slave_writedata < 1) ? 1 :
(wrclk_control_slave_writedata > 15) ? 15 :
wrclk_control_slave_writedata[4 : 0];
assign wrclk_control_slave_event_almostfull_signal = wrclk_control_slave_almostfull_pulse;
assign wrclk_control_slave_event_almostempty_signal = wrclk_control_slave_almostempty_pulse;
assign wrclk_control_slave_status_almostfull_signal = wrclk_control_slave_almostfull_signal;
assign wrclk_control_slave_status_almostempty_signal = wrclk_control_slave_almostempty_signal;
assign wrclk_control_slave_event_full_signal = wrclk_control_slave_full_pulse;
assign wrclk_control_slave_event_empty_signal = wrclk_control_slave_empty_pulse;
assign wrclk_control_slave_status_full_signal = wrclk_control_slave_full_signal;
assign wrclk_control_slave_status_empty_signal = wrclk_control_slave_empty_signal;
assign wrclk_control_slave_event_overflow_signal = overflow;
assign wrclk_control_slave_event_underflow_signal = underflow;
assign wrclk_control_slave_status_overflow_signal = overflow;
assign wrclk_control_slave_status_underflow_signal = underflow;
assign wrclk_control_slave_empty_signal = empty;
assign wrclk_control_slave_empty_pulse = wrclk_control_slave_empty_signal & wrclk_control_slave_empty_n_reg;
always @(posedge clock or negedge reset_n)
begin
if (reset_n == 0)
wrclk_control_slave_empty_n_reg <= 0;
else
wrclk_control_slave_empty_n_reg <= !wrclk_control_slave_empty_signal;
end
assign wrclk_control_slave_full_signal = full;
assign wrclk_control_slave_full_pulse = wrclk_control_slave_full_signal & wrclk_control_slave_full_n_reg;
always @(posedge clock or negedge reset_n)
begin
if (reset_n == 0)
wrclk_control_slave_full_n_reg <= 0;
else
wrclk_control_slave_full_n_reg <= !wrclk_control_slave_full_signal;
end
assign wrclk_control_slave_almostempty_signal = level <= wrclk_control_slave_almostempty_threshold_register;
assign wrclk_control_slave_almostempty_pulse = wrclk_control_slave_almostempty_signal & wrclk_control_slave_almostempty_n_reg;
always @(posedge clock or negedge reset_n)
begin
if (reset_n == 0)
wrclk_control_slave_almostempty_n_reg <= 0;
else
wrclk_control_slave_almostempty_n_reg <= !wrclk_control_slave_almostempty_signal;
end
assign wrclk_control_slave_almostfull_signal = level >= wrclk_control_slave_almostfull_threshold_register;
assign wrclk_control_slave_almostfull_pulse = wrclk_control_slave_almostfull_signal & wrclk_control_slave_almostfull_n_reg;
always @(posedge clock or negedge reset_n)
begin
if (reset_n == 0)
wrclk_control_slave_almostfull_n_reg <= 0;
else
wrclk_control_slave_almostfull_n_reg <= !wrclk_control_slave_almostfull_signal;
end
always @(posedge clock or negedge reset_n)
begin
if (reset_n == 0)
wrclk_control_slave_almostempty_threshold_register <= 1;
else if ((wrclk_control_slave_address == 5) & wrclk_control_slave_write)
wrclk_control_slave_almostempty_threshold_register <= wrclk_control_slave_threshold_writedata;
end
always @(posedge clock or negedge reset_n)
begin
if (reset_n == 0)
wrclk_control_slave_almostfull_threshold_register <= 15;
else if ((wrclk_control_slave_address == 4) & wrclk_control_slave_write)
wrclk_control_slave_almostfull_threshold_register <= wrclk_control_slave_threshold_writedata;
end
always @(posedge clock or negedge reset_n)
begin
if (reset_n == 0)
wrclk_control_slave_ienable_register <= 0;
else if ((wrclk_control_slave_address == 3) & wrclk_control_slave_write)
wrclk_control_slave_ienable_register <= wrclk_control_slave_writedata[5 : 0];
end
assign wrclk_control_slave_level_register = level;
always @(posedge clock or negedge reset_n)
begin
if (reset_n == 0)
wrclk_control_slave_event_underflow_q <= 0;
else if (wrclk_control_slave_write &
(wrclk_control_slave_address == 2) &
wrclk_control_slave_writedata[5])
wrclk_control_slave_event_underflow_q <= 0;
else if (wrclk_control_slave_event_underflow_signal)
wrclk_control_slave_event_underflow_q <= -1;
end
always @(posedge clock or negedge reset_n)
begin
if (reset_n == 0)
wrclk_control_slave_event_overflow_q <= 0;
else if (wrclk_control_slave_write &
(wrclk_control_slave_address == 2) &
wrclk_control_slave_writedata[4])
wrclk_control_slave_event_overflow_q <= 0;
else if (wrclk_control_slave_event_overflow_signal)
wrclk_control_slave_event_overflow_q <= -1;
end
always @(posedge clock or negedge reset_n)
begin
if (reset_n == 0)
wrclk_control_slave_event_almostempty_q <= 0;
else if (wrclk_control_slave_write &
(wrclk_control_slave_address == 2) &
wrclk_control_slave_writedata[3])
wrclk_control_slave_event_almostempty_q <= 0;
else if (wrclk_control_slave_event_almostempty_signal)
wrclk_control_slave_event_almostempty_q <= -1;
end
always @(posedge clock or negedge reset_n)
begin
if (reset_n == 0)
wrclk_control_slave_event_almostfull_q <= 0;
else if (wrclk_control_slave_write &
(wrclk_control_slave_address == 2) &
wrclk_control_slave_writedata[2])
wrclk_control_slave_event_almostfull_q <= 0;
else if (wrclk_control_slave_event_almostfull_signal)
wrclk_control_slave_event_almostfull_q <= -1;
end
always @(posedge clock or negedge reset_n)
begin
if (reset_n == 0)
wrclk_control_slave_event_empty_q <= 0;
else if (wrclk_control_slave_write &
(wrclk_control_slave_address == 2) &
wrclk_control_slave_writedata[1])
wrclk_control_slave_event_empty_q <= 0;
else if (wrclk_control_slave_event_empty_signal)
wrclk_control_slave_event_empty_q <= -1;
end
always @(posedge clock or negedge reset_n)
begin
if (reset_n == 0)
wrclk_control_slave_event_full_q <= 0;
else if (wrclk_control_slave_write &
(wrclk_control_slave_address == 2) &
wrclk_control_slave_writedata[0])
wrclk_control_slave_event_full_q <= 0;
else if (wrclk_control_slave_event_full_signal)
wrclk_control_slave_event_full_q <= -1;
end
assign wrclk_control_slave_event_register = {wrclk_control_slave_event_underflow_q,
wrclk_control_slave_event_overflow_q,
wrclk_control_slave_event_almostempty_q,
wrclk_control_slave_event_almostfull_q,
wrclk_control_slave_event_empty_q,
wrclk_control_slave_event_full_q};
assign wrclk_control_slave_irq = | (wrclk_control_slave_event_register & wrclk_control_slave_ienable_register);
always @(posedge clock or negedge reset_n)
begin
if (reset_n == 0)
wrclk_control_slave_status_underflow_q <= 0;
else
wrclk_control_slave_status_underflow_q <= wrclk_control_slave_status_underflow_signal;
end
always @(posedge clock or negedge reset_n)
begin
if (reset_n == 0)
wrclk_control_slave_status_overflow_q <= 0;
else
wrclk_control_slave_status_overflow_q <= wrclk_control_slave_status_overflow_signal;
end
always @(posedge clock or negedge reset_n)
begin
if (reset_n == 0)
wrclk_control_slave_status_almostempty_q <= 0;
else
wrclk_control_slave_status_almostempty_q <= wrclk_control_slave_status_almostempty_signal;
end
always @(posedge clock or negedge reset_n)
begin
if (reset_n == 0)
wrclk_control_slave_status_almostfull_q <= 0;
else
wrclk_control_slave_status_almostfull_q <= wrclk_control_slave_status_almostfull_signal;
end
always @(posedge clock or negedge reset_n)
begin
if (reset_n == 0)
wrclk_control_slave_status_empty_q <= 0;
else
wrclk_control_slave_status_empty_q <= wrclk_control_slave_status_empty_signal;
end
always @(posedge clock or negedge reset_n)
begin
if (reset_n == 0)
wrclk_control_slave_status_full_q <= 0;
else
wrclk_control_slave_status_full_q <= wrclk_control_slave_status_full_signal;
end
assign wrclk_control_slave_status_register = {wrclk_control_slave_status_underflow_q,
wrclk_control_slave_status_overflow_q,
wrclk_control_slave_status_almostempty_q,
wrclk_control_slave_status_almostfull_q,
wrclk_control_slave_status_empty_q,
wrclk_control_slave_status_full_q};
assign wrclk_control_slave_read_mux = ({32 {(wrclk_control_slave_address == 0)}} & wrclk_control_slave_level_register) |
({32 {(wrclk_control_slave_address == 1)}} & wrclk_control_slave_status_register) |
({32 {(wrclk_control_slave_address == 2)}} & wrclk_control_slave_event_register) |
({32 {(wrclk_control_slave_address == 3)}} & wrclk_control_slave_ienable_register) |
({32 {(wrclk_control_slave_address == 4)}} & wrclk_control_slave_almostfull_threshold_register) |
({32 {(wrclk_control_slave_address == 5)}} & wrclk_control_slave_almostempty_threshold_register) |
({32 {(~((wrclk_control_slave_address == 0))) && (~((wrclk_control_slave_address == 1))) && (~((wrclk_control_slave_address == 2))) && (~((wrclk_control_slave_address == 3))) && (~((wrclk_control_slave_address == 4))) && (~((wrclk_control_slave_address == 5)))}} & wrclk_control_slave_level_register);
always @(posedge clock or negedge reset_n)
begin
if (reset_n == 0)
wrclk_control_slave_readdata <= 0;
else if (wrclk_control_slave_read)
wrclk_control_slave_readdata <= wrclk_control_slave_read_mux;
end
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module DE4_SOPC_transmit_fifo_map_avalonmm_to_avalonst (
// inputs:
avalonmm_data,
// outputs:
avalonst_data
)
;
output [ 31: 0] avalonst_data;
input [ 31: 0] avalonmm_data;
wire [ 31: 0] avalonst_data;
assign avalonst_data[31 : 24] = avalonmm_data[7 : 0];
assign avalonst_data[23 : 16] = avalonmm_data[15 : 8];
assign avalonst_data[15 : 8] = avalonmm_data[23 : 16];
assign avalonst_data[7 : 0] = avalonmm_data[31 : 24];
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module DE4_SOPC_transmit_fifo_single_clock_fifo_for_other_info (
// inputs:
aclr,
clock,
data,
rdreq,
wrreq,
// outputs:
q
)
;
output [ 4: 0] q;
input aclr;
input clock;
input [ 4: 0] data;
input rdreq;
input wrreq;
wire [ 4: 0] q;
scfifo single_clock_fifo
(
.aclr (aclr),
.clock (clock),
.data (data),
.q (q),
.rdreq (rdreq),
.wrreq (wrreq)
);
defparam single_clock_fifo.add_ram_output_register = "OFF",
single_clock_fifo.intended_device_family = "STRATIXIV",
single_clock_fifo.lpm_numwords = 16,
single_clock_fifo.lpm_showahead = "OFF",
single_clock_fifo.lpm_type = "scfifo",
single_clock_fifo.lpm_width = 5,
single_clock_fifo.lpm_widthu = 4,
single_clock_fifo.overflow_checking = "ON",
single_clock_fifo.underflow_checking = "ON",
single_clock_fifo.use_eab = "ON";
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module DE4_SOPC_transmit_fifo_map_avalonmm_to_avalonst_other_info (
// inputs:
auto_clr,
avalonmm_other_info,
clock,
enable,
reset_n,
// outputs:
avalonst_other_info
)
;
output [ 4: 0] avalonst_other_info;
input auto_clr;
input [ 31: 0] avalonmm_other_info;
input clock;
input enable;
input reset_n;
wire [ 4: 0] avalonst_other_info;
wire [ 1: 0] empty;
reg [ 1: 0] empty_q;
wire eop;
reg eop_q;
wire error;
reg error_q;
wire sop;
reg sop_q;
assign error = avalonmm_other_info[16];
assign empty = avalonmm_other_info[3 : 2];
assign sop = avalonmm_other_info[0];
assign eop = avalonmm_other_info[1];
assign avalonst_other_info = {error_q,
empty_q,
eop_q,
sop_q};
always @(posedge clock or negedge reset_n)
begin
if (reset_n == 0)
sop_q <= 0;
else if (enable | auto_clr)
if (auto_clr)
sop_q <= 0;
else
sop_q <= sop;
end
always @(posedge clock or negedge reset_n)
begin
if (reset_n == 0)
eop_q <= 0;
else if (enable | auto_clr)
if (auto_clr)
eop_q <= 0;
else
eop_q <= eop;
end
always @(posedge clock or negedge reset_n)
begin
if (reset_n == 0)
empty_q <= 0;
else if (enable)
empty_q <= empty;
end
always @(posedge clock or negedge reset_n)
begin
if (reset_n == 0)
error_q <= 0;
else if (enable)
error_q <= error;
end
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module DE4_SOPC_transmit_fifo_map_fifo_other_info_to_avalonst (
// inputs:
data_in,
// outputs:
avalonst_source_empty,
avalonst_source_endofpacket,
avalonst_source_error,
avalonst_source_startofpacket
)
;
output [ 1: 0] avalonst_source_empty;
output avalonst_source_endofpacket;
output avalonst_source_error;
output avalonst_source_startofpacket;
input [ 4: 0] data_in;
wire [ 1: 0] avalonst_source_empty;
wire avalonst_source_endofpacket;
wire avalonst_source_error;
wire avalonst_source_startofpacket;
assign {avalonst_source_error,
avalonst_source_empty,
avalonst_source_endofpacket,
avalonst_source_startofpacket} = data_in;
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module DE4_SOPC_transmit_fifo (
// inputs:
avalonmm_write_slave_address,
avalonmm_write_slave_write,
avalonmm_write_slave_writedata,
avalonst_source_ready,
reset_n,
wrclk_control_slave_address,
wrclk_control_slave_read,
wrclk_control_slave_write,
wrclk_control_slave_writedata,
wrclock,
// outputs:
avalonmm_write_slave_waitrequest,
avalonst_source_data,
avalonst_source_empty,
avalonst_source_endofpacket,
avalonst_source_error,
avalonst_source_startofpacket,
avalonst_source_valid,
wrclk_control_slave_irq,
wrclk_control_slave_readdata
)
;
output avalonmm_write_slave_waitrequest;
output [ 31: 0] avalonst_source_data;
output [ 1: 0] avalonst_source_empty;
output avalonst_source_endofpacket;
output avalonst_source_error;
output avalonst_source_startofpacket;
output avalonst_source_valid;
output wrclk_control_slave_irq;
output [ 31: 0] wrclk_control_slave_readdata;
input avalonmm_write_slave_address;
input avalonmm_write_slave_write;
input [ 31: 0] avalonmm_write_slave_writedata;
input avalonst_source_ready;
input reset_n;
input [ 2: 0] wrclk_control_slave_address;
input wrclk_control_slave_read;
input wrclk_control_slave_write;
input [ 31: 0] wrclk_control_slave_writedata;
input wrclock;
wire [ 31: 0] avalonmm_map_data_in;
wire avalonmm_write_slave_waitrequest;
wire [ 31: 0] avalonst_map_data_out;
wire [ 4: 0] avalonst_other_info;
wire [ 31: 0] avalonst_source_data;
wire [ 1: 0] avalonst_source_empty;
wire avalonst_source_endofpacket;
wire avalonst_source_error;
wire avalonst_source_startofpacket;
reg avalonst_source_valid;
wire clock;
wire [ 31: 0] data;
wire empty;
wire full;
wire [ 31: 0] q;
wire [ 4: 0] q_i;
wire rdreq;
wire rdreq_i;
wire wrclk_control_slave_irq;
wire [ 31: 0] wrclk_control_slave_readdata;
wire wrreq;
wire wrreq_driver;
//the_scfifo_with_controls, which is an e_instance
DE4_SOPC_transmit_fifo_scfifo_with_controls the_scfifo_with_controls
(
.clock (clock),
.data (data),
.empty (empty),
.full (full),
.q (q),
.rdreq (rdreq),
.reset_n (reset_n),
.wrclk_control_slave_address (wrclk_control_slave_address),
.wrclk_control_slave_irq (wrclk_control_slave_irq),
.wrclk_control_slave_read (wrclk_control_slave_read),
.wrclk_control_slave_readdata (wrclk_control_slave_readdata),
.wrclk_control_slave_write (wrclk_control_slave_write),
.wrclk_control_slave_writedata (wrclk_control_slave_writedata),
.wrreq (wrreq)
);
//in, which is an e_avalon_slave
assign avalonmm_write_slave_waitrequest = full;
//the_map_avalonmm_to_avalonst, which is an e_instance
DE4_SOPC_transmit_fifo_map_avalonmm_to_avalonst the_map_avalonmm_to_avalonst
(
.avalonmm_data (avalonmm_map_data_in),
.avalonst_data (avalonst_map_data_out)
);
assign wrreq_driver = (avalonmm_write_slave_address == 0) & avalonmm_write_slave_write;
assign avalonmm_map_data_in = avalonmm_write_slave_writedata;
assign wrreq = wrreq_driver;
assign data = avalonst_map_data_out;
assign clock = wrclock;
//the_scfifo_other_info, which is an e_instance
DE4_SOPC_transmit_fifo_single_clock_fifo_for_other_info the_scfifo_other_info
(
.aclr (~reset_n),
.clock (clock),
.data (avalonst_other_info),
.q (q_i),
.rdreq (rdreq_i),
.wrreq (wrreq_driver & ~full)
);
//the_map_avalonmm_to_avalonst_other_info, which is an e_instance
DE4_SOPC_transmit_fifo_map_avalonmm_to_avalonst_other_info the_map_avalonmm_to_avalonst_other_info
(
.auto_clr (wrreq_driver & !full),
.avalonmm_other_info (avalonmm_write_slave_writedata),
.avalonst_other_info (avalonst_other_info),
.clock (clock),
.enable ((avalonmm_write_slave_address == 1) & avalonmm_write_slave_write),
.reset_n (reset_n)
);
//the_map_fifo_other_info_to_avalonst, which is an e_instance
DE4_SOPC_transmit_fifo_map_fifo_other_info_to_avalonst the_map_fifo_other_info_to_avalonst
(
.avalonst_source_empty (avalonst_source_empty),
.avalonst_source_endofpacket (avalonst_source_endofpacket),
.avalonst_source_error (avalonst_source_error),
.avalonst_source_startofpacket (avalonst_source_startofpacket),
.data_in (q_i)
);
assign avalonst_source_data = q;
assign rdreq = !empty & avalonst_source_ready;
assign rdreq_i = rdreq;
always @(posedge clock or negedge reset_n)
begin
if (reset_n == 0)
avalonst_source_valid <= 0;
else
avalonst_source_valid <= !empty & avalonst_source_ready;
end
//out, which is an e_atlantic_master
//in_csr, which is an e_avalon_slave
endmodule
|
// megafunction wizard: %Triple Speed Ethernet v12.1%
// GENERATION: XML
// ============================================================
// Megafunction Name(s):
// altera_tse_mac_pcs_pma
// ============================================================
// Generated by Triple Speed Ethernet 12.1 [Altera, IP Toolbench 1.3.0 Build 177]
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
// ************************************************************
// Copyright (C) 1991-2013 Altera Corporation
// Any megafunction design, and related net list (encrypted or decrypted),
// support information, device programming or simulation file, and any other
// associated documentation or information provided by Altera or a partner
// under Altera's Megafunction Partnership Program may be used only to
// program PLD devices (but not masked PLD devices) from Altera. Any other
// use of such megafunction design, net list, support information, device
// programming or simulation file, or any other related documentation or
// information is prohibited for any other purpose, including, but not
// limited to modification, reverse engineering, de-compiling, or use with
// any other silicon devices, unless such use is explicitly licensed under
// a separate agreement with Altera or a megafunction partner. Title to
// the intellectual property, including patents, copyrights, trademarks,
// trade secrets, or maskworks, embodied in any such megafunction design,
// net list, support information, device programming or simulation file, or
// any other related documentation or information provided by Altera or a
// megafunction partner, remains with Altera, the megafunction partner, or
// their respective licensors. No other licenses, including any licenses
// needed under any third party's intellectual property, are provided herein.
module DE4_SOPC_tse_mac (
ff_tx_data,
ff_tx_eop,
ff_tx_err,
ff_tx_mod,
ff_tx_sop,
ff_tx_wren,
ff_tx_clk,
ff_rx_rdy,
ff_rx_clk,
address,
read,
writedata,
write,
clk,
reset,
mdio_in,
rxp,
ref_clk,
ff_tx_rdy,
ff_rx_data,
ff_rx_dval,
ff_rx_eop,
ff_rx_mod,
ff_rx_sop,
rx_err,
readdata,
waitrequest,
mdio_out,
mdio_oen,
mdc,
led_an,
led_char_err,
led_link,
led_disp_err,
txp,
rx_recovclkout);
input [31:0] ff_tx_data;
input ff_tx_eop;
input ff_tx_err;
input [1:0] ff_tx_mod;
input ff_tx_sop;
input ff_tx_wren;
input ff_tx_clk;
input ff_rx_rdy;
input ff_rx_clk;
input [7:0] address;
input read;
input [31:0] writedata;
input write;
input clk;
input reset;
input mdio_in;
input rxp;
input ref_clk;
output ff_tx_rdy;
output [31:0] ff_rx_data;
output ff_rx_dval;
output ff_rx_eop;
output [1:0] ff_rx_mod;
output ff_rx_sop;
output [5:0] rx_err;
output [31:0] readdata;
output waitrequest;
output mdio_out;
output mdio_oen;
output mdc;
output led_an;
output led_char_err;
output led_link;
output led_disp_err;
output txp;
output rx_recovclkout;
altera_tse_mac_pcs_pma altera_tse_mac_pcs_pma_inst(
.ff_tx_data(ff_tx_data),
.ff_tx_eop(ff_tx_eop),
.ff_tx_err(ff_tx_err),
.ff_tx_mod(ff_tx_mod),
.ff_tx_sop(ff_tx_sop),
.ff_tx_wren(ff_tx_wren),
.ff_tx_clk(ff_tx_clk),
.ff_rx_rdy(ff_rx_rdy),
.ff_rx_clk(ff_rx_clk),
.address(address),
.read(read),
.writedata(writedata),
.write(write),
.clk(clk),
.reset(reset),
.mdio_in(mdio_in),
.rxp(rxp),
.ref_clk(ref_clk),
.ff_tx_rdy(ff_tx_rdy),
.ff_rx_data(ff_rx_data),
.ff_rx_dval(ff_rx_dval),
.ff_rx_eop(ff_rx_eop),
.ff_rx_mod(ff_rx_mod),
.ff_rx_sop(ff_rx_sop),
.rx_err(rx_err),
.readdata(readdata),
.waitrequest(waitrequest),
.mdio_out(mdio_out),
.mdio_oen(mdio_oen),
.mdc(mdc),
.led_an(led_an),
.led_char_err(led_char_err),
.led_link(led_link),
.led_disp_err(led_disp_err),
.txp(txp),
.rx_recovclkout(rx_recovclkout));
defparam
altera_tse_mac_pcs_pma_inst.ENABLE_MAGIC_DETECT = 0,
altera_tse_mac_pcs_pma_inst.ENABLE_MDIO = 1,
altera_tse_mac_pcs_pma_inst.ENABLE_SHIFT16 = 0,
altera_tse_mac_pcs_pma_inst.ENABLE_SUP_ADDR = 0,
altera_tse_mac_pcs_pma_inst.CORE_VERSION = 16'h0c01,
altera_tse_mac_pcs_pma_inst.CRC32GENDELAY = 6,
altera_tse_mac_pcs_pma_inst.MDIO_CLK_DIV = 40,
altera_tse_mac_pcs_pma_inst.ENA_HASH = 0,
altera_tse_mac_pcs_pma_inst.USE_SYNC_RESET = 1,
altera_tse_mac_pcs_pma_inst.STAT_CNT_ENA = 0,
altera_tse_mac_pcs_pma_inst.ENABLE_EXTENDED_STAT_REG = 0,
altera_tse_mac_pcs_pma_inst.ENABLE_HD_LOGIC = 0,
altera_tse_mac_pcs_pma_inst.REDUCED_INTERFACE_ENA = 0,
altera_tse_mac_pcs_pma_inst.CRC32S1L2_EXTERN = 0,
altera_tse_mac_pcs_pma_inst.ENABLE_GMII_LOOPBACK = 0,
altera_tse_mac_pcs_pma_inst.CRC32DWIDTH = 8,
altera_tse_mac_pcs_pma_inst.CUST_VERSION = 0,
altera_tse_mac_pcs_pma_inst.RESET_LEVEL = 8'h01,
altera_tse_mac_pcs_pma_inst.CRC32CHECK16BIT = 8'h00,
altera_tse_mac_pcs_pma_inst.ENABLE_MAC_FLOW_CTRL = 0,
altera_tse_mac_pcs_pma_inst.ENABLE_MAC_TXADDR_SET = 1,
altera_tse_mac_pcs_pma_inst.ENABLE_MAC_RX_VLAN = 0,
altera_tse_mac_pcs_pma_inst.ENABLE_MAC_TX_VLAN = 0,
altera_tse_mac_pcs_pma_inst.SYNCHRONIZER_DEPTH = 4,
altera_tse_mac_pcs_pma_inst.EG_FIFO = 2048,
altera_tse_mac_pcs_pma_inst.EG_ADDR = 11,
altera_tse_mac_pcs_pma_inst.ING_FIFO = 2048,
altera_tse_mac_pcs_pma_inst.ENABLE_ENA = 32,
altera_tse_mac_pcs_pma_inst.ING_ADDR = 11,
altera_tse_mac_pcs_pma_inst.RAM_TYPE = "AUTO",
altera_tse_mac_pcs_pma_inst.INSERT_TA = 1,
altera_tse_mac_pcs_pma_inst.ENABLE_MACLITE = 0,
altera_tse_mac_pcs_pma_inst.MACLITE_GIGE = 0,
altera_tse_mac_pcs_pma_inst.TSTAMP_FP_WIDTH = 4,
altera_tse_mac_pcs_pma_inst.PHY_IDENTIFIER = 32'h00000000,
altera_tse_mac_pcs_pma_inst.DEV_VERSION = 16'h0c01,
altera_tse_mac_pcs_pma_inst.ENABLE_SGMII = 0,
altera_tse_mac_pcs_pma_inst.DEVICE_FAMILY = "STRATIXIV",
altera_tse_mac_pcs_pma_inst.EXPORT_PWRDN = 0,
altera_tse_mac_pcs_pma_inst.TRANSCEIVER_OPTION = 1,
altera_tse_mac_pcs_pma_inst.ENABLE_ALT_RECONFIG = 0;
endmodule
// =========================================================
// Triple Speed Ethernet Wizard Data
// ===============================
// DO NOT EDIT FOLLOWING DATA
// @Altera, IP Toolbench@
// Warning: If you modify this section, Triple Speed Ethernet Wizard may not be able to reproduce your chosen configuration.
//
// Retrieval info: <?xml version="1.0"?>
// Retrieval info: <MEGACORE title="Triple Speed Ethernet MegaCore Function" version="12.1" build="177" iptb_version="1.3.0 Build 177" format_version="120" >
// Retrieval info: <NETLIST_SECTION class="altera.ipbu.flowbase.netlist.model.TSEMVCModel" active_core="altera_tse_mac_pcs_pma" >
// Retrieval info: <STATIC_SECTION>
// Retrieval info: <PRIVATES>
// Retrieval info: <NAMESPACE name = "parameterization">
// Retrieval info: <PRIVATE name = "atlanticSinkClockRate" value="0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "atlanticSinkClockSource" value="unassigned" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "atlanticSourceClockRate" value="0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "atlanticSourceClockSource" value="unassigned" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "avalonSlaveClockRate" value="0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "avalonSlaveClockSource" value="unassigned" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "avalonStNeighbours" value="unassigned=unassigned" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "channel_count" value="1" type="INTEGER" enable="1" />
// Retrieval info: <PRIVATE name = "core_variation" value="MAC_PCS" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "core_version" value="3073" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "crc32dwidth" value="8" type="INTEGER" enable="1" />
// Retrieval info: <PRIVATE name = "crc32gendelay" value="6" type="INTEGER" enable="1" />
// Retrieval info: <PRIVATE name = "crc32s1l2_extern" value="0" type="BOOLEAN" enable="1" />
// Retrieval info: <PRIVATE name = "cust_version" value="0" type="INTEGER" enable="1" />
// Retrieval info: <PRIVATE name = "dataBitsPerSymbol" value="8" type="INTEGER" enable="1" />
// Retrieval info: <PRIVATE name = "dev_version" value="3073" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "deviceFamily" value="STRATIXIV" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "deviceFamilyName" value="Stratix IV" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "eg_addr" value="11" type="INTEGER" enable="1" />
// Retrieval info: <PRIVATE name = "eg_fifo" value="2048" type="INTEGER" enable="1" />
// Retrieval info: <PRIVATE name = "ena_hash" value="0" type="BOOLEAN" enable="1" />
// Retrieval info: <PRIVATE name = "enable_alt_reconfig" value="0" type="BOOLEAN" enable="1" />
// Retrieval info: <PRIVATE name = "enable_clk_sharing" value="0" type="BOOLEAN" enable="1" />
// Retrieval info: <PRIVATE name = "enable_ena" value="32" type="INTEGER" enable="1" />
// Retrieval info: <PRIVATE name = "enable_fifoless" value="0" type="BOOLEAN" enable="1" />
// Retrieval info: <PRIVATE name = "enable_gmii_loopback" value="0" type="BOOLEAN" enable="1" />
// Retrieval info: <PRIVATE name = "enable_hd_logic" value="0" type="BOOLEAN" enable="1" />
// Retrieval info: <PRIVATE name = "enable_mac_flow_ctrl" value="0" type="BOOLEAN" enable="1" />
// Retrieval info: <PRIVATE name = "enable_mac_txaddr_set" value="1" type="BOOLEAN" enable="1" />
// Retrieval info: <PRIVATE name = "enable_mac_vlan" value="0" type="BOOLEAN" enable="1" />
// Retrieval info: <PRIVATE name = "enable_maclite" value="0" type="BOOLEAN" enable="1" />
// Retrieval info: <PRIVATE name = "enable_magic_detect" value="0" type="BOOLEAN" enable="1" />
// Retrieval info: <PRIVATE name = "enable_multi_channel" value="0" type="BOOLEAN" enable="1" />
// Retrieval info: <PRIVATE name = "enable_pkt_class" value="1" type="BOOLEAN" enable="1" />
// Retrieval info: <PRIVATE name = "enable_pma" value="0" type="BOOLEAN" enable="1" />
// Retrieval info: <PRIVATE name = "enable_ptp_1step" value="0" type="BOOLEAN" enable="1" />
// Retrieval info: <PRIVATE name = "enable_reg_sharing" value="0" type="BOOLEAN" enable="1" />
// Retrieval info: <PRIVATE name = "enable_sgmii" value="0" type="BOOLEAN" enable="1" />
// Retrieval info: <PRIVATE name = "enable_shift16" value="0" type="BOOLEAN" enable="1" />
// Retrieval info: <PRIVATE name = "enable_sup_addr" value="0" type="BOOLEAN" enable="1" />
// Retrieval info: <PRIVATE name = "enable_timestamping" value="0" type="BOOLEAN" enable="1" />
// Retrieval info: <PRIVATE name = "enable_use_internal_fifo" value="1" type="BOOLEAN" enable="1" />
// Retrieval info: <PRIVATE name = "export_calblkclk" value="0" type="BOOLEAN" enable="1" />
// Retrieval info: <PRIVATE name = "export_pwrdn" value="0" type="BOOLEAN" enable="1" />
// Retrieval info: <PRIVATE name = "ext_stat_cnt_ena" value="0" type="BOOLEAN" enable="1" />
// Retrieval info: <PRIVATE name = "gigeAdvanceMode" value="1" type="BOOLEAN" enable="1" />
// Retrieval info: <PRIVATE name = "ifGMII" value="MII_GMII" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "ifPCSuseEmbeddedSerdes" value="1" type="BOOLEAN" enable="1" />
// Retrieval info: <PRIVATE name = "ing_addr" value="11" type="INTEGER" enable="1" />
// Retrieval info: <PRIVATE name = "ing_fifo" value="2048" type="INTEGER" enable="1" />
// Retrieval info: <PRIVATE name = "insert_ta" value="1" type="BOOLEAN" enable="1" />
// Retrieval info: <PRIVATE name = "maclite_gige" value="0" type="BOOLEAN" enable="1" />
// Retrieval info: <PRIVATE name = "max_channels" value="1" type="INTEGER" enable="1" />
// Retrieval info: <PRIVATE name = "mdio_clk_div" value="40" type="INTEGER" enable="1" />
// Retrieval info: <PRIVATE name = "phy_identifier" value="0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "ramType" value="AUTO" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "sopcSystemTopLevelName" value="system" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "starting_channel_number" value="0" type="INTEGER" enable="1" />
// Retrieval info: <PRIVATE name = "stat_cnt_ena" value="0" type="BOOLEAN" enable="1" />
// Retrieval info: <PRIVATE name = "timingAdapterName" value="timingAdapter" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "toolContext" value="SOPC_BUILDER" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "transceiver_type" value="LVDS_IO" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "tstamp_fp_width" value="4" type="INTEGER" enable="1" />
// Retrieval info: <PRIVATE name = "uiEgFIFOSize" value="2048 x 32 Bits" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "uiHostClockFrequency" value="0" type="INTEGER" enable="1" />
// Retrieval info: <PRIVATE name = "uiIngFIFOSize" value="2048 x 32 Bits" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "uiMACFIFO" value="0" type="BOOLEAN" enable="1" />
// Retrieval info: <PRIVATE name = "uiMACOptions" value="0" type="BOOLEAN" enable="1" />
// Retrieval info: <PRIVATE name = "uiMDIOFreq" value="0.0 MHz" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "uiMIIInterfaceOptions" value="0" type="BOOLEAN" enable="1" />
// Retrieval info: <PRIVATE name = "uiPCSInterface" value="0" type="BOOLEAN" enable="1" />
// Retrieval info: <PRIVATE name = "uiPCSInterfaceOptions" value="0" type="BOOLEAN" enable="1" />
// Retrieval info: <PRIVATE name = "useLvds" value="1" type="BOOLEAN" enable="1" />
// Retrieval info: <PRIVATE name = "useMAC" value="1" type="BOOLEAN" enable="1" />
// Retrieval info: <PRIVATE name = "useMDIO" value="1" type="BOOLEAN" enable="1" />
// Retrieval info: <PRIVATE name = "usePCS" value="1" type="BOOLEAN" enable="1" />
// Retrieval info: <PRIVATE name = "use_sync_reset" value="1" type="BOOLEAN" enable="1" />
// Retrieval info: </NAMESPACE>
// Retrieval info: <NAMESPACE name = "simgen_enable">
// Retrieval info: <PRIVATE name = "language" value="VERILOG" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "enabled" value="0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "gb_enabled" value="0" type="STRING" enable="1" />
// Retrieval info: </NAMESPACE>
// Retrieval info: <NAMESPACE name = "testbench">
// Retrieval info: <PRIVATE name = "variation_name" value="DE4_SOPC_tse_mac" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "project_name" value="DE4_SOPC" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "output_name" value="DE4_SOPC_tse_mac" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "tool_context" value="SOPC_BUILDER" type="STRING" enable="1" />
// Retrieval info: </NAMESPACE>
// Retrieval info: <NAMESPACE name = "constraint_file_generator">
// Retrieval info: <PRIVATE name = "variation_name" value="DE4_SOPC_tse_mac" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "instance_name" value="DE4_SOPC_tse_mac" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "output_name" value="DE4_SOPC_tse_mac" type="STRING" enable="1" />
// Retrieval info: </NAMESPACE>
// Retrieval info: <NAMESPACE name = "modelsim_script_generator">
// Retrieval info: <PRIVATE name = "variation_name" value="DE4_SOPC_tse_mac" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "instance_name" value="DE4_SOPC_tse_mac" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "plugin_worker" value="0" type="STRING" enable="1" />
// Retrieval info: </NAMESPACE>
// Retrieval info: <NAMESPACE name = "europa_executor">
// Retrieval info: <PRIVATE name = "plugin_worker" value="0" type="STRING" enable="1" />
// Retrieval info: </NAMESPACE>
// Retrieval info: <NAMESPACE name = "simgen">
// Retrieval info: <PRIVATE name = "use_alt_top" value="0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "family" value="Stratix IV" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "filename" value="DE4_SOPC_tse_mac.vo" type="STRING" enable="1" />
// Retrieval info: </NAMESPACE>
// Retrieval info: <NAMESPACE name = "modelsim_wave_script_plugin">
// Retrieval info: <PRIVATE name = "plugin_worker" value="0" type="STRING" enable="1" />
// Retrieval info: </NAMESPACE>
// Retrieval info: <NAMESPACE name = "nativelink">
// Retrieval info: <PRIVATE name = "plugin_worker" value="0" type="STRING" enable="1" />
// Retrieval info: </NAMESPACE>
// Retrieval info: <NAMESPACE name = "settings">
// Retrieval info: <PRIVATE name = "WEB_BROWSER" value="/usr/bin/google-chrome" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "LICENSE_FILE" value="[email protected]" type="STRING" enable="1" />
// Retrieval info: </NAMESPACE>
// Retrieval info: <NAMESPACE name = "greybox">
// Retrieval info: <PRIVATE name = "filename" value="DE4_SOPC_tse_mac_syn.v" type="STRING" enable="1" />
// Retrieval info: </NAMESPACE>
// Retrieval info: <NAMESPACE name = "quartus_settings">
// Retrieval info: <PRIVATE name = "WEB_BROWSER" value="/usr/bin/google-chrome" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "LICENSE_FILE" value="[email protected]" type="STRING" enable="1" />
// Retrieval info: </NAMESPACE>
// Retrieval info: <NAMESPACE name = "serializer"/>
// Retrieval info: </PRIVATES>
// Retrieval info: <FILES/>
// Retrieval info: <PORTS/>
// Retrieval info: <LIBRARIES/>
// Retrieval info: </STATIC_SECTION>
// Retrieval info: </NETLIST_SECTION>
// Retrieval info: </MEGACORE>
// =========================================================
|
// #####################################################################################
// # Copyright (C) 1991-2008 Altera Corporation
// # Any megafunction design, and related netlist (encrypted or decrypted),
// # support information, device programming or simulation file, and any other
// # associated documentation or information provided by Altera or a partner
// # under Altera's Megafunction Partnership Program may be used only
// # to program PLD devices (but not masked PLD devices) from Altera. Any
// # other use of such megafunction design, netlist, support information,
// # device programming or simulation file, or any other related documentation
// # or information is prohibited for any other purpose, including, but not
// # limited to modification, reverse engineering, de-compiling, or use with
// # any other silicon devices, unless such use is explicitly licensed under
// # a separate agreement with Altera or a megafunction partner. Title to the
// # intellectual property, including patents, copyrights, trademarks, trade
// # secrets, or maskworks, embodied in any such megafunction design, netlist,
// # support information, device programming or simulation file, or any other
// # related documentation or information provided by Altera or a megafunction
// # partner, remains with Altera, the megafunction partner, or their respective
// # licensors. No other licenses, including any licenses needed under any third
// # party's intellectual property, are provided herein.
// #####################################################################################
// #####################################################################################
// # Loopback module for SOPC system simulation with
// # Altera Triple Speed Ethernet (TSE) Megacore
// #
// # Generated at Thu Jan 17 17:51:38 2013 as a SOPC Builder component
// #
// #####################################################################################
// # This is a module used to provide external loopback on the TSE megacore by supplying
// # necessary clocks and default signal values on the network side interface
// # (GMII/MII/TBI/Serial)
// #
// # - by default this module generate clocks for operation in Gigabit mode that is
// # of 8 ns clock period
// # - no support for forcing collision detection and carrier sense in MII mode
// # the mii_col and mii_crs signal always pulled to zero
// # - you are recomment to set the the MAC operation mode using register access
// # rather than directly pulling the control signals
// #
// #####################################################################################
`timescale 1ns / 1ps
module DE4_SOPC_tse_mac_loopback (
ref_clk,
txp,
rxp
);
output ref_clk;
input txp;
output rxp;
reg clk_tmp;
initial
clk_tmp <= 1'b0;
always
#4 clk_tmp <= ~clk_tmp;
reg reconfig_clk_tmp;
initial
reconfig_clk_tmp <= 1'b0;
always
#20 reconfig_clk_tmp <= ~reconfig_clk_tmp;
assign ref_clk = clk_tmp;
assign rxp=txp;
endmodule
|
//Legal Notice: (C)2013 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module DE4_SOPC_versionRom (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
debugaccess,
reset,
write,
writedata,
// outputs:
readdata
)
;
parameter INIT_FILE = "../version.hex";
output [ 31: 0] readdata;
input [ 2: 0] address;
input [ 3: 0] byteenable;
input chipselect;
input clk;
input clken;
input debugaccess;
input reset;
input write;
input [ 31: 0] writedata;
wire [ 31: 0] readdata;
wire wren;
assign wren = chipselect & write & debugaccess;
//s1, which is an e_avalon_slave
//s2, which is an e_avalon_slave
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
altsyncram the_altsyncram
(
.address_a (address),
.byteena_a (byteenable),
.clock0 (clk),
.clocken0 (clken),
.data_a (writedata),
.q_a (readdata),
.wren_a (wren)
);
defparam the_altsyncram.byte_size = 8,
the_altsyncram.init_file = INIT_FILE,
the_altsyncram.lpm_type = "altsyncram",
the_altsyncram.maximum_depth = 5,
the_altsyncram.numwords_a = 5,
the_altsyncram.operation_mode = "SINGLE_PORT",
the_altsyncram.outdata_reg_a = "UNREGISTERED",
the_altsyncram.ram_block_type = "AUTO",
the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE",
the_altsyncram.width_a = 32,
the_altsyncram.width_byteena_a = 4,
the_altsyncram.widthad_a = 3;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// altsyncram the_altsyncram
// (
// .address_a (address),
// .byteena_a (byteenable),
// .clock0 (clk),
// .clocken0 (clken),
// .data_a (writedata),
// .q_a (readdata),
// .wren_a (wren)
// );
//
// defparam the_altsyncram.byte_size = 8,
// the_altsyncram.init_file = "version.hex",
// the_altsyncram.lpm_type = "altsyncram",
// the_altsyncram.maximum_depth = 5,
// the_altsyncram.numwords_a = 5,
// the_altsyncram.operation_mode = "SINGLE_PORT",
// the_altsyncram.outdata_reg_a = "UNREGISTERED",
// the_altsyncram.ram_block_type = "AUTO",
// the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE",
// the_altsyncram.width_a = 32,
// the_altsyncram.width_byteena_a = 4,
// the_altsyncram.widthad_a = 3;
//
//synthesis read_comments_as_HDL off
endmodule
|
//
// Generated by Bluespec Compiler, version 2012.07.beta1 (build 29243, 2012-07-26)
//
// On Thu Aug 16 11:48:36 BST 2012
//
// Method conflict info:
// Method: asi_stream_in
// Conflict-free: asi_stream_in_ready,
// coe_tpadlcd_mtl_r,
// coe_tpadlcd_mtl_g,
// coe_tpadlcd_mtl_b,
// coe_tpadlcd_mtl_hsd,
// coe_tpadlcd_mtl_vsd
// Conflicts: asi_stream_in
//
// Method: asi_stream_in_ready
// Conflict-free: asi_stream_in,
// asi_stream_in_ready,
// coe_tpadlcd_mtl_r,
// coe_tpadlcd_mtl_g,
// coe_tpadlcd_mtl_b,
// coe_tpadlcd_mtl_hsd,
// coe_tpadlcd_mtl_vsd
//
// Method: coe_tpadlcd_mtl_r
// Conflict-free: asi_stream_in,
// asi_stream_in_ready,
// coe_tpadlcd_mtl_r,
// coe_tpadlcd_mtl_g,
// coe_tpadlcd_mtl_b,
// coe_tpadlcd_mtl_hsd,
// coe_tpadlcd_mtl_vsd
//
// Method: coe_tpadlcd_mtl_g
// Conflict-free: asi_stream_in,
// asi_stream_in_ready,
// coe_tpadlcd_mtl_r,
// coe_tpadlcd_mtl_g,
// coe_tpadlcd_mtl_b,
// coe_tpadlcd_mtl_hsd,
// coe_tpadlcd_mtl_vsd
//
// Method: coe_tpadlcd_mtl_b
// Conflict-free: asi_stream_in,
// asi_stream_in_ready,
// coe_tpadlcd_mtl_r,
// coe_tpadlcd_mtl_g,
// coe_tpadlcd_mtl_b,
// coe_tpadlcd_mtl_hsd,
// coe_tpadlcd_mtl_vsd
//
// Method: coe_tpadlcd_mtl_hsd
// Conflict-free: asi_stream_in,
// asi_stream_in_ready,
// coe_tpadlcd_mtl_r,
// coe_tpadlcd_mtl_g,
// coe_tpadlcd_mtl_b,
// coe_tpadlcd_mtl_hsd,
// coe_tpadlcd_mtl_vsd
//
// Method: coe_tpadlcd_mtl_vsd
// Conflict-free: asi_stream_in,
// asi_stream_in_ready,
// coe_tpadlcd_mtl_r,
// coe_tpadlcd_mtl_g,
// coe_tpadlcd_mtl_b,
// coe_tpadlcd_mtl_hsd,
// coe_tpadlcd_mtl_vsd
//
//
// Ports:
// Name I/O size props
// asi_stream_in_ready O 1
// coe_tpadlcd_mtl_r O 8 reg
// coe_tpadlcd_mtl_g O 8 reg
// coe_tpadlcd_mtl_b O 8 reg
// coe_tpadlcd_mtl_hsd O 1 reg
// coe_tpadlcd_mtl_vsd O 1 reg
// csi_clockreset_clk I 1 clock
// csi_clockreset_reset_n I 1 reset
// asi_stream_in_data I 24
// asi_stream_in_valid I 1
// asi_stream_in_startofpacket I 1
// asi_stream_in_endofpacket I 1
//
// No combinational paths from inputs to outputs
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
module mkAvalonStream2MTL_LCD24bit(csi_clockreset_clk,
csi_clockreset_reset_n,
asi_stream_in_data,
asi_stream_in_valid,
asi_stream_in_startofpacket,
asi_stream_in_endofpacket,
asi_stream_in_ready,
coe_tpadlcd_mtl_r,
coe_tpadlcd_mtl_g,
coe_tpadlcd_mtl_b,
coe_tpadlcd_mtl_hsd,
coe_tpadlcd_mtl_vsd);
input csi_clockreset_clk;
input csi_clockreset_reset_n;
// action method asi_stream_in
input [23 : 0] asi_stream_in_data;
input asi_stream_in_valid;
input asi_stream_in_startofpacket;
input asi_stream_in_endofpacket;
// value method asi_stream_in_ready
output asi_stream_in_ready;
// value method coe_tpadlcd_mtl_r
output [7 : 0] coe_tpadlcd_mtl_r;
// value method coe_tpadlcd_mtl_g
output [7 : 0] coe_tpadlcd_mtl_g;
// value method coe_tpadlcd_mtl_b
output [7 : 0] coe_tpadlcd_mtl_b;
// value method coe_tpadlcd_mtl_hsd
output coe_tpadlcd_mtl_hsd;
// value method coe_tpadlcd_mtl_vsd
output coe_tpadlcd_mtl_vsd;
// signals for module outputs
wire [7 : 0] coe_tpadlcd_mtl_b, coe_tpadlcd_mtl_g, coe_tpadlcd_mtl_r;
wire asi_stream_in_ready, coe_tpadlcd_mtl_hsd, coe_tpadlcd_mtl_vsd;
// inlined wires
wire [26 : 0] streamIn_d_dw$wget;
// register lcdtiming_hsd
reg lcdtiming_hsd;
wire lcdtiming_hsd$D_IN, lcdtiming_hsd$EN;
// register lcdtiming_pixel_out
reg [24 : 0] lcdtiming_pixel_out;
wire [24 : 0] lcdtiming_pixel_out$D_IN;
wire lcdtiming_pixel_out$EN;
// register lcdtiming_vsd
reg lcdtiming_vsd;
wire lcdtiming_vsd$D_IN, lcdtiming_vsd$EN;
// register lcdtiming_x
reg [11 : 0] lcdtiming_x;
wire [11 : 0] lcdtiming_x$D_IN;
wire lcdtiming_x$EN;
// register lcdtiming_y
reg [11 : 0] lcdtiming_y;
wire [11 : 0] lcdtiming_y$D_IN;
wire lcdtiming_y$EN;
// ports of submodule lcdtiming_pixel_buf
wire [24 : 0] lcdtiming_pixel_buf$D_IN, lcdtiming_pixel_buf$D_OUT;
wire lcdtiming_pixel_buf$CLR,
lcdtiming_pixel_buf$DEQ,
lcdtiming_pixel_buf$EMPTY_N,
lcdtiming_pixel_buf$ENQ,
lcdtiming_pixel_buf$FULL_N;
// ports of submodule streamIn_f
wire [25 : 0] streamIn_f$D_IN, streamIn_f$D_OUT;
wire streamIn_f$CLR,
streamIn_f$DEQ,
streamIn_f$EMPTY_N,
streamIn_f$ENQ,
streamIn_f$FULL_N;
// rule scheduling signals
wire CAN_FIRE_RL_connect_stream_to_lcd_interface,
CAN_FIRE_RL_lcdtiming_every_clock_cycle,
CAN_FIRE_RL_streamIn_push_data_into_fifo,
CAN_FIRE_asi_stream_in,
WILL_FIRE_RL_connect_stream_to_lcd_interface,
WILL_FIRE_RL_lcdtiming_every_clock_cycle,
WILL_FIRE_RL_streamIn_push_data_into_fifo,
WILL_FIRE_asi_stream_in;
// remaining internal signals
wire [7 : 0] IF_NOT_lcdtiming_y_BIT_11_4_5_AND_lcdtiming_y__ETC___d34,
IF_NOT_lcdtiming_y_BIT_11_4_5_AND_lcdtiming_y__ETC___d37,
IF_NOT_lcdtiming_y_BIT_11_4_5_AND_lcdtiming_y__ETC___d40;
wire NOT_lcdtiming_y_BIT_11_4_5_AND_lcdtiming_y_SLT_ETC___d59,
lcdtiming_pixel_buf_i_notEmpty__3_AND_lcdtimin_ETC___d65,
lcdtiming_x_SLT_1009___d66;
// action method asi_stream_in
assign CAN_FIRE_asi_stream_in = 1'd1 ;
assign WILL_FIRE_asi_stream_in = 1'd1 ;
// value method asi_stream_in_ready
assign asi_stream_in_ready = streamIn_f$FULL_N ;
// value method coe_tpadlcd_mtl_r
assign coe_tpadlcd_mtl_r = lcdtiming_pixel_out[24:17] ;
// value method coe_tpadlcd_mtl_g
assign coe_tpadlcd_mtl_g = lcdtiming_pixel_out[16:9] ;
// value method coe_tpadlcd_mtl_b
assign coe_tpadlcd_mtl_b = lcdtiming_pixel_out[8:1] ;
// value method coe_tpadlcd_mtl_hsd
assign coe_tpadlcd_mtl_hsd = lcdtiming_hsd ;
// value method coe_tpadlcd_mtl_vsd
assign coe_tpadlcd_mtl_vsd = lcdtiming_vsd ;
// submodule lcdtiming_pixel_buf
FIFO2 #(.width(32'd25),
.guarded(32'd1)) lcdtiming_pixel_buf(.RST_N(csi_clockreset_reset_n),
.CLK(csi_clockreset_clk),
.D_IN(lcdtiming_pixel_buf$D_IN),
.ENQ(lcdtiming_pixel_buf$ENQ),
.DEQ(lcdtiming_pixel_buf$DEQ),
.CLR(lcdtiming_pixel_buf$CLR),
.D_OUT(lcdtiming_pixel_buf$D_OUT),
.FULL_N(lcdtiming_pixel_buf$FULL_N),
.EMPTY_N(lcdtiming_pixel_buf$EMPTY_N));
// submodule streamIn_f
FIFOL1 #(.width(32'd26)) streamIn_f(.RST_N(csi_clockreset_reset_n),
.CLK(csi_clockreset_clk),
.D_IN(streamIn_f$D_IN),
.ENQ(streamIn_f$ENQ),
.DEQ(streamIn_f$DEQ),
.CLR(streamIn_f$CLR),
.D_OUT(streamIn_f$D_OUT),
.FULL_N(streamIn_f$FULL_N),
.EMPTY_N(streamIn_f$EMPTY_N));
// rule RL_connect_stream_to_lcd_interface
assign CAN_FIRE_RL_connect_stream_to_lcd_interface =
streamIn_f$EMPTY_N && lcdtiming_pixel_buf$FULL_N ;
assign WILL_FIRE_RL_connect_stream_to_lcd_interface =
CAN_FIRE_RL_connect_stream_to_lcd_interface ;
// rule RL_lcdtiming_every_clock_cycle
assign CAN_FIRE_RL_lcdtiming_every_clock_cycle = 1'd1 ;
assign WILL_FIRE_RL_lcdtiming_every_clock_cycle = 1'd1 ;
// rule RL_streamIn_push_data_into_fifo
assign CAN_FIRE_RL_streamIn_push_data_into_fifo =
streamIn_f$FULL_N && asi_stream_in_valid &&
streamIn_d_dw$wget[26] ;
assign WILL_FIRE_RL_streamIn_push_data_into_fifo =
CAN_FIRE_RL_streamIn_push_data_into_fifo ;
// inlined wires
assign streamIn_d_dw$wget =
{ 1'd1,
asi_stream_in_data,
asi_stream_in_startofpacket,
asi_stream_in_endofpacket } ;
// register lcdtiming_hsd
assign lcdtiming_hsd$D_IN = (lcdtiming_x ^ 12'h800) >= 12'd2032 ;
assign lcdtiming_hsd$EN = 1'd1 ;
// register lcdtiming_pixel_out
assign lcdtiming_pixel_out$D_IN =
{ IF_NOT_lcdtiming_y_BIT_11_4_5_AND_lcdtiming_y__ETC___d34,
IF_NOT_lcdtiming_y_BIT_11_4_5_AND_lcdtiming_y__ETC___d37,
IF_NOT_lcdtiming_y_BIT_11_4_5_AND_lcdtiming_y__ETC___d40,
NOT_lcdtiming_y_BIT_11_4_5_AND_lcdtiming_y_SLT_ETC___d59 } ;
assign lcdtiming_pixel_out$EN = 1'd1 ;
// register lcdtiming_vsd
assign lcdtiming_vsd$D_IN = (lcdtiming_y ^ 12'h800) >= 12'd2038 ;
assign lcdtiming_vsd$EN = 1'd1 ;
// register lcdtiming_x
assign lcdtiming_x$D_IN =
lcdtiming_x_SLT_1009___d66 ? lcdtiming_x + 12'd1 : 12'd4050 ;
assign lcdtiming_x$EN = 1'd1 ;
// register lcdtiming_y
assign lcdtiming_y$D_IN =
((lcdtiming_y ^ 12'h800) < 12'd2549) ?
lcdtiming_y + 12'd1 :
12'd4073 ;
assign lcdtiming_y$EN = !lcdtiming_x_SLT_1009___d66 ;
// submodule lcdtiming_pixel_buf
assign lcdtiming_pixel_buf$D_IN = streamIn_f$D_OUT[25:1] ;
assign lcdtiming_pixel_buf$ENQ =
CAN_FIRE_RL_connect_stream_to_lcd_interface ;
assign lcdtiming_pixel_buf$DEQ =
NOT_lcdtiming_y_BIT_11_4_5_AND_lcdtiming_y_SLT_ETC___d59 &&
lcdtiming_pixel_buf_i_notEmpty__3_AND_lcdtimin_ETC___d65 ;
assign lcdtiming_pixel_buf$CLR = 1'b0 ;
// submodule streamIn_f
assign streamIn_f$D_IN = streamIn_d_dw$wget[25:0] ;
assign streamIn_f$ENQ = CAN_FIRE_RL_streamIn_push_data_into_fifo ;
assign streamIn_f$DEQ = CAN_FIRE_RL_connect_stream_to_lcd_interface ;
assign streamIn_f$CLR = 1'b0 ;
// remaining internal signals
assign IF_NOT_lcdtiming_y_BIT_11_4_5_AND_lcdtiming_y__ETC___d34 =
NOT_lcdtiming_y_BIT_11_4_5_AND_lcdtiming_y_SLT_ETC___d59 ?
(lcdtiming_pixel_buf_i_notEmpty__3_AND_lcdtimin_ETC___d65 ?
lcdtiming_pixel_buf$D_OUT[24:17] :
8'd255) :
8'd0 ;
assign IF_NOT_lcdtiming_y_BIT_11_4_5_AND_lcdtiming_y__ETC___d37 =
NOT_lcdtiming_y_BIT_11_4_5_AND_lcdtiming_y_SLT_ETC___d59 ?
(lcdtiming_pixel_buf_i_notEmpty__3_AND_lcdtimin_ETC___d65 ?
lcdtiming_pixel_buf$D_OUT[16:9] :
8'd0) :
8'd0 ;
assign IF_NOT_lcdtiming_y_BIT_11_4_5_AND_lcdtiming_y__ETC___d40 =
NOT_lcdtiming_y_BIT_11_4_5_AND_lcdtiming_y_SLT_ETC___d59 ?
(lcdtiming_pixel_buf_i_notEmpty__3_AND_lcdtimin_ETC___d65 ?
lcdtiming_pixel_buf$D_OUT[8:1] :
8'd0) :
8'd0 ;
assign NOT_lcdtiming_y_BIT_11_4_5_AND_lcdtiming_y_SLT_ETC___d59 =
!lcdtiming_y[11] && (lcdtiming_y ^ 12'h800) < 12'd2528 &&
!lcdtiming_x[11] &&
(lcdtiming_x ^ 12'h800) < 12'd2848 ;
assign lcdtiming_pixel_buf_i_notEmpty__3_AND_lcdtimin_ETC___d65 =
lcdtiming_pixel_buf$EMPTY_N &&
lcdtiming_pixel_buf$D_OUT[0] ==
(lcdtiming_x == 12'd0 && lcdtiming_y == 12'd0) ;
assign lcdtiming_x_SLT_1009___d66 = (lcdtiming_x ^ 12'h800) < 12'd3057 ;
// handling of inlined registers
always@(posedge csi_clockreset_clk)
begin
if (!csi_clockreset_reset_n)
begin
lcdtiming_x <= `BSV_ASSIGNMENT_DELAY 12'd4050;
lcdtiming_y <= `BSV_ASSIGNMENT_DELAY 12'd4073;
end
else
begin
if (lcdtiming_x$EN)
lcdtiming_x <= `BSV_ASSIGNMENT_DELAY lcdtiming_x$D_IN;
if (lcdtiming_y$EN)
lcdtiming_y <= `BSV_ASSIGNMENT_DELAY lcdtiming_y$D_IN;
end
if (lcdtiming_hsd$EN)
lcdtiming_hsd <= `BSV_ASSIGNMENT_DELAY lcdtiming_hsd$D_IN;
if (lcdtiming_pixel_out$EN)
lcdtiming_pixel_out <= `BSV_ASSIGNMENT_DELAY lcdtiming_pixel_out$D_IN;
if (lcdtiming_vsd$EN)
lcdtiming_vsd <= `BSV_ASSIGNMENT_DELAY lcdtiming_vsd$D_IN;
end
// synopsys translate_off
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
lcdtiming_hsd = 1'h0;
lcdtiming_pixel_out = 25'h0AAAAAA;
lcdtiming_vsd = 1'h0;
lcdtiming_x = 12'hAAA;
lcdtiming_y = 12'hAAA;
end
`endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on
endmodule // mkAvalonStream2MTL_LCD24bit
|
//
// Generated by Bluespec Compiler, version 2012.07.beta1 (build 29243, 2012-07-26)
//
// On Thu Aug 16 15:00:30 BST 2012
//
// Method conflict info:
// Method: avs_s0
// Conflict-free: avs_s0_readdata,
// aso_stream_out_data,
// aso_stream_out_valid,
// aso_stream_out,
// aso_stream_out_startofpacket,
// aso_stream_out_endofpacket,
// coe_ssram_adv,
// coe_ssram_bwa_n,
// coe_ssram_bwb_n,
// coe_ssram_ce_n,
// coe_ssram_cke_n,
// coe_ssram_oe_n,
// coe_ssram_we_n,
// coe_fsm_a,
// coe_fsm_d_out,
// coe_fsm_d,
// coe_fsm_dout_req,
// coe_flash_adv_n,
// coe_flash_ce_n,
// coe_flash_clk,
// coe_flash_oe_n,
// coe_flash_we_n,
// coe_touch
// Sequenced before (restricted): avs_s0_waitrequest
// Conflicts: avs_s0
//
// Method: avs_s0_readdata
// Conflict-free: avs_s0,
// avs_s0_readdata,
// avs_s0_waitrequest,
// aso_stream_out_data,
// aso_stream_out_valid,
// aso_stream_out,
// aso_stream_out_startofpacket,
// aso_stream_out_endofpacket,
// coe_ssram_adv,
// coe_ssram_bwa_n,
// coe_ssram_bwb_n,
// coe_ssram_ce_n,
// coe_ssram_cke_n,
// coe_ssram_oe_n,
// coe_ssram_we_n,
// coe_fsm_a,
// coe_fsm_d_out,
// coe_fsm_d,
// coe_fsm_dout_req,
// coe_flash_adv_n,
// coe_flash_ce_n,
// coe_flash_clk,
// coe_flash_oe_n,
// coe_flash_we_n,
// coe_touch
//
// Method: avs_s0_waitrequest
// Conflict-free: avs_s0_readdata,
// avs_s0_waitrequest,
// aso_stream_out_data,
// aso_stream_out_valid,
// aso_stream_out,
// aso_stream_out_startofpacket,
// aso_stream_out_endofpacket,
// coe_ssram_adv,
// coe_ssram_bwa_n,
// coe_ssram_bwb_n,
// coe_ssram_ce_n,
// coe_ssram_cke_n,
// coe_ssram_oe_n,
// coe_ssram_we_n,
// coe_fsm_a,
// coe_fsm_d_out,
// coe_fsm_d,
// coe_fsm_dout_req,
// coe_flash_adv_n,
// coe_flash_ce_n,
// coe_flash_clk,
// coe_flash_oe_n,
// coe_flash_we_n,
// coe_touch
// Sequenced after (restricted): avs_s0
//
// Method: aso_stream_out_data
// Conflict-free: avs_s0,
// avs_s0_readdata,
// avs_s0_waitrequest,
// aso_stream_out_data,
// aso_stream_out_valid,
// aso_stream_out_startofpacket,
// aso_stream_out_endofpacket,
// coe_ssram_adv,
// coe_ssram_bwa_n,
// coe_ssram_bwb_n,
// coe_ssram_ce_n,
// coe_ssram_cke_n,
// coe_ssram_oe_n,
// coe_ssram_we_n,
// coe_fsm_a,
// coe_fsm_d_out,
// coe_fsm_d,
// coe_fsm_dout_req,
// coe_flash_adv_n,
// coe_flash_ce_n,
// coe_flash_clk,
// coe_flash_oe_n,
// coe_flash_we_n,
// coe_touch
// Sequenced after (restricted): aso_stream_out
//
// Method: aso_stream_out_valid
// Conflict-free: avs_s0,
// avs_s0_readdata,
// avs_s0_waitrequest,
// aso_stream_out_data,
// aso_stream_out_valid,
// aso_stream_out_startofpacket,
// aso_stream_out_endofpacket,
// coe_ssram_adv,
// coe_ssram_bwa_n,
// coe_ssram_bwb_n,
// coe_ssram_ce_n,
// coe_ssram_cke_n,
// coe_ssram_oe_n,
// coe_ssram_we_n,
// coe_fsm_a,
// coe_fsm_d_out,
// coe_fsm_d,
// coe_fsm_dout_req,
// coe_flash_adv_n,
// coe_flash_ce_n,
// coe_flash_clk,
// coe_flash_oe_n,
// coe_flash_we_n,
// coe_touch
// Sequenced after (restricted): aso_stream_out
//
// Method: aso_stream_out
// Conflict-free: avs_s0,
// avs_s0_readdata,
// avs_s0_waitrequest,
// coe_ssram_adv,
// coe_ssram_bwa_n,
// coe_ssram_bwb_n,
// coe_ssram_ce_n,
// coe_ssram_cke_n,
// coe_ssram_oe_n,
// coe_ssram_we_n,
// coe_fsm_a,
// coe_fsm_d_out,
// coe_fsm_d,
// coe_fsm_dout_req,
// coe_flash_adv_n,
// coe_flash_ce_n,
// coe_flash_clk,
// coe_flash_oe_n,
// coe_flash_we_n,
// coe_touch
// Sequenced before (restricted): aso_stream_out_data,
// aso_stream_out_valid,
// aso_stream_out_startofpacket,
// aso_stream_out_endofpacket
// Conflicts: aso_stream_out
//
// Method: aso_stream_out_startofpacket
// Conflict-free: avs_s0,
// avs_s0_readdata,
// avs_s0_waitrequest,
// aso_stream_out_data,
// aso_stream_out_valid,
// aso_stream_out_startofpacket,
// aso_stream_out_endofpacket,
// coe_ssram_adv,
// coe_ssram_bwa_n,
// coe_ssram_bwb_n,
// coe_ssram_ce_n,
// coe_ssram_cke_n,
// coe_ssram_oe_n,
// coe_ssram_we_n,
// coe_fsm_a,
// coe_fsm_d_out,
// coe_fsm_d,
// coe_fsm_dout_req,
// coe_flash_adv_n,
// coe_flash_ce_n,
// coe_flash_clk,
// coe_flash_oe_n,
// coe_flash_we_n,
// coe_touch
// Sequenced after (restricted): aso_stream_out
//
// Method: aso_stream_out_endofpacket
// Conflict-free: avs_s0,
// avs_s0_readdata,
// avs_s0_waitrequest,
// aso_stream_out_data,
// aso_stream_out_valid,
// aso_stream_out_startofpacket,
// aso_stream_out_endofpacket,
// coe_ssram_adv,
// coe_ssram_bwa_n,
// coe_ssram_bwb_n,
// coe_ssram_ce_n,
// coe_ssram_cke_n,
// coe_ssram_oe_n,
// coe_ssram_we_n,
// coe_fsm_a,
// coe_fsm_d_out,
// coe_fsm_d,
// coe_fsm_dout_req,
// coe_flash_adv_n,
// coe_flash_ce_n,
// coe_flash_clk,
// coe_flash_oe_n,
// coe_flash_we_n,
// coe_touch
// Sequenced after (restricted): aso_stream_out
//
// Method: coe_ssram_adv
// Conflict-free: avs_s0,
// avs_s0_readdata,
// avs_s0_waitrequest,
// aso_stream_out_data,
// aso_stream_out_valid,
// aso_stream_out,
// aso_stream_out_startofpacket,
// aso_stream_out_endofpacket,
// coe_ssram_adv,
// coe_ssram_bwa_n,
// coe_ssram_bwb_n,
// coe_ssram_ce_n,
// coe_ssram_cke_n,
// coe_ssram_oe_n,
// coe_ssram_we_n,
// coe_fsm_a,
// coe_fsm_d_out,
// coe_fsm_d,
// coe_fsm_dout_req,
// coe_flash_adv_n,
// coe_flash_ce_n,
// coe_flash_clk,
// coe_flash_oe_n,
// coe_flash_we_n,
// coe_touch
//
// Method: coe_ssram_bwa_n
// Conflict-free: avs_s0,
// avs_s0_readdata,
// avs_s0_waitrequest,
// aso_stream_out_data,
// aso_stream_out_valid,
// aso_stream_out,
// aso_stream_out_startofpacket,
// aso_stream_out_endofpacket,
// coe_ssram_adv,
// coe_ssram_bwa_n,
// coe_ssram_bwb_n,
// coe_ssram_ce_n,
// coe_ssram_cke_n,
// coe_ssram_oe_n,
// coe_ssram_we_n,
// coe_fsm_a,
// coe_fsm_d_out,
// coe_fsm_dout_req,
// coe_flash_adv_n,
// coe_flash_ce_n,
// coe_flash_clk,
// coe_flash_oe_n,
// coe_flash_we_n,
// coe_touch
// Sequenced after (restricted): coe_fsm_d
//
// Method: coe_ssram_bwb_n
// Conflict-free: avs_s0,
// avs_s0_readdata,
// avs_s0_waitrequest,
// aso_stream_out_data,
// aso_stream_out_valid,
// aso_stream_out,
// aso_stream_out_startofpacket,
// aso_stream_out_endofpacket,
// coe_ssram_adv,
// coe_ssram_bwa_n,
// coe_ssram_bwb_n,
// coe_ssram_ce_n,
// coe_ssram_cke_n,
// coe_ssram_oe_n,
// coe_ssram_we_n,
// coe_fsm_a,
// coe_fsm_d_out,
// coe_fsm_dout_req,
// coe_flash_adv_n,
// coe_flash_ce_n,
// coe_flash_clk,
// coe_flash_oe_n,
// coe_flash_we_n,
// coe_touch
// Sequenced after (restricted): coe_fsm_d
//
// Method: coe_ssram_ce_n
// Conflict-free: avs_s0,
// avs_s0_readdata,
// avs_s0_waitrequest,
// aso_stream_out_data,
// aso_stream_out_valid,
// aso_stream_out,
// aso_stream_out_startofpacket,
// aso_stream_out_endofpacket,
// coe_ssram_adv,
// coe_ssram_bwa_n,
// coe_ssram_bwb_n,
// coe_ssram_ce_n,
// coe_ssram_cke_n,
// coe_ssram_oe_n,
// coe_ssram_we_n,
// coe_fsm_a,
// coe_fsm_d_out,
// coe_fsm_dout_req,
// coe_flash_adv_n,
// coe_flash_ce_n,
// coe_flash_clk,
// coe_flash_oe_n,
// coe_flash_we_n,
// coe_touch
// Sequenced after (restricted): coe_fsm_d
//
// Method: coe_ssram_cke_n
// Conflict-free: avs_s0,
// avs_s0_readdata,
// avs_s0_waitrequest,
// aso_stream_out_data,
// aso_stream_out_valid,
// aso_stream_out,
// aso_stream_out_startofpacket,
// aso_stream_out_endofpacket,
// coe_ssram_adv,
// coe_ssram_bwa_n,
// coe_ssram_bwb_n,
// coe_ssram_ce_n,
// coe_ssram_cke_n,
// coe_ssram_oe_n,
// coe_ssram_we_n,
// coe_fsm_a,
// coe_fsm_d_out,
// coe_fsm_d,
// coe_fsm_dout_req,
// coe_flash_adv_n,
// coe_flash_ce_n,
// coe_flash_clk,
// coe_flash_oe_n,
// coe_flash_we_n,
// coe_touch
//
// Method: coe_ssram_oe_n
// Conflict-free: avs_s0,
// avs_s0_readdata,
// avs_s0_waitrequest,
// aso_stream_out_data,
// aso_stream_out_valid,
// aso_stream_out,
// aso_stream_out_startofpacket,
// aso_stream_out_endofpacket,
// coe_ssram_adv,
// coe_ssram_bwa_n,
// coe_ssram_bwb_n,
// coe_ssram_ce_n,
// coe_ssram_cke_n,
// coe_ssram_oe_n,
// coe_ssram_we_n,
// coe_fsm_a,
// coe_fsm_d_out,
// coe_fsm_dout_req,
// coe_flash_adv_n,
// coe_flash_ce_n,
// coe_flash_clk,
// coe_flash_oe_n,
// coe_flash_we_n,
// coe_touch
// Sequenced after (restricted): coe_fsm_d
//
// Method: coe_ssram_we_n
// Conflict-free: avs_s0,
// avs_s0_readdata,
// avs_s0_waitrequest,
// aso_stream_out_data,
// aso_stream_out_valid,
// aso_stream_out,
// aso_stream_out_startofpacket,
// aso_stream_out_endofpacket,
// coe_ssram_adv,
// coe_ssram_bwa_n,
// coe_ssram_bwb_n,
// coe_ssram_ce_n,
// coe_ssram_cke_n,
// coe_ssram_oe_n,
// coe_ssram_we_n,
// coe_fsm_a,
// coe_fsm_d_out,
// coe_fsm_dout_req,
// coe_flash_adv_n,
// coe_flash_ce_n,
// coe_flash_clk,
// coe_flash_oe_n,
// coe_flash_we_n,
// coe_touch
// Sequenced after (restricted): coe_fsm_d
//
// Method: coe_fsm_a
// Conflict-free: avs_s0,
// avs_s0_readdata,
// avs_s0_waitrequest,
// aso_stream_out_data,
// aso_stream_out_valid,
// aso_stream_out,
// aso_stream_out_startofpacket,
// aso_stream_out_endofpacket,
// coe_ssram_adv,
// coe_ssram_bwa_n,
// coe_ssram_bwb_n,
// coe_ssram_ce_n,
// coe_ssram_cke_n,
// coe_ssram_oe_n,
// coe_ssram_we_n,
// coe_fsm_a,
// coe_fsm_d_out,
// coe_fsm_dout_req,
// coe_flash_adv_n,
// coe_flash_ce_n,
// coe_flash_clk,
// coe_flash_oe_n,
// coe_flash_we_n,
// coe_touch
// Sequenced after (restricted): coe_fsm_d
//
// Method: coe_fsm_d_out
// Conflict-free: avs_s0,
// avs_s0_readdata,
// avs_s0_waitrequest,
// aso_stream_out_data,
// aso_stream_out_valid,
// aso_stream_out,
// aso_stream_out_startofpacket,
// aso_stream_out_endofpacket,
// coe_ssram_adv,
// coe_ssram_bwa_n,
// coe_ssram_bwb_n,
// coe_ssram_ce_n,
// coe_ssram_cke_n,
// coe_ssram_oe_n,
// coe_ssram_we_n,
// coe_fsm_a,
// coe_fsm_d_out,
// coe_fsm_dout_req,
// coe_flash_adv_n,
// coe_flash_ce_n,
// coe_flash_clk,
// coe_flash_oe_n,
// coe_flash_we_n,
// coe_touch
// Sequenced after (restricted): coe_fsm_d
//
// Method: coe_fsm_d
// Conflict-free: avs_s0,
// avs_s0_readdata,
// avs_s0_waitrequest,
// aso_stream_out_data,
// aso_stream_out_valid,
// aso_stream_out,
// aso_stream_out_startofpacket,
// aso_stream_out_endofpacket,
// coe_ssram_adv,
// coe_ssram_cke_n,
// coe_flash_clk,
// coe_touch
// Sequenced before (restricted): coe_ssram_bwa_n,
// coe_ssram_bwb_n,
// coe_ssram_ce_n,
// coe_ssram_oe_n,
// coe_ssram_we_n,
// coe_fsm_a,
// coe_fsm_d_out,
// coe_fsm_dout_req,
// coe_flash_adv_n,
// coe_flash_ce_n,
// coe_flash_oe_n,
// coe_flash_we_n
// Conflicts: coe_fsm_d
//
// Method: coe_fsm_dout_req
// Conflict-free: avs_s0,
// avs_s0_readdata,
// avs_s0_waitrequest,
// aso_stream_out_data,
// aso_stream_out_valid,
// aso_stream_out,
// aso_stream_out_startofpacket,
// aso_stream_out_endofpacket,
// coe_ssram_adv,
// coe_ssram_bwa_n,
// coe_ssram_bwb_n,
// coe_ssram_ce_n,
// coe_ssram_cke_n,
// coe_ssram_oe_n,
// coe_ssram_we_n,
// coe_fsm_a,
// coe_fsm_d_out,
// coe_fsm_dout_req,
// coe_flash_adv_n,
// coe_flash_ce_n,
// coe_flash_clk,
// coe_flash_oe_n,
// coe_flash_we_n,
// coe_touch
// Sequenced after (restricted): coe_fsm_d
//
// Method: coe_flash_adv_n
// Conflict-free: avs_s0,
// avs_s0_readdata,
// avs_s0_waitrequest,
// aso_stream_out_data,
// aso_stream_out_valid,
// aso_stream_out,
// aso_stream_out_startofpacket,
// aso_stream_out_endofpacket,
// coe_ssram_adv,
// coe_ssram_bwa_n,
// coe_ssram_bwb_n,
// coe_ssram_ce_n,
// coe_ssram_cke_n,
// coe_ssram_oe_n,
// coe_ssram_we_n,
// coe_fsm_a,
// coe_fsm_d_out,
// coe_fsm_dout_req,
// coe_flash_adv_n,
// coe_flash_ce_n,
// coe_flash_clk,
// coe_flash_oe_n,
// coe_flash_we_n,
// coe_touch
// Sequenced after (restricted): coe_fsm_d
//
// Method: coe_flash_ce_n
// Conflict-free: avs_s0,
// avs_s0_readdata,
// avs_s0_waitrequest,
// aso_stream_out_data,
// aso_stream_out_valid,
// aso_stream_out,
// aso_stream_out_startofpacket,
// aso_stream_out_endofpacket,
// coe_ssram_adv,
// coe_ssram_bwa_n,
// coe_ssram_bwb_n,
// coe_ssram_ce_n,
// coe_ssram_cke_n,
// coe_ssram_oe_n,
// coe_ssram_we_n,
// coe_fsm_a,
// coe_fsm_d_out,
// coe_fsm_dout_req,
// coe_flash_adv_n,
// coe_flash_ce_n,
// coe_flash_clk,
// coe_flash_oe_n,
// coe_flash_we_n,
// coe_touch
// Sequenced after (restricted): coe_fsm_d
//
// Method: coe_flash_clk
// Conflict-free: avs_s0,
// avs_s0_readdata,
// avs_s0_waitrequest,
// aso_stream_out_data,
// aso_stream_out_valid,
// aso_stream_out,
// aso_stream_out_startofpacket,
// aso_stream_out_endofpacket,
// coe_ssram_adv,
// coe_ssram_bwa_n,
// coe_ssram_bwb_n,
// coe_ssram_ce_n,
// coe_ssram_cke_n,
// coe_ssram_oe_n,
// coe_ssram_we_n,
// coe_fsm_a,
// coe_fsm_d_out,
// coe_fsm_d,
// coe_fsm_dout_req,
// coe_flash_adv_n,
// coe_flash_ce_n,
// coe_flash_clk,
// coe_flash_oe_n,
// coe_flash_we_n,
// coe_touch
//
// Method: coe_flash_oe_n
// Conflict-free: avs_s0,
// avs_s0_readdata,
// avs_s0_waitrequest,
// aso_stream_out_data,
// aso_stream_out_valid,
// aso_stream_out,
// aso_stream_out_startofpacket,
// aso_stream_out_endofpacket,
// coe_ssram_adv,
// coe_ssram_bwa_n,
// coe_ssram_bwb_n,
// coe_ssram_ce_n,
// coe_ssram_cke_n,
// coe_ssram_oe_n,
// coe_ssram_we_n,
// coe_fsm_a,
// coe_fsm_d_out,
// coe_fsm_dout_req,
// coe_flash_adv_n,
// coe_flash_ce_n,
// coe_flash_clk,
// coe_flash_oe_n,
// coe_flash_we_n,
// coe_touch
// Sequenced after (restricted): coe_fsm_d
//
// Method: coe_flash_we_n
// Conflict-free: avs_s0,
// avs_s0_readdata,
// avs_s0_waitrequest,
// aso_stream_out_data,
// aso_stream_out_valid,
// aso_stream_out,
// aso_stream_out_startofpacket,
// aso_stream_out_endofpacket,
// coe_ssram_adv,
// coe_ssram_bwa_n,
// coe_ssram_bwb_n,
// coe_ssram_ce_n,
// coe_ssram_cke_n,
// coe_ssram_oe_n,
// coe_ssram_we_n,
// coe_fsm_a,
// coe_fsm_d_out,
// coe_fsm_dout_req,
// coe_flash_adv_n,
// coe_flash_ce_n,
// coe_flash_clk,
// coe_flash_oe_n,
// coe_flash_we_n,
// coe_touch
// Sequenced after (restricted): coe_fsm_d
//
// Method: coe_touch
// Conflict-free: avs_s0,
// avs_s0_readdata,
// avs_s0_waitrequest,
// aso_stream_out_data,
// aso_stream_out_valid,
// aso_stream_out,
// aso_stream_out_startofpacket,
// aso_stream_out_endofpacket,
// coe_ssram_adv,
// coe_ssram_bwa_n,
// coe_ssram_bwb_n,
// coe_ssram_ce_n,
// coe_ssram_cke_n,
// coe_ssram_oe_n,
// coe_ssram_we_n,
// coe_fsm_a,
// coe_fsm_d_out,
// coe_fsm_d,
// coe_fsm_dout_req,
// coe_flash_adv_n,
// coe_flash_ce_n,
// coe_flash_clk,
// coe_flash_oe_n,
// coe_flash_we_n
// Conflicts: coe_touch
//
//
// Ports:
// Name I/O size props
// avs_s0_readdata O 32
// avs_s0_waitrequest O 1
// aso_stream_out_data O 24
// aso_stream_out_valid O 1
// aso_stream_out_startofpacket O 1
// aso_stream_out_endofpacket O 1
// coe_ssram_adv O 1 const
// coe_ssram_bwa_n O 1
// coe_ssram_bwb_n O 1
// coe_ssram_ce_n O 1
// coe_ssram_cke_n O 1 const
// coe_ssram_oe_n O 1
// coe_ssram_we_n O 1
// coe_fsm_a O 25
// coe_fsm_d_out O 16
// coe_fsm_dout_req O 1
// coe_flash_adv_n O 1
// coe_flash_ce_n O 1
// coe_flash_clk O 1 const
// coe_flash_oe_n O 1
// coe_flash_we_n O 1
// csi_clockreset_clk I 1 clock
// csi_clockreset_reset_n I 1 reset
// avs_s0_address I 25 reg
// avs_s0_writedata I 32 reg
// avs_s0_write I 1
// avs_s0_read I 1
// avs_s0_byteenable I 4 reg
// aso_stream_out_ready I 1
// coe_fsm_d_in I 16
// coe_touch_x1 I 10
// coe_touch_y1 I 9
// coe_touch_x2 I 10
// coe_touch_y2 I 9
// coe_touch_count_gesture I 10
// coe_touch_touch_valid I 1
//
// Combinational paths from inputs to outputs:
// (avs_s0_write, avs_s0_read) -> avs_s0_waitrequest
// aso_stream_out_ready -> aso_stream_out_data
// aso_stream_out_ready -> aso_stream_out_valid
// aso_stream_out_ready -> aso_stream_out_startofpacket
// aso_stream_out_ready -> aso_stream_out_endofpacket
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
module mkMTL_Framebuffer_Flash(csi_clockreset_clk,
csi_clockreset_reset_n,
avs_s0_address,
avs_s0_writedata,
avs_s0_write,
avs_s0_read,
avs_s0_byteenable,
avs_s0_readdata,
avs_s0_waitrequest,
aso_stream_out_data,
aso_stream_out_valid,
aso_stream_out_ready,
aso_stream_out_startofpacket,
aso_stream_out_endofpacket,
coe_ssram_adv,
coe_ssram_bwa_n,
coe_ssram_bwb_n,
coe_ssram_ce_n,
coe_ssram_cke_n,
coe_ssram_oe_n,
coe_ssram_we_n,
coe_fsm_a,
coe_fsm_d_out,
coe_fsm_d_in,
coe_fsm_dout_req,
coe_flash_adv_n,
coe_flash_ce_n,
coe_flash_clk,
coe_flash_oe_n,
coe_flash_we_n,
coe_touch_x1,
coe_touch_y1,
coe_touch_x2,
coe_touch_y2,
coe_touch_count_gesture,
coe_touch_touch_valid);
input csi_clockreset_clk;
input csi_clockreset_reset_n;
// action method avs_s0
input [24 : 0] avs_s0_address;
input [31 : 0] avs_s0_writedata;
input avs_s0_write;
input avs_s0_read;
input [3 : 0] avs_s0_byteenable;
// value method avs_s0_readdata
output [31 : 0] avs_s0_readdata;
// value method avs_s0_waitrequest
output avs_s0_waitrequest;
// value method aso_stream_out_data
output [23 : 0] aso_stream_out_data;
// value method aso_stream_out_valid
output aso_stream_out_valid;
// action method aso_stream_out
input aso_stream_out_ready;
// value method aso_stream_out_startofpacket
output aso_stream_out_startofpacket;
// value method aso_stream_out_endofpacket
output aso_stream_out_endofpacket;
// value method coe_ssram_adv
output coe_ssram_adv;
// value method coe_ssram_bwa_n
output coe_ssram_bwa_n;
// value method coe_ssram_bwb_n
output coe_ssram_bwb_n;
// value method coe_ssram_ce_n
output coe_ssram_ce_n;
// value method coe_ssram_cke_n
output coe_ssram_cke_n;
// value method coe_ssram_oe_n
output coe_ssram_oe_n;
// value method coe_ssram_we_n
output coe_ssram_we_n;
// value method coe_fsm_a
output [24 : 0] coe_fsm_a;
// value method coe_fsm_d_out
output [15 : 0] coe_fsm_d_out;
// action method coe_fsm_d
input [15 : 0] coe_fsm_d_in;
// value method coe_fsm_dout_req
output coe_fsm_dout_req;
// value method coe_flash_adv_n
output coe_flash_adv_n;
// value method coe_flash_ce_n
output coe_flash_ce_n;
// value method coe_flash_clk
output coe_flash_clk;
// value method coe_flash_oe_n
output coe_flash_oe_n;
// value method coe_flash_we_n
output coe_flash_we_n;
// action method coe_touch
input [9 : 0] coe_touch_x1;
input [8 : 0] coe_touch_y1;
input [9 : 0] coe_touch_x2;
input [8 : 0] coe_touch_y2;
input [9 : 0] coe_touch_count_gesture;
input coe_touch_touch_valid;
// signals for module outputs
wire [31 : 0] avs_s0_readdata;
wire [24 : 0] coe_fsm_a;
wire [23 : 0] aso_stream_out_data;
wire [15 : 0] coe_fsm_d_out;
wire aso_stream_out_endofpacket,
aso_stream_out_startofpacket,
aso_stream_out_valid,
avs_s0_waitrequest,
coe_flash_adv_n,
coe_flash_ce_n,
coe_flash_clk,
coe_flash_oe_n,
coe_flash_we_n,
coe_fsm_dout_req,
coe_ssram_adv,
coe_ssram_bwa_n,
coe_ssram_bwb_n,
coe_ssram_ce_n,
coe_ssram_cke_n,
coe_ssram_oe_n,
coe_ssram_we_n;
// inlined wires
wire [24 : 0] pixel_engine_lcd_stream_data_dw$wget;
wire [15 : 0] mem_fsm_dout_dw$wget;
wire avalon_slave_avalonwait$wget,
avalon_slave_avalonwait_end_read$whas,
avalon_slave_avalonwait_end_write$whas,
mem_flash_ce_n_dw$wget,
mem_flash_we_n_dw$wget,
mem_fsm_a_w$whas,
mem_fsm_dout_dw$whas,
mem_fsm_dout_req_dw$wget,
mem_ssram_ce_pw$whas;
// register avalon_slave_ignore_further_requests
reg avalon_slave_ignore_further_requests;
wire avalon_slave_ignore_further_requests$D_IN,
avalon_slave_ignore_further_requests$EN;
// register mem_flash_timer
reg [3 : 0] mem_flash_timer;
wire [3 : 0] mem_flash_timer$D_IN;
wire mem_flash_timer$EN;
// register pixel_engine_addr
reg [24 : 0] pixel_engine_addr;
wire [24 : 0] pixel_engine_addr$D_IN;
wire pixel_engine_addr$EN;
// register pixel_engine_char_addr
reg [24 : 0] pixel_engine_char_addr;
wire [24 : 0] pixel_engine_char_addr$D_IN;
wire pixel_engine_char_addr$EN;
// register pixel_engine_char_base
reg [24 : 0] pixel_engine_char_base;
wire [24 : 0] pixel_engine_char_base$D_IN;
wire pixel_engine_char_base$EN;
// register pixel_engine_char_ctr
reg pixel_engine_char_ctr;
wire pixel_engine_char_ctr$D_IN, pixel_engine_char_ctr$EN;
// register pixel_engine_char_end
reg [24 : 0] pixel_engine_char_end;
wire [24 : 0] pixel_engine_char_end$D_IN;
wire pixel_engine_char_end$EN;
// register pixel_engine_char_x_pos
reg [2 : 0] pixel_engine_char_x_pos;
wire [2 : 0] pixel_engine_char_x_pos$D_IN;
wire pixel_engine_char_x_pos$EN;
// register pixel_engine_char_x_two_char
reg [5 : 0] pixel_engine_char_x_two_char;
wire [5 : 0] pixel_engine_char_x_two_char$D_IN;
wire pixel_engine_char_x_two_char$EN;
// register pixel_engine_char_y
reg [24 : 0] pixel_engine_char_y;
wire [24 : 0] pixel_engine_char_y$D_IN;
wire pixel_engine_char_y$EN;
// register pixel_engine_cursor_pos
reg [15 : 0] pixel_engine_cursor_pos;
wire [15 : 0] pixel_engine_cursor_pos$D_IN;
wire pixel_engine_cursor_pos$EN;
// register pixel_engine_fb_blend
reg [31 : 0] pixel_engine_fb_blend;
wire [31 : 0] pixel_engine_fb_blend$D_IN;
wire pixel_engine_fb_blend$EN;
// register pixel_engine_flash_col
reg [5 : 0] pixel_engine_flash_col;
wire [5 : 0] pixel_engine_flash_col$D_IN;
wire pixel_engine_flash_col$EN;
// register pixel_engine_font_y
reg [3 : 0] pixel_engine_font_y;
wire [3 : 0] pixel_engine_font_y$D_IN;
wire pixel_engine_font_y$EN;
// register prev_touch_info
reg [47 : 0] prev_touch_info;
wire [47 : 0] prev_touch_info$D_IN;
wire prev_touch_info$EN;
// ports of submodule avalon_control_reg_resp
wire [32 : 0] avalon_control_reg_resp$D_IN, avalon_control_reg_resp$D_OUT;
wire avalon_control_reg_resp$CLR,
avalon_control_reg_resp$DEQ,
avalon_control_reg_resp$EMPTY_N,
avalon_control_reg_resp$ENQ,
avalon_control_reg_resp$FULL_N;
// ports of submodule avalon_mem_resp
wire [32 : 0] avalon_mem_resp$D_IN, avalon_mem_resp$D_OUT;
wire avalon_mem_resp$CLR,
avalon_mem_resp$DEQ,
avalon_mem_resp$EMPTY_N,
avalon_mem_resp$ENQ,
avalon_mem_resp$FULL_N;
// ports of submodule avalon_req
wire [61 : 0] avalon_req$D_IN, avalon_req$D_OUT;
wire avalon_req$CLR,
avalon_req$DEQ,
avalon_req$EMPTY_N,
avalon_req$ENQ,
avalon_req$FULL_N;
// ports of submodule avalon_slave_outbuf
wire [62 : 0] avalon_slave_outbuf$D_IN, avalon_slave_outbuf$D_OUT;
wire avalon_slave_outbuf$CLR,
avalon_slave_outbuf$DEQ,
avalon_slave_outbuf$EMPTY_N,
avalon_slave_outbuf$ENQ,
avalon_slave_outbuf$FULL_N;
// ports of submodule lower_16b_returned
wire [16 : 0] lower_16b_returned$D_IN, lower_16b_returned$D_OUT;
wire lower_16b_returned$CLR,
lower_16b_returned$DEQ,
lower_16b_returned$EMPTY_N,
lower_16b_returned$ENQ;
// ports of submodule mem_pipe0
wire [16 : 0] mem_pipe0$D_IN, mem_pipe0$D_OUT;
wire mem_pipe0$CLR,
mem_pipe0$DEQ,
mem_pipe0$EMPTY_N,
mem_pipe0$ENQ,
mem_pipe0$FULL_N;
// ports of submodule mem_pipe1
wire [16 : 0] mem_pipe1$D_IN, mem_pipe1$D_OUT;
wire mem_pipe1$CLR,
mem_pipe1$DEQ,
mem_pipe1$EMPTY_N,
mem_pipe1$ENQ,
mem_pipe1$FULL_N;
// ports of submodule mem_pipe2
wire [16 : 0] mem_pipe2$D_IN, mem_pipe2$D_OUT;
wire mem_pipe2$CLR,
mem_pipe2$DEQ,
mem_pipe2$EMPTY_N,
mem_pipe2$ENQ,
mem_pipe2$FULL_N;
// ports of submodule mem_req
wire [44 : 0] mem_req$D_IN, mem_req$D_OUT;
wire mem_req$CLR, mem_req$DEQ, mem_req$EMPTY_N, mem_req$ENQ, mem_req$FULL_N;
// ports of submodule mem_resp
wire [16 : 0] mem_resp$D_IN, mem_resp$D_OUT;
wire mem_resp$CLR,
mem_resp$DEQ,
mem_resp$EMPTY_N,
mem_resp$ENQ,
mem_resp$FULL_N;
// ports of submodule mem_upper_16b_request
wire [44 : 0] mem_upper_16b_request$D_IN, mem_upper_16b_request$D_OUT;
wire mem_upper_16b_request$CLR,
mem_upper_16b_request$DEQ,
mem_upper_16b_request$EMPTY_N,
mem_upper_16b_request$ENQ;
// ports of submodule pixel_engine_char_colour
wire [9 : 0] pixel_engine_char_colour$D_IN, pixel_engine_char_colour$D_OUT;
wire pixel_engine_char_colour$CLR,
pixel_engine_char_colour$DEQ,
pixel_engine_char_colour$EMPTY_N,
pixel_engine_char_colour$ENQ,
pixel_engine_char_colour$FULL_N;
// ports of submodule pixel_engine_char_pixel
wire [9 : 0] pixel_engine_char_pixel$D_IN, pixel_engine_char_pixel$D_OUT;
wire pixel_engine_char_pixel$CLR,
pixel_engine_char_pixel$DEQ,
pixel_engine_char_pixel$EMPTY_N,
pixel_engine_char_pixel$ENQ,
pixel_engine_char_pixel$FULL_N;
// ports of submodule pixel_engine_char_pos
wire [15 : 0] pixel_engine_char_pos$D_IN, pixel_engine_char_pos$D_OUT;
wire pixel_engine_char_pos$CLR,
pixel_engine_char_pos$DEQ,
pixel_engine_char_pos$EMPTY_N,
pixel_engine_char_pos$ENQ,
pixel_engine_char_pos$FULL_N;
// ports of submodule pixel_engine_chars_read
wire pixel_engine_chars_read$CLR,
pixel_engine_chars_read$DEQ,
pixel_engine_chars_read$D_IN,
pixel_engine_chars_read$D_OUT,
pixel_engine_chars_read$EMPTY_N,
pixel_engine_chars_read$ENQ,
pixel_engine_chars_read$FULL_N;
// ports of submodule pixel_engine_font_y_pos
wire [3 : 0] pixel_engine_font_y_pos$D_IN, pixel_engine_font_y_pos$D_OUT;
wire pixel_engine_font_y_pos$CLR,
pixel_engine_font_y_pos$DEQ,
pixel_engine_font_y_pos$EMPTY_N,
pixel_engine_font_y_pos$ENQ,
pixel_engine_font_y_pos$FULL_N;
// ports of submodule pixel_engine_fontbits
wire [7 : 0] pixel_engine_fontbits$D_IN, pixel_engine_fontbits$D_OUT;
wire pixel_engine_fontbits$CLR,
pixel_engine_fontbits$DEQ,
pixel_engine_fontbits$EMPTY_N,
pixel_engine_fontbits$ENQ,
pixel_engine_fontbits$FULL_N;
// ports of submodule pixel_engine_fontrom_rom
wire [11 : 0] pixel_engine_fontrom_rom$v_addr;
wire [7 : 0] pixel_engine_fontrom_rom$v_data;
wire pixel_engine_fontrom_rom$v_en;
// ports of submodule pixel_engine_fontrom_seq_fifo
wire pixel_engine_fontrom_seq_fifo$CLR,
pixel_engine_fontrom_seq_fifo$DEQ,
pixel_engine_fontrom_seq_fifo$D_IN,
pixel_engine_fontrom_seq_fifo$EMPTY_N,
pixel_engine_fontrom_seq_fifo$ENQ,
pixel_engine_fontrom_seq_fifo$FULL_N;
// ports of submodule pixel_engine_pixpos
wire [1 : 0] pixel_engine_pixpos$D_IN, pixel_engine_pixpos$D_OUT;
wire pixel_engine_pixpos$CLR,
pixel_engine_pixpos$DEQ,
pixel_engine_pixpos$EMPTY_N,
pixel_engine_pixpos$ENQ,
pixel_engine_pixpos$FULL_N;
// ports of submodule pixel_engine_req
wire [61 : 0] pixel_engine_req$D_IN, pixel_engine_req$D_OUT;
wire pixel_engine_req$CLR,
pixel_engine_req$DEQ,
pixel_engine_req$EMPTY_N,
pixel_engine_req$ENQ,
pixel_engine_req$FULL_N;
// ports of submodule pixel_engine_ssram_req
wire [61 : 0] pixel_engine_ssram_req$D_IN, pixel_engine_ssram_req$D_OUT;
wire pixel_engine_ssram_req$CLR,
pixel_engine_ssram_req$DEQ,
pixel_engine_ssram_req$EMPTY_N,
pixel_engine_ssram_req$ENQ,
pixel_engine_ssram_req$FULL_N;
// ports of submodule pixel_engine_ssram_resp
wire [31 : 0] pixel_engine_ssram_resp$D_IN, pixel_engine_ssram_resp$D_OUT;
wire pixel_engine_ssram_resp$CLR,
pixel_engine_ssram_resp$DEQ,
pixel_engine_ssram_resp$EMPTY_N,
pixel_engine_ssram_resp$ENQ,
pixel_engine_ssram_resp$FULL_N;
// ports of submodule pixel_engine_two_chars
wire [31 : 0] pixel_engine_two_chars$D_IN, pixel_engine_two_chars$D_OUT;
wire pixel_engine_two_chars$CLR,
pixel_engine_two_chars$DEQ,
pixel_engine_two_chars$EMPTY_N,
pixel_engine_two_chars$ENQ,
pixel_engine_two_chars$FULL_N;
// ports of submodule response_for_avalon
wire response_for_avalon$CLR,
response_for_avalon$DEQ,
response_for_avalon$D_IN,
response_for_avalon$D_OUT,
response_for_avalon$EMPTY_N,
response_for_avalon$ENQ,
response_for_avalon$FULL_N;
// ports of submodule touch
wire [47 : 0] touch$D_IN, touch$D_OUT;
wire touch$CLR, touch$DEQ, touch$EMPTY_N, touch$ENQ, touch$FULL_N;
// rule scheduling signals
wire CAN_FIRE_RL_arbitrate_requests,
CAN_FIRE_RL_avalon_request_splitter,
CAN_FIRE_RL_avalon_slave_cancel_ingore_further_requests,
CAN_FIRE_RL_avalon_slave_hanlde_bus_requests,
CAN_FIRE_RL_avalon_slave_wire_up_avalonwait,
CAN_FIRE_RL_forward_upper_bytes,
CAN_FIRE_RL_mem_forward_requests_flash,
CAN_FIRE_RL_mem_forward_requests_ssram,
CAN_FIRE_RL_mem_pipe_stage_0,
CAN_FIRE_RL_mem_pipe_stage_1,
CAN_FIRE_RL_mem_pipe_stage_2,
CAN_FIRE_RL_mkConnectionGetPut,
CAN_FIRE_RL_pixel_engine_buffer_characters_read,
CAN_FIRE_RL_pixel_engine_char_pixels,
CAN_FIRE_RL_pixel_engine_demux_two_chars,
CAN_FIRE_RL_pixel_engine_forward_pixel_values,
CAN_FIRE_RL_pixel_engine_mkConnectionGetPut,
CAN_FIRE_RL_pixel_engine_request_char_values,
CAN_FIRE_RL_pixel_engine_request_pixel_values,
CAN_FIRE_RL_receive_mem_responses,
CAN_FIRE_RL_return_control_register_response,
CAN_FIRE_RL_return_mem_response,
CAN_FIRE_aso_stream_out,
CAN_FIRE_avs_s0,
CAN_FIRE_coe_fsm_d,
CAN_FIRE_coe_touch,
WILL_FIRE_RL_arbitrate_requests,
WILL_FIRE_RL_avalon_request_splitter,
WILL_FIRE_RL_avalon_slave_cancel_ingore_further_requests,
WILL_FIRE_RL_avalon_slave_hanlde_bus_requests,
WILL_FIRE_RL_avalon_slave_wire_up_avalonwait,
WILL_FIRE_RL_forward_upper_bytes,
WILL_FIRE_RL_mem_forward_requests_flash,
WILL_FIRE_RL_mem_forward_requests_ssram,
WILL_FIRE_RL_mem_pipe_stage_0,
WILL_FIRE_RL_mem_pipe_stage_1,
WILL_FIRE_RL_mem_pipe_stage_2,
WILL_FIRE_RL_mkConnectionGetPut,
WILL_FIRE_RL_pixel_engine_buffer_characters_read,
WILL_FIRE_RL_pixel_engine_char_pixels,
WILL_FIRE_RL_pixel_engine_demux_two_chars,
WILL_FIRE_RL_pixel_engine_forward_pixel_values,
WILL_FIRE_RL_pixel_engine_mkConnectionGetPut,
WILL_FIRE_RL_pixel_engine_request_char_values,
WILL_FIRE_RL_pixel_engine_request_pixel_values,
WILL_FIRE_RL_receive_mem_responses,
WILL_FIRE_RL_return_control_register_response,
WILL_FIRE_RL_return_mem_response,
WILL_FIRE_aso_stream_out,
WILL_FIRE_avs_s0,
WILL_FIRE_coe_fsm_d,
WILL_FIRE_coe_touch;
// inputs to muxes for submodule ports
wire [61 : 0] MUX_pixel_engine_ssram_req$enq_1__VAL_1,
MUX_pixel_engine_ssram_req$enq_1__VAL_2;
wire [44 : 0] MUX_mem_req$enq_1__VAL_1;
wire [16 : 0] MUX_mem_resp$enq_1__VAL_1, MUX_mem_resp$enq_1__VAL_2;
wire [15 : 0] MUX_mem_fsm_dout_dw$wset_1__VAL_2;
wire MUX_avalon_slave_datareturned$wset_1__SEL_1,
MUX_mem_fsm_a_w$wset_1__SEL_1,
MUX_mem_resp$enq_1__SEL_1;
// remaining internal signals
reg [23 : 0] IF_pixel_engine_char_pixel_first__16_BITS_4_TO_ETC___d654,
IF_pixel_engine_char_pixel_first__16_BITS_7_TO_ETC___d655,
IF_pixel_engine_fb_blend_0_BITS_27_TO_24_1_EQ__ETC___d652;
wire [49 : 0] IF_pixel_engine_char_x_two_char_5_EQ_49_0_THEN_ETC___d55;
wire [31 : 0] IF_avalon_slave_outbuf_first__89_BITS_53_TO_36_ETC___d452,
IF_avalon_slave_outbuf_first__89_BITS_53_TO_36_ETC___d453,
IF_avalon_slave_outbuf_first__89_BITS_53_TO_36_ETC___d454,
IF_avalon_slave_outbuf_first__89_BITS_53_TO_36_ETC___d455,
IF_avalon_slave_outbuf_first__89_BITS_53_TO_36_ETC___d456,
IF_avalon_slave_outbuf_first__89_BITS_53_TO_36_ETC___d458,
IF_pixel_engine_req_i_notEmpty__75_THEN_pixel__ETC___d669,
b__h14135;
wire [25 : 0] x__h13071, x_addr__h13123;
wire [24 : 0] IF_pixel_engine_font_y_4_EQ_11_3_THEN_IF_pixel_ETC___d645,
next_addr__h3065,
next_char_y___2__h3016,
next_char_y__h2903,
x1_avValue_addr__h12990,
x__h3050,
y__h3053;
wire [8 : 0] minus__h3867,
minus__h4723,
minus__h5121,
minus__h5335,
minus__h5712,
minus__h5926,
sum__h3311,
sum__h3767,
sum__h4866,
sum__h5021,
sum__h5457,
sum__h5612;
wire [7 : 0] a__h3765,
a__h3866,
a__h5019,
a__h5120,
a__h5610,
a__h5711,
b__h3310,
b__h3766,
b__h4865,
b__h5020,
b__h5456,
b__h5611,
bitmap_col_chan_b__h3300,
bitmap_col_chan_g__h3299,
bitmap_col_chan_r__h3298,
char__h6798,
char_alpha__h3227,
x__h2840,
x__h7183;
wire [5 : 0] next_x_two_char_addr__h2897, next_x_two_char_addr__h2901;
wire [3 : 0] IF_pixel_engine_req_i_notEmpty__75_THEN_pixel__ETC___d668,
next_font_y___2__h2969;
wire [2 : 0] x__h7767;
wire [1 : 0] IF_mem_ssram_byteenable_w_whas__65_THEN_mem_ss_ETC___d710;
wire IF_pixel_engine_req_i_notEmpty__75_THEN_pixel__ETC___d621,
NOT_coe_touch_x1_EQ_prev_touch_info_92_BITS_47_ETC___d611,
mem_req_i_notEmpty__24_AND_IF_mem_req_first__2_ETC___d345,
pixel_engine_char_pixel_first__16_BIT_9_17_AND_ETC___d706,
response_for_avalon_i_notEmpty__24_AND_IF_resp_ETC___d529,
x__h7731;
// action method avs_s0
assign CAN_FIRE_avs_s0 = 1'd1 ;
assign WILL_FIRE_avs_s0 = 1'd1 ;
// value method avs_s0_readdata
assign avs_s0_readdata =
avalon_slave_avalonwait_end_read$whas ?
b__h14135 :
32'hDEADDEAD ;
// value method avs_s0_waitrequest
assign avs_s0_waitrequest =
avs_s0_read && !avalon_slave_avalonwait_end_read$whas ||
avs_s0_write && !avalon_slave_avalonwait_end_write$whas ;
// value method aso_stream_out_data
assign aso_stream_out_data =
(!CAN_FIRE_RL_pixel_engine_forward_pixel_values ||
!pixel_engine_lcd_stream_data_dw$wget[24]) ?
24'd0 :
pixel_engine_lcd_stream_data_dw$wget[23:0] ;
// value method aso_stream_out_valid
assign aso_stream_out_valid =
CAN_FIRE_RL_pixel_engine_forward_pixel_values &&
pixel_engine_lcd_stream_data_dw$wget[24] ;
// action method aso_stream_out
assign CAN_FIRE_aso_stream_out = 1'd1 ;
assign WILL_FIRE_aso_stream_out = 1'd1 ;
// value method aso_stream_out_startofpacket
assign aso_stream_out_startofpacket =
CAN_FIRE_RL_pixel_engine_forward_pixel_values &&
pixel_engine_pixpos$D_OUT[1] ;
// value method aso_stream_out_endofpacket
assign aso_stream_out_endofpacket =
CAN_FIRE_RL_pixel_engine_forward_pixel_values &&
pixel_engine_pixpos$D_OUT[0] ;
// value method coe_ssram_adv
assign coe_ssram_adv = 1'd0 ;
// value method coe_ssram_bwa_n
assign coe_ssram_bwa_n =
!IF_mem_ssram_byteenable_w_whas__65_THEN_mem_ss_ETC___d710[0] ;
// value method coe_ssram_bwb_n
assign coe_ssram_bwb_n =
!IF_mem_ssram_byteenable_w_whas__65_THEN_mem_ss_ETC___d710[1] ;
// value method coe_ssram_ce_n
assign coe_ssram_ce_n = !mem_ssram_ce_pw$whas ;
// value method coe_ssram_cke_n
assign coe_ssram_cke_n = 1'd0 ;
// value method coe_ssram_oe_n
assign coe_ssram_oe_n = mem_fsm_dout_dw$whas && mem_fsm_dout_req_dw$wget ;
// value method coe_ssram_we_n
assign coe_ssram_we_n =
!CAN_FIRE_RL_mem_forward_requests_ssram || !mem_req$D_OUT[44] ;
// value method coe_fsm_a
assign coe_fsm_a = mem_fsm_a_w$whas ? mem_req$D_OUT[40:16] : 25'd0 ;
// value method coe_fsm_d_out
assign coe_fsm_d_out =
mem_fsm_dout_dw$whas ? mem_fsm_dout_dw$wget : 16'hDEAD ;
// action method coe_fsm_d
assign CAN_FIRE_coe_fsm_d = 1'd1 ;
assign WILL_FIRE_coe_fsm_d = 1'd1 ;
// value method coe_fsm_dout_req
assign coe_fsm_dout_req = mem_fsm_dout_dw$whas && mem_fsm_dout_req_dw$wget ;
// value method coe_flash_adv_n
assign coe_flash_adv_n = !MUX_mem_fsm_a_w$wset_1__SEL_1 ;
// value method coe_flash_ce_n
assign coe_flash_ce_n =
!MUX_mem_fsm_a_w$wset_1__SEL_1 || mem_flash_ce_n_dw$wget ;
// value method coe_flash_clk
assign coe_flash_clk = 1'd0 ;
// value method coe_flash_oe_n
assign coe_flash_oe_n =
!MUX_mem_fsm_a_w$wset_1__SEL_1 || mem_req$D_OUT[44] ;
// value method coe_flash_we_n
assign coe_flash_we_n =
!MUX_mem_fsm_a_w$wset_1__SEL_1 || mem_flash_we_n_dw$wget ;
// action method coe_touch
assign CAN_FIRE_coe_touch = 1'd1 ;
assign WILL_FIRE_coe_touch = 1'd1 ;
// submodule avalon_control_reg_resp
FIFO1 #(.width(32'd33),
.guarded(32'd1)) avalon_control_reg_resp(.RST_N(csi_clockreset_reset_n),
.CLK(csi_clockreset_clk),
.D_IN(avalon_control_reg_resp$D_IN),
.ENQ(avalon_control_reg_resp$ENQ),
.DEQ(avalon_control_reg_resp$DEQ),
.CLR(avalon_control_reg_resp$CLR),
.D_OUT(avalon_control_reg_resp$D_OUT),
.FULL_N(avalon_control_reg_resp$FULL_N),
.EMPTY_N(avalon_control_reg_resp$EMPTY_N));
// submodule avalon_mem_resp
FIFO1 #(.width(32'd33),
.guarded(32'd1)) avalon_mem_resp(.RST_N(csi_clockreset_reset_n),
.CLK(csi_clockreset_clk),
.D_IN(avalon_mem_resp$D_IN),
.ENQ(avalon_mem_resp$ENQ),
.DEQ(avalon_mem_resp$DEQ),
.CLR(avalon_mem_resp$CLR),
.D_OUT(avalon_mem_resp$D_OUT),
.FULL_N(avalon_mem_resp$FULL_N),
.EMPTY_N(avalon_mem_resp$EMPTY_N));
// submodule avalon_req
FIFO2 #(.width(32'd62),
.guarded(32'd1)) avalon_req(.RST_N(csi_clockreset_reset_n),
.CLK(csi_clockreset_clk),
.D_IN(avalon_req$D_IN),
.ENQ(avalon_req$ENQ),
.DEQ(avalon_req$DEQ),
.CLR(avalon_req$CLR),
.D_OUT(avalon_req$D_OUT),
.FULL_N(avalon_req$FULL_N),
.EMPTY_N(avalon_req$EMPTY_N));
// submodule avalon_slave_outbuf
FIFO2 #(.width(32'd63),
.guarded(32'd1)) avalon_slave_outbuf(.RST_N(csi_clockreset_reset_n),
.CLK(csi_clockreset_clk),
.D_IN(avalon_slave_outbuf$D_IN),
.ENQ(avalon_slave_outbuf$ENQ),
.DEQ(avalon_slave_outbuf$DEQ),
.CLR(avalon_slave_outbuf$CLR),
.D_OUT(avalon_slave_outbuf$D_OUT),
.FULL_N(avalon_slave_outbuf$FULL_N),
.EMPTY_N(avalon_slave_outbuf$EMPTY_N));
// submodule lower_16b_returned
FIFO2 #(.width(32'd17),
.guarded(32'd0)) lower_16b_returned(.RST_N(csi_clockreset_reset_n),
.CLK(csi_clockreset_clk),
.D_IN(lower_16b_returned$D_IN),
.ENQ(lower_16b_returned$ENQ),
.DEQ(lower_16b_returned$DEQ),
.CLR(lower_16b_returned$CLR),
.D_OUT(lower_16b_returned$D_OUT),
.FULL_N(),
.EMPTY_N(lower_16b_returned$EMPTY_N));
// submodule mem_pipe0
FIFOL1 #(.width(32'd17)) mem_pipe0(.RST_N(csi_clockreset_reset_n),
.CLK(csi_clockreset_clk),
.D_IN(mem_pipe0$D_IN),
.ENQ(mem_pipe0$ENQ),
.DEQ(mem_pipe0$DEQ),
.CLR(mem_pipe0$CLR),
.D_OUT(mem_pipe0$D_OUT),
.FULL_N(mem_pipe0$FULL_N),
.EMPTY_N(mem_pipe0$EMPTY_N));
// submodule mem_pipe1
FIFOL1 #(.width(32'd17)) mem_pipe1(.RST_N(csi_clockreset_reset_n),
.CLK(csi_clockreset_clk),
.D_IN(mem_pipe1$D_IN),
.ENQ(mem_pipe1$ENQ),
.DEQ(mem_pipe1$DEQ),
.CLR(mem_pipe1$CLR),
.D_OUT(mem_pipe1$D_OUT),
.FULL_N(mem_pipe1$FULL_N),
.EMPTY_N(mem_pipe1$EMPTY_N));
// submodule mem_pipe2
FIFOL1 #(.width(32'd17)) mem_pipe2(.RST_N(csi_clockreset_reset_n),
.CLK(csi_clockreset_clk),
.D_IN(mem_pipe2$D_IN),
.ENQ(mem_pipe2$ENQ),
.DEQ(mem_pipe2$DEQ),
.CLR(mem_pipe2$CLR),
.D_OUT(mem_pipe2$D_OUT),
.FULL_N(mem_pipe2$FULL_N),
.EMPTY_N(mem_pipe2$EMPTY_N));
// submodule mem_req
FIFOL1 #(.width(32'd45)) mem_req(.RST_N(csi_clockreset_reset_n),
.CLK(csi_clockreset_clk),
.D_IN(mem_req$D_IN),
.ENQ(mem_req$ENQ),
.DEQ(mem_req$DEQ),
.CLR(mem_req$CLR),
.D_OUT(mem_req$D_OUT),
.FULL_N(mem_req$FULL_N),
.EMPTY_N(mem_req$EMPTY_N));
// submodule mem_resp
FIFOL1 #(.width(32'd17)) mem_resp(.RST_N(csi_clockreset_reset_n),
.CLK(csi_clockreset_clk),
.D_IN(mem_resp$D_IN),
.ENQ(mem_resp$ENQ),
.DEQ(mem_resp$DEQ),
.CLR(mem_resp$CLR),
.D_OUT(mem_resp$D_OUT),
.FULL_N(mem_resp$FULL_N),
.EMPTY_N(mem_resp$EMPTY_N));
// submodule mem_upper_16b_request
FIFO2 #(.width(32'd45),
.guarded(32'd0)) mem_upper_16b_request(.RST_N(csi_clockreset_reset_n),
.CLK(csi_clockreset_clk),
.D_IN(mem_upper_16b_request$D_IN),
.ENQ(mem_upper_16b_request$ENQ),
.DEQ(mem_upper_16b_request$DEQ),
.CLR(mem_upper_16b_request$CLR),
.D_OUT(mem_upper_16b_request$D_OUT),
.FULL_N(),
.EMPTY_N(mem_upper_16b_request$EMPTY_N));
// submodule pixel_engine_char_colour
FIFO2 #(.width(32'd10),
.guarded(32'd1)) pixel_engine_char_colour(.RST_N(csi_clockreset_reset_n),
.CLK(csi_clockreset_clk),
.D_IN(pixel_engine_char_colour$D_IN),
.ENQ(pixel_engine_char_colour$ENQ),
.DEQ(pixel_engine_char_colour$DEQ),
.CLR(pixel_engine_char_colour$CLR),
.D_OUT(pixel_engine_char_colour$D_OUT),
.FULL_N(pixel_engine_char_colour$FULL_N),
.EMPTY_N(pixel_engine_char_colour$EMPTY_N));
// submodule pixel_engine_char_pixel
FIFO2 #(.width(32'd10),
.guarded(32'd1)) pixel_engine_char_pixel(.RST_N(csi_clockreset_reset_n),
.CLK(csi_clockreset_clk),
.D_IN(pixel_engine_char_pixel$D_IN),
.ENQ(pixel_engine_char_pixel$ENQ),
.DEQ(pixel_engine_char_pixel$DEQ),
.CLR(pixel_engine_char_pixel$CLR),
.D_OUT(pixel_engine_char_pixel$D_OUT),
.FULL_N(pixel_engine_char_pixel$FULL_N),
.EMPTY_N(pixel_engine_char_pixel$EMPTY_N));
// submodule pixel_engine_char_pos
SizedFIFO #(.p1width(32'd16),
.p2depth(32'd4),
.p3cntr_width(32'd2),
.guarded(32'd1)) pixel_engine_char_pos(.RST_N(csi_clockreset_reset_n),
.CLK(csi_clockreset_clk),
.D_IN(pixel_engine_char_pos$D_IN),
.ENQ(pixel_engine_char_pos$ENQ),
.DEQ(pixel_engine_char_pos$DEQ),
.CLR(pixel_engine_char_pos$CLR),
.D_OUT(pixel_engine_char_pos$D_OUT),
.FULL_N(pixel_engine_char_pos$FULL_N),
.EMPTY_N(pixel_engine_char_pos$EMPTY_N));
// submodule pixel_engine_chars_read
SizedFIFO #(.p1width(32'd1),
.p2depth(32'd8),
.p3cntr_width(32'd3),
.guarded(32'd1)) pixel_engine_chars_read(.RST_N(csi_clockreset_reset_n),
.CLK(csi_clockreset_clk),
.D_IN(pixel_engine_chars_read$D_IN),
.ENQ(pixel_engine_chars_read$ENQ),
.DEQ(pixel_engine_chars_read$DEQ),
.CLR(pixel_engine_chars_read$CLR),
.D_OUT(pixel_engine_chars_read$D_OUT),
.FULL_N(pixel_engine_chars_read$FULL_N),
.EMPTY_N(pixel_engine_chars_read$EMPTY_N));
// submodule pixel_engine_font_y_pos
FIFO2 #(.width(32'd4),
.guarded(32'd1)) pixel_engine_font_y_pos(.RST_N(csi_clockreset_reset_n),
.CLK(csi_clockreset_clk),
.D_IN(pixel_engine_font_y_pos$D_IN),
.ENQ(pixel_engine_font_y_pos$ENQ),
.DEQ(pixel_engine_font_y_pos$DEQ),
.CLR(pixel_engine_font_y_pos$CLR),
.D_OUT(pixel_engine_font_y_pos$D_OUT),
.FULL_N(pixel_engine_font_y_pos$FULL_N),
.EMPTY_N(pixel_engine_font_y_pos$EMPTY_N));
// submodule pixel_engine_fontbits
FIFO2 #(.width(32'd8),
.guarded(32'd1)) pixel_engine_fontbits(.RST_N(csi_clockreset_reset_n),
.CLK(csi_clockreset_clk),
.D_IN(pixel_engine_fontbits$D_IN),
.ENQ(pixel_engine_fontbits$ENQ),
.DEQ(pixel_engine_fontbits$DEQ),
.CLR(pixel_engine_fontbits$CLR),
.D_OUT(pixel_engine_fontbits$D_OUT),
.FULL_N(pixel_engine_fontbits$FULL_N),
.EMPTY_N(pixel_engine_fontbits$EMPTY_N));
// submodule pixel_engine_fontrom_rom
VerilogAlteraROM #(.FILENAME("vgafontrom.mif"),
.ADDRESS_WIDTH(32'd12),
.DATA_WIDTH(32'd8)) pixel_engine_fontrom_rom(.clk(csi_clockreset_clk),
.v_addr(pixel_engine_fontrom_rom$v_addr),
.v_en(pixel_engine_fontrom_rom$v_en),
.v_data(pixel_engine_fontrom_rom$v_data));
// submodule pixel_engine_fontrom_seq_fifo
FIFO1 #(.width(32'd1),
.guarded(32'd1)) pixel_engine_fontrom_seq_fifo(.RST_N(csi_clockreset_reset_n),
.CLK(csi_clockreset_clk),
.D_IN(pixel_engine_fontrom_seq_fifo$D_IN),
.ENQ(pixel_engine_fontrom_seq_fifo$ENQ),
.DEQ(pixel_engine_fontrom_seq_fifo$DEQ),
.CLR(pixel_engine_fontrom_seq_fifo$CLR),
.D_OUT(),
.FULL_N(pixel_engine_fontrom_seq_fifo$FULL_N),
.EMPTY_N(pixel_engine_fontrom_seq_fifo$EMPTY_N));
// submodule pixel_engine_pixpos
SizedFIFO #(.p1width(32'd2),
.p2depth(32'd8),
.p3cntr_width(32'd3),
.guarded(32'd1)) pixel_engine_pixpos(.RST_N(csi_clockreset_reset_n),
.CLK(csi_clockreset_clk),
.D_IN(pixel_engine_pixpos$D_IN),
.ENQ(pixel_engine_pixpos$ENQ),
.DEQ(pixel_engine_pixpos$DEQ),
.CLR(pixel_engine_pixpos$CLR),
.D_OUT(pixel_engine_pixpos$D_OUT),
.FULL_N(pixel_engine_pixpos$FULL_N),
.EMPTY_N(pixel_engine_pixpos$EMPTY_N));
// submodule pixel_engine_req
FIFO2 #(.width(32'd62),
.guarded(32'd1)) pixel_engine_req(.RST_N(csi_clockreset_reset_n),
.CLK(csi_clockreset_clk),
.D_IN(pixel_engine_req$D_IN),
.ENQ(pixel_engine_req$ENQ),
.DEQ(pixel_engine_req$DEQ),
.CLR(pixel_engine_req$CLR),
.D_OUT(pixel_engine_req$D_OUT),
.FULL_N(pixel_engine_req$FULL_N),
.EMPTY_N(pixel_engine_req$EMPTY_N));
// submodule pixel_engine_ssram_req
FIFOL1 #(.width(32'd62)) pixel_engine_ssram_req(.RST_N(csi_clockreset_reset_n),
.CLK(csi_clockreset_clk),
.D_IN(pixel_engine_ssram_req$D_IN),
.ENQ(pixel_engine_ssram_req$ENQ),
.DEQ(pixel_engine_ssram_req$DEQ),
.CLR(pixel_engine_ssram_req$CLR),
.D_OUT(pixel_engine_ssram_req$D_OUT),
.FULL_N(pixel_engine_ssram_req$FULL_N),
.EMPTY_N(pixel_engine_ssram_req$EMPTY_N));
// submodule pixel_engine_ssram_resp
SizedFIFO #(.p1width(32'd32),
.p2depth(32'd8),
.p3cntr_width(32'd3),
.guarded(32'd1)) pixel_engine_ssram_resp(.RST_N(csi_clockreset_reset_n),
.CLK(csi_clockreset_clk),
.D_IN(pixel_engine_ssram_resp$D_IN),
.ENQ(pixel_engine_ssram_resp$ENQ),
.DEQ(pixel_engine_ssram_resp$DEQ),
.CLR(pixel_engine_ssram_resp$CLR),
.D_OUT(pixel_engine_ssram_resp$D_OUT),
.FULL_N(pixel_engine_ssram_resp$FULL_N),
.EMPTY_N(pixel_engine_ssram_resp$EMPTY_N));
// submodule pixel_engine_two_chars
FIFO2 #(.width(32'd32),
.guarded(32'd1)) pixel_engine_two_chars(.RST_N(csi_clockreset_reset_n),
.CLK(csi_clockreset_clk),
.D_IN(pixel_engine_two_chars$D_IN),
.ENQ(pixel_engine_two_chars$ENQ),
.DEQ(pixel_engine_two_chars$DEQ),
.CLR(pixel_engine_two_chars$CLR),
.D_OUT(pixel_engine_two_chars$D_OUT),
.FULL_N(pixel_engine_two_chars$FULL_N),
.EMPTY_N(pixel_engine_two_chars$EMPTY_N));
// submodule response_for_avalon
SizedFIFO #(.p1width(32'd1),
.p2depth(32'd8),
.p3cntr_width(32'd3),
.guarded(32'd1)) response_for_avalon(.RST_N(csi_clockreset_reset_n),
.CLK(csi_clockreset_clk),
.D_IN(response_for_avalon$D_IN),
.ENQ(response_for_avalon$ENQ),
.DEQ(response_for_avalon$DEQ),
.CLR(response_for_avalon$CLR),
.D_OUT(response_for_avalon$D_OUT),
.FULL_N(response_for_avalon$FULL_N),
.EMPTY_N(response_for_avalon$EMPTY_N));
// submodule touch
FIFO2 #(.width(32'd48),
.guarded(32'd0)) touch(.RST_N(csi_clockreset_reset_n),
.CLK(csi_clockreset_clk),
.D_IN(touch$D_IN),
.ENQ(touch$ENQ),
.DEQ(touch$DEQ),
.CLR(touch$CLR),
.D_OUT(touch$D_OUT),
.FULL_N(touch$FULL_N),
.EMPTY_N(touch$EMPTY_N));
// rule RL_mkConnectionGetPut
assign CAN_FIRE_RL_mkConnectionGetPut =
pixel_engine_ssram_req$EMPTY_N && pixel_engine_req$FULL_N ;
assign WILL_FIRE_RL_mkConnectionGetPut = CAN_FIRE_RL_mkConnectionGetPut ;
// rule RL_return_control_register_response
assign CAN_FIRE_RL_return_control_register_response =
avalon_control_reg_resp$EMPTY_N && !avalon_mem_resp$EMPTY_N ;
assign WILL_FIRE_RL_return_control_register_response =
CAN_FIRE_RL_return_control_register_response ;
// rule RL_return_mem_response
assign CAN_FIRE_RL_return_mem_response = avalon_mem_resp$EMPTY_N ;
assign WILL_FIRE_RL_return_mem_response = avalon_mem_resp$EMPTY_N ;
// rule RL_receive_mem_responses
assign CAN_FIRE_RL_receive_mem_responses =
mem_resp$EMPTY_N &&
(!lower_16b_returned$EMPTY_N ||
response_for_avalon_i_notEmpty__24_AND_IF_resp_ETC___d529) ;
assign WILL_FIRE_RL_receive_mem_responses =
CAN_FIRE_RL_receive_mem_responses ;
// rule RL_avalon_slave_hanlde_bus_requests
assign CAN_FIRE_RL_avalon_slave_hanlde_bus_requests =
avalon_slave_outbuf$FULL_N && (avs_s0_read || avs_s0_write) &&
!avalon_slave_ignore_further_requests ;
assign WILL_FIRE_RL_avalon_slave_hanlde_bus_requests =
CAN_FIRE_RL_avalon_slave_hanlde_bus_requests ;
// rule RL_avalon_slave_wire_up_avalonwait
assign CAN_FIRE_RL_avalon_slave_wire_up_avalonwait = 1'd1 ;
assign WILL_FIRE_RL_avalon_slave_wire_up_avalonwait = 1'd1 ;
// rule RL_avalon_slave_cancel_ingore_further_requests
assign CAN_FIRE_RL_avalon_slave_cancel_ingore_further_requests =
!avalon_slave_avalonwait$wget &&
avalon_slave_ignore_further_requests ;
assign WILL_FIRE_RL_avalon_slave_cancel_ingore_further_requests =
CAN_FIRE_RL_avalon_slave_cancel_ingore_further_requests ;
// rule RL_pixel_engine_request_char_values
assign CAN_FIRE_RL_pixel_engine_request_char_values =
pixel_engine_ssram_req$FULL_N &&
pixel_engine_font_y_pos$FULL_N &&
pixel_engine_char_pos$FULL_N &&
pixel_engine_chars_read$FULL_N ;
assign WILL_FIRE_RL_pixel_engine_request_char_values =
CAN_FIRE_RL_pixel_engine_request_char_values ;
// rule RL_pixel_engine_request_pixel_values
assign CAN_FIRE_RL_pixel_engine_request_pixel_values =
pixel_engine_ssram_req$FULL_N &&
pixel_engine_chars_read$FULL_N &&
pixel_engine_pixpos$FULL_N ;
assign WILL_FIRE_RL_pixel_engine_request_pixel_values =
CAN_FIRE_RL_pixel_engine_request_pixel_values &&
!WILL_FIRE_RL_pixel_engine_request_char_values ;
// rule RL_pixel_engine_forward_pixel_values
assign CAN_FIRE_RL_pixel_engine_forward_pixel_values =
pixel_engine_chars_read$EMPTY_N && aso_stream_out_ready &&
pixel_engine_char_pixel$EMPTY_N &&
pixel_engine_ssram_resp$EMPTY_N &&
pixel_engine_pixpos$EMPTY_N &&
!pixel_engine_chars_read$D_OUT ;
assign WILL_FIRE_RL_pixel_engine_forward_pixel_values =
CAN_FIRE_RL_pixel_engine_forward_pixel_values ;
// rule RL_pixel_engine_buffer_characters_read
assign CAN_FIRE_RL_pixel_engine_buffer_characters_read =
pixel_engine_chars_read$EMPTY_N &&
pixel_engine_ssram_resp$EMPTY_N &&
pixel_engine_two_chars$FULL_N &&
pixel_engine_chars_read$D_OUT ;
assign WILL_FIRE_RL_pixel_engine_buffer_characters_read =
CAN_FIRE_RL_pixel_engine_buffer_characters_read ;
// rule RL_pixel_engine_mkConnectionGetPut
assign CAN_FIRE_RL_pixel_engine_mkConnectionGetPut =
pixel_engine_fontrom_seq_fifo$EMPTY_N &&
pixel_engine_fontbits$FULL_N ;
assign WILL_FIRE_RL_pixel_engine_mkConnectionGetPut =
CAN_FIRE_RL_pixel_engine_mkConnectionGetPut ;
// rule RL_pixel_engine_demux_two_chars
assign CAN_FIRE_RL_pixel_engine_demux_two_chars =
pixel_engine_two_chars$EMPTY_N &&
pixel_engine_font_y_pos$EMPTY_N &&
pixel_engine_fontrom_seq_fifo$FULL_N &&
pixel_engine_char_colour$FULL_N &&
pixel_engine_char_pos$EMPTY_N ;
assign WILL_FIRE_RL_pixel_engine_demux_two_chars =
CAN_FIRE_RL_pixel_engine_demux_two_chars ;
// rule RL_avalon_request_splitter
assign CAN_FIRE_RL_avalon_request_splitter =
avalon_slave_outbuf$EMPTY_N &&
((avalon_slave_outbuf$D_OUT[60:54] == 7'd4) ?
avalon_control_reg_resp$FULL_N :
avalon_req$FULL_N) ;
assign WILL_FIRE_RL_avalon_request_splitter =
CAN_FIRE_RL_avalon_request_splitter ;
// rule RL_pixel_engine_char_pixels
assign CAN_FIRE_RL_pixel_engine_char_pixels =
pixel_engine_char_pixel$FULL_N &&
pixel_engine_char_colour$EMPTY_N &&
pixel_engine_fontbits$EMPTY_N ;
assign WILL_FIRE_RL_pixel_engine_char_pixels =
CAN_FIRE_RL_pixel_engine_char_pixels ;
// rule RL_mem_pipe_stage_2
assign CAN_FIRE_RL_mem_pipe_stage_2 = mem_resp$FULL_N && mem_pipe2$EMPTY_N ;
assign WILL_FIRE_RL_mem_pipe_stage_2 = CAN_FIRE_RL_mem_pipe_stage_2 ;
// rule RL_mem_pipe_stage_1
assign CAN_FIRE_RL_mem_pipe_stage_1 =
mem_pipe1$EMPTY_N && mem_pipe2$FULL_N ;
assign WILL_FIRE_RL_mem_pipe_stage_1 = CAN_FIRE_RL_mem_pipe_stage_1 ;
// rule RL_mem_pipe_stage_0
assign CAN_FIRE_RL_mem_pipe_stage_0 =
mem_pipe1$FULL_N && mem_pipe0$EMPTY_N ;
assign WILL_FIRE_RL_mem_pipe_stage_0 = CAN_FIRE_RL_mem_pipe_stage_0 ;
// rule RL_mem_forward_requests_ssram
assign CAN_FIRE_RL_mem_forward_requests_ssram =
mem_req$EMPTY_N && mem_pipe0$FULL_N && !mem_req$D_OUT[41] ;
assign WILL_FIRE_RL_mem_forward_requests_ssram =
CAN_FIRE_RL_mem_forward_requests_ssram ;
// rule RL_mem_forward_requests_flash
assign CAN_FIRE_RL_mem_forward_requests_flash =
mem_req_i_notEmpty__24_AND_IF_mem_req_first__2_ETC___d345 &&
mem_req$D_OUT[41] &&
!mem_ssram_ce_pw$whas ;
assign WILL_FIRE_RL_mem_forward_requests_flash =
CAN_FIRE_RL_mem_forward_requests_flash &&
!WILL_FIRE_RL_mem_pipe_stage_1 &&
!WILL_FIRE_RL_mem_pipe_stage_2 ;
// rule RL_arbitrate_requests
assign CAN_FIRE_RL_arbitrate_requests =
response_for_avalon$FULL_N && mem_req$FULL_N &&
!mem_upper_16b_request$EMPTY_N &&
(pixel_engine_req$EMPTY_N || avalon_req$EMPTY_N) ;
assign WILL_FIRE_RL_arbitrate_requests = CAN_FIRE_RL_arbitrate_requests ;
// rule RL_forward_upper_bytes
assign CAN_FIRE_RL_forward_upper_bytes =
mem_req$FULL_N && mem_upper_16b_request$EMPTY_N ;
assign WILL_FIRE_RL_forward_upper_bytes = CAN_FIRE_RL_forward_upper_bytes ;
// inputs to muxes for submodule ports
assign MUX_avalon_slave_datareturned$wset_1__SEL_1 =
avalon_mem_resp$EMPTY_N && avalon_mem_resp$D_OUT[32] ;
assign MUX_mem_fsm_a_w$wset_1__SEL_1 =
WILL_FIRE_RL_mem_forward_requests_flash &&
mem_req$D_OUT[43:42] != 2'b0 ;
assign MUX_mem_resp$enq_1__SEL_1 =
WILL_FIRE_RL_mem_forward_requests_flash &&
(mem_req$D_OUT[43:42] == 2'b0 || mem_flash_timer == 4'd10) ;
assign MUX_mem_fsm_dout_dw$wset_1__VAL_2 =
mem_pipe1$D_OUT[16] ? mem_pipe1$D_OUT[15:0] : 16'hEEEE ;
assign MUX_mem_req$enq_1__VAL_1 =
{ IF_pixel_engine_req_i_notEmpty__75_THEN_pixel__ETC___d621,
IF_pixel_engine_req_i_notEmpty__75_THEN_pixel__ETC___d668[1:0],
x__h13071,
IF_pixel_engine_req_i_notEmpty__75_THEN_pixel__ETC___d669[15:0] } ;
assign MUX_mem_resp$enq_1__VAL_1 =
(mem_req$D_OUT[43:42] == 2'b0) ?
(mem_req$D_OUT[44] ? 17'd43690 : 17'd65536) :
{ !mem_req$D_OUT[44], coe_fsm_d_in } ;
assign MUX_mem_resp$enq_1__VAL_2 = { !mem_pipe2$D_OUT[16], coe_fsm_d_in } ;
assign MUX_pixel_engine_ssram_req$enq_1__VAL_1 =
{ 5'd15, pixel_engine_char_addr, 32'd0 } ;
assign MUX_pixel_engine_ssram_req$enq_1__VAL_2 =
{ 5'd15, pixel_engine_addr, 32'd0 } ;
// inlined wires
assign pixel_engine_lcd_stream_data_dw$wget =
{ 1'd1,
bitmap_col_chan_r__h3298,
bitmap_col_chan_g__h3299,
bitmap_col_chan_b__h3300 } ;
assign mem_fsm_a_w$whas =
WILL_FIRE_RL_mem_forward_requests_flash &&
mem_req$D_OUT[43:42] != 2'b0 ||
WILL_FIRE_RL_mem_forward_requests_ssram ;
assign mem_fsm_dout_dw$wget =
MUX_mem_fsm_a_w$wset_1__SEL_1 ?
mem_req$D_OUT[15:0] :
MUX_mem_fsm_dout_dw$wset_1__VAL_2 ;
assign mem_fsm_dout_dw$whas =
WILL_FIRE_RL_mem_forward_requests_flash &&
mem_req$D_OUT[43:42] != 2'b0 ||
WILL_FIRE_RL_mem_pipe_stage_1 ;
assign mem_fsm_dout_req_dw$wget =
MUX_mem_fsm_a_w$wset_1__SEL_1 ?
mem_req$D_OUT[44] :
mem_pipe1$D_OUT[16] ;
assign mem_flash_ce_n_dw$wget =
mem_req$D_OUT[44] && mem_flash_timer == 4'd10 ;
assign mem_flash_we_n_dw$wget =
!mem_req$D_OUT[44] || mem_flash_timer == 4'd10 ||
mem_flash_timer == 4'd9 ;
assign avalon_slave_avalonwait_end_read$whas =
avalon_mem_resp$EMPTY_N && avalon_mem_resp$D_OUT[32] ||
WILL_FIRE_RL_return_control_register_response &&
avalon_control_reg_resp$D_OUT[32] ;
assign avalon_slave_avalonwait_end_write$whas =
WILL_FIRE_RL_avalon_slave_hanlde_bus_requests && avs_s0_write ;
assign mem_ssram_ce_pw$whas =
WILL_FIRE_RL_mem_pipe_stage_2 || WILL_FIRE_RL_mem_pipe_stage_1 ||
WILL_FIRE_RL_mem_pipe_stage_0 ||
WILL_FIRE_RL_mem_forward_requests_ssram ;
assign avalon_slave_avalonwait$wget =
avs_s0_read && !avalon_slave_avalonwait_end_read$whas ||
avs_s0_write && !avalon_slave_avalonwait_end_write$whas ;
// register avalon_slave_ignore_further_requests
assign avalon_slave_ignore_further_requests$D_IN =
WILL_FIRE_RL_avalon_slave_hanlde_bus_requests && avs_s0_read ;
assign avalon_slave_ignore_further_requests$EN =
WILL_FIRE_RL_avalon_slave_hanlde_bus_requests ||
WILL_FIRE_RL_avalon_slave_cancel_ingore_further_requests ;
// register mem_flash_timer
assign mem_flash_timer$D_IN =
(mem_flash_timer == 4'd10) ? 4'd0 : mem_flash_timer + 4'd1 ;
assign mem_flash_timer$EN = MUX_mem_fsm_a_w$wset_1__SEL_1 ;
// register pixel_engine_addr
assign pixel_engine_addr$D_IN =
(pixel_engine_addr == 25'd383999) ? 25'd0 : next_addr__h3065 ;
assign pixel_engine_addr$EN =
WILL_FIRE_RL_pixel_engine_request_pixel_values ;
// register pixel_engine_char_addr
assign pixel_engine_char_addr$D_IN =
x__h3050 +
IF_pixel_engine_char_x_two_char_5_EQ_49_0_THEN_ETC___d55[24:0] ;
assign pixel_engine_char_addr$EN =
CAN_FIRE_RL_pixel_engine_request_char_values ;
// register pixel_engine_char_base
assign pixel_engine_char_base$D_IN = avalon_slave_outbuf$D_OUT[30:6] ;
assign pixel_engine_char_base$EN =
WILL_FIRE_RL_avalon_request_splitter &&
avalon_slave_outbuf$D_OUT[60:54] == 7'd4 &&
avalon_slave_outbuf$D_OUT[53:36] == 18'd2 &&
avalon_slave_outbuf$D_OUT[62:61] == 2'd1 ;
// register pixel_engine_char_ctr
assign pixel_engine_char_ctr$D_IN = pixel_engine_char_ctr + 1'd1 ;
assign pixel_engine_char_ctr$EN = CAN_FIRE_RL_pixel_engine_demux_two_chars ;
// register pixel_engine_char_end
assign pixel_engine_char_end$D_IN =
avalon_slave_outbuf$D_OUT[30:6] + 25'd6000 ;
assign pixel_engine_char_end$EN =
WILL_FIRE_RL_avalon_request_splitter &&
avalon_slave_outbuf$D_OUT[60:54] == 7'd4 &&
avalon_slave_outbuf$D_OUT[53:36] == 18'd2 &&
avalon_slave_outbuf$D_OUT[62:61] == 2'd1 ;
// register pixel_engine_char_x_pos
assign pixel_engine_char_x_pos$D_IN = pixel_engine_char_x_pos + 3'd1 ;
assign pixel_engine_char_x_pos$EN = CAN_FIRE_RL_pixel_engine_char_pixels ;
// register pixel_engine_char_x_two_char
assign pixel_engine_char_x_two_char$D_IN = next_x_two_char_addr__h2901 ;
assign pixel_engine_char_x_two_char$EN =
CAN_FIRE_RL_pixel_engine_request_char_values ;
// register pixel_engine_char_y
assign pixel_engine_char_y$D_IN = next_char_y__h2903 ;
assign pixel_engine_char_y$EN =
CAN_FIRE_RL_pixel_engine_request_char_values ;
// register pixel_engine_cursor_pos
assign pixel_engine_cursor_pos$D_IN = avalon_slave_outbuf$D_OUT[19:4] ;
assign pixel_engine_cursor_pos$EN =
WILL_FIRE_RL_avalon_request_splitter &&
avalon_slave_outbuf$D_OUT[60:54] == 7'd4 &&
avalon_slave_outbuf$D_OUT[53:36] == 18'd1 &&
avalon_slave_outbuf$D_OUT[62:61] == 2'd1 ;
// register pixel_engine_fb_blend
assign pixel_engine_fb_blend$D_IN = avalon_slave_outbuf$D_OUT[35:4] ;
assign pixel_engine_fb_blend$EN =
WILL_FIRE_RL_avalon_request_splitter &&
avalon_slave_outbuf$D_OUT[60:54] == 7'd4 &&
avalon_slave_outbuf$D_OUT[53:36] == 18'd0 &&
avalon_slave_outbuf$D_OUT[62:61] == 2'd1 ;
// register pixel_engine_flash_col
assign pixel_engine_flash_col$D_IN = pixel_engine_flash_col + 6'd1 ;
assign pixel_engine_flash_col$EN =
WILL_FIRE_RL_pixel_engine_forward_pixel_values &&
pixel_engine_pixpos$D_OUT[0] ;
// register pixel_engine_font_y
assign pixel_engine_font_y$D_IN =
(pixel_engine_char_x_two_char == 6'd49) ?
((pixel_engine_font_y == 4'd11) ?
4'd0 :
next_font_y___2__h2969) :
pixel_engine_font_y ;
assign pixel_engine_font_y$EN =
CAN_FIRE_RL_pixel_engine_request_char_values ;
// register prev_touch_info
assign prev_touch_info$D_IN =
{ coe_touch_x1,
coe_touch_y1,
coe_touch_x2,
coe_touch_y2,
coe_touch_count_gesture } ;
assign prev_touch_info$EN =
coe_touch_touch_valid &&
NOT_coe_touch_x1_EQ_prev_touch_info_92_BITS_47_ETC___d611 &&
touch$FULL_N ;
// submodule avalon_control_reg_resp
assign avalon_control_reg_resp$D_IN =
{ avalon_slave_outbuf$D_OUT[62:61] == 2'd0,
(avalon_slave_outbuf$D_OUT[53:36] == 18'd0 &&
avalon_slave_outbuf$D_OUT[62:61] == 2'd0) ?
pixel_engine_fb_blend :
IF_avalon_slave_outbuf_first__89_BITS_53_TO_36_ETC___d458 } ;
assign avalon_control_reg_resp$ENQ =
WILL_FIRE_RL_avalon_request_splitter &&
avalon_slave_outbuf$D_OUT[60:54] == 7'd4 ;
assign avalon_control_reg_resp$DEQ =
CAN_FIRE_RL_return_control_register_response ;
assign avalon_control_reg_resp$CLR = 1'b0 ;
// submodule avalon_mem_resp
assign avalon_mem_resp$D_IN =
{ mem_resp$D_OUT[16] && lower_16b_returned$D_OUT[16],
mem_resp$D_OUT[15:0],
lower_16b_returned$D_OUT[15:0] } ;
assign avalon_mem_resp$ENQ =
WILL_FIRE_RL_receive_mem_responses &&
lower_16b_returned$EMPTY_N &&
response_for_avalon$D_OUT ;
assign avalon_mem_resp$DEQ = avalon_mem_resp$EMPTY_N ;
assign avalon_mem_resp$CLR = 1'b0 ;
// submodule avalon_req
assign avalon_req$D_IN =
{ avalon_slave_outbuf$D_OUT[62:61] == 2'd1,
avalon_slave_outbuf$D_OUT[3:0],
avalon_slave_outbuf$D_OUT[60:4] } ;
assign avalon_req$ENQ =
WILL_FIRE_RL_avalon_request_splitter &&
avalon_slave_outbuf$D_OUT[60:54] != 7'd4 ;
assign avalon_req$DEQ =
WILL_FIRE_RL_arbitrate_requests && !pixel_engine_req$EMPTY_N ;
assign avalon_req$CLR = 1'b0 ;
// submodule avalon_slave_outbuf
assign avalon_slave_outbuf$D_IN =
{ avs_s0_read ? 2'd0 : 2'd1,
avs_s0_address,
avs_s0_writedata,
avs_s0_byteenable } ;
assign avalon_slave_outbuf$ENQ =
CAN_FIRE_RL_avalon_slave_hanlde_bus_requests ;
assign avalon_slave_outbuf$DEQ = CAN_FIRE_RL_avalon_request_splitter ;
assign avalon_slave_outbuf$CLR = 1'b0 ;
// submodule lower_16b_returned
assign lower_16b_returned$D_IN = mem_resp$D_OUT ;
assign lower_16b_returned$ENQ =
WILL_FIRE_RL_receive_mem_responses &&
!lower_16b_returned$EMPTY_N ;
assign lower_16b_returned$DEQ =
WILL_FIRE_RL_receive_mem_responses &&
lower_16b_returned$EMPTY_N ;
assign lower_16b_returned$CLR = 1'b0 ;
// submodule mem_pipe0
assign mem_pipe0$D_IN = { mem_req$D_OUT[44], mem_req$D_OUT[15:0] } ;
assign mem_pipe0$ENQ = CAN_FIRE_RL_mem_forward_requests_ssram ;
assign mem_pipe0$DEQ = CAN_FIRE_RL_mem_pipe_stage_0 ;
assign mem_pipe0$CLR = 1'b0 ;
// submodule mem_pipe1
assign mem_pipe1$D_IN = mem_pipe0$D_OUT ;
assign mem_pipe1$ENQ = CAN_FIRE_RL_mem_pipe_stage_0 ;
assign mem_pipe1$DEQ = CAN_FIRE_RL_mem_pipe_stage_1 ;
assign mem_pipe1$CLR = 1'b0 ;
// submodule mem_pipe2
assign mem_pipe2$D_IN = mem_pipe1$D_OUT ;
assign mem_pipe2$ENQ = CAN_FIRE_RL_mem_pipe_stage_1 ;
assign mem_pipe2$DEQ = CAN_FIRE_RL_mem_pipe_stage_2 ;
assign mem_pipe2$CLR = 1'b0 ;
// submodule mem_req
assign mem_req$D_IN =
WILL_FIRE_RL_arbitrate_requests ?
MUX_mem_req$enq_1__VAL_1 :
mem_upper_16b_request$D_OUT ;
assign mem_req$ENQ =
WILL_FIRE_RL_arbitrate_requests ||
WILL_FIRE_RL_forward_upper_bytes ;
assign mem_req$DEQ =
WILL_FIRE_RL_mem_forward_requests_flash &&
(mem_req$D_OUT[43:42] == 2'b0 || mem_flash_timer == 4'd10) ||
WILL_FIRE_RL_mem_forward_requests_ssram ;
assign mem_req$CLR = 1'b0 ;
// submodule mem_resp
assign mem_resp$D_IN =
MUX_mem_resp$enq_1__SEL_1 ?
MUX_mem_resp$enq_1__VAL_1 :
MUX_mem_resp$enq_1__VAL_2 ;
assign mem_resp$ENQ =
WILL_FIRE_RL_mem_forward_requests_flash &&
(mem_req$D_OUT[43:42] == 2'b0 || mem_flash_timer == 4'd10) ||
WILL_FIRE_RL_mem_pipe_stage_2 ;
assign mem_resp$DEQ = CAN_FIRE_RL_receive_mem_responses ;
assign mem_resp$CLR = 1'b0 ;
// submodule mem_upper_16b_request
assign mem_upper_16b_request$D_IN =
{ IF_pixel_engine_req_i_notEmpty__75_THEN_pixel__ETC___d621,
IF_pixel_engine_req_i_notEmpty__75_THEN_pixel__ETC___d668[3:2],
x_addr__h13123,
IF_pixel_engine_req_i_notEmpty__75_THEN_pixel__ETC___d669[31:16] } ;
assign mem_upper_16b_request$ENQ = CAN_FIRE_RL_arbitrate_requests ;
assign mem_upper_16b_request$DEQ = CAN_FIRE_RL_forward_upper_bytes ;
assign mem_upper_16b_request$CLR = 1'b0 ;
// submodule pixel_engine_char_colour
assign pixel_engine_char_colour$D_IN =
{ x__h7183 == pixel_engine_cursor_pos[15:8] &&
pixel_engine_char_pos$D_OUT[7:0] ==
pixel_engine_cursor_pos[7:0],
pixel_engine_char_ctr ?
pixel_engine_two_chars$D_OUT[31:24] :
pixel_engine_two_chars$D_OUT[15:8],
1'd0 } ;
assign pixel_engine_char_colour$ENQ =
CAN_FIRE_RL_pixel_engine_demux_two_chars ;
assign pixel_engine_char_colour$DEQ =
WILL_FIRE_RL_pixel_engine_char_pixels &&
pixel_engine_char_x_pos == 3'd7 ;
assign pixel_engine_char_colour$CLR = 1'b0 ;
// submodule pixel_engine_char_pixel
assign pixel_engine_char_pixel$D_IN =
{ pixel_engine_char_colour$D_OUT[9:1], x__h7731 } ;
assign pixel_engine_char_pixel$ENQ = CAN_FIRE_RL_pixel_engine_char_pixels ;
assign pixel_engine_char_pixel$DEQ =
CAN_FIRE_RL_pixel_engine_forward_pixel_values ;
assign pixel_engine_char_pixel$CLR = 1'b0 ;
// submodule pixel_engine_char_pos
assign pixel_engine_char_pos$D_IN = { x__h2840, pixel_engine_char_y[7:0] } ;
assign pixel_engine_char_pos$ENQ =
CAN_FIRE_RL_pixel_engine_request_char_values ;
assign pixel_engine_char_pos$DEQ =
WILL_FIRE_RL_pixel_engine_demux_two_chars &&
pixel_engine_char_ctr ;
assign pixel_engine_char_pos$CLR = 1'b0 ;
// submodule pixel_engine_chars_read
assign pixel_engine_chars_read$D_IN =
!WILL_FIRE_RL_pixel_engine_request_pixel_values ;
assign pixel_engine_chars_read$ENQ =
WILL_FIRE_RL_pixel_engine_request_pixel_values ||
WILL_FIRE_RL_pixel_engine_request_char_values ;
assign pixel_engine_chars_read$DEQ =
WILL_FIRE_RL_pixel_engine_buffer_characters_read ||
WILL_FIRE_RL_pixel_engine_forward_pixel_values ;
assign pixel_engine_chars_read$CLR = 1'b0 ;
// submodule pixel_engine_font_y_pos
assign pixel_engine_font_y_pos$D_IN = pixel_engine_font_y ;
assign pixel_engine_font_y_pos$ENQ =
CAN_FIRE_RL_pixel_engine_request_char_values ;
assign pixel_engine_font_y_pos$DEQ =
WILL_FIRE_RL_pixel_engine_demux_two_chars &&
pixel_engine_char_ctr ;
assign pixel_engine_font_y_pos$CLR = 1'b0 ;
// submodule pixel_engine_fontbits
assign pixel_engine_fontbits$D_IN = pixel_engine_fontrom_rom$v_data ;
assign pixel_engine_fontbits$ENQ =
CAN_FIRE_RL_pixel_engine_mkConnectionGetPut ;
assign pixel_engine_fontbits$DEQ =
WILL_FIRE_RL_pixel_engine_char_pixels &&
pixel_engine_char_x_pos == 3'd7 ;
assign pixel_engine_fontbits$CLR = 1'b0 ;
// submodule pixel_engine_fontrom_rom
assign pixel_engine_fontrom_rom$v_addr =
{ char__h6798, pixel_engine_font_y_pos$D_OUT } ;
assign pixel_engine_fontrom_rom$v_en =
CAN_FIRE_RL_pixel_engine_demux_two_chars ;
// submodule pixel_engine_fontrom_seq_fifo
assign pixel_engine_fontrom_seq_fifo$D_IN = 1'd1 ;
assign pixel_engine_fontrom_seq_fifo$ENQ =
CAN_FIRE_RL_pixel_engine_demux_two_chars ;
assign pixel_engine_fontrom_seq_fifo$DEQ =
CAN_FIRE_RL_pixel_engine_mkConnectionGetPut ;
assign pixel_engine_fontrom_seq_fifo$CLR = 1'b0 ;
// submodule pixel_engine_pixpos
assign pixel_engine_pixpos$D_IN =
{ pixel_engine_addr == 25'd0, pixel_engine_addr == 25'd383999 } ;
assign pixel_engine_pixpos$ENQ =
WILL_FIRE_RL_pixel_engine_request_pixel_values ;
assign pixel_engine_pixpos$DEQ =
CAN_FIRE_RL_pixel_engine_forward_pixel_values ;
assign pixel_engine_pixpos$CLR = 1'b0 ;
// submodule pixel_engine_req
assign pixel_engine_req$D_IN = pixel_engine_ssram_req$D_OUT ;
assign pixel_engine_req$ENQ = CAN_FIRE_RL_mkConnectionGetPut ;
assign pixel_engine_req$DEQ =
WILL_FIRE_RL_arbitrate_requests && pixel_engine_req$EMPTY_N ;
assign pixel_engine_req$CLR = 1'b0 ;
// submodule pixel_engine_ssram_req
assign pixel_engine_ssram_req$D_IN =
WILL_FIRE_RL_pixel_engine_request_char_values ?
MUX_pixel_engine_ssram_req$enq_1__VAL_1 :
MUX_pixel_engine_ssram_req$enq_1__VAL_2 ;
assign pixel_engine_ssram_req$ENQ =
WILL_FIRE_RL_pixel_engine_request_char_values ||
WILL_FIRE_RL_pixel_engine_request_pixel_values ;
assign pixel_engine_ssram_req$DEQ = CAN_FIRE_RL_mkConnectionGetPut ;
assign pixel_engine_ssram_req$CLR = 1'b0 ;
// submodule pixel_engine_ssram_resp
assign pixel_engine_ssram_resp$D_IN =
{ mem_resp$D_OUT[15:0], lower_16b_returned$D_OUT[15:0] } ;
assign pixel_engine_ssram_resp$ENQ =
WILL_FIRE_RL_receive_mem_responses &&
lower_16b_returned$EMPTY_N &&
!response_for_avalon$D_OUT ;
assign pixel_engine_ssram_resp$DEQ =
WILL_FIRE_RL_pixel_engine_buffer_characters_read ||
WILL_FIRE_RL_pixel_engine_forward_pixel_values ;
assign pixel_engine_ssram_resp$CLR = 1'b0 ;
// submodule pixel_engine_two_chars
assign pixel_engine_two_chars$D_IN = pixel_engine_ssram_resp$D_OUT ;
assign pixel_engine_two_chars$ENQ =
CAN_FIRE_RL_pixel_engine_buffer_characters_read ;
assign pixel_engine_two_chars$DEQ =
WILL_FIRE_RL_pixel_engine_demux_two_chars &&
pixel_engine_char_ctr ;
assign pixel_engine_two_chars$CLR = 1'b0 ;
// submodule response_for_avalon
assign response_for_avalon$D_IN = !pixel_engine_req$EMPTY_N ;
assign response_for_avalon$ENQ = CAN_FIRE_RL_arbitrate_requests ;
assign response_for_avalon$DEQ =
WILL_FIRE_RL_receive_mem_responses &&
lower_16b_returned$EMPTY_N ;
assign response_for_avalon$CLR = 1'b0 ;
// submodule touch
assign touch$D_IN = prev_touch_info$D_IN ;
assign touch$ENQ =
coe_touch_touch_valid &&
NOT_coe_touch_x1_EQ_prev_touch_info_92_BITS_47_ETC___d611 &&
touch$FULL_N ;
assign touch$DEQ =
WILL_FIRE_RL_avalon_request_splitter &&
avalon_slave_outbuf$D_OUT[60:54] == 7'd4 &&
avalon_slave_outbuf$D_OUT[53:36] == 18'd7 &&
avalon_slave_outbuf$D_OUT[62:61] == 2'd0 ;
assign touch$CLR = 1'b0 ;
// remaining internal signals
assign IF_avalon_slave_outbuf_first__89_BITS_53_TO_36_ETC___d452 =
(avalon_slave_outbuf$D_OUT[53:36] == 18'd7 &&
avalon_slave_outbuf$D_OUT[62:61] == 2'd0) ?
(touch$EMPTY_N ? { 22'd0, touch$D_OUT[9:0] } : 32'hFFFFFFFF) :
32'hFFFFFFFF ;
assign IF_avalon_slave_outbuf_first__89_BITS_53_TO_36_ETC___d453 =
(avalon_slave_outbuf$D_OUT[53:36] == 18'd6 &&
avalon_slave_outbuf$D_OUT[62:61] == 2'd0) ?
(touch$EMPTY_N ?
{ 23'd0, touch$D_OUT[18:10] } :
32'hFFFFFFFF) :
IF_avalon_slave_outbuf_first__89_BITS_53_TO_36_ETC___d452 ;
assign IF_avalon_slave_outbuf_first__89_BITS_53_TO_36_ETC___d454 =
(avalon_slave_outbuf$D_OUT[53:36] == 18'd5 &&
avalon_slave_outbuf$D_OUT[62:61] == 2'd0) ?
(touch$EMPTY_N ?
{ 22'd0, touch$D_OUT[28:19] } :
32'hFFFFFFFF) :
IF_avalon_slave_outbuf_first__89_BITS_53_TO_36_ETC___d453 ;
assign IF_avalon_slave_outbuf_first__89_BITS_53_TO_36_ETC___d455 =
(avalon_slave_outbuf$D_OUT[53:36] == 18'd4 &&
avalon_slave_outbuf$D_OUT[62:61] == 2'd0) ?
(touch$EMPTY_N ?
{ 23'd0, touch$D_OUT[37:29] } :
32'hFFFFFFFF) :
IF_avalon_slave_outbuf_first__89_BITS_53_TO_36_ETC___d454 ;
assign IF_avalon_slave_outbuf_first__89_BITS_53_TO_36_ETC___d456 =
(avalon_slave_outbuf$D_OUT[53:36] == 18'd3 &&
avalon_slave_outbuf$D_OUT[62:61] == 2'd0) ?
(touch$EMPTY_N ?
{ 22'd0, touch$D_OUT[47:38] } :
32'hFFFFFFFF) :
IF_avalon_slave_outbuf_first__89_BITS_53_TO_36_ETC___d455 ;
assign IF_avalon_slave_outbuf_first__89_BITS_53_TO_36_ETC___d458 =
(avalon_slave_outbuf$D_OUT[53:36] == 18'd1 &&
avalon_slave_outbuf$D_OUT[62:61] == 2'd0) ?
{ 16'd0, pixel_engine_cursor_pos } :
((avalon_slave_outbuf$D_OUT[53:36] == 18'd2 &&
avalon_slave_outbuf$D_OUT[62:61] == 2'd0) ?
{ 7'd0, pixel_engine_char_base[22:0], 2'd0 } :
IF_avalon_slave_outbuf_first__89_BITS_53_TO_36_ETC___d456) ;
assign IF_mem_ssram_byteenable_w_whas__65_THEN_mem_ss_ETC___d710 =
CAN_FIRE_RL_mem_forward_requests_ssram ?
mem_req$D_OUT[43:42] :
2'b0 ;
assign IF_pixel_engine_char_x_two_char_5_EQ_49_0_THEN_ETC___d55 =
next_char_y__h2903 * 25'd50 ;
assign IF_pixel_engine_font_y_4_EQ_11_3_THEN_IF_pixel_ETC___d645 =
(pixel_engine_font_y == 4'd11) ?
((pixel_engine_char_y == 25'd39) ?
25'd0 :
next_char_y___2__h3016) :
pixel_engine_char_y ;
assign IF_pixel_engine_req_i_notEmpty__75_THEN_pixel__ETC___d621 =
pixel_engine_req$EMPTY_N ?
pixel_engine_req$D_OUT[61] :
avalon_req$D_OUT[61] ;
assign IF_pixel_engine_req_i_notEmpty__75_THEN_pixel__ETC___d668 =
pixel_engine_req$EMPTY_N ?
pixel_engine_req$D_OUT[60:57] :
avalon_req$D_OUT[60:57] ;
assign IF_pixel_engine_req_i_notEmpty__75_THEN_pixel__ETC___d669 =
pixel_engine_req$EMPTY_N ?
pixel_engine_req$D_OUT[31:0] :
avalon_req$D_OUT[31:0] ;
assign NOT_coe_touch_x1_EQ_prev_touch_info_92_BITS_47_ETC___d611 =
coe_touch_x1 != prev_touch_info[47:38] ||
coe_touch_y1 != prev_touch_info[37:29] ||
coe_touch_x2 != prev_touch_info[28:19] ||
coe_touch_y2 != prev_touch_info[18:10] ||
coe_touch_count_gesture != prev_touch_info[9:0] ;
assign a__h3765 = minus__h3867[8] ? 8'd0 : minus__h3867[7:0] ;
assign a__h3866 =
pixel_engine_char_pixel_first__16_BIT_9_17_AND_ETC___d706 ?
IF_pixel_engine_char_pixel_first__16_BITS_7_TO_ETC___d655[23:16] :
IF_pixel_engine_char_pixel_first__16_BITS_4_TO_ETC___d654[23:16] ;
assign a__h5019 = minus__h5121[8] ? 8'd0 : minus__h5121[7:0] ;
assign a__h5120 =
pixel_engine_char_pixel_first__16_BIT_9_17_AND_ETC___d706 ?
IF_pixel_engine_char_pixel_first__16_BITS_7_TO_ETC___d655[15:8] :
IF_pixel_engine_char_pixel_first__16_BITS_4_TO_ETC___d654[15:8] ;
assign a__h5610 = minus__h5712[8] ? 8'd0 : minus__h5712[7:0] ;
assign a__h5711 =
pixel_engine_char_pixel_first__16_BIT_9_17_AND_ETC___d706 ?
IF_pixel_engine_char_pixel_first__16_BITS_7_TO_ETC___d655[7:0] :
IF_pixel_engine_char_pixel_first__16_BITS_4_TO_ETC___d654[7:0] ;
assign b__h14135 =
MUX_avalon_slave_datareturned$wset_1__SEL_1 ?
avalon_mem_resp$D_OUT[31:0] :
avalon_control_reg_resp$D_OUT[31:0] ;
assign b__h3310 = sum__h3767[8] ? 8'hFF : sum__h3767[7:0] ;
assign b__h3766 = minus__h4723[8] ? 8'd0 : minus__h4723[7:0] ;
assign b__h4865 = sum__h5021[8] ? 8'hFF : sum__h5021[7:0] ;
assign b__h5020 = minus__h5335[8] ? 8'd0 : minus__h5335[7:0] ;
assign b__h5456 = sum__h5612[8] ? 8'hFF : sum__h5612[7:0] ;
assign b__h5611 = minus__h5926[8] ? 8'd0 : minus__h5926[7:0] ;
assign bitmap_col_chan_b__h3300 = sum__h5457[8] ? 8'hFF : sum__h5457[7:0] ;
assign bitmap_col_chan_g__h3299 = sum__h4866[8] ? 8'hFF : sum__h4866[7:0] ;
assign bitmap_col_chan_r__h3298 = sum__h3311[8] ? 8'hFF : sum__h3311[7:0] ;
assign char__h6798 =
pixel_engine_char_ctr ?
pixel_engine_two_chars$D_OUT[23:16] :
pixel_engine_two_chars$D_OUT[7:0] ;
assign char_alpha__h3227 =
pixel_engine_char_pixel_first__16_BIT_9_17_AND_ETC___d706 ?
pixel_engine_fb_blend[7:0] :
pixel_engine_fb_blend[15:8] ;
assign mem_req_i_notEmpty__24_AND_IF_mem_req_first__2_ETC___d345 =
mem_req$EMPTY_N &&
((mem_req$D_OUT[43:42] == 2'b0) ?
mem_resp$FULL_N :
mem_flash_timer != 4'd10 || mem_resp$FULL_N) ;
assign minus__h3867 =
{ 1'd0, a__h3866 } - { 1'd0, pixel_engine_fb_blend[23:16] } ;
assign minus__h4723 =
{ 1'd0, pixel_engine_ssram_resp$D_OUT[23:16] } -
{ 1'd0, char_alpha__h3227 } ;
assign minus__h5121 =
{ 1'd0, a__h5120 } - { 1'd0, pixel_engine_fb_blend[23:16] } ;
assign minus__h5335 =
{ 1'd0, pixel_engine_ssram_resp$D_OUT[15:8] } -
{ 1'd0, char_alpha__h3227 } ;
assign minus__h5712 =
{ 1'd0, a__h5711 } - { 1'd0, pixel_engine_fb_blend[23:16] } ;
assign minus__h5926 =
{ 1'd0, pixel_engine_ssram_resp$D_OUT[7:0] } -
{ 1'd0, char_alpha__h3227 } ;
assign next_addr__h3065 = pixel_engine_addr + 25'd1 ;
assign next_char_y___2__h3016 = pixel_engine_char_y + 25'd1 ;
assign next_char_y__h2903 =
(pixel_engine_char_x_two_char == 6'd49) ?
IF_pixel_engine_font_y_4_EQ_11_3_THEN_IF_pixel_ETC___d645 :
pixel_engine_char_y ;
assign next_font_y___2__h2969 = pixel_engine_font_y + 4'd1 ;
assign next_x_two_char_addr__h2897 = pixel_engine_char_x_two_char + 6'd1 ;
assign next_x_two_char_addr__h2901 =
(pixel_engine_char_x_two_char == 6'd49) ?
6'd0 :
next_x_two_char_addr__h2897 ;
assign pixel_engine_char_pixel_first__16_BIT_9_17_AND_ETC___d706 =
(pixel_engine_char_pixel$D_OUT[9] &&
pixel_engine_flash_col[5]) ==
(pixel_engine_char_pixel$D_OUT[0] &&
(!pixel_engine_char_pixel$D_OUT[8] ||
pixel_engine_flash_col[4])) ;
assign response_for_avalon_i_notEmpty__24_AND_IF_resp_ETC___d529 =
response_for_avalon$EMPTY_N &&
(response_for_avalon$D_OUT ?
avalon_mem_resp$FULL_N :
pixel_engine_ssram_resp$FULL_N) ;
assign sum__h3311 =
{ 1'd0,
IF_pixel_engine_fb_blend_0_BITS_27_TO_24_1_EQ__ETC___d652[23:16] } +
{ 1'd0, b__h3310 } ;
assign sum__h3767 = { 1'd0, a__h3765 } + { 1'd0, b__h3766 } ;
assign sum__h4866 =
{ 1'd0,
IF_pixel_engine_fb_blend_0_BITS_27_TO_24_1_EQ__ETC___d652[15:8] } +
{ 1'd0, b__h4865 } ;
assign sum__h5021 = { 1'd0, a__h5019 } + { 1'd0, b__h5020 } ;
assign sum__h5457 =
{ 1'd0,
IF_pixel_engine_fb_blend_0_BITS_27_TO_24_1_EQ__ETC___d652[7:0] } +
{ 1'd0, b__h5456 } ;
assign sum__h5612 = { 1'd0, a__h5610 } + { 1'd0, b__h5611 } ;
assign x1_avValue_addr__h12990 =
pixel_engine_req$EMPTY_N ?
pixel_engine_req$D_OUT[56:32] :
avalon_req$D_OUT[56:32] ;
assign x__h13071 = { x1_avValue_addr__h12990, 1'b0 } ;
assign x__h2840 = { 1'd0, pixel_engine_char_x_two_char, 1'd0 } ;
assign x__h3050 = pixel_engine_char_base + y__h3053 ;
assign x__h7183 =
pixel_engine_char_pos$D_OUT[15:8] +
{ 7'd0, pixel_engine_char_ctr } ;
assign x__h7731 = pixel_engine_fontbits$D_OUT[x__h7767] ;
assign x__h7767 = 3'd7 - pixel_engine_char_x_pos ;
assign x_addr__h13123 = { x1_avValue_addr__h12990, 1'b1 } ;
assign y__h3053 = { 19'd0, next_x_two_char_addr__h2901 } ;
always@(pixel_engine_fb_blend)
begin
case (pixel_engine_fb_blend[27:24])
4'd0: IF_pixel_engine_fb_blend_0_BITS_27_TO_24_1_EQ__ETC___d652 = 24'h0;
4'd1:
IF_pixel_engine_fb_blend_0_BITS_27_TO_24_1_EQ__ETC___d652 =
24'h0000AA;
4'd2:
IF_pixel_engine_fb_blend_0_BITS_27_TO_24_1_EQ__ETC___d652 =
24'h00AA00;
4'd3:
IF_pixel_engine_fb_blend_0_BITS_27_TO_24_1_EQ__ETC___d652 =
24'h00AAAA;
4'd4:
IF_pixel_engine_fb_blend_0_BITS_27_TO_24_1_EQ__ETC___d652 =
24'hAA0000;
4'd5:
IF_pixel_engine_fb_blend_0_BITS_27_TO_24_1_EQ__ETC___d652 =
24'hAA00AA;
4'd6:
IF_pixel_engine_fb_blend_0_BITS_27_TO_24_1_EQ__ETC___d652 =
24'hAA5500;
4'd7:
IF_pixel_engine_fb_blend_0_BITS_27_TO_24_1_EQ__ETC___d652 =
24'hAAAAAA;
4'd8:
IF_pixel_engine_fb_blend_0_BITS_27_TO_24_1_EQ__ETC___d652 =
24'h555555;
4'd9:
IF_pixel_engine_fb_blend_0_BITS_27_TO_24_1_EQ__ETC___d652 =
24'h5555FF;
4'd10:
IF_pixel_engine_fb_blend_0_BITS_27_TO_24_1_EQ__ETC___d652 =
24'h55FF55;
4'd11:
IF_pixel_engine_fb_blend_0_BITS_27_TO_24_1_EQ__ETC___d652 =
24'h55FFFF;
4'd12:
IF_pixel_engine_fb_blend_0_BITS_27_TO_24_1_EQ__ETC___d652 =
24'hFF5555;
4'd13:
IF_pixel_engine_fb_blend_0_BITS_27_TO_24_1_EQ__ETC___d652 =
24'hFF55FF;
4'd14:
IF_pixel_engine_fb_blend_0_BITS_27_TO_24_1_EQ__ETC___d652 =
24'hFFFF55;
4'd15:
IF_pixel_engine_fb_blend_0_BITS_27_TO_24_1_EQ__ETC___d652 =
24'hFFFFFF;
endcase
end
always@(pixel_engine_char_pixel$D_OUT)
begin
case (pixel_engine_char_pixel$D_OUT[7:5])
3'd0: IF_pixel_engine_char_pixel_first__16_BITS_7_TO_ETC___d655 = 24'h0;
3'd1:
IF_pixel_engine_char_pixel_first__16_BITS_7_TO_ETC___d655 =
24'h0000AA;
3'd2:
IF_pixel_engine_char_pixel_first__16_BITS_7_TO_ETC___d655 =
24'h00AA00;
3'd3:
IF_pixel_engine_char_pixel_first__16_BITS_7_TO_ETC___d655 =
24'h00AAAA;
3'd4:
IF_pixel_engine_char_pixel_first__16_BITS_7_TO_ETC___d655 =
24'hAA0000;
3'd5:
IF_pixel_engine_char_pixel_first__16_BITS_7_TO_ETC___d655 =
24'hAA00AA;
3'd6:
IF_pixel_engine_char_pixel_first__16_BITS_7_TO_ETC___d655 =
24'hAA5500;
3'd7:
IF_pixel_engine_char_pixel_first__16_BITS_7_TO_ETC___d655 =
24'hAAAAAA;
endcase
end
always@(pixel_engine_char_pixel$D_OUT)
begin
case (pixel_engine_char_pixel$D_OUT[4:1])
4'd0: IF_pixel_engine_char_pixel_first__16_BITS_4_TO_ETC___d654 = 24'h0;
4'd1:
IF_pixel_engine_char_pixel_first__16_BITS_4_TO_ETC___d654 =
24'h0000AA;
4'd2:
IF_pixel_engine_char_pixel_first__16_BITS_4_TO_ETC___d654 =
24'h00AA00;
4'd3:
IF_pixel_engine_char_pixel_first__16_BITS_4_TO_ETC___d654 =
24'h00AAAA;
4'd4:
IF_pixel_engine_char_pixel_first__16_BITS_4_TO_ETC___d654 =
24'hAA0000;
4'd5:
IF_pixel_engine_char_pixel_first__16_BITS_4_TO_ETC___d654 =
24'hAA00AA;
4'd6:
IF_pixel_engine_char_pixel_first__16_BITS_4_TO_ETC___d654 =
24'hAA5500;
4'd7:
IF_pixel_engine_char_pixel_first__16_BITS_4_TO_ETC___d654 =
24'hAAAAAA;
4'd8:
IF_pixel_engine_char_pixel_first__16_BITS_4_TO_ETC___d654 =
24'h555555;
4'd9:
IF_pixel_engine_char_pixel_first__16_BITS_4_TO_ETC___d654 =
24'h5555FF;
4'd10:
IF_pixel_engine_char_pixel_first__16_BITS_4_TO_ETC___d654 =
24'h55FF55;
4'd11:
IF_pixel_engine_char_pixel_first__16_BITS_4_TO_ETC___d654 =
24'h55FFFF;
4'd12:
IF_pixel_engine_char_pixel_first__16_BITS_4_TO_ETC___d654 =
24'hFF5555;
4'd13:
IF_pixel_engine_char_pixel_first__16_BITS_4_TO_ETC___d654 =
24'hFF55FF;
4'd14:
IF_pixel_engine_char_pixel_first__16_BITS_4_TO_ETC___d654 =
24'hFFFF55;
4'd15:
IF_pixel_engine_char_pixel_first__16_BITS_4_TO_ETC___d654 =
24'hFFFFFF;
endcase
end
// handling of inlined registers
always@(posedge csi_clockreset_clk)
begin
if (!csi_clockreset_reset_n)
begin
avalon_slave_ignore_further_requests <= `BSV_ASSIGNMENT_DELAY 1'd0;
mem_flash_timer <= `BSV_ASSIGNMENT_DELAY 4'd0;
pixel_engine_addr <= `BSV_ASSIGNMENT_DELAY 25'd0;
pixel_engine_char_addr <= `BSV_ASSIGNMENT_DELAY 25'd384000;
pixel_engine_char_base <= `BSV_ASSIGNMENT_DELAY 25'd384000;
pixel_engine_char_ctr <= `BSV_ASSIGNMENT_DELAY 1'd0;
pixel_engine_char_end <= `BSV_ASSIGNMENT_DELAY 25'd390000;
pixel_engine_char_x_pos <= `BSV_ASSIGNMENT_DELAY 3'd0;
pixel_engine_char_x_two_char <= `BSV_ASSIGNMENT_DELAY 6'd0;
pixel_engine_char_y <= `BSV_ASSIGNMENT_DELAY 25'd0;
pixel_engine_cursor_pos <= `BSV_ASSIGNMENT_DELAY 16'd65535;
pixel_engine_fb_blend <= `BSV_ASSIGNMENT_DELAY 32'd50331647;
pixel_engine_flash_col <= `BSV_ASSIGNMENT_DELAY 6'd0;
pixel_engine_font_y <= `BSV_ASSIGNMENT_DELAY 4'd0;
prev_touch_info <= `BSV_ASSIGNMENT_DELAY 48'hAAAAAAAAAAAA;
end
else
begin
if (avalon_slave_ignore_further_requests$EN)
avalon_slave_ignore_further_requests <= `BSV_ASSIGNMENT_DELAY
avalon_slave_ignore_further_requests$D_IN;
if (mem_flash_timer$EN)
mem_flash_timer <= `BSV_ASSIGNMENT_DELAY mem_flash_timer$D_IN;
if (pixel_engine_addr$EN)
pixel_engine_addr <= `BSV_ASSIGNMENT_DELAY pixel_engine_addr$D_IN;
if (pixel_engine_char_addr$EN)
pixel_engine_char_addr <= `BSV_ASSIGNMENT_DELAY
pixel_engine_char_addr$D_IN;
if (pixel_engine_char_base$EN)
pixel_engine_char_base <= `BSV_ASSIGNMENT_DELAY
pixel_engine_char_base$D_IN;
if (pixel_engine_char_ctr$EN)
pixel_engine_char_ctr <= `BSV_ASSIGNMENT_DELAY
pixel_engine_char_ctr$D_IN;
if (pixel_engine_char_end$EN)
pixel_engine_char_end <= `BSV_ASSIGNMENT_DELAY
pixel_engine_char_end$D_IN;
if (pixel_engine_char_x_pos$EN)
pixel_engine_char_x_pos <= `BSV_ASSIGNMENT_DELAY
pixel_engine_char_x_pos$D_IN;
if (pixel_engine_char_x_two_char$EN)
pixel_engine_char_x_two_char <= `BSV_ASSIGNMENT_DELAY
pixel_engine_char_x_two_char$D_IN;
if (pixel_engine_char_y$EN)
pixel_engine_char_y <= `BSV_ASSIGNMENT_DELAY
pixel_engine_char_y$D_IN;
if (pixel_engine_cursor_pos$EN)
pixel_engine_cursor_pos <= `BSV_ASSIGNMENT_DELAY
pixel_engine_cursor_pos$D_IN;
if (pixel_engine_fb_blend$EN)
pixel_engine_fb_blend <= `BSV_ASSIGNMENT_DELAY
pixel_engine_fb_blend$D_IN;
if (pixel_engine_flash_col$EN)
pixel_engine_flash_col <= `BSV_ASSIGNMENT_DELAY
pixel_engine_flash_col$D_IN;
if (pixel_engine_font_y$EN)
pixel_engine_font_y <= `BSV_ASSIGNMENT_DELAY
pixel_engine_font_y$D_IN;
if (prev_touch_info$EN)
prev_touch_info <= `BSV_ASSIGNMENT_DELAY prev_touch_info$D_IN;
end
end
// synopsys translate_off
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
avalon_slave_ignore_further_requests = 1'h0;
mem_flash_timer = 4'hA;
pixel_engine_addr = 25'h0AAAAAA;
pixel_engine_char_addr = 25'h0AAAAAA;
pixel_engine_char_base = 25'h0AAAAAA;
pixel_engine_char_ctr = 1'h0;
pixel_engine_char_end = 25'h0AAAAAA;
pixel_engine_char_x_pos = 3'h2;
pixel_engine_char_x_two_char = 6'h2A;
pixel_engine_char_y = 25'h0AAAAAA;
pixel_engine_cursor_pos = 16'hAAAA;
pixel_engine_fb_blend = 32'hAAAAAAAA;
pixel_engine_flash_col = 6'h2A;
pixel_engine_font_y = 4'hA;
prev_touch_info = 48'hAAAAAAAAAAAA;
end
`endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on
endmodule // mkMTL_Framebuffer_Flash
|
//
// Generated by Bluespec Compiler, version 2012.07.beta1 (build 29243, 2012-07-26)
//
// On Fri Aug 31 13:45:36 BST 2012
//
// Method conflict info:
// Method: avm_m0
// Conflict-free: avm_irq,
// avm_writedata,
// avm_address,
// avm_read,
// avm_write,
// avm_byteenable,
// debugStreamSink_stream_in,
// debugStreamSink_stream_in_ready,
// debugStreamSource_stream_out_data,
// debugStreamSource_stream_out_valid,
// debugStreamSource_stream_out
// Conflicts: avm_m0
//
// Method: avm_irq
// Conflict-free: avm_m0,
// avm_writedata,
// avm_address,
// avm_read,
// avm_write,
// avm_byteenable,
// debugStreamSink_stream_in,
// debugStreamSink_stream_in_ready,
// debugStreamSource_stream_out_data,
// debugStreamSource_stream_out_valid,
// debugStreamSource_stream_out
// Sequenced before (restricted): avm_irq
//
// Method: avm_writedata
// Conflict-free: avm_m0,
// avm_irq,
// avm_writedata,
// avm_address,
// avm_read,
// avm_write,
// avm_byteenable,
// debugStreamSink_stream_in,
// debugStreamSink_stream_in_ready,
// debugStreamSource_stream_out_data,
// debugStreamSource_stream_out_valid,
// debugStreamSource_stream_out
//
// Method: avm_address
// Conflict-free: avm_m0,
// avm_irq,
// avm_writedata,
// avm_address,
// avm_read,
// avm_write,
// avm_byteenable,
// debugStreamSink_stream_in,
// debugStreamSink_stream_in_ready,
// debugStreamSource_stream_out_data,
// debugStreamSource_stream_out_valid,
// debugStreamSource_stream_out
//
// Method: avm_read
// Conflict-free: avm_m0,
// avm_irq,
// avm_writedata,
// avm_address,
// avm_read,
// avm_write,
// avm_byteenable,
// debugStreamSink_stream_in,
// debugStreamSink_stream_in_ready,
// debugStreamSource_stream_out_data,
// debugStreamSource_stream_out_valid,
// debugStreamSource_stream_out
//
// Method: avm_write
// Conflict-free: avm_m0,
// avm_irq,
// avm_writedata,
// avm_address,
// avm_read,
// avm_write,
// avm_byteenable,
// debugStreamSink_stream_in,
// debugStreamSink_stream_in_ready,
// debugStreamSource_stream_out_data,
// debugStreamSource_stream_out_valid,
// debugStreamSource_stream_out
//
// Method: avm_byteenable
// Conflict-free: avm_m0,
// avm_irq,
// avm_writedata,
// avm_address,
// avm_read,
// avm_write,
// avm_byteenable,
// debugStreamSink_stream_in,
// debugStreamSink_stream_in_ready,
// debugStreamSource_stream_out_data,
// debugStreamSource_stream_out_valid,
// debugStreamSource_stream_out
//
// Method: debugStreamSink_stream_in
// Conflict-free: avm_m0,
// avm_irq,
// avm_writedata,
// avm_address,
// avm_read,
// avm_write,
// avm_byteenable,
// debugStreamSink_stream_in_ready,
// debugStreamSource_stream_out_data,
// debugStreamSource_stream_out_valid,
// debugStreamSource_stream_out
// Conflicts: debugStreamSink_stream_in
//
// Method: debugStreamSink_stream_in_ready
// Conflict-free: avm_m0,
// avm_irq,
// avm_writedata,
// avm_address,
// avm_read,
// avm_write,
// avm_byteenable,
// debugStreamSink_stream_in,
// debugStreamSink_stream_in_ready,
// debugStreamSource_stream_out_data,
// debugStreamSource_stream_out_valid,
// debugStreamSource_stream_out
//
// Method: debugStreamSource_stream_out_data
// Conflict-free: avm_m0,
// avm_irq,
// avm_writedata,
// avm_address,
// avm_read,
// avm_write,
// avm_byteenable,
// debugStreamSink_stream_in,
// debugStreamSink_stream_in_ready,
// debugStreamSource_stream_out_data,
// debugStreamSource_stream_out_valid
// Sequenced after (restricted): debugStreamSource_stream_out
//
// Method: debugStreamSource_stream_out_valid
// Conflict-free: avm_m0,
// avm_irq,
// avm_writedata,
// avm_address,
// avm_read,
// avm_write,
// avm_byteenable,
// debugStreamSink_stream_in,
// debugStreamSink_stream_in_ready,
// debugStreamSource_stream_out_data,
// debugStreamSource_stream_out_valid
// Sequenced after (restricted): debugStreamSource_stream_out
//
// Method: debugStreamSource_stream_out
// Conflict-free: avm_m0,
// avm_irq,
// avm_writedata,
// avm_address,
// avm_read,
// avm_write,
// avm_byteenable,
// debugStreamSink_stream_in,
// debugStreamSink_stream_in_ready
// Sequenced before (restricted): debugStreamSource_stream_out_data,
// debugStreamSource_stream_out_valid
// Conflicts: debugStreamSource_stream_out
//
//
// Ports:
// Name I/O size props
// avm_writedata O 256 reg
// avm_address O 32
// avm_read O 1 reg
// avm_write O 1 reg
// avm_byteenable O 32 reg
// debugStreamSink_stream_in_ready O 1
// debugStreamSource_stream_out_data O 8
// debugStreamSource_stream_out_valid O 1
// csi_clockreset_clk I 1 clock
// csi_clockreset_reset_n I 1 reset
// avm_readdata I 256
// avm_readdatavalid I 1
// avm_waitrequest I 1
// avm_irq_irqs I 5 reg
// debugStreamSink_stream_in_data I 8
// debugStreamSink_stream_in_valid I 1
// debugStreamSource_stream_out_ready I 1
//
// Combinational paths from inputs to outputs:
// debugStreamSource_stream_out_ready -> debugStreamSource_stream_out_data
// debugStreamSource_stream_out_ready -> debugStreamSource_stream_out_valid
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
module mkTopAvalonPhy(csi_clockreset_clk,
csi_clockreset_reset_n,
avm_readdata,
avm_readdatavalid,
avm_waitrequest,
avm_irq_irqs,
avm_writedata,
avm_address,
avm_read,
avm_write,
avm_byteenable,
debugStreamSink_stream_in_data,
debugStreamSink_stream_in_valid,
debugStreamSink_stream_in_ready,
debugStreamSource_stream_out_data,
debugStreamSource_stream_out_valid,
debugStreamSource_stream_out_ready);
input csi_clockreset_clk;
input csi_clockreset_reset_n;
// action method avm_m0
input [255 : 0] avm_readdata;
input avm_readdatavalid;
input avm_waitrequest;
// action method avm_irq
input [4 : 0] avm_irq_irqs;
// value method avm_writedata
output [255 : 0] avm_writedata;
// value method avm_address
output [31 : 0] avm_address;
// value method avm_read
output avm_read;
// value method avm_write
output avm_write;
// value method avm_byteenable
output [31 : 0] avm_byteenable;
// action method debugStreamSink_stream_in
input [7 : 0] debugStreamSink_stream_in_data;
input debugStreamSink_stream_in_valid;
// value method debugStreamSink_stream_in_ready
output debugStreamSink_stream_in_ready;
// value method debugStreamSource_stream_out_data
output [7 : 0] debugStreamSource_stream_out_data;
// value method debugStreamSource_stream_out_valid
output debugStreamSource_stream_out_valid;
// action method debugStreamSource_stream_out
input debugStreamSource_stream_out_ready;
// signals for module outputs
wire [255 : 0] avm_writedata;
wire [31 : 0] avm_address, avm_byteenable;
wire [7 : 0] debugStreamSource_stream_out_data;
wire avm_read,
avm_write,
debugStreamSink_stream_in_ready,
debugStreamSource_stream_out_valid;
// inlined wires
wire [256 : 0] datareturnbuf_rw_enq$wget;
wire [8 : 0] streamIn_d_dw$wget, streamOut_data_dw$wget;
wire signal_read$whas, signal_write$whas, streamOut_data_dw$whas;
// register address_r
reg [26 : 0] address_r;
wire [26 : 0] address_r$D_IN;
wire address_r$EN;
// register byteenable_r
reg [31 : 0] byteenable_r;
wire [31 : 0] byteenable_r$D_IN;
wire byteenable_r$EN;
// register count
reg [15 : 0] count;
wire [15 : 0] count$D_IN;
wire count$EN;
// register datareturnbuf_taggedReg
reg [257 : 0] datareturnbuf_taggedReg;
wire [257 : 0] datareturnbuf_taggedReg$D_IN;
wire datareturnbuf_taggedReg$EN;
// register interrupts
reg [4 : 0] interrupts;
wire [4 : 0] interrupts$D_IN;
wire interrupts$EN;
// register read_r
reg read_r;
wire read_r$D_IN, read_r$EN;
// register write_r
reg write_r;
wire write_r$D_IN, write_r$EN;
// register writedata_r
reg [255 : 0] writedata_r;
wire [255 : 0] writedata_r$D_IN;
wire writedata_r$EN;
// ports of submodule beri
wire [316 : 0] beri$memory_request_get;
wire [255 : 0] beri$memory_response_put;
wire [7 : 0] beri$debugStream_request_put, beri$debugStream_response_get;
wire [4 : 0] beri$putIrqs_interruptLines;
wire beri$EN_debugStream_request_put,
beri$EN_debugStream_response_get,
beri$EN_memory_request_get,
beri$EN_memory_response_put,
beri$EN_putIrqs,
beri$RDY_debugStream_request_put,
beri$RDY_debugStream_response_get,
beri$RDY_memory_request_get,
beri$RDY_memory_response_put;
// ports of submodule pending_acks
wire pending_acks$CLR,
pending_acks$DEQ,
pending_acks$D_IN,
pending_acks$EMPTY_N,
pending_acks$ENQ,
pending_acks$FULL_N;
// ports of submodule perif_reads
wire [2 : 0] perif_reads$D_IN, perif_reads$D_OUT;
wire perif_reads$CLR, perif_reads$DEQ, perif_reads$EMPTY_N, perif_reads$ENQ;
// ports of submodule streamIn_f
wire [7 : 0] streamIn_f$D_IN, streamIn_f$D_OUT;
wire streamIn_f$CLR,
streamIn_f$DEQ,
streamIn_f$EMPTY_N,
streamIn_f$ENQ,
streamIn_f$FULL_N;
// rule scheduling signals
wire WILL_FIRE_RL_buffer_data_read,
WILL_FIRE_RL_datareturnbuf_rule_enq,
WILL_FIRE_RL_getRequest;
// inputs to muxes for submodule ports
wire [257 : 0] MUX_datareturnbuf_taggedReg$write_1__VAL_1;
wire MUX_datareturnbuf_taggedReg$write_1__SEL_2;
// remaining internal signals
wire [255 : 0] v__h1794, v__h1820;
// value method avm_writedata
assign avm_writedata = writedata_r ;
// value method avm_address
assign avm_address = { address_r, 5'b0 } ;
// value method avm_read
assign avm_read = read_r ;
// value method avm_write
assign avm_write = write_r ;
// value method avm_byteenable
assign avm_byteenable = byteenable_r ;
// value method debugStreamSink_stream_in_ready
assign debugStreamSink_stream_in_ready = streamIn_f$FULL_N ;
// value method debugStreamSource_stream_out_data
assign debugStreamSource_stream_out_data = streamOut_data_dw$wget[7:0] ;
// value method debugStreamSource_stream_out_valid
assign debugStreamSource_stream_out_valid =
streamOut_data_dw$whas && streamOut_data_dw$wget[8] ;
// submodule beri
mkMIPSTop beri(.csi_c0_clk(csi_clockreset_clk),
.csi_c0_reset_n(csi_clockreset_reset_n),
.debugStream_request_put(beri$debugStream_request_put),
.memory_response_put(beri$memory_response_put),
.putIrqs_interruptLines(beri$putIrqs_interruptLines),
.EN_memory_request_get(beri$EN_memory_request_get),
.EN_memory_response_put(beri$EN_memory_response_put),
.EN_putIrqs(beri$EN_putIrqs),
.EN_debugStream_request_put(beri$EN_debugStream_request_put),
.EN_debugStream_response_get(beri$EN_debugStream_response_get),
.memory_request_get(beri$memory_request_get),
.RDY_memory_request_get(beri$RDY_memory_request_get),
.RDY_memory_response_put(beri$RDY_memory_response_put),
.RDY_putIrqs(),
.RDY_debugStream_request_put(beri$RDY_debugStream_request_put),
.debugStream_response_get(beri$debugStream_response_get),
.RDY_debugStream_response_get(beri$RDY_debugStream_response_get));
// submodule pending_acks
SizedFIFO #(.p1width(32'd1),
.p2depth(32'd4),
.p3cntr_width(32'd2),
.guarded(32'd1)) pending_acks(.RST_N(csi_clockreset_reset_n),
.CLK(csi_clockreset_clk),
.D_IN(pending_acks$D_IN),
.ENQ(pending_acks$ENQ),
.DEQ(pending_acks$DEQ),
.CLR(pending_acks$CLR),
.D_OUT(),
.FULL_N(pending_acks$FULL_N),
.EMPTY_N(pending_acks$EMPTY_N));
// submodule perif_reads
FIFO2 #(.width(32'd3),
.guarded(32'd0)) perif_reads(.RST_N(csi_clockreset_reset_n),
.CLK(csi_clockreset_clk),
.D_IN(perif_reads$D_IN),
.ENQ(perif_reads$ENQ),
.DEQ(perif_reads$DEQ),
.CLR(perif_reads$CLR),
.D_OUT(perif_reads$D_OUT),
.FULL_N(),
.EMPTY_N(perif_reads$EMPTY_N));
// submodule streamIn_f
FIFOL1 #(.width(32'd8)) streamIn_f(.RST_N(csi_clockreset_reset_n),
.CLK(csi_clockreset_clk),
.D_IN(streamIn_f$D_IN),
.ENQ(streamIn_f$ENQ),
.DEQ(streamIn_f$DEQ),
.CLR(streamIn_f$CLR),
.D_OUT(streamIn_f$D_OUT),
.FULL_N(streamIn_f$FULL_N),
.EMPTY_N(streamIn_f$EMPTY_N));
// rule RL_buffer_data_read
assign WILL_FIRE_RL_buffer_data_read =
!datareturnbuf_taggedReg[257] && avm_readdatavalid ;
// rule RL_getRequest
assign WILL_FIRE_RL_getRequest =
beri$RDY_memory_request_get && pending_acks$FULL_N &&
(!avm_waitrequest || !read_r && !write_r) ;
// rule RL_datareturnbuf_rule_enq
assign WILL_FIRE_RL_datareturnbuf_rule_enq =
WILL_FIRE_RL_buffer_data_read &&
!MUX_datareturnbuf_taggedReg$write_1__SEL_2 ;
// inputs to muxes for submodule ports
assign MUX_datareturnbuf_taggedReg$write_1__SEL_2 =
beri$RDY_memory_response_put &&
(datareturnbuf_taggedReg[257] ||
WILL_FIRE_RL_buffer_data_read) &&
pending_acks$EMPTY_N ;
assign MUX_datareturnbuf_taggedReg$write_1__VAL_1 =
{ 1'd1, datareturnbuf_rw_enq$wget } ;
// inlined wires
assign datareturnbuf_rw_enq$wget =
{ 1'd1, perif_reads$EMPTY_N ? v__h1794 : avm_readdata } ;
assign streamIn_d_dw$wget = { 1'd1, debugStreamSink_stream_in_data } ;
assign streamOut_data_dw$wget = { 1'd1, beri$debugStream_response_get } ;
assign streamOut_data_dw$whas =
beri$RDY_debugStream_response_get &&
debugStreamSource_stream_out_ready ;
assign signal_read$whas =
WILL_FIRE_RL_getRequest && !beri$memory_request_get[316] ;
assign signal_write$whas =
WILL_FIRE_RL_getRequest && beri$memory_request_get[316] ;
// register address_r
assign address_r$D_IN = beri$memory_request_get[315:289] ;
assign address_r$EN = WILL_FIRE_RL_getRequest ;
// register byteenable_r
assign byteenable_r$D_IN = beri$memory_request_get[32:1] ;
assign byteenable_r$EN = WILL_FIRE_RL_getRequest ;
// register count
assign count$D_IN = count + 16'd1 ;
assign count$EN =
WILL_FIRE_RL_buffer_data_read && perif_reads$EMPTY_N &&
perif_reads$D_OUT == 3'd2 ;
// register datareturnbuf_taggedReg
assign datareturnbuf_taggedReg$D_IN =
WILL_FIRE_RL_datareturnbuf_rule_enq ?
MUX_datareturnbuf_taggedReg$write_1__VAL_1 :
258'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA ;
assign datareturnbuf_taggedReg$EN =
WILL_FIRE_RL_datareturnbuf_rule_enq ||
beri$RDY_memory_response_put &&
(datareturnbuf_taggedReg[257] ||
WILL_FIRE_RL_buffer_data_read) &&
pending_acks$EMPTY_N ;
// register interrupts
assign interrupts$D_IN = avm_irq_irqs ;
assign interrupts$EN = 1'd1 ;
// register read_r
assign read_r$D_IN = signal_read$whas ;
assign read_r$EN = signal_read$whas || !avm_waitrequest ;
// register write_r
assign write_r$D_IN = signal_write$whas ;
assign write_r$EN = signal_write$whas || !avm_waitrequest ;
// register writedata_r
assign writedata_r$D_IN = beri$memory_request_get[288:33] ;
assign writedata_r$EN = WILL_FIRE_RL_getRequest ;
// submodule beri
assign beri$debugStream_request_put = streamIn_f$D_OUT ;
assign beri$memory_response_put =
(WILL_FIRE_RL_buffer_data_read ?
!datareturnbuf_rw_enq$wget[256] :
datareturnbuf_taggedReg[257] &&
!datareturnbuf_taggedReg[256]) ?
256'b0 :
(WILL_FIRE_RL_buffer_data_read ?
datareturnbuf_rw_enq$wget[255:0] :
datareturnbuf_taggedReg[255:0]) ;
assign beri$putIrqs_interruptLines = interrupts ;
assign beri$EN_memory_request_get = WILL_FIRE_RL_getRequest ;
assign beri$EN_memory_response_put =
MUX_datareturnbuf_taggedReg$write_1__SEL_2 ;
assign beri$EN_putIrqs = 1'd1 ;
assign beri$EN_debugStream_request_put =
beri$RDY_debugStream_request_put && streamIn_f$EMPTY_N ;
assign beri$EN_debugStream_response_get =
beri$RDY_debugStream_response_get &&
debugStreamSource_stream_out_ready ;
// submodule pending_acks
assign pending_acks$D_IN = 1'd0 ;
assign pending_acks$ENQ = signal_read$whas ;
assign pending_acks$DEQ = MUX_datareturnbuf_taggedReg$write_1__SEL_2 ;
assign pending_acks$CLR = 1'b0 ;
// submodule perif_reads
assign perif_reads$D_IN =
(beri$memory_request_get[315:289] == 27'h3F80200) ? 3'd2 : 3'd5 ;
assign perif_reads$ENQ = signal_read$whas ;
assign perif_reads$DEQ =
WILL_FIRE_RL_buffer_data_read && perif_reads$EMPTY_N ;
assign perif_reads$CLR = 1'b0 ;
// submodule streamIn_f
assign streamIn_f$D_IN = streamIn_d_dw$wget[7:0] ;
assign streamIn_f$ENQ =
streamIn_f$FULL_N && debugStreamSink_stream_in_valid &&
streamIn_d_dw$wget[8] ;
assign streamIn_f$DEQ =
beri$RDY_debugStream_request_put && streamIn_f$EMPTY_N ;
assign streamIn_f$CLR = 1'b0 ;
// remaining internal signals
assign v__h1794 = (perif_reads$D_OUT == 3'd2) ? v__h1820 : avm_readdata ;
assign v__h1820 = { avm_readdata[255:16], count } ;
// handling of inlined registers
always@(posedge csi_clockreset_clk)
begin
if (!csi_clockreset_reset_n)
begin
address_r <= `BSV_ASSIGNMENT_DELAY 27'd0;
byteenable_r <= `BSV_ASSIGNMENT_DELAY 32'hAAAAAAAA;
count <= `BSV_ASSIGNMENT_DELAY 16'd0;
datareturnbuf_taggedReg <= `BSV_ASSIGNMENT_DELAY
258'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
interrupts <= `BSV_ASSIGNMENT_DELAY 5'b0;
read_r <= `BSV_ASSIGNMENT_DELAY 1'd0;
write_r <= `BSV_ASSIGNMENT_DELAY 1'd0;
writedata_r <= `BSV_ASSIGNMENT_DELAY 256'd0;
end
else
begin
if (address_r$EN) address_r <= `BSV_ASSIGNMENT_DELAY address_r$D_IN;
if (byteenable_r$EN)
byteenable_r <= `BSV_ASSIGNMENT_DELAY byteenable_r$D_IN;
if (count$EN) count <= `BSV_ASSIGNMENT_DELAY count$D_IN;
if (datareturnbuf_taggedReg$EN)
datareturnbuf_taggedReg <= `BSV_ASSIGNMENT_DELAY
datareturnbuf_taggedReg$D_IN;
if (interrupts$EN)
interrupts <= `BSV_ASSIGNMENT_DELAY interrupts$D_IN;
if (read_r$EN) read_r <= `BSV_ASSIGNMENT_DELAY read_r$D_IN;
if (write_r$EN) write_r <= `BSV_ASSIGNMENT_DELAY write_r$D_IN;
if (writedata_r$EN)
writedata_r <= `BSV_ASSIGNMENT_DELAY writedata_r$D_IN;
end
end
// synopsys translate_off
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
address_r = 27'h2AAAAAA;
byteenable_r = 32'hAAAAAAAA;
count = 16'hAAAA;
datareturnbuf_taggedReg =
258'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
interrupts = 5'h0A;
read_r = 1'h0;
write_r = 1'h0;
writedata_r =
256'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
end
`endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on
endmodule // mkTopAvalonPhy
|
// (C) 2001-2012 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module rw_manager_ac_ROM_no_ifdef_params (
clock,
data,
rdaddress,
wraddress,
wren,
q);
parameter ROM_INIT_FILE_NAME = "AC_ROM.hex";
input clock;
input [31:0] data;
input [5:0] rdaddress;
input [5:0] wraddress;
input wren;
output [31:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
tri0 wren;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [31:0] sub_wire0;
wire [31:0] q = sub_wire0[31:0];
altsyncram altsyncram_component (
.address_a (wraddress),
.clock0 (clock),
.data_a (data),
.wren_a (wren),
.address_b (rdaddress),
.q_b (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b ({32{1'b1}}),
.eccstatus (),
.q_a (),
//synthesis translate_off
.rden_a (1'b0),
//synthesis translate_on
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_b = "NONE",
altsyncram_component.address_reg_b = "CLOCK0",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
`ifdef NO_PLI
altsyncram_component.init_file = "AC_ROM.rif"
`else
altsyncram_component.init_file = ROM_INIT_FILE_NAME
`endif
,
altsyncram_component.intended_device_family = "Stratix III",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 40,
altsyncram_component.numwords_b = 40,
altsyncram_component.operation_mode = "DUAL_PORT",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_b = "CLOCK0",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.ram_block_type = "MLAB",
altsyncram_component.widthad_a = 6,
altsyncram_component.widthad_b = 6,
altsyncram_component.width_a = 32,
altsyncram_component.width_b = 32,
altsyncram_component.width_byteena_a = 1;
endmodule
|
// (C) 2001-2012 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1 ps / 1 ps
module rw_manager_ac_ROM_reg(
rdaddress,
clock,
wraddress,
data,
wren,
q);
parameter AC_ROM_DATA_WIDTH = "";
parameter AC_ROM_ADDRESS_WIDTH = "";
input [(AC_ROM_ADDRESS_WIDTH-1):0] rdaddress;
input clock;
input [(AC_ROM_ADDRESS_WIDTH-1):0] wraddress;
input [(AC_ROM_DATA_WIDTH-1):0] data;
input wren;
output reg [(AC_ROM_DATA_WIDTH-1):0] q;
reg [(AC_ROM_DATA_WIDTH-1):0] ac_mem[(2**AC_ROM_ADDRESS_WIDTH-1):0];
always @(posedge clock)
begin
if(wren)
ac_mem[wraddress] <= data;
q <= ac_mem[rdaddress];
end
endmodule
|
// (C) 2001-2012 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1 ps / 1 ps
module rw_manager_bitcheck(
ck,
reset_n,
clear,
enable,
read_data,
reference_data,
mask,
error_word
);
parameter DATA_WIDTH = "";
parameter AFI_RATIO = "";
localparam NUMBER_OF_WORDS = 2 * AFI_RATIO;
localparam DATA_BUS_SIZE = DATA_WIDTH * NUMBER_OF_WORDS;
input ck;
input reset_n;
input clear;
input enable;
input [DATA_BUS_SIZE - 1 : 0] read_data;
input [DATA_BUS_SIZE - 1 : 0] reference_data;
input [NUMBER_OF_WORDS - 1 : 0] mask;
output [DATA_WIDTH - 1 : 0] error_word;
reg [DATA_BUS_SIZE - 1 : 0] read_data_r;
reg [DATA_WIDTH - 1 : 0] error_word;
reg enable_r;
wire [DATA_WIDTH - 1 : 0] error_compute;
always @(posedge ck or negedge reset_n) begin
if(~reset_n) begin
error_word <= {DATA_WIDTH{1'b0}};
read_data_r <= {DATA_BUS_SIZE{1'b0}};
enable_r <= 1'b0;
end
else begin
if(clear) begin
error_word <= {DATA_WIDTH{1'b0}};
end
else if(enable_r) begin
error_word <= error_word | error_compute;
end
read_data_r <= read_data;
enable_r <= enable;
end
end
genvar b;
generate
for(b = 0; b < DATA_WIDTH; b = b + 1)
begin : bit_loop
if (AFI_RATIO == 4) begin
assign error_compute[b] =
((read_data_r[b] ^ reference_data[b]) & ~mask[0]) |
((read_data_r[b + DATA_WIDTH] ^ reference_data[b + DATA_WIDTH]) & ~mask[1]) |
((read_data_r[b + 2 * DATA_WIDTH] ^ reference_data[b + 2 * DATA_WIDTH]) & ~mask[2]) |
((read_data_r[b + 3 * DATA_WIDTH] ^ reference_data[b + 3 * DATA_WIDTH]) & ~mask[3]) |
((read_data_r[b + 4 * DATA_WIDTH] ^ reference_data[b + 4 * DATA_WIDTH]) & ~mask[4]) |
((read_data_r[b + 5 * DATA_WIDTH] ^ reference_data[b + 5 * DATA_WIDTH]) & ~mask[5]) |
((read_data_r[b + 6 * DATA_WIDTH] ^ reference_data[b + 6 * DATA_WIDTH]) & ~mask[6]) |
((read_data_r[b + 7 * DATA_WIDTH] ^ reference_data[b + 7 * DATA_WIDTH]) & ~mask[7]);
end
else if (AFI_RATIO == 2) begin
assign error_compute[b] =
((read_data_r[b] ^ reference_data[b]) & ~mask[0]) |
((read_data_r[b + DATA_WIDTH] ^ reference_data[b + DATA_WIDTH]) & ~mask[1]) |
((read_data_r[b + 2 * DATA_WIDTH] ^ reference_data[b + 2 * DATA_WIDTH]) & ~mask[2])|
((read_data_r[b + 3 * DATA_WIDTH] ^ reference_data[b + 3 * DATA_WIDTH]) & ~mask[3]);
end
else begin
assign error_compute[b] =
((read_data_r[b] ^ reference_data[b]) & ~mask[0]) |
((read_data_r[b + DATA_WIDTH] ^ reference_data[b + DATA_WIDTH]) & ~mask[1]);
end
end
endgenerate
endmodule
|
// (C) 2001-2012 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1 ps / 1 ps
module rw_manager_datamux(datain, sel, dataout);
parameter DATA_WIDTH = 8;
parameter SELECT_WIDTH = 1;
parameter NUMBER_OF_CHANNELS = 2;
input [NUMBER_OF_CHANNELS * DATA_WIDTH - 1 : 0] datain;
input [SELECT_WIDTH - 1 : 0] sel;
output [DATA_WIDTH - 1 : 0] dataout;
wire [DATA_WIDTH - 1 : 0] vectorized_data [0 : NUMBER_OF_CHANNELS - 1];
assign dataout = vectorized_data[sel];
genvar c;
generate
for(c = 0 ; c < NUMBER_OF_CHANNELS ; c = c + 1)
begin : channel_iterator
assign vectorized_data[c] = datain[(c + 1) * DATA_WIDTH - 1 : c * DATA_WIDTH];
end
endgenerate
`ifdef ADD_UNIPHY_SIM_SVA
assert property (@datain NUMBER_OF_CHANNELS == 2**SELECT_WIDTH) else
$error("%t, [DATAMUX ASSERT] NUMBER_OF_CHANNELS PARAMETER is incorrect, NUMBER_OF_CHANNELS = %d, 2**SELECT_WIDTH = %d", $time, NUMBER_OF_CHANNELS, 2**SELECT_WIDTH);
`endif
endmodule
|
// (C) 2001-2012 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1 ps / 1 ps
module rw_manager_data_broadcast(
dq_data_in,
dm_data_in,
dq_data_out,
dm_data_out
);
parameter NUMBER_OF_DQS_GROUPS = "";
parameter NUMBER_OF_DQ_PER_DQS = "";
parameter AFI_RATIO = "";
parameter MEM_DM_WIDTH = "";
localparam NUMBER_OF_DQ_BITS = NUMBER_OF_DQS_GROUPS * NUMBER_OF_DQ_PER_DQS;
localparam NUMBER_OF_WORDS = 2 * AFI_RATIO;
input [NUMBER_OF_DQ_PER_DQS * NUMBER_OF_WORDS - 1 : 0] dq_data_in;
input [NUMBER_OF_WORDS - 1 : 0] dm_data_in;
output [NUMBER_OF_DQ_BITS * NUMBER_OF_WORDS - 1 : 0] dq_data_out;
output [MEM_DM_WIDTH * 2 * AFI_RATIO - 1 : 0] dm_data_out;
genvar gr, wr, dmbit;
generate
for(wr = 0; wr < NUMBER_OF_WORDS; wr = wr + 1)
begin : word
for(gr = 0; gr < NUMBER_OF_DQS_GROUPS; gr = gr + 1)
begin : group
assign dq_data_out[wr * NUMBER_OF_DQ_BITS + (gr + 1) * NUMBER_OF_DQ_PER_DQS - 1 : wr * NUMBER_OF_DQ_BITS + gr * NUMBER_OF_DQ_PER_DQS] =
dq_data_in[(wr + 1) * NUMBER_OF_DQ_PER_DQS - 1 : wr * NUMBER_OF_DQ_PER_DQS];
end
for(dmbit = 0; dmbit < MEM_DM_WIDTH; dmbit = dmbit + 1)
begin : data_mask_bit
assign dm_data_out[wr * MEM_DM_WIDTH + dmbit] = dm_data_in[wr];
end
end
endgenerate
`ifdef ADD_UNIPHY_SIM_SVA
assert property (@dm_data_in NUMBER_OF_DQS_GROUPS == MEM_DM_WIDTH) else
$error("%t, [DATA BROADCAST ASSERT] NUMBER_OF_DQS_GROUPS and MEM_DM_WIDTH mismatch, NUMBER_OF_DQS_GROUPS = %d, MEM_DM_WIDTH = %d", $time, NUMBER_OF_DQS_GROUPS, MEM_DM_WIDTH);
`endif
endmodule
|
// (C) 2001-2012 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1 ps / 1 ps
module rw_manager_data_decoder(
ck,
reset_n,
code,
pattern
);
parameter DATA_WIDTH = "";
parameter AFI_RATIO = "";
input ck;
input reset_n;
input [3:0] code;
output [2 * DATA_WIDTH * AFI_RATIO - 1 : 0] pattern;
reg [3:0] code_R;
always @(posedge ck or negedge reset_n) begin
if(~reset_n) begin
code_R <= 4'b0000;
end
else begin
code_R <= code;
end
end
genvar j;
generate
for(j = 0; j < DATA_WIDTH; j = j + 1)
begin : bit_pattern
if(j % 2 == 0) begin
assign pattern[j] = code_R[3];
assign pattern[j + DATA_WIDTH] = code_R[2];
if (AFI_RATIO == 2) begin
assign pattern[j + 2 * DATA_WIDTH] = code_R[3] ^ code_R[1];
assign pattern[j + 3 * DATA_WIDTH] = code_R[2] ^ code_R[1];
end else if (AFI_RATIO == 4) begin
assign pattern[j + 2 * DATA_WIDTH] = code_R[3] ^ code_R[1];
assign pattern[j + 3 * DATA_WIDTH] = code_R[2] ^ code_R[1];
assign pattern[j + 4 * DATA_WIDTH] = code_R[3];
assign pattern[j + 5 * DATA_WIDTH] = code_R[2];
assign pattern[j + 6 * DATA_WIDTH] = code_R[3] ^ code_R[1];
assign pattern[j + 7 * DATA_WIDTH] = code_R[2] ^ code_R[1];
end
end
else begin
assign pattern[j] = code_R[3] ^ code_R[0];
assign pattern[j + DATA_WIDTH] = code_R[2] ^ code_R[0];
if (AFI_RATIO == 2) begin
assign pattern[j + 2 * DATA_WIDTH] = code_R[3] ^ code_R[1] ^ code_R[0];
assign pattern[j + 3 * DATA_WIDTH] = code_R[2] ^ code_R[1] ^ code_R[0];
end else if (AFI_RATIO == 4) begin
assign pattern[j + 2 * DATA_WIDTH] = code_R[3] ^ code_R[1] ^ code_R[0];
assign pattern[j + 3 * DATA_WIDTH] = code_R[2] ^ code_R[1] ^ code_R[0];
assign pattern[j + 4 * DATA_WIDTH] = code_R[3] ^ code_R[0];
assign pattern[j + 5 * DATA_WIDTH] = code_R[2] ^ code_R[0];
assign pattern[j + 6 * DATA_WIDTH] = code_R[3] ^ code_R[1] ^ code_R[0];
assign pattern[j + 7 * DATA_WIDTH] = code_R[2] ^ code_R[1] ^ code_R[0];
end
end
end
endgenerate
endmodule
|
// (C) 2001-2012 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1 ps / 1 ps
module rw_manager_ddr2 (
avl_clk,
avl_reset_n,
avl_address,
avl_write,
avl_writedata,
avl_read,
avl_readdata,
avl_waitrequest,
afi_clk,
afi_reset_n,
afi_addr,
afi_ba,
afi_cs_n,
afi_cke,
afi_odt,
afi_ras_n,
afi_cas_n,
afi_we_n,
afi_dqs_burst,
afi_wdata,
afi_wdata_valid,
afi_dm,
afi_rdata_en,
afi_rdata_en_full,
afi_rdata,
afi_rdata_valid,
csr_clk,
csr_ena,
csr_dout_phy,
csr_dout
);
parameter AVL_DATA_WIDTH = 32;
parameter AVL_ADDR_WIDTH = 16;
parameter MEM_ADDRESS_WIDTH = 19;
parameter MEM_CONTROL_WIDTH = 4;
parameter MEM_DQ_WIDTH = 36;
parameter MEM_DM_WIDTH = 4;
parameter MEM_NUMBER_OF_RANKS = 1;
parameter MEM_CLK_EN_WIDTH = 1;
parameter MEM_BANK_WIDTH = 2;
parameter MEM_ODT_WIDTH = 1;
parameter MEM_CHIP_SELECT_WIDTH = 1;
parameter MEM_READ_DQS_WIDTH = 4;
parameter MEM_WRITE_DQS_WIDTH = 4;
parameter AFI_RATIO = 2;
parameter RATE = "Half";
parameter HCX_COMPAT_MODE = 0;
parameter DEVICE_FAMILY = "STRATIXIV";
parameter AC_ROM_INIT_FILE_NAME = "AC_ROM.hex";
parameter INST_ROM_INIT_FILE_NAME = "inst_ROM.hex";
parameter DEBUG_WRITE_TO_READ_RATIO_2_EXPONENT = 0;
parameter DEBUG_WRITE_TO_READ_RATIO = 0;
parameter MAX_DI_BUFFER_WORDS_LOG_2 = 0;
localparam ZERO_EXTEND_WIDTH = (MEM_ADDRESS_WIDTH > 13) ? MEM_ADDRESS_WIDTH - 13 : 0;
input avl_clk;
input avl_reset_n;
input [AVL_ADDR_WIDTH-1:0] avl_address;
input avl_write;
input [AVL_DATA_WIDTH-1:0] avl_writedata;
input avl_read;
output [AVL_DATA_WIDTH-1:0] avl_readdata;
output avl_waitrequest;
input afi_clk;
input afi_reset_n;
output [MEM_ADDRESS_WIDTH * AFI_RATIO - 1:0] afi_addr;
output [MEM_BANK_WIDTH * AFI_RATIO - 1:0] afi_ba;
output [MEM_CHIP_SELECT_WIDTH * AFI_RATIO - 1:0] afi_cs_n;
output [MEM_CLK_EN_WIDTH * AFI_RATIO - 1:0] afi_cke;
output [MEM_ODT_WIDTH * AFI_RATIO - 1:0] afi_odt;
output [MEM_CONTROL_WIDTH * AFI_RATIO - 1:0] afi_ras_n;
output [MEM_CONTROL_WIDTH * AFI_RATIO - 1:0] afi_cas_n;
output [MEM_CONTROL_WIDTH * AFI_RATIO - 1:0] afi_we_n;
output [MEM_WRITE_DQS_WIDTH * AFI_RATIO - 1:0] afi_dqs_burst;
output [MEM_DQ_WIDTH * 2 * AFI_RATIO - 1:0] afi_wdata;
output [MEM_WRITE_DQS_WIDTH * AFI_RATIO - 1:0] afi_wdata_valid;
output [MEM_DM_WIDTH * 2 * AFI_RATIO - 1:0] afi_dm;
output [AFI_RATIO-1:0] afi_rdata_en;
output [AFI_RATIO-1:0] afi_rdata_en_full;
input [MEM_DQ_WIDTH * 2 * AFI_RATIO - 1:0] afi_rdata;
input [AFI_RATIO-1:0] afi_rdata_valid;
input csr_clk;
input csr_ena;
input csr_dout_phy;
output csr_dout;
parameter AC_BUS_WIDTH = 30;
wire [AC_BUS_WIDTH - 1:0] ac_bus;
rw_manager_generic rw_mgr_inst (
.avl_clk(avl_clk),
.avl_reset_n(avl_reset_n),
.avl_address(avl_address),
.avl_write(avl_write),
.avl_writedata(avl_writedata),
.avl_read(avl_read),
.avl_readdata(avl_readdata),
.avl_waitrequest(avl_waitrequest),
.afi_clk(afi_clk),
.afi_reset_n(afi_reset_n),
.ac_masked_bus (afi_cs_n),
.ac_bus (ac_bus),
.afi_wdata(afi_wdata),
.afi_dm(afi_dm),
.afi_odt(afi_odt),
.afi_rdata(afi_rdata),
.afi_rdata_valid(afi_rdata_valid),
.afi_rrank(),
.afi_wrank(),
.csr_clk(csr_clk),
.csr_ena(csr_ena),
.csr_dout_phy(csr_dout_phy),
.csr_dout(csr_dout)
);
defparam rw_mgr_inst.AVL_DATA_WIDTH = AVL_DATA_WIDTH;
defparam rw_mgr_inst.AVL_ADDRESS_WIDTH = AVL_ADDR_WIDTH;
defparam rw_mgr_inst.MEM_DQ_WIDTH = MEM_DQ_WIDTH;
defparam rw_mgr_inst.MEM_DM_WIDTH = MEM_DM_WIDTH;
defparam rw_mgr_inst.MEM_ODT_WIDTH = MEM_ODT_WIDTH;
defparam rw_mgr_inst.AC_BUS_WIDTH = AC_BUS_WIDTH;
defparam rw_mgr_inst.AC_MASKED_BUS_WIDTH = MEM_CHIP_SELECT_WIDTH * AFI_RATIO;
defparam rw_mgr_inst.MASK_WIDTH = MEM_CHIP_SELECT_WIDTH;
defparam rw_mgr_inst.AFI_RATIO = AFI_RATIO;
defparam rw_mgr_inst.MEM_READ_DQS_WIDTH = MEM_READ_DQS_WIDTH;
defparam rw_mgr_inst.MEM_WRITE_DQS_WIDTH = MEM_WRITE_DQS_WIDTH;
defparam rw_mgr_inst.MEM_NUMBER_OF_RANKS = MEM_NUMBER_OF_RANKS;
defparam rw_mgr_inst.RATE = RATE;
defparam rw_mgr_inst.HCX_COMPAT_MODE = HCX_COMPAT_MODE;
defparam rw_mgr_inst.DEVICE_FAMILY = DEVICE_FAMILY;
defparam rw_mgr_inst.DEBUG_READ_DI_WIDTH = 32;
defparam rw_mgr_inst.DEBUG_WRITE_TO_READ_RATIO_2_EXPONENT = DEBUG_WRITE_TO_READ_RATIO_2_EXPONENT;
defparam rw_mgr_inst.DEBUG_WRITE_TO_READ_RATIO = DEBUG_WRITE_TO_READ_RATIO;
defparam rw_mgr_inst.MAX_DI_BUFFER_WORDS_LOG_2 = MAX_DI_BUFFER_WORDS_LOG_2;
defparam rw_mgr_inst.AC_ROM_INIT_FILE_NAME = AC_ROM_INIT_FILE_NAME;
defparam rw_mgr_inst.INST_ROM_INIT_FILE_NAME = INST_ROM_INIT_FILE_NAME;
defparam rw_mgr_inst.AC_ODT_BIT =
(AFI_RATIO == 2) ? 24 :
23;
generate
begin
wire [MEM_ADDRESS_WIDTH-1:0] afi_address_half;
assign afi_address_half = ac_bus[12:0];
assign afi_addr = {AFI_RATIO{afi_address_half}};
assign afi_ba = {AFI_RATIO{ac_bus[MEM_BANK_WIDTH - 1 + 13:13]}};
assign afi_ras_n = {(MEM_CONTROL_WIDTH * AFI_RATIO){ac_bus[16]}};
assign afi_cas_n = {(MEM_CONTROL_WIDTH * AFI_RATIO){ac_bus[17]}};
assign afi_we_n = {(MEM_CONTROL_WIDTH * AFI_RATIO){ac_bus[18]}};
if (AFI_RATIO == 2) begin
assign afi_dqs_burst = {{(MEM_WRITE_DQS_WIDTH * AFI_RATIO / 2){ac_bus[20]}}, {(MEM_WRITE_DQS_WIDTH * AFI_RATIO / 2){ac_bus[19]}}};
assign afi_rdata_en_full = {AFI_RATIO{ac_bus[21]}};
assign afi_rdata_en = {AFI_RATIO{ac_bus[22]}};
assign afi_wdata_valid = {MEM_WRITE_DQS_WIDTH * AFI_RATIO{ac_bus[23]}};
assign afi_cke = {(MEM_CLK_EN_WIDTH * AFI_RATIO){ac_bus[25]}};
end else begin
assign afi_dqs_burst = {(MEM_WRITE_DQS_WIDTH * AFI_RATIO){ac_bus[19]}};
assign afi_rdata_en_full = {AFI_RATIO{ac_bus[20]}};
assign afi_rdata_en = {AFI_RATIO{ac_bus[21]}};
assign afi_wdata_valid = {MEM_WRITE_DQS_WIDTH * AFI_RATIO{ac_bus[22]}};
assign afi_cke = {(MEM_CLK_EN_WIDTH * AFI_RATIO){ac_bus[24]}};
end
end
endgenerate
endmodule
|
// (C) 2001-2012 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module rw_manager_di_buffer (
clock,
data,
rdaddress,
wraddress,
wren,
q,
clear);
parameter DATA_WIDTH = 32;
parameter ADDR_WIDTH = 4;
parameter NUM_WORDS = 16;
input clock;
input [DATA_WIDTH-1:0] data;
input [ADDR_WIDTH-1:0] rdaddress;
input [ADDR_WIDTH-1:0] wraddress;
input wren;
output [DATA_WIDTH-1:0] q;
input clear;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
tri0 wren;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
// synthesis translate_off
reg [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] mem [0:NUM_WORDS-1];
integer i;
/*
integer j;
always @(posedge clock or posedge clear) begin
if (clear) begin
for (i = 0; i < NUM_WORDS; i = i + 1) begin
for (j = 0; j < DATA_WIDTH/32; j = j+ 1) begin
mem[i][32*j+:32] <= i*(DATA_WIDTH/32) + j;
end
end
end
else begin
q <= mem[rdaddress];
end
end
*/
always @(posedge clock or posedge clear) begin
if (clear) begin
for (i = 0; i < NUM_WORDS; i = i + 1) begin
mem[i] <= 0;
end
end
else begin
if (wren)
mem[wraddress] <= data;
q <= mem[rdaddress];
end
end
// synthesis translate_on
// synthesis read_comments_as_HDL on
// wire [DATA_WIDTH-1:0] sub_wire0;
// wire [DATA_WIDTH-1:0] q = sub_wire0[DATA_WIDTH-1:0];
//
// altsyncram altsyncram_component (
// .address_a (wraddress),
// .clock0 (clock),
// .data_a (data),
// .wren_a (wren),
// .address_b (rdaddress),
// .q_b (sub_wire0),
// .aclr0 (1'b0),
// .aclr1 (1'b0),
// .addressstall_a (1'b0),
// .addressstall_b (1'b0),
// .byteena_a (1'b1),
// .byteena_b (1'b1),
// .clock1 (1'b1),
// .clocken0 (1'b1),
// .clocken1 (1'b1),
// .clocken2 (1'b1),
// .clocken3 (1'b1),
// .data_b ({DATA_WIDTH{1'b1}}),
// .eccstatus (),
// .q_a (),
// .rden_a (1'b1),
// .rden_b ((rdaddress < NUM_WORDS) ? 1'b1 : 1'b0),
// .wren_b (1'b0));
// defparam
// altsyncram_component.address_aclr_b = "NONE",
// altsyncram_component.address_reg_b = "CLOCK0",
// altsyncram_component.clock_enable_input_a = "BYPASS",
// altsyncram_component.clock_enable_input_b = "BYPASS",
// altsyncram_component.clock_enable_output_b = "BYPASS",
// altsyncram_component.intended_device_family = "Stratix III",
// altsyncram_component.lpm_type = "altsyncram",
// altsyncram_component.numwords_a = NUM_WORDS,
// altsyncram_component.numwords_b = NUM_WORDS,
// altsyncram_component.operation_mode = "DUAL_PORT",
// altsyncram_component.outdata_aclr_b = "NONE",
// altsyncram_component.outdata_reg_b = "UNREGISTERED",
// altsyncram_component.power_up_uninitialized = "FALSE",
// altsyncram_component.ram_block_type = "MLAB",
// altsyncram_component.widthad_a = ADDR_WIDTH,
// altsyncram_component.widthad_b = ADDR_WIDTH,
// altsyncram_component.width_a = DATA_WIDTH,
// altsyncram_component.width_b = DATA_WIDTH,
// altsyncram_component.width_byteena_a = 1;
// synthesis read_comments_as_HDL off
endmodule
|
// (C) 2001-2012 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1 ps / 1 ps
module rw_manager_di_buffer_wrap(
clock,
data,
rdaddress,
wraddress,
wren,
q,
clear);
parameter DATA_WIDTH = 18;
parameter READ_DATA_SIZE = 9;
parameter WRITE_TO_READ_RATIO_2_EXPONENT = 2;
parameter WRITE_TO_READ_RATIO = 1;
parameter ADDR_WIDTH = 2;
parameter NUM_WORDS = 16;
input clock;
input [DATA_WIDTH-1:0] data;
input [ADDR_WIDTH - 1 : 0] rdaddress;
input [ADDR_WIDTH-1:0] wraddress;
input wren;
output [READ_DATA_SIZE - 1 : 0] q;
input clear;
wire [DATA_WIDTH-1:0] q_wire;
wire wren_gated;
wire [ADDR_WIDTH + ADDR_WIDTH - WRITE_TO_READ_RATIO_2_EXPONENT - 1 : 0] rdaddress_tmp = {{ADDR_WIDTH{1'b0}}, rdaddress[ADDR_WIDTH-1 : WRITE_TO_READ_RATIO_2_EXPONENT]};
assign wren_gated = (wraddress >= NUM_WORDS) ? 1'b0 : wren;
rw_manager_di_buffer rw_manager_di_buffer_i(
.clock(clock),
.data(data),
.rdaddress(rdaddress_tmp[ADDR_WIDTH-1 : 0]),
.wraddress(wraddress),
.wren(wren_gated),
.q(q_wire),
.clear(clear));
defparam rw_manager_di_buffer_i.DATA_WIDTH = DATA_WIDTH;
defparam rw_manager_di_buffer_i.ADDR_WIDTH = ADDR_WIDTH;
defparam rw_manager_di_buffer_i.NUM_WORDS = NUM_WORDS;
generate
if(WRITE_TO_READ_RATIO_2_EXPONENT > 0) begin
wire [WRITE_TO_READ_RATIO * READ_DATA_SIZE + DATA_WIDTH - 1 : 0] datain_tmp = {{(WRITE_TO_READ_RATIO * READ_DATA_SIZE){1'b0}}, q_wire};
rw_manager_datamux rw_manager_datamux_i(
.datain(datain_tmp[WRITE_TO_READ_RATIO*READ_DATA_SIZE-1:0]),
.sel(rdaddress[WRITE_TO_READ_RATIO_2_EXPONENT - 1 : 0]),
.dataout(q)
);
defparam rw_manager_datamux_i.DATA_WIDTH = READ_DATA_SIZE;
defparam rw_manager_datamux_i.SELECT_WIDTH = WRITE_TO_READ_RATIO_2_EXPONENT;
defparam rw_manager_datamux_i.NUMBER_OF_CHANNELS = WRITE_TO_READ_RATIO;
end
else begin
assign q = q_wire;
end
endgenerate
endmodule
|
// (C) 2001-2012 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1 ps / 1 ps
module rw_manager_dm_decoder(ck, reset_n, code, pattern);
parameter AFI_RATIO = "";
input ck;
input reset_n;
input [2:0] code;
output [2 * AFI_RATIO - 1 : 0] pattern;
reg [2:0] code_R;
always @(posedge ck or negedge reset_n) begin
if(~reset_n) begin
code_R <= 3'b000;
end
else begin
code_R <= code;
end
end
assign pattern[0] = code_R[2];
assign pattern[1] = code_R[1];
generate
if (AFI_RATIO == 2) begin
assign pattern[2] = code_R[2] ^ code_R[0];
assign pattern[3] = code_R[1] ^ code_R[0];
end else if (AFI_RATIO == 4) begin
assign pattern[2] = code_R[2] ^ code_R[0];
assign pattern[3] = code_R[1] ^ code_R[0];
assign pattern[4] = code_R[2];
assign pattern[5] = code_R[1];
assign pattern[6] = code_R[2] ^ code_R[0];
assign pattern[7] = code_R[1] ^ code_R[0];
end
endgenerate
endmodule
|
// (C) 2001-2012 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module rw_manager_inst_ROM_no_ifdef_params (
clock,
data,
rdaddress,
wraddress,
wren,
q);
parameter ROM_INIT_FILE_NAME = "inst_ROM.hex";
input clock;
input [19:0] data;
input [6:0] rdaddress;
input [6:0] wraddress;
input wren;
output [19:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
tri0 wren;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [19:0] sub_wire0;
wire [19:0] q = sub_wire0[19:0];
altsyncram altsyncram_component (
.clock0 (clock),
.address_a (rdaddress),
.wren_a (1'b0),
.data_a ({20{1'b1}}),
.q_a (sub_wire0),
.address_b (),
.q_b (),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b ({20{1'b1}}),
.eccstatus (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_b = "NONE",
altsyncram_component.address_reg_b = "CLOCK0",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
`ifdef NO_PLI
altsyncram_component.init_file = "inst_ROM.rif",
`else
altsyncram_component.init_file = ROM_INIT_FILE_NAME,
`endif
altsyncram_component.intended_device_family = "Stratix III",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 128,
altsyncram_component.numwords_b = 128,
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_b = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.operation_mode = "ROM",
altsyncram_component.ram_block_type = "MLAB",
altsyncram_component.widthad_a = 7,
altsyncram_component.widthad_b = 7,
altsyncram_component.width_a = 20,
altsyncram_component.width_b = 20,
altsyncram_component.width_byteena_a = 1;
endmodule
|
// (C) 2001-2012 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1 ps / 1 ps
module rw_manager_inst_ROM_reg(
rdaddress,
clock,
data,
wraddress,
wren,
q);
parameter INST_ROM_DATA_WIDTH = "";
parameter INST_ROM_ADDRESS_WIDTH = "";
input [(INST_ROM_ADDRESS_WIDTH-1):0] rdaddress;
input clock;
input [(INST_ROM_ADDRESS_WIDTH-1):0] wraddress;
input [(INST_ROM_DATA_WIDTH-1):0] data;
input wren;
output reg [(INST_ROM_DATA_WIDTH-1):0] q;
reg [(INST_ROM_DATA_WIDTH-1):0] inst_mem[(2**INST_ROM_ADDRESS_WIDTH-1):0];
always @(posedge clock)
begin
if (wren)
inst_mem[wraddress]<= data;
q <= inst_mem[rdaddress];
end
endmodule
|
// (C) 2001-2012 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1 ps / 1 ps
module rw_manager_jumplogic(
ck,
reset_n,
cntr_value,
cntr_load,
reg_select,
reg_load_select,
jump_value,
jump_load,
jump_check,
jump_taken,
jump_address,
cntr_3
);
parameter DATA_WIDTH = 8;
input ck;
input reset_n;
input [DATA_WIDTH-1:0] cntr_value;
input cntr_load;
input [1:0] reg_select;
input [1:0] reg_load_select;
input [DATA_WIDTH-1:0] jump_value;
input jump_load;
input jump_check;
output jump_taken;
output [DATA_WIDTH-1:0] jump_address;
output [DATA_WIDTH-1:0] cntr_3;
reg [7:0] cntr [0:3];
reg [7:0] cntr_shadow [0:3];
reg [7:0] jump_pointers [0:3];
wire [3:0] comparisons;
assign jump_address = jump_pointers[reg_select];
assign jump_taken = (jump_check & ~comparisons[reg_select]);
assign cntr_3 = cntr[3];
genvar c;
generate
for(c = 0; c < 4; c = c + 1)
begin : jumpcounter
assign comparisons[c] = (cntr[c] == {DATA_WIDTH{1'b0}});
always @(posedge ck or negedge reset_n) begin
if(~reset_n) begin
cntr[c] <= {DATA_WIDTH{1'b0}};
end
else if (cntr_load && reg_load_select == c) begin
cntr[c] <= cntr_value;
end
else if (jump_check && reg_select == c) begin
cntr[c] <= (comparisons[c]) ? cntr_shadow[c] : cntr[c] - 1'b1;
end
end
end
endgenerate
always @(posedge ck or negedge reset_n) begin
if(~reset_n) begin
jump_pointers[0] <= {DATA_WIDTH{1'b0}};
jump_pointers[1] <= {DATA_WIDTH{1'b0}};
jump_pointers[2] <= {DATA_WIDTH{1'b0}};
jump_pointers[3] <= {DATA_WIDTH{1'b0}};
cntr_shadow[0] <= {DATA_WIDTH{1'b0}};
cntr_shadow[1] <= {DATA_WIDTH{1'b0}};
cntr_shadow[2] <= {DATA_WIDTH{1'b0}};
cntr_shadow[3] <= {DATA_WIDTH{1'b0}};
end
else begin
if(jump_load) begin
jump_pointers[0] <= (reg_load_select == 2'b00)? jump_value : jump_pointers[0];
jump_pointers[1] <= (reg_load_select == 2'b01)? jump_value : jump_pointers[1];
jump_pointers[2] <= (reg_load_select == 2'b10)? jump_value : jump_pointers[2];
jump_pointers[3] <= (reg_load_select == 2'b11)? jump_value : jump_pointers[3];
end
if(cntr_load) begin
cntr_shadow[0] <= (reg_load_select == 2'b00)? cntr_value : cntr_shadow[0];
cntr_shadow[1] <= (reg_load_select == 2'b01)? cntr_value : cntr_shadow[1];
cntr_shadow[2] <= (reg_load_select == 2'b10)? cntr_value : cntr_shadow[2];
cntr_shadow[3] <= (reg_load_select == 2'b11)? cntr_value : cntr_shadow[3];
end
end
end
endmodule
|
// (C) 2001-2012 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1 ps / 1 ps
module rw_manager_lfsr12(
clk,
nrst,
ena,
word
);
input clk;
input nrst;
input ena;
output reg [11:0] word;
always @(posedge clk or negedge nrst) begin
if(~nrst) begin
word <= 12'b101001101011;
end
else if(ena) begin
word[11] <= word[0];
word[10] <= word[11];
word[9] <= word[10];
word[8] <= word[9];
word[7] <= word[8];
word[6] <= word[7];
word[5] <= word[6] ^ word[0];
word[4] <= word[5];
word[3] <= word[4] ^ word[0];
word[2] <= word[3];
word[1] <= word[2];
word[0] <= word[1] ^ word[0];
end
end
endmodule
|
// (C) 2001-2012 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1 ps / 1 ps
module rw_manager_lfsr36(
clk,
nrst,
ena,
word
);
input clk;
input nrst;
input ena;
output reg [35:0] word;
always @(posedge clk or negedge nrst) begin
if(~nrst) begin
word <= 36'hF0F0AA55;
end
else if(ena) begin
word[35] <= word[0];
word[34] <= word[35];
word[33] <= word[34];
word[32] <= word[33];
word[31] <= word[32];
word[30] <= word[31];
word[29] <= word[30];
word[28] <= word[29];
word[27] <= word[28];
word[26] <= word[27];
word[25] <= word[26];
word[24] <= word[25] ^ word[0];
word[23] <= word[24];
word[22] <= word[23];
word[21] <= word[22];
word[20] <= word[21];
word[19] <= word[20];
word[18] <= word[19];
word[17] <= word[18];
word[16] <= word[17];
word[15] <= word[16];
word[14] <= word[15];
word[13] <= word[14];
word[12] <= word[13];
word[11] <= word[12];
word[10] <= word[11];
word[9] <= word[10];
word[8] <= word[9];
word[7] <= word[8];
word[6] <= word[7];
word[5] <= word[6];
word[4] <= word[5];
word[3] <= word[4];
word[2] <= word[3];
word[1] <= word[2];
word[0] <= word[1];
end
end
endmodule
|
// (C) 2001-2012 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1 ps / 1 ps
module rw_manager_lfsr72(
clk,
nrst,
ena,
word
);
input clk;
input nrst;
input ena;
output reg [71:0] word;
always @(posedge clk or negedge nrst) begin
if(~nrst) begin
word <= 72'hAAF0F0AA55F0F0AA55;
end
else if(ena) begin
word[71] <= word[0];
word[70:66] <= word[71:67];
word[65] <= word[66] ^ word[0];
word[64:25] <= word[65:26];
word[24] <= word[25] ^ word[0];
word[23:19] <= word[24:20];
word[18] <= word[19] ^ word[0];
word[17:0] <= word[18:1];
end
end
endmodule
|
// (C) 2001-2012 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module rw_manager_pattern_fifo (
clock,
data,
rdaddress,
wraddress,
wren,
q);
input clock;
input [8:0] data;
input [4:0] rdaddress;
input [4:0] wraddress;
input wren;
output [8:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
tri0 wren;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [8:0] sub_wire0;
wire [8:0] q = sub_wire0[8:0];
altsyncram altsyncram_component (
.address_a (wraddress),
.clock0 (clock),
.data_a (data),
.wren_a (wren),
.address_b (rdaddress),
.q_b (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b ({9{1'b1}}),
.eccstatus (),
.q_a (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_b = "NONE",
altsyncram_component.address_reg_b = "CLOCK0",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.intended_device_family = "Stratix IV",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 32,
altsyncram_component.numwords_b = 32,
altsyncram_component.operation_mode = "DUAL_PORT",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_b = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.ram_block_type = "MLAB",
altsyncram_component.widthad_a = 5,
altsyncram_component.widthad_b = 5,
altsyncram_component.width_a = 9,
altsyncram_component.width_b = 9,
altsyncram_component.width_byteena_a = 1;
endmodule
|
// (C) 2001-2012 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1 ps / 1 ps
module rw_manager_ram
(
data,
rdaddress,
wraddress,
wren, clock,
q
);
parameter DATA_WIDTH=36;
parameter ADDR_WIDTH=8;
input [(DATA_WIDTH-1):0] data;
input [(ADDR_WIDTH-1):0] rdaddress, wraddress;
input wren, clock;
output reg [(DATA_WIDTH-1):0] q;
reg [DATA_WIDTH-1:0] ram[2**ADDR_WIDTH-1:0];
always @ (posedge clock)
begin
if (wren)
ram[wraddress] <= data[DATA_WIDTH-1:0];
q <= ram[rdaddress];
end
endmodule
|
// (C) 2001-2012 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1 ps / 1 ps
module rw_manager_ram_csr #(
parameter DATA_WIDTH = 32,
parameter ADDR_WIDTH = 2,
parameter NUM_WORDS = 4
) (
input csr_clk,
input csr_ena,
input csr_din,
input ram_clk,
input wren,
input [(DATA_WIDTH-1):0] data,
input [(ADDR_WIDTH-1):0] wraddress,
input [(ADDR_WIDTH-1):0] rdaddress,
output reg [(DATA_WIDTH-1):0] q,
output reg csr_dout
);
localparam integer DATA_COUNT = DATA_WIDTH*NUM_WORDS;
reg [DATA_COUNT-1:0] all_data;
wire [DATA_COUNT-1:0] load_data;
wire [DATA_WIDTH-1:0] row_data [NUM_WORDS-1:0];
wire int_clk;
assign int_clk = (~csr_ena)? csr_clk : ram_clk;
always @(posedge int_clk)
begin
if (~csr_ena)
all_data <= {all_data[DATA_COUNT-2:0], csr_din};
else if (wren)
all_data <= load_data;
else
all_data <= all_data;
q <= row_data[rdaddress];
end
always @(negedge csr_clk)
begin
csr_dout <= all_data[DATA_COUNT-1];
end
generate
genvar i;
for (i = 0; i < (NUM_WORDS); i = i + 1)
begin: row_assign
assign row_data[i] = all_data[(DATA_WIDTH*(i+1)-1) : (DATA_WIDTH*i)];
end
endgenerate
generate
genvar j,k;
for (j = 0; j < (NUM_WORDS); j = j + 1)
begin: row
for (k = 0; k < (DATA_WIDTH); k = k + 1)
begin: column
assign load_data[(DATA_WIDTH*j)+k] = (wraddress == j)? data[k] : all_data[(DATA_WIDTH*j)+k];
end
end
endgenerate
endmodule
|
// (C) 2001-2012 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1 ps / 1 ps
module rw_manager_read_datapath(
ck,
reset_n,
check_do,
check_dm,
check_do_lfsr,
check_dm_lfsr,
check_pattern_push,
clear_error,
read_data,
read_data_valid,
error_word
);
parameter DATA_WIDTH = "";
parameter AFI_RATIO = "";
localparam NUMBER_OF_WORDS = 2 * AFI_RATIO;
localparam DATA_BUS_SIZE = DATA_WIDTH * NUMBER_OF_WORDS;
input ck;
input reset_n;
input [3:0] check_do;
input [2:0] check_dm;
input check_do_lfsr;
input check_dm_lfsr;
input check_pattern_push;
input clear_error;
input [DATA_BUS_SIZE - 1 : 0] read_data;
input read_data_valid;
output [DATA_WIDTH - 1 : 0] error_word;
reg [4:0] pattern_radd;
reg [4:0] pattern_wadd;
wire [4:0] pattern_radd_next;
wire [8:0] check_word_write = { check_do, check_dm, check_do_lfsr, check_dm_lfsr };
wire [8:0] check_word_read;
wire [3:0] check_do_read = check_word_read[8:5];
wire [2:0] check_dm_read = check_word_read[4:2];
wire check_do_lfsr_read = check_word_read[1];
wire check_dm_lfsr_read = check_word_read[0];
wire [DATA_BUS_SIZE - 1 : 0] do_data;
wire [NUMBER_OF_WORDS - 1 : 0] dm_data;
wire do_lfsr_step = check_do_lfsr_read & read_data_valid;
wire dm_lfsr_step = check_dm_lfsr_read & read_data_valid;
rw_manager_bitcheck bitcheck_i(
.ck(ck),
.reset_n(reset_n),
.clear(clear_error),
.enable(read_data_valid),
.read_data(read_data),
.reference_data(do_data),
.mask(dm_data),
.error_word(error_word)
);
defparam bitcheck_i.DATA_WIDTH = DATA_WIDTH;
defparam bitcheck_i.AFI_RATIO = AFI_RATIO;
rw_manager_write_decoder write_decoder_i(
.ck(ck),
.reset_n(reset_n),
.do_lfsr(check_do_lfsr_read),
.dm_lfsr(check_dm_lfsr_read),
.do_lfsr_step(do_lfsr_step),
.dm_lfsr_step(dm_lfsr_step),
.do_code(check_do_read),
.dm_code(check_dm_read),
.do_data(do_data),
.dm_data(dm_data)
);
defparam write_decoder_i.DATA_WIDTH = DATA_WIDTH;
defparam write_decoder_i.AFI_RATIO = AFI_RATIO;
rw_manager_pattern_fifo pattern_fifo_i(
.clock(ck),
.data(check_word_write),
.rdaddress(pattern_radd_next),
.wraddress(pattern_wadd),
.wren(check_pattern_push),
.q(check_word_read)
);
assign pattern_radd_next = pattern_radd + (read_data_valid ? 1'b1 : 1'b0);
always @(posedge ck or negedge reset_n) begin
if(~reset_n) begin
pattern_radd <= 5'b00000;
pattern_wadd <= 5'b00000;
end
else begin
if (clear_error) begin
pattern_radd <= 5'b00000;
pattern_wadd <= 5'b00000;
end else begin
if(read_data_valid) begin
pattern_radd <= pattern_radd + 1'b1;
end
if(check_pattern_push) begin
pattern_wadd <= pattern_wadd + 1'b1;
end
end
end
end
endmodule
|
// (C) 2001-2012 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1 ps / 1 ps
module rw_manager_write_decoder(
ck,
reset_n,
do_lfsr,
dm_lfsr,
do_lfsr_step,
dm_lfsr_step,
do_code,
dm_code,
do_data,
dm_data
);
parameter DATA_WIDTH = "";
parameter AFI_RATIO = "";
localparam NUMBER_OF_WORDS = 2 * AFI_RATIO;
localparam DO_LFSR_WIDTH = ((AFI_RATIO == 4) ? 72 : 36);
input ck;
input reset_n;
input do_lfsr;
input dm_lfsr;
input do_lfsr_step;
input dm_lfsr_step;
input [3:0] do_code;
input [2:0] dm_code;
output [2 * DATA_WIDTH * AFI_RATIO - 1 : 0] do_data;
output [NUMBER_OF_WORDS-1:0] dm_data;
reg do_lfsr_r;
reg dm_lfsr_r;
wire [DO_LFSR_WIDTH-1:0] do_lfsr_word;
wire [11:0] dm_lfsr_word;
wire [2 * DATA_WIDTH * AFI_RATIO - 1 : 0] do_word;
wire [NUMBER_OF_WORDS -1 : 0] dm_word;
rw_manager_data_decoder DO_decoder(
.ck(ck),
.reset_n(reset_n),
.code(do_code),
.pattern(do_word)
);
defparam DO_decoder.DATA_WIDTH = DATA_WIDTH;
defparam DO_decoder.AFI_RATIO = AFI_RATIO;
rw_manager_dm_decoder DM_decoder_i(
.ck(ck),
.reset_n(reset_n),
.code(dm_code),
.pattern(dm_word)
);
defparam DM_decoder_i.AFI_RATIO = AFI_RATIO;
generate
begin
if (AFI_RATIO == 4) begin
rw_manager_lfsr72 do_lfsr_i(
.clk(ck),
.nrst(reset_n),
.ena(do_lfsr_step),
.word(do_lfsr_word)
);
end else begin
rw_manager_lfsr36 do_lfsr_i(
.clk(ck),
.nrst(reset_n),
.ena(do_lfsr_step),
.word(do_lfsr_word)
);
end
end
endgenerate
rw_manager_lfsr12 dm_lfsr_i(
.clk(ck),
.nrst(reset_n),
.ena(dm_lfsr_step),
.word(dm_lfsr_word)
);
always @(posedge ck or negedge reset_n) begin
if(~reset_n) begin
do_lfsr_r <= 1'b0;
dm_lfsr_r <= 1'b0;
end
else begin
do_lfsr_r <= do_lfsr;
dm_lfsr_r <= dm_lfsr;
end
end
assign do_data = (do_lfsr_r) ? do_lfsr_word[2 * DATA_WIDTH * AFI_RATIO - 1 : 0] : do_word;
assign dm_data = (dm_lfsr_r) ? dm_lfsr_word[NUMBER_OF_WORDS+1: 2] : dm_word;
endmodule
|
// (C) 2001-2012 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1 ps / 1 ps
module sequencer_scc_acv_phase_decode
# (parameter
AVL_DATA_WIDTH = 32,
DLL_DELAY_CHAIN_LENGTH = 8
)
(
avl_writedata,
dqse_phase
);
input [AVL_DATA_WIDTH - 1:0] avl_writedata;
// Arria V and Cyclone V only have dqse_phase control
// phase decoding.
output [3:0] dqse_phase;
reg [3:0] dqse_phase;
always @ (*) begin
// DQSE = 270
dqse_phase = 4'b0110;
case (avl_writedata[2:0])
3'b000: // DQSE = 90
begin
dqse_phase = 4'b0010;
end
3'b001: // DQSE = 135
begin
dqse_phase = 4'b0011;
end
3'b010: // DQSE = 180
begin
dqse_phase = 4'b0100;
end
3'b011: // DQSE = 225
begin
dqse_phase = 4'b0101;
end
3'b100: // DQSE = 270
begin
dqse_phase = 4'b0110;
end
3'b101: // DQSE = 315
begin
dqse_phase = 4'b1111;
end
3'b110: // DQSE = 360
begin
dqse_phase = 4'b1000;
end
3'b111: // DQSE = 405
begin
dqse_phase = 4'b1001;
end
default : begin end
endcase
end
endmodule
|
// (C) 2001-2012 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module sequencer_scc_reg_file (
clock,
data,
rdaddress,
wraddress,
wren,
q);
parameter WIDTH = "";
parameter DEPTH = "";
input clock;
input [WIDTH-1:0] data;
input [DEPTH-1:0] rdaddress;
input [DEPTH-1:0] wraddress;
input wren;
output [WIDTH-1:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 wren;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [WIDTH-1:0] sub_wire0;
wire [WIDTH-1:0] q = sub_wire0[WIDTH-1:0];
altdpram altdpram_component (
.data (data),
.outclock (),
.rdaddress (rdaddress),
.wren (wren),
.inclock (clock),
.wraddress (wraddress),
.q (sub_wire0),
.aclr (1'b0),
.byteena (1'b1),
.inclocken (1'b1),
.outclocken (1'b1),
.rdaddressstall (1'b0),
.rden (1'b1),
.wraddressstall (1'b0));
defparam
altdpram_component.indata_aclr = "OFF",
altdpram_component.indata_reg = "INCLOCK",
altdpram_component.intended_device_family = "Stratix IV",
altdpram_component.lpm_type = "altdpram",
altdpram_component.outdata_aclr = "OFF",
altdpram_component.outdata_reg = "UNREGISTERED",
altdpram_component.ram_block_type = "MLAB",
altdpram_component.rdaddress_aclr = "OFF",
altdpram_component.rdaddress_reg = "UNREGISTERED",
altdpram_component.rdcontrol_aclr = "OFF",
altdpram_component.rdcontrol_reg = "UNREGISTERED",
altdpram_component.width = WIDTH,
altdpram_component.widthad = DEPTH,
altdpram_component.width_byteena = 1,
altdpram_component.wraddress_aclr = "OFF",
altdpram_component.wraddress_reg = "INCLOCK",
altdpram_component.wrcontrol_aclr = "OFF",
altdpram_component.wrcontrol_reg = "INCLOCK";
endmodule
|
// (C) 2001-2012 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1 ps / 1 ps
module sequencer_scc_siii_phase_decode
# (parameter
AVL_DATA_WIDTH = 32,
DLL_DELAY_CHAIN_LENGTH = 6
)
(
avl_writedata,
dqsi_phase,
dqs_phase,
dq_phase,
dqse_phase
);
input [AVL_DATA_WIDTH - 1:0] avl_writedata;
output [2:0] dqsi_phase;
output [6:0] dqs_phase;
output [6:0] dq_phase;
output [5:0] dqse_phase;
// phase decoding.
reg [2:0] dqsi_phase;
reg [6:0] dqs_phase;
reg [6:0] dq_phase;
reg [5:0] dqse_phase;
// decode phases
always @ (*) begin
dqsi_phase = 0;
dqs_phase = 0;
dq_phase = 0;
dqse_phase = 0;
case (DLL_DELAY_CHAIN_LENGTH)
6: begin
// DQSin = 60, DQS = 180, DQ = 120, DQSE = 120
dqsi_phase = 3'b000;
dqs_phase = 7'b0010100;
dq_phase = 7'b0001100;
dqse_phase = 6'b001000;
case (avl_writedata[4:0])
5'b00000: // DQS = 180, DQ = 120, DQSE = 120
begin
dqs_phase = 7'b0010100;
dq_phase = 7'b0001100;
dqse_phase = 6'b001000;
end
5'b00001: // DQS = 240, DQ = 180, DQSE = 180
begin
dqs_phase = 7'b0011100;
dq_phase = 7'b0010100;
dqse_phase = 6'b001100;
end
5'b00010: // DQS = 300, DQ = 240, DQSE = 240
begin
dqs_phase = 7'b0100110;
dq_phase = 7'b0011100;
dqse_phase = 6'b000110;
end
5'b00011: // DQS = 360, DQ = 300, DQSE = 300
begin
dqs_phase = 7'b0010010;
dq_phase = 7'b0001010;
dqse_phase = 6'b001011;
end
5'b00100: // DQS = 420, DQ = 360, DQSE = 360
begin
dqs_phase = 7'b0011010;
dq_phase = 7'b0010010;
dqse_phase = 6'b001111;
end
5'b00101: // DQS = 480, DQ = 420, DQSE = 420
begin
dqs_phase = 7'b0100001;
dq_phase = 7'b0011010;
dqse_phase = 6'b000101;
end
5'b00110: // DQS = 540, DQ = 480
begin
dqs_phase = 7'b0010101;
dq_phase = 7'b0001101;
end
5'b00111: // DQS = 600, DQ = 540
begin
dqs_phase = 7'b0011101;
dq_phase = 7'b0010101;
end
5'b01000: // DQS = 660, DQ = 600
begin
dqs_phase = 7'b0100111;
dq_phase = 7'b0011101;
end
5'b01001: // DQS = 720, DQ = 660
begin
dqs_phase = 7'b0010011;
dq_phase = 7'b0001011;
end
5'b01010: // DQS = 780, DQ = 720
begin
dqs_phase = 7'b0011011;
dq_phase = 7'b0010011;
end
default : begin end
endcase
end
8: begin
// DQSin = 90, DQS = 180, DQ = 90, DQSE = 90
dqsi_phase = 3'b001;
dqs_phase = 7'b0010100;
dq_phase = 7'b0000100;
dqse_phase = 6'b001000;
case (avl_writedata[4:0])
5'b00000: // DQS = 180, DQ = 90, DQSE = 90
begin
dqs_phase = 7'b0010100;
dq_phase = 7'b0000100;
dqse_phase = 6'b001000;
end
5'b00001: // DQS = 225, DQ = 135, DQSE = 135
begin
dqs_phase = 7'b0011100;
dq_phase = 7'b0001100;
dqse_phase = 6'b001100;
end
5'b00010: // DQS = 270, DQ = 180, DQSE = 180
begin
dqs_phase = 7'b0100100;
dq_phase = 7'b0010100;
dqse_phase = 6'b010000;
end
5'b00011: // DQS = 315, DQ = 225, DQSE = 225
begin
dqs_phase = 7'b0101110;
dq_phase = 7'b0011100;
dqse_phase = 6'b000110;
end
5'b00100: // DQS = 360, DQ = 270, DQSE = 270
begin
dqs_phase = 7'b0010010;
dq_phase = 7'b0000000;
dqse_phase = 6'b001010;
end
5'b00101: // DQS = 405, DQ = 315, DQSE = 315
begin
dqs_phase = 7'b0011010;
dq_phase = 7'b0001010;
dqse_phase = 6'b001111;
end
5'b00110: // DQS = 450, DQ = 360, DQSE = 360
begin
dqs_phase = 7'b0100010;
dq_phase = 7'b0010010;
dqse_phase = 6'b010011;
end
5'b00111: // DQS = 495, DQ = 405, DQSE = 405
begin
dqs_phase = 7'b0101001;
dq_phase = 7'b0011010;
dqse_phase = 6'b000101;
end
5'b01000: // DQS = 540, DQ = 450
begin
dqs_phase = 7'b0010101;
dq_phase = 7'b0000110;
end
5'b01001: // DQS = 585, DQ = 495
begin
dqs_phase = 7'b0011101;
dq_phase = 7'b0001101;
end
5'b01010: // DQS = 630, DQ = 540
begin
dqs_phase = 7'b0100101;
dq_phase = 7'b0010101;
end
5'b01011: // DQS = 675, DQ = 585
begin
dqs_phase = 7'b0101111;
dq_phase = 7'b0011101;
end
5'b01100: // DQS = 720, DQ = 630
begin
dqs_phase = 7'b0010011;
dq_phase = 7'b0000001;
end
5'b01101: // DQS = 765, DQ = 675
begin
dqs_phase = 7'b0011011;
dq_phase = 7'b0001011;
end
5'b01110: // DQS = 810, DQ = 720
begin
dqs_phase = 7'b0100011;
dq_phase = 7'b0010011;
end
default : begin end
endcase
end
10: begin
// DQSin = 72, DQS = 180, DQ = 108, DQSE = 108
dqsi_phase = 3'b001;
dqs_phase = 7'b0010100;
dq_phase = 7'b0000100;
dqse_phase = 6'b001100;
case (avl_writedata[4:0])
5'b00000: // DQS = 180, DQ = 108, DQSE = 108
begin
dqs_phase = 7'b0010100;
dq_phase = 7'b0000100;
dqse_phase = 6'b001100;
end
5'b00001: // DQS = 216, DQ = 144, DQSE = 144
begin
dqs_phase = 7'b0011100;
dq_phase = 7'b0001100;
dqse_phase = 6'b010000;
end
5'b00010: // DQS = 252, DQ = 180, DQSE = 180
begin
dqs_phase = 7'b0100100;
dq_phase = 7'b0010100;
dqse_phase = 6'b010100;
end
5'b00011: // DQS = 288, DQ = 216, DQSE = 216
begin
dqs_phase = 7'b0101110;
dq_phase = 7'b0011100;
dqse_phase = 6'b000110;
end
5'b00100: // DQS = 324, DQ = 252, DQSE = 252
begin
dqs_phase = 7'b0110110;
dq_phase = 7'b0100100;
dqse_phase = 6'b001010;
end
5'b00101: // DQS = 360, DQ = 288, DQSE = 288
begin
dqs_phase = 7'b0010010;
dq_phase = 7'b0000010;
dqse_phase = 6'b001111;
end
5'b00110: // DQS = 396, DQ = 324, DQSE = 324
begin
dqs_phase = 7'b0011010;
dq_phase = 7'b0001010;
dqse_phase = 6'b010011;
end
5'b00111: // DQS = 432, DQ = 360, DQSE = 360
begin
dqs_phase = 7'b0100010;
dq_phase = 7'b0010010;
dqse_phase = 6'b010111;
end
5'b01000: // DQS = 468, DQ = 396, DQSE = 396
begin
dqs_phase = 7'b0101001;
dq_phase = 7'b0011010;
dqse_phase = 6'b000101;
end
5'b01001: // DQS = 504, DQ = 432, DQSE = 432
begin
dqs_phase = 7'b0110001;
dq_phase = 7'b0100010;
dqse_phase = 6'b001001;
end
5'b01010: // DQS = 540, DQ = 468
begin
dqs_phase = 7'b0010101;
dq_phase = 7'b0000101;
end
5'b01011: // DQS = 576, DQ = 504
begin
dqs_phase = 7'b0011101;
dq_phase = 7'b0001101;
end
5'b01100: // DQS = 612, DQ = 540
begin
dqs_phase = 7'b0100101;
dq_phase = 7'b0010101;
end
5'b01101: // DQS = 648, DQ = 576
begin
dqs_phase = 7'b0101111;
dq_phase = 7'b0011101;
end
5'b01110: // DQS = 684, DQ = 612
begin
dqs_phase = 7'b0110111;
dq_phase = 7'b0100101;
end
5'b01111: // DQS = 720, DQ = 648
begin
dqs_phase = 7'b0010011;
dq_phase = 7'b0000011;
end
5'b10000: // DQS = 756, DQ = 684
begin
dqs_phase = 7'b0011011;
dq_phase = 7'b0001011;
end
5'b10001: // DQS = 792, DQ = 720
begin
dqs_phase = 7'b0100011;
dq_phase = 7'b0010011;
end
default : begin end
endcase
end
12: begin
// DQSin = 60, DQS = 180, DQ = 120, DQSE = 90
dqsi_phase = 3'b001;
dqs_phase = 7'b0010100;
dq_phase = 7'b0000100;
dqse_phase = 6'b001100;
case (avl_writedata[4:0])
5'b00000: // DQS = 180, DQ = 120, DQSE = 90
begin
dqs_phase = 7'b0010100;
dq_phase = 7'b0000100;
dqse_phase = 6'b001100;
end
5'b00001: // DQS = 210, DQ = 150, DQSE = 120
begin
dqs_phase = 7'b0011100;
dq_phase = 7'b0001100;
dqse_phase = 6'b010000;
end
5'b00010: // DQS = 240, DQ = 180, DQSE = 150
begin
dqs_phase = 7'b0100100;
dq_phase = 7'b0010100;
dqse_phase = 6'b010100;
end
5'b00011: // DQS = 270, DQ = 210, DQSE = 180
begin
dqs_phase = 7'b0101100;
dq_phase = 7'b0011100;
dqse_phase = 6'b011000;
end
5'b00100: // DQS = 300, DQ = 240, DQSE = 210
begin
dqs_phase = 7'b0110110;
dq_phase = 7'b0100100;
dqse_phase = 6'b000110;
end
5'b00101: // DQS = 330, DQ = 270, DQSE = 240
begin
dqs_phase = 7'b0111110;
dq_phase = 7'b0101100;
dqse_phase = 6'b001010;
end
5'b00110: // DQS = 360, DQ = 300, DQSE = 270
begin
dqs_phase = 7'b0010010;
dq_phase = 7'b0000010;
dqse_phase = 6'b001110;
end
5'b00111: // DQS = 390, DQ = 330, DQSE = 300
begin
dqs_phase = 7'b0011010;
dq_phase = 7'b0001010;
dqse_phase = 6'b010011;
end
5'b01000: // DQS = 420, DQ = 360, DQSE = 330
begin
dqs_phase = 7'b0100010;
dq_phase = 7'b0010010;
dqse_phase = 6'b010111;
end
5'b01001: // DQS = 450, DQ = 390, DQSE = 360
begin
dqs_phase = 7'b0101010;
dq_phase = 7'b0011010;
dqse_phase = 6'b011011;
end
5'b01010: // DQS = 480, DQ = 420, DQSE = 390
begin
dqs_phase = 7'b0110001;
dq_phase = 7'b0100010;
dqse_phase = 6'b000101;
end
5'b01011: // DQS = 510, DQ = 450, DQSE = 420
begin
dqs_phase = 7'b0111001;
dq_phase = 7'b0101010;
dqse_phase = 6'b001001;
end
5'b01100: // DQS = 540, DQ = 480
begin
dqs_phase = 7'b0010101;
dq_phase = 7'b0000101;
end
5'b01101: // DQS = 570, DQ = 510
begin
dqs_phase = 7'b0011101;
dq_phase = 7'b0001101;
end
5'b01110: // DQS = 600, DQ = 540
begin
dqs_phase = 7'b0100101;
dq_phase = 7'b0010101;
end
5'b01111: // DQS = 630, DQ = 570
begin
dqs_phase = 7'b0101101;
dq_phase = 7'b0011101;
end
5'b10000: // DQS = 660, DQ = 600
begin
dqs_phase = 7'b0110111;
dq_phase = 7'b0100101;
end
5'b10001: // DQS = 690, DQ = 630
begin
dqs_phase = 7'b0111111;
dq_phase = 7'b0101101;
end
5'b10010: // DQS = 720, DQ = 660
begin
dqs_phase = 7'b0010011;
dq_phase = 7'b0000011;
end
5'b10011: // DQS = 750, DQ = 690
begin
dqs_phase = 7'b0011011;
dq_phase = 7'b0001011;
end
5'b10100: // DQS = 780, DQ = 720
begin
dqs_phase = 7'b0100011;
dq_phase = 7'b0010011;
end
5'b10101: // DQS = 810, DQ = 750
begin
dqs_phase = 7'b0101011;
dq_phase = 7'b0011011;
end
default : begin end
endcase
end
default : begin end
endcase
end
endmodule
|
// (C) 2001-2012 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1 ps / 1 ps
module sequencer_scc_sv_phase_decode
# (parameter
AVL_DATA_WIDTH = 32,
DLL_DELAY_CHAIN_LENGTH = 6
)
(
avl_writedata,
dqsi_phase,
dqs_phase,
dq_phase,
dqse_phase
);
input [AVL_DATA_WIDTH - 1:0] avl_writedata;
output [2:0] dqsi_phase;
output [6:0] dqs_phase;
output [6:0] dq_phase;
output [5:0] dqse_phase;
reg [2:0] dqsi_phase;
reg [6:0] dqs_phase;
reg [6:0] dq_phase;
reg [5:0] dqse_phase;
always @ (*) begin
dqsi_phase = 3'b010;
dqs_phase = 7'b1110110;
dq_phase = 7'b0110100;
dqse_phase = 6'b000110;
case (avl_writedata[4:0])
5'b00000: // DQS = 180, DQ = 90, DQSE = 90
begin
dqs_phase = 7'b0010110;
dq_phase = 7'b1000110;
dqse_phase = 6'b000010;
end
5'b00001: // DQS = 225, DQ = 135, DQSE = 135
begin
dqs_phase = 7'b0110110;
dq_phase = 7'b1100110;
dqse_phase = 6'b000011;
end
5'b00010: // DQS = 270, DQ = 180, DQSE = 180
begin
dqs_phase = 7'b1010110;
dq_phase = 7'b0010110;
dqse_phase = 6'b000100;
end
5'b00011: // DQS = 315, DQ = 225, DQSE = 225
begin
dqs_phase = 7'b1110111;
dq_phase = 7'b0110110;
dqse_phase = 6'b000101;
end
5'b00100: // DQS = 360, DQ = 270, DQSE = 270
begin
dqs_phase = 7'b0000111;
dq_phase = 7'b1010110;
dqse_phase = 6'b000110;
end
5'b00101: // DQS = 405, DQ = 315, DQSE = 315
begin
dqs_phase = 7'b0100111;
dq_phase = 7'b1110111;
dqse_phase = 6'b001111;
end
5'b00110: // DQS = 450, DQ = 360, DQSE = 360
begin
dqs_phase = 7'b1001000;
dq_phase = 7'b0000111;
dqse_phase = 6'b001000;
end
5'b00111: // DQS = 495, DQ = 405, DQSE = 405
begin
dqs_phase = 7'b1101000;
dq_phase = 7'b0100111;
dqse_phase = 6'b001001;
end
5'b01000: // DQS = 540, DQ = 450
begin
dqs_phase = 7'b0011000;
dq_phase = 7'b1001000;
end
5'b01001:
begin
dqs_phase = 7'b0111000;
dq_phase = 7'b1101000;
end
5'b01010:
begin
dqs_phase = 7'b1011000;
dq_phase = 7'b0011000;
end
5'b01011:
begin
dqs_phase = 7'b1111001;
dq_phase = 7'b0111000;
end
5'b01100:
begin
dqs_phase = 7'b0001001;
dq_phase = 7'b1011000;
end
5'b01101:
begin
dqs_phase = 7'b0101001;
dq_phase = 7'b1111001;
end
5'b01110:
begin
dqs_phase = 7'b1001010;
dq_phase = 7'b0001001;
end
5'b01111:
begin
dqs_phase = 7'b1101010;
dq_phase = 7'b0101001;
end
5'b10000:
begin
dqs_phase = 7'b0011010;
dq_phase = 7'b1001010;
end
5'b10001:
begin
dqs_phase = 7'b0111010;
dq_phase = 7'b1101010;
end
5'b10010:
begin
dqs_phase = 7'b1011010;
dq_phase = 7'b0011010;
end
5'b10011:
begin
dqs_phase = 7'b1111011;
dq_phase = 7'b0111010;
end
5'b10100:
begin
dqs_phase = 7'b0001011;
dq_phase = 7'b1011010;
end
5'b10101:
begin
dqs_phase = 7'b0101011;
dq_phase = 7'b1111011;
end
default : begin end
endcase
end
endmodule
|
`timescale 1 ns / 1 ns
module memory_controller
(
clk,
memory_controller_address,
memory_controller_write_enable,
memory_controller_in,
memory_controller_out
);
`define MEMORY_CONTROLLER_TAGS 7
`define MEMORY_CONTROLLER_TAG_SIZE 3
`define TAG_countLeadingZerosHigh_1302 `MEMORY_CONTROLLER_TAG_SIZE'd0
`define TAG_float_exception_flags `MEMORY_CONTROLLER_TAG_SIZE'd1
`define TAG_test_in `MEMORY_CONTROLLER_TAG_SIZE'd2
`define TAG_test_out `MEMORY_CONTROLLER_TAG_SIZE'd3
`define TAG__str `MEMORY_CONTROLLER_TAG_SIZE'd4
`define TAG__str1 `MEMORY_CONTROLLER_TAG_SIZE'd5
`define TAG__str2 `MEMORY_CONTROLLER_TAG_SIZE'd6
`define MEMORY_CONTROLLER_ADDR_SIZE `MEMORY_CONTROLLER_TAG_SIZE+32
`define MEMORY_CONTROLLER_DATA_SIZE 64
input clk;
input [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] memory_controller_address;
input memory_controller_write_enable;
input [`MEMORY_CONTROLLER_DATA_SIZE-1:0] memory_controller_in;
output reg [`MEMORY_CONTROLLER_DATA_SIZE-1:0] memory_controller_out;
reg [7:0] countLeadingZerosHigh_1302_address;
reg countLeadingZerosHigh_1302_write_enable;
reg [31:0] countLeadingZerosHigh_1302_in;
wire [31:0] countLeadingZerosHigh_1302_out;
ram_one_port countLeadingZerosHigh_1302 (
.clk( clk ),
.address( countLeadingZerosHigh_1302_address ),
.write_enable( countLeadingZerosHigh_1302_write_enable ),
.data( countLeadingZerosHigh_1302_in ),
.q( countLeadingZerosHigh_1302_out )
);
defparam countLeadingZerosHigh_1302.width_a = 32;
defparam countLeadingZerosHigh_1302.widthad_a = 8;
defparam countLeadingZerosHigh_1302.numwords_a = 256;
defparam countLeadingZerosHigh_1302.init_file = "countLeadingZerosHigh_1302.mif";
reg [0:0] float_exception_flags_address;
reg float_exception_flags_write_enable;
reg [31:0] float_exception_flags_in;
wire [31:0] float_exception_flags_out;
ram_one_port float_exception_flags (
.clk( clk ),
.address( float_exception_flags_address ),
.write_enable( float_exception_flags_write_enable ),
.data( float_exception_flags_in ),
.q( float_exception_flags_out )
);
defparam float_exception_flags.width_a = 32;
defparam float_exception_flags.widthad_a = 1;
defparam float_exception_flags.numwords_a = 1;
defparam float_exception_flags.init_file = "float_exception_flags.mif";
reg [5:0] test_in_address;
reg test_in_write_enable;
reg [63:0] test_in_in;
wire [63:0] test_in_out;
ram_one_port test_in (
.clk( clk ),
.address( test_in_address ),
.write_enable( test_in_write_enable ),
.data( test_in_in ),
.q( test_in_out )
);
defparam test_in.width_a = 64;
defparam test_in.widthad_a = 6;
defparam test_in.numwords_a = 36;
defparam test_in.init_file = "test_in.mif";
reg [5:0] test_out_address;
reg test_out_write_enable;
reg [63:0] test_out_in;
wire [63:0] test_out_out;
ram_one_port test_out (
.clk( clk ),
.address( test_out_address ),
.write_enable( test_out_write_enable ),
.data( test_out_in ),
.q( test_out_out )
);
defparam test_out.width_a = 64;
defparam test_out.widthad_a = 6;
defparam test_out.numwords_a = 36;
defparam test_out.init_file = "test_out.mif";
reg [5:0] _str_address;
reg _str_write_enable;
reg [7:0] _str_in;
wire [7:0] _str_out;
ram_one_port _str (
.clk( clk ),
.address( _str_address ),
.write_enable( _str_write_enable ),
.data( _str_in ),
.q( _str_out )
);
defparam _str.width_a = 8;
defparam _str.widthad_a = 6;
defparam _str.numwords_a = 53;
defparam _str.init_file = "_str.mif";
reg [1:0] _str1_address;
reg _str1_write_enable;
reg [7:0] _str1_in;
wire [7:0] _str1_out;
ram_one_port _str1 (
.clk( clk ),
.address( _str1_address ),
.write_enable( _str1_write_enable ),
.data( _str1_in ),
.q( _str1_out )
);
defparam _str1.width_a = 8;
defparam _str1.widthad_a = 2;
defparam _str1.numwords_a = 4;
defparam _str1.init_file = "_str1.mif";
reg [4:0] _str2_address;
reg _str2_write_enable;
reg [7:0] _str2_in;
wire [7:0] _str2_out;
ram_one_port _str2 (
.clk( clk ),
.address( _str2_address ),
.write_enable( _str2_write_enable ),
.data( _str2_in ),
.q( _str2_out )
);
defparam _str2.width_a = 8;
defparam _str2.widthad_a = 5;
defparam _str2.numwords_a = 32;
defparam _str2.init_file = "_str2.mif";
wire [`MEMORY_CONTROLLER_TAG_SIZE-1:0] tag = memory_controller_address[`MEMORY_CONTROLLER_ADDR_SIZE-1:`MEMORY_CONTROLLER_ADDR_SIZE-`MEMORY_CONTROLLER_TAG_SIZE];
reg [`MEMORY_CONTROLLER_TAG_SIZE-1:0] prevTag;
always @(posedge clk)
prevTag = tag;
always @(*)
begin
countLeadingZerosHigh_1302_address = 0;
countLeadingZerosHigh_1302_write_enable = 0;
countLeadingZerosHigh_1302_in = 0;
float_exception_flags_address = 0;
float_exception_flags_write_enable = 0;
float_exception_flags_in = 0;
test_in_address = 0;
test_in_write_enable = 0;
test_in_in = 0;
test_out_address = 0;
test_out_write_enable = 0;
test_out_in = 0;
_str_address = 0;
_str_write_enable = 0;
_str_in = 0;
_str1_address = 0;
_str1_write_enable = 0;
_str1_in = 0;
_str2_address = 0;
_str2_write_enable = 0;
_str2_in = 0;
case(tag)
default:
begin
// quartus issues a warning if we have no default case
end
`TAG_countLeadingZerosHigh_1302:
begin
if (memory_controller_address[1:0] != 0)
begin
$display("Error: memory address not aligned to ram word size!");
$finish;
end
countLeadingZerosHigh_1302_address = memory_controller_address[8-1+2:2];
countLeadingZerosHigh_1302_write_enable = memory_controller_write_enable;
countLeadingZerosHigh_1302_in[32-1:0] = memory_controller_in[32-1:0];
end
`TAG_float_exception_flags:
begin
if (memory_controller_address[1:0] != 0)
begin
$display("Error: memory address not aligned to ram word size!");
$finish;
end
float_exception_flags_address = memory_controller_address[1-1+2:2];
float_exception_flags_write_enable = memory_controller_write_enable;
float_exception_flags_in[32-1:0] = memory_controller_in[32-1:0];
end
`TAG_test_in:
begin
if (memory_controller_address[2:0] != 0)
begin
$display("Error: memory address not aligned to ram word size!");
$finish;
end
test_in_address = memory_controller_address[6-1+3:3];
test_in_write_enable = memory_controller_write_enable;
test_in_in[64-1:0] = memory_controller_in[64-1:0];
end
`TAG_test_out:
begin
if (memory_controller_address[2:0] != 0)
begin
$display("Error: memory address not aligned to ram word size!");
$finish;
end
test_out_address = memory_controller_address[6-1+3:3];
test_out_write_enable = memory_controller_write_enable;
test_out_in[64-1:0] = memory_controller_in[64-1:0];
end
`TAG__str:
begin
_str_address = memory_controller_address[6-1+0:0];
_str_write_enable = memory_controller_write_enable;
_str_in[8-1:0] = memory_controller_in[8-1:0];
end
`TAG__str1:
begin
_str1_address = memory_controller_address[2-1+0:0];
_str1_write_enable = memory_controller_write_enable;
_str1_in[8-1:0] = memory_controller_in[8-1:0];
end
`TAG__str2:
begin
_str2_address = memory_controller_address[5-1+0:0];
_str2_write_enable = memory_controller_write_enable;
_str2_in[8-1:0] = memory_controller_in[8-1:0];
end
endcase
memory_controller_out = 0;
case(prevTag)
default:
begin
// quartus issues a warning if we have no default case
end
`TAG_countLeadingZerosHigh_1302:
memory_controller_out = countLeadingZerosHigh_1302_out;
`TAG_float_exception_flags:
memory_controller_out = float_exception_flags_out;
`TAG_test_in:
memory_controller_out = test_in_out;
`TAG_test_out:
memory_controller_out = test_out_out;
`TAG__str:
memory_controller_out = _str_out;
`TAG__str1:
memory_controller_out = _str1_out;
`TAG__str2:
memory_controller_out = _str2_out;
endcase
end
endmodule
`timescale 1 ns / 1 ns
module main
(
clk,
reset,
start,
finish,
return_val
);
output reg [31:0] return_val;
input clk;
input reset;
input start;
output reg finish;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] memory_controller_address;
reg memory_controller_write_enable;
reg [`MEMORY_CONTROLLER_DATA_SIZE-1:0] memory_controller_in;
wire [`MEMORY_CONTROLLER_DATA_SIZE-1:0] memory_controller_out;
memory_controller memory_controller_inst (
.clk( clk ),
.memory_controller_address( memory_controller_address ),
.memory_controller_write_enable( memory_controller_write_enable ),
.memory_controller_in( memory_controller_in ),
.memory_controller_out( memory_controller_out )
);
reg roundAndPackFloat64_start;
wire roundAndPackFloat64_finish;
wire [63:0] roundAndPackFloat64_return_val;
wire [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] roundAndPackFloat64_memory_controller_address;
wire roundAndPackFloat64_memory_controller_write_enable;
wire [`MEMORY_CONTROLLER_DATA_SIZE-1:0] roundAndPackFloat64_memory_controller_in;
reg [`MEMORY_CONTROLLER_DATA_SIZE-1:0] roundAndPackFloat64_memory_controller_out;
reg [31:0] roundAndPackFloat64_zSign;
reg [31:0] roundAndPackFloat64_zExp;
reg [63:0] roundAndPackFloat64_zSig;
roundAndPackFloat64 roundAndPackFloat64_inst(
.clk( clk ),
.reset( reset ),
.start( roundAndPackFloat64_start ),
.finish( roundAndPackFloat64_finish ),
.return_val( roundAndPackFloat64_return_val ),
.memory_controller_address( roundAndPackFloat64_memory_controller_address ),
.memory_controller_write_enable( roundAndPackFloat64_memory_controller_write_enable ),
.memory_controller_in( roundAndPackFloat64_memory_controller_in ),
.memory_controller_out( roundAndPackFloat64_memory_controller_out ),
.zSign( roundAndPackFloat64_zSign ),
.zExp( roundAndPackFloat64_zExp ),
.zSig( roundAndPackFloat64_zSig )
);
reg float64_mul_start;
wire float64_mul_finish;
wire [63:0] float64_mul_return_val;
wire [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] float64_mul_memory_controller_address;
wire float64_mul_memory_controller_write_enable;
wire [`MEMORY_CONTROLLER_DATA_SIZE-1:0] float64_mul_memory_controller_in;
reg [`MEMORY_CONTROLLER_DATA_SIZE-1:0] float64_mul_memory_controller_out;
reg [63:0] float64_mul_a;
reg [63:0] float64_mul_b;
float64_mul float64_mul_inst(
.clk( clk ),
.reset( reset ),
.start( float64_mul_start ),
.finish( float64_mul_finish ),
.return_val( float64_mul_return_val ),
.memory_controller_address( float64_mul_memory_controller_address ),
.memory_controller_write_enable( float64_mul_memory_controller_write_enable ),
.memory_controller_in( float64_mul_memory_controller_in ),
.memory_controller_out( float64_mul_memory_controller_out ),
.a( float64_mul_a ),
.b( float64_mul_b )
);
reg [9:0] cur_state;
parameter Wait = 10'd0;
parameter bb_nph = 10'd1;
parameter bb = 10'd2;
parameter bb_1 = 10'd3;
parameter bb_2 = 10'd4;
parameter bb_3 = 10'd5;
parameter bb_4 = 10'd6;
parameter bb_4_call_0 = 10'd7;
parameter bb_4_call_1 = 10'd8;
parameter bb_5 = 10'd9;
parameter bb_i = 10'd10;
parameter bb_i_1 = 10'd11;
parameter bb_i_2 = 10'd12;
parameter bb_i_3 = 10'd13;
parameter bb_i_4 = 10'd14;
parameter bb_i_5 = 10'd15;
parameter bb1_i_i = 10'd16;
parameter bb1_i_i_1 = 10'd17;
parameter bb1_i_i_2 = 10'd18;
parameter bb1_i_i_3 = 10'd19;
parameter bb1_i_i_4 = 10'd20;
parameter bb1_i_i_5 = 10'd21;
parameter bb1_i_i_6 = 10'd22;
parameter bb1_i_i_7 = 10'd23;
parameter bb1_i_i_8 = 10'd24;
parameter bb1_i_i_9 = 10'd25;
parameter bb1_i_i_10 = 10'd26;
parameter bb1_i_i_11 = 10'd27;
parameter bb1_i_i_12 = 10'd28;
parameter bb1_i_i_13 = 10'd29;
parameter bb1_i_i_14 = 10'd30;
parameter bb1_i_i_15 = 10'd31;
parameter bb1_i_i_16 = 10'd32;
parameter int32_to_float64_exit_i = 10'd33;
parameter int32_to_float64_exit_i_call_0 = 10'd34;
parameter int32_to_float64_exit_i_call_1 = 10'd35;
parameter int32_to_float64_exit_i_1 = 10'd36;
parameter int32_to_float64_exit_i_2 = 10'd37;
parameter int32_to_float64_exit_i_3 = 10'd38;
parameter int32_to_float64_exit_i_4 = 10'd39;
parameter int32_to_float64_exit_i_5 = 10'd40;
parameter bb_i_i = 10'd41;
parameter bb_i_i_1 = 10'd42;
parameter bb1_i1_i = 10'd43;
parameter bb1_i1_i_1 = 10'd44;
parameter bb1_i1_i_2 = 10'd45;
parameter bb_i14_i65_i_i = 10'd46;
parameter bb_i14_i65_i_i_1 = 10'd47;
parameter bb_i14_i65_i_i_2 = 10'd48;
parameter float64_is_signaling_nan_exit16_i66_i_i = 10'd49;
parameter float64_is_signaling_nan_exit16_i66_i_i_1 = 10'd50;
parameter float64_is_signaling_nan_exit16_i66_i_i_2 = 10'd51;
parameter bb_i_i69_i_i = 10'd52;
parameter bb_i_i69_i_i_1 = 10'd53;
parameter bb_i_i69_i_i_2 = 10'd54;
parameter float64_is_signaling_nan_exit_i70_i_i = 10'd55;
parameter float64_is_signaling_nan_exit_i70_i_i_1 = 10'd56;
parameter float64_is_signaling_nan_exit_i70_i_i_2 = 10'd57;
parameter float64_is_signaling_nan_exit_i70_i_i_3 = 10'd58;
parameter bb_i71_i_i = 10'd59;
parameter bb_i71_i_i_1 = 10'd60;
parameter bb_i71_i_i_2 = 10'd61;
parameter bb_i71_i_i_3 = 10'd62;
parameter bb1_i72_i_i = 10'd63;
parameter bb1_i72_i_i_1 = 10'd64;
parameter bb2_i73_i_i = 10'd65;
parameter bb2_i73_i_i_1 = 10'd66;
parameter bb3_i75_i_i = 10'd67;
parameter bb2_i_i = 10'd68;
parameter bb2_i_i_1 = 10'd69;
parameter bb3_i_i = 10'd70;
parameter bb3_i_i_1 = 10'd71;
parameter bb4_i_i = 10'd72;
parameter bb4_i_i_1 = 10'd73;
parameter bb4_i_i_2 = 10'd74;
parameter bb_i14_i49_i_i = 10'd75;
parameter bb_i14_i49_i_i_1 = 10'd76;
parameter bb_i14_i49_i_i_2 = 10'd77;
parameter float64_is_signaling_nan_exit16_i50_i_i = 10'd78;
parameter float64_is_signaling_nan_exit16_i50_i_i_1 = 10'd79;
parameter float64_is_signaling_nan_exit16_i50_i_i_2 = 10'd80;
parameter bb_i_i53_i_i = 10'd81;
parameter bb_i_i53_i_i_1 = 10'd82;
parameter bb_i_i53_i_i_2 = 10'd83;
parameter float64_is_signaling_nan_exit_i54_i_i = 10'd84;
parameter float64_is_signaling_nan_exit_i54_i_i_1 = 10'd85;
parameter float64_is_signaling_nan_exit_i54_i_i_2 = 10'd86;
parameter float64_is_signaling_nan_exit_i54_i_i_3 = 10'd87;
parameter bb_i55_i_i = 10'd88;
parameter bb_i55_i_i_1 = 10'd89;
parameter bb_i55_i_i_2 = 10'd90;
parameter bb_i55_i_i_3 = 10'd91;
parameter bb1_i56_i_i = 10'd92;
parameter bb1_i56_i_i_1 = 10'd93;
parameter bb2_i57_i_i = 10'd94;
parameter bb2_i57_i_i_1 = 10'd95;
parameter bb3_i59_i_i = 10'd96;
parameter bb5_i_i = 10'd97;
parameter bb5_i_i_1 = 10'd98;
parameter bb5_i_i_2 = 10'd99;
parameter bb5_i_i_3 = 10'd100;
parameter bb6_i_i = 10'd101;
parameter bb6_i_i_1 = 10'd102;
parameter bb7_i_i = 10'd103;
parameter bb8_i_i = 10'd104;
parameter bb8_i_i_1 = 10'd105;
parameter bb9_i_i = 10'd106;
parameter bb9_i_i_1 = 10'd107;
parameter bb9_i_i_2 = 10'd108;
parameter bb_i14_i_i_i = 10'd109;
parameter bb_i14_i_i_i_1 = 10'd110;
parameter bb_i14_i_i_i_2 = 10'd111;
parameter float64_is_signaling_nan_exit16_i_i_i = 10'd112;
parameter float64_is_signaling_nan_exit16_i_i_i_1 = 10'd113;
parameter float64_is_signaling_nan_exit16_i_i_i_2 = 10'd114;
parameter bb_i_i43_i_i = 10'd115;
parameter bb_i_i43_i_i_1 = 10'd116;
parameter bb_i_i43_i_i_2 = 10'd117;
parameter float64_is_signaling_nan_exit_i_i_i = 10'd118;
parameter float64_is_signaling_nan_exit_i_i_i_1 = 10'd119;
parameter float64_is_signaling_nan_exit_i_i_i_2 = 10'd120;
parameter float64_is_signaling_nan_exit_i_i_i_3 = 10'd121;
parameter bb_i_i_i = 10'd122;
parameter bb_i_i_i_1 = 10'd123;
parameter bb_i_i_i_2 = 10'd124;
parameter bb_i_i_i_3 = 10'd125;
parameter bb1_i44_i_i = 10'd126;
parameter bb1_i44_i_i_1 = 10'd127;
parameter bb2_i45_i_i = 10'd128;
parameter bb2_i45_i_i_1 = 10'd129;
parameter bb3_i_i2_i = 10'd130;
parameter bb10_i_i = 10'd131;
parameter bb12_i_i = 10'd132;
parameter bb12_i_i_1 = 10'd133;
parameter bb13_i_i = 10'd134;
parameter bb13_i_i_1 = 10'd135;
parameter bb13_i_i_2 = 10'd136;
parameter bb13_i_i_3 = 10'd137;
parameter bb14_i_i = 10'd138;
parameter bb14_i_i_1 = 10'd139;
parameter bb15_i_i = 10'd140;
parameter bb15_i_i_1 = 10'd141;
parameter bb16_i_i = 10'd142;
parameter bb16_i_i_1 = 10'd143;
parameter bb_i_i32_i_i = 10'd144;
parameter bb1_i_i34_i_i = 10'd145;
parameter bb1_i_i34_i_i_1 = 10'd146;
parameter normalizeFloat64Subnormal_exit42_i_i = 10'd147;
parameter normalizeFloat64Subnormal_exit42_i_i_1 = 10'd148;
parameter normalizeFloat64Subnormal_exit42_i_i_2 = 10'd149;
parameter normalizeFloat64Subnormal_exit42_i_i_3 = 10'd150;
parameter normalizeFloat64Subnormal_exit42_i_i_4 = 10'd151;
parameter normalizeFloat64Subnormal_exit42_i_i_5 = 10'd152;
parameter normalizeFloat64Subnormal_exit42_i_i_6 = 10'd153;
parameter normalizeFloat64Subnormal_exit42_i_i_7 = 10'd154;
parameter normalizeFloat64Subnormal_exit42_i_i_8 = 10'd155;
parameter normalizeFloat64Subnormal_exit42_i_i_9 = 10'd156;
parameter normalizeFloat64Subnormal_exit42_i_i_10 = 10'd157;
parameter normalizeFloat64Subnormal_exit42_i_i_11 = 10'd158;
parameter normalizeFloat64Subnormal_exit42_i_i_12 = 10'd159;
parameter normalizeFloat64Subnormal_exit42_i_i_13 = 10'd160;
parameter bb17_i_i = 10'd161;
parameter bb17_i_i_1 = 10'd162;
parameter bb18_i_i = 10'd163;
parameter bb18_i_i_1 = 10'd164;
parameter bb19_i_i = 10'd165;
parameter bb20_i_i = 10'd166;
parameter bb20_i_i_1 = 10'd167;
parameter bb_i_i_i_i = 10'd168;
parameter bb1_i_i_i_i = 10'd169;
parameter bb1_i_i_i_i_1 = 10'd170;
parameter normalizeFloat64Subnormal_exit_i_i = 10'd171;
parameter normalizeFloat64Subnormal_exit_i_i_1 = 10'd172;
parameter normalizeFloat64Subnormal_exit_i_i_2 = 10'd173;
parameter normalizeFloat64Subnormal_exit_i_i_3 = 10'd174;
parameter normalizeFloat64Subnormal_exit_i_i_4 = 10'd175;
parameter normalizeFloat64Subnormal_exit_i_i_5 = 10'd176;
parameter normalizeFloat64Subnormal_exit_i_i_6 = 10'd177;
parameter normalizeFloat64Subnormal_exit_i_i_7 = 10'd178;
parameter normalizeFloat64Subnormal_exit_i_i_8 = 10'd179;
parameter normalizeFloat64Subnormal_exit_i_i_9 = 10'd180;
parameter normalizeFloat64Subnormal_exit_i_i_10 = 10'd181;
parameter normalizeFloat64Subnormal_exit_i_i_11 = 10'd182;
parameter normalizeFloat64Subnormal_exit_i_i_12 = 10'd183;
parameter normalizeFloat64Subnormal_exit_i_i_13 = 10'd184;
parameter bb21_i_i = 10'd185;
parameter bb21_i_i_1 = 10'd186;
parameter bb21_i_i_2 = 10'd187;
parameter bb21_i_i_3 = 10'd188;
parameter bb21_i_i_4 = 10'd189;
parameter bb21_i_i_5 = 10'd190;
parameter bb21_i_i_6 = 10'd191;
parameter bb21_i_i_7 = 10'd192;
parameter bb21_i_i_8 = 10'd193;
parameter bb21_i_i_9 = 10'd194;
parameter bb1_i_i_i = 10'd195;
parameter bb1_i_i_i_1 = 10'd196;
parameter bb1_i_i_i_2 = 10'd197;
parameter bb2_i_i3_i = 10'd198;
parameter bb2_i_i3_i_1 = 10'd199;
parameter bb4_i_i_i = 10'd200;
parameter bb4_i_i_i_1 = 10'd201;
parameter bb4_i_i_i_2 = 10'd202;
parameter bb4_i_i_i_3 = 10'd203;
parameter bb4_i_i_i_4 = 10'd204;
parameter bb4_i_i_i_5 = 10'd205;
parameter bb4_i_i_i_6 = 10'd206;
parameter bb4_i_i_i_7 = 10'd207;
parameter bb4_i_i_i_8 = 10'd208;
parameter bb_nph_i_i_i = 10'd209;
parameter bb_nph_i_i_i_1 = 10'd210;
parameter bb_nph_i_i_i_2 = 10'd211;
parameter bb_nph_i_i_i_3 = 10'd212;
parameter bb_nph_i_i_i_4 = 10'd213;
parameter bb_nph_i_i_i_5 = 10'd214;
parameter bb5_i_i_i = 10'd215;
parameter bb5_i_i_i_1 = 10'd216;
parameter bb5_i_i_i_2 = 10'd217;
parameter bb5_i_i_i_3 = 10'd218;
parameter bb5_i_i_i_4 = 10'd219;
parameter bb5_i_i_i_5 = 10'd220;
parameter bb5_i_i_i_6 = 10'd221;
parameter bb5_i_i_i_7 = 10'd222;
parameter bb5_i_i_i_8 = 10'd223;
parameter bb6_bb7_crit_edge_i_i_i = 10'd224;
parameter bb6_bb7_crit_edge_i_i_i_1 = 10'd225;
parameter bb7_i_i_i = 10'd226;
parameter bb7_i_i_i_1 = 10'd227;
parameter bb7_i_i_i_2 = 10'd228;
parameter bb7_i_i_i_3 = 10'd229;
parameter bb7_i_i_i_4 = 10'd230;
parameter bb8_i_i_i = 10'd231;
parameter bb10_i_i4_i = 10'd232;
parameter bb10_i_i4_i_1 = 10'd233;
parameter estimateDiv128To64_exit_i_i = 10'd234;
parameter estimateDiv128To64_exit_i_i_1 = 10'd235;
parameter estimateDiv128To64_exit_i_i_2 = 10'd236;
parameter estimateDiv128To64_exit_i_i_3 = 10'd237;
parameter bb24_i_i = 10'd238;
parameter bb24_i_i_1 = 10'd239;
parameter bb24_i_i_2 = 10'd240;
parameter bb24_i_i_3 = 10'd241;
parameter bb24_i_i_4 = 10'd242;
parameter bb24_i_i_5 = 10'd243;
parameter bb24_i_i_6 = 10'd244;
parameter bb24_i_i_7 = 10'd245;
parameter bb24_i_i_8 = 10'd246;
parameter bb24_i_i_9 = 10'd247;
parameter bb24_i_i_10 = 10'd248;
parameter bb_nph_i_i = 10'd249;
parameter bb_nph_i_i_1 = 10'd250;
parameter bb_nph_i_i_2 = 10'd251;
parameter bb_nph_i_i_3 = 10'd252;
parameter bb_nph_i_i_4 = 10'd253;
parameter bb_nph_i_i_5 = 10'd254;
parameter bb_nph_i_i_6 = 10'd255;
parameter bb_nph_i_i_7 = 10'd256;
parameter bb25_i_i = 10'd257;
parameter bb25_i_i_1 = 10'd258;
parameter bb25_i_i_2 = 10'd259;
parameter bb25_i_i_3 = 10'd260;
parameter bb25_i_i_4 = 10'd261;
parameter bb25_i_i_5 = 10'd262;
parameter bb25_i_i_6 = 10'd263;
parameter bb25_i_i_7 = 10'd264;
parameter bb26_bb27_crit_edge_i_i = 10'd265;
parameter bb27_i_i = 10'd266;
parameter bb27_i_i_1 = 10'd267;
parameter bb27_i_i_2 = 10'd268;
parameter bb27_i_i_3 = 10'd269;
parameter bb28_i_i = 10'd270;
parameter bb28_i_i_1 = 10'd271;
parameter bb28_i_i_1_call_0 = 10'd272;
parameter bb28_i_i_1_call_1 = 10'd273;
parameter float64_div_exit_i = 10'd274;
parameter float64_div_exit_i_1 = 10'd275;
parameter float64_div_exit_i_2 = 10'd276;
parameter float64_div_exit_i_3 = 10'd277;
parameter float64_div_exit_i_4 = 10'd278;
parameter bb_i5_i = 10'd279;
parameter bb_i5_i_1 = 10'd280;
parameter bb_i4_i_i = 10'd281;
parameter bb_i4_i_i_1 = 10'd282;
parameter bb1_i5_i_i = 10'd283;
parameter bb1_i5_i_i_1 = 10'd284;
parameter bb2_i6_i_i = 10'd285;
parameter bb2_i6_i_i_1 = 10'd286;
parameter bb2_i6_i_i_2 = 10'd287;
parameter bb_i14_i55_i9_i_i = 10'd288;
parameter bb_i14_i55_i9_i_i_1 = 10'd289;
parameter bb_i14_i55_i9_i_i_2 = 10'd290;
parameter float64_is_signaling_nan_exit16_i56_i10_i_i = 10'd291;
parameter float64_is_signaling_nan_exit16_i56_i10_i_i_1 = 10'd292;
parameter float64_is_signaling_nan_exit16_i56_i10_i_i_2 = 10'd293;
parameter bb_i_i59_i13_i_i = 10'd294;
parameter bb_i_i59_i13_i_i_1 = 10'd295;
parameter bb_i_i59_i13_i_i_2 = 10'd296;
parameter float64_is_signaling_nan_exit_i60_i14_i_i = 10'd297;
parameter float64_is_signaling_nan_exit_i60_i14_i_i_1 = 10'd298;
parameter float64_is_signaling_nan_exit_i60_i14_i_i_2 = 10'd299;
parameter float64_is_signaling_nan_exit_i60_i14_i_i_3 = 10'd300;
parameter bb_i61_i15_i_i = 10'd301;
parameter bb_i61_i15_i_i_1 = 10'd302;
parameter bb_i61_i15_i_i_2 = 10'd303;
parameter bb_i61_i15_i_i_3 = 10'd304;
parameter bb1_i62_i16_i_i = 10'd305;
parameter bb1_i62_i16_i_i_1 = 10'd306;
parameter bb2_i63_i17_i_i = 10'd307;
parameter bb2_i63_i17_i_i_1 = 10'd308;
parameter bb3_i65_i19_i_i = 10'd309;
parameter bb4_i23_i_i = 10'd310;
parameter bb4_i23_i_i_1 = 10'd311;
parameter bb4_i23_i_i_2 = 10'd312;
parameter bb4_i23_i_i_3 = 10'd313;
parameter bb1_i46_i24_i_i = 10'd314;
parameter bb1_i46_i24_i_i_1 = 10'd315;
parameter bb2_i49_i_i_i = 10'd316;
parameter bb2_i49_i_i_i_1 = 10'd317;
parameter bb2_i49_i_i_i_2 = 10'd318;
parameter bb2_i49_i_i_i_3 = 10'd319;
parameter bb2_i49_i_i_i_4 = 10'd320;
parameter bb2_i49_i_i_i_5 = 10'd321;
parameter bb2_i49_i_i_i_6 = 10'd322;
parameter bb4_i50_i_i_i = 10'd323;
parameter bb4_i50_i_i_i_1 = 10'd324;
parameter bb8_i25_i_i = 10'd325;
parameter bb8_i25_i_i_1 = 10'd326;
parameter bb9_i26_i_i = 10'd327;
parameter bb9_i26_i_i_1 = 10'd328;
parameter bb10_i27_i_i = 10'd329;
parameter bb10_i27_i_i_1 = 10'd330;
parameter bb11_i28_i_i = 10'd331;
parameter bb11_i28_i_i_1 = 10'd332;
parameter bb11_i28_i_i_2 = 10'd333;
parameter bb_i14_i32_i_i_i = 10'd334;
parameter bb_i14_i32_i_i_i_1 = 10'd335;
parameter bb_i14_i32_i_i_i_2 = 10'd336;
parameter float64_is_signaling_nan_exit16_i33_i_i_i = 10'd337;
parameter float64_is_signaling_nan_exit16_i33_i_i_i_1 = 10'd338;
parameter float64_is_signaling_nan_exit16_i33_i_i_i_2 = 10'd339;
parameter bb_i_i36_i_i_i = 10'd340;
parameter bb_i_i36_i_i_i_1 = 10'd341;
parameter bb_i_i36_i_i_i_2 = 10'd342;
parameter float64_is_signaling_nan_exit_i37_i_i_i = 10'd343;
parameter float64_is_signaling_nan_exit_i37_i_i_i_1 = 10'd344;
parameter float64_is_signaling_nan_exit_i37_i_i_i_2 = 10'd345;
parameter float64_is_signaling_nan_exit_i37_i_i_i_3 = 10'd346;
parameter bb_i38_i_i_i = 10'd347;
parameter bb_i38_i_i_i_1 = 10'd348;
parameter bb_i38_i_i_i_2 = 10'd349;
parameter bb_i38_i_i_i_3 = 10'd350;
parameter bb1_i39_i_i_i = 10'd351;
parameter bb1_i39_i_i_i_1 = 10'd352;
parameter bb2_i40_i_i_i = 10'd353;
parameter bb2_i40_i_i_i_1 = 10'd354;
parameter bb3_i42_i_i_i = 10'd355;
parameter bb12_i29_i_i = 10'd356;
parameter bb12_i29_i_i_1 = 10'd357;
parameter bb13_i32_i_i = 10'd358;
parameter bb13_i32_i_i_1 = 10'd359;
parameter bb13_i32_i_i_2 = 10'd360;
parameter bb13_i32_i_i_3 = 10'd361;
parameter bb13_i32_i_i_4 = 10'd362;
parameter bb1_i28_i33_i_i = 10'd363;
parameter bb1_i28_i33_i_i_1 = 10'd364;
parameter bb2_i29_i36_i_i = 10'd365;
parameter bb2_i29_i36_i_i_1 = 10'd366;
parameter bb2_i29_i36_i_i_2 = 10'd367;
parameter bb2_i29_i36_i_i_3 = 10'd368;
parameter bb2_i29_i36_i_i_4 = 10'd369;
parameter bb2_i29_i36_i_i_5 = 10'd370;
parameter bb4_i_i37_i_i = 10'd371;
parameter bb4_i_i37_i_i_1 = 10'd372;
parameter bb17_i38_i_i = 10'd373;
parameter bb17_i38_i_i_1 = 10'd374;
parameter bb18_i39_i_i = 10'd375;
parameter bb18_i39_i_i_1 = 10'd376;
parameter bb18_i39_i_i_2 = 10'd377;
parameter bb19_i_i_i = 10'd378;
parameter bb19_i_i_i_1 = 10'd379;
parameter bb19_i_i_i_2 = 10'd380;
parameter bb_i14_i_i42_i_i = 10'd381;
parameter bb_i14_i_i42_i_i_1 = 10'd382;
parameter bb_i14_i_i42_i_i_2 = 10'd383;
parameter float64_is_signaling_nan_exit16_i_i43_i_i = 10'd384;
parameter float64_is_signaling_nan_exit16_i_i43_i_i_1 = 10'd385;
parameter float64_is_signaling_nan_exit16_i_i43_i_i_2 = 10'd386;
parameter bb_i_i_i46_i_i = 10'd387;
parameter bb_i_i_i46_i_i_1 = 10'd388;
parameter bb_i_i_i46_i_i_2 = 10'd389;
parameter float64_is_signaling_nan_exit_i_i47_i_i = 10'd390;
parameter float64_is_signaling_nan_exit_i_i47_i_i_1 = 10'd391;
parameter float64_is_signaling_nan_exit_i_i47_i_i_2 = 10'd392;
parameter float64_is_signaling_nan_exit_i_i47_i_i_3 = 10'd393;
parameter bb_i_i48_i_i = 10'd394;
parameter bb_i_i48_i_i_1 = 10'd395;
parameter bb_i_i48_i_i_2 = 10'd396;
parameter bb_i_i48_i_i_3 = 10'd397;
parameter bb1_i_i49_i_i = 10'd398;
parameter bb1_i_i49_i_i_1 = 10'd399;
parameter bb2_i_i50_i_i = 10'd400;
parameter bb2_i_i50_i_i_1 = 10'd401;
parameter bb3_i_i52_i_i = 10'd402;
parameter bb21_i_i_i = 10'd403;
parameter bb21_i_i_i_1 = 10'd404;
parameter bb22_i_i_i = 10'd405;
parameter bb22_i_i_i_1 = 10'd406;
parameter bb23_i_i_i = 10'd407;
parameter bb24_i57_i_i = 10'd408;
parameter bb24_i57_i_i_1 = 10'd409;
parameter bb24_i57_i_i_2 = 10'd410;
parameter bb24_i57_i_i_3 = 10'd411;
parameter bb24_i57_i_i_4 = 10'd412;
parameter bb24_i57_i_i_5 = 10'd413;
parameter bb25_i_i_i = 10'd414;
parameter roundAndPack_i_i_i = 10'd415;
parameter roundAndPack_i_i_i_1 = 10'd416;
parameter roundAndPack_i_i_i_1_call_0 = 10'd417;
parameter roundAndPack_i_i_i_1_call_1 = 10'd418;
parameter bb1_i6_i = 10'd419;
parameter bb1_i6_i_1 = 10'd420;
parameter bb_i_i7_i = 10'd421;
parameter bb_i_i7_i_1 = 10'd422;
parameter bb1_i_i8_i = 10'd423;
parameter bb2_i_i9_i = 10'd424;
parameter bb2_i_i9_i_1 = 10'd425;
parameter bb2_i_i9_i_2 = 10'd426;
parameter bb3_i_i10_i = 10'd427;
parameter bb3_i_i10_i_1 = 10'd428;
parameter bb3_i_i10_i_2 = 10'd429;
parameter bb_i14_i55_i_i_i = 10'd430;
parameter bb_i14_i55_i_i_i_1 = 10'd431;
parameter bb_i14_i55_i_i_i_2 = 10'd432;
parameter float64_is_signaling_nan_exit16_i56_i_i_i = 10'd433;
parameter float64_is_signaling_nan_exit16_i56_i_i_i_1 = 10'd434;
parameter float64_is_signaling_nan_exit16_i56_i_i_i_2 = 10'd435;
parameter bb_i_i59_i_i_i = 10'd436;
parameter bb_i_i59_i_i_i_1 = 10'd437;
parameter bb_i_i59_i_i_i_2 = 10'd438;
parameter float64_is_signaling_nan_exit_i60_i_i_i = 10'd439;
parameter float64_is_signaling_nan_exit_i60_i_i_i_1 = 10'd440;
parameter float64_is_signaling_nan_exit_i60_i_i_i_2 = 10'd441;
parameter float64_is_signaling_nan_exit_i60_i_i_i_3 = 10'd442;
parameter bb_i61_i_i_i = 10'd443;
parameter bb_i61_i_i_i_1 = 10'd444;
parameter bb_i61_i_i_i_2 = 10'd445;
parameter bb_i61_i_i_i_3 = 10'd446;
parameter bb1_i62_i_i_i = 10'd447;
parameter bb1_i62_i_i_i_1 = 10'd448;
parameter bb2_i63_i_i_i = 10'd449;
parameter bb2_i63_i_i_i_1 = 10'd450;
parameter bb3_i65_i_i_i = 10'd451;
parameter bb4_i_i11_i = 10'd452;
parameter bb4_i_i11_i_1 = 10'd453;
parameter bb4_i_i11_i_2 = 10'd454;
parameter bb4_i_i11_i_3 = 10'd455;
parameter bb6_i_i_i = 10'd456;
parameter bb7_i_i12_i = 10'd457;
parameter bb7_i_i12_i_1 = 10'd458;
parameter bb8_i_i13_i = 10'd459;
parameter bb8_i_i13_i_1 = 10'd460;
parameter bExpBigger_i_i_i = 10'd461;
parameter bExpBigger_i_i_i_1 = 10'd462;
parameter bb10_i_i14_i = 10'd463;
parameter bb10_i_i14_i_1 = 10'd464;
parameter bb11_i_i_i = 10'd465;
parameter bb11_i_i_i_1 = 10'd466;
parameter bb11_i_i_i_2 = 10'd467;
parameter bb_i14_i39_i_i_i = 10'd468;
parameter bb_i14_i39_i_i_i_1 = 10'd469;
parameter bb_i14_i39_i_i_i_2 = 10'd470;
parameter float64_is_signaling_nan_exit16_i40_i_i_i = 10'd471;
parameter float64_is_signaling_nan_exit16_i40_i_i_i_1 = 10'd472;
parameter float64_is_signaling_nan_exit16_i40_i_i_i_2 = 10'd473;
parameter bb_i_i43_i_i_i = 10'd474;
parameter bb_i_i43_i_i_i_1 = 10'd475;
parameter bb_i_i43_i_i_i_2 = 10'd476;
parameter float64_is_signaling_nan_exit_i44_i_i_i = 10'd477;
parameter float64_is_signaling_nan_exit_i44_i_i_i_1 = 10'd478;
parameter float64_is_signaling_nan_exit_i44_i_i_i_2 = 10'd479;
parameter float64_is_signaling_nan_exit_i44_i_i_i_3 = 10'd480;
parameter bb_i45_i_i_i = 10'd481;
parameter bb_i45_i_i_i_1 = 10'd482;
parameter bb_i45_i_i_i_2 = 10'd483;
parameter bb_i45_i_i_i_3 = 10'd484;
parameter bb1_i46_i_i_i = 10'd485;
parameter bb1_i46_i_i_i_1 = 10'd486;
parameter bb2_i47_i_i_i = 10'd487;
parameter bb2_i47_i_i_i_1 = 10'd488;
parameter bb3_i49_i_i_i = 10'd489;
parameter bb12_i_i_i = 10'd490;
parameter bb12_i_i_i_1 = 10'd491;
parameter bb12_i_i_i_2 = 10'd492;
parameter bb12_i_i_i_3 = 10'd493;
parameter bb13_i_i_i = 10'd494;
parameter bb13_i_i_i_1 = 10'd495;
parameter bb13_i_i_i_2 = 10'd496;
parameter bb13_i_i_i_3 = 10'd497;
parameter bb13_i_i_i_4 = 10'd498;
parameter bb1_i30_i_i_i = 10'd499;
parameter bb1_i30_i_i_i_1 = 10'd500;
parameter bb2_i33_i_i_i = 10'd501;
parameter bb2_i33_i_i_i_1 = 10'd502;
parameter bb2_i33_i_i_i_2 = 10'd503;
parameter bb2_i33_i_i_i_3 = 10'd504;
parameter bb2_i33_i_i_i_4 = 10'd505;
parameter bb2_i33_i_i_i_5 = 10'd506;
parameter bb4_i34_i_i_i = 10'd507;
parameter bb4_i34_i_i_i_1 = 10'd508;
parameter shift64RightJamming_exit36_i_i_i = 10'd509;
parameter bBigger_i_i_i = 10'd510;
parameter bBigger_i_i_i_1 = 10'd511;
parameter aExpBigger_i_i_i = 10'd512;
parameter aExpBigger_i_i_i_1 = 10'd513;
parameter bb17_i_i_i = 10'd514;
parameter bb17_i_i_i_1 = 10'd515;
parameter bb18_i_i_i = 10'd516;
parameter bb18_i_i_i_1 = 10'd517;
parameter bb18_i_i_i_2 = 10'd518;
parameter bb_i14_i_i_i_i = 10'd519;
parameter bb_i14_i_i_i_i_1 = 10'd520;
parameter bb_i14_i_i_i_i_2 = 10'd521;
parameter float64_is_signaling_nan_exit16_i_i_i_i = 10'd522;
parameter float64_is_signaling_nan_exit16_i_i_i_i_1 = 10'd523;
parameter float64_is_signaling_nan_exit16_i_i_i_i_2 = 10'd524;
parameter bb_i_i27_i_i_i = 10'd525;
parameter bb_i_i27_i_i_i_1 = 10'd526;
parameter bb_i_i27_i_i_i_2 = 10'd527;
parameter float64_is_signaling_nan_exit_i_i_i_i = 10'd528;
parameter float64_is_signaling_nan_exit_i_i_i_i_1 = 10'd529;
parameter float64_is_signaling_nan_exit_i_i_i_i_2 = 10'd530;
parameter float64_is_signaling_nan_exit_i_i_i_i_3 = 10'd531;
parameter bb_i_i_i15_i = 10'd532;
parameter bb_i_i_i15_i_1 = 10'd533;
parameter bb_i_i_i15_i_2 = 10'd534;
parameter bb_i_i_i15_i_3 = 10'd535;
parameter bb1_i28_i_i_i = 10'd536;
parameter bb1_i28_i_i_i_1 = 10'd537;
parameter bb2_i29_i_i_i = 10'd538;
parameter bb2_i29_i_i_i_1 = 10'd539;
parameter bb3_i_i_i_i = 10'd540;
parameter bb20_i_i_i = 10'd541;
parameter bb20_i_i_i_1 = 10'd542;
parameter bb20_i_i_i_2 = 10'd543;
parameter bb20_i_i_i_3 = 10'd544;
parameter bb1_i_i_i16_i = 10'd545;
parameter bb1_i_i_i16_i_1 = 10'd546;
parameter bb2_i_i_i_i = 10'd547;
parameter bb2_i_i_i_i_1 = 10'd548;
parameter bb2_i_i_i_i_2 = 10'd549;
parameter bb2_i_i_i_i_3 = 10'd550;
parameter bb2_i_i_i_i_4 = 10'd551;
parameter bb2_i_i_i_i_5 = 10'd552;
parameter bb2_i_i_i_i_6 = 10'd553;
parameter bb4_i_i_i_i = 10'd554;
parameter bb4_i_i_i_i_1 = 10'd555;
parameter shift64RightJamming_exit_i_i_i = 10'd556;
parameter aBigger_i_i_i = 10'd557;
parameter aBigger_i_i_i_1 = 10'd558;
parameter normalizeRoundAndPack_i_i_i = 10'd559;
parameter normalizeRoundAndPack_i_i_i_1 = 10'd560;
parameter normalizeRoundAndPack_i_i_i_2 = 10'd561;
parameter bb_i_i_i_i_i = 10'd562;
parameter bb1_i_i_i_i_i = 10'd563;
parameter bb1_i_i_i_i_i_1 = 10'd564;
parameter normalizeRoundAndPackFloat64_exit_i_i_i = 10'd565;
parameter normalizeRoundAndPackFloat64_exit_i_i_i_1 = 10'd566;
parameter normalizeRoundAndPackFloat64_exit_i_i_i_2 = 10'd567;
parameter normalizeRoundAndPackFloat64_exit_i_i_i_3 = 10'd568;
parameter normalizeRoundAndPackFloat64_exit_i_i_i_4 = 10'd569;
parameter normalizeRoundAndPackFloat64_exit_i_i_i_5 = 10'd570;
parameter normalizeRoundAndPackFloat64_exit_i_i_i_6 = 10'd571;
parameter normalizeRoundAndPackFloat64_exit_i_i_i_7 = 10'd572;
parameter normalizeRoundAndPackFloat64_exit_i_i_i_8 = 10'd573;
parameter normalizeRoundAndPackFloat64_exit_i_i_i_9 = 10'd574;
parameter normalizeRoundAndPackFloat64_exit_i_i_i_10 = 10'd575;
parameter normalizeRoundAndPackFloat64_exit_i_i_i_11 = 10'd576;
parameter normalizeRoundAndPackFloat64_exit_i_i_i_12 = 10'd577;
parameter normalizeRoundAndPackFloat64_exit_i_i_i_13 = 10'd578;
parameter normalizeRoundAndPackFloat64_exit_i_i_i_13_call_0 = 10'd579;
parameter normalizeRoundAndPackFloat64_exit_i_i_i_13_call_1 = 10'd580;
parameter float64_add_exit_i = 10'd581;
parameter float64_add_exit_i_1 = 10'd582;
parameter float64_add_exit_i_2 = 10'd583;
parameter bb2_i_i_i = 10'd584;
parameter bb2_i_i_i_1 = 10'd585;
parameter bb2_i_i_i_2 = 10'd586;
parameter bb3_i_i_i = 10'd587;
parameter bb3_i_i_i_1 = 10'd588;
parameter bb3_i_i_i_2 = 10'd589;
parameter bb3_i_i_i_3 = 10'd590;
parameter bb10_i_i_i = 10'd591;
parameter bb10_i_i_i_1 = 10'd592;
parameter sin_exit = 10'd593;
parameter sin_exit_1 = 10'd594;
parameter sin_exit_2 = 10'd595;
parameter sin_exit_3 = 10'd596;
parameter sin_exit_4 = 10'd597;
parameter bb2 = 10'd598;
reg [31:0] load_noop1;
reg [31:0] load_noop2;
reg [63:0] bSig_2_i_i_i;
reg [31:0] aExp_1_i_i_i;
reg [63:0] var446;
reg [31:0] zExp_0_i_i_i;
reg [63:0] zSig_0_i_i_i;
reg [31:0] zSign_addr_0_i_i_i;
reg var447;
reg [31:0] extract_t_i_i_i_i_i;
reg [63:0] var448;
reg [31:0] extract_t4_i_i_i_i_i;
reg [31:0] shiftCount_0_i_i_i_i17_i;
reg [31:0] a_addr_0_off0_i_i_i_i_i;
reg [31:0] var450;
reg var451;
reg [31:0] _a_i_i_i_i_i_i;
reg [31:0] shiftCount_0_i_i_i_i_i_i;
reg var452;
reg [31:0] var453;
reg [31:0] var454;
reg [31:0] shiftCount_1_i_i_i_i_i_i;
reg [31:0] a_addr_1_i_i_i_i_i_i;
reg [31:0] var455;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] var456;
reg [31:0] var457;
reg [31:0] var458;
reg [31:0] var459;
reg [63:0] _cast_i_i_i_i;
reg [63:0] var461;
reg [31:0] var449;
reg [31:0] var460;
reg [63:0] var462;
reg [63:0] var237;
reg [31:0] var463;
reg [63:0] var464;
reg [63:0] var465;
reg var466;
reg [63:0] var467;
reg var468;
reg [31:0] var469;
reg [31:0] var470;
reg or_cond_i;
reg [31:0] indvar_next_i;
reg [63:0] var473;
reg var474;
reg [31:0] var475;
reg [31:0] var476;
reg [63:0] var471;
reg [31:0] var472;
reg exitcond;
reg [31:0] i_04;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] scevgep;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] scevgep9;
reg [63:0] var0;
reg [63:0] var1;
reg [63:0] var2;
reg [31:0] indvar_i;
reg [31:0] inc_0_i;
reg [63:0] diff_0_i;
reg [63:0] app_0_i;
reg [31:0] tmp_i;
reg [31:0] tmp5_i;
reg [31:0] var3;
reg [31:0] var4;
reg [31:0] var5;
reg var6;
reg [31:0] a_lobit_i_i;
reg var9;
reg [31:0] var8;
reg [31:0] iftmp_44_0_i_i;
reg [31:0] var12;
reg var13;
reg [31:0] _a_i_i_i;
reg [31:0] shiftCount_0_i_i_i;
reg var15;
reg [31:0] var16;
reg [31:0] var17;
reg [31:0] shiftCount_1_i_i_i;
reg [31:0] a_addr_1_i_i_i;
reg [31:0] var18;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] var19;
reg [31:0] var20;
reg [31:0] var21;
reg [31:0] var22;
reg [63:0] var14;
reg [63:0] _cast_i_i;
reg [63:0] var25;
reg [31:0] var23;
reg [63:0] var10;
reg [63:0] var11;
reg [63:0] var24;
reg [63:0] var26;
reg [63:0] var27;
reg [63:0] var28;
reg [63:0] var7;
reg [63:0] var29;
reg [63:0] var30;
reg [63:0] var31;
reg [31:0] var35;
reg [31:0] var38;
reg [63:0] var32;
reg [63:0] var33;
reg [31:0] var36;
reg [31:0] var39;
reg [63:0] var34;
reg [63:0] var37;
reg [31:0] var40;
reg var41;
reg var42;
reg [63:0] var43;
reg var44;
reg [63:0] var46;
reg not__i12_i63_i_i;
reg [31:0] retval_i13_i64_i_i;
reg [31:0] var45;
reg [63:0] var47;
reg var49;
reg [63:0] var48;
reg var50;
reg [31:0] var124;
reg [31:0] var125;
reg [31:0] var126;
reg [31:0] var127;
reg [63:0] _cast_i41_i_i;
reg [63:0] var129;
reg [31:0] var128;
reg [63:0] bSig_0_i_i;
reg [31:0] bExp_0_i_i;
reg var130;
reg var131;
reg [63:0] var132;
reg var133;
reg [31:0] extract_t_i_i_i_i;
reg [63:0] var134;
reg [31:0] extract_t4_i_i_i_i;
reg [31:0] shiftCount_0_i_i_i_i;
reg [31:0] a_addr_0_off0_i_i_i_i;
reg [31:0] var135;
reg [31:0] main_result_08;
reg [63:0] var52;
reg not__i_i67_i_i;
reg [31:0] retval_i_i68_i_i;
reg [31:0] var51;
reg [63:0] var53;
reg [63:0] var54;
reg [31:0] var55;
reg var56;
reg [31:0] var57;
reg [31:0] var58;
reg var59;
reg var61;
reg [63:0] iftmp_34_0_i74_i_i;
reg var62;
reg var63;
reg [63:0] var64;
reg var65;
reg [63:0] var67;
reg not__i12_i47_i_i;
reg [31:0] retval_i13_i48_i_i;
reg [31:0] var66;
reg [63:0] var68;
reg var70;
reg [63:0] var69;
reg var71;
reg [63:0] var73;
reg not__i_i51_i_i;
reg [31:0] retval_i_i52_i_i;
reg [31:0] var72;
reg [63:0] var74;
reg [63:0] var75;
reg [31:0] var76;
reg var77;
reg [31:0] var78;
reg [31:0] var79;
reg var80;
reg var81;
reg [63:0] iftmp_34_0_i58_i_i;
reg [31:0] var82;
reg [31:0] var83;
reg [63:0] var84;
reg [63:0] var85;
reg var86;
reg [63:0] var87;
reg var88;
reg [63:0] var90;
reg not__i12_i_i_i;
reg [31:0] retval_i13_i_i_i;
reg [31:0] var89;
reg [63:0] var91;
reg var93;
reg [63:0] var92;
reg var94;
reg [63:0] var96;
reg not__i_i_i_i;
reg [31:0] retval_i_i_i_i;
reg [31:0] var95;
reg [63:0] var97;
reg [63:0] var98;
reg [31:0] var99;
reg var100;
reg [31:0] var101;
reg [31:0] var102;
reg var103;
reg var104;
reg [63:0] iftmp_34_0_i_i_i;
reg [63:0] var105;
reg var106;
reg [63:0] var107;
reg [63:0] var109;
reg var110;
reg [31:0] var108;
reg [31:0] var111;
reg [31:0] var112;
reg [63:0] var113;
reg [63:0] var114;
reg var115;
reg [31:0] extract_t_i_i31_i_i;
reg [63:0] var116;
reg [31:0] extract_t4_i_i33_i_i;
reg [31:0] shiftCount_0_i_i35_i_i;
reg [31:0] a_addr_0_off0_i_i36_i_i;
reg [31:0] var117;
reg var118;
reg [31:0] _a_i_i_i37_i_i;
reg [31:0] shiftCount_0_i_i_i38_i_i;
reg var119;
reg [31:0] var120;
reg [31:0] var121;
reg [31:0] shiftCount_1_i_i_i39_i_i;
reg [31:0] a_addr_1_i_i_i40_i_i;
reg [31:0] var122;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] var123;
reg [63:0] var407;
reg [63:0] z_0_i35_i_i_i;
reg [63:0] var408;
reg [63:0] aSig_1_i_i_i;
reg [63:0] bSig_0_i_i_i;
reg [31:0] bExp_1_i_i_i;
reg [63:0] var410;
reg [31:0] var409;
reg var411;
reg var412;
reg [63:0] var413;
reg var414;
reg [63:0] var416;
reg not__i12_i_i_i_i;
reg [31:0] retval_i13_i_i_i_i;
reg [31:0] var415;
reg [63:0] var417;
reg var419;
reg [63:0] var418;
reg var420;
reg [63:0] var422;
reg not__i_i_i_i_i;
reg [31:0] retval_i_i_i_i_i;
reg [31:0] var421;
reg [63:0] var423;
reg [63:0] var424;
reg [31:0] var425;
reg var426;
reg [31:0] var427;
reg [31:0] var428;
reg var429;
reg var430;
reg [63:0] iftmp_34_0_i_i_i_i;
reg var431;
reg [31:0] var432;
reg [63:0] var433;
reg [63:0] bSig_1_i_i_i;
reg var136;
reg [31:0] _a_i_i_i_i_i;
reg [31:0] shiftCount_0_i_i_i_i_i;
reg var137;
reg [31:0] var138;
reg [31:0] var139;
reg [31:0] shiftCount_1_i_i_i_i_i;
reg [31:0] a_addr_1_i_i_i_i_i;
reg [31:0] var140;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] var141;
reg [31:0] var142;
reg [31:0] var143;
reg [31:0] var144;
reg [31:0] var145;
reg [63:0] _cast_i_i_i;
reg [63:0] var147;
reg [31:0] var146;
reg [63:0] aSig_1_i_i;
reg [31:0] aExp_0_i_i;
reg [63:0] var149;
reg [63:0] var152;
reg [63:0] var148;
reg [63:0] var150;
reg [63:0] var153;
reg var154;
reg [63:0] var155;
reg [63:0] var156;
reg [63:0] aSig_0_i_i;
reg [31:0] zExp_0_v_i_i;
reg [31:0] var151;
reg [31:0] zExp_0_i_i;
reg var157;
reg [63:0] var159;
reg [63:0] var160;
reg var161;
reg [63:0] var162;
reg [63:0] var163;
reg [63:0] iftmp_18_0_i_i_i;
reg [63:0] var165;
reg [63:0] var164;
reg [63:0] var166;
reg [63:0] var167;
reg [63:0] var168;
reg [63:0] var169;
reg [63:0] var170;
reg var171;
reg [63:0] _neg_i_i_i_i;
reg [63:0] _neg2_i_i_i;
reg [63:0] var172;
reg [63:0] var173;
reg var174;
reg [31:0] bSig_0130_i_i;
reg [31:0] tmp121_i_i;
reg [63:0] tmp122_i_i;
reg [63:0] tmp123_i_i;
reg [63:0] tmp124_i_i;
reg [63:0] tmp125_i_i;
reg [63:0] tmp126_i_i;
reg [63:0] var175;
reg [63:0] rem0_05_i_i_i;
reg [63:0] tmp117_i_i;
reg [63:0] tmp118_i_i;
reg [63:0] tmp23_i_i_i;
reg [63:0] rem1_04_i_i_i;
reg var177;
reg [63:0] var178;
reg [63:0] var176;
reg [63:0] var179;
reg var180;
reg [63:0] indvar_next_i_i_i;
reg [63:0] tmp_i_i_i;
reg [63:0] tmp11_i_i_i;
reg [63:0] tmp12_i_i_i;
reg [63:0] z_0_lcssa_i_i_i;
reg [63:0] rem0_0_lcssa_i_i_i;
reg [63:0] rem1_0_lcssa_i_i_i;
reg [63:0] var181;
reg [63:0] var182;
reg [63:0] var183;
reg var184;
reg [63:0] var185;
reg [63:0] iftmp_27_0_i_i_i;
reg [63:0] var186;
reg [63:0] var158;
reg [63:0] var187;
reg var188;
reg [63:0] var189;
reg [63:0] var190;
reg [63:0] var191;
reg [63:0] var192;
reg [63:0] var193;
reg [63:0] var194;
reg [63:0] var195;
reg [63:0] var196;
reg [63:0] var197;
reg var198;
reg [63:0] iftmp_17_0_i_i_i;
reg [63:0] var199;
reg [63:0] var202;
reg [63:0] var200;
reg [63:0] var201;
reg var203;
reg [63:0] var204;
reg var205;
reg [63:0] _neg_i_i_i;
reg [63:0] _neg83_i_i;
reg [63:0] _neg82_i_i;
reg [63:0] _neg84_i_i;
reg [63:0] var206;
reg [63:0] var207;
reg var208;
reg [63:0] tmp91_i_i;
reg [31:0] bSig_0129_i_i;
reg [31:0] tmp97_i_i;
reg [63:0] tmp98_i_i;
reg [63:0] tmp99_i_i;
reg [63:0] tmp101_i_i;
reg [63:0] tmp103_i_i;
reg [63:0] tmp105_i_i;
reg [63:0] tmp106_i_i;
reg [63:0] tmp107_i_i;
reg [63:0] tmp108_i_i;
reg [63:0] tmp111_i_i;
reg [63:0] tmp112_i_i;
reg [63:0] tmp114_i_i;
reg [63:0] indvar_i_i;
reg [63:0] rem1_087_i_i;
reg [63:0] rem0_085_i_i;
reg [63:0] tmp93_i_i;
reg [63:0] tmp115_i_i;
reg [63:0] var209;
reg var210;
reg [63:0] var211;
reg [63:0] var212;
reg var213;
reg [63:0] indvar_next_i_i;
reg [63:0] tmp92_i_i;
reg [63:0] tmp109_i_i;
reg [63:0] zSig_0_lcssa_i_i;
reg [63:0] rem1_0_lcssa_i_i;
reg var214;
reg [63:0] var215;
reg [63:0] var216;
reg [63:0] zSig_1_i_i;
reg [63:0] var217;
reg [63:0] var60;
reg [63:0] var218;
reg [31:0] var220;
reg [63:0] var221;
reg [31:0] var224;
reg var227;
reg [63:0] var219;
reg [31:0] var222;
reg [31:0] var225;
reg [63:0] var223;
reg [31:0] var226;
reg [31:0] var228;
reg [31:0] var229;
reg [63:0] var230;
reg [63:0] var233;
reg [63:0] var231;
reg [63:0] var234;
reg var232;
reg var235;
reg var236;
reg [63:0] var238;
reg var239;
reg [63:0] var241;
reg not__i12_i53_i7_i_i;
reg [31:0] retval_i13_i54_i8_i_i;
reg [31:0] var240;
reg [63:0] var242;
reg var244;
reg [63:0] var243;
reg var245;
reg [63:0] var247;
reg not__i_i57_i11_i_i;
reg [31:0] retval_i_i58_i12_i_i;
reg [31:0] var246;
reg [63:0] var248;
reg [63:0] var249;
reg [31:0] var250;
reg var251;
reg [31:0] var252;
reg [31:0] var253;
reg var254;
reg var255;
reg [63:0] iftmp_34_0_i64_i18_i_i;
reg var256;
reg [31:0] var257;
reg [63:0] var258;
reg [63:0] bSig_0_i21_i_i;
reg [31:0] expDiff_0_i22_i_i;
reg var259;
reg var260;
reg [63:0] _cast_i47_i_i_i;
reg [63:0] var262;
reg [31:0] var261;
reg [31:0] var263;
reg [63:0] _cast3_i48_i_i_i;
reg [63:0] var264;
reg var265;
reg [63:0] var266;
reg [63:0] var267;
reg var268;
reg [63:0] var269;
reg var270;
reg var271;
reg var272;
reg [63:0] var273;
reg var274;
reg [63:0] var276;
reg not__i12_i30_i_i_i;
reg [31:0] retval_i13_i31_i_i_i;
reg [31:0] var275;
reg [63:0] var277;
reg var279;
reg [63:0] var278;
reg var280;
reg [63:0] var282;
reg not__i_i34_i_i_i;
reg [31:0] retval_i_i35_i_i_i;
reg [31:0] var281;
reg [63:0] var283;
reg [63:0] var284;
reg [31:0] var285;
reg var286;
reg [31:0] var287;
reg [31:0] var288;
reg var289;
reg var290;
reg [63:0] iftmp_34_0_i41_i_i_i;
reg [63:0] var291;
reg [63:0] var292;
reg var293;
reg [63:0] var294;
reg [63:0] aSig_0_i30_i_i;
reg [31:0] var295;
reg [31:0] expDiff_1_i31_i_i;
reg [31:0] var296;
reg var297;
reg var298;
reg [63:0] _cast_i_i34_i_i;
reg [63:0] var300;
reg [31:0] var299;
reg [63:0] _cast3_i_i35_i_i;
reg [63:0] var301;
reg var302;
reg [63:0] var303;
reg [63:0] var304;
reg var305;
reg [63:0] var306;
reg var307;
reg [63:0] var308;
reg var309;
reg [63:0] var310;
reg var311;
reg [63:0] var313;
reg not__i12_i_i40_i_i;
reg [31:0] retval_i13_i_i41_i_i;
reg [31:0] var312;
reg [63:0] var314;
reg var316;
reg [63:0] var315;
reg var317;
reg [63:0] var319;
reg not__i_i_i44_i_i;
reg [31:0] retval_i_i_i45_i_i;
reg [31:0] var318;
reg [63:0] var320;
reg [63:0] var321;
reg [31:0] var322;
reg var323;
reg [31:0] var324;
reg [31:0] var325;
reg var326;
reg var327;
reg [63:0] iftmp_34_0_i_i51_i_i;
reg var328;
reg [63:0] var329;
reg [63:0] var330;
reg [63:0] var331;
reg [63:0] var332;
reg [63:0] var333;
reg [63:0] aSig_1_i54_i_i;
reg [63:0] bSig_1_i55_i_i;
reg [31:0] zExp_0_i56_i_i;
reg [63:0] var334;
reg [63:0] var336;
reg [63:0] var337;
reg [31:0] var335;
reg var338;
reg [63:0] __i_i_i;
reg [63:0] zSig_0_i58_i_i;
reg [31:0] zExp_1_i_i_i;
reg [63:0] var339;
reg [63:0] var340;
reg [63:0] var343;
reg [63:0] var341;
reg [63:0] var344;
reg var342;
reg var345;
reg [63:0] var346;
reg var347;
reg [63:0] var348;
reg var349;
reg [63:0] var351;
reg not__i12_i53_i_i_i;
reg [31:0] retval_i13_i54_i_i_i;
reg [31:0] var350;
reg [63:0] var352;
reg var354;
reg [63:0] var353;
reg var355;
reg [63:0] var357;
reg not__i_i57_i_i_i;
reg [31:0] retval_i_i58_i_i_i;
reg [31:0] var356;
reg [63:0] var358;
reg [63:0] var359;
reg [31:0] var360;
reg var361;
reg [31:0] var362;
reg [31:0] var363;
reg var364;
reg var365;
reg [63:0] iftmp_34_0_i64_i_i_i;
reg [31:0] var366;
reg [31:0] var367;
reg [31:0] bExp_0_i_i_i;
reg [31:0] aExp_0_i_i_i;
reg var368;
reg var369;
reg var370;
reg var371;
reg [63:0] var372;
reg var373;
reg [63:0] var375;
reg not__i12_i37_i_i_i;
reg [31:0] retval_i13_i38_i_i_i;
reg [31:0] var374;
reg [63:0] var376;
reg var378;
reg [63:0] var377;
reg var379;
reg [63:0] var381;
reg not__i_i41_i_i_i;
reg [31:0] retval_i_i42_i_i_i;
reg [31:0] var380;
reg [63:0] var382;
reg [63:0] var383;
reg [31:0] var384;
reg var385;
reg [31:0] var386;
reg [31:0] var387;
reg var388;
reg var389;
reg [63:0] iftmp_34_0_i48_i_i_i;
reg [31:0] var390;
reg [63:0] var391;
reg [63:0] var392;
reg [63:0] var393;
reg var394;
reg [63:0] var395;
reg [63:0] aSig_0_i_i_i;
reg [31:0] var396;
reg [31:0] expDiff_0_i_i_i;
reg [31:0] var397;
reg var398;
reg var399;
reg [63:0] _cast_i31_i_i_i;
reg [63:0] var401;
reg [31:0] var400;
reg [63:0] _cast3_i32_i_i_i;
reg [63:0] var402;
reg var403;
reg [63:0] var404;
reg [63:0] var405;
reg var406;
reg [31:0] expDiff_1_i_i_i;
reg var434;
reg var435;
reg [63:0] _cast_i26_i_i_i;
reg [63:0] var437;
reg [31:0] var436;
reg [31:0] var438;
reg [63:0] _cast3_i_i_i_i;
reg [63:0] var439;
reg var440;
reg [63:0] var441;
reg [63:0] var442;
reg var443;
reg [63:0] var444;
reg [63:0] z_0_i_i_i_i;
reg [63:0] var445;
reg [63:0] aSig_2_i_i_i;
reg [31:0] load_noop3;
reg [31:0] load_noop4;
reg [63:0] load_noop;
reg [31:0] load_noop17;
reg [63:0] load_noop18;
reg [31:0] load_noop5;
reg [31:0] load_noop6;
reg [31:0] load_noop7;
reg [31:0] load_noop8;
reg [31:0] load_noop9;
reg [31:0] load_noop10;
reg [31:0] load_noop11;
reg [31:0] load_noop12;
reg [31:0] load_noop13;
reg [31:0] load_noop14;
reg [31:0] load_noop15;
reg [31:0] load_noop16;
always @(posedge clk)
if (reset)
cur_state = Wait;
else
case(cur_state)
Wait:
begin
finish = 0;
if (start == 1)
cur_state = bb_nph;
else
cur_state = Wait;
end
bb_nph:
begin
/* br label %bb*/
main_result_08 = 32'd0; /* for PHI node */
i_04 = 32'd0; /* for PHI node */
cur_state = bb;
end
bb:
begin
/* %main_result.08 = phi i32 [ 0, %bb.nph ], [ %477, %sin.exit_4 ] ; <i32> [#uses=1]*/
/* %i.04 = phi i32 [ 0, %bb.nph ], [ %473, %sin.exit_4 ] ; <i32> [#uses=3]*/
/* br label %bb_1*/
cur_state = bb_1;
end
bb_1:
begin
/* %scevgep = getelementptr [36 x i64]* @test_in, i32 0, i32 %i.04 ; <i64*> [#uses=1]*/
scevgep = {`TAG_test_in, 32'b0} + ((i_04 + 36*(32'd0)) << 3);
/* %scevgep9 = getelementptr [36 x i64]* @test_out, i32 0, i32 %i.04 ; <i64*> [#uses=1]*/
scevgep9 = {`TAG_test_out, 32'b0} + ((i_04 + 36*(32'd0)) << 3);
/* br label %bb_2*/
cur_state = bb_2;
end
bb_2:
begin
/* %0 = load i64* %scevgep, align 8 ; <i64> [#uses=1]*/
/* br label %bb_3*/
cur_state = bb_3;
end
bb_3:
begin
var0 = memory_controller_out[63:0];
/* %load_noop = add i64 %0, 0 ; <i64> [#uses=5]*/
load_noop = var0 + 64'd0;
/* br label %bb_4*/
cur_state = bb_4;
end
bb_4:
begin
/* %1 = tail call fastcc i64 @float64_mul(i64 %load_noop, i64 %load_noop) nounwind ; <i64> [#uses=1]*/
float64_mul_start = 1;
/* Argument: %load_noop = add i64 %0, 0 ; <i64> [#uses=5]*/
float64_mul_a = load_noop;
/* Argument: %load_noop = add i64 %0, 0 ; <i64> [#uses=5]*/
float64_mul_b = load_noop;
cur_state = bb_4_call_0;
end
bb_4_call_0:
begin
float64_mul_start = 0;
if (float64_mul_finish == 1)
begin
var1 = float64_mul_return_val;
cur_state = bb_4_call_1;
end
else
cur_state = bb_4_call_0;
end
bb_4_call_1:
begin
/* br label %bb_5*/
cur_state = bb_5;
end
bb_5:
begin
/* %2 = xor i64 %1, -9223372036854775808 ; <i64> [#uses=1]*/
var2 = var1 ^ -64'd9223372036854775808;
/* br label %bb.i*/
indvar_i = 32'd0; /* for PHI node */
inc_0_i = 32'd1; /* for PHI node */
diff_0_i = load_noop; /* for PHI node */
app_0_i = load_noop; /* for PHI node */
cur_state = bb_i;
end
bb_i:
begin
/* %indvar.i = phi i32 [ %indvar.next.i, %bb10.i.i.i_1 ], [ 0, %bb_5 ] ; <i32> [#uses=2]*/
/* %inc.0.i = phi i32 [ %463, %bb10.i.i.i_1 ], [ 1, %bb_5 ] ; <i32> [#uses=2]*/
/* %diff.0.i = phi i64 [ %217, %bb10.i.i.i_1 ], [ %load_noop, %bb_5 ] ; <i64> [#uses=1]*/
/* %app.0.i = phi i64 [ %462, %bb10.i.i.i_1 ], [ %load_noop, %bb_5 ] ; <i64> [#uses=27]*/
/* br label %bb.i_1*/
cur_state = bb_i_1;
end
bb_i_1:
begin
/* %tmp.i = shl i32 %indvar.i, 1 ; <i32> [#uses=1]*/
tmp_i = indvar_i <<< (32'd1 % 32);
/* %3 = shl i32 %inc.0.i, 1 ; <i32> [#uses=1]*/
var3 = inc_0_i <<< (32'd1 % 32);
/* br label %bb.i_2*/
cur_state = bb_i_2;
end
bb_i_2:
begin
/* %tmp5.i = add i32 %tmp.i, 2 ; <i32> [#uses=1]*/
tmp5_i = tmp_i + 32'd2;
/* %4 = or i32 %3, 1 ; <i32> [#uses=1]*/
var4 = var3 | 32'd1;
/* br label %bb.i_3*/
cur_state = bb_i_3;
end
bb_i_3:
begin
/* %5 = mul i32 %4, %tmp5.i ; <i32> [#uses=4]*/
var5 = var4 * tmp5_i;
/* br label %bb.i_4*/
cur_state = bb_i_4;
end
bb_i_4:
begin
/* %6 = icmp eq i32 %5, 0 ; <i1> [#uses=1]*/
var6 = var5 == 32'd0;
/* br label %bb.i_5*/
cur_state = bb_i_5;
end
bb_i_5:
begin
/* br i1 %6, label %int32_to_float64.exit.i, label %bb1.i.i*/
if (var6) begin
var7 = 64'd0; /* for PHI node */
cur_state = int32_to_float64_exit_i;
end
else begin
cur_state = bb1_i_i;
end
end
bb1_i_i:
begin
/* %a.lobit.i.i = lshr i32 %5, 31 ; <i32> [#uses=2]*/
a_lobit_i_i = var5 >>> (32'd31 % 32);
/* %7 = sub i32 0, %5 ; <i32> [#uses=1]*/
var8 = 32'd0 - var5;
/* br label %bb1.i.i_1*/
cur_state = bb1_i_i_1;
end
bb1_i_i_1:
begin
/* %8 = icmp eq i32 %a.lobit.i.i, 0 ; <i1> [#uses=1]*/
var9 = a_lobit_i_i == 32'd0;
/* %9 = zext i32 %a.lobit.i.i to i64 ; <i64> [#uses=1]*/
var10 = a_lobit_i_i;
/* br label %bb1.i.i_2*/
cur_state = bb1_i_i_2;
end
bb1_i_i_2:
begin
/* %iftmp.44.0.i.i = select i1 %8, i32 %5, i32 %7 ; <i32> [#uses=4]*/
iftmp_44_0_i_i = (var9) ? var5 : var8;
/* %10 = shl i64 %9, 63 ; <i64> [#uses=1]*/
var11 = var10 <<< (64'd63 % 64);
/* br label %bb1.i.i_3*/
cur_state = bb1_i_i_3;
end
bb1_i_i_3:
begin
/* %11 = shl i32 %iftmp.44.0.i.i, 16 ; <i32> [#uses=1]*/
var12 = iftmp_44_0_i_i <<< (32'd16 % 32);
/* %12 = icmp ult i32 %iftmp.44.0.i.i, 65536 ; <i1> [#uses=2]*/
var13 = iftmp_44_0_i_i < 32'd65536;
/* %13 = zext i32 %iftmp.44.0.i.i to i64 ; <i64> [#uses=1]*/
var14 = iftmp_44_0_i_i;
/* br label %bb1.i.i_4*/
cur_state = bb1_i_i_4;
end
bb1_i_i_4:
begin
/* %.a.i.i.i = select i1 %12, i32 %11, i32 %iftmp.44.0.i.i ; <i32> [#uses=3]*/
_a_i_i_i = (var13) ? var12 : iftmp_44_0_i_i;
/* %shiftCount.0.i.i.i = select i1 %12, i32 16, i32 0 ; <i32> [#uses=2]*/
shiftCount_0_i_i_i = (var13) ? 32'd16 : 32'd0;
/* br label %bb1.i.i_5*/
cur_state = bb1_i_i_5;
end
bb1_i_i_5:
begin
/* %14 = icmp ult i32 %.a.i.i.i, 16777216 ; <i1> [#uses=2]*/
var15 = _a_i_i_i < 32'd16777216;
/* %15 = or i32 %shiftCount.0.i.i.i, 8 ; <i32> [#uses=1]*/
var16 = shiftCount_0_i_i_i | 32'd8;
/* %16 = shl i32 %.a.i.i.i, 8 ; <i32> [#uses=1]*/
var17 = _a_i_i_i <<< (32'd8 % 32);
/* br label %bb1.i.i_6*/
cur_state = bb1_i_i_6;
end
bb1_i_i_6:
begin
/* %shiftCount.1.i.i.i = select i1 %14, i32 %15, i32 %shiftCount.0.i.i.i ; <i32> [#uses=1]*/
shiftCount_1_i_i_i = (var15) ? var16 : shiftCount_0_i_i_i;
/* %a_addr.1.i.i.i = select i1 %14, i32 %16, i32 %.a.i.i.i ; <i32> [#uses=1]*/
a_addr_1_i_i_i = (var15) ? var17 : _a_i_i_i;
/* br label %bb1.i.i_7*/
cur_state = bb1_i_i_7;
end
bb1_i_i_7:
begin
/* %17 = lshr i32 %a_addr.1.i.i.i, 24 ; <i32> [#uses=1]*/
var18 = a_addr_1_i_i_i >>> (32'd24 % 32);
/* br label %bb1.i.i_8*/
cur_state = bb1_i_i_8;
end
bb1_i_i_8:
begin
/* %18 = getelementptr inbounds [256 x i32]* @countLeadingZerosHigh.1302, i32 0, i32 %17 ; <i32*> [#uses=1]*/
var19 = {`TAG_countLeadingZerosHigh_1302, 32'b0} + ((var18 + 256*(32'd0)) << 2);
/* br label %bb1.i.i_9*/
cur_state = bb1_i_i_9;
end
bb1_i_i_9:
begin
/* %19 = load i32* %18, align 4 ; <i32> [#uses=1]*/
/* br label %bb1.i.i_10*/
cur_state = bb1_i_i_10;
end
bb1_i_i_10:
begin
var20 = memory_controller_out[31:0];
/* %load_noop1 = add i32 %19, 0 ; <i32> [#uses=1]*/
load_noop1 = var20 + 32'd0;
/* br label %bb1.i.i_11*/
cur_state = bb1_i_i_11;
end
bb1_i_i_11:
begin
/* %20 = add nsw i32 %load_noop1, %shiftCount.1.i.i.i ; <i32> [#uses=2]*/
var21 = load_noop1 + shiftCount_1_i_i_i;
/* br label %bb1.i.i_12*/
cur_state = bb1_i_i_12;
end
bb1_i_i_12:
begin
/* %21 = add nsw i32 %20, 21 ; <i32> [#uses=1]*/
var22 = var21 + 32'd21;
/* %22 = sub i32 1053, %20 ; <i32> [#uses=1]*/
var23 = 32'd1053 - var21;
/* br label %bb1.i.i_13*/
cur_state = bb1_i_i_13;
end
bb1_i_i_13:
begin
/* %.cast.i.i = zext i32 %21 to i64 ; <i64> [#uses=1]*/
_cast_i_i = var22;
/* %23 = zext i32 %22 to i64 ; <i64> [#uses=1]*/
var24 = var23;
/* br label %bb1.i.i_14*/
cur_state = bb1_i_i_14;
end
bb1_i_i_14:
begin
/* %24 = shl i64 %13, %.cast.i.i ; <i64> [#uses=1]*/
var25 = var14 <<< (_cast_i_i % 64);
/* %25 = shl i64 %23, 52 ; <i64> [#uses=1]*/
var26 = var24 <<< (64'd52 % 64);
/* br label %bb1.i.i_15*/
cur_state = bb1_i_i_15;
end
bb1_i_i_15:
begin
/* %26 = add i64 %24, %10 ; <i64> [#uses=1]*/
var27 = var25 + var11;
/* br label %bb1.i.i_16*/
cur_state = bb1_i_i_16;
end
bb1_i_i_16:
begin
/* %27 = add i64 %26, %25 ; <i64> [#uses=1]*/
var28 = var27 + var26;
/* br label %int32_to_float64.exit.i*/
var7 = var28; /* for PHI node */
cur_state = int32_to_float64_exit_i;
end
int32_to_float64_exit_i:
begin
/* %28 = phi i64 [ %27, %bb1.i.i_16 ], [ 0, %bb.i_5 ] ; <i64> [#uses=16]*/
/* %29 = tail call fastcc i64 @float64_mul(i64 %diff.0.i, i64 %2) nounwind ; <i64> [#uses=13]*/
float64_mul_start = 1;
/* Argument: %diff.0.i = phi i64 [ %217, %bb10.i.i.i_1 ], [ %load_noop, %bb_5 ] ; <i64> [#uses=1]*/
float64_mul_a = diff_0_i;
/* Argument: %2 = xor i64 %1, -9223372036854775808 ; <i64> [#uses=1]*/
float64_mul_b = var2;
cur_state = int32_to_float64_exit_i_call_0;
end
int32_to_float64_exit_i_call_0:
begin
float64_mul_start = 0;
if (float64_mul_finish == 1)
begin
var29 = float64_mul_return_val;
cur_state = int32_to_float64_exit_i_call_1;
end
else
cur_state = int32_to_float64_exit_i_call_0;
end
int32_to_float64_exit_i_call_1:
begin
/* br label %int32_to_float64.exit.i_1*/
cur_state = int32_to_float64_exit_i_1;
end
int32_to_float64_exit_i_1:
begin
/* %30 = and i64 %29, 4503599627370495 ; <i64> [#uses=7]*/
var30 = var29 & 64'd4503599627370495;
/* %31 = lshr i64 %29, 52 ; <i64> [#uses=1]*/
var31 = var29 >>> (64'd52 % 64);
/* %32 = and i64 %28, 4503599627370495 ; <i64> [#uses=7]*/
var32 = var7 & 64'd4503599627370495;
/* %33 = lshr i64 %28, 52 ; <i64> [#uses=1]*/
var33 = var7 >>> (64'd52 % 64);
/* %34 = xor i64 %28, %29 ; <i64> [#uses=5]*/
var34 = var7 ^ var29;
/* br label %int32_to_float64.exit.i_2*/
cur_state = int32_to_float64_exit_i_2;
end
int32_to_float64_exit_i_2:
begin
/* %35 = trunc i64 %31 to i32 ; <i32> [#uses=1]*/
var35 = var31[31:0];
/* %36 = trunc i64 %33 to i32 ; <i32> [#uses=1]*/
var36 = var33[31:0];
/* %37 = lshr i64 %34, 63 ; <i64> [#uses=1]*/
var37 = var34 >>> (64'd63 % 64);
/* br label %int32_to_float64.exit.i_3*/
cur_state = int32_to_float64_exit_i_3;
end
int32_to_float64_exit_i_3:
begin
/* %38 = and i32 %35, 2047 ; <i32> [#uses=4]*/
var38 = var35 & 32'd2047;
/* %39 = and i32 %36, 2047 ; <i32> [#uses=3]*/
var39 = var36 & 32'd2047;
/* %40 = trunc i64 %37 to i32 ; <i32> [#uses=1]*/
var40 = var37[31:0];
/* br label %int32_to_float64.exit.i_4*/
cur_state = int32_to_float64_exit_i_4;
end
int32_to_float64_exit_i_4:
begin
/* %41 = icmp eq i32 %38, 2047 ; <i1> [#uses=1]*/
var41 = var38 == 32'd2047;
/* br label %int32_to_float64.exit.i_5*/
cur_state = int32_to_float64_exit_i_5;
end
int32_to_float64_exit_i_5:
begin
/* br i1 %41, label %bb.i.i, label %bb7.i.i*/
if (var41) begin
cur_state = bb_i_i;
end
else begin
cur_state = bb7_i_i;
end
end
bb_i_i:
begin
/* %42 = icmp eq i64 %30, 0 ; <i1> [#uses=1]*/
var42 = var30 == 64'd0;
/* br label %bb.i.i_1*/
cur_state = bb_i_i_1;
end
bb_i_i_1:
begin
/* br i1 %42, label %bb2.i.i, label %bb1.i1.i*/
if (var42) begin
cur_state = bb2_i_i;
end
else begin
cur_state = bb1_i1_i;
end
end
bb1_i1_i:
begin
/* %43 = and i64 %29, 9221120237041090560 ; <i64> [#uses=1]*/
var43 = var29 & 64'd9221120237041090560;
/* br label %bb1.i1.i_1*/
cur_state = bb1_i1_i_1;
end
bb1_i1_i_1:
begin
/* %44 = icmp eq i64 %43, 9218868437227405312 ; <i1> [#uses=1]*/
var44 = var43 == 64'd9218868437227405312;
/* br label %bb1.i1.i_2*/
cur_state = bb1_i1_i_2;
end
bb1_i1_i_2:
begin
/* br i1 %44, label %bb.i14.i65.i.i, label %float64_is_signaling_nan.exit16.i66.i.i*/
if (var44) begin
cur_state = bb_i14_i65_i_i;
end
else begin
var45 = 32'd0; /* for PHI node */
cur_state = float64_is_signaling_nan_exit16_i66_i_i;
end
end
bb_i14_i65_i_i:
begin
/* %45 = and i64 %29, 2251799813685247 ; <i64> [#uses=1]*/
var46 = var29 & 64'd2251799813685247;
/* br label %bb.i14.i65.i.i_1*/
cur_state = bb_i14_i65_i_i_1;
end
bb_i14_i65_i_i_1:
begin
/* %not..i12.i63.i.i = icmp ne i64 %45, 0 ; <i1> [#uses=1]*/
not__i12_i63_i_i = var46 != 64'd0;
/* br label %bb.i14.i65.i.i_2*/
cur_state = bb_i14_i65_i_i_2;
end
bb_i14_i65_i_i_2:
begin
/* %retval.i13.i64.i.i = zext i1 %not..i12.i63.i.i to i32 ; <i32> [#uses=1]*/
retval_i13_i64_i_i = not__i12_i63_i_i;
/* br label %float64_is_signaling_nan.exit16.i66.i.i*/
var45 = retval_i13_i64_i_i; /* for PHI node */
cur_state = float64_is_signaling_nan_exit16_i66_i_i;
end
float64_is_signaling_nan_exit16_i66_i_i:
begin
/* %46 = phi i32 [ %retval.i13.i64.i.i, %bb.i14.i65.i.i_2 ], [ 0, %bb1.i1.i_2 ] ; <i32> [#uses=2]*/
/* %47 = shl i64 %28, 1 ; <i64> [#uses=1]*/
var47 = var7 <<< (64'd1 % 64);
/* %48 = and i64 %28, 9221120237041090560 ; <i64> [#uses=1]*/
var48 = var7 & 64'd9221120237041090560;
/* br label %float64_is_signaling_nan.exit16.i66.i.i_1*/
cur_state = float64_is_signaling_nan_exit16_i66_i_i_1;
end
float64_is_signaling_nan_exit16_i66_i_i_1:
begin
/* %49 = icmp ugt i64 %47, -9007199254740992 ; <i1> [#uses=1]*/
var49 = var47 > -64'd9007199254740992;
/* %50 = icmp eq i64 %48, 9218868437227405312 ; <i1> [#uses=1]*/
var50 = var48 == 64'd9218868437227405312;
/* br label %float64_is_signaling_nan.exit16.i66.i.i_2*/
cur_state = float64_is_signaling_nan_exit16_i66_i_i_2;
end
float64_is_signaling_nan_exit16_i66_i_i_2:
begin
/* br i1 %50, label %bb.i.i69.i.i, label %float64_is_signaling_nan.exit.i70.i.i*/
if (var50) begin
cur_state = bb_i_i69_i_i;
end
else begin
var51 = 32'd0; /* for PHI node */
cur_state = float64_is_signaling_nan_exit_i70_i_i;
end
end
bb_i_i69_i_i:
begin
/* %51 = and i64 %28, 2251799813685247 ; <i64> [#uses=1]*/
var52 = var7 & 64'd2251799813685247;
/* br label %bb.i.i69.i.i_1*/
cur_state = bb_i_i69_i_i_1;
end
bb_i_i69_i_i_1:
begin
/* %not..i.i67.i.i = icmp ne i64 %51, 0 ; <i1> [#uses=1]*/
not__i_i67_i_i = var52 != 64'd0;
/* br label %bb.i.i69.i.i_2*/
cur_state = bb_i_i69_i_i_2;
end
bb_i_i69_i_i_2:
begin
/* %retval.i.i68.i.i = zext i1 %not..i.i67.i.i to i32 ; <i32> [#uses=1]*/
retval_i_i68_i_i = not__i_i67_i_i;
/* br label %float64_is_signaling_nan.exit.i70.i.i*/
var51 = retval_i_i68_i_i; /* for PHI node */
cur_state = float64_is_signaling_nan_exit_i70_i_i;
end
float64_is_signaling_nan_exit_i70_i_i:
begin
/* %52 = phi i32 [ %retval.i.i68.i.i, %bb.i.i69.i.i_2 ], [ 0, %float64_is_signaling_nan.exit16.i66.i.i_2 ] ; <i32> [#uses=2]*/
/* %53 = or i64 %29, 2251799813685248 ; <i64> [#uses=2]*/
var53 = var29 | 64'd2251799813685248;
/* %54 = or i64 %28, 2251799813685248 ; <i64> [#uses=2]*/
var54 = var7 | 64'd2251799813685248;
/* br label %float64_is_signaling_nan.exit.i70.i.i_1*/
cur_state = float64_is_signaling_nan_exit_i70_i_i_1;
end
float64_is_signaling_nan_exit_i70_i_i_1:
begin
/* %55 = or i32 %52, %46 ; <i32> [#uses=1]*/
var55 = var51 | var45;
/* br label %float64_is_signaling_nan.exit.i70.i.i_2*/
cur_state = float64_is_signaling_nan_exit_i70_i_i_2;
end
float64_is_signaling_nan_exit_i70_i_i_2:
begin
/* %56 = icmp eq i32 %55, 0 ; <i1> [#uses=1]*/
var56 = var55 == 32'd0;
/* br label %float64_is_signaling_nan.exit.i70.i.i_3*/
cur_state = float64_is_signaling_nan_exit_i70_i_i_3;
end
float64_is_signaling_nan_exit_i70_i_i_3:
begin
/* br i1 %56, label %bb1.i72.i.i, label %bb.i71.i.i*/
if (var56) begin
cur_state = bb1_i72_i_i;
end
else begin
cur_state = bb_i71_i_i;
end
end
bb_i71_i_i:
begin
/* %57 = load i32* @float_exception_flags, align 4 ; <i32> [#uses=1]*/
/* br label %bb.i71.i.i_1*/
cur_state = bb_i71_i_i_1;
end
bb_i71_i_i_1:
begin
var57 = memory_controller_out[31:0];
/* %load_noop2 = add i32 %57, 0 ; <i32> [#uses=1]*/
load_noop2 = var57 + 32'd0;
/* br label %bb.i71.i.i_2*/
cur_state = bb_i71_i_i_2;
end
bb_i71_i_i_2:
begin
/* %58 = or i32 %load_noop2, 16 ; <i32> [#uses=1]*/
var58 = load_noop2 | 32'd16;
/* br label %bb.i71.i.i_3*/
cur_state = bb_i71_i_i_3;
end
bb_i71_i_i_3:
begin
/* store i32 %58, i32* @float_exception_flags, align 4*/
/* br label %bb1.i72.i.i*/
cur_state = bb1_i72_i_i;
end
bb1_i72_i_i:
begin
/* %59 = icmp eq i32 %52, 0 ; <i1> [#uses=1]*/
var59 = var51 == 32'd0;
/* br label %bb1.i72.i.i_1*/
cur_state = bb1_i72_i_i_1;
end
bb1_i72_i_i_1:
begin
/* br i1 %59, label %bb2.i73.i.i, label %float64_div.exit.i*/
if (var59) begin
cur_state = bb2_i73_i_i;
end
else begin
var60 = var54; /* for PHI node */
cur_state = float64_div_exit_i;
end
end
bb2_i73_i_i:
begin
/* %60 = icmp eq i32 %46, 0 ; <i1> [#uses=1]*/
var61 = var45 == 32'd0;
/* br label %bb2.i73.i.i_1*/
cur_state = bb2_i73_i_i_1;
end
bb2_i73_i_i_1:
begin
/* br i1 %60, label %bb3.i75.i.i, label %float64_div.exit.i*/
if (var61) begin
cur_state = bb3_i75_i_i;
end
else begin
var60 = var53; /* for PHI node */
cur_state = float64_div_exit_i;
end
end
bb3_i75_i_i:
begin
/* %iftmp.34.0.i74.i.i = select i1 %49, i64 %54, i64 %53 ; <i64> [#uses=1]*/
iftmp_34_0_i74_i_i = (var49) ? var54 : var53;
/* br label %float64_div.exit.i*/
var60 = iftmp_34_0_i74_i_i; /* for PHI node */
cur_state = float64_div_exit_i;
end
bb2_i_i:
begin
/* %61 = icmp eq i32 %39, 2047 ; <i1> [#uses=1]*/
var62 = var39 == 32'd2047;
/* br label %bb2.i.i_1*/
cur_state = bb2_i_i_1;
end
bb2_i_i_1:
begin
/* br i1 %61, label %bb3.i.i, label %bb6.i.i*/
if (var62) begin
cur_state = bb3_i_i;
end
else begin
cur_state = bb6_i_i;
end
end
bb3_i_i:
begin
/* %62 = icmp eq i64 %32, 0 ; <i1> [#uses=1]*/
var63 = var32 == 64'd0;
/* br label %bb3.i.i_1*/
cur_state = bb3_i_i_1;
end
bb3_i_i_1:
begin
/* br i1 %62, label %bb5.i.i, label %bb4.i.i*/
if (var63) begin
cur_state = bb5_i_i;
end
else begin
cur_state = bb4_i_i;
end
end
bb4_i_i:
begin
/* %63 = and i64 %29, 9221120237041090560 ; <i64> [#uses=1]*/
var64 = var29 & 64'd9221120237041090560;
/* br label %bb4.i.i_1*/
cur_state = bb4_i_i_1;
end
bb4_i_i_1:
begin
/* %64 = icmp eq i64 %63, 9218868437227405312 ; <i1> [#uses=1]*/
var65 = var64 == 64'd9218868437227405312;
/* br label %bb4.i.i_2*/
cur_state = bb4_i_i_2;
end
bb4_i_i_2:
begin
/* br i1 %64, label %bb.i14.i49.i.i, label %float64_is_signaling_nan.exit16.i50.i.i*/
if (var65) begin
cur_state = bb_i14_i49_i_i;
end
else begin
var66 = 32'd0; /* for PHI node */
cur_state = float64_is_signaling_nan_exit16_i50_i_i;
end
end
bb_i14_i49_i_i:
begin
/* %65 = and i64 %29, 2251799813685247 ; <i64> [#uses=1]*/
var67 = var29 & 64'd2251799813685247;
/* br label %bb.i14.i49.i.i_1*/
cur_state = bb_i14_i49_i_i_1;
end
bb_i14_i49_i_i_1:
begin
/* %not..i12.i47.i.i = icmp ne i64 %65, 0 ; <i1> [#uses=1]*/
not__i12_i47_i_i = var67 != 64'd0;
/* br label %bb.i14.i49.i.i_2*/
cur_state = bb_i14_i49_i_i_2;
end
bb_i14_i49_i_i_2:
begin
/* %retval.i13.i48.i.i = zext i1 %not..i12.i47.i.i to i32 ; <i32> [#uses=1]*/
retval_i13_i48_i_i = not__i12_i47_i_i;
/* br label %float64_is_signaling_nan.exit16.i50.i.i*/
var66 = retval_i13_i48_i_i; /* for PHI node */
cur_state = float64_is_signaling_nan_exit16_i50_i_i;
end
float64_is_signaling_nan_exit16_i50_i_i:
begin
/* %66 = phi i32 [ %retval.i13.i48.i.i, %bb.i14.i49.i.i_2 ], [ 0, %bb4.i.i_2 ] ; <i32> [#uses=2]*/
/* %67 = shl i64 %28, 1 ; <i64> [#uses=1]*/
var68 = var7 <<< (64'd1 % 64);
/* %68 = and i64 %28, 9221120237041090560 ; <i64> [#uses=1]*/
var69 = var7 & 64'd9221120237041090560;
/* br label %float64_is_signaling_nan.exit16.i50.i.i_1*/
cur_state = float64_is_signaling_nan_exit16_i50_i_i_1;
end
float64_is_signaling_nan_exit16_i50_i_i_1:
begin
/* %69 = icmp ugt i64 %67, -9007199254740992 ; <i1> [#uses=1]*/
var70 = var68 > -64'd9007199254740992;
/* %70 = icmp eq i64 %68, 9218868437227405312 ; <i1> [#uses=1]*/
var71 = var69 == 64'd9218868437227405312;
/* br label %float64_is_signaling_nan.exit16.i50.i.i_2*/
cur_state = float64_is_signaling_nan_exit16_i50_i_i_2;
end
float64_is_signaling_nan_exit16_i50_i_i_2:
begin
/* br i1 %70, label %bb.i.i53.i.i, label %float64_is_signaling_nan.exit.i54.i.i*/
if (var71) begin
cur_state = bb_i_i53_i_i;
end
else begin
var72 = 32'd0; /* for PHI node */
cur_state = float64_is_signaling_nan_exit_i54_i_i;
end
end
bb_i_i53_i_i:
begin
/* %71 = and i64 %28, 2251799813685247 ; <i64> [#uses=1]*/
var73 = var7 & 64'd2251799813685247;
/* br label %bb.i.i53.i.i_1*/
cur_state = bb_i_i53_i_i_1;
end
bb_i_i53_i_i_1:
begin
/* %not..i.i51.i.i = icmp ne i64 %71, 0 ; <i1> [#uses=1]*/
not__i_i51_i_i = var73 != 64'd0;
/* br label %bb.i.i53.i.i_2*/
cur_state = bb_i_i53_i_i_2;
end
bb_i_i53_i_i_2:
begin
/* %retval.i.i52.i.i = zext i1 %not..i.i51.i.i to i32 ; <i32> [#uses=1]*/
retval_i_i52_i_i = not__i_i51_i_i;
/* br label %float64_is_signaling_nan.exit.i54.i.i*/
var72 = retval_i_i52_i_i; /* for PHI node */
cur_state = float64_is_signaling_nan_exit_i54_i_i;
end
float64_is_signaling_nan_exit_i54_i_i:
begin
/* %72 = phi i32 [ %retval.i.i52.i.i, %bb.i.i53.i.i_2 ], [ 0, %float64_is_signaling_nan.exit16.i50.i.i_2 ] ; <i32> [#uses=2]*/
/* %73 = or i64 %29, 2251799813685248 ; <i64> [#uses=2]*/
var74 = var29 | 64'd2251799813685248;
/* %74 = or i64 %28, 2251799813685248 ; <i64> [#uses=2]*/
var75 = var7 | 64'd2251799813685248;
/* br label %float64_is_signaling_nan.exit.i54.i.i_1*/
cur_state = float64_is_signaling_nan_exit_i54_i_i_1;
end
float64_is_signaling_nan_exit_i54_i_i_1:
begin
/* %75 = or i32 %72, %66 ; <i32> [#uses=1]*/
var76 = var72 | var66;
/* br label %float64_is_signaling_nan.exit.i54.i.i_2*/
cur_state = float64_is_signaling_nan_exit_i54_i_i_2;
end
float64_is_signaling_nan_exit_i54_i_i_2:
begin
/* %76 = icmp eq i32 %75, 0 ; <i1> [#uses=1]*/
var77 = var76 == 32'd0;
/* br label %float64_is_signaling_nan.exit.i54.i.i_3*/
cur_state = float64_is_signaling_nan_exit_i54_i_i_3;
end
float64_is_signaling_nan_exit_i54_i_i_3:
begin
/* br i1 %76, label %bb1.i56.i.i, label %bb.i55.i.i*/
if (var77) begin
cur_state = bb1_i56_i_i;
end
else begin
cur_state = bb_i55_i_i;
end
end
bb_i55_i_i:
begin
/* %77 = load i32* @float_exception_flags, align 4 ; <i32> [#uses=1]*/
/* br label %bb.i55.i.i_1*/
cur_state = bb_i55_i_i_1;
end
bb_i55_i_i_1:
begin
var78 = memory_controller_out[31:0];
/* %load_noop3 = add i32 %77, 0 ; <i32> [#uses=1]*/
load_noop3 = var78 + 32'd0;
/* br label %bb.i55.i.i_2*/
cur_state = bb_i55_i_i_2;
end
bb_i55_i_i_2:
begin
/* %78 = or i32 %load_noop3, 16 ; <i32> [#uses=1]*/
var79 = load_noop3 | 32'd16;
/* br label %bb.i55.i.i_3*/
cur_state = bb_i55_i_i_3;
end
bb_i55_i_i_3:
begin
/* store i32 %78, i32* @float_exception_flags, align 4*/
/* br label %bb1.i56.i.i*/
cur_state = bb1_i56_i_i;
end
bb1_i56_i_i:
begin
/* %79 = icmp eq i32 %72, 0 ; <i1> [#uses=1]*/
var80 = var72 == 32'd0;
/* br label %bb1.i56.i.i_1*/
cur_state = bb1_i56_i_i_1;
end
bb1_i56_i_i_1:
begin
/* br i1 %79, label %bb2.i57.i.i, label %float64_div.exit.i*/
if (var80) begin
cur_state = bb2_i57_i_i;
end
else begin
var60 = var75; /* for PHI node */
cur_state = float64_div_exit_i;
end
end
bb2_i57_i_i:
begin
/* %80 = icmp eq i32 %66, 0 ; <i1> [#uses=1]*/
var81 = var66 == 32'd0;
/* br label %bb2.i57.i.i_1*/
cur_state = bb2_i57_i_i_1;
end
bb2_i57_i_i_1:
begin
/* br i1 %80, label %bb3.i59.i.i, label %float64_div.exit.i*/
if (var81) begin
cur_state = bb3_i59_i_i;
end
else begin
var60 = var74; /* for PHI node */
cur_state = float64_div_exit_i;
end
end
bb3_i59_i_i:
begin
/* %iftmp.34.0.i58.i.i = select i1 %69, i64 %74, i64 %73 ; <i64> [#uses=1]*/
iftmp_34_0_i58_i_i = (var70) ? var75 : var74;
/* br label %float64_div.exit.i*/
var60 = iftmp_34_0_i58_i_i; /* for PHI node */
cur_state = float64_div_exit_i;
end
bb5_i_i:
begin
/* %81 = load i32* @float_exception_flags, align 4 ; <i32> [#uses=1]*/
/* br label %bb5.i.i_1*/
cur_state = bb5_i_i_1;
end
bb5_i_i_1:
begin
var82 = memory_controller_out[31:0];
/* %load_noop4 = add i32 %81, 0 ; <i32> [#uses=1]*/
load_noop4 = var82 + 32'd0;
/* br label %bb5.i.i_2*/
cur_state = bb5_i_i_2;
end
bb5_i_i_2:
begin
/* %82 = or i32 %load_noop4, 16 ; <i32> [#uses=1]*/
var83 = load_noop4 | 32'd16;
/* br label %bb5.i.i_3*/
cur_state = bb5_i_i_3;
end
bb5_i_i_3:
begin
/* store i32 %82, i32* @float_exception_flags, align 4*/
/* br label %float64_div.exit.i*/
var60 = 64'd9223372036854775807; /* for PHI node */
cur_state = float64_div_exit_i;
end
bb6_i_i:
begin
/* %83 = or i64 %34, 9218868437227405312 ; <i64> [#uses=1]*/
var84 = var34 | 64'd9218868437227405312;
/* br label %bb6.i.i_1*/
cur_state = bb6_i_i_1;
end
bb6_i_i_1:
begin
/* %84 = and i64 %83, -4503599627370496 ; <i64> [#uses=1]*/
var85 = var84 & -64'd4503599627370496;
/* br label %float64_div.exit.i*/
var60 = var85; /* for PHI node */
cur_state = float64_div_exit_i;
end
bb7_i_i:
begin
/* switch i32 %39, label %bb17.i.i [
i32 2047, label %bb8.i.i
i32 0, label %bb12.i.i
]*/
case(var39)
32'd2047:
begin
cur_state = bb8_i_i;
end
32'd0:
begin
cur_state = bb12_i_i;
end
default:
begin
bSig_0_i_i = var32; /* for PHI node */
bExp_0_i_i = var39; /* for PHI node */
cur_state = bb17_i_i;
end
endcase
end
bb8_i_i:
begin
/* %85 = icmp eq i64 %32, 0 ; <i1> [#uses=1]*/
var86 = var32 == 64'd0;
/* br label %bb8.i.i_1*/
cur_state = bb8_i_i_1;
end
bb8_i_i_1:
begin
/* br i1 %85, label %bb10.i.i, label %bb9.i.i*/
if (var86) begin
cur_state = bb10_i_i;
end
else begin
cur_state = bb9_i_i;
end
end
bb9_i_i:
begin
/* %86 = and i64 %29, 9221120237041090560 ; <i64> [#uses=1]*/
var87 = var29 & 64'd9221120237041090560;
/* br label %bb9.i.i_1*/
cur_state = bb9_i_i_1;
end
bb9_i_i_1:
begin
/* %87 = icmp eq i64 %86, 9218868437227405312 ; <i1> [#uses=1]*/
var88 = var87 == 64'd9218868437227405312;
/* br label %bb9.i.i_2*/
cur_state = bb9_i_i_2;
end
bb9_i_i_2:
begin
/* br i1 %87, label %bb.i14.i.i.i, label %float64_is_signaling_nan.exit16.i.i.i*/
if (var88) begin
cur_state = bb_i14_i_i_i;
end
else begin
var89 = 32'd0; /* for PHI node */
cur_state = float64_is_signaling_nan_exit16_i_i_i;
end
end
bb_i14_i_i_i:
begin
/* %88 = and i64 %29, 2251799813685247 ; <i64> [#uses=1]*/
var90 = var29 & 64'd2251799813685247;
/* br label %bb.i14.i.i.i_1*/
cur_state = bb_i14_i_i_i_1;
end
bb_i14_i_i_i_1:
begin
/* %not..i12.i.i.i = icmp ne i64 %88, 0 ; <i1> [#uses=1]*/
not__i12_i_i_i = var90 != 64'd0;
/* br label %bb.i14.i.i.i_2*/
cur_state = bb_i14_i_i_i_2;
end
bb_i14_i_i_i_2:
begin
/* %retval.i13.i.i.i = zext i1 %not..i12.i.i.i to i32 ; <i32> [#uses=1]*/
retval_i13_i_i_i = not__i12_i_i_i;
/* br label %float64_is_signaling_nan.exit16.i.i.i*/
var89 = retval_i13_i_i_i; /* for PHI node */
cur_state = float64_is_signaling_nan_exit16_i_i_i;
end
float64_is_signaling_nan_exit16_i_i_i:
begin
/* %89 = phi i32 [ %retval.i13.i.i.i, %bb.i14.i.i.i_2 ], [ 0, %bb9.i.i_2 ] ; <i32> [#uses=2]*/
/* %90 = shl i64 %28, 1 ; <i64> [#uses=1]*/
var91 = var7 <<< (64'd1 % 64);
/* %91 = and i64 %28, 9221120237041090560 ; <i64> [#uses=1]*/
var92 = var7 & 64'd9221120237041090560;
/* br label %float64_is_signaling_nan.exit16.i.i.i_1*/
cur_state = float64_is_signaling_nan_exit16_i_i_i_1;
end
float64_is_signaling_nan_exit16_i_i_i_1:
begin
/* %92 = icmp ugt i64 %90, -9007199254740992 ; <i1> [#uses=1]*/
var93 = var91 > -64'd9007199254740992;
/* %93 = icmp eq i64 %91, 9218868437227405312 ; <i1> [#uses=1]*/
var94 = var92 == 64'd9218868437227405312;
/* br label %float64_is_signaling_nan.exit16.i.i.i_2*/
cur_state = float64_is_signaling_nan_exit16_i_i_i_2;
end
float64_is_signaling_nan_exit16_i_i_i_2:
begin
/* br i1 %93, label %bb.i.i43.i.i, label %float64_is_signaling_nan.exit.i.i.i*/
if (var94) begin
cur_state = bb_i_i43_i_i;
end
else begin
var95 = 32'd0; /* for PHI node */
cur_state = float64_is_signaling_nan_exit_i_i_i;
end
end
bb_i_i43_i_i:
begin
/* %94 = and i64 %28, 2251799813685247 ; <i64> [#uses=1]*/
var96 = var7 & 64'd2251799813685247;
/* br label %bb.i.i43.i.i_1*/
cur_state = bb_i_i43_i_i_1;
end
bb_i_i43_i_i_1:
begin
/* %not..i.i.i.i = icmp ne i64 %94, 0 ; <i1> [#uses=1]*/
not__i_i_i_i = var96 != 64'd0;
/* br label %bb.i.i43.i.i_2*/
cur_state = bb_i_i43_i_i_2;
end
bb_i_i43_i_i_2:
begin
/* %retval.i.i.i.i = zext i1 %not..i.i.i.i to i32 ; <i32> [#uses=1]*/
retval_i_i_i_i = not__i_i_i_i;
/* br label %float64_is_signaling_nan.exit.i.i.i*/
var95 = retval_i_i_i_i; /* for PHI node */
cur_state = float64_is_signaling_nan_exit_i_i_i;
end
float64_is_signaling_nan_exit_i_i_i:
begin
/* %95 = phi i32 [ %retval.i.i.i.i, %bb.i.i43.i.i_2 ], [ 0, %float64_is_signaling_nan.exit16.i.i.i_2 ] ; <i32> [#uses=2]*/
/* %96 = or i64 %29, 2251799813685248 ; <i64> [#uses=2]*/
var97 = var29 | 64'd2251799813685248;
/* %97 = or i64 %28, 2251799813685248 ; <i64> [#uses=2]*/
var98 = var7 | 64'd2251799813685248;
/* br label %float64_is_signaling_nan.exit.i.i.i_1*/
cur_state = float64_is_signaling_nan_exit_i_i_i_1;
end
float64_is_signaling_nan_exit_i_i_i_1:
begin
/* %98 = or i32 %95, %89 ; <i32> [#uses=1]*/
var99 = var95 | var89;
/* br label %float64_is_signaling_nan.exit.i.i.i_2*/
cur_state = float64_is_signaling_nan_exit_i_i_i_2;
end
float64_is_signaling_nan_exit_i_i_i_2:
begin
/* %99 = icmp eq i32 %98, 0 ; <i1> [#uses=1]*/
var100 = var99 == 32'd0;
/* br label %float64_is_signaling_nan.exit.i.i.i_3*/
cur_state = float64_is_signaling_nan_exit_i_i_i_3;
end
float64_is_signaling_nan_exit_i_i_i_3:
begin
/* br i1 %99, label %bb1.i44.i.i, label %bb.i.i.i*/
if (var100) begin
cur_state = bb1_i44_i_i;
end
else begin
cur_state = bb_i_i_i;
end
end
bb_i_i_i:
begin
/* %100 = load i32* @float_exception_flags, align 4 ; <i32> [#uses=1]*/
/* br label %bb.i.i.i_1*/
cur_state = bb_i_i_i_1;
end
bb_i_i_i_1:
begin
var101 = memory_controller_out[31:0];
/* %load_noop5 = add i32 %100, 0 ; <i32> [#uses=1]*/
load_noop5 = var101 + 32'd0;
/* br label %bb.i.i.i_2*/
cur_state = bb_i_i_i_2;
end
bb_i_i_i_2:
begin
/* %101 = or i32 %load_noop5, 16 ; <i32> [#uses=1]*/
var102 = load_noop5 | 32'd16;
/* br label %bb.i.i.i_3*/
cur_state = bb_i_i_i_3;
end
bb_i_i_i_3:
begin
/* store i32 %101, i32* @float_exception_flags, align 4*/
/* br label %bb1.i44.i.i*/
cur_state = bb1_i44_i_i;
end
bb1_i44_i_i:
begin
/* %102 = icmp eq i32 %95, 0 ; <i1> [#uses=1]*/
var103 = var95 == 32'd0;
/* br label %bb1.i44.i.i_1*/
cur_state = bb1_i44_i_i_1;
end
bb1_i44_i_i_1:
begin
/* br i1 %102, label %bb2.i45.i.i, label %float64_div.exit.i*/
if (var103) begin
cur_state = bb2_i45_i_i;
end
else begin
var60 = var98; /* for PHI node */
cur_state = float64_div_exit_i;
end
end
bb2_i45_i_i:
begin
/* %103 = icmp eq i32 %89, 0 ; <i1> [#uses=1]*/
var104 = var89 == 32'd0;
/* br label %bb2.i45.i.i_1*/
cur_state = bb2_i45_i_i_1;
end
bb2_i45_i_i_1:
begin
/* br i1 %103, label %bb3.i.i2.i, label %float64_div.exit.i*/
if (var104) begin
cur_state = bb3_i_i2_i;
end
else begin
var60 = var97; /* for PHI node */
cur_state = float64_div_exit_i;
end
end
bb3_i_i2_i:
begin
/* %iftmp.34.0.i.i.i = select i1 %92, i64 %97, i64 %96 ; <i64> [#uses=1]*/
iftmp_34_0_i_i_i = (var93) ? var98 : var97;
/* br label %float64_div.exit.i*/
var60 = iftmp_34_0_i_i_i; /* for PHI node */
cur_state = float64_div_exit_i;
end
bb10_i_i:
begin
/* %104 = and i64 %34, -9223372036854775808 ; <i64> [#uses=1]*/
var105 = var34 & -64'd9223372036854775808;
/* br label %float64_div.exit.i*/
var60 = var105; /* for PHI node */
cur_state = float64_div_exit_i;
end
bb12_i_i:
begin
/* %105 = icmp eq i64 %32, 0 ; <i1> [#uses=1]*/
var106 = var32 == 64'd0;
/* br label %bb12.i.i_1*/
cur_state = bb12_i_i_1;
end
bb12_i_i_1:
begin
/* br i1 %105, label %bb13.i.i, label %bb16.i.i*/
if (var106) begin
cur_state = bb13_i_i;
end
else begin
cur_state = bb16_i_i;
end
end
bb13_i_i:
begin
/* %106 = zext i32 %38 to i64 ; <i64> [#uses=1]*/
var107 = var38;
/* %107 = load i32* @float_exception_flags, align 4 ; <i32> [#uses=1]*/
/* br label %bb13.i.i_1*/
cur_state = bb13_i_i_1;
end
bb13_i_i_1:
begin
var108 = memory_controller_out[31:0];
/* %108 = or i64 %106, %30 ; <i64> [#uses=1]*/
var109 = var107 | var30;
/* %load_noop6 = add i32 %107, 0 ; <i32> [#uses=2]*/
load_noop6 = var108 + 32'd0;
/* br label %bb13.i.i_2*/
cur_state = bb13_i_i_2;
end
bb13_i_i_2:
begin
/* %109 = icmp eq i64 %108, 0 ; <i1> [#uses=1]*/
var110 = var109 == 64'd0;
/* br label %bb13.i.i_3*/
cur_state = bb13_i_i_3;
end
bb13_i_i_3:
begin
/* br i1 %109, label %bb14.i.i, label %bb15.i.i*/
if (var110) begin
cur_state = bb14_i_i;
end
else begin
cur_state = bb15_i_i;
end
end
bb14_i_i:
begin
/* %110 = or i32 %load_noop6, 16 ; <i32> [#uses=1]*/
var111 = load_noop6 | 32'd16;
/* br label %bb14.i.i_1*/
cur_state = bb14_i_i_1;
end
bb14_i_i_1:
begin
/* store i32 %110, i32* @float_exception_flags, align 4*/
/* br label %float64_div.exit.i*/
var60 = 64'd9223372036854775807; /* for PHI node */
cur_state = float64_div_exit_i;
end
bb15_i_i:
begin
/* %111 = or i32 %load_noop6, 2 ; <i32> [#uses=1]*/
var112 = load_noop6 | 32'd2;
/* %112 = or i64 %34, 9218868437227405312 ; <i64> [#uses=1]*/
var113 = var34 | 64'd9218868437227405312;
/* br label %bb15.i.i_1*/
cur_state = bb15_i_i_1;
end
bb15_i_i_1:
begin
/* store i32 %111, i32* @float_exception_flags, align 4*/
/* %113 = and i64 %112, -4503599627370496 ; <i64> [#uses=1]*/
var114 = var113 & -64'd4503599627370496;
/* br label %float64_div.exit.i*/
var60 = var114; /* for PHI node */
cur_state = float64_div_exit_i;
end
bb16_i_i:
begin
/* %114 = icmp ult i64 %32, 4294967296 ; <i1> [#uses=1]*/
var115 = var32 < 64'd4294967296;
/* br label %bb16.i.i_1*/
cur_state = bb16_i_i_1;
end
bb16_i_i_1:
begin
/* br i1 %114, label %bb.i.i32.i.i, label %bb1.i.i34.i.i*/
if (var115) begin
cur_state = bb_i_i32_i_i;
end
else begin
cur_state = bb1_i_i34_i_i;
end
end
bb_i_i32_i_i:
begin
/* %extract.t.i.i31.i.i = trunc i64 %28 to i32 ; <i32> [#uses=1]*/
extract_t_i_i31_i_i = var7[31:0];
/* br label %normalizeFloat64Subnormal.exit42.i.i*/
shiftCount_0_i_i35_i_i = 32'd32; /* for PHI node */
a_addr_0_off0_i_i36_i_i = extract_t_i_i31_i_i; /* for PHI node */
cur_state = normalizeFloat64Subnormal_exit42_i_i;
end
bb1_i_i34_i_i:
begin
/* %115 = lshr i64 %32, 32 ; <i64> [#uses=1]*/
var116 = var32 >>> (64'd32 % 64);
/* br label %bb1.i.i34.i.i_1*/
cur_state = bb1_i_i34_i_i_1;
end
bb1_i_i34_i_i_1:
begin
/* %extract.t4.i.i33.i.i = trunc i64 %115 to i32 ; <i32> [#uses=1]*/
extract_t4_i_i33_i_i = var116[31:0];
/* br label %normalizeFloat64Subnormal.exit42.i.i*/
shiftCount_0_i_i35_i_i = 32'd0; /* for PHI node */
a_addr_0_off0_i_i36_i_i = extract_t4_i_i33_i_i; /* for PHI node */
cur_state = normalizeFloat64Subnormal_exit42_i_i;
end
normalizeFloat64Subnormal_exit42_i_i:
begin
/* %shiftCount.0.i.i35.i.i = phi i32 [ 32, %bb.i.i32.i.i ], [ 0, %bb1.i.i34.i.i_1 ] ; <i32> [#uses=1]*/
/* %a_addr.0.off0.i.i36.i.i = phi i32 [ %extract.t.i.i31.i.i, %bb.i.i32.i.i ], [ %extract.t4.i.i33.i.i, %bb1.i.i34.i.i_1 ] ; <i32> [#uses=3]*/
/* br label %normalizeFloat64Subnormal.exit42.i.i_1*/
cur_state = normalizeFloat64Subnormal_exit42_i_i_1;
end
normalizeFloat64Subnormal_exit42_i_i_1:
begin
/* %116 = shl i32 %a_addr.0.off0.i.i36.i.i, 16 ; <i32> [#uses=1]*/
var117 = a_addr_0_off0_i_i36_i_i <<< (32'd16 % 32);
/* %117 = icmp ult i32 %a_addr.0.off0.i.i36.i.i, 65536 ; <i1> [#uses=2]*/
var118 = a_addr_0_off0_i_i36_i_i < 32'd65536;
/* br label %normalizeFloat64Subnormal.exit42.i.i_2*/
cur_state = normalizeFloat64Subnormal_exit42_i_i_2;
end
normalizeFloat64Subnormal_exit42_i_i_2:
begin
/* %.a.i.i.i37.i.i = select i1 %117, i32 %116, i32 %a_addr.0.off0.i.i36.i.i ; <i32> [#uses=3]*/
_a_i_i_i37_i_i = (var118) ? var117 : a_addr_0_off0_i_i36_i_i;
/* %shiftCount.0.i.i.i38.i.i = select i1 %117, i32 16, i32 0 ; <i32> [#uses=2]*/
shiftCount_0_i_i_i38_i_i = (var118) ? 32'd16 : 32'd0;
/* br label %normalizeFloat64Subnormal.exit42.i.i_3*/
cur_state = normalizeFloat64Subnormal_exit42_i_i_3;
end
normalizeFloat64Subnormal_exit42_i_i_3:
begin
/* %118 = icmp ult i32 %.a.i.i.i37.i.i, 16777216 ; <i1> [#uses=2]*/
var119 = _a_i_i_i37_i_i < 32'd16777216;
/* %119 = or i32 %shiftCount.0.i.i.i38.i.i, 8 ; <i32> [#uses=1]*/
var120 = shiftCount_0_i_i_i38_i_i | 32'd8;
/* %120 = shl i32 %.a.i.i.i37.i.i, 8 ; <i32> [#uses=1]*/
var121 = _a_i_i_i37_i_i <<< (32'd8 % 32);
/* br label %normalizeFloat64Subnormal.exit42.i.i_4*/
cur_state = normalizeFloat64Subnormal_exit42_i_i_4;
end
normalizeFloat64Subnormal_exit42_i_i_4:
begin
/* %shiftCount.1.i.i.i39.i.i = select i1 %118, i32 %119, i32 %shiftCount.0.i.i.i38.i.i ; <i32> [#uses=1]*/
shiftCount_1_i_i_i39_i_i = (var119) ? var120 : shiftCount_0_i_i_i38_i_i;
/* %a_addr.1.i.i.i40.i.i = select i1 %118, i32 %120, i32 %.a.i.i.i37.i.i ; <i32> [#uses=1]*/
a_addr_1_i_i_i40_i_i = (var119) ? var121 : _a_i_i_i37_i_i;
/* br label %normalizeFloat64Subnormal.exit42.i.i_5*/
cur_state = normalizeFloat64Subnormal_exit42_i_i_5;
end
normalizeFloat64Subnormal_exit42_i_i_5:
begin
/* %121 = lshr i32 %a_addr.1.i.i.i40.i.i, 24 ; <i32> [#uses=1]*/
var122 = a_addr_1_i_i_i40_i_i >>> (32'd24 % 32);
/* br label %normalizeFloat64Subnormal.exit42.i.i_6*/
cur_state = normalizeFloat64Subnormal_exit42_i_i_6;
end
normalizeFloat64Subnormal_exit42_i_i_6:
begin
/* %122 = getelementptr inbounds [256 x i32]* @countLeadingZerosHigh.1302, i32 0, i32 %121 ; <i32*> [#uses=1]*/
var123 = {`TAG_countLeadingZerosHigh_1302, 32'b0} + ((var122 + 256*(32'd0)) << 2);
/* br label %normalizeFloat64Subnormal.exit42.i.i_7*/
cur_state = normalizeFloat64Subnormal_exit42_i_i_7;
end
normalizeFloat64Subnormal_exit42_i_i_7:
begin
/* %123 = load i32* %122, align 4 ; <i32> [#uses=1]*/
/* br label %normalizeFloat64Subnormal.exit42.i.i_8*/
cur_state = normalizeFloat64Subnormal_exit42_i_i_8;
end
normalizeFloat64Subnormal_exit42_i_i_8:
begin
var124 = memory_controller_out[31:0];
/* %load_noop7 = add i32 %123, 0 ; <i32> [#uses=1]*/
load_noop7 = var124 + 32'd0;
/* br label %normalizeFloat64Subnormal.exit42.i.i_9*/
cur_state = normalizeFloat64Subnormal_exit42_i_i_9;
end
normalizeFloat64Subnormal_exit42_i_i_9:
begin
/* %124 = add nsw i32 %load_noop7, %shiftCount.0.i.i35.i.i ; <i32> [#uses=1]*/
var125 = load_noop7 + shiftCount_0_i_i35_i_i;
/* br label %normalizeFloat64Subnormal.exit42.i.i_10*/
cur_state = normalizeFloat64Subnormal_exit42_i_i_10;
end
normalizeFloat64Subnormal_exit42_i_i_10:
begin
/* %125 = add nsw i32 %124, %shiftCount.1.i.i.i39.i.i ; <i32> [#uses=2]*/
var126 = var125 + shiftCount_1_i_i_i39_i_i;
/* br label %normalizeFloat64Subnormal.exit42.i.i_11*/
cur_state = normalizeFloat64Subnormal_exit42_i_i_11;
end
normalizeFloat64Subnormal_exit42_i_i_11:
begin
/* %126 = add i32 %125, -11 ; <i32> [#uses=1]*/
var127 = var126 + -32'd11;
/* %127 = sub i32 12, %125 ; <i32> [#uses=1]*/
var128 = 32'd12 - var126;
/* br label %normalizeFloat64Subnormal.exit42.i.i_12*/
cur_state = normalizeFloat64Subnormal_exit42_i_i_12;
end
normalizeFloat64Subnormal_exit42_i_i_12:
begin
/* %.cast.i41.i.i = zext i32 %126 to i64 ; <i64> [#uses=1]*/
_cast_i41_i_i = var127;
/* br label %normalizeFloat64Subnormal.exit42.i.i_13*/
cur_state = normalizeFloat64Subnormal_exit42_i_i_13;
end
normalizeFloat64Subnormal_exit42_i_i_13:
begin
/* %128 = shl i64 %32, %.cast.i41.i.i ; <i64> [#uses=1]*/
var129 = var32 <<< (_cast_i41_i_i % 64);
/* br label %bb17.i.i*/
bSig_0_i_i = var129; /* for PHI node */
bExp_0_i_i = var128; /* for PHI node */
cur_state = bb17_i_i;
end
bb17_i_i:
begin
/* %bSig.0.i.i = phi i64 [ %128, %normalizeFloat64Subnormal.exit42.i.i_13 ], [ %32, %bb7.i.i ] ; <i64> [#uses=5]*/
/* %bExp.0.i.i = phi i32 [ %127, %normalizeFloat64Subnormal.exit42.i.i_13 ], [ %39, %bb7.i.i ] ; <i32> [#uses=1]*/
/* %129 = icmp eq i32 %38, 0 ; <i1> [#uses=1]*/
var130 = var38 == 32'd0;
/* br label %bb17.i.i_1*/
cur_state = bb17_i_i_1;
end
bb17_i_i_1:
begin
/* br i1 %129, label %bb18.i.i, label %bb21.i.i*/
if (var130) begin
cur_state = bb18_i_i;
end
else begin
aSig_1_i_i = var30; /* for PHI node */
aExp_0_i_i = var38; /* for PHI node */
cur_state = bb21_i_i;
end
end
bb18_i_i:
begin
/* %130 = icmp eq i64 %30, 0 ; <i1> [#uses=1]*/
var131 = var30 == 64'd0;
/* br label %bb18.i.i_1*/
cur_state = bb18_i_i_1;
end
bb18_i_i_1:
begin
/* br i1 %130, label %bb19.i.i, label %bb20.i.i*/
if (var131) begin
cur_state = bb19_i_i;
end
else begin
cur_state = bb20_i_i;
end
end
bb19_i_i:
begin
/* %131 = and i64 %34, -9223372036854775808 ; <i64> [#uses=1]*/
var132 = var34 & -64'd9223372036854775808;
/* br label %float64_div.exit.i*/
var60 = var132; /* for PHI node */
cur_state = float64_div_exit_i;
end
bb20_i_i:
begin
/* %132 = icmp ult i64 %30, 4294967296 ; <i1> [#uses=1]*/
var133 = var30 < 64'd4294967296;
/* br label %bb20.i.i_1*/
cur_state = bb20_i_i_1;
end
bb20_i_i_1:
begin
/* br i1 %132, label %bb.i.i.i.i, label %bb1.i.i.i.i*/
if (var133) begin
cur_state = bb_i_i_i_i;
end
else begin
cur_state = bb1_i_i_i_i;
end
end
bb_i_i_i_i:
begin
/* %extract.t.i.i.i.i = trunc i64 %29 to i32 ; <i32> [#uses=1]*/
extract_t_i_i_i_i = var29[31:0];
/* br label %normalizeFloat64Subnormal.exit.i.i*/
shiftCount_0_i_i_i_i = 32'd32; /* for PHI node */
a_addr_0_off0_i_i_i_i = extract_t_i_i_i_i; /* for PHI node */
cur_state = normalizeFloat64Subnormal_exit_i_i;
end
bb1_i_i_i_i:
begin
/* %133 = lshr i64 %30, 32 ; <i64> [#uses=1]*/
var134 = var30 >>> (64'd32 % 64);
/* br label %bb1.i.i.i.i_1*/
cur_state = bb1_i_i_i_i_1;
end
bb1_i_i_i_i_1:
begin
/* %extract.t4.i.i.i.i = trunc i64 %133 to i32 ; <i32> [#uses=1]*/
extract_t4_i_i_i_i = var134[31:0];
/* br label %normalizeFloat64Subnormal.exit.i.i*/
shiftCount_0_i_i_i_i = 32'd0; /* for PHI node */
a_addr_0_off0_i_i_i_i = extract_t4_i_i_i_i; /* for PHI node */
cur_state = normalizeFloat64Subnormal_exit_i_i;
end
normalizeFloat64Subnormal_exit_i_i:
begin
/* %shiftCount.0.i.i.i.i = phi i32 [ 32, %bb.i.i.i.i ], [ 0, %bb1.i.i.i.i_1 ] ; <i32> [#uses=1]*/
/* %a_addr.0.off0.i.i.i.i = phi i32 [ %extract.t.i.i.i.i, %bb.i.i.i.i ], [ %extract.t4.i.i.i.i, %bb1.i.i.i.i_1 ] ; <i32> [#uses=3]*/
/* br label %normalizeFloat64Subnormal.exit.i.i_1*/
cur_state = normalizeFloat64Subnormal_exit_i_i_1;
end
normalizeFloat64Subnormal_exit_i_i_1:
begin
/* %134 = shl i32 %a_addr.0.off0.i.i.i.i, 16 ; <i32> [#uses=1]*/
var135 = a_addr_0_off0_i_i_i_i <<< (32'd16 % 32);
/* %135 = icmp ult i32 %a_addr.0.off0.i.i.i.i, 65536 ; <i1> [#uses=2]*/
var136 = a_addr_0_off0_i_i_i_i < 32'd65536;
/* br label %normalizeFloat64Subnormal.exit.i.i_2*/
cur_state = normalizeFloat64Subnormal_exit_i_i_2;
end
normalizeFloat64Subnormal_exit_i_i_2:
begin
/* %.a.i.i.i.i.i = select i1 %135, i32 %134, i32 %a_addr.0.off0.i.i.i.i ; <i32> [#uses=3]*/
_a_i_i_i_i_i = (var136) ? var135 : a_addr_0_off0_i_i_i_i;
/* %shiftCount.0.i.i.i.i.i = select i1 %135, i32 16, i32 0 ; <i32> [#uses=2]*/
shiftCount_0_i_i_i_i_i = (var136) ? 32'd16 : 32'd0;
/* br label %normalizeFloat64Subnormal.exit.i.i_3*/
cur_state = normalizeFloat64Subnormal_exit_i_i_3;
end
normalizeFloat64Subnormal_exit_i_i_3:
begin
/* %136 = icmp ult i32 %.a.i.i.i.i.i, 16777216 ; <i1> [#uses=2]*/
var137 = _a_i_i_i_i_i < 32'd16777216;
/* %137 = or i32 %shiftCount.0.i.i.i.i.i, 8 ; <i32> [#uses=1]*/
var138 = shiftCount_0_i_i_i_i_i | 32'd8;
/* %138 = shl i32 %.a.i.i.i.i.i, 8 ; <i32> [#uses=1]*/
var139 = _a_i_i_i_i_i <<< (32'd8 % 32);
/* br label %normalizeFloat64Subnormal.exit.i.i_4*/
cur_state = normalizeFloat64Subnormal_exit_i_i_4;
end
normalizeFloat64Subnormal_exit_i_i_4:
begin
/* %shiftCount.1.i.i.i.i.i = select i1 %136, i32 %137, i32 %shiftCount.0.i.i.i.i.i ; <i32> [#uses=1]*/
shiftCount_1_i_i_i_i_i = (var137) ? var138 : shiftCount_0_i_i_i_i_i;
/* %a_addr.1.i.i.i.i.i = select i1 %136, i32 %138, i32 %.a.i.i.i.i.i ; <i32> [#uses=1]*/
a_addr_1_i_i_i_i_i = (var137) ? var139 : _a_i_i_i_i_i;
/* br label %normalizeFloat64Subnormal.exit.i.i_5*/
cur_state = normalizeFloat64Subnormal_exit_i_i_5;
end
normalizeFloat64Subnormal_exit_i_i_5:
begin
/* %139 = lshr i32 %a_addr.1.i.i.i.i.i, 24 ; <i32> [#uses=1]*/
var140 = a_addr_1_i_i_i_i_i >>> (32'd24 % 32);
/* br label %normalizeFloat64Subnormal.exit.i.i_6*/
cur_state = normalizeFloat64Subnormal_exit_i_i_6;
end
normalizeFloat64Subnormal_exit_i_i_6:
begin
/* %140 = getelementptr inbounds [256 x i32]* @countLeadingZerosHigh.1302, i32 0, i32 %139 ; <i32*> [#uses=1]*/
var141 = {`TAG_countLeadingZerosHigh_1302, 32'b0} + ((var140 + 256*(32'd0)) << 2);
/* br label %normalizeFloat64Subnormal.exit.i.i_7*/
cur_state = normalizeFloat64Subnormal_exit_i_i_7;
end
normalizeFloat64Subnormal_exit_i_i_7:
begin
/* %141 = load i32* %140, align 4 ; <i32> [#uses=1]*/
/* br label %normalizeFloat64Subnormal.exit.i.i_8*/
cur_state = normalizeFloat64Subnormal_exit_i_i_8;
end
normalizeFloat64Subnormal_exit_i_i_8:
begin
var142 = memory_controller_out[31:0];
/* %load_noop8 = add i32 %141, 0 ; <i32> [#uses=1]*/
load_noop8 = var142 + 32'd0;
/* br label %normalizeFloat64Subnormal.exit.i.i_9*/
cur_state = normalizeFloat64Subnormal_exit_i_i_9;
end
normalizeFloat64Subnormal_exit_i_i_9:
begin
/* %142 = add nsw i32 %load_noop8, %shiftCount.0.i.i.i.i ; <i32> [#uses=1]*/
var143 = load_noop8 + shiftCount_0_i_i_i_i;
/* br label %normalizeFloat64Subnormal.exit.i.i_10*/
cur_state = normalizeFloat64Subnormal_exit_i_i_10;
end
normalizeFloat64Subnormal_exit_i_i_10:
begin
/* %143 = add nsw i32 %142, %shiftCount.1.i.i.i.i.i ; <i32> [#uses=2]*/
var144 = var143 + shiftCount_1_i_i_i_i_i;
/* br label %normalizeFloat64Subnormal.exit.i.i_11*/
cur_state = normalizeFloat64Subnormal_exit_i_i_11;
end
normalizeFloat64Subnormal_exit_i_i_11:
begin
/* %144 = add i32 %143, -11 ; <i32> [#uses=1]*/
var145 = var144 + -32'd11;
/* %145 = sub i32 12, %143 ; <i32> [#uses=1]*/
var146 = 32'd12 - var144;
/* br label %normalizeFloat64Subnormal.exit.i.i_12*/
cur_state = normalizeFloat64Subnormal_exit_i_i_12;
end
normalizeFloat64Subnormal_exit_i_i_12:
begin
/* %.cast.i.i.i = zext i32 %144 to i64 ; <i64> [#uses=1]*/
_cast_i_i_i = var145;
/* br label %normalizeFloat64Subnormal.exit.i.i_13*/
cur_state = normalizeFloat64Subnormal_exit_i_i_13;
end
normalizeFloat64Subnormal_exit_i_i_13:
begin
/* %146 = shl i64 %30, %.cast.i.i.i ; <i64> [#uses=1]*/
var147 = var30 <<< (_cast_i_i_i % 64);
/* br label %bb21.i.i*/
aSig_1_i_i = var147; /* for PHI node */
aExp_0_i_i = var146; /* for PHI node */
cur_state = bb21_i_i;
end
bb21_i_i:
begin
/* %aSig.1.i.i = phi i64 [ %146, %normalizeFloat64Subnormal.exit.i.i_13 ], [ %30, %bb17.i.i_1 ] ; <i64> [#uses=1]*/
/* %aExp.0.i.i = phi i32 [ %145, %normalizeFloat64Subnormal.exit.i.i_13 ], [ %38, %bb17.i.i_1 ] ; <i32> [#uses=1]*/
/* %147 = shl i64 %bSig.0.i.i, 11 ; <i64> [#uses=3]*/
var148 = bSig_0_i_i <<< (64'd11 % 64);
/* br label %bb21.i.i_1*/
cur_state = bb21_i_i_1;
end
bb21_i_i_1:
begin
/* %148 = shl i64 %aSig.1.i.i, 10 ; <i64> [#uses=1]*/
var149 = aSig_1_i_i <<< (64'd10 % 64);
/* %149 = or i64 %147, -9223372036854775808 ; <i64> [#uses=9]*/
var150 = var148 | -64'd9223372036854775808;
/* %150 = sub i32 %aExp.0.i.i, %bExp.0.i.i ; <i32> [#uses=1]*/
var151 = aExp_0_i_i - bExp_0_i_i;
/* br label %bb21.i.i_2*/
cur_state = bb21_i_i_2;
end
bb21_i_i_2:
begin
/* %151 = or i64 %148, 4611686018427387904 ; <i64> [#uses=2]*/
var152 = var149 | 64'd4611686018427387904;
/* br label %bb21.i.i_3*/
cur_state = bb21_i_i_3;
end
bb21_i_i_3:
begin
/* %152 = shl i64 %151, 1 ; <i64> [#uses=1]*/
var153 = var152 <<< (64'd1 % 64);
/* br label %bb21.i.i_4*/
cur_state = bb21_i_i_4;
end
bb21_i_i_4:
begin
/* %153 = icmp ult i64 %152, %149 ; <i1> [#uses=2]*/
var154 = var153 < var150;
/* br label %bb21.i.i_5*/
cur_state = bb21_i_i_5;
end
bb21_i_i_5:
begin
/* %154 = zext i1 %153 to i64 ; <i64> [#uses=1]*/
var155 = var154;
/* %zExp.0.v.i.i = select i1 %153, i32 1021, i32 1022 ; <i32> [#uses=1]*/
zExp_0_v_i_i = (var154) ? 32'd1021 : 32'd1022;
/* br label %bb21.i.i_6*/
cur_state = bb21_i_i_6;
end
bb21_i_i_6:
begin
/* %155 = xor i64 %154, 1 ; <i64> [#uses=1]*/
var156 = var155 ^ 64'd1;
/* %zExp.0.i.i = add i32 %150, %zExp.0.v.i.i ; <i32> [#uses=1]*/
zExp_0_i_i = var151 + zExp_0_v_i_i;
/* br label %bb21.i.i_7*/
cur_state = bb21_i_i_7;
end
bb21_i_i_7:
begin
/* %aSig.0.i.i = lshr i64 %151, %155 ; <i64> [#uses=5]*/
aSig_0_i_i = var152 >>> (var156 % 64);
/* br label %bb21.i.i_8*/
cur_state = bb21_i_i_8;
end
bb21_i_i_8:
begin
/* %156 = icmp ugt i64 %149, %aSig.0.i.i ; <i1> [#uses=1]*/
var157 = var150 > aSig_0_i_i;
/* br label %bb21.i.i_9*/
cur_state = bb21_i_i_9;
end
bb21_i_i_9:
begin
/* br i1 %156, label %bb1.i.i.i, label %estimateDiv128To64.exit.i.i*/
if (var157) begin
cur_state = bb1_i_i_i;
end
else begin
var158 = -64'd1; /* for PHI node */
cur_state = estimateDiv128To64_exit_i_i;
end
end
bb1_i_i_i:
begin
/* %157 = lshr i64 %149, 32 ; <i64> [#uses=4]*/
var159 = var150 >>> (64'd32 % 64);
/* %158 = and i64 %149, -4294967296 ; <i64> [#uses=2]*/
var160 = var150 & -64'd4294967296;
/* br label %bb1.i.i.i_1*/
cur_state = bb1_i_i_i_1;
end
bb1_i_i_i_1:
begin
/* %159 = icmp ugt i64 %158, %aSig.0.i.i ; <i1> [#uses=1]*/
var161 = var160 > aSig_0_i_i;
/* br label %bb1.i.i.i_2*/
cur_state = bb1_i_i_i_2;
end
bb1_i_i_i_2:
begin
/* br i1 %159, label %bb2.i.i3.i, label %bb4.i.i.i*/
if (var161) begin
cur_state = bb2_i_i3_i;
end
else begin
iftmp_18_0_i_i_i = -64'd4294967296; /* for PHI node */
cur_state = bb4_i_i_i;
end
end
bb2_i_i3_i:
begin
/* %160 = udiv i64 %aSig.0.i.i, %157 ; <i64> [#uses=1]*/
var162 = aSig_0_i_i / var159;
/* br label %bb2.i.i3.i_1*/
cur_state = bb2_i_i3_i_1;
end
bb2_i_i3_i_1:
begin
/* %161 = shl i64 %160, 32 ; <i64> [#uses=1]*/
var163 = var162 <<< (64'd32 % 64);
/* br label %bb4.i.i.i*/
iftmp_18_0_i_i_i = var163; /* for PHI node */
cur_state = bb4_i_i_i;
end
bb4_i_i_i:
begin
/* %iftmp.18.0.i.i.i = phi i64 [ %161, %bb2.i.i3.i_1 ], [ -4294967296, %bb1.i.i.i_2 ] ; <i64> [#uses=3]*/
/* %162 = and i64 %147, 4294965248 ; <i64> [#uses=1]*/
var164 = var148 & 64'd4294965248;
/* br label %bb4.i.i.i_1*/
cur_state = bb4_i_i_i_1;
end
bb4_i_i_i_1:
begin
/* %163 = lshr i64 %iftmp.18.0.i.i.i, 32 ; <i64> [#uses=3]*/
var165 = iftmp_18_0_i_i_i >>> (64'd32 % 64);
/* br label %bb4.i.i.i_2*/
cur_state = bb4_i_i_i_2;
end
bb4_i_i_i_2:
begin
/* %164 = mul i64 %163, %162 ; <i64> [#uses=2]*/
var166 = var165 * var164;
/* %165 = mul i64 %163, %157 ; <i64> [#uses=1]*/
var167 = var165 * var159;
/* br label %bb4.i.i.i_3*/
cur_state = bb4_i_i_i_3;
end
bb4_i_i_i_3:
begin
/* %166 = lshr i64 %164, 32 ; <i64> [#uses=1]*/
var168 = var166 >>> (64'd32 % 64);
/* %167 = shl i64 %164, 32 ; <i64> [#uses=2]*/
var169 = var166 <<< (64'd32 % 64);
/* %.neg2.i.i.i = sub i64 %aSig.0.i.i, %165 ; <i64> [#uses=1]*/
_neg2_i_i_i = aSig_0_i_i - var167;
/* br label %bb4.i.i.i_4*/
cur_state = bb4_i_i_i_4;
end
bb4_i_i_i_4:
begin
/* %168 = sub i64 0, %167 ; <i64> [#uses=1]*/
var170 = 64'd0 - var169;
/* %169 = icmp ne i64 %167, 0 ; <i1> [#uses=1]*/
var171 = var169 != 64'd0;
/* %170 = sub i64 %.neg2.i.i.i, %166 ; <i64> [#uses=1]*/
var172 = _neg2_i_i_i - var168;
/* br label %bb4.i.i.i_5*/
cur_state = bb4_i_i_i_5;
end
bb4_i_i_i_5:
begin
/* %.neg.i.i.i.i = select i1 %169, i64 -1, i64 0 ; <i64> [#uses=1]*/
_neg_i_i_i_i = (var171) ? -64'd1 : 64'd0;
/* br label %bb4.i.i.i_6*/
cur_state = bb4_i_i_i_6;
end
bb4_i_i_i_6:
begin
/* %171 = add i64 %170, %.neg.i.i.i.i ; <i64> [#uses=3]*/
var173 = var172 + _neg_i_i_i_i;
/* br label %bb4.i.i.i_7*/
cur_state = bb4_i_i_i_7;
end
bb4_i_i_i_7:
begin
/* %172 = icmp slt i64 %171, 0 ; <i1> [#uses=1]*/
var174 = $signed(var173) < $signed(64'd0);
/* br label %bb4.i.i.i_8*/
cur_state = bb4_i_i_i_8;
end
bb4_i_i_i_8:
begin
/* br i1 %172, label %bb.nph.i.i.i, label %bb7.i.i.i*/
if (var174) begin
cur_state = bb_nph_i_i_i;
end
else begin
z_0_lcssa_i_i_i = iftmp_18_0_i_i_i; /* for PHI node */
rem0_0_lcssa_i_i_i = var173; /* for PHI node */
rem1_0_lcssa_i_i_i = var170; /* for PHI node */
cur_state = bb7_i_i_i;
end
end
bb_nph_i_i_i:
begin
/* %bSig.0130.i.i = trunc i64 %bSig.0.i.i to i32 ; <i32> [#uses=1]*/
bSig_0130_i_i = bSig_0_i_i[31:0];
/* %tmp125.i.i = shl i64 %bSig.0.i.i, 43 ; <i64> [#uses=1]*/
tmp125_i_i = bSig_0_i_i <<< (64'd43 % 64);
/* br label %bb.nph.i.i.i_1*/
cur_state = bb_nph_i_i_i_1;
end
bb_nph_i_i_i_1:
begin
/* %tmp121.i.i = shl i32 %bSig.0130.i.i, 11 ; <i32> [#uses=1]*/
tmp121_i_i = bSig_0130_i_i <<< (32'd11 % 32);
/* br label %bb.nph.i.i.i_2*/
cur_state = bb_nph_i_i_i_2;
end
bb_nph_i_i_i_2:
begin
/* %tmp122.i.i = zext i32 %tmp121.i.i to i64 ; <i64> [#uses=1]*/
tmp122_i_i = tmp121_i_i;
/* br label %bb.nph.i.i.i_3*/
cur_state = bb_nph_i_i_i_3;
end
bb_nph_i_i_i_3:
begin
/* %tmp123.i.i = mul i64 %163, %tmp122.i.i ; <i64> [#uses=1]*/
tmp123_i_i = var165 * tmp122_i_i;
/* br label %bb.nph.i.i.i_4*/
cur_state = bb_nph_i_i_i_4;
end
bb_nph_i_i_i_4:
begin
/* %tmp124.i.i = mul i64 %tmp123.i.i, -4294967296 ; <i64> [#uses=2]*/
tmp124_i_i = tmp123_i_i * -64'd4294967296;
/* br label %bb.nph.i.i.i_5*/
cur_state = bb_nph_i_i_i_5;
end
bb_nph_i_i_i_5:
begin
/* %tmp126.i.i = add i64 %tmp124.i.i, %tmp125.i.i ; <i64> [#uses=1]*/
tmp126_i_i = tmp124_i_i + tmp125_i_i;
/* br label %bb5.i.i.i*/
var175 = 64'd0; /* for PHI node */
rem0_05_i_i_i = var173; /* for PHI node */
cur_state = bb5_i_i_i;
end
bb5_i_i_i:
begin
/* %173 = phi i64 [ 0, %bb.nph.i.i.i_5 ], [ %indvar.next.i.i.i, %bb5.i.i.i_8 ] ; <i64> [#uses=3]*/
/* %rem0.05.i.i.i = phi i64 [ %171, %bb.nph.i.i.i_5 ], [ %177, %bb5.i.i.i_8 ] ; <i64> [#uses=1]*/
/* br label %bb5.i.i.i_1*/
cur_state = bb5_i_i_i_1;
end
bb5_i_i_i_1:
begin
/* %tmp117.i.i = mul i64 %173, %bSig.0.i.i ; <i64> [#uses=1]*/
tmp117_i_i = var175 * bSig_0_i_i;
/* %174 = add i64 %rem0.05.i.i.i, %157 ; <i64> [#uses=1]*/
var176 = rem0_05_i_i_i + var159;
/* %indvar.next.i.i.i = add i64 %173, 1 ; <i64> [#uses=1]*/
indvar_next_i_i_i = var175 + 64'd1;
/* br label %bb5.i.i.i_2*/
cur_state = bb5_i_i_i_2;
end
bb5_i_i_i_2:
begin
/* %tmp118.i.i = shl i64 %tmp117.i.i, 43 ; <i64> [#uses=2]*/
tmp118_i_i = tmp117_i_i <<< (64'd43 % 64);
/* br label %bb5.i.i.i_3*/
cur_state = bb5_i_i_i_3;
end
bb5_i_i_i_3:
begin
/* %tmp23.i.i.i = add i64 %tmp118.i.i, %tmp126.i.i ; <i64> [#uses=2]*/
tmp23_i_i_i = tmp118_i_i + tmp126_i_i;
/* %rem1.04.i.i.i = add i64 %tmp118.i.i, %tmp124.i.i ; <i64> [#uses=1]*/
rem1_04_i_i_i = tmp118_i_i + tmp124_i_i;
/* br label %bb5.i.i.i_4*/
cur_state = bb5_i_i_i_4;
end
bb5_i_i_i_4:
begin
/* %175 = icmp ult i64 %tmp23.i.i.i, %rem1.04.i.i.i ; <i1> [#uses=1]*/
var177 = tmp23_i_i_i < rem1_04_i_i_i;
/* br label %bb5.i.i.i_5*/
cur_state = bb5_i_i_i_5;
end
bb5_i_i_i_5:
begin
/* %176 = zext i1 %175 to i64 ; <i64> [#uses=1]*/
var178 = var177;
/* br label %bb5.i.i.i_6*/
cur_state = bb5_i_i_i_6;
end
bb5_i_i_i_6:
begin
/* %177 = add i64 %174, %176 ; <i64> [#uses=3]*/
var179 = var176 + var178;
/* br label %bb5.i.i.i_7*/
cur_state = bb5_i_i_i_7;
end
bb5_i_i_i_7:
begin
/* %178 = icmp slt i64 %177, 0 ; <i1> [#uses=1]*/
var180 = $signed(var179) < $signed(64'd0);
/* br label %bb5.i.i.i_8*/
cur_state = bb5_i_i_i_8;
end
bb5_i_i_i_8:
begin
/* br i1 %178, label %bb5.i.i.i, label %bb6.bb7_crit_edge.i.i.i*/
if (var180) begin
var175 = indvar_next_i_i_i; /* for PHI node */
rem0_05_i_i_i = var179; /* for PHI node */
cur_state = bb5_i_i_i;
end
else begin
cur_state = bb6_bb7_crit_edge_i_i_i;
end
end
bb6_bb7_crit_edge_i_i_i:
begin
/* %tmp.i.i.i = mul i64 %173, -4294967296 ; <i64> [#uses=1]*/
tmp_i_i_i = var175 * -64'd4294967296;
/* %tmp11.i.i.i = add i64 %iftmp.18.0.i.i.i, -4294967296 ; <i64> [#uses=1]*/
tmp11_i_i_i = iftmp_18_0_i_i_i + -64'd4294967296;
/* br label %bb6.bb7_crit_edge.i.i.i_1*/
cur_state = bb6_bb7_crit_edge_i_i_i_1;
end
bb6_bb7_crit_edge_i_i_i_1:
begin
/* %tmp12.i.i.i = add i64 %tmp11.i.i.i, %tmp.i.i.i ; <i64> [#uses=1]*/
tmp12_i_i_i = tmp11_i_i_i + tmp_i_i_i;
/* br label %bb7.i.i.i*/
z_0_lcssa_i_i_i = tmp12_i_i_i; /* for PHI node */
rem0_0_lcssa_i_i_i = var179; /* for PHI node */
rem1_0_lcssa_i_i_i = tmp23_i_i_i; /* for PHI node */
cur_state = bb7_i_i_i;
end
bb7_i_i_i:
begin
/* %z.0.lcssa.i.i.i = phi i64 [ %tmp12.i.i.i, %bb6.bb7_crit_edge.i.i.i_1 ], [ %iftmp.18.0.i.i.i, %bb4.i.i.i_8 ] ; <i64> [#uses=1]*/
/* %rem0.0.lcssa.i.i.i = phi i64 [ %177, %bb6.bb7_crit_edge.i.i.i_1 ], [ %171, %bb4.i.i.i_8 ] ; <i64> [#uses=1]*/
/* %rem1.0.lcssa.i.i.i = phi i64 [ %tmp23.i.i.i, %bb6.bb7_crit_edge.i.i.i_1 ], [ %168, %bb4.i.i.i_8 ] ; <i64> [#uses=1]*/
/* br label %bb7.i.i.i_1*/
cur_state = bb7_i_i_i_1;
end
bb7_i_i_i_1:
begin
/* %179 = shl i64 %rem0.0.lcssa.i.i.i, 32 ; <i64> [#uses=1]*/
var181 = rem0_0_lcssa_i_i_i <<< (64'd32 % 64);
/* %180 = lshr i64 %rem1.0.lcssa.i.i.i, 32 ; <i64> [#uses=1]*/
var182 = rem1_0_lcssa_i_i_i >>> (64'd32 % 64);
/* br label %bb7.i.i.i_2*/
cur_state = bb7_i_i_i_2;
end
bb7_i_i_i_2:
begin
/* %181 = or i64 %180, %179 ; <i64> [#uses=2]*/
var183 = var182 | var181;
/* br label %bb7.i.i.i_3*/
cur_state = bb7_i_i_i_3;
end
bb7_i_i_i_3:
begin
/* %182 = icmp ugt i64 %158, %181 ; <i1> [#uses=1]*/
var184 = var160 > var183;
/* br label %bb7.i.i.i_4*/
cur_state = bb7_i_i_i_4;
end
bb7_i_i_i_4:
begin
/* br i1 %182, label %bb8.i.i.i, label %bb10.i.i4.i*/
if (var184) begin
cur_state = bb8_i_i_i;
end
else begin
iftmp_27_0_i_i_i = 64'd4294967295; /* for PHI node */
cur_state = bb10_i_i4_i;
end
end
bb8_i_i_i:
begin
/* %183 = udiv i64 %181, %157 ; <i64> [#uses=1]*/
var185 = var183 / var159;
/* br label %bb10.i.i4.i*/
iftmp_27_0_i_i_i = var185; /* for PHI node */
cur_state = bb10_i_i4_i;
end
bb10_i_i4_i:
begin
/* %iftmp.27.0.i.i.i = phi i64 [ %183, %bb8.i.i.i ], [ 4294967295, %bb7.i.i.i_4 ] ; <i64> [#uses=1]*/
/* br label %bb10.i.i4.i_1*/
cur_state = bb10_i_i4_i_1;
end
bb10_i_i4_i_1:
begin
/* %184 = or i64 %iftmp.27.0.i.i.i, %z.0.lcssa.i.i.i ; <i64> [#uses=1]*/
var186 = iftmp_27_0_i_i_i | z_0_lcssa_i_i_i;
/* br label %estimateDiv128To64.exit.i.i*/
var158 = var186; /* for PHI node */
cur_state = estimateDiv128To64_exit_i_i;
end
estimateDiv128To64_exit_i_i:
begin
/* %185 = phi i64 [ %184, %bb10.i.i4.i_1 ], [ -1, %bb21.i.i_9 ] ; <i64> [#uses=6]*/
/* br label %estimateDiv128To64.exit.i.i_1*/
cur_state = estimateDiv128To64_exit_i_i_1;
end
estimateDiv128To64_exit_i_i_1:
begin
/* %186 = and i64 %185, 511 ; <i64> [#uses=1]*/
var187 = var158 & 64'd511;
/* br label %estimateDiv128To64.exit.i.i_2*/
cur_state = estimateDiv128To64_exit_i_i_2;
end
estimateDiv128To64_exit_i_i_2:
begin
/* %187 = icmp ult i64 %186, 3 ; <i1> [#uses=1]*/
var188 = var187 < 64'd3;
/* br label %estimateDiv128To64.exit.i.i_3*/
cur_state = estimateDiv128To64_exit_i_i_3;
end
estimateDiv128To64_exit_i_i_3:
begin
/* br i1 %187, label %bb24.i.i, label %bb28.i.i*/
if (var188) begin
cur_state = bb24_i_i;
end
else begin
zSig_1_i_i = var158; /* for PHI node */
cur_state = bb28_i_i;
end
end
bb24_i_i:
begin
/* %188 = lshr i64 %149, 32 ; <i64> [#uses=3]*/
var189 = var150 >>> (64'd32 % 64);
/* %189 = lshr i64 %185, 32 ; <i64> [#uses=3]*/
var190 = var158 >>> (64'd32 % 64);
/* %190 = and i64 %147, 4294965248 ; <i64> [#uses=2]*/
var191 = var148 & 64'd4294965248;
/* %191 = and i64 %185, 4294967295 ; <i64> [#uses=4]*/
var192 = var158 & 64'd4294967295;
/* br label %bb24.i.i_1*/
cur_state = bb24_i_i_1;
end
bb24_i_i_1:
begin
/* %192 = mul i64 %191, %190 ; <i64> [#uses=1]*/
var193 = var192 * var191;
/* %193 = mul i64 %189, %190 ; <i64> [#uses=1]*/
var194 = var190 * var191;
/* %194 = mul i64 %191, %188 ; <i64> [#uses=2]*/
var195 = var192 * var189;
/* %195 = mul i64 %189, %188 ; <i64> [#uses=1]*/
var196 = var190 * var189;
/* br label %bb24.i.i_2*/
cur_state = bb24_i_i_2;
end
bb24_i_i_2:
begin
/* %196 = add i64 %193, %194 ; <i64> [#uses=3]*/
var197 = var194 + var195;
/* %.neg82.i.i = sub i64 %aSig.0.i.i, %195 ; <i64> [#uses=1]*/
_neg82_i_i = aSig_0_i_i - var196;
/* br label %bb24.i.i_3*/
cur_state = bb24_i_i_3;
end
bb24_i_i_3:
begin
/* %197 = icmp ult i64 %196, %194 ; <i1> [#uses=1]*/
var198 = var197 < var195;
/* %198 = lshr i64 %196, 32 ; <i64> [#uses=1]*/
var199 = var197 >>> (64'd32 % 64);
/* %199 = shl i64 %196, 32 ; <i64> [#uses=2]*/
var200 = var197 <<< (64'd32 % 64);
/* br label %bb24.i.i_4*/
cur_state = bb24_i_i_4;
end
bb24_i_i_4:
begin
/* %iftmp.17.0.i.i.i = select i1 %197, i64 4294967296, i64 0 ; <i64> [#uses=1]*/
iftmp_17_0_i_i_i = (var198) ? 64'd4294967296 : 64'd0;
/* %200 = add i64 %199, %192 ; <i64> [#uses=3]*/
var201 = var200 + var193;
/* br label %bb24.i.i_5*/
cur_state = bb24_i_i_5;
end
bb24_i_i_5:
begin
/* %201 = or i64 %iftmp.17.0.i.i.i, %198 ; <i64> [#uses=1]*/
var202 = iftmp_17_0_i_i_i | var199;
/* %202 = icmp ult i64 %200, %199 ; <i1> [#uses=1]*/
var203 = var201 < var200;
/* %203 = sub i64 0, %200 ; <i64> [#uses=2]*/
var204 = 64'd0 - var201;
/* %204 = icmp ne i64 %200, 0 ; <i1> [#uses=1]*/
var205 = var201 != 64'd0;
/* br label %bb24.i.i_6*/
cur_state = bb24_i_i_6;
end
bb24_i_i_6:
begin
/* %.neg.i.i.i = select i1 %204, i64 -1, i64 0 ; <i64> [#uses=1]*/
_neg_i_i_i = (var205) ? -64'd1 : 64'd0;
/* %.neg83.i.i = select i1 %202, i64 -1, i64 0 ; <i64> [#uses=1]*/
_neg83_i_i = (var203) ? -64'd1 : 64'd0;
/* %.neg84.i.i = sub i64 %.neg82.i.i, %201 ; <i64> [#uses=1]*/
_neg84_i_i = _neg82_i_i - var202;
/* br label %bb24.i.i_7*/
cur_state = bb24_i_i_7;
end
bb24_i_i_7:
begin
/* %205 = add i64 %.neg84.i.i, %.neg.i.i.i ; <i64> [#uses=1]*/
var206 = _neg84_i_i + _neg_i_i_i;
/* br label %bb24.i.i_8*/
cur_state = bb24_i_i_8;
end
bb24_i_i_8:
begin
/* %206 = add i64 %205, %.neg83.i.i ; <i64> [#uses=2]*/
var207 = var206 + _neg83_i_i;
/* br label %bb24.i.i_9*/
cur_state = bb24_i_i_9;
end
bb24_i_i_9:
begin
/* %207 = icmp slt i64 %206, 0 ; <i1> [#uses=1]*/
var208 = $signed(var207) < $signed(64'd0);
/* br label %bb24.i.i_10*/
cur_state = bb24_i_i_10;
end
bb24_i_i_10:
begin
/* br i1 %207, label %bb.nph.i.i, label %bb27.i.i*/
if (var208) begin
cur_state = bb_nph_i_i;
end
else begin
zSig_0_lcssa_i_i = var158; /* for PHI node */
rem1_0_lcssa_i_i = var204; /* for PHI node */
cur_state = bb27_i_i;
end
end
bb_nph_i_i:
begin
/* %tmp91.i.i = add i64 %185, -1 ; <i64> [#uses=1]*/
tmp91_i_i = var158 + -64'd1;
/* %bSig.0129.i.i = trunc i64 %bSig.0.i.i to i32 ; <i32> [#uses=1]*/
bSig_0129_i_i = bSig_0_i_i[31:0];
/* %tmp103.i.i = mul i64 %188, %191 ; <i64> [#uses=1]*/
tmp103_i_i = var189 * var192;
/* br label %bb.nph.i.i_1*/
cur_state = bb_nph_i_i_1;
end
bb_nph_i_i_1:
begin
/* %tmp97.i.i = shl i32 %bSig.0129.i.i, 11 ; <i32> [#uses=1]*/
tmp97_i_i = bSig_0129_i_i <<< (32'd11 % 32);
/* br label %bb.nph.i.i_2*/
cur_state = bb_nph_i_i_2;
end
bb_nph_i_i_2:
begin
/* %tmp98.i.i = zext i32 %tmp97.i.i to i64 ; <i64> [#uses=2]*/
tmp98_i_i = tmp97_i_i;
/* br label %bb.nph.i.i_3*/
cur_state = bb_nph_i_i_3;
end
bb_nph_i_i_3:
begin
/* %tmp99.i.i = mul i64 %191, %tmp98.i.i ; <i64> [#uses=2]*/
tmp99_i_i = var192 * tmp98_i_i;
/* %tmp105.i.i = mul i64 %189, %tmp98.i.i ; <i64> [#uses=1]*/
tmp105_i_i = var190 * tmp98_i_i;
/* br label %bb.nph.i.i_4*/
cur_state = bb_nph_i_i_4;
end
bb_nph_i_i_4:
begin
/* %tmp101.i.i = sub i64 %149, %tmp99.i.i ; <i64> [#uses=1]*/
tmp101_i_i = var150 - tmp99_i_i;
/* %tmp106.i.i = add i64 %tmp103.i.i, %tmp105.i.i ; <i64> [#uses=2]*/
tmp106_i_i = tmp103_i_i + tmp105_i_i;
/* br label %bb.nph.i.i_5*/
cur_state = bb_nph_i_i_5;
end
bb_nph_i_i_5:
begin
/* %tmp107.i.i = mul i64 %tmp106.i.i, -4294967296 ; <i64> [#uses=1]*/
tmp107_i_i = tmp106_i_i * -64'd4294967296;
/* %tmp111.i.i = shl i64 %tmp106.i.i, 32 ; <i64> [#uses=1]*/
tmp111_i_i = tmp106_i_i <<< (64'd32 % 64);
/* br label %bb.nph.i.i_6*/
cur_state = bb_nph_i_i_6;
end
bb_nph_i_i_6:
begin
/* %tmp108.i.i = add i64 %tmp101.i.i, %tmp107.i.i ; <i64> [#uses=1]*/
tmp108_i_i = tmp101_i_i + tmp107_i_i;
/* %tmp112.i.i = add i64 %tmp99.i.i, %tmp111.i.i ; <i64> [#uses=1]*/
tmp112_i_i = tmp99_i_i + tmp111_i_i;
/* br label %bb.nph.i.i_7*/
cur_state = bb_nph_i_i_7;
end
bb_nph_i_i_7:
begin
/* %tmp114.i.i = sub i64 %149, %tmp112.i.i ; <i64> [#uses=1]*/
tmp114_i_i = var150 - tmp112_i_i;
/* br label %bb25.i.i*/
indvar_i_i = 64'd0; /* for PHI node */
rem1_087_i_i = var204; /* for PHI node */
rem0_085_i_i = var207; /* for PHI node */
cur_state = bb25_i_i;
end
bb25_i_i:
begin
/* %indvar.i.i = phi i64 [ 0, %bb.nph.i.i_7 ], [ %indvar.next.i.i, %bb25.i.i_7 ] ; <i64> [#uses=3]*/
/* %rem1.087.i.i = phi i64 [ %203, %bb.nph.i.i_7 ], [ %208, %bb25.i.i_7 ] ; <i64> [#uses=2]*/
/* %rem0.085.i.i = phi i64 [ %206, %bb.nph.i.i_7 ], [ %211, %bb25.i.i_7 ] ; <i64> [#uses=1]*/
/* br label %bb25.i.i_1*/
cur_state = bb25_i_i_1;
end
bb25_i_i_1:
begin
/* %tmp93.i.i = mul i64 %indvar.i.i, %149 ; <i64> [#uses=2]*/
tmp93_i_i = indvar_i_i * var150;
/* %208 = add i64 %rem1.087.i.i, %149 ; <i64> [#uses=1]*/
var209 = rem1_087_i_i + var150;
/* %indvar.next.i.i = add i64 %indvar.i.i, 1 ; <i64> [#uses=1]*/
indvar_next_i_i = indvar_i_i + 64'd1;
/* br label %bb25.i.i_2*/
cur_state = bb25_i_i_2;
end
bb25_i_i_2:
begin
/* %tmp115.i.i = add i64 %tmp93.i.i, %tmp114.i.i ; <i64> [#uses=1]*/
tmp115_i_i = tmp93_i_i + tmp114_i_i;
/* br label %bb25.i.i_3*/
cur_state = bb25_i_i_3;
end
bb25_i_i_3:
begin
/* %209 = icmp ult i64 %tmp115.i.i, %rem1.087.i.i ; <i1> [#uses=1]*/
var210 = tmp115_i_i < rem1_087_i_i;
/* br label %bb25.i.i_4*/
cur_state = bb25_i_i_4;
end
bb25_i_i_4:
begin
/* %210 = zext i1 %209 to i64 ; <i64> [#uses=1]*/
var211 = var210;
/* br label %bb25.i.i_5*/
cur_state = bb25_i_i_5;
end
bb25_i_i_5:
begin
/* %211 = add i64 %210, %rem0.085.i.i ; <i64> [#uses=2]*/
var212 = var211 + rem0_085_i_i;
/* br label %bb25.i.i_6*/
cur_state = bb25_i_i_6;
end
bb25_i_i_6:
begin
/* %212 = icmp slt i64 %211, 0 ; <i1> [#uses=1]*/
var213 = $signed(var212) < $signed(64'd0);
/* br label %bb25.i.i_7*/
cur_state = bb25_i_i_7;
end
bb25_i_i_7:
begin
/* br i1 %212, label %bb25.i.i, label %bb26.bb27_crit_edge.i.i*/
if (var213) begin
indvar_i_i = indvar_next_i_i; /* for PHI node */
rem1_087_i_i = var209; /* for PHI node */
rem0_085_i_i = var212; /* for PHI node */
cur_state = bb25_i_i;
end
else begin
cur_state = bb26_bb27_crit_edge_i_i;
end
end
bb26_bb27_crit_edge_i_i:
begin
/* %tmp92.i.i = sub i64 %tmp91.i.i, %indvar.i.i ; <i64> [#uses=1]*/
tmp92_i_i = tmp91_i_i - indvar_i_i;
/* %tmp109.i.i = add i64 %tmp93.i.i, %tmp108.i.i ; <i64> [#uses=1]*/
tmp109_i_i = tmp93_i_i + tmp108_i_i;
/* br label %bb27.i.i*/
zSig_0_lcssa_i_i = tmp92_i_i; /* for PHI node */
rem1_0_lcssa_i_i = tmp109_i_i; /* for PHI node */
cur_state = bb27_i_i;
end
bb27_i_i:
begin
/* %zSig.0.lcssa.i.i = phi i64 [ %tmp92.i.i, %bb26.bb27_crit_edge.i.i ], [ %185, %bb24.i.i_10 ] ; <i64> [#uses=1]*/
/* %rem1.0.lcssa.i.i = phi i64 [ %tmp109.i.i, %bb26.bb27_crit_edge.i.i ], [ %203, %bb24.i.i_10 ] ; <i64> [#uses=1]*/
/* br label %bb27.i.i_1*/
cur_state = bb27_i_i_1;
end
bb27_i_i_1:
begin
/* %213 = icmp ne i64 %rem1.0.lcssa.i.i, 0 ; <i1> [#uses=1]*/
var214 = rem1_0_lcssa_i_i != 64'd0;
/* br label %bb27.i.i_2*/
cur_state = bb27_i_i_2;
end
bb27_i_i_2:
begin
/* %214 = zext i1 %213 to i64 ; <i64> [#uses=1]*/
var215 = var214;
/* br label %bb27.i.i_3*/
cur_state = bb27_i_i_3;
end
bb27_i_i_3:
begin
/* %215 = or i64 %214, %zSig.0.lcssa.i.i ; <i64> [#uses=1]*/
var216 = var215 | zSig_0_lcssa_i_i;
/* br label %bb28.i.i*/
zSig_1_i_i = var216; /* for PHI node */
cur_state = bb28_i_i;
end
bb28_i_i:
begin
/* %zSig.1.i.i = phi i64 [ %215, %bb27.i.i_3 ], [ %185, %estimateDiv128To64.exit.i.i_3 ] ; <i64> [#uses=1]*/
/* br label %bb28.i.i_1*/
cur_state = bb28_i_i_1;
end
bb28_i_i_1:
begin
/* %216 = tail call fastcc i64 @roundAndPackFloat64(i32 %40, i32 %zExp.0.i.i, i64 %zSig.1.i.i) nounwind ; <i64> [#uses=1]*/
roundAndPackFloat64_start = 1;
/* Argument: %40 = trunc i64 %37 to i32 ; <i32> [#uses=1]*/
roundAndPackFloat64_zSign = var40;
/* Argument: %zExp.0.i.i = add i32 %150, %zExp.0.v.i.i ; <i32> [#uses=1]*/
roundAndPackFloat64_zExp = zExp_0_i_i;
/* Argument: %zSig.1.i.i = phi i64 [ %215, %bb27.i.i_3 ], [ %185, %estimateDiv128To64.exit.i.i_3 ] ; <i64> [#uses=1]*/
roundAndPackFloat64_zSig = zSig_1_i_i;
cur_state = bb28_i_i_1_call_0;
end
bb28_i_i_1_call_0:
begin
roundAndPackFloat64_start = 0;
if (roundAndPackFloat64_finish == 1)
begin
var217 = roundAndPackFloat64_return_val;
cur_state = bb28_i_i_1_call_1;
end
else
cur_state = bb28_i_i_1_call_0;
end
bb28_i_i_1_call_1:
begin
/* br label %float64_div.exit.i*/
var60 = var217; /* for PHI node */
cur_state = float64_div_exit_i;
end
float64_div_exit_i:
begin
/* %217 = phi i64 [ %216, %bb28.i.i_1 ], [ %131, %bb19.i.i ], [ %113, %bb15.i.i_1 ], [ 9223372036854775807, %bb14.i.i_1 ], [ %iftmp.34.0.i.i.i, %bb3.i.i2.i ], [ %104, %bb10.i.i ], [ %iftmp.34.0.i74.i.i, %bb3.i75.i.i ], [ %84, %bb6.i.i_1 ], [ %iftmp.34.0.i58.i.i, %bb3.i59.i.i ], [ 9223372036854775807, %bb5.i.i_3 ], [ %53, %bb2.i73.i.i_1 ], [ %54, %bb1.i72.i.i_1 ], [ %73, %bb2.i57.i.i_1 ], [ %74, %bb1.i56.i.i_1 ], [ %96, %bb2.i45.i.i_1 ], [ %97, %bb1.i44.i.i_1 ] ; <i64> [#uses=32]*/
/* %218 = lshr i64 %app.0.i, 63 ; <i64> [#uses=1]*/
var218 = app_0_i >>> (64'd63 % 64);
/* %219 = lshr i64 %app.0.i, 52 ; <i64> [#uses=1]*/
var219 = app_0_i >>> (64'd52 % 64);
/* br label %float64_div.exit.i_1*/
cur_state = float64_div_exit_i_1;
end
float64_div_exit_i_1:
begin
/* %220 = trunc i64 %218 to i32 ; <i32> [#uses=5]*/
var220 = var218[31:0];
/* %221 = lshr i64 %217, 63 ; <i64> [#uses=1]*/
var221 = var60 >>> (64'd63 % 64);
/* %222 = trunc i64 %219 to i32 ; <i32> [#uses=1]*/
var222 = var219[31:0];
/* %223 = lshr i64 %217, 52 ; <i64> [#uses=1]*/
var223 = var60 >>> (64'd52 % 64);
/* br label %float64_div.exit.i_2*/
cur_state = float64_div_exit_i_2;
end
float64_div_exit_i_2:
begin
/* %224 = trunc i64 %221 to i32 ; <i32> [#uses=1]*/
var224 = var221[31:0];
/* %225 = and i32 %222, 2047 ; <i32> [#uses=14]*/
var225 = var222 & 32'd2047;
/* %226 = trunc i64 %223 to i32 ; <i32> [#uses=1]*/
var226 = var223[31:0];
/* br label %float64_div.exit.i_3*/
cur_state = float64_div_exit_i_3;
end
float64_div_exit_i_3:
begin
/* %227 = icmp eq i32 %220, %224 ; <i1> [#uses=1]*/
var227 = var220 == var224;
/* %228 = and i32 %226, 2047 ; <i32> [#uses=10]*/
var228 = var226 & 32'd2047;
/* br label %float64_div.exit.i_4*/
cur_state = float64_div_exit_i_4;
end
float64_div_exit_i_4:
begin
/* %229 = sub i32 %225, %228 ; <i32> [#uses=10]*/
var229 = var225 - var228;
/* br i1 %227, label %bb.i5.i, label %bb1.i6.i*/
if (var227) begin
cur_state = bb_i5_i;
end
else begin
cur_state = bb1_i6_i;
end
end
bb_i5_i:
begin
/* %230 = shl i64 %app.0.i, 9 ; <i64> [#uses=1]*/
var230 = app_0_i <<< (64'd9 % 64);
/* %231 = shl i64 %217, 9 ; <i64> [#uses=1]*/
var231 = var60 <<< (64'd9 % 64);
/* %232 = icmp sgt i32 %229, 0 ; <i1> [#uses=1]*/
var232 = $signed(var229) > $signed(32'd0);
/* br label %bb.i5.i_1*/
cur_state = bb_i5_i_1;
end
bb_i5_i_1:
begin
/* %233 = and i64 %230, 2305843009213693440 ; <i64> [#uses=8]*/
var233 = var230 & 64'd2305843009213693440;
/* %234 = and i64 %231, 2305843009213693440 ; <i64> [#uses=8]*/
var234 = var231 & 64'd2305843009213693440;
/* br i1 %232, label %bb.i4.i.i, label %bb8.i25.i.i*/
if (var232) begin
cur_state = bb_i4_i_i;
end
else begin
cur_state = bb8_i25_i_i;
end
end
bb_i4_i_i:
begin
/* %235 = icmp eq i32 %225, 2047 ; <i1> [#uses=1]*/
var235 = var225 == 32'd2047;
/* br label %bb.i4.i.i_1*/
cur_state = bb_i4_i_i_1;
end
bb_i4_i_i_1:
begin
/* br i1 %235, label %bb1.i5.i.i, label %bb4.i23.i.i*/
if (var235) begin
cur_state = bb1_i5_i_i;
end
else begin
cur_state = bb4_i23_i_i;
end
end
bb1_i5_i_i:
begin
/* %236 = icmp eq i64 %233, 0 ; <i1> [#uses=1]*/
var236 = var233 == 64'd0;
/* br label %bb1.i5.i.i_1*/
cur_state = bb1_i5_i_i_1;
end
bb1_i5_i_i_1:
begin
/* br i1 %236, label %float64_add.exit.i, label %bb2.i6.i.i*/
if (var236) begin
var237 = app_0_i; /* for PHI node */
cur_state = float64_add_exit_i;
end
else begin
cur_state = bb2_i6_i_i;
end
end
bb2_i6_i_i:
begin
/* %237 = and i64 %app.0.i, 9221120237041090560 ; <i64> [#uses=1]*/
var238 = app_0_i & 64'd9221120237041090560;
/* br label %bb2.i6.i.i_1*/
cur_state = bb2_i6_i_i_1;
end
bb2_i6_i_i_1:
begin
/* %238 = icmp eq i64 %237, 9218868437227405312 ; <i1> [#uses=1]*/
var239 = var238 == 64'd9218868437227405312;
/* br label %bb2.i6.i.i_2*/
cur_state = bb2_i6_i_i_2;
end
bb2_i6_i_i_2:
begin
/* br i1 %238, label %bb.i14.i55.i9.i.i, label %float64_is_signaling_nan.exit16.i56.i10.i.i*/
if (var239) begin
cur_state = bb_i14_i55_i9_i_i;
end
else begin
var240 = 32'd0; /* for PHI node */
cur_state = float64_is_signaling_nan_exit16_i56_i10_i_i;
end
end
bb_i14_i55_i9_i_i:
begin
/* %239 = and i64 %app.0.i, 2251799813685247 ; <i64> [#uses=1]*/
var241 = app_0_i & 64'd2251799813685247;
/* br label %bb.i14.i55.i9.i.i_1*/
cur_state = bb_i14_i55_i9_i_i_1;
end
bb_i14_i55_i9_i_i_1:
begin
/* %not..i12.i53.i7.i.i = icmp ne i64 %239, 0 ; <i1> [#uses=1]*/
not__i12_i53_i7_i_i = var241 != 64'd0;
/* br label %bb.i14.i55.i9.i.i_2*/
cur_state = bb_i14_i55_i9_i_i_2;
end
bb_i14_i55_i9_i_i_2:
begin
/* %retval.i13.i54.i8.i.i = zext i1 %not..i12.i53.i7.i.i to i32 ; <i32> [#uses=1]*/
retval_i13_i54_i8_i_i = not__i12_i53_i7_i_i;
/* br label %float64_is_signaling_nan.exit16.i56.i10.i.i*/
var240 = retval_i13_i54_i8_i_i; /* for PHI node */
cur_state = float64_is_signaling_nan_exit16_i56_i10_i_i;
end
float64_is_signaling_nan_exit16_i56_i10_i_i:
begin
/* %240 = phi i32 [ %retval.i13.i54.i8.i.i, %bb.i14.i55.i9.i.i_2 ], [ 0, %bb2.i6.i.i_2 ] ; <i32> [#uses=2]*/
/* %241 = shl i64 %217, 1 ; <i64> [#uses=1]*/
var242 = var60 <<< (64'd1 % 64);
/* %242 = and i64 %217, 9221120237041090560 ; <i64> [#uses=1]*/
var243 = var60 & 64'd9221120237041090560;
/* br label %float64_is_signaling_nan.exit16.i56.i10.i.i_1*/
cur_state = float64_is_signaling_nan_exit16_i56_i10_i_i_1;
end
float64_is_signaling_nan_exit16_i56_i10_i_i_1:
begin
/* %243 = icmp ugt i64 %241, -9007199254740992 ; <i1> [#uses=1]*/
var244 = var242 > -64'd9007199254740992;
/* %244 = icmp eq i64 %242, 9218868437227405312 ; <i1> [#uses=1]*/
var245 = var243 == 64'd9218868437227405312;
/* br label %float64_is_signaling_nan.exit16.i56.i10.i.i_2*/
cur_state = float64_is_signaling_nan_exit16_i56_i10_i_i_2;
end
float64_is_signaling_nan_exit16_i56_i10_i_i_2:
begin
/* br i1 %244, label %bb.i.i59.i13.i.i, label %float64_is_signaling_nan.exit.i60.i14.i.i*/
if (var245) begin
cur_state = bb_i_i59_i13_i_i;
end
else begin
var246 = 32'd0; /* for PHI node */
cur_state = float64_is_signaling_nan_exit_i60_i14_i_i;
end
end
bb_i_i59_i13_i_i:
begin
/* %245 = and i64 %217, 2251799813685247 ; <i64> [#uses=1]*/
var247 = var60 & 64'd2251799813685247;
/* br label %bb.i.i59.i13.i.i_1*/
cur_state = bb_i_i59_i13_i_i_1;
end
bb_i_i59_i13_i_i_1:
begin
/* %not..i.i57.i11.i.i = icmp ne i64 %245, 0 ; <i1> [#uses=1]*/
not__i_i57_i11_i_i = var247 != 64'd0;
/* br label %bb.i.i59.i13.i.i_2*/
cur_state = bb_i_i59_i13_i_i_2;
end
bb_i_i59_i13_i_i_2:
begin
/* %retval.i.i58.i12.i.i = zext i1 %not..i.i57.i11.i.i to i32 ; <i32> [#uses=1]*/
retval_i_i58_i12_i_i = not__i_i57_i11_i_i;
/* br label %float64_is_signaling_nan.exit.i60.i14.i.i*/
var246 = retval_i_i58_i12_i_i; /* for PHI node */
cur_state = float64_is_signaling_nan_exit_i60_i14_i_i;
end
float64_is_signaling_nan_exit_i60_i14_i_i:
begin
/* %246 = phi i32 [ %retval.i.i58.i12.i.i, %bb.i.i59.i13.i.i_2 ], [ 0, %float64_is_signaling_nan.exit16.i56.i10.i.i_2 ] ; <i32> [#uses=2]*/
/* %247 = or i64 %app.0.i, 2251799813685248 ; <i64> [#uses=2]*/
var248 = app_0_i | 64'd2251799813685248;
/* %248 = or i64 %217, 2251799813685248 ; <i64> [#uses=2]*/
var249 = var60 | 64'd2251799813685248;
/* br label %float64_is_signaling_nan.exit.i60.i14.i.i_1*/
cur_state = float64_is_signaling_nan_exit_i60_i14_i_i_1;
end
float64_is_signaling_nan_exit_i60_i14_i_i_1:
begin
/* %249 = or i32 %246, %240 ; <i32> [#uses=1]*/
var250 = var246 | var240;
/* br label %float64_is_signaling_nan.exit.i60.i14.i.i_2*/
cur_state = float64_is_signaling_nan_exit_i60_i14_i_i_2;
end
float64_is_signaling_nan_exit_i60_i14_i_i_2:
begin
/* %250 = icmp eq i32 %249, 0 ; <i1> [#uses=1]*/
var251 = var250 == 32'd0;
/* br label %float64_is_signaling_nan.exit.i60.i14.i.i_3*/
cur_state = float64_is_signaling_nan_exit_i60_i14_i_i_3;
end
float64_is_signaling_nan_exit_i60_i14_i_i_3:
begin
/* br i1 %250, label %bb1.i62.i16.i.i, label %bb.i61.i15.i.i*/
if (var251) begin
cur_state = bb1_i62_i16_i_i;
end
else begin
cur_state = bb_i61_i15_i_i;
end
end
bb_i61_i15_i_i:
begin
/* %251 = load i32* @float_exception_flags, align 4 ; <i32> [#uses=1]*/
/* br label %bb.i61.i15.i.i_1*/
cur_state = bb_i61_i15_i_i_1;
end
bb_i61_i15_i_i_1:
begin
var252 = memory_controller_out[31:0];
/* %load_noop9 = add i32 %251, 0 ; <i32> [#uses=1]*/
load_noop9 = var252 + 32'd0;
/* br label %bb.i61.i15.i.i_2*/
cur_state = bb_i61_i15_i_i_2;
end
bb_i61_i15_i_i_2:
begin
/* %252 = or i32 %load_noop9, 16 ; <i32> [#uses=1]*/
var253 = load_noop9 | 32'd16;
/* br label %bb.i61.i15.i.i_3*/
cur_state = bb_i61_i15_i_i_3;
end
bb_i61_i15_i_i_3:
begin
/* store i32 %252, i32* @float_exception_flags, align 4*/
/* br label %bb1.i62.i16.i.i*/
cur_state = bb1_i62_i16_i_i;
end
bb1_i62_i16_i_i:
begin
/* %253 = icmp eq i32 %246, 0 ; <i1> [#uses=1]*/
var254 = var246 == 32'd0;
/* br label %bb1.i62.i16.i.i_1*/
cur_state = bb1_i62_i16_i_i_1;
end
bb1_i62_i16_i_i_1:
begin
/* br i1 %253, label %bb2.i63.i17.i.i, label %float64_add.exit.i*/
if (var254) begin
cur_state = bb2_i63_i17_i_i;
end
else begin
var237 = var249; /* for PHI node */
cur_state = float64_add_exit_i;
end
end
bb2_i63_i17_i_i:
begin
/* %254 = icmp eq i32 %240, 0 ; <i1> [#uses=1]*/
var255 = var240 == 32'd0;
/* br label %bb2.i63.i17.i.i_1*/
cur_state = bb2_i63_i17_i_i_1;
end
bb2_i63_i17_i_i_1:
begin
/* br i1 %254, label %bb3.i65.i19.i.i, label %float64_add.exit.i*/
if (var255) begin
cur_state = bb3_i65_i19_i_i;
end
else begin
var237 = var248; /* for PHI node */
cur_state = float64_add_exit_i;
end
end
bb3_i65_i19_i_i:
begin
/* %iftmp.34.0.i64.i18.i.i = select i1 %243, i64 %248, i64 %247 ; <i64> [#uses=1]*/
iftmp_34_0_i64_i18_i_i = (var244) ? var249 : var248;
/* br label %float64_add.exit.i*/
var237 = iftmp_34_0_i64_i18_i_i; /* for PHI node */
cur_state = float64_add_exit_i;
end
bb4_i23_i_i:
begin
/* %255 = icmp eq i32 %228, 0 ; <i1> [#uses=2]*/
var256 = var228 == 32'd0;
/* %256 = add i32 %229, -1 ; <i32> [#uses=1]*/
var257 = var229 + -32'd1;
/* %257 = or i64 %234, 2305843009213693952 ; <i64> [#uses=1]*/
var258 = var234 | 64'd2305843009213693952;
/* br label %bb4.i23.i.i_1*/
cur_state = bb4_i23_i_i_1;
end
bb4_i23_i_i_1:
begin
/* %bSig.0.i21.i.i = select i1 %255, i64 %234, i64 %257 ; <i64> [#uses=4]*/
bSig_0_i21_i_i = (var256) ? var234 : var258;
/* %expDiff.0.i22.i.i = select i1 %255, i32 %256, i32 %229 ; <i32> [#uses=4]*/
expDiff_0_i22_i_i = (var256) ? var257 : var229;
/* br label %bb4.i23.i.i_2*/
cur_state = bb4_i23_i_i_2;
end
bb4_i23_i_i_2:
begin
/* %258 = icmp eq i32 %expDiff.0.i22.i.i, 0 ; <i1> [#uses=1]*/
var259 = expDiff_0_i22_i_i == 32'd0;
/* br label %bb4.i23.i.i_3*/
cur_state = bb4_i23_i_i_3;
end
bb4_i23_i_i_3:
begin
/* br i1 %258, label %bb24.i57.i.i, label %bb1.i46.i24.i.i*/
if (var259) begin
aSig_1_i54_i_i = var233; /* for PHI node */
bSig_1_i55_i_i = bSig_0_i21_i_i; /* for PHI node */
zExp_0_i56_i_i = var225; /* for PHI node */
cur_state = bb24_i57_i_i;
end
else begin
cur_state = bb1_i46_i24_i_i;
end
end
bb1_i46_i24_i_i:
begin
/* %259 = icmp slt i32 %expDiff.0.i22.i.i, 64 ; <i1> [#uses=1]*/
var260 = $signed(expDiff_0_i22_i_i) < $signed(32'd64);
/* br label %bb1.i46.i24.i.i_1*/
cur_state = bb1_i46_i24_i_i_1;
end
bb1_i46_i24_i_i_1:
begin
/* br i1 %259, label %bb2.i49.i.i.i, label %bb4.i50.i.i.i*/
if (var260) begin
cur_state = bb2_i49_i_i_i;
end
else begin
cur_state = bb4_i50_i_i_i;
end
end
bb2_i49_i_i_i:
begin
/* %.cast.i47.i.i.i = zext i32 %expDiff.0.i22.i.i to i64 ; <i64> [#uses=1]*/
_cast_i47_i_i_i = expDiff_0_i22_i_i;
/* %260 = sub i32 0, %expDiff.0.i22.i.i ; <i32> [#uses=1]*/
var261 = 32'd0 - expDiff_0_i22_i_i;
/* br label %bb2.i49.i.i.i_1*/
cur_state = bb2_i49_i_i_i_1;
end
bb2_i49_i_i_i_1:
begin
/* %261 = lshr i64 %bSig.0.i21.i.i, %.cast.i47.i.i.i ; <i64> [#uses=1]*/
var262 = bSig_0_i21_i_i >>> (_cast_i47_i_i_i % 64);
/* %262 = and i32 %260, 63 ; <i32> [#uses=1]*/
var263 = var261 & 32'd63;
/* br label %bb2.i49.i.i.i_2*/
cur_state = bb2_i49_i_i_i_2;
end
bb2_i49_i_i_i_2:
begin
/* %.cast3.i48.i.i.i = zext i32 %262 to i64 ; <i64> [#uses=1]*/
_cast3_i48_i_i_i = var263;
/* br label %bb2.i49.i.i.i_3*/
cur_state = bb2_i49_i_i_i_3;
end
bb2_i49_i_i_i_3:
begin
/* %263 = shl i64 %bSig.0.i21.i.i, %.cast3.i48.i.i.i ; <i64> [#uses=1]*/
var264 = bSig_0_i21_i_i <<< (_cast3_i48_i_i_i % 64);
/* br label %bb2.i49.i.i.i_4*/
cur_state = bb2_i49_i_i_i_4;
end
bb2_i49_i_i_i_4:
begin
/* %264 = icmp ne i64 %263, 0 ; <i1> [#uses=1]*/
var265 = var264 != 64'd0;
/* br label %bb2.i49.i.i.i_5*/
cur_state = bb2_i49_i_i_i_5;
end
bb2_i49_i_i_i_5:
begin
/* %265 = zext i1 %264 to i64 ; <i64> [#uses=1]*/
var266 = var265;
/* br label %bb2.i49.i.i.i_6*/
cur_state = bb2_i49_i_i_i_6;
end
bb2_i49_i_i_i_6:
begin
/* %266 = or i64 %265, %261 ; <i64> [#uses=1]*/
var267 = var266 | var262;
/* br label %bb24.i57.i.i*/
aSig_1_i54_i_i = var233; /* for PHI node */
bSig_1_i55_i_i = var267; /* for PHI node */
zExp_0_i56_i_i = var225; /* for PHI node */
cur_state = bb24_i57_i_i;
end
bb4_i50_i_i_i:
begin
/* %267 = icmp ne i64 %bSig.0.i21.i.i, 0 ; <i1> [#uses=1]*/
var268 = bSig_0_i21_i_i != 64'd0;
/* br label %bb4.i50.i.i.i_1*/
cur_state = bb4_i50_i_i_i_1;
end
bb4_i50_i_i_i_1:
begin
/* %268 = zext i1 %267 to i64 ; <i64> [#uses=1]*/
var269 = var268;
/* br label %bb24.i57.i.i*/
aSig_1_i54_i_i = var233; /* for PHI node */
bSig_1_i55_i_i = var269; /* for PHI node */
zExp_0_i56_i_i = var225; /* for PHI node */
cur_state = bb24_i57_i_i;
end
bb8_i25_i_i:
begin
/* %269 = icmp slt i32 %229, 0 ; <i1> [#uses=1]*/
var270 = $signed(var229) < $signed(32'd0);
/* br label %bb8.i25.i.i_1*/
cur_state = bb8_i25_i_i_1;
end
bb8_i25_i_i_1:
begin
/* br i1 %269, label %bb9.i26.i.i, label %bb17.i38.i.i*/
if (var270) begin
cur_state = bb9_i26_i_i;
end
else begin
cur_state = bb17_i38_i_i;
end
end
bb9_i26_i_i:
begin
/* %270 = icmp eq i32 %228, 2047 ; <i1> [#uses=1]*/
var271 = var228 == 32'd2047;
/* br label %bb9.i26.i.i_1*/
cur_state = bb9_i26_i_i_1;
end
bb9_i26_i_i_1:
begin
/* br i1 %270, label %bb10.i27.i.i, label %bb13.i32.i.i*/
if (var271) begin
cur_state = bb10_i27_i_i;
end
else begin
cur_state = bb13_i32_i_i;
end
end
bb10_i27_i_i:
begin
/* %271 = icmp eq i64 %234, 0 ; <i1> [#uses=1]*/
var272 = var234 == 64'd0;
/* br label %bb10.i27.i.i_1*/
cur_state = bb10_i27_i_i_1;
end
bb10_i27_i_i_1:
begin
/* br i1 %271, label %bb12.i29.i.i, label %bb11.i28.i.i*/
if (var272) begin
cur_state = bb12_i29_i_i;
end
else begin
cur_state = bb11_i28_i_i;
end
end
bb11_i28_i_i:
begin
/* %272 = and i64 %app.0.i, 9221120237041090560 ; <i64> [#uses=1]*/
var273 = app_0_i & 64'd9221120237041090560;
/* br label %bb11.i28.i.i_1*/
cur_state = bb11_i28_i_i_1;
end
bb11_i28_i_i_1:
begin
/* %273 = icmp eq i64 %272, 9218868437227405312 ; <i1> [#uses=1]*/
var274 = var273 == 64'd9218868437227405312;
/* br label %bb11.i28.i.i_2*/
cur_state = bb11_i28_i_i_2;
end
bb11_i28_i_i_2:
begin
/* br i1 %273, label %bb.i14.i32.i.i.i, label %float64_is_signaling_nan.exit16.i33.i.i.i*/
if (var274) begin
cur_state = bb_i14_i32_i_i_i;
end
else begin
var275 = 32'd0; /* for PHI node */
cur_state = float64_is_signaling_nan_exit16_i33_i_i_i;
end
end
bb_i14_i32_i_i_i:
begin
/* %274 = and i64 %app.0.i, 2251799813685247 ; <i64> [#uses=1]*/
var276 = app_0_i & 64'd2251799813685247;
/* br label %bb.i14.i32.i.i.i_1*/
cur_state = bb_i14_i32_i_i_i_1;
end
bb_i14_i32_i_i_i_1:
begin
/* %not..i12.i30.i.i.i = icmp ne i64 %274, 0 ; <i1> [#uses=1]*/
not__i12_i30_i_i_i = var276 != 64'd0;
/* br label %bb.i14.i32.i.i.i_2*/
cur_state = bb_i14_i32_i_i_i_2;
end
bb_i14_i32_i_i_i_2:
begin
/* %retval.i13.i31.i.i.i = zext i1 %not..i12.i30.i.i.i to i32 ; <i32> [#uses=1]*/
retval_i13_i31_i_i_i = not__i12_i30_i_i_i;
/* br label %float64_is_signaling_nan.exit16.i33.i.i.i*/
var275 = retval_i13_i31_i_i_i; /* for PHI node */
cur_state = float64_is_signaling_nan_exit16_i33_i_i_i;
end
float64_is_signaling_nan_exit16_i33_i_i_i:
begin
/* %275 = phi i32 [ %retval.i13.i31.i.i.i, %bb.i14.i32.i.i.i_2 ], [ 0, %bb11.i28.i.i_2 ] ; <i32> [#uses=2]*/
/* %276 = shl i64 %217, 1 ; <i64> [#uses=1]*/
var277 = var60 <<< (64'd1 % 64);
/* %277 = and i64 %217, 9221120237041090560 ; <i64> [#uses=1]*/
var278 = var60 & 64'd9221120237041090560;
/* br label %float64_is_signaling_nan.exit16.i33.i.i.i_1*/
cur_state = float64_is_signaling_nan_exit16_i33_i_i_i_1;
end
float64_is_signaling_nan_exit16_i33_i_i_i_1:
begin
/* %278 = icmp ugt i64 %276, -9007199254740992 ; <i1> [#uses=1]*/
var279 = var277 > -64'd9007199254740992;
/* %279 = icmp eq i64 %277, 9218868437227405312 ; <i1> [#uses=1]*/
var280 = var278 == 64'd9218868437227405312;
/* br label %float64_is_signaling_nan.exit16.i33.i.i.i_2*/
cur_state = float64_is_signaling_nan_exit16_i33_i_i_i_2;
end
float64_is_signaling_nan_exit16_i33_i_i_i_2:
begin
/* br i1 %279, label %bb.i.i36.i.i.i, label %float64_is_signaling_nan.exit.i37.i.i.i*/
if (var280) begin
cur_state = bb_i_i36_i_i_i;
end
else begin
var281 = 32'd0; /* for PHI node */
cur_state = float64_is_signaling_nan_exit_i37_i_i_i;
end
end
bb_i_i36_i_i_i:
begin
/* %280 = and i64 %217, 2251799813685247 ; <i64> [#uses=1]*/
var282 = var60 & 64'd2251799813685247;
/* br label %bb.i.i36.i.i.i_1*/
cur_state = bb_i_i36_i_i_i_1;
end
bb_i_i36_i_i_i_1:
begin
/* %not..i.i34.i.i.i = icmp ne i64 %280, 0 ; <i1> [#uses=1]*/
not__i_i34_i_i_i = var282 != 64'd0;
/* br label %bb.i.i36.i.i.i_2*/
cur_state = bb_i_i36_i_i_i_2;
end
bb_i_i36_i_i_i_2:
begin
/* %retval.i.i35.i.i.i = zext i1 %not..i.i34.i.i.i to i32 ; <i32> [#uses=1]*/
retval_i_i35_i_i_i = not__i_i34_i_i_i;
/* br label %float64_is_signaling_nan.exit.i37.i.i.i*/
var281 = retval_i_i35_i_i_i; /* for PHI node */
cur_state = float64_is_signaling_nan_exit_i37_i_i_i;
end
float64_is_signaling_nan_exit_i37_i_i_i:
begin
/* %281 = phi i32 [ %retval.i.i35.i.i.i, %bb.i.i36.i.i.i_2 ], [ 0, %float64_is_signaling_nan.exit16.i33.i.i.i_2 ] ; <i32> [#uses=2]*/
/* %282 = or i64 %app.0.i, 2251799813685248 ; <i64> [#uses=2]*/
var283 = app_0_i | 64'd2251799813685248;
/* %283 = or i64 %217, 2251799813685248 ; <i64> [#uses=2]*/
var284 = var60 | 64'd2251799813685248;
/* br label %float64_is_signaling_nan.exit.i37.i.i.i_1*/
cur_state = float64_is_signaling_nan_exit_i37_i_i_i_1;
end
float64_is_signaling_nan_exit_i37_i_i_i_1:
begin
/* %284 = or i32 %281, %275 ; <i32> [#uses=1]*/
var285 = var281 | var275;
/* br label %float64_is_signaling_nan.exit.i37.i.i.i_2*/
cur_state = float64_is_signaling_nan_exit_i37_i_i_i_2;
end
float64_is_signaling_nan_exit_i37_i_i_i_2:
begin
/* %285 = icmp eq i32 %284, 0 ; <i1> [#uses=1]*/
var286 = var285 == 32'd0;
/* br label %float64_is_signaling_nan.exit.i37.i.i.i_3*/
cur_state = float64_is_signaling_nan_exit_i37_i_i_i_3;
end
float64_is_signaling_nan_exit_i37_i_i_i_3:
begin
/* br i1 %285, label %bb1.i39.i.i.i, label %bb.i38.i.i.i*/
if (var286) begin
cur_state = bb1_i39_i_i_i;
end
else begin
cur_state = bb_i38_i_i_i;
end
end
bb_i38_i_i_i:
begin
/* %286 = load i32* @float_exception_flags, align 4 ; <i32> [#uses=1]*/
/* br label %bb.i38.i.i.i_1*/
cur_state = bb_i38_i_i_i_1;
end
bb_i38_i_i_i_1:
begin
var287 = memory_controller_out[31:0];
/* %load_noop10 = add i32 %286, 0 ; <i32> [#uses=1]*/
load_noop10 = var287 + 32'd0;
/* br label %bb.i38.i.i.i_2*/
cur_state = bb_i38_i_i_i_2;
end
bb_i38_i_i_i_2:
begin
/* %287 = or i32 %load_noop10, 16 ; <i32> [#uses=1]*/
var288 = load_noop10 | 32'd16;
/* br label %bb.i38.i.i.i_3*/
cur_state = bb_i38_i_i_i_3;
end
bb_i38_i_i_i_3:
begin
/* store i32 %287, i32* @float_exception_flags, align 4*/
/* br label %bb1.i39.i.i.i*/
cur_state = bb1_i39_i_i_i;
end
bb1_i39_i_i_i:
begin
/* %288 = icmp eq i32 %281, 0 ; <i1> [#uses=1]*/
var289 = var281 == 32'd0;
/* br label %bb1.i39.i.i.i_1*/
cur_state = bb1_i39_i_i_i_1;
end
bb1_i39_i_i_i_1:
begin
/* br i1 %288, label %bb2.i40.i.i.i, label %float64_add.exit.i*/
if (var289) begin
cur_state = bb2_i40_i_i_i;
end
else begin
var237 = var284; /* for PHI node */
cur_state = float64_add_exit_i;
end
end
bb2_i40_i_i_i:
begin
/* %289 = icmp eq i32 %275, 0 ; <i1> [#uses=1]*/
var290 = var275 == 32'd0;
/* br label %bb2.i40.i.i.i_1*/
cur_state = bb2_i40_i_i_i_1;
end
bb2_i40_i_i_i_1:
begin
/* br i1 %289, label %bb3.i42.i.i.i, label %float64_add.exit.i*/
if (var290) begin
cur_state = bb3_i42_i_i_i;
end
else begin
var237 = var283; /* for PHI node */
cur_state = float64_add_exit_i;
end
end
bb3_i42_i_i_i:
begin
/* %iftmp.34.0.i41.i.i.i = select i1 %278, i64 %283, i64 %282 ; <i64> [#uses=1]*/
iftmp_34_0_i41_i_i_i = (var279) ? var284 : var283;
/* br label %float64_add.exit.i*/
var237 = iftmp_34_0_i41_i_i_i; /* for PHI node */
cur_state = float64_add_exit_i;
end
bb12_i29_i_i:
begin
/* %290 = or i64 %app.0.i, 9218868437227405312 ; <i64> [#uses=1]*/
var291 = app_0_i | 64'd9218868437227405312;
/* br label %bb12.i29.i.i_1*/
cur_state = bb12_i29_i_i_1;
end
bb12_i29_i_i_1:
begin
/* %291 = and i64 %290, -4503599627370496 ; <i64> [#uses=1]*/
var292 = var291 & -64'd4503599627370496;
/* br label %float64_add.exit.i*/
var237 = var292; /* for PHI node */
cur_state = float64_add_exit_i;
end
bb13_i32_i_i:
begin
/* %292 = icmp eq i32 %225, 0 ; <i1> [#uses=2]*/
var293 = var225 == 32'd0;
/* %293 = or i64 %233, 2305843009213693952 ; <i64> [#uses=1]*/
var294 = var233 | 64'd2305843009213693952;
/* br label %bb13.i32.i.i_1*/
cur_state = bb13_i32_i_i_1;
end
bb13_i32_i_i_1:
begin
/* %aSig.0.i30.i.i = select i1 %292, i64 %233, i64 %293 ; <i64> [#uses=4]*/
aSig_0_i30_i_i = (var293) ? var233 : var294;
/* %294 = zext i1 %292 to i32 ; <i32> [#uses=1]*/
var295 = var293;
/* br label %bb13.i32.i.i_2*/
cur_state = bb13_i32_i_i_2;
end
bb13_i32_i_i_2:
begin
/* %expDiff.1.i31.i.i = add i32 %229, %294 ; <i32> [#uses=3]*/
expDiff_1_i31_i_i = var229 + var295;
/* br label %bb13.i32.i.i_3*/
cur_state = bb13_i32_i_i_3;
end
bb13_i32_i_i_3:
begin
/* %295 = sub i32 0, %expDiff.1.i31.i.i ; <i32> [#uses=2]*/
var296 = 32'd0 - expDiff_1_i31_i_i;
/* %296 = icmp eq i32 %expDiff.1.i31.i.i, 0 ; <i1> [#uses=1]*/
var297 = expDiff_1_i31_i_i == 32'd0;
/* br label %bb13.i32.i.i_4*/
cur_state = bb13_i32_i_i_4;
end
bb13_i32_i_i_4:
begin
/* br i1 %296, label %bb24.i57.i.i, label %bb1.i28.i33.i.i*/
if (var297) begin
aSig_1_i54_i_i = aSig_0_i30_i_i; /* for PHI node */
bSig_1_i55_i_i = var234; /* for PHI node */
zExp_0_i56_i_i = var228; /* for PHI node */
cur_state = bb24_i57_i_i;
end
else begin
cur_state = bb1_i28_i33_i_i;
end
end
bb1_i28_i33_i_i:
begin
/* %297 = icmp slt i32 %295, 64 ; <i1> [#uses=1]*/
var298 = $signed(var296) < $signed(32'd64);
/* br label %bb1.i28.i33.i.i_1*/
cur_state = bb1_i28_i33_i_i_1;
end
bb1_i28_i33_i_i_1:
begin
/* br i1 %297, label %bb2.i29.i36.i.i, label %bb4.i.i37.i.i*/
if (var298) begin
cur_state = bb2_i29_i36_i_i;
end
else begin
cur_state = bb4_i_i37_i_i;
end
end
bb2_i29_i36_i_i:
begin
/* %.cast.i.i34.i.i = zext i32 %295 to i64 ; <i64> [#uses=1]*/
_cast_i_i34_i_i = var296;
/* %298 = and i32 %expDiff.1.i31.i.i, 63 ; <i32> [#uses=1]*/
var299 = expDiff_1_i31_i_i & 32'd63;
/* br label %bb2.i29.i36.i.i_1*/
cur_state = bb2_i29_i36_i_i_1;
end
bb2_i29_i36_i_i_1:
begin
/* %299 = lshr i64 %aSig.0.i30.i.i, %.cast.i.i34.i.i ; <i64> [#uses=1]*/
var300 = aSig_0_i30_i_i >>> (_cast_i_i34_i_i % 64);
/* %.cast3.i.i35.i.i = zext i32 %298 to i64 ; <i64> [#uses=1]*/
_cast3_i_i35_i_i = var299;
/* br label %bb2.i29.i36.i.i_2*/
cur_state = bb2_i29_i36_i_i_2;
end
bb2_i29_i36_i_i_2:
begin
/* %300 = shl i64 %aSig.0.i30.i.i, %.cast3.i.i35.i.i ; <i64> [#uses=1]*/
var301 = aSig_0_i30_i_i <<< (_cast3_i_i35_i_i % 64);
/* br label %bb2.i29.i36.i.i_3*/
cur_state = bb2_i29_i36_i_i_3;
end
bb2_i29_i36_i_i_3:
begin
/* %301 = icmp ne i64 %300, 0 ; <i1> [#uses=1]*/
var302 = var301 != 64'd0;
/* br label %bb2.i29.i36.i.i_4*/
cur_state = bb2_i29_i36_i_i_4;
end
bb2_i29_i36_i_i_4:
begin
/* %302 = zext i1 %301 to i64 ; <i64> [#uses=1]*/
var303 = var302;
/* br label %bb2.i29.i36.i.i_5*/
cur_state = bb2_i29_i36_i_i_5;
end
bb2_i29_i36_i_i_5:
begin
/* %303 = or i64 %302, %299 ; <i64> [#uses=1]*/
var304 = var303 | var300;
/* br label %bb24.i57.i.i*/
aSig_1_i54_i_i = var304; /* for PHI node */
bSig_1_i55_i_i = var234; /* for PHI node */
zExp_0_i56_i_i = var228; /* for PHI node */
cur_state = bb24_i57_i_i;
end
bb4_i_i37_i_i:
begin
/* %304 = icmp ne i64 %aSig.0.i30.i.i, 0 ; <i1> [#uses=1]*/
var305 = aSig_0_i30_i_i != 64'd0;
/* br label %bb4.i.i37.i.i_1*/
cur_state = bb4_i_i37_i_i_1;
end
bb4_i_i37_i_i_1:
begin
/* %305 = zext i1 %304 to i64 ; <i64> [#uses=1]*/
var306 = var305;
/* br label %bb24.i57.i.i*/
aSig_1_i54_i_i = var306; /* for PHI node */
bSig_1_i55_i_i = var234; /* for PHI node */
zExp_0_i56_i_i = var228; /* for PHI node */
cur_state = bb24_i57_i_i;
end
bb17_i38_i_i:
begin
/* %306 = icmp eq i32 %225, 2047 ; <i1> [#uses=1]*/
var307 = var225 == 32'd2047;
/* br label %bb17.i38.i.i_1*/
cur_state = bb17_i38_i_i_1;
end
bb17_i38_i_i_1:
begin
/* br i1 %306, label %bb18.i39.i.i, label %bb21.i.i.i*/
if (var307) begin
cur_state = bb18_i39_i_i;
end
else begin
cur_state = bb21_i_i_i;
end
end
bb18_i39_i_i:
begin
/* %307 = or i64 %234, %233 ; <i64> [#uses=1]*/
var308 = var234 | var233;
/* br label %bb18.i39.i.i_1*/
cur_state = bb18_i39_i_i_1;
end
bb18_i39_i_i_1:
begin
/* %308 = icmp eq i64 %307, 0 ; <i1> [#uses=1]*/
var309 = var308 == 64'd0;
/* br label %bb18.i39.i.i_2*/
cur_state = bb18_i39_i_i_2;
end
bb18_i39_i_i_2:
begin
/* br i1 %308, label %float64_add.exit.i, label %bb19.i.i.i*/
if (var309) begin
var237 = app_0_i; /* for PHI node */
cur_state = float64_add_exit_i;
end
else begin
cur_state = bb19_i_i_i;
end
end
bb19_i_i_i:
begin
/* %309 = and i64 %app.0.i, 9221120237041090560 ; <i64> [#uses=1]*/
var310 = app_0_i & 64'd9221120237041090560;
/* br label %bb19.i.i.i_1*/
cur_state = bb19_i_i_i_1;
end
bb19_i_i_i_1:
begin
/* %310 = icmp eq i64 %309, 9218868437227405312 ; <i1> [#uses=1]*/
var311 = var310 == 64'd9218868437227405312;
/* br label %bb19.i.i.i_2*/
cur_state = bb19_i_i_i_2;
end
bb19_i_i_i_2:
begin
/* br i1 %310, label %bb.i14.i.i42.i.i, label %float64_is_signaling_nan.exit16.i.i43.i.i*/
if (var311) begin
cur_state = bb_i14_i_i42_i_i;
end
else begin
var312 = 32'd0; /* for PHI node */
cur_state = float64_is_signaling_nan_exit16_i_i43_i_i;
end
end
bb_i14_i_i42_i_i:
begin
/* %311 = and i64 %app.0.i, 2251799813685247 ; <i64> [#uses=1]*/
var313 = app_0_i & 64'd2251799813685247;
/* br label %bb.i14.i.i42.i.i_1*/
cur_state = bb_i14_i_i42_i_i_1;
end
bb_i14_i_i42_i_i_1:
begin
/* %not..i12.i.i40.i.i = icmp ne i64 %311, 0 ; <i1> [#uses=1]*/
not__i12_i_i40_i_i = var313 != 64'd0;
/* br label %bb.i14.i.i42.i.i_2*/
cur_state = bb_i14_i_i42_i_i_2;
end
bb_i14_i_i42_i_i_2:
begin
/* %retval.i13.i.i41.i.i = zext i1 %not..i12.i.i40.i.i to i32 ; <i32> [#uses=1]*/
retval_i13_i_i41_i_i = not__i12_i_i40_i_i;
/* br label %float64_is_signaling_nan.exit16.i.i43.i.i*/
var312 = retval_i13_i_i41_i_i; /* for PHI node */
cur_state = float64_is_signaling_nan_exit16_i_i43_i_i;
end
float64_is_signaling_nan_exit16_i_i43_i_i:
begin
/* %312 = phi i32 [ %retval.i13.i.i41.i.i, %bb.i14.i.i42.i.i_2 ], [ 0, %bb19.i.i.i_2 ] ; <i32> [#uses=2]*/
/* %313 = shl i64 %217, 1 ; <i64> [#uses=1]*/
var314 = var60 <<< (64'd1 % 64);
/* %314 = and i64 %217, 9221120237041090560 ; <i64> [#uses=1]*/
var315 = var60 & 64'd9221120237041090560;
/* br label %float64_is_signaling_nan.exit16.i.i43.i.i_1*/
cur_state = float64_is_signaling_nan_exit16_i_i43_i_i_1;
end
float64_is_signaling_nan_exit16_i_i43_i_i_1:
begin
/* %315 = icmp ugt i64 %313, -9007199254740992 ; <i1> [#uses=1]*/
var316 = var314 > -64'd9007199254740992;
/* %316 = icmp eq i64 %314, 9218868437227405312 ; <i1> [#uses=1]*/
var317 = var315 == 64'd9218868437227405312;
/* br label %float64_is_signaling_nan.exit16.i.i43.i.i_2*/
cur_state = float64_is_signaling_nan_exit16_i_i43_i_i_2;
end
float64_is_signaling_nan_exit16_i_i43_i_i_2:
begin
/* br i1 %316, label %bb.i.i.i46.i.i, label %float64_is_signaling_nan.exit.i.i47.i.i*/
if (var317) begin
cur_state = bb_i_i_i46_i_i;
end
else begin
var318 = 32'd0; /* for PHI node */
cur_state = float64_is_signaling_nan_exit_i_i47_i_i;
end
end
bb_i_i_i46_i_i:
begin
/* %317 = and i64 %217, 2251799813685247 ; <i64> [#uses=1]*/
var319 = var60 & 64'd2251799813685247;
/* br label %bb.i.i.i46.i.i_1*/
cur_state = bb_i_i_i46_i_i_1;
end
bb_i_i_i46_i_i_1:
begin
/* %not..i.i.i44.i.i = icmp ne i64 %317, 0 ; <i1> [#uses=1]*/
not__i_i_i44_i_i = var319 != 64'd0;
/* br label %bb.i.i.i46.i.i_2*/
cur_state = bb_i_i_i46_i_i_2;
end
bb_i_i_i46_i_i_2:
begin
/* %retval.i.i.i45.i.i = zext i1 %not..i.i.i44.i.i to i32 ; <i32> [#uses=1]*/
retval_i_i_i45_i_i = not__i_i_i44_i_i;
/* br label %float64_is_signaling_nan.exit.i.i47.i.i*/
var318 = retval_i_i_i45_i_i; /* for PHI node */
cur_state = float64_is_signaling_nan_exit_i_i47_i_i;
end
float64_is_signaling_nan_exit_i_i47_i_i:
begin
/* %318 = phi i32 [ %retval.i.i.i45.i.i, %bb.i.i.i46.i.i_2 ], [ 0, %float64_is_signaling_nan.exit16.i.i43.i.i_2 ] ; <i32> [#uses=2]*/
/* %319 = or i64 %app.0.i, 2251799813685248 ; <i64> [#uses=2]*/
var320 = app_0_i | 64'd2251799813685248;
/* %320 = or i64 %217, 2251799813685248 ; <i64> [#uses=2]*/
var321 = var60 | 64'd2251799813685248;
/* br label %float64_is_signaling_nan.exit.i.i47.i.i_1*/
cur_state = float64_is_signaling_nan_exit_i_i47_i_i_1;
end
float64_is_signaling_nan_exit_i_i47_i_i_1:
begin
/* %321 = or i32 %318, %312 ; <i32> [#uses=1]*/
var322 = var318 | var312;
/* br label %float64_is_signaling_nan.exit.i.i47.i.i_2*/
cur_state = float64_is_signaling_nan_exit_i_i47_i_i_2;
end
float64_is_signaling_nan_exit_i_i47_i_i_2:
begin
/* %322 = icmp eq i32 %321, 0 ; <i1> [#uses=1]*/
var323 = var322 == 32'd0;
/* br label %float64_is_signaling_nan.exit.i.i47.i.i_3*/
cur_state = float64_is_signaling_nan_exit_i_i47_i_i_3;
end
float64_is_signaling_nan_exit_i_i47_i_i_3:
begin
/* br i1 %322, label %bb1.i.i49.i.i, label %bb.i.i48.i.i*/
if (var323) begin
cur_state = bb1_i_i49_i_i;
end
else begin
cur_state = bb_i_i48_i_i;
end
end
bb_i_i48_i_i:
begin
/* %323 = load i32* @float_exception_flags, align 4 ; <i32> [#uses=1]*/
/* br label %bb.i.i48.i.i_1*/
cur_state = bb_i_i48_i_i_1;
end
bb_i_i48_i_i_1:
begin
var324 = memory_controller_out[31:0];
/* %load_noop11 = add i32 %323, 0 ; <i32> [#uses=1]*/
load_noop11 = var324 + 32'd0;
/* br label %bb.i.i48.i.i_2*/
cur_state = bb_i_i48_i_i_2;
end
bb_i_i48_i_i_2:
begin
/* %324 = or i32 %load_noop11, 16 ; <i32> [#uses=1]*/
var325 = load_noop11 | 32'd16;
/* br label %bb.i.i48.i.i_3*/
cur_state = bb_i_i48_i_i_3;
end
bb_i_i48_i_i_3:
begin
/* store i32 %324, i32* @float_exception_flags, align 4*/
/* br label %bb1.i.i49.i.i*/
cur_state = bb1_i_i49_i_i;
end
bb1_i_i49_i_i:
begin
/* %325 = icmp eq i32 %318, 0 ; <i1> [#uses=1]*/
var326 = var318 == 32'd0;
/* br label %bb1.i.i49.i.i_1*/
cur_state = bb1_i_i49_i_i_1;
end
bb1_i_i49_i_i_1:
begin
/* br i1 %325, label %bb2.i.i50.i.i, label %float64_add.exit.i*/
if (var326) begin
cur_state = bb2_i_i50_i_i;
end
else begin
var237 = var321; /* for PHI node */
cur_state = float64_add_exit_i;
end
end
bb2_i_i50_i_i:
begin
/* %326 = icmp eq i32 %312, 0 ; <i1> [#uses=1]*/
var327 = var312 == 32'd0;
/* br label %bb2.i.i50.i.i_1*/
cur_state = bb2_i_i50_i_i_1;
end
bb2_i_i50_i_i_1:
begin
/* br i1 %326, label %bb3.i.i52.i.i, label %float64_add.exit.i*/
if (var327) begin
cur_state = bb3_i_i52_i_i;
end
else begin
var237 = var320; /* for PHI node */
cur_state = float64_add_exit_i;
end
end
bb3_i_i52_i_i:
begin
/* %iftmp.34.0.i.i51.i.i = select i1 %315, i64 %320, i64 %319 ; <i64> [#uses=1]*/
iftmp_34_0_i_i51_i_i = (var316) ? var321 : var320;
/* br label %float64_add.exit.i*/
var237 = iftmp_34_0_i_i51_i_i; /* for PHI node */
cur_state = float64_add_exit_i;
end
bb21_i_i_i:
begin
/* %327 = icmp eq i32 %225, 0 ; <i1> [#uses=1]*/
var328 = var225 == 32'd0;
/* %328 = add i64 %234, %233 ; <i64> [#uses=2]*/
var329 = var234 + var233;
/* br label %bb21.i.i.i_1*/
cur_state = bb21_i_i_i_1;
end
bb21_i_i_i_1:
begin
/* br i1 %327, label %bb22.i.i.i, label %bb23.i.i.i*/
if (var328) begin
cur_state = bb22_i_i_i;
end
else begin
cur_state = bb23_i_i_i;
end
end
bb22_i_i_i:
begin
/* %329 = lshr i64 %328, 9 ; <i64> [#uses=1]*/
var330 = var329 >>> (64'd9 % 64);
/* %330 = and i64 %app.0.i, -9223372036854775808 ; <i64> [#uses=1]*/
var331 = app_0_i & -64'd9223372036854775808;
/* br label %bb22.i.i.i_1*/
cur_state = bb22_i_i_i_1;
end
bb22_i_i_i_1:
begin
/* %331 = or i64 %329, %330 ; <i64> [#uses=1]*/
var332 = var330 | var331;
/* br label %float64_add.exit.i*/
var237 = var332; /* for PHI node */
cur_state = float64_add_exit_i;
end
bb23_i_i_i:
begin
/* %332 = add i64 %328, 4611686018427387904 ; <i64> [#uses=1]*/
var333 = var329 + 64'd4611686018427387904;
/* br label %roundAndPack.i.i.i*/
zSig_0_i58_i_i = var333; /* for PHI node */
zExp_1_i_i_i = var225; /* for PHI node */
cur_state = roundAndPack_i_i_i;
end
bb24_i57_i_i:
begin
/* %aSig.1.i54.i.i = phi i64 [ %233, %bb4.i23.i.i_3 ], [ %233, %bb2.i49.i.i.i_6 ], [ %233, %bb4.i50.i.i.i_1 ], [ %303, %bb2.i29.i36.i.i_5 ], [ %305, %bb4.i.i37.i.i_1 ], [ %aSig.0.i30.i.i, %bb13.i32.i.i_4 ] ; <i64> [#uses=1]*/
/* %bSig.1.i55.i.i = phi i64 [ %bSig.0.i21.i.i, %bb4.i23.i.i_3 ], [ %266, %bb2.i49.i.i.i_6 ], [ %268, %bb4.i50.i.i.i_1 ], [ %234, %bb2.i29.i36.i.i_5 ], [ %234, %bb4.i.i37.i.i_1 ], [ %234, %bb13.i32.i.i_4 ] ; <i64> [#uses=1]*/
/* %zExp.0.i56.i.i = phi i32 [ %225, %bb4.i23.i.i_3 ], [ %225, %bb2.i49.i.i.i_6 ], [ %225, %bb4.i50.i.i.i_1 ], [ %228, %bb2.i29.i36.i.i_5 ], [ %228, %bb4.i.i37.i.i_1 ], [ %228, %bb13.i32.i.i_4 ] ; <i32> [#uses=2]*/
/* br label %bb24.i57.i.i_1*/
cur_state = bb24_i57_i_i_1;
end
bb24_i57_i_i_1:
begin
/* %333 = or i64 %aSig.1.i54.i.i, 2305843009213693952 ; <i64> [#uses=1]*/
var334 = aSig_1_i54_i_i | 64'd2305843009213693952;
/* %334 = add i32 %zExp.0.i56.i.i, -1 ; <i32> [#uses=1]*/
var335 = zExp_0_i56_i_i + -32'd1;
/* br label %bb24.i57.i.i_2*/
cur_state = bb24_i57_i_i_2;
end
bb24_i57_i_i_2:
begin
/* %335 = add i64 %333, %bSig.1.i55.i.i ; <i64> [#uses=2]*/
var336 = var334 + bSig_1_i55_i_i;
/* br label %bb24.i57.i.i_3*/
cur_state = bb24_i57_i_i_3;
end
bb24_i57_i_i_3:
begin
/* %336 = shl i64 %335, 1 ; <i64> [#uses=2]*/
var337 = var336 <<< (64'd1 % 64);
/* br label %bb24.i57.i.i_4*/
cur_state = bb24_i57_i_i_4;
end
bb24_i57_i_i_4:
begin
/* %337 = icmp slt i64 %336, 0 ; <i1> [#uses=2]*/
var338 = $signed(var337) < $signed(64'd0);
/* br label %bb24.i57.i.i_5*/
cur_state = bb24_i57_i_i_5;
end
bb24_i57_i_i_5:
begin
/* %..i.i.i = select i1 %337, i64 %335, i64 %336 ; <i64> [#uses=2]*/
__i_i_i = (var338) ? var336 : var337;
/* br i1 %337, label %bb25.i.i.i, label %roundAndPack.i.i.i*/
if (var338) begin
cur_state = bb25_i_i_i;
end
else begin
zSig_0_i58_i_i = __i_i_i; /* for PHI node */
zExp_1_i_i_i = var335; /* for PHI node */
cur_state = roundAndPack_i_i_i;
end
end
bb25_i_i_i:
begin
/* br label %roundAndPack.i.i.i*/
zSig_0_i58_i_i = __i_i_i; /* for PHI node */
zExp_1_i_i_i = zExp_0_i56_i_i; /* for PHI node */
cur_state = roundAndPack_i_i_i;
end
roundAndPack_i_i_i:
begin
/* %zSig.0.i58.i.i = phi i64 [ %..i.i.i, %bb25.i.i.i ], [ %..i.i.i, %bb24.i57.i.i_5 ], [ %332, %bb23.i.i.i ] ; <i64> [#uses=1]*/
/* %zExp.1.i.i.i = phi i32 [ %zExp.0.i56.i.i, %bb25.i.i.i ], [ %334, %bb24.i57.i.i_5 ], [ %225, %bb23.i.i.i ] ; <i32> [#uses=1]*/
/* br label %roundAndPack.i.i.i_1*/
cur_state = roundAndPack_i_i_i_1;
end
roundAndPack_i_i_i_1:
begin
/* %338 = tail call fastcc i64 @roundAndPackFloat64(i32 %220, i32 %zExp.1.i.i.i, i64 %zSig.0.i58.i.i) nounwind ; <i64> [#uses=1]*/
roundAndPackFloat64_start = 1;
/* Argument: %220 = trunc i64 %218 to i32 ; <i32> [#uses=5]*/
roundAndPackFloat64_zSign = var220;
/* Argument: %zExp.1.i.i.i = phi i32 [ %zExp.0.i56.i.i, %bb25.i.i.i ], [ %334, %bb24.i57.i.i_5 ], [ %225, %bb23.i.i.i ] ; <i32> [#uses=1]*/
roundAndPackFloat64_zExp = zExp_1_i_i_i;
/* Argument: %zSig.0.i58.i.i = phi i64 [ %..i.i.i, %bb25.i.i.i ], [ %..i.i.i, %bb24.i57.i.i_5 ], [ %332, %bb23.i.i.i ] ; <i64> [#uses=1]*/
roundAndPackFloat64_zSig = zSig_0_i58_i_i;
cur_state = roundAndPack_i_i_i_1_call_0;
end
roundAndPack_i_i_i_1_call_0:
begin
roundAndPackFloat64_start = 0;
if (roundAndPackFloat64_finish == 1)
begin
var339 = roundAndPackFloat64_return_val;
cur_state = roundAndPack_i_i_i_1_call_1;
end
else
cur_state = roundAndPack_i_i_i_1_call_0;
end
roundAndPack_i_i_i_1_call_1:
begin
/* br label %float64_add.exit.i*/
var237 = var339; /* for PHI node */
cur_state = float64_add_exit_i;
end
bb1_i6_i:
begin
/* %339 = shl i64 %app.0.i, 10 ; <i64> [#uses=1]*/
var340 = app_0_i <<< (64'd10 % 64);
/* %340 = shl i64 %217, 10 ; <i64> [#uses=1]*/
var341 = var60 <<< (64'd10 % 64);
/* %341 = icmp sgt i32 %229, 0 ; <i1> [#uses=1]*/
var342 = $signed(var229) > $signed(32'd0);
/* br label %bb1.i6.i_1*/
cur_state = bb1_i6_i_1;
end
bb1_i6_i_1:
begin
/* %342 = and i64 %339, 4611686018427386880 ; <i64> [#uses=9]*/
var343 = var340 & 64'd4611686018427386880;
/* %343 = and i64 %340, 4611686018427386880 ; <i64> [#uses=9]*/
var344 = var341 & 64'd4611686018427386880;
/* br i1 %341, label %aExpBigger.i.i.i, label %bb.i.i7.i*/
if (var342) begin
cur_state = aExpBigger_i_i_i;
end
else begin
cur_state = bb_i_i7_i;
end
end
bb_i_i7_i:
begin
/* %344 = icmp slt i32 %229, 0 ; <i1> [#uses=1]*/
var345 = $signed(var229) < $signed(32'd0);
/* br label %bb.i.i7.i_1*/
cur_state = bb_i_i7_i_1;
end
bb_i_i7_i_1:
begin
/* br i1 %344, label %bExpBigger.i.i.i, label %bb1.i.i8.i*/
if (var345) begin
cur_state = bExpBigger_i_i_i;
end
else begin
cur_state = bb1_i_i8_i;
end
end
bb1_i_i8_i:
begin
/* switch i32 %225, label %bb7.i.i12.i [
i32 2047, label %bb2.i.i9.i
i32 0, label %bb6.i.i.i
]*/
case(var225)
32'd2047:
begin
cur_state = bb2_i_i9_i;
end
32'd0:
begin
cur_state = bb6_i_i_i;
end
default:
begin
bExp_0_i_i_i = var228; /* for PHI node */
aExp_0_i_i_i = var225; /* for PHI node */
cur_state = bb7_i_i12_i;
end
endcase
end
bb2_i_i9_i:
begin
/* %345 = or i64 %343, %342 ; <i64> [#uses=1]*/
var346 = var344 | var343;
/* br label %bb2.i.i9.i_1*/
cur_state = bb2_i_i9_i_1;
end
bb2_i_i9_i_1:
begin
/* %346 = icmp eq i64 %345, 0 ; <i1> [#uses=1]*/
var347 = var346 == 64'd0;
/* br label %bb2.i.i9.i_2*/
cur_state = bb2_i_i9_i_2;
end
bb2_i_i9_i_2:
begin
/* br i1 %346, label %bb4.i.i11.i, label %bb3.i.i10.i*/
if (var347) begin
cur_state = bb4_i_i11_i;
end
else begin
cur_state = bb3_i_i10_i;
end
end
bb3_i_i10_i:
begin
/* %347 = and i64 %app.0.i, 9221120237041090560 ; <i64> [#uses=1]*/
var348 = app_0_i & 64'd9221120237041090560;
/* br label %bb3.i.i10.i_1*/
cur_state = bb3_i_i10_i_1;
end
bb3_i_i10_i_1:
begin
/* %348 = icmp eq i64 %347, 9218868437227405312 ; <i1> [#uses=1]*/
var349 = var348 == 64'd9218868437227405312;
/* br label %bb3.i.i10.i_2*/
cur_state = bb3_i_i10_i_2;
end
bb3_i_i10_i_2:
begin
/* br i1 %348, label %bb.i14.i55.i.i.i, label %float64_is_signaling_nan.exit16.i56.i.i.i*/
if (var349) begin
cur_state = bb_i14_i55_i_i_i;
end
else begin
var350 = 32'd0; /* for PHI node */
cur_state = float64_is_signaling_nan_exit16_i56_i_i_i;
end
end
bb_i14_i55_i_i_i:
begin
/* %349 = and i64 %app.0.i, 2251799813685247 ; <i64> [#uses=1]*/
var351 = app_0_i & 64'd2251799813685247;
/* br label %bb.i14.i55.i.i.i_1*/
cur_state = bb_i14_i55_i_i_i_1;
end
bb_i14_i55_i_i_i_1:
begin
/* %not..i12.i53.i.i.i = icmp ne i64 %349, 0 ; <i1> [#uses=1]*/
not__i12_i53_i_i_i = var351 != 64'd0;
/* br label %bb.i14.i55.i.i.i_2*/
cur_state = bb_i14_i55_i_i_i_2;
end
bb_i14_i55_i_i_i_2:
begin
/* %retval.i13.i54.i.i.i = zext i1 %not..i12.i53.i.i.i to i32 ; <i32> [#uses=1]*/
retval_i13_i54_i_i_i = not__i12_i53_i_i_i;
/* br label %float64_is_signaling_nan.exit16.i56.i.i.i*/
var350 = retval_i13_i54_i_i_i; /* for PHI node */
cur_state = float64_is_signaling_nan_exit16_i56_i_i_i;
end
float64_is_signaling_nan_exit16_i56_i_i_i:
begin
/* %350 = phi i32 [ %retval.i13.i54.i.i.i, %bb.i14.i55.i.i.i_2 ], [ 0, %bb3.i.i10.i_2 ] ; <i32> [#uses=2]*/
/* %351 = shl i64 %217, 1 ; <i64> [#uses=1]*/
var352 = var60 <<< (64'd1 % 64);
/* %352 = and i64 %217, 9221120237041090560 ; <i64> [#uses=1]*/
var353 = var60 & 64'd9221120237041090560;
/* br label %float64_is_signaling_nan.exit16.i56.i.i.i_1*/
cur_state = float64_is_signaling_nan_exit16_i56_i_i_i_1;
end
float64_is_signaling_nan_exit16_i56_i_i_i_1:
begin
/* %353 = icmp ugt i64 %351, -9007199254740992 ; <i1> [#uses=1]*/
var354 = var352 > -64'd9007199254740992;
/* %354 = icmp eq i64 %352, 9218868437227405312 ; <i1> [#uses=1]*/
var355 = var353 == 64'd9218868437227405312;
/* br label %float64_is_signaling_nan.exit16.i56.i.i.i_2*/
cur_state = float64_is_signaling_nan_exit16_i56_i_i_i_2;
end
float64_is_signaling_nan_exit16_i56_i_i_i_2:
begin
/* br i1 %354, label %bb.i.i59.i.i.i, label %float64_is_signaling_nan.exit.i60.i.i.i*/
if (var355) begin
cur_state = bb_i_i59_i_i_i;
end
else begin
var356 = 32'd0; /* for PHI node */
cur_state = float64_is_signaling_nan_exit_i60_i_i_i;
end
end
bb_i_i59_i_i_i:
begin
/* %355 = and i64 %217, 2251799813685247 ; <i64> [#uses=1]*/
var357 = var60 & 64'd2251799813685247;
/* br label %bb.i.i59.i.i.i_1*/
cur_state = bb_i_i59_i_i_i_1;
end
bb_i_i59_i_i_i_1:
begin
/* %not..i.i57.i.i.i = icmp ne i64 %355, 0 ; <i1> [#uses=1]*/
not__i_i57_i_i_i = var357 != 64'd0;
/* br label %bb.i.i59.i.i.i_2*/
cur_state = bb_i_i59_i_i_i_2;
end
bb_i_i59_i_i_i_2:
begin
/* %retval.i.i58.i.i.i = zext i1 %not..i.i57.i.i.i to i32 ; <i32> [#uses=1]*/
retval_i_i58_i_i_i = not__i_i57_i_i_i;
/* br label %float64_is_signaling_nan.exit.i60.i.i.i*/
var356 = retval_i_i58_i_i_i; /* for PHI node */
cur_state = float64_is_signaling_nan_exit_i60_i_i_i;
end
float64_is_signaling_nan_exit_i60_i_i_i:
begin
/* %356 = phi i32 [ %retval.i.i58.i.i.i, %bb.i.i59.i.i.i_2 ], [ 0, %float64_is_signaling_nan.exit16.i56.i.i.i_2 ] ; <i32> [#uses=2]*/
/* %357 = or i64 %app.0.i, 2251799813685248 ; <i64> [#uses=2]*/
var358 = app_0_i | 64'd2251799813685248;
/* %358 = or i64 %217, 2251799813685248 ; <i64> [#uses=2]*/
var359 = var60 | 64'd2251799813685248;
/* br label %float64_is_signaling_nan.exit.i60.i.i.i_1*/
cur_state = float64_is_signaling_nan_exit_i60_i_i_i_1;
end
float64_is_signaling_nan_exit_i60_i_i_i_1:
begin
/* %359 = or i32 %356, %350 ; <i32> [#uses=1]*/
var360 = var356 | var350;
/* br label %float64_is_signaling_nan.exit.i60.i.i.i_2*/
cur_state = float64_is_signaling_nan_exit_i60_i_i_i_2;
end
float64_is_signaling_nan_exit_i60_i_i_i_2:
begin
/* %360 = icmp eq i32 %359, 0 ; <i1> [#uses=1]*/
var361 = var360 == 32'd0;
/* br label %float64_is_signaling_nan.exit.i60.i.i.i_3*/
cur_state = float64_is_signaling_nan_exit_i60_i_i_i_3;
end
float64_is_signaling_nan_exit_i60_i_i_i_3:
begin
/* br i1 %360, label %bb1.i62.i.i.i, label %bb.i61.i.i.i*/
if (var361) begin
cur_state = bb1_i62_i_i_i;
end
else begin
cur_state = bb_i61_i_i_i;
end
end
bb_i61_i_i_i:
begin
/* %361 = load i32* @float_exception_flags, align 4 ; <i32> [#uses=1]*/
/* br label %bb.i61.i.i.i_1*/
cur_state = bb_i61_i_i_i_1;
end
bb_i61_i_i_i_1:
begin
var362 = memory_controller_out[31:0];
/* %load_noop12 = add i32 %361, 0 ; <i32> [#uses=1]*/
load_noop12 = var362 + 32'd0;
/* br label %bb.i61.i.i.i_2*/
cur_state = bb_i61_i_i_i_2;
end
bb_i61_i_i_i_2:
begin
/* %362 = or i32 %load_noop12, 16 ; <i32> [#uses=1]*/
var363 = load_noop12 | 32'd16;
/* br label %bb.i61.i.i.i_3*/
cur_state = bb_i61_i_i_i_3;
end
bb_i61_i_i_i_3:
begin
/* store i32 %362, i32* @float_exception_flags, align 4*/
/* br label %bb1.i62.i.i.i*/
cur_state = bb1_i62_i_i_i;
end
bb1_i62_i_i_i:
begin
/* %363 = icmp eq i32 %356, 0 ; <i1> [#uses=1]*/
var364 = var356 == 32'd0;
/* br label %bb1.i62.i.i.i_1*/
cur_state = bb1_i62_i_i_i_1;
end
bb1_i62_i_i_i_1:
begin
/* br i1 %363, label %bb2.i63.i.i.i, label %float64_add.exit.i*/
if (var364) begin
cur_state = bb2_i63_i_i_i;
end
else begin
var237 = var359; /* for PHI node */
cur_state = float64_add_exit_i;
end
end
bb2_i63_i_i_i:
begin
/* %364 = icmp eq i32 %350, 0 ; <i1> [#uses=1]*/
var365 = var350 == 32'd0;
/* br label %bb2.i63.i.i.i_1*/
cur_state = bb2_i63_i_i_i_1;
end
bb2_i63_i_i_i_1:
begin
/* br i1 %364, label %bb3.i65.i.i.i, label %float64_add.exit.i*/
if (var365) begin
cur_state = bb3_i65_i_i_i;
end
else begin
var237 = var358; /* for PHI node */
cur_state = float64_add_exit_i;
end
end
bb3_i65_i_i_i:
begin
/* %iftmp.34.0.i64.i.i.i = select i1 %353, i64 %358, i64 %357 ; <i64> [#uses=1]*/
iftmp_34_0_i64_i_i_i = (var354) ? var359 : var358;
/* br label %float64_add.exit.i*/
var237 = iftmp_34_0_i64_i_i_i; /* for PHI node */
cur_state = float64_add_exit_i;
end
bb4_i_i11_i:
begin
/* %365 = load i32* @float_exception_flags, align 4 ; <i32> [#uses=1]*/
/* br label %bb4.i.i11.i_1*/
cur_state = bb4_i_i11_i_1;
end
bb4_i_i11_i_1:
begin
var366 = memory_controller_out[31:0];
/* %load_noop13 = add i32 %365, 0 ; <i32> [#uses=1]*/
load_noop13 = var366 + 32'd0;
/* br label %bb4.i.i11.i_2*/
cur_state = bb4_i_i11_i_2;
end
bb4_i_i11_i_2:
begin
/* %366 = or i32 %load_noop13, 16 ; <i32> [#uses=1]*/
var367 = load_noop13 | 32'd16;
/* br label %bb4.i.i11.i_3*/
cur_state = bb4_i_i11_i_3;
end
bb4_i_i11_i_3:
begin
/* store i32 %366, i32* @float_exception_flags, align 4*/
/* br label %float64_add.exit.i*/
var237 = 64'd9223372036854775807; /* for PHI node */
cur_state = float64_add_exit_i;
end
bb6_i_i_i:
begin
/* br label %bb7.i.i12.i*/
bExp_0_i_i_i = 32'd1; /* for PHI node */
aExp_0_i_i_i = 32'd1; /* for PHI node */
cur_state = bb7_i_i12_i;
end
bb7_i_i12_i:
begin
/* %bExp.0.i.i.i = phi i32 [ 1, %bb6.i.i.i ], [ %228, %bb1.i.i8.i ] ; <i32> [#uses=1]*/
/* %aExp.0.i.i.i = phi i32 [ 1, %bb6.i.i.i ], [ %225, %bb1.i.i8.i ] ; <i32> [#uses=1]*/
/* %367 = icmp ult i64 %343, %342 ; <i1> [#uses=1]*/
var368 = var344 < var343;
/* br label %bb7.i.i12.i_1*/
cur_state = bb7_i_i12_i_1;
end
bb7_i_i12_i_1:
begin
/* br i1 %367, label %aBigger.i.i.i, label %bb8.i.i13.i*/
if (var368) begin
aSig_2_i_i_i = var343; /* for PHI node */
bSig_2_i_i_i = var344; /* for PHI node */
aExp_1_i_i_i = aExp_0_i_i_i; /* for PHI node */
cur_state = aBigger_i_i_i;
end
else begin
cur_state = bb8_i_i13_i;
end
end
bb8_i_i13_i:
begin
/* %368 = icmp ult i64 %342, %343 ; <i1> [#uses=1]*/
var369 = var343 < var344;
/* br label %bb8.i.i13.i_1*/
cur_state = bb8_i_i13_i_1;
end
bb8_i_i13_i_1:
begin
/* br i1 %368, label %bBigger.i.i.i, label %float64_add.exit.i*/
if (var369) begin
aSig_1_i_i_i = var343; /* for PHI node */
bSig_0_i_i_i = var344; /* for PHI node */
bExp_1_i_i_i = bExp_0_i_i_i; /* for PHI node */
cur_state = bBigger_i_i_i;
end
else begin
var237 = 64'd0; /* for PHI node */
cur_state = float64_add_exit_i;
end
end
bExpBigger_i_i_i:
begin
/* %369 = icmp eq i32 %228, 2047 ; <i1> [#uses=1]*/
var370 = var228 == 32'd2047;
/* br label %bExpBigger.i.i.i_1*/
cur_state = bExpBigger_i_i_i_1;
end
bExpBigger_i_i_i_1:
begin
/* br i1 %369, label %bb10.i.i14.i, label %bb13.i.i.i*/
if (var370) begin
cur_state = bb10_i_i14_i;
end
else begin
cur_state = bb13_i_i_i;
end
end
bb10_i_i14_i:
begin
/* %370 = icmp eq i64 %343, 0 ; <i1> [#uses=1]*/
var371 = var344 == 64'd0;
/* br label %bb10.i.i14.i_1*/
cur_state = bb10_i_i14_i_1;
end
bb10_i_i14_i_1:
begin
/* br i1 %370, label %bb12.i.i.i, label %bb11.i.i.i*/
if (var371) begin
cur_state = bb12_i_i_i;
end
else begin
cur_state = bb11_i_i_i;
end
end
bb11_i_i_i:
begin
/* %371 = and i64 %app.0.i, 9221120237041090560 ; <i64> [#uses=1]*/
var372 = app_0_i & 64'd9221120237041090560;
/* br label %bb11.i.i.i_1*/
cur_state = bb11_i_i_i_1;
end
bb11_i_i_i_1:
begin
/* %372 = icmp eq i64 %371, 9218868437227405312 ; <i1> [#uses=1]*/
var373 = var372 == 64'd9218868437227405312;
/* br label %bb11.i.i.i_2*/
cur_state = bb11_i_i_i_2;
end
bb11_i_i_i_2:
begin
/* br i1 %372, label %bb.i14.i39.i.i.i, label %float64_is_signaling_nan.exit16.i40.i.i.i*/
if (var373) begin
cur_state = bb_i14_i39_i_i_i;
end
else begin
var374 = 32'd0; /* for PHI node */
cur_state = float64_is_signaling_nan_exit16_i40_i_i_i;
end
end
bb_i14_i39_i_i_i:
begin
/* %373 = and i64 %app.0.i, 2251799813685247 ; <i64> [#uses=1]*/
var375 = app_0_i & 64'd2251799813685247;
/* br label %bb.i14.i39.i.i.i_1*/
cur_state = bb_i14_i39_i_i_i_1;
end
bb_i14_i39_i_i_i_1:
begin
/* %not..i12.i37.i.i.i = icmp ne i64 %373, 0 ; <i1> [#uses=1]*/
not__i12_i37_i_i_i = var375 != 64'd0;
/* br label %bb.i14.i39.i.i.i_2*/
cur_state = bb_i14_i39_i_i_i_2;
end
bb_i14_i39_i_i_i_2:
begin
/* %retval.i13.i38.i.i.i = zext i1 %not..i12.i37.i.i.i to i32 ; <i32> [#uses=1]*/
retval_i13_i38_i_i_i = not__i12_i37_i_i_i;
/* br label %float64_is_signaling_nan.exit16.i40.i.i.i*/
var374 = retval_i13_i38_i_i_i; /* for PHI node */
cur_state = float64_is_signaling_nan_exit16_i40_i_i_i;
end
float64_is_signaling_nan_exit16_i40_i_i_i:
begin
/* %374 = phi i32 [ %retval.i13.i38.i.i.i, %bb.i14.i39.i.i.i_2 ], [ 0, %bb11.i.i.i_2 ] ; <i32> [#uses=2]*/
/* %375 = shl i64 %217, 1 ; <i64> [#uses=1]*/
var376 = var60 <<< (64'd1 % 64);
/* %376 = and i64 %217, 9221120237041090560 ; <i64> [#uses=1]*/
var377 = var60 & 64'd9221120237041090560;
/* br label %float64_is_signaling_nan.exit16.i40.i.i.i_1*/
cur_state = float64_is_signaling_nan_exit16_i40_i_i_i_1;
end
float64_is_signaling_nan_exit16_i40_i_i_i_1:
begin
/* %377 = icmp ugt i64 %375, -9007199254740992 ; <i1> [#uses=1]*/
var378 = var376 > -64'd9007199254740992;
/* %378 = icmp eq i64 %376, 9218868437227405312 ; <i1> [#uses=1]*/
var379 = var377 == 64'd9218868437227405312;
/* br label %float64_is_signaling_nan.exit16.i40.i.i.i_2*/
cur_state = float64_is_signaling_nan_exit16_i40_i_i_i_2;
end
float64_is_signaling_nan_exit16_i40_i_i_i_2:
begin
/* br i1 %378, label %bb.i.i43.i.i.i, label %float64_is_signaling_nan.exit.i44.i.i.i*/
if (var379) begin
cur_state = bb_i_i43_i_i_i;
end
else begin
var380 = 32'd0; /* for PHI node */
cur_state = float64_is_signaling_nan_exit_i44_i_i_i;
end
end
bb_i_i43_i_i_i:
begin
/* %379 = and i64 %217, 2251799813685247 ; <i64> [#uses=1]*/
var381 = var60 & 64'd2251799813685247;
/* br label %bb.i.i43.i.i.i_1*/
cur_state = bb_i_i43_i_i_i_1;
end
bb_i_i43_i_i_i_1:
begin
/* %not..i.i41.i.i.i = icmp ne i64 %379, 0 ; <i1> [#uses=1]*/
not__i_i41_i_i_i = var381 != 64'd0;
/* br label %bb.i.i43.i.i.i_2*/
cur_state = bb_i_i43_i_i_i_2;
end
bb_i_i43_i_i_i_2:
begin
/* %retval.i.i42.i.i.i = zext i1 %not..i.i41.i.i.i to i32 ; <i32> [#uses=1]*/
retval_i_i42_i_i_i = not__i_i41_i_i_i;
/* br label %float64_is_signaling_nan.exit.i44.i.i.i*/
var380 = retval_i_i42_i_i_i; /* for PHI node */
cur_state = float64_is_signaling_nan_exit_i44_i_i_i;
end
float64_is_signaling_nan_exit_i44_i_i_i:
begin
/* %380 = phi i32 [ %retval.i.i42.i.i.i, %bb.i.i43.i.i.i_2 ], [ 0, %float64_is_signaling_nan.exit16.i40.i.i.i_2 ] ; <i32> [#uses=2]*/
/* %381 = or i64 %app.0.i, 2251799813685248 ; <i64> [#uses=2]*/
var382 = app_0_i | 64'd2251799813685248;
/* %382 = or i64 %217, 2251799813685248 ; <i64> [#uses=2]*/
var383 = var60 | 64'd2251799813685248;
/* br label %float64_is_signaling_nan.exit.i44.i.i.i_1*/
cur_state = float64_is_signaling_nan_exit_i44_i_i_i_1;
end
float64_is_signaling_nan_exit_i44_i_i_i_1:
begin
/* %383 = or i32 %380, %374 ; <i32> [#uses=1]*/
var384 = var380 | var374;
/* br label %float64_is_signaling_nan.exit.i44.i.i.i_2*/
cur_state = float64_is_signaling_nan_exit_i44_i_i_i_2;
end
float64_is_signaling_nan_exit_i44_i_i_i_2:
begin
/* %384 = icmp eq i32 %383, 0 ; <i1> [#uses=1]*/
var385 = var384 == 32'd0;
/* br label %float64_is_signaling_nan.exit.i44.i.i.i_3*/
cur_state = float64_is_signaling_nan_exit_i44_i_i_i_3;
end
float64_is_signaling_nan_exit_i44_i_i_i_3:
begin
/* br i1 %384, label %bb1.i46.i.i.i, label %bb.i45.i.i.i*/
if (var385) begin
cur_state = bb1_i46_i_i_i;
end
else begin
cur_state = bb_i45_i_i_i;
end
end
bb_i45_i_i_i:
begin
/* %385 = load i32* @float_exception_flags, align 4 ; <i32> [#uses=1]*/
/* br label %bb.i45.i.i.i_1*/
cur_state = bb_i45_i_i_i_1;
end
bb_i45_i_i_i_1:
begin
var386 = memory_controller_out[31:0];
/* %load_noop14 = add i32 %385, 0 ; <i32> [#uses=1]*/
load_noop14 = var386 + 32'd0;
/* br label %bb.i45.i.i.i_2*/
cur_state = bb_i45_i_i_i_2;
end
bb_i45_i_i_i_2:
begin
/* %386 = or i32 %load_noop14, 16 ; <i32> [#uses=1]*/
var387 = load_noop14 | 32'd16;
/* br label %bb.i45.i.i.i_3*/
cur_state = bb_i45_i_i_i_3;
end
bb_i45_i_i_i_3:
begin
/* store i32 %386, i32* @float_exception_flags, align 4*/
/* br label %bb1.i46.i.i.i*/
cur_state = bb1_i46_i_i_i;
end
bb1_i46_i_i_i:
begin
/* %387 = icmp eq i32 %380, 0 ; <i1> [#uses=1]*/
var388 = var380 == 32'd0;
/* br label %bb1.i46.i.i.i_1*/
cur_state = bb1_i46_i_i_i_1;
end
bb1_i46_i_i_i_1:
begin
/* br i1 %387, label %bb2.i47.i.i.i, label %float64_add.exit.i*/
if (var388) begin
cur_state = bb2_i47_i_i_i;
end
else begin
var237 = var383; /* for PHI node */
cur_state = float64_add_exit_i;
end
end
bb2_i47_i_i_i:
begin
/* %388 = icmp eq i32 %374, 0 ; <i1> [#uses=1]*/
var389 = var374 == 32'd0;
/* br label %bb2.i47.i.i.i_1*/
cur_state = bb2_i47_i_i_i_1;
end
bb2_i47_i_i_i_1:
begin
/* br i1 %388, label %bb3.i49.i.i.i, label %float64_add.exit.i*/
if (var389) begin
cur_state = bb3_i49_i_i_i;
end
else begin
var237 = var382; /* for PHI node */
cur_state = float64_add_exit_i;
end
end
bb3_i49_i_i_i:
begin
/* %iftmp.34.0.i48.i.i.i = select i1 %377, i64 %382, i64 %381 ; <i64> [#uses=1]*/
iftmp_34_0_i48_i_i_i = (var378) ? var383 : var382;
/* br label %float64_add.exit.i*/
var237 = iftmp_34_0_i48_i_i_i; /* for PHI node */
cur_state = float64_add_exit_i;
end
bb12_i_i_i:
begin
/* %389 = xor i32 %220, 1 ; <i32> [#uses=1]*/
var390 = var220 ^ 32'd1;
/* br label %bb12.i.i.i_1*/
cur_state = bb12_i_i_i_1;
end
bb12_i_i_i_1:
begin
/* %390 = zext i32 %389 to i64 ; <i64> [#uses=1]*/
var391 = var390;
/* br label %bb12.i.i.i_2*/
cur_state = bb12_i_i_i_2;
end
bb12_i_i_i_2:
begin
/* %391 = shl i64 %390, 63 ; <i64> [#uses=1]*/
var392 = var391 <<< (64'd63 % 64);
/* br label %bb12.i.i.i_3*/
cur_state = bb12_i_i_i_3;
end
bb12_i_i_i_3:
begin
/* %392 = or i64 %391, 9218868437227405312 ; <i64> [#uses=1]*/
var393 = var392 | 64'd9218868437227405312;
/* br label %float64_add.exit.i*/
var237 = var393; /* for PHI node */
cur_state = float64_add_exit_i;
end
bb13_i_i_i:
begin
/* %393 = icmp eq i32 %225, 0 ; <i1> [#uses=2]*/
var394 = var225 == 32'd0;
/* %394 = or i64 %342, 4611686018427387904 ; <i64> [#uses=1]*/
var395 = var343 | 64'd4611686018427387904;
/* br label %bb13.i.i.i_1*/
cur_state = bb13_i_i_i_1;
end
bb13_i_i_i_1:
begin
/* %aSig.0.i.i.i = select i1 %393, i64 %342, i64 %394 ; <i64> [#uses=4]*/
aSig_0_i_i_i = (var394) ? var343 : var395;
/* %395 = zext i1 %393 to i32 ; <i32> [#uses=1]*/
var396 = var394;
/* br label %bb13.i.i.i_2*/
cur_state = bb13_i_i_i_2;
end
bb13_i_i_i_2:
begin
/* %expDiff.0.i.i.i = add i32 %229, %395 ; <i32> [#uses=3]*/
expDiff_0_i_i_i = var229 + var396;
/* br label %bb13.i.i.i_3*/
cur_state = bb13_i_i_i_3;
end
bb13_i_i_i_3:
begin
/* %396 = sub i32 0, %expDiff.0.i.i.i ; <i32> [#uses=2]*/
var397 = 32'd0 - expDiff_0_i_i_i;
/* %397 = icmp eq i32 %expDiff.0.i.i.i, 0 ; <i1> [#uses=1]*/
var398 = expDiff_0_i_i_i == 32'd0;
/* br label %bb13.i.i.i_4*/
cur_state = bb13_i_i_i_4;
end
bb13_i_i_i_4:
begin
/* br i1 %397, label %shift64RightJamming.exit36.i.i.i, label %bb1.i30.i.i.i*/
if (var398) begin
z_0_i35_i_i_i = aSig_0_i_i_i; /* for PHI node */
cur_state = shift64RightJamming_exit36_i_i_i;
end
else begin
cur_state = bb1_i30_i_i_i;
end
end
bb1_i30_i_i_i:
begin
/* %398 = icmp slt i32 %396, 64 ; <i1> [#uses=1]*/
var399 = $signed(var397) < $signed(32'd64);
/* br label %bb1.i30.i.i.i_1*/
cur_state = bb1_i30_i_i_i_1;
end
bb1_i30_i_i_i_1:
begin
/* br i1 %398, label %bb2.i33.i.i.i, label %bb4.i34.i.i.i*/
if (var399) begin
cur_state = bb2_i33_i_i_i;
end
else begin
cur_state = bb4_i34_i_i_i;
end
end
bb2_i33_i_i_i:
begin
/* %.cast.i31.i.i.i = zext i32 %396 to i64 ; <i64> [#uses=1]*/
_cast_i31_i_i_i = var397;
/* %399 = and i32 %expDiff.0.i.i.i, 63 ; <i32> [#uses=1]*/
var400 = expDiff_0_i_i_i & 32'd63;
/* br label %bb2.i33.i.i.i_1*/
cur_state = bb2_i33_i_i_i_1;
end
bb2_i33_i_i_i_1:
begin
/* %400 = lshr i64 %aSig.0.i.i.i, %.cast.i31.i.i.i ; <i64> [#uses=1]*/
var401 = aSig_0_i_i_i >>> (_cast_i31_i_i_i % 64);
/* %.cast3.i32.i.i.i = zext i32 %399 to i64 ; <i64> [#uses=1]*/
_cast3_i32_i_i_i = var400;
/* br label %bb2.i33.i.i.i_2*/
cur_state = bb2_i33_i_i_i_2;
end
bb2_i33_i_i_i_2:
begin
/* %401 = shl i64 %aSig.0.i.i.i, %.cast3.i32.i.i.i ; <i64> [#uses=1]*/
var402 = aSig_0_i_i_i <<< (_cast3_i32_i_i_i % 64);
/* br label %bb2.i33.i.i.i_3*/
cur_state = bb2_i33_i_i_i_3;
end
bb2_i33_i_i_i_3:
begin
/* %402 = icmp ne i64 %401, 0 ; <i1> [#uses=1]*/
var403 = var402 != 64'd0;
/* br label %bb2.i33.i.i.i_4*/
cur_state = bb2_i33_i_i_i_4;
end
bb2_i33_i_i_i_4:
begin
/* %403 = zext i1 %402 to i64 ; <i64> [#uses=1]*/
var404 = var403;
/* br label %bb2.i33.i.i.i_5*/
cur_state = bb2_i33_i_i_i_5;
end
bb2_i33_i_i_i_5:
begin
/* %404 = or i64 %403, %400 ; <i64> [#uses=1]*/
var405 = var404 | var401;
/* br label %shift64RightJamming.exit36.i.i.i*/
z_0_i35_i_i_i = var405; /* for PHI node */
cur_state = shift64RightJamming_exit36_i_i_i;
end
bb4_i34_i_i_i:
begin
/* %405 = icmp ne i64 %aSig.0.i.i.i, 0 ; <i1> [#uses=1]*/
var406 = aSig_0_i_i_i != 64'd0;
/* br label %bb4.i34.i.i.i_1*/
cur_state = bb4_i34_i_i_i_1;
end
bb4_i34_i_i_i_1:
begin
/* %406 = zext i1 %405 to i64 ; <i64> [#uses=1]*/
var407 = var406;
/* br label %shift64RightJamming.exit36.i.i.i*/
z_0_i35_i_i_i = var407; /* for PHI node */
cur_state = shift64RightJamming_exit36_i_i_i;
end
shift64RightJamming_exit36_i_i_i:
begin
/* %z.0.i35.i.i.i = phi i64 [ %404, %bb2.i33.i.i.i_5 ], [ %406, %bb4.i34.i.i.i_1 ], [ %aSig.0.i.i.i, %bb13.i.i.i_4 ] ; <i64> [#uses=1]*/
/* %407 = or i64 %343, 4611686018427387904 ; <i64> [#uses=1]*/
var408 = var344 | 64'd4611686018427387904;
/* br label %bBigger.i.i.i*/
aSig_1_i_i_i = z_0_i35_i_i_i; /* for PHI node */
bSig_0_i_i_i = var408; /* for PHI node */
bExp_1_i_i_i = var228; /* for PHI node */
cur_state = bBigger_i_i_i;
end
bBigger_i_i_i:
begin
/* %aSig.1.i.i.i = phi i64 [ %z.0.i35.i.i.i, %shift64RightJamming.exit36.i.i.i ], [ %342, %bb8.i.i13.i_1 ] ; <i64> [#uses=1]*/
/* %bSig.0.i.i.i = phi i64 [ %407, %shift64RightJamming.exit36.i.i.i ], [ %343, %bb8.i.i13.i_1 ] ; <i64> [#uses=1]*/
/* %bExp.1.i.i.i = phi i32 [ %228, %shift64RightJamming.exit36.i.i.i ], [ %bExp.0.i.i.i, %bb8.i.i13.i_1 ] ; <i32> [#uses=1]*/
/* %408 = xor i32 %220, 1 ; <i32> [#uses=1]*/
var409 = var220 ^ 32'd1;
/* br label %bBigger.i.i.i_1*/
cur_state = bBigger_i_i_i_1;
end
bBigger_i_i_i_1:
begin
/* %409 = sub i64 %bSig.0.i.i.i, %aSig.1.i.i.i ; <i64> [#uses=1]*/
var410 = bSig_0_i_i_i - aSig_1_i_i_i;
/* br label %normalizeRoundAndPack.i.i.i*/
zExp_0_i_i_i = bExp_1_i_i_i; /* for PHI node */
zSig_0_i_i_i = var410; /* for PHI node */
zSign_addr_0_i_i_i = var409; /* for PHI node */
cur_state = normalizeRoundAndPack_i_i_i;
end
aExpBigger_i_i_i:
begin
/* %410 = icmp eq i32 %225, 2047 ; <i1> [#uses=1]*/
var411 = var225 == 32'd2047;
/* br label %aExpBigger.i.i.i_1*/
cur_state = aExpBigger_i_i_i_1;
end
aExpBigger_i_i_i_1:
begin
/* br i1 %410, label %bb17.i.i.i, label %bb20.i.i.i*/
if (var411) begin
cur_state = bb17_i_i_i;
end
else begin
cur_state = bb20_i_i_i;
end
end
bb17_i_i_i:
begin
/* %411 = icmp eq i64 %342, 0 ; <i1> [#uses=1]*/
var412 = var343 == 64'd0;
/* br label %bb17.i.i.i_1*/
cur_state = bb17_i_i_i_1;
end
bb17_i_i_i_1:
begin
/* br i1 %411, label %float64_add.exit.i, label %bb18.i.i.i*/
if (var412) begin
var237 = app_0_i; /* for PHI node */
cur_state = float64_add_exit_i;
end
else begin
cur_state = bb18_i_i_i;
end
end
bb18_i_i_i:
begin
/* %412 = and i64 %app.0.i, 9221120237041090560 ; <i64> [#uses=1]*/
var413 = app_0_i & 64'd9221120237041090560;
/* br label %bb18.i.i.i_1*/
cur_state = bb18_i_i_i_1;
end
bb18_i_i_i_1:
begin
/* %413 = icmp eq i64 %412, 9218868437227405312 ; <i1> [#uses=1]*/
var414 = var413 == 64'd9218868437227405312;
/* br label %bb18.i.i.i_2*/
cur_state = bb18_i_i_i_2;
end
bb18_i_i_i_2:
begin
/* br i1 %413, label %bb.i14.i.i.i.i, label %float64_is_signaling_nan.exit16.i.i.i.i*/
if (var414) begin
cur_state = bb_i14_i_i_i_i;
end
else begin
var415 = 32'd0; /* for PHI node */
cur_state = float64_is_signaling_nan_exit16_i_i_i_i;
end
end
bb_i14_i_i_i_i:
begin
/* %414 = and i64 %app.0.i, 2251799813685247 ; <i64> [#uses=1]*/
var416 = app_0_i & 64'd2251799813685247;
/* br label %bb.i14.i.i.i.i_1*/
cur_state = bb_i14_i_i_i_i_1;
end
bb_i14_i_i_i_i_1:
begin
/* %not..i12.i.i.i.i = icmp ne i64 %414, 0 ; <i1> [#uses=1]*/
not__i12_i_i_i_i = var416 != 64'd0;
/* br label %bb.i14.i.i.i.i_2*/
cur_state = bb_i14_i_i_i_i_2;
end
bb_i14_i_i_i_i_2:
begin
/* %retval.i13.i.i.i.i = zext i1 %not..i12.i.i.i.i to i32 ; <i32> [#uses=1]*/
retval_i13_i_i_i_i = not__i12_i_i_i_i;
/* br label %float64_is_signaling_nan.exit16.i.i.i.i*/
var415 = retval_i13_i_i_i_i; /* for PHI node */
cur_state = float64_is_signaling_nan_exit16_i_i_i_i;
end
float64_is_signaling_nan_exit16_i_i_i_i:
begin
/* %415 = phi i32 [ %retval.i13.i.i.i.i, %bb.i14.i.i.i.i_2 ], [ 0, %bb18.i.i.i_2 ] ; <i32> [#uses=2]*/
/* %416 = shl i64 %217, 1 ; <i64> [#uses=1]*/
var417 = var60 <<< (64'd1 % 64);
/* %417 = and i64 %217, 9221120237041090560 ; <i64> [#uses=1]*/
var418 = var60 & 64'd9221120237041090560;
/* br label %float64_is_signaling_nan.exit16.i.i.i.i_1*/
cur_state = float64_is_signaling_nan_exit16_i_i_i_i_1;
end
float64_is_signaling_nan_exit16_i_i_i_i_1:
begin
/* %418 = icmp ugt i64 %416, -9007199254740992 ; <i1> [#uses=1]*/
var419 = var417 > -64'd9007199254740992;
/* %419 = icmp eq i64 %417, 9218868437227405312 ; <i1> [#uses=1]*/
var420 = var418 == 64'd9218868437227405312;
/* br label %float64_is_signaling_nan.exit16.i.i.i.i_2*/
cur_state = float64_is_signaling_nan_exit16_i_i_i_i_2;
end
float64_is_signaling_nan_exit16_i_i_i_i_2:
begin
/* br i1 %419, label %bb.i.i27.i.i.i, label %float64_is_signaling_nan.exit.i.i.i.i*/
if (var420) begin
cur_state = bb_i_i27_i_i_i;
end
else begin
var421 = 32'd0; /* for PHI node */
cur_state = float64_is_signaling_nan_exit_i_i_i_i;
end
end
bb_i_i27_i_i_i:
begin
/* %420 = and i64 %217, 2251799813685247 ; <i64> [#uses=1]*/
var422 = var60 & 64'd2251799813685247;
/* br label %bb.i.i27.i.i.i_1*/
cur_state = bb_i_i27_i_i_i_1;
end
bb_i_i27_i_i_i_1:
begin
/* %not..i.i.i.i.i = icmp ne i64 %420, 0 ; <i1> [#uses=1]*/
not__i_i_i_i_i = var422 != 64'd0;
/* br label %bb.i.i27.i.i.i_2*/
cur_state = bb_i_i27_i_i_i_2;
end
bb_i_i27_i_i_i_2:
begin
/* %retval.i.i.i.i.i = zext i1 %not..i.i.i.i.i to i32 ; <i32> [#uses=1]*/
retval_i_i_i_i_i = not__i_i_i_i_i;
/* br label %float64_is_signaling_nan.exit.i.i.i.i*/
var421 = retval_i_i_i_i_i; /* for PHI node */
cur_state = float64_is_signaling_nan_exit_i_i_i_i;
end
float64_is_signaling_nan_exit_i_i_i_i:
begin
/* %421 = phi i32 [ %retval.i.i.i.i.i, %bb.i.i27.i.i.i_2 ], [ 0, %float64_is_signaling_nan.exit16.i.i.i.i_2 ] ; <i32> [#uses=2]*/
/* %422 = or i64 %app.0.i, 2251799813685248 ; <i64> [#uses=2]*/
var423 = app_0_i | 64'd2251799813685248;
/* %423 = or i64 %217, 2251799813685248 ; <i64> [#uses=2]*/
var424 = var60 | 64'd2251799813685248;
/* br label %float64_is_signaling_nan.exit.i.i.i.i_1*/
cur_state = float64_is_signaling_nan_exit_i_i_i_i_1;
end
float64_is_signaling_nan_exit_i_i_i_i_1:
begin
/* %424 = or i32 %421, %415 ; <i32> [#uses=1]*/
var425 = var421 | var415;
/* br label %float64_is_signaling_nan.exit.i.i.i.i_2*/
cur_state = float64_is_signaling_nan_exit_i_i_i_i_2;
end
float64_is_signaling_nan_exit_i_i_i_i_2:
begin
/* %425 = icmp eq i32 %424, 0 ; <i1> [#uses=1]*/
var426 = var425 == 32'd0;
/* br label %float64_is_signaling_nan.exit.i.i.i.i_3*/
cur_state = float64_is_signaling_nan_exit_i_i_i_i_3;
end
float64_is_signaling_nan_exit_i_i_i_i_3:
begin
/* br i1 %425, label %bb1.i28.i.i.i, label %bb.i.i.i15.i*/
if (var426) begin
cur_state = bb1_i28_i_i_i;
end
else begin
cur_state = bb_i_i_i15_i;
end
end
bb_i_i_i15_i:
begin
/* %426 = load i32* @float_exception_flags, align 4 ; <i32> [#uses=1]*/
/* br label %bb.i.i.i15.i_1*/
cur_state = bb_i_i_i15_i_1;
end
bb_i_i_i15_i_1:
begin
var427 = memory_controller_out[31:0];
/* %load_noop15 = add i32 %426, 0 ; <i32> [#uses=1]*/
load_noop15 = var427 + 32'd0;
/* br label %bb.i.i.i15.i_2*/
cur_state = bb_i_i_i15_i_2;
end
bb_i_i_i15_i_2:
begin
/* %427 = or i32 %load_noop15, 16 ; <i32> [#uses=1]*/
var428 = load_noop15 | 32'd16;
/* br label %bb.i.i.i15.i_3*/
cur_state = bb_i_i_i15_i_3;
end
bb_i_i_i15_i_3:
begin
/* store i32 %427, i32* @float_exception_flags, align 4*/
/* br label %bb1.i28.i.i.i*/
cur_state = bb1_i28_i_i_i;
end
bb1_i28_i_i_i:
begin
/* %428 = icmp eq i32 %421, 0 ; <i1> [#uses=1]*/
var429 = var421 == 32'd0;
/* br label %bb1.i28.i.i.i_1*/
cur_state = bb1_i28_i_i_i_1;
end
bb1_i28_i_i_i_1:
begin
/* br i1 %428, label %bb2.i29.i.i.i, label %float64_add.exit.i*/
if (var429) begin
cur_state = bb2_i29_i_i_i;
end
else begin
var237 = var424; /* for PHI node */
cur_state = float64_add_exit_i;
end
end
bb2_i29_i_i_i:
begin
/* %429 = icmp eq i32 %415, 0 ; <i1> [#uses=1]*/
var430 = var415 == 32'd0;
/* br label %bb2.i29.i.i.i_1*/
cur_state = bb2_i29_i_i_i_1;
end
bb2_i29_i_i_i_1:
begin
/* br i1 %429, label %bb3.i.i.i.i, label %float64_add.exit.i*/
if (var430) begin
cur_state = bb3_i_i_i_i;
end
else begin
var237 = var423; /* for PHI node */
cur_state = float64_add_exit_i;
end
end
bb3_i_i_i_i:
begin
/* %iftmp.34.0.i.i.i.i = select i1 %418, i64 %423, i64 %422 ; <i64> [#uses=1]*/
iftmp_34_0_i_i_i_i = (var419) ? var424 : var423;
/* br label %float64_add.exit.i*/
var237 = iftmp_34_0_i_i_i_i; /* for PHI node */
cur_state = float64_add_exit_i;
end
bb20_i_i_i:
begin
/* %430 = icmp eq i32 %228, 0 ; <i1> [#uses=2]*/
var431 = var228 == 32'd0;
/* %431 = add i32 %229, -1 ; <i32> [#uses=1]*/
var432 = var229 + -32'd1;
/* %432 = or i64 %343, 4611686018427387904 ; <i64> [#uses=1]*/
var433 = var344 | 64'd4611686018427387904;
/* br label %bb20.i.i.i_1*/
cur_state = bb20_i_i_i_1;
end
bb20_i_i_i_1:
begin
/* %bSig.1.i.i.i = select i1 %430, i64 %343, i64 %432 ; <i64> [#uses=4]*/
bSig_1_i_i_i = (var431) ? var344 : var433;
/* %expDiff.1.i.i.i = select i1 %430, i32 %431, i32 %229 ; <i32> [#uses=4]*/
expDiff_1_i_i_i = (var431) ? var432 : var229;
/* br label %bb20.i.i.i_2*/
cur_state = bb20_i_i_i_2;
end
bb20_i_i_i_2:
begin
/* %433 = icmp eq i32 %expDiff.1.i.i.i, 0 ; <i1> [#uses=1]*/
var434 = expDiff_1_i_i_i == 32'd0;
/* br label %bb20.i.i.i_3*/
cur_state = bb20_i_i_i_3;
end
bb20_i_i_i_3:
begin
/* br i1 %433, label %shift64RightJamming.exit.i.i.i, label %bb1.i.i.i16.i*/
if (var434) begin
z_0_i_i_i_i = bSig_1_i_i_i; /* for PHI node */
cur_state = shift64RightJamming_exit_i_i_i;
end
else begin
cur_state = bb1_i_i_i16_i;
end
end
bb1_i_i_i16_i:
begin
/* %434 = icmp slt i32 %expDiff.1.i.i.i, 64 ; <i1> [#uses=1]*/
var435 = $signed(expDiff_1_i_i_i) < $signed(32'd64);
/* br label %bb1.i.i.i16.i_1*/
cur_state = bb1_i_i_i16_i_1;
end
bb1_i_i_i16_i_1:
begin
/* br i1 %434, label %bb2.i.i.i.i, label %bb4.i.i.i.i*/
if (var435) begin
cur_state = bb2_i_i_i_i;
end
else begin
cur_state = bb4_i_i_i_i;
end
end
bb2_i_i_i_i:
begin
/* %.cast.i26.i.i.i = zext i32 %expDiff.1.i.i.i to i64 ; <i64> [#uses=1]*/
_cast_i26_i_i_i = expDiff_1_i_i_i;
/* %435 = sub i32 0, %expDiff.1.i.i.i ; <i32> [#uses=1]*/
var436 = 32'd0 - expDiff_1_i_i_i;
/* br label %bb2.i.i.i.i_1*/
cur_state = bb2_i_i_i_i_1;
end
bb2_i_i_i_i_1:
begin
/* %436 = lshr i64 %bSig.1.i.i.i, %.cast.i26.i.i.i ; <i64> [#uses=1]*/
var437 = bSig_1_i_i_i >>> (_cast_i26_i_i_i % 64);
/* %437 = and i32 %435, 63 ; <i32> [#uses=1]*/
var438 = var436 & 32'd63;
/* br label %bb2.i.i.i.i_2*/
cur_state = bb2_i_i_i_i_2;
end
bb2_i_i_i_i_2:
begin
/* %.cast3.i.i.i.i = zext i32 %437 to i64 ; <i64> [#uses=1]*/
_cast3_i_i_i_i = var438;
/* br label %bb2.i.i.i.i_3*/
cur_state = bb2_i_i_i_i_3;
end
bb2_i_i_i_i_3:
begin
/* %438 = shl i64 %bSig.1.i.i.i, %.cast3.i.i.i.i ; <i64> [#uses=1]*/
var439 = bSig_1_i_i_i <<< (_cast3_i_i_i_i % 64);
/* br label %bb2.i.i.i.i_4*/
cur_state = bb2_i_i_i_i_4;
end
bb2_i_i_i_i_4:
begin
/* %439 = icmp ne i64 %438, 0 ; <i1> [#uses=1]*/
var440 = var439 != 64'd0;
/* br label %bb2.i.i.i.i_5*/
cur_state = bb2_i_i_i_i_5;
end
bb2_i_i_i_i_5:
begin
/* %440 = zext i1 %439 to i64 ; <i64> [#uses=1]*/
var441 = var440;
/* br label %bb2.i.i.i.i_6*/
cur_state = bb2_i_i_i_i_6;
end
bb2_i_i_i_i_6:
begin
/* %441 = or i64 %440, %436 ; <i64> [#uses=1]*/
var442 = var441 | var437;
/* br label %shift64RightJamming.exit.i.i.i*/
z_0_i_i_i_i = var442; /* for PHI node */
cur_state = shift64RightJamming_exit_i_i_i;
end
bb4_i_i_i_i:
begin
/* %442 = icmp ne i64 %bSig.1.i.i.i, 0 ; <i1> [#uses=1]*/
var443 = bSig_1_i_i_i != 64'd0;
/* br label %bb4.i.i.i.i_1*/
cur_state = bb4_i_i_i_i_1;
end
bb4_i_i_i_i_1:
begin
/* %443 = zext i1 %442 to i64 ; <i64> [#uses=1]*/
var444 = var443;
/* br label %shift64RightJamming.exit.i.i.i*/
z_0_i_i_i_i = var444; /* for PHI node */
cur_state = shift64RightJamming_exit_i_i_i;
end
shift64RightJamming_exit_i_i_i:
begin
/* %z.0.i.i.i.i = phi i64 [ %441, %bb2.i.i.i.i_6 ], [ %443, %bb4.i.i.i.i_1 ], [ %bSig.1.i.i.i, %bb20.i.i.i_3 ] ; <i64> [#uses=1]*/
/* %444 = or i64 %342, 4611686018427387904 ; <i64> [#uses=1]*/
var445 = var343 | 64'd4611686018427387904;
/* br label %aBigger.i.i.i*/
aSig_2_i_i_i = var445; /* for PHI node */
bSig_2_i_i_i = z_0_i_i_i_i; /* for PHI node */
aExp_1_i_i_i = var225; /* for PHI node */
cur_state = aBigger_i_i_i;
end
aBigger_i_i_i:
begin
/* %aSig.2.i.i.i = phi i64 [ %444, %shift64RightJamming.exit.i.i.i ], [ %342, %bb7.i.i12.i_1 ] ; <i64> [#uses=1]*/
/* %bSig.2.i.i.i = phi i64 [ %z.0.i.i.i.i, %shift64RightJamming.exit.i.i.i ], [ %343, %bb7.i.i12.i_1 ] ; <i64> [#uses=1]*/
/* %aExp.1.i.i.i = phi i32 [ %225, %shift64RightJamming.exit.i.i.i ], [ %aExp.0.i.i.i, %bb7.i.i12.i_1 ] ; <i32> [#uses=1]*/
/* br label %aBigger.i.i.i_1*/
cur_state = aBigger_i_i_i_1;
end
aBigger_i_i_i_1:
begin
/* %445 = sub i64 %aSig.2.i.i.i, %bSig.2.i.i.i ; <i64> [#uses=1]*/
var446 = aSig_2_i_i_i - bSig_2_i_i_i;
/* br label %normalizeRoundAndPack.i.i.i*/
zExp_0_i_i_i = aExp_1_i_i_i; /* for PHI node */
zSig_0_i_i_i = var446; /* for PHI node */
zSign_addr_0_i_i_i = var220; /* for PHI node */
cur_state = normalizeRoundAndPack_i_i_i;
end
normalizeRoundAndPack_i_i_i:
begin
/* %zExp.0.i.i.i = phi i32 [ %aExp.1.i.i.i, %aBigger.i.i.i_1 ], [ %bExp.1.i.i.i, %bBigger.i.i.i_1 ] ; <i32> [#uses=1]*/
/* %zSig.0.i.i.i = phi i64 [ %445, %aBigger.i.i.i_1 ], [ %409, %bBigger.i.i.i_1 ] ; <i64> [#uses=4]*/
/* %zSign_addr.0.i.i.i = phi i32 [ %220, %aBigger.i.i.i_1 ], [ %408, %bBigger.i.i.i_1 ] ; <i32> [#uses=1]*/
/* br label %normalizeRoundAndPack.i.i.i_1*/
cur_state = normalizeRoundAndPack_i_i_i_1;
end
normalizeRoundAndPack_i_i_i_1:
begin
/* %446 = icmp ult i64 %zSig.0.i.i.i, 4294967296 ; <i1> [#uses=1]*/
var447 = zSig_0_i_i_i < 64'd4294967296;
/* br label %normalizeRoundAndPack.i.i.i_2*/
cur_state = normalizeRoundAndPack_i_i_i_2;
end
normalizeRoundAndPack_i_i_i_2:
begin
/* br i1 %446, label %bb.i.i.i.i.i, label %bb1.i.i.i.i.i*/
if (var447) begin
cur_state = bb_i_i_i_i_i;
end
else begin
cur_state = bb1_i_i_i_i_i;
end
end
bb_i_i_i_i_i:
begin
/* %extract.t.i.i.i.i.i = trunc i64 %zSig.0.i.i.i to i32 ; <i32> [#uses=1]*/
extract_t_i_i_i_i_i = zSig_0_i_i_i[31:0];
/* br label %normalizeRoundAndPackFloat64.exit.i.i.i*/
shiftCount_0_i_i_i_i17_i = 32'd31; /* for PHI node */
a_addr_0_off0_i_i_i_i_i = extract_t_i_i_i_i_i; /* for PHI node */
cur_state = normalizeRoundAndPackFloat64_exit_i_i_i;
end
bb1_i_i_i_i_i:
begin
/* %447 = lshr i64 %zSig.0.i.i.i, 32 ; <i64> [#uses=1]*/
var448 = zSig_0_i_i_i >>> (64'd32 % 64);
/* br label %bb1.i.i.i.i.i_1*/
cur_state = bb1_i_i_i_i_i_1;
end
bb1_i_i_i_i_i_1:
begin
/* %extract.t4.i.i.i.i.i = trunc i64 %447 to i32 ; <i32> [#uses=1]*/
extract_t4_i_i_i_i_i = var448[31:0];
/* br label %normalizeRoundAndPackFloat64.exit.i.i.i*/
shiftCount_0_i_i_i_i17_i = -32'd1; /* for PHI node */
a_addr_0_off0_i_i_i_i_i = extract_t4_i_i_i_i_i; /* for PHI node */
cur_state = normalizeRoundAndPackFloat64_exit_i_i_i;
end
normalizeRoundAndPackFloat64_exit_i_i_i:
begin
/* %shiftCount.0.i.i.i.i17.i = phi i32 [ 31, %bb.i.i.i.i.i ], [ -1, %bb1.i.i.i.i.i_1 ] ; <i32> [#uses=1]*/
/* %a_addr.0.off0.i.i.i.i.i = phi i32 [ %extract.t.i.i.i.i.i, %bb.i.i.i.i.i ], [ %extract.t4.i.i.i.i.i, %bb1.i.i.i.i.i_1 ] ; <i32> [#uses=3]*/
/* %448 = add i32 %zExp.0.i.i.i, -1 ; <i32> [#uses=1]*/
var449 = zExp_0_i_i_i + -32'd1;
/* br label %normalizeRoundAndPackFloat64.exit.i.i.i_1*/
cur_state = normalizeRoundAndPackFloat64_exit_i_i_i_1;
end
normalizeRoundAndPackFloat64_exit_i_i_i_1:
begin
/* %449 = shl i32 %a_addr.0.off0.i.i.i.i.i, 16 ; <i32> [#uses=1]*/
var450 = a_addr_0_off0_i_i_i_i_i <<< (32'd16 % 32);
/* %450 = icmp ult i32 %a_addr.0.off0.i.i.i.i.i, 65536 ; <i1> [#uses=2]*/
var451 = a_addr_0_off0_i_i_i_i_i < 32'd65536;
/* br label %normalizeRoundAndPackFloat64.exit.i.i.i_2*/
cur_state = normalizeRoundAndPackFloat64_exit_i_i_i_2;
end
normalizeRoundAndPackFloat64_exit_i_i_i_2:
begin
/* %.a.i.i.i.i.i.i = select i1 %450, i32 %449, i32 %a_addr.0.off0.i.i.i.i.i ; <i32> [#uses=3]*/
_a_i_i_i_i_i_i = (var451) ? var450 : a_addr_0_off0_i_i_i_i_i;
/* %shiftCount.0.i.i.i.i.i.i = select i1 %450, i32 16, i32 0 ; <i32> [#uses=2]*/
shiftCount_0_i_i_i_i_i_i = (var451) ? 32'd16 : 32'd0;
/* br label %normalizeRoundAndPackFloat64.exit.i.i.i_3*/
cur_state = normalizeRoundAndPackFloat64_exit_i_i_i_3;
end
normalizeRoundAndPackFloat64_exit_i_i_i_3:
begin
/* %451 = icmp ult i32 %.a.i.i.i.i.i.i, 16777216 ; <i1> [#uses=2]*/
var452 = _a_i_i_i_i_i_i < 32'd16777216;
/* %452 = or i32 %shiftCount.0.i.i.i.i.i.i, 8 ; <i32> [#uses=1]*/
var453 = shiftCount_0_i_i_i_i_i_i | 32'd8;
/* %453 = shl i32 %.a.i.i.i.i.i.i, 8 ; <i32> [#uses=1]*/
var454 = _a_i_i_i_i_i_i <<< (32'd8 % 32);
/* br label %normalizeRoundAndPackFloat64.exit.i.i.i_4*/
cur_state = normalizeRoundAndPackFloat64_exit_i_i_i_4;
end
normalizeRoundAndPackFloat64_exit_i_i_i_4:
begin
/* %shiftCount.1.i.i.i.i.i.i = select i1 %451, i32 %452, i32 %shiftCount.0.i.i.i.i.i.i ; <i32> [#uses=1]*/
shiftCount_1_i_i_i_i_i_i = (var452) ? var453 : shiftCount_0_i_i_i_i_i_i;
/* %a_addr.1.i.i.i.i.i.i = select i1 %451, i32 %453, i32 %.a.i.i.i.i.i.i ; <i32> [#uses=1]*/
a_addr_1_i_i_i_i_i_i = (var452) ? var454 : _a_i_i_i_i_i_i;
/* br label %normalizeRoundAndPackFloat64.exit.i.i.i_5*/
cur_state = normalizeRoundAndPackFloat64_exit_i_i_i_5;
end
normalizeRoundAndPackFloat64_exit_i_i_i_5:
begin
/* %454 = lshr i32 %a_addr.1.i.i.i.i.i.i, 24 ; <i32> [#uses=1]*/
var455 = a_addr_1_i_i_i_i_i_i >>> (32'd24 % 32);
/* br label %normalizeRoundAndPackFloat64.exit.i.i.i_6*/
cur_state = normalizeRoundAndPackFloat64_exit_i_i_i_6;
end
normalizeRoundAndPackFloat64_exit_i_i_i_6:
begin
/* %455 = getelementptr inbounds [256 x i32]* @countLeadingZerosHigh.1302, i32 0, i32 %454 ; <i32*> [#uses=1]*/
var456 = {`TAG_countLeadingZerosHigh_1302, 32'b0} + ((var455 + 256*(32'd0)) << 2);
/* br label %normalizeRoundAndPackFloat64.exit.i.i.i_7*/
cur_state = normalizeRoundAndPackFloat64_exit_i_i_i_7;
end
normalizeRoundAndPackFloat64_exit_i_i_i_7:
begin
/* %456 = load i32* %455, align 4 ; <i32> [#uses=1]*/
/* br label %normalizeRoundAndPackFloat64.exit.i.i.i_8*/
cur_state = normalizeRoundAndPackFloat64_exit_i_i_i_8;
end
normalizeRoundAndPackFloat64_exit_i_i_i_8:
begin
var457 = memory_controller_out[31:0];
/* %load_noop16 = add i32 %456, 0 ; <i32> [#uses=1]*/
load_noop16 = var457 + 32'd0;
/* br label %normalizeRoundAndPackFloat64.exit.i.i.i_9*/
cur_state = normalizeRoundAndPackFloat64_exit_i_i_i_9;
end
normalizeRoundAndPackFloat64_exit_i_i_i_9:
begin
/* %457 = add nsw i32 %load_noop16, %shiftCount.0.i.i.i.i17.i ; <i32> [#uses=1]*/
var458 = load_noop16 + shiftCount_0_i_i_i_i17_i;
/* br label %normalizeRoundAndPackFloat64.exit.i.i.i_10*/
cur_state = normalizeRoundAndPackFloat64_exit_i_i_i_10;
end
normalizeRoundAndPackFloat64_exit_i_i_i_10:
begin
/* %458 = add i32 %457, %shiftCount.1.i.i.i.i.i.i ; <i32> [#uses=2]*/
var459 = var458 + shiftCount_1_i_i_i_i_i_i;
/* br label %normalizeRoundAndPackFloat64.exit.i.i.i_11*/
cur_state = normalizeRoundAndPackFloat64_exit_i_i_i_11;
end
normalizeRoundAndPackFloat64_exit_i_i_i_11:
begin
/* %.cast.i.i.i.i = zext i32 %458 to i64 ; <i64> [#uses=1]*/
_cast_i_i_i_i = var459;
/* %459 = sub i32 %448, %458 ; <i32> [#uses=1]*/
var460 = var449 - var459;
/* br label %normalizeRoundAndPackFloat64.exit.i.i.i_12*/
cur_state = normalizeRoundAndPackFloat64_exit_i_i_i_12;
end
normalizeRoundAndPackFloat64_exit_i_i_i_12:
begin
/* %460 = shl i64 %zSig.0.i.i.i, %.cast.i.i.i.i ; <i64> [#uses=1]*/
var461 = zSig_0_i_i_i <<< (_cast_i_i_i_i % 64);
/* br label %normalizeRoundAndPackFloat64.exit.i.i.i_13*/
cur_state = normalizeRoundAndPackFloat64_exit_i_i_i_13;
end
normalizeRoundAndPackFloat64_exit_i_i_i_13:
begin
/* %461 = tail call fastcc i64 @roundAndPackFloat64(i32 %zSign_addr.0.i.i.i, i32 %459, i64 %460) nounwind ; <i64> [#uses=1]*/
roundAndPackFloat64_start = 1;
/* Argument: %zSign_addr.0.i.i.i = phi i32 [ %220, %aBigger.i.i.i_1 ], [ %408, %bBigger.i.i.i_1 ] ; <i32> [#uses=1]*/
roundAndPackFloat64_zSign = zSign_addr_0_i_i_i;
/* Argument: %459 = sub i32 %448, %458 ; <i32> [#uses=1]*/
roundAndPackFloat64_zExp = var460;
/* Argument: %460 = shl i64 %zSig.0.i.i.i, %.cast.i.i.i.i ; <i64> [#uses=1]*/
roundAndPackFloat64_zSig = var461;
cur_state = normalizeRoundAndPackFloat64_exit_i_i_i_13_call_0;
end
normalizeRoundAndPackFloat64_exit_i_i_i_13_call_0:
begin
roundAndPackFloat64_start = 0;
if (roundAndPackFloat64_finish == 1)
begin
var462 = roundAndPackFloat64_return_val;
cur_state = normalizeRoundAndPackFloat64_exit_i_i_i_13_call_1;
end
else
cur_state = normalizeRoundAndPackFloat64_exit_i_i_i_13_call_0;
end
normalizeRoundAndPackFloat64_exit_i_i_i_13_call_1:
begin
/* br label %float64_add.exit.i*/
var237 = var462; /* for PHI node */
cur_state = float64_add_exit_i;
end
float64_add_exit_i:
begin
/* %462 = phi i64 [ %461, %normalizeRoundAndPackFloat64.exit.i.i.i_13 ], [ %iftmp.34.0.i64.i.i.i, %bb3.i65.i.i.i ], [ 9223372036854775807, %bb4.i.i11.i_3 ], [ %iftmp.34.0.i48.i.i.i, %bb3.i49.i.i.i ], [ %392, %bb12.i.i.i_3 ], [ %iftmp.34.0.i.i.i.i, %bb3.i.i.i.i ], [ %338, %roundAndPack.i.i.i_1 ], [ %331, %bb22.i.i.i_1 ], [ %iftmp.34.0.i.i51.i.i, %bb3.i.i52.i.i ], [ %iftmp.34.0.i41.i.i.i, %bb3.i42.i.i.i ], [ %291, %bb12.i29.i.i_1 ], [ %iftmp.34.0.i64.i18.i.i, %bb3.i65.i19.i.i ], [ %247, %bb2.i63.i17.i.i_1 ], [ %248, %bb1.i62.i16.i.i_1 ], [ %282, %bb2.i40.i.i.i_1 ], [ %283, %bb1.i39.i.i.i_1 ], [ %319, %bb2.i.i50.i.i_1 ], [ %320, %bb1.i.i49.i.i_1 ], [ %app.0.i, %bb18.i39.i.i_2 ], [ %app.0.i, %bb1.i5.i.i_1 ], [ 0, %bb8.i.i13.i_1 ], [ %357, %bb2.i63.i.i.i_1 ], [ %358, %bb1.i62.i.i.i_1 ], [ %381, %bb2.i47.i.i.i_1 ], [ %382, %bb1.i46.i.i.i_1 ], [ %422, %bb2.i29.i.i.i_1 ], [ %423, %bb1.i28.i.i.i_1 ], [ %app.0.i, %bb17.i.i.i_1 ] ; <i64> [#uses=4]*/
/* %463 = add nsw i32 %inc.0.i, 1 ; <i32> [#uses=1]*/
var463 = inc_0_i + 32'd1;
/* %464 = and i64 %217, 9223372036854775807 ; <i64> [#uses=1]*/
var464 = var60 & 64'd9223372036854775807;
/* %465 = and i64 %217, 9218868437227405312 ; <i64> [#uses=1]*/
var465 = var60 & 64'd9218868437227405312;
/* br label %float64_add.exit.i_1*/
cur_state = float64_add_exit_i_1;
end
float64_add_exit_i_1:
begin
/* %466 = icmp eq i64 %465, 9218868437227405312 ; <i1> [#uses=1]*/
var466 = var465 == 64'd9218868437227405312;
/* br label %float64_add.exit.i_2*/
cur_state = float64_add_exit_i_2;
end
float64_add_exit_i_2:
begin
/* br i1 %466, label %bb2.i.i.i, label %bb10.i.i.i*/
if (var466) begin
cur_state = bb2_i_i_i;
end
else begin
cur_state = bb10_i_i_i;
end
end
bb2_i_i_i:
begin
/* %467 = and i64 %217, 4503599627370495 ; <i64> [#uses=1]*/
var467 = var60 & 64'd4503599627370495;
/* br label %bb2.i.i.i_1*/
cur_state = bb2_i_i_i_1;
end
bb2_i_i_i_1:
begin
/* %468 = icmp eq i64 %467, 0 ; <i1> [#uses=1]*/
var468 = var467 == 64'd0;
/* br label %bb2.i.i.i_2*/
cur_state = bb2_i_i_i_2;
end
bb2_i_i_i_2:
begin
/* br i1 %468, label %bb10.i.i.i, label %bb3.i.i.i*/
if (var468) begin
cur_state = bb10_i_i_i;
end
else begin
cur_state = bb3_i_i_i;
end
end
bb3_i_i_i:
begin
/* %469 = load i32* @float_exception_flags, align 4 ; <i32> [#uses=1]*/
/* br label %bb3.i.i.i_1*/
cur_state = bb3_i_i_i_1;
end
bb3_i_i_i_1:
begin
var469 = memory_controller_out[31:0];
/* %load_noop17 = add i32 %469, 0 ; <i32> [#uses=1]*/
load_noop17 = var469 + 32'd0;
/* br label %bb3.i.i.i_2*/
cur_state = bb3_i_i_i_2;
end
bb3_i_i_i_2:
begin
/* %470 = or i32 %load_noop17, 16 ; <i32> [#uses=1]*/
var470 = load_noop17 | 32'd16;
/* br label %bb3.i.i.i_3*/
cur_state = bb3_i_i_i_3;
end
bb3_i_i_i_3:
begin
/* store i32 %470, i32* @float_exception_flags, align 4*/
/* br label %sin.exit*/
cur_state = sin_exit;
end
bb10_i_i_i:
begin
/* %or.cond.i = icmp ult i64 %464, 4532020583610935537 ; <i1> [#uses=1]*/
or_cond_i = var464 < 64'd4532020583610935537;
/* %indvar.next.i = add i32 %indvar.i, 1 ; <i32> [#uses=1]*/
indvar_next_i = indvar_i + 32'd1;
/* br label %bb10.i.i.i_1*/
cur_state = bb10_i_i_i_1;
end
bb10_i_i_i_1:
begin
/* br i1 %or.cond.i, label %sin.exit, label %bb.i*/
if (or_cond_i) begin
cur_state = sin_exit;
end
else begin
indvar_i = indvar_next_i; /* for PHI node */
inc_0_i = var463; /* for PHI node */
diff_0_i = var60; /* for PHI node */
app_0_i = var237; /* for PHI node */
cur_state = bb_i;
end
end
sin_exit:
begin
/* %471 = load i64* %scevgep9, align 8 ; <i64> [#uses=1]*/
/* %472 = bitcast i64 %462 to double ; <double> [#uses=1]*/
var471 = var237;
/* %473 = add nsw i32 %i.04, 1 ; <i32> [#uses=2]*/
var472 = i_04 + 32'd1;
/* br label %sin.exit_1*/
cur_state = sin_exit_1;
end
sin_exit_1:
begin
var473 = memory_controller_out[63:0];
/* %load_noop18 = add i64 %471, 0 ; <i64> [#uses=2]*/
load_noop18 = var473 + 64'd0;
/* %exitcond = icmp eq i32 %473, 36 ; <i1> [#uses=1]*/
exitcond = var472 == 32'd36;
/* br label %sin.exit_2*/
cur_state = sin_exit_2;
end
sin_exit_2:
begin
/* %474 = icmp ne i64 %load_noop18, %462 ; <i1> [#uses=1]*/
var474 = load_noop18 != var237;
/* %475 = tail call i32 (i8*, ...)* @printf(i8* noalias getelementptr inbounds ([53 x i8]* @.str, i32 0, i32 0), i64 %load_noop, i64 %load_noop18, i64 %462, double %472) nounwind ; <i32> [#uses=0]*/
$write("input=%016h expected=%016h output=%016h (%h)\n", load_noop, load_noop18, var237, var471); /* br label %sin.exit_3*/
cur_state = sin_exit_3;
end
sin_exit_3:
begin
/* %476 = zext i1 %474 to i32 ; <i32> [#uses=1]*/
var475 = var474;
/* br label %sin.exit_4*/
cur_state = sin_exit_4;
end
sin_exit_4:
begin
/* %477 = add nsw i32 %476, %main_result.08 ; <i32> [#uses=3]*/
var476 = var475 + main_result_08;
/* br i1 %exitcond, label %bb2, label %bb*/
if (exitcond) begin
cur_state = bb2;
end
else begin
main_result_08 = var476; /* for PHI node */
i_04 = var472; /* for PHI node */
cur_state = bb;
end
end
bb2:
begin
/* %478 = tail call i32 (i8*, ...)* @printf(i8* noalias getelementptr inbounds ([4 x i8]* @.str1, i32 0, i32 0), i32 %477) nounwind ; <i32> [#uses=0]*/
$write("%d\n", var476); /* ret i32 %477*/
return_val = var476;
finish = 1;
cur_state = Wait;
end
endcase
always @(*)
begin
memory_controller_write_enable = 0;
memory_controller_address = 0;
memory_controller_in = 0;
float64_mul_memory_controller_out = 0;
float64_mul_memory_controller_out = 0;
roundAndPackFloat64_memory_controller_out = 0;
roundAndPackFloat64_memory_controller_out = 0;
roundAndPackFloat64_memory_controller_out = 0;
case(cur_state)
default:
begin
// quartus issues a warning if we have no default case
end
bb_2:
begin
memory_controller_address = scevgep;
memory_controller_write_enable = 0;
end
bb_4:
begin
end
bb_4_call_0:
begin
memory_controller_address = float64_mul_memory_controller_address;
memory_controller_write_enable = float64_mul_memory_controller_write_enable;
memory_controller_in = float64_mul_memory_controller_in;
float64_mul_memory_controller_out = memory_controller_out;
end
bb_4_call_1:
begin
end
bb1_i_i_9:
begin
memory_controller_address = var19;
memory_controller_write_enable = 0;
end
int32_to_float64_exit_i:
begin
end
int32_to_float64_exit_i_call_0:
begin
memory_controller_address = float64_mul_memory_controller_address;
memory_controller_write_enable = float64_mul_memory_controller_write_enable;
memory_controller_in = float64_mul_memory_controller_in;
float64_mul_memory_controller_out = memory_controller_out;
end
int32_to_float64_exit_i_call_1:
begin
end
bb_i71_i_i:
begin
memory_controller_address = {`TAG_float_exception_flags, 32'b0};
memory_controller_write_enable = 0;
end
bb_i71_i_i_3:
begin
memory_controller_address = {`TAG_float_exception_flags, 32'b0};
memory_controller_write_enable = 1;
memory_controller_in = var58;
end
bb_i55_i_i:
begin
memory_controller_address = {`TAG_float_exception_flags, 32'b0};
memory_controller_write_enable = 0;
end
bb_i55_i_i_3:
begin
memory_controller_address = {`TAG_float_exception_flags, 32'b0};
memory_controller_write_enable = 1;
memory_controller_in = var79;
end
bb5_i_i:
begin
memory_controller_address = {`TAG_float_exception_flags, 32'b0};
memory_controller_write_enable = 0;
end
bb5_i_i_3:
begin
memory_controller_address = {`TAG_float_exception_flags, 32'b0};
memory_controller_write_enable = 1;
memory_controller_in = var83;
end
bb_i_i_i:
begin
memory_controller_address = {`TAG_float_exception_flags, 32'b0};
memory_controller_write_enable = 0;
end
bb_i_i_i_3:
begin
memory_controller_address = {`TAG_float_exception_flags, 32'b0};
memory_controller_write_enable = 1;
memory_controller_in = var102;
end
bb13_i_i:
begin
memory_controller_address = {`TAG_float_exception_flags, 32'b0};
memory_controller_write_enable = 0;
end
bb14_i_i_1:
begin
memory_controller_address = {`TAG_float_exception_flags, 32'b0};
memory_controller_write_enable = 1;
memory_controller_in = var111;
end
bb15_i_i_1:
begin
memory_controller_address = {`TAG_float_exception_flags, 32'b0};
memory_controller_write_enable = 1;
memory_controller_in = var112;
end
normalizeFloat64Subnormal_exit42_i_i_7:
begin
memory_controller_address = var123;
memory_controller_write_enable = 0;
end
normalizeFloat64Subnormal_exit_i_i_7:
begin
memory_controller_address = var141;
memory_controller_write_enable = 0;
end
bb28_i_i_1:
begin
end
bb28_i_i_1_call_0:
begin
memory_controller_address = roundAndPackFloat64_memory_controller_address;
memory_controller_write_enable = roundAndPackFloat64_memory_controller_write_enable;
memory_controller_in = roundAndPackFloat64_memory_controller_in;
roundAndPackFloat64_memory_controller_out = memory_controller_out;
end
bb28_i_i_1_call_1:
begin
end
bb_i61_i15_i_i:
begin
memory_controller_address = {`TAG_float_exception_flags, 32'b0};
memory_controller_write_enable = 0;
end
bb_i61_i15_i_i_3:
begin
memory_controller_address = {`TAG_float_exception_flags, 32'b0};
memory_controller_write_enable = 1;
memory_controller_in = var253;
end
bb_i38_i_i_i:
begin
memory_controller_address = {`TAG_float_exception_flags, 32'b0};
memory_controller_write_enable = 0;
end
bb_i38_i_i_i_3:
begin
memory_controller_address = {`TAG_float_exception_flags, 32'b0};
memory_controller_write_enable = 1;
memory_controller_in = var288;
end
bb_i_i48_i_i:
begin
memory_controller_address = {`TAG_float_exception_flags, 32'b0};
memory_controller_write_enable = 0;
end
bb_i_i48_i_i_3:
begin
memory_controller_address = {`TAG_float_exception_flags, 32'b0};
memory_controller_write_enable = 1;
memory_controller_in = var325;
end
roundAndPack_i_i_i_1:
begin
end
roundAndPack_i_i_i_1_call_0:
begin
memory_controller_address = roundAndPackFloat64_memory_controller_address;
memory_controller_write_enable = roundAndPackFloat64_memory_controller_write_enable;
memory_controller_in = roundAndPackFloat64_memory_controller_in;
roundAndPackFloat64_memory_controller_out = memory_controller_out;
end
roundAndPack_i_i_i_1_call_1:
begin
end
bb_i61_i_i_i:
begin
memory_controller_address = {`TAG_float_exception_flags, 32'b0};
memory_controller_write_enable = 0;
end
bb_i61_i_i_i_3:
begin
memory_controller_address = {`TAG_float_exception_flags, 32'b0};
memory_controller_write_enable = 1;
memory_controller_in = var363;
end
bb4_i_i11_i:
begin
memory_controller_address = {`TAG_float_exception_flags, 32'b0};
memory_controller_write_enable = 0;
end
bb4_i_i11_i_3:
begin
memory_controller_address = {`TAG_float_exception_flags, 32'b0};
memory_controller_write_enable = 1;
memory_controller_in = var367;
end
bb_i45_i_i_i:
begin
memory_controller_address = {`TAG_float_exception_flags, 32'b0};
memory_controller_write_enable = 0;
end
bb_i45_i_i_i_3:
begin
memory_controller_address = {`TAG_float_exception_flags, 32'b0};
memory_controller_write_enable = 1;
memory_controller_in = var387;
end
bb_i_i_i15_i:
begin
memory_controller_address = {`TAG_float_exception_flags, 32'b0};
memory_controller_write_enable = 0;
end
bb_i_i_i15_i_3:
begin
memory_controller_address = {`TAG_float_exception_flags, 32'b0};
memory_controller_write_enable = 1;
memory_controller_in = var428;
end
normalizeRoundAndPackFloat64_exit_i_i_i_7:
begin
memory_controller_address = var456;
memory_controller_write_enable = 0;
end
normalizeRoundAndPackFloat64_exit_i_i_i_13:
begin
end
normalizeRoundAndPackFloat64_exit_i_i_i_13_call_0:
begin
memory_controller_address = roundAndPackFloat64_memory_controller_address;
memory_controller_write_enable = roundAndPackFloat64_memory_controller_write_enable;
memory_controller_in = roundAndPackFloat64_memory_controller_in;
roundAndPackFloat64_memory_controller_out = memory_controller_out;
end
normalizeRoundAndPackFloat64_exit_i_i_i_13_call_1:
begin
end
bb3_i_i_i:
begin
memory_controller_address = {`TAG_float_exception_flags, 32'b0};
memory_controller_write_enable = 0;
end
bb3_i_i_i_3:
begin
memory_controller_address = {`TAG_float_exception_flags, 32'b0};
memory_controller_write_enable = 1;
memory_controller_in = var470;
end
sin_exit:
begin
memory_controller_address = scevgep9;
memory_controller_write_enable = 0;
end
endcase
end
endmodule
`timescale 1 ns / 1 ns
module roundAndPackFloat64
(
clk,
reset,
start,
finish,
return_val,
zSign,
zExp,
zSig,
memory_controller_write_enable,
memory_controller_address,
memory_controller_in,
memory_controller_out
);
output reg [63:0] return_val;
input clk;
input reset;
input start;
output reg finish;
input [31:0] zSign;
input [31:0] zExp;
input [63:0] zSig;
output reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] memory_controller_address;
output reg memory_controller_write_enable;
output reg [`MEMORY_CONTROLLER_DATA_SIZE-1:0] memory_controller_in;
input wire [`MEMORY_CONTROLLER_DATA_SIZE-1:0] memory_controller_out;
reg [5:0] cur_state;
parameter Wait = 6'd0;
parameter bb7 = 6'd1;
parameter bb7_1 = 6'd2;
parameter bb7_2 = 6'd3;
parameter bb8 = 6'd4;
parameter bb8_1 = 6'd5;
parameter bb9 = 6'd6;
parameter bb9_1 = 6'd7;
parameter bb10 = 6'd8;
parameter bb10_1 = 6'd9;
parameter bb10_2 = 6'd10;
parameter bb11 = 6'd11;
parameter bb11_1 = 6'd12;
parameter bb11_2 = 6'd13;
parameter bb11_3 = 6'd14;
parameter bb12 = 6'd15;
parameter bb12_1 = 6'd16;
parameter bb13 = 6'd17;
parameter bb13_1 = 6'd18;
parameter bb1_i = 6'd19;
parameter bb1_i_1 = 6'd20;
parameter bb2_i = 6'd21;
parameter bb2_i_1 = 6'd22;
parameter bb2_i_2 = 6'd23;
parameter bb2_i_3 = 6'd24;
parameter bb2_i_4 = 6'd25;
parameter bb2_i_5 = 6'd26;
parameter bb4_i = 6'd27;
parameter bb4_i_1 = 6'd28;
parameter shift64RightJamming_exit = 6'd29;
parameter shift64RightJamming_exit_1 = 6'd30;
parameter shift64RightJamming_exit_2 = 6'd31;
parameter shift64RightJamming_exit_3 = 6'd32;
parameter shift64RightJamming_exit_4 = 6'd33;
parameter bb16 = 6'd34;
parameter bb16_1 = 6'd35;
parameter bb16_2 = 6'd36;
parameter bb16_3 = 6'd37;
parameter bb17 = 6'd38;
parameter bb17_1 = 6'd39;
parameter bb17_2 = 6'd40;
parameter bb18 = 6'd41;
parameter bb18_1 = 6'd42;
parameter bb18_2 = 6'd43;
parameter bb18_3 = 6'd44;
parameter bb19 = 6'd45;
parameter bb19_1 = 6'd46;
parameter bb19_2 = 6'd47;
parameter bb19_3 = 6'd48;
parameter bb19_4 = 6'd49;
parameter bb19_5 = 6'd50;
parameter bb19_6 = 6'd51;
parameter bb19_7 = 6'd52;
parameter bb19_8 = 6'd53;
reg [31:0] var0;
reg [15:0] var1;
reg [31:0] var2;
reg [63:0] z_0_i;
reg [31:0] var25;
reg [31:0] var26;
reg var27;
reg [31:0] var28;
reg [31:0] var29;
reg [63:0] zSig_addr_0;
reg [31:0] roundBits_0;
reg [31:0] zExp_addr_0;
reg var30;
reg [31:0] var31;
reg [31:0] var32;
reg var3;
reg [31:0] var14;
reg var15;
reg var16;
reg [63:0] _cast_i;
reg [63:0] var18;
reg [31:0] var17;
reg [63:0] _cast3_i;
reg [63:0] var19;
reg var20;
reg [63:0] var21;
reg [63:0] var22;
reg var23;
reg [63:0] var24;
reg var4;
reg var5;
reg [63:0] var6;
reg var7;
reg [31:0] var9;
reg [31:0] var11;
reg [63:0] var8;
reg [63:0] var10;
reg [63:0] var12;
reg var13;
reg [63:0] var33;
reg [63:0] var37;
reg var34;
reg [31:0] var38;
reg [31:0] not_var40;
reg [63:0] var41;
reg [63:0] var42;
reg var43;
reg [63:0] var35;
reg [63:0] var39;
reg [63:0] var36;
reg [63:0] _op;
reg [63:0] var45;
reg [63:0] var44;
reg [63:0] var46;
reg [31:0] load_noop1;
reg [31:0] load_noop;
reg [31:0] load_noop2;
always @(posedge clk)
if (reset)
cur_state = Wait;
else
case(cur_state)
Wait:
begin
finish = 0;
if (start == 1)
cur_state = bb7;
else
cur_state = Wait;
end
bb7:
begin
/* %0 = trunc i64 %zSig to i32 ; <i32> [#uses=1]*/
var0 = zSig[31:0];
/* %1 = trunc i32 %zExp to i16 ; <i16> [#uses=1]*/
var1 = zExp[15:0];
/* br label %bb7_1*/
cur_state = bb7_1;
end
bb7_1:
begin
/* %2 = and i32 %0, 1023 ; <i32> [#uses=2]*/
var2 = var0 & 32'd1023;
/* %3 = icmp ugt i16 %1, 2044 ; <i1> [#uses=1]*/
var3 = var1 > 16'd2044;
/* br label %bb7_2*/
cur_state = bb7_2;
end
bb7_2:
begin
/* br i1 %3, label %bb8, label %bb17*/
if (var3) begin
cur_state = bb8;
end
else begin
zSig_addr_0 = zSig; /* for PHI node */
roundBits_0 = var2; /* for PHI node */
zExp_addr_0 = zExp; /* for PHI node */
cur_state = bb17;
end
end
bb8:
begin
/* %4 = icmp sgt i32 %zExp, 2045 ; <i1> [#uses=1]*/
var4 = $signed(zExp) > $signed(32'd2045);
/* br label %bb8_1*/
cur_state = bb8_1;
end
bb8_1:
begin
/* br i1 %4, label %bb11, label %bb9*/
if (var4) begin
cur_state = bb11;
end
else begin
cur_state = bb9;
end
end
bb9:
begin
/* %5 = icmp eq i32 %zExp, 2045 ; <i1> [#uses=1]*/
var5 = zExp == 32'd2045;
/* br label %bb9_1*/
cur_state = bb9_1;
end
bb9_1:
begin
/* br i1 %5, label %bb10, label %bb12*/
if (var5) begin
cur_state = bb10;
end
else begin
cur_state = bb12;
end
end
bb10:
begin
/* %6 = add i64 %zSig, 512 ; <i64> [#uses=1]*/
var6 = zSig + 64'd512;
/* br label %bb10_1*/
cur_state = bb10_1;
end
bb10_1:
begin
/* %7 = icmp slt i64 %6, 0 ; <i1> [#uses=1]*/
var7 = $signed(var6) < $signed(64'd0);
/* br label %bb10_2*/
cur_state = bb10_2;
end
bb10_2:
begin
/* br i1 %7, label %bb11, label %bb12*/
if (var7) begin
cur_state = bb11;
end
else begin
cur_state = bb12;
end
end
bb11:
begin
/* %8 = load i32* @float_exception_flags, align 4 ; <i32> [#uses=1]*/
/* %9 = zext i32 %zSign to i64 ; <i64> [#uses=1]*/
var8 = zSign;
/* br label %bb11_1*/
cur_state = bb11_1;
end
bb11_1:
begin
var9 = memory_controller_out[31:0];
/* %load_noop = add i32 %8, 0 ; <i32> [#uses=1]*/
load_noop = var9 + 32'd0;
/* %10 = shl i64 %9, 63 ; <i64> [#uses=1]*/
var10 = var8 <<< (64'd63 % 64);
/* br label %bb11_2*/
cur_state = bb11_2;
end
bb11_2:
begin
/* %11 = or i32 %load_noop, 9 ; <i32> [#uses=1]*/
var11 = load_noop | 32'd9;
/* %12 = or i64 %10, 9218868437227405312 ; <i64> [#uses=1]*/
var12 = var10 | 64'd9218868437227405312;
/* br label %bb11_3*/
cur_state = bb11_3;
end
bb11_3:
begin
/* store i32 %11, i32* @float_exception_flags, align 4*/
/* ret i64 %12*/
return_val = var12;
finish = 1;
cur_state = Wait;
end
bb12:
begin
/* %13 = icmp slt i32 %zExp, 0 ; <i1> [#uses=1]*/
var13 = $signed(zExp) < $signed(32'd0);
/* br label %bb12_1*/
cur_state = bb12_1;
end
bb12_1:
begin
/* br i1 %13, label %bb13, label %bb17*/
if (var13) begin
cur_state = bb13;
end
else begin
zSig_addr_0 = zSig; /* for PHI node */
roundBits_0 = var2; /* for PHI node */
zExp_addr_0 = zExp; /* for PHI node */
cur_state = bb17;
end
end
bb13:
begin
/* %14 = sub i32 0, %zExp ; <i32> [#uses=2]*/
var14 = 32'd0 - zExp;
/* %15 = icmp eq i32 %zExp, 0 ; <i1> [#uses=1]*/
var15 = zExp == 32'd0;
/* br label %bb13_1*/
cur_state = bb13_1;
end
bb13_1:
begin
/* br i1 %15, label %shift64RightJamming.exit, label %bb1.i*/
if (var15) begin
z_0_i = zSig; /* for PHI node */
cur_state = shift64RightJamming_exit;
end
else begin
cur_state = bb1_i;
end
end
bb1_i:
begin
/* %16 = icmp slt i32 %14, 64 ; <i1> [#uses=1]*/
var16 = $signed(var14) < $signed(32'd64);
/* br label %bb1.i_1*/
cur_state = bb1_i_1;
end
bb1_i_1:
begin
/* br i1 %16, label %bb2.i, label %bb4.i*/
if (var16) begin
cur_state = bb2_i;
end
else begin
cur_state = bb4_i;
end
end
bb2_i:
begin
/* %.cast.i = zext i32 %14 to i64 ; <i64> [#uses=1]*/
_cast_i = var14;
/* %17 = and i32 %zExp, 63 ; <i32> [#uses=1]*/
var17 = zExp & 32'd63;
/* br label %bb2.i_1*/
cur_state = bb2_i_1;
end
bb2_i_1:
begin
/* %18 = lshr i64 %zSig, %.cast.i ; <i64> [#uses=1]*/
var18 = zSig >>> (_cast_i % 64);
/* %.cast3.i = zext i32 %17 to i64 ; <i64> [#uses=1]*/
_cast3_i = var17;
/* br label %bb2.i_2*/
cur_state = bb2_i_2;
end
bb2_i_2:
begin
/* %19 = shl i64 %zSig, %.cast3.i ; <i64> [#uses=1]*/
var19 = zSig <<< (_cast3_i % 64);
/* br label %bb2.i_3*/
cur_state = bb2_i_3;
end
bb2_i_3:
begin
/* %20 = icmp ne i64 %19, 0 ; <i1> [#uses=1]*/
var20 = var19 != 64'd0;
/* br label %bb2.i_4*/
cur_state = bb2_i_4;
end
bb2_i_4:
begin
/* %21 = zext i1 %20 to i64 ; <i64> [#uses=1]*/
var21 = var20;
/* br label %bb2.i_5*/
cur_state = bb2_i_5;
end
bb2_i_5:
begin
/* %22 = or i64 %21, %18 ; <i64> [#uses=1]*/
var22 = var21 | var18;
/* br label %shift64RightJamming.exit*/
z_0_i = var22; /* for PHI node */
cur_state = shift64RightJamming_exit;
end
bb4_i:
begin
/* %23 = icmp ne i64 %zSig, 0 ; <i1> [#uses=1]*/
var23 = zSig != 64'd0;
/* br label %bb4.i_1*/
cur_state = bb4_i_1;
end
bb4_i_1:
begin
/* %24 = zext i1 %23 to i64 ; <i64> [#uses=1]*/
var24 = var23;
/* br label %shift64RightJamming.exit*/
z_0_i = var24; /* for PHI node */
cur_state = shift64RightJamming_exit;
end
shift64RightJamming_exit:
begin
/* %z.0.i = phi i64 [ %22, %bb2.i_5 ], [ %24, %bb4.i_1 ], [ %zSig, %bb13_1 ] ; <i64> [#uses=3]*/
/* br label %shift64RightJamming.exit_1*/
cur_state = shift64RightJamming_exit_1;
end
shift64RightJamming_exit_1:
begin
/* %25 = trunc i64 %z.0.i to i32 ; <i32> [#uses=1]*/
var25 = z_0_i[31:0];
/* br label %shift64RightJamming.exit_2*/
cur_state = shift64RightJamming_exit_2;
end
shift64RightJamming_exit_2:
begin
/* %26 = and i32 %25, 1023 ; <i32> [#uses=3]*/
var26 = var25 & 32'd1023;
/* br label %shift64RightJamming.exit_3*/
cur_state = shift64RightJamming_exit_3;
end
shift64RightJamming_exit_3:
begin
/* %27 = icmp eq i32 %26, 0 ; <i1> [#uses=1]*/
var27 = var26 == 32'd0;
/* br label %shift64RightJamming.exit_4*/
cur_state = shift64RightJamming_exit_4;
end
shift64RightJamming_exit_4:
begin
/* br i1 %27, label %bb17, label %bb16*/
if (var27) begin
zSig_addr_0 = z_0_i; /* for PHI node */
roundBits_0 = var26; /* for PHI node */
zExp_addr_0 = 32'd0; /* for PHI node */
cur_state = bb17;
end
else begin
cur_state = bb16;
end
end
bb16:
begin
/* %28 = load i32* @float_exception_flags, align 4 ; <i32> [#uses=1]*/
/* br label %bb16_1*/
cur_state = bb16_1;
end
bb16_1:
begin
var28 = memory_controller_out[31:0];
/* %load_noop1 = add i32 %28, 0 ; <i32> [#uses=1]*/
load_noop1 = var28 + 32'd0;
/* br label %bb16_2*/
cur_state = bb16_2;
end
bb16_2:
begin
/* %29 = or i32 %load_noop1, 4 ; <i32> [#uses=1]*/
var29 = load_noop1 | 32'd4;
/* br label %bb16_3*/
cur_state = bb16_3;
end
bb16_3:
begin
/* store i32 %29, i32* @float_exception_flags, align 4*/
/* br label %bb17*/
zSig_addr_0 = z_0_i; /* for PHI node */
roundBits_0 = var26; /* for PHI node */
zExp_addr_0 = 32'd0; /* for PHI node */
cur_state = bb17;
end
bb17:
begin
/* %zSig_addr.0 = phi i64 [ %z.0.i, %shift64RightJamming.exit_4 ], [ %z.0.i, %bb16_3 ], [ %zSig, %bb12_1 ], [ %zSig, %bb7_2 ] ; <i64> [#uses=1]*/
/* %roundBits.0 = phi i32 [ %26, %shift64RightJamming.exit_4 ], [ %26, %bb16_3 ], [ %2, %bb12_1 ], [ %2, %bb7_2 ] ; <i32> [#uses=2]*/
/* %zExp_addr.0 = phi i32 [ 0, %shift64RightJamming.exit_4 ], [ 0, %bb16_3 ], [ %zExp, %bb12_1 ], [ %zExp, %bb7_2 ] ; <i32> [#uses=1]*/
/* br label %bb17_1*/
cur_state = bb17_1;
end
bb17_1:
begin
/* %30 = icmp eq i32 %roundBits.0, 0 ; <i1> [#uses=1]*/
var30 = roundBits_0 == 32'd0;
/* br label %bb17_2*/
cur_state = bb17_2;
end
bb17_2:
begin
/* br i1 %30, label %bb19, label %bb18*/
if (var30) begin
cur_state = bb19;
end
else begin
cur_state = bb18;
end
end
bb18:
begin
/* %31 = load i32* @float_exception_flags, align 4 ; <i32> [#uses=1]*/
/* br label %bb18_1*/
cur_state = bb18_1;
end
bb18_1:
begin
var31 = memory_controller_out[31:0];
/* %load_noop2 = add i32 %31, 0 ; <i32> [#uses=1]*/
load_noop2 = var31 + 32'd0;
/* br label %bb18_2*/
cur_state = bb18_2;
end
bb18_2:
begin
/* %32 = or i32 %load_noop2, 1 ; <i32> [#uses=1]*/
var32 = load_noop2 | 32'd1;
/* br label %bb18_3*/
cur_state = bb18_3;
end
bb18_3:
begin
/* store i32 %32, i32* @float_exception_flags, align 4*/
/* br label %bb19*/
cur_state = bb19;
end
bb19:
begin
/* %33 = add i64 %zSig_addr.0, 512 ; <i64> [#uses=1]*/
var33 = zSig_addr_0 + 64'd512;
/* %34 = icmp eq i32 %roundBits.0, 512 ; <i1> [#uses=1]*/
var34 = roundBits_0 == 32'd512;
/* %35 = zext i32 %zSign to i64 ; <i64> [#uses=1]*/
var35 = zSign;
/* %36 = zext i32 %zExp_addr.0 to i64 ; <i64> [#uses=1]*/
var36 = zExp_addr_0;
/* br label %bb19_1*/
cur_state = bb19_1;
end
bb19_1:
begin
/* %37 = lshr i64 %33, 10 ; <i64> [#uses=1]*/
var37 = var33 >>> (64'd10 % 64);
/* %38 = zext i1 %34 to i32 ; <i32> [#uses=1]*/
var38 = var34;
/* %39 = shl i64 %35, 63 ; <i64> [#uses=1]*/
var39 = var35 <<< (64'd63 % 64);
/* %.op = shl i64 %36, 52 ; <i64> [#uses=1]*/
_op = var36 <<< (64'd52 % 64);
/* br label %bb19_2*/
cur_state = bb19_2;
end
bb19_2:
begin
/* %not = xor i32 %38, -1 ; <i32> [#uses=1]*/
not_var40 = var38 ^ -32'd1;
/* br label %bb19_3*/
cur_state = bb19_3;
end
bb19_3:
begin
/* %40 = sext i32 %not to i64 ; <i64> [#uses=1]*/
var41 = $signed(not_var40);
/* br label %bb19_4*/
cur_state = bb19_4;
end
bb19_4:
begin
/* %41 = and i64 %40, %37 ; <i64> [#uses=2]*/
var42 = var41 & var37;
/* br label %bb19_5*/
cur_state = bb19_5;
end
bb19_5:
begin
/* %42 = icmp eq i64 %41, 0 ; <i1> [#uses=1]*/
var43 = var42 == 64'd0;
/* %43 = or i64 %41, %39 ; <i64> [#uses=1]*/
var44 = var42 | var39;
/* br label %bb19_6*/
cur_state = bb19_6;
end
bb19_6:
begin
/* %44 = select i1 %42, i64 0, i64 %.op ; <i64> [#uses=1]*/
var45 = (var43) ? 64'd0 : _op;
/* br label %bb19_7*/
cur_state = bb19_7;
end
bb19_7:
begin
/* %45 = add i64 %44, %43 ; <i64> [#uses=1]*/
var46 = var45 + var44;
/* br label %bb19_8*/
cur_state = bb19_8;
end
bb19_8:
begin
/* ret i64 %45*/
return_val = var46;
finish = 1;
cur_state = Wait;
end
endcase
always @(*)
begin
memory_controller_write_enable = 0;
memory_controller_address = 0;
memory_controller_in = 0;
case(cur_state)
default:
begin
// quartus issues a warning if we have no default case
end
bb11:
begin
memory_controller_address = {`TAG_float_exception_flags, 32'b0};
memory_controller_write_enable = 0;
end
bb11_3:
begin
memory_controller_address = {`TAG_float_exception_flags, 32'b0};
memory_controller_write_enable = 1;
memory_controller_in = var11;
end
bb16:
begin
memory_controller_address = {`TAG_float_exception_flags, 32'b0};
memory_controller_write_enable = 0;
end
bb16_3:
begin
memory_controller_address = {`TAG_float_exception_flags, 32'b0};
memory_controller_write_enable = 1;
memory_controller_in = var29;
end
bb18:
begin
memory_controller_address = {`TAG_float_exception_flags, 32'b0};
memory_controller_write_enable = 0;
end
bb18_3:
begin
memory_controller_address = {`TAG_float_exception_flags, 32'b0};
memory_controller_write_enable = 1;
memory_controller_in = var32;
end
endcase
end
endmodule
`timescale 1 ns / 1 ns
module float64_mul
(
clk,
reset,
start,
finish,
return_val,
a,
b,
memory_controller_write_enable,
memory_controller_address,
memory_controller_in,
memory_controller_out
);
output reg [63:0] return_val;
input clk;
input reset;
input start;
output reg finish;
input [63:0] a;
input [63:0] b;
output reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] memory_controller_address;
output reg memory_controller_write_enable;
output reg [`MEMORY_CONTROLLER_DATA_SIZE-1:0] memory_controller_in;
input wire [`MEMORY_CONTROLLER_DATA_SIZE-1:0] memory_controller_out;
reg roundAndPackFloat64_start;
wire roundAndPackFloat64_finish;
wire [63:0] roundAndPackFloat64_return_val;
wire [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] roundAndPackFloat64_memory_controller_address;
wire roundAndPackFloat64_memory_controller_write_enable;
wire [`MEMORY_CONTROLLER_DATA_SIZE-1:0] roundAndPackFloat64_memory_controller_in;
reg [`MEMORY_CONTROLLER_DATA_SIZE-1:0] roundAndPackFloat64_memory_controller_out;
reg [31:0] roundAndPackFloat64_zSign;
reg [31:0] roundAndPackFloat64_zExp;
reg [63:0] roundAndPackFloat64_zSig;
roundAndPackFloat64 roundAndPackFloat64_inst(
.clk( clk ),
.reset( reset ),
.start( roundAndPackFloat64_start ),
.finish( roundAndPackFloat64_finish ),
.return_val( roundAndPackFloat64_return_val ),
.memory_controller_address( roundAndPackFloat64_memory_controller_address ),
.memory_controller_write_enable( roundAndPackFloat64_memory_controller_write_enable ),
.memory_controller_in( roundAndPackFloat64_memory_controller_in ),
.memory_controller_out( roundAndPackFloat64_memory_controller_out ),
.zSign( roundAndPackFloat64_zSign ),
.zExp( roundAndPackFloat64_zExp ),
.zSig( roundAndPackFloat64_zSig )
);
reg [7:0] cur_state;
parameter Wait = 8'd0;
parameter entry = 8'd1;
parameter entry_1 = 8'd2;
parameter entry_2 = 8'd3;
parameter entry_3 = 8'd4;
parameter entry_4 = 8'd5;
parameter bb = 8'd6;
parameter bb_1 = 8'd7;
parameter bb1 = 8'd8;
parameter bb1_1 = 8'd9;
parameter bb1_2 = 8'd10;
parameter bb4 = 8'd11;
parameter bb4_1 = 8'd12;
parameter bb4_2 = 8'd13;
parameter bb_i14_i42 = 8'd14;
parameter bb_i14_i42_1 = 8'd15;
parameter bb_i14_i42_2 = 8'd16;
parameter float64_is_signaling_nan_exit16_i43 = 8'd17;
parameter float64_is_signaling_nan_exit16_i43_1 = 8'd18;
parameter float64_is_signaling_nan_exit16_i43_2 = 8'd19;
parameter bb_i_i46 = 8'd20;
parameter bb_i_i46_1 = 8'd21;
parameter bb_i_i46_2 = 8'd22;
parameter float64_is_signaling_nan_exit_i47 = 8'd23;
parameter float64_is_signaling_nan_exit_i47_1 = 8'd24;
parameter float64_is_signaling_nan_exit_i47_2 = 8'd25;
parameter float64_is_signaling_nan_exit_i47_3 = 8'd26;
parameter bb_i48 = 8'd27;
parameter bb_i48_1 = 8'd28;
parameter bb_i48_2 = 8'd29;
parameter bb_i48_3 = 8'd30;
parameter bb1_i49 = 8'd31;
parameter bb1_i49_1 = 8'd32;
parameter bb2_i50 = 8'd33;
parameter bb2_i50_1 = 8'd34;
parameter bb3_i52 = 8'd35;
parameter bb3_i52_1 = 8'd36;
parameter propagateFloat64NaN_exit55 = 8'd37;
parameter propagateFloat64NaN_exit55_1 = 8'd38;
parameter bb5 = 8'd39;
parameter bb5_1 = 8'd40;
parameter bb5_2 = 8'd41;
parameter bb5_3 = 8'd42;
parameter bb6 = 8'd43;
parameter bb6_1 = 8'd44;
parameter bb6_2 = 8'd45;
parameter bb6_3 = 8'd46;
parameter bb7 = 8'd47;
parameter bb7_1 = 8'd48;
parameter bb7_2 = 8'd49;
parameter bb8 = 8'd50;
parameter bb8_1 = 8'd51;
parameter bb9 = 8'd52;
parameter bb9_1 = 8'd53;
parameter bb10 = 8'd54;
parameter bb10_1 = 8'd55;
parameter bb10_2 = 8'd56;
parameter bb_i14_i = 8'd57;
parameter bb_i14_i_1 = 8'd58;
parameter bb_i14_i_2 = 8'd59;
parameter float64_is_signaling_nan_exit16_i = 8'd60;
parameter float64_is_signaling_nan_exit16_i_1 = 8'd61;
parameter float64_is_signaling_nan_exit16_i_2 = 8'd62;
parameter bb_i_i39 = 8'd63;
parameter bb_i_i39_1 = 8'd64;
parameter bb_i_i39_2 = 8'd65;
parameter float64_is_signaling_nan_exit_i = 8'd66;
parameter float64_is_signaling_nan_exit_i_1 = 8'd67;
parameter float64_is_signaling_nan_exit_i_2 = 8'd68;
parameter float64_is_signaling_nan_exit_i_3 = 8'd69;
parameter bb_i = 8'd70;
parameter bb_i_1 = 8'd71;
parameter bb_i_2 = 8'd72;
parameter bb_i_3 = 8'd73;
parameter bb1_i = 8'd74;
parameter bb1_i_1 = 8'd75;
parameter bb2_i = 8'd76;
parameter bb2_i_1 = 8'd77;
parameter bb3_i = 8'd78;
parameter bb3_i_1 = 8'd79;
parameter propagateFloat64NaN_exit = 8'd80;
parameter propagateFloat64NaN_exit_1 = 8'd81;
parameter bb11 = 8'd82;
parameter bb11_1 = 8'd83;
parameter bb11_2 = 8'd84;
parameter bb11_3 = 8'd85;
parameter bb12 = 8'd86;
parameter bb12_1 = 8'd87;
parameter bb12_2 = 8'd88;
parameter bb12_3 = 8'd89;
parameter bb13 = 8'd90;
parameter bb13_1 = 8'd91;
parameter bb13_2 = 8'd92;
parameter bb14 = 8'd93;
parameter bb14_1 = 8'd94;
parameter bb15 = 8'd95;
parameter bb15_1 = 8'd96;
parameter bb16 = 8'd97;
parameter bb16_1 = 8'd98;
parameter bb17 = 8'd99;
parameter bb17_1 = 8'd100;
parameter bb_i_i28 = 8'd101;
parameter bb1_i_i30 = 8'd102;
parameter bb1_i_i30_1 = 8'd103;
parameter normalizeFloat64Subnormal_exit38 = 8'd104;
parameter normalizeFloat64Subnormal_exit38_1 = 8'd105;
parameter normalizeFloat64Subnormal_exit38_2 = 8'd106;
parameter normalizeFloat64Subnormal_exit38_3 = 8'd107;
parameter normalizeFloat64Subnormal_exit38_4 = 8'd108;
parameter normalizeFloat64Subnormal_exit38_5 = 8'd109;
parameter normalizeFloat64Subnormal_exit38_6 = 8'd110;
parameter normalizeFloat64Subnormal_exit38_7 = 8'd111;
parameter normalizeFloat64Subnormal_exit38_8 = 8'd112;
parameter normalizeFloat64Subnormal_exit38_9 = 8'd113;
parameter normalizeFloat64Subnormal_exit38_10 = 8'd114;
parameter normalizeFloat64Subnormal_exit38_11 = 8'd115;
parameter normalizeFloat64Subnormal_exit38_12 = 8'd116;
parameter normalizeFloat64Subnormal_exit38_13 = 8'd117;
parameter bb18 = 8'd118;
parameter bb18_1 = 8'd119;
parameter bb19 = 8'd120;
parameter bb19_1 = 8'd121;
parameter bb20 = 8'd122;
parameter bb20_1 = 8'd123;
parameter bb21 = 8'd124;
parameter bb21_1 = 8'd125;
parameter bb_i_i = 8'd126;
parameter bb1_i_i = 8'd127;
parameter bb1_i_i_1 = 8'd128;
parameter normalizeFloat64Subnormal_exit = 8'd129;
parameter normalizeFloat64Subnormal_exit_1 = 8'd130;
parameter normalizeFloat64Subnormal_exit_2 = 8'd131;
parameter normalizeFloat64Subnormal_exit_3 = 8'd132;
parameter normalizeFloat64Subnormal_exit_4 = 8'd133;
parameter normalizeFloat64Subnormal_exit_5 = 8'd134;
parameter normalizeFloat64Subnormal_exit_6 = 8'd135;
parameter normalizeFloat64Subnormal_exit_7 = 8'd136;
parameter normalizeFloat64Subnormal_exit_8 = 8'd137;
parameter normalizeFloat64Subnormal_exit_9 = 8'd138;
parameter normalizeFloat64Subnormal_exit_10 = 8'd139;
parameter normalizeFloat64Subnormal_exit_11 = 8'd140;
parameter normalizeFloat64Subnormal_exit_12 = 8'd141;
parameter normalizeFloat64Subnormal_exit_13 = 8'd142;
parameter bb22 = 8'd143;
parameter bb22_1 = 8'd144;
parameter bb22_2 = 8'd145;
parameter bb22_3 = 8'd146;
parameter bb22_4 = 8'd147;
parameter bb22_5 = 8'd148;
parameter bb22_6 = 8'd149;
parameter bb22_7 = 8'd150;
parameter bb22_8 = 8'd151;
parameter bb22_9 = 8'd152;
parameter bb22_10 = 8'd153;
parameter bb22_11 = 8'd154;
parameter bb22_12 = 8'd155;
parameter bb22_13 = 8'd156;
parameter bb22_14 = 8'd157;
parameter bb22_15 = 8'd158;
parameter bb22_15_call_0 = 8'd159;
parameter bb22_15_call_1 = 8'd160;
parameter bb22_16 = 8'd161;
reg [31:0] var5;
reg var50;
reg [63:0] var49;
reg var51;
reg [63:0] var53;
reg not__i_i;
reg [31:0] retval_i_i;
reg [31:0] var52;
reg [63:0] var54;
reg [63:0] var55;
reg [31:0] var56;
reg var57;
reg [31:0] var58;
reg [31:0] var59;
reg var60;
reg var62;
reg [63:0] iftmp_34_0_i;
reg [63:0] var61;
reg [63:0] var63;
reg [31:0] shiftCount_0_i_i_i;
reg var95;
reg [31:0] var96;
reg [31:0] var97;
reg [31:0] shiftCount_1_i_i_i;
reg [31:0] a_addr_1_i_i_i;
reg [31:0] var98;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] var99;
reg [31:0] var100;
reg [31:0] var101;
reg [31:0] var102;
reg [31:0] var103;
reg [63:0] _cast_i;
reg [63:0] var105;
reg [31:0] var104;
reg [63:0] var119;
reg [63:0] var118;
reg [63:0] var120;
reg [63:0] var121;
reg var122;
reg [63:0] iftmp_17_0_i;
reg [63:0] var123;
reg [63:0] var126;
reg [63:0] var124;
reg [63:0] var125;
reg var127;
reg [63:0] var129;
reg [63:0] var130;
reg [63:0] var132;
reg var128;
reg [63:0] var131;
reg [63:0] var133;
reg [63:0] _mask;
reg var134;
reg [63:0] _mask_lobit;
reg [63:0] tmp;
reg [63:0] zSig0_0;
reg [31:0] zExp_0_v;
reg [31:0] var112;
reg [31:0] zExp_0;
reg [31:0] var38;
reg [31:0] var39;
reg [63:0] var40;
reg [63:0] var41;
reg [63:0] var0;
reg [63:0] var1;
reg [31:0] var8;
reg [63:0] var2;
reg [63:0] var3;
reg [31:0] var6;
reg [31:0] var9;
reg [63:0] var4;
reg [63:0] var7;
reg [31:0] var10;
reg var11;
reg var12;
reg var13;
reg var14;
reg var15;
reg [63:0] var16;
reg var17;
reg [63:0] var19;
reg not__i12_i40;
reg [31:0] retval_i13_i41;
reg [31:0] var18;
reg [63:0] var20;
reg var22;
reg [63:0] var21;
reg var23;
reg [63:0] var25;
reg not__i_i44;
reg [31:0] retval_i_i45;
reg [31:0] var24;
reg [63:0] var26;
reg [63:0] var27;
reg [31:0] var28;
reg var29;
reg [31:0] var30;
reg [31:0] var31;
reg var32;
reg var34;
reg [63:0] iftmp_34_0_i51;
reg [63:0] var33;
reg [63:0] var35;
reg [63:0] var36;
reg var37;
reg [31:0] bExp_0;
reg [63:0] bSig_0;
reg [63:0] var106;
reg [63:0] var108;
reg [63:0] var107;
reg [63:0] var109;
reg [63:0] var113;
reg [63:0] var110;
reg [63:0] var114;
reg [63:0] var116;
reg [63:0] var111;
reg [63:0] var115;
reg [63:0] var117;
reg var42;
reg var43;
reg [63:0] var44;
reg var45;
reg [63:0] var47;
reg not__i12_i;
reg [31:0] retval_i13_i;
reg [31:0] var46;
reg [63:0] var48;
reg [63:0] var64;
reg var65;
reg [31:0] var66;
reg [31:0] var67;
reg [63:0] var68;
reg [63:0] var69;
reg var70;
reg var71;
reg [63:0] var72;
reg var73;
reg [31:0] extract_t_i_i27;
reg [63:0] var74;
reg [31:0] extract_t4_i_i29;
reg [31:0] shiftCount_0_i_i31;
reg [31:0] a_addr_0_off0_i_i32;
reg [31:0] var75;
reg var76;
reg [31:0] _a_i_i_i33;
reg [31:0] shiftCount_0_i_i_i34;
reg var77;
reg [31:0] var78;
reg [31:0] var79;
reg [31:0] shiftCount_1_i_i_i35;
reg [31:0] a_addr_1_i_i_i36;
reg [31:0] var80;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] var81;
reg [31:0] var82;
reg [31:0] var83;
reg [31:0] var84;
reg [31:0] var85;
reg [63:0] _cast_i37;
reg [63:0] var87;
reg [31:0] var86;
reg [63:0] aSig_0;
reg [31:0] aExp_0;
reg var88;
reg var89;
reg [63:0] var90;
reg var91;
reg [31:0] extract_t_i_i;
reg [63:0] var92;
reg [31:0] extract_t4_i_i;
reg [31:0] shiftCount_0_i_i;
reg [31:0] a_addr_0_off0_i_i;
reg [31:0] var93;
reg var94;
reg [31:0] _a_i_i_i;
reg [63:0] var135;
reg [31:0] load_noop1;
reg [31:0] load_noop;
reg [31:0] load_noop2;
reg [31:0] load_noop3;
reg [31:0] load_noop4;
reg [31:0] load_noop5;
always @(posedge clk)
if (reset)
cur_state = Wait;
else
case(cur_state)
Wait:
begin
finish = 0;
if (start == 1)
cur_state = entry;
else
cur_state = Wait;
end
entry:
begin
/* %0 = and i64 %a, 4503599627370495 ; <i64> [#uses=7]*/
var0 = a & 64'd4503599627370495;
/* %1 = lshr i64 %a, 52 ; <i64> [#uses=1]*/
var1 = a >>> (64'd52 % 64);
/* %2 = and i64 %b, 4503599627370495 ; <i64> [#uses=8]*/
var2 = b & 64'd4503599627370495;
/* %3 = lshr i64 %b, 52 ; <i64> [#uses=1]*/
var3 = b >>> (64'd52 % 64);
/* %4 = xor i64 %b, %a ; <i64> [#uses=5]*/
var4 = b ^ a;
/* br label %entry_1*/
cur_state = entry_1;
end
entry_1:
begin
/* %5 = trunc i64 %1 to i32 ; <i32> [#uses=1]*/
var5 = var1[31:0];
/* %6 = trunc i64 %3 to i32 ; <i32> [#uses=1]*/
var6 = var3[31:0];
/* %7 = lshr i64 %4, 63 ; <i64> [#uses=1]*/
var7 = var4 >>> (64'd63 % 64);
/* br label %entry_2*/
cur_state = entry_2;
end
entry_2:
begin
/* %8 = and i32 %5, 2047 ; <i32> [#uses=4]*/
var8 = var5 & 32'd2047;
/* %9 = and i32 %6, 2047 ; <i32> [#uses=5]*/
var9 = var6 & 32'd2047;
/* %10 = trunc i64 %7 to i32 ; <i32> [#uses=1]*/
var10 = var7[31:0];
/* br label %entry_3*/
cur_state = entry_3;
end
entry_3:
begin
/* %11 = icmp eq i32 %8, 2047 ; <i1> [#uses=1]*/
var11 = var8 == 32'd2047;
/* br label %entry_4*/
cur_state = entry_4;
end
entry_4:
begin
/* br i1 %11, label %bb, label %bb8*/
if (var11) begin
cur_state = bb;
end
else begin
cur_state = bb8;
end
end
bb:
begin
/* %12 = icmp eq i64 %0, 0 ; <i1> [#uses=1]*/
var12 = var0 == 64'd0;
/* br label %bb_1*/
cur_state = bb_1;
end
bb_1:
begin
/* br i1 %12, label %bb1, label %bb4*/
if (var12) begin
cur_state = bb1;
end
else begin
cur_state = bb4;
end
end
bb1:
begin
/* %13 = icmp eq i32 %9, 2047 ; <i1> [#uses=1]*/
var13 = var9 == 32'd2047;
/* %14 = icmp ne i64 %2, 0 ; <i1> [#uses=1]*/
var14 = var2 != 64'd0;
/* br label %bb1_1*/
cur_state = bb1_1;
end
bb1_1:
begin
/* %15 = and i1 %13, %14 ; <i1> [#uses=1]*/
var15 = var13 & var14;
/* br label %bb1_2*/
cur_state = bb1_2;
end
bb1_2:
begin
/* br i1 %15, label %bb4, label %bb5*/
if (var15) begin
cur_state = bb4;
end
else begin
cur_state = bb5;
end
end
bb4:
begin
/* %16 = and i64 %a, 9221120237041090560 ; <i64> [#uses=1]*/
var16 = a & 64'd9221120237041090560;
/* br label %bb4_1*/
cur_state = bb4_1;
end
bb4_1:
begin
/* %17 = icmp eq i64 %16, 9218868437227405312 ; <i1> [#uses=1]*/
var17 = var16 == 64'd9218868437227405312;
/* br label %bb4_2*/
cur_state = bb4_2;
end
bb4_2:
begin
/* br i1 %17, label %bb.i14.i42, label %float64_is_signaling_nan.exit16.i43*/
if (var17) begin
cur_state = bb_i14_i42;
end
else begin
var18 = 32'd0; /* for PHI node */
cur_state = float64_is_signaling_nan_exit16_i43;
end
end
bb_i14_i42:
begin
/* %18 = and i64 %a, 2251799813685247 ; <i64> [#uses=1]*/
var19 = a & 64'd2251799813685247;
/* br label %bb.i14.i42_1*/
cur_state = bb_i14_i42_1;
end
bb_i14_i42_1:
begin
/* %not..i12.i40 = icmp ne i64 %18, 0 ; <i1> [#uses=1]*/
not__i12_i40 = var19 != 64'd0;
/* br label %bb.i14.i42_2*/
cur_state = bb_i14_i42_2;
end
bb_i14_i42_2:
begin
/* %retval.i13.i41 = zext i1 %not..i12.i40 to i32 ; <i32> [#uses=1]*/
retval_i13_i41 = not__i12_i40;
/* br label %float64_is_signaling_nan.exit16.i43*/
var18 = retval_i13_i41; /* for PHI node */
cur_state = float64_is_signaling_nan_exit16_i43;
end
float64_is_signaling_nan_exit16_i43:
begin
/* %19 = phi i32 [ %retval.i13.i41, %bb.i14.i42_2 ], [ 0, %bb4_2 ] ; <i32> [#uses=2]*/
/* %20 = shl i64 %b, 1 ; <i64> [#uses=1]*/
var20 = b <<< (64'd1 % 64);
/* %21 = and i64 %b, 9221120237041090560 ; <i64> [#uses=1]*/
var21 = b & 64'd9221120237041090560;
/* br label %float64_is_signaling_nan.exit16.i43_1*/
cur_state = float64_is_signaling_nan_exit16_i43_1;
end
float64_is_signaling_nan_exit16_i43_1:
begin
/* %22 = icmp ugt i64 %20, -9007199254740992 ; <i1> [#uses=1]*/
var22 = var20 > -64'd9007199254740992;
/* %23 = icmp eq i64 %21, 9218868437227405312 ; <i1> [#uses=1]*/
var23 = var21 == 64'd9218868437227405312;
/* br label %float64_is_signaling_nan.exit16.i43_2*/
cur_state = float64_is_signaling_nan_exit16_i43_2;
end
float64_is_signaling_nan_exit16_i43_2:
begin
/* br i1 %23, label %bb.i.i46, label %float64_is_signaling_nan.exit.i47*/
if (var23) begin
cur_state = bb_i_i46;
end
else begin
var24 = 32'd0; /* for PHI node */
cur_state = float64_is_signaling_nan_exit_i47;
end
end
bb_i_i46:
begin
/* %24 = and i64 %b, 2251799813685247 ; <i64> [#uses=1]*/
var25 = b & 64'd2251799813685247;
/* br label %bb.i.i46_1*/
cur_state = bb_i_i46_1;
end
bb_i_i46_1:
begin
/* %not..i.i44 = icmp ne i64 %24, 0 ; <i1> [#uses=1]*/
not__i_i44 = var25 != 64'd0;
/* br label %bb.i.i46_2*/
cur_state = bb_i_i46_2;
end
bb_i_i46_2:
begin
/* %retval.i.i45 = zext i1 %not..i.i44 to i32 ; <i32> [#uses=1]*/
retval_i_i45 = not__i_i44;
/* br label %float64_is_signaling_nan.exit.i47*/
var24 = retval_i_i45; /* for PHI node */
cur_state = float64_is_signaling_nan_exit_i47;
end
float64_is_signaling_nan_exit_i47:
begin
/* %25 = phi i32 [ %retval.i.i45, %bb.i.i46_2 ], [ 0, %float64_is_signaling_nan.exit16.i43_2 ] ; <i32> [#uses=2]*/
/* %26 = or i64 %a, 2251799813685248 ; <i64> [#uses=2]*/
var26 = a | 64'd2251799813685248;
/* %27 = or i64 %b, 2251799813685248 ; <i64> [#uses=2]*/
var27 = b | 64'd2251799813685248;
/* br label %float64_is_signaling_nan.exit.i47_1*/
cur_state = float64_is_signaling_nan_exit_i47_1;
end
float64_is_signaling_nan_exit_i47_1:
begin
/* %28 = or i32 %25, %19 ; <i32> [#uses=1]*/
var28 = var24 | var18;
/* br label %float64_is_signaling_nan.exit.i47_2*/
cur_state = float64_is_signaling_nan_exit_i47_2;
end
float64_is_signaling_nan_exit_i47_2:
begin
/* %29 = icmp eq i32 %28, 0 ; <i1> [#uses=1]*/
var29 = var28 == 32'd0;
/* br label %float64_is_signaling_nan.exit.i47_3*/
cur_state = float64_is_signaling_nan_exit_i47_3;
end
float64_is_signaling_nan_exit_i47_3:
begin
/* br i1 %29, label %bb1.i49, label %bb.i48*/
if (var29) begin
cur_state = bb1_i49;
end
else begin
cur_state = bb_i48;
end
end
bb_i48:
begin
/* %30 = load i32* @float_exception_flags, align 4 ; <i32> [#uses=1]*/
/* br label %bb.i48_1*/
cur_state = bb_i48_1;
end
bb_i48_1:
begin
var30 = memory_controller_out[31:0];
/* %load_noop = add i32 %30, 0 ; <i32> [#uses=1]*/
load_noop = var30 + 32'd0;
/* br label %bb.i48_2*/
cur_state = bb_i48_2;
end
bb_i48_2:
begin
/* %31 = or i32 %load_noop, 16 ; <i32> [#uses=1]*/
var31 = load_noop | 32'd16;
/* br label %bb.i48_3*/
cur_state = bb_i48_3;
end
bb_i48_3:
begin
/* store i32 %31, i32* @float_exception_flags, align 4*/
/* br label %bb1.i49*/
cur_state = bb1_i49;
end
bb1_i49:
begin
/* %32 = icmp eq i32 %25, 0 ; <i1> [#uses=1]*/
var32 = var24 == 32'd0;
/* br label %bb1.i49_1*/
cur_state = bb1_i49_1;
end
bb1_i49_1:
begin
/* br i1 %32, label %bb2.i50, label %propagateFloat64NaN.exit55*/
if (var32) begin
cur_state = bb2_i50;
end
else begin
var33 = var27; /* for PHI node */
cur_state = propagateFloat64NaN_exit55;
end
end
bb2_i50:
begin
/* %33 = icmp eq i32 %19, 0 ; <i1> [#uses=1]*/
var34 = var18 == 32'd0;
/* br label %bb2.i50_1*/
cur_state = bb2_i50_1;
end
bb2_i50_1:
begin
/* br i1 %33, label %bb3.i52, label %propagateFloat64NaN.exit55*/
if (var34) begin
cur_state = bb3_i52;
end
else begin
var33 = var26; /* for PHI node */
cur_state = propagateFloat64NaN_exit55;
end
end
bb3_i52:
begin
/* %iftmp.34.0.i51 = select i1 %22, i64 %27, i64 %26 ; <i64> [#uses=1]*/
iftmp_34_0_i51 = (var22) ? var27 : var26;
/* br label %bb3.i52_1*/
cur_state = bb3_i52_1;
end
bb3_i52_1:
begin
/* ret i64 %iftmp.34.0.i51*/
return_val = iftmp_34_0_i51;
finish = 1;
cur_state = Wait;
end
propagateFloat64NaN_exit55:
begin
/* %34 = phi i64 [ %26, %bb2.i50_1 ], [ %27, %bb1.i49_1 ] ; <i64> [#uses=1]*/
/* br label %propagateFloat64NaN.exit55_1*/
cur_state = propagateFloat64NaN_exit55_1;
end
propagateFloat64NaN_exit55_1:
begin
/* ret i64 %34*/
return_val = var33;
finish = 1;
cur_state = Wait;
end
bb5:
begin
/* %35 = zext i32 %9 to i64 ; <i64> [#uses=1]*/
var35 = var9;
/* br label %bb5_1*/
cur_state = bb5_1;
end
bb5_1:
begin
/* %36 = or i64 %35, %2 ; <i64> [#uses=1]*/
var36 = var35 | var2;
/* br label %bb5_2*/
cur_state = bb5_2;
end
bb5_2:
begin
/* %37 = icmp eq i64 %36, 0 ; <i1> [#uses=1]*/
var37 = var36 == 64'd0;
/* br label %bb5_3*/
cur_state = bb5_3;
end
bb5_3:
begin
/* br i1 %37, label %bb6, label %bb7*/
if (var37) begin
cur_state = bb6;
end
else begin
cur_state = bb7;
end
end
bb6:
begin
/* %38 = load i32* @float_exception_flags, align 4 ; <i32> [#uses=1]*/
/* br label %bb6_1*/
cur_state = bb6_1;
end
bb6_1:
begin
var38 = memory_controller_out[31:0];
/* %load_noop1 = add i32 %38, 0 ; <i32> [#uses=1]*/
load_noop1 = var38 + 32'd0;
/* br label %bb6_2*/
cur_state = bb6_2;
end
bb6_2:
begin
/* %39 = or i32 %load_noop1, 16 ; <i32> [#uses=1]*/
var39 = load_noop1 | 32'd16;
/* br label %bb6_3*/
cur_state = bb6_3;
end
bb6_3:
begin
/* store i32 %39, i32* @float_exception_flags, align 4*/
/* ret i64 9223372036854775807*/
return_val = 64'd9223372036854775807;
finish = 1;
cur_state = Wait;
end
bb7:
begin
/* %40 = or i64 %4, 9218868437227405312 ; <i64> [#uses=1]*/
var40 = var4 | 64'd9218868437227405312;
/* br label %bb7_1*/
cur_state = bb7_1;
end
bb7_1:
begin
/* %41 = and i64 %40, -4503599627370496 ; <i64> [#uses=1]*/
var41 = var40 & -64'd4503599627370496;
/* br label %bb7_2*/
cur_state = bb7_2;
end
bb7_2:
begin
/* ret i64 %41*/
return_val = var41;
finish = 1;
cur_state = Wait;
end
bb8:
begin
/* %42 = icmp eq i32 %9, 2047 ; <i1> [#uses=1]*/
var42 = var9 == 32'd2047;
/* br label %bb8_1*/
cur_state = bb8_1;
end
bb8_1:
begin
/* br i1 %42, label %bb9, label %bb14*/
if (var42) begin
cur_state = bb9;
end
else begin
cur_state = bb14;
end
end
bb9:
begin
/* %43 = icmp eq i64 %2, 0 ; <i1> [#uses=1]*/
var43 = var2 == 64'd0;
/* br label %bb9_1*/
cur_state = bb9_1;
end
bb9_1:
begin
/* br i1 %43, label %bb11, label %bb10*/
if (var43) begin
cur_state = bb11;
end
else begin
cur_state = bb10;
end
end
bb10:
begin
/* %44 = and i64 %a, 9221120237041090560 ; <i64> [#uses=1]*/
var44 = a & 64'd9221120237041090560;
/* br label %bb10_1*/
cur_state = bb10_1;
end
bb10_1:
begin
/* %45 = icmp eq i64 %44, 9218868437227405312 ; <i1> [#uses=1]*/
var45 = var44 == 64'd9218868437227405312;
/* br label %bb10_2*/
cur_state = bb10_2;
end
bb10_2:
begin
/* br i1 %45, label %bb.i14.i, label %float64_is_signaling_nan.exit16.i*/
if (var45) begin
cur_state = bb_i14_i;
end
else begin
var46 = 32'd0; /* for PHI node */
cur_state = float64_is_signaling_nan_exit16_i;
end
end
bb_i14_i:
begin
/* %46 = and i64 %a, 2251799813685247 ; <i64> [#uses=1]*/
var47 = a & 64'd2251799813685247;
/* br label %bb.i14.i_1*/
cur_state = bb_i14_i_1;
end
bb_i14_i_1:
begin
/* %not..i12.i = icmp ne i64 %46, 0 ; <i1> [#uses=1]*/
not__i12_i = var47 != 64'd0;
/* br label %bb.i14.i_2*/
cur_state = bb_i14_i_2;
end
bb_i14_i_2:
begin
/* %retval.i13.i = zext i1 %not..i12.i to i32 ; <i32> [#uses=1]*/
retval_i13_i = not__i12_i;
/* br label %float64_is_signaling_nan.exit16.i*/
var46 = retval_i13_i; /* for PHI node */
cur_state = float64_is_signaling_nan_exit16_i;
end
float64_is_signaling_nan_exit16_i:
begin
/* %47 = phi i32 [ %retval.i13.i, %bb.i14.i_2 ], [ 0, %bb10_2 ] ; <i32> [#uses=2]*/
/* %48 = shl i64 %b, 1 ; <i64> [#uses=1]*/
var48 = b <<< (64'd1 % 64);
/* %49 = and i64 %b, 9221120237041090560 ; <i64> [#uses=1]*/
var49 = b & 64'd9221120237041090560;
/* br label %float64_is_signaling_nan.exit16.i_1*/
cur_state = float64_is_signaling_nan_exit16_i_1;
end
float64_is_signaling_nan_exit16_i_1:
begin
/* %50 = icmp ugt i64 %48, -9007199254740992 ; <i1> [#uses=1]*/
var50 = var48 > -64'd9007199254740992;
/* %51 = icmp eq i64 %49, 9218868437227405312 ; <i1> [#uses=1]*/
var51 = var49 == 64'd9218868437227405312;
/* br label %float64_is_signaling_nan.exit16.i_2*/
cur_state = float64_is_signaling_nan_exit16_i_2;
end
float64_is_signaling_nan_exit16_i_2:
begin
/* br i1 %51, label %bb.i.i39, label %float64_is_signaling_nan.exit.i*/
if (var51) begin
cur_state = bb_i_i39;
end
else begin
var52 = 32'd0; /* for PHI node */
cur_state = float64_is_signaling_nan_exit_i;
end
end
bb_i_i39:
begin
/* %52 = and i64 %b, 2251799813685247 ; <i64> [#uses=1]*/
var53 = b & 64'd2251799813685247;
/* br label %bb.i.i39_1*/
cur_state = bb_i_i39_1;
end
bb_i_i39_1:
begin
/* %not..i.i = icmp ne i64 %52, 0 ; <i1> [#uses=1]*/
not__i_i = var53 != 64'd0;
/* br label %bb.i.i39_2*/
cur_state = bb_i_i39_2;
end
bb_i_i39_2:
begin
/* %retval.i.i = zext i1 %not..i.i to i32 ; <i32> [#uses=1]*/
retval_i_i = not__i_i;
/* br label %float64_is_signaling_nan.exit.i*/
var52 = retval_i_i; /* for PHI node */
cur_state = float64_is_signaling_nan_exit_i;
end
float64_is_signaling_nan_exit_i:
begin
/* %53 = phi i32 [ %retval.i.i, %bb.i.i39_2 ], [ 0, %float64_is_signaling_nan.exit16.i_2 ] ; <i32> [#uses=2]*/
/* %54 = or i64 %a, 2251799813685248 ; <i64> [#uses=2]*/
var54 = a | 64'd2251799813685248;
/* %55 = or i64 %b, 2251799813685248 ; <i64> [#uses=2]*/
var55 = b | 64'd2251799813685248;
/* br label %float64_is_signaling_nan.exit.i_1*/
cur_state = float64_is_signaling_nan_exit_i_1;
end
float64_is_signaling_nan_exit_i_1:
begin
/* %56 = or i32 %53, %47 ; <i32> [#uses=1]*/
var56 = var52 | var46;
/* br label %float64_is_signaling_nan.exit.i_2*/
cur_state = float64_is_signaling_nan_exit_i_2;
end
float64_is_signaling_nan_exit_i_2:
begin
/* %57 = icmp eq i32 %56, 0 ; <i1> [#uses=1]*/
var57 = var56 == 32'd0;
/* br label %float64_is_signaling_nan.exit.i_3*/
cur_state = float64_is_signaling_nan_exit_i_3;
end
float64_is_signaling_nan_exit_i_3:
begin
/* br i1 %57, label %bb1.i, label %bb.i*/
if (var57) begin
cur_state = bb1_i;
end
else begin
cur_state = bb_i;
end
end
bb_i:
begin
/* %58 = load i32* @float_exception_flags, align 4 ; <i32> [#uses=1]*/
/* br label %bb.i_1*/
cur_state = bb_i_1;
end
bb_i_1:
begin
var58 = memory_controller_out[31:0];
/* %load_noop2 = add i32 %58, 0 ; <i32> [#uses=1]*/
load_noop2 = var58 + 32'd0;
/* br label %bb.i_2*/
cur_state = bb_i_2;
end
bb_i_2:
begin
/* %59 = or i32 %load_noop2, 16 ; <i32> [#uses=1]*/
var59 = load_noop2 | 32'd16;
/* br label %bb.i_3*/
cur_state = bb_i_3;
end
bb_i_3:
begin
/* store i32 %59, i32* @float_exception_flags, align 4*/
/* br label %bb1.i*/
cur_state = bb1_i;
end
bb1_i:
begin
/* %60 = icmp eq i32 %53, 0 ; <i1> [#uses=1]*/
var60 = var52 == 32'd0;
/* br label %bb1.i_1*/
cur_state = bb1_i_1;
end
bb1_i_1:
begin
/* br i1 %60, label %bb2.i, label %propagateFloat64NaN.exit*/
if (var60) begin
cur_state = bb2_i;
end
else begin
var61 = var55; /* for PHI node */
cur_state = propagateFloat64NaN_exit;
end
end
bb2_i:
begin
/* %61 = icmp eq i32 %47, 0 ; <i1> [#uses=1]*/
var62 = var46 == 32'd0;
/* br label %bb2.i_1*/
cur_state = bb2_i_1;
end
bb2_i_1:
begin
/* br i1 %61, label %bb3.i, label %propagateFloat64NaN.exit*/
if (var62) begin
cur_state = bb3_i;
end
else begin
var61 = var54; /* for PHI node */
cur_state = propagateFloat64NaN_exit;
end
end
bb3_i:
begin
/* %iftmp.34.0.i = select i1 %50, i64 %55, i64 %54 ; <i64> [#uses=1]*/
iftmp_34_0_i = (var50) ? var55 : var54;
/* br label %bb3.i_1*/
cur_state = bb3_i_1;
end
bb3_i_1:
begin
/* ret i64 %iftmp.34.0.i*/
return_val = iftmp_34_0_i;
finish = 1;
cur_state = Wait;
end
propagateFloat64NaN_exit:
begin
/* %62 = phi i64 [ %54, %bb2.i_1 ], [ %55, %bb1.i_1 ] ; <i64> [#uses=1]*/
/* br label %propagateFloat64NaN.exit_1*/
cur_state = propagateFloat64NaN_exit_1;
end
propagateFloat64NaN_exit_1:
begin
/* ret i64 %62*/
return_val = var61;
finish = 1;
cur_state = Wait;
end
bb11:
begin
/* %63 = zext i32 %8 to i64 ; <i64> [#uses=1]*/
var63 = var8;
/* br label %bb11_1*/
cur_state = bb11_1;
end
bb11_1:
begin
/* %64 = or i64 %63, %0 ; <i64> [#uses=1]*/
var64 = var63 | var0;
/* br label %bb11_2*/
cur_state = bb11_2;
end
bb11_2:
begin
/* %65 = icmp eq i64 %64, 0 ; <i1> [#uses=1]*/
var65 = var64 == 64'd0;
/* br label %bb11_3*/
cur_state = bb11_3;
end
bb11_3:
begin
/* br i1 %65, label %bb12, label %bb13*/
if (var65) begin
cur_state = bb12;
end
else begin
cur_state = bb13;
end
end
bb12:
begin
/* %66 = load i32* @float_exception_flags, align 4 ; <i32> [#uses=1]*/
/* br label %bb12_1*/
cur_state = bb12_1;
end
bb12_1:
begin
var66 = memory_controller_out[31:0];
/* %load_noop3 = add i32 %66, 0 ; <i32> [#uses=1]*/
load_noop3 = var66 + 32'd0;
/* br label %bb12_2*/
cur_state = bb12_2;
end
bb12_2:
begin
/* %67 = or i32 %load_noop3, 16 ; <i32> [#uses=1]*/
var67 = load_noop3 | 32'd16;
/* br label %bb12_3*/
cur_state = bb12_3;
end
bb12_3:
begin
/* store i32 %67, i32* @float_exception_flags, align 4*/
/* ret i64 9223372036854775807*/
return_val = 64'd9223372036854775807;
finish = 1;
cur_state = Wait;
end
bb13:
begin
/* %68 = or i64 %4, 9218868437227405312 ; <i64> [#uses=1]*/
var68 = var4 | 64'd9218868437227405312;
/* br label %bb13_1*/
cur_state = bb13_1;
end
bb13_1:
begin
/* %69 = and i64 %68, -4503599627370496 ; <i64> [#uses=1]*/
var69 = var68 & -64'd4503599627370496;
/* br label %bb13_2*/
cur_state = bb13_2;
end
bb13_2:
begin
/* ret i64 %69*/
return_val = var69;
finish = 1;
cur_state = Wait;
end
bb14:
begin
/* %70 = icmp eq i32 %8, 0 ; <i1> [#uses=1]*/
var70 = var8 == 32'd0;
/* br label %bb14_1*/
cur_state = bb14_1;
end
bb14_1:
begin
/* br i1 %70, label %bb15, label %bb18*/
if (var70) begin
cur_state = bb15;
end
else begin
aSig_0 = var0; /* for PHI node */
aExp_0 = var8; /* for PHI node */
cur_state = bb18;
end
end
bb15:
begin
/* %71 = icmp eq i64 %0, 0 ; <i1> [#uses=1]*/
var71 = var0 == 64'd0;
/* br label %bb15_1*/
cur_state = bb15_1;
end
bb15_1:
begin
/* br i1 %71, label %bb16, label %bb17*/
if (var71) begin
cur_state = bb16;
end
else begin
cur_state = bb17;
end
end
bb16:
begin
/* %72 = and i64 %4, -9223372036854775808 ; <i64> [#uses=1]*/
var72 = var4 & -64'd9223372036854775808;
/* br label %bb16_1*/
cur_state = bb16_1;
end
bb16_1:
begin
/* ret i64 %72*/
return_val = var72;
finish = 1;
cur_state = Wait;
end
bb17:
begin
/* %73 = icmp ult i64 %0, 4294967296 ; <i1> [#uses=1]*/
var73 = var0 < 64'd4294967296;
/* br label %bb17_1*/
cur_state = bb17_1;
end
bb17_1:
begin
/* br i1 %73, label %bb.i.i28, label %bb1.i.i30*/
if (var73) begin
cur_state = bb_i_i28;
end
else begin
cur_state = bb1_i_i30;
end
end
bb_i_i28:
begin
/* %extract.t.i.i27 = trunc i64 %a to i32 ; <i32> [#uses=1]*/
extract_t_i_i27 = a[31:0];
/* br label %normalizeFloat64Subnormal.exit38*/
shiftCount_0_i_i31 = 32'd32; /* for PHI node */
a_addr_0_off0_i_i32 = extract_t_i_i27; /* for PHI node */
cur_state = normalizeFloat64Subnormal_exit38;
end
bb1_i_i30:
begin
/* %74 = lshr i64 %0, 32 ; <i64> [#uses=1]*/
var74 = var0 >>> (64'd32 % 64);
/* br label %bb1.i.i30_1*/
cur_state = bb1_i_i30_1;
end
bb1_i_i30_1:
begin
/* %extract.t4.i.i29 = trunc i64 %74 to i32 ; <i32> [#uses=1]*/
extract_t4_i_i29 = var74[31:0];
/* br label %normalizeFloat64Subnormal.exit38*/
shiftCount_0_i_i31 = 32'd0; /* for PHI node */
a_addr_0_off0_i_i32 = extract_t4_i_i29; /* for PHI node */
cur_state = normalizeFloat64Subnormal_exit38;
end
normalizeFloat64Subnormal_exit38:
begin
/* %shiftCount.0.i.i31 = phi i32 [ 32, %bb.i.i28 ], [ 0, %bb1.i.i30_1 ] ; <i32> [#uses=1]*/
/* %a_addr.0.off0.i.i32 = phi i32 [ %extract.t.i.i27, %bb.i.i28 ], [ %extract.t4.i.i29, %bb1.i.i30_1 ] ; <i32> [#uses=3]*/
/* br label %normalizeFloat64Subnormal.exit38_1*/
cur_state = normalizeFloat64Subnormal_exit38_1;
end
normalizeFloat64Subnormal_exit38_1:
begin
/* %75 = shl i32 %a_addr.0.off0.i.i32, 16 ; <i32> [#uses=1]*/
var75 = a_addr_0_off0_i_i32 <<< (32'd16 % 32);
/* %76 = icmp ult i32 %a_addr.0.off0.i.i32, 65536 ; <i1> [#uses=2]*/
var76 = a_addr_0_off0_i_i32 < 32'd65536;
/* br label %normalizeFloat64Subnormal.exit38_2*/
cur_state = normalizeFloat64Subnormal_exit38_2;
end
normalizeFloat64Subnormal_exit38_2:
begin
/* %.a.i.i.i33 = select i1 %76, i32 %75, i32 %a_addr.0.off0.i.i32 ; <i32> [#uses=3]*/
_a_i_i_i33 = (var76) ? var75 : a_addr_0_off0_i_i32;
/* %shiftCount.0.i.i.i34 = select i1 %76, i32 16, i32 0 ; <i32> [#uses=2]*/
shiftCount_0_i_i_i34 = (var76) ? 32'd16 : 32'd0;
/* br label %normalizeFloat64Subnormal.exit38_3*/
cur_state = normalizeFloat64Subnormal_exit38_3;
end
normalizeFloat64Subnormal_exit38_3:
begin
/* %77 = icmp ult i32 %.a.i.i.i33, 16777216 ; <i1> [#uses=2]*/
var77 = _a_i_i_i33 < 32'd16777216;
/* %78 = or i32 %shiftCount.0.i.i.i34, 8 ; <i32> [#uses=1]*/
var78 = shiftCount_0_i_i_i34 | 32'd8;
/* %79 = shl i32 %.a.i.i.i33, 8 ; <i32> [#uses=1]*/
var79 = _a_i_i_i33 <<< (32'd8 % 32);
/* br label %normalizeFloat64Subnormal.exit38_4*/
cur_state = normalizeFloat64Subnormal_exit38_4;
end
normalizeFloat64Subnormal_exit38_4:
begin
/* %shiftCount.1.i.i.i35 = select i1 %77, i32 %78, i32 %shiftCount.0.i.i.i34 ; <i32> [#uses=1]*/
shiftCount_1_i_i_i35 = (var77) ? var78 : shiftCount_0_i_i_i34;
/* %a_addr.1.i.i.i36 = select i1 %77, i32 %79, i32 %.a.i.i.i33 ; <i32> [#uses=1]*/
a_addr_1_i_i_i36 = (var77) ? var79 : _a_i_i_i33;
/* br label %normalizeFloat64Subnormal.exit38_5*/
cur_state = normalizeFloat64Subnormal_exit38_5;
end
normalizeFloat64Subnormal_exit38_5:
begin
/* %80 = lshr i32 %a_addr.1.i.i.i36, 24 ; <i32> [#uses=1]*/
var80 = a_addr_1_i_i_i36 >>> (32'd24 % 32);
/* br label %normalizeFloat64Subnormal.exit38_6*/
cur_state = normalizeFloat64Subnormal_exit38_6;
end
normalizeFloat64Subnormal_exit38_6:
begin
/* %81 = getelementptr inbounds [256 x i32]* @countLeadingZerosHigh.1302, i32 0, i32 %80 ; <i32*> [#uses=1]*/
var81 = {`TAG_countLeadingZerosHigh_1302, 32'b0} + ((var80 + 256*(32'd0)) << 2);
/* br label %normalizeFloat64Subnormal.exit38_7*/
cur_state = normalizeFloat64Subnormal_exit38_7;
end
normalizeFloat64Subnormal_exit38_7:
begin
/* %82 = load i32* %81, align 4 ; <i32> [#uses=1]*/
/* br label %normalizeFloat64Subnormal.exit38_8*/
cur_state = normalizeFloat64Subnormal_exit38_8;
end
normalizeFloat64Subnormal_exit38_8:
begin
var82 = memory_controller_out[31:0];
/* %load_noop4 = add i32 %82, 0 ; <i32> [#uses=1]*/
load_noop4 = var82 + 32'd0;
/* br label %normalizeFloat64Subnormal.exit38_9*/
cur_state = normalizeFloat64Subnormal_exit38_9;
end
normalizeFloat64Subnormal_exit38_9:
begin
/* %83 = add nsw i32 %load_noop4, %shiftCount.0.i.i31 ; <i32> [#uses=1]*/
var83 = load_noop4 + shiftCount_0_i_i31;
/* br label %normalizeFloat64Subnormal.exit38_10*/
cur_state = normalizeFloat64Subnormal_exit38_10;
end
normalizeFloat64Subnormal_exit38_10:
begin
/* %84 = add nsw i32 %83, %shiftCount.1.i.i.i35 ; <i32> [#uses=2]*/
var84 = var83 + shiftCount_1_i_i_i35;
/* br label %normalizeFloat64Subnormal.exit38_11*/
cur_state = normalizeFloat64Subnormal_exit38_11;
end
normalizeFloat64Subnormal_exit38_11:
begin
/* %85 = add i32 %84, -11 ; <i32> [#uses=1]*/
var85 = var84 + -32'd11;
/* %86 = sub i32 12, %84 ; <i32> [#uses=1]*/
var86 = 32'd12 - var84;
/* br label %normalizeFloat64Subnormal.exit38_12*/
cur_state = normalizeFloat64Subnormal_exit38_12;
end
normalizeFloat64Subnormal_exit38_12:
begin
/* %.cast.i37 = zext i32 %85 to i64 ; <i64> [#uses=1]*/
_cast_i37 = var85;
/* br label %normalizeFloat64Subnormal.exit38_13*/
cur_state = normalizeFloat64Subnormal_exit38_13;
end
normalizeFloat64Subnormal_exit38_13:
begin
/* %87 = shl i64 %0, %.cast.i37 ; <i64> [#uses=1]*/
var87 = var0 <<< (_cast_i37 % 64);
/* br label %bb18*/
aSig_0 = var87; /* for PHI node */
aExp_0 = var86; /* for PHI node */
cur_state = bb18;
end
bb18:
begin
/* %aSig.0 = phi i64 [ %87, %normalizeFloat64Subnormal.exit38_13 ], [ %0, %bb14_1 ] ; <i64> [#uses=2]*/
/* %aExp.0 = phi i32 [ %86, %normalizeFloat64Subnormal.exit38_13 ], [ %8, %bb14_1 ] ; <i32> [#uses=1]*/
/* %88 = icmp eq i32 %9, 0 ; <i1> [#uses=1]*/
var88 = var9 == 32'd0;
/* br label %bb18_1*/
cur_state = bb18_1;
end
bb18_1:
begin
/* br i1 %88, label %bb19, label %bb22*/
if (var88) begin
cur_state = bb19;
end
else begin
bExp_0 = var9; /* for PHI node */
bSig_0 = var2; /* for PHI node */
cur_state = bb22;
end
end
bb19:
begin
/* %89 = icmp eq i64 %2, 0 ; <i1> [#uses=1]*/
var89 = var2 == 64'd0;
/* br label %bb19_1*/
cur_state = bb19_1;
end
bb19_1:
begin
/* br i1 %89, label %bb20, label %bb21*/
if (var89) begin
cur_state = bb20;
end
else begin
cur_state = bb21;
end
end
bb20:
begin
/* %90 = and i64 %4, -9223372036854775808 ; <i64> [#uses=1]*/
var90 = var4 & -64'd9223372036854775808;
/* br label %bb20_1*/
cur_state = bb20_1;
end
bb20_1:
begin
/* ret i64 %90*/
return_val = var90;
finish = 1;
cur_state = Wait;
end
bb21:
begin
/* %91 = icmp ult i64 %2, 4294967296 ; <i1> [#uses=1]*/
var91 = var2 < 64'd4294967296;
/* br label %bb21_1*/
cur_state = bb21_1;
end
bb21_1:
begin
/* br i1 %91, label %bb.i.i, label %bb1.i.i*/
if (var91) begin
cur_state = bb_i_i;
end
else begin
cur_state = bb1_i_i;
end
end
bb_i_i:
begin
/* %extract.t.i.i = trunc i64 %b to i32 ; <i32> [#uses=1]*/
extract_t_i_i = b[31:0];
/* br label %normalizeFloat64Subnormal.exit*/
shiftCount_0_i_i = 32'd32; /* for PHI node */
a_addr_0_off0_i_i = extract_t_i_i; /* for PHI node */
cur_state = normalizeFloat64Subnormal_exit;
end
bb1_i_i:
begin
/* %92 = lshr i64 %2, 32 ; <i64> [#uses=1]*/
var92 = var2 >>> (64'd32 % 64);
/* br label %bb1.i.i_1*/
cur_state = bb1_i_i_1;
end
bb1_i_i_1:
begin
/* %extract.t4.i.i = trunc i64 %92 to i32 ; <i32> [#uses=1]*/
extract_t4_i_i = var92[31:0];
/* br label %normalizeFloat64Subnormal.exit*/
shiftCount_0_i_i = 32'd0; /* for PHI node */
a_addr_0_off0_i_i = extract_t4_i_i; /* for PHI node */
cur_state = normalizeFloat64Subnormal_exit;
end
normalizeFloat64Subnormal_exit:
begin
/* %shiftCount.0.i.i = phi i32 [ 32, %bb.i.i ], [ 0, %bb1.i.i_1 ] ; <i32> [#uses=1]*/
/* %a_addr.0.off0.i.i = phi i32 [ %extract.t.i.i, %bb.i.i ], [ %extract.t4.i.i, %bb1.i.i_1 ] ; <i32> [#uses=3]*/
/* br label %normalizeFloat64Subnormal.exit_1*/
cur_state = normalizeFloat64Subnormal_exit_1;
end
normalizeFloat64Subnormal_exit_1:
begin
/* %93 = shl i32 %a_addr.0.off0.i.i, 16 ; <i32> [#uses=1]*/
var93 = a_addr_0_off0_i_i <<< (32'd16 % 32);
/* %94 = icmp ult i32 %a_addr.0.off0.i.i, 65536 ; <i1> [#uses=2]*/
var94 = a_addr_0_off0_i_i < 32'd65536;
/* br label %normalizeFloat64Subnormal.exit_2*/
cur_state = normalizeFloat64Subnormal_exit_2;
end
normalizeFloat64Subnormal_exit_2:
begin
/* %.a.i.i.i = select i1 %94, i32 %93, i32 %a_addr.0.off0.i.i ; <i32> [#uses=3]*/
_a_i_i_i = (var94) ? var93 : a_addr_0_off0_i_i;
/* %shiftCount.0.i.i.i = select i1 %94, i32 16, i32 0 ; <i32> [#uses=2]*/
shiftCount_0_i_i_i = (var94) ? 32'd16 : 32'd0;
/* br label %normalizeFloat64Subnormal.exit_3*/
cur_state = normalizeFloat64Subnormal_exit_3;
end
normalizeFloat64Subnormal_exit_3:
begin
/* %95 = icmp ult i32 %.a.i.i.i, 16777216 ; <i1> [#uses=2]*/
var95 = _a_i_i_i < 32'd16777216;
/* %96 = or i32 %shiftCount.0.i.i.i, 8 ; <i32> [#uses=1]*/
var96 = shiftCount_0_i_i_i | 32'd8;
/* %97 = shl i32 %.a.i.i.i, 8 ; <i32> [#uses=1]*/
var97 = _a_i_i_i <<< (32'd8 % 32);
/* br label %normalizeFloat64Subnormal.exit_4*/
cur_state = normalizeFloat64Subnormal_exit_4;
end
normalizeFloat64Subnormal_exit_4:
begin
/* %shiftCount.1.i.i.i = select i1 %95, i32 %96, i32 %shiftCount.0.i.i.i ; <i32> [#uses=1]*/
shiftCount_1_i_i_i = (var95) ? var96 : shiftCount_0_i_i_i;
/* %a_addr.1.i.i.i = select i1 %95, i32 %97, i32 %.a.i.i.i ; <i32> [#uses=1]*/
a_addr_1_i_i_i = (var95) ? var97 : _a_i_i_i;
/* br label %normalizeFloat64Subnormal.exit_5*/
cur_state = normalizeFloat64Subnormal_exit_5;
end
normalizeFloat64Subnormal_exit_5:
begin
/* %98 = lshr i32 %a_addr.1.i.i.i, 24 ; <i32> [#uses=1]*/
var98 = a_addr_1_i_i_i >>> (32'd24 % 32);
/* br label %normalizeFloat64Subnormal.exit_6*/
cur_state = normalizeFloat64Subnormal_exit_6;
end
normalizeFloat64Subnormal_exit_6:
begin
/* %99 = getelementptr inbounds [256 x i32]* @countLeadingZerosHigh.1302, i32 0, i32 %98 ; <i32*> [#uses=1]*/
var99 = {`TAG_countLeadingZerosHigh_1302, 32'b0} + ((var98 + 256*(32'd0)) << 2);
/* br label %normalizeFloat64Subnormal.exit_7*/
cur_state = normalizeFloat64Subnormal_exit_7;
end
normalizeFloat64Subnormal_exit_7:
begin
/* %100 = load i32* %99, align 4 ; <i32> [#uses=1]*/
/* br label %normalizeFloat64Subnormal.exit_8*/
cur_state = normalizeFloat64Subnormal_exit_8;
end
normalizeFloat64Subnormal_exit_8:
begin
var100 = memory_controller_out[31:0];
/* %load_noop5 = add i32 %100, 0 ; <i32> [#uses=1]*/
load_noop5 = var100 + 32'd0;
/* br label %normalizeFloat64Subnormal.exit_9*/
cur_state = normalizeFloat64Subnormal_exit_9;
end
normalizeFloat64Subnormal_exit_9:
begin
/* %101 = add nsw i32 %load_noop5, %shiftCount.0.i.i ; <i32> [#uses=1]*/
var101 = load_noop5 + shiftCount_0_i_i;
/* br label %normalizeFloat64Subnormal.exit_10*/
cur_state = normalizeFloat64Subnormal_exit_10;
end
normalizeFloat64Subnormal_exit_10:
begin
/* %102 = add nsw i32 %101, %shiftCount.1.i.i.i ; <i32> [#uses=2]*/
var102 = var101 + shiftCount_1_i_i_i;
/* br label %normalizeFloat64Subnormal.exit_11*/
cur_state = normalizeFloat64Subnormal_exit_11;
end
normalizeFloat64Subnormal_exit_11:
begin
/* %103 = add i32 %102, -11 ; <i32> [#uses=1]*/
var103 = var102 + -32'd11;
/* %104 = sub i32 12, %102 ; <i32> [#uses=1]*/
var104 = 32'd12 - var102;
/* br label %normalizeFloat64Subnormal.exit_12*/
cur_state = normalizeFloat64Subnormal_exit_12;
end
normalizeFloat64Subnormal_exit_12:
begin
/* %.cast.i = zext i32 %103 to i64 ; <i64> [#uses=1]*/
_cast_i = var103;
/* br label %normalizeFloat64Subnormal.exit_13*/
cur_state = normalizeFloat64Subnormal_exit_13;
end
normalizeFloat64Subnormal_exit_13:
begin
/* %105 = shl i64 %2, %.cast.i ; <i64> [#uses=1]*/
var105 = var2 <<< (_cast_i % 64);
/* br label %bb22*/
bExp_0 = var104; /* for PHI node */
bSig_0 = var105; /* for PHI node */
cur_state = bb22;
end
bb22:
begin
/* %bExp.0 = phi i32 [ %104, %normalizeFloat64Subnormal.exit_13 ], [ %9, %bb18_1 ] ; <i32> [#uses=1]*/
/* %bSig.0 = phi i64 [ %105, %normalizeFloat64Subnormal.exit_13 ], [ %2, %bb18_1 ] ; <i64> [#uses=2]*/
/* %106 = shl i64 %aSig.0, 10 ; <i64> [#uses=1]*/
var106 = aSig_0 <<< (64'd10 % 64);
/* %107 = lshr i64 %aSig.0, 22 ; <i64> [#uses=1]*/
var107 = aSig_0 >>> (64'd22 % 64);
/* br label %bb22_1*/
cur_state = bb22_1;
end
bb22_1:
begin
/* %108 = shl i64 %bSig.0, 11 ; <i64> [#uses=1]*/
var108 = bSig_0 <<< (64'd11 % 64);
/* %109 = or i64 %107, 1073741824 ; <i64> [#uses=1]*/
var109 = var107 | 64'd1073741824;
/* %110 = lshr i64 %bSig.0, 21 ; <i64> [#uses=1]*/
var110 = bSig_0 >>> (64'd21 % 64);
/* %111 = and i64 %106, 4294966272 ; <i64> [#uses=2]*/
var111 = var106 & 64'd4294966272;
/* %112 = add nsw i32 %bExp.0, %aExp.0 ; <i32> [#uses=1]*/
var112 = bExp_0 + aExp_0;
/* br label %bb22_2*/
cur_state = bb22_2;
end
bb22_2:
begin
/* %113 = and i64 %109, 4294967295 ; <i64> [#uses=2]*/
var113 = var109 & 64'd4294967295;
/* %114 = or i64 %110, 2147483648 ; <i64> [#uses=1]*/
var114 = var110 | 64'd2147483648;
/* %115 = and i64 %108, 4294965248 ; <i64> [#uses=2]*/
var115 = var108 & 64'd4294965248;
/* br label %bb22_3*/
cur_state = bb22_3;
end
bb22_3:
begin
/* %116 = and i64 %114, 4294967295 ; <i64> [#uses=2]*/
var116 = var114 & 64'd4294967295;
/* %117 = mul i64 %115, %111 ; <i64> [#uses=1]*/
var117 = var115 * var111;
/* %118 = mul i64 %115, %113 ; <i64> [#uses=2]*/
var118 = var115 * var113;
/* br label %bb22_4*/
cur_state = bb22_4;
end
bb22_4:
begin
/* %119 = mul i64 %116, %111 ; <i64> [#uses=1]*/
var119 = var116 * var111;
/* %120 = mul i64 %116, %113 ; <i64> [#uses=1]*/
var120 = var116 * var113;
/* br label %bb22_5*/
cur_state = bb22_5;
end
bb22_5:
begin
/* %121 = add i64 %119, %118 ; <i64> [#uses=3]*/
var121 = var119 + var118;
/* br label %bb22_6*/
cur_state = bb22_6;
end
bb22_6:
begin
/* %122 = icmp ult i64 %121, %118 ; <i1> [#uses=1]*/
var122 = var121 < var118;
/* %123 = lshr i64 %121, 32 ; <i64> [#uses=1]*/
var123 = var121 >>> (64'd32 % 64);
/* %124 = shl i64 %121, 32 ; <i64> [#uses=2]*/
var124 = var121 <<< (64'd32 % 64);
/* br label %bb22_7*/
cur_state = bb22_7;
end
bb22_7:
begin
/* %iftmp.17.0.i = select i1 %122, i64 4294967296, i64 0 ; <i64> [#uses=1]*/
iftmp_17_0_i = (var122) ? 64'd4294967296 : 64'd0;
/* %125 = add i64 %124, %117 ; <i64> [#uses=2]*/
var125 = var124 + var117;
/* br label %bb22_8*/
cur_state = bb22_8;
end
bb22_8:
begin
/* %126 = or i64 %iftmp.17.0.i, %123 ; <i64> [#uses=1]*/
var126 = iftmp_17_0_i | var123;
/* %127 = icmp ult i64 %125, %124 ; <i1> [#uses=1]*/
var127 = var125 < var124;
/* %128 = icmp ne i64 %125, 0 ; <i1> [#uses=1]*/
var128 = var125 != 64'd0;
/* br label %bb22_9*/
cur_state = bb22_9;
end
bb22_9:
begin
/* %129 = zext i1 %127 to i64 ; <i64> [#uses=1]*/
var129 = var127;
/* %130 = add i64 %126, %120 ; <i64> [#uses=1]*/
var130 = var126 + var120;
/* %131 = zext i1 %128 to i64 ; <i64> [#uses=1]*/
var131 = var128;
/* br label %bb22_10*/
cur_state = bb22_10;
end
bb22_10:
begin
/* %132 = add i64 %130, %129 ; <i64> [#uses=2]*/
var132 = var130 + var129;
/* br label %bb22_11*/
cur_state = bb22_11;
end
bb22_11:
begin
/* %133 = or i64 %132, %131 ; <i64> [#uses=1]*/
var133 = var132 | var131;
/* %.mask = and i64 %132, 4611686018427387904 ; <i64> [#uses=2]*/
_mask = var132 & 64'd4611686018427387904;
/* br label %bb22_12*/
cur_state = bb22_12;
end
bb22_12:
begin
/* %134 = icmp eq i64 %.mask, 0 ; <i1> [#uses=1]*/
var134 = _mask == 64'd0;
/* %.mask.lobit = lshr i64 %.mask, 62 ; <i64> [#uses=1]*/
_mask_lobit = _mask >>> (64'd62 % 64);
/* br label %bb22_13*/
cur_state = bb22_13;
end
bb22_13:
begin
/* %tmp = xor i64 %.mask.lobit, 1 ; <i64> [#uses=1]*/
tmp = _mask_lobit ^ 64'd1;
/* %zExp.0.v = select i1 %134, i32 -1024, i32 -1023 ; <i32> [#uses=1]*/
zExp_0_v = (var134) ? -32'd1024 : -32'd1023;
/* br label %bb22_14*/
cur_state = bb22_14;
end
bb22_14:
begin
/* %zSig0.0 = shl i64 %133, %tmp ; <i64> [#uses=1]*/
zSig0_0 = var133 <<< (tmp % 64);
/* %zExp.0 = add i32 %112, %zExp.0.v ; <i32> [#uses=1]*/
zExp_0 = var112 + zExp_0_v;
/* br label %bb22_15*/
cur_state = bb22_15;
end
bb22_15:
begin
/* %135 = tail call fastcc i64 @roundAndPackFloat64(i32 %10, i32 %zExp.0, i64 %zSig0.0) nounwind ; <i64> [#uses=1]*/
roundAndPackFloat64_start = 1;
/* Argument: %10 = trunc i64 %7 to i32 ; <i32> [#uses=1]*/
roundAndPackFloat64_zSign = var10;
/* Argument: %zExp.0 = add i32 %112, %zExp.0.v ; <i32> [#uses=1]*/
roundAndPackFloat64_zExp = zExp_0;
/* Argument: %zSig0.0 = shl i64 %133, %tmp ; <i64> [#uses=1]*/
roundAndPackFloat64_zSig = zSig0_0;
cur_state = bb22_15_call_0;
end
bb22_15_call_0:
begin
roundAndPackFloat64_start = 0;
if (roundAndPackFloat64_finish == 1)
begin
var135 = roundAndPackFloat64_return_val;
cur_state = bb22_15_call_1;
end
else
cur_state = bb22_15_call_0;
end
bb22_15_call_1:
begin
/* br label %bb22_16*/
cur_state = bb22_16;
end
bb22_16:
begin
/* ret i64 %135*/
return_val = var135;
finish = 1;
cur_state = Wait;
end
endcase
always @(*)
begin
memory_controller_write_enable = 0;
memory_controller_address = 0;
memory_controller_in = 0;
roundAndPackFloat64_memory_controller_out = 0;
case(cur_state)
default:
begin
// quartus issues a warning if we have no default case
end
bb_i48:
begin
memory_controller_address = {`TAG_float_exception_flags, 32'b0};
memory_controller_write_enable = 0;
end
bb_i48_3:
begin
memory_controller_address = {`TAG_float_exception_flags, 32'b0};
memory_controller_write_enable = 1;
memory_controller_in = var31;
end
bb6:
begin
memory_controller_address = {`TAG_float_exception_flags, 32'b0};
memory_controller_write_enable = 0;
end
bb6_3:
begin
memory_controller_address = {`TAG_float_exception_flags, 32'b0};
memory_controller_write_enable = 1;
memory_controller_in = var39;
end
bb_i:
begin
memory_controller_address = {`TAG_float_exception_flags, 32'b0};
memory_controller_write_enable = 0;
end
bb_i_3:
begin
memory_controller_address = {`TAG_float_exception_flags, 32'b0};
memory_controller_write_enable = 1;
memory_controller_in = var59;
end
bb12:
begin
memory_controller_address = {`TAG_float_exception_flags, 32'b0};
memory_controller_write_enable = 0;
end
bb12_3:
begin
memory_controller_address = {`TAG_float_exception_flags, 32'b0};
memory_controller_write_enable = 1;
memory_controller_in = var67;
end
normalizeFloat64Subnormal_exit38_7:
begin
memory_controller_address = var81;
memory_controller_write_enable = 0;
end
normalizeFloat64Subnormal_exit_7:
begin
memory_controller_address = var99;
memory_controller_write_enable = 0;
end
bb22_15:
begin
end
bb22_15_call_0:
begin
memory_controller_address = roundAndPackFloat64_memory_controller_address;
memory_controller_write_enable = roundAndPackFloat64_memory_controller_write_enable;
memory_controller_in = roundAndPackFloat64_memory_controller_in;
roundAndPackFloat64_memory_controller_out = memory_controller_out;
end
bb22_15_call_1:
begin
end
endcase
end
endmodule
`timescale 1 ns / 1 ns
module memset
(
clk,
reset,
start,
finish,
return_val,
m,
c,
n,
memory_controller_write_enable,
memory_controller_address,
memory_controller_in,
memory_controller_out
);
output reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] return_val;
input clk;
input reset;
input start;
output reg finish;
input [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] m;
input [31:0] c;
input [31:0] n;
output reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] memory_controller_address;
output reg memory_controller_write_enable;
output reg [`MEMORY_CONTROLLER_DATA_SIZE-1:0] memory_controller_in;
input wire [`MEMORY_CONTROLLER_DATA_SIZE-1:0] memory_controller_out;
reg [3:0] cur_state;
parameter Wait = 4'd0;
parameter entry = 4'd1;
parameter entry_1 = 4'd2;
parameter entry_2 = 4'd3;
parameter bb = 4'd4;
parameter bb_1 = 4'd5;
parameter bb1 = 4'd6;
parameter bb1_1 = 4'd7;
parameter bb1_2 = 4'd8;
parameter bb_nph = 4'd9;
parameter bb2 = 4'd10;
parameter bb2_1 = 4'd11;
parameter bb2_2 = 4'd12;
parameter bb2_3 = 4'd13;
parameter bb2_4 = 4'd14;
parameter bb4 = 4'd15;
reg [31:0] var0;
reg var1;
reg [7:0] var2;
reg [31:0] var4;
reg [31:0] var5;
reg var3;
reg [31:0] tmp;
reg [31:0] indvar;
reg [31:0] tmp8;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] scevgep;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] s_07;
reg [31:0] indvar_next;
reg exitcond;
always @(posedge clk)
if (reset)
cur_state = Wait;
else
case(cur_state)
Wait:
begin
finish = 0;
if (start == 1)
cur_state = entry;
else
cur_state = Wait;
end
entry:
begin
/* %0 = and i32 %n, 3 ; <i32> [#uses=1]*/
var0 = n & 32'd3;
/* br label %entry_1*/
cur_state = entry_1;
end
entry_1:
begin
/* %1 = icmp eq i32 %0, 0 ; <i1> [#uses=1]*/
var1 = var0 == 32'd0;
/* br label %entry_2*/
cur_state = entry_2;
end
entry_2:
begin
/* br i1 %1, label %bb1, label %bb*/
if (var1) begin
cur_state = bb1;
end
else begin
cur_state = bb;
end
end
bb:
begin
/* %2 = tail call i32 (i8*, ...)* @printf(i8* noalias getelementptr inbounds ([32 x i8]* @.str2, i32 0, i32 0)) nounwind ; <i32> [#uses=0]*/
$write("Expecting word-aligned memset!\n"); /* br label %bb_1*/
cur_state = bb_1;
end
bb_1:
begin
/* tail call void @exit(i32 1) noreturn nounwind*/
$finish; /* unreachable*/
end
bb1:
begin
/* %3 = trunc i32 %c to i8 ; <i8> [#uses=1]*/
var2 = c[7:0];
/* %4 = icmp ult i32 %n, 4 ; <i1> [#uses=1]*/
var3 = n < 32'd4;
/* br label %bb1_1*/
cur_state = bb1_1;
end
bb1_1:
begin
/* %5 = sext i8 %3 to i32 ; <i32> [#uses=1]*/
var4 = $signed(var2);
/* br label %bb1_2*/
cur_state = bb1_2;
end
bb1_2:
begin
/* %6 = mul i32 %5, 16843009 ; <i32> [#uses=1]*/
var5 = var4 * 32'd16843009;
/* br i1 %4, label %bb4, label %bb.nph*/
if (var3) begin
cur_state = bb4;
end
else begin
cur_state = bb_nph;
end
end
bb_nph:
begin
/* %tmp = lshr i32 %n, 2 ; <i32> [#uses=1]*/
tmp = n >>> (32'd2 % 32);
/* br label %bb2*/
indvar = 32'd0; /* for PHI node */
cur_state = bb2;
end
bb2:
begin
/* %indvar = phi i32 [ 0, %bb.nph ], [ %indvar.next, %bb2_4 ] ; <i32> [#uses=2]*/
/* br label %bb2_1*/
cur_state = bb2_1;
end
bb2_1:
begin
/* %tmp8 = shl i32 %indvar, 2 ; <i32> [#uses=1]*/
tmp8 = indvar <<< (32'd2 % 32);
/* %indvar.next = add i32 %indvar, 1 ; <i32> [#uses=2]*/
indvar_next = indvar + 32'd1;
/* br label %bb2_2*/
cur_state = bb2_2;
end
bb2_2:
begin
/* %scevgep = getelementptr i8* %m, i32 %tmp8 ; <i8*> [#uses=1]*/
scevgep = m + ((tmp8) << 0);
/* %exitcond = icmp eq i32 %indvar.next, %tmp ; <i1> [#uses=1]*/
exitcond = indvar_next == tmp;
/* br label %bb2_3*/
cur_state = bb2_3;
end
bb2_3:
begin
/* %s.07 = bitcast i8* %scevgep to i32* ; <i32*> [#uses=1]*/
s_07 = scevgep;
/* br label %bb2_4*/
cur_state = bb2_4;
end
bb2_4:
begin
/* store i32 %6, i32* %s.07, align 4*/
/* br i1 %exitcond, label %bb4, label %bb2*/
if (exitcond) begin
cur_state = bb4;
end
else begin
indvar = indvar_next; /* for PHI node */
cur_state = bb2;
end
end
bb4:
begin
/* ret i8* %m*/
return_val = m;
finish = 1;
cur_state = Wait;
end
endcase
always @(*)
begin
memory_controller_write_enable = 0;
memory_controller_address = 0;
memory_controller_in = 0;
case(cur_state)
default:
begin
// quartus issues a warning if we have no default case
end
bb2_4:
begin
memory_controller_address = s_07;
memory_controller_write_enable = 1;
memory_controller_in = var5;
end
endcase
end
endmodule
module ram_one_port
(
clk,
address,
write_enable,
data,
q
);
parameter width_a = 0;
parameter widthad_a = 0;
parameter numwords_a = 0;
parameter init_file = "UNUSED";
input clk;
input [(widthad_a-1):0] address;
input write_enable;
input [(width_a-1):0] data;
output [(width_a-1):0] q;
altsyncram altsyncram_component (
.wren_a (write_enable),
.clock0 (clk),
.address_a (address),
.data_a (data),
.q_a (q),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.init_file = init_file,
altsyncram_component.intended_device_family = "Stratix IV",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = numwords_a,
altsyncram_component.operation_mode = "SINGLE_PORT",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_port_a = "DONT_CARE",
altsyncram_component.widthad_a = widthad_a,
altsyncram_component.width_a = width_a,
altsyncram_component.width_byteena_a = 1;
endmodule
module main_tb();
// inputs
reg clk, reset, start;
// outputs
wire [31:0] return_val;
wire finish;
main main_inst(clk, reset, start, finish, return_val);
initial
clk = #0 0;
always @(clk)
clk <= #1 ~clk;
initial begin
//$monitor("At t=%t clk=%b %b %b %b %d", $time, clk, reset, start, finish, return_val);
@(negedge clk);
reset = 1;
@(negedge clk);
reset = 0;
start = 1;
end
always@(finish) begin
if (finish == 1) begin
$display("At t=%t clk=%b finish=%b return_val=%d", $time, clk, finish, return_val);
$finish;
end
end
endmodule
|
`timescale 1 ns/100 ps // time unit = 1ns; precision = 1/10 ns
/* Static arbiter. Grant to the first request starting from the
* least-significant bit
*/
module arbiter_static #(
parameter SIZE = 10
)
(
input [SIZE-1:0] requests,
output [SIZE-1:0] grants,
output grant_valid
);
// This module only supports SIZE = 1, 2, 4, 8
// psl ERROR_unsupported_arbiter_size: assert always {(SIZE > 0 && SIZE <= 10) || SIZE == 16};
reg [SIZE:0] grant_temp;
assign {grant_valid, grants} = grant_temp;
generate
if (SIZE == 1)
begin
always @(*)
begin
grant_temp = {requests, requests};
end
end
else if (SIZE == 2)
begin
always @(*)
begin
if (requests[0]) grant_temp = 3'b101;
else if (requests[1]) grant_temp = 3'b110;
else grant_temp = 3'b000;
end
end
else if (SIZE == 3)
begin
always @(*)
begin
if (requests[0]) grant_temp = 4'b1001;
else if (requests[1]) grant_temp = 4'b1010;
else if (requests[2]) grant_temp = 4'b1100;
else grant_temp = 4'b0000;
end
end
else if (SIZE == 4)
begin
always @(*)
begin
if (requests[0]) grant_temp = 5'b10001;
else if (requests[1]) grant_temp = 5'b10010;
else if (requests[2]) grant_temp = 5'b10100;
else if (requests[3]) grant_temp = 5'b11000;
else grant_temp = 5'b00000;
end
end
else if (SIZE == 5)
begin
always @(*)
begin
if (requests[0]) grant_temp = 6'b10_0001;
else if (requests[1]) grant_temp = 6'b10_0010;
else if (requests[2]) grant_temp = 6'b10_0100;
else if (requests[3]) grant_temp = 6'b10_1000;
else if (requests[4]) grant_temp = 6'b11_0000;
else grant_temp = 6'b00_0000;
end
end
else if (SIZE == 6)
begin
always @(*)
begin
if (requests[0]) grant_temp = 7'b100_0001;
else if (requests[1]) grant_temp = 7'b100_0010;
else if (requests[2]) grant_temp = 7'b100_0100;
else if (requests[3]) grant_temp = 7'b100_1000;
else if (requests[4]) grant_temp = 7'b101_0000;
else if (requests[5]) grant_temp = 7'b110_0000;
else grant_temp = 7'b000_0000;
end
end
else if (SIZE == 7)
begin
always @(*)
begin
if (requests[0]) grant_temp = 8'b1000_0001;
else if (requests[1]) grant_temp = 8'b1000_0010;
else if (requests[2]) grant_temp = 8'b1000_0100;
else if (requests[3]) grant_temp = 8'b1000_1000;
else if (requests[4]) grant_temp = 8'b1001_0000;
else if (requests[5]) grant_temp = 8'b1010_0000;
else if (requests[6]) grant_temp = 8'b1100_0000;
else grant_temp = 8'b0000_0000;
end
end
else if (SIZE == 8)
begin
always @(*)
begin
if (requests[0]) grant_temp = 9'b10000_0001;
else if (requests[1]) grant_temp = 9'b10000_0010;
else if (requests[2]) grant_temp = 9'b10000_0100;
else if (requests[3]) grant_temp = 9'b10000_1000;
else if (requests[4]) grant_temp = 9'b10001_0000;
else if (requests[5]) grant_temp = 9'b10010_0000;
else if (requests[6]) grant_temp = 9'b10100_0000;
else if (requests[7]) grant_temp = 9'b11000_0000;
else grant_temp = 9'b00000_0000;
end
end
else if (SIZE == 9)
begin
always @(*)
begin
if (requests[0]) grant_temp = 10'b10_0000_0001;
else if (requests[1]) grant_temp = 10'b10_0000_0010;
else if (requests[2]) grant_temp = 10'b10_0000_0100;
else if (requests[3]) grant_temp = 10'b10_0000_1000;
else if (requests[4]) grant_temp = 10'b10_0001_0000;
else if (requests[5]) grant_temp = 10'b10_0010_0000;
else if (requests[6]) grant_temp = 10'b10_0100_0000;
else if (requests[7]) grant_temp = 10'b10_1000_0000;
else if (requests[8]) grant_temp = 10'b11_0000_0000;
else grant_temp = 10'b00_0000_0000;
end
end
else if (SIZE == 10)
begin
always @(*)
begin
if (requests[0]) grant_temp = 11'b100_0000_0001;
else if (requests[1]) grant_temp = 11'b100_0000_0010;
else if (requests[2]) grant_temp = 11'b100_0000_0100;
else if (requests[3]) grant_temp = 11'b100_0000_1000;
else if (requests[4]) grant_temp = 11'b100_0001_0000;
else if (requests[5]) grant_temp = 11'b100_0010_0000;
else if (requests[6]) grant_temp = 11'b100_0100_0000;
else if (requests[7]) grant_temp = 11'b100_1000_0000;
else if (requests[8]) grant_temp = 11'b101_0000_0000;
else if (requests[9]) grant_temp = 11'b110_0000_0000;
else grant_temp = 11'b000_0000_0000;
end
end
else if (SIZE == 16)
begin
always @(*)
begin
if (requests[0]) grant_temp = 17'h10001;
else if (requests[1]) grant_temp = 17'h10002;
else if (requests[2]) grant_temp = 17'h10004;
else if (requests[3]) grant_temp = 17'h10008;
else if (requests[4]) grant_temp = 17'h10010;
else if (requests[5]) grant_temp = 17'h10020;
else if (requests[6]) grant_temp = 17'h10040;
else if (requests[7]) grant_temp = 17'h10080;
else if (requests[8]) grant_temp = 17'h10100;
else if (requests[9]) grant_temp = 17'h10200;
else if (requests[10]) grant_temp = 17'h10400;
else if (requests[11]) grant_temp = 17'h10800;
else if (requests[12]) grant_temp = 17'h11000;
else if (requests[13]) grant_temp = 17'h12000;
else if (requests[14]) grant_temp = 17'h14000;
else if (requests[15]) grant_temp = 17'h18000;
else grant_temp = 17'h00000;
end
end
endgenerate
endmodule
|
`timescale 1ns / 1ps
/* Baud rate generator (9600)
* Assume 50 MHz clock input
*/
module baud_gen #(
parameter BAUD_RATE = 9600
)
(
input clock,
input reset,
input start,
output reg baud_tick
);
`include "math.v"
localparam WIDTH = 16;
reg [WIDTH-1: 0] counter_r;
wire [WIDTH-1:0] max;
// Counter values are selected for each baud rate
generate
if (BAUD_RATE == 9600) // 9600
begin
reg [1:0] toggle;
assign max = (toggle == 0) ? 16'd5209 : 16'd5208;
always @(posedge clock)
begin
if (reset)
toggle <= 0;
else if (baud_tick)
if (toggle == 2)
toggle <= 0;
else
toggle <= toggle + 1;
end
end
else if (BAUD_RATE == 115200) // 115200
begin
reg [6:0] toggle;
assign max = (toggle == 0) ? 16'd435 : 16'd434;
always @(posedge clock)
begin
if (reset)
toggle <= 0;
else if (baud_tick)
if (toggle == 35)
toggle <= 0;
else
toggle <= toggle + 1;
end
end
else if (BAUD_RATE == 0) // Simulation
begin
assign max = 16'h4;
end
endgenerate
// Baud tick counter
always @(posedge clock)
begin
if (reset)
begin
counter_r <= {(WIDTH){1'b0}};
baud_tick <= 1'b0;
end
else
begin
if (counter_r == max)
begin
baud_tick <= 1'b1;
counter_r <= {(WIDTH){1'b0}};
end
else
begin
baud_tick <= 1'b0;
if (start)
counter_r <= {1'b0, max[WIDTH-1:1]}; // Reset counter to half the max value
else
counter_r <= counter_r + {{(WIDTH-1){1'b0}}, 1'b1};
end
end
end
endmodule
|
`timescale 1 ns/100 ps // time unit = 1ns; precision = 1/10 ns
/* Check Destination
* check_dest.v
*
* Given a set of input nexthop and enable bits, generate a vector
* that indicate if each incoming packet is for a node in this
* partition.
*
* Node addresses follow the convention below:
* addr2 = {partition ID (4), node ID (4), port ID (3)}
*/
`include "const.v"
module check_dest (
src_nexthop_in,
valid
);
parameter N = 8; // Number of incoming packets
parameter PID = 4'h0; // Partition number
input [N*`A_WIDTH-1:0] src_nexthop_in;
output [N-1:0] valid;
genvar i;
generate
for (i = 0; i < N; i = i + 1)
begin : in
wire [`A_WIDTH-1:0] nexthop;
assign nexthop = src_nexthop_in[(i+1)*`A_WIDTH-1:i*`A_WIDTH];
assign valid[i] = (nexthop[`A_DPID] == PID) ? 1'b1 : 1'b0;
end
endgenerate
endmodule
|
/* const.v
* This file contains all the global defines used by all
* Verilog modules.
*/
`define FLIT_WIDTH 36
`define CREDIT_WIDTH 11
`define TS_WIDTH 10
`define ADDR_WIDTH 8
`define VC_WIDTH 1
`define BW_WIDTH 8
`define LAT_WIDTH 8
`define ADDR_DPID 7:5 // DestPart ID
`define ADDR_NPID 4:0 // Node and port ID
`define F_HEAD 35 // Head flit
`define F_TAIL 34 // Tail flit
`define F_MEASURE 33 // Measurement flit
`define F_FLAGS 35:33
`define F_TS 32:23
`define F_DEST 22:15 // Does not include port ID
`define F_SRC_INJ 14:5
`define F_OPORT 4:2
`define F_OVC 1:0
`define A_WIDTH 11
`define A_DPID 10:7
`define A_NID 6:3 // 4-bit local node ID
`define A_PORTID 2:0
`define A_FQID 6:0 // 4-bit local node ID + 3-bit port ID
`define A_DNID 10:3 // 8-bit global node ID
// Packet descriptor
`define P_SRC 7:0 // 8-bit address
`define P_DEST 15:8
`define P_SIZE 18:16 // 3-bit packet size
`define P_VC 20:19 // 2-bit VC ID
`define P_INJ 30:21 // 10-bit timestamp
`define P_MEASURE 31
`define P_SIZE_WIDTH 4
|
`timescale 1ns / 1ps
/* Control Unit
*/
module Control (
input clock,
input reset,
input enable,
output control_error,
// To UART interface
input [15:0] rx_word,
input rx_word_valid,
output reg [15:0] tx_word,
output reg tx_word_valid,
input tx_ack,
// To simulator interface
output sim_reset,
output sim_enable,
input sim_error,
output stop_injection,
output measure,
input [9:0] sim_time,
input sim_time_tick,
input sim_quiescent,
output reg [15:0] config_word,
output reg config_valid,
output reg stats_shift,
input [15:0] stats_word
);
// Control bits
`define C_OFFSET 15:12
localparam [3:0] O_RESET = 0,
O_COMMON = 1,
O_TIMER_VALUE = 2,
O_TIMER_VALUE_HI = 3,
O_CONFIG_ENABLE = 4,
O_DATA_REQUEST = 5,
O_STATES_REQUEST = 6;
localparam C_SIM_ENABLE = 0,
C_MEASURE = 1,
C_STOP_INJECTION = 2,
C_TIMER_ENABLE = 3,
C_NUM_BITS = 4;
localparam DECODE = 0,
RESET_SIM = 1,
LOAD_CONFIG_LENGTH = 2,
CONFIG = 3,
LOAD_DATA_LENGTH = 4,
BLOCK_SEND_STATES = 5;
localparam TX_IDLE = 0,
TX_SHIFT_DATA = 1,
TX_SEND_STATE = 2,
TX_SEND_STATE_2 = 3,
TX_SEND_STATE_3 = 4,
TX_SEND_STATE_4 = 5;
// Internal states
reg [C_NUM_BITS-1:0] r_control;
reg r_sim_reset;
reg [2:0] r_state;
reg [2:0] r_tx_state;
reg [3:0] r_counter; // Reset counter
reg [23:0] r_timer_counter;
reg [15:0] r_config_counter;
reg [15:0] r_data_counter;
// Wires
reg [2:0] next_state;
reg next_sim_reset;
reg [C_NUM_BITS-1:0] next_control;
reg [2:0] next_tx_state;
reg [15:0] next_config_word;
reg next_config_valid;
reg reset_counter;
reg shift_timer_counter;
reg load_config_counter;
reg load_data_counter;
reg start_send_state;
// Output
assign control_error = 1'b0;
assign sim_reset = r_sim_reset;
assign sim_enable = (r_tx_state == TX_IDLE) ? r_control[C_SIM_ENABLE] : 1'b0;
assign stop_injection = r_control[C_STOP_INJECTION];
assign measure = r_control[C_MEASURE];
//
// Control FSM
//
always @(posedge clock)
begin
if (reset)
begin
r_state <= DECODE;
r_sim_reset <= 1'b0;
r_control <= 0;
config_word <= 0;
config_valid <= 0;
end
else if (enable)
begin
r_state <= next_state;
r_sim_reset <= next_sim_reset;
r_control <= next_control;
config_word <= next_config_word;
config_valid <= next_config_valid;
end
end
always @(*)
begin
next_state = r_state;
next_sim_reset = r_sim_reset;
next_control = r_control;
reset_counter = 1'b0;
shift_timer_counter = 1'b0;
load_config_counter = 1'b0;
load_data_counter = 1'b0;
start_send_state = 1'b0;
next_config_word = 0;
next_config_valid = 1'b0;
case (r_state)
DECODE:
begin
if (rx_word_valid)
begin
case (rx_word[`C_OFFSET])
O_RESET:
begin
next_sim_reset = 1'b1;
next_state = RESET_SIM;
reset_counter = 1'b1;
end
O_COMMON: // Load the command bits
begin
next_control = rx_word[C_NUM_BITS-1:0];
end
O_TIMER_VALUE: // Timer value is encoded in this command
begin
shift_timer_counter = 1'b1;
end
O_TIMER_VALUE_HI:
begin
shift_timer_counter = 1'b1;
end
O_CONFIG_ENABLE: // Counter value is in the next command
begin
next_state = LOAD_CONFIG_LENGTH;
end
O_DATA_REQUEST: // Counter value is in the next command
begin
next_state = LOAD_DATA_LENGTH;
end
O_STATES_REQUEST:
begin
if (r_control[C_TIMER_ENABLE] & rx_word[0])
begin // When timer-enable is set, block and send states after sim stops
next_state = BLOCK_SEND_STATES;
end
else // Non-blocking
start_send_state = 1'b1;
end
endcase
end
end
RESET_SIM: // Hold reset for 16 cycles
begin
if (r_counter == 0)
begin
next_sim_reset = 1'b0;
next_state = DECODE;
end
end
LOAD_CONFIG_LENGTH: // Load the # of config words to receive (N <= 64K)
begin
if (rx_word_valid)
begin
load_config_counter = 1'b1;
next_state = CONFIG;
end
end
CONFIG: // Receive words and send to config_word port
begin
if (rx_word_valid)
begin
next_config_valid = 1'b1;
next_config_word = rx_word;
if (r_config_counter == 1)
next_state = DECODE;
end
end
LOAD_DATA_LENGTH: // Load the # of data words to send back (N <= 64K)
begin
if (rx_word_valid)
begin
load_data_counter = 1'b1;
next_state = DECODE;
end
end
BLOCK_SEND_STATES: // Wait until sim_enable is low and initiate send states
begin
if (~r_control[C_SIM_ENABLE])
begin
start_send_state = 1'b1;
next_state = DECODE;
end
end
endcase
// Timer controlled simulation
if (r_control[C_TIMER_ENABLE] == 1'b1 && r_timer_counter == 0)
next_control[C_SIM_ENABLE] = 1'b0;
end
// Reset counter
always @(posedge clock)
begin
if (reset)
r_counter <= 4'hF;
else if (enable)
begin
if (reset_counter)
r_counter <= 4'hF;
else if (r_state == RESET_SIM)
r_counter <= r_counter - 1;
end
/* // This causes non-deterministic behaviours
if (reset_counter)
r_counter <= 4'hF;
else if (enable)
r_counter <= r_counter - 1;*/
end
// Timer counter
always @(posedge clock)
begin
if (reset)
r_timer_counter <= 0;
else if (enable)
begin
if (shift_timer_counter)
r_timer_counter <= {rx_word[11:0], r_timer_counter[23:12]}; // load low 12 bits first
else if (r_control[C_TIMER_ENABLE] & sim_time_tick)
r_timer_counter <= r_timer_counter - 1;
end
end
// Config word counter
always @(posedge clock)
begin
if (reset)
r_config_counter <= 0;
else if (enable)
begin
if (load_config_counter)
r_config_counter <= rx_word;
else if (rx_word_valid)
r_config_counter <= r_config_counter - 1;
end
end
// Data counter
always @(posedge clock)
begin
if (reset)
r_data_counter <= 0;
else if (enable)
begin
if (load_data_counter)
r_data_counter <= rx_word;
else if (tx_ack)
r_data_counter <= r_data_counter - 1;
end
end
//
// TX State Machine
//
always @(posedge clock)
begin
if (reset)
r_tx_state <= TX_IDLE;
else if (enable)
r_tx_state <= next_tx_state;
end
always @(*)
begin
next_tx_state = r_tx_state;
stats_shift = 1'b0;
tx_word = 0;
tx_word_valid = 1'b0;
case (r_tx_state)
TX_IDLE:
begin
if (load_data_counter) // Start sending data words
next_tx_state = TX_SHIFT_DATA;
else if (start_send_state)
next_tx_state = TX_SEND_STATE;
end
TX_SHIFT_DATA:
begin
tx_word = stats_word;
tx_word_valid = 1'b1;
if (tx_ack)
begin
stats_shift = 1'b1;
if (r_data_counter == 1)
next_tx_state = TX_IDLE;
end
end
TX_SEND_STATE:
begin
tx_word = {control_error, sim_error, r_control, sim_quiescent, r_state, r_tx_state, 3'h0};
tx_word_valid = 1'b1;
if (tx_ack)
next_tx_state = TX_SEND_STATE_2;
end
TX_SEND_STATE_2:
begin
tx_word = {6'h00, sim_time};
tx_word_valid = 1'b1;
if (tx_ack)
next_tx_state = TX_SEND_STATE_3;
end
TX_SEND_STATE_3:
begin
tx_word = r_timer_counter[15:0];
tx_word_valid = 1'b1;
if (tx_ack)
next_tx_state = TX_SEND_STATE_4;
end
TX_SEND_STATE_4:
begin
tx_word = {8'h00, r_timer_counter[23:16]};
tx_word_valid = 1'b1;
if (tx_ack)
next_tx_state = TX_IDLE;
end
endcase
end
endmodule
|
`timescale 1ns / 1ps
/* CreditCounter
* CreditCounter.v
*
* A single credit counter
*
* Config path:
* config_in -> r_count -> config_out
*/
module CreditCounter(
clock,
reset,
enable,
sim_time_tick,
config_in,
config_in_valid,
config_out,
config_out_valid,
credit_in_valid,
credit_ack,
decrement,
count_out
);
parameter WIDTH = 4; // Width of credit counter
// Global ports
input clock;
input reset;
input enable;
input sim_time_tick;
// Configuration ports
input [WIDTH-1: 0] config_in;
input config_in_valid;
output [WIDTH-1: 0] config_out;
output config_out_valid;
// Credit ports
input credit_in_valid;
output credit_ack;
input decrement;
output [WIDTH-1: 0] count_out;
reg [WIDTH-1:0] r_count;
reg [WIDTH-1:0] w_count;
// Output
assign count_out = r_count;
assign config_out = r_count;
assign config_out_valid = config_in_valid;
assign credit_ack = enable & credit_in_valid;
always @(posedge clock)
begin
if (reset)
r_count <= 0;
else if (config_in_valid)
r_count <= config_in;
else if (enable)
r_count <= w_count;
end
always @(*)
begin
if (credit_in_valid & ~decrement)
w_count = r_count + 1;
else if (~credit_in_valid & decrement)
w_count = r_count - 1;
else
w_count = r_count;
end
endmodule
|
`timescale 1ns / 1ps
/* Top level module that communicates with the PC
*/
module dart (
input SYSTEM_CLOCK,
input SW_0,
input SW_1,
input SW_2,
input SW_3,
input PB_ENTER,
input PB_UP,
input RS232_RX_DATA,
output RS232_TX_DATA,
output LED_0,
output LED_1,
output LED_2,
output LED_3
);
wire dcm_locked;
wire clock_100;
wire clock_50;
wire reset;
wire arst;
wire error;
wire rx_error;
wire tx_error;
wire control_error;
wire [15:0] rx_word;
wire rx_word_valid;
wire [15:0] tx_word;
wire tx_word_valid;
wire tx_ack;
wire sim_error;
wire sim_reset;
wire sim_enable;
wire [9:0] sim_time;
wire sim_time_tick;
wire [15:0] config_word;
wire config_valid;
wire [15:0] stats_word;
wire stats_shift;
wire stop_injection;
wire measure;
wire sim_quiescent;
wire [7:0] fdp_error;
wire [7:0] cdp_error;
wire [7:0] part_error;
reg [4:0] r_sync_reset;
always @(posedge clock_50)
begin
r_sync_reset <= {r_sync_reset[3:0], ~PB_ENTER};
end
assign reset = r_sync_reset[4];
IBUF dcm_arst_buf (.O(arst), .I(~PB_UP));
//
// LEDs for debugging
//
reg [3:0] led_out;
assign {LED_3, LED_2, LED_1, LED_0} = ~led_out;
always @(*)
begin
case ({SW_3, SW_2, SW_1, SW_0})
4'h0: led_out = {reset, dcm_locked, rx_error, tx_error};
4'h1: led_out = {sim_reset, sim_error, ~RS232_RX_DATA, ~RS232_TX_DATA};
4'h2: led_out = {stop_injection, measure, sim_enable, sim_quiescent};
4'h3: led_out = part_error[3:0];
4'h4: led_out = part_error[7:4];
4'h5: led_out = fdp_error[3:0];
4'h6: led_out = fdp_error[7:4];
4'h7: led_out = cdp_error[3:0];
4'h8: led_out = cdp_error[7:4];
4'h9: led_out = {control_error, 3'b000};
default: led_out = 4'b0000;
endcase
end
//
// DCM
//
wire dcm_sys_clk_in;
wire dcm_clk_100;
wire dcm_clk_50;
IBUFG sys_clk_buf (.O(dcm_sys_clk_in), .I(SYSTEM_CLOCK));
BUFG clk_100_buf (.O(clock_100), .I(dcm_clk_100));
BUFG clk_50_buf (.O(clock_50), .I(dcm_clk_50));
DCM #(
.SIM_MODE("SAFE"), // Simulation: "SAFE" vs. "FAST", see "Synthesis and Simulation Design Guide" for details
.CLKDV_DIVIDE(4.0), // Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
// 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
.CLKFX_DIVIDE(1), // Can be any integer from 1 to 32
.CLKFX_MULTIPLY(4), // Can be any integer from 2 to 32
.CLKIN_DIVIDE_BY_2("FALSE"), // TRUE/FALSE to enable CLKIN divide by two feature
.CLKIN_PERIOD(0.0), // Specify period of input clock
.CLKOUT_PHASE_SHIFT("NONE"), // Specify phase shift of NONE, FIXED or VARIABLE
.CLK_FEEDBACK("1X"), // Specify clock feedback of NONE, 1X or 2X
.DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), // SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
// an integer from 0 to 15
.DFS_FREQUENCY_MODE("LOW"), // HIGH or LOW frequency mode for frequency synthesis
.DLL_FREQUENCY_MODE("LOW"), // HIGH or LOW frequency mode for DLL
.DUTY_CYCLE_CORRECTION("TRUE"), // Duty cycle correction, TRUE or FALSE
.FACTORY_JF(16'hC080), // FACTORY JF values
.PHASE_SHIFT(0), // Amount of fixed phase shift from -255 to 255
.STARTUP_WAIT("FALSE") // Delay configuration DONE until DCM LOCK, TRUE/FALSE
) DCM_inst (
.CLK0(dcm_clk_100), // 0 degree DCM CLK output
.CLK180(), // 180 degree DCM CLK output
.CLK270(), // 270 degree DCM CLK output
.CLK2X(), // 2X DCM CLK output
.CLK2X180(), // 2X, 180 degree DCM CLK out
.CLK90(), // 90 degree DCM CLK output
.CLKDV(dcm_clk_50), // Divided DCM CLK out (CLKDV_DIVIDE)
.CLKFX(), // DCM CLK synthesis out (M/D)
.CLKFX180(), // 180 degree CLK synthesis out
.LOCKED(dcm_locked), // DCM LOCK status output
.PSDONE(), // Dynamic phase adjust done output
.STATUS(), // 8-bit DCM status bits output
.CLKFB(clock_100), // DCM clock feedback
.CLKIN(dcm_sys_clk_in), // Clock input (from IBUFG, BUFG or DCM)
.PSCLK(1'b0), // Dynamic phase adjust clock input
.PSEN(1'b0), // Dynamic phase adjust enable input
.PSINCDEC(0), // Dynamic phase adjust increment/decrement
.RST(arst) // DCM asynchronous reset input
);
//
// DART UART port (user data width = 16)
//
dartport #(.WIDTH(16), .BAUD_RATE(9600)) dartio (
.clock (clock_50),
.reset (reset),
.enable (dcm_locked),
.rx_error (rx_error),
.tx_error (tx_error),
.RS232_RX_DATA (RS232_RX_DATA),
.RS232_TX_DATA (RS232_TX_DATA),
.rx_data (rx_word),
.rx_valid (rx_word_valid),
.tx_data (tx_word),
.tx_valid (tx_word_valid),
.tx_ack (tx_ack));
//
// Control Unit
//
Control controller (
.clock (clock_50),
.reset (reset),
.enable (dcm_locked),
.control_error (control_error),
.rx_word (rx_word),
.rx_word_valid (rx_word_valid),
.tx_word (tx_word),
.tx_word_valid (tx_word_valid),
.tx_ack (tx_ack),
.sim_reset (sim_reset),
.sim_enable (sim_enable),
.sim_error (sim_error),
.stop_injection (stop_injection),
.measure (measure),
.sim_time (sim_time),
.sim_time_tick (sim_time_tick),
.sim_quiescent (sim_quiescent),
.config_word (config_word),
.config_valid (config_valid),
.stats_shift (stats_shift),
.stats_word (stats_word));
//
// Simulator
//
sim9_8x8 dart_sim (
.clock (clock_50),
.clock_2x (clock_100),
.reset (sim_reset),
.enable (sim_enable),
.stop_injection (stop_injection),
.measure (measure),
.sim_time (sim_time),
.sim_time_tick (sim_time_tick),
.error (sim_error),
.fdp_error (fdp_error),
.cdp_error (cdp_error),
.part_error (part_error),
.quiescent (sim_quiescent),
.config_in (config_word),
.config_in_valid (config_valid),
.config_out (),
.config_out_valid (),
.stats_out (stats_word),
.stats_shift (stats_shift));
endmodule
|
`timescale 1ns / 1ps
/* Top level module that communicates with the PC
*/
module dart32_8x8 (
input SYSTEM_CLOCK,
input SW_0,
input SW_1,
input SW_2,
input SW_3,
input PB_ENTER,
input RS232_RX_DATA,
output RS232_TX_DATA,
output LED_0,
output LED_1,
output LED_2,
output LED_3
);
wire dcm_locked;
wire clock_100;
wire clock_50;
wire reset;
wire error;
wire rx_error;
wire tx_error;
wire control_error;
wire [15:0] rx_word;
wire rx_word_valid;
wire [15:0] tx_word;
wire tx_word_valid;
wire tx_ack;
wire sim_error;
wire sim_reset;
wire sim_enable;
wire [9:0] sim_time;
wire sim_time_tick;
wire [15:0] config_word;
wire config_valid;
wire [15:0] stats_word;
wire stats_shift;
wire stop_injection;
wire measure;
wire sim_quiescent;
assign reset = SW_3;
//
// LEDs for debugging
//
reg [3:0] led_out;
assign {LED_3, LED_2, LED_1, LED_0} = ~led_out;
always @(*)
begin
case ({SW_1, SW_0})
2'b00: led_out = {reset, rx_error, tx_error, control_error};
2'b01: led_out = {sim_reset, sim_error, ~RS232_RX_DATA, ~RS232_TX_DATA};
2'b10: led_out = {stop_injection, measure, sim_enable, SW_2};
2'b11: led_out = stats_word[3:0];
default: led_out = 4'b0000;
endcase
end
//
// DCM
//
DCM #(
.SIM_MODE("SAFE"), // Simulation: "SAFE" vs. "FAST", see "Synthesis and Simulation Design Guide" for details
.CLKDV_DIVIDE(2.0), // Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
// 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
.CLKFX_DIVIDE(1), // Can be any integer from 1 to 32
.CLKFX_MULTIPLY(4), // Can be any integer from 2 to 32
.CLKIN_DIVIDE_BY_2("FALSE"), // TRUE/FALSE to enable CLKIN divide by two feature
.CLKIN_PERIOD(0.0), // Specify period of input clock
.CLKOUT_PHASE_SHIFT("NONE"), // Specify phase shift of NONE, FIXED or VARIABLE
.CLK_FEEDBACK("1X"), // Specify clock feedback of NONE, 1X or 2X
.DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), // SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
// an integer from 0 to 15
.DFS_FREQUENCY_MODE("LOW"), // HIGH or LOW frequency mode for frequency synthesis
.DLL_FREQUENCY_MODE("LOW"), // HIGH or LOW frequency mode for DLL
.DUTY_CYCLE_CORRECTION("TRUE"), // Duty cycle correction, TRUE or FALSE
.FACTORY_JF(16'hC080), // FACTORY JF values
.PHASE_SHIFT(0), // Amount of fixed phase shift from -255 to 255
.STARTUP_WAIT("FALSE") // Delay configuration DONE until DCM LOCK, TRUE/FALSE
) DCM_inst (
.CLK0(clock_100), // 0 degree DCM CLK output
.CLK180(), // 180 degree DCM CLK output
.CLK270(), // 270 degree DCM CLK output
.CLK2X(), // 2X DCM CLK output
.CLK2X180(), // 2X, 180 degree DCM CLK out
.CLK90(), // 90 degree DCM CLK output
.CLKDV(clock_50), // Divided DCM CLK out (CLKDV_DIVIDE)
.CLKFX(), // DCM CLK synthesis out (M/D)
.CLKFX180(), // 180 degree CLK synthesis out
.LOCKED(dcm_locked), // DCM LOCK status output
.PSDONE(), // Dynamic phase adjust done output
.STATUS(), // 8-bit DCM status bits output
.CLKFB(clock_100), // DCM clock feedback
.CLKIN(SYSTEM_CLOCK), // Clock input (from IBUFG, BUFG or DCM)
.PSCLK(1'b0), // Dynamic phase adjust clock input
.PSEN(1'b0), // Dynamic phase adjust enable input
.PSINCDEC(0), // Dynamic phase adjust increment/decrement
.RST(reset) // DCM asynchronous reset input
);
//
// DART UART port (user data width = 16)
//
dartport #(.WIDTH(16), .BAUD_RATE(9600)) dartio (
.clock (clock_50),
.reset (reset),
.enable (dcm_locked),
.rx_error (rx_error),
.tx_error (tx_error),
.RS232_RX_DATA (RS232_RX_DATA),
.RS232_TX_DATA (RS232_TX_DATA),
.rx_data (rx_word),
.rx_valid (rx_word_valid),
.tx_data (tx_word),
.tx_valid (tx_word_valid),
.tx_ack (tx_ack));
//
// Control Unit
//
Control controller (
.clock (clock_50),
.reset (reset),
.enable (dcm_locked),
.control_error (control_error),
.rx_word (rx_word),
.rx_word_valid (rx_word_valid),
.tx_word (tx_word),
.tx_word_valid (tx_word_valid),
.tx_ack (tx_ack),
.sim_reset (sim_reset),
.sim_enable (sim_enable),
.sim_error (sim_error),
.stop_injection (stop_injection),
.measure (measure),
.sim_time (sim_time),
.sim_time_tick (sim_time_tick),
.sim_quiescent (sim_quiescent),
.config_word (config_word),
.config_valid (config_valid),
.stats_shift (stats_shift),
.stats_word (stats_word));
//
// Simulator
//
sim32_8x8 dart_sim (
.clock (clock_50),
.reset (sim_reset),
.enable (sim_enable),
.stop_injection (stop_injection),
.measure (measure),
.sim_time (sim_time),
.sim_time_tick (sim_time_tick),
.error (sim_error),
.quiescent (sim_quiescent),
.config_in (config_word),
.config_in_valid (config_valid),
.config_out (),
.config_out_valid (),
.stats_out (stats_word),
.stats_shift (stats_shift));
endmodule
|
`timescale 1ns / 1ps
/* DART UART ports
*/
module dartport #(
parameter WIDTH = 16,
BAUD_RATE = 9600
)
(
input clock,
input reset,
input enable,
output rx_error,
output tx_error,
input RS232_RX_DATA,
output RS232_TX_DATA,
output [WIDTH-1:0] rx_data,
output rx_valid,
input [WIDTH-1:0] tx_data,
input tx_valid,
output tx_ack
);
localparam N = (WIDTH+7)>>3; // The number of 8-bit words required
localparam IDLE = 0, TRANSMITTING = 1;
wire [7:0] rx_word;
wire rx_word_valid;
wire [7:0] tx_to_fifo_word;
wire tx_to_fifo_valid;
wire tx_serializer_busy;
wire [7:0] tx_word;
wire tx_fifo_empty;
wire tx_fifo_full;
wire tx_start;
wire tx_ready;
reg tx_state;
// RX Side
// Receive data from UART (8-bit) and deserialize into WIDTH words
// Ready words must be consumed immediately
myuart_rx #(.BAUD_RATE(BAUD_RATE)) rx_module (
.clock (clock),
.reset (reset),
.enable (enable),
.error (rx_error),
.rx_data_in (RS232_RX_DATA),
.data_out (rx_word),
.data_out_valid (rx_word_valid));
deserializer #(.WIDTH(8), .N(N)) rx_deserializer (
.clock(clock),
.reset(reset),
.data_in(rx_word),
.data_in_valid(rx_word_valid & enable),
.data_out(rx_data),
.data_out_valid(rx_valid));
// TX Side
// Receive data from user. The user should not send a new word to the TX
// module until an ack is received.
// User data is serialized into 8-bit words before sending out through
// the UART's TX module
assign tx_ack = tx_valid & ~tx_fifo_full & ~tx_serializer_busy;
assign tx_start = (tx_state == IDLE) ? (~tx_fifo_empty & tx_ready) : 1'b0;
serializer #(.WIDTH(8), .N(N)) tx_serializer (
.clock (clock),
.reset (reset),
.data_in (tx_data),
.data_in_valid (tx_valid & enable),
.data_out (tx_to_fifo_word),
.data_out_valid (tx_to_fifo_valid),
.busy (tx_serializer_busy));
// TX FIFO
fifo_8bit tx_buffer (
.clk (clock),
.rst (reset),
.din (tx_to_fifo_word),
.wr_en (tx_to_fifo_valid & enable),
.dout (tx_word),
.rd_en (tx_start & enable),
.empty (tx_fifo_empty),
.full (tx_fifo_full));
myuart_tx #(.BAUD_RATE(BAUD_RATE)) tx_module (
.clock (clock),
.reset (reset),
.enable (enable),
.error (tx_error),
.data_in (tx_word),
.tx_start (tx_start),
.tx_data_out (RS232_TX_DATA),
.tx_ready (tx_ready));
// State machine that coordinates between tx_buffer and tx_module
always @(posedge clock)
begin
if (reset)
begin
tx_state <= IDLE;
end
else if (enable)
begin
case (tx_state)
IDLE:
begin
if (~tx_fifo_empty & tx_ready)
tx_state <= TRANSMITTING;
end
TRANSMITTING:
begin
if (tx_ready)
tx_state <= IDLE;
end
endcase
end
end
endmodule
|
`timescale 1ns / 1ps
/* decoder_N.v
* General N-bit decoder (one-hot)
*/
module decoder_N(
encoded,
decoded
);
`include "math.v"
parameter SIZE = 8;
input [CLogB2(SIZE-1)-1: 0] encoded;
output [SIZE-1: 0] decoded;
reg [SIZE-1: 0] decoded;
genvar i;
generate
for (i = 0; i < SIZE; i = i + 1)
begin : decode
always @(*)
begin
if (i == encoded)
decoded[i] = 1'b1;
else
decoded[i] = 1'b0;
end
end
endgenerate
endmodule
|
`timescale 1 ns/100 ps // time unit = 1ns; precision = 1/10 ns
/* Distributed RAM
* DistroRAM.v
*
* Implement a small dual-port RAM using distributed RAM
*/
module DistroRAM (
clock,
wen,
waddr,
raddr,
din,
wdout,
rdout
);
parameter WIDTH = 8;
parameter LOG_DEP = 3;
localparam DEPTH = 1 << LOG_DEP;
input clock;
input wen;
input [LOG_DEP-1: 0] waddr;
input [LOG_DEP-1: 0] raddr;
input [WIDTH-1: 0] din;
output [WIDTH-1: 0] wdout;
output [WIDTH-1: 0] rdout;
// Infer distributed RAM
reg [WIDTH-1: 0] ram [DEPTH-1: 0];
// synthesis attribute RAM_STYLE of ram is distributed
always @(posedge clock)
begin
if (wen)
ram[waddr] <= din;
end
assign wdout = ram[waddr];
assign rdout = ram[raddr];
endmodule
|
`timescale 1ns / 1ps
/* Dual-Port RAM with synchronous read (read through)
*/
module DualBRAM #(
parameter WIDTH = 36,
parameter LOG_DEP = 6
)
(
input clock,
input enable,
input wen,
input [LOG_DEP-1:0] waddr,
input [LOG_DEP-1:0] raddr,
input [WIDTH-1:0] din,
output [WIDTH-1:0] dout,
output [WIDTH-1:0] wdout
);
localparam DEPTH = 1 << LOG_DEP;
// Infer Block RAM
reg [WIDTH-1:0] ram [DEPTH-1:0];
reg [LOG_DEP-1: 0] read_addr;
reg [LOG_DEP-1: 0] write_addr;
// synthesis attribute RAM_STYLE of ram is block
always @(posedge clock)
begin
if (enable)
begin
if (wen)
ram[waddr] <= din;
read_addr <= raddr;
write_addr <= waddr;
end
end
assign dout = ram[read_addr];
assign wdout = ram[write_addr];
endmodule
|
`timescale 1ns / 1ps
/* encoder_N.v
* General N-bit encoder (input is one-hot)
*/
module encoder_N(
decoded,
encoded,
valid
);
`include "math.v"
parameter SIZE = 8;
localparam LOG_SIZE = CLogB2(SIZE-1);
localparam NPOT = 1 << LOG_SIZE;
input [SIZE-1:0] decoded;
output [LOG_SIZE-1:0] encoded;
output valid;
wire [NPOT-1:0] w_decoded;
assign valid = |decoded;
generate
if (NPOT == SIZE)
assign w_decoded = decoded;
else
assign w_decoded = {{(NPOT-SIZE){1'b0}}, decoded};
endgenerate
// Only a set of input sizes are selected
// psl ERROR_encoder_size: assert always {LOG_SIZE <= 4 && LOG_SIZE != 0};
generate
if (LOG_SIZE == 1)
begin
assign encoded = w_decoded[1];
end
else if (LOG_SIZE == 2)
begin
assign encoded = {w_decoded[2] | w_decoded[3], w_decoded[1] | w_decoded[3]};
end
else if (LOG_SIZE == 3)
begin
// This produces slightly smaller area than the case-statement based implementation
assign encoded = {w_decoded[4] | w_decoded[5] | w_decoded[6] | w_decoded[7],
w_decoded[2] | w_decoded[3] | w_decoded[6] | w_decoded[7],
w_decoded[1] | w_decoded[3] | w_decoded[5] | w_decoded[7]};
end
else if (LOG_SIZE == 4)
begin
reg [LOG_SIZE-1:0] w_encoded;
assign encoded = w_encoded;
always @(*)
begin
case (w_decoded)
16'h0001: w_encoded = 4'h0;
16'h0002: w_encoded = 4'h1;
16'h0004: w_encoded = 4'h2;
16'h0008: w_encoded = 4'h3;
16'h0010: w_encoded = 4'h4;
16'h0020: w_encoded = 4'h5;
16'h0040: w_encoded = 4'h6;
16'h0080: w_encoded = 4'h7;
16'h0100: w_encoded = 4'h8;
16'h0200: w_encoded = 4'h9;
16'h0400: w_encoded = 4'hA;
16'h0800: w_encoded = 4'hB;
16'h1000: w_encoded = 4'hC;
16'h2000: w_encoded = 4'hD;
16'h4000: w_encoded = 4'hE;
16'h8000: w_encoded = 4'hF;
default: w_encoded = 4'bxxxx;
endcase
end
end
endgenerate
endmodule
|
`timescale 1ns / 1ps
/* Flit Queue
* FlitQueue.v
*
* Models a single input unit of a Router
*
* Configuration path
* config_in -> FlitQueue_NC -> config_out
*/
`include "const.v"
module FlitQueue(
clock,
reset,
enable,
sim_time,
error,
is_quiescent,
config_in,
config_in_valid,
config_out,
config_out_valid,
flit_full,
flit_in_valid,
flit_in,
nexthop_in,
flit_ack,
flit_out,
flit_out_valid,
dequeue,
credit_full,
credit_in_valid,
credit_in,
credit_in_nexthop,
credit_ack,
credit_out,
credit_out_valid,
credit_dequeue
);
`include "util.v"
parameter [`A_WIDTH-1:0] HADDR = 1; // 8-bit global node ID + 3-bit port ID
parameter LOG_NVCS = 1;
localparam NVCS = 1 << LOG_NVCS;
input clock;
input reset;
input enable;
input [`TS_WIDTH-1:0] sim_time;
output error;
output is_quiescent;
// Config interface
input [15: 0] config_in;
input config_in_valid;
output [15: 0] config_out;
output config_out_valid;
// Flit interface (1 in, NVCS out)
output [NVCS-1: 0] flit_full;
input flit_in_valid;
input [`FLIT_WIDTH-1:0] flit_in;
input [`A_FQID] nexthop_in;
output flit_ack;
output [NVCS*`FLIT_WIDTH-1:0] flit_out; // One out interface per VC
output [NVCS-1: 0] flit_out_valid;
input [NVCS-1: 0] dequeue;
// Credit interface (1 in, 1 out)
output credit_full;
input credit_in_valid;
input [`CREDIT_WIDTH-1: 0] credit_in;
input [`A_FQID] credit_in_nexthop;
output credit_ack;
output [`CREDIT_WIDTH-1: 0] credit_out; // Two output interfaces for the two VCs
output credit_out_valid;
input credit_dequeue;
// Wires
wire w_flit_error;
wire [`LAT_WIDTH-1:0] w_latency;
wire [NVCS-1: 0] w_flit_full;
wire w_flit_is_quiescent;
wire [NVCS-1: 0] w_flit_dequeue;
wire [`TS_WIDTH-1:0] w_credit_in_ts;
wire [`TS_WIDTH-1:0] w_credit_new_ts;
wire [`TS_WIDTH-1:0] w_credit_out_ts;
wire [`CREDIT_WIDTH-1:0] w_credit_to_enqueue;
wire [`CREDIT_WIDTH-1:0] w_credit_out;
wire w_credit_enqueue;
wire w_credit_full;
wire w_credit_empty;
wire w_credit_error;
wire w_credit_has_data;
// Output
assign error = w_credit_error | w_flit_error;
assign is_quiescent = w_flit_is_quiescent & w_credit_empty;
assign flit_full = w_flit_full;
assign credit_full = w_credit_full;
assign credit_out = w_credit_out;
assign credit_ack = w_credit_enqueue;
// For now only supports 2 VCs (1 LSB in nexthop)
// psl ERROR_unsupported_NVCS: assert always {NVCS == 2};
// Simulation stuff
`ifdef SIMULATION
always @(posedge clock)
begin
if (credit_dequeue)
$display ("T %x FQ (%x) sends credit %x port 0", sim_time, HADDR, credit_out);
end
`endif
// Flit Queue
FlitQueue_NC #(.HADDR(HADDR), .LOG_NVCS(LOG_NVCS)) fq (
.clock (clock),
.reset (reset),
.enable (enable),
.sim_time (sim_time),
.error (w_flit_error),
.is_quiescent (w_flit_is_quiescent),
.latency (w_latency),
.config_in (config_in),
.config_in_valid (config_in_valid),
.config_out (config_out),
.config_out_valid (config_out_valid),
.flit_full (w_flit_full),
.flit_in_valid (flit_in_valid),
.flit_in (flit_in),
.nexthop_in (nexthop_in),
.flit_ack (flit_ack),
.flit_out (flit_out),
.flit_out_valid (flit_out_valid),
.dequeue (w_flit_dequeue));
// Credit FIFO (32 deep)
assign w_credit_in_ts = credit_ts (credit_in);
assign w_credit_to_enqueue = update_credit_ts (credit_in, w_credit_new_ts);
assign w_credit_enqueue = (credit_in_nexthop == HADDR[`A_FQID]) ? (enable & credit_in_valid & ~w_credit_full) : 1'b0;
assign w_credit_error = (credit_in_valid & w_credit_full) | (credit_dequeue & w_credit_empty);
assign w_credit_new_ts = w_credit_in_ts + w_latency;
//srl_fifo #(.WIDTH(`CREDIT_WIDTH), .LOG_LEN(5)) cq (
RAMFIFO_single_slow #(.WIDTH(`CREDIT_WIDTH), .LOG_DEP(5)) cq (
.clock (clock),
.reset (reset),
.enable (enable),
.data_in (w_credit_to_enqueue),
.data_out (w_credit_out),
.write (w_credit_enqueue),
.read (credit_dequeue),
.full (w_credit_full),
.empty (w_credit_empty),
.has_data (w_credit_has_data));
// Credit out interface
assign w_credit_out_ts = credit_ts (w_credit_out);
flit_out_inf cout_inf (
.clock (clock),
.reset (reset),
.dequeue (credit_dequeue),
.flit_valid (w_credit_has_data),
.flit_timestamp (w_credit_out_ts),
.sim_time (sim_time),
.ready (credit_out_valid));
// Generate dequeue signals
assign w_flit_dequeue = dequeue;
endmodule
|
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